2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
18 #define pr_fmt(fmt) "SVM: " fmt
20 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40 #include <linux/psp-sev.h>
41 #include <linux/file.h>
42 #include <linux/pagemap.h>
43 #include <linux/swap.h>
46 #include <asm/perf_event.h>
47 #include <asm/tlbflush.h>
49 #include <asm/debugreg.h>
50 #include <asm/kvm_para.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/microcode.h>
53 #include <asm/nospec-branch.h>
55 #include <asm/virtext.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
60 MODULE_AUTHOR("Qumranet");
61 MODULE_LICENSE("GPL");
63 static const struct x86_cpu_id svm_cpu_id
[] = {
64 X86_FEATURE_MATCH(X86_FEATURE_SVM
),
67 MODULE_DEVICE_TABLE(x86cpu
, svm_cpu_id
);
69 #define IOPM_ALLOC_ORDER 2
70 #define MSRPM_ALLOC_ORDER 1
72 #define SEG_TYPE_LDT 2
73 #define SEG_TYPE_BUSY_TSS16 3
75 #define SVM_FEATURE_NPT (1 << 0)
76 #define SVM_FEATURE_LBRV (1 << 1)
77 #define SVM_FEATURE_SVML (1 << 2)
78 #define SVM_FEATURE_NRIP (1 << 3)
79 #define SVM_FEATURE_TSC_RATE (1 << 4)
80 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
81 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
82 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
83 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
85 #define SVM_AVIC_DOORBELL 0xc001011b
87 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
88 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
89 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
91 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
93 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
94 #define TSC_RATIO_MIN 0x0000000000000001ULL
95 #define TSC_RATIO_MAX 0x000000ffffffffffULL
97 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
100 * 0xff is broadcast, so the max index allowed for physical APIC ID
101 * table is 0xfe. APIC IDs above 0xff are reserved.
103 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
105 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
106 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
107 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
109 /* AVIC GATAG is encoded using VM and VCPU IDs */
110 #define AVIC_VCPU_ID_BITS 8
111 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
113 #define AVIC_VM_ID_BITS 24
114 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
115 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
117 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
118 (y & AVIC_VCPU_ID_MASK))
119 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
120 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
122 static bool erratum_383_found __read_mostly
;
124 static const u32 host_save_user_msrs
[] = {
126 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
129 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
133 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
135 struct kvm_sev_info
{
136 bool active
; /* SEV enabled guest */
137 unsigned int asid
; /* ASID used for this guest */
138 unsigned int handle
; /* SEV firmware handle */
139 int fd
; /* SEV device fd */
140 unsigned long pages_locked
; /* Number of pages locked */
141 struct list_head regions_list
; /* List of registered regions */
147 /* Struct members for AVIC */
150 struct page
*avic_logical_id_table_page
;
151 struct page
*avic_physical_id_table_page
;
152 struct hlist_node hnode
;
154 struct kvm_sev_info sev_info
;
159 struct nested_state
{
165 /* These are the merged vectors */
168 /* gpa pointers to the real vectors */
172 /* A VMEXIT is required but not yet emulated */
175 /* cache for intercepts of the guest */
178 u32 intercept_exceptions
;
181 /* Nested Paging related state */
185 #define MSRPM_OFFSETS 16
186 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
189 * Set osvw_len to higher value when updated Revision Guides
190 * are published and we know what the new status bits are
192 static uint64_t osvw_len
= 4, osvw_status
;
195 struct kvm_vcpu vcpu
;
197 unsigned long vmcb_pa
;
198 struct svm_cpu_data
*svm_data
;
199 uint64_t asid_generation
;
200 uint64_t sysenter_esp
;
201 uint64_t sysenter_eip
;
208 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
222 struct nested_state nested
;
225 u64 nmi_singlestep_guest_rflags
;
227 unsigned int3_injected
;
228 unsigned long int3_rip
;
230 /* cached guest cpuid flags for faster access */
231 bool nrips_enabled
: 1;
234 struct page
*avic_backing_page
;
235 u64
*avic_physical_id_cache
;
236 bool avic_is_running
;
239 * Per-vcpu list of struct amd_svm_iommu_ir:
240 * This is used mainly to store interrupt remapping information used
241 * when update the vcpu affinity. This avoids the need to scan for
242 * IRTE and try to match ga_tag in the IOMMU driver.
244 struct list_head ir_list
;
245 spinlock_t ir_list_lock
;
247 /* which host CPU was used for running this vcpu */
248 unsigned int last_cpu
;
252 * This is a wrapper of struct amd_iommu_ir_data.
254 struct amd_svm_iommu_ir
{
255 struct list_head node
; /* Used by SVM for per-vcpu ir_list */
256 void *data
; /* Storing pointer to struct amd_ir_data */
259 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
260 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
262 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
263 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
264 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
265 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
267 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
268 #define TSC_RATIO_DEFAULT 0x0100000000ULL
270 #define MSR_INVALID 0xffffffffU
272 static const struct svm_direct_access_msrs
{
273 u32 index
; /* Index of the MSR */
274 bool always
; /* True if intercept is always on */
275 } direct_access_msrs
[] = {
276 { .index
= MSR_STAR
, .always
= true },
277 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
279 { .index
= MSR_GS_BASE
, .always
= true },
280 { .index
= MSR_FS_BASE
, .always
= true },
281 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
282 { .index
= MSR_LSTAR
, .always
= true },
283 { .index
= MSR_CSTAR
, .always
= true },
284 { .index
= MSR_SYSCALL_MASK
, .always
= true },
286 { .index
= MSR_IA32_SPEC_CTRL
, .always
= false },
287 { .index
= MSR_IA32_PRED_CMD
, .always
= false },
288 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
289 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
290 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
291 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
292 { .index
= MSR_INVALID
, .always
= false },
295 /* enable NPT for AMD64 and X86 with PAE */
296 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
297 static bool npt_enabled
= true;
299 static bool npt_enabled
;
303 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
304 * pause_filter_count: On processors that support Pause filtering(indicated
305 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
306 * count value. On VMRUN this value is loaded into an internal counter.
307 * Each time a pause instruction is executed, this counter is decremented
308 * until it reaches zero at which time a #VMEXIT is generated if pause
309 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
310 * Intercept Filtering for more details.
311 * This also indicate if ple logic enabled.
313 * pause_filter_thresh: In addition, some processor families support advanced
314 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
315 * the amount of time a guest is allowed to execute in a pause loop.
316 * In this mode, a 16-bit pause filter threshold field is added in the
317 * VMCB. The threshold value is a cycle count that is used to reset the
318 * pause counter. As with simple pause filtering, VMRUN loads the pause
319 * count value from VMCB into an internal counter. Then, on each pause
320 * instruction the hardware checks the elapsed number of cycles since
321 * the most recent pause instruction against the pause filter threshold.
322 * If the elapsed cycle count is greater than the pause filter threshold,
323 * then the internal pause count is reloaded from the VMCB and execution
324 * continues. If the elapsed cycle count is less than the pause filter
325 * threshold, then the internal pause count is decremented. If the count
326 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
327 * triggered. If advanced pause filtering is supported and pause filter
328 * threshold field is set to zero, the filter will operate in the simpler,
332 static unsigned short pause_filter_thresh
= KVM_DEFAULT_PLE_GAP
;
333 module_param(pause_filter_thresh
, ushort
, 0444);
335 static unsigned short pause_filter_count
= KVM_SVM_DEFAULT_PLE_WINDOW
;
336 module_param(pause_filter_count
, ushort
, 0444);
338 /* Default doubles per-vcpu window every exit. */
339 static unsigned short pause_filter_count_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
340 module_param(pause_filter_count_grow
, ushort
, 0444);
342 /* Default resets per-vcpu window every exit to pause_filter_count. */
343 static unsigned short pause_filter_count_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
344 module_param(pause_filter_count_shrink
, ushort
, 0444);
346 /* Default is to compute the maximum so we can never overflow. */
347 static unsigned short pause_filter_count_max
= KVM_SVM_DEFAULT_PLE_WINDOW_MAX
;
348 module_param(pause_filter_count_max
, ushort
, 0444);
350 /* allow nested paging (virtualized MMU) for all guests */
351 static int npt
= true;
352 module_param(npt
, int, S_IRUGO
);
354 /* allow nested virtualization in KVM/SVM */
355 static int nested
= true;
356 module_param(nested
, int, S_IRUGO
);
358 /* enable / disable AVIC */
360 #ifdef CONFIG_X86_LOCAL_APIC
361 module_param(avic
, int, S_IRUGO
);
364 /* enable/disable Virtual VMLOAD VMSAVE */
365 static int vls
= true;
366 module_param(vls
, int, 0444);
368 /* enable/disable Virtual GIF */
369 static int vgif
= true;
370 module_param(vgif
, int, 0444);
372 /* enable/disable SEV support */
373 static int sev
= IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
);
374 module_param(sev
, int, 0444);
376 static u8 rsm_ins_bytes
[] = "\x0f\xaa";
378 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
);
379 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
);
380 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
382 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
383 static int nested_svm_intercept(struct vcpu_svm
*svm
);
384 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
385 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
386 bool has_error_code
, u32 error_code
);
389 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
390 pause filter count */
391 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
392 VMCB_ASID
, /* ASID */
393 VMCB_INTR
, /* int_ctl, int_vector */
394 VMCB_NPT
, /* npt_en, nCR3, gPAT */
395 VMCB_CR
, /* CR0, CR3, CR4, EFER */
396 VMCB_DR
, /* DR6, DR7 */
397 VMCB_DT
, /* GDT, IDT */
398 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
399 VMCB_CR2
, /* CR2 only */
400 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
401 VMCB_AVIC
, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
402 * AVIC PHYSICAL_TABLE pointer,
403 * AVIC LOGICAL_TABLE pointer
408 /* TPR and CR2 are always written before VMRUN */
409 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
411 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
413 static unsigned int max_sev_asid
;
414 static unsigned int min_sev_asid
;
415 static unsigned long *sev_asid_bitmap
;
416 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
419 struct list_head list
;
420 unsigned long npages
;
427 static inline struct kvm_svm
*to_kvm_svm(struct kvm
*kvm
)
429 return container_of(kvm
, struct kvm_svm
, kvm
);
432 static inline bool svm_sev_enabled(void)
437 static inline bool sev_guest(struct kvm
*kvm
)
439 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
444 static inline int sev_get_asid(struct kvm
*kvm
)
446 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
451 static inline void mark_all_dirty(struct vmcb
*vmcb
)
453 vmcb
->control
.clean
= 0;
456 static inline void mark_all_clean(struct vmcb
*vmcb
)
458 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
459 & ~VMCB_ALWAYS_DIRTY_MASK
;
462 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
464 vmcb
->control
.clean
&= ~(1 << bit
);
467 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
469 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
472 static inline void avic_update_vapic_bar(struct vcpu_svm
*svm
, u64 data
)
474 svm
->vmcb
->control
.avic_vapic_bar
= data
& VMCB_AVIC_APIC_BAR_MASK
;
475 mark_dirty(svm
->vmcb
, VMCB_AVIC
);
478 static inline bool avic_vcpu_is_running(struct kvm_vcpu
*vcpu
)
480 struct vcpu_svm
*svm
= to_svm(vcpu
);
481 u64
*entry
= svm
->avic_physical_id_cache
;
486 return (READ_ONCE(*entry
) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
489 static void recalc_intercepts(struct vcpu_svm
*svm
)
491 struct vmcb_control_area
*c
, *h
;
492 struct nested_state
*g
;
494 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
496 if (!is_guest_mode(&svm
->vcpu
))
499 c
= &svm
->vmcb
->control
;
500 h
= &svm
->nested
.hsave
->control
;
503 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
504 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
505 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
506 c
->intercept
= h
->intercept
| g
->intercept
;
509 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
511 if (is_guest_mode(&svm
->vcpu
))
512 return svm
->nested
.hsave
;
517 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
519 struct vmcb
*vmcb
= get_host_vmcb(svm
);
521 vmcb
->control
.intercept_cr
|= (1U << bit
);
523 recalc_intercepts(svm
);
526 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
528 struct vmcb
*vmcb
= get_host_vmcb(svm
);
530 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
532 recalc_intercepts(svm
);
535 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
537 struct vmcb
*vmcb
= get_host_vmcb(svm
);
539 return vmcb
->control
.intercept_cr
& (1U << bit
);
542 static inline void set_dr_intercepts(struct vcpu_svm
*svm
)
544 struct vmcb
*vmcb
= get_host_vmcb(svm
);
546 vmcb
->control
.intercept_dr
= (1 << INTERCEPT_DR0_READ
)
547 | (1 << INTERCEPT_DR1_READ
)
548 | (1 << INTERCEPT_DR2_READ
)
549 | (1 << INTERCEPT_DR3_READ
)
550 | (1 << INTERCEPT_DR4_READ
)
551 | (1 << INTERCEPT_DR5_READ
)
552 | (1 << INTERCEPT_DR6_READ
)
553 | (1 << INTERCEPT_DR7_READ
)
554 | (1 << INTERCEPT_DR0_WRITE
)
555 | (1 << INTERCEPT_DR1_WRITE
)
556 | (1 << INTERCEPT_DR2_WRITE
)
557 | (1 << INTERCEPT_DR3_WRITE
)
558 | (1 << INTERCEPT_DR4_WRITE
)
559 | (1 << INTERCEPT_DR5_WRITE
)
560 | (1 << INTERCEPT_DR6_WRITE
)
561 | (1 << INTERCEPT_DR7_WRITE
);
563 recalc_intercepts(svm
);
566 static inline void clr_dr_intercepts(struct vcpu_svm
*svm
)
568 struct vmcb
*vmcb
= get_host_vmcb(svm
);
570 vmcb
->control
.intercept_dr
= 0;
572 recalc_intercepts(svm
);
575 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
577 struct vmcb
*vmcb
= get_host_vmcb(svm
);
579 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
581 recalc_intercepts(svm
);
584 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
586 struct vmcb
*vmcb
= get_host_vmcb(svm
);
588 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
590 recalc_intercepts(svm
);
593 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
595 struct vmcb
*vmcb
= get_host_vmcb(svm
);
597 vmcb
->control
.intercept
|= (1ULL << bit
);
599 recalc_intercepts(svm
);
602 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
604 struct vmcb
*vmcb
= get_host_vmcb(svm
);
606 vmcb
->control
.intercept
&= ~(1ULL << bit
);
608 recalc_intercepts(svm
);
611 static inline bool vgif_enabled(struct vcpu_svm
*svm
)
613 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_ENABLE_MASK
);
616 static inline void enable_gif(struct vcpu_svm
*svm
)
618 if (vgif_enabled(svm
))
619 svm
->vmcb
->control
.int_ctl
|= V_GIF_MASK
;
621 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
624 static inline void disable_gif(struct vcpu_svm
*svm
)
626 if (vgif_enabled(svm
))
627 svm
->vmcb
->control
.int_ctl
&= ~V_GIF_MASK
;
629 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
632 static inline bool gif_set(struct vcpu_svm
*svm
)
634 if (vgif_enabled(svm
))
635 return !!(svm
->vmcb
->control
.int_ctl
& V_GIF_MASK
);
637 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
640 static unsigned long iopm_base
;
642 struct kvm_ldttss_desc
{
645 unsigned base1
:8, type
:5, dpl
:2, p
:1;
646 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
649 } __attribute__((packed
));
651 struct svm_cpu_data
{
658 struct kvm_ldttss_desc
*tss_desc
;
660 struct page
*save_area
;
661 struct vmcb
*current_vmcb
;
663 /* index = sev_asid, value = vmcb pointer */
664 struct vmcb
**sev_vmcbs
;
667 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
669 struct svm_init_data
{
674 static const u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
676 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
677 #define MSRS_RANGE_SIZE 2048
678 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
680 static u32
svm_msrpm_offset(u32 msr
)
685 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
686 if (msr
< msrpm_ranges
[i
] ||
687 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
690 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
691 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
693 /* Now we have the u8 offset - but need the u32 offset */
697 /* MSR not in any range */
701 #define MAX_INST_SIZE 15
703 static inline void clgi(void)
705 asm volatile (__ex(SVM_CLGI
));
708 static inline void stgi(void)
710 asm volatile (__ex(SVM_STGI
));
713 static inline void invlpga(unsigned long addr
, u32 asid
)
715 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
718 static int get_npt_level(struct kvm_vcpu
*vcpu
)
721 return PT64_ROOT_4LEVEL
;
723 return PT32E_ROOT_LEVEL
;
727 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
729 vcpu
->arch
.efer
= efer
;
730 if (!npt_enabled
&& !(efer
& EFER_LMA
))
733 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
734 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
737 static int is_external_interrupt(u32 info
)
739 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
740 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
743 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
745 struct vcpu_svm
*svm
= to_svm(vcpu
);
748 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
749 ret
= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
753 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
755 struct vcpu_svm
*svm
= to_svm(vcpu
);
758 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
760 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
764 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
766 struct vcpu_svm
*svm
= to_svm(vcpu
);
768 if (svm
->vmcb
->control
.next_rip
!= 0) {
769 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS
));
770 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
773 if (!svm
->next_rip
) {
774 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
776 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
779 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
780 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
781 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
783 kvm_rip_write(vcpu
, svm
->next_rip
);
784 svm_set_interrupt_shadow(vcpu
, 0);
787 static void svm_queue_exception(struct kvm_vcpu
*vcpu
)
789 struct vcpu_svm
*svm
= to_svm(vcpu
);
790 unsigned nr
= vcpu
->arch
.exception
.nr
;
791 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
792 bool reinject
= vcpu
->arch
.exception
.injected
;
793 u32 error_code
= vcpu
->arch
.exception
.error_code
;
796 * If we are within a nested VM we'd better #VMEXIT and let the guest
797 * handle the exception
800 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
803 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
804 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
807 * For guest debugging where we have to reinject #BP if some
808 * INT3 is guest-owned:
809 * Emulate nRIP by moving RIP forward. Will fail if injection
810 * raises a fault that is not intercepted. Still better than
811 * failing in all cases.
813 skip_emulated_instruction(&svm
->vcpu
);
814 rip
= kvm_rip_read(&svm
->vcpu
);
815 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
816 svm
->int3_injected
= rip
- old_rip
;
819 svm
->vmcb
->control
.event_inj
= nr
821 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
822 | SVM_EVTINJ_TYPE_EXEPT
;
823 svm
->vmcb
->control
.event_inj_err
= error_code
;
826 static void svm_init_erratum_383(void)
832 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH
))
835 /* Use _safe variants to not break nested virtualization */
836 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
842 low
= lower_32_bits(val
);
843 high
= upper_32_bits(val
);
845 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
847 erratum_383_found
= true;
850 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
853 * Guests should see errata 400 and 415 as fixed (assuming that
854 * HLT and IO instructions are intercepted).
856 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
857 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
860 * By increasing VCPU's osvw.length to 3 we are telling the guest that
861 * all osvw.status bits inside that length, including bit 0 (which is
862 * reserved for erratum 298), are valid. However, if host processor's
863 * osvw_len is 0 then osvw_status[0] carries no information. We need to
864 * be conservative here and therefore we tell the guest that erratum 298
865 * is present (because we really don't know).
867 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
868 vcpu
->arch
.osvw
.status
|= 1;
871 static int has_svm(void)
875 if (!cpu_has_svm(&msg
)) {
876 printk(KERN_INFO
"has_svm: %s\n", msg
);
883 static void svm_hardware_disable(void)
885 /* Make sure we clean up behind us */
886 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
887 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
891 amd_pmu_disable_virt();
894 static int svm_hardware_enable(void)
897 struct svm_cpu_data
*sd
;
899 struct desc_struct
*gdt
;
900 int me
= raw_smp_processor_id();
902 rdmsrl(MSR_EFER
, efer
);
903 if (efer
& EFER_SVME
)
907 pr_err("%s: err EOPNOTSUPP on %d\n", __func__
, me
);
910 sd
= per_cpu(svm_data
, me
);
912 pr_err("%s: svm_data is NULL on %d\n", __func__
, me
);
916 sd
->asid_generation
= 1;
917 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
918 sd
->next_asid
= sd
->max_asid
+ 1;
919 sd
->min_asid
= max_sev_asid
+ 1;
921 gdt
= get_current_gdt_rw();
922 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
924 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
926 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
928 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
929 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
930 __this_cpu_write(current_tsc_ratio
, TSC_RATIO_DEFAULT
);
937 * Note that it is possible to have a system with mixed processor
938 * revisions and therefore different OSVW bits. If bits are not the same
939 * on different processors then choose the worst case (i.e. if erratum
940 * is present on one processor and not on another then assume that the
941 * erratum is present everywhere).
943 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
944 uint64_t len
, status
= 0;
947 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
949 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
953 osvw_status
= osvw_len
= 0;
957 osvw_status
|= status
;
958 osvw_status
&= (1ULL << osvw_len
) - 1;
961 osvw_status
= osvw_len
= 0;
963 svm_init_erratum_383();
965 amd_pmu_enable_virt();
970 static void svm_cpu_uninit(int cpu
)
972 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
977 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
978 kfree(sd
->sev_vmcbs
);
979 __free_page(sd
->save_area
);
983 static int svm_cpu_init(int cpu
)
985 struct svm_cpu_data
*sd
;
988 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
993 sd
->save_area
= alloc_page(GFP_KERNEL
);
997 if (svm_sev_enabled()) {
999 sd
->sev_vmcbs
= kmalloc((max_sev_asid
+ 1) * sizeof(void *), GFP_KERNEL
);
1004 per_cpu(svm_data
, cpu
) = sd
;
1014 static bool valid_msr_intercept(u32 index
)
1018 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
1019 if (direct_access_msrs
[i
].index
== index
)
1025 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, unsigned msr
)
1032 msrpm
= is_guest_mode(vcpu
) ? to_svm(vcpu
)->nested
.msrpm
:
1033 to_svm(vcpu
)->msrpm
;
1035 offset
= svm_msrpm_offset(msr
);
1036 bit_write
= 2 * (msr
& 0x0f) + 1;
1037 tmp
= msrpm
[offset
];
1039 BUG_ON(offset
== MSR_INVALID
);
1041 return !!test_bit(bit_write
, &tmp
);
1044 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
1045 int read
, int write
)
1047 u8 bit_read
, bit_write
;
1052 * If this warning triggers extend the direct_access_msrs list at the
1053 * beginning of the file
1055 WARN_ON(!valid_msr_intercept(msr
));
1057 offset
= svm_msrpm_offset(msr
);
1058 bit_read
= 2 * (msr
& 0x0f);
1059 bit_write
= 2 * (msr
& 0x0f) + 1;
1060 tmp
= msrpm
[offset
];
1062 BUG_ON(offset
== MSR_INVALID
);
1064 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
1065 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
1067 msrpm
[offset
] = tmp
;
1070 static void svm_vcpu_init_msrpm(u32
*msrpm
)
1074 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
1076 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1077 if (!direct_access_msrs
[i
].always
)
1080 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
1084 static void add_msr_offset(u32 offset
)
1088 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
1090 /* Offset already in list? */
1091 if (msrpm_offsets
[i
] == offset
)
1094 /* Slot used by another offset? */
1095 if (msrpm_offsets
[i
] != MSR_INVALID
)
1098 /* Add offset to list */
1099 msrpm_offsets
[i
] = offset
;
1105 * If this BUG triggers the msrpm_offsets table has an overflow. Just
1106 * increase MSRPM_OFFSETS in this case.
1111 static void init_msrpm_offsets(void)
1115 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
1117 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
1120 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
1121 BUG_ON(offset
== MSR_INVALID
);
1123 add_msr_offset(offset
);
1127 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
1129 u32
*msrpm
= svm
->msrpm
;
1131 svm
->vmcb
->control
.virt_ext
|= LBR_CTL_ENABLE_MASK
;
1132 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
1133 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
1134 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
1135 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
1138 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
1140 u32
*msrpm
= svm
->msrpm
;
1142 svm
->vmcb
->control
.virt_ext
&= ~LBR_CTL_ENABLE_MASK
;
1143 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
1144 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
1145 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
1146 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
1149 static void disable_nmi_singlestep(struct vcpu_svm
*svm
)
1151 svm
->nmi_singlestep
= false;
1153 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
)) {
1154 /* Clear our flags if they were not set by the guest */
1155 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
1156 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_TF
;
1157 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
1158 svm
->vmcb
->save
.rflags
&= ~X86_EFLAGS_RF
;
1163 * This hash table is used to map VM_ID to a struct kvm_svm,
1164 * when handling AMD IOMMU GALOG notification to schedule in
1165 * a particular vCPU.
1167 #define SVM_VM_DATA_HASH_BITS 8
1168 static DEFINE_HASHTABLE(svm_vm_data_hash
, SVM_VM_DATA_HASH_BITS
);
1169 static u32 next_vm_id
= 0;
1170 static bool next_vm_id_wrapped
= 0;
1171 static DEFINE_SPINLOCK(svm_vm_data_hash_lock
);
1174 * This function is called from IOMMU driver to notify
1175 * SVM to schedule in a particular vCPU of a particular VM.
1177 static int avic_ga_log_notifier(u32 ga_tag
)
1179 unsigned long flags
;
1180 struct kvm_svm
*kvm_svm
;
1181 struct kvm_vcpu
*vcpu
= NULL
;
1182 u32 vm_id
= AVIC_GATAG_TO_VMID(ga_tag
);
1183 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(ga_tag
);
1185 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__
, vm_id
, vcpu_id
);
1187 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1188 hash_for_each_possible(svm_vm_data_hash
, kvm_svm
, hnode
, vm_id
) {
1189 if (kvm_svm
->avic_vm_id
!= vm_id
)
1191 vcpu
= kvm_get_vcpu_by_id(&kvm_svm
->kvm
, vcpu_id
);
1194 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1197 * At this point, the IOMMU should have already set the pending
1198 * bit in the vAPIC backing page. So, we just need to schedule
1202 kvm_vcpu_wake_up(vcpu
);
1207 static __init
int sev_hardware_setup(void)
1209 struct sev_user_data_status
*status
;
1212 /* Maximum number of encrypted guests supported simultaneously */
1213 max_sev_asid
= cpuid_ecx(0x8000001F);
1218 /* Minimum ASID value that should be used for SEV guest */
1219 min_sev_asid
= cpuid_edx(0x8000001F);
1221 /* Initialize SEV ASID bitmap */
1222 sev_asid_bitmap
= kcalloc(BITS_TO_LONGS(max_sev_asid
),
1223 sizeof(unsigned long), GFP_KERNEL
);
1224 if (!sev_asid_bitmap
)
1227 status
= kmalloc(sizeof(*status
), GFP_KERNEL
);
1232 * Check SEV platform status.
1234 * PLATFORM_STATUS can be called in any state, if we failed to query
1235 * the PLATFORM status then either PSP firmware does not support SEV
1236 * feature or SEV firmware is dead.
1238 rc
= sev_platform_status(status
, NULL
);
1242 pr_info("SEV supported\n");
1249 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
1251 struct vcpu_svm
*svm
= to_svm(vcpu
);
1252 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1253 int old
= control
->pause_filter_count
;
1255 control
->pause_filter_count
= __grow_ple_window(old
,
1257 pause_filter_count_grow
,
1258 pause_filter_count_max
);
1260 if (control
->pause_filter_count
!= old
)
1261 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1263 trace_kvm_ple_window_grow(vcpu
->vcpu_id
,
1264 control
->pause_filter_count
, old
);
1267 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
1269 struct vcpu_svm
*svm
= to_svm(vcpu
);
1270 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1271 int old
= control
->pause_filter_count
;
1273 control
->pause_filter_count
=
1274 __shrink_ple_window(old
,
1276 pause_filter_count_shrink
,
1277 pause_filter_count
);
1278 if (control
->pause_filter_count
!= old
)
1279 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1281 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
,
1282 control
->pause_filter_count
, old
);
1285 static __init
int svm_hardware_setup(void)
1288 struct page
*iopm_pages
;
1292 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
1297 iopm_va
= page_address(iopm_pages
);
1298 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
1299 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
1301 init_msrpm_offsets();
1303 if (boot_cpu_has(X86_FEATURE_NX
))
1304 kvm_enable_efer_bits(EFER_NX
);
1306 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
1307 kvm_enable_efer_bits(EFER_FFXSR
);
1309 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
1310 kvm_has_tsc_control
= true;
1311 kvm_max_tsc_scaling_ratio
= TSC_RATIO_MAX
;
1312 kvm_tsc_scaling_ratio_frac_bits
= 32;
1315 /* Check for pause filtering support */
1316 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1317 pause_filter_count
= 0;
1318 pause_filter_thresh
= 0;
1319 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD
)) {
1320 pause_filter_thresh
= 0;
1324 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
1325 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
1329 if (boot_cpu_has(X86_FEATURE_SEV
) &&
1330 IS_ENABLED(CONFIG_KVM_AMD_SEV
)) {
1331 r
= sev_hardware_setup();
1339 for_each_possible_cpu(cpu
) {
1340 r
= svm_cpu_init(cpu
);
1345 if (!boot_cpu_has(X86_FEATURE_NPT
))
1346 npt_enabled
= false;
1348 if (npt_enabled
&& !npt
) {
1349 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
1350 npt_enabled
= false;
1354 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
1361 !boot_cpu_has(X86_FEATURE_AVIC
) ||
1362 !IS_ENABLED(CONFIG_X86_LOCAL_APIC
)) {
1365 pr_info("AVIC enabled\n");
1367 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier
);
1373 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD
) ||
1374 !IS_ENABLED(CONFIG_X86_64
)) {
1377 pr_info("Virtual VMLOAD VMSAVE supported\n");
1382 if (!boot_cpu_has(X86_FEATURE_VGIF
))
1385 pr_info("Virtual GIF supported\n");
1391 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
1396 static __exit
void svm_hardware_unsetup(void)
1400 if (svm_sev_enabled())
1401 kfree(sev_asid_bitmap
);
1403 for_each_possible_cpu(cpu
)
1404 svm_cpu_uninit(cpu
);
1406 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
1410 static void init_seg(struct vmcb_seg
*seg
)
1413 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
1414 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
1415 seg
->limit
= 0xffff;
1419 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
1422 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
1423 seg
->limit
= 0xffff;
1427 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1429 struct vcpu_svm
*svm
= to_svm(vcpu
);
1430 u64 g_tsc_offset
= 0;
1432 if (is_guest_mode(vcpu
)) {
1433 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1434 svm
->nested
.hsave
->control
.tsc_offset
;
1435 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1437 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
1438 svm
->vmcb
->control
.tsc_offset
,
1441 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1443 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1446 static void avic_init_vmcb(struct vcpu_svm
*svm
)
1448 struct vmcb
*vmcb
= svm
->vmcb
;
1449 struct kvm_svm
*kvm_svm
= to_kvm_svm(svm
->vcpu
.kvm
);
1450 phys_addr_t bpa
= __sme_set(page_to_phys(svm
->avic_backing_page
));
1451 phys_addr_t lpa
= __sme_set(page_to_phys(kvm_svm
->avic_logical_id_table_page
));
1452 phys_addr_t ppa
= __sme_set(page_to_phys(kvm_svm
->avic_physical_id_table_page
));
1454 vmcb
->control
.avic_backing_page
= bpa
& AVIC_HPA_MASK
;
1455 vmcb
->control
.avic_logical_id
= lpa
& AVIC_HPA_MASK
;
1456 vmcb
->control
.avic_physical_id
= ppa
& AVIC_HPA_MASK
;
1457 vmcb
->control
.avic_physical_id
|= AVIC_MAX_PHYSICAL_ID_COUNT
;
1458 vmcb
->control
.int_ctl
|= AVIC_ENABLE_MASK
;
1461 static void init_vmcb(struct vcpu_svm
*svm
)
1463 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1464 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1466 svm
->vcpu
.arch
.hflags
= 0;
1468 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1469 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1470 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1471 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1472 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1473 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1474 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
1475 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1477 set_dr_intercepts(svm
);
1479 set_exception_intercept(svm
, PF_VECTOR
);
1480 set_exception_intercept(svm
, UD_VECTOR
);
1481 set_exception_intercept(svm
, MC_VECTOR
);
1482 set_exception_intercept(svm
, AC_VECTOR
);
1483 set_exception_intercept(svm
, DB_VECTOR
);
1485 * Guest access to VMware backdoor ports could legitimately
1486 * trigger #GP because of TSS I/O permission bitmap.
1487 * We intercept those #GP and allow access to them anyway
1490 if (enable_vmware_backdoor
)
1491 set_exception_intercept(svm
, GP_VECTOR
);
1493 set_intercept(svm
, INTERCEPT_INTR
);
1494 set_intercept(svm
, INTERCEPT_NMI
);
1495 set_intercept(svm
, INTERCEPT_SMI
);
1496 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1497 set_intercept(svm
, INTERCEPT_RDPMC
);
1498 set_intercept(svm
, INTERCEPT_CPUID
);
1499 set_intercept(svm
, INTERCEPT_INVD
);
1500 set_intercept(svm
, INTERCEPT_INVLPG
);
1501 set_intercept(svm
, INTERCEPT_INVLPGA
);
1502 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1503 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1504 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1505 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1506 set_intercept(svm
, INTERCEPT_VMRUN
);
1507 set_intercept(svm
, INTERCEPT_VMMCALL
);
1508 set_intercept(svm
, INTERCEPT_VMLOAD
);
1509 set_intercept(svm
, INTERCEPT_VMSAVE
);
1510 set_intercept(svm
, INTERCEPT_STGI
);
1511 set_intercept(svm
, INTERCEPT_CLGI
);
1512 set_intercept(svm
, INTERCEPT_SKINIT
);
1513 set_intercept(svm
, INTERCEPT_WBINVD
);
1514 set_intercept(svm
, INTERCEPT_XSETBV
);
1515 set_intercept(svm
, INTERCEPT_RSM
);
1517 if (!kvm_mwait_in_guest(svm
->vcpu
.kvm
)) {
1518 set_intercept(svm
, INTERCEPT_MONITOR
);
1519 set_intercept(svm
, INTERCEPT_MWAIT
);
1522 if (!kvm_hlt_in_guest(svm
->vcpu
.kvm
))
1523 set_intercept(svm
, INTERCEPT_HLT
);
1525 control
->iopm_base_pa
= __sme_set(iopm_base
);
1526 control
->msrpm_base_pa
= __sme_set(__pa(svm
->msrpm
));
1527 control
->int_ctl
= V_INTR_MASKING_MASK
;
1529 init_seg(&save
->es
);
1530 init_seg(&save
->ss
);
1531 init_seg(&save
->ds
);
1532 init_seg(&save
->fs
);
1533 init_seg(&save
->gs
);
1535 save
->cs
.selector
= 0xf000;
1536 save
->cs
.base
= 0xffff0000;
1537 /* Executable/Readable Code Segment */
1538 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1539 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1540 save
->cs
.limit
= 0xffff;
1542 save
->gdtr
.limit
= 0xffff;
1543 save
->idtr
.limit
= 0xffff;
1545 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1546 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1548 svm_set_efer(&svm
->vcpu
, 0);
1549 save
->dr6
= 0xffff0ff0;
1550 kvm_set_rflags(&svm
->vcpu
, 2);
1551 save
->rip
= 0x0000fff0;
1552 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1555 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1556 * It also updates the guest-visible cr0 value.
1558 svm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1559 kvm_mmu_reset_context(&svm
->vcpu
);
1561 save
->cr4
= X86_CR4_PAE
;
1565 /* Setup VMCB for Nested Paging */
1566 control
->nested_ctl
|= SVM_NESTED_CTL_NP_ENABLE
;
1567 clr_intercept(svm
, INTERCEPT_INVLPG
);
1568 clr_exception_intercept(svm
, PF_VECTOR
);
1569 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1570 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1571 save
->g_pat
= svm
->vcpu
.arch
.pat
;
1575 svm
->asid_generation
= 0;
1577 svm
->nested
.vmcb
= 0;
1578 svm
->vcpu
.arch
.hflags
= 0;
1580 if (pause_filter_count
) {
1581 control
->pause_filter_count
= pause_filter_count
;
1582 if (pause_filter_thresh
)
1583 control
->pause_filter_thresh
= pause_filter_thresh
;
1584 set_intercept(svm
, INTERCEPT_PAUSE
);
1586 clr_intercept(svm
, INTERCEPT_PAUSE
);
1589 if (kvm_vcpu_apicv_active(&svm
->vcpu
))
1590 avic_init_vmcb(svm
);
1593 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1594 * in VMCB and clear intercepts to avoid #VMEXIT.
1597 clr_intercept(svm
, INTERCEPT_VMLOAD
);
1598 clr_intercept(svm
, INTERCEPT_VMSAVE
);
1599 svm
->vmcb
->control
.virt_ext
|= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK
;
1603 clr_intercept(svm
, INTERCEPT_STGI
);
1604 clr_intercept(svm
, INTERCEPT_CLGI
);
1605 svm
->vmcb
->control
.int_ctl
|= V_GIF_ENABLE_MASK
;
1608 if (sev_guest(svm
->vcpu
.kvm
)) {
1609 svm
->vmcb
->control
.nested_ctl
|= SVM_NESTED_CTL_SEV_ENABLE
;
1610 clr_exception_intercept(svm
, UD_VECTOR
);
1613 mark_all_dirty(svm
->vmcb
);
1619 static u64
*avic_get_physical_id_entry(struct kvm_vcpu
*vcpu
,
1622 u64
*avic_physical_id_table
;
1623 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
1625 if (index
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1628 avic_physical_id_table
= page_address(kvm_svm
->avic_physical_id_table_page
);
1630 return &avic_physical_id_table
[index
];
1635 * AVIC hardware walks the nested page table to check permissions,
1636 * but does not use the SPA address specified in the leaf page
1637 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1638 * field of the VMCB. Therefore, we set up the
1639 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1641 static int avic_init_access_page(struct kvm_vcpu
*vcpu
)
1643 struct kvm
*kvm
= vcpu
->kvm
;
1646 if (kvm
->arch
.apic_access_page_done
)
1649 ret
= x86_set_memory_region(kvm
,
1650 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
1651 APIC_DEFAULT_PHYS_BASE
,
1656 kvm
->arch
.apic_access_page_done
= true;
1660 static int avic_init_backing_page(struct kvm_vcpu
*vcpu
)
1663 u64
*entry
, new_entry
;
1664 int id
= vcpu
->vcpu_id
;
1665 struct vcpu_svm
*svm
= to_svm(vcpu
);
1667 ret
= avic_init_access_page(vcpu
);
1671 if (id
>= AVIC_MAX_PHYSICAL_ID_COUNT
)
1674 if (!svm
->vcpu
.arch
.apic
->regs
)
1677 svm
->avic_backing_page
= virt_to_page(svm
->vcpu
.arch
.apic
->regs
);
1679 /* Setting AVIC backing page address in the phy APIC ID table */
1680 entry
= avic_get_physical_id_entry(vcpu
, id
);
1684 new_entry
= READ_ONCE(*entry
);
1685 new_entry
= __sme_set((page_to_phys(svm
->avic_backing_page
) &
1686 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK
) |
1687 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK
);
1688 WRITE_ONCE(*entry
, new_entry
);
1690 svm
->avic_physical_id_cache
= entry
;
1695 static void __sev_asid_free(int asid
)
1697 struct svm_cpu_data
*sd
;
1701 clear_bit(pos
, sev_asid_bitmap
);
1703 for_each_possible_cpu(cpu
) {
1704 sd
= per_cpu(svm_data
, cpu
);
1705 sd
->sev_vmcbs
[pos
] = NULL
;
1709 static void sev_asid_free(struct kvm
*kvm
)
1711 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1713 __sev_asid_free(sev
->asid
);
1716 static void sev_unbind_asid(struct kvm
*kvm
, unsigned int handle
)
1718 struct sev_data_decommission
*decommission
;
1719 struct sev_data_deactivate
*data
;
1724 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
1728 /* deactivate handle */
1729 data
->handle
= handle
;
1730 sev_guest_deactivate(data
, NULL
);
1732 wbinvd_on_all_cpus();
1733 sev_guest_df_flush(NULL
);
1736 decommission
= kzalloc(sizeof(*decommission
), GFP_KERNEL
);
1740 /* decommission handle */
1741 decommission
->handle
= handle
;
1742 sev_guest_decommission(decommission
, NULL
);
1744 kfree(decommission
);
1747 static struct page
**sev_pin_memory(struct kvm
*kvm
, unsigned long uaddr
,
1748 unsigned long ulen
, unsigned long *n
,
1751 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1752 unsigned long npages
, npinned
, size
;
1753 unsigned long locked
, lock_limit
;
1754 struct page
**pages
;
1757 /* Calculate number of pages. */
1758 first
= (uaddr
& PAGE_MASK
) >> PAGE_SHIFT
;
1759 last
= ((uaddr
+ ulen
- 1) & PAGE_MASK
) >> PAGE_SHIFT
;
1760 npages
= (last
- first
+ 1);
1762 locked
= sev
->pages_locked
+ npages
;
1763 lock_limit
= rlimit(RLIMIT_MEMLOCK
) >> PAGE_SHIFT
;
1764 if (locked
> lock_limit
&& !capable(CAP_IPC_LOCK
)) {
1765 pr_err("SEV: %lu locked pages exceed the lock limit of %lu.\n", locked
, lock_limit
);
1769 /* Avoid using vmalloc for smaller buffers. */
1770 size
= npages
* sizeof(struct page
*);
1771 if (size
> PAGE_SIZE
)
1772 pages
= vmalloc(size
);
1774 pages
= kmalloc(size
, GFP_KERNEL
);
1779 /* Pin the user virtual address. */
1780 npinned
= get_user_pages_fast(uaddr
, npages
, write
? FOLL_WRITE
: 0, pages
);
1781 if (npinned
!= npages
) {
1782 pr_err("SEV: Failure locking %lu pages.\n", npages
);
1787 sev
->pages_locked
= locked
;
1793 release_pages(pages
, npinned
);
1799 static void sev_unpin_memory(struct kvm
*kvm
, struct page
**pages
,
1800 unsigned long npages
)
1802 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1804 release_pages(pages
, npages
);
1806 sev
->pages_locked
-= npages
;
1809 static void sev_clflush_pages(struct page
*pages
[], unsigned long npages
)
1811 uint8_t *page_virtual
;
1814 if (npages
== 0 || pages
== NULL
)
1817 for (i
= 0; i
< npages
; i
++) {
1818 page_virtual
= kmap_atomic(pages
[i
]);
1819 clflush_cache_range(page_virtual
, PAGE_SIZE
);
1820 kunmap_atomic(page_virtual
);
1824 static void __unregister_enc_region_locked(struct kvm
*kvm
,
1825 struct enc_region
*region
)
1828 * The guest may change the memory encryption attribute from C=0 -> C=1
1829 * or vice versa for this memory range. Lets make sure caches are
1830 * flushed to ensure that guest data gets written into memory with
1833 sev_clflush_pages(region
->pages
, region
->npages
);
1835 sev_unpin_memory(kvm
, region
->pages
, region
->npages
);
1836 list_del(®ion
->list
);
1840 static struct kvm
*svm_vm_alloc(void)
1842 struct kvm_svm
*kvm_svm
= kzalloc(sizeof(struct kvm_svm
), GFP_KERNEL
);
1843 return &kvm_svm
->kvm
;
1846 static void svm_vm_free(struct kvm
*kvm
)
1848 kfree(to_kvm_svm(kvm
));
1851 static void sev_vm_destroy(struct kvm
*kvm
)
1853 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
1854 struct list_head
*head
= &sev
->regions_list
;
1855 struct list_head
*pos
, *q
;
1857 if (!sev_guest(kvm
))
1860 mutex_lock(&kvm
->lock
);
1863 * if userspace was terminated before unregistering the memory regions
1864 * then lets unpin all the registered memory.
1866 if (!list_empty(head
)) {
1867 list_for_each_safe(pos
, q
, head
) {
1868 __unregister_enc_region_locked(kvm
,
1869 list_entry(pos
, struct enc_region
, list
));
1873 mutex_unlock(&kvm
->lock
);
1875 sev_unbind_asid(kvm
, sev
->handle
);
1879 static void avic_vm_destroy(struct kvm
*kvm
)
1881 unsigned long flags
;
1882 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1887 if (kvm_svm
->avic_logical_id_table_page
)
1888 __free_page(kvm_svm
->avic_logical_id_table_page
);
1889 if (kvm_svm
->avic_physical_id_table_page
)
1890 __free_page(kvm_svm
->avic_physical_id_table_page
);
1892 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1893 hash_del(&kvm_svm
->hnode
);
1894 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1897 static void svm_vm_destroy(struct kvm
*kvm
)
1899 avic_vm_destroy(kvm
);
1900 sev_vm_destroy(kvm
);
1903 static int avic_vm_init(struct kvm
*kvm
)
1905 unsigned long flags
;
1907 struct kvm_svm
*kvm_svm
= to_kvm_svm(kvm
);
1909 struct page
*p_page
;
1910 struct page
*l_page
;
1916 /* Allocating physical APIC ID table (4KB) */
1917 p_page
= alloc_page(GFP_KERNEL
);
1921 kvm_svm
->avic_physical_id_table_page
= p_page
;
1922 clear_page(page_address(p_page
));
1924 /* Allocating logical APIC ID table (4KB) */
1925 l_page
= alloc_page(GFP_KERNEL
);
1929 kvm_svm
->avic_logical_id_table_page
= l_page
;
1930 clear_page(page_address(l_page
));
1932 spin_lock_irqsave(&svm_vm_data_hash_lock
, flags
);
1934 vm_id
= next_vm_id
= (next_vm_id
+ 1) & AVIC_VM_ID_MASK
;
1935 if (vm_id
== 0) { /* id is 1-based, zero is not okay */
1936 next_vm_id_wrapped
= 1;
1939 /* Is it still in use? Only possible if wrapped at least once */
1940 if (next_vm_id_wrapped
) {
1941 hash_for_each_possible(svm_vm_data_hash
, k2
, hnode
, vm_id
) {
1942 if (k2
->avic_vm_id
== vm_id
)
1946 kvm_svm
->avic_vm_id
= vm_id
;
1947 hash_add(svm_vm_data_hash
, &kvm_svm
->hnode
, kvm_svm
->avic_vm_id
);
1948 spin_unlock_irqrestore(&svm_vm_data_hash_lock
, flags
);
1953 avic_vm_destroy(kvm
);
1958 avic_update_iommu_vcpu_affinity(struct kvm_vcpu
*vcpu
, int cpu
, bool r
)
1961 unsigned long flags
;
1962 struct amd_svm_iommu_ir
*ir
;
1963 struct vcpu_svm
*svm
= to_svm(vcpu
);
1965 if (!kvm_arch_has_assigned_device(vcpu
->kvm
))
1969 * Here, we go through the per-vcpu ir_list to update all existing
1970 * interrupt remapping table entry targeting this vcpu.
1972 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
1974 if (list_empty(&svm
->ir_list
))
1977 list_for_each_entry(ir
, &svm
->ir_list
, node
) {
1978 ret
= amd_iommu_update_ga(cpu
, r
, ir
->data
);
1983 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
1987 static void avic_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1990 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1991 int h_physical_id
= kvm_cpu_get_apicid(cpu
);
1992 struct vcpu_svm
*svm
= to_svm(vcpu
);
1994 if (!kvm_vcpu_apicv_active(vcpu
))
1997 if (WARN_ON(h_physical_id
>= AVIC_MAX_PHYSICAL_ID_COUNT
))
2000 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2001 WARN_ON(entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
);
2003 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
;
2004 entry
|= (h_physical_id
& AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK
);
2006 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2007 if (svm
->avic_is_running
)
2008 entry
|= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2010 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2011 avic_update_iommu_vcpu_affinity(vcpu
, h_physical_id
,
2012 svm
->avic_is_running
);
2015 static void avic_vcpu_put(struct kvm_vcpu
*vcpu
)
2018 struct vcpu_svm
*svm
= to_svm(vcpu
);
2020 if (!kvm_vcpu_apicv_active(vcpu
))
2023 entry
= READ_ONCE(*(svm
->avic_physical_id_cache
));
2024 if (entry
& AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
)
2025 avic_update_iommu_vcpu_affinity(vcpu
, -1, 0);
2027 entry
&= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK
;
2028 WRITE_ONCE(*(svm
->avic_physical_id_cache
), entry
);
2032 * This function is called during VCPU halt/unhalt.
2034 static void avic_set_running(struct kvm_vcpu
*vcpu
, bool is_run
)
2036 struct vcpu_svm
*svm
= to_svm(vcpu
);
2038 svm
->avic_is_running
= is_run
;
2040 avic_vcpu_load(vcpu
, vcpu
->cpu
);
2042 avic_vcpu_put(vcpu
);
2045 static void svm_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
2047 struct vcpu_svm
*svm
= to_svm(vcpu
);
2051 vcpu
->arch
.microcode_version
= 0x01000065;
2055 svm
->vcpu
.arch
.apic_base
= APIC_DEFAULT_PHYS_BASE
|
2056 MSR_IA32_APICBASE_ENABLE
;
2057 if (kvm_vcpu_is_reset_bsp(&svm
->vcpu
))
2058 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
2062 kvm_cpuid(vcpu
, &eax
, &dummy
, &dummy
, &dummy
, true);
2063 kvm_register_write(vcpu
, VCPU_REGS_RDX
, eax
);
2065 if (kvm_vcpu_apicv_active(vcpu
) && !init_event
)
2066 avic_update_vapic_bar(svm
, APIC_DEFAULT_PHYS_BASE
);
2069 static int avic_init_vcpu(struct vcpu_svm
*svm
)
2073 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
2076 ret
= avic_init_backing_page(&svm
->vcpu
);
2080 INIT_LIST_HEAD(&svm
->ir_list
);
2081 spin_lock_init(&svm
->ir_list_lock
);
2086 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
2088 struct vcpu_svm
*svm
;
2090 struct page
*msrpm_pages
;
2091 struct page
*hsave_page
;
2092 struct page
*nested_msrpm_pages
;
2095 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
2101 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
2106 page
= alloc_page(GFP_KERNEL
);
2110 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2114 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
2115 if (!nested_msrpm_pages
)
2118 hsave_page
= alloc_page(GFP_KERNEL
);
2122 err
= avic_init_vcpu(svm
);
2126 /* We initialize this flag to true to make sure that the is_running
2127 * bit would be set the first time the vcpu is loaded.
2129 svm
->avic_is_running
= true;
2131 svm
->nested
.hsave
= page_address(hsave_page
);
2133 svm
->msrpm
= page_address(msrpm_pages
);
2134 svm_vcpu_init_msrpm(svm
->msrpm
);
2136 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
2137 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
2139 svm
->vmcb
= page_address(page
);
2140 clear_page(svm
->vmcb
);
2141 svm
->vmcb_pa
= __sme_set(page_to_pfn(page
) << PAGE_SHIFT
);
2142 svm
->asid_generation
= 0;
2145 svm_init_osvw(&svm
->vcpu
);
2150 __free_page(hsave_page
);
2152 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
2154 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
2158 kvm_vcpu_uninit(&svm
->vcpu
);
2160 kmem_cache_free(kvm_vcpu_cache
, svm
);
2162 return ERR_PTR(err
);
2165 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
2167 struct vcpu_svm
*svm
= to_svm(vcpu
);
2169 __free_page(pfn_to_page(__sme_clr(svm
->vmcb_pa
) >> PAGE_SHIFT
));
2170 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
2171 __free_page(virt_to_page(svm
->nested
.hsave
));
2172 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
2173 kvm_vcpu_uninit(vcpu
);
2174 kmem_cache_free(kvm_vcpu_cache
, svm
);
2176 * The vmcb page can be recycled, causing a false negative in
2177 * svm_vcpu_load(). So do a full IBPB now.
2179 indirect_branch_prediction_barrier();
2182 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2184 struct vcpu_svm
*svm
= to_svm(vcpu
);
2185 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2188 if (unlikely(cpu
!= vcpu
->cpu
)) {
2189 svm
->asid_generation
= 0;
2190 mark_all_dirty(svm
->vmcb
);
2193 #ifdef CONFIG_X86_64
2194 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
2196 savesegment(fs
, svm
->host
.fs
);
2197 savesegment(gs
, svm
->host
.gs
);
2198 svm
->host
.ldt
= kvm_read_ldt();
2200 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2201 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2203 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
2204 u64 tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2205 if (tsc_ratio
!= __this_cpu_read(current_tsc_ratio
)) {
2206 __this_cpu_write(current_tsc_ratio
, tsc_ratio
);
2207 wrmsrl(MSR_AMD64_TSC_RATIO
, tsc_ratio
);
2210 /* This assumes that the kernel never uses MSR_TSC_AUX */
2211 if (static_cpu_has(X86_FEATURE_RDTSCP
))
2212 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
2214 if (sd
->current_vmcb
!= svm
->vmcb
) {
2215 sd
->current_vmcb
= svm
->vmcb
;
2216 indirect_branch_prediction_barrier();
2218 avic_vcpu_load(vcpu
, cpu
);
2221 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
2223 struct vcpu_svm
*svm
= to_svm(vcpu
);
2226 avic_vcpu_put(vcpu
);
2228 ++vcpu
->stat
.host_state_reload
;
2229 kvm_load_ldt(svm
->host
.ldt
);
2230 #ifdef CONFIG_X86_64
2231 loadsegment(fs
, svm
->host
.fs
);
2232 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gsbase
);
2233 load_gs_index(svm
->host
.gs
);
2235 #ifdef CONFIG_X86_32_LAZY_GS
2236 loadsegment(gs
, svm
->host
.gs
);
2239 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
2240 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
2243 static void svm_vcpu_blocking(struct kvm_vcpu
*vcpu
)
2245 avic_set_running(vcpu
, false);
2248 static void svm_vcpu_unblocking(struct kvm_vcpu
*vcpu
)
2250 avic_set_running(vcpu
, true);
2253 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
2255 struct vcpu_svm
*svm
= to_svm(vcpu
);
2256 unsigned long rflags
= svm
->vmcb
->save
.rflags
;
2258 if (svm
->nmi_singlestep
) {
2259 /* Hide our flags if they were not set by the guest */
2260 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
))
2261 rflags
&= ~X86_EFLAGS_TF
;
2262 if (!(svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_RF
))
2263 rflags
&= ~X86_EFLAGS_RF
;
2268 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2270 if (to_svm(vcpu
)->nmi_singlestep
)
2271 rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2274 * Any change of EFLAGS.VM is accompanied by a reload of SS
2275 * (caused by either a task switch or an inter-privilege IRET),
2276 * so we do not need to update the CPL here.
2278 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
2281 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2284 case VCPU_EXREG_PDPTR
:
2285 BUG_ON(!npt_enabled
);
2286 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
2293 static void svm_set_vintr(struct vcpu_svm
*svm
)
2295 set_intercept(svm
, INTERCEPT_VINTR
);
2298 static void svm_clear_vintr(struct vcpu_svm
*svm
)
2300 clr_intercept(svm
, INTERCEPT_VINTR
);
2303 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
2305 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2308 case VCPU_SREG_CS
: return &save
->cs
;
2309 case VCPU_SREG_DS
: return &save
->ds
;
2310 case VCPU_SREG_ES
: return &save
->es
;
2311 case VCPU_SREG_FS
: return &save
->fs
;
2312 case VCPU_SREG_GS
: return &save
->gs
;
2313 case VCPU_SREG_SS
: return &save
->ss
;
2314 case VCPU_SREG_TR
: return &save
->tr
;
2315 case VCPU_SREG_LDTR
: return &save
->ldtr
;
2321 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2323 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2328 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
2329 struct kvm_segment
*var
, int seg
)
2331 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2333 var
->base
= s
->base
;
2334 var
->limit
= s
->limit
;
2335 var
->selector
= s
->selector
;
2336 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
2337 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
2338 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
2339 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
2340 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
2341 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
2342 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
2345 * AMD CPUs circa 2014 track the G bit for all segments except CS.
2346 * However, the SVM spec states that the G bit is not observed by the
2347 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
2348 * So let's synthesize a legal G bit for all segments, this helps
2349 * running KVM nested. It also helps cross-vendor migration, because
2350 * Intel's vmentry has a check on the 'G' bit.
2352 var
->g
= s
->limit
> 0xfffff;
2355 * AMD's VMCB does not have an explicit unusable field, so emulate it
2356 * for cross vendor migration purposes by "not present"
2358 var
->unusable
= !var
->present
;
2363 * Work around a bug where the busy flag in the tr selector
2373 * The accessed bit must always be set in the segment
2374 * descriptor cache, although it can be cleared in the
2375 * descriptor, the cached bit always remains at 1. Since
2376 * Intel has a check on this, set it here to support
2377 * cross-vendor migration.
2384 * On AMD CPUs sometimes the DB bit in the segment
2385 * descriptor is left as 1, although the whole segment has
2386 * been made unusable. Clear it here to pass an Intel VMX
2387 * entry check when cross vendor migrating.
2391 /* This is symmetric with svm_set_segment() */
2392 var
->dpl
= to_svm(vcpu
)->vmcb
->save
.cpl
;
2397 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
2399 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
2404 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2406 struct vcpu_svm
*svm
= to_svm(vcpu
);
2408 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
2409 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
2412 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2414 struct vcpu_svm
*svm
= to_svm(vcpu
);
2416 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
2417 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
2418 mark_dirty(svm
->vmcb
, VMCB_DT
);
2421 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2423 struct vcpu_svm
*svm
= to_svm(vcpu
);
2425 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
2426 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
2429 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2431 struct vcpu_svm
*svm
= to_svm(vcpu
);
2433 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
2434 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
2435 mark_dirty(svm
->vmcb
, VMCB_DT
);
2438 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2442 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
2446 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2450 static void update_cr0_intercept(struct vcpu_svm
*svm
)
2452 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
2453 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
2455 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
2456 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
2458 mark_dirty(svm
->vmcb
, VMCB_CR
);
2460 if (gcr0
== *hcr0
) {
2461 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2462 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2464 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
2465 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
2469 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2471 struct vcpu_svm
*svm
= to_svm(vcpu
);
2473 #ifdef CONFIG_X86_64
2474 if (vcpu
->arch
.efer
& EFER_LME
) {
2475 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
2476 vcpu
->arch
.efer
|= EFER_LMA
;
2477 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
2480 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
2481 vcpu
->arch
.efer
&= ~EFER_LMA
;
2482 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
2486 vcpu
->arch
.cr0
= cr0
;
2489 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
2492 * re-enable caching here because the QEMU bios
2493 * does not do it - this results in some delay at
2496 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
2497 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
2498 svm
->vmcb
->save
.cr0
= cr0
;
2499 mark_dirty(svm
->vmcb
, VMCB_CR
);
2500 update_cr0_intercept(svm
);
2503 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2505 unsigned long host_cr4_mce
= cr4_read_shadow() & X86_CR4_MCE
;
2506 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
2508 if (cr4
& X86_CR4_VMXE
)
2511 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
2512 svm_flush_tlb(vcpu
, true);
2514 vcpu
->arch
.cr4
= cr4
;
2517 cr4
|= host_cr4_mce
;
2518 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
2519 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
2523 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
2524 struct kvm_segment
*var
, int seg
)
2526 struct vcpu_svm
*svm
= to_svm(vcpu
);
2527 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
2529 s
->base
= var
->base
;
2530 s
->limit
= var
->limit
;
2531 s
->selector
= var
->selector
;
2532 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
2533 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
2534 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
2535 s
->attrib
|= ((var
->present
& 1) && !var
->unusable
) << SVM_SELECTOR_P_SHIFT
;
2536 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
2537 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
2538 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
2539 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
2542 * This is always accurate, except if SYSRET returned to a segment
2543 * with SS.DPL != 3. Intel does not have this quirk, and always
2544 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2545 * would entail passing the CPL to userspace and back.
2547 if (seg
== VCPU_SREG_SS
)
2548 /* This is symmetric with svm_get_segment() */
2549 svm
->vmcb
->save
.cpl
= (var
->dpl
& 3);
2551 mark_dirty(svm
->vmcb
, VMCB_SEG
);
2554 static void update_bp_intercept(struct kvm_vcpu
*vcpu
)
2556 struct vcpu_svm
*svm
= to_svm(vcpu
);
2558 clr_exception_intercept(svm
, BP_VECTOR
);
2560 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
2561 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2562 set_exception_intercept(svm
, BP_VECTOR
);
2564 vcpu
->guest_debug
= 0;
2567 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
2569 if (sd
->next_asid
> sd
->max_asid
) {
2570 ++sd
->asid_generation
;
2571 sd
->next_asid
= sd
->min_asid
;
2572 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
2575 svm
->asid_generation
= sd
->asid_generation
;
2576 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
2578 mark_dirty(svm
->vmcb
, VMCB_ASID
);
2581 static u64
svm_get_dr6(struct kvm_vcpu
*vcpu
)
2583 return to_svm(vcpu
)->vmcb
->save
.dr6
;
2586 static void svm_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long value
)
2588 struct vcpu_svm
*svm
= to_svm(vcpu
);
2590 svm
->vmcb
->save
.dr6
= value
;
2591 mark_dirty(svm
->vmcb
, VMCB_DR
);
2594 static void svm_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
2596 struct vcpu_svm
*svm
= to_svm(vcpu
);
2598 get_debugreg(vcpu
->arch
.db
[0], 0);
2599 get_debugreg(vcpu
->arch
.db
[1], 1);
2600 get_debugreg(vcpu
->arch
.db
[2], 2);
2601 get_debugreg(vcpu
->arch
.db
[3], 3);
2602 vcpu
->arch
.dr6
= svm_get_dr6(vcpu
);
2603 vcpu
->arch
.dr7
= svm
->vmcb
->save
.dr7
;
2605 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
2606 set_dr_intercepts(svm
);
2609 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
2611 struct vcpu_svm
*svm
= to_svm(vcpu
);
2613 svm
->vmcb
->save
.dr7
= value
;
2614 mark_dirty(svm
->vmcb
, VMCB_DR
);
2617 static int pf_interception(struct vcpu_svm
*svm
)
2619 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2620 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2622 return kvm_handle_page_fault(&svm
->vcpu
, error_code
, fault_address
,
2623 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2624 svm
->vmcb
->control
.insn_bytes
: NULL
,
2625 svm
->vmcb
->control
.insn_len
);
2628 static int npf_interception(struct vcpu_svm
*svm
)
2630 u64 fault_address
= __sme_clr(svm
->vmcb
->control
.exit_info_2
);
2631 u64 error_code
= svm
->vmcb
->control
.exit_info_1
;
2633 trace_kvm_page_fault(fault_address
, error_code
);
2634 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
2635 static_cpu_has(X86_FEATURE_DECODEASSISTS
) ?
2636 svm
->vmcb
->control
.insn_bytes
: NULL
,
2637 svm
->vmcb
->control
.insn_len
);
2640 static int db_interception(struct vcpu_svm
*svm
)
2642 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2644 if (!(svm
->vcpu
.guest_debug
&
2645 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
2646 !svm
->nmi_singlestep
) {
2647 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
2651 if (svm
->nmi_singlestep
) {
2652 disable_nmi_singlestep(svm
);
2655 if (svm
->vcpu
.guest_debug
&
2656 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
2657 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2658 kvm_run
->debug
.arch
.pc
=
2659 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2660 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2667 static int bp_interception(struct vcpu_svm
*svm
)
2669 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2671 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2672 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
2673 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
2677 static int ud_interception(struct vcpu_svm
*svm
)
2681 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
2682 if (er
== EMULATE_USER_EXIT
)
2684 if (er
!= EMULATE_DONE
)
2685 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2689 static int ac_interception(struct vcpu_svm
*svm
)
2691 kvm_queue_exception_e(&svm
->vcpu
, AC_VECTOR
, 0);
2695 static int gp_interception(struct vcpu_svm
*svm
)
2697 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2698 u32 error_code
= svm
->vmcb
->control
.exit_info_1
;
2701 WARN_ON_ONCE(!enable_vmware_backdoor
);
2703 er
= emulate_instruction(vcpu
,
2704 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
2705 if (er
== EMULATE_USER_EXIT
)
2707 else if (er
!= EMULATE_DONE
)
2708 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
2712 static bool is_erratum_383(void)
2717 if (!erratum_383_found
)
2720 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
2724 /* Bit 62 may or may not be set for this mce */
2725 value
&= ~(1ULL << 62);
2727 if (value
!= 0xb600000000010015ULL
)
2730 /* Clear MCi_STATUS registers */
2731 for (i
= 0; i
< 6; ++i
)
2732 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
2734 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
2738 value
&= ~(1ULL << 2);
2739 low
= lower_32_bits(value
);
2740 high
= upper_32_bits(value
);
2742 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
2745 /* Flush tlb to evict multi-match entries */
2751 static void svm_handle_mce(struct vcpu_svm
*svm
)
2753 if (is_erratum_383()) {
2755 * Erratum 383 triggered. Guest state is corrupt so kill the
2758 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2760 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
2766 * On an #MC intercept the MCE handler is not called automatically in
2767 * the host. So do it by hand here.
2771 /* not sure if we ever come back to this point */
2776 static int mc_interception(struct vcpu_svm
*svm
)
2781 static int shutdown_interception(struct vcpu_svm
*svm
)
2783 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2786 * VMCB is undefined after a SHUTDOWN intercept
2787 * so reinitialize it.
2789 clear_page(svm
->vmcb
);
2792 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2796 static int io_interception(struct vcpu_svm
*svm
)
2798 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2799 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
2800 int size
, in
, string
;
2803 ++svm
->vcpu
.stat
.io_exits
;
2804 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
2805 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
2807 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
2809 port
= io_info
>> 16;
2810 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
2811 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
2813 return kvm_fast_pio(&svm
->vcpu
, size
, port
, in
);
2816 static int nmi_interception(struct vcpu_svm
*svm
)
2821 static int intr_interception(struct vcpu_svm
*svm
)
2823 ++svm
->vcpu
.stat
.irq_exits
;
2827 static int nop_on_interception(struct vcpu_svm
*svm
)
2832 static int halt_interception(struct vcpu_svm
*svm
)
2834 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
2835 return kvm_emulate_halt(&svm
->vcpu
);
2838 static int vmmcall_interception(struct vcpu_svm
*svm
)
2840 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2841 return kvm_emulate_hypercall(&svm
->vcpu
);
2844 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
2846 struct vcpu_svm
*svm
= to_svm(vcpu
);
2848 return svm
->nested
.nested_cr3
;
2851 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
2853 struct vcpu_svm
*svm
= to_svm(vcpu
);
2854 u64 cr3
= svm
->nested
.nested_cr3
;
2858 ret
= kvm_vcpu_read_guest_page(vcpu
, gpa_to_gfn(__sme_clr(cr3
)), &pdpte
,
2859 offset_in_page(cr3
) + index
* 8, 8);
2865 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
2868 struct vcpu_svm
*svm
= to_svm(vcpu
);
2870 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
2871 mark_dirty(svm
->vmcb
, VMCB_NPT
);
2872 svm_flush_tlb(vcpu
, true);
2875 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
2876 struct x86_exception
*fault
)
2878 struct vcpu_svm
*svm
= to_svm(vcpu
);
2880 if (svm
->vmcb
->control
.exit_code
!= SVM_EXIT_NPF
) {
2882 * TODO: track the cause of the nested page fault, and
2883 * correctly fill in the high bits of exit_info_1.
2885 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
2886 svm
->vmcb
->control
.exit_code_hi
= 0;
2887 svm
->vmcb
->control
.exit_info_1
= (1ULL << 32);
2888 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
2891 svm
->vmcb
->control
.exit_info_1
&= ~0xffffffffULL
;
2892 svm
->vmcb
->control
.exit_info_1
|= fault
->error_code
;
2895 * The present bit is always zero for page structure faults on real
2898 if (svm
->vmcb
->control
.exit_info_1
& (2ULL << 32))
2899 svm
->vmcb
->control
.exit_info_1
&= ~1;
2901 nested_svm_vmexit(svm
);
2904 static void nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
2906 WARN_ON(mmu_is_nested(vcpu
));
2907 kvm_init_shadow_mmu(vcpu
);
2908 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
2909 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
2910 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
2911 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
2912 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level(vcpu
);
2913 reset_shadow_zero_bits_mask(vcpu
, &vcpu
->arch
.mmu
);
2914 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
2917 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
2919 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
2922 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
2924 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
) ||
2925 !is_paging(&svm
->vcpu
)) {
2926 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2930 if (svm
->vmcb
->save
.cpl
) {
2931 kvm_inject_gp(&svm
->vcpu
, 0);
2938 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
2939 bool has_error_code
, u32 error_code
)
2943 if (!is_guest_mode(&svm
->vcpu
))
2946 vmexit
= nested_svm_intercept(svm
);
2947 if (vmexit
!= NESTED_EXIT_DONE
)
2950 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
2951 svm
->vmcb
->control
.exit_code_hi
= 0;
2952 svm
->vmcb
->control
.exit_info_1
= error_code
;
2955 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2956 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2957 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2958 * written only when inject_pending_event runs (DR6 would written here
2959 * too). This should be conditional on a new capability---if the
2960 * capability is disabled, kvm_multiple_exception would write the
2961 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2963 if (svm
->vcpu
.arch
.exception
.nested_apf
)
2964 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.apf
.nested_apf_token
;
2966 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
2968 svm
->nested
.exit_required
= true;
2972 /* This function returns true if it is save to enable the irq window */
2973 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2975 if (!is_guest_mode(&svm
->vcpu
))
2978 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2981 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2985 * if vmexit was already requested (by intercepted exception
2986 * for instance) do not overwrite it with "external interrupt"
2989 if (svm
->nested
.exit_required
)
2992 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2993 svm
->vmcb
->control
.exit_info_1
= 0;
2994 svm
->vmcb
->control
.exit_info_2
= 0;
2996 if (svm
->nested
.intercept
& 1ULL) {
2998 * The #vmexit can't be emulated here directly because this
2999 * code path runs with irqs and preemption disabled. A
3000 * #vmexit emulation might sleep. Only signal request for
3003 svm
->nested
.exit_required
= true;
3004 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
3011 /* This function returns true if it is save to enable the nmi window */
3012 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
3014 if (!is_guest_mode(&svm
->vcpu
))
3017 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
3020 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
3021 svm
->nested
.exit_required
= true;
3026 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
3032 page
= kvm_vcpu_gfn_to_page(&svm
->vcpu
, gpa
>> PAGE_SHIFT
);
3033 if (is_error_page(page
))
3041 kvm_inject_gp(&svm
->vcpu
, 0);
3046 static void nested_svm_unmap(struct page
*page
)
3049 kvm_release_page_dirty(page
);
3052 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
3054 unsigned port
, size
, iopm_len
;
3059 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
3060 return NESTED_EXIT_HOST
;
3062 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
3063 size
= (svm
->vmcb
->control
.exit_info_1
& SVM_IOIO_SIZE_MASK
) >>
3064 SVM_IOIO_SIZE_SHIFT
;
3065 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
3066 start_bit
= port
% 8;
3067 iopm_len
= (start_bit
+ size
> 8) ? 2 : 1;
3068 mask
= (0xf >> (4 - size
)) << start_bit
;
3071 if (kvm_vcpu_read_guest(&svm
->vcpu
, gpa
, &val
, iopm_len
))
3072 return NESTED_EXIT_DONE
;
3074 return (val
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3077 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
3079 u32 offset
, msr
, value
;
3082 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3083 return NESTED_EXIT_HOST
;
3085 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3086 offset
= svm_msrpm_offset(msr
);
3087 write
= svm
->vmcb
->control
.exit_info_1
& 1;
3088 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
3090 if (offset
== MSR_INVALID
)
3091 return NESTED_EXIT_DONE
;
3093 /* Offset is in 32 bit units but need in 8 bit units */
3096 if (kvm_vcpu_read_guest(&svm
->vcpu
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
3097 return NESTED_EXIT_DONE
;
3099 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
3102 /* DB exceptions for our internal use must not cause vmexit */
3103 static int nested_svm_intercept_db(struct vcpu_svm
*svm
)
3107 /* if we're not singlestepping, it's not ours */
3108 if (!svm
->nmi_singlestep
)
3109 return NESTED_EXIT_DONE
;
3111 /* if it's not a singlestep exception, it's not ours */
3112 if (kvm_get_dr(&svm
->vcpu
, 6, &dr6
))
3113 return NESTED_EXIT_DONE
;
3114 if (!(dr6
& DR6_BS
))
3115 return NESTED_EXIT_DONE
;
3117 /* if the guest is singlestepping, it should get the vmexit */
3118 if (svm
->nmi_singlestep_guest_rflags
& X86_EFLAGS_TF
) {
3119 disable_nmi_singlestep(svm
);
3120 return NESTED_EXIT_DONE
;
3123 /* it's ours, the nested hypervisor must not see this one */
3124 return NESTED_EXIT_HOST
;
3127 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
3129 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3131 switch (exit_code
) {
3134 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
3135 return NESTED_EXIT_HOST
;
3137 /* For now we are always handling NPFs when using them */
3139 return NESTED_EXIT_HOST
;
3141 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
3142 /* When we're shadowing, trap PFs, but not async PF */
3143 if (!npt_enabled
&& svm
->vcpu
.arch
.apf
.host_apf_reason
== 0)
3144 return NESTED_EXIT_HOST
;
3150 return NESTED_EXIT_CONTINUE
;
3154 * If this function returns true, this #vmexit was already handled
3156 static int nested_svm_intercept(struct vcpu_svm
*svm
)
3158 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3159 int vmexit
= NESTED_EXIT_HOST
;
3161 switch (exit_code
) {
3163 vmexit
= nested_svm_exit_handled_msr(svm
);
3166 vmexit
= nested_svm_intercept_ioio(svm
);
3168 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
3169 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
3170 if (svm
->nested
.intercept_cr
& bit
)
3171 vmexit
= NESTED_EXIT_DONE
;
3174 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
3175 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
3176 if (svm
->nested
.intercept_dr
& bit
)
3177 vmexit
= NESTED_EXIT_DONE
;
3180 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
3181 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
3182 if (svm
->nested
.intercept_exceptions
& excp_bits
) {
3183 if (exit_code
== SVM_EXIT_EXCP_BASE
+ DB_VECTOR
)
3184 vmexit
= nested_svm_intercept_db(svm
);
3186 vmexit
= NESTED_EXIT_DONE
;
3188 /* async page fault always cause vmexit */
3189 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
3190 svm
->vcpu
.arch
.exception
.nested_apf
!= 0)
3191 vmexit
= NESTED_EXIT_DONE
;
3194 case SVM_EXIT_ERR
: {
3195 vmexit
= NESTED_EXIT_DONE
;
3199 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
3200 if (svm
->nested
.intercept
& exit_bits
)
3201 vmexit
= NESTED_EXIT_DONE
;
3208 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
3212 vmexit
= nested_svm_intercept(svm
);
3214 if (vmexit
== NESTED_EXIT_DONE
)
3215 nested_svm_vmexit(svm
);
3220 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
3222 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
3223 struct vmcb_control_area
*from
= &from_vmcb
->control
;
3225 dst
->intercept_cr
= from
->intercept_cr
;
3226 dst
->intercept_dr
= from
->intercept_dr
;
3227 dst
->intercept_exceptions
= from
->intercept_exceptions
;
3228 dst
->intercept
= from
->intercept
;
3229 dst
->iopm_base_pa
= from
->iopm_base_pa
;
3230 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
3231 dst
->tsc_offset
= from
->tsc_offset
;
3232 dst
->asid
= from
->asid
;
3233 dst
->tlb_ctl
= from
->tlb_ctl
;
3234 dst
->int_ctl
= from
->int_ctl
;
3235 dst
->int_vector
= from
->int_vector
;
3236 dst
->int_state
= from
->int_state
;
3237 dst
->exit_code
= from
->exit_code
;
3238 dst
->exit_code_hi
= from
->exit_code_hi
;
3239 dst
->exit_info_1
= from
->exit_info_1
;
3240 dst
->exit_info_2
= from
->exit_info_2
;
3241 dst
->exit_int_info
= from
->exit_int_info
;
3242 dst
->exit_int_info_err
= from
->exit_int_info_err
;
3243 dst
->nested_ctl
= from
->nested_ctl
;
3244 dst
->event_inj
= from
->event_inj
;
3245 dst
->event_inj_err
= from
->event_inj_err
;
3246 dst
->nested_cr3
= from
->nested_cr3
;
3247 dst
->virt_ext
= from
->virt_ext
;
3250 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
3252 struct vmcb
*nested_vmcb
;
3253 struct vmcb
*hsave
= svm
->nested
.hsave
;
3254 struct vmcb
*vmcb
= svm
->vmcb
;
3257 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
3258 vmcb
->control
.exit_info_1
,
3259 vmcb
->control
.exit_info_2
,
3260 vmcb
->control
.exit_int_info
,
3261 vmcb
->control
.exit_int_info_err
,
3264 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
3268 /* Exit Guest-Mode */
3269 leave_guest_mode(&svm
->vcpu
);
3270 svm
->nested
.vmcb
= 0;
3272 /* Give the current vmcb to the guest */
3275 nested_vmcb
->save
.es
= vmcb
->save
.es
;
3276 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
3277 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
3278 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
3279 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
3280 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
3281 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
3282 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3283 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3284 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
3285 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3286 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3287 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
3288 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
3289 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
3290 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
3291 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
3292 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
3294 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
3295 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
3296 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
3297 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
3298 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
3299 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
3300 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
3301 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
3302 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
3304 if (svm
->nrips_enabled
)
3305 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
3308 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
3309 * to make sure that we do not lose injected events. So check event_inj
3310 * here and copy it to exit_int_info if it is valid.
3311 * Exit_int_info and event_inj can't be both valid because the case
3312 * below only happens on a VMRUN instruction intercept which has
3313 * no valid exit_int_info set.
3315 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
3316 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
3318 nc
->exit_int_info
= vmcb
->control
.event_inj
;
3319 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
3322 nested_vmcb
->control
.tlb_ctl
= 0;
3323 nested_vmcb
->control
.event_inj
= 0;
3324 nested_vmcb
->control
.event_inj_err
= 0;
3326 /* We always set V_INTR_MASKING and remember the old value in hflags */
3327 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
3328 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
3330 /* Restore the original control entries */
3331 copy_vmcb_control_area(vmcb
, hsave
);
3333 kvm_clear_exception_queue(&svm
->vcpu
);
3334 kvm_clear_interrupt_queue(&svm
->vcpu
);
3336 svm
->nested
.nested_cr3
= 0;
3338 /* Restore selected save entries */
3339 svm
->vmcb
->save
.es
= hsave
->save
.es
;
3340 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
3341 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
3342 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
3343 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
3344 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
3345 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
3346 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
3347 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
3348 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
3350 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
3351 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
3353 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
3355 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
3356 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
3357 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
3358 svm
->vmcb
->save
.dr7
= 0;
3359 svm
->vmcb
->save
.cpl
= 0;
3360 svm
->vmcb
->control
.exit_int_info
= 0;
3362 mark_all_dirty(svm
->vmcb
);
3364 nested_svm_unmap(page
);
3366 nested_svm_uninit_mmu_context(&svm
->vcpu
);
3367 kvm_mmu_reset_context(&svm
->vcpu
);
3368 kvm_mmu_load(&svm
->vcpu
);
3373 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
3376 * This function merges the msr permission bitmaps of kvm and the
3377 * nested vmcb. It is optimized in that it only merges the parts where
3378 * the kvm msr permission bitmap may contain zero bits
3382 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
3385 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
3389 if (msrpm_offsets
[i
] == 0xffffffff)
3392 p
= msrpm_offsets
[i
];
3393 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
3395 if (kvm_vcpu_read_guest(&svm
->vcpu
, offset
, &value
, 4))
3398 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
3401 svm
->vmcb
->control
.msrpm_base_pa
= __sme_set(__pa(svm
->nested
.msrpm
));
3406 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
3408 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
3411 if (vmcb
->control
.asid
== 0)
3414 if ((vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) &&
3421 static void enter_svm_guest_mode(struct vcpu_svm
*svm
, u64 vmcb_gpa
,
3422 struct vmcb
*nested_vmcb
, struct page
*page
)
3424 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
3425 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
3427 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
3429 if (nested_vmcb
->control
.nested_ctl
& SVM_NESTED_CTL_NP_ENABLE
) {
3430 kvm_mmu_unload(&svm
->vcpu
);
3431 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
3432 nested_svm_init_mmu_context(&svm
->vcpu
);
3435 /* Load the nested guest state */
3436 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
3437 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
3438 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
3439 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
3440 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
3441 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
3442 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
3443 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
3444 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
3445 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
3447 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
3448 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
3450 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
3452 /* Guest paging mode is active - reset mmu */
3453 kvm_mmu_reset_context(&svm
->vcpu
);
3455 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
3456 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
3457 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
3458 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
3460 /* In case we don't even reach vcpu_run, the fields are not updated */
3461 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
3462 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
3463 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
3464 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
3465 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
3466 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
3468 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
3469 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
3471 /* cache intercepts */
3472 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
3473 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
3474 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
3475 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
3477 svm_flush_tlb(&svm
->vcpu
, true);
3478 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
3479 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
3480 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
3482 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
3484 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
3485 /* We only want the cr8 intercept bits of the guest */
3486 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
3487 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3490 /* We don't want to see VMMCALLs from a nested guest */
3491 clr_intercept(svm
, INTERCEPT_VMMCALL
);
3493 svm
->vmcb
->control
.virt_ext
= nested_vmcb
->control
.virt_ext
;
3494 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
3495 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
3496 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
3497 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
3498 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
3500 nested_svm_unmap(page
);
3502 /* Enter Guest-Mode */
3503 enter_guest_mode(&svm
->vcpu
);
3506 * Merge guest and host intercepts - must be called with vcpu in
3507 * guest-mode to take affect here
3509 recalc_intercepts(svm
);
3511 svm
->nested
.vmcb
= vmcb_gpa
;
3515 mark_all_dirty(svm
->vmcb
);
3518 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
3520 struct vmcb
*nested_vmcb
;
3521 struct vmcb
*hsave
= svm
->nested
.hsave
;
3522 struct vmcb
*vmcb
= svm
->vmcb
;
3526 vmcb_gpa
= svm
->vmcb
->save
.rax
;
3528 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3532 if (!nested_vmcb_checks(nested_vmcb
)) {
3533 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3534 nested_vmcb
->control
.exit_code_hi
= 0;
3535 nested_vmcb
->control
.exit_info_1
= 0;
3536 nested_vmcb
->control
.exit_info_2
= 0;
3538 nested_svm_unmap(page
);
3543 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
3544 nested_vmcb
->save
.rip
,
3545 nested_vmcb
->control
.int_ctl
,
3546 nested_vmcb
->control
.event_inj
,
3547 nested_vmcb
->control
.nested_ctl
);
3549 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
3550 nested_vmcb
->control
.intercept_cr
>> 16,
3551 nested_vmcb
->control
.intercept_exceptions
,
3552 nested_vmcb
->control
.intercept
);
3554 /* Clear internal status */
3555 kvm_clear_exception_queue(&svm
->vcpu
);
3556 kvm_clear_interrupt_queue(&svm
->vcpu
);
3559 * Save the old vmcb, so we don't need to pick what we save, but can
3560 * restore everything when a VMEXIT occurs
3562 hsave
->save
.es
= vmcb
->save
.es
;
3563 hsave
->save
.cs
= vmcb
->save
.cs
;
3564 hsave
->save
.ss
= vmcb
->save
.ss
;
3565 hsave
->save
.ds
= vmcb
->save
.ds
;
3566 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
3567 hsave
->save
.idtr
= vmcb
->save
.idtr
;
3568 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
3569 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
3570 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
3571 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
3572 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
3573 hsave
->save
.rsp
= vmcb
->save
.rsp
;
3574 hsave
->save
.rax
= vmcb
->save
.rax
;
3576 hsave
->save
.cr3
= vmcb
->save
.cr3
;
3578 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
3580 copy_vmcb_control_area(hsave
, vmcb
);
3582 enter_svm_guest_mode(svm
, vmcb_gpa
, nested_vmcb
, page
);
3587 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
3589 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
3590 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
3591 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
3592 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
3593 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
3594 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
3595 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
3596 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
3597 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
3598 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
3599 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
3600 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
3603 static int vmload_interception(struct vcpu_svm
*svm
)
3605 struct vmcb
*nested_vmcb
;
3609 if (nested_svm_check_permissions(svm
))
3612 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3616 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3617 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3619 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
3620 nested_svm_unmap(page
);
3625 static int vmsave_interception(struct vcpu_svm
*svm
)
3627 struct vmcb
*nested_vmcb
;
3631 if (nested_svm_check_permissions(svm
))
3634 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
3638 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3639 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3641 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
3642 nested_svm_unmap(page
);
3647 static int vmrun_interception(struct vcpu_svm
*svm
)
3649 if (nested_svm_check_permissions(svm
))
3652 /* Save rip after vmrun instruction */
3653 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
3655 if (!nested_svm_vmrun(svm
))
3658 if (!nested_svm_vmrun_msrpm(svm
))
3665 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
3666 svm
->vmcb
->control
.exit_code_hi
= 0;
3667 svm
->vmcb
->control
.exit_info_1
= 0;
3668 svm
->vmcb
->control
.exit_info_2
= 0;
3670 nested_svm_vmexit(svm
);
3675 static int stgi_interception(struct vcpu_svm
*svm
)
3679 if (nested_svm_check_permissions(svm
))
3683 * If VGIF is enabled, the STGI intercept is only added to
3684 * detect the opening of the SMI/NMI window; remove it now.
3686 if (vgif_enabled(svm
))
3687 clr_intercept(svm
, INTERCEPT_STGI
);
3689 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3690 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3691 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3698 static int clgi_interception(struct vcpu_svm
*svm
)
3702 if (nested_svm_check_permissions(svm
))
3705 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3706 ret
= kvm_skip_emulated_instruction(&svm
->vcpu
);
3710 /* After a CLGI no interrupts should come */
3711 if (!kvm_vcpu_apicv_active(&svm
->vcpu
)) {
3712 svm_clear_vintr(svm
);
3713 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3714 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3720 static int invlpga_interception(struct vcpu_svm
*svm
)
3722 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
3724 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
),
3725 kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3727 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3728 kvm_mmu_invlpg(vcpu
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3730 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3731 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3734 static int skinit_interception(struct vcpu_svm
*svm
)
3736 trace_kvm_skinit(svm
->vmcb
->save
.rip
, kvm_register_read(&svm
->vcpu
, VCPU_REGS_RAX
));
3738 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3742 static int wbinvd_interception(struct vcpu_svm
*svm
)
3744 return kvm_emulate_wbinvd(&svm
->vcpu
);
3747 static int xsetbv_interception(struct vcpu_svm
*svm
)
3749 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
3750 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
3752 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
3753 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
3754 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3760 static int task_switch_interception(struct vcpu_svm
*svm
)
3764 int int_type
= svm
->vmcb
->control
.exit_int_info
&
3765 SVM_EXITINTINFO_TYPE_MASK
;
3766 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
3768 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
3770 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
3771 bool has_error_code
= false;
3774 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
3776 if (svm
->vmcb
->control
.exit_info_2
&
3777 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
3778 reason
= TASK_SWITCH_IRET
;
3779 else if (svm
->vmcb
->control
.exit_info_2
&
3780 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
3781 reason
= TASK_SWITCH_JMP
;
3783 reason
= TASK_SWITCH_GATE
;
3785 reason
= TASK_SWITCH_CALL
;
3787 if (reason
== TASK_SWITCH_GATE
) {
3789 case SVM_EXITINTINFO_TYPE_NMI
:
3790 svm
->vcpu
.arch
.nmi_injected
= false;
3792 case SVM_EXITINTINFO_TYPE_EXEPT
:
3793 if (svm
->vmcb
->control
.exit_info_2
&
3794 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
3795 has_error_code
= true;
3797 (u32
)svm
->vmcb
->control
.exit_info_2
;
3799 kvm_clear_exception_queue(&svm
->vcpu
);
3801 case SVM_EXITINTINFO_TYPE_INTR
:
3802 kvm_clear_interrupt_queue(&svm
->vcpu
);
3809 if (reason
!= TASK_SWITCH_GATE
||
3810 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
3811 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
3812 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
3813 skip_emulated_instruction(&svm
->vcpu
);
3815 if (int_type
!= SVM_EXITINTINFO_TYPE_SOFT
)
3818 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, int_vec
, reason
,
3819 has_error_code
, error_code
) == EMULATE_FAIL
) {
3820 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3821 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3822 svm
->vcpu
.run
->internal
.ndata
= 0;
3828 static int cpuid_interception(struct vcpu_svm
*svm
)
3830 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3831 return kvm_emulate_cpuid(&svm
->vcpu
);
3834 static int iret_interception(struct vcpu_svm
*svm
)
3836 ++svm
->vcpu
.stat
.nmi_window_exits
;
3837 clr_intercept(svm
, INTERCEPT_IRET
);
3838 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
3839 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
3840 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3844 static int invlpg_interception(struct vcpu_svm
*svm
)
3846 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3847 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3849 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
3850 return kvm_skip_emulated_instruction(&svm
->vcpu
);
3853 static int emulate_on_interception(struct vcpu_svm
*svm
)
3855 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
3858 static int rsm_interception(struct vcpu_svm
*svm
)
3860 return x86_emulate_instruction(&svm
->vcpu
, 0, 0,
3861 rsm_ins_bytes
, 2) == EMULATE_DONE
;
3864 static int rdpmc_interception(struct vcpu_svm
*svm
)
3868 if (!static_cpu_has(X86_FEATURE_NRIPS
))
3869 return emulate_on_interception(svm
);
3871 err
= kvm_rdpmc(&svm
->vcpu
);
3872 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3875 static bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
,
3878 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
3882 intercept
= svm
->nested
.intercept
;
3884 if (!is_guest_mode(&svm
->vcpu
) ||
3885 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
3888 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
3889 val
&= ~SVM_CR0_SELECTIVE_MASK
;
3892 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
3893 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
3899 #define CR_VALID (1ULL << 63)
3901 static int cr_interception(struct vcpu_svm
*svm
)
3907 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
3908 return emulate_on_interception(svm
);
3910 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
3911 return emulate_on_interception(svm
);
3913 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3914 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_CR0_SEL_WRITE
)
3915 cr
= SVM_EXIT_WRITE_CR0
- SVM_EXIT_READ_CR0
;
3917 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
3920 if (cr
>= 16) { /* mov to cr */
3922 val
= kvm_register_read(&svm
->vcpu
, reg
);
3925 if (!check_selective_cr0_intercepted(svm
, val
))
3926 err
= kvm_set_cr0(&svm
->vcpu
, val
);
3932 err
= kvm_set_cr3(&svm
->vcpu
, val
);
3935 err
= kvm_set_cr4(&svm
->vcpu
, val
);
3938 err
= kvm_set_cr8(&svm
->vcpu
, val
);
3941 WARN(1, "unhandled write to CR%d", cr
);
3942 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3945 } else { /* mov from cr */
3948 val
= kvm_read_cr0(&svm
->vcpu
);
3951 val
= svm
->vcpu
.arch
.cr2
;
3954 val
= kvm_read_cr3(&svm
->vcpu
);
3957 val
= kvm_read_cr4(&svm
->vcpu
);
3960 val
= kvm_get_cr8(&svm
->vcpu
);
3963 WARN(1, "unhandled read from CR%d", cr
);
3964 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
3967 kvm_register_write(&svm
->vcpu
, reg
, val
);
3969 return kvm_complete_insn_gp(&svm
->vcpu
, err
);
3972 static int dr_interception(struct vcpu_svm
*svm
)
3977 if (svm
->vcpu
.guest_debug
== 0) {
3979 * No more DR vmexits; force a reload of the debug registers
3980 * and reenter on this instruction. The next vmexit will
3981 * retrieve the full state of the debug registers.
3983 clr_dr_intercepts(svm
);
3984 svm
->vcpu
.arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
3988 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
3989 return emulate_on_interception(svm
);
3991 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
3992 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
3994 if (dr
>= 16) { /* mov to DRn */
3995 if (!kvm_require_dr(&svm
->vcpu
, dr
- 16))
3997 val
= kvm_register_read(&svm
->vcpu
, reg
);
3998 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
4000 if (!kvm_require_dr(&svm
->vcpu
, dr
))
4002 kvm_get_dr(&svm
->vcpu
, dr
, &val
);
4003 kvm_register_write(&svm
->vcpu
, reg
, val
);
4006 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4009 static int cr8_write_interception(struct vcpu_svm
*svm
)
4011 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
4014 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
4015 /* instruction emulation calls kvm_set_cr8() */
4016 r
= cr_interception(svm
);
4017 if (lapic_in_kernel(&svm
->vcpu
))
4019 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
4021 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
4025 static int svm_get_msr_feature(struct kvm_msr_entry
*msr
)
4029 switch (msr
->index
) {
4030 case MSR_F10H_DECFG
:
4031 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC
))
4032 msr
->data
|= MSR_F10H_DECFG_LFENCE_SERIALIZE
;
4041 static int svm_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4043 struct vcpu_svm
*svm
= to_svm(vcpu
);
4045 switch (msr_info
->index
) {
4046 case MSR_IA32_TSC
: {
4047 msr_info
->data
= svm
->vmcb
->control
.tsc_offset
+
4048 kvm_scale_tsc(vcpu
, rdtsc());
4053 msr_info
->data
= svm
->vmcb
->save
.star
;
4055 #ifdef CONFIG_X86_64
4057 msr_info
->data
= svm
->vmcb
->save
.lstar
;
4060 msr_info
->data
= svm
->vmcb
->save
.cstar
;
4062 case MSR_KERNEL_GS_BASE
:
4063 msr_info
->data
= svm
->vmcb
->save
.kernel_gs_base
;
4065 case MSR_SYSCALL_MASK
:
4066 msr_info
->data
= svm
->vmcb
->save
.sfmask
;
4069 case MSR_IA32_SYSENTER_CS
:
4070 msr_info
->data
= svm
->vmcb
->save
.sysenter_cs
;
4072 case MSR_IA32_SYSENTER_EIP
:
4073 msr_info
->data
= svm
->sysenter_eip
;
4075 case MSR_IA32_SYSENTER_ESP
:
4076 msr_info
->data
= svm
->sysenter_esp
;
4079 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4081 msr_info
->data
= svm
->tsc_aux
;
4084 * Nobody will change the following 5 values in the VMCB so we can
4085 * safely return them on rdmsr. They will always be 0 until LBRV is
4088 case MSR_IA32_DEBUGCTLMSR
:
4089 msr_info
->data
= svm
->vmcb
->save
.dbgctl
;
4091 case MSR_IA32_LASTBRANCHFROMIP
:
4092 msr_info
->data
= svm
->vmcb
->save
.br_from
;
4094 case MSR_IA32_LASTBRANCHTOIP
:
4095 msr_info
->data
= svm
->vmcb
->save
.br_to
;
4097 case MSR_IA32_LASTINTFROMIP
:
4098 msr_info
->data
= svm
->vmcb
->save
.last_excp_from
;
4100 case MSR_IA32_LASTINTTOIP
:
4101 msr_info
->data
= svm
->vmcb
->save
.last_excp_to
;
4103 case MSR_VM_HSAVE_PA
:
4104 msr_info
->data
= svm
->nested
.hsave_msr
;
4107 msr_info
->data
= svm
->nested
.vm_cr_msr
;
4109 case MSR_IA32_SPEC_CTRL
:
4110 if (!msr_info
->host_initiated
&&
4111 !guest_cpuid_has(vcpu
, X86_FEATURE_IBRS
))
4114 msr_info
->data
= svm
->spec_ctrl
;
4116 case MSR_F15H_IC_CFG
: {
4120 family
= guest_cpuid_family(vcpu
);
4121 model
= guest_cpuid_model(vcpu
);
4123 if (family
< 0 || model
< 0)
4124 return kvm_get_msr_common(vcpu
, msr_info
);
4128 if (family
== 0x15 &&
4129 (model
>= 0x2 && model
< 0x20))
4130 msr_info
->data
= 0x1E;
4133 case MSR_F10H_DECFG
:
4134 msr_info
->data
= svm
->msr_decfg
;
4137 return kvm_get_msr_common(vcpu
, msr_info
);
4142 static int rdmsr_interception(struct vcpu_svm
*svm
)
4144 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4145 struct msr_data msr_info
;
4147 msr_info
.index
= ecx
;
4148 msr_info
.host_initiated
= false;
4149 if (svm_get_msr(&svm
->vcpu
, &msr_info
)) {
4150 trace_kvm_msr_read_ex(ecx
);
4151 kvm_inject_gp(&svm
->vcpu
, 0);
4154 trace_kvm_msr_read(ecx
, msr_info
.data
);
4156 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
,
4157 msr_info
.data
& 0xffffffff);
4158 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RDX
,
4159 msr_info
.data
>> 32);
4160 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4161 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4165 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
4167 struct vcpu_svm
*svm
= to_svm(vcpu
);
4168 int svm_dis
, chg_mask
;
4170 if (data
& ~SVM_VM_CR_VALID_MASK
)
4173 chg_mask
= SVM_VM_CR_VALID_MASK
;
4175 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
4176 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
4178 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
4179 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
4181 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
4183 /* check for svm_disable while efer.svme is set */
4184 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
4190 static int svm_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr
)
4192 struct vcpu_svm
*svm
= to_svm(vcpu
);
4194 u32 ecx
= msr
->index
;
4195 u64 data
= msr
->data
;
4197 case MSR_IA32_CR_PAT
:
4198 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
4200 vcpu
->arch
.pat
= data
;
4201 svm
->vmcb
->save
.g_pat
= data
;
4202 mark_dirty(svm
->vmcb
, VMCB_NPT
);
4205 kvm_write_tsc(vcpu
, msr
);
4207 case MSR_IA32_SPEC_CTRL
:
4208 if (!msr
->host_initiated
&&
4209 !guest_cpuid_has(vcpu
, X86_FEATURE_IBRS
))
4212 /* The STIBP bit doesn't fault even if it's not advertised */
4213 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
))
4216 svm
->spec_ctrl
= data
;
4223 * When it's written (to non-zero) for the first time, pass
4227 * The handling of the MSR bitmap for L2 guests is done in
4228 * nested_svm_vmrun_msrpm.
4229 * We update the L1 MSR bit as well since it will end up
4230 * touching the MSR anyway now.
4232 set_msr_interception(svm
->msrpm
, MSR_IA32_SPEC_CTRL
, 1, 1);
4234 case MSR_IA32_PRED_CMD
:
4235 if (!msr
->host_initiated
&&
4236 !guest_cpuid_has(vcpu
, X86_FEATURE_IBPB
))
4239 if (data
& ~PRED_CMD_IBPB
)
4245 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
4246 if (is_guest_mode(vcpu
))
4248 set_msr_interception(svm
->msrpm
, MSR_IA32_PRED_CMD
, 0, 1);
4251 svm
->vmcb
->save
.star
= data
;
4253 #ifdef CONFIG_X86_64
4255 svm
->vmcb
->save
.lstar
= data
;
4258 svm
->vmcb
->save
.cstar
= data
;
4260 case MSR_KERNEL_GS_BASE
:
4261 svm
->vmcb
->save
.kernel_gs_base
= data
;
4263 case MSR_SYSCALL_MASK
:
4264 svm
->vmcb
->save
.sfmask
= data
;
4267 case MSR_IA32_SYSENTER_CS
:
4268 svm
->vmcb
->save
.sysenter_cs
= data
;
4270 case MSR_IA32_SYSENTER_EIP
:
4271 svm
->sysenter_eip
= data
;
4272 svm
->vmcb
->save
.sysenter_eip
= data
;
4274 case MSR_IA32_SYSENTER_ESP
:
4275 svm
->sysenter_esp
= data
;
4276 svm
->vmcb
->save
.sysenter_esp
= data
;
4279 if (!boot_cpu_has(X86_FEATURE_RDTSCP
))
4283 * This is rare, so we update the MSR here instead of using
4284 * direct_access_msrs. Doing that would require a rdmsr in
4287 svm
->tsc_aux
= data
;
4288 wrmsrl(MSR_TSC_AUX
, svm
->tsc_aux
);
4290 case MSR_IA32_DEBUGCTLMSR
:
4291 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
4292 vcpu_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
4296 if (data
& DEBUGCTL_RESERVED_BITS
)
4299 svm
->vmcb
->save
.dbgctl
= data
;
4300 mark_dirty(svm
->vmcb
, VMCB_LBR
);
4301 if (data
& (1ULL<<0))
4302 svm_enable_lbrv(svm
);
4304 svm_disable_lbrv(svm
);
4306 case MSR_VM_HSAVE_PA
:
4307 svm
->nested
.hsave_msr
= data
;
4310 return svm_set_vm_cr(vcpu
, data
);
4312 vcpu_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
4314 case MSR_F10H_DECFG
: {
4315 struct kvm_msr_entry msr_entry
;
4317 msr_entry
.index
= msr
->index
;
4318 if (svm_get_msr_feature(&msr_entry
))
4321 /* Check the supported bits */
4322 if (data
& ~msr_entry
.data
)
4325 /* Don't allow the guest to change a bit, #GP */
4326 if (!msr
->host_initiated
&& (data
^ msr_entry
.data
))
4329 svm
->msr_decfg
= data
;
4332 case MSR_IA32_APICBASE
:
4333 if (kvm_vcpu_apicv_active(vcpu
))
4334 avic_update_vapic_bar(to_svm(vcpu
), data
);
4335 /* Follow through */
4337 return kvm_set_msr_common(vcpu
, msr
);
4342 static int wrmsr_interception(struct vcpu_svm
*svm
)
4344 struct msr_data msr
;
4345 u32 ecx
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
4346 u64 data
= kvm_read_edx_eax(&svm
->vcpu
);
4350 msr
.host_initiated
= false;
4352 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
4353 if (kvm_set_msr(&svm
->vcpu
, &msr
)) {
4354 trace_kvm_msr_write_ex(ecx
, data
);
4355 kvm_inject_gp(&svm
->vcpu
, 0);
4358 trace_kvm_msr_write(ecx
, data
);
4359 return kvm_skip_emulated_instruction(&svm
->vcpu
);
4363 static int msr_interception(struct vcpu_svm
*svm
)
4365 if (svm
->vmcb
->control
.exit_info_1
)
4366 return wrmsr_interception(svm
);
4368 return rdmsr_interception(svm
);
4371 static int interrupt_window_interception(struct vcpu_svm
*svm
)
4373 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
4374 svm_clear_vintr(svm
);
4375 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
4376 mark_dirty(svm
->vmcb
, VMCB_INTR
);
4377 ++svm
->vcpu
.stat
.irq_window_exits
;
4381 static int pause_interception(struct vcpu_svm
*svm
)
4383 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
4384 bool in_kernel
= (svm_get_cpl(vcpu
) == 0);
4386 if (pause_filter_thresh
)
4387 grow_ple_window(vcpu
);
4389 kvm_vcpu_on_spin(vcpu
, in_kernel
);
4393 static int nop_interception(struct vcpu_svm
*svm
)
4395 return kvm_skip_emulated_instruction(&(svm
->vcpu
));
4398 static int monitor_interception(struct vcpu_svm
*svm
)
4400 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
4401 return nop_interception(svm
);
4404 static int mwait_interception(struct vcpu_svm
*svm
)
4406 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
4407 return nop_interception(svm
);
4410 enum avic_ipi_failure_cause
{
4411 AVIC_IPI_FAILURE_INVALID_INT_TYPE
,
4412 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
,
4413 AVIC_IPI_FAILURE_INVALID_TARGET
,
4414 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
,
4417 static int avic_incomplete_ipi_interception(struct vcpu_svm
*svm
)
4419 u32 icrh
= svm
->vmcb
->control
.exit_info_1
>> 32;
4420 u32 icrl
= svm
->vmcb
->control
.exit_info_1
;
4421 u32 id
= svm
->vmcb
->control
.exit_info_2
>> 32;
4422 u32 index
= svm
->vmcb
->control
.exit_info_2
& 0xFF;
4423 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4425 trace_kvm_avic_incomplete_ipi(svm
->vcpu
.vcpu_id
, icrh
, icrl
, id
, index
);
4428 case AVIC_IPI_FAILURE_INVALID_INT_TYPE
:
4430 * AVIC hardware handles the generation of
4431 * IPIs when the specified Message Type is Fixed
4432 * (also known as fixed delivery mode) and
4433 * the Trigger Mode is edge-triggered. The hardware
4434 * also supports self and broadcast delivery modes
4435 * specified via the Destination Shorthand(DSH)
4436 * field of the ICRL. Logical and physical APIC ID
4437 * formats are supported. All other IPI types cause
4438 * a #VMEXIT, which needs to emulated.
4440 kvm_lapic_reg_write(apic
, APIC_ICR2
, icrh
);
4441 kvm_lapic_reg_write(apic
, APIC_ICR
, icrl
);
4443 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING
: {
4445 struct kvm_vcpu
*vcpu
;
4446 struct kvm
*kvm
= svm
->vcpu
.kvm
;
4447 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4450 * At this point, we expect that the AVIC HW has already
4451 * set the appropriate IRR bits on the valid target
4452 * vcpus. So, we just need to kick the appropriate vcpu.
4454 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
4455 bool m
= kvm_apic_match_dest(vcpu
, apic
,
4456 icrl
& KVM_APIC_SHORT_MASK
,
4457 GET_APIC_DEST_FIELD(icrh
),
4458 icrl
& KVM_APIC_DEST_MASK
);
4460 if (m
&& !avic_vcpu_is_running(vcpu
))
4461 kvm_vcpu_wake_up(vcpu
);
4465 case AVIC_IPI_FAILURE_INVALID_TARGET
:
4467 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE
:
4468 WARN_ONCE(1, "Invalid backing page\n");
4471 pr_err("Unknown IPI interception\n");
4477 static u32
*avic_get_logical_id_entry(struct kvm_vcpu
*vcpu
, u32 ldr
, bool flat
)
4479 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4481 u32
*logical_apic_id_table
;
4482 int dlid
= GET_APIC_LOGICAL_ID(ldr
);
4487 if (flat
) { /* flat */
4488 index
= ffs(dlid
) - 1;
4491 } else { /* cluster */
4492 int cluster
= (dlid
& 0xf0) >> 4;
4493 int apic
= ffs(dlid
& 0x0f) - 1;
4495 if ((apic
< 0) || (apic
> 7) ||
4498 index
= (cluster
<< 2) + apic
;
4501 logical_apic_id_table
= (u32
*) page_address(kvm_svm
->avic_logical_id_table_page
);
4503 return &logical_apic_id_table
[index
];
4506 static int avic_ldr_write(struct kvm_vcpu
*vcpu
, u8 g_physical_id
, u32 ldr
,
4510 u32
*entry
, new_entry
;
4512 flat
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
) == APIC_DFR_FLAT
;
4513 entry
= avic_get_logical_id_entry(vcpu
, ldr
, flat
);
4517 new_entry
= READ_ONCE(*entry
);
4518 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
;
4519 new_entry
|= (g_physical_id
& AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK
);
4521 new_entry
|= AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4523 new_entry
&= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK
;
4524 WRITE_ONCE(*entry
, new_entry
);
4529 static int avic_handle_ldr_update(struct kvm_vcpu
*vcpu
)
4532 struct vcpu_svm
*svm
= to_svm(vcpu
);
4533 u32 ldr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_LDR
);
4538 ret
= avic_ldr_write(vcpu
, vcpu
->vcpu_id
, ldr
, true);
4539 if (ret
&& svm
->ldr_reg
) {
4540 avic_ldr_write(vcpu
, 0, svm
->ldr_reg
, false);
4548 static int avic_handle_apic_id_update(struct kvm_vcpu
*vcpu
)
4551 struct vcpu_svm
*svm
= to_svm(vcpu
);
4552 u32 apic_id_reg
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_ID
);
4553 u32 id
= (apic_id_reg
>> 24) & 0xff;
4555 if (vcpu
->vcpu_id
== id
)
4558 old
= avic_get_physical_id_entry(vcpu
, vcpu
->vcpu_id
);
4559 new = avic_get_physical_id_entry(vcpu
, id
);
4563 /* We need to move physical_id_entry to new offset */
4566 to_svm(vcpu
)->avic_physical_id_cache
= new;
4569 * Also update the guest physical APIC ID in the logical
4570 * APIC ID table entry if already setup the LDR.
4573 avic_handle_ldr_update(vcpu
);
4578 static int avic_handle_dfr_update(struct kvm_vcpu
*vcpu
)
4580 struct vcpu_svm
*svm
= to_svm(vcpu
);
4581 struct kvm_svm
*kvm_svm
= to_kvm_svm(vcpu
->kvm
);
4582 u32 dfr
= kvm_lapic_get_reg(vcpu
->arch
.apic
, APIC_DFR
);
4583 u32 mod
= (dfr
>> 28) & 0xf;
4586 * We assume that all local APICs are using the same type.
4587 * If this changes, we need to flush the AVIC logical
4590 if (kvm_svm
->ldr_mode
== mod
)
4593 clear_page(page_address(kvm_svm
->avic_logical_id_table_page
));
4594 kvm_svm
->ldr_mode
= mod
;
4597 avic_handle_ldr_update(vcpu
);
4601 static int avic_unaccel_trap_write(struct vcpu_svm
*svm
)
4603 struct kvm_lapic
*apic
= svm
->vcpu
.arch
.apic
;
4604 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4605 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4609 if (avic_handle_apic_id_update(&svm
->vcpu
))
4613 if (avic_handle_ldr_update(&svm
->vcpu
))
4617 avic_handle_dfr_update(&svm
->vcpu
);
4623 kvm_lapic_reg_write(apic
, offset
, kvm_lapic_get_reg(apic
, offset
));
4628 static bool is_avic_unaccelerated_access_trap(u32 offset
)
4657 static int avic_unaccelerated_access_interception(struct vcpu_svm
*svm
)
4660 u32 offset
= svm
->vmcb
->control
.exit_info_1
&
4661 AVIC_UNACCEL_ACCESS_OFFSET_MASK
;
4662 u32 vector
= svm
->vmcb
->control
.exit_info_2
&
4663 AVIC_UNACCEL_ACCESS_VECTOR_MASK
;
4664 bool write
= (svm
->vmcb
->control
.exit_info_1
>> 32) &
4665 AVIC_UNACCEL_ACCESS_WRITE_MASK
;
4666 bool trap
= is_avic_unaccelerated_access_trap(offset
);
4668 trace_kvm_avic_unaccelerated_access(svm
->vcpu
.vcpu_id
, offset
,
4669 trap
, write
, vector
);
4672 WARN_ONCE(!write
, "svm: Handling trap read.\n");
4673 ret
= avic_unaccel_trap_write(svm
);
4675 /* Handling Fault */
4676 ret
= (emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
);
4682 static int (*const svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
4683 [SVM_EXIT_READ_CR0
] = cr_interception
,
4684 [SVM_EXIT_READ_CR3
] = cr_interception
,
4685 [SVM_EXIT_READ_CR4
] = cr_interception
,
4686 [SVM_EXIT_READ_CR8
] = cr_interception
,
4687 [SVM_EXIT_CR0_SEL_WRITE
] = cr_interception
,
4688 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
4689 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
4690 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
4691 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
4692 [SVM_EXIT_READ_DR0
] = dr_interception
,
4693 [SVM_EXIT_READ_DR1
] = dr_interception
,
4694 [SVM_EXIT_READ_DR2
] = dr_interception
,
4695 [SVM_EXIT_READ_DR3
] = dr_interception
,
4696 [SVM_EXIT_READ_DR4
] = dr_interception
,
4697 [SVM_EXIT_READ_DR5
] = dr_interception
,
4698 [SVM_EXIT_READ_DR6
] = dr_interception
,
4699 [SVM_EXIT_READ_DR7
] = dr_interception
,
4700 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
4701 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
4702 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
4703 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
4704 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
4705 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
4706 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
4707 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
4708 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
4709 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
4710 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
4711 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
4712 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
4713 [SVM_EXIT_EXCP_BASE
+ AC_VECTOR
] = ac_interception
,
4714 [SVM_EXIT_EXCP_BASE
+ GP_VECTOR
] = gp_interception
,
4715 [SVM_EXIT_INTR
] = intr_interception
,
4716 [SVM_EXIT_NMI
] = nmi_interception
,
4717 [SVM_EXIT_SMI
] = nop_on_interception
,
4718 [SVM_EXIT_INIT
] = nop_on_interception
,
4719 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
4720 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
4721 [SVM_EXIT_CPUID
] = cpuid_interception
,
4722 [SVM_EXIT_IRET
] = iret_interception
,
4723 [SVM_EXIT_INVD
] = emulate_on_interception
,
4724 [SVM_EXIT_PAUSE
] = pause_interception
,
4725 [SVM_EXIT_HLT
] = halt_interception
,
4726 [SVM_EXIT_INVLPG
] = invlpg_interception
,
4727 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
4728 [SVM_EXIT_IOIO
] = io_interception
,
4729 [SVM_EXIT_MSR
] = msr_interception
,
4730 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
4731 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
4732 [SVM_EXIT_VMRUN
] = vmrun_interception
,
4733 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
4734 [SVM_EXIT_VMLOAD
] = vmload_interception
,
4735 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
4736 [SVM_EXIT_STGI
] = stgi_interception
,
4737 [SVM_EXIT_CLGI
] = clgi_interception
,
4738 [SVM_EXIT_SKINIT
] = skinit_interception
,
4739 [SVM_EXIT_WBINVD
] = wbinvd_interception
,
4740 [SVM_EXIT_MONITOR
] = monitor_interception
,
4741 [SVM_EXIT_MWAIT
] = mwait_interception
,
4742 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
4743 [SVM_EXIT_NPF
] = npf_interception
,
4744 [SVM_EXIT_RSM
] = rsm_interception
,
4745 [SVM_EXIT_AVIC_INCOMPLETE_IPI
] = avic_incomplete_ipi_interception
,
4746 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS
] = avic_unaccelerated_access_interception
,
4749 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
4751 struct vcpu_svm
*svm
= to_svm(vcpu
);
4752 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
4753 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
4755 pr_err("VMCB Control Area:\n");
4756 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
4757 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
4758 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
4759 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
4760 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
4761 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
4762 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
4763 pr_err("%-20s%d\n", "pause filter threshold:",
4764 control
->pause_filter_thresh
);
4765 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
4766 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
4767 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
4768 pr_err("%-20s%d\n", "asid:", control
->asid
);
4769 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
4770 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
4771 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
4772 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
4773 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
4774 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
4775 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
4776 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
4777 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
4778 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
4779 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
4780 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control
->avic_vapic_bar
);
4781 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
4782 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
4783 pr_err("%-20s%lld\n", "virt_ext:", control
->virt_ext
);
4784 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
4785 pr_err("%-20s%016llx\n", "avic_backing_page:", control
->avic_backing_page
);
4786 pr_err("%-20s%016llx\n", "avic_logical_id:", control
->avic_logical_id
);
4787 pr_err("%-20s%016llx\n", "avic_physical_id:", control
->avic_physical_id
);
4788 pr_err("VMCB State Save Area:\n");
4789 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4791 save
->es
.selector
, save
->es
.attrib
,
4792 save
->es
.limit
, save
->es
.base
);
4793 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4795 save
->cs
.selector
, save
->cs
.attrib
,
4796 save
->cs
.limit
, save
->cs
.base
);
4797 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4799 save
->ss
.selector
, save
->ss
.attrib
,
4800 save
->ss
.limit
, save
->ss
.base
);
4801 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4803 save
->ds
.selector
, save
->ds
.attrib
,
4804 save
->ds
.limit
, save
->ds
.base
);
4805 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4807 save
->fs
.selector
, save
->fs
.attrib
,
4808 save
->fs
.limit
, save
->fs
.base
);
4809 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4811 save
->gs
.selector
, save
->gs
.attrib
,
4812 save
->gs
.limit
, save
->gs
.base
);
4813 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4815 save
->gdtr
.selector
, save
->gdtr
.attrib
,
4816 save
->gdtr
.limit
, save
->gdtr
.base
);
4817 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4819 save
->ldtr
.selector
, save
->ldtr
.attrib
,
4820 save
->ldtr
.limit
, save
->ldtr
.base
);
4821 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4823 save
->idtr
.selector
, save
->idtr
.attrib
,
4824 save
->idtr
.limit
, save
->idtr
.base
);
4825 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4827 save
->tr
.selector
, save
->tr
.attrib
,
4828 save
->tr
.limit
, save
->tr
.base
);
4829 pr_err("cpl: %d efer: %016llx\n",
4830 save
->cpl
, save
->efer
);
4831 pr_err("%-15s %016llx %-13s %016llx\n",
4832 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
4833 pr_err("%-15s %016llx %-13s %016llx\n",
4834 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
4835 pr_err("%-15s %016llx %-13s %016llx\n",
4836 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
4837 pr_err("%-15s %016llx %-13s %016llx\n",
4838 "rip:", save
->rip
, "rflags:", save
->rflags
);
4839 pr_err("%-15s %016llx %-13s %016llx\n",
4840 "rsp:", save
->rsp
, "rax:", save
->rax
);
4841 pr_err("%-15s %016llx %-13s %016llx\n",
4842 "star:", save
->star
, "lstar:", save
->lstar
);
4843 pr_err("%-15s %016llx %-13s %016llx\n",
4844 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
4845 pr_err("%-15s %016llx %-13s %016llx\n",
4846 "kernel_gs_base:", save
->kernel_gs_base
,
4847 "sysenter_cs:", save
->sysenter_cs
);
4848 pr_err("%-15s %016llx %-13s %016llx\n",
4849 "sysenter_esp:", save
->sysenter_esp
,
4850 "sysenter_eip:", save
->sysenter_eip
);
4851 pr_err("%-15s %016llx %-13s %016llx\n",
4852 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
4853 pr_err("%-15s %016llx %-13s %016llx\n",
4854 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
4855 pr_err("%-15s %016llx %-13s %016llx\n",
4856 "excp_from:", save
->last_excp_from
,
4857 "excp_to:", save
->last_excp_to
);
4860 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4862 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
4864 *info1
= control
->exit_info_1
;
4865 *info2
= control
->exit_info_2
;
4868 static int handle_exit(struct kvm_vcpu
*vcpu
)
4870 struct vcpu_svm
*svm
= to_svm(vcpu
);
4871 struct kvm_run
*kvm_run
= vcpu
->run
;
4872 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
4874 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
4876 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
4877 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
4879 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
4881 if (unlikely(svm
->nested
.exit_required
)) {
4882 nested_svm_vmexit(svm
);
4883 svm
->nested
.exit_required
= false;
4888 if (is_guest_mode(vcpu
)) {
4891 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
4892 svm
->vmcb
->control
.exit_info_1
,
4893 svm
->vmcb
->control
.exit_info_2
,
4894 svm
->vmcb
->control
.exit_int_info
,
4895 svm
->vmcb
->control
.exit_int_info_err
,
4898 vmexit
= nested_svm_exit_special(svm
);
4900 if (vmexit
== NESTED_EXIT_CONTINUE
)
4901 vmexit
= nested_svm_exit_handled(svm
);
4903 if (vmexit
== NESTED_EXIT_DONE
)
4907 svm_complete_interrupts(svm
);
4909 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
4910 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4911 kvm_run
->fail_entry
.hardware_entry_failure_reason
4912 = svm
->vmcb
->control
.exit_code
;
4913 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4918 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
4919 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
4920 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
4921 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
4922 printk(KERN_ERR
"%s: unexpected exit_int_info 0x%x "
4924 __func__
, svm
->vmcb
->control
.exit_int_info
,
4927 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
4928 || !svm_exit_handlers
[exit_code
]) {
4929 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code
);
4930 kvm_queue_exception(vcpu
, UD_VECTOR
);
4934 return svm_exit_handlers
[exit_code
](svm
);
4937 static void reload_tss(struct kvm_vcpu
*vcpu
)
4939 int cpu
= raw_smp_processor_id();
4941 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4942 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
4946 static void pre_sev_run(struct vcpu_svm
*svm
, int cpu
)
4948 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4949 int asid
= sev_get_asid(svm
->vcpu
.kvm
);
4951 /* Assign the asid allocated with this SEV guest */
4952 svm
->vmcb
->control
.asid
= asid
;
4957 * 1) when different VMCB for the same ASID is to be run on the same host CPU.
4958 * 2) or this VMCB was executed on different host CPU in previous VMRUNs.
4960 if (sd
->sev_vmcbs
[asid
] == svm
->vmcb
&&
4961 svm
->last_cpu
== cpu
)
4964 svm
->last_cpu
= cpu
;
4965 sd
->sev_vmcbs
[asid
] = svm
->vmcb
;
4966 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
4967 mark_dirty(svm
->vmcb
, VMCB_ASID
);
4970 static void pre_svm_run(struct vcpu_svm
*svm
)
4972 int cpu
= raw_smp_processor_id();
4974 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
4976 if (sev_guest(svm
->vcpu
.kvm
))
4977 return pre_sev_run(svm
, cpu
);
4979 /* FIXME: handle wraparound of asid_generation */
4980 if (svm
->asid_generation
!= sd
->asid_generation
)
4984 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
4986 struct vcpu_svm
*svm
= to_svm(vcpu
);
4988 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
4989 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
4990 set_intercept(svm
, INTERCEPT_IRET
);
4991 ++vcpu
->stat
.nmi_injections
;
4994 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
4996 struct vmcb_control_area
*control
;
4998 /* The following fields are ignored when AVIC is enabled */
4999 control
= &svm
->vmcb
->control
;
5000 control
->int_vector
= irq
;
5001 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
5002 control
->int_ctl
|= V_IRQ_MASK
|
5003 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
5004 mark_dirty(svm
->vmcb
, VMCB_INTR
);
5007 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
5009 struct vcpu_svm
*svm
= to_svm(vcpu
);
5011 BUG_ON(!(gif_set(svm
)));
5013 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
5014 ++vcpu
->stat
.irq_injections
;
5016 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
5017 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
5020 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu
*vcpu
)
5022 return is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
);
5025 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5027 struct vcpu_svm
*svm
= to_svm(vcpu
);
5029 if (svm_nested_virtualize_tpr(vcpu
) ||
5030 kvm_vcpu_apicv_active(vcpu
))
5033 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5039 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
5042 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
5047 static bool svm_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5049 return avic
&& irqchip_split(vcpu
->kvm
);
5052 static void svm_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
5056 static void svm_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
5060 /* Note: Currently only used by Hyper-V. */
5061 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5063 struct vcpu_svm
*svm
= to_svm(vcpu
);
5064 struct vmcb
*vmcb
= svm
->vmcb
;
5066 if (!kvm_vcpu_apicv_active(&svm
->vcpu
))
5069 vmcb
->control
.int_ctl
&= ~AVIC_ENABLE_MASK
;
5070 mark_dirty(vmcb
, VMCB_INTR
);
5073 static void svm_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
5078 static void svm_deliver_avic_intr(struct kvm_vcpu
*vcpu
, int vec
)
5080 kvm_lapic_set_irr(vec
, vcpu
->arch
.apic
);
5081 smp_mb__after_atomic();
5083 if (avic_vcpu_is_running(vcpu
))
5084 wrmsrl(SVM_AVIC_DOORBELL
,
5085 kvm_cpu_get_apicid(vcpu
->cpu
));
5087 kvm_vcpu_wake_up(vcpu
);
5090 static void svm_ir_list_del(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5092 unsigned long flags
;
5093 struct amd_svm_iommu_ir
*cur
;
5095 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5096 list_for_each_entry(cur
, &svm
->ir_list
, node
) {
5097 if (cur
->data
!= pi
->ir_data
)
5099 list_del(&cur
->node
);
5103 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5106 static int svm_ir_list_add(struct vcpu_svm
*svm
, struct amd_iommu_pi_data
*pi
)
5109 unsigned long flags
;
5110 struct amd_svm_iommu_ir
*ir
;
5113 * In some cases, the existing irte is updaed and re-set,
5114 * so we need to check here if it's already been * added
5117 if (pi
->ir_data
&& (pi
->prev_ga_tag
!= 0)) {
5118 struct kvm
*kvm
= svm
->vcpu
.kvm
;
5119 u32 vcpu_id
= AVIC_GATAG_TO_VCPUID(pi
->prev_ga_tag
);
5120 struct kvm_vcpu
*prev_vcpu
= kvm_get_vcpu_by_id(kvm
, vcpu_id
);
5121 struct vcpu_svm
*prev_svm
;
5128 prev_svm
= to_svm(prev_vcpu
);
5129 svm_ir_list_del(prev_svm
, pi
);
5133 * Allocating new amd_iommu_pi_data, which will get
5134 * add to the per-vcpu ir_list.
5136 ir
= kzalloc(sizeof(struct amd_svm_iommu_ir
), GFP_KERNEL
);
5141 ir
->data
= pi
->ir_data
;
5143 spin_lock_irqsave(&svm
->ir_list_lock
, flags
);
5144 list_add(&ir
->node
, &svm
->ir_list
);
5145 spin_unlock_irqrestore(&svm
->ir_list_lock
, flags
);
5152 * The HW cannot support posting multicast/broadcast
5153 * interrupts to a vCPU. So, we still use legacy interrupt
5154 * remapping for these kind of interrupts.
5156 * For lowest-priority interrupts, we only support
5157 * those with single CPU as the destination, e.g. user
5158 * configures the interrupts via /proc/irq or uses
5159 * irqbalance to make the interrupts single-CPU.
5162 get_pi_vcpu_info(struct kvm
*kvm
, struct kvm_kernel_irq_routing_entry
*e
,
5163 struct vcpu_data
*vcpu_info
, struct vcpu_svm
**svm
)
5165 struct kvm_lapic_irq irq
;
5166 struct kvm_vcpu
*vcpu
= NULL
;
5168 kvm_set_msi_irq(kvm
, e
, &irq
);
5170 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
5171 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
5172 __func__
, irq
.vector
);
5176 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__
,
5178 *svm
= to_svm(vcpu
);
5179 vcpu_info
->pi_desc_addr
= __sme_set(page_to_phys((*svm
)->avic_backing_page
));
5180 vcpu_info
->vector
= irq
.vector
;
5186 * svm_update_pi_irte - set IRTE for Posted-Interrupts
5189 * @host_irq: host irq of the interrupt
5190 * @guest_irq: gsi of the interrupt
5191 * @set: set or unset PI
5192 * returns 0 on success, < 0 on failure
5194 static int svm_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
5195 uint32_t guest_irq
, bool set
)
5197 struct kvm_kernel_irq_routing_entry
*e
;
5198 struct kvm_irq_routing_table
*irq_rt
;
5199 int idx
, ret
= -EINVAL
;
5201 if (!kvm_arch_has_assigned_device(kvm
) ||
5202 !irq_remapping_cap(IRQ_POSTING_CAP
))
5205 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
5206 __func__
, host_irq
, guest_irq
, set
);
5208 idx
= srcu_read_lock(&kvm
->irq_srcu
);
5209 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
5210 WARN_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
5212 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
5213 struct vcpu_data vcpu_info
;
5214 struct vcpu_svm
*svm
= NULL
;
5216 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
5220 * Here, we setup with legacy mode in the following cases:
5221 * 1. When cannot target interrupt to a specific vcpu.
5222 * 2. Unsetting posted interrupt.
5223 * 3. APIC virtialization is disabled for the vcpu.
5225 if (!get_pi_vcpu_info(kvm
, e
, &vcpu_info
, &svm
) && set
&&
5226 kvm_vcpu_apicv_active(&svm
->vcpu
)) {
5227 struct amd_iommu_pi_data pi
;
5229 /* Try to enable guest_mode in IRTE */
5230 pi
.base
= __sme_set(page_to_phys(svm
->avic_backing_page
) &
5232 pi
.ga_tag
= AVIC_GATAG(to_kvm_svm(kvm
)->avic_vm_id
,
5234 pi
.is_guest_mode
= true;
5235 pi
.vcpu_data
= &vcpu_info
;
5236 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5239 * Here, we successfully setting up vcpu affinity in
5240 * IOMMU guest mode. Now, we need to store the posted
5241 * interrupt information in a per-vcpu ir_list so that
5242 * we can reference to them directly when we update vcpu
5243 * scheduling information in IOMMU irte.
5245 if (!ret
&& pi
.is_guest_mode
)
5246 svm_ir_list_add(svm
, &pi
);
5248 /* Use legacy mode in IRTE */
5249 struct amd_iommu_pi_data pi
;
5252 * Here, pi is used to:
5253 * - Tell IOMMU to use legacy mode for this interrupt.
5254 * - Retrieve ga_tag of prior interrupt remapping data.
5256 pi
.is_guest_mode
= false;
5257 ret
= irq_set_vcpu_affinity(host_irq
, &pi
);
5260 * Check if the posted interrupt was previously
5261 * setup with the guest_mode by checking if the ga_tag
5262 * was cached. If so, we need to clean up the per-vcpu
5265 if (!ret
&& pi
.prev_ga_tag
) {
5266 int id
= AVIC_GATAG_TO_VCPUID(pi
.prev_ga_tag
);
5267 struct kvm_vcpu
*vcpu
;
5269 vcpu
= kvm_get_vcpu_by_id(kvm
, id
);
5271 svm_ir_list_del(to_svm(vcpu
), &pi
);
5276 trace_kvm_pi_irte_update(svm
->vcpu
.vcpu_id
,
5279 vcpu_info
.pi_desc_addr
, set
);
5283 pr_err("%s: failed to update PI IRTE\n", __func__
);
5290 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
5294 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
5296 struct vcpu_svm
*svm
= to_svm(vcpu
);
5297 struct vmcb
*vmcb
= svm
->vmcb
;
5299 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
5300 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5301 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
5306 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5308 struct vcpu_svm
*svm
= to_svm(vcpu
);
5310 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
5313 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5315 struct vcpu_svm
*svm
= to_svm(vcpu
);
5318 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
5319 set_intercept(svm
, INTERCEPT_IRET
);
5321 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
5322 clr_intercept(svm
, INTERCEPT_IRET
);
5326 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5328 struct vcpu_svm
*svm
= to_svm(vcpu
);
5329 struct vmcb
*vmcb
= svm
->vmcb
;
5332 if (!gif_set(svm
) ||
5333 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
5336 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
5338 if (is_guest_mode(vcpu
))
5339 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
5344 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5346 struct vcpu_svm
*svm
= to_svm(vcpu
);
5348 if (kvm_vcpu_apicv_active(vcpu
))
5352 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
5353 * 1, because that's a separate STGI/VMRUN intercept. The next time we
5354 * get that intercept, this function will be called again though and
5355 * we'll get the vintr intercept. However, if the vGIF feature is
5356 * enabled, the STGI interception will not occur. Enable the irq
5357 * window under the assumption that the hardware will set the GIF.
5359 if ((vgif_enabled(svm
) || gif_set(svm
)) && nested_svm_intr(svm
)) {
5361 svm_inject_irq(svm
, 0x0);
5365 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5367 struct vcpu_svm
*svm
= to_svm(vcpu
);
5369 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
5371 return; /* IRET will cause a vm exit */
5373 if (!gif_set(svm
)) {
5374 if (vgif_enabled(svm
))
5375 set_intercept(svm
, INTERCEPT_STGI
);
5376 return; /* STGI will cause a vm exit */
5379 if (svm
->nested
.exit_required
)
5380 return; /* we're not going to run the guest yet */
5383 * Something prevents NMI from been injected. Single step over possible
5384 * problem (IRET or exception injection or interrupt shadow)
5386 svm
->nmi_singlestep_guest_rflags
= svm_get_rflags(vcpu
);
5387 svm
->nmi_singlestep
= true;
5388 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
5391 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5396 static int svm_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
5401 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
5403 struct vcpu_svm
*svm
= to_svm(vcpu
);
5405 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
5406 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
5408 svm
->asid_generation
--;
5411 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
5415 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
5417 struct vcpu_svm
*svm
= to_svm(vcpu
);
5419 if (svm_nested_virtualize_tpr(vcpu
))
5422 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
5423 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
5424 kvm_set_cr8(vcpu
, cr8
);
5428 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
5430 struct vcpu_svm
*svm
= to_svm(vcpu
);
5433 if (svm_nested_virtualize_tpr(vcpu
) ||
5434 kvm_vcpu_apicv_active(vcpu
))
5437 cr8
= kvm_get_cr8(vcpu
);
5438 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
5439 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
5442 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
5446 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
5447 unsigned int3_injected
= svm
->int3_injected
;
5449 svm
->int3_injected
= 0;
5452 * If we've made progress since setting HF_IRET_MASK, we've
5453 * executed an IRET and can allow NMI injection.
5455 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
5456 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
5457 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
5458 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5461 svm
->vcpu
.arch
.nmi_injected
= false;
5462 kvm_clear_exception_queue(&svm
->vcpu
);
5463 kvm_clear_interrupt_queue(&svm
->vcpu
);
5465 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
5468 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
5470 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
5471 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
5474 case SVM_EXITINTINFO_TYPE_NMI
:
5475 svm
->vcpu
.arch
.nmi_injected
= true;
5477 case SVM_EXITINTINFO_TYPE_EXEPT
:
5479 * In case of software exceptions, do not reinject the vector,
5480 * but re-execute the instruction instead. Rewind RIP first
5481 * if we emulated INT3 before.
5483 if (kvm_exception_is_soft(vector
)) {
5484 if (vector
== BP_VECTOR
&& int3_injected
&&
5485 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
5486 kvm_rip_write(&svm
->vcpu
,
5487 kvm_rip_read(&svm
->vcpu
) -
5491 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
5492 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
5493 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
5496 kvm_requeue_exception(&svm
->vcpu
, vector
);
5498 case SVM_EXITINTINFO_TYPE_INTR
:
5499 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
5506 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
5508 struct vcpu_svm
*svm
= to_svm(vcpu
);
5509 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
5511 control
->exit_int_info
= control
->event_inj
;
5512 control
->exit_int_info_err
= control
->event_inj_err
;
5513 control
->event_inj
= 0;
5514 svm_complete_interrupts(svm
);
5517 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
5519 struct vcpu_svm
*svm
= to_svm(vcpu
);
5521 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
5522 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
5523 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
5526 * A vmexit emulation is required before the vcpu can be executed
5529 if (unlikely(svm
->nested
.exit_required
))
5533 * Disable singlestep if we're injecting an interrupt/exception.
5534 * We don't want our modified rflags to be pushed on the stack where
5535 * we might not be able to easily reset them if we disabled NMI
5538 if (svm
->nmi_singlestep
&& svm
->vmcb
->control
.event_inj
) {
5540 * Event injection happens before external interrupts cause a
5541 * vmexit and interrupts are disabled here, so smp_send_reschedule
5542 * is enough to force an immediate vmexit.
5544 disable_nmi_singlestep(svm
);
5545 smp_send_reschedule(vcpu
->cpu
);
5550 sync_lapic_to_cr8(vcpu
);
5552 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
5559 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
5560 * it's non-zero. Since vmentry is serialising on affected CPUs, there
5561 * is no need to worry about the conditional branch over the wrmsr
5562 * being speculatively taken.
5565 native_wrmsrl(MSR_IA32_SPEC_CTRL
, svm
->spec_ctrl
);
5568 "push %%" _ASM_BP
"; \n\t"
5569 "mov %c[rbx](%[svm]), %%" _ASM_BX
" \n\t"
5570 "mov %c[rcx](%[svm]), %%" _ASM_CX
" \n\t"
5571 "mov %c[rdx](%[svm]), %%" _ASM_DX
" \n\t"
5572 "mov %c[rsi](%[svm]), %%" _ASM_SI
" \n\t"
5573 "mov %c[rdi](%[svm]), %%" _ASM_DI
" \n\t"
5574 "mov %c[rbp](%[svm]), %%" _ASM_BP
" \n\t"
5575 #ifdef CONFIG_X86_64
5576 "mov %c[r8](%[svm]), %%r8 \n\t"
5577 "mov %c[r9](%[svm]), %%r9 \n\t"
5578 "mov %c[r10](%[svm]), %%r10 \n\t"
5579 "mov %c[r11](%[svm]), %%r11 \n\t"
5580 "mov %c[r12](%[svm]), %%r12 \n\t"
5581 "mov %c[r13](%[svm]), %%r13 \n\t"
5582 "mov %c[r14](%[svm]), %%r14 \n\t"
5583 "mov %c[r15](%[svm]), %%r15 \n\t"
5586 /* Enter guest mode */
5587 "push %%" _ASM_AX
" \n\t"
5588 "mov %c[vmcb](%[svm]), %%" _ASM_AX
" \n\t"
5589 __ex(SVM_VMLOAD
) "\n\t"
5590 __ex(SVM_VMRUN
) "\n\t"
5591 __ex(SVM_VMSAVE
) "\n\t"
5592 "pop %%" _ASM_AX
" \n\t"
5594 /* Save guest registers, load host registers */
5595 "mov %%" _ASM_BX
", %c[rbx](%[svm]) \n\t"
5596 "mov %%" _ASM_CX
", %c[rcx](%[svm]) \n\t"
5597 "mov %%" _ASM_DX
", %c[rdx](%[svm]) \n\t"
5598 "mov %%" _ASM_SI
", %c[rsi](%[svm]) \n\t"
5599 "mov %%" _ASM_DI
", %c[rdi](%[svm]) \n\t"
5600 "mov %%" _ASM_BP
", %c[rbp](%[svm]) \n\t"
5601 #ifdef CONFIG_X86_64
5602 "mov %%r8, %c[r8](%[svm]) \n\t"
5603 "mov %%r9, %c[r9](%[svm]) \n\t"
5604 "mov %%r10, %c[r10](%[svm]) \n\t"
5605 "mov %%r11, %c[r11](%[svm]) \n\t"
5606 "mov %%r12, %c[r12](%[svm]) \n\t"
5607 "mov %%r13, %c[r13](%[svm]) \n\t"
5608 "mov %%r14, %c[r14](%[svm]) \n\t"
5609 "mov %%r15, %c[r15](%[svm]) \n\t"
5612 * Clear host registers marked as clobbered to prevent
5615 "xor %%" _ASM_BX
", %%" _ASM_BX
" \n\t"
5616 "xor %%" _ASM_CX
", %%" _ASM_CX
" \n\t"
5617 "xor %%" _ASM_DX
", %%" _ASM_DX
" \n\t"
5618 "xor %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
5619 "xor %%" _ASM_DI
", %%" _ASM_DI
" \n\t"
5620 #ifdef CONFIG_X86_64
5621 "xor %%r8, %%r8 \n\t"
5622 "xor %%r9, %%r9 \n\t"
5623 "xor %%r10, %%r10 \n\t"
5624 "xor %%r11, %%r11 \n\t"
5625 "xor %%r12, %%r12 \n\t"
5626 "xor %%r13, %%r13 \n\t"
5627 "xor %%r14, %%r14 \n\t"
5628 "xor %%r15, %%r15 \n\t"
5633 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
5634 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
5635 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
5636 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
5637 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
5638 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
5639 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
5640 #ifdef CONFIG_X86_64
5641 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
5642 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
5643 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
5644 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
5645 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
5646 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
5647 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
5648 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
5651 #ifdef CONFIG_X86_64
5652 , "rbx", "rcx", "rdx", "rsi", "rdi"
5653 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
5655 , "ebx", "ecx", "edx", "esi", "edi"
5660 * We do not use IBRS in the kernel. If this vCPU has used the
5661 * SPEC_CTRL MSR it may have left it on; save the value and
5662 * turn it off. This is much more efficient than blindly adding
5663 * it to the atomic save/restore list. Especially as the former
5664 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
5666 * For non-nested case:
5667 * If the L01 MSR bitmap does not intercept the MSR, then we need to
5671 * If the L02 MSR bitmap does not intercept the MSR, then we need to
5674 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
5675 svm
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
5678 native_wrmsrl(MSR_IA32_SPEC_CTRL
, 0);
5680 /* Eliminate branch target predictions from guest mode */
5683 #ifdef CONFIG_X86_64
5684 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
5686 loadsegment(fs
, svm
->host
.fs
);
5687 #ifndef CONFIG_X86_32_LAZY_GS
5688 loadsegment(gs
, svm
->host
.gs
);
5694 local_irq_disable();
5696 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
5697 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
5698 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
5699 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
5701 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5702 kvm_before_interrupt(&svm
->vcpu
);
5706 /* Any pending NMI will happen here */
5708 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
5709 kvm_after_interrupt(&svm
->vcpu
);
5711 sync_cr8_to_lapic(vcpu
);
5715 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
5717 /* if exit due to PF check for async PF */
5718 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
5719 svm
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
5722 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
5723 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
5727 * We need to handle MC intercepts here before the vcpu has a chance to
5728 * change the physical cpu
5730 if (unlikely(svm
->vmcb
->control
.exit_code
==
5731 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
5732 svm_handle_mce(svm
);
5734 mark_all_clean(svm
->vmcb
);
5736 STACK_FRAME_NON_STANDARD(svm_vcpu_run
);
5738 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5740 struct vcpu_svm
*svm
= to_svm(vcpu
);
5742 svm
->vmcb
->save
.cr3
= __sme_set(root
);
5743 mark_dirty(svm
->vmcb
, VMCB_CR
);
5744 svm_flush_tlb(vcpu
, true);
5747 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
5749 struct vcpu_svm
*svm
= to_svm(vcpu
);
5751 svm
->vmcb
->control
.nested_cr3
= __sme_set(root
);
5752 mark_dirty(svm
->vmcb
, VMCB_NPT
);
5754 /* Also sync guest cr3 here in case we live migrate */
5755 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
5756 mark_dirty(svm
->vmcb
, VMCB_CR
);
5758 svm_flush_tlb(vcpu
, true);
5761 static int is_disabled(void)
5765 rdmsrl(MSR_VM_CR
, vm_cr
);
5766 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
5773 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5776 * Patch in the VMMCALL instruction:
5778 hypercall
[0] = 0x0f;
5779 hypercall
[1] = 0x01;
5780 hypercall
[2] = 0xd9;
5783 static void svm_check_processor_compat(void *rtn
)
5788 static bool svm_cpu_has_accelerated_tpr(void)
5793 static bool svm_has_high_real_mode_segbase(void)
5798 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
5803 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
5805 struct vcpu_svm
*svm
= to_svm(vcpu
);
5807 /* Update nrips enabled cache */
5808 svm
->nrips_enabled
= !!guest_cpuid_has(&svm
->vcpu
, X86_FEATURE_NRIPS
);
5810 if (!kvm_vcpu_apicv_active(vcpu
))
5813 guest_cpuid_clear(vcpu
, X86_FEATURE_X2APIC
);
5816 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5821 entry
->ecx
&= ~bit(X86_FEATURE_X2APIC
);
5825 entry
->ecx
|= (1 << 2); /* Set SVM bit */
5828 entry
->eax
= 1; /* SVM revision 1 */
5829 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
5830 ASID emulation to nested SVM */
5831 entry
->ecx
= 0; /* Reserved */
5832 entry
->edx
= 0; /* Per default do not support any
5833 additional features */
5835 /* Support next_rip if host supports it */
5836 if (boot_cpu_has(X86_FEATURE_NRIPS
))
5837 entry
->edx
|= SVM_FEATURE_NRIP
;
5839 /* Support NPT for the guest if enabled */
5841 entry
->edx
|= SVM_FEATURE_NPT
;
5845 /* Support memory encryption cpuid if host supports it */
5846 if (boot_cpu_has(X86_FEATURE_SEV
))
5847 cpuid(0x8000001f, &entry
->eax
, &entry
->ebx
,
5848 &entry
->ecx
, &entry
->edx
);
5853 static int svm_get_lpage_level(void)
5855 return PT_PDPE_LEVEL
;
5858 static bool svm_rdtscp_supported(void)
5860 return boot_cpu_has(X86_FEATURE_RDTSCP
);
5863 static bool svm_invpcid_supported(void)
5868 static bool svm_mpx_supported(void)
5873 static bool svm_xsaves_supported(void)
5878 static bool svm_umip_emulated(void)
5883 static bool svm_has_wbinvd_exit(void)
5888 #define PRE_EX(exit) { .exit_code = (exit), \
5889 .stage = X86_ICPT_PRE_EXCEPT, }
5890 #define POST_EX(exit) { .exit_code = (exit), \
5891 .stage = X86_ICPT_POST_EXCEPT, }
5892 #define POST_MEM(exit) { .exit_code = (exit), \
5893 .stage = X86_ICPT_POST_MEMACCESS, }
5895 static const struct __x86_intercept
{
5897 enum x86_intercept_stage stage
;
5898 } x86_intercept_map
[] = {
5899 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
5900 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5901 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5902 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
5903 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
5904 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
5905 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
5906 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
5907 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
5908 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
5909 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
5910 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
5911 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
5912 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
5913 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
5914 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
5915 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
5916 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
5917 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
5918 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
5919 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
5920 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
5921 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
5922 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
5923 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
5924 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
5925 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
5926 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
5927 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
5928 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
5929 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
5930 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
5931 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
5932 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
5933 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
5934 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
5935 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
5936 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
5937 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
5938 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
5939 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
5940 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
5941 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
5942 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
5943 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
5944 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
5951 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
5952 struct x86_instruction_info
*info
,
5953 enum x86_intercept_stage stage
)
5955 struct vcpu_svm
*svm
= to_svm(vcpu
);
5956 int vmexit
, ret
= X86EMUL_CONTINUE
;
5957 struct __x86_intercept icpt_info
;
5958 struct vmcb
*vmcb
= svm
->vmcb
;
5960 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
5963 icpt_info
= x86_intercept_map
[info
->intercept
];
5965 if (stage
!= icpt_info
.stage
)
5968 switch (icpt_info
.exit_code
) {
5969 case SVM_EXIT_READ_CR0
:
5970 if (info
->intercept
== x86_intercept_cr_read
)
5971 icpt_info
.exit_code
+= info
->modrm_reg
;
5973 case SVM_EXIT_WRITE_CR0
: {
5974 unsigned long cr0
, val
;
5977 if (info
->intercept
== x86_intercept_cr_write
)
5978 icpt_info
.exit_code
+= info
->modrm_reg
;
5980 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
||
5981 info
->intercept
== x86_intercept_clts
)
5984 intercept
= svm
->nested
.intercept
;
5986 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
5989 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
5990 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
5992 if (info
->intercept
== x86_intercept_lmsw
) {
5995 /* lmsw can't clear PE - catch this here */
5996 if (cr0
& X86_CR0_PE
)
6001 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
6005 case SVM_EXIT_READ_DR0
:
6006 case SVM_EXIT_WRITE_DR0
:
6007 icpt_info
.exit_code
+= info
->modrm_reg
;
6010 if (info
->intercept
== x86_intercept_wrmsr
)
6011 vmcb
->control
.exit_info_1
= 1;
6013 vmcb
->control
.exit_info_1
= 0;
6015 case SVM_EXIT_PAUSE
:
6017 * We get this for NOP only, but pause
6018 * is rep not, check this here
6020 if (info
->rep_prefix
!= REPE_PREFIX
)
6023 case SVM_EXIT_IOIO
: {
6027 if (info
->intercept
== x86_intercept_in
||
6028 info
->intercept
== x86_intercept_ins
) {
6029 exit_info
= ((info
->src_val
& 0xffff) << 16) |
6031 bytes
= info
->dst_bytes
;
6033 exit_info
= (info
->dst_val
& 0xffff) << 16;
6034 bytes
= info
->src_bytes
;
6037 if (info
->intercept
== x86_intercept_outs
||
6038 info
->intercept
== x86_intercept_ins
)
6039 exit_info
|= SVM_IOIO_STR_MASK
;
6041 if (info
->rep_prefix
)
6042 exit_info
|= SVM_IOIO_REP_MASK
;
6044 bytes
= min(bytes
, 4u);
6046 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
6048 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
6050 vmcb
->control
.exit_info_1
= exit_info
;
6051 vmcb
->control
.exit_info_2
= info
->next_rip
;
6059 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
6060 if (static_cpu_has(X86_FEATURE_NRIPS
))
6061 vmcb
->control
.next_rip
= info
->next_rip
;
6062 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
6063 vmexit
= nested_svm_exit_handled(svm
);
6065 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
6072 static void svm_handle_external_intr(struct kvm_vcpu
*vcpu
)
6076 * We must have an instruction with interrupts enabled, so
6077 * the timer interrupt isn't delayed by the interrupt shadow.
6080 local_irq_disable();
6083 static void svm_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
6085 if (pause_filter_thresh
)
6086 shrink_ple_window(vcpu
);
6089 static inline void avic_post_state_restore(struct kvm_vcpu
*vcpu
)
6091 if (avic_handle_apic_id_update(vcpu
) != 0)
6093 if (avic_handle_dfr_update(vcpu
) != 0)
6095 avic_handle_ldr_update(vcpu
);
6098 static void svm_setup_mce(struct kvm_vcpu
*vcpu
)
6100 /* [63:9] are reserved. */
6101 vcpu
->arch
.mcg_cap
&= 0x1ff;
6104 static int svm_smi_allowed(struct kvm_vcpu
*vcpu
)
6106 struct vcpu_svm
*svm
= to_svm(vcpu
);
6108 /* Per APM Vol.2 15.22.2 "Response to SMI" */
6112 if (is_guest_mode(&svm
->vcpu
) &&
6113 svm
->nested
.intercept
& (1ULL << INTERCEPT_SMI
)) {
6114 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
6115 svm
->vmcb
->control
.exit_code
= SVM_EXIT_SMI
;
6116 svm
->nested
.exit_required
= true;
6123 static int svm_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
6125 struct vcpu_svm
*svm
= to_svm(vcpu
);
6128 if (is_guest_mode(vcpu
)) {
6129 /* FED8h - SVM Guest */
6130 put_smstate(u64
, smstate
, 0x7ed8, 1);
6131 /* FEE0h - SVM Guest VMCB Physical Address */
6132 put_smstate(u64
, smstate
, 0x7ee0, svm
->nested
.vmcb
);
6134 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
6135 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
6136 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
6138 ret
= nested_svm_vmexit(svm
);
6145 static int svm_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
6147 struct vcpu_svm
*svm
= to_svm(vcpu
);
6148 struct vmcb
*nested_vmcb
;
6156 ret
= kvm_vcpu_read_guest(vcpu
, smbase
+ 0xfed8, &svm_state_save
,
6157 sizeof(svm_state_save
));
6161 if (svm_state_save
.guest
) {
6162 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
6163 nested_vmcb
= nested_svm_map(svm
, svm_state_save
.vmcb
, &page
);
6165 enter_svm_guest_mode(svm
, svm_state_save
.vmcb
, nested_vmcb
, page
);
6168 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
6173 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
6175 struct vcpu_svm
*svm
= to_svm(vcpu
);
6177 if (!gif_set(svm
)) {
6178 if (vgif_enabled(svm
))
6179 set_intercept(svm
, INTERCEPT_STGI
);
6180 /* STGI will cause a vm exit */
6186 static int sev_asid_new(void)
6191 * SEV-enabled guest must use asid from min_sev_asid to max_sev_asid.
6193 pos
= find_next_zero_bit(sev_asid_bitmap
, max_sev_asid
, min_sev_asid
- 1);
6194 if (pos
>= max_sev_asid
)
6197 set_bit(pos
, sev_asid_bitmap
);
6201 static int sev_guest_init(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6203 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6207 asid
= sev_asid_new();
6211 ret
= sev_platform_init(&argp
->error
);
6217 INIT_LIST_HEAD(&sev
->regions_list
);
6222 __sev_asid_free(asid
);
6226 static int sev_bind_asid(struct kvm
*kvm
, unsigned int handle
, int *error
)
6228 struct sev_data_activate
*data
;
6229 int asid
= sev_get_asid(kvm
);
6232 wbinvd_on_all_cpus();
6234 ret
= sev_guest_df_flush(error
);
6238 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6242 /* activate ASID on the given handle */
6243 data
->handle
= handle
;
6245 ret
= sev_guest_activate(data
, error
);
6251 static int __sev_issue_cmd(int fd
, int id
, void *data
, int *error
)
6260 ret
= sev_issue_cmd_external_user(f
.file
, id
, data
, error
);
6266 static int sev_issue_cmd(struct kvm
*kvm
, int id
, void *data
, int *error
)
6268 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6270 return __sev_issue_cmd(sev
->fd
, id
, data
, error
);
6273 static int sev_launch_start(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6275 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6276 struct sev_data_launch_start
*start
;
6277 struct kvm_sev_launch_start params
;
6278 void *dh_blob
, *session_blob
;
6279 int *error
= &argp
->error
;
6282 if (!sev_guest(kvm
))
6285 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6288 start
= kzalloc(sizeof(*start
), GFP_KERNEL
);
6293 if (params
.dh_uaddr
) {
6294 dh_blob
= psp_copy_user_blob(params
.dh_uaddr
, params
.dh_len
);
6295 if (IS_ERR(dh_blob
)) {
6296 ret
= PTR_ERR(dh_blob
);
6300 start
->dh_cert_address
= __sme_set(__pa(dh_blob
));
6301 start
->dh_cert_len
= params
.dh_len
;
6304 session_blob
= NULL
;
6305 if (params
.session_uaddr
) {
6306 session_blob
= psp_copy_user_blob(params
.session_uaddr
, params
.session_len
);
6307 if (IS_ERR(session_blob
)) {
6308 ret
= PTR_ERR(session_blob
);
6312 start
->session_address
= __sme_set(__pa(session_blob
));
6313 start
->session_len
= params
.session_len
;
6316 start
->handle
= params
.handle
;
6317 start
->policy
= params
.policy
;
6319 /* create memory encryption context */
6320 ret
= __sev_issue_cmd(argp
->sev_fd
, SEV_CMD_LAUNCH_START
, start
, error
);
6322 goto e_free_session
;
6324 /* Bind ASID to this guest */
6325 ret
= sev_bind_asid(kvm
, start
->handle
, error
);
6327 goto e_free_session
;
6329 /* return handle to userspace */
6330 params
.handle
= start
->handle
;
6331 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
))) {
6332 sev_unbind_asid(kvm
, start
->handle
);
6334 goto e_free_session
;
6337 sev
->handle
= start
->handle
;
6338 sev
->fd
= argp
->sev_fd
;
6341 kfree(session_blob
);
6349 static int get_num_contig_pages(int idx
, struct page
**inpages
,
6350 unsigned long npages
)
6352 unsigned long paddr
, next_paddr
;
6353 int i
= idx
+ 1, pages
= 1;
6355 /* find the number of contiguous pages starting from idx */
6356 paddr
= __sme_page_pa(inpages
[idx
]);
6357 while (i
< npages
) {
6358 next_paddr
= __sme_page_pa(inpages
[i
++]);
6359 if ((paddr
+ PAGE_SIZE
) == next_paddr
) {
6370 static int sev_launch_update_data(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6372 unsigned long vaddr
, vaddr_end
, next_vaddr
, npages
, size
;
6373 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6374 struct kvm_sev_launch_update_data params
;
6375 struct sev_data_launch_update_data
*data
;
6376 struct page
**inpages
;
6379 if (!sev_guest(kvm
))
6382 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6385 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6389 vaddr
= params
.uaddr
;
6391 vaddr_end
= vaddr
+ size
;
6393 /* Lock the user memory. */
6394 inpages
= sev_pin_memory(kvm
, vaddr
, size
, &npages
, 1);
6401 * The LAUNCH_UPDATE command will perform in-place encryption of the
6402 * memory content (i.e it will write the same memory region with C=1).
6403 * It's possible that the cache may contain the data with C=0, i.e.,
6404 * unencrypted so invalidate it first.
6406 sev_clflush_pages(inpages
, npages
);
6408 for (i
= 0; vaddr
< vaddr_end
; vaddr
= next_vaddr
, i
+= pages
) {
6412 * If the user buffer is not page-aligned, calculate the offset
6415 offset
= vaddr
& (PAGE_SIZE
- 1);
6417 /* Calculate the number of pages that can be encrypted in one go. */
6418 pages
= get_num_contig_pages(i
, inpages
, npages
);
6420 len
= min_t(size_t, ((pages
* PAGE_SIZE
) - offset
), size
);
6422 data
->handle
= sev
->handle
;
6424 data
->address
= __sme_page_pa(inpages
[i
]) + offset
;
6425 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_DATA
, data
, &argp
->error
);
6430 next_vaddr
= vaddr
+ len
;
6434 /* content of memory is updated, mark pages dirty */
6435 for (i
= 0; i
< npages
; i
++) {
6436 set_page_dirty_lock(inpages
[i
]);
6437 mark_page_accessed(inpages
[i
]);
6439 /* unlock the user pages */
6440 sev_unpin_memory(kvm
, inpages
, npages
);
6446 static int sev_launch_measure(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6448 void __user
*measure
= (void __user
*)(uintptr_t)argp
->data
;
6449 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6450 struct sev_data_launch_measure
*data
;
6451 struct kvm_sev_launch_measure params
;
6452 void __user
*p
= NULL
;
6456 if (!sev_guest(kvm
))
6459 if (copy_from_user(¶ms
, measure
, sizeof(params
)))
6462 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6466 /* User wants to query the blob length */
6470 p
= (void __user
*)(uintptr_t)params
.uaddr
;
6472 if (params
.len
> SEV_FW_BLOB_MAX_SIZE
) {
6478 blob
= kmalloc(params
.len
, GFP_KERNEL
);
6482 data
->address
= __psp_pa(blob
);
6483 data
->len
= params
.len
;
6487 data
->handle
= sev
->handle
;
6488 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_MEASURE
, data
, &argp
->error
);
6491 * If we query the session length, FW responded with expected data.
6500 if (copy_to_user(p
, blob
, params
.len
))
6505 params
.len
= data
->len
;
6506 if (copy_to_user(measure
, ¶ms
, sizeof(params
)))
6515 static int sev_launch_finish(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6517 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6518 struct sev_data_launch_finish
*data
;
6521 if (!sev_guest(kvm
))
6524 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6528 data
->handle
= sev
->handle
;
6529 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_FINISH
, data
, &argp
->error
);
6535 static int sev_guest_status(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6537 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6538 struct kvm_sev_guest_status params
;
6539 struct sev_data_guest_status
*data
;
6542 if (!sev_guest(kvm
))
6545 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6549 data
->handle
= sev
->handle
;
6550 ret
= sev_issue_cmd(kvm
, SEV_CMD_GUEST_STATUS
, data
, &argp
->error
);
6554 params
.policy
= data
->policy
;
6555 params
.state
= data
->state
;
6556 params
.handle
= data
->handle
;
6558 if (copy_to_user((void __user
*)(uintptr_t)argp
->data
, ¶ms
, sizeof(params
)))
6565 static int __sev_issue_dbg_cmd(struct kvm
*kvm
, unsigned long src
,
6566 unsigned long dst
, int size
,
6567 int *error
, bool enc
)
6569 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6570 struct sev_data_dbg
*data
;
6573 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6577 data
->handle
= sev
->handle
;
6578 data
->dst_addr
= dst
;
6579 data
->src_addr
= src
;
6582 ret
= sev_issue_cmd(kvm
,
6583 enc
? SEV_CMD_DBG_ENCRYPT
: SEV_CMD_DBG_DECRYPT
,
6589 static int __sev_dbg_decrypt(struct kvm
*kvm
, unsigned long src_paddr
,
6590 unsigned long dst_paddr
, int sz
, int *err
)
6595 * Its safe to read more than we are asked, caller should ensure that
6596 * destination has enough space.
6598 src_paddr
= round_down(src_paddr
, 16);
6599 offset
= src_paddr
& 15;
6600 sz
= round_up(sz
+ offset
, 16);
6602 return __sev_issue_dbg_cmd(kvm
, src_paddr
, dst_paddr
, sz
, err
, false);
6605 static int __sev_dbg_decrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6606 unsigned long __user dst_uaddr
,
6607 unsigned long dst_paddr
,
6610 struct page
*tpage
= NULL
;
6613 /* if inputs are not 16-byte then use intermediate buffer */
6614 if (!IS_ALIGNED(dst_paddr
, 16) ||
6615 !IS_ALIGNED(paddr
, 16) ||
6616 !IS_ALIGNED(size
, 16)) {
6617 tpage
= (void *)alloc_page(GFP_KERNEL
);
6621 dst_paddr
= __sme_page_pa(tpage
);
6624 ret
= __sev_dbg_decrypt(kvm
, paddr
, dst_paddr
, size
, err
);
6629 offset
= paddr
& 15;
6630 if (copy_to_user((void __user
*)(uintptr_t)dst_uaddr
,
6631 page_address(tpage
) + offset
, size
))
6642 static int __sev_dbg_encrypt_user(struct kvm
*kvm
, unsigned long paddr
,
6643 unsigned long __user vaddr
,
6644 unsigned long dst_paddr
,
6645 unsigned long __user dst_vaddr
,
6646 int size
, int *error
)
6648 struct page
*src_tpage
= NULL
;
6649 struct page
*dst_tpage
= NULL
;
6650 int ret
, len
= size
;
6652 /* If source buffer is not aligned then use an intermediate buffer */
6653 if (!IS_ALIGNED(vaddr
, 16)) {
6654 src_tpage
= alloc_page(GFP_KERNEL
);
6658 if (copy_from_user(page_address(src_tpage
),
6659 (void __user
*)(uintptr_t)vaddr
, size
)) {
6660 __free_page(src_tpage
);
6664 paddr
= __sme_page_pa(src_tpage
);
6668 * If destination buffer or length is not aligned then do read-modify-write:
6669 * - decrypt destination in an intermediate buffer
6670 * - copy the source buffer in an intermediate buffer
6671 * - use the intermediate buffer as source buffer
6673 if (!IS_ALIGNED(dst_vaddr
, 16) || !IS_ALIGNED(size
, 16)) {
6676 dst_tpage
= alloc_page(GFP_KERNEL
);
6682 ret
= __sev_dbg_decrypt(kvm
, dst_paddr
,
6683 __sme_page_pa(dst_tpage
), size
, error
);
6688 * If source is kernel buffer then use memcpy() otherwise
6691 dst_offset
= dst_paddr
& 15;
6694 memcpy(page_address(dst_tpage
) + dst_offset
,
6695 page_address(src_tpage
), size
);
6697 if (copy_from_user(page_address(dst_tpage
) + dst_offset
,
6698 (void __user
*)(uintptr_t)vaddr
, size
)) {
6704 paddr
= __sme_page_pa(dst_tpage
);
6705 dst_paddr
= round_down(dst_paddr
, 16);
6706 len
= round_up(size
, 16);
6709 ret
= __sev_issue_dbg_cmd(kvm
, paddr
, dst_paddr
, len
, error
, true);
6713 __free_page(src_tpage
);
6715 __free_page(dst_tpage
);
6719 static int sev_dbg_crypt(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
, bool dec
)
6721 unsigned long vaddr
, vaddr_end
, next_vaddr
;
6722 unsigned long dst_vaddr
, dst_vaddr_end
;
6723 struct page
**src_p
, **dst_p
;
6724 struct kvm_sev_dbg debug
;
6728 if (!sev_guest(kvm
))
6731 if (copy_from_user(&debug
, (void __user
*)(uintptr_t)argp
->data
, sizeof(debug
)))
6734 vaddr
= debug
.src_uaddr
;
6736 vaddr_end
= vaddr
+ size
;
6737 dst_vaddr
= debug
.dst_uaddr
;
6738 dst_vaddr_end
= dst_vaddr
+ size
;
6740 for (; vaddr
< vaddr_end
; vaddr
= next_vaddr
) {
6741 int len
, s_off
, d_off
;
6743 /* lock userspace source and destination page */
6744 src_p
= sev_pin_memory(kvm
, vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 0);
6748 dst_p
= sev_pin_memory(kvm
, dst_vaddr
& PAGE_MASK
, PAGE_SIZE
, &n
, 1);
6750 sev_unpin_memory(kvm
, src_p
, n
);
6755 * The DBG_{DE,EN}CRYPT commands will perform {dec,en}cryption of the
6756 * memory content (i.e it will write the same memory region with C=1).
6757 * It's possible that the cache may contain the data with C=0, i.e.,
6758 * unencrypted so invalidate it first.
6760 sev_clflush_pages(src_p
, 1);
6761 sev_clflush_pages(dst_p
, 1);
6764 * Since user buffer may not be page aligned, calculate the
6765 * offset within the page.
6767 s_off
= vaddr
& ~PAGE_MASK
;
6768 d_off
= dst_vaddr
& ~PAGE_MASK
;
6769 len
= min_t(size_t, (PAGE_SIZE
- s_off
), size
);
6772 ret
= __sev_dbg_decrypt_user(kvm
,
6773 __sme_page_pa(src_p
[0]) + s_off
,
6775 __sme_page_pa(dst_p
[0]) + d_off
,
6778 ret
= __sev_dbg_encrypt_user(kvm
,
6779 __sme_page_pa(src_p
[0]) + s_off
,
6781 __sme_page_pa(dst_p
[0]) + d_off
,
6785 sev_unpin_memory(kvm
, src_p
, 1);
6786 sev_unpin_memory(kvm
, dst_p
, 1);
6791 next_vaddr
= vaddr
+ len
;
6792 dst_vaddr
= dst_vaddr
+ len
;
6799 static int sev_launch_secret(struct kvm
*kvm
, struct kvm_sev_cmd
*argp
)
6801 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6802 struct sev_data_launch_secret
*data
;
6803 struct kvm_sev_launch_secret params
;
6804 struct page
**pages
;
6809 if (!sev_guest(kvm
))
6812 if (copy_from_user(¶ms
, (void __user
*)(uintptr_t)argp
->data
, sizeof(params
)))
6815 pages
= sev_pin_memory(kvm
, params
.guest_uaddr
, params
.guest_len
, &n
, 1);
6820 * The secret must be copied into contiguous memory region, lets verify
6821 * that userspace memory pages are contiguous before we issue command.
6823 if (get_num_contig_pages(0, pages
, n
) != n
) {
6825 goto e_unpin_memory
;
6829 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
6831 goto e_unpin_memory
;
6833 offset
= params
.guest_uaddr
& (PAGE_SIZE
- 1);
6834 data
->guest_address
= __sme_page_pa(pages
[0]) + offset
;
6835 data
->guest_len
= params
.guest_len
;
6837 blob
= psp_copy_user_blob(params
.trans_uaddr
, params
.trans_len
);
6839 ret
= PTR_ERR(blob
);
6843 data
->trans_address
= __psp_pa(blob
);
6844 data
->trans_len
= params
.trans_len
;
6846 hdr
= psp_copy_user_blob(params
.hdr_uaddr
, params
.hdr_len
);
6851 data
->hdr_address
= __psp_pa(hdr
);
6852 data
->hdr_len
= params
.hdr_len
;
6854 data
->handle
= sev
->handle
;
6855 ret
= sev_issue_cmd(kvm
, SEV_CMD_LAUNCH_UPDATE_SECRET
, data
, &argp
->error
);
6864 sev_unpin_memory(kvm
, pages
, n
);
6868 static int svm_mem_enc_op(struct kvm
*kvm
, void __user
*argp
)
6870 struct kvm_sev_cmd sev_cmd
;
6873 if (!svm_sev_enabled())
6876 if (copy_from_user(&sev_cmd
, argp
, sizeof(struct kvm_sev_cmd
)))
6879 mutex_lock(&kvm
->lock
);
6881 switch (sev_cmd
.id
) {
6883 r
= sev_guest_init(kvm
, &sev_cmd
);
6885 case KVM_SEV_LAUNCH_START
:
6886 r
= sev_launch_start(kvm
, &sev_cmd
);
6888 case KVM_SEV_LAUNCH_UPDATE_DATA
:
6889 r
= sev_launch_update_data(kvm
, &sev_cmd
);
6891 case KVM_SEV_LAUNCH_MEASURE
:
6892 r
= sev_launch_measure(kvm
, &sev_cmd
);
6894 case KVM_SEV_LAUNCH_FINISH
:
6895 r
= sev_launch_finish(kvm
, &sev_cmd
);
6897 case KVM_SEV_GUEST_STATUS
:
6898 r
= sev_guest_status(kvm
, &sev_cmd
);
6900 case KVM_SEV_DBG_DECRYPT
:
6901 r
= sev_dbg_crypt(kvm
, &sev_cmd
, true);
6903 case KVM_SEV_DBG_ENCRYPT
:
6904 r
= sev_dbg_crypt(kvm
, &sev_cmd
, false);
6906 case KVM_SEV_LAUNCH_SECRET
:
6907 r
= sev_launch_secret(kvm
, &sev_cmd
);
6914 if (copy_to_user(argp
, &sev_cmd
, sizeof(struct kvm_sev_cmd
)))
6918 mutex_unlock(&kvm
->lock
);
6922 static int svm_register_enc_region(struct kvm
*kvm
,
6923 struct kvm_enc_region
*range
)
6925 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6926 struct enc_region
*region
;
6929 if (!sev_guest(kvm
))
6932 region
= kzalloc(sizeof(*region
), GFP_KERNEL
);
6936 region
->pages
= sev_pin_memory(kvm
, range
->addr
, range
->size
, ®ion
->npages
, 1);
6937 if (!region
->pages
) {
6943 * The guest may change the memory encryption attribute from C=0 -> C=1
6944 * or vice versa for this memory range. Lets make sure caches are
6945 * flushed to ensure that guest data gets written into memory with
6948 sev_clflush_pages(region
->pages
, region
->npages
);
6950 region
->uaddr
= range
->addr
;
6951 region
->size
= range
->size
;
6953 mutex_lock(&kvm
->lock
);
6954 list_add_tail(®ion
->list
, &sev
->regions_list
);
6955 mutex_unlock(&kvm
->lock
);
6964 static struct enc_region
*
6965 find_enc_region(struct kvm
*kvm
, struct kvm_enc_region
*range
)
6967 struct kvm_sev_info
*sev
= &to_kvm_svm(kvm
)->sev_info
;
6968 struct list_head
*head
= &sev
->regions_list
;
6969 struct enc_region
*i
;
6971 list_for_each_entry(i
, head
, list
) {
6972 if (i
->uaddr
== range
->addr
&&
6973 i
->size
== range
->size
)
6981 static int svm_unregister_enc_region(struct kvm
*kvm
,
6982 struct kvm_enc_region
*range
)
6984 struct enc_region
*region
;
6987 mutex_lock(&kvm
->lock
);
6989 if (!sev_guest(kvm
)) {
6994 region
= find_enc_region(kvm
, range
);
7000 __unregister_enc_region_locked(kvm
, region
);
7002 mutex_unlock(&kvm
->lock
);
7006 mutex_unlock(&kvm
->lock
);
7010 static struct kvm_x86_ops svm_x86_ops __ro_after_init
= {
7011 .cpu_has_kvm_support
= has_svm
,
7012 .disabled_by_bios
= is_disabled
,
7013 .hardware_setup
= svm_hardware_setup
,
7014 .hardware_unsetup
= svm_hardware_unsetup
,
7015 .check_processor_compatibility
= svm_check_processor_compat
,
7016 .hardware_enable
= svm_hardware_enable
,
7017 .hardware_disable
= svm_hardware_disable
,
7018 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
7019 .cpu_has_high_real_mode_segbase
= svm_has_high_real_mode_segbase
,
7021 .vcpu_create
= svm_create_vcpu
,
7022 .vcpu_free
= svm_free_vcpu
,
7023 .vcpu_reset
= svm_vcpu_reset
,
7025 .vm_alloc
= svm_vm_alloc
,
7026 .vm_free
= svm_vm_free
,
7027 .vm_init
= avic_vm_init
,
7028 .vm_destroy
= svm_vm_destroy
,
7030 .prepare_guest_switch
= svm_prepare_guest_switch
,
7031 .vcpu_load
= svm_vcpu_load
,
7032 .vcpu_put
= svm_vcpu_put
,
7033 .vcpu_blocking
= svm_vcpu_blocking
,
7034 .vcpu_unblocking
= svm_vcpu_unblocking
,
7036 .update_bp_intercept
= update_bp_intercept
,
7037 .get_msr_feature
= svm_get_msr_feature
,
7038 .get_msr
= svm_get_msr
,
7039 .set_msr
= svm_set_msr
,
7040 .get_segment_base
= svm_get_segment_base
,
7041 .get_segment
= svm_get_segment
,
7042 .set_segment
= svm_set_segment
,
7043 .get_cpl
= svm_get_cpl
,
7044 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
7045 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
7046 .decache_cr3
= svm_decache_cr3
,
7047 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
7048 .set_cr0
= svm_set_cr0
,
7049 .set_cr3
= svm_set_cr3
,
7050 .set_cr4
= svm_set_cr4
,
7051 .set_efer
= svm_set_efer
,
7052 .get_idt
= svm_get_idt
,
7053 .set_idt
= svm_set_idt
,
7054 .get_gdt
= svm_get_gdt
,
7055 .set_gdt
= svm_set_gdt
,
7056 .get_dr6
= svm_get_dr6
,
7057 .set_dr6
= svm_set_dr6
,
7058 .set_dr7
= svm_set_dr7
,
7059 .sync_dirty_debug_regs
= svm_sync_dirty_debug_regs
,
7060 .cache_reg
= svm_cache_reg
,
7061 .get_rflags
= svm_get_rflags
,
7062 .set_rflags
= svm_set_rflags
,
7064 .tlb_flush
= svm_flush_tlb
,
7066 .run
= svm_vcpu_run
,
7067 .handle_exit
= handle_exit
,
7068 .skip_emulated_instruction
= skip_emulated_instruction
,
7069 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
7070 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
7071 .patch_hypercall
= svm_patch_hypercall
,
7072 .set_irq
= svm_set_irq
,
7073 .set_nmi
= svm_inject_nmi
,
7074 .queue_exception
= svm_queue_exception
,
7075 .cancel_injection
= svm_cancel_injection
,
7076 .interrupt_allowed
= svm_interrupt_allowed
,
7077 .nmi_allowed
= svm_nmi_allowed
,
7078 .get_nmi_mask
= svm_get_nmi_mask
,
7079 .set_nmi_mask
= svm_set_nmi_mask
,
7080 .enable_nmi_window
= enable_nmi_window
,
7081 .enable_irq_window
= enable_irq_window
,
7082 .update_cr8_intercept
= update_cr8_intercept
,
7083 .set_virtual_x2apic_mode
= svm_set_virtual_x2apic_mode
,
7084 .get_enable_apicv
= svm_get_enable_apicv
,
7085 .refresh_apicv_exec_ctrl
= svm_refresh_apicv_exec_ctrl
,
7086 .load_eoi_exitmap
= svm_load_eoi_exitmap
,
7087 .hwapic_irr_update
= svm_hwapic_irr_update
,
7088 .hwapic_isr_update
= svm_hwapic_isr_update
,
7089 .sync_pir_to_irr
= kvm_lapic_find_highest_irr
,
7090 .apicv_post_state_restore
= avic_post_state_restore
,
7092 .set_tss_addr
= svm_set_tss_addr
,
7093 .set_identity_map_addr
= svm_set_identity_map_addr
,
7094 .get_tdp_level
= get_npt_level
,
7095 .get_mt_mask
= svm_get_mt_mask
,
7097 .get_exit_info
= svm_get_exit_info
,
7099 .get_lpage_level
= svm_get_lpage_level
,
7101 .cpuid_update
= svm_cpuid_update
,
7103 .rdtscp_supported
= svm_rdtscp_supported
,
7104 .invpcid_supported
= svm_invpcid_supported
,
7105 .mpx_supported
= svm_mpx_supported
,
7106 .xsaves_supported
= svm_xsaves_supported
,
7107 .umip_emulated
= svm_umip_emulated
,
7109 .set_supported_cpuid
= svm_set_supported_cpuid
,
7111 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
7113 .write_tsc_offset
= svm_write_tsc_offset
,
7115 .set_tdp_cr3
= set_tdp_cr3
,
7117 .check_intercept
= svm_check_intercept
,
7118 .handle_external_intr
= svm_handle_external_intr
,
7120 .sched_in
= svm_sched_in
,
7122 .pmu_ops
= &amd_pmu_ops
,
7123 .deliver_posted_interrupt
= svm_deliver_avic_intr
,
7124 .update_pi_irte
= svm_update_pi_irte
,
7125 .setup_mce
= svm_setup_mce
,
7127 .smi_allowed
= svm_smi_allowed
,
7128 .pre_enter_smm
= svm_pre_enter_smm
,
7129 .pre_leave_smm
= svm_pre_leave_smm
,
7130 .enable_smi_window
= enable_smi_window
,
7132 .mem_enc_op
= svm_mem_enc_op
,
7133 .mem_enc_reg_region
= svm_register_enc_region
,
7134 .mem_enc_unreg_region
= svm_unregister_enc_region
,
7137 static int __init
svm_init(void)
7139 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
7140 __alignof__(struct vcpu_svm
), THIS_MODULE
);
7143 static void __exit
svm_exit(void)
7148 module_init(svm_init
)
7149 module_exit(svm_exit
)