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KVM: async_pf: Add L1 guest async_pf #PF vmexit handler
[mirror_ubuntu-jammy-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48
49 #include <asm/virtext.h>
50 #include "trace.h"
51
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53
54 MODULE_AUTHOR("Qumranet");
55 MODULE_LICENSE("GPL");
56
57 static const struct x86_cpu_id svm_cpu_id[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_SVM),
59 {}
60 };
61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62
63 #define IOPM_ALLOC_ORDER 2
64 #define MSRPM_ALLOC_ORDER 1
65
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
68
69 #define SVM_FEATURE_NPT (1 << 0)
70 #define SVM_FEATURE_LBRV (1 << 1)
71 #define SVM_FEATURE_SVML (1 << 2)
72 #define SVM_FEATURE_NRIP (1 << 3)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78
79 #define SVM_AVIC_DOORBELL 0xc001011b
80
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
92
93 /*
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
96 */
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115
116 static bool erratum_383_found __read_mostly;
117
118 static const u32 host_save_user_msrs[] = {
119 #ifdef CONFIG_X86_64
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
121 MSR_FS_BASE,
122 #endif
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
124 MSR_TSC_AUX,
125 };
126
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
128
129 struct kvm_vcpu;
130
131 struct nested_state {
132 struct vmcb *hsave;
133 u64 hsave_msr;
134 u64 vm_cr_msr;
135 u64 vmcb;
136
137 /* These are the merged vectors */
138 u32 *msrpm;
139
140 /* gpa pointers to the real vectors */
141 u64 vmcb_msrpm;
142 u64 vmcb_iopm;
143
144 /* A VMEXIT is required but not yet emulated */
145 bool exit_required;
146
147 /* cache for intercepts of the guest */
148 u32 intercept_cr;
149 u32 intercept_dr;
150 u32 intercept_exceptions;
151 u64 intercept;
152
153 /* Nested Paging related state */
154 u64 nested_cr3;
155 };
156
157 #define MSRPM_OFFSETS 16
158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
159
160 /*
161 * Set osvw_len to higher value when updated Revision Guides
162 * are published and we know what the new status bits are
163 */
164 static uint64_t osvw_len = 4, osvw_status;
165
166 struct vcpu_svm {
167 struct kvm_vcpu vcpu;
168 struct vmcb *vmcb;
169 unsigned long vmcb_pa;
170 struct svm_cpu_data *svm_data;
171 uint64_t asid_generation;
172 uint64_t sysenter_esp;
173 uint64_t sysenter_eip;
174 uint64_t tsc_aux;
175
176 u64 next_rip;
177
178 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
179 struct {
180 u16 fs;
181 u16 gs;
182 u16 ldt;
183 u64 gs_base;
184 } host;
185
186 u32 *msrpm;
187
188 ulong nmi_iret_rip;
189
190 struct nested_state nested;
191
192 bool nmi_singlestep;
193 u64 nmi_singlestep_guest_rflags;
194
195 unsigned int3_injected;
196 unsigned long int3_rip;
197
198 /* cached guest cpuid flags for faster access */
199 bool nrips_enabled : 1;
200
201 u32 ldr_reg;
202 struct page *avic_backing_page;
203 u64 *avic_physical_id_cache;
204 bool avic_is_running;
205
206 /*
207 * Per-vcpu list of struct amd_svm_iommu_ir:
208 * This is used mainly to store interrupt remapping information used
209 * when update the vcpu affinity. This avoids the need to scan for
210 * IRTE and try to match ga_tag in the IOMMU driver.
211 */
212 struct list_head ir_list;
213 spinlock_t ir_list_lock;
214 };
215
216 /*
217 * This is a wrapper of struct amd_iommu_ir_data.
218 */
219 struct amd_svm_iommu_ir {
220 struct list_head node; /* Used by SVM for per-vcpu ir_list */
221 void *data; /* Storing pointer to struct amd_ir_data */
222 };
223
224 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
225 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226
227 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
228 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
229 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
230 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231
232 static DEFINE_PER_CPU(u64, current_tsc_ratio);
233 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234
235 #define MSR_INVALID 0xffffffffU
236
237 static const struct svm_direct_access_msrs {
238 u32 index; /* Index of the MSR */
239 bool always; /* True if intercept is always on */
240 } direct_access_msrs[] = {
241 { .index = MSR_STAR, .always = true },
242 { .index = MSR_IA32_SYSENTER_CS, .always = true },
243 #ifdef CONFIG_X86_64
244 { .index = MSR_GS_BASE, .always = true },
245 { .index = MSR_FS_BASE, .always = true },
246 { .index = MSR_KERNEL_GS_BASE, .always = true },
247 { .index = MSR_LSTAR, .always = true },
248 { .index = MSR_CSTAR, .always = true },
249 { .index = MSR_SYSCALL_MASK, .always = true },
250 #endif
251 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
252 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
253 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
254 { .index = MSR_IA32_LASTINTTOIP, .always = false },
255 { .index = MSR_INVALID, .always = false },
256 };
257
258 /* enable NPT for AMD64 and X86 with PAE */
259 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
260 static bool npt_enabled = true;
261 #else
262 static bool npt_enabled;
263 #endif
264
265 /* allow nested paging (virtualized MMU) for all guests */
266 static int npt = true;
267 module_param(npt, int, S_IRUGO);
268
269 /* allow nested virtualization in KVM/SVM */
270 static int nested = true;
271 module_param(nested, int, S_IRUGO);
272
273 /* enable / disable AVIC */
274 static int avic;
275 #ifdef CONFIG_X86_LOCAL_APIC
276 module_param(avic, int, S_IRUGO);
277 #endif
278
279 /* enable/disable Virtual VMLOAD VMSAVE */
280 static int vls = true;
281 module_param(vls, int, 0444);
282
283 /* AVIC VM ID bit masks and lock */
284 static DECLARE_BITMAP(avic_vm_id_bitmap, AVIC_VM_ID_NR);
285 static DEFINE_SPINLOCK(avic_vm_id_lock);
286
287 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
288 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
289 static void svm_complete_interrupts(struct vcpu_svm *svm);
290
291 static int nested_svm_exit_handled(struct vcpu_svm *svm);
292 static int nested_svm_intercept(struct vcpu_svm *svm);
293 static int nested_svm_vmexit(struct vcpu_svm *svm);
294 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
295 bool has_error_code, u32 error_code);
296
297 enum {
298 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
299 pause filter count */
300 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
301 VMCB_ASID, /* ASID */
302 VMCB_INTR, /* int_ctl, int_vector */
303 VMCB_NPT, /* npt_en, nCR3, gPAT */
304 VMCB_CR, /* CR0, CR3, CR4, EFER */
305 VMCB_DR, /* DR6, DR7 */
306 VMCB_DT, /* GDT, IDT */
307 VMCB_SEG, /* CS, DS, SS, ES, CPL */
308 VMCB_CR2, /* CR2 only */
309 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
310 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
311 * AVIC PHYSICAL_TABLE pointer,
312 * AVIC LOGICAL_TABLE pointer
313 */
314 VMCB_DIRTY_MAX,
315 };
316
317 /* TPR and CR2 are always written before VMRUN */
318 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
319
320 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
321
322 static inline void mark_all_dirty(struct vmcb *vmcb)
323 {
324 vmcb->control.clean = 0;
325 }
326
327 static inline void mark_all_clean(struct vmcb *vmcb)
328 {
329 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
330 & ~VMCB_ALWAYS_DIRTY_MASK;
331 }
332
333 static inline void mark_dirty(struct vmcb *vmcb, int bit)
334 {
335 vmcb->control.clean &= ~(1 << bit);
336 }
337
338 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
339 {
340 return container_of(vcpu, struct vcpu_svm, vcpu);
341 }
342
343 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
344 {
345 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
346 mark_dirty(svm->vmcb, VMCB_AVIC);
347 }
348
349 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
350 {
351 struct vcpu_svm *svm = to_svm(vcpu);
352 u64 *entry = svm->avic_physical_id_cache;
353
354 if (!entry)
355 return false;
356
357 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
358 }
359
360 static void recalc_intercepts(struct vcpu_svm *svm)
361 {
362 struct vmcb_control_area *c, *h;
363 struct nested_state *g;
364
365 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
366
367 if (!is_guest_mode(&svm->vcpu))
368 return;
369
370 c = &svm->vmcb->control;
371 h = &svm->nested.hsave->control;
372 g = &svm->nested;
373
374 c->intercept_cr = h->intercept_cr | g->intercept_cr;
375 c->intercept_dr = h->intercept_dr | g->intercept_dr;
376 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
377 c->intercept = h->intercept | g->intercept;
378 }
379
380 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
381 {
382 if (is_guest_mode(&svm->vcpu))
383 return svm->nested.hsave;
384 else
385 return svm->vmcb;
386 }
387
388 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
389 {
390 struct vmcb *vmcb = get_host_vmcb(svm);
391
392 vmcb->control.intercept_cr |= (1U << bit);
393
394 recalc_intercepts(svm);
395 }
396
397 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
398 {
399 struct vmcb *vmcb = get_host_vmcb(svm);
400
401 vmcb->control.intercept_cr &= ~(1U << bit);
402
403 recalc_intercepts(svm);
404 }
405
406 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
407 {
408 struct vmcb *vmcb = get_host_vmcb(svm);
409
410 return vmcb->control.intercept_cr & (1U << bit);
411 }
412
413 static inline void set_dr_intercepts(struct vcpu_svm *svm)
414 {
415 struct vmcb *vmcb = get_host_vmcb(svm);
416
417 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
418 | (1 << INTERCEPT_DR1_READ)
419 | (1 << INTERCEPT_DR2_READ)
420 | (1 << INTERCEPT_DR3_READ)
421 | (1 << INTERCEPT_DR4_READ)
422 | (1 << INTERCEPT_DR5_READ)
423 | (1 << INTERCEPT_DR6_READ)
424 | (1 << INTERCEPT_DR7_READ)
425 | (1 << INTERCEPT_DR0_WRITE)
426 | (1 << INTERCEPT_DR1_WRITE)
427 | (1 << INTERCEPT_DR2_WRITE)
428 | (1 << INTERCEPT_DR3_WRITE)
429 | (1 << INTERCEPT_DR4_WRITE)
430 | (1 << INTERCEPT_DR5_WRITE)
431 | (1 << INTERCEPT_DR6_WRITE)
432 | (1 << INTERCEPT_DR7_WRITE);
433
434 recalc_intercepts(svm);
435 }
436
437 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
438 {
439 struct vmcb *vmcb = get_host_vmcb(svm);
440
441 vmcb->control.intercept_dr = 0;
442
443 recalc_intercepts(svm);
444 }
445
446 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
447 {
448 struct vmcb *vmcb = get_host_vmcb(svm);
449
450 vmcb->control.intercept_exceptions |= (1U << bit);
451
452 recalc_intercepts(svm);
453 }
454
455 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
456 {
457 struct vmcb *vmcb = get_host_vmcb(svm);
458
459 vmcb->control.intercept_exceptions &= ~(1U << bit);
460
461 recalc_intercepts(svm);
462 }
463
464 static inline void set_intercept(struct vcpu_svm *svm, int bit)
465 {
466 struct vmcb *vmcb = get_host_vmcb(svm);
467
468 vmcb->control.intercept |= (1ULL << bit);
469
470 recalc_intercepts(svm);
471 }
472
473 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
474 {
475 struct vmcb *vmcb = get_host_vmcb(svm);
476
477 vmcb->control.intercept &= ~(1ULL << bit);
478
479 recalc_intercepts(svm);
480 }
481
482 static inline void enable_gif(struct vcpu_svm *svm)
483 {
484 svm->vcpu.arch.hflags |= HF_GIF_MASK;
485 }
486
487 static inline void disable_gif(struct vcpu_svm *svm)
488 {
489 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
490 }
491
492 static inline bool gif_set(struct vcpu_svm *svm)
493 {
494 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
495 }
496
497 static unsigned long iopm_base;
498
499 struct kvm_ldttss_desc {
500 u16 limit0;
501 u16 base0;
502 unsigned base1:8, type:5, dpl:2, p:1;
503 unsigned limit1:4, zero0:3, g:1, base2:8;
504 u32 base3;
505 u32 zero1;
506 } __attribute__((packed));
507
508 struct svm_cpu_data {
509 int cpu;
510
511 u64 asid_generation;
512 u32 max_asid;
513 u32 next_asid;
514 struct kvm_ldttss_desc *tss_desc;
515
516 struct page *save_area;
517 };
518
519 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
520
521 struct svm_init_data {
522 int cpu;
523 int r;
524 };
525
526 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
527
528 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
529 #define MSRS_RANGE_SIZE 2048
530 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
531
532 static u32 svm_msrpm_offset(u32 msr)
533 {
534 u32 offset;
535 int i;
536
537 for (i = 0; i < NUM_MSR_MAPS; i++) {
538 if (msr < msrpm_ranges[i] ||
539 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
540 continue;
541
542 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
543 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
544
545 /* Now we have the u8 offset - but need the u32 offset */
546 return offset / 4;
547 }
548
549 /* MSR not in any range */
550 return MSR_INVALID;
551 }
552
553 #define MAX_INST_SIZE 15
554
555 static inline void clgi(void)
556 {
557 asm volatile (__ex(SVM_CLGI));
558 }
559
560 static inline void stgi(void)
561 {
562 asm volatile (__ex(SVM_STGI));
563 }
564
565 static inline void invlpga(unsigned long addr, u32 asid)
566 {
567 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
568 }
569
570 static int get_npt_level(void)
571 {
572 #ifdef CONFIG_X86_64
573 return PT64_ROOT_LEVEL;
574 #else
575 return PT32E_ROOT_LEVEL;
576 #endif
577 }
578
579 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
580 {
581 vcpu->arch.efer = efer;
582 if (!npt_enabled && !(efer & EFER_LMA))
583 efer &= ~EFER_LME;
584
585 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
586 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
587 }
588
589 static int is_external_interrupt(u32 info)
590 {
591 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
592 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
593 }
594
595 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
596 {
597 struct vcpu_svm *svm = to_svm(vcpu);
598 u32 ret = 0;
599
600 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
601 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
602 return ret;
603 }
604
605 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
606 {
607 struct vcpu_svm *svm = to_svm(vcpu);
608
609 if (mask == 0)
610 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
611 else
612 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
613
614 }
615
616 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
617 {
618 struct vcpu_svm *svm = to_svm(vcpu);
619
620 if (svm->vmcb->control.next_rip != 0) {
621 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
622 svm->next_rip = svm->vmcb->control.next_rip;
623 }
624
625 if (!svm->next_rip) {
626 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
627 EMULATE_DONE)
628 printk(KERN_DEBUG "%s: NOP\n", __func__);
629 return;
630 }
631 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
632 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
633 __func__, kvm_rip_read(vcpu), svm->next_rip);
634
635 kvm_rip_write(vcpu, svm->next_rip);
636 svm_set_interrupt_shadow(vcpu, 0);
637 }
638
639 static void svm_queue_exception(struct kvm_vcpu *vcpu)
640 {
641 struct vcpu_svm *svm = to_svm(vcpu);
642 unsigned nr = vcpu->arch.exception.nr;
643 bool has_error_code = vcpu->arch.exception.has_error_code;
644 bool reinject = vcpu->arch.exception.reinject;
645 u32 error_code = vcpu->arch.exception.error_code;
646
647 /*
648 * If we are within a nested VM we'd better #VMEXIT and let the guest
649 * handle the exception
650 */
651 if (!reinject &&
652 nested_svm_check_exception(svm, nr, has_error_code, error_code))
653 return;
654
655 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
656 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
657
658 /*
659 * For guest debugging where we have to reinject #BP if some
660 * INT3 is guest-owned:
661 * Emulate nRIP by moving RIP forward. Will fail if injection
662 * raises a fault that is not intercepted. Still better than
663 * failing in all cases.
664 */
665 skip_emulated_instruction(&svm->vcpu);
666 rip = kvm_rip_read(&svm->vcpu);
667 svm->int3_rip = rip + svm->vmcb->save.cs.base;
668 svm->int3_injected = rip - old_rip;
669 }
670
671 svm->vmcb->control.event_inj = nr
672 | SVM_EVTINJ_VALID
673 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
674 | SVM_EVTINJ_TYPE_EXEPT;
675 svm->vmcb->control.event_inj_err = error_code;
676 }
677
678 static void svm_init_erratum_383(void)
679 {
680 u32 low, high;
681 int err;
682 u64 val;
683
684 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
685 return;
686
687 /* Use _safe variants to not break nested virtualization */
688 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
689 if (err)
690 return;
691
692 val |= (1ULL << 47);
693
694 low = lower_32_bits(val);
695 high = upper_32_bits(val);
696
697 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
698
699 erratum_383_found = true;
700 }
701
702 static void svm_init_osvw(struct kvm_vcpu *vcpu)
703 {
704 /*
705 * Guests should see errata 400 and 415 as fixed (assuming that
706 * HLT and IO instructions are intercepted).
707 */
708 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
709 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
710
711 /*
712 * By increasing VCPU's osvw.length to 3 we are telling the guest that
713 * all osvw.status bits inside that length, including bit 0 (which is
714 * reserved for erratum 298), are valid. However, if host processor's
715 * osvw_len is 0 then osvw_status[0] carries no information. We need to
716 * be conservative here and therefore we tell the guest that erratum 298
717 * is present (because we really don't know).
718 */
719 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
720 vcpu->arch.osvw.status |= 1;
721 }
722
723 static int has_svm(void)
724 {
725 const char *msg;
726
727 if (!cpu_has_svm(&msg)) {
728 printk(KERN_INFO "has_svm: %s\n", msg);
729 return 0;
730 }
731
732 return 1;
733 }
734
735 static void svm_hardware_disable(void)
736 {
737 /* Make sure we clean up behind us */
738 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
739 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
740
741 cpu_svm_disable();
742
743 amd_pmu_disable_virt();
744 }
745
746 static int svm_hardware_enable(void)
747 {
748
749 struct svm_cpu_data *sd;
750 uint64_t efer;
751 struct desc_struct *gdt;
752 int me = raw_smp_processor_id();
753
754 rdmsrl(MSR_EFER, efer);
755 if (efer & EFER_SVME)
756 return -EBUSY;
757
758 if (!has_svm()) {
759 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
760 return -EINVAL;
761 }
762 sd = per_cpu(svm_data, me);
763 if (!sd) {
764 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
765 return -EINVAL;
766 }
767
768 sd->asid_generation = 1;
769 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
770 sd->next_asid = sd->max_asid + 1;
771
772 gdt = get_current_gdt_rw();
773 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
774
775 wrmsrl(MSR_EFER, efer | EFER_SVME);
776
777 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
778
779 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
780 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
781 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
782 }
783
784
785 /*
786 * Get OSVW bits.
787 *
788 * Note that it is possible to have a system with mixed processor
789 * revisions and therefore different OSVW bits. If bits are not the same
790 * on different processors then choose the worst case (i.e. if erratum
791 * is present on one processor and not on another then assume that the
792 * erratum is present everywhere).
793 */
794 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
795 uint64_t len, status = 0;
796 int err;
797
798 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
799 if (!err)
800 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
801 &err);
802
803 if (err)
804 osvw_status = osvw_len = 0;
805 else {
806 if (len < osvw_len)
807 osvw_len = len;
808 osvw_status |= status;
809 osvw_status &= (1ULL << osvw_len) - 1;
810 }
811 } else
812 osvw_status = osvw_len = 0;
813
814 svm_init_erratum_383();
815
816 amd_pmu_enable_virt();
817
818 return 0;
819 }
820
821 static void svm_cpu_uninit(int cpu)
822 {
823 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
824
825 if (!sd)
826 return;
827
828 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
829 __free_page(sd->save_area);
830 kfree(sd);
831 }
832
833 static int svm_cpu_init(int cpu)
834 {
835 struct svm_cpu_data *sd;
836 int r;
837
838 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
839 if (!sd)
840 return -ENOMEM;
841 sd->cpu = cpu;
842 sd->save_area = alloc_page(GFP_KERNEL);
843 r = -ENOMEM;
844 if (!sd->save_area)
845 goto err_1;
846
847 per_cpu(svm_data, cpu) = sd;
848
849 return 0;
850
851 err_1:
852 kfree(sd);
853 return r;
854
855 }
856
857 static bool valid_msr_intercept(u32 index)
858 {
859 int i;
860
861 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
862 if (direct_access_msrs[i].index == index)
863 return true;
864
865 return false;
866 }
867
868 static void set_msr_interception(u32 *msrpm, unsigned msr,
869 int read, int write)
870 {
871 u8 bit_read, bit_write;
872 unsigned long tmp;
873 u32 offset;
874
875 /*
876 * If this warning triggers extend the direct_access_msrs list at the
877 * beginning of the file
878 */
879 WARN_ON(!valid_msr_intercept(msr));
880
881 offset = svm_msrpm_offset(msr);
882 bit_read = 2 * (msr & 0x0f);
883 bit_write = 2 * (msr & 0x0f) + 1;
884 tmp = msrpm[offset];
885
886 BUG_ON(offset == MSR_INVALID);
887
888 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
889 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
890
891 msrpm[offset] = tmp;
892 }
893
894 static void svm_vcpu_init_msrpm(u32 *msrpm)
895 {
896 int i;
897
898 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
899
900 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
901 if (!direct_access_msrs[i].always)
902 continue;
903
904 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
905 }
906 }
907
908 static void add_msr_offset(u32 offset)
909 {
910 int i;
911
912 for (i = 0; i < MSRPM_OFFSETS; ++i) {
913
914 /* Offset already in list? */
915 if (msrpm_offsets[i] == offset)
916 return;
917
918 /* Slot used by another offset? */
919 if (msrpm_offsets[i] != MSR_INVALID)
920 continue;
921
922 /* Add offset to list */
923 msrpm_offsets[i] = offset;
924
925 return;
926 }
927
928 /*
929 * If this BUG triggers the msrpm_offsets table has an overflow. Just
930 * increase MSRPM_OFFSETS in this case.
931 */
932 BUG();
933 }
934
935 static void init_msrpm_offsets(void)
936 {
937 int i;
938
939 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
940
941 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
942 u32 offset;
943
944 offset = svm_msrpm_offset(direct_access_msrs[i].index);
945 BUG_ON(offset == MSR_INVALID);
946
947 add_msr_offset(offset);
948 }
949 }
950
951 static void svm_enable_lbrv(struct vcpu_svm *svm)
952 {
953 u32 *msrpm = svm->msrpm;
954
955 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
956 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
957 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
958 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
959 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
960 }
961
962 static void svm_disable_lbrv(struct vcpu_svm *svm)
963 {
964 u32 *msrpm = svm->msrpm;
965
966 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
967 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
968 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
969 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
970 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
971 }
972
973 static void disable_nmi_singlestep(struct vcpu_svm *svm)
974 {
975 svm->nmi_singlestep = false;
976 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
977 /* Clear our flags if they were not set by the guest */
978 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
979 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
980 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
981 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
982 }
983 }
984
985 /* Note:
986 * This hash table is used to map VM_ID to a struct kvm_arch,
987 * when handling AMD IOMMU GALOG notification to schedule in
988 * a particular vCPU.
989 */
990 #define SVM_VM_DATA_HASH_BITS 8
991 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
992 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
993
994 /* Note:
995 * This function is called from IOMMU driver to notify
996 * SVM to schedule in a particular vCPU of a particular VM.
997 */
998 static int avic_ga_log_notifier(u32 ga_tag)
999 {
1000 unsigned long flags;
1001 struct kvm_arch *ka = NULL;
1002 struct kvm_vcpu *vcpu = NULL;
1003 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1004 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1005
1006 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1007
1008 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1009 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1010 struct kvm *kvm = container_of(ka, struct kvm, arch);
1011 struct kvm_arch *vm_data = &kvm->arch;
1012
1013 if (vm_data->avic_vm_id != vm_id)
1014 continue;
1015 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1016 break;
1017 }
1018 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1019
1020 if (!vcpu)
1021 return 0;
1022
1023 /* Note:
1024 * At this point, the IOMMU should have already set the pending
1025 * bit in the vAPIC backing page. So, we just need to schedule
1026 * in the vcpu.
1027 */
1028 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1029 kvm_vcpu_wake_up(vcpu);
1030
1031 return 0;
1032 }
1033
1034 static __init int svm_hardware_setup(void)
1035 {
1036 int cpu;
1037 struct page *iopm_pages;
1038 void *iopm_va;
1039 int r;
1040
1041 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1042
1043 if (!iopm_pages)
1044 return -ENOMEM;
1045
1046 iopm_va = page_address(iopm_pages);
1047 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1048 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1049
1050 init_msrpm_offsets();
1051
1052 if (boot_cpu_has(X86_FEATURE_NX))
1053 kvm_enable_efer_bits(EFER_NX);
1054
1055 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1056 kvm_enable_efer_bits(EFER_FFXSR);
1057
1058 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1059 kvm_has_tsc_control = true;
1060 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1061 kvm_tsc_scaling_ratio_frac_bits = 32;
1062 }
1063
1064 if (nested) {
1065 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1066 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1067 }
1068
1069 for_each_possible_cpu(cpu) {
1070 r = svm_cpu_init(cpu);
1071 if (r)
1072 goto err;
1073 }
1074
1075 if (!boot_cpu_has(X86_FEATURE_NPT))
1076 npt_enabled = false;
1077
1078 if (npt_enabled && !npt) {
1079 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1080 npt_enabled = false;
1081 }
1082
1083 if (npt_enabled) {
1084 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1085 kvm_enable_tdp();
1086 } else
1087 kvm_disable_tdp();
1088
1089 if (avic) {
1090 if (!npt_enabled ||
1091 !boot_cpu_has(X86_FEATURE_AVIC) ||
1092 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1093 avic = false;
1094 } else {
1095 pr_info("AVIC enabled\n");
1096
1097 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1098 }
1099 }
1100
1101 if (vls) {
1102 if (!npt_enabled ||
1103 !boot_cpu_has(X86_FEATURE_VIRTUAL_VMLOAD_VMSAVE) ||
1104 !IS_ENABLED(CONFIG_X86_64)) {
1105 vls = false;
1106 } else {
1107 pr_info("Virtual VMLOAD VMSAVE supported\n");
1108 }
1109 }
1110
1111 return 0;
1112
1113 err:
1114 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1115 iopm_base = 0;
1116 return r;
1117 }
1118
1119 static __exit void svm_hardware_unsetup(void)
1120 {
1121 int cpu;
1122
1123 for_each_possible_cpu(cpu)
1124 svm_cpu_uninit(cpu);
1125
1126 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1127 iopm_base = 0;
1128 }
1129
1130 static void init_seg(struct vmcb_seg *seg)
1131 {
1132 seg->selector = 0;
1133 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1134 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1135 seg->limit = 0xffff;
1136 seg->base = 0;
1137 }
1138
1139 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1140 {
1141 seg->selector = 0;
1142 seg->attrib = SVM_SELECTOR_P_MASK | type;
1143 seg->limit = 0xffff;
1144 seg->base = 0;
1145 }
1146
1147 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1148 {
1149 struct vcpu_svm *svm = to_svm(vcpu);
1150 u64 g_tsc_offset = 0;
1151
1152 if (is_guest_mode(vcpu)) {
1153 g_tsc_offset = svm->vmcb->control.tsc_offset -
1154 svm->nested.hsave->control.tsc_offset;
1155 svm->nested.hsave->control.tsc_offset = offset;
1156 } else
1157 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1158 svm->vmcb->control.tsc_offset,
1159 offset);
1160
1161 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1162
1163 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1164 }
1165
1166 static void avic_init_vmcb(struct vcpu_svm *svm)
1167 {
1168 struct vmcb *vmcb = svm->vmcb;
1169 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1170 phys_addr_t bpa = page_to_phys(svm->avic_backing_page);
1171 phys_addr_t lpa = page_to_phys(vm_data->avic_logical_id_table_page);
1172 phys_addr_t ppa = page_to_phys(vm_data->avic_physical_id_table_page);
1173
1174 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1175 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1176 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1177 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1178 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1179 svm->vcpu.arch.apicv_active = true;
1180 }
1181
1182 static void init_vmcb(struct vcpu_svm *svm)
1183 {
1184 struct vmcb_control_area *control = &svm->vmcb->control;
1185 struct vmcb_save_area *save = &svm->vmcb->save;
1186
1187 svm->vcpu.arch.hflags = 0;
1188
1189 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1190 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1191 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1192 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1193 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1194 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1195 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1196 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1197
1198 set_dr_intercepts(svm);
1199
1200 set_exception_intercept(svm, PF_VECTOR);
1201 set_exception_intercept(svm, UD_VECTOR);
1202 set_exception_intercept(svm, MC_VECTOR);
1203 set_exception_intercept(svm, AC_VECTOR);
1204 set_exception_intercept(svm, DB_VECTOR);
1205
1206 set_intercept(svm, INTERCEPT_INTR);
1207 set_intercept(svm, INTERCEPT_NMI);
1208 set_intercept(svm, INTERCEPT_SMI);
1209 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1210 set_intercept(svm, INTERCEPT_RDPMC);
1211 set_intercept(svm, INTERCEPT_CPUID);
1212 set_intercept(svm, INTERCEPT_INVD);
1213 set_intercept(svm, INTERCEPT_HLT);
1214 set_intercept(svm, INTERCEPT_INVLPG);
1215 set_intercept(svm, INTERCEPT_INVLPGA);
1216 set_intercept(svm, INTERCEPT_IOIO_PROT);
1217 set_intercept(svm, INTERCEPT_MSR_PROT);
1218 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1219 set_intercept(svm, INTERCEPT_SHUTDOWN);
1220 set_intercept(svm, INTERCEPT_VMRUN);
1221 set_intercept(svm, INTERCEPT_VMMCALL);
1222 set_intercept(svm, INTERCEPT_VMLOAD);
1223 set_intercept(svm, INTERCEPT_VMSAVE);
1224 set_intercept(svm, INTERCEPT_STGI);
1225 set_intercept(svm, INTERCEPT_CLGI);
1226 set_intercept(svm, INTERCEPT_SKINIT);
1227 set_intercept(svm, INTERCEPT_WBINVD);
1228 set_intercept(svm, INTERCEPT_XSETBV);
1229
1230 if (!kvm_mwait_in_guest()) {
1231 set_intercept(svm, INTERCEPT_MONITOR);
1232 set_intercept(svm, INTERCEPT_MWAIT);
1233 }
1234
1235 control->iopm_base_pa = iopm_base;
1236 control->msrpm_base_pa = __pa(svm->msrpm);
1237 control->int_ctl = V_INTR_MASKING_MASK;
1238
1239 init_seg(&save->es);
1240 init_seg(&save->ss);
1241 init_seg(&save->ds);
1242 init_seg(&save->fs);
1243 init_seg(&save->gs);
1244
1245 save->cs.selector = 0xf000;
1246 save->cs.base = 0xffff0000;
1247 /* Executable/Readable Code Segment */
1248 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1249 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1250 save->cs.limit = 0xffff;
1251
1252 save->gdtr.limit = 0xffff;
1253 save->idtr.limit = 0xffff;
1254
1255 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1256 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1257
1258 svm_set_efer(&svm->vcpu, 0);
1259 save->dr6 = 0xffff0ff0;
1260 kvm_set_rflags(&svm->vcpu, 2);
1261 save->rip = 0x0000fff0;
1262 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1263
1264 /*
1265 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1266 * It also updates the guest-visible cr0 value.
1267 */
1268 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1269 kvm_mmu_reset_context(&svm->vcpu);
1270
1271 save->cr4 = X86_CR4_PAE;
1272 /* rdx = ?? */
1273
1274 if (npt_enabled) {
1275 /* Setup VMCB for Nested Paging */
1276 control->nested_ctl = 1;
1277 clr_intercept(svm, INTERCEPT_INVLPG);
1278 clr_exception_intercept(svm, PF_VECTOR);
1279 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1280 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1281 save->g_pat = svm->vcpu.arch.pat;
1282 save->cr3 = 0;
1283 save->cr4 = 0;
1284 }
1285 svm->asid_generation = 0;
1286
1287 svm->nested.vmcb = 0;
1288 svm->vcpu.arch.hflags = 0;
1289
1290 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1291 control->pause_filter_count = 3000;
1292 set_intercept(svm, INTERCEPT_PAUSE);
1293 }
1294
1295 if (avic)
1296 avic_init_vmcb(svm);
1297
1298 /*
1299 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1300 * in VMCB and clear intercepts to avoid #VMEXIT.
1301 */
1302 if (vls) {
1303 clr_intercept(svm, INTERCEPT_VMLOAD);
1304 clr_intercept(svm, INTERCEPT_VMSAVE);
1305 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1306 }
1307
1308 mark_all_dirty(svm->vmcb);
1309
1310 enable_gif(svm);
1311
1312 }
1313
1314 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1315 unsigned int index)
1316 {
1317 u64 *avic_physical_id_table;
1318 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1319
1320 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1321 return NULL;
1322
1323 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1324
1325 return &avic_physical_id_table[index];
1326 }
1327
1328 /**
1329 * Note:
1330 * AVIC hardware walks the nested page table to check permissions,
1331 * but does not use the SPA address specified in the leaf page
1332 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1333 * field of the VMCB. Therefore, we set up the
1334 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1335 */
1336 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1337 {
1338 struct kvm *kvm = vcpu->kvm;
1339 int ret;
1340
1341 if (kvm->arch.apic_access_page_done)
1342 return 0;
1343
1344 ret = x86_set_memory_region(kvm,
1345 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1346 APIC_DEFAULT_PHYS_BASE,
1347 PAGE_SIZE);
1348 if (ret)
1349 return ret;
1350
1351 kvm->arch.apic_access_page_done = true;
1352 return 0;
1353 }
1354
1355 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1356 {
1357 int ret;
1358 u64 *entry, new_entry;
1359 int id = vcpu->vcpu_id;
1360 struct vcpu_svm *svm = to_svm(vcpu);
1361
1362 ret = avic_init_access_page(vcpu);
1363 if (ret)
1364 return ret;
1365
1366 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1367 return -EINVAL;
1368
1369 if (!svm->vcpu.arch.apic->regs)
1370 return -EINVAL;
1371
1372 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1373
1374 /* Setting AVIC backing page address in the phy APIC ID table */
1375 entry = avic_get_physical_id_entry(vcpu, id);
1376 if (!entry)
1377 return -EINVAL;
1378
1379 new_entry = READ_ONCE(*entry);
1380 new_entry = (page_to_phys(svm->avic_backing_page) &
1381 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1382 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK;
1383 WRITE_ONCE(*entry, new_entry);
1384
1385 svm->avic_physical_id_cache = entry;
1386
1387 return 0;
1388 }
1389
1390 static inline int avic_get_next_vm_id(void)
1391 {
1392 int id;
1393
1394 spin_lock(&avic_vm_id_lock);
1395
1396 /* AVIC VM ID is one-based. */
1397 id = find_next_zero_bit(avic_vm_id_bitmap, AVIC_VM_ID_NR, 1);
1398 if (id <= AVIC_VM_ID_MASK)
1399 __set_bit(id, avic_vm_id_bitmap);
1400 else
1401 id = -EAGAIN;
1402
1403 spin_unlock(&avic_vm_id_lock);
1404 return id;
1405 }
1406
1407 static inline int avic_free_vm_id(int id)
1408 {
1409 if (id <= 0 || id > AVIC_VM_ID_MASK)
1410 return -EINVAL;
1411
1412 spin_lock(&avic_vm_id_lock);
1413 __clear_bit(id, avic_vm_id_bitmap);
1414 spin_unlock(&avic_vm_id_lock);
1415 return 0;
1416 }
1417
1418 static void avic_vm_destroy(struct kvm *kvm)
1419 {
1420 unsigned long flags;
1421 struct kvm_arch *vm_data = &kvm->arch;
1422
1423 if (!avic)
1424 return;
1425
1426 avic_free_vm_id(vm_data->avic_vm_id);
1427
1428 if (vm_data->avic_logical_id_table_page)
1429 __free_page(vm_data->avic_logical_id_table_page);
1430 if (vm_data->avic_physical_id_table_page)
1431 __free_page(vm_data->avic_physical_id_table_page);
1432
1433 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1434 hash_del(&vm_data->hnode);
1435 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1436 }
1437
1438 static int avic_vm_init(struct kvm *kvm)
1439 {
1440 unsigned long flags;
1441 int vm_id, err = -ENOMEM;
1442 struct kvm_arch *vm_data = &kvm->arch;
1443 struct page *p_page;
1444 struct page *l_page;
1445
1446 if (!avic)
1447 return 0;
1448
1449 vm_id = avic_get_next_vm_id();
1450 if (vm_id < 0)
1451 return vm_id;
1452 vm_data->avic_vm_id = (u32)vm_id;
1453
1454 /* Allocating physical APIC ID table (4KB) */
1455 p_page = alloc_page(GFP_KERNEL);
1456 if (!p_page)
1457 goto free_avic;
1458
1459 vm_data->avic_physical_id_table_page = p_page;
1460 clear_page(page_address(p_page));
1461
1462 /* Allocating logical APIC ID table (4KB) */
1463 l_page = alloc_page(GFP_KERNEL);
1464 if (!l_page)
1465 goto free_avic;
1466
1467 vm_data->avic_logical_id_table_page = l_page;
1468 clear_page(page_address(l_page));
1469
1470 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1471 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1472 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1473
1474 return 0;
1475
1476 free_avic:
1477 avic_vm_destroy(kvm);
1478 return err;
1479 }
1480
1481 static inline int
1482 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1483 {
1484 int ret = 0;
1485 unsigned long flags;
1486 struct amd_svm_iommu_ir *ir;
1487 struct vcpu_svm *svm = to_svm(vcpu);
1488
1489 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1490 return 0;
1491
1492 /*
1493 * Here, we go through the per-vcpu ir_list to update all existing
1494 * interrupt remapping table entry targeting this vcpu.
1495 */
1496 spin_lock_irqsave(&svm->ir_list_lock, flags);
1497
1498 if (list_empty(&svm->ir_list))
1499 goto out;
1500
1501 list_for_each_entry(ir, &svm->ir_list, node) {
1502 ret = amd_iommu_update_ga(cpu, r, ir->data);
1503 if (ret)
1504 break;
1505 }
1506 out:
1507 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1508 return ret;
1509 }
1510
1511 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1512 {
1513 u64 entry;
1514 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1515 int h_physical_id = kvm_cpu_get_apicid(cpu);
1516 struct vcpu_svm *svm = to_svm(vcpu);
1517
1518 if (!kvm_vcpu_apicv_active(vcpu))
1519 return;
1520
1521 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1522 return;
1523
1524 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1525 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1526
1527 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1528 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1529
1530 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1531 if (svm->avic_is_running)
1532 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1533
1534 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1535 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1536 svm->avic_is_running);
1537 }
1538
1539 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1540 {
1541 u64 entry;
1542 struct vcpu_svm *svm = to_svm(vcpu);
1543
1544 if (!kvm_vcpu_apicv_active(vcpu))
1545 return;
1546
1547 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1548 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1549 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1550
1551 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1552 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1553 }
1554
1555 /**
1556 * This function is called during VCPU halt/unhalt.
1557 */
1558 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1559 {
1560 struct vcpu_svm *svm = to_svm(vcpu);
1561
1562 svm->avic_is_running = is_run;
1563 if (is_run)
1564 avic_vcpu_load(vcpu, vcpu->cpu);
1565 else
1566 avic_vcpu_put(vcpu);
1567 }
1568
1569 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1570 {
1571 struct vcpu_svm *svm = to_svm(vcpu);
1572 u32 dummy;
1573 u32 eax = 1;
1574
1575 if (!init_event) {
1576 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1577 MSR_IA32_APICBASE_ENABLE;
1578 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1579 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1580 }
1581 init_vmcb(svm);
1582
1583 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1584 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1585
1586 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1587 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1588 }
1589
1590 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1591 {
1592 struct vcpu_svm *svm;
1593 struct page *page;
1594 struct page *msrpm_pages;
1595 struct page *hsave_page;
1596 struct page *nested_msrpm_pages;
1597 int err;
1598
1599 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1600 if (!svm) {
1601 err = -ENOMEM;
1602 goto out;
1603 }
1604
1605 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1606 if (err)
1607 goto free_svm;
1608
1609 err = -ENOMEM;
1610 page = alloc_page(GFP_KERNEL);
1611 if (!page)
1612 goto uninit;
1613
1614 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1615 if (!msrpm_pages)
1616 goto free_page1;
1617
1618 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1619 if (!nested_msrpm_pages)
1620 goto free_page2;
1621
1622 hsave_page = alloc_page(GFP_KERNEL);
1623 if (!hsave_page)
1624 goto free_page3;
1625
1626 if (avic) {
1627 err = avic_init_backing_page(&svm->vcpu);
1628 if (err)
1629 goto free_page4;
1630
1631 INIT_LIST_HEAD(&svm->ir_list);
1632 spin_lock_init(&svm->ir_list_lock);
1633 }
1634
1635 /* We initialize this flag to true to make sure that the is_running
1636 * bit would be set the first time the vcpu is loaded.
1637 */
1638 svm->avic_is_running = true;
1639
1640 svm->nested.hsave = page_address(hsave_page);
1641
1642 svm->msrpm = page_address(msrpm_pages);
1643 svm_vcpu_init_msrpm(svm->msrpm);
1644
1645 svm->nested.msrpm = page_address(nested_msrpm_pages);
1646 svm_vcpu_init_msrpm(svm->nested.msrpm);
1647
1648 svm->vmcb = page_address(page);
1649 clear_page(svm->vmcb);
1650 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1651 svm->asid_generation = 0;
1652 init_vmcb(svm);
1653
1654 svm_init_osvw(&svm->vcpu);
1655
1656 return &svm->vcpu;
1657
1658 free_page4:
1659 __free_page(hsave_page);
1660 free_page3:
1661 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1662 free_page2:
1663 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1664 free_page1:
1665 __free_page(page);
1666 uninit:
1667 kvm_vcpu_uninit(&svm->vcpu);
1668 free_svm:
1669 kmem_cache_free(kvm_vcpu_cache, svm);
1670 out:
1671 return ERR_PTR(err);
1672 }
1673
1674 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1675 {
1676 struct vcpu_svm *svm = to_svm(vcpu);
1677
1678 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1679 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1680 __free_page(virt_to_page(svm->nested.hsave));
1681 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1682 kvm_vcpu_uninit(vcpu);
1683 kmem_cache_free(kvm_vcpu_cache, svm);
1684 }
1685
1686 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1687 {
1688 struct vcpu_svm *svm = to_svm(vcpu);
1689 int i;
1690
1691 if (unlikely(cpu != vcpu->cpu)) {
1692 svm->asid_generation = 0;
1693 mark_all_dirty(svm->vmcb);
1694 }
1695
1696 #ifdef CONFIG_X86_64
1697 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1698 #endif
1699 savesegment(fs, svm->host.fs);
1700 savesegment(gs, svm->host.gs);
1701 svm->host.ldt = kvm_read_ldt();
1702
1703 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1704 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1705
1706 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1707 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1708 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1709 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1710 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1711 }
1712 }
1713 /* This assumes that the kernel never uses MSR_TSC_AUX */
1714 if (static_cpu_has(X86_FEATURE_RDTSCP))
1715 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1716
1717 avic_vcpu_load(vcpu, cpu);
1718 }
1719
1720 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1721 {
1722 struct vcpu_svm *svm = to_svm(vcpu);
1723 int i;
1724
1725 avic_vcpu_put(vcpu);
1726
1727 ++vcpu->stat.host_state_reload;
1728 kvm_load_ldt(svm->host.ldt);
1729 #ifdef CONFIG_X86_64
1730 loadsegment(fs, svm->host.fs);
1731 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1732 load_gs_index(svm->host.gs);
1733 #else
1734 #ifdef CONFIG_X86_32_LAZY_GS
1735 loadsegment(gs, svm->host.gs);
1736 #endif
1737 #endif
1738 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1739 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1740 }
1741
1742 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1743 {
1744 avic_set_running(vcpu, false);
1745 }
1746
1747 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1748 {
1749 avic_set_running(vcpu, true);
1750 }
1751
1752 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1753 {
1754 struct vcpu_svm *svm = to_svm(vcpu);
1755 unsigned long rflags = svm->vmcb->save.rflags;
1756
1757 if (svm->nmi_singlestep) {
1758 /* Hide our flags if they were not set by the guest */
1759 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1760 rflags &= ~X86_EFLAGS_TF;
1761 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1762 rflags &= ~X86_EFLAGS_RF;
1763 }
1764 return rflags;
1765 }
1766
1767 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1768 {
1769 if (to_svm(vcpu)->nmi_singlestep)
1770 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1771
1772 /*
1773 * Any change of EFLAGS.VM is accompanied by a reload of SS
1774 * (caused by either a task switch or an inter-privilege IRET),
1775 * so we do not need to update the CPL here.
1776 */
1777 to_svm(vcpu)->vmcb->save.rflags = rflags;
1778 }
1779
1780 static u32 svm_get_pkru(struct kvm_vcpu *vcpu)
1781 {
1782 return 0;
1783 }
1784
1785 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1786 {
1787 switch (reg) {
1788 case VCPU_EXREG_PDPTR:
1789 BUG_ON(!npt_enabled);
1790 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1791 break;
1792 default:
1793 BUG();
1794 }
1795 }
1796
1797 static void svm_set_vintr(struct vcpu_svm *svm)
1798 {
1799 set_intercept(svm, INTERCEPT_VINTR);
1800 }
1801
1802 static void svm_clear_vintr(struct vcpu_svm *svm)
1803 {
1804 clr_intercept(svm, INTERCEPT_VINTR);
1805 }
1806
1807 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1808 {
1809 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1810
1811 switch (seg) {
1812 case VCPU_SREG_CS: return &save->cs;
1813 case VCPU_SREG_DS: return &save->ds;
1814 case VCPU_SREG_ES: return &save->es;
1815 case VCPU_SREG_FS: return &save->fs;
1816 case VCPU_SREG_GS: return &save->gs;
1817 case VCPU_SREG_SS: return &save->ss;
1818 case VCPU_SREG_TR: return &save->tr;
1819 case VCPU_SREG_LDTR: return &save->ldtr;
1820 }
1821 BUG();
1822 return NULL;
1823 }
1824
1825 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1826 {
1827 struct vmcb_seg *s = svm_seg(vcpu, seg);
1828
1829 return s->base;
1830 }
1831
1832 static void svm_get_segment(struct kvm_vcpu *vcpu,
1833 struct kvm_segment *var, int seg)
1834 {
1835 struct vmcb_seg *s = svm_seg(vcpu, seg);
1836
1837 var->base = s->base;
1838 var->limit = s->limit;
1839 var->selector = s->selector;
1840 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1841 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1842 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1843 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1844 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1845 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1846 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1847
1848 /*
1849 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1850 * However, the SVM spec states that the G bit is not observed by the
1851 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1852 * So let's synthesize a legal G bit for all segments, this helps
1853 * running KVM nested. It also helps cross-vendor migration, because
1854 * Intel's vmentry has a check on the 'G' bit.
1855 */
1856 var->g = s->limit > 0xfffff;
1857
1858 /*
1859 * AMD's VMCB does not have an explicit unusable field, so emulate it
1860 * for cross vendor migration purposes by "not present"
1861 */
1862 var->unusable = !var->present;
1863
1864 switch (seg) {
1865 case VCPU_SREG_TR:
1866 /*
1867 * Work around a bug where the busy flag in the tr selector
1868 * isn't exposed
1869 */
1870 var->type |= 0x2;
1871 break;
1872 case VCPU_SREG_DS:
1873 case VCPU_SREG_ES:
1874 case VCPU_SREG_FS:
1875 case VCPU_SREG_GS:
1876 /*
1877 * The accessed bit must always be set in the segment
1878 * descriptor cache, although it can be cleared in the
1879 * descriptor, the cached bit always remains at 1. Since
1880 * Intel has a check on this, set it here to support
1881 * cross-vendor migration.
1882 */
1883 if (!var->unusable)
1884 var->type |= 0x1;
1885 break;
1886 case VCPU_SREG_SS:
1887 /*
1888 * On AMD CPUs sometimes the DB bit in the segment
1889 * descriptor is left as 1, although the whole segment has
1890 * been made unusable. Clear it here to pass an Intel VMX
1891 * entry check when cross vendor migrating.
1892 */
1893 if (var->unusable)
1894 var->db = 0;
1895 /* This is symmetric with svm_set_segment() */
1896 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1897 break;
1898 }
1899 }
1900
1901 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1902 {
1903 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1904
1905 return save->cpl;
1906 }
1907
1908 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1909 {
1910 struct vcpu_svm *svm = to_svm(vcpu);
1911
1912 dt->size = svm->vmcb->save.idtr.limit;
1913 dt->address = svm->vmcb->save.idtr.base;
1914 }
1915
1916 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1917 {
1918 struct vcpu_svm *svm = to_svm(vcpu);
1919
1920 svm->vmcb->save.idtr.limit = dt->size;
1921 svm->vmcb->save.idtr.base = dt->address ;
1922 mark_dirty(svm->vmcb, VMCB_DT);
1923 }
1924
1925 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1926 {
1927 struct vcpu_svm *svm = to_svm(vcpu);
1928
1929 dt->size = svm->vmcb->save.gdtr.limit;
1930 dt->address = svm->vmcb->save.gdtr.base;
1931 }
1932
1933 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1934 {
1935 struct vcpu_svm *svm = to_svm(vcpu);
1936
1937 svm->vmcb->save.gdtr.limit = dt->size;
1938 svm->vmcb->save.gdtr.base = dt->address ;
1939 mark_dirty(svm->vmcb, VMCB_DT);
1940 }
1941
1942 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1943 {
1944 }
1945
1946 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1947 {
1948 }
1949
1950 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1951 {
1952 }
1953
1954 static void update_cr0_intercept(struct vcpu_svm *svm)
1955 {
1956 ulong gcr0 = svm->vcpu.arch.cr0;
1957 u64 *hcr0 = &svm->vmcb->save.cr0;
1958
1959 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1960 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1961
1962 mark_dirty(svm->vmcb, VMCB_CR);
1963
1964 if (gcr0 == *hcr0) {
1965 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1966 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1967 } else {
1968 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1969 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1970 }
1971 }
1972
1973 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1974 {
1975 struct vcpu_svm *svm = to_svm(vcpu);
1976
1977 #ifdef CONFIG_X86_64
1978 if (vcpu->arch.efer & EFER_LME) {
1979 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1980 vcpu->arch.efer |= EFER_LMA;
1981 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1982 }
1983
1984 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1985 vcpu->arch.efer &= ~EFER_LMA;
1986 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1987 }
1988 }
1989 #endif
1990 vcpu->arch.cr0 = cr0;
1991
1992 if (!npt_enabled)
1993 cr0 |= X86_CR0_PG | X86_CR0_WP;
1994
1995 /*
1996 * re-enable caching here because the QEMU bios
1997 * does not do it - this results in some delay at
1998 * reboot
1999 */
2000 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2001 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2002 svm->vmcb->save.cr0 = cr0;
2003 mark_dirty(svm->vmcb, VMCB_CR);
2004 update_cr0_intercept(svm);
2005 }
2006
2007 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2008 {
2009 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2010 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2011
2012 if (cr4 & X86_CR4_VMXE)
2013 return 1;
2014
2015 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2016 svm_flush_tlb(vcpu);
2017
2018 vcpu->arch.cr4 = cr4;
2019 if (!npt_enabled)
2020 cr4 |= X86_CR4_PAE;
2021 cr4 |= host_cr4_mce;
2022 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2023 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2024 return 0;
2025 }
2026
2027 static void svm_set_segment(struct kvm_vcpu *vcpu,
2028 struct kvm_segment *var, int seg)
2029 {
2030 struct vcpu_svm *svm = to_svm(vcpu);
2031 struct vmcb_seg *s = svm_seg(vcpu, seg);
2032
2033 s->base = var->base;
2034 s->limit = var->limit;
2035 s->selector = var->selector;
2036 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2037 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2038 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2039 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2040 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2041 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2042 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2043 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2044
2045 /*
2046 * This is always accurate, except if SYSRET returned to a segment
2047 * with SS.DPL != 3. Intel does not have this quirk, and always
2048 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2049 * would entail passing the CPL to userspace and back.
2050 */
2051 if (seg == VCPU_SREG_SS)
2052 /* This is symmetric with svm_get_segment() */
2053 svm->vmcb->save.cpl = (var->dpl & 3);
2054
2055 mark_dirty(svm->vmcb, VMCB_SEG);
2056 }
2057
2058 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2059 {
2060 struct vcpu_svm *svm = to_svm(vcpu);
2061
2062 clr_exception_intercept(svm, BP_VECTOR);
2063
2064 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2065 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2066 set_exception_intercept(svm, BP_VECTOR);
2067 } else
2068 vcpu->guest_debug = 0;
2069 }
2070
2071 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2072 {
2073 if (sd->next_asid > sd->max_asid) {
2074 ++sd->asid_generation;
2075 sd->next_asid = 1;
2076 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2077 }
2078
2079 svm->asid_generation = sd->asid_generation;
2080 svm->vmcb->control.asid = sd->next_asid++;
2081
2082 mark_dirty(svm->vmcb, VMCB_ASID);
2083 }
2084
2085 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2086 {
2087 return to_svm(vcpu)->vmcb->save.dr6;
2088 }
2089
2090 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2091 {
2092 struct vcpu_svm *svm = to_svm(vcpu);
2093
2094 svm->vmcb->save.dr6 = value;
2095 mark_dirty(svm->vmcb, VMCB_DR);
2096 }
2097
2098 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2099 {
2100 struct vcpu_svm *svm = to_svm(vcpu);
2101
2102 get_debugreg(vcpu->arch.db[0], 0);
2103 get_debugreg(vcpu->arch.db[1], 1);
2104 get_debugreg(vcpu->arch.db[2], 2);
2105 get_debugreg(vcpu->arch.db[3], 3);
2106 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2107 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2108
2109 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2110 set_dr_intercepts(svm);
2111 }
2112
2113 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2114 {
2115 struct vcpu_svm *svm = to_svm(vcpu);
2116
2117 svm->vmcb->save.dr7 = value;
2118 mark_dirty(svm->vmcb, VMCB_DR);
2119 }
2120
2121 static int pf_interception(struct vcpu_svm *svm)
2122 {
2123 u64 fault_address = svm->vmcb->control.exit_info_2;
2124 u64 error_code = svm->vmcb->control.exit_info_1;
2125
2126 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2127 svm->vmcb->control.insn_bytes,
2128 svm->vmcb->control.insn_len, !npt_enabled);
2129 }
2130
2131 static int db_interception(struct vcpu_svm *svm)
2132 {
2133 struct kvm_run *kvm_run = svm->vcpu.run;
2134
2135 if (!(svm->vcpu.guest_debug &
2136 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2137 !svm->nmi_singlestep) {
2138 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2139 return 1;
2140 }
2141
2142 if (svm->nmi_singlestep) {
2143 disable_nmi_singlestep(svm);
2144 }
2145
2146 if (svm->vcpu.guest_debug &
2147 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2148 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2149 kvm_run->debug.arch.pc =
2150 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2151 kvm_run->debug.arch.exception = DB_VECTOR;
2152 return 0;
2153 }
2154
2155 return 1;
2156 }
2157
2158 static int bp_interception(struct vcpu_svm *svm)
2159 {
2160 struct kvm_run *kvm_run = svm->vcpu.run;
2161
2162 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2163 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2164 kvm_run->debug.arch.exception = BP_VECTOR;
2165 return 0;
2166 }
2167
2168 static int ud_interception(struct vcpu_svm *svm)
2169 {
2170 int er;
2171
2172 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2173 if (er != EMULATE_DONE)
2174 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2175 return 1;
2176 }
2177
2178 static int ac_interception(struct vcpu_svm *svm)
2179 {
2180 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2181 return 1;
2182 }
2183
2184 static bool is_erratum_383(void)
2185 {
2186 int err, i;
2187 u64 value;
2188
2189 if (!erratum_383_found)
2190 return false;
2191
2192 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2193 if (err)
2194 return false;
2195
2196 /* Bit 62 may or may not be set for this mce */
2197 value &= ~(1ULL << 62);
2198
2199 if (value != 0xb600000000010015ULL)
2200 return false;
2201
2202 /* Clear MCi_STATUS registers */
2203 for (i = 0; i < 6; ++i)
2204 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2205
2206 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2207 if (!err) {
2208 u32 low, high;
2209
2210 value &= ~(1ULL << 2);
2211 low = lower_32_bits(value);
2212 high = upper_32_bits(value);
2213
2214 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2215 }
2216
2217 /* Flush tlb to evict multi-match entries */
2218 __flush_tlb_all();
2219
2220 return true;
2221 }
2222
2223 static void svm_handle_mce(struct vcpu_svm *svm)
2224 {
2225 if (is_erratum_383()) {
2226 /*
2227 * Erratum 383 triggered. Guest state is corrupt so kill the
2228 * guest.
2229 */
2230 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2231
2232 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2233
2234 return;
2235 }
2236
2237 /*
2238 * On an #MC intercept the MCE handler is not called automatically in
2239 * the host. So do it by hand here.
2240 */
2241 asm volatile (
2242 "int $0x12\n");
2243 /* not sure if we ever come back to this point */
2244
2245 return;
2246 }
2247
2248 static int mc_interception(struct vcpu_svm *svm)
2249 {
2250 return 1;
2251 }
2252
2253 static int shutdown_interception(struct vcpu_svm *svm)
2254 {
2255 struct kvm_run *kvm_run = svm->vcpu.run;
2256
2257 /*
2258 * VMCB is undefined after a SHUTDOWN intercept
2259 * so reinitialize it.
2260 */
2261 clear_page(svm->vmcb);
2262 init_vmcb(svm);
2263
2264 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2265 return 0;
2266 }
2267
2268 static int io_interception(struct vcpu_svm *svm)
2269 {
2270 struct kvm_vcpu *vcpu = &svm->vcpu;
2271 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2272 int size, in, string, ret;
2273 unsigned port;
2274
2275 ++svm->vcpu.stat.io_exits;
2276 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2277 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2278 if (string)
2279 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2280
2281 port = io_info >> 16;
2282 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2283 svm->next_rip = svm->vmcb->control.exit_info_2;
2284 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2285
2286 /*
2287 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2288 * KVM_EXIT_DEBUG here.
2289 */
2290 if (in)
2291 return kvm_fast_pio_in(vcpu, size, port) && ret;
2292 else
2293 return kvm_fast_pio_out(vcpu, size, port) && ret;
2294 }
2295
2296 static int nmi_interception(struct vcpu_svm *svm)
2297 {
2298 return 1;
2299 }
2300
2301 static int intr_interception(struct vcpu_svm *svm)
2302 {
2303 ++svm->vcpu.stat.irq_exits;
2304 return 1;
2305 }
2306
2307 static int nop_on_interception(struct vcpu_svm *svm)
2308 {
2309 return 1;
2310 }
2311
2312 static int halt_interception(struct vcpu_svm *svm)
2313 {
2314 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2315 return kvm_emulate_halt(&svm->vcpu);
2316 }
2317
2318 static int vmmcall_interception(struct vcpu_svm *svm)
2319 {
2320 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2321 return kvm_emulate_hypercall(&svm->vcpu);
2322 }
2323
2324 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2325 {
2326 struct vcpu_svm *svm = to_svm(vcpu);
2327
2328 return svm->nested.nested_cr3;
2329 }
2330
2331 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2332 {
2333 struct vcpu_svm *svm = to_svm(vcpu);
2334 u64 cr3 = svm->nested.nested_cr3;
2335 u64 pdpte;
2336 int ret;
2337
2338 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(cr3), &pdpte,
2339 offset_in_page(cr3) + index * 8, 8);
2340 if (ret)
2341 return 0;
2342 return pdpte;
2343 }
2344
2345 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2346 unsigned long root)
2347 {
2348 struct vcpu_svm *svm = to_svm(vcpu);
2349
2350 svm->vmcb->control.nested_cr3 = root;
2351 mark_dirty(svm->vmcb, VMCB_NPT);
2352 svm_flush_tlb(vcpu);
2353 }
2354
2355 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2356 struct x86_exception *fault)
2357 {
2358 struct vcpu_svm *svm = to_svm(vcpu);
2359
2360 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2361 /*
2362 * TODO: track the cause of the nested page fault, and
2363 * correctly fill in the high bits of exit_info_1.
2364 */
2365 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2366 svm->vmcb->control.exit_code_hi = 0;
2367 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2368 svm->vmcb->control.exit_info_2 = fault->address;
2369 }
2370
2371 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2372 svm->vmcb->control.exit_info_1 |= fault->error_code;
2373
2374 /*
2375 * The present bit is always zero for page structure faults on real
2376 * hardware.
2377 */
2378 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2379 svm->vmcb->control.exit_info_1 &= ~1;
2380
2381 nested_svm_vmexit(svm);
2382 }
2383
2384 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2385 {
2386 WARN_ON(mmu_is_nested(vcpu));
2387 kvm_init_shadow_mmu(vcpu);
2388 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2389 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2390 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2391 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2392 vcpu->arch.mmu.shadow_root_level = get_npt_level();
2393 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2394 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2395 }
2396
2397 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2398 {
2399 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2400 }
2401
2402 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2403 {
2404 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2405 !is_paging(&svm->vcpu)) {
2406 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2407 return 1;
2408 }
2409
2410 if (svm->vmcb->save.cpl) {
2411 kvm_inject_gp(&svm->vcpu, 0);
2412 return 1;
2413 }
2414
2415 return 0;
2416 }
2417
2418 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2419 bool has_error_code, u32 error_code)
2420 {
2421 int vmexit;
2422
2423 if (!is_guest_mode(&svm->vcpu))
2424 return 0;
2425
2426 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2427 svm->vmcb->control.exit_code_hi = 0;
2428 svm->vmcb->control.exit_info_1 = error_code;
2429 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2430
2431 vmexit = nested_svm_intercept(svm);
2432 if (vmexit == NESTED_EXIT_DONE)
2433 svm->nested.exit_required = true;
2434
2435 return vmexit;
2436 }
2437
2438 /* This function returns true if it is save to enable the irq window */
2439 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2440 {
2441 if (!is_guest_mode(&svm->vcpu))
2442 return true;
2443
2444 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2445 return true;
2446
2447 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2448 return false;
2449
2450 /*
2451 * if vmexit was already requested (by intercepted exception
2452 * for instance) do not overwrite it with "external interrupt"
2453 * vmexit.
2454 */
2455 if (svm->nested.exit_required)
2456 return false;
2457
2458 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2459 svm->vmcb->control.exit_info_1 = 0;
2460 svm->vmcb->control.exit_info_2 = 0;
2461
2462 if (svm->nested.intercept & 1ULL) {
2463 /*
2464 * The #vmexit can't be emulated here directly because this
2465 * code path runs with irqs and preemption disabled. A
2466 * #vmexit emulation might sleep. Only signal request for
2467 * the #vmexit here.
2468 */
2469 svm->nested.exit_required = true;
2470 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2471 return false;
2472 }
2473
2474 return true;
2475 }
2476
2477 /* This function returns true if it is save to enable the nmi window */
2478 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2479 {
2480 if (!is_guest_mode(&svm->vcpu))
2481 return true;
2482
2483 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2484 return true;
2485
2486 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2487 svm->nested.exit_required = true;
2488
2489 return false;
2490 }
2491
2492 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2493 {
2494 struct page *page;
2495
2496 might_sleep();
2497
2498 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2499 if (is_error_page(page))
2500 goto error;
2501
2502 *_page = page;
2503
2504 return kmap(page);
2505
2506 error:
2507 kvm_inject_gp(&svm->vcpu, 0);
2508
2509 return NULL;
2510 }
2511
2512 static void nested_svm_unmap(struct page *page)
2513 {
2514 kunmap(page);
2515 kvm_release_page_dirty(page);
2516 }
2517
2518 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2519 {
2520 unsigned port, size, iopm_len;
2521 u16 val, mask;
2522 u8 start_bit;
2523 u64 gpa;
2524
2525 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2526 return NESTED_EXIT_HOST;
2527
2528 port = svm->vmcb->control.exit_info_1 >> 16;
2529 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2530 SVM_IOIO_SIZE_SHIFT;
2531 gpa = svm->nested.vmcb_iopm + (port / 8);
2532 start_bit = port % 8;
2533 iopm_len = (start_bit + size > 8) ? 2 : 1;
2534 mask = (0xf >> (4 - size)) << start_bit;
2535 val = 0;
2536
2537 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2538 return NESTED_EXIT_DONE;
2539
2540 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2541 }
2542
2543 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2544 {
2545 u32 offset, msr, value;
2546 int write, mask;
2547
2548 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2549 return NESTED_EXIT_HOST;
2550
2551 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2552 offset = svm_msrpm_offset(msr);
2553 write = svm->vmcb->control.exit_info_1 & 1;
2554 mask = 1 << ((2 * (msr & 0xf)) + write);
2555
2556 if (offset == MSR_INVALID)
2557 return NESTED_EXIT_DONE;
2558
2559 /* Offset is in 32 bit units but need in 8 bit units */
2560 offset *= 4;
2561
2562 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2563 return NESTED_EXIT_DONE;
2564
2565 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2566 }
2567
2568 /* DB exceptions for our internal use must not cause vmexit */
2569 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2570 {
2571 unsigned long dr6;
2572
2573 /* if we're not singlestepping, it's not ours */
2574 if (!svm->nmi_singlestep)
2575 return NESTED_EXIT_DONE;
2576
2577 /* if it's not a singlestep exception, it's not ours */
2578 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2579 return NESTED_EXIT_DONE;
2580 if (!(dr6 & DR6_BS))
2581 return NESTED_EXIT_DONE;
2582
2583 /* if the guest is singlestepping, it should get the vmexit */
2584 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2585 disable_nmi_singlestep(svm);
2586 return NESTED_EXIT_DONE;
2587 }
2588
2589 /* it's ours, the nested hypervisor must not see this one */
2590 return NESTED_EXIT_HOST;
2591 }
2592
2593 static int nested_svm_exit_special(struct vcpu_svm *svm)
2594 {
2595 u32 exit_code = svm->vmcb->control.exit_code;
2596
2597 switch (exit_code) {
2598 case SVM_EXIT_INTR:
2599 case SVM_EXIT_NMI:
2600 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2601 return NESTED_EXIT_HOST;
2602 case SVM_EXIT_NPF:
2603 /* For now we are always handling NPFs when using them */
2604 if (npt_enabled)
2605 return NESTED_EXIT_HOST;
2606 break;
2607 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2608 /* When we're shadowing, trap PFs, but not async PF */
2609 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2610 return NESTED_EXIT_HOST;
2611 break;
2612 default:
2613 break;
2614 }
2615
2616 return NESTED_EXIT_CONTINUE;
2617 }
2618
2619 /*
2620 * If this function returns true, this #vmexit was already handled
2621 */
2622 static int nested_svm_intercept(struct vcpu_svm *svm)
2623 {
2624 u32 exit_code = svm->vmcb->control.exit_code;
2625 int vmexit = NESTED_EXIT_HOST;
2626
2627 switch (exit_code) {
2628 case SVM_EXIT_MSR:
2629 vmexit = nested_svm_exit_handled_msr(svm);
2630 break;
2631 case SVM_EXIT_IOIO:
2632 vmexit = nested_svm_intercept_ioio(svm);
2633 break;
2634 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2635 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2636 if (svm->nested.intercept_cr & bit)
2637 vmexit = NESTED_EXIT_DONE;
2638 break;
2639 }
2640 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2641 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2642 if (svm->nested.intercept_dr & bit)
2643 vmexit = NESTED_EXIT_DONE;
2644 break;
2645 }
2646 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2647 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2648 if (svm->nested.intercept_exceptions & excp_bits) {
2649 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2650 vmexit = nested_svm_intercept_db(svm);
2651 else
2652 vmexit = NESTED_EXIT_DONE;
2653 }
2654 /* async page fault always cause vmexit */
2655 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2656 svm->vcpu.arch.apf.host_apf_reason != 0)
2657 vmexit = NESTED_EXIT_DONE;
2658 break;
2659 }
2660 case SVM_EXIT_ERR: {
2661 vmexit = NESTED_EXIT_DONE;
2662 break;
2663 }
2664 default: {
2665 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2666 if (svm->nested.intercept & exit_bits)
2667 vmexit = NESTED_EXIT_DONE;
2668 }
2669 }
2670
2671 return vmexit;
2672 }
2673
2674 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2675 {
2676 int vmexit;
2677
2678 vmexit = nested_svm_intercept(svm);
2679
2680 if (vmexit == NESTED_EXIT_DONE)
2681 nested_svm_vmexit(svm);
2682
2683 return vmexit;
2684 }
2685
2686 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2687 {
2688 struct vmcb_control_area *dst = &dst_vmcb->control;
2689 struct vmcb_control_area *from = &from_vmcb->control;
2690
2691 dst->intercept_cr = from->intercept_cr;
2692 dst->intercept_dr = from->intercept_dr;
2693 dst->intercept_exceptions = from->intercept_exceptions;
2694 dst->intercept = from->intercept;
2695 dst->iopm_base_pa = from->iopm_base_pa;
2696 dst->msrpm_base_pa = from->msrpm_base_pa;
2697 dst->tsc_offset = from->tsc_offset;
2698 dst->asid = from->asid;
2699 dst->tlb_ctl = from->tlb_ctl;
2700 dst->int_ctl = from->int_ctl;
2701 dst->int_vector = from->int_vector;
2702 dst->int_state = from->int_state;
2703 dst->exit_code = from->exit_code;
2704 dst->exit_code_hi = from->exit_code_hi;
2705 dst->exit_info_1 = from->exit_info_1;
2706 dst->exit_info_2 = from->exit_info_2;
2707 dst->exit_int_info = from->exit_int_info;
2708 dst->exit_int_info_err = from->exit_int_info_err;
2709 dst->nested_ctl = from->nested_ctl;
2710 dst->event_inj = from->event_inj;
2711 dst->event_inj_err = from->event_inj_err;
2712 dst->nested_cr3 = from->nested_cr3;
2713 dst->virt_ext = from->virt_ext;
2714 }
2715
2716 static int nested_svm_vmexit(struct vcpu_svm *svm)
2717 {
2718 struct vmcb *nested_vmcb;
2719 struct vmcb *hsave = svm->nested.hsave;
2720 struct vmcb *vmcb = svm->vmcb;
2721 struct page *page;
2722
2723 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2724 vmcb->control.exit_info_1,
2725 vmcb->control.exit_info_2,
2726 vmcb->control.exit_int_info,
2727 vmcb->control.exit_int_info_err,
2728 KVM_ISA_SVM);
2729
2730 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2731 if (!nested_vmcb)
2732 return 1;
2733
2734 /* Exit Guest-Mode */
2735 leave_guest_mode(&svm->vcpu);
2736 svm->nested.vmcb = 0;
2737
2738 /* Give the current vmcb to the guest */
2739 disable_gif(svm);
2740
2741 nested_vmcb->save.es = vmcb->save.es;
2742 nested_vmcb->save.cs = vmcb->save.cs;
2743 nested_vmcb->save.ss = vmcb->save.ss;
2744 nested_vmcb->save.ds = vmcb->save.ds;
2745 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2746 nested_vmcb->save.idtr = vmcb->save.idtr;
2747 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2748 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2749 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2750 nested_vmcb->save.cr2 = vmcb->save.cr2;
2751 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2752 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2753 nested_vmcb->save.rip = vmcb->save.rip;
2754 nested_vmcb->save.rsp = vmcb->save.rsp;
2755 nested_vmcb->save.rax = vmcb->save.rax;
2756 nested_vmcb->save.dr7 = vmcb->save.dr7;
2757 nested_vmcb->save.dr6 = vmcb->save.dr6;
2758 nested_vmcb->save.cpl = vmcb->save.cpl;
2759
2760 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2761 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2762 nested_vmcb->control.int_state = vmcb->control.int_state;
2763 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2764 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2765 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2766 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2767 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2768 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2769
2770 if (svm->nrips_enabled)
2771 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2772
2773 /*
2774 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2775 * to make sure that we do not lose injected events. So check event_inj
2776 * here and copy it to exit_int_info if it is valid.
2777 * Exit_int_info and event_inj can't be both valid because the case
2778 * below only happens on a VMRUN instruction intercept which has
2779 * no valid exit_int_info set.
2780 */
2781 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2782 struct vmcb_control_area *nc = &nested_vmcb->control;
2783
2784 nc->exit_int_info = vmcb->control.event_inj;
2785 nc->exit_int_info_err = vmcb->control.event_inj_err;
2786 }
2787
2788 nested_vmcb->control.tlb_ctl = 0;
2789 nested_vmcb->control.event_inj = 0;
2790 nested_vmcb->control.event_inj_err = 0;
2791
2792 /* We always set V_INTR_MASKING and remember the old value in hflags */
2793 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2794 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2795
2796 /* Restore the original control entries */
2797 copy_vmcb_control_area(vmcb, hsave);
2798
2799 kvm_clear_exception_queue(&svm->vcpu);
2800 kvm_clear_interrupt_queue(&svm->vcpu);
2801
2802 svm->nested.nested_cr3 = 0;
2803
2804 /* Restore selected save entries */
2805 svm->vmcb->save.es = hsave->save.es;
2806 svm->vmcb->save.cs = hsave->save.cs;
2807 svm->vmcb->save.ss = hsave->save.ss;
2808 svm->vmcb->save.ds = hsave->save.ds;
2809 svm->vmcb->save.gdtr = hsave->save.gdtr;
2810 svm->vmcb->save.idtr = hsave->save.idtr;
2811 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2812 svm_set_efer(&svm->vcpu, hsave->save.efer);
2813 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2814 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2815 if (npt_enabled) {
2816 svm->vmcb->save.cr3 = hsave->save.cr3;
2817 svm->vcpu.arch.cr3 = hsave->save.cr3;
2818 } else {
2819 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2820 }
2821 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2822 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2823 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2824 svm->vmcb->save.dr7 = 0;
2825 svm->vmcb->save.cpl = 0;
2826 svm->vmcb->control.exit_int_info = 0;
2827
2828 mark_all_dirty(svm->vmcb);
2829
2830 nested_svm_unmap(page);
2831
2832 nested_svm_uninit_mmu_context(&svm->vcpu);
2833 kvm_mmu_reset_context(&svm->vcpu);
2834 kvm_mmu_load(&svm->vcpu);
2835
2836 return 0;
2837 }
2838
2839 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2840 {
2841 /*
2842 * This function merges the msr permission bitmaps of kvm and the
2843 * nested vmcb. It is optimized in that it only merges the parts where
2844 * the kvm msr permission bitmap may contain zero bits
2845 */
2846 int i;
2847
2848 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2849 return true;
2850
2851 for (i = 0; i < MSRPM_OFFSETS; i++) {
2852 u32 value, p;
2853 u64 offset;
2854
2855 if (msrpm_offsets[i] == 0xffffffff)
2856 break;
2857
2858 p = msrpm_offsets[i];
2859 offset = svm->nested.vmcb_msrpm + (p * 4);
2860
2861 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2862 return false;
2863
2864 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2865 }
2866
2867 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2868
2869 return true;
2870 }
2871
2872 static bool nested_vmcb_checks(struct vmcb *vmcb)
2873 {
2874 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2875 return false;
2876
2877 if (vmcb->control.asid == 0)
2878 return false;
2879
2880 if (vmcb->control.nested_ctl && !npt_enabled)
2881 return false;
2882
2883 return true;
2884 }
2885
2886 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2887 {
2888 struct vmcb *nested_vmcb;
2889 struct vmcb *hsave = svm->nested.hsave;
2890 struct vmcb *vmcb = svm->vmcb;
2891 struct page *page;
2892 u64 vmcb_gpa;
2893
2894 vmcb_gpa = svm->vmcb->save.rax;
2895
2896 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2897 if (!nested_vmcb)
2898 return false;
2899
2900 if (!nested_vmcb_checks(nested_vmcb)) {
2901 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2902 nested_vmcb->control.exit_code_hi = 0;
2903 nested_vmcb->control.exit_info_1 = 0;
2904 nested_vmcb->control.exit_info_2 = 0;
2905
2906 nested_svm_unmap(page);
2907
2908 return false;
2909 }
2910
2911 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2912 nested_vmcb->save.rip,
2913 nested_vmcb->control.int_ctl,
2914 nested_vmcb->control.event_inj,
2915 nested_vmcb->control.nested_ctl);
2916
2917 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2918 nested_vmcb->control.intercept_cr >> 16,
2919 nested_vmcb->control.intercept_exceptions,
2920 nested_vmcb->control.intercept);
2921
2922 /* Clear internal status */
2923 kvm_clear_exception_queue(&svm->vcpu);
2924 kvm_clear_interrupt_queue(&svm->vcpu);
2925
2926 /*
2927 * Save the old vmcb, so we don't need to pick what we save, but can
2928 * restore everything when a VMEXIT occurs
2929 */
2930 hsave->save.es = vmcb->save.es;
2931 hsave->save.cs = vmcb->save.cs;
2932 hsave->save.ss = vmcb->save.ss;
2933 hsave->save.ds = vmcb->save.ds;
2934 hsave->save.gdtr = vmcb->save.gdtr;
2935 hsave->save.idtr = vmcb->save.idtr;
2936 hsave->save.efer = svm->vcpu.arch.efer;
2937 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2938 hsave->save.cr4 = svm->vcpu.arch.cr4;
2939 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2940 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2941 hsave->save.rsp = vmcb->save.rsp;
2942 hsave->save.rax = vmcb->save.rax;
2943 if (npt_enabled)
2944 hsave->save.cr3 = vmcb->save.cr3;
2945 else
2946 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2947
2948 copy_vmcb_control_area(hsave, vmcb);
2949
2950 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2951 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2952 else
2953 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2954
2955 if (nested_vmcb->control.nested_ctl) {
2956 kvm_mmu_unload(&svm->vcpu);
2957 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2958 nested_svm_init_mmu_context(&svm->vcpu);
2959 }
2960
2961 /* Load the nested guest state */
2962 svm->vmcb->save.es = nested_vmcb->save.es;
2963 svm->vmcb->save.cs = nested_vmcb->save.cs;
2964 svm->vmcb->save.ss = nested_vmcb->save.ss;
2965 svm->vmcb->save.ds = nested_vmcb->save.ds;
2966 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2967 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2968 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2969 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2970 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2971 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2972 if (npt_enabled) {
2973 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2974 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2975 } else
2976 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2977
2978 /* Guest paging mode is active - reset mmu */
2979 kvm_mmu_reset_context(&svm->vcpu);
2980
2981 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2982 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2983 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2984 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2985
2986 /* In case we don't even reach vcpu_run, the fields are not updated */
2987 svm->vmcb->save.rax = nested_vmcb->save.rax;
2988 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2989 svm->vmcb->save.rip = nested_vmcb->save.rip;
2990 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2991 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2992 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2993
2994 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2995 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2996
2997 /* cache intercepts */
2998 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2999 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3000 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3001 svm->nested.intercept = nested_vmcb->control.intercept;
3002
3003 svm_flush_tlb(&svm->vcpu);
3004 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3005 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3006 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3007 else
3008 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3009
3010 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3011 /* We only want the cr8 intercept bits of the guest */
3012 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3013 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3014 }
3015
3016 /* We don't want to see VMMCALLs from a nested guest */
3017 clr_intercept(svm, INTERCEPT_VMMCALL);
3018
3019 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3020 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3021 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3022 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3023 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3024 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3025
3026 nested_svm_unmap(page);
3027
3028 /* Enter Guest-Mode */
3029 enter_guest_mode(&svm->vcpu);
3030
3031 /*
3032 * Merge guest and host intercepts - must be called with vcpu in
3033 * guest-mode to take affect here
3034 */
3035 recalc_intercepts(svm);
3036
3037 svm->nested.vmcb = vmcb_gpa;
3038
3039 enable_gif(svm);
3040
3041 mark_all_dirty(svm->vmcb);
3042
3043 return true;
3044 }
3045
3046 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3047 {
3048 to_vmcb->save.fs = from_vmcb->save.fs;
3049 to_vmcb->save.gs = from_vmcb->save.gs;
3050 to_vmcb->save.tr = from_vmcb->save.tr;
3051 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3052 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3053 to_vmcb->save.star = from_vmcb->save.star;
3054 to_vmcb->save.lstar = from_vmcb->save.lstar;
3055 to_vmcb->save.cstar = from_vmcb->save.cstar;
3056 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3057 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3058 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3059 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3060 }
3061
3062 static int vmload_interception(struct vcpu_svm *svm)
3063 {
3064 struct vmcb *nested_vmcb;
3065 struct page *page;
3066 int ret;
3067
3068 if (nested_svm_check_permissions(svm))
3069 return 1;
3070
3071 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3072 if (!nested_vmcb)
3073 return 1;
3074
3075 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3076 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3077
3078 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3079 nested_svm_unmap(page);
3080
3081 return ret;
3082 }
3083
3084 static int vmsave_interception(struct vcpu_svm *svm)
3085 {
3086 struct vmcb *nested_vmcb;
3087 struct page *page;
3088 int ret;
3089
3090 if (nested_svm_check_permissions(svm))
3091 return 1;
3092
3093 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3094 if (!nested_vmcb)
3095 return 1;
3096
3097 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3098 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3099
3100 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3101 nested_svm_unmap(page);
3102
3103 return ret;
3104 }
3105
3106 static int vmrun_interception(struct vcpu_svm *svm)
3107 {
3108 if (nested_svm_check_permissions(svm))
3109 return 1;
3110
3111 /* Save rip after vmrun instruction */
3112 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3113
3114 if (!nested_svm_vmrun(svm))
3115 return 1;
3116
3117 if (!nested_svm_vmrun_msrpm(svm))
3118 goto failed;
3119
3120 return 1;
3121
3122 failed:
3123
3124 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3125 svm->vmcb->control.exit_code_hi = 0;
3126 svm->vmcb->control.exit_info_1 = 0;
3127 svm->vmcb->control.exit_info_2 = 0;
3128
3129 nested_svm_vmexit(svm);
3130
3131 return 1;
3132 }
3133
3134 static int stgi_interception(struct vcpu_svm *svm)
3135 {
3136 int ret;
3137
3138 if (nested_svm_check_permissions(svm))
3139 return 1;
3140
3141 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3142 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3143 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3144
3145 enable_gif(svm);
3146
3147 return ret;
3148 }
3149
3150 static int clgi_interception(struct vcpu_svm *svm)
3151 {
3152 int ret;
3153
3154 if (nested_svm_check_permissions(svm))
3155 return 1;
3156
3157 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3158 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3159
3160 disable_gif(svm);
3161
3162 /* After a CLGI no interrupts should come */
3163 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3164 svm_clear_vintr(svm);
3165 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3166 mark_dirty(svm->vmcb, VMCB_INTR);
3167 }
3168
3169 return ret;
3170 }
3171
3172 static int invlpga_interception(struct vcpu_svm *svm)
3173 {
3174 struct kvm_vcpu *vcpu = &svm->vcpu;
3175
3176 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3177 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3178
3179 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3180 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3181
3182 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3183 return kvm_skip_emulated_instruction(&svm->vcpu);
3184 }
3185
3186 static int skinit_interception(struct vcpu_svm *svm)
3187 {
3188 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3189
3190 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3191 return 1;
3192 }
3193
3194 static int wbinvd_interception(struct vcpu_svm *svm)
3195 {
3196 return kvm_emulate_wbinvd(&svm->vcpu);
3197 }
3198
3199 static int xsetbv_interception(struct vcpu_svm *svm)
3200 {
3201 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3202 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3203
3204 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3205 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3206 return kvm_skip_emulated_instruction(&svm->vcpu);
3207 }
3208
3209 return 1;
3210 }
3211
3212 static int task_switch_interception(struct vcpu_svm *svm)
3213 {
3214 u16 tss_selector;
3215 int reason;
3216 int int_type = svm->vmcb->control.exit_int_info &
3217 SVM_EXITINTINFO_TYPE_MASK;
3218 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3219 uint32_t type =
3220 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3221 uint32_t idt_v =
3222 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3223 bool has_error_code = false;
3224 u32 error_code = 0;
3225
3226 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3227
3228 if (svm->vmcb->control.exit_info_2 &
3229 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3230 reason = TASK_SWITCH_IRET;
3231 else if (svm->vmcb->control.exit_info_2 &
3232 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3233 reason = TASK_SWITCH_JMP;
3234 else if (idt_v)
3235 reason = TASK_SWITCH_GATE;
3236 else
3237 reason = TASK_SWITCH_CALL;
3238
3239 if (reason == TASK_SWITCH_GATE) {
3240 switch (type) {
3241 case SVM_EXITINTINFO_TYPE_NMI:
3242 svm->vcpu.arch.nmi_injected = false;
3243 break;
3244 case SVM_EXITINTINFO_TYPE_EXEPT:
3245 if (svm->vmcb->control.exit_info_2 &
3246 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3247 has_error_code = true;
3248 error_code =
3249 (u32)svm->vmcb->control.exit_info_2;
3250 }
3251 kvm_clear_exception_queue(&svm->vcpu);
3252 break;
3253 case SVM_EXITINTINFO_TYPE_INTR:
3254 kvm_clear_interrupt_queue(&svm->vcpu);
3255 break;
3256 default:
3257 break;
3258 }
3259 }
3260
3261 if (reason != TASK_SWITCH_GATE ||
3262 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3263 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3264 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3265 skip_emulated_instruction(&svm->vcpu);
3266
3267 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3268 int_vec = -1;
3269
3270 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3271 has_error_code, error_code) == EMULATE_FAIL) {
3272 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3273 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3274 svm->vcpu.run->internal.ndata = 0;
3275 return 0;
3276 }
3277 return 1;
3278 }
3279
3280 static int cpuid_interception(struct vcpu_svm *svm)
3281 {
3282 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3283 return kvm_emulate_cpuid(&svm->vcpu);
3284 }
3285
3286 static int iret_interception(struct vcpu_svm *svm)
3287 {
3288 ++svm->vcpu.stat.nmi_window_exits;
3289 clr_intercept(svm, INTERCEPT_IRET);
3290 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3291 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3292 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3293 return 1;
3294 }
3295
3296 static int invlpg_interception(struct vcpu_svm *svm)
3297 {
3298 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3299 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3300
3301 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3302 return kvm_skip_emulated_instruction(&svm->vcpu);
3303 }
3304
3305 static int emulate_on_interception(struct vcpu_svm *svm)
3306 {
3307 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3308 }
3309
3310 static int rdpmc_interception(struct vcpu_svm *svm)
3311 {
3312 int err;
3313
3314 if (!static_cpu_has(X86_FEATURE_NRIPS))
3315 return emulate_on_interception(svm);
3316
3317 err = kvm_rdpmc(&svm->vcpu);
3318 return kvm_complete_insn_gp(&svm->vcpu, err);
3319 }
3320
3321 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3322 unsigned long val)
3323 {
3324 unsigned long cr0 = svm->vcpu.arch.cr0;
3325 bool ret = false;
3326 u64 intercept;
3327
3328 intercept = svm->nested.intercept;
3329
3330 if (!is_guest_mode(&svm->vcpu) ||
3331 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3332 return false;
3333
3334 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3335 val &= ~SVM_CR0_SELECTIVE_MASK;
3336
3337 if (cr0 ^ val) {
3338 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3339 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3340 }
3341
3342 return ret;
3343 }
3344
3345 #define CR_VALID (1ULL << 63)
3346
3347 static int cr_interception(struct vcpu_svm *svm)
3348 {
3349 int reg, cr;
3350 unsigned long val;
3351 int err;
3352
3353 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3354 return emulate_on_interception(svm);
3355
3356 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3357 return emulate_on_interception(svm);
3358
3359 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3360 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3361 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3362 else
3363 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3364
3365 err = 0;
3366 if (cr >= 16) { /* mov to cr */
3367 cr -= 16;
3368 val = kvm_register_read(&svm->vcpu, reg);
3369 switch (cr) {
3370 case 0:
3371 if (!check_selective_cr0_intercepted(svm, val))
3372 err = kvm_set_cr0(&svm->vcpu, val);
3373 else
3374 return 1;
3375
3376 break;
3377 case 3:
3378 err = kvm_set_cr3(&svm->vcpu, val);
3379 break;
3380 case 4:
3381 err = kvm_set_cr4(&svm->vcpu, val);
3382 break;
3383 case 8:
3384 err = kvm_set_cr8(&svm->vcpu, val);
3385 break;
3386 default:
3387 WARN(1, "unhandled write to CR%d", cr);
3388 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3389 return 1;
3390 }
3391 } else { /* mov from cr */
3392 switch (cr) {
3393 case 0:
3394 val = kvm_read_cr0(&svm->vcpu);
3395 break;
3396 case 2:
3397 val = svm->vcpu.arch.cr2;
3398 break;
3399 case 3:
3400 val = kvm_read_cr3(&svm->vcpu);
3401 break;
3402 case 4:
3403 val = kvm_read_cr4(&svm->vcpu);
3404 break;
3405 case 8:
3406 val = kvm_get_cr8(&svm->vcpu);
3407 break;
3408 default:
3409 WARN(1, "unhandled read from CR%d", cr);
3410 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3411 return 1;
3412 }
3413 kvm_register_write(&svm->vcpu, reg, val);
3414 }
3415 return kvm_complete_insn_gp(&svm->vcpu, err);
3416 }
3417
3418 static int dr_interception(struct vcpu_svm *svm)
3419 {
3420 int reg, dr;
3421 unsigned long val;
3422
3423 if (svm->vcpu.guest_debug == 0) {
3424 /*
3425 * No more DR vmexits; force a reload of the debug registers
3426 * and reenter on this instruction. The next vmexit will
3427 * retrieve the full state of the debug registers.
3428 */
3429 clr_dr_intercepts(svm);
3430 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3431 return 1;
3432 }
3433
3434 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3435 return emulate_on_interception(svm);
3436
3437 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3438 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3439
3440 if (dr >= 16) { /* mov to DRn */
3441 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3442 return 1;
3443 val = kvm_register_read(&svm->vcpu, reg);
3444 kvm_set_dr(&svm->vcpu, dr - 16, val);
3445 } else {
3446 if (!kvm_require_dr(&svm->vcpu, dr))
3447 return 1;
3448 kvm_get_dr(&svm->vcpu, dr, &val);
3449 kvm_register_write(&svm->vcpu, reg, val);
3450 }
3451
3452 return kvm_skip_emulated_instruction(&svm->vcpu);
3453 }
3454
3455 static int cr8_write_interception(struct vcpu_svm *svm)
3456 {
3457 struct kvm_run *kvm_run = svm->vcpu.run;
3458 int r;
3459
3460 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3461 /* instruction emulation calls kvm_set_cr8() */
3462 r = cr_interception(svm);
3463 if (lapic_in_kernel(&svm->vcpu))
3464 return r;
3465 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3466 return r;
3467 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3468 return 0;
3469 }
3470
3471 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3472 {
3473 struct vcpu_svm *svm = to_svm(vcpu);
3474
3475 switch (msr_info->index) {
3476 case MSR_IA32_TSC: {
3477 msr_info->data = svm->vmcb->control.tsc_offset +
3478 kvm_scale_tsc(vcpu, rdtsc());
3479
3480 break;
3481 }
3482 case MSR_STAR:
3483 msr_info->data = svm->vmcb->save.star;
3484 break;
3485 #ifdef CONFIG_X86_64
3486 case MSR_LSTAR:
3487 msr_info->data = svm->vmcb->save.lstar;
3488 break;
3489 case MSR_CSTAR:
3490 msr_info->data = svm->vmcb->save.cstar;
3491 break;
3492 case MSR_KERNEL_GS_BASE:
3493 msr_info->data = svm->vmcb->save.kernel_gs_base;
3494 break;
3495 case MSR_SYSCALL_MASK:
3496 msr_info->data = svm->vmcb->save.sfmask;
3497 break;
3498 #endif
3499 case MSR_IA32_SYSENTER_CS:
3500 msr_info->data = svm->vmcb->save.sysenter_cs;
3501 break;
3502 case MSR_IA32_SYSENTER_EIP:
3503 msr_info->data = svm->sysenter_eip;
3504 break;
3505 case MSR_IA32_SYSENTER_ESP:
3506 msr_info->data = svm->sysenter_esp;
3507 break;
3508 case MSR_TSC_AUX:
3509 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3510 return 1;
3511 msr_info->data = svm->tsc_aux;
3512 break;
3513 /*
3514 * Nobody will change the following 5 values in the VMCB so we can
3515 * safely return them on rdmsr. They will always be 0 until LBRV is
3516 * implemented.
3517 */
3518 case MSR_IA32_DEBUGCTLMSR:
3519 msr_info->data = svm->vmcb->save.dbgctl;
3520 break;
3521 case MSR_IA32_LASTBRANCHFROMIP:
3522 msr_info->data = svm->vmcb->save.br_from;
3523 break;
3524 case MSR_IA32_LASTBRANCHTOIP:
3525 msr_info->data = svm->vmcb->save.br_to;
3526 break;
3527 case MSR_IA32_LASTINTFROMIP:
3528 msr_info->data = svm->vmcb->save.last_excp_from;
3529 break;
3530 case MSR_IA32_LASTINTTOIP:
3531 msr_info->data = svm->vmcb->save.last_excp_to;
3532 break;
3533 case MSR_VM_HSAVE_PA:
3534 msr_info->data = svm->nested.hsave_msr;
3535 break;
3536 case MSR_VM_CR:
3537 msr_info->data = svm->nested.vm_cr_msr;
3538 break;
3539 case MSR_IA32_UCODE_REV:
3540 msr_info->data = 0x01000065;
3541 break;
3542 case MSR_F15H_IC_CFG: {
3543
3544 int family, model;
3545
3546 family = guest_cpuid_family(vcpu);
3547 model = guest_cpuid_model(vcpu);
3548
3549 if (family < 0 || model < 0)
3550 return kvm_get_msr_common(vcpu, msr_info);
3551
3552 msr_info->data = 0;
3553
3554 if (family == 0x15 &&
3555 (model >= 0x2 && model < 0x20))
3556 msr_info->data = 0x1E;
3557 }
3558 break;
3559 default:
3560 return kvm_get_msr_common(vcpu, msr_info);
3561 }
3562 return 0;
3563 }
3564
3565 static int rdmsr_interception(struct vcpu_svm *svm)
3566 {
3567 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3568 struct msr_data msr_info;
3569
3570 msr_info.index = ecx;
3571 msr_info.host_initiated = false;
3572 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3573 trace_kvm_msr_read_ex(ecx);
3574 kvm_inject_gp(&svm->vcpu, 0);
3575 return 1;
3576 } else {
3577 trace_kvm_msr_read(ecx, msr_info.data);
3578
3579 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3580 msr_info.data & 0xffffffff);
3581 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3582 msr_info.data >> 32);
3583 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3584 return kvm_skip_emulated_instruction(&svm->vcpu);
3585 }
3586 }
3587
3588 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3589 {
3590 struct vcpu_svm *svm = to_svm(vcpu);
3591 int svm_dis, chg_mask;
3592
3593 if (data & ~SVM_VM_CR_VALID_MASK)
3594 return 1;
3595
3596 chg_mask = SVM_VM_CR_VALID_MASK;
3597
3598 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3599 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3600
3601 svm->nested.vm_cr_msr &= ~chg_mask;
3602 svm->nested.vm_cr_msr |= (data & chg_mask);
3603
3604 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3605
3606 /* check for svm_disable while efer.svme is set */
3607 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3608 return 1;
3609
3610 return 0;
3611 }
3612
3613 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3614 {
3615 struct vcpu_svm *svm = to_svm(vcpu);
3616
3617 u32 ecx = msr->index;
3618 u64 data = msr->data;
3619 switch (ecx) {
3620 case MSR_IA32_TSC:
3621 kvm_write_tsc(vcpu, msr);
3622 break;
3623 case MSR_STAR:
3624 svm->vmcb->save.star = data;
3625 break;
3626 #ifdef CONFIG_X86_64
3627 case MSR_LSTAR:
3628 svm->vmcb->save.lstar = data;
3629 break;
3630 case MSR_CSTAR:
3631 svm->vmcb->save.cstar = data;
3632 break;
3633 case MSR_KERNEL_GS_BASE:
3634 svm->vmcb->save.kernel_gs_base = data;
3635 break;
3636 case MSR_SYSCALL_MASK:
3637 svm->vmcb->save.sfmask = data;
3638 break;
3639 #endif
3640 case MSR_IA32_SYSENTER_CS:
3641 svm->vmcb->save.sysenter_cs = data;
3642 break;
3643 case MSR_IA32_SYSENTER_EIP:
3644 svm->sysenter_eip = data;
3645 svm->vmcb->save.sysenter_eip = data;
3646 break;
3647 case MSR_IA32_SYSENTER_ESP:
3648 svm->sysenter_esp = data;
3649 svm->vmcb->save.sysenter_esp = data;
3650 break;
3651 case MSR_TSC_AUX:
3652 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3653 return 1;
3654
3655 /*
3656 * This is rare, so we update the MSR here instead of using
3657 * direct_access_msrs. Doing that would require a rdmsr in
3658 * svm_vcpu_put.
3659 */
3660 svm->tsc_aux = data;
3661 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3662 break;
3663 case MSR_IA32_DEBUGCTLMSR:
3664 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3665 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3666 __func__, data);
3667 break;
3668 }
3669 if (data & DEBUGCTL_RESERVED_BITS)
3670 return 1;
3671
3672 svm->vmcb->save.dbgctl = data;
3673 mark_dirty(svm->vmcb, VMCB_LBR);
3674 if (data & (1ULL<<0))
3675 svm_enable_lbrv(svm);
3676 else
3677 svm_disable_lbrv(svm);
3678 break;
3679 case MSR_VM_HSAVE_PA:
3680 svm->nested.hsave_msr = data;
3681 break;
3682 case MSR_VM_CR:
3683 return svm_set_vm_cr(vcpu, data);
3684 case MSR_VM_IGNNE:
3685 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3686 break;
3687 case MSR_IA32_APICBASE:
3688 if (kvm_vcpu_apicv_active(vcpu))
3689 avic_update_vapic_bar(to_svm(vcpu), data);
3690 /* Follow through */
3691 default:
3692 return kvm_set_msr_common(vcpu, msr);
3693 }
3694 return 0;
3695 }
3696
3697 static int wrmsr_interception(struct vcpu_svm *svm)
3698 {
3699 struct msr_data msr;
3700 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3701 u64 data = kvm_read_edx_eax(&svm->vcpu);
3702
3703 msr.data = data;
3704 msr.index = ecx;
3705 msr.host_initiated = false;
3706
3707 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3708 if (kvm_set_msr(&svm->vcpu, &msr)) {
3709 trace_kvm_msr_write_ex(ecx, data);
3710 kvm_inject_gp(&svm->vcpu, 0);
3711 return 1;
3712 } else {
3713 trace_kvm_msr_write(ecx, data);
3714 return kvm_skip_emulated_instruction(&svm->vcpu);
3715 }
3716 }
3717
3718 static int msr_interception(struct vcpu_svm *svm)
3719 {
3720 if (svm->vmcb->control.exit_info_1)
3721 return wrmsr_interception(svm);
3722 else
3723 return rdmsr_interception(svm);
3724 }
3725
3726 static int interrupt_window_interception(struct vcpu_svm *svm)
3727 {
3728 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3729 svm_clear_vintr(svm);
3730 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3731 mark_dirty(svm->vmcb, VMCB_INTR);
3732 ++svm->vcpu.stat.irq_window_exits;
3733 return 1;
3734 }
3735
3736 static int pause_interception(struct vcpu_svm *svm)
3737 {
3738 kvm_vcpu_on_spin(&(svm->vcpu));
3739 return 1;
3740 }
3741
3742 static int nop_interception(struct vcpu_svm *svm)
3743 {
3744 return kvm_skip_emulated_instruction(&(svm->vcpu));
3745 }
3746
3747 static int monitor_interception(struct vcpu_svm *svm)
3748 {
3749 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3750 return nop_interception(svm);
3751 }
3752
3753 static int mwait_interception(struct vcpu_svm *svm)
3754 {
3755 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3756 return nop_interception(svm);
3757 }
3758
3759 enum avic_ipi_failure_cause {
3760 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3761 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3762 AVIC_IPI_FAILURE_INVALID_TARGET,
3763 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3764 };
3765
3766 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3767 {
3768 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3769 u32 icrl = svm->vmcb->control.exit_info_1;
3770 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3771 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3772 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3773
3774 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3775
3776 switch (id) {
3777 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3778 /*
3779 * AVIC hardware handles the generation of
3780 * IPIs when the specified Message Type is Fixed
3781 * (also known as fixed delivery mode) and
3782 * the Trigger Mode is edge-triggered. The hardware
3783 * also supports self and broadcast delivery modes
3784 * specified via the Destination Shorthand(DSH)
3785 * field of the ICRL. Logical and physical APIC ID
3786 * formats are supported. All other IPI types cause
3787 * a #VMEXIT, which needs to emulated.
3788 */
3789 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3790 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3791 break;
3792 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3793 int i;
3794 struct kvm_vcpu *vcpu;
3795 struct kvm *kvm = svm->vcpu.kvm;
3796 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3797
3798 /*
3799 * At this point, we expect that the AVIC HW has already
3800 * set the appropriate IRR bits on the valid target
3801 * vcpus. So, we just need to kick the appropriate vcpu.
3802 */
3803 kvm_for_each_vcpu(i, vcpu, kvm) {
3804 bool m = kvm_apic_match_dest(vcpu, apic,
3805 icrl & KVM_APIC_SHORT_MASK,
3806 GET_APIC_DEST_FIELD(icrh),
3807 icrl & KVM_APIC_DEST_MASK);
3808
3809 if (m && !avic_vcpu_is_running(vcpu))
3810 kvm_vcpu_wake_up(vcpu);
3811 }
3812 break;
3813 }
3814 case AVIC_IPI_FAILURE_INVALID_TARGET:
3815 break;
3816 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3817 WARN_ONCE(1, "Invalid backing page\n");
3818 break;
3819 default:
3820 pr_err("Unknown IPI interception\n");
3821 }
3822
3823 return 1;
3824 }
3825
3826 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3827 {
3828 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3829 int index;
3830 u32 *logical_apic_id_table;
3831 int dlid = GET_APIC_LOGICAL_ID(ldr);
3832
3833 if (!dlid)
3834 return NULL;
3835
3836 if (flat) { /* flat */
3837 index = ffs(dlid) - 1;
3838 if (index > 7)
3839 return NULL;
3840 } else { /* cluster */
3841 int cluster = (dlid & 0xf0) >> 4;
3842 int apic = ffs(dlid & 0x0f) - 1;
3843
3844 if ((apic < 0) || (apic > 7) ||
3845 (cluster >= 0xf))
3846 return NULL;
3847 index = (cluster << 2) + apic;
3848 }
3849
3850 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3851
3852 return &logical_apic_id_table[index];
3853 }
3854
3855 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3856 bool valid)
3857 {
3858 bool flat;
3859 u32 *entry, new_entry;
3860
3861 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3862 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3863 if (!entry)
3864 return -EINVAL;
3865
3866 new_entry = READ_ONCE(*entry);
3867 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3868 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3869 if (valid)
3870 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3871 else
3872 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3873 WRITE_ONCE(*entry, new_entry);
3874
3875 return 0;
3876 }
3877
3878 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3879 {
3880 int ret;
3881 struct vcpu_svm *svm = to_svm(vcpu);
3882 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3883
3884 if (!ldr)
3885 return 1;
3886
3887 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3888 if (ret && svm->ldr_reg) {
3889 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3890 svm->ldr_reg = 0;
3891 } else {
3892 svm->ldr_reg = ldr;
3893 }
3894 return ret;
3895 }
3896
3897 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3898 {
3899 u64 *old, *new;
3900 struct vcpu_svm *svm = to_svm(vcpu);
3901 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3902 u32 id = (apic_id_reg >> 24) & 0xff;
3903
3904 if (vcpu->vcpu_id == id)
3905 return 0;
3906
3907 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3908 new = avic_get_physical_id_entry(vcpu, id);
3909 if (!new || !old)
3910 return 1;
3911
3912 /* We need to move physical_id_entry to new offset */
3913 *new = *old;
3914 *old = 0ULL;
3915 to_svm(vcpu)->avic_physical_id_cache = new;
3916
3917 /*
3918 * Also update the guest physical APIC ID in the logical
3919 * APIC ID table entry if already setup the LDR.
3920 */
3921 if (svm->ldr_reg)
3922 avic_handle_ldr_update(vcpu);
3923
3924 return 0;
3925 }
3926
3927 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3928 {
3929 struct vcpu_svm *svm = to_svm(vcpu);
3930 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3931 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3932 u32 mod = (dfr >> 28) & 0xf;
3933
3934 /*
3935 * We assume that all local APICs are using the same type.
3936 * If this changes, we need to flush the AVIC logical
3937 * APID id table.
3938 */
3939 if (vm_data->ldr_mode == mod)
3940 return 0;
3941
3942 clear_page(page_address(vm_data->avic_logical_id_table_page));
3943 vm_data->ldr_mode = mod;
3944
3945 if (svm->ldr_reg)
3946 avic_handle_ldr_update(vcpu);
3947 return 0;
3948 }
3949
3950 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3951 {
3952 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3953 u32 offset = svm->vmcb->control.exit_info_1 &
3954 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3955
3956 switch (offset) {
3957 case APIC_ID:
3958 if (avic_handle_apic_id_update(&svm->vcpu))
3959 return 0;
3960 break;
3961 case APIC_LDR:
3962 if (avic_handle_ldr_update(&svm->vcpu))
3963 return 0;
3964 break;
3965 case APIC_DFR:
3966 avic_handle_dfr_update(&svm->vcpu);
3967 break;
3968 default:
3969 break;
3970 }
3971
3972 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
3973
3974 return 1;
3975 }
3976
3977 static bool is_avic_unaccelerated_access_trap(u32 offset)
3978 {
3979 bool ret = false;
3980
3981 switch (offset) {
3982 case APIC_ID:
3983 case APIC_EOI:
3984 case APIC_RRR:
3985 case APIC_LDR:
3986 case APIC_DFR:
3987 case APIC_SPIV:
3988 case APIC_ESR:
3989 case APIC_ICR:
3990 case APIC_LVTT:
3991 case APIC_LVTTHMR:
3992 case APIC_LVTPC:
3993 case APIC_LVT0:
3994 case APIC_LVT1:
3995 case APIC_LVTERR:
3996 case APIC_TMICT:
3997 case APIC_TDCR:
3998 ret = true;
3999 break;
4000 default:
4001 break;
4002 }
4003 return ret;
4004 }
4005
4006 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4007 {
4008 int ret = 0;
4009 u32 offset = svm->vmcb->control.exit_info_1 &
4010 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4011 u32 vector = svm->vmcb->control.exit_info_2 &
4012 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4013 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4014 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4015 bool trap = is_avic_unaccelerated_access_trap(offset);
4016
4017 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4018 trap, write, vector);
4019 if (trap) {
4020 /* Handling Trap */
4021 WARN_ONCE(!write, "svm: Handling trap read.\n");
4022 ret = avic_unaccel_trap_write(svm);
4023 } else {
4024 /* Handling Fault */
4025 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4026 }
4027
4028 return ret;
4029 }
4030
4031 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4032 [SVM_EXIT_READ_CR0] = cr_interception,
4033 [SVM_EXIT_READ_CR3] = cr_interception,
4034 [SVM_EXIT_READ_CR4] = cr_interception,
4035 [SVM_EXIT_READ_CR8] = cr_interception,
4036 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4037 [SVM_EXIT_WRITE_CR0] = cr_interception,
4038 [SVM_EXIT_WRITE_CR3] = cr_interception,
4039 [SVM_EXIT_WRITE_CR4] = cr_interception,
4040 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4041 [SVM_EXIT_READ_DR0] = dr_interception,
4042 [SVM_EXIT_READ_DR1] = dr_interception,
4043 [SVM_EXIT_READ_DR2] = dr_interception,
4044 [SVM_EXIT_READ_DR3] = dr_interception,
4045 [SVM_EXIT_READ_DR4] = dr_interception,
4046 [SVM_EXIT_READ_DR5] = dr_interception,
4047 [SVM_EXIT_READ_DR6] = dr_interception,
4048 [SVM_EXIT_READ_DR7] = dr_interception,
4049 [SVM_EXIT_WRITE_DR0] = dr_interception,
4050 [SVM_EXIT_WRITE_DR1] = dr_interception,
4051 [SVM_EXIT_WRITE_DR2] = dr_interception,
4052 [SVM_EXIT_WRITE_DR3] = dr_interception,
4053 [SVM_EXIT_WRITE_DR4] = dr_interception,
4054 [SVM_EXIT_WRITE_DR5] = dr_interception,
4055 [SVM_EXIT_WRITE_DR6] = dr_interception,
4056 [SVM_EXIT_WRITE_DR7] = dr_interception,
4057 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4058 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4059 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4060 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4061 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4062 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4063 [SVM_EXIT_INTR] = intr_interception,
4064 [SVM_EXIT_NMI] = nmi_interception,
4065 [SVM_EXIT_SMI] = nop_on_interception,
4066 [SVM_EXIT_INIT] = nop_on_interception,
4067 [SVM_EXIT_VINTR] = interrupt_window_interception,
4068 [SVM_EXIT_RDPMC] = rdpmc_interception,
4069 [SVM_EXIT_CPUID] = cpuid_interception,
4070 [SVM_EXIT_IRET] = iret_interception,
4071 [SVM_EXIT_INVD] = emulate_on_interception,
4072 [SVM_EXIT_PAUSE] = pause_interception,
4073 [SVM_EXIT_HLT] = halt_interception,
4074 [SVM_EXIT_INVLPG] = invlpg_interception,
4075 [SVM_EXIT_INVLPGA] = invlpga_interception,
4076 [SVM_EXIT_IOIO] = io_interception,
4077 [SVM_EXIT_MSR] = msr_interception,
4078 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4079 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4080 [SVM_EXIT_VMRUN] = vmrun_interception,
4081 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4082 [SVM_EXIT_VMLOAD] = vmload_interception,
4083 [SVM_EXIT_VMSAVE] = vmsave_interception,
4084 [SVM_EXIT_STGI] = stgi_interception,
4085 [SVM_EXIT_CLGI] = clgi_interception,
4086 [SVM_EXIT_SKINIT] = skinit_interception,
4087 [SVM_EXIT_WBINVD] = wbinvd_interception,
4088 [SVM_EXIT_MONITOR] = monitor_interception,
4089 [SVM_EXIT_MWAIT] = mwait_interception,
4090 [SVM_EXIT_XSETBV] = xsetbv_interception,
4091 [SVM_EXIT_NPF] = pf_interception,
4092 [SVM_EXIT_RSM] = emulate_on_interception,
4093 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4094 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4095 };
4096
4097 static void dump_vmcb(struct kvm_vcpu *vcpu)
4098 {
4099 struct vcpu_svm *svm = to_svm(vcpu);
4100 struct vmcb_control_area *control = &svm->vmcb->control;
4101 struct vmcb_save_area *save = &svm->vmcb->save;
4102
4103 pr_err("VMCB Control Area:\n");
4104 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4105 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4106 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4107 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4108 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4109 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4110 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4111 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4112 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4113 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4114 pr_err("%-20s%d\n", "asid:", control->asid);
4115 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4116 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4117 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4118 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4119 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4120 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4121 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4122 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4123 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4124 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4125 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4126 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4127 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4128 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4129 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4130 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4131 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4132 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4133 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4134 pr_err("VMCB State Save Area:\n");
4135 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4136 "es:",
4137 save->es.selector, save->es.attrib,
4138 save->es.limit, save->es.base);
4139 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4140 "cs:",
4141 save->cs.selector, save->cs.attrib,
4142 save->cs.limit, save->cs.base);
4143 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4144 "ss:",
4145 save->ss.selector, save->ss.attrib,
4146 save->ss.limit, save->ss.base);
4147 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4148 "ds:",
4149 save->ds.selector, save->ds.attrib,
4150 save->ds.limit, save->ds.base);
4151 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4152 "fs:",
4153 save->fs.selector, save->fs.attrib,
4154 save->fs.limit, save->fs.base);
4155 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4156 "gs:",
4157 save->gs.selector, save->gs.attrib,
4158 save->gs.limit, save->gs.base);
4159 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4160 "gdtr:",
4161 save->gdtr.selector, save->gdtr.attrib,
4162 save->gdtr.limit, save->gdtr.base);
4163 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4164 "ldtr:",
4165 save->ldtr.selector, save->ldtr.attrib,
4166 save->ldtr.limit, save->ldtr.base);
4167 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4168 "idtr:",
4169 save->idtr.selector, save->idtr.attrib,
4170 save->idtr.limit, save->idtr.base);
4171 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4172 "tr:",
4173 save->tr.selector, save->tr.attrib,
4174 save->tr.limit, save->tr.base);
4175 pr_err("cpl: %d efer: %016llx\n",
4176 save->cpl, save->efer);
4177 pr_err("%-15s %016llx %-13s %016llx\n",
4178 "cr0:", save->cr0, "cr2:", save->cr2);
4179 pr_err("%-15s %016llx %-13s %016llx\n",
4180 "cr3:", save->cr3, "cr4:", save->cr4);
4181 pr_err("%-15s %016llx %-13s %016llx\n",
4182 "dr6:", save->dr6, "dr7:", save->dr7);
4183 pr_err("%-15s %016llx %-13s %016llx\n",
4184 "rip:", save->rip, "rflags:", save->rflags);
4185 pr_err("%-15s %016llx %-13s %016llx\n",
4186 "rsp:", save->rsp, "rax:", save->rax);
4187 pr_err("%-15s %016llx %-13s %016llx\n",
4188 "star:", save->star, "lstar:", save->lstar);
4189 pr_err("%-15s %016llx %-13s %016llx\n",
4190 "cstar:", save->cstar, "sfmask:", save->sfmask);
4191 pr_err("%-15s %016llx %-13s %016llx\n",
4192 "kernel_gs_base:", save->kernel_gs_base,
4193 "sysenter_cs:", save->sysenter_cs);
4194 pr_err("%-15s %016llx %-13s %016llx\n",
4195 "sysenter_esp:", save->sysenter_esp,
4196 "sysenter_eip:", save->sysenter_eip);
4197 pr_err("%-15s %016llx %-13s %016llx\n",
4198 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4199 pr_err("%-15s %016llx %-13s %016llx\n",
4200 "br_from:", save->br_from, "br_to:", save->br_to);
4201 pr_err("%-15s %016llx %-13s %016llx\n",
4202 "excp_from:", save->last_excp_from,
4203 "excp_to:", save->last_excp_to);
4204 }
4205
4206 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4207 {
4208 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4209
4210 *info1 = control->exit_info_1;
4211 *info2 = control->exit_info_2;
4212 }
4213
4214 static int handle_exit(struct kvm_vcpu *vcpu)
4215 {
4216 struct vcpu_svm *svm = to_svm(vcpu);
4217 struct kvm_run *kvm_run = vcpu->run;
4218 u32 exit_code = svm->vmcb->control.exit_code;
4219
4220 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4221
4222 vcpu->arch.gpa_available = (exit_code == SVM_EXIT_NPF);
4223
4224 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4225 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4226 if (npt_enabled)
4227 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4228
4229 if (unlikely(svm->nested.exit_required)) {
4230 nested_svm_vmexit(svm);
4231 svm->nested.exit_required = false;
4232
4233 return 1;
4234 }
4235
4236 if (is_guest_mode(vcpu)) {
4237 int vmexit;
4238
4239 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4240 svm->vmcb->control.exit_info_1,
4241 svm->vmcb->control.exit_info_2,
4242 svm->vmcb->control.exit_int_info,
4243 svm->vmcb->control.exit_int_info_err,
4244 KVM_ISA_SVM);
4245
4246 vmexit = nested_svm_exit_special(svm);
4247
4248 if (vmexit == NESTED_EXIT_CONTINUE)
4249 vmexit = nested_svm_exit_handled(svm);
4250
4251 if (vmexit == NESTED_EXIT_DONE)
4252 return 1;
4253 }
4254
4255 svm_complete_interrupts(svm);
4256
4257 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4258 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4259 kvm_run->fail_entry.hardware_entry_failure_reason
4260 = svm->vmcb->control.exit_code;
4261 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4262 dump_vmcb(vcpu);
4263 return 0;
4264 }
4265
4266 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4267 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4268 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4269 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4270 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4271 "exit_code 0x%x\n",
4272 __func__, svm->vmcb->control.exit_int_info,
4273 exit_code);
4274
4275 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4276 || !svm_exit_handlers[exit_code]) {
4277 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4278 kvm_queue_exception(vcpu, UD_VECTOR);
4279 return 1;
4280 }
4281
4282 return svm_exit_handlers[exit_code](svm);
4283 }
4284
4285 static void reload_tss(struct kvm_vcpu *vcpu)
4286 {
4287 int cpu = raw_smp_processor_id();
4288
4289 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4290 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4291 load_TR_desc();
4292 }
4293
4294 static void pre_svm_run(struct vcpu_svm *svm)
4295 {
4296 int cpu = raw_smp_processor_id();
4297
4298 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4299
4300 /* FIXME: handle wraparound of asid_generation */
4301 if (svm->asid_generation != sd->asid_generation)
4302 new_asid(svm, sd);
4303 }
4304
4305 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4306 {
4307 struct vcpu_svm *svm = to_svm(vcpu);
4308
4309 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4310 vcpu->arch.hflags |= HF_NMI_MASK;
4311 set_intercept(svm, INTERCEPT_IRET);
4312 ++vcpu->stat.nmi_injections;
4313 }
4314
4315 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4316 {
4317 struct vmcb_control_area *control;
4318
4319 /* The following fields are ignored when AVIC is enabled */
4320 control = &svm->vmcb->control;
4321 control->int_vector = irq;
4322 control->int_ctl &= ~V_INTR_PRIO_MASK;
4323 control->int_ctl |= V_IRQ_MASK |
4324 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4325 mark_dirty(svm->vmcb, VMCB_INTR);
4326 }
4327
4328 static void svm_set_irq(struct kvm_vcpu *vcpu)
4329 {
4330 struct vcpu_svm *svm = to_svm(vcpu);
4331
4332 BUG_ON(!(gif_set(svm)));
4333
4334 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4335 ++vcpu->stat.irq_injections;
4336
4337 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4338 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4339 }
4340
4341 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4342 {
4343 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4344 }
4345
4346 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4347 {
4348 struct vcpu_svm *svm = to_svm(vcpu);
4349
4350 if (svm_nested_virtualize_tpr(vcpu) ||
4351 kvm_vcpu_apicv_active(vcpu))
4352 return;
4353
4354 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4355
4356 if (irr == -1)
4357 return;
4358
4359 if (tpr >= irr)
4360 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4361 }
4362
4363 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4364 {
4365 return;
4366 }
4367
4368 static bool svm_get_enable_apicv(void)
4369 {
4370 return avic;
4371 }
4372
4373 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4374 {
4375 }
4376
4377 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4378 {
4379 }
4380
4381 /* Note: Currently only used by Hyper-V. */
4382 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4383 {
4384 struct vcpu_svm *svm = to_svm(vcpu);
4385 struct vmcb *vmcb = svm->vmcb;
4386
4387 if (!avic)
4388 return;
4389
4390 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4391 mark_dirty(vmcb, VMCB_INTR);
4392 }
4393
4394 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4395 {
4396 return;
4397 }
4398
4399 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4400 {
4401 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4402 smp_mb__after_atomic();
4403
4404 if (avic_vcpu_is_running(vcpu))
4405 wrmsrl(SVM_AVIC_DOORBELL,
4406 kvm_cpu_get_apicid(vcpu->cpu));
4407 else
4408 kvm_vcpu_wake_up(vcpu);
4409 }
4410
4411 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4412 {
4413 unsigned long flags;
4414 struct amd_svm_iommu_ir *cur;
4415
4416 spin_lock_irqsave(&svm->ir_list_lock, flags);
4417 list_for_each_entry(cur, &svm->ir_list, node) {
4418 if (cur->data != pi->ir_data)
4419 continue;
4420 list_del(&cur->node);
4421 kfree(cur);
4422 break;
4423 }
4424 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4425 }
4426
4427 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4428 {
4429 int ret = 0;
4430 unsigned long flags;
4431 struct amd_svm_iommu_ir *ir;
4432
4433 /**
4434 * In some cases, the existing irte is updaed and re-set,
4435 * so we need to check here if it's already been * added
4436 * to the ir_list.
4437 */
4438 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4439 struct kvm *kvm = svm->vcpu.kvm;
4440 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4441 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4442 struct vcpu_svm *prev_svm;
4443
4444 if (!prev_vcpu) {
4445 ret = -EINVAL;
4446 goto out;
4447 }
4448
4449 prev_svm = to_svm(prev_vcpu);
4450 svm_ir_list_del(prev_svm, pi);
4451 }
4452
4453 /**
4454 * Allocating new amd_iommu_pi_data, which will get
4455 * add to the per-vcpu ir_list.
4456 */
4457 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4458 if (!ir) {
4459 ret = -ENOMEM;
4460 goto out;
4461 }
4462 ir->data = pi->ir_data;
4463
4464 spin_lock_irqsave(&svm->ir_list_lock, flags);
4465 list_add(&ir->node, &svm->ir_list);
4466 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4467 out:
4468 return ret;
4469 }
4470
4471 /**
4472 * Note:
4473 * The HW cannot support posting multicast/broadcast
4474 * interrupts to a vCPU. So, we still use legacy interrupt
4475 * remapping for these kind of interrupts.
4476 *
4477 * For lowest-priority interrupts, we only support
4478 * those with single CPU as the destination, e.g. user
4479 * configures the interrupts via /proc/irq or uses
4480 * irqbalance to make the interrupts single-CPU.
4481 */
4482 static int
4483 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4484 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4485 {
4486 struct kvm_lapic_irq irq;
4487 struct kvm_vcpu *vcpu = NULL;
4488
4489 kvm_set_msi_irq(kvm, e, &irq);
4490
4491 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4492 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4493 __func__, irq.vector);
4494 return -1;
4495 }
4496
4497 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4498 irq.vector);
4499 *svm = to_svm(vcpu);
4500 vcpu_info->pi_desc_addr = page_to_phys((*svm)->avic_backing_page);
4501 vcpu_info->vector = irq.vector;
4502
4503 return 0;
4504 }
4505
4506 /*
4507 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4508 *
4509 * @kvm: kvm
4510 * @host_irq: host irq of the interrupt
4511 * @guest_irq: gsi of the interrupt
4512 * @set: set or unset PI
4513 * returns 0 on success, < 0 on failure
4514 */
4515 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4516 uint32_t guest_irq, bool set)
4517 {
4518 struct kvm_kernel_irq_routing_entry *e;
4519 struct kvm_irq_routing_table *irq_rt;
4520 int idx, ret = -EINVAL;
4521
4522 if (!kvm_arch_has_assigned_device(kvm) ||
4523 !irq_remapping_cap(IRQ_POSTING_CAP))
4524 return 0;
4525
4526 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4527 __func__, host_irq, guest_irq, set);
4528
4529 idx = srcu_read_lock(&kvm->irq_srcu);
4530 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4531 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4532
4533 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4534 struct vcpu_data vcpu_info;
4535 struct vcpu_svm *svm = NULL;
4536
4537 if (e->type != KVM_IRQ_ROUTING_MSI)
4538 continue;
4539
4540 /**
4541 * Here, we setup with legacy mode in the following cases:
4542 * 1. When cannot target interrupt to a specific vcpu.
4543 * 2. Unsetting posted interrupt.
4544 * 3. APIC virtialization is disabled for the vcpu.
4545 */
4546 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4547 kvm_vcpu_apicv_active(&svm->vcpu)) {
4548 struct amd_iommu_pi_data pi;
4549
4550 /* Try to enable guest_mode in IRTE */
4551 pi.base = page_to_phys(svm->avic_backing_page) & AVIC_HPA_MASK;
4552 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4553 svm->vcpu.vcpu_id);
4554 pi.is_guest_mode = true;
4555 pi.vcpu_data = &vcpu_info;
4556 ret = irq_set_vcpu_affinity(host_irq, &pi);
4557
4558 /**
4559 * Here, we successfully setting up vcpu affinity in
4560 * IOMMU guest mode. Now, we need to store the posted
4561 * interrupt information in a per-vcpu ir_list so that
4562 * we can reference to them directly when we update vcpu
4563 * scheduling information in IOMMU irte.
4564 */
4565 if (!ret && pi.is_guest_mode)
4566 svm_ir_list_add(svm, &pi);
4567 } else {
4568 /* Use legacy mode in IRTE */
4569 struct amd_iommu_pi_data pi;
4570
4571 /**
4572 * Here, pi is used to:
4573 * - Tell IOMMU to use legacy mode for this interrupt.
4574 * - Retrieve ga_tag of prior interrupt remapping data.
4575 */
4576 pi.is_guest_mode = false;
4577 ret = irq_set_vcpu_affinity(host_irq, &pi);
4578
4579 /**
4580 * Check if the posted interrupt was previously
4581 * setup with the guest_mode by checking if the ga_tag
4582 * was cached. If so, we need to clean up the per-vcpu
4583 * ir_list.
4584 */
4585 if (!ret && pi.prev_ga_tag) {
4586 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4587 struct kvm_vcpu *vcpu;
4588
4589 vcpu = kvm_get_vcpu_by_id(kvm, id);
4590 if (vcpu)
4591 svm_ir_list_del(to_svm(vcpu), &pi);
4592 }
4593 }
4594
4595 if (!ret && svm) {
4596 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4597 host_irq, e->gsi,
4598 vcpu_info.vector,
4599 vcpu_info.pi_desc_addr, set);
4600 }
4601
4602 if (ret < 0) {
4603 pr_err("%s: failed to update PI IRTE\n", __func__);
4604 goto out;
4605 }
4606 }
4607
4608 ret = 0;
4609 out:
4610 srcu_read_unlock(&kvm->irq_srcu, idx);
4611 return ret;
4612 }
4613
4614 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4615 {
4616 struct vcpu_svm *svm = to_svm(vcpu);
4617 struct vmcb *vmcb = svm->vmcb;
4618 int ret;
4619 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4620 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4621 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4622
4623 return ret;
4624 }
4625
4626 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4627 {
4628 struct vcpu_svm *svm = to_svm(vcpu);
4629
4630 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4631 }
4632
4633 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4634 {
4635 struct vcpu_svm *svm = to_svm(vcpu);
4636
4637 if (masked) {
4638 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4639 set_intercept(svm, INTERCEPT_IRET);
4640 } else {
4641 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4642 clr_intercept(svm, INTERCEPT_IRET);
4643 }
4644 }
4645
4646 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4647 {
4648 struct vcpu_svm *svm = to_svm(vcpu);
4649 struct vmcb *vmcb = svm->vmcb;
4650 int ret;
4651
4652 if (!gif_set(svm) ||
4653 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4654 return 0;
4655
4656 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4657
4658 if (is_guest_mode(vcpu))
4659 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4660
4661 return ret;
4662 }
4663
4664 static void enable_irq_window(struct kvm_vcpu *vcpu)
4665 {
4666 struct vcpu_svm *svm = to_svm(vcpu);
4667
4668 if (kvm_vcpu_apicv_active(vcpu))
4669 return;
4670
4671 /*
4672 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4673 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4674 * get that intercept, this function will be called again though and
4675 * we'll get the vintr intercept.
4676 */
4677 if (gif_set(svm) && nested_svm_intr(svm)) {
4678 svm_set_vintr(svm);
4679 svm_inject_irq(svm, 0x0);
4680 }
4681 }
4682
4683 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4684 {
4685 struct vcpu_svm *svm = to_svm(vcpu);
4686
4687 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4688 == HF_NMI_MASK)
4689 return; /* IRET will cause a vm exit */
4690
4691 if ((svm->vcpu.arch.hflags & HF_GIF_MASK) == 0)
4692 return; /* STGI will cause a vm exit */
4693
4694 if (svm->nested.exit_required)
4695 return; /* we're not going to run the guest yet */
4696
4697 /*
4698 * Something prevents NMI from been injected. Single step over possible
4699 * problem (IRET or exception injection or interrupt shadow)
4700 */
4701 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4702 svm->nmi_singlestep = true;
4703 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4704 }
4705
4706 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4707 {
4708 return 0;
4709 }
4710
4711 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4712 {
4713 struct vcpu_svm *svm = to_svm(vcpu);
4714
4715 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4716 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4717 else
4718 svm->asid_generation--;
4719 }
4720
4721 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4722 {
4723 }
4724
4725 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4726 {
4727 struct vcpu_svm *svm = to_svm(vcpu);
4728
4729 if (svm_nested_virtualize_tpr(vcpu))
4730 return;
4731
4732 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4733 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4734 kvm_set_cr8(vcpu, cr8);
4735 }
4736 }
4737
4738 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4739 {
4740 struct vcpu_svm *svm = to_svm(vcpu);
4741 u64 cr8;
4742
4743 if (svm_nested_virtualize_tpr(vcpu) ||
4744 kvm_vcpu_apicv_active(vcpu))
4745 return;
4746
4747 cr8 = kvm_get_cr8(vcpu);
4748 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4749 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4750 }
4751
4752 static void svm_complete_interrupts(struct vcpu_svm *svm)
4753 {
4754 u8 vector;
4755 int type;
4756 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4757 unsigned int3_injected = svm->int3_injected;
4758
4759 svm->int3_injected = 0;
4760
4761 /*
4762 * If we've made progress since setting HF_IRET_MASK, we've
4763 * executed an IRET and can allow NMI injection.
4764 */
4765 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4766 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4767 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4768 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4769 }
4770
4771 svm->vcpu.arch.nmi_injected = false;
4772 kvm_clear_exception_queue(&svm->vcpu);
4773 kvm_clear_interrupt_queue(&svm->vcpu);
4774
4775 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4776 return;
4777
4778 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4779
4780 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4781 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4782
4783 switch (type) {
4784 case SVM_EXITINTINFO_TYPE_NMI:
4785 svm->vcpu.arch.nmi_injected = true;
4786 break;
4787 case SVM_EXITINTINFO_TYPE_EXEPT:
4788 /*
4789 * In case of software exceptions, do not reinject the vector,
4790 * but re-execute the instruction instead. Rewind RIP first
4791 * if we emulated INT3 before.
4792 */
4793 if (kvm_exception_is_soft(vector)) {
4794 if (vector == BP_VECTOR && int3_injected &&
4795 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4796 kvm_rip_write(&svm->vcpu,
4797 kvm_rip_read(&svm->vcpu) -
4798 int3_injected);
4799 break;
4800 }
4801 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4802 u32 err = svm->vmcb->control.exit_int_info_err;
4803 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4804
4805 } else
4806 kvm_requeue_exception(&svm->vcpu, vector);
4807 break;
4808 case SVM_EXITINTINFO_TYPE_INTR:
4809 kvm_queue_interrupt(&svm->vcpu, vector, false);
4810 break;
4811 default:
4812 break;
4813 }
4814 }
4815
4816 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4817 {
4818 struct vcpu_svm *svm = to_svm(vcpu);
4819 struct vmcb_control_area *control = &svm->vmcb->control;
4820
4821 control->exit_int_info = control->event_inj;
4822 control->exit_int_info_err = control->event_inj_err;
4823 control->event_inj = 0;
4824 svm_complete_interrupts(svm);
4825 }
4826
4827 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4828 {
4829 struct vcpu_svm *svm = to_svm(vcpu);
4830
4831 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4832 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4833 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4834
4835 /*
4836 * A vmexit emulation is required before the vcpu can be executed
4837 * again.
4838 */
4839 if (unlikely(svm->nested.exit_required))
4840 return;
4841
4842 /*
4843 * Disable singlestep if we're injecting an interrupt/exception.
4844 * We don't want our modified rflags to be pushed on the stack where
4845 * we might not be able to easily reset them if we disabled NMI
4846 * singlestep later.
4847 */
4848 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4849 /*
4850 * Event injection happens before external interrupts cause a
4851 * vmexit and interrupts are disabled here, so smp_send_reschedule
4852 * is enough to force an immediate vmexit.
4853 */
4854 disable_nmi_singlestep(svm);
4855 smp_send_reschedule(vcpu->cpu);
4856 }
4857
4858 pre_svm_run(svm);
4859
4860 sync_lapic_to_cr8(vcpu);
4861
4862 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4863
4864 clgi();
4865
4866 local_irq_enable();
4867
4868 asm volatile (
4869 "push %%" _ASM_BP "; \n\t"
4870 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4871 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4872 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4873 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4874 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4875 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4876 #ifdef CONFIG_X86_64
4877 "mov %c[r8](%[svm]), %%r8 \n\t"
4878 "mov %c[r9](%[svm]), %%r9 \n\t"
4879 "mov %c[r10](%[svm]), %%r10 \n\t"
4880 "mov %c[r11](%[svm]), %%r11 \n\t"
4881 "mov %c[r12](%[svm]), %%r12 \n\t"
4882 "mov %c[r13](%[svm]), %%r13 \n\t"
4883 "mov %c[r14](%[svm]), %%r14 \n\t"
4884 "mov %c[r15](%[svm]), %%r15 \n\t"
4885 #endif
4886
4887 /* Enter guest mode */
4888 "push %%" _ASM_AX " \n\t"
4889 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4890 __ex(SVM_VMLOAD) "\n\t"
4891 __ex(SVM_VMRUN) "\n\t"
4892 __ex(SVM_VMSAVE) "\n\t"
4893 "pop %%" _ASM_AX " \n\t"
4894
4895 /* Save guest registers, load host registers */
4896 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4897 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4898 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4899 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4900 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4901 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4902 #ifdef CONFIG_X86_64
4903 "mov %%r8, %c[r8](%[svm]) \n\t"
4904 "mov %%r9, %c[r9](%[svm]) \n\t"
4905 "mov %%r10, %c[r10](%[svm]) \n\t"
4906 "mov %%r11, %c[r11](%[svm]) \n\t"
4907 "mov %%r12, %c[r12](%[svm]) \n\t"
4908 "mov %%r13, %c[r13](%[svm]) \n\t"
4909 "mov %%r14, %c[r14](%[svm]) \n\t"
4910 "mov %%r15, %c[r15](%[svm]) \n\t"
4911 #endif
4912 "pop %%" _ASM_BP
4913 :
4914 : [svm]"a"(svm),
4915 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4916 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4917 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4918 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4919 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4920 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4921 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4922 #ifdef CONFIG_X86_64
4923 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4924 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4925 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4926 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4927 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4928 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4929 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4930 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4931 #endif
4932 : "cc", "memory"
4933 #ifdef CONFIG_X86_64
4934 , "rbx", "rcx", "rdx", "rsi", "rdi"
4935 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4936 #else
4937 , "ebx", "ecx", "edx", "esi", "edi"
4938 #endif
4939 );
4940
4941 #ifdef CONFIG_X86_64
4942 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4943 #else
4944 loadsegment(fs, svm->host.fs);
4945 #ifndef CONFIG_X86_32_LAZY_GS
4946 loadsegment(gs, svm->host.gs);
4947 #endif
4948 #endif
4949
4950 reload_tss(vcpu);
4951
4952 local_irq_disable();
4953
4954 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4955 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4956 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4957 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4958
4959 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4960 kvm_before_handle_nmi(&svm->vcpu);
4961
4962 stgi();
4963
4964 /* Any pending NMI will happen here */
4965
4966 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4967 kvm_after_handle_nmi(&svm->vcpu);
4968
4969 sync_cr8_to_lapic(vcpu);
4970
4971 svm->next_rip = 0;
4972
4973 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4974
4975 /* if exit due to PF check for async PF */
4976 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4977 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
4978
4979 if (npt_enabled) {
4980 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
4981 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
4982 }
4983
4984 /*
4985 * We need to handle MC intercepts here before the vcpu has a chance to
4986 * change the physical cpu
4987 */
4988 if (unlikely(svm->vmcb->control.exit_code ==
4989 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4990 svm_handle_mce(svm);
4991
4992 mark_all_clean(svm->vmcb);
4993 }
4994 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
4995
4996 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4997 {
4998 struct vcpu_svm *svm = to_svm(vcpu);
4999
5000 svm->vmcb->save.cr3 = root;
5001 mark_dirty(svm->vmcb, VMCB_CR);
5002 svm_flush_tlb(vcpu);
5003 }
5004
5005 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5006 {
5007 struct vcpu_svm *svm = to_svm(vcpu);
5008
5009 svm->vmcb->control.nested_cr3 = root;
5010 mark_dirty(svm->vmcb, VMCB_NPT);
5011
5012 /* Also sync guest cr3 here in case we live migrate */
5013 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5014 mark_dirty(svm->vmcb, VMCB_CR);
5015
5016 svm_flush_tlb(vcpu);
5017 }
5018
5019 static int is_disabled(void)
5020 {
5021 u64 vm_cr;
5022
5023 rdmsrl(MSR_VM_CR, vm_cr);
5024 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5025 return 1;
5026
5027 return 0;
5028 }
5029
5030 static void
5031 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5032 {
5033 /*
5034 * Patch in the VMMCALL instruction:
5035 */
5036 hypercall[0] = 0x0f;
5037 hypercall[1] = 0x01;
5038 hypercall[2] = 0xd9;
5039 }
5040
5041 static void svm_check_processor_compat(void *rtn)
5042 {
5043 *(int *)rtn = 0;
5044 }
5045
5046 static bool svm_cpu_has_accelerated_tpr(void)
5047 {
5048 return false;
5049 }
5050
5051 static bool svm_has_high_real_mode_segbase(void)
5052 {
5053 return true;
5054 }
5055
5056 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5057 {
5058 return 0;
5059 }
5060
5061 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5062 {
5063 struct vcpu_svm *svm = to_svm(vcpu);
5064 struct kvm_cpuid_entry2 *entry;
5065
5066 /* Update nrips enabled cache */
5067 svm->nrips_enabled = !!guest_cpuid_has_nrips(&svm->vcpu);
5068
5069 if (!kvm_vcpu_apicv_active(vcpu))
5070 return;
5071
5072 entry = kvm_find_cpuid_entry(vcpu, 1, 0);
5073 if (entry)
5074 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5075 }
5076
5077 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5078 {
5079 switch (func) {
5080 case 0x1:
5081 if (avic)
5082 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5083 break;
5084 case 0x80000001:
5085 if (nested)
5086 entry->ecx |= (1 << 2); /* Set SVM bit */
5087 break;
5088 case 0x8000000A:
5089 entry->eax = 1; /* SVM revision 1 */
5090 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5091 ASID emulation to nested SVM */
5092 entry->ecx = 0; /* Reserved */
5093 entry->edx = 0; /* Per default do not support any
5094 additional features */
5095
5096 /* Support next_rip if host supports it */
5097 if (boot_cpu_has(X86_FEATURE_NRIPS))
5098 entry->edx |= SVM_FEATURE_NRIP;
5099
5100 /* Support NPT for the guest if enabled */
5101 if (npt_enabled)
5102 entry->edx |= SVM_FEATURE_NPT;
5103
5104 break;
5105 }
5106 }
5107
5108 static int svm_get_lpage_level(void)
5109 {
5110 return PT_PDPE_LEVEL;
5111 }
5112
5113 static bool svm_rdtscp_supported(void)
5114 {
5115 return boot_cpu_has(X86_FEATURE_RDTSCP);
5116 }
5117
5118 static bool svm_invpcid_supported(void)
5119 {
5120 return false;
5121 }
5122
5123 static bool svm_mpx_supported(void)
5124 {
5125 return false;
5126 }
5127
5128 static bool svm_xsaves_supported(void)
5129 {
5130 return false;
5131 }
5132
5133 static bool svm_has_wbinvd_exit(void)
5134 {
5135 return true;
5136 }
5137
5138 #define PRE_EX(exit) { .exit_code = (exit), \
5139 .stage = X86_ICPT_PRE_EXCEPT, }
5140 #define POST_EX(exit) { .exit_code = (exit), \
5141 .stage = X86_ICPT_POST_EXCEPT, }
5142 #define POST_MEM(exit) { .exit_code = (exit), \
5143 .stage = X86_ICPT_POST_MEMACCESS, }
5144
5145 static const struct __x86_intercept {
5146 u32 exit_code;
5147 enum x86_intercept_stage stage;
5148 } x86_intercept_map[] = {
5149 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5150 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5151 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5152 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5153 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5154 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5155 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5156 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5157 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5158 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5159 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5160 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5161 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5162 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5163 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5164 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5165 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5166 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5167 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5168 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5169 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5170 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5171 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5172 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5173 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5174 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5175 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5176 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5177 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5178 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5179 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5180 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5181 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5182 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5183 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5184 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5185 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5186 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5187 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5188 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5189 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5190 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5191 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5192 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5193 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5194 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5195 };
5196
5197 #undef PRE_EX
5198 #undef POST_EX
5199 #undef POST_MEM
5200
5201 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5202 struct x86_instruction_info *info,
5203 enum x86_intercept_stage stage)
5204 {
5205 struct vcpu_svm *svm = to_svm(vcpu);
5206 int vmexit, ret = X86EMUL_CONTINUE;
5207 struct __x86_intercept icpt_info;
5208 struct vmcb *vmcb = svm->vmcb;
5209
5210 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5211 goto out;
5212
5213 icpt_info = x86_intercept_map[info->intercept];
5214
5215 if (stage != icpt_info.stage)
5216 goto out;
5217
5218 switch (icpt_info.exit_code) {
5219 case SVM_EXIT_READ_CR0:
5220 if (info->intercept == x86_intercept_cr_read)
5221 icpt_info.exit_code += info->modrm_reg;
5222 break;
5223 case SVM_EXIT_WRITE_CR0: {
5224 unsigned long cr0, val;
5225 u64 intercept;
5226
5227 if (info->intercept == x86_intercept_cr_write)
5228 icpt_info.exit_code += info->modrm_reg;
5229
5230 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5231 info->intercept == x86_intercept_clts)
5232 break;
5233
5234 intercept = svm->nested.intercept;
5235
5236 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5237 break;
5238
5239 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5240 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5241
5242 if (info->intercept == x86_intercept_lmsw) {
5243 cr0 &= 0xfUL;
5244 val &= 0xfUL;
5245 /* lmsw can't clear PE - catch this here */
5246 if (cr0 & X86_CR0_PE)
5247 val |= X86_CR0_PE;
5248 }
5249
5250 if (cr0 ^ val)
5251 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5252
5253 break;
5254 }
5255 case SVM_EXIT_READ_DR0:
5256 case SVM_EXIT_WRITE_DR0:
5257 icpt_info.exit_code += info->modrm_reg;
5258 break;
5259 case SVM_EXIT_MSR:
5260 if (info->intercept == x86_intercept_wrmsr)
5261 vmcb->control.exit_info_1 = 1;
5262 else
5263 vmcb->control.exit_info_1 = 0;
5264 break;
5265 case SVM_EXIT_PAUSE:
5266 /*
5267 * We get this for NOP only, but pause
5268 * is rep not, check this here
5269 */
5270 if (info->rep_prefix != REPE_PREFIX)
5271 goto out;
5272 case SVM_EXIT_IOIO: {
5273 u64 exit_info;
5274 u32 bytes;
5275
5276 if (info->intercept == x86_intercept_in ||
5277 info->intercept == x86_intercept_ins) {
5278 exit_info = ((info->src_val & 0xffff) << 16) |
5279 SVM_IOIO_TYPE_MASK;
5280 bytes = info->dst_bytes;
5281 } else {
5282 exit_info = (info->dst_val & 0xffff) << 16;
5283 bytes = info->src_bytes;
5284 }
5285
5286 if (info->intercept == x86_intercept_outs ||
5287 info->intercept == x86_intercept_ins)
5288 exit_info |= SVM_IOIO_STR_MASK;
5289
5290 if (info->rep_prefix)
5291 exit_info |= SVM_IOIO_REP_MASK;
5292
5293 bytes = min(bytes, 4u);
5294
5295 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5296
5297 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5298
5299 vmcb->control.exit_info_1 = exit_info;
5300 vmcb->control.exit_info_2 = info->next_rip;
5301
5302 break;
5303 }
5304 default:
5305 break;
5306 }
5307
5308 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5309 if (static_cpu_has(X86_FEATURE_NRIPS))
5310 vmcb->control.next_rip = info->next_rip;
5311 vmcb->control.exit_code = icpt_info.exit_code;
5312 vmexit = nested_svm_exit_handled(svm);
5313
5314 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5315 : X86EMUL_CONTINUE;
5316
5317 out:
5318 return ret;
5319 }
5320
5321 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5322 {
5323 local_irq_enable();
5324 /*
5325 * We must have an instruction with interrupts enabled, so
5326 * the timer interrupt isn't delayed by the interrupt shadow.
5327 */
5328 asm("nop");
5329 local_irq_disable();
5330 }
5331
5332 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5333 {
5334 }
5335
5336 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5337 {
5338 if (avic_handle_apic_id_update(vcpu) != 0)
5339 return;
5340 if (avic_handle_dfr_update(vcpu) != 0)
5341 return;
5342 avic_handle_ldr_update(vcpu);
5343 }
5344
5345 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5346 {
5347 /* [63:9] are reserved. */
5348 vcpu->arch.mcg_cap &= 0x1ff;
5349 }
5350
5351 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5352 .cpu_has_kvm_support = has_svm,
5353 .disabled_by_bios = is_disabled,
5354 .hardware_setup = svm_hardware_setup,
5355 .hardware_unsetup = svm_hardware_unsetup,
5356 .check_processor_compatibility = svm_check_processor_compat,
5357 .hardware_enable = svm_hardware_enable,
5358 .hardware_disable = svm_hardware_disable,
5359 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5360 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5361
5362 .vcpu_create = svm_create_vcpu,
5363 .vcpu_free = svm_free_vcpu,
5364 .vcpu_reset = svm_vcpu_reset,
5365
5366 .vm_init = avic_vm_init,
5367 .vm_destroy = avic_vm_destroy,
5368
5369 .prepare_guest_switch = svm_prepare_guest_switch,
5370 .vcpu_load = svm_vcpu_load,
5371 .vcpu_put = svm_vcpu_put,
5372 .vcpu_blocking = svm_vcpu_blocking,
5373 .vcpu_unblocking = svm_vcpu_unblocking,
5374
5375 .update_bp_intercept = update_bp_intercept,
5376 .get_msr = svm_get_msr,
5377 .set_msr = svm_set_msr,
5378 .get_segment_base = svm_get_segment_base,
5379 .get_segment = svm_get_segment,
5380 .set_segment = svm_set_segment,
5381 .get_cpl = svm_get_cpl,
5382 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5383 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5384 .decache_cr3 = svm_decache_cr3,
5385 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5386 .set_cr0 = svm_set_cr0,
5387 .set_cr3 = svm_set_cr3,
5388 .set_cr4 = svm_set_cr4,
5389 .set_efer = svm_set_efer,
5390 .get_idt = svm_get_idt,
5391 .set_idt = svm_set_idt,
5392 .get_gdt = svm_get_gdt,
5393 .set_gdt = svm_set_gdt,
5394 .get_dr6 = svm_get_dr6,
5395 .set_dr6 = svm_set_dr6,
5396 .set_dr7 = svm_set_dr7,
5397 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5398 .cache_reg = svm_cache_reg,
5399 .get_rflags = svm_get_rflags,
5400 .set_rflags = svm_set_rflags,
5401
5402 .get_pkru = svm_get_pkru,
5403
5404 .tlb_flush = svm_flush_tlb,
5405
5406 .run = svm_vcpu_run,
5407 .handle_exit = handle_exit,
5408 .skip_emulated_instruction = skip_emulated_instruction,
5409 .set_interrupt_shadow = svm_set_interrupt_shadow,
5410 .get_interrupt_shadow = svm_get_interrupt_shadow,
5411 .patch_hypercall = svm_patch_hypercall,
5412 .set_irq = svm_set_irq,
5413 .set_nmi = svm_inject_nmi,
5414 .queue_exception = svm_queue_exception,
5415 .cancel_injection = svm_cancel_injection,
5416 .interrupt_allowed = svm_interrupt_allowed,
5417 .nmi_allowed = svm_nmi_allowed,
5418 .get_nmi_mask = svm_get_nmi_mask,
5419 .set_nmi_mask = svm_set_nmi_mask,
5420 .enable_nmi_window = enable_nmi_window,
5421 .enable_irq_window = enable_irq_window,
5422 .update_cr8_intercept = update_cr8_intercept,
5423 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5424 .get_enable_apicv = svm_get_enable_apicv,
5425 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5426 .load_eoi_exitmap = svm_load_eoi_exitmap,
5427 .hwapic_irr_update = svm_hwapic_irr_update,
5428 .hwapic_isr_update = svm_hwapic_isr_update,
5429 .apicv_post_state_restore = avic_post_state_restore,
5430
5431 .set_tss_addr = svm_set_tss_addr,
5432 .get_tdp_level = get_npt_level,
5433 .get_mt_mask = svm_get_mt_mask,
5434
5435 .get_exit_info = svm_get_exit_info,
5436
5437 .get_lpage_level = svm_get_lpage_level,
5438
5439 .cpuid_update = svm_cpuid_update,
5440
5441 .rdtscp_supported = svm_rdtscp_supported,
5442 .invpcid_supported = svm_invpcid_supported,
5443 .mpx_supported = svm_mpx_supported,
5444 .xsaves_supported = svm_xsaves_supported,
5445
5446 .set_supported_cpuid = svm_set_supported_cpuid,
5447
5448 .has_wbinvd_exit = svm_has_wbinvd_exit,
5449
5450 .write_tsc_offset = svm_write_tsc_offset,
5451
5452 .set_tdp_cr3 = set_tdp_cr3,
5453
5454 .check_intercept = svm_check_intercept,
5455 .handle_external_intr = svm_handle_external_intr,
5456
5457 .sched_in = svm_sched_in,
5458
5459 .pmu_ops = &amd_pmu_ops,
5460 .deliver_posted_interrupt = svm_deliver_avic_intr,
5461 .update_pi_irte = svm_update_pi_irte,
5462 .setup_mce = svm_setup_mce,
5463 };
5464
5465 static int __init svm_init(void)
5466 {
5467 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5468 __alignof__(struct vcpu_svm), THIS_MODULE);
5469 }
5470
5471 static void __exit svm_exit(void)
5472 {
5473 kvm_exit();
5474 }
5475
5476 module_init(svm_init)
5477 module_exit(svm_exit)
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