2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
66 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
67 #define TSC_RATIO_MIN 0x0000000000000001ULL
68 #define TSC_RATIO_MAX 0x000000ffffffffffULL
70 static bool erratum_383_found __read_mostly
;
72 static const u32 host_save_user_msrs
[] = {
74 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
77 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
80 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
90 /* These are the merged vectors */
93 /* gpa pointers to the real vectors */
97 /* A VMEXIT is required but not yet emulated */
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions
;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
114 * Set osvw_len to higher value when updated Revision Guides
115 * are published and we know what the new status bits are
117 static uint64_t osvw_len
= 4, osvw_status
;
120 struct kvm_vcpu vcpu
;
122 unsigned long vmcb_pa
;
123 struct svm_cpu_data
*svm_data
;
124 uint64_t asid_generation
;
125 uint64_t sysenter_esp
;
126 uint64_t sysenter_eip
;
130 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
142 struct nested_state nested
;
146 unsigned int3_injected
;
147 unsigned long int3_rip
;
153 static DEFINE_PER_CPU(u64
, current_tsc_ratio
);
154 #define TSC_RATIO_DEFAULT 0x0100000000ULL
156 #define MSR_INVALID 0xffffffffU
158 static struct svm_direct_access_msrs
{
159 u32 index
; /* Index of the MSR */
160 bool always
; /* True if intercept is always on */
161 } direct_access_msrs
[] = {
162 { .index
= MSR_STAR
, .always
= true },
163 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
165 { .index
= MSR_GS_BASE
, .always
= true },
166 { .index
= MSR_FS_BASE
, .always
= true },
167 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
168 { .index
= MSR_LSTAR
, .always
= true },
169 { .index
= MSR_CSTAR
, .always
= true },
170 { .index
= MSR_SYSCALL_MASK
, .always
= true },
172 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
173 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
174 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
175 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
176 { .index
= MSR_INVALID
, .always
= false },
179 /* enable NPT for AMD64 and X86 with PAE */
180 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
181 static bool npt_enabled
= true;
183 static bool npt_enabled
;
187 module_param(npt
, int, S_IRUGO
);
189 static int nested
= 1;
190 module_param(nested
, int, S_IRUGO
);
192 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
193 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
195 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
196 static int nested_svm_intercept(struct vcpu_svm
*svm
);
197 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
198 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
199 bool has_error_code
, u32 error_code
);
200 static u64
__scale_tsc(u64 ratio
, u64 tsc
);
203 VMCB_INTERCEPTS
, /* Intercept vectors, TSC offset,
204 pause filter count */
205 VMCB_PERM_MAP
, /* IOPM Base and MSRPM Base */
206 VMCB_ASID
, /* ASID */
207 VMCB_INTR
, /* int_ctl, int_vector */
208 VMCB_NPT
, /* npt_en, nCR3, gPAT */
209 VMCB_CR
, /* CR0, CR3, CR4, EFER */
210 VMCB_DR
, /* DR6, DR7 */
211 VMCB_DT
, /* GDT, IDT */
212 VMCB_SEG
, /* CS, DS, SS, ES, CPL */
213 VMCB_CR2
, /* CR2 only */
214 VMCB_LBR
, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
218 /* TPR and CR2 are always written before VMRUN */
219 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
221 static inline void mark_all_dirty(struct vmcb
*vmcb
)
223 vmcb
->control
.clean
= 0;
226 static inline void mark_all_clean(struct vmcb
*vmcb
)
228 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
229 & ~VMCB_ALWAYS_DIRTY_MASK
;
232 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
234 vmcb
->control
.clean
&= ~(1 << bit
);
237 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
239 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
242 static void recalc_intercepts(struct vcpu_svm
*svm
)
244 struct vmcb_control_area
*c
, *h
;
245 struct nested_state
*g
;
247 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
249 if (!is_guest_mode(&svm
->vcpu
))
252 c
= &svm
->vmcb
->control
;
253 h
= &svm
->nested
.hsave
->control
;
256 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
257 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
258 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
259 c
->intercept
= h
->intercept
| g
->intercept
;
262 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
264 if (is_guest_mode(&svm
->vcpu
))
265 return svm
->nested
.hsave
;
270 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
272 struct vmcb
*vmcb
= get_host_vmcb(svm
);
274 vmcb
->control
.intercept_cr
|= (1U << bit
);
276 recalc_intercepts(svm
);
279 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
281 struct vmcb
*vmcb
= get_host_vmcb(svm
);
283 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
285 recalc_intercepts(svm
);
288 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
290 struct vmcb
*vmcb
= get_host_vmcb(svm
);
292 return vmcb
->control
.intercept_cr
& (1U << bit
);
295 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
297 struct vmcb
*vmcb
= get_host_vmcb(svm
);
299 vmcb
->control
.intercept_dr
|= (1U << bit
);
301 recalc_intercepts(svm
);
304 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
306 struct vmcb
*vmcb
= get_host_vmcb(svm
);
308 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
310 recalc_intercepts(svm
);
313 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
315 struct vmcb
*vmcb
= get_host_vmcb(svm
);
317 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
319 recalc_intercepts(svm
);
322 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
324 struct vmcb
*vmcb
= get_host_vmcb(svm
);
326 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
328 recalc_intercepts(svm
);
331 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
333 struct vmcb
*vmcb
= get_host_vmcb(svm
);
335 vmcb
->control
.intercept
|= (1ULL << bit
);
337 recalc_intercepts(svm
);
340 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
342 struct vmcb
*vmcb
= get_host_vmcb(svm
);
344 vmcb
->control
.intercept
&= ~(1ULL << bit
);
346 recalc_intercepts(svm
);
349 static inline void enable_gif(struct vcpu_svm
*svm
)
351 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
354 static inline void disable_gif(struct vcpu_svm
*svm
)
356 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
359 static inline bool gif_set(struct vcpu_svm
*svm
)
361 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
364 static unsigned long iopm_base
;
366 struct kvm_ldttss_desc
{
369 unsigned base1
:8, type
:5, dpl
:2, p
:1;
370 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
373 } __attribute__((packed
));
375 struct svm_cpu_data
{
381 struct kvm_ldttss_desc
*tss_desc
;
383 struct page
*save_area
;
386 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
388 struct svm_init_data
{
393 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
395 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
396 #define MSRS_RANGE_SIZE 2048
397 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
399 static u32
svm_msrpm_offset(u32 msr
)
404 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
405 if (msr
< msrpm_ranges
[i
] ||
406 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
409 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
410 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
412 /* Now we have the u8 offset - but need the u32 offset */
416 /* MSR not in any range */
420 #define MAX_INST_SIZE 15
422 static inline void clgi(void)
424 asm volatile (__ex(SVM_CLGI
));
427 static inline void stgi(void)
429 asm volatile (__ex(SVM_STGI
));
432 static inline void invlpga(unsigned long addr
, u32 asid
)
434 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
437 static int get_npt_level(void)
440 return PT64_ROOT_LEVEL
;
442 return PT32E_ROOT_LEVEL
;
446 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
448 vcpu
->arch
.efer
= efer
;
449 if (!npt_enabled
&& !(efer
& EFER_LMA
))
452 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
453 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
456 static int is_external_interrupt(u32 info
)
458 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
459 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
462 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
464 struct vcpu_svm
*svm
= to_svm(vcpu
);
467 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
468 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
472 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
474 struct vcpu_svm
*svm
= to_svm(vcpu
);
477 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
479 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
483 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
485 struct vcpu_svm
*svm
= to_svm(vcpu
);
487 if (svm
->vmcb
->control
.next_rip
!= 0)
488 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
490 if (!svm
->next_rip
) {
491 if (emulate_instruction(vcpu
, EMULTYPE_SKIP
) !=
493 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
496 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
497 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
498 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
500 kvm_rip_write(vcpu
, svm
->next_rip
);
501 svm_set_interrupt_shadow(vcpu
, 0);
504 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
505 bool has_error_code
, u32 error_code
,
508 struct vcpu_svm
*svm
= to_svm(vcpu
);
511 * If we are within a nested VM we'd better #VMEXIT and let the guest
512 * handle the exception
515 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
518 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
519 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
522 * For guest debugging where we have to reinject #BP if some
523 * INT3 is guest-owned:
524 * Emulate nRIP by moving RIP forward. Will fail if injection
525 * raises a fault that is not intercepted. Still better than
526 * failing in all cases.
528 skip_emulated_instruction(&svm
->vcpu
);
529 rip
= kvm_rip_read(&svm
->vcpu
);
530 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
531 svm
->int3_injected
= rip
- old_rip
;
534 svm
->vmcb
->control
.event_inj
= nr
536 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
537 | SVM_EVTINJ_TYPE_EXEPT
;
538 svm
->vmcb
->control
.event_inj_err
= error_code
;
541 static void svm_init_erratum_383(void)
547 if (!cpu_has_amd_erratum(amd_erratum_383
))
550 /* Use _safe variants to not break nested virtualization */
551 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
557 low
= lower_32_bits(val
);
558 high
= upper_32_bits(val
);
560 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
562 erratum_383_found
= true;
565 static void svm_init_osvw(struct kvm_vcpu
*vcpu
)
568 * Guests should see errata 400 and 415 as fixed (assuming that
569 * HLT and IO instructions are intercepted).
571 vcpu
->arch
.osvw
.length
= (osvw_len
>= 3) ? (osvw_len
) : 3;
572 vcpu
->arch
.osvw
.status
= osvw_status
& ~(6ULL);
575 * By increasing VCPU's osvw.length to 3 we are telling the guest that
576 * all osvw.status bits inside that length, including bit 0 (which is
577 * reserved for erratum 298), are valid. However, if host processor's
578 * osvw_len is 0 then osvw_status[0] carries no information. We need to
579 * be conservative here and therefore we tell the guest that erratum 298
580 * is present (because we really don't know).
582 if (osvw_len
== 0 && boot_cpu_data
.x86
== 0x10)
583 vcpu
->arch
.osvw
.status
|= 1;
586 static int has_svm(void)
590 if (!cpu_has_svm(&msg
)) {
591 printk(KERN_INFO
"has_svm: %s\n", msg
);
598 static void svm_hardware_disable(void *garbage
)
600 /* Make sure we clean up behind us */
601 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
))
602 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
607 static int svm_hardware_enable(void *garbage
)
610 struct svm_cpu_data
*sd
;
612 struct desc_ptr gdt_descr
;
613 struct desc_struct
*gdt
;
614 int me
= raw_smp_processor_id();
616 rdmsrl(MSR_EFER
, efer
);
617 if (efer
& EFER_SVME
)
621 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
625 sd
= per_cpu(svm_data
, me
);
628 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
633 sd
->asid_generation
= 1;
634 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
635 sd
->next_asid
= sd
->max_asid
+ 1;
637 native_store_gdt(&gdt_descr
);
638 gdt
= (struct desc_struct
*)gdt_descr
.address
;
639 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
641 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
643 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
645 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
646 wrmsrl(MSR_AMD64_TSC_RATIO
, TSC_RATIO_DEFAULT
);
647 __get_cpu_var(current_tsc_ratio
) = TSC_RATIO_DEFAULT
;
654 * Note that it is possible to have a system with mixed processor
655 * revisions and therefore different OSVW bits. If bits are not the same
656 * on different processors then choose the worst case (i.e. if erratum
657 * is present on one processor and not on another then assume that the
658 * erratum is present everywhere).
660 if (cpu_has(&boot_cpu_data
, X86_FEATURE_OSVW
)) {
661 uint64_t len
, status
= 0;
664 len
= native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH
, &err
);
666 status
= native_read_msr_safe(MSR_AMD64_OSVW_STATUS
,
670 osvw_status
= osvw_len
= 0;
674 osvw_status
|= status
;
675 osvw_status
&= (1ULL << osvw_len
) - 1;
678 osvw_status
= osvw_len
= 0;
680 svm_init_erratum_383();
685 static void svm_cpu_uninit(int cpu
)
687 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
692 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
693 __free_page(sd
->save_area
);
697 static int svm_cpu_init(int cpu
)
699 struct svm_cpu_data
*sd
;
702 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
706 sd
->save_area
= alloc_page(GFP_KERNEL
);
711 per_cpu(svm_data
, cpu
) = sd
;
721 static bool valid_msr_intercept(u32 index
)
725 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
726 if (direct_access_msrs
[i
].index
== index
)
732 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
735 u8 bit_read
, bit_write
;
740 * If this warning triggers extend the direct_access_msrs list at the
741 * beginning of the file
743 WARN_ON(!valid_msr_intercept(msr
));
745 offset
= svm_msrpm_offset(msr
);
746 bit_read
= 2 * (msr
& 0x0f);
747 bit_write
= 2 * (msr
& 0x0f) + 1;
750 BUG_ON(offset
== MSR_INVALID
);
752 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
753 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
758 static void svm_vcpu_init_msrpm(u32
*msrpm
)
762 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
764 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
765 if (!direct_access_msrs
[i
].always
)
768 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
772 static void add_msr_offset(u32 offset
)
776 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
778 /* Offset already in list? */
779 if (msrpm_offsets
[i
] == offset
)
782 /* Slot used by another offset? */
783 if (msrpm_offsets
[i
] != MSR_INVALID
)
786 /* Add offset to list */
787 msrpm_offsets
[i
] = offset
;
793 * If this BUG triggers the msrpm_offsets table has an overflow. Just
794 * increase MSRPM_OFFSETS in this case.
799 static void init_msrpm_offsets(void)
803 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
805 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
808 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
809 BUG_ON(offset
== MSR_INVALID
);
811 add_msr_offset(offset
);
815 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
817 u32
*msrpm
= svm
->msrpm
;
819 svm
->vmcb
->control
.lbr_ctl
= 1;
820 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
821 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
822 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
823 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
826 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
828 u32
*msrpm
= svm
->msrpm
;
830 svm
->vmcb
->control
.lbr_ctl
= 0;
831 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
832 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
833 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
834 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
837 static __init
int svm_hardware_setup(void)
840 struct page
*iopm_pages
;
844 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
849 iopm_va
= page_address(iopm_pages
);
850 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
851 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
853 init_msrpm_offsets();
855 if (boot_cpu_has(X86_FEATURE_NX
))
856 kvm_enable_efer_bits(EFER_NX
);
858 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
859 kvm_enable_efer_bits(EFER_FFXSR
);
861 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR
)) {
864 kvm_has_tsc_control
= true;
867 * Make sure the user can only configure tsc_khz values that
868 * fit into a signed integer.
869 * A min value is not calculated needed because it will always
870 * be 1 on all machines and a value of 0 is used to disable
871 * tsc-scaling for the vcpu.
873 max
= min(0x7fffffffULL
, __scale_tsc(tsc_khz
, TSC_RATIO_MAX
));
875 kvm_max_guest_tsc_khz
= max
;
879 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
880 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
883 for_each_possible_cpu(cpu
) {
884 r
= svm_cpu_init(cpu
);
889 if (!boot_cpu_has(X86_FEATURE_NPT
))
892 if (npt_enabled
&& !npt
) {
893 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
898 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
906 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
911 static __exit
void svm_hardware_unsetup(void)
915 for_each_possible_cpu(cpu
)
918 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
922 static void init_seg(struct vmcb_seg
*seg
)
925 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
926 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
931 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
934 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
939 static u64
__scale_tsc(u64 ratio
, u64 tsc
)
941 u64 mult
, frac
, _tsc
;
944 frac
= ratio
& ((1ULL << 32) - 1);
948 _tsc
+= (tsc
>> 32) * frac
;
949 _tsc
+= ((tsc
& ((1ULL << 32) - 1)) * frac
) >> 32;
954 static u64
svm_scale_tsc(struct kvm_vcpu
*vcpu
, u64 tsc
)
956 struct vcpu_svm
*svm
= to_svm(vcpu
);
959 if (svm
->tsc_ratio
!= TSC_RATIO_DEFAULT
)
960 _tsc
= __scale_tsc(svm
->tsc_ratio
, tsc
);
965 static void svm_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
)
967 struct vcpu_svm
*svm
= to_svm(vcpu
);
971 /* TSC scaling supported? */
972 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR
))
975 /* TSC-Scaling disabled or guest TSC same frequency as host TSC? */
976 if (user_tsc_khz
== 0) {
977 vcpu
->arch
.virtual_tsc_khz
= 0;
978 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
984 /* TSC scaling required - calculate ratio */
986 do_div(ratio
, tsc_khz
);
988 if (ratio
== 0 || ratio
& TSC_RATIO_RSVD
) {
989 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
993 vcpu
->arch
.virtual_tsc_khz
= user_tsc_khz
;
994 svm
->tsc_ratio
= ratio
;
997 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
999 struct vcpu_svm
*svm
= to_svm(vcpu
);
1000 u64 g_tsc_offset
= 0;
1002 if (is_guest_mode(vcpu
)) {
1003 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
1004 svm
->nested
.hsave
->control
.tsc_offset
;
1005 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
1008 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
1010 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1013 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1015 struct vcpu_svm
*svm
= to_svm(vcpu
);
1017 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
1018 if (is_guest_mode(vcpu
))
1019 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
1020 mark_dirty(svm
->vmcb
, VMCB_INTERCEPTS
);
1023 static u64
svm_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1027 tsc
= svm_scale_tsc(vcpu
, native_read_tsc());
1029 return target_tsc
- tsc
;
1032 static void init_vmcb(struct vcpu_svm
*svm
)
1034 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
1035 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
1037 svm
->vcpu
.fpu_active
= 1;
1038 svm
->vcpu
.arch
.hflags
= 0;
1040 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1041 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1042 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
1043 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1044 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1045 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
1046 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
1048 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
1049 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
1050 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
1051 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
1052 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
1053 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
1054 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
1055 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
1057 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
1058 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
1059 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
1060 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
1061 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
1062 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
1063 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
1064 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
1066 set_exception_intercept(svm
, PF_VECTOR
);
1067 set_exception_intercept(svm
, UD_VECTOR
);
1068 set_exception_intercept(svm
, MC_VECTOR
);
1070 set_intercept(svm
, INTERCEPT_INTR
);
1071 set_intercept(svm
, INTERCEPT_NMI
);
1072 set_intercept(svm
, INTERCEPT_SMI
);
1073 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
1074 set_intercept(svm
, INTERCEPT_RDPMC
);
1075 set_intercept(svm
, INTERCEPT_CPUID
);
1076 set_intercept(svm
, INTERCEPT_INVD
);
1077 set_intercept(svm
, INTERCEPT_HLT
);
1078 set_intercept(svm
, INTERCEPT_INVLPG
);
1079 set_intercept(svm
, INTERCEPT_INVLPGA
);
1080 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
1081 set_intercept(svm
, INTERCEPT_MSR_PROT
);
1082 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
1083 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
1084 set_intercept(svm
, INTERCEPT_VMRUN
);
1085 set_intercept(svm
, INTERCEPT_VMMCALL
);
1086 set_intercept(svm
, INTERCEPT_VMLOAD
);
1087 set_intercept(svm
, INTERCEPT_VMSAVE
);
1088 set_intercept(svm
, INTERCEPT_STGI
);
1089 set_intercept(svm
, INTERCEPT_CLGI
);
1090 set_intercept(svm
, INTERCEPT_SKINIT
);
1091 set_intercept(svm
, INTERCEPT_WBINVD
);
1092 set_intercept(svm
, INTERCEPT_MONITOR
);
1093 set_intercept(svm
, INTERCEPT_MWAIT
);
1094 set_intercept(svm
, INTERCEPT_XSETBV
);
1096 control
->iopm_base_pa
= iopm_base
;
1097 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
1098 control
->int_ctl
= V_INTR_MASKING_MASK
;
1100 init_seg(&save
->es
);
1101 init_seg(&save
->ss
);
1102 init_seg(&save
->ds
);
1103 init_seg(&save
->fs
);
1104 init_seg(&save
->gs
);
1106 save
->cs
.selector
= 0xf000;
1107 /* Executable/Readable Code Segment */
1108 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
1109 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
1110 save
->cs
.limit
= 0xffff;
1112 * cs.base should really be 0xffff0000, but vmx can't handle that, so
1113 * be consistent with it.
1115 * Replace when we have real mode working for vmx.
1117 save
->cs
.base
= 0xf0000;
1119 save
->gdtr
.limit
= 0xffff;
1120 save
->idtr
.limit
= 0xffff;
1122 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
1123 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
1125 svm_set_efer(&svm
->vcpu
, 0);
1126 save
->dr6
= 0xffff0ff0;
1128 kvm_set_rflags(&svm
->vcpu
, 2);
1129 save
->rip
= 0x0000fff0;
1130 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
1133 * This is the guest-visible cr0 value.
1134 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1136 svm
->vcpu
.arch
.cr0
= 0;
1137 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
1139 save
->cr4
= X86_CR4_PAE
;
1143 /* Setup VMCB for Nested Paging */
1144 control
->nested_ctl
= 1;
1145 clr_intercept(svm
, INTERCEPT_INVLPG
);
1146 clr_exception_intercept(svm
, PF_VECTOR
);
1147 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
1148 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
1149 save
->g_pat
= 0x0007040600070406ULL
;
1153 svm
->asid_generation
= 0;
1155 svm
->nested
.vmcb
= 0;
1156 svm
->vcpu
.arch
.hflags
= 0;
1158 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
1159 control
->pause_filter_count
= 3000;
1160 set_intercept(svm
, INTERCEPT_PAUSE
);
1163 mark_all_dirty(svm
->vmcb
);
1168 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1170 struct vcpu_svm
*svm
= to_svm(vcpu
);
1174 if (!kvm_vcpu_is_bsp(vcpu
)) {
1175 kvm_rip_write(vcpu
, 0);
1176 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1177 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1179 vcpu
->arch
.regs_avail
= ~0;
1180 vcpu
->arch
.regs_dirty
= ~0;
1185 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1187 struct vcpu_svm
*svm
;
1189 struct page
*msrpm_pages
;
1190 struct page
*hsave_page
;
1191 struct page
*nested_msrpm_pages
;
1194 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1200 svm
->tsc_ratio
= TSC_RATIO_DEFAULT
;
1202 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1207 page
= alloc_page(GFP_KERNEL
);
1211 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1215 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1216 if (!nested_msrpm_pages
)
1219 hsave_page
= alloc_page(GFP_KERNEL
);
1223 svm
->nested
.hsave
= page_address(hsave_page
);
1225 svm
->msrpm
= page_address(msrpm_pages
);
1226 svm_vcpu_init_msrpm(svm
->msrpm
);
1228 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1229 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1231 svm
->vmcb
= page_address(page
);
1232 clear_page(svm
->vmcb
);
1233 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1234 svm
->asid_generation
= 0;
1236 kvm_write_tsc(&svm
->vcpu
, 0);
1238 err
= fx_init(&svm
->vcpu
);
1242 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1243 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1244 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1246 svm_init_osvw(&svm
->vcpu
);
1251 __free_page(hsave_page
);
1253 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1255 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1259 kvm_vcpu_uninit(&svm
->vcpu
);
1261 kmem_cache_free(kvm_vcpu_cache
, svm
);
1263 return ERR_PTR(err
);
1266 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1268 struct vcpu_svm
*svm
= to_svm(vcpu
);
1270 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1271 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1272 __free_page(virt_to_page(svm
->nested
.hsave
));
1273 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1274 kvm_vcpu_uninit(vcpu
);
1275 kmem_cache_free(kvm_vcpu_cache
, svm
);
1278 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1280 struct vcpu_svm
*svm
= to_svm(vcpu
);
1283 if (unlikely(cpu
!= vcpu
->cpu
)) {
1284 svm
->asid_generation
= 0;
1285 mark_all_dirty(svm
->vmcb
);
1288 #ifdef CONFIG_X86_64
1289 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1291 savesegment(fs
, svm
->host
.fs
);
1292 savesegment(gs
, svm
->host
.gs
);
1293 svm
->host
.ldt
= kvm_read_ldt();
1295 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1296 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1298 if (static_cpu_has(X86_FEATURE_TSCRATEMSR
) &&
1299 svm
->tsc_ratio
!= __get_cpu_var(current_tsc_ratio
)) {
1300 __get_cpu_var(current_tsc_ratio
) = svm
->tsc_ratio
;
1301 wrmsrl(MSR_AMD64_TSC_RATIO
, svm
->tsc_ratio
);
1305 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1307 struct vcpu_svm
*svm
= to_svm(vcpu
);
1310 ++vcpu
->stat
.host_state_reload
;
1311 kvm_load_ldt(svm
->host
.ldt
);
1312 #ifdef CONFIG_X86_64
1313 loadsegment(fs
, svm
->host
.fs
);
1314 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1315 load_gs_index(svm
->host
.gs
);
1317 #ifdef CONFIG_X86_32_LAZY_GS
1318 loadsegment(gs
, svm
->host
.gs
);
1321 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1322 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1325 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1327 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1330 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1332 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1335 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1338 case VCPU_EXREG_PDPTR
:
1339 BUG_ON(!npt_enabled
);
1340 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, kvm_read_cr3(vcpu
));
1347 static void svm_set_vintr(struct vcpu_svm
*svm
)
1349 set_intercept(svm
, INTERCEPT_VINTR
);
1352 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1354 clr_intercept(svm
, INTERCEPT_VINTR
);
1357 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1359 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1362 case VCPU_SREG_CS
: return &save
->cs
;
1363 case VCPU_SREG_DS
: return &save
->ds
;
1364 case VCPU_SREG_ES
: return &save
->es
;
1365 case VCPU_SREG_FS
: return &save
->fs
;
1366 case VCPU_SREG_GS
: return &save
->gs
;
1367 case VCPU_SREG_SS
: return &save
->ss
;
1368 case VCPU_SREG_TR
: return &save
->tr
;
1369 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1375 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1377 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1382 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1383 struct kvm_segment
*var
, int seg
)
1385 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1387 var
->base
= s
->base
;
1388 var
->limit
= s
->limit
;
1389 var
->selector
= s
->selector
;
1390 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1391 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1392 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1393 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1394 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1395 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1396 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1397 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1400 * AMD's VMCB does not have an explicit unusable field, so emulate it
1401 * for cross vendor migration purposes by "not present"
1403 var
->unusable
= !var
->present
|| (var
->type
== 0);
1408 * SVM always stores 0 for the 'G' bit in the CS selector in
1409 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1410 * Intel's VMENTRY has a check on the 'G' bit.
1412 var
->g
= s
->limit
> 0xfffff;
1416 * Work around a bug where the busy flag in the tr selector
1426 * The accessed bit must always be set in the segment
1427 * descriptor cache, although it can be cleared in the
1428 * descriptor, the cached bit always remains at 1. Since
1429 * Intel has a check on this, set it here to support
1430 * cross-vendor migration.
1437 * On AMD CPUs sometimes the DB bit in the segment
1438 * descriptor is left as 1, although the whole segment has
1439 * been made unusable. Clear it here to pass an Intel VMX
1440 * entry check when cross vendor migrating.
1448 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1450 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1455 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1457 struct vcpu_svm
*svm
= to_svm(vcpu
);
1459 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1460 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1463 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1465 struct vcpu_svm
*svm
= to_svm(vcpu
);
1467 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1468 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1469 mark_dirty(svm
->vmcb
, VMCB_DT
);
1472 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1474 struct vcpu_svm
*svm
= to_svm(vcpu
);
1476 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1477 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1480 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1482 struct vcpu_svm
*svm
= to_svm(vcpu
);
1484 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1485 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1486 mark_dirty(svm
->vmcb
, VMCB_DT
);
1489 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1493 static void svm_decache_cr3(struct kvm_vcpu
*vcpu
)
1497 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1501 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1503 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1504 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1506 if (!svm
->vcpu
.fpu_active
)
1507 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1509 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1510 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1512 mark_dirty(svm
->vmcb
, VMCB_CR
);
1514 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1515 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1516 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1518 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1519 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1523 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1525 struct vcpu_svm
*svm
= to_svm(vcpu
);
1527 #ifdef CONFIG_X86_64
1528 if (vcpu
->arch
.efer
& EFER_LME
) {
1529 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1530 vcpu
->arch
.efer
|= EFER_LMA
;
1531 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1534 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1535 vcpu
->arch
.efer
&= ~EFER_LMA
;
1536 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1540 vcpu
->arch
.cr0
= cr0
;
1543 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1545 if (!vcpu
->fpu_active
)
1548 * re-enable caching here because the QEMU bios
1549 * does not do it - this results in some delay at
1552 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1553 svm
->vmcb
->save
.cr0
= cr0
;
1554 mark_dirty(svm
->vmcb
, VMCB_CR
);
1555 update_cr0_intercept(svm
);
1558 static int svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1560 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1561 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1563 if (cr4
& X86_CR4_VMXE
)
1566 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1567 svm_flush_tlb(vcpu
);
1569 vcpu
->arch
.cr4
= cr4
;
1572 cr4
|= host_cr4_mce
;
1573 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1574 mark_dirty(to_svm(vcpu
)->vmcb
, VMCB_CR
);
1578 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1579 struct kvm_segment
*var
, int seg
)
1581 struct vcpu_svm
*svm
= to_svm(vcpu
);
1582 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1584 s
->base
= var
->base
;
1585 s
->limit
= var
->limit
;
1586 s
->selector
= var
->selector
;
1590 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1591 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1592 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1593 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1594 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1595 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1596 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1597 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1599 if (seg
== VCPU_SREG_CS
)
1601 = (svm
->vmcb
->save
.cs
.attrib
1602 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1604 mark_dirty(svm
->vmcb
, VMCB_SEG
);
1607 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1609 struct vcpu_svm
*svm
= to_svm(vcpu
);
1611 clr_exception_intercept(svm
, DB_VECTOR
);
1612 clr_exception_intercept(svm
, BP_VECTOR
);
1614 if (svm
->nmi_singlestep
)
1615 set_exception_intercept(svm
, DB_VECTOR
);
1617 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1618 if (vcpu
->guest_debug
&
1619 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1620 set_exception_intercept(svm
, DB_VECTOR
);
1621 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1622 set_exception_intercept(svm
, BP_VECTOR
);
1624 vcpu
->guest_debug
= 0;
1627 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1629 struct vcpu_svm
*svm
= to_svm(vcpu
);
1631 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1632 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1634 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1636 mark_dirty(svm
->vmcb
, VMCB_DR
);
1638 update_db_intercept(vcpu
);
1641 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1643 if (sd
->next_asid
> sd
->max_asid
) {
1644 ++sd
->asid_generation
;
1646 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1649 svm
->asid_generation
= sd
->asid_generation
;
1650 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1652 mark_dirty(svm
->vmcb
, VMCB_ASID
);
1655 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1657 struct vcpu_svm
*svm
= to_svm(vcpu
);
1659 svm
->vmcb
->save
.dr7
= value
;
1660 mark_dirty(svm
->vmcb
, VMCB_DR
);
1663 static int pf_interception(struct vcpu_svm
*svm
)
1665 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1669 switch (svm
->apf_reason
) {
1671 error_code
= svm
->vmcb
->control
.exit_info_1
;
1673 trace_kvm_page_fault(fault_address
, error_code
);
1674 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1675 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1676 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
,
1677 svm
->vmcb
->control
.insn_bytes
,
1678 svm
->vmcb
->control
.insn_len
);
1680 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1681 svm
->apf_reason
= 0;
1682 local_irq_disable();
1683 kvm_async_pf_task_wait(fault_address
);
1686 case KVM_PV_REASON_PAGE_READY
:
1687 svm
->apf_reason
= 0;
1688 local_irq_disable();
1689 kvm_async_pf_task_wake(fault_address
);
1696 static int db_interception(struct vcpu_svm
*svm
)
1698 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1700 if (!(svm
->vcpu
.guest_debug
&
1701 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1702 !svm
->nmi_singlestep
) {
1703 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1707 if (svm
->nmi_singlestep
) {
1708 svm
->nmi_singlestep
= false;
1709 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1710 svm
->vmcb
->save
.rflags
&=
1711 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1712 update_db_intercept(&svm
->vcpu
);
1715 if (svm
->vcpu
.guest_debug
&
1716 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1717 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1718 kvm_run
->debug
.arch
.pc
=
1719 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1720 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1727 static int bp_interception(struct vcpu_svm
*svm
)
1729 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1731 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1732 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1733 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1737 static int ud_interception(struct vcpu_svm
*svm
)
1741 er
= emulate_instruction(&svm
->vcpu
, EMULTYPE_TRAP_UD
);
1742 if (er
!= EMULATE_DONE
)
1743 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1747 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1749 struct vcpu_svm
*svm
= to_svm(vcpu
);
1751 clr_exception_intercept(svm
, NM_VECTOR
);
1753 svm
->vcpu
.fpu_active
= 1;
1754 update_cr0_intercept(svm
);
1757 static int nm_interception(struct vcpu_svm
*svm
)
1759 svm_fpu_activate(&svm
->vcpu
);
1763 static bool is_erratum_383(void)
1768 if (!erratum_383_found
)
1771 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1775 /* Bit 62 may or may not be set for this mce */
1776 value
&= ~(1ULL << 62);
1778 if (value
!= 0xb600000000010015ULL
)
1781 /* Clear MCi_STATUS registers */
1782 for (i
= 0; i
< 6; ++i
)
1783 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1785 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1789 value
&= ~(1ULL << 2);
1790 low
= lower_32_bits(value
);
1791 high
= upper_32_bits(value
);
1793 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1796 /* Flush tlb to evict multi-match entries */
1802 static void svm_handle_mce(struct vcpu_svm
*svm
)
1804 if (is_erratum_383()) {
1806 * Erratum 383 triggered. Guest state is corrupt so kill the
1809 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1811 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1817 * On an #MC intercept the MCE handler is not called automatically in
1818 * the host. So do it by hand here.
1822 /* not sure if we ever come back to this point */
1827 static int mc_interception(struct vcpu_svm
*svm
)
1832 static int shutdown_interception(struct vcpu_svm
*svm
)
1834 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1837 * VMCB is undefined after a SHUTDOWN intercept
1838 * so reinitialize it.
1840 clear_page(svm
->vmcb
);
1843 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1847 static int io_interception(struct vcpu_svm
*svm
)
1849 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1850 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1851 int size
, in
, string
;
1854 ++svm
->vcpu
.stat
.io_exits
;
1855 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1856 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1858 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
1860 port
= io_info
>> 16;
1861 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1862 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1863 skip_emulated_instruction(&svm
->vcpu
);
1865 return kvm_fast_pio_out(vcpu
, size
, port
);
1868 static int nmi_interception(struct vcpu_svm
*svm
)
1873 static int intr_interception(struct vcpu_svm
*svm
)
1875 ++svm
->vcpu
.stat
.irq_exits
;
1879 static int nop_on_interception(struct vcpu_svm
*svm
)
1884 static int halt_interception(struct vcpu_svm
*svm
)
1886 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1887 skip_emulated_instruction(&svm
->vcpu
);
1888 return kvm_emulate_halt(&svm
->vcpu
);
1891 static int vmmcall_interception(struct vcpu_svm
*svm
)
1893 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1894 skip_emulated_instruction(&svm
->vcpu
);
1895 kvm_emulate_hypercall(&svm
->vcpu
);
1899 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1901 struct vcpu_svm
*svm
= to_svm(vcpu
);
1903 return svm
->nested
.nested_cr3
;
1906 static u64
nested_svm_get_tdp_pdptr(struct kvm_vcpu
*vcpu
, int index
)
1908 struct vcpu_svm
*svm
= to_svm(vcpu
);
1909 u64 cr3
= svm
->nested
.nested_cr3
;
1913 ret
= kvm_read_guest_page(vcpu
->kvm
, gpa_to_gfn(cr3
), &pdpte
,
1914 offset_in_page(cr3
) + index
* 8, 8);
1920 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1923 struct vcpu_svm
*svm
= to_svm(vcpu
);
1925 svm
->vmcb
->control
.nested_cr3
= root
;
1926 mark_dirty(svm
->vmcb
, VMCB_NPT
);
1927 svm_flush_tlb(vcpu
);
1930 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1931 struct x86_exception
*fault
)
1933 struct vcpu_svm
*svm
= to_svm(vcpu
);
1935 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1936 svm
->vmcb
->control
.exit_code_hi
= 0;
1937 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1938 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1940 nested_svm_vmexit(svm
);
1943 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1947 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1949 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1950 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1951 vcpu
->arch
.mmu
.get_pdptr
= nested_svm_get_tdp_pdptr
;
1952 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1953 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1954 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1959 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1961 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1964 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1966 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1967 || !is_paging(&svm
->vcpu
)) {
1968 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1972 if (svm
->vmcb
->save
.cpl
) {
1973 kvm_inject_gp(&svm
->vcpu
, 0);
1980 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1981 bool has_error_code
, u32 error_code
)
1985 if (!is_guest_mode(&svm
->vcpu
))
1988 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1989 svm
->vmcb
->control
.exit_code_hi
= 0;
1990 svm
->vmcb
->control
.exit_info_1
= error_code
;
1991 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1993 vmexit
= nested_svm_intercept(svm
);
1994 if (vmexit
== NESTED_EXIT_DONE
)
1995 svm
->nested
.exit_required
= true;
2000 /* This function returns true if it is save to enable the irq window */
2001 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
2003 if (!is_guest_mode(&svm
->vcpu
))
2006 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2009 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
2013 * if vmexit was already requested (by intercepted exception
2014 * for instance) do not overwrite it with "external interrupt"
2017 if (svm
->nested
.exit_required
)
2020 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
2021 svm
->vmcb
->control
.exit_info_1
= 0;
2022 svm
->vmcb
->control
.exit_info_2
= 0;
2024 if (svm
->nested
.intercept
& 1ULL) {
2026 * The #vmexit can't be emulated here directly because this
2027 * code path runs with irqs and preemtion disabled. A
2028 * #vmexit emulation might sleep. Only signal request for
2031 svm
->nested
.exit_required
= true;
2032 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
2039 /* This function returns true if it is save to enable the nmi window */
2040 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
2042 if (!is_guest_mode(&svm
->vcpu
))
2045 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
2048 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
2049 svm
->nested
.exit_required
= true;
2054 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
2060 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
2061 if (is_error_page(page
))
2069 kvm_release_page_clean(page
);
2070 kvm_inject_gp(&svm
->vcpu
, 0);
2075 static void nested_svm_unmap(struct page
*page
)
2078 kvm_release_page_dirty(page
);
2081 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
2087 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
2088 return NESTED_EXIT_HOST
;
2090 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
2091 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
2095 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
2098 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2101 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
2103 u32 offset
, msr
, value
;
2106 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2107 return NESTED_EXIT_HOST
;
2109 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2110 offset
= svm_msrpm_offset(msr
);
2111 write
= svm
->vmcb
->control
.exit_info_1
& 1;
2112 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
2114 if (offset
== MSR_INVALID
)
2115 return NESTED_EXIT_DONE
;
2117 /* Offset is in 32 bit units but need in 8 bit units */
2120 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
2121 return NESTED_EXIT_DONE
;
2123 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
2126 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
2128 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2130 switch (exit_code
) {
2133 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
2134 return NESTED_EXIT_HOST
;
2136 /* For now we are always handling NPFs when using them */
2138 return NESTED_EXIT_HOST
;
2140 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
2141 /* When we're shadowing, trap PFs, but not async PF */
2142 if (!npt_enabled
&& svm
->apf_reason
== 0)
2143 return NESTED_EXIT_HOST
;
2145 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
2146 nm_interception(svm
);
2152 return NESTED_EXIT_CONTINUE
;
2156 * If this function returns true, this #vmexit was already handled
2158 static int nested_svm_intercept(struct vcpu_svm
*svm
)
2160 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2161 int vmexit
= NESTED_EXIT_HOST
;
2163 switch (exit_code
) {
2165 vmexit
= nested_svm_exit_handled_msr(svm
);
2168 vmexit
= nested_svm_intercept_ioio(svm
);
2170 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
2171 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
2172 if (svm
->nested
.intercept_cr
& bit
)
2173 vmexit
= NESTED_EXIT_DONE
;
2176 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
2177 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
2178 if (svm
->nested
.intercept_dr
& bit
)
2179 vmexit
= NESTED_EXIT_DONE
;
2182 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
2183 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
2184 if (svm
->nested
.intercept_exceptions
& excp_bits
)
2185 vmexit
= NESTED_EXIT_DONE
;
2186 /* async page fault always cause vmexit */
2187 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
2188 svm
->apf_reason
!= 0)
2189 vmexit
= NESTED_EXIT_DONE
;
2192 case SVM_EXIT_ERR
: {
2193 vmexit
= NESTED_EXIT_DONE
;
2197 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2198 if (svm
->nested
.intercept
& exit_bits
)
2199 vmexit
= NESTED_EXIT_DONE
;
2206 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2210 vmexit
= nested_svm_intercept(svm
);
2212 if (vmexit
== NESTED_EXIT_DONE
)
2213 nested_svm_vmexit(svm
);
2218 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2220 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2221 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2223 dst
->intercept_cr
= from
->intercept_cr
;
2224 dst
->intercept_dr
= from
->intercept_dr
;
2225 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2226 dst
->intercept
= from
->intercept
;
2227 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2228 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2229 dst
->tsc_offset
= from
->tsc_offset
;
2230 dst
->asid
= from
->asid
;
2231 dst
->tlb_ctl
= from
->tlb_ctl
;
2232 dst
->int_ctl
= from
->int_ctl
;
2233 dst
->int_vector
= from
->int_vector
;
2234 dst
->int_state
= from
->int_state
;
2235 dst
->exit_code
= from
->exit_code
;
2236 dst
->exit_code_hi
= from
->exit_code_hi
;
2237 dst
->exit_info_1
= from
->exit_info_1
;
2238 dst
->exit_info_2
= from
->exit_info_2
;
2239 dst
->exit_int_info
= from
->exit_int_info
;
2240 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2241 dst
->nested_ctl
= from
->nested_ctl
;
2242 dst
->event_inj
= from
->event_inj
;
2243 dst
->event_inj_err
= from
->event_inj_err
;
2244 dst
->nested_cr3
= from
->nested_cr3
;
2245 dst
->lbr_ctl
= from
->lbr_ctl
;
2248 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2250 struct vmcb
*nested_vmcb
;
2251 struct vmcb
*hsave
= svm
->nested
.hsave
;
2252 struct vmcb
*vmcb
= svm
->vmcb
;
2255 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2256 vmcb
->control
.exit_info_1
,
2257 vmcb
->control
.exit_info_2
,
2258 vmcb
->control
.exit_int_info
,
2259 vmcb
->control
.exit_int_info_err
,
2262 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2266 /* Exit Guest-Mode */
2267 leave_guest_mode(&svm
->vcpu
);
2268 svm
->nested
.vmcb
= 0;
2270 /* Give the current vmcb to the guest */
2273 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2274 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2275 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2276 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2277 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2278 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2279 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2280 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2281 nested_vmcb
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2282 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2283 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2284 nested_vmcb
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2285 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2286 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2287 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2288 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2289 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2290 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2292 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2293 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2294 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2295 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2296 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2297 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2298 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2299 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2300 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2301 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2304 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2305 * to make sure that we do not lose injected events. So check event_inj
2306 * here and copy it to exit_int_info if it is valid.
2307 * Exit_int_info and event_inj can't be both valid because the case
2308 * below only happens on a VMRUN instruction intercept which has
2309 * no valid exit_int_info set.
2311 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2312 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2314 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2315 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2318 nested_vmcb
->control
.tlb_ctl
= 0;
2319 nested_vmcb
->control
.event_inj
= 0;
2320 nested_vmcb
->control
.event_inj_err
= 0;
2322 /* We always set V_INTR_MASKING and remember the old value in hflags */
2323 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2324 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2326 /* Restore the original control entries */
2327 copy_vmcb_control_area(vmcb
, hsave
);
2329 kvm_clear_exception_queue(&svm
->vcpu
);
2330 kvm_clear_interrupt_queue(&svm
->vcpu
);
2332 svm
->nested
.nested_cr3
= 0;
2334 /* Restore selected save entries */
2335 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2336 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2337 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2338 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2339 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2340 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2341 kvm_set_rflags(&svm
->vcpu
, hsave
->save
.rflags
);
2342 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2343 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2344 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2346 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2347 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2349 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2351 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2352 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2353 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2354 svm
->vmcb
->save
.dr7
= 0;
2355 svm
->vmcb
->save
.cpl
= 0;
2356 svm
->vmcb
->control
.exit_int_info
= 0;
2358 mark_all_dirty(svm
->vmcb
);
2360 nested_svm_unmap(page
);
2362 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2363 kvm_mmu_reset_context(&svm
->vcpu
);
2364 kvm_mmu_load(&svm
->vcpu
);
2369 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2372 * This function merges the msr permission bitmaps of kvm and the
2373 * nested vmcb. It is omptimized in that it only merges the parts where
2374 * the kvm msr permission bitmap may contain zero bits
2378 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2381 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2385 if (msrpm_offsets
[i
] == 0xffffffff)
2388 p
= msrpm_offsets
[i
];
2389 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2391 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2394 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2397 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2402 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2404 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2407 if (vmcb
->control
.asid
== 0)
2410 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2416 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2418 struct vmcb
*nested_vmcb
;
2419 struct vmcb
*hsave
= svm
->nested
.hsave
;
2420 struct vmcb
*vmcb
= svm
->vmcb
;
2424 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2426 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2430 if (!nested_vmcb_checks(nested_vmcb
)) {
2431 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2432 nested_vmcb
->control
.exit_code_hi
= 0;
2433 nested_vmcb
->control
.exit_info_1
= 0;
2434 nested_vmcb
->control
.exit_info_2
= 0;
2436 nested_svm_unmap(page
);
2441 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2442 nested_vmcb
->save
.rip
,
2443 nested_vmcb
->control
.int_ctl
,
2444 nested_vmcb
->control
.event_inj
,
2445 nested_vmcb
->control
.nested_ctl
);
2447 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2448 nested_vmcb
->control
.intercept_cr
>> 16,
2449 nested_vmcb
->control
.intercept_exceptions
,
2450 nested_vmcb
->control
.intercept
);
2452 /* Clear internal status */
2453 kvm_clear_exception_queue(&svm
->vcpu
);
2454 kvm_clear_interrupt_queue(&svm
->vcpu
);
2457 * Save the old vmcb, so we don't need to pick what we save, but can
2458 * restore everything when a VMEXIT occurs
2460 hsave
->save
.es
= vmcb
->save
.es
;
2461 hsave
->save
.cs
= vmcb
->save
.cs
;
2462 hsave
->save
.ss
= vmcb
->save
.ss
;
2463 hsave
->save
.ds
= vmcb
->save
.ds
;
2464 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2465 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2466 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2467 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2468 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2469 hsave
->save
.rflags
= kvm_get_rflags(&svm
->vcpu
);
2470 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2471 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2472 hsave
->save
.rax
= vmcb
->save
.rax
;
2474 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2476 hsave
->save
.cr3
= kvm_read_cr3(&svm
->vcpu
);
2478 copy_vmcb_control_area(hsave
, vmcb
);
2480 if (kvm_get_rflags(&svm
->vcpu
) & X86_EFLAGS_IF
)
2481 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2483 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2485 if (nested_vmcb
->control
.nested_ctl
) {
2486 kvm_mmu_unload(&svm
->vcpu
);
2487 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2488 nested_svm_init_mmu_context(&svm
->vcpu
);
2491 /* Load the nested guest state */
2492 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2493 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2494 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2495 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2496 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2497 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2498 kvm_set_rflags(&svm
->vcpu
, nested_vmcb
->save
.rflags
);
2499 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2500 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2501 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2503 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2504 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2506 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2508 /* Guest paging mode is active - reset mmu */
2509 kvm_mmu_reset_context(&svm
->vcpu
);
2511 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2512 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2513 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2514 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2516 /* In case we don't even reach vcpu_run, the fields are not updated */
2517 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2518 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2519 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2520 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2521 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2522 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2524 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2525 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2527 /* cache intercepts */
2528 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2529 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2530 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2531 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2533 svm_flush_tlb(&svm
->vcpu
);
2534 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2535 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2536 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2538 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2540 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2541 /* We only want the cr8 intercept bits of the guest */
2542 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2543 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2546 /* We don't want to see VMMCALLs from a nested guest */
2547 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2549 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2550 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2551 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2552 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2553 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2554 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2556 nested_svm_unmap(page
);
2558 /* Enter Guest-Mode */
2559 enter_guest_mode(&svm
->vcpu
);
2562 * Merge guest and host intercepts - must be called with vcpu in
2563 * guest-mode to take affect here
2565 recalc_intercepts(svm
);
2567 svm
->nested
.vmcb
= vmcb_gpa
;
2571 mark_all_dirty(svm
->vmcb
);
2576 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2578 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2579 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2580 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2581 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2582 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2583 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2584 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2585 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2586 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2587 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2588 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2589 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2592 static int vmload_interception(struct vcpu_svm
*svm
)
2594 struct vmcb
*nested_vmcb
;
2597 if (nested_svm_check_permissions(svm
))
2600 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2604 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2605 skip_emulated_instruction(&svm
->vcpu
);
2607 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2608 nested_svm_unmap(page
);
2613 static int vmsave_interception(struct vcpu_svm
*svm
)
2615 struct vmcb
*nested_vmcb
;
2618 if (nested_svm_check_permissions(svm
))
2621 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2625 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2626 skip_emulated_instruction(&svm
->vcpu
);
2628 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2629 nested_svm_unmap(page
);
2634 static int vmrun_interception(struct vcpu_svm
*svm
)
2636 if (nested_svm_check_permissions(svm
))
2639 /* Save rip after vmrun instruction */
2640 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2642 if (!nested_svm_vmrun(svm
))
2645 if (!nested_svm_vmrun_msrpm(svm
))
2652 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2653 svm
->vmcb
->control
.exit_code_hi
= 0;
2654 svm
->vmcb
->control
.exit_info_1
= 0;
2655 svm
->vmcb
->control
.exit_info_2
= 0;
2657 nested_svm_vmexit(svm
);
2662 static int stgi_interception(struct vcpu_svm
*svm
)
2664 if (nested_svm_check_permissions(svm
))
2667 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2668 skip_emulated_instruction(&svm
->vcpu
);
2669 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2676 static int clgi_interception(struct vcpu_svm
*svm
)
2678 if (nested_svm_check_permissions(svm
))
2681 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2682 skip_emulated_instruction(&svm
->vcpu
);
2686 /* After a CLGI no interrupts should come */
2687 svm_clear_vintr(svm
);
2688 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2690 mark_dirty(svm
->vmcb
, VMCB_INTR
);
2695 static int invlpga_interception(struct vcpu_svm
*svm
)
2697 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2699 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2700 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2702 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2703 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2705 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2706 skip_emulated_instruction(&svm
->vcpu
);
2710 static int skinit_interception(struct vcpu_svm
*svm
)
2712 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2714 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2718 static int xsetbv_interception(struct vcpu_svm
*svm
)
2720 u64 new_bv
= kvm_read_edx_eax(&svm
->vcpu
);
2721 u32 index
= kvm_register_read(&svm
->vcpu
, VCPU_REGS_RCX
);
2723 if (kvm_set_xcr(&svm
->vcpu
, index
, new_bv
) == 0) {
2724 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2725 skip_emulated_instruction(&svm
->vcpu
);
2731 static int invalid_op_interception(struct vcpu_svm
*svm
)
2733 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2737 static int task_switch_interception(struct vcpu_svm
*svm
)
2741 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2742 SVM_EXITINTINFO_TYPE_MASK
;
2743 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2745 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2747 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2748 bool has_error_code
= false;
2751 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2753 if (svm
->vmcb
->control
.exit_info_2
&
2754 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2755 reason
= TASK_SWITCH_IRET
;
2756 else if (svm
->vmcb
->control
.exit_info_2
&
2757 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2758 reason
= TASK_SWITCH_JMP
;
2760 reason
= TASK_SWITCH_GATE
;
2762 reason
= TASK_SWITCH_CALL
;
2764 if (reason
== TASK_SWITCH_GATE
) {
2766 case SVM_EXITINTINFO_TYPE_NMI
:
2767 svm
->vcpu
.arch
.nmi_injected
= false;
2769 case SVM_EXITINTINFO_TYPE_EXEPT
:
2770 if (svm
->vmcb
->control
.exit_info_2
&
2771 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2772 has_error_code
= true;
2774 (u32
)svm
->vmcb
->control
.exit_info_2
;
2776 kvm_clear_exception_queue(&svm
->vcpu
);
2778 case SVM_EXITINTINFO_TYPE_INTR
:
2779 kvm_clear_interrupt_queue(&svm
->vcpu
);
2786 if (reason
!= TASK_SWITCH_GATE
||
2787 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2788 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2789 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2790 skip_emulated_instruction(&svm
->vcpu
);
2792 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2793 has_error_code
, error_code
) == EMULATE_FAIL
) {
2794 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2795 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2796 svm
->vcpu
.run
->internal
.ndata
= 0;
2802 static int cpuid_interception(struct vcpu_svm
*svm
)
2804 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2805 kvm_emulate_cpuid(&svm
->vcpu
);
2809 static int iret_interception(struct vcpu_svm
*svm
)
2811 ++svm
->vcpu
.stat
.nmi_window_exits
;
2812 clr_intercept(svm
, INTERCEPT_IRET
);
2813 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2814 svm
->nmi_iret_rip
= kvm_rip_read(&svm
->vcpu
);
2818 static int invlpg_interception(struct vcpu_svm
*svm
)
2820 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2821 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2823 kvm_mmu_invlpg(&svm
->vcpu
, svm
->vmcb
->control
.exit_info_1
);
2824 skip_emulated_instruction(&svm
->vcpu
);
2828 static int emulate_on_interception(struct vcpu_svm
*svm
)
2830 return emulate_instruction(&svm
->vcpu
, 0) == EMULATE_DONE
;
2833 static int rdpmc_interception(struct vcpu_svm
*svm
)
2837 if (!static_cpu_has(X86_FEATURE_NRIPS
))
2838 return emulate_on_interception(svm
);
2840 err
= kvm_rdpmc(&svm
->vcpu
);
2841 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2846 bool check_selective_cr0_intercepted(struct vcpu_svm
*svm
, unsigned long val
)
2848 unsigned long cr0
= svm
->vcpu
.arch
.cr0
;
2852 intercept
= svm
->nested
.intercept
;
2854 if (!is_guest_mode(&svm
->vcpu
) ||
2855 (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
))))
2858 cr0
&= ~SVM_CR0_SELECTIVE_MASK
;
2859 val
&= ~SVM_CR0_SELECTIVE_MASK
;
2862 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
2863 ret
= (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
);
2869 #define CR_VALID (1ULL << 63)
2871 static int cr_interception(struct vcpu_svm
*svm
)
2877 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS
))
2878 return emulate_on_interception(svm
);
2880 if (unlikely((svm
->vmcb
->control
.exit_info_1
& CR_VALID
) == 0))
2881 return emulate_on_interception(svm
);
2883 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2884 cr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_CR0
;
2887 if (cr
>= 16) { /* mov to cr */
2889 val
= kvm_register_read(&svm
->vcpu
, reg
);
2892 if (!check_selective_cr0_intercepted(svm
, val
))
2893 err
= kvm_set_cr0(&svm
->vcpu
, val
);
2899 err
= kvm_set_cr3(&svm
->vcpu
, val
);
2902 err
= kvm_set_cr4(&svm
->vcpu
, val
);
2905 err
= kvm_set_cr8(&svm
->vcpu
, val
);
2908 WARN(1, "unhandled write to CR%d", cr
);
2909 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2912 } else { /* mov from cr */
2915 val
= kvm_read_cr0(&svm
->vcpu
);
2918 val
= svm
->vcpu
.arch
.cr2
;
2921 val
= kvm_read_cr3(&svm
->vcpu
);
2924 val
= kvm_read_cr4(&svm
->vcpu
);
2927 val
= kvm_get_cr8(&svm
->vcpu
);
2930 WARN(1, "unhandled read from CR%d", cr
);
2931 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2934 kvm_register_write(&svm
->vcpu
, reg
, val
);
2936 kvm_complete_insn_gp(&svm
->vcpu
, err
);
2941 static int dr_interception(struct vcpu_svm
*svm
)
2947 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS
))
2948 return emulate_on_interception(svm
);
2950 reg
= svm
->vmcb
->control
.exit_info_1
& SVM_EXITINFO_REG_MASK
;
2951 dr
= svm
->vmcb
->control
.exit_code
- SVM_EXIT_READ_DR0
;
2953 if (dr
>= 16) { /* mov to DRn */
2954 val
= kvm_register_read(&svm
->vcpu
, reg
);
2955 kvm_set_dr(&svm
->vcpu
, dr
- 16, val
);
2957 err
= kvm_get_dr(&svm
->vcpu
, dr
, &val
);
2959 kvm_register_write(&svm
->vcpu
, reg
, val
);
2962 skip_emulated_instruction(&svm
->vcpu
);
2967 static int cr8_write_interception(struct vcpu_svm
*svm
)
2969 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2972 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2973 /* instruction emulation calls kvm_set_cr8() */
2974 r
= cr_interception(svm
);
2975 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2976 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2979 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2981 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2985 u64
svm_read_l1_tsc(struct kvm_vcpu
*vcpu
)
2987 struct vmcb
*vmcb
= get_host_vmcb(to_svm(vcpu
));
2988 return vmcb
->control
.tsc_offset
+
2989 svm_scale_tsc(vcpu
, native_read_tsc());
2992 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2994 struct vcpu_svm
*svm
= to_svm(vcpu
);
2997 case MSR_IA32_TSC
: {
2998 *data
= svm
->vmcb
->control
.tsc_offset
+
2999 svm_scale_tsc(vcpu
, native_read_tsc());
3004 *data
= svm
->vmcb
->save
.star
;
3006 #ifdef CONFIG_X86_64
3008 *data
= svm
->vmcb
->save
.lstar
;
3011 *data
= svm
->vmcb
->save
.cstar
;
3013 case MSR_KERNEL_GS_BASE
:
3014 *data
= svm
->vmcb
->save
.kernel_gs_base
;
3016 case MSR_SYSCALL_MASK
:
3017 *data
= svm
->vmcb
->save
.sfmask
;
3020 case MSR_IA32_SYSENTER_CS
:
3021 *data
= svm
->vmcb
->save
.sysenter_cs
;
3023 case MSR_IA32_SYSENTER_EIP
:
3024 *data
= svm
->sysenter_eip
;
3026 case MSR_IA32_SYSENTER_ESP
:
3027 *data
= svm
->sysenter_esp
;
3030 * Nobody will change the following 5 values in the VMCB so we can
3031 * safely return them on rdmsr. They will always be 0 until LBRV is
3034 case MSR_IA32_DEBUGCTLMSR
:
3035 *data
= svm
->vmcb
->save
.dbgctl
;
3037 case MSR_IA32_LASTBRANCHFROMIP
:
3038 *data
= svm
->vmcb
->save
.br_from
;
3040 case MSR_IA32_LASTBRANCHTOIP
:
3041 *data
= svm
->vmcb
->save
.br_to
;
3043 case MSR_IA32_LASTINTFROMIP
:
3044 *data
= svm
->vmcb
->save
.last_excp_from
;
3046 case MSR_IA32_LASTINTTOIP
:
3047 *data
= svm
->vmcb
->save
.last_excp_to
;
3049 case MSR_VM_HSAVE_PA
:
3050 *data
= svm
->nested
.hsave_msr
;
3053 *data
= svm
->nested
.vm_cr_msr
;
3055 case MSR_IA32_UCODE_REV
:
3059 return kvm_get_msr_common(vcpu
, ecx
, data
);
3064 static int rdmsr_interception(struct vcpu_svm
*svm
)
3066 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3069 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
3070 trace_kvm_msr_read_ex(ecx
);
3071 kvm_inject_gp(&svm
->vcpu
, 0);
3073 trace_kvm_msr_read(ecx
, data
);
3075 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
3076 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
3077 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3078 skip_emulated_instruction(&svm
->vcpu
);
3083 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
3085 struct vcpu_svm
*svm
= to_svm(vcpu
);
3086 int svm_dis
, chg_mask
;
3088 if (data
& ~SVM_VM_CR_VALID_MASK
)
3091 chg_mask
= SVM_VM_CR_VALID_MASK
;
3093 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
3094 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
3096 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
3097 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
3099 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
3101 /* check for svm_disable while efer.svme is set */
3102 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
3108 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
3110 struct vcpu_svm
*svm
= to_svm(vcpu
);
3114 kvm_write_tsc(vcpu
, data
);
3117 svm
->vmcb
->save
.star
= data
;
3119 #ifdef CONFIG_X86_64
3121 svm
->vmcb
->save
.lstar
= data
;
3124 svm
->vmcb
->save
.cstar
= data
;
3126 case MSR_KERNEL_GS_BASE
:
3127 svm
->vmcb
->save
.kernel_gs_base
= data
;
3129 case MSR_SYSCALL_MASK
:
3130 svm
->vmcb
->save
.sfmask
= data
;
3133 case MSR_IA32_SYSENTER_CS
:
3134 svm
->vmcb
->save
.sysenter_cs
= data
;
3136 case MSR_IA32_SYSENTER_EIP
:
3137 svm
->sysenter_eip
= data
;
3138 svm
->vmcb
->save
.sysenter_eip
= data
;
3140 case MSR_IA32_SYSENTER_ESP
:
3141 svm
->sysenter_esp
= data
;
3142 svm
->vmcb
->save
.sysenter_esp
= data
;
3144 case MSR_IA32_DEBUGCTLMSR
:
3145 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
3146 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3150 if (data
& DEBUGCTL_RESERVED_BITS
)
3153 svm
->vmcb
->save
.dbgctl
= data
;
3154 mark_dirty(svm
->vmcb
, VMCB_LBR
);
3155 if (data
& (1ULL<<0))
3156 svm_enable_lbrv(svm
);
3158 svm_disable_lbrv(svm
);
3160 case MSR_VM_HSAVE_PA
:
3161 svm
->nested
.hsave_msr
= data
;
3164 return svm_set_vm_cr(vcpu
, data
);
3166 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
3169 return kvm_set_msr_common(vcpu
, ecx
, data
);
3174 static int wrmsr_interception(struct vcpu_svm
*svm
)
3176 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
3177 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
3178 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3181 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
3182 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
3183 trace_kvm_msr_write_ex(ecx
, data
);
3184 kvm_inject_gp(&svm
->vcpu
, 0);
3186 trace_kvm_msr_write(ecx
, data
);
3187 skip_emulated_instruction(&svm
->vcpu
);
3192 static int msr_interception(struct vcpu_svm
*svm
)
3194 if (svm
->vmcb
->control
.exit_info_1
)
3195 return wrmsr_interception(svm
);
3197 return rdmsr_interception(svm
);
3200 static int interrupt_window_interception(struct vcpu_svm
*svm
)
3202 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
3204 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3205 svm_clear_vintr(svm
);
3206 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
3207 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3209 * If the user space waits to inject interrupts, exit as soon as
3212 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
3213 kvm_run
->request_interrupt_window
&&
3214 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
3215 ++svm
->vcpu
.stat
.irq_window_exits
;
3216 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3223 static int pause_interception(struct vcpu_svm
*svm
)
3225 kvm_vcpu_on_spin(&(svm
->vcpu
));
3229 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
3230 [SVM_EXIT_READ_CR0
] = cr_interception
,
3231 [SVM_EXIT_READ_CR3
] = cr_interception
,
3232 [SVM_EXIT_READ_CR4
] = cr_interception
,
3233 [SVM_EXIT_READ_CR8
] = cr_interception
,
3234 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
3235 [SVM_EXIT_WRITE_CR0
] = cr_interception
,
3236 [SVM_EXIT_WRITE_CR3
] = cr_interception
,
3237 [SVM_EXIT_WRITE_CR4
] = cr_interception
,
3238 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
3239 [SVM_EXIT_READ_DR0
] = dr_interception
,
3240 [SVM_EXIT_READ_DR1
] = dr_interception
,
3241 [SVM_EXIT_READ_DR2
] = dr_interception
,
3242 [SVM_EXIT_READ_DR3
] = dr_interception
,
3243 [SVM_EXIT_READ_DR4
] = dr_interception
,
3244 [SVM_EXIT_READ_DR5
] = dr_interception
,
3245 [SVM_EXIT_READ_DR6
] = dr_interception
,
3246 [SVM_EXIT_READ_DR7
] = dr_interception
,
3247 [SVM_EXIT_WRITE_DR0
] = dr_interception
,
3248 [SVM_EXIT_WRITE_DR1
] = dr_interception
,
3249 [SVM_EXIT_WRITE_DR2
] = dr_interception
,
3250 [SVM_EXIT_WRITE_DR3
] = dr_interception
,
3251 [SVM_EXIT_WRITE_DR4
] = dr_interception
,
3252 [SVM_EXIT_WRITE_DR5
] = dr_interception
,
3253 [SVM_EXIT_WRITE_DR6
] = dr_interception
,
3254 [SVM_EXIT_WRITE_DR7
] = dr_interception
,
3255 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
3256 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
3257 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
3258 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
3259 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
3260 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
3261 [SVM_EXIT_INTR
] = intr_interception
,
3262 [SVM_EXIT_NMI
] = nmi_interception
,
3263 [SVM_EXIT_SMI
] = nop_on_interception
,
3264 [SVM_EXIT_INIT
] = nop_on_interception
,
3265 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
3266 [SVM_EXIT_RDPMC
] = rdpmc_interception
,
3267 [SVM_EXIT_CPUID
] = cpuid_interception
,
3268 [SVM_EXIT_IRET
] = iret_interception
,
3269 [SVM_EXIT_INVD
] = emulate_on_interception
,
3270 [SVM_EXIT_PAUSE
] = pause_interception
,
3271 [SVM_EXIT_HLT
] = halt_interception
,
3272 [SVM_EXIT_INVLPG
] = invlpg_interception
,
3273 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
3274 [SVM_EXIT_IOIO
] = io_interception
,
3275 [SVM_EXIT_MSR
] = msr_interception
,
3276 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
3277 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
3278 [SVM_EXIT_VMRUN
] = vmrun_interception
,
3279 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
3280 [SVM_EXIT_VMLOAD
] = vmload_interception
,
3281 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
3282 [SVM_EXIT_STGI
] = stgi_interception
,
3283 [SVM_EXIT_CLGI
] = clgi_interception
,
3284 [SVM_EXIT_SKINIT
] = skinit_interception
,
3285 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
3286 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
3287 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
3288 [SVM_EXIT_XSETBV
] = xsetbv_interception
,
3289 [SVM_EXIT_NPF
] = pf_interception
,
3292 static void dump_vmcb(struct kvm_vcpu
*vcpu
)
3294 struct vcpu_svm
*svm
= to_svm(vcpu
);
3295 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3296 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
3298 pr_err("VMCB Control Area:\n");
3299 pr_err("%-20s%04x\n", "cr_read:", control
->intercept_cr
& 0xffff);
3300 pr_err("%-20s%04x\n", "cr_write:", control
->intercept_cr
>> 16);
3301 pr_err("%-20s%04x\n", "dr_read:", control
->intercept_dr
& 0xffff);
3302 pr_err("%-20s%04x\n", "dr_write:", control
->intercept_dr
>> 16);
3303 pr_err("%-20s%08x\n", "exceptions:", control
->intercept_exceptions
);
3304 pr_err("%-20s%016llx\n", "intercepts:", control
->intercept
);
3305 pr_err("%-20s%d\n", "pause filter count:", control
->pause_filter_count
);
3306 pr_err("%-20s%016llx\n", "iopm_base_pa:", control
->iopm_base_pa
);
3307 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control
->msrpm_base_pa
);
3308 pr_err("%-20s%016llx\n", "tsc_offset:", control
->tsc_offset
);
3309 pr_err("%-20s%d\n", "asid:", control
->asid
);
3310 pr_err("%-20s%d\n", "tlb_ctl:", control
->tlb_ctl
);
3311 pr_err("%-20s%08x\n", "int_ctl:", control
->int_ctl
);
3312 pr_err("%-20s%08x\n", "int_vector:", control
->int_vector
);
3313 pr_err("%-20s%08x\n", "int_state:", control
->int_state
);
3314 pr_err("%-20s%08x\n", "exit_code:", control
->exit_code
);
3315 pr_err("%-20s%016llx\n", "exit_info1:", control
->exit_info_1
);
3316 pr_err("%-20s%016llx\n", "exit_info2:", control
->exit_info_2
);
3317 pr_err("%-20s%08x\n", "exit_int_info:", control
->exit_int_info
);
3318 pr_err("%-20s%08x\n", "exit_int_info_err:", control
->exit_int_info_err
);
3319 pr_err("%-20s%lld\n", "nested_ctl:", control
->nested_ctl
);
3320 pr_err("%-20s%016llx\n", "nested_cr3:", control
->nested_cr3
);
3321 pr_err("%-20s%08x\n", "event_inj:", control
->event_inj
);
3322 pr_err("%-20s%08x\n", "event_inj_err:", control
->event_inj_err
);
3323 pr_err("%-20s%lld\n", "lbr_ctl:", control
->lbr_ctl
);
3324 pr_err("%-20s%016llx\n", "next_rip:", control
->next_rip
);
3325 pr_err("VMCB State Save Area:\n");
3326 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3328 save
->es
.selector
, save
->es
.attrib
,
3329 save
->es
.limit
, save
->es
.base
);
3330 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3332 save
->cs
.selector
, save
->cs
.attrib
,
3333 save
->cs
.limit
, save
->cs
.base
);
3334 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3336 save
->ss
.selector
, save
->ss
.attrib
,
3337 save
->ss
.limit
, save
->ss
.base
);
3338 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3340 save
->ds
.selector
, save
->ds
.attrib
,
3341 save
->ds
.limit
, save
->ds
.base
);
3342 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3344 save
->fs
.selector
, save
->fs
.attrib
,
3345 save
->fs
.limit
, save
->fs
.base
);
3346 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3348 save
->gs
.selector
, save
->gs
.attrib
,
3349 save
->gs
.limit
, save
->gs
.base
);
3350 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3352 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3353 save
->gdtr
.limit
, save
->gdtr
.base
);
3354 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3356 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3357 save
->ldtr
.limit
, save
->ldtr
.base
);
3358 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3360 save
->idtr
.selector
, save
->idtr
.attrib
,
3361 save
->idtr
.limit
, save
->idtr
.base
);
3362 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3364 save
->tr
.selector
, save
->tr
.attrib
,
3365 save
->tr
.limit
, save
->tr
.base
);
3366 pr_err("cpl: %d efer: %016llx\n",
3367 save
->cpl
, save
->efer
);
3368 pr_err("%-15s %016llx %-13s %016llx\n",
3369 "cr0:", save
->cr0
, "cr2:", save
->cr2
);
3370 pr_err("%-15s %016llx %-13s %016llx\n",
3371 "cr3:", save
->cr3
, "cr4:", save
->cr4
);
3372 pr_err("%-15s %016llx %-13s %016llx\n",
3373 "dr6:", save
->dr6
, "dr7:", save
->dr7
);
3374 pr_err("%-15s %016llx %-13s %016llx\n",
3375 "rip:", save
->rip
, "rflags:", save
->rflags
);
3376 pr_err("%-15s %016llx %-13s %016llx\n",
3377 "rsp:", save
->rsp
, "rax:", save
->rax
);
3378 pr_err("%-15s %016llx %-13s %016llx\n",
3379 "star:", save
->star
, "lstar:", save
->lstar
);
3380 pr_err("%-15s %016llx %-13s %016llx\n",
3381 "cstar:", save
->cstar
, "sfmask:", save
->sfmask
);
3382 pr_err("%-15s %016llx %-13s %016llx\n",
3383 "kernel_gs_base:", save
->kernel_gs_base
,
3384 "sysenter_cs:", save
->sysenter_cs
);
3385 pr_err("%-15s %016llx %-13s %016llx\n",
3386 "sysenter_esp:", save
->sysenter_esp
,
3387 "sysenter_eip:", save
->sysenter_eip
);
3388 pr_err("%-15s %016llx %-13s %016llx\n",
3389 "gpat:", save
->g_pat
, "dbgctl:", save
->dbgctl
);
3390 pr_err("%-15s %016llx %-13s %016llx\n",
3391 "br_from:", save
->br_from
, "br_to:", save
->br_to
);
3392 pr_err("%-15s %016llx %-13s %016llx\n",
3393 "excp_from:", save
->last_excp_from
,
3394 "excp_to:", save
->last_excp_to
);
3397 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3399 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3401 *info1
= control
->exit_info_1
;
3402 *info2
= control
->exit_info_2
;
3405 static int handle_exit(struct kvm_vcpu
*vcpu
)
3407 struct vcpu_svm
*svm
= to_svm(vcpu
);
3408 struct kvm_run
*kvm_run
= vcpu
->run
;
3409 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3411 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3412 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3414 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3416 if (unlikely(svm
->nested
.exit_required
)) {
3417 nested_svm_vmexit(svm
);
3418 svm
->nested
.exit_required
= false;
3423 if (is_guest_mode(vcpu
)) {
3426 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3427 svm
->vmcb
->control
.exit_info_1
,
3428 svm
->vmcb
->control
.exit_info_2
,
3429 svm
->vmcb
->control
.exit_int_info
,
3430 svm
->vmcb
->control
.exit_int_info_err
,
3433 vmexit
= nested_svm_exit_special(svm
);
3435 if (vmexit
== NESTED_EXIT_CONTINUE
)
3436 vmexit
= nested_svm_exit_handled(svm
);
3438 if (vmexit
== NESTED_EXIT_DONE
)
3442 svm_complete_interrupts(svm
);
3444 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3445 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3446 kvm_run
->fail_entry
.hardware_entry_failure_reason
3447 = svm
->vmcb
->control
.exit_code
;
3448 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3453 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3454 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3455 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3456 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3457 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3459 __func__
, svm
->vmcb
->control
.exit_int_info
,
3462 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3463 || !svm_exit_handlers
[exit_code
]) {
3464 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3465 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3469 return svm_exit_handlers
[exit_code
](svm
);
3472 static void reload_tss(struct kvm_vcpu
*vcpu
)
3474 int cpu
= raw_smp_processor_id();
3476 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3477 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3481 static void pre_svm_run(struct vcpu_svm
*svm
)
3483 int cpu
= raw_smp_processor_id();
3485 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3487 /* FIXME: handle wraparound of asid_generation */
3488 if (svm
->asid_generation
!= sd
->asid_generation
)
3492 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3494 struct vcpu_svm
*svm
= to_svm(vcpu
);
3496 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3497 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3498 set_intercept(svm
, INTERCEPT_IRET
);
3499 ++vcpu
->stat
.nmi_injections
;
3502 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3504 struct vmcb_control_area
*control
;
3506 control
= &svm
->vmcb
->control
;
3507 control
->int_vector
= irq
;
3508 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3509 control
->int_ctl
|= V_IRQ_MASK
|
3510 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3511 mark_dirty(svm
->vmcb
, VMCB_INTR
);
3514 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3516 struct vcpu_svm
*svm
= to_svm(vcpu
);
3518 BUG_ON(!(gif_set(svm
)));
3520 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3521 ++vcpu
->stat
.irq_injections
;
3523 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3524 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3527 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3529 struct vcpu_svm
*svm
= to_svm(vcpu
);
3531 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3538 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3541 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3543 struct vcpu_svm
*svm
= to_svm(vcpu
);
3544 struct vmcb
*vmcb
= svm
->vmcb
;
3546 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3547 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3548 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3553 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3555 struct vcpu_svm
*svm
= to_svm(vcpu
);
3557 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3560 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3562 struct vcpu_svm
*svm
= to_svm(vcpu
);
3565 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3566 set_intercept(svm
, INTERCEPT_IRET
);
3568 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3569 clr_intercept(svm
, INTERCEPT_IRET
);
3573 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3575 struct vcpu_svm
*svm
= to_svm(vcpu
);
3576 struct vmcb
*vmcb
= svm
->vmcb
;
3579 if (!gif_set(svm
) ||
3580 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3583 ret
= !!(kvm_get_rflags(vcpu
) & X86_EFLAGS_IF
);
3585 if (is_guest_mode(vcpu
))
3586 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3591 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3593 struct vcpu_svm
*svm
= to_svm(vcpu
);
3596 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3597 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3598 * get that intercept, this function will be called again though and
3599 * we'll get the vintr intercept.
3601 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3603 svm_inject_irq(svm
, 0x0);
3607 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3609 struct vcpu_svm
*svm
= to_svm(vcpu
);
3611 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3613 return; /* IRET will cause a vm exit */
3616 * Something prevents NMI from been injected. Single step over possible
3617 * problem (IRET or exception injection or interrupt shadow)
3619 svm
->nmi_singlestep
= true;
3620 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3621 update_db_intercept(vcpu
);
3624 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3629 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3631 struct vcpu_svm
*svm
= to_svm(vcpu
);
3633 if (static_cpu_has(X86_FEATURE_FLUSHBYASID
))
3634 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ASID
;
3636 svm
->asid_generation
--;
3639 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3643 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3645 struct vcpu_svm
*svm
= to_svm(vcpu
);
3647 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3650 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3651 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3652 kvm_set_cr8(vcpu
, cr8
);
3656 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3658 struct vcpu_svm
*svm
= to_svm(vcpu
);
3661 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3664 cr8
= kvm_get_cr8(vcpu
);
3665 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3666 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3669 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3673 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3674 unsigned int3_injected
= svm
->int3_injected
;
3676 svm
->int3_injected
= 0;
3679 * If we've made progress since setting HF_IRET_MASK, we've
3680 * executed an IRET and can allow NMI injection.
3682 if ((svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3683 && kvm_rip_read(&svm
->vcpu
) != svm
->nmi_iret_rip
) {
3684 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3685 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3688 svm
->vcpu
.arch
.nmi_injected
= false;
3689 kvm_clear_exception_queue(&svm
->vcpu
);
3690 kvm_clear_interrupt_queue(&svm
->vcpu
);
3692 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3695 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3697 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3698 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3701 case SVM_EXITINTINFO_TYPE_NMI
:
3702 svm
->vcpu
.arch
.nmi_injected
= true;
3704 case SVM_EXITINTINFO_TYPE_EXEPT
:
3706 * In case of software exceptions, do not reinject the vector,
3707 * but re-execute the instruction instead. Rewind RIP first
3708 * if we emulated INT3 before.
3710 if (kvm_exception_is_soft(vector
)) {
3711 if (vector
== BP_VECTOR
&& int3_injected
&&
3712 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3713 kvm_rip_write(&svm
->vcpu
,
3714 kvm_rip_read(&svm
->vcpu
) -
3718 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3719 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3720 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3723 kvm_requeue_exception(&svm
->vcpu
, vector
);
3725 case SVM_EXITINTINFO_TYPE_INTR
:
3726 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3733 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3735 struct vcpu_svm
*svm
= to_svm(vcpu
);
3736 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3738 control
->exit_int_info
= control
->event_inj
;
3739 control
->exit_int_info_err
= control
->event_inj_err
;
3740 control
->event_inj
= 0;
3741 svm_complete_interrupts(svm
);
3744 #ifdef CONFIG_X86_64
3750 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3752 struct vcpu_svm
*svm
= to_svm(vcpu
);
3754 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3755 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3756 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3759 * A vmexit emulation is required before the vcpu can be executed
3762 if (unlikely(svm
->nested
.exit_required
))
3767 sync_lapic_to_cr8(vcpu
);
3769 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3776 "push %%"R
"bp; \n\t"
3777 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3778 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3779 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3780 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3781 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3782 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3783 #ifdef CONFIG_X86_64
3784 "mov %c[r8](%[svm]), %%r8 \n\t"
3785 "mov %c[r9](%[svm]), %%r9 \n\t"
3786 "mov %c[r10](%[svm]), %%r10 \n\t"
3787 "mov %c[r11](%[svm]), %%r11 \n\t"
3788 "mov %c[r12](%[svm]), %%r12 \n\t"
3789 "mov %c[r13](%[svm]), %%r13 \n\t"
3790 "mov %c[r14](%[svm]), %%r14 \n\t"
3791 "mov %c[r15](%[svm]), %%r15 \n\t"
3794 /* Enter guest mode */
3796 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3797 __ex(SVM_VMLOAD
) "\n\t"
3798 __ex(SVM_VMRUN
) "\n\t"
3799 __ex(SVM_VMSAVE
) "\n\t"
3802 /* Save guest registers, load host registers */
3803 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3804 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3805 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3806 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3807 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3808 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3809 #ifdef CONFIG_X86_64
3810 "mov %%r8, %c[r8](%[svm]) \n\t"
3811 "mov %%r9, %c[r9](%[svm]) \n\t"
3812 "mov %%r10, %c[r10](%[svm]) \n\t"
3813 "mov %%r11, %c[r11](%[svm]) \n\t"
3814 "mov %%r12, %c[r12](%[svm]) \n\t"
3815 "mov %%r13, %c[r13](%[svm]) \n\t"
3816 "mov %%r14, %c[r14](%[svm]) \n\t"
3817 "mov %%r15, %c[r15](%[svm]) \n\t"
3822 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3823 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3824 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3825 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3826 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3827 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3828 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3829 #ifdef CONFIG_X86_64
3830 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3831 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3832 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3833 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3834 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3835 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3836 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3837 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3840 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3841 #ifdef CONFIG_X86_64
3842 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3846 #ifdef CONFIG_X86_64
3847 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3849 loadsegment(fs
, svm
->host
.fs
);
3850 #ifndef CONFIG_X86_32_LAZY_GS
3851 loadsegment(gs
, svm
->host
.gs
);
3857 local_irq_disable();
3859 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3860 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3861 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3862 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3864 trace_kvm_exit(svm
->vmcb
->control
.exit_code
, vcpu
, KVM_ISA_SVM
);
3866 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3867 kvm_before_handle_nmi(&svm
->vcpu
);
3871 /* Any pending NMI will happen here */
3873 if (unlikely(svm
->vmcb
->control
.exit_code
== SVM_EXIT_NMI
))
3874 kvm_after_handle_nmi(&svm
->vcpu
);
3876 sync_cr8_to_lapic(vcpu
);
3880 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3882 /* if exit due to PF check for async PF */
3883 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3884 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3887 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3888 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3892 * We need to handle MC intercepts here before the vcpu has a chance to
3893 * change the physical cpu
3895 if (unlikely(svm
->vmcb
->control
.exit_code
==
3896 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3897 svm_handle_mce(svm
);
3899 mark_all_clean(svm
->vmcb
);
3904 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3906 struct vcpu_svm
*svm
= to_svm(vcpu
);
3908 svm
->vmcb
->save
.cr3
= root
;
3909 mark_dirty(svm
->vmcb
, VMCB_CR
);
3910 svm_flush_tlb(vcpu
);
3913 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3915 struct vcpu_svm
*svm
= to_svm(vcpu
);
3917 svm
->vmcb
->control
.nested_cr3
= root
;
3918 mark_dirty(svm
->vmcb
, VMCB_NPT
);
3920 /* Also sync guest cr3 here in case we live migrate */
3921 svm
->vmcb
->save
.cr3
= kvm_read_cr3(vcpu
);
3922 mark_dirty(svm
->vmcb
, VMCB_CR
);
3924 svm_flush_tlb(vcpu
);
3927 static int is_disabled(void)
3931 rdmsrl(MSR_VM_CR
, vm_cr
);
3932 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3939 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3942 * Patch in the VMMCALL instruction:
3944 hypercall
[0] = 0x0f;
3945 hypercall
[1] = 0x01;
3946 hypercall
[2] = 0xd9;
3949 static void svm_check_processor_compat(void *rtn
)
3954 static bool svm_cpu_has_accelerated_tpr(void)
3959 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3964 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3968 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3973 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3976 entry
->eax
= 1; /* SVM revision 1 */
3977 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3978 ASID emulation to nested SVM */
3979 entry
->ecx
= 0; /* Reserved */
3980 entry
->edx
= 0; /* Per default do not support any
3981 additional features */
3983 /* Support next_rip if host supports it */
3984 if (boot_cpu_has(X86_FEATURE_NRIPS
))
3985 entry
->edx
|= SVM_FEATURE_NRIP
;
3987 /* Support NPT for the guest if enabled */
3989 entry
->edx
|= SVM_FEATURE_NPT
;
3995 static int svm_get_lpage_level(void)
3997 return PT_PDPE_LEVEL
;
4000 static bool svm_rdtscp_supported(void)
4005 static bool svm_has_wbinvd_exit(void)
4010 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
4012 struct vcpu_svm
*svm
= to_svm(vcpu
);
4014 set_exception_intercept(svm
, NM_VECTOR
);
4015 update_cr0_intercept(svm
);
4018 #define PRE_EX(exit) { .exit_code = (exit), \
4019 .stage = X86_ICPT_PRE_EXCEPT, }
4020 #define POST_EX(exit) { .exit_code = (exit), \
4021 .stage = X86_ICPT_POST_EXCEPT, }
4022 #define POST_MEM(exit) { .exit_code = (exit), \
4023 .stage = X86_ICPT_POST_MEMACCESS, }
4025 static struct __x86_intercept
{
4027 enum x86_intercept_stage stage
;
4028 } x86_intercept_map
[] = {
4029 [x86_intercept_cr_read
] = POST_EX(SVM_EXIT_READ_CR0
),
4030 [x86_intercept_cr_write
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4031 [x86_intercept_clts
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4032 [x86_intercept_lmsw
] = POST_EX(SVM_EXIT_WRITE_CR0
),
4033 [x86_intercept_smsw
] = POST_EX(SVM_EXIT_READ_CR0
),
4034 [x86_intercept_dr_read
] = POST_EX(SVM_EXIT_READ_DR0
),
4035 [x86_intercept_dr_write
] = POST_EX(SVM_EXIT_WRITE_DR0
),
4036 [x86_intercept_sldt
] = POST_EX(SVM_EXIT_LDTR_READ
),
4037 [x86_intercept_str
] = POST_EX(SVM_EXIT_TR_READ
),
4038 [x86_intercept_lldt
] = POST_EX(SVM_EXIT_LDTR_WRITE
),
4039 [x86_intercept_ltr
] = POST_EX(SVM_EXIT_TR_WRITE
),
4040 [x86_intercept_sgdt
] = POST_EX(SVM_EXIT_GDTR_READ
),
4041 [x86_intercept_sidt
] = POST_EX(SVM_EXIT_IDTR_READ
),
4042 [x86_intercept_lgdt
] = POST_EX(SVM_EXIT_GDTR_WRITE
),
4043 [x86_intercept_lidt
] = POST_EX(SVM_EXIT_IDTR_WRITE
),
4044 [x86_intercept_vmrun
] = POST_EX(SVM_EXIT_VMRUN
),
4045 [x86_intercept_vmmcall
] = POST_EX(SVM_EXIT_VMMCALL
),
4046 [x86_intercept_vmload
] = POST_EX(SVM_EXIT_VMLOAD
),
4047 [x86_intercept_vmsave
] = POST_EX(SVM_EXIT_VMSAVE
),
4048 [x86_intercept_stgi
] = POST_EX(SVM_EXIT_STGI
),
4049 [x86_intercept_clgi
] = POST_EX(SVM_EXIT_CLGI
),
4050 [x86_intercept_skinit
] = POST_EX(SVM_EXIT_SKINIT
),
4051 [x86_intercept_invlpga
] = POST_EX(SVM_EXIT_INVLPGA
),
4052 [x86_intercept_rdtscp
] = POST_EX(SVM_EXIT_RDTSCP
),
4053 [x86_intercept_monitor
] = POST_MEM(SVM_EXIT_MONITOR
),
4054 [x86_intercept_mwait
] = POST_EX(SVM_EXIT_MWAIT
),
4055 [x86_intercept_invlpg
] = POST_EX(SVM_EXIT_INVLPG
),
4056 [x86_intercept_invd
] = POST_EX(SVM_EXIT_INVD
),
4057 [x86_intercept_wbinvd
] = POST_EX(SVM_EXIT_WBINVD
),
4058 [x86_intercept_wrmsr
] = POST_EX(SVM_EXIT_MSR
),
4059 [x86_intercept_rdtsc
] = POST_EX(SVM_EXIT_RDTSC
),
4060 [x86_intercept_rdmsr
] = POST_EX(SVM_EXIT_MSR
),
4061 [x86_intercept_rdpmc
] = POST_EX(SVM_EXIT_RDPMC
),
4062 [x86_intercept_cpuid
] = PRE_EX(SVM_EXIT_CPUID
),
4063 [x86_intercept_rsm
] = PRE_EX(SVM_EXIT_RSM
),
4064 [x86_intercept_pause
] = PRE_EX(SVM_EXIT_PAUSE
),
4065 [x86_intercept_pushf
] = PRE_EX(SVM_EXIT_PUSHF
),
4066 [x86_intercept_popf
] = PRE_EX(SVM_EXIT_POPF
),
4067 [x86_intercept_intn
] = PRE_EX(SVM_EXIT_SWINT
),
4068 [x86_intercept_iret
] = PRE_EX(SVM_EXIT_IRET
),
4069 [x86_intercept_icebp
] = PRE_EX(SVM_EXIT_ICEBP
),
4070 [x86_intercept_hlt
] = POST_EX(SVM_EXIT_HLT
),
4071 [x86_intercept_in
] = POST_EX(SVM_EXIT_IOIO
),
4072 [x86_intercept_ins
] = POST_EX(SVM_EXIT_IOIO
),
4073 [x86_intercept_out
] = POST_EX(SVM_EXIT_IOIO
),
4074 [x86_intercept_outs
] = POST_EX(SVM_EXIT_IOIO
),
4081 static int svm_check_intercept(struct kvm_vcpu
*vcpu
,
4082 struct x86_instruction_info
*info
,
4083 enum x86_intercept_stage stage
)
4085 struct vcpu_svm
*svm
= to_svm(vcpu
);
4086 int vmexit
, ret
= X86EMUL_CONTINUE
;
4087 struct __x86_intercept icpt_info
;
4088 struct vmcb
*vmcb
= svm
->vmcb
;
4090 if (info
->intercept
>= ARRAY_SIZE(x86_intercept_map
))
4093 icpt_info
= x86_intercept_map
[info
->intercept
];
4095 if (stage
!= icpt_info
.stage
)
4098 switch (icpt_info
.exit_code
) {
4099 case SVM_EXIT_READ_CR0
:
4100 if (info
->intercept
== x86_intercept_cr_read
)
4101 icpt_info
.exit_code
+= info
->modrm_reg
;
4103 case SVM_EXIT_WRITE_CR0
: {
4104 unsigned long cr0
, val
;
4107 if (info
->intercept
== x86_intercept_cr_write
)
4108 icpt_info
.exit_code
+= info
->modrm_reg
;
4110 if (icpt_info
.exit_code
!= SVM_EXIT_WRITE_CR0
)
4113 intercept
= svm
->nested
.intercept
;
4115 if (!(intercept
& (1ULL << INTERCEPT_SELECTIVE_CR0
)))
4118 cr0
= vcpu
->arch
.cr0
& ~SVM_CR0_SELECTIVE_MASK
;
4119 val
= info
->src_val
& ~SVM_CR0_SELECTIVE_MASK
;
4121 if (info
->intercept
== x86_intercept_lmsw
) {
4124 /* lmsw can't clear PE - catch this here */
4125 if (cr0
& X86_CR0_PE
)
4130 icpt_info
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
4134 case SVM_EXIT_READ_DR0
:
4135 case SVM_EXIT_WRITE_DR0
:
4136 icpt_info
.exit_code
+= info
->modrm_reg
;
4139 if (info
->intercept
== x86_intercept_wrmsr
)
4140 vmcb
->control
.exit_info_1
= 1;
4142 vmcb
->control
.exit_info_1
= 0;
4144 case SVM_EXIT_PAUSE
:
4146 * We get this for NOP only, but pause
4147 * is rep not, check this here
4149 if (info
->rep_prefix
!= REPE_PREFIX
)
4151 case SVM_EXIT_IOIO
: {
4155 exit_info
= (vcpu
->arch
.regs
[VCPU_REGS_RDX
] & 0xffff) << 16;
4157 if (info
->intercept
== x86_intercept_in
||
4158 info
->intercept
== x86_intercept_ins
) {
4159 exit_info
|= SVM_IOIO_TYPE_MASK
;
4160 bytes
= info
->src_bytes
;
4162 bytes
= info
->dst_bytes
;
4165 if (info
->intercept
== x86_intercept_outs
||
4166 info
->intercept
== x86_intercept_ins
)
4167 exit_info
|= SVM_IOIO_STR_MASK
;
4169 if (info
->rep_prefix
)
4170 exit_info
|= SVM_IOIO_REP_MASK
;
4172 bytes
= min(bytes
, 4u);
4174 exit_info
|= bytes
<< SVM_IOIO_SIZE_SHIFT
;
4176 exit_info
|= (u32
)info
->ad_bytes
<< (SVM_IOIO_ASIZE_SHIFT
- 1);
4178 vmcb
->control
.exit_info_1
= exit_info
;
4179 vmcb
->control
.exit_info_2
= info
->next_rip
;
4187 vmcb
->control
.next_rip
= info
->next_rip
;
4188 vmcb
->control
.exit_code
= icpt_info
.exit_code
;
4189 vmexit
= nested_svm_exit_handled(svm
);
4191 ret
= (vmexit
== NESTED_EXIT_DONE
) ? X86EMUL_INTERCEPTED
4198 static struct kvm_x86_ops svm_x86_ops
= {
4199 .cpu_has_kvm_support
= has_svm
,
4200 .disabled_by_bios
= is_disabled
,
4201 .hardware_setup
= svm_hardware_setup
,
4202 .hardware_unsetup
= svm_hardware_unsetup
,
4203 .check_processor_compatibility
= svm_check_processor_compat
,
4204 .hardware_enable
= svm_hardware_enable
,
4205 .hardware_disable
= svm_hardware_disable
,
4206 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
4208 .vcpu_create
= svm_create_vcpu
,
4209 .vcpu_free
= svm_free_vcpu
,
4210 .vcpu_reset
= svm_vcpu_reset
,
4212 .prepare_guest_switch
= svm_prepare_guest_switch
,
4213 .vcpu_load
= svm_vcpu_load
,
4214 .vcpu_put
= svm_vcpu_put
,
4216 .set_guest_debug
= svm_guest_debug
,
4217 .get_msr
= svm_get_msr
,
4218 .set_msr
= svm_set_msr
,
4219 .get_segment_base
= svm_get_segment_base
,
4220 .get_segment
= svm_get_segment
,
4221 .set_segment
= svm_set_segment
,
4222 .get_cpl
= svm_get_cpl
,
4223 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
4224 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
4225 .decache_cr3
= svm_decache_cr3
,
4226 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
4227 .set_cr0
= svm_set_cr0
,
4228 .set_cr3
= svm_set_cr3
,
4229 .set_cr4
= svm_set_cr4
,
4230 .set_efer
= svm_set_efer
,
4231 .get_idt
= svm_get_idt
,
4232 .set_idt
= svm_set_idt
,
4233 .get_gdt
= svm_get_gdt
,
4234 .set_gdt
= svm_set_gdt
,
4235 .set_dr7
= svm_set_dr7
,
4236 .cache_reg
= svm_cache_reg
,
4237 .get_rflags
= svm_get_rflags
,
4238 .set_rflags
= svm_set_rflags
,
4239 .fpu_activate
= svm_fpu_activate
,
4240 .fpu_deactivate
= svm_fpu_deactivate
,
4242 .tlb_flush
= svm_flush_tlb
,
4244 .run
= svm_vcpu_run
,
4245 .handle_exit
= handle_exit
,
4246 .skip_emulated_instruction
= skip_emulated_instruction
,
4247 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
4248 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
4249 .patch_hypercall
= svm_patch_hypercall
,
4250 .set_irq
= svm_set_irq
,
4251 .set_nmi
= svm_inject_nmi
,
4252 .queue_exception
= svm_queue_exception
,
4253 .cancel_injection
= svm_cancel_injection
,
4254 .interrupt_allowed
= svm_interrupt_allowed
,
4255 .nmi_allowed
= svm_nmi_allowed
,
4256 .get_nmi_mask
= svm_get_nmi_mask
,
4257 .set_nmi_mask
= svm_set_nmi_mask
,
4258 .enable_nmi_window
= enable_nmi_window
,
4259 .enable_irq_window
= enable_irq_window
,
4260 .update_cr8_intercept
= update_cr8_intercept
,
4262 .set_tss_addr
= svm_set_tss_addr
,
4263 .get_tdp_level
= get_npt_level
,
4264 .get_mt_mask
= svm_get_mt_mask
,
4266 .get_exit_info
= svm_get_exit_info
,
4268 .get_lpage_level
= svm_get_lpage_level
,
4270 .cpuid_update
= svm_cpuid_update
,
4272 .rdtscp_supported
= svm_rdtscp_supported
,
4274 .set_supported_cpuid
= svm_set_supported_cpuid
,
4276 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
4278 .set_tsc_khz
= svm_set_tsc_khz
,
4279 .write_tsc_offset
= svm_write_tsc_offset
,
4280 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
4281 .compute_tsc_offset
= svm_compute_tsc_offset
,
4282 .read_l1_tsc
= svm_read_l1_tsc
,
4284 .set_tdp_cr3
= set_tdp_cr3
,
4286 .check_intercept
= svm_check_intercept
,
4289 static int __init
svm_init(void)
4291 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
4292 __alignof__(struct vcpu_svm
), THIS_MODULE
);
4295 static void __exit
svm_exit(void)
4300 module_init(svm_init
)
4301 module_exit(svm_exit
)