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KVM: SVM: copy only necessary parts of the control area on vmrun/vmexit
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49
50 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
51
52 /* Turn on to get debugging output*/
53 /* #define NESTED_DEBUG */
54
55 #ifdef NESTED_DEBUG
56 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
57 #else
58 #define nsvm_printk(fmt, args...) do {} while(0)
59 #endif
60
61 static const u32 host_save_user_msrs[] = {
62 #ifdef CONFIG_X86_64
63 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
64 MSR_FS_BASE,
65 #endif
66 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
67 };
68
69 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
70
71 struct kvm_vcpu;
72
73 struct vcpu_svm {
74 struct kvm_vcpu vcpu;
75 struct vmcb *vmcb;
76 unsigned long vmcb_pa;
77 struct svm_cpu_data *svm_data;
78 uint64_t asid_generation;
79 uint64_t sysenter_esp;
80 uint64_t sysenter_eip;
81
82 u64 next_rip;
83
84 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
85 u64 host_gs_base;
86
87 u32 *msrpm;
88 struct vmcb *hsave;
89 u64 hsave_msr;
90
91 u64 nested_vmcb;
92
93 /* These are the merged vectors */
94 u32 *nested_msrpm;
95
96 /* gpa pointers to the real vectors */
97 u64 nested_vmcb_msrpm;
98 };
99
100 /* enable NPT for AMD64 and X86 with PAE */
101 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
102 static bool npt_enabled = true;
103 #else
104 static bool npt_enabled = false;
105 #endif
106 static int npt = 1;
107
108 module_param(npt, int, S_IRUGO);
109
110 static int nested = 0;
111 module_param(nested, int, S_IRUGO);
112
113 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
114
115 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
116 static int nested_svm_vmexit(struct vcpu_svm *svm);
117 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
118 void *arg2, void *opaque);
119 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
120 bool has_error_code, u32 error_code);
121
122 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
123 {
124 return container_of(vcpu, struct vcpu_svm, vcpu);
125 }
126
127 static inline bool is_nested(struct vcpu_svm *svm)
128 {
129 return svm->nested_vmcb;
130 }
131
132 static inline void enable_gif(struct vcpu_svm *svm)
133 {
134 svm->vcpu.arch.hflags |= HF_GIF_MASK;
135 }
136
137 static inline void disable_gif(struct vcpu_svm *svm)
138 {
139 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
140 }
141
142 static inline bool gif_set(struct vcpu_svm *svm)
143 {
144 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
145 }
146
147 static unsigned long iopm_base;
148
149 struct kvm_ldttss_desc {
150 u16 limit0;
151 u16 base0;
152 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
153 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
154 u32 base3;
155 u32 zero1;
156 } __attribute__((packed));
157
158 struct svm_cpu_data {
159 int cpu;
160
161 u64 asid_generation;
162 u32 max_asid;
163 u32 next_asid;
164 struct kvm_ldttss_desc *tss_desc;
165
166 struct page *save_area;
167 };
168
169 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
170 static uint32_t svm_features;
171
172 struct svm_init_data {
173 int cpu;
174 int r;
175 };
176
177 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
178
179 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
180 #define MSRS_RANGE_SIZE 2048
181 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
182
183 #define MAX_INST_SIZE 15
184
185 static inline u32 svm_has(u32 feat)
186 {
187 return svm_features & feat;
188 }
189
190 static inline void clgi(void)
191 {
192 asm volatile (__ex(SVM_CLGI));
193 }
194
195 static inline void stgi(void)
196 {
197 asm volatile (__ex(SVM_STGI));
198 }
199
200 static inline void invlpga(unsigned long addr, u32 asid)
201 {
202 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
203 }
204
205 static inline void force_new_asid(struct kvm_vcpu *vcpu)
206 {
207 to_svm(vcpu)->asid_generation--;
208 }
209
210 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
211 {
212 force_new_asid(vcpu);
213 }
214
215 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
216 {
217 if (!npt_enabled && !(efer & EFER_LMA))
218 efer &= ~EFER_LME;
219
220 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
221 vcpu->arch.shadow_efer = efer;
222 }
223
224 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
225 bool has_error_code, u32 error_code)
226 {
227 struct vcpu_svm *svm = to_svm(vcpu);
228
229 /* If we are within a nested VM we'd better #VMEXIT and let the
230 guest handle the exception */
231 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
232 return;
233
234 svm->vmcb->control.event_inj = nr
235 | SVM_EVTINJ_VALID
236 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
237 | SVM_EVTINJ_TYPE_EXEPT;
238 svm->vmcb->control.event_inj_err = error_code;
239 }
240
241 static int is_external_interrupt(u32 info)
242 {
243 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
244 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
245 }
246
247 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
248 {
249 struct vcpu_svm *svm = to_svm(vcpu);
250 u32 ret = 0;
251
252 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
253 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
254 return ret & mask;
255 }
256
257 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
258 {
259 struct vcpu_svm *svm = to_svm(vcpu);
260
261 if (mask == 0)
262 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
263 else
264 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
265
266 }
267
268 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
269 {
270 struct vcpu_svm *svm = to_svm(vcpu);
271
272 if (!svm->next_rip) {
273 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
274 EMULATE_DONE)
275 printk(KERN_DEBUG "%s: NOP\n", __func__);
276 return;
277 }
278 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
279 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
280 __func__, kvm_rip_read(vcpu), svm->next_rip);
281
282 kvm_rip_write(vcpu, svm->next_rip);
283 svm_set_interrupt_shadow(vcpu, 0);
284 }
285
286 static int has_svm(void)
287 {
288 const char *msg;
289
290 if (!cpu_has_svm(&msg)) {
291 printk(KERN_INFO "has_svm: %s\n", msg);
292 return 0;
293 }
294
295 return 1;
296 }
297
298 static void svm_hardware_disable(void *garbage)
299 {
300 cpu_svm_disable();
301 }
302
303 static void svm_hardware_enable(void *garbage)
304 {
305
306 struct svm_cpu_data *svm_data;
307 uint64_t efer;
308 struct descriptor_table gdt_descr;
309 struct desc_struct *gdt;
310 int me = raw_smp_processor_id();
311
312 if (!has_svm()) {
313 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
314 return;
315 }
316 svm_data = per_cpu(svm_data, me);
317
318 if (!svm_data) {
319 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
320 me);
321 return;
322 }
323
324 svm_data->asid_generation = 1;
325 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
326 svm_data->next_asid = svm_data->max_asid + 1;
327
328 kvm_get_gdt(&gdt_descr);
329 gdt = (struct desc_struct *)gdt_descr.base;
330 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
331
332 rdmsrl(MSR_EFER, efer);
333 wrmsrl(MSR_EFER, efer | EFER_SVME);
334
335 wrmsrl(MSR_VM_HSAVE_PA,
336 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
337 }
338
339 static void svm_cpu_uninit(int cpu)
340 {
341 struct svm_cpu_data *svm_data
342 = per_cpu(svm_data, raw_smp_processor_id());
343
344 if (!svm_data)
345 return;
346
347 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
348 __free_page(svm_data->save_area);
349 kfree(svm_data);
350 }
351
352 static int svm_cpu_init(int cpu)
353 {
354 struct svm_cpu_data *svm_data;
355 int r;
356
357 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
358 if (!svm_data)
359 return -ENOMEM;
360 svm_data->cpu = cpu;
361 svm_data->save_area = alloc_page(GFP_KERNEL);
362 r = -ENOMEM;
363 if (!svm_data->save_area)
364 goto err_1;
365
366 per_cpu(svm_data, cpu) = svm_data;
367
368 return 0;
369
370 err_1:
371 kfree(svm_data);
372 return r;
373
374 }
375
376 static void set_msr_interception(u32 *msrpm, unsigned msr,
377 int read, int write)
378 {
379 int i;
380
381 for (i = 0; i < NUM_MSR_MAPS; i++) {
382 if (msr >= msrpm_ranges[i] &&
383 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
384 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
385 msrpm_ranges[i]) * 2;
386
387 u32 *base = msrpm + (msr_offset / 32);
388 u32 msr_shift = msr_offset % 32;
389 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
390 *base = (*base & ~(0x3 << msr_shift)) |
391 (mask << msr_shift);
392 return;
393 }
394 }
395 BUG();
396 }
397
398 static void svm_vcpu_init_msrpm(u32 *msrpm)
399 {
400 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
401
402 #ifdef CONFIG_X86_64
403 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
404 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
405 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
406 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
407 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
408 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
409 #endif
410 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
411 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
412 }
413
414 static void svm_enable_lbrv(struct vcpu_svm *svm)
415 {
416 u32 *msrpm = svm->msrpm;
417
418 svm->vmcb->control.lbr_ctl = 1;
419 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
420 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
421 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
422 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
423 }
424
425 static void svm_disable_lbrv(struct vcpu_svm *svm)
426 {
427 u32 *msrpm = svm->msrpm;
428
429 svm->vmcb->control.lbr_ctl = 0;
430 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
431 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
432 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
433 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
434 }
435
436 static __init int svm_hardware_setup(void)
437 {
438 int cpu;
439 struct page *iopm_pages;
440 void *iopm_va;
441 int r;
442
443 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
444
445 if (!iopm_pages)
446 return -ENOMEM;
447
448 iopm_va = page_address(iopm_pages);
449 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
450 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
451
452 if (boot_cpu_has(X86_FEATURE_NX))
453 kvm_enable_efer_bits(EFER_NX);
454
455 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
456 kvm_enable_efer_bits(EFER_FFXSR);
457
458 if (nested) {
459 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
460 kvm_enable_efer_bits(EFER_SVME);
461 }
462
463 for_each_online_cpu(cpu) {
464 r = svm_cpu_init(cpu);
465 if (r)
466 goto err;
467 }
468
469 svm_features = cpuid_edx(SVM_CPUID_FUNC);
470
471 if (!svm_has(SVM_FEATURE_NPT))
472 npt_enabled = false;
473
474 if (npt_enabled && !npt) {
475 printk(KERN_INFO "kvm: Nested Paging disabled\n");
476 npt_enabled = false;
477 }
478
479 if (npt_enabled) {
480 printk(KERN_INFO "kvm: Nested Paging enabled\n");
481 kvm_enable_tdp();
482 } else
483 kvm_disable_tdp();
484
485 return 0;
486
487 err:
488 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
489 iopm_base = 0;
490 return r;
491 }
492
493 static __exit void svm_hardware_unsetup(void)
494 {
495 int cpu;
496
497 for_each_online_cpu(cpu)
498 svm_cpu_uninit(cpu);
499
500 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
501 iopm_base = 0;
502 }
503
504 static void init_seg(struct vmcb_seg *seg)
505 {
506 seg->selector = 0;
507 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
508 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
509 seg->limit = 0xffff;
510 seg->base = 0;
511 }
512
513 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
514 {
515 seg->selector = 0;
516 seg->attrib = SVM_SELECTOR_P_MASK | type;
517 seg->limit = 0xffff;
518 seg->base = 0;
519 }
520
521 static void init_vmcb(struct vcpu_svm *svm)
522 {
523 struct vmcb_control_area *control = &svm->vmcb->control;
524 struct vmcb_save_area *save = &svm->vmcb->save;
525
526 control->intercept_cr_read = INTERCEPT_CR0_MASK |
527 INTERCEPT_CR3_MASK |
528 INTERCEPT_CR4_MASK;
529
530 control->intercept_cr_write = INTERCEPT_CR0_MASK |
531 INTERCEPT_CR3_MASK |
532 INTERCEPT_CR4_MASK |
533 INTERCEPT_CR8_MASK;
534
535 control->intercept_dr_read = INTERCEPT_DR0_MASK |
536 INTERCEPT_DR1_MASK |
537 INTERCEPT_DR2_MASK |
538 INTERCEPT_DR3_MASK;
539
540 control->intercept_dr_write = INTERCEPT_DR0_MASK |
541 INTERCEPT_DR1_MASK |
542 INTERCEPT_DR2_MASK |
543 INTERCEPT_DR3_MASK |
544 INTERCEPT_DR5_MASK |
545 INTERCEPT_DR7_MASK;
546
547 control->intercept_exceptions = (1 << PF_VECTOR) |
548 (1 << UD_VECTOR) |
549 (1 << MC_VECTOR);
550
551
552 control->intercept = (1ULL << INTERCEPT_INTR) |
553 (1ULL << INTERCEPT_NMI) |
554 (1ULL << INTERCEPT_SMI) |
555 (1ULL << INTERCEPT_CPUID) |
556 (1ULL << INTERCEPT_INVD) |
557 (1ULL << INTERCEPT_HLT) |
558 (1ULL << INTERCEPT_INVLPG) |
559 (1ULL << INTERCEPT_INVLPGA) |
560 (1ULL << INTERCEPT_IOIO_PROT) |
561 (1ULL << INTERCEPT_MSR_PROT) |
562 (1ULL << INTERCEPT_TASK_SWITCH) |
563 (1ULL << INTERCEPT_SHUTDOWN) |
564 (1ULL << INTERCEPT_VMRUN) |
565 (1ULL << INTERCEPT_VMMCALL) |
566 (1ULL << INTERCEPT_VMLOAD) |
567 (1ULL << INTERCEPT_VMSAVE) |
568 (1ULL << INTERCEPT_STGI) |
569 (1ULL << INTERCEPT_CLGI) |
570 (1ULL << INTERCEPT_SKINIT) |
571 (1ULL << INTERCEPT_WBINVD) |
572 (1ULL << INTERCEPT_MONITOR) |
573 (1ULL << INTERCEPT_MWAIT);
574
575 control->iopm_base_pa = iopm_base;
576 control->msrpm_base_pa = __pa(svm->msrpm);
577 control->tsc_offset = 0;
578 control->int_ctl = V_INTR_MASKING_MASK;
579
580 init_seg(&save->es);
581 init_seg(&save->ss);
582 init_seg(&save->ds);
583 init_seg(&save->fs);
584 init_seg(&save->gs);
585
586 save->cs.selector = 0xf000;
587 /* Executable/Readable Code Segment */
588 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
589 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
590 save->cs.limit = 0xffff;
591 /*
592 * cs.base should really be 0xffff0000, but vmx can't handle that, so
593 * be consistent with it.
594 *
595 * Replace when we have real mode working for vmx.
596 */
597 save->cs.base = 0xf0000;
598
599 save->gdtr.limit = 0xffff;
600 save->idtr.limit = 0xffff;
601
602 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
603 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
604
605 save->efer = EFER_SVME;
606 save->dr6 = 0xffff0ff0;
607 save->dr7 = 0x400;
608 save->rflags = 2;
609 save->rip = 0x0000fff0;
610 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
611
612 /*
613 * cr0 val on cpu init should be 0x60000010, we enable cpu
614 * cache by default. the orderly way is to enable cache in bios.
615 */
616 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
617 save->cr4 = X86_CR4_PAE;
618 /* rdx = ?? */
619
620 if (npt_enabled) {
621 /* Setup VMCB for Nested Paging */
622 control->nested_ctl = 1;
623 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
624 (1ULL << INTERCEPT_INVLPG));
625 control->intercept_exceptions &= ~(1 << PF_VECTOR);
626 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
627 INTERCEPT_CR3_MASK);
628 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
629 INTERCEPT_CR3_MASK);
630 save->g_pat = 0x0007040600070406ULL;
631 /* enable caching because the QEMU Bios doesn't enable it */
632 save->cr0 = X86_CR0_ET;
633 save->cr3 = 0;
634 save->cr4 = 0;
635 }
636 force_new_asid(&svm->vcpu);
637
638 svm->nested_vmcb = 0;
639 svm->vcpu.arch.hflags = 0;
640
641 enable_gif(svm);
642 }
643
644 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
645 {
646 struct vcpu_svm *svm = to_svm(vcpu);
647
648 init_vmcb(svm);
649
650 if (!kvm_vcpu_is_bsp(vcpu)) {
651 kvm_rip_write(vcpu, 0);
652 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
653 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
654 }
655 vcpu->arch.regs_avail = ~0;
656 vcpu->arch.regs_dirty = ~0;
657
658 return 0;
659 }
660
661 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
662 {
663 struct vcpu_svm *svm;
664 struct page *page;
665 struct page *msrpm_pages;
666 struct page *hsave_page;
667 struct page *nested_msrpm_pages;
668 int err;
669
670 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
671 if (!svm) {
672 err = -ENOMEM;
673 goto out;
674 }
675
676 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
677 if (err)
678 goto free_svm;
679
680 page = alloc_page(GFP_KERNEL);
681 if (!page) {
682 err = -ENOMEM;
683 goto uninit;
684 }
685
686 err = -ENOMEM;
687 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
688 if (!msrpm_pages)
689 goto uninit;
690
691 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
692 if (!nested_msrpm_pages)
693 goto uninit;
694
695 svm->msrpm = page_address(msrpm_pages);
696 svm_vcpu_init_msrpm(svm->msrpm);
697
698 hsave_page = alloc_page(GFP_KERNEL);
699 if (!hsave_page)
700 goto uninit;
701 svm->hsave = page_address(hsave_page);
702
703 svm->nested_msrpm = page_address(nested_msrpm_pages);
704
705 svm->vmcb = page_address(page);
706 clear_page(svm->vmcb);
707 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
708 svm->asid_generation = 0;
709 init_vmcb(svm);
710
711 fx_init(&svm->vcpu);
712 svm->vcpu.fpu_active = 1;
713 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
714 if (kvm_vcpu_is_bsp(&svm->vcpu))
715 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
716
717 return &svm->vcpu;
718
719 uninit:
720 kvm_vcpu_uninit(&svm->vcpu);
721 free_svm:
722 kmem_cache_free(kvm_vcpu_cache, svm);
723 out:
724 return ERR_PTR(err);
725 }
726
727 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
728 {
729 struct vcpu_svm *svm = to_svm(vcpu);
730
731 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
732 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
733 __free_page(virt_to_page(svm->hsave));
734 __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
735 kvm_vcpu_uninit(vcpu);
736 kmem_cache_free(kvm_vcpu_cache, svm);
737 }
738
739 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
740 {
741 struct vcpu_svm *svm = to_svm(vcpu);
742 int i;
743
744 if (unlikely(cpu != vcpu->cpu)) {
745 u64 tsc_this, delta;
746
747 /*
748 * Make sure that the guest sees a monotonically
749 * increasing TSC.
750 */
751 rdtscll(tsc_this);
752 delta = vcpu->arch.host_tsc - tsc_this;
753 svm->vmcb->control.tsc_offset += delta;
754 vcpu->cpu = cpu;
755 kvm_migrate_timers(vcpu);
756 svm->asid_generation = 0;
757 }
758
759 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
760 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
761 }
762
763 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
764 {
765 struct vcpu_svm *svm = to_svm(vcpu);
766 int i;
767
768 ++vcpu->stat.host_state_reload;
769 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
770 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
771
772 rdtscll(vcpu->arch.host_tsc);
773 }
774
775 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
776 {
777 return to_svm(vcpu)->vmcb->save.rflags;
778 }
779
780 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
781 {
782 to_svm(vcpu)->vmcb->save.rflags = rflags;
783 }
784
785 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
786 {
787 switch (reg) {
788 case VCPU_EXREG_PDPTR:
789 BUG_ON(!npt_enabled);
790 load_pdptrs(vcpu, vcpu->arch.cr3);
791 break;
792 default:
793 BUG();
794 }
795 }
796
797 static void svm_set_vintr(struct vcpu_svm *svm)
798 {
799 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
800 }
801
802 static void svm_clear_vintr(struct vcpu_svm *svm)
803 {
804 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
805 }
806
807 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
808 {
809 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
810
811 switch (seg) {
812 case VCPU_SREG_CS: return &save->cs;
813 case VCPU_SREG_DS: return &save->ds;
814 case VCPU_SREG_ES: return &save->es;
815 case VCPU_SREG_FS: return &save->fs;
816 case VCPU_SREG_GS: return &save->gs;
817 case VCPU_SREG_SS: return &save->ss;
818 case VCPU_SREG_TR: return &save->tr;
819 case VCPU_SREG_LDTR: return &save->ldtr;
820 }
821 BUG();
822 return NULL;
823 }
824
825 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
826 {
827 struct vmcb_seg *s = svm_seg(vcpu, seg);
828
829 return s->base;
830 }
831
832 static void svm_get_segment(struct kvm_vcpu *vcpu,
833 struct kvm_segment *var, int seg)
834 {
835 struct vmcb_seg *s = svm_seg(vcpu, seg);
836
837 var->base = s->base;
838 var->limit = s->limit;
839 var->selector = s->selector;
840 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
841 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
842 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
843 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
844 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
845 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
846 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
847 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
848
849 /* AMD's VMCB does not have an explicit unusable field, so emulate it
850 * for cross vendor migration purposes by "not present"
851 */
852 var->unusable = !var->present || (var->type == 0);
853
854 switch (seg) {
855 case VCPU_SREG_CS:
856 /*
857 * SVM always stores 0 for the 'G' bit in the CS selector in
858 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
859 * Intel's VMENTRY has a check on the 'G' bit.
860 */
861 var->g = s->limit > 0xfffff;
862 break;
863 case VCPU_SREG_TR:
864 /*
865 * Work around a bug where the busy flag in the tr selector
866 * isn't exposed
867 */
868 var->type |= 0x2;
869 break;
870 case VCPU_SREG_DS:
871 case VCPU_SREG_ES:
872 case VCPU_SREG_FS:
873 case VCPU_SREG_GS:
874 /*
875 * The accessed bit must always be set in the segment
876 * descriptor cache, although it can be cleared in the
877 * descriptor, the cached bit always remains at 1. Since
878 * Intel has a check on this, set it here to support
879 * cross-vendor migration.
880 */
881 if (!var->unusable)
882 var->type |= 0x1;
883 break;
884 case VCPU_SREG_SS:
885 /* On AMD CPUs sometimes the DB bit in the segment
886 * descriptor is left as 1, although the whole segment has
887 * been made unusable. Clear it here to pass an Intel VMX
888 * entry check when cross vendor migrating.
889 */
890 if (var->unusable)
891 var->db = 0;
892 break;
893 }
894 }
895
896 static int svm_get_cpl(struct kvm_vcpu *vcpu)
897 {
898 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
899
900 return save->cpl;
901 }
902
903 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
904 {
905 struct vcpu_svm *svm = to_svm(vcpu);
906
907 dt->limit = svm->vmcb->save.idtr.limit;
908 dt->base = svm->vmcb->save.idtr.base;
909 }
910
911 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
912 {
913 struct vcpu_svm *svm = to_svm(vcpu);
914
915 svm->vmcb->save.idtr.limit = dt->limit;
916 svm->vmcb->save.idtr.base = dt->base ;
917 }
918
919 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
920 {
921 struct vcpu_svm *svm = to_svm(vcpu);
922
923 dt->limit = svm->vmcb->save.gdtr.limit;
924 dt->base = svm->vmcb->save.gdtr.base;
925 }
926
927 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
928 {
929 struct vcpu_svm *svm = to_svm(vcpu);
930
931 svm->vmcb->save.gdtr.limit = dt->limit;
932 svm->vmcb->save.gdtr.base = dt->base ;
933 }
934
935 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
936 {
937 }
938
939 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
940 {
941 struct vcpu_svm *svm = to_svm(vcpu);
942
943 #ifdef CONFIG_X86_64
944 if (vcpu->arch.shadow_efer & EFER_LME) {
945 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
946 vcpu->arch.shadow_efer |= EFER_LMA;
947 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
948 }
949
950 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
951 vcpu->arch.shadow_efer &= ~EFER_LMA;
952 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
953 }
954 }
955 #endif
956 if (npt_enabled)
957 goto set;
958
959 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
960 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
961 vcpu->fpu_active = 1;
962 }
963
964 vcpu->arch.cr0 = cr0;
965 cr0 |= X86_CR0_PG | X86_CR0_WP;
966 if (!vcpu->fpu_active) {
967 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
968 cr0 |= X86_CR0_TS;
969 }
970 set:
971 /*
972 * re-enable caching here because the QEMU bios
973 * does not do it - this results in some delay at
974 * reboot
975 */
976 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
977 svm->vmcb->save.cr0 = cr0;
978 }
979
980 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
981 {
982 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
983 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
984
985 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
986 force_new_asid(vcpu);
987
988 vcpu->arch.cr4 = cr4;
989 if (!npt_enabled)
990 cr4 |= X86_CR4_PAE;
991 cr4 |= host_cr4_mce;
992 to_svm(vcpu)->vmcb->save.cr4 = cr4;
993 }
994
995 static void svm_set_segment(struct kvm_vcpu *vcpu,
996 struct kvm_segment *var, int seg)
997 {
998 struct vcpu_svm *svm = to_svm(vcpu);
999 struct vmcb_seg *s = svm_seg(vcpu, seg);
1000
1001 s->base = var->base;
1002 s->limit = var->limit;
1003 s->selector = var->selector;
1004 if (var->unusable)
1005 s->attrib = 0;
1006 else {
1007 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1008 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1009 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1010 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1011 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1012 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1013 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1014 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1015 }
1016 if (seg == VCPU_SREG_CS)
1017 svm->vmcb->save.cpl
1018 = (svm->vmcb->save.cs.attrib
1019 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1020
1021 }
1022
1023 static void update_db_intercept(struct kvm_vcpu *vcpu)
1024 {
1025 struct vcpu_svm *svm = to_svm(vcpu);
1026
1027 svm->vmcb->control.intercept_exceptions &=
1028 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1029
1030 if (vcpu->arch.singlestep)
1031 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1032
1033 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1034 if (vcpu->guest_debug &
1035 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1036 svm->vmcb->control.intercept_exceptions |=
1037 1 << DB_VECTOR;
1038 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1039 svm->vmcb->control.intercept_exceptions |=
1040 1 << BP_VECTOR;
1041 } else
1042 vcpu->guest_debug = 0;
1043 }
1044
1045 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1046 {
1047 int old_debug = vcpu->guest_debug;
1048 struct vcpu_svm *svm = to_svm(vcpu);
1049
1050 vcpu->guest_debug = dbg->control;
1051
1052 update_db_intercept(vcpu);
1053
1054 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1055 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1056 else
1057 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1058
1059 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1060 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1061 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1062 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1063
1064 return 0;
1065 }
1066
1067 static void load_host_msrs(struct kvm_vcpu *vcpu)
1068 {
1069 #ifdef CONFIG_X86_64
1070 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1071 #endif
1072 }
1073
1074 static void save_host_msrs(struct kvm_vcpu *vcpu)
1075 {
1076 #ifdef CONFIG_X86_64
1077 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1078 #endif
1079 }
1080
1081 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1082 {
1083 if (svm_data->next_asid > svm_data->max_asid) {
1084 ++svm_data->asid_generation;
1085 svm_data->next_asid = 1;
1086 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1087 }
1088
1089 svm->asid_generation = svm_data->asid_generation;
1090 svm->vmcb->control.asid = svm_data->next_asid++;
1091 }
1092
1093 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1094 {
1095 struct vcpu_svm *svm = to_svm(vcpu);
1096 unsigned long val;
1097
1098 switch (dr) {
1099 case 0 ... 3:
1100 val = vcpu->arch.db[dr];
1101 break;
1102 case 6:
1103 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1104 val = vcpu->arch.dr6;
1105 else
1106 val = svm->vmcb->save.dr6;
1107 break;
1108 case 7:
1109 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1110 val = vcpu->arch.dr7;
1111 else
1112 val = svm->vmcb->save.dr7;
1113 break;
1114 default:
1115 val = 0;
1116 }
1117
1118 return val;
1119 }
1120
1121 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1122 int *exception)
1123 {
1124 struct vcpu_svm *svm = to_svm(vcpu);
1125
1126 *exception = 0;
1127
1128 switch (dr) {
1129 case 0 ... 3:
1130 vcpu->arch.db[dr] = value;
1131 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1132 vcpu->arch.eff_db[dr] = value;
1133 return;
1134 case 4 ... 5:
1135 if (vcpu->arch.cr4 & X86_CR4_DE)
1136 *exception = UD_VECTOR;
1137 return;
1138 case 6:
1139 if (value & 0xffffffff00000000ULL) {
1140 *exception = GP_VECTOR;
1141 return;
1142 }
1143 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1144 return;
1145 case 7:
1146 if (value & 0xffffffff00000000ULL) {
1147 *exception = GP_VECTOR;
1148 return;
1149 }
1150 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1151 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1152 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1153 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1154 }
1155 return;
1156 default:
1157 /* FIXME: Possible case? */
1158 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1159 __func__, dr);
1160 *exception = UD_VECTOR;
1161 return;
1162 }
1163 }
1164
1165 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1166 {
1167 u64 fault_address;
1168 u32 error_code;
1169
1170 fault_address = svm->vmcb->control.exit_info_2;
1171 error_code = svm->vmcb->control.exit_info_1;
1172
1173 trace_kvm_page_fault(fault_address, error_code);
1174 /*
1175 * FIXME: Tis shouldn't be necessary here, but there is a flush
1176 * missing in the MMU code. Until we find this bug, flush the
1177 * complete TLB here on an NPF
1178 */
1179 if (npt_enabled)
1180 svm_flush_tlb(&svm->vcpu);
1181 else {
1182 if (kvm_event_needs_reinjection(&svm->vcpu))
1183 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1184 }
1185 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1186 }
1187
1188 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1189 {
1190 if (!(svm->vcpu.guest_debug &
1191 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1192 !svm->vcpu.arch.singlestep) {
1193 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1194 return 1;
1195 }
1196
1197 if (svm->vcpu.arch.singlestep) {
1198 svm->vcpu.arch.singlestep = false;
1199 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1200 svm->vmcb->save.rflags &=
1201 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1202 update_db_intercept(&svm->vcpu);
1203 }
1204
1205 if (svm->vcpu.guest_debug &
1206 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1207 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1208 kvm_run->debug.arch.pc =
1209 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1210 kvm_run->debug.arch.exception = DB_VECTOR;
1211 return 0;
1212 }
1213
1214 return 1;
1215 }
1216
1217 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1218 {
1219 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1220 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1221 kvm_run->debug.arch.exception = BP_VECTOR;
1222 return 0;
1223 }
1224
1225 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1226 {
1227 int er;
1228
1229 er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1230 if (er != EMULATE_DONE)
1231 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1232 return 1;
1233 }
1234
1235 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1236 {
1237 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1238 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1239 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1240 svm->vcpu.fpu_active = 1;
1241
1242 return 1;
1243 }
1244
1245 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1246 {
1247 /*
1248 * On an #MC intercept the MCE handler is not called automatically in
1249 * the host. So do it by hand here.
1250 */
1251 asm volatile (
1252 "int $0x12\n");
1253 /* not sure if we ever come back to this point */
1254
1255 return 1;
1256 }
1257
1258 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1259 {
1260 /*
1261 * VMCB is undefined after a SHUTDOWN intercept
1262 * so reinitialize it.
1263 */
1264 clear_page(svm->vmcb);
1265 init_vmcb(svm);
1266
1267 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1268 return 0;
1269 }
1270
1271 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1272 {
1273 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1274 int size, in, string;
1275 unsigned port;
1276
1277 ++svm->vcpu.stat.io_exits;
1278
1279 svm->next_rip = svm->vmcb->control.exit_info_2;
1280
1281 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1282
1283 if (string) {
1284 if (emulate_instruction(&svm->vcpu,
1285 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1286 return 0;
1287 return 1;
1288 }
1289
1290 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1291 port = io_info >> 16;
1292 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1293
1294 skip_emulated_instruction(&svm->vcpu);
1295 return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1296 }
1297
1298 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1299 {
1300 return 1;
1301 }
1302
1303 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1304 {
1305 ++svm->vcpu.stat.irq_exits;
1306 return 1;
1307 }
1308
1309 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1310 {
1311 return 1;
1312 }
1313
1314 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1315 {
1316 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1317 skip_emulated_instruction(&svm->vcpu);
1318 return kvm_emulate_halt(&svm->vcpu);
1319 }
1320
1321 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1322 {
1323 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1324 skip_emulated_instruction(&svm->vcpu);
1325 kvm_emulate_hypercall(&svm->vcpu);
1326 return 1;
1327 }
1328
1329 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1330 {
1331 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1332 || !is_paging(&svm->vcpu)) {
1333 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1334 return 1;
1335 }
1336
1337 if (svm->vmcb->save.cpl) {
1338 kvm_inject_gp(&svm->vcpu, 0);
1339 return 1;
1340 }
1341
1342 return 0;
1343 }
1344
1345 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1346 bool has_error_code, u32 error_code)
1347 {
1348 if (is_nested(svm)) {
1349 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1350 svm->vmcb->control.exit_code_hi = 0;
1351 svm->vmcb->control.exit_info_1 = error_code;
1352 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1353 if (nested_svm_exit_handled(svm, false)) {
1354 nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1355
1356 nested_svm_vmexit(svm);
1357 return 1;
1358 }
1359 }
1360
1361 return 0;
1362 }
1363
1364 static inline int nested_svm_intr(struct vcpu_svm *svm)
1365 {
1366 if (is_nested(svm)) {
1367 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1368 return 0;
1369
1370 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1371 return 0;
1372
1373 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1374
1375 if (nested_svm_exit_handled(svm, false)) {
1376 nsvm_printk("VMexit -> INTR\n");
1377 nested_svm_vmexit(svm);
1378 return 1;
1379 }
1380 }
1381
1382 return 0;
1383 }
1384
1385 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1386 {
1387 struct page *page;
1388
1389 down_read(&current->mm->mmap_sem);
1390 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1391 up_read(&current->mm->mmap_sem);
1392
1393 if (is_error_page(page)) {
1394 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1395 __func__, gpa);
1396 kvm_release_page_clean(page);
1397 kvm_inject_gp(&svm->vcpu, 0);
1398 return NULL;
1399 }
1400 return page;
1401 }
1402
1403 static int nested_svm_do(struct vcpu_svm *svm,
1404 u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1405 int (*handler)(struct vcpu_svm *svm,
1406 void *arg1,
1407 void *arg2,
1408 void *opaque))
1409 {
1410 struct page *arg1_page;
1411 struct page *arg2_page = NULL;
1412 void *arg1;
1413 void *arg2 = NULL;
1414 int retval;
1415
1416 arg1_page = nested_svm_get_page(svm, arg1_gpa);
1417 if(arg1_page == NULL)
1418 return 1;
1419
1420 if (arg2_gpa) {
1421 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1422 if(arg2_page == NULL) {
1423 kvm_release_page_clean(arg1_page);
1424 return 1;
1425 }
1426 }
1427
1428 arg1 = kmap_atomic(arg1_page, KM_USER0);
1429 if (arg2_gpa)
1430 arg2 = kmap_atomic(arg2_page, KM_USER1);
1431
1432 retval = handler(svm, arg1, arg2, opaque);
1433
1434 kunmap_atomic(arg1, KM_USER0);
1435 if (arg2_gpa)
1436 kunmap_atomic(arg2, KM_USER1);
1437
1438 kvm_release_page_dirty(arg1_page);
1439 if (arg2_gpa)
1440 kvm_release_page_dirty(arg2_page);
1441
1442 return retval;
1443 }
1444
1445 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1446 void *arg1,
1447 void *arg2,
1448 void *opaque)
1449 {
1450 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1451 bool kvm_overrides = *(bool *)opaque;
1452 u32 exit_code = svm->vmcb->control.exit_code;
1453
1454 if (kvm_overrides) {
1455 switch (exit_code) {
1456 case SVM_EXIT_INTR:
1457 case SVM_EXIT_NMI:
1458 return 0;
1459 /* For now we are always handling NPFs when using them */
1460 case SVM_EXIT_NPF:
1461 if (npt_enabled)
1462 return 0;
1463 break;
1464 /* When we're shadowing, trap PFs */
1465 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1466 if (!npt_enabled)
1467 return 0;
1468 break;
1469 default:
1470 break;
1471 }
1472 }
1473
1474 switch (exit_code) {
1475 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1476 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1477 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1478 return 1;
1479 break;
1480 }
1481 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1482 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1483 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1484 return 1;
1485 break;
1486 }
1487 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1488 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1489 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1490 return 1;
1491 break;
1492 }
1493 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1494 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1495 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1496 return 1;
1497 break;
1498 }
1499 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1500 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1501 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1502 return 1;
1503 break;
1504 }
1505 default: {
1506 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1507 nsvm_printk("exit code: 0x%x\n", exit_code);
1508 if (nested_vmcb->control.intercept & exit_bits)
1509 return 1;
1510 }
1511 }
1512
1513 return 0;
1514 }
1515
1516 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1517 void *arg1, void *arg2,
1518 void *opaque)
1519 {
1520 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1521 u8 *msrpm = (u8 *)arg2;
1522 u32 t0, t1;
1523 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1524 u32 param = svm->vmcb->control.exit_info_1 & 1;
1525
1526 if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1527 return 0;
1528
1529 switch(msr) {
1530 case 0 ... 0x1fff:
1531 t0 = (msr * 2) % 8;
1532 t1 = msr / 8;
1533 break;
1534 case 0xc0000000 ... 0xc0001fff:
1535 t0 = (8192 + msr - 0xc0000000) * 2;
1536 t1 = (t0 / 8);
1537 t0 %= 8;
1538 break;
1539 case 0xc0010000 ... 0xc0011fff:
1540 t0 = (16384 + msr - 0xc0010000) * 2;
1541 t1 = (t0 / 8);
1542 t0 %= 8;
1543 break;
1544 default:
1545 return 1;
1546 break;
1547 }
1548 if (msrpm[t1] & ((1 << param) << t0))
1549 return 1;
1550
1551 return 0;
1552 }
1553
1554 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1555 {
1556 bool k = kvm_override;
1557
1558 switch (svm->vmcb->control.exit_code) {
1559 case SVM_EXIT_MSR:
1560 return nested_svm_do(svm, svm->nested_vmcb,
1561 svm->nested_vmcb_msrpm, NULL,
1562 nested_svm_exit_handled_msr);
1563 default: break;
1564 }
1565
1566 return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1567 nested_svm_exit_handled_real);
1568 }
1569
1570 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1571 {
1572 struct vmcb_control_area *dst = &dst_vmcb->control;
1573 struct vmcb_control_area *from = &from_vmcb->control;
1574
1575 dst->intercept_cr_read = from->intercept_cr_read;
1576 dst->intercept_cr_write = from->intercept_cr_write;
1577 dst->intercept_dr_read = from->intercept_dr_read;
1578 dst->intercept_dr_write = from->intercept_dr_write;
1579 dst->intercept_exceptions = from->intercept_exceptions;
1580 dst->intercept = from->intercept;
1581 dst->iopm_base_pa = from->iopm_base_pa;
1582 dst->msrpm_base_pa = from->msrpm_base_pa;
1583 dst->tsc_offset = from->tsc_offset;
1584 dst->asid = from->asid;
1585 dst->tlb_ctl = from->tlb_ctl;
1586 dst->int_ctl = from->int_ctl;
1587 dst->int_vector = from->int_vector;
1588 dst->int_state = from->int_state;
1589 dst->exit_code = from->exit_code;
1590 dst->exit_code_hi = from->exit_code_hi;
1591 dst->exit_info_1 = from->exit_info_1;
1592 dst->exit_info_2 = from->exit_info_2;
1593 dst->exit_int_info = from->exit_int_info;
1594 dst->exit_int_info_err = from->exit_int_info_err;
1595 dst->nested_ctl = from->nested_ctl;
1596 dst->event_inj = from->event_inj;
1597 dst->event_inj_err = from->event_inj_err;
1598 dst->nested_cr3 = from->nested_cr3;
1599 dst->lbr_ctl = from->lbr_ctl;
1600 }
1601
1602 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1603 void *arg2, void *opaque)
1604 {
1605 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1606 struct vmcb *hsave = svm->hsave;
1607 struct vmcb *vmcb = svm->vmcb;
1608
1609 /* Give the current vmcb to the guest */
1610 disable_gif(svm);
1611
1612 nested_vmcb->save.es = vmcb->save.es;
1613 nested_vmcb->save.cs = vmcb->save.cs;
1614 nested_vmcb->save.ss = vmcb->save.ss;
1615 nested_vmcb->save.ds = vmcb->save.ds;
1616 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1617 nested_vmcb->save.idtr = vmcb->save.idtr;
1618 if (npt_enabled)
1619 nested_vmcb->save.cr3 = vmcb->save.cr3;
1620 nested_vmcb->save.cr2 = vmcb->save.cr2;
1621 nested_vmcb->save.rflags = vmcb->save.rflags;
1622 nested_vmcb->save.rip = vmcb->save.rip;
1623 nested_vmcb->save.rsp = vmcb->save.rsp;
1624 nested_vmcb->save.rax = vmcb->save.rax;
1625 nested_vmcb->save.dr7 = vmcb->save.dr7;
1626 nested_vmcb->save.dr6 = vmcb->save.dr6;
1627 nested_vmcb->save.cpl = vmcb->save.cpl;
1628
1629 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1630 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1631 nested_vmcb->control.int_state = vmcb->control.int_state;
1632 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1633 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1634 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1635 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1636 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1637 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1638 nested_vmcb->control.tlb_ctl = 0;
1639 nested_vmcb->control.event_inj = 0;
1640 nested_vmcb->control.event_inj_err = 0;
1641
1642 /* We always set V_INTR_MASKING and remember the old value in hflags */
1643 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1644 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1645
1646 /* Restore the original control entries */
1647 copy_vmcb_control_area(vmcb, hsave);
1648
1649 /* Kill any pending exceptions */
1650 if (svm->vcpu.arch.exception.pending == true)
1651 nsvm_printk("WARNING: Pending Exception\n");
1652
1653 kvm_clear_exception_queue(&svm->vcpu);
1654 kvm_clear_interrupt_queue(&svm->vcpu);
1655
1656 /* Restore selected save entries */
1657 svm->vmcb->save.es = hsave->save.es;
1658 svm->vmcb->save.cs = hsave->save.cs;
1659 svm->vmcb->save.ss = hsave->save.ss;
1660 svm->vmcb->save.ds = hsave->save.ds;
1661 svm->vmcb->save.gdtr = hsave->save.gdtr;
1662 svm->vmcb->save.idtr = hsave->save.idtr;
1663 svm->vmcb->save.rflags = hsave->save.rflags;
1664 svm_set_efer(&svm->vcpu, hsave->save.efer);
1665 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1666 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1667 if (npt_enabled) {
1668 svm->vmcb->save.cr3 = hsave->save.cr3;
1669 svm->vcpu.arch.cr3 = hsave->save.cr3;
1670 } else {
1671 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1672 }
1673 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1674 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1675 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1676 svm->vmcb->save.dr7 = 0;
1677 svm->vmcb->save.cpl = 0;
1678 svm->vmcb->control.exit_int_info = 0;
1679
1680 /* Exit nested SVM mode */
1681 svm->nested_vmcb = 0;
1682
1683 return 0;
1684 }
1685
1686 static int nested_svm_vmexit(struct vcpu_svm *svm)
1687 {
1688 nsvm_printk("VMexit\n");
1689 if (nested_svm_do(svm, svm->nested_vmcb, 0,
1690 NULL, nested_svm_vmexit_real))
1691 return 1;
1692
1693 kvm_mmu_reset_context(&svm->vcpu);
1694 kvm_mmu_load(&svm->vcpu);
1695
1696 return 0;
1697 }
1698
1699 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1700 void *arg2, void *opaque)
1701 {
1702 int i;
1703 u32 *nested_msrpm = (u32*)arg1;
1704 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1705 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1706 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1707
1708 return 0;
1709 }
1710
1711 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1712 void *arg2, void *opaque)
1713 {
1714 struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1715 struct vmcb *hsave = svm->hsave;
1716 struct vmcb *vmcb = svm->vmcb;
1717
1718 /* nested_vmcb is our indicator if nested SVM is activated */
1719 svm->nested_vmcb = svm->vmcb->save.rax;
1720
1721 /* Clear internal status */
1722 kvm_clear_exception_queue(&svm->vcpu);
1723 kvm_clear_interrupt_queue(&svm->vcpu);
1724
1725 /* Save the old vmcb, so we don't need to pick what we save, but
1726 can restore everything when a VMEXIT occurs */
1727 hsave->save.es = vmcb->save.es;
1728 hsave->save.cs = vmcb->save.cs;
1729 hsave->save.ss = vmcb->save.ss;
1730 hsave->save.ds = vmcb->save.ds;
1731 hsave->save.gdtr = vmcb->save.gdtr;
1732 hsave->save.idtr = vmcb->save.idtr;
1733 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1734 hsave->save.cr0 = svm->vcpu.arch.cr0;
1735 hsave->save.cr4 = svm->vcpu.arch.cr4;
1736 hsave->save.rflags = vmcb->save.rflags;
1737 hsave->save.rip = svm->next_rip;
1738 hsave->save.rsp = vmcb->save.rsp;
1739 hsave->save.rax = vmcb->save.rax;
1740 if (npt_enabled)
1741 hsave->save.cr3 = vmcb->save.cr3;
1742 else
1743 hsave->save.cr3 = svm->vcpu.arch.cr3;
1744
1745 copy_vmcb_control_area(hsave, vmcb);
1746
1747 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1748 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1749 else
1750 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1751
1752 /* Load the nested guest state */
1753 svm->vmcb->save.es = nested_vmcb->save.es;
1754 svm->vmcb->save.cs = nested_vmcb->save.cs;
1755 svm->vmcb->save.ss = nested_vmcb->save.ss;
1756 svm->vmcb->save.ds = nested_vmcb->save.ds;
1757 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1758 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1759 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1760 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1761 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1762 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1763 if (npt_enabled) {
1764 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1765 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1766 } else {
1767 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1768 kvm_mmu_reset_context(&svm->vcpu);
1769 }
1770 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1771 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1772 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1773 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1774 /* In case we don't even reach vcpu_run, the fields are not updated */
1775 svm->vmcb->save.rax = nested_vmcb->save.rax;
1776 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1777 svm->vmcb->save.rip = nested_vmcb->save.rip;
1778 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1779 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1780 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1781
1782 /* We don't want a nested guest to be more powerful than the guest,
1783 so all intercepts are ORed */
1784 svm->vmcb->control.intercept_cr_read |=
1785 nested_vmcb->control.intercept_cr_read;
1786 svm->vmcb->control.intercept_cr_write |=
1787 nested_vmcb->control.intercept_cr_write;
1788 svm->vmcb->control.intercept_dr_read |=
1789 nested_vmcb->control.intercept_dr_read;
1790 svm->vmcb->control.intercept_dr_write |=
1791 nested_vmcb->control.intercept_dr_write;
1792 svm->vmcb->control.intercept_exceptions |=
1793 nested_vmcb->control.intercept_exceptions;
1794
1795 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1796
1797 svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1798
1799 force_new_asid(&svm->vcpu);
1800 svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1801 svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1802 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1803 if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1804 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1805 nested_vmcb->control.int_ctl);
1806 }
1807 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1808 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1809 else
1810 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1811
1812 nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1813 nested_vmcb->control.exit_int_info,
1814 nested_vmcb->control.int_state);
1815
1816 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1817 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1818 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1819 if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1820 nsvm_printk("Injecting Event: 0x%x\n",
1821 nested_vmcb->control.event_inj);
1822 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1823 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1824
1825 enable_gif(svm);
1826
1827 return 0;
1828 }
1829
1830 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1831 {
1832 to_vmcb->save.fs = from_vmcb->save.fs;
1833 to_vmcb->save.gs = from_vmcb->save.gs;
1834 to_vmcb->save.tr = from_vmcb->save.tr;
1835 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1836 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1837 to_vmcb->save.star = from_vmcb->save.star;
1838 to_vmcb->save.lstar = from_vmcb->save.lstar;
1839 to_vmcb->save.cstar = from_vmcb->save.cstar;
1840 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1841 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1842 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1843 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1844
1845 return 1;
1846 }
1847
1848 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1849 void *arg2, void *opaque)
1850 {
1851 return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1852 }
1853
1854 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1855 void *arg2, void *opaque)
1856 {
1857 return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1858 }
1859
1860 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1861 {
1862 if (nested_svm_check_permissions(svm))
1863 return 1;
1864
1865 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1866 skip_emulated_instruction(&svm->vcpu);
1867
1868 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1869
1870 return 1;
1871 }
1872
1873 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1874 {
1875 if (nested_svm_check_permissions(svm))
1876 return 1;
1877
1878 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1879 skip_emulated_instruction(&svm->vcpu);
1880
1881 nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1882
1883 return 1;
1884 }
1885
1886 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1887 {
1888 nsvm_printk("VMrun\n");
1889 if (nested_svm_check_permissions(svm))
1890 return 1;
1891
1892 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1893 skip_emulated_instruction(&svm->vcpu);
1894
1895 if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1896 NULL, nested_svm_vmrun))
1897 return 1;
1898
1899 if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1900 NULL, nested_svm_vmrun_msrpm))
1901 return 1;
1902
1903 return 1;
1904 }
1905
1906 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1907 {
1908 if (nested_svm_check_permissions(svm))
1909 return 1;
1910
1911 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1912 skip_emulated_instruction(&svm->vcpu);
1913
1914 enable_gif(svm);
1915
1916 return 1;
1917 }
1918
1919 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1920 {
1921 if (nested_svm_check_permissions(svm))
1922 return 1;
1923
1924 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1925 skip_emulated_instruction(&svm->vcpu);
1926
1927 disable_gif(svm);
1928
1929 /* After a CLGI no interrupts should come */
1930 svm_clear_vintr(svm);
1931 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1932
1933 return 1;
1934 }
1935
1936 static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1937 {
1938 struct kvm_vcpu *vcpu = &svm->vcpu;
1939 nsvm_printk("INVLPGA\n");
1940
1941 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1942 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1943
1944 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1945 skip_emulated_instruction(&svm->vcpu);
1946 return 1;
1947 }
1948
1949 static int invalid_op_interception(struct vcpu_svm *svm,
1950 struct kvm_run *kvm_run)
1951 {
1952 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1953 return 1;
1954 }
1955
1956 static int task_switch_interception(struct vcpu_svm *svm,
1957 struct kvm_run *kvm_run)
1958 {
1959 u16 tss_selector;
1960 int reason;
1961 int int_type = svm->vmcb->control.exit_int_info &
1962 SVM_EXITINTINFO_TYPE_MASK;
1963 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1964 uint32_t type =
1965 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1966 uint32_t idt_v =
1967 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1968
1969 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1970
1971 if (svm->vmcb->control.exit_info_2 &
1972 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1973 reason = TASK_SWITCH_IRET;
1974 else if (svm->vmcb->control.exit_info_2 &
1975 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1976 reason = TASK_SWITCH_JMP;
1977 else if (idt_v)
1978 reason = TASK_SWITCH_GATE;
1979 else
1980 reason = TASK_SWITCH_CALL;
1981
1982 if (reason == TASK_SWITCH_GATE) {
1983 switch (type) {
1984 case SVM_EXITINTINFO_TYPE_NMI:
1985 svm->vcpu.arch.nmi_injected = false;
1986 break;
1987 case SVM_EXITINTINFO_TYPE_EXEPT:
1988 kvm_clear_exception_queue(&svm->vcpu);
1989 break;
1990 case SVM_EXITINTINFO_TYPE_INTR:
1991 kvm_clear_interrupt_queue(&svm->vcpu);
1992 break;
1993 default:
1994 break;
1995 }
1996 }
1997
1998 if (reason != TASK_SWITCH_GATE ||
1999 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2000 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2001 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2002 skip_emulated_instruction(&svm->vcpu);
2003
2004 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2005 }
2006
2007 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2008 {
2009 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2010 kvm_emulate_cpuid(&svm->vcpu);
2011 return 1;
2012 }
2013
2014 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2015 {
2016 ++svm->vcpu.stat.nmi_window_exits;
2017 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2018 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2019 return 1;
2020 }
2021
2022 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2023 {
2024 if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
2025 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2026 return 1;
2027 }
2028
2029 static int emulate_on_interception(struct vcpu_svm *svm,
2030 struct kvm_run *kvm_run)
2031 {
2032 if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
2033 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2034 return 1;
2035 }
2036
2037 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2038 {
2039 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2040 /* instruction emulation calls kvm_set_cr8() */
2041 emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
2042 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2043 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2044 return 1;
2045 }
2046 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2047 return 1;
2048 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2049 return 0;
2050 }
2051
2052 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2053 {
2054 struct vcpu_svm *svm = to_svm(vcpu);
2055
2056 switch (ecx) {
2057 case MSR_IA32_TSC: {
2058 u64 tsc;
2059
2060 rdtscll(tsc);
2061 *data = svm->vmcb->control.tsc_offset + tsc;
2062 break;
2063 }
2064 case MSR_K6_STAR:
2065 *data = svm->vmcb->save.star;
2066 break;
2067 #ifdef CONFIG_X86_64
2068 case MSR_LSTAR:
2069 *data = svm->vmcb->save.lstar;
2070 break;
2071 case MSR_CSTAR:
2072 *data = svm->vmcb->save.cstar;
2073 break;
2074 case MSR_KERNEL_GS_BASE:
2075 *data = svm->vmcb->save.kernel_gs_base;
2076 break;
2077 case MSR_SYSCALL_MASK:
2078 *data = svm->vmcb->save.sfmask;
2079 break;
2080 #endif
2081 case MSR_IA32_SYSENTER_CS:
2082 *data = svm->vmcb->save.sysenter_cs;
2083 break;
2084 case MSR_IA32_SYSENTER_EIP:
2085 *data = svm->sysenter_eip;
2086 break;
2087 case MSR_IA32_SYSENTER_ESP:
2088 *data = svm->sysenter_esp;
2089 break;
2090 /* Nobody will change the following 5 values in the VMCB so
2091 we can safely return them on rdmsr. They will always be 0
2092 until LBRV is implemented. */
2093 case MSR_IA32_DEBUGCTLMSR:
2094 *data = svm->vmcb->save.dbgctl;
2095 break;
2096 case MSR_IA32_LASTBRANCHFROMIP:
2097 *data = svm->vmcb->save.br_from;
2098 break;
2099 case MSR_IA32_LASTBRANCHTOIP:
2100 *data = svm->vmcb->save.br_to;
2101 break;
2102 case MSR_IA32_LASTINTFROMIP:
2103 *data = svm->vmcb->save.last_excp_from;
2104 break;
2105 case MSR_IA32_LASTINTTOIP:
2106 *data = svm->vmcb->save.last_excp_to;
2107 break;
2108 case MSR_VM_HSAVE_PA:
2109 *data = svm->hsave_msr;
2110 break;
2111 case MSR_VM_CR:
2112 *data = 0;
2113 break;
2114 case MSR_IA32_UCODE_REV:
2115 *data = 0x01000065;
2116 break;
2117 default:
2118 return kvm_get_msr_common(vcpu, ecx, data);
2119 }
2120 return 0;
2121 }
2122
2123 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2124 {
2125 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2126 u64 data;
2127
2128 if (svm_get_msr(&svm->vcpu, ecx, &data))
2129 kvm_inject_gp(&svm->vcpu, 0);
2130 else {
2131 trace_kvm_msr_read(ecx, data);
2132
2133 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2134 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2135 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2136 skip_emulated_instruction(&svm->vcpu);
2137 }
2138 return 1;
2139 }
2140
2141 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2142 {
2143 struct vcpu_svm *svm = to_svm(vcpu);
2144
2145 switch (ecx) {
2146 case MSR_IA32_TSC: {
2147 u64 tsc;
2148
2149 rdtscll(tsc);
2150 svm->vmcb->control.tsc_offset = data - tsc;
2151 break;
2152 }
2153 case MSR_K6_STAR:
2154 svm->vmcb->save.star = data;
2155 break;
2156 #ifdef CONFIG_X86_64
2157 case MSR_LSTAR:
2158 svm->vmcb->save.lstar = data;
2159 break;
2160 case MSR_CSTAR:
2161 svm->vmcb->save.cstar = data;
2162 break;
2163 case MSR_KERNEL_GS_BASE:
2164 svm->vmcb->save.kernel_gs_base = data;
2165 break;
2166 case MSR_SYSCALL_MASK:
2167 svm->vmcb->save.sfmask = data;
2168 break;
2169 #endif
2170 case MSR_IA32_SYSENTER_CS:
2171 svm->vmcb->save.sysenter_cs = data;
2172 break;
2173 case MSR_IA32_SYSENTER_EIP:
2174 svm->sysenter_eip = data;
2175 svm->vmcb->save.sysenter_eip = data;
2176 break;
2177 case MSR_IA32_SYSENTER_ESP:
2178 svm->sysenter_esp = data;
2179 svm->vmcb->save.sysenter_esp = data;
2180 break;
2181 case MSR_IA32_DEBUGCTLMSR:
2182 if (!svm_has(SVM_FEATURE_LBRV)) {
2183 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2184 __func__, data);
2185 break;
2186 }
2187 if (data & DEBUGCTL_RESERVED_BITS)
2188 return 1;
2189
2190 svm->vmcb->save.dbgctl = data;
2191 if (data & (1ULL<<0))
2192 svm_enable_lbrv(svm);
2193 else
2194 svm_disable_lbrv(svm);
2195 break;
2196 case MSR_VM_HSAVE_PA:
2197 svm->hsave_msr = data;
2198 break;
2199 case MSR_VM_CR:
2200 case MSR_VM_IGNNE:
2201 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2202 break;
2203 default:
2204 return kvm_set_msr_common(vcpu, ecx, data);
2205 }
2206 return 0;
2207 }
2208
2209 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2210 {
2211 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2212 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2213 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2214
2215 trace_kvm_msr_write(ecx, data);
2216
2217 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2218 if (svm_set_msr(&svm->vcpu, ecx, data))
2219 kvm_inject_gp(&svm->vcpu, 0);
2220 else
2221 skip_emulated_instruction(&svm->vcpu);
2222 return 1;
2223 }
2224
2225 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2226 {
2227 if (svm->vmcb->control.exit_info_1)
2228 return wrmsr_interception(svm, kvm_run);
2229 else
2230 return rdmsr_interception(svm, kvm_run);
2231 }
2232
2233 static int interrupt_window_interception(struct vcpu_svm *svm,
2234 struct kvm_run *kvm_run)
2235 {
2236 svm_clear_vintr(svm);
2237 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2238 /*
2239 * If the user space waits to inject interrupts, exit as soon as
2240 * possible
2241 */
2242 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2243 kvm_run->request_interrupt_window &&
2244 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2245 ++svm->vcpu.stat.irq_window_exits;
2246 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2247 return 0;
2248 }
2249
2250 return 1;
2251 }
2252
2253 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2254 struct kvm_run *kvm_run) = {
2255 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2256 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2257 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2258 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2259 /* for now: */
2260 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2261 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2262 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2263 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2264 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2265 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2266 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2267 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2268 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2269 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2270 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2271 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2272 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2273 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2274 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2275 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2276 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2277 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2278 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2279 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2280 [SVM_EXIT_INTR] = intr_interception,
2281 [SVM_EXIT_NMI] = nmi_interception,
2282 [SVM_EXIT_SMI] = nop_on_interception,
2283 [SVM_EXIT_INIT] = nop_on_interception,
2284 [SVM_EXIT_VINTR] = interrupt_window_interception,
2285 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2286 [SVM_EXIT_CPUID] = cpuid_interception,
2287 [SVM_EXIT_IRET] = iret_interception,
2288 [SVM_EXIT_INVD] = emulate_on_interception,
2289 [SVM_EXIT_HLT] = halt_interception,
2290 [SVM_EXIT_INVLPG] = invlpg_interception,
2291 [SVM_EXIT_INVLPGA] = invlpga_interception,
2292 [SVM_EXIT_IOIO] = io_interception,
2293 [SVM_EXIT_MSR] = msr_interception,
2294 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2295 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2296 [SVM_EXIT_VMRUN] = vmrun_interception,
2297 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2298 [SVM_EXIT_VMLOAD] = vmload_interception,
2299 [SVM_EXIT_VMSAVE] = vmsave_interception,
2300 [SVM_EXIT_STGI] = stgi_interception,
2301 [SVM_EXIT_CLGI] = clgi_interception,
2302 [SVM_EXIT_SKINIT] = invalid_op_interception,
2303 [SVM_EXIT_WBINVD] = emulate_on_interception,
2304 [SVM_EXIT_MONITOR] = invalid_op_interception,
2305 [SVM_EXIT_MWAIT] = invalid_op_interception,
2306 [SVM_EXIT_NPF] = pf_interception,
2307 };
2308
2309 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2310 {
2311 struct vcpu_svm *svm = to_svm(vcpu);
2312 u32 exit_code = svm->vmcb->control.exit_code;
2313
2314 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2315
2316 if (is_nested(svm)) {
2317 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2318 exit_code, svm->vmcb->control.exit_info_1,
2319 svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2320 if (nested_svm_exit_handled(svm, true)) {
2321 nested_svm_vmexit(svm);
2322 nsvm_printk("-> #VMEXIT\n");
2323 return 1;
2324 }
2325 }
2326
2327 if (npt_enabled) {
2328 int mmu_reload = 0;
2329 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2330 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2331 mmu_reload = 1;
2332 }
2333 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2334 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2335 if (mmu_reload) {
2336 kvm_mmu_reset_context(vcpu);
2337 kvm_mmu_load(vcpu);
2338 }
2339 }
2340
2341
2342 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2343 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2344 kvm_run->fail_entry.hardware_entry_failure_reason
2345 = svm->vmcb->control.exit_code;
2346 return 0;
2347 }
2348
2349 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2350 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2351 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2352 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2353 "exit_code 0x%x\n",
2354 __func__, svm->vmcb->control.exit_int_info,
2355 exit_code);
2356
2357 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2358 || !svm_exit_handlers[exit_code]) {
2359 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2360 kvm_run->hw.hardware_exit_reason = exit_code;
2361 return 0;
2362 }
2363
2364 return svm_exit_handlers[exit_code](svm, kvm_run);
2365 }
2366
2367 static void reload_tss(struct kvm_vcpu *vcpu)
2368 {
2369 int cpu = raw_smp_processor_id();
2370
2371 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2372 svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2373 load_TR_desc();
2374 }
2375
2376 static void pre_svm_run(struct vcpu_svm *svm)
2377 {
2378 int cpu = raw_smp_processor_id();
2379
2380 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2381
2382 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2383 /* FIXME: handle wraparound of asid_generation */
2384 if (svm->asid_generation != svm_data->asid_generation)
2385 new_asid(svm, svm_data);
2386 }
2387
2388 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2389 {
2390 struct vcpu_svm *svm = to_svm(vcpu);
2391
2392 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2393 vcpu->arch.hflags |= HF_NMI_MASK;
2394 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2395 ++vcpu->stat.nmi_injections;
2396 }
2397
2398 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2399 {
2400 struct vmcb_control_area *control;
2401
2402 trace_kvm_inj_virq(irq);
2403
2404 ++svm->vcpu.stat.irq_injections;
2405 control = &svm->vmcb->control;
2406 control->int_vector = irq;
2407 control->int_ctl &= ~V_INTR_PRIO_MASK;
2408 control->int_ctl |= V_IRQ_MASK |
2409 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2410 }
2411
2412 static void svm_set_irq(struct kvm_vcpu *vcpu)
2413 {
2414 struct vcpu_svm *svm = to_svm(vcpu);
2415
2416 BUG_ON(!(gif_set(svm)));
2417
2418 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2419 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2420 }
2421
2422 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2423 {
2424 struct vcpu_svm *svm = to_svm(vcpu);
2425
2426 if (irr == -1)
2427 return;
2428
2429 if (tpr >= irr)
2430 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2431 }
2432
2433 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2434 {
2435 struct vcpu_svm *svm = to_svm(vcpu);
2436 struct vmcb *vmcb = svm->vmcb;
2437 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2438 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2439 }
2440
2441 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2442 {
2443 struct vcpu_svm *svm = to_svm(vcpu);
2444 struct vmcb *vmcb = svm->vmcb;
2445 return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2446 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2447 gif_set(svm) &&
2448 !is_nested(svm);
2449 }
2450
2451 static void enable_irq_window(struct kvm_vcpu *vcpu)
2452 {
2453 struct vcpu_svm *svm = to_svm(vcpu);
2454 nsvm_printk("Trying to open IRQ window\n");
2455
2456 nested_svm_intr(svm);
2457
2458 /* In case GIF=0 we can't rely on the CPU to tell us when
2459 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2460 * The next time we get that intercept, this function will be
2461 * called again though and we'll get the vintr intercept. */
2462 if (gif_set(svm)) {
2463 svm_set_vintr(svm);
2464 svm_inject_irq(svm, 0x0);
2465 }
2466 }
2467
2468 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2469 {
2470 struct vcpu_svm *svm = to_svm(vcpu);
2471
2472 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2473 == HF_NMI_MASK)
2474 return; /* IRET will cause a vm exit */
2475
2476 /* Something prevents NMI from been injected. Single step over
2477 possible problem (IRET or exception injection or interrupt
2478 shadow) */
2479 vcpu->arch.singlestep = true;
2480 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2481 update_db_intercept(vcpu);
2482 }
2483
2484 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2485 {
2486 return 0;
2487 }
2488
2489 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2490 {
2491 force_new_asid(vcpu);
2492 }
2493
2494 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2495 {
2496 }
2497
2498 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2499 {
2500 struct vcpu_svm *svm = to_svm(vcpu);
2501
2502 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2503 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2504 kvm_set_cr8(vcpu, cr8);
2505 }
2506 }
2507
2508 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2509 {
2510 struct vcpu_svm *svm = to_svm(vcpu);
2511 u64 cr8;
2512
2513 cr8 = kvm_get_cr8(vcpu);
2514 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2515 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2516 }
2517
2518 static void svm_complete_interrupts(struct vcpu_svm *svm)
2519 {
2520 u8 vector;
2521 int type;
2522 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2523
2524 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2525 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2526
2527 svm->vcpu.arch.nmi_injected = false;
2528 kvm_clear_exception_queue(&svm->vcpu);
2529 kvm_clear_interrupt_queue(&svm->vcpu);
2530
2531 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2532 return;
2533
2534 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2535 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2536
2537 switch (type) {
2538 case SVM_EXITINTINFO_TYPE_NMI:
2539 svm->vcpu.arch.nmi_injected = true;
2540 break;
2541 case SVM_EXITINTINFO_TYPE_EXEPT:
2542 /* In case of software exception do not reinject an exception
2543 vector, but re-execute and instruction instead */
2544 if (is_nested(svm))
2545 break;
2546 if (kvm_exception_is_soft(vector))
2547 break;
2548 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2549 u32 err = svm->vmcb->control.exit_int_info_err;
2550 kvm_queue_exception_e(&svm->vcpu, vector, err);
2551
2552 } else
2553 kvm_queue_exception(&svm->vcpu, vector);
2554 break;
2555 case SVM_EXITINTINFO_TYPE_INTR:
2556 kvm_queue_interrupt(&svm->vcpu, vector, false);
2557 break;
2558 default:
2559 break;
2560 }
2561 }
2562
2563 #ifdef CONFIG_X86_64
2564 #define R "r"
2565 #else
2566 #define R "e"
2567 #endif
2568
2569 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2570 {
2571 struct vcpu_svm *svm = to_svm(vcpu);
2572 u16 fs_selector;
2573 u16 gs_selector;
2574 u16 ldt_selector;
2575
2576 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2577 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2578 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2579
2580 pre_svm_run(svm);
2581
2582 sync_lapic_to_cr8(vcpu);
2583
2584 save_host_msrs(vcpu);
2585 fs_selector = kvm_read_fs();
2586 gs_selector = kvm_read_gs();
2587 ldt_selector = kvm_read_ldt();
2588 if (!is_nested(svm))
2589 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2590 /* required for live migration with NPT */
2591 if (npt_enabled)
2592 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2593
2594 clgi();
2595
2596 local_irq_enable();
2597
2598 asm volatile (
2599 "push %%"R"bp; \n\t"
2600 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2601 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2602 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2603 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2604 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2605 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2606 #ifdef CONFIG_X86_64
2607 "mov %c[r8](%[svm]), %%r8 \n\t"
2608 "mov %c[r9](%[svm]), %%r9 \n\t"
2609 "mov %c[r10](%[svm]), %%r10 \n\t"
2610 "mov %c[r11](%[svm]), %%r11 \n\t"
2611 "mov %c[r12](%[svm]), %%r12 \n\t"
2612 "mov %c[r13](%[svm]), %%r13 \n\t"
2613 "mov %c[r14](%[svm]), %%r14 \n\t"
2614 "mov %c[r15](%[svm]), %%r15 \n\t"
2615 #endif
2616
2617 /* Enter guest mode */
2618 "push %%"R"ax \n\t"
2619 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2620 __ex(SVM_VMLOAD) "\n\t"
2621 __ex(SVM_VMRUN) "\n\t"
2622 __ex(SVM_VMSAVE) "\n\t"
2623 "pop %%"R"ax \n\t"
2624
2625 /* Save guest registers, load host registers */
2626 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2627 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2628 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2629 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2630 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2631 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2632 #ifdef CONFIG_X86_64
2633 "mov %%r8, %c[r8](%[svm]) \n\t"
2634 "mov %%r9, %c[r9](%[svm]) \n\t"
2635 "mov %%r10, %c[r10](%[svm]) \n\t"
2636 "mov %%r11, %c[r11](%[svm]) \n\t"
2637 "mov %%r12, %c[r12](%[svm]) \n\t"
2638 "mov %%r13, %c[r13](%[svm]) \n\t"
2639 "mov %%r14, %c[r14](%[svm]) \n\t"
2640 "mov %%r15, %c[r15](%[svm]) \n\t"
2641 #endif
2642 "pop %%"R"bp"
2643 :
2644 : [svm]"a"(svm),
2645 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2646 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2647 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2648 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2649 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2650 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2651 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2652 #ifdef CONFIG_X86_64
2653 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2654 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2655 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2656 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2657 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2658 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2659 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2660 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2661 #endif
2662 : "cc", "memory"
2663 , R"bx", R"cx", R"dx", R"si", R"di"
2664 #ifdef CONFIG_X86_64
2665 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2666 #endif
2667 );
2668
2669 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2670 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2671 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2672 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2673
2674 kvm_load_fs(fs_selector);
2675 kvm_load_gs(gs_selector);
2676 kvm_load_ldt(ldt_selector);
2677 load_host_msrs(vcpu);
2678
2679 reload_tss(vcpu);
2680
2681 local_irq_disable();
2682
2683 stgi();
2684
2685 sync_cr8_to_lapic(vcpu);
2686
2687 svm->next_rip = 0;
2688
2689 if (npt_enabled) {
2690 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2691 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2692 }
2693
2694 svm_complete_interrupts(svm);
2695 }
2696
2697 #undef R
2698
2699 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2700 {
2701 struct vcpu_svm *svm = to_svm(vcpu);
2702
2703 if (npt_enabled) {
2704 svm->vmcb->control.nested_cr3 = root;
2705 force_new_asid(vcpu);
2706 return;
2707 }
2708
2709 svm->vmcb->save.cr3 = root;
2710 force_new_asid(vcpu);
2711
2712 if (vcpu->fpu_active) {
2713 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2714 svm->vmcb->save.cr0 |= X86_CR0_TS;
2715 vcpu->fpu_active = 0;
2716 }
2717 }
2718
2719 static int is_disabled(void)
2720 {
2721 u64 vm_cr;
2722
2723 rdmsrl(MSR_VM_CR, vm_cr);
2724 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2725 return 1;
2726
2727 return 0;
2728 }
2729
2730 static void
2731 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2732 {
2733 /*
2734 * Patch in the VMMCALL instruction:
2735 */
2736 hypercall[0] = 0x0f;
2737 hypercall[1] = 0x01;
2738 hypercall[2] = 0xd9;
2739 }
2740
2741 static void svm_check_processor_compat(void *rtn)
2742 {
2743 *(int *)rtn = 0;
2744 }
2745
2746 static bool svm_cpu_has_accelerated_tpr(void)
2747 {
2748 return false;
2749 }
2750
2751 static int get_npt_level(void)
2752 {
2753 #ifdef CONFIG_X86_64
2754 return PT64_ROOT_LEVEL;
2755 #else
2756 return PT32E_ROOT_LEVEL;
2757 #endif
2758 }
2759
2760 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2761 {
2762 return 0;
2763 }
2764
2765 static const struct trace_print_flags svm_exit_reasons_str[] = {
2766 { SVM_EXIT_READ_CR0, "read_cr0" },
2767 { SVM_EXIT_READ_CR3, "read_cr3" },
2768 { SVM_EXIT_READ_CR4, "read_cr4" },
2769 { SVM_EXIT_READ_CR8, "read_cr8" },
2770 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2771 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2772 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2773 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2774 { SVM_EXIT_READ_DR0, "read_dr0" },
2775 { SVM_EXIT_READ_DR1, "read_dr1" },
2776 { SVM_EXIT_READ_DR2, "read_dr2" },
2777 { SVM_EXIT_READ_DR3, "read_dr3" },
2778 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2779 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2780 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2781 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2782 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2783 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2784 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2785 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2786 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2787 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2788 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2789 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2790 { SVM_EXIT_INTR, "interrupt" },
2791 { SVM_EXIT_NMI, "nmi" },
2792 { SVM_EXIT_SMI, "smi" },
2793 { SVM_EXIT_INIT, "init" },
2794 { SVM_EXIT_VINTR, "vintr" },
2795 { SVM_EXIT_CPUID, "cpuid" },
2796 { SVM_EXIT_INVD, "invd" },
2797 { SVM_EXIT_HLT, "hlt" },
2798 { SVM_EXIT_INVLPG, "invlpg" },
2799 { SVM_EXIT_INVLPGA, "invlpga" },
2800 { SVM_EXIT_IOIO, "io" },
2801 { SVM_EXIT_MSR, "msr" },
2802 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2803 { SVM_EXIT_SHUTDOWN, "shutdown" },
2804 { SVM_EXIT_VMRUN, "vmrun" },
2805 { SVM_EXIT_VMMCALL, "hypercall" },
2806 { SVM_EXIT_VMLOAD, "vmload" },
2807 { SVM_EXIT_VMSAVE, "vmsave" },
2808 { SVM_EXIT_STGI, "stgi" },
2809 { SVM_EXIT_CLGI, "clgi" },
2810 { SVM_EXIT_SKINIT, "skinit" },
2811 { SVM_EXIT_WBINVD, "wbinvd" },
2812 { SVM_EXIT_MONITOR, "monitor" },
2813 { SVM_EXIT_MWAIT, "mwait" },
2814 { SVM_EXIT_NPF, "npf" },
2815 { -1, NULL }
2816 };
2817
2818 static bool svm_gb_page_enable(void)
2819 {
2820 return true;
2821 }
2822
2823 static struct kvm_x86_ops svm_x86_ops = {
2824 .cpu_has_kvm_support = has_svm,
2825 .disabled_by_bios = is_disabled,
2826 .hardware_setup = svm_hardware_setup,
2827 .hardware_unsetup = svm_hardware_unsetup,
2828 .check_processor_compatibility = svm_check_processor_compat,
2829 .hardware_enable = svm_hardware_enable,
2830 .hardware_disable = svm_hardware_disable,
2831 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2832
2833 .vcpu_create = svm_create_vcpu,
2834 .vcpu_free = svm_free_vcpu,
2835 .vcpu_reset = svm_vcpu_reset,
2836
2837 .prepare_guest_switch = svm_prepare_guest_switch,
2838 .vcpu_load = svm_vcpu_load,
2839 .vcpu_put = svm_vcpu_put,
2840
2841 .set_guest_debug = svm_guest_debug,
2842 .get_msr = svm_get_msr,
2843 .set_msr = svm_set_msr,
2844 .get_segment_base = svm_get_segment_base,
2845 .get_segment = svm_get_segment,
2846 .set_segment = svm_set_segment,
2847 .get_cpl = svm_get_cpl,
2848 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2849 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2850 .set_cr0 = svm_set_cr0,
2851 .set_cr3 = svm_set_cr3,
2852 .set_cr4 = svm_set_cr4,
2853 .set_efer = svm_set_efer,
2854 .get_idt = svm_get_idt,
2855 .set_idt = svm_set_idt,
2856 .get_gdt = svm_get_gdt,
2857 .set_gdt = svm_set_gdt,
2858 .get_dr = svm_get_dr,
2859 .set_dr = svm_set_dr,
2860 .cache_reg = svm_cache_reg,
2861 .get_rflags = svm_get_rflags,
2862 .set_rflags = svm_set_rflags,
2863
2864 .tlb_flush = svm_flush_tlb,
2865
2866 .run = svm_vcpu_run,
2867 .handle_exit = handle_exit,
2868 .skip_emulated_instruction = skip_emulated_instruction,
2869 .set_interrupt_shadow = svm_set_interrupt_shadow,
2870 .get_interrupt_shadow = svm_get_interrupt_shadow,
2871 .patch_hypercall = svm_patch_hypercall,
2872 .set_irq = svm_set_irq,
2873 .set_nmi = svm_inject_nmi,
2874 .queue_exception = svm_queue_exception,
2875 .interrupt_allowed = svm_interrupt_allowed,
2876 .nmi_allowed = svm_nmi_allowed,
2877 .enable_nmi_window = enable_nmi_window,
2878 .enable_irq_window = enable_irq_window,
2879 .update_cr8_intercept = update_cr8_intercept,
2880
2881 .set_tss_addr = svm_set_tss_addr,
2882 .get_tdp_level = get_npt_level,
2883 .get_mt_mask = svm_get_mt_mask,
2884
2885 .exit_reasons_str = svm_exit_reasons_str,
2886 .gb_page_enable = svm_gb_page_enable,
2887 };
2888
2889 static int __init svm_init(void)
2890 {
2891 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2892 THIS_MODULE);
2893 }
2894
2895 static void __exit svm_exit(void)
2896 {
2897 kvm_exit();
2898 }
2899
2900 module_init(svm_init)
2901 module_exit(svm_exit)
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