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Merge tag 'mmc-updates-for-3.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23 #include "cpuid.h"
24
25 #include <linux/module.h>
26 #include <linux/mod_devicetable.h>
27 #include <linux/kernel.h>
28 #include <linux/vmalloc.h>
29 #include <linux/highmem.h>
30 #include <linux/sched.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33
34 #include <asm/perf_event.h>
35 #include <asm/tlbflush.h>
36 #include <asm/desc.h>
37 #include <asm/debugreg.h>
38 #include <asm/kvm_para.h>
39
40 #include <asm/virtext.h>
41 #include "trace.h"
42
43 #define __ex(x) __kvm_handle_fault_on_reboot(x)
44
45 MODULE_AUTHOR("Qumranet");
46 MODULE_LICENSE("GPL");
47
48 static const struct x86_cpu_id svm_cpu_id[] = {
49 X86_FEATURE_MATCH(X86_FEATURE_SVM),
50 {}
51 };
52 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
53
54 #define IOPM_ALLOC_ORDER 2
55 #define MSRPM_ALLOC_ORDER 1
56
57 #define SEG_TYPE_LDT 2
58 #define SEG_TYPE_BUSY_TSS16 3
59
60 #define SVM_FEATURE_NPT (1 << 0)
61 #define SVM_FEATURE_LBRV (1 << 1)
62 #define SVM_FEATURE_SVML (1 << 2)
63 #define SVM_FEATURE_NRIP (1 << 3)
64 #define SVM_FEATURE_TSC_RATE (1 << 4)
65 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
66 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
67 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
68 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
69
70 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
71 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
72 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
73
74 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75
76 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
77 #define TSC_RATIO_MIN 0x0000000000000001ULL
78 #define TSC_RATIO_MAX 0x000000ffffffffffULL
79
80 static bool erratum_383_found __read_mostly;
81
82 static const u32 host_save_user_msrs[] = {
83 #ifdef CONFIG_X86_64
84 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
85 MSR_FS_BASE,
86 #endif
87 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
88 };
89
90 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
91
92 struct kvm_vcpu;
93
94 struct nested_state {
95 struct vmcb *hsave;
96 u64 hsave_msr;
97 u64 vm_cr_msr;
98 u64 vmcb;
99
100 /* These are the merged vectors */
101 u32 *msrpm;
102
103 /* gpa pointers to the real vectors */
104 u64 vmcb_msrpm;
105 u64 vmcb_iopm;
106
107 /* A VMEXIT is required but not yet emulated */
108 bool exit_required;
109
110 /* cache for intercepts of the guest */
111 u32 intercept_cr;
112 u32 intercept_dr;
113 u32 intercept_exceptions;
114 u64 intercept;
115
116 /* Nested Paging related state */
117 u64 nested_cr3;
118 };
119
120 #define MSRPM_OFFSETS 16
121 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
122
123 /*
124 * Set osvw_len to higher value when updated Revision Guides
125 * are published and we know what the new status bits are
126 */
127 static uint64_t osvw_len = 4, osvw_status;
128
129 struct vcpu_svm {
130 struct kvm_vcpu vcpu;
131 struct vmcb *vmcb;
132 unsigned long vmcb_pa;
133 struct svm_cpu_data *svm_data;
134 uint64_t asid_generation;
135 uint64_t sysenter_esp;
136 uint64_t sysenter_eip;
137
138 u64 next_rip;
139
140 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
141 struct {
142 u16 fs;
143 u16 gs;
144 u16 ldt;
145 u64 gs_base;
146 } host;
147
148 u32 *msrpm;
149
150 ulong nmi_iret_rip;
151
152 struct nested_state nested;
153
154 bool nmi_singlestep;
155
156 unsigned int3_injected;
157 unsigned long int3_rip;
158 u32 apf_reason;
159
160 u64 tsc_ratio;
161 };
162
163 static DEFINE_PER_CPU(u64, current_tsc_ratio);
164 #define TSC_RATIO_DEFAULT 0x0100000000ULL
165
166 #define MSR_INVALID 0xffffffffU
167
168 static const struct svm_direct_access_msrs {
169 u32 index; /* Index of the MSR */
170 bool always; /* True if intercept is always on */
171 } direct_access_msrs[] = {
172 { .index = MSR_STAR, .always = true },
173 { .index = MSR_IA32_SYSENTER_CS, .always = true },
174 #ifdef CONFIG_X86_64
175 { .index = MSR_GS_BASE, .always = true },
176 { .index = MSR_FS_BASE, .always = true },
177 { .index = MSR_KERNEL_GS_BASE, .always = true },
178 { .index = MSR_LSTAR, .always = true },
179 { .index = MSR_CSTAR, .always = true },
180 { .index = MSR_SYSCALL_MASK, .always = true },
181 #endif
182 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
183 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
184 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
185 { .index = MSR_IA32_LASTINTTOIP, .always = false },
186 { .index = MSR_INVALID, .always = false },
187 };
188
189 /* enable NPT for AMD64 and X86 with PAE */
190 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
191 static bool npt_enabled = true;
192 #else
193 static bool npt_enabled;
194 #endif
195
196 /* allow nested paging (virtualized MMU) for all guests */
197 static int npt = true;
198 module_param(npt, int, S_IRUGO);
199
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
203
204 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
205 static void svm_complete_interrupts(struct vcpu_svm *svm);
206
207 static int nested_svm_exit_handled(struct vcpu_svm *svm);
208 static int nested_svm_intercept(struct vcpu_svm *svm);
209 static int nested_svm_vmexit(struct vcpu_svm *svm);
210 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
211 bool has_error_code, u32 error_code);
212 static u64 __scale_tsc(u64 ratio, u64 tsc);
213
214 enum {
215 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
216 pause filter count */
217 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
218 VMCB_ASID, /* ASID */
219 VMCB_INTR, /* int_ctl, int_vector */
220 VMCB_NPT, /* npt_en, nCR3, gPAT */
221 VMCB_CR, /* CR0, CR3, CR4, EFER */
222 VMCB_DR, /* DR6, DR7 */
223 VMCB_DT, /* GDT, IDT */
224 VMCB_SEG, /* CS, DS, SS, ES, CPL */
225 VMCB_CR2, /* CR2 only */
226 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
227 VMCB_DIRTY_MAX,
228 };
229
230 /* TPR and CR2 are always written before VMRUN */
231 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
232
233 static inline void mark_all_dirty(struct vmcb *vmcb)
234 {
235 vmcb->control.clean = 0;
236 }
237
238 static inline void mark_all_clean(struct vmcb *vmcb)
239 {
240 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
241 & ~VMCB_ALWAYS_DIRTY_MASK;
242 }
243
244 static inline void mark_dirty(struct vmcb *vmcb, int bit)
245 {
246 vmcb->control.clean &= ~(1 << bit);
247 }
248
249 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
250 {
251 return container_of(vcpu, struct vcpu_svm, vcpu);
252 }
253
254 static void recalc_intercepts(struct vcpu_svm *svm)
255 {
256 struct vmcb_control_area *c, *h;
257 struct nested_state *g;
258
259 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
260
261 if (!is_guest_mode(&svm->vcpu))
262 return;
263
264 c = &svm->vmcb->control;
265 h = &svm->nested.hsave->control;
266 g = &svm->nested;
267
268 c->intercept_cr = h->intercept_cr | g->intercept_cr;
269 c->intercept_dr = h->intercept_dr | g->intercept_dr;
270 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
271 c->intercept = h->intercept | g->intercept;
272 }
273
274 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
275 {
276 if (is_guest_mode(&svm->vcpu))
277 return svm->nested.hsave;
278 else
279 return svm->vmcb;
280 }
281
282 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
283 {
284 struct vmcb *vmcb = get_host_vmcb(svm);
285
286 vmcb->control.intercept_cr |= (1U << bit);
287
288 recalc_intercepts(svm);
289 }
290
291 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
292 {
293 struct vmcb *vmcb = get_host_vmcb(svm);
294
295 vmcb->control.intercept_cr &= ~(1U << bit);
296
297 recalc_intercepts(svm);
298 }
299
300 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
301 {
302 struct vmcb *vmcb = get_host_vmcb(svm);
303
304 return vmcb->control.intercept_cr & (1U << bit);
305 }
306
307 static inline void set_dr_intercepts(struct vcpu_svm *svm)
308 {
309 struct vmcb *vmcb = get_host_vmcb(svm);
310
311 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
312 | (1 << INTERCEPT_DR1_READ)
313 | (1 << INTERCEPT_DR2_READ)
314 | (1 << INTERCEPT_DR3_READ)
315 | (1 << INTERCEPT_DR4_READ)
316 | (1 << INTERCEPT_DR5_READ)
317 | (1 << INTERCEPT_DR6_READ)
318 | (1 << INTERCEPT_DR7_READ)
319 | (1 << INTERCEPT_DR0_WRITE)
320 | (1 << INTERCEPT_DR1_WRITE)
321 | (1 << INTERCEPT_DR2_WRITE)
322 | (1 << INTERCEPT_DR3_WRITE)
323 | (1 << INTERCEPT_DR4_WRITE)
324 | (1 << INTERCEPT_DR5_WRITE)
325 | (1 << INTERCEPT_DR6_WRITE)
326 | (1 << INTERCEPT_DR7_WRITE);
327
328 recalc_intercepts(svm);
329 }
330
331 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
332 {
333 struct vmcb *vmcb = get_host_vmcb(svm);
334
335 vmcb->control.intercept_dr = 0;
336
337 recalc_intercepts(svm);
338 }
339
340 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
341 {
342 struct vmcb *vmcb = get_host_vmcb(svm);
343
344 vmcb->control.intercept_exceptions |= (1U << bit);
345
346 recalc_intercepts(svm);
347 }
348
349 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
350 {
351 struct vmcb *vmcb = get_host_vmcb(svm);
352
353 vmcb->control.intercept_exceptions &= ~(1U << bit);
354
355 recalc_intercepts(svm);
356 }
357
358 static inline void set_intercept(struct vcpu_svm *svm, int bit)
359 {
360 struct vmcb *vmcb = get_host_vmcb(svm);
361
362 vmcb->control.intercept |= (1ULL << bit);
363
364 recalc_intercepts(svm);
365 }
366
367 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
368 {
369 struct vmcb *vmcb = get_host_vmcb(svm);
370
371 vmcb->control.intercept &= ~(1ULL << bit);
372
373 recalc_intercepts(svm);
374 }
375
376 static inline void enable_gif(struct vcpu_svm *svm)
377 {
378 svm->vcpu.arch.hflags |= HF_GIF_MASK;
379 }
380
381 static inline void disable_gif(struct vcpu_svm *svm)
382 {
383 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
384 }
385
386 static inline bool gif_set(struct vcpu_svm *svm)
387 {
388 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
389 }
390
391 static unsigned long iopm_base;
392
393 struct kvm_ldttss_desc {
394 u16 limit0;
395 u16 base0;
396 unsigned base1:8, type:5, dpl:2, p:1;
397 unsigned limit1:4, zero0:3, g:1, base2:8;
398 u32 base3;
399 u32 zero1;
400 } __attribute__((packed));
401
402 struct svm_cpu_data {
403 int cpu;
404
405 u64 asid_generation;
406 u32 max_asid;
407 u32 next_asid;
408 struct kvm_ldttss_desc *tss_desc;
409
410 struct page *save_area;
411 };
412
413 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
414
415 struct svm_init_data {
416 int cpu;
417 int r;
418 };
419
420 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
421
422 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
423 #define MSRS_RANGE_SIZE 2048
424 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
425
426 static u32 svm_msrpm_offset(u32 msr)
427 {
428 u32 offset;
429 int i;
430
431 for (i = 0; i < NUM_MSR_MAPS; i++) {
432 if (msr < msrpm_ranges[i] ||
433 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
434 continue;
435
436 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
437 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
438
439 /* Now we have the u8 offset - but need the u32 offset */
440 return offset / 4;
441 }
442
443 /* MSR not in any range */
444 return MSR_INVALID;
445 }
446
447 #define MAX_INST_SIZE 15
448
449 static inline void clgi(void)
450 {
451 asm volatile (__ex(SVM_CLGI));
452 }
453
454 static inline void stgi(void)
455 {
456 asm volatile (__ex(SVM_STGI));
457 }
458
459 static inline void invlpga(unsigned long addr, u32 asid)
460 {
461 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
462 }
463
464 static int get_npt_level(void)
465 {
466 #ifdef CONFIG_X86_64
467 return PT64_ROOT_LEVEL;
468 #else
469 return PT32E_ROOT_LEVEL;
470 #endif
471 }
472
473 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
474 {
475 vcpu->arch.efer = efer;
476 if (!npt_enabled && !(efer & EFER_LMA))
477 efer &= ~EFER_LME;
478
479 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
480 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
481 }
482
483 static int is_external_interrupt(u32 info)
484 {
485 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
486 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
487 }
488
489 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
490 {
491 struct vcpu_svm *svm = to_svm(vcpu);
492 u32 ret = 0;
493
494 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
495 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
496 return ret & mask;
497 }
498
499 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
500 {
501 struct vcpu_svm *svm = to_svm(vcpu);
502
503 if (mask == 0)
504 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
505 else
506 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
507
508 }
509
510 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
511 {
512 struct vcpu_svm *svm = to_svm(vcpu);
513
514 if (svm->vmcb->control.next_rip != 0)
515 svm->next_rip = svm->vmcb->control.next_rip;
516
517 if (!svm->next_rip) {
518 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
519 EMULATE_DONE)
520 printk(KERN_DEBUG "%s: NOP\n", __func__);
521 return;
522 }
523 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
524 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
525 __func__, kvm_rip_read(vcpu), svm->next_rip);
526
527 kvm_rip_write(vcpu, svm->next_rip);
528 svm_set_interrupt_shadow(vcpu, 0);
529 }
530
531 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
532 bool has_error_code, u32 error_code,
533 bool reinject)
534 {
535 struct vcpu_svm *svm = to_svm(vcpu);
536
537 /*
538 * If we are within a nested VM we'd better #VMEXIT and let the guest
539 * handle the exception
540 */
541 if (!reinject &&
542 nested_svm_check_exception(svm, nr, has_error_code, error_code))
543 return;
544
545 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
546 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
547
548 /*
549 * For guest debugging where we have to reinject #BP if some
550 * INT3 is guest-owned:
551 * Emulate nRIP by moving RIP forward. Will fail if injection
552 * raises a fault that is not intercepted. Still better than
553 * failing in all cases.
554 */
555 skip_emulated_instruction(&svm->vcpu);
556 rip = kvm_rip_read(&svm->vcpu);
557 svm->int3_rip = rip + svm->vmcb->save.cs.base;
558 svm->int3_injected = rip - old_rip;
559 }
560
561 svm->vmcb->control.event_inj = nr
562 | SVM_EVTINJ_VALID
563 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
564 | SVM_EVTINJ_TYPE_EXEPT;
565 svm->vmcb->control.event_inj_err = error_code;
566 }
567
568 static void svm_init_erratum_383(void)
569 {
570 u32 low, high;
571 int err;
572 u64 val;
573
574 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
575 return;
576
577 /* Use _safe variants to not break nested virtualization */
578 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
579 if (err)
580 return;
581
582 val |= (1ULL << 47);
583
584 low = lower_32_bits(val);
585 high = upper_32_bits(val);
586
587 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
588
589 erratum_383_found = true;
590 }
591
592 static void svm_init_osvw(struct kvm_vcpu *vcpu)
593 {
594 /*
595 * Guests should see errata 400 and 415 as fixed (assuming that
596 * HLT and IO instructions are intercepted).
597 */
598 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
599 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
600
601 /*
602 * By increasing VCPU's osvw.length to 3 we are telling the guest that
603 * all osvw.status bits inside that length, including bit 0 (which is
604 * reserved for erratum 298), are valid. However, if host processor's
605 * osvw_len is 0 then osvw_status[0] carries no information. We need to
606 * be conservative here and therefore we tell the guest that erratum 298
607 * is present (because we really don't know).
608 */
609 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
610 vcpu->arch.osvw.status |= 1;
611 }
612
613 static int has_svm(void)
614 {
615 const char *msg;
616
617 if (!cpu_has_svm(&msg)) {
618 printk(KERN_INFO "has_svm: %s\n", msg);
619 return 0;
620 }
621
622 return 1;
623 }
624
625 static void svm_hardware_disable(void *garbage)
626 {
627 /* Make sure we clean up behind us */
628 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
629 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
630
631 cpu_svm_disable();
632
633 amd_pmu_disable_virt();
634 }
635
636 static int svm_hardware_enable(void *garbage)
637 {
638
639 struct svm_cpu_data *sd;
640 uint64_t efer;
641 struct desc_ptr gdt_descr;
642 struct desc_struct *gdt;
643 int me = raw_smp_processor_id();
644
645 rdmsrl(MSR_EFER, efer);
646 if (efer & EFER_SVME)
647 return -EBUSY;
648
649 if (!has_svm()) {
650 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
651 return -EINVAL;
652 }
653 sd = per_cpu(svm_data, me);
654 if (!sd) {
655 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
656 return -EINVAL;
657 }
658
659 sd->asid_generation = 1;
660 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
661 sd->next_asid = sd->max_asid + 1;
662
663 native_store_gdt(&gdt_descr);
664 gdt = (struct desc_struct *)gdt_descr.address;
665 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
666
667 wrmsrl(MSR_EFER, efer | EFER_SVME);
668
669 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
670
671 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
672 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
673 __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
674 }
675
676
677 /*
678 * Get OSVW bits.
679 *
680 * Note that it is possible to have a system with mixed processor
681 * revisions and therefore different OSVW bits. If bits are not the same
682 * on different processors then choose the worst case (i.e. if erratum
683 * is present on one processor and not on another then assume that the
684 * erratum is present everywhere).
685 */
686 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
687 uint64_t len, status = 0;
688 int err;
689
690 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
691 if (!err)
692 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
693 &err);
694
695 if (err)
696 osvw_status = osvw_len = 0;
697 else {
698 if (len < osvw_len)
699 osvw_len = len;
700 osvw_status |= status;
701 osvw_status &= (1ULL << osvw_len) - 1;
702 }
703 } else
704 osvw_status = osvw_len = 0;
705
706 svm_init_erratum_383();
707
708 amd_pmu_enable_virt();
709
710 return 0;
711 }
712
713 static void svm_cpu_uninit(int cpu)
714 {
715 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
716
717 if (!sd)
718 return;
719
720 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
721 __free_page(sd->save_area);
722 kfree(sd);
723 }
724
725 static int svm_cpu_init(int cpu)
726 {
727 struct svm_cpu_data *sd;
728 int r;
729
730 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
731 if (!sd)
732 return -ENOMEM;
733 sd->cpu = cpu;
734 sd->save_area = alloc_page(GFP_KERNEL);
735 r = -ENOMEM;
736 if (!sd->save_area)
737 goto err_1;
738
739 per_cpu(svm_data, cpu) = sd;
740
741 return 0;
742
743 err_1:
744 kfree(sd);
745 return r;
746
747 }
748
749 static bool valid_msr_intercept(u32 index)
750 {
751 int i;
752
753 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
754 if (direct_access_msrs[i].index == index)
755 return true;
756
757 return false;
758 }
759
760 static void set_msr_interception(u32 *msrpm, unsigned msr,
761 int read, int write)
762 {
763 u8 bit_read, bit_write;
764 unsigned long tmp;
765 u32 offset;
766
767 /*
768 * If this warning triggers extend the direct_access_msrs list at the
769 * beginning of the file
770 */
771 WARN_ON(!valid_msr_intercept(msr));
772
773 offset = svm_msrpm_offset(msr);
774 bit_read = 2 * (msr & 0x0f);
775 bit_write = 2 * (msr & 0x0f) + 1;
776 tmp = msrpm[offset];
777
778 BUG_ON(offset == MSR_INVALID);
779
780 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
781 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
782
783 msrpm[offset] = tmp;
784 }
785
786 static void svm_vcpu_init_msrpm(u32 *msrpm)
787 {
788 int i;
789
790 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
791
792 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
793 if (!direct_access_msrs[i].always)
794 continue;
795
796 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
797 }
798 }
799
800 static void add_msr_offset(u32 offset)
801 {
802 int i;
803
804 for (i = 0; i < MSRPM_OFFSETS; ++i) {
805
806 /* Offset already in list? */
807 if (msrpm_offsets[i] == offset)
808 return;
809
810 /* Slot used by another offset? */
811 if (msrpm_offsets[i] != MSR_INVALID)
812 continue;
813
814 /* Add offset to list */
815 msrpm_offsets[i] = offset;
816
817 return;
818 }
819
820 /*
821 * If this BUG triggers the msrpm_offsets table has an overflow. Just
822 * increase MSRPM_OFFSETS in this case.
823 */
824 BUG();
825 }
826
827 static void init_msrpm_offsets(void)
828 {
829 int i;
830
831 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
832
833 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
834 u32 offset;
835
836 offset = svm_msrpm_offset(direct_access_msrs[i].index);
837 BUG_ON(offset == MSR_INVALID);
838
839 add_msr_offset(offset);
840 }
841 }
842
843 static void svm_enable_lbrv(struct vcpu_svm *svm)
844 {
845 u32 *msrpm = svm->msrpm;
846
847 svm->vmcb->control.lbr_ctl = 1;
848 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
849 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
850 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
851 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
852 }
853
854 static void svm_disable_lbrv(struct vcpu_svm *svm)
855 {
856 u32 *msrpm = svm->msrpm;
857
858 svm->vmcb->control.lbr_ctl = 0;
859 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
860 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
861 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
862 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
863 }
864
865 static __init int svm_hardware_setup(void)
866 {
867 int cpu;
868 struct page *iopm_pages;
869 void *iopm_va;
870 int r;
871
872 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
873
874 if (!iopm_pages)
875 return -ENOMEM;
876
877 iopm_va = page_address(iopm_pages);
878 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
879 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
880
881 init_msrpm_offsets();
882
883 if (boot_cpu_has(X86_FEATURE_NX))
884 kvm_enable_efer_bits(EFER_NX);
885
886 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
887 kvm_enable_efer_bits(EFER_FFXSR);
888
889 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
890 u64 max;
891
892 kvm_has_tsc_control = true;
893
894 /*
895 * Make sure the user can only configure tsc_khz values that
896 * fit into a signed integer.
897 * A min value is not calculated needed because it will always
898 * be 1 on all machines and a value of 0 is used to disable
899 * tsc-scaling for the vcpu.
900 */
901 max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
902
903 kvm_max_guest_tsc_khz = max;
904 }
905
906 if (nested) {
907 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
908 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
909 }
910
911 for_each_possible_cpu(cpu) {
912 r = svm_cpu_init(cpu);
913 if (r)
914 goto err;
915 }
916
917 if (!boot_cpu_has(X86_FEATURE_NPT))
918 npt_enabled = false;
919
920 if (npt_enabled && !npt) {
921 printk(KERN_INFO "kvm: Nested Paging disabled\n");
922 npt_enabled = false;
923 }
924
925 if (npt_enabled) {
926 printk(KERN_INFO "kvm: Nested Paging enabled\n");
927 kvm_enable_tdp();
928 } else
929 kvm_disable_tdp();
930
931 return 0;
932
933 err:
934 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
935 iopm_base = 0;
936 return r;
937 }
938
939 static __exit void svm_hardware_unsetup(void)
940 {
941 int cpu;
942
943 for_each_possible_cpu(cpu)
944 svm_cpu_uninit(cpu);
945
946 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
947 iopm_base = 0;
948 }
949
950 static void init_seg(struct vmcb_seg *seg)
951 {
952 seg->selector = 0;
953 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
954 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
955 seg->limit = 0xffff;
956 seg->base = 0;
957 }
958
959 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
960 {
961 seg->selector = 0;
962 seg->attrib = SVM_SELECTOR_P_MASK | type;
963 seg->limit = 0xffff;
964 seg->base = 0;
965 }
966
967 static u64 __scale_tsc(u64 ratio, u64 tsc)
968 {
969 u64 mult, frac, _tsc;
970
971 mult = ratio >> 32;
972 frac = ratio & ((1ULL << 32) - 1);
973
974 _tsc = tsc;
975 _tsc *= mult;
976 _tsc += (tsc >> 32) * frac;
977 _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
978
979 return _tsc;
980 }
981
982 static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
983 {
984 struct vcpu_svm *svm = to_svm(vcpu);
985 u64 _tsc = tsc;
986
987 if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
988 _tsc = __scale_tsc(svm->tsc_ratio, tsc);
989
990 return _tsc;
991 }
992
993 static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
994 {
995 struct vcpu_svm *svm = to_svm(vcpu);
996 u64 ratio;
997 u64 khz;
998
999 /* Guest TSC same frequency as host TSC? */
1000 if (!scale) {
1001 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1002 return;
1003 }
1004
1005 /* TSC scaling supported? */
1006 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1007 if (user_tsc_khz > tsc_khz) {
1008 vcpu->arch.tsc_catchup = 1;
1009 vcpu->arch.tsc_always_catchup = 1;
1010 } else
1011 WARN(1, "user requested TSC rate below hardware speed\n");
1012 return;
1013 }
1014
1015 khz = user_tsc_khz;
1016
1017 /* TSC scaling required - calculate ratio */
1018 ratio = khz << 32;
1019 do_div(ratio, tsc_khz);
1020
1021 if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
1022 WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
1023 user_tsc_khz);
1024 return;
1025 }
1026 svm->tsc_ratio = ratio;
1027 }
1028
1029 static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
1030 {
1031 struct vcpu_svm *svm = to_svm(vcpu);
1032
1033 return svm->vmcb->control.tsc_offset;
1034 }
1035
1036 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1037 {
1038 struct vcpu_svm *svm = to_svm(vcpu);
1039 u64 g_tsc_offset = 0;
1040
1041 if (is_guest_mode(vcpu)) {
1042 g_tsc_offset = svm->vmcb->control.tsc_offset -
1043 svm->nested.hsave->control.tsc_offset;
1044 svm->nested.hsave->control.tsc_offset = offset;
1045 } else
1046 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1047 svm->vmcb->control.tsc_offset,
1048 offset);
1049
1050 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1051
1052 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1053 }
1054
1055 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1056 {
1057 struct vcpu_svm *svm = to_svm(vcpu);
1058
1059 WARN_ON(adjustment < 0);
1060 if (host)
1061 adjustment = svm_scale_tsc(vcpu, adjustment);
1062
1063 svm->vmcb->control.tsc_offset += adjustment;
1064 if (is_guest_mode(vcpu))
1065 svm->nested.hsave->control.tsc_offset += adjustment;
1066 else
1067 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1068 svm->vmcb->control.tsc_offset - adjustment,
1069 svm->vmcb->control.tsc_offset);
1070
1071 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1072 }
1073
1074 static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1075 {
1076 u64 tsc;
1077
1078 tsc = svm_scale_tsc(vcpu, native_read_tsc());
1079
1080 return target_tsc - tsc;
1081 }
1082
1083 static void init_vmcb(struct vcpu_svm *svm)
1084 {
1085 struct vmcb_control_area *control = &svm->vmcb->control;
1086 struct vmcb_save_area *save = &svm->vmcb->save;
1087
1088 svm->vcpu.fpu_active = 1;
1089 svm->vcpu.arch.hflags = 0;
1090
1091 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1092 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1093 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1094 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1095 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1096 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1097 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1098
1099 set_dr_intercepts(svm);
1100
1101 set_exception_intercept(svm, PF_VECTOR);
1102 set_exception_intercept(svm, UD_VECTOR);
1103 set_exception_intercept(svm, MC_VECTOR);
1104
1105 set_intercept(svm, INTERCEPT_INTR);
1106 set_intercept(svm, INTERCEPT_NMI);
1107 set_intercept(svm, INTERCEPT_SMI);
1108 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1109 set_intercept(svm, INTERCEPT_RDPMC);
1110 set_intercept(svm, INTERCEPT_CPUID);
1111 set_intercept(svm, INTERCEPT_INVD);
1112 set_intercept(svm, INTERCEPT_HLT);
1113 set_intercept(svm, INTERCEPT_INVLPG);
1114 set_intercept(svm, INTERCEPT_INVLPGA);
1115 set_intercept(svm, INTERCEPT_IOIO_PROT);
1116 set_intercept(svm, INTERCEPT_MSR_PROT);
1117 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1118 set_intercept(svm, INTERCEPT_SHUTDOWN);
1119 set_intercept(svm, INTERCEPT_VMRUN);
1120 set_intercept(svm, INTERCEPT_VMMCALL);
1121 set_intercept(svm, INTERCEPT_VMLOAD);
1122 set_intercept(svm, INTERCEPT_VMSAVE);
1123 set_intercept(svm, INTERCEPT_STGI);
1124 set_intercept(svm, INTERCEPT_CLGI);
1125 set_intercept(svm, INTERCEPT_SKINIT);
1126 set_intercept(svm, INTERCEPT_WBINVD);
1127 set_intercept(svm, INTERCEPT_MONITOR);
1128 set_intercept(svm, INTERCEPT_MWAIT);
1129 set_intercept(svm, INTERCEPT_XSETBV);
1130
1131 control->iopm_base_pa = iopm_base;
1132 control->msrpm_base_pa = __pa(svm->msrpm);
1133 control->int_ctl = V_INTR_MASKING_MASK;
1134
1135 init_seg(&save->es);
1136 init_seg(&save->ss);
1137 init_seg(&save->ds);
1138 init_seg(&save->fs);
1139 init_seg(&save->gs);
1140
1141 save->cs.selector = 0xf000;
1142 save->cs.base = 0xffff0000;
1143 /* Executable/Readable Code Segment */
1144 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1145 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1146 save->cs.limit = 0xffff;
1147
1148 save->gdtr.limit = 0xffff;
1149 save->idtr.limit = 0xffff;
1150
1151 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1152 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1153
1154 svm_set_efer(&svm->vcpu, 0);
1155 save->dr6 = 0xffff0ff0;
1156 kvm_set_rflags(&svm->vcpu, 2);
1157 save->rip = 0x0000fff0;
1158 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1159
1160 /*
1161 * This is the guest-visible cr0 value.
1162 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1163 */
1164 svm->vcpu.arch.cr0 = 0;
1165 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1166
1167 save->cr4 = X86_CR4_PAE;
1168 /* rdx = ?? */
1169
1170 if (npt_enabled) {
1171 /* Setup VMCB for Nested Paging */
1172 control->nested_ctl = 1;
1173 clr_intercept(svm, INTERCEPT_INVLPG);
1174 clr_exception_intercept(svm, PF_VECTOR);
1175 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1176 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1177 save->g_pat = 0x0007040600070406ULL;
1178 save->cr3 = 0;
1179 save->cr4 = 0;
1180 }
1181 svm->asid_generation = 0;
1182
1183 svm->nested.vmcb = 0;
1184 svm->vcpu.arch.hflags = 0;
1185
1186 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1187 control->pause_filter_count = 3000;
1188 set_intercept(svm, INTERCEPT_PAUSE);
1189 }
1190
1191 mark_all_dirty(svm->vmcb);
1192
1193 enable_gif(svm);
1194 }
1195
1196 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
1197 {
1198 struct vcpu_svm *svm = to_svm(vcpu);
1199 u32 dummy;
1200 u32 eax = 1;
1201
1202 init_vmcb(svm);
1203
1204 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
1205 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1206 }
1207
1208 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1209 {
1210 struct vcpu_svm *svm;
1211 struct page *page;
1212 struct page *msrpm_pages;
1213 struct page *hsave_page;
1214 struct page *nested_msrpm_pages;
1215 int err;
1216
1217 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1218 if (!svm) {
1219 err = -ENOMEM;
1220 goto out;
1221 }
1222
1223 svm->tsc_ratio = TSC_RATIO_DEFAULT;
1224
1225 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1226 if (err)
1227 goto free_svm;
1228
1229 err = -ENOMEM;
1230 page = alloc_page(GFP_KERNEL);
1231 if (!page)
1232 goto uninit;
1233
1234 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1235 if (!msrpm_pages)
1236 goto free_page1;
1237
1238 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1239 if (!nested_msrpm_pages)
1240 goto free_page2;
1241
1242 hsave_page = alloc_page(GFP_KERNEL);
1243 if (!hsave_page)
1244 goto free_page3;
1245
1246 svm->nested.hsave = page_address(hsave_page);
1247
1248 svm->msrpm = page_address(msrpm_pages);
1249 svm_vcpu_init_msrpm(svm->msrpm);
1250
1251 svm->nested.msrpm = page_address(nested_msrpm_pages);
1252 svm_vcpu_init_msrpm(svm->nested.msrpm);
1253
1254 svm->vmcb = page_address(page);
1255 clear_page(svm->vmcb);
1256 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1257 svm->asid_generation = 0;
1258 init_vmcb(svm);
1259
1260 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1261 if (kvm_vcpu_is_bsp(&svm->vcpu))
1262 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1263
1264 svm_init_osvw(&svm->vcpu);
1265
1266 return &svm->vcpu;
1267
1268 free_page3:
1269 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1270 free_page2:
1271 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1272 free_page1:
1273 __free_page(page);
1274 uninit:
1275 kvm_vcpu_uninit(&svm->vcpu);
1276 free_svm:
1277 kmem_cache_free(kvm_vcpu_cache, svm);
1278 out:
1279 return ERR_PTR(err);
1280 }
1281
1282 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1283 {
1284 struct vcpu_svm *svm = to_svm(vcpu);
1285
1286 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1287 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1288 __free_page(virt_to_page(svm->nested.hsave));
1289 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1290 kvm_vcpu_uninit(vcpu);
1291 kmem_cache_free(kvm_vcpu_cache, svm);
1292 }
1293
1294 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1295 {
1296 struct vcpu_svm *svm = to_svm(vcpu);
1297 int i;
1298
1299 if (unlikely(cpu != vcpu->cpu)) {
1300 svm->asid_generation = 0;
1301 mark_all_dirty(svm->vmcb);
1302 }
1303
1304 #ifdef CONFIG_X86_64
1305 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1306 #endif
1307 savesegment(fs, svm->host.fs);
1308 savesegment(gs, svm->host.gs);
1309 svm->host.ldt = kvm_read_ldt();
1310
1311 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1312 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313
1314 if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
1315 svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
1316 __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
1317 wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
1318 }
1319 }
1320
1321 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1322 {
1323 struct vcpu_svm *svm = to_svm(vcpu);
1324 int i;
1325
1326 ++vcpu->stat.host_state_reload;
1327 kvm_load_ldt(svm->host.ldt);
1328 #ifdef CONFIG_X86_64
1329 loadsegment(fs, svm->host.fs);
1330 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1331 load_gs_index(svm->host.gs);
1332 #else
1333 #ifdef CONFIG_X86_32_LAZY_GS
1334 loadsegment(gs, svm->host.gs);
1335 #endif
1336 #endif
1337 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1338 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1339 }
1340
1341 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1342 {
1343 return to_svm(vcpu)->vmcb->save.rflags;
1344 }
1345
1346 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1347 {
1348 /*
1349 * Any change of EFLAGS.VM is accompained by a reload of SS
1350 * (caused by either a task switch or an inter-privilege IRET),
1351 * so we do not need to update the CPL here.
1352 */
1353 to_svm(vcpu)->vmcb->save.rflags = rflags;
1354 }
1355
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1357 {
1358 switch (reg) {
1359 case VCPU_EXREG_PDPTR:
1360 BUG_ON(!npt_enabled);
1361 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1362 break;
1363 default:
1364 BUG();
1365 }
1366 }
1367
1368 static void svm_set_vintr(struct vcpu_svm *svm)
1369 {
1370 set_intercept(svm, INTERCEPT_VINTR);
1371 }
1372
1373 static void svm_clear_vintr(struct vcpu_svm *svm)
1374 {
1375 clr_intercept(svm, INTERCEPT_VINTR);
1376 }
1377
1378 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1379 {
1380 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1381
1382 switch (seg) {
1383 case VCPU_SREG_CS: return &save->cs;
1384 case VCPU_SREG_DS: return &save->ds;
1385 case VCPU_SREG_ES: return &save->es;
1386 case VCPU_SREG_FS: return &save->fs;
1387 case VCPU_SREG_GS: return &save->gs;
1388 case VCPU_SREG_SS: return &save->ss;
1389 case VCPU_SREG_TR: return &save->tr;
1390 case VCPU_SREG_LDTR: return &save->ldtr;
1391 }
1392 BUG();
1393 return NULL;
1394 }
1395
1396 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1397 {
1398 struct vmcb_seg *s = svm_seg(vcpu, seg);
1399
1400 return s->base;
1401 }
1402
1403 static void svm_get_segment(struct kvm_vcpu *vcpu,
1404 struct kvm_segment *var, int seg)
1405 {
1406 struct vmcb_seg *s = svm_seg(vcpu, seg);
1407
1408 var->base = s->base;
1409 var->limit = s->limit;
1410 var->selector = s->selector;
1411 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1412 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1413 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1414 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1415 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1416 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1417 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1418 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1419
1420 /*
1421 * AMD's VMCB does not have an explicit unusable field, so emulate it
1422 * for cross vendor migration purposes by "not present"
1423 */
1424 var->unusable = !var->present || (var->type == 0);
1425
1426 switch (seg) {
1427 case VCPU_SREG_CS:
1428 /*
1429 * SVM always stores 0 for the 'G' bit in the CS selector in
1430 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1431 * Intel's VMENTRY has a check on the 'G' bit.
1432 */
1433 var->g = s->limit > 0xfffff;
1434 break;
1435 case VCPU_SREG_TR:
1436 /*
1437 * Work around a bug where the busy flag in the tr selector
1438 * isn't exposed
1439 */
1440 var->type |= 0x2;
1441 break;
1442 case VCPU_SREG_DS:
1443 case VCPU_SREG_ES:
1444 case VCPU_SREG_FS:
1445 case VCPU_SREG_GS:
1446 /*
1447 * The accessed bit must always be set in the segment
1448 * descriptor cache, although it can be cleared in the
1449 * descriptor, the cached bit always remains at 1. Since
1450 * Intel has a check on this, set it here to support
1451 * cross-vendor migration.
1452 */
1453 if (!var->unusable)
1454 var->type |= 0x1;
1455 break;
1456 case VCPU_SREG_SS:
1457 /*
1458 * On AMD CPUs sometimes the DB bit in the segment
1459 * descriptor is left as 1, although the whole segment has
1460 * been made unusable. Clear it here to pass an Intel VMX
1461 * entry check when cross vendor migrating.
1462 */
1463 if (var->unusable)
1464 var->db = 0;
1465 break;
1466 }
1467 }
1468
1469 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1470 {
1471 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1472
1473 return save->cpl;
1474 }
1475
1476 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1477 {
1478 struct vcpu_svm *svm = to_svm(vcpu);
1479
1480 dt->size = svm->vmcb->save.idtr.limit;
1481 dt->address = svm->vmcb->save.idtr.base;
1482 }
1483
1484 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1485 {
1486 struct vcpu_svm *svm = to_svm(vcpu);
1487
1488 svm->vmcb->save.idtr.limit = dt->size;
1489 svm->vmcb->save.idtr.base = dt->address ;
1490 mark_dirty(svm->vmcb, VMCB_DT);
1491 }
1492
1493 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1494 {
1495 struct vcpu_svm *svm = to_svm(vcpu);
1496
1497 dt->size = svm->vmcb->save.gdtr.limit;
1498 dt->address = svm->vmcb->save.gdtr.base;
1499 }
1500
1501 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1502 {
1503 struct vcpu_svm *svm = to_svm(vcpu);
1504
1505 svm->vmcb->save.gdtr.limit = dt->size;
1506 svm->vmcb->save.gdtr.base = dt->address ;
1507 mark_dirty(svm->vmcb, VMCB_DT);
1508 }
1509
1510 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1511 {
1512 }
1513
1514 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1515 {
1516 }
1517
1518 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1519 {
1520 }
1521
1522 static void update_cr0_intercept(struct vcpu_svm *svm)
1523 {
1524 ulong gcr0 = svm->vcpu.arch.cr0;
1525 u64 *hcr0 = &svm->vmcb->save.cr0;
1526
1527 if (!svm->vcpu.fpu_active)
1528 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1529 else
1530 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1531 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1532
1533 mark_dirty(svm->vmcb, VMCB_CR);
1534
1535 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1536 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1537 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1538 } else {
1539 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1540 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1541 }
1542 }
1543
1544 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1545 {
1546 struct vcpu_svm *svm = to_svm(vcpu);
1547
1548 #ifdef CONFIG_X86_64
1549 if (vcpu->arch.efer & EFER_LME) {
1550 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1551 vcpu->arch.efer |= EFER_LMA;
1552 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1553 }
1554
1555 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1556 vcpu->arch.efer &= ~EFER_LMA;
1557 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1558 }
1559 }
1560 #endif
1561 vcpu->arch.cr0 = cr0;
1562
1563 if (!npt_enabled)
1564 cr0 |= X86_CR0_PG | X86_CR0_WP;
1565
1566 if (!vcpu->fpu_active)
1567 cr0 |= X86_CR0_TS;
1568 /*
1569 * re-enable caching here because the QEMU bios
1570 * does not do it - this results in some delay at
1571 * reboot
1572 */
1573 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1574 svm->vmcb->save.cr0 = cr0;
1575 mark_dirty(svm->vmcb, VMCB_CR);
1576 update_cr0_intercept(svm);
1577 }
1578
1579 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1580 {
1581 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1582 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1583
1584 if (cr4 & X86_CR4_VMXE)
1585 return 1;
1586
1587 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1588 svm_flush_tlb(vcpu);
1589
1590 vcpu->arch.cr4 = cr4;
1591 if (!npt_enabled)
1592 cr4 |= X86_CR4_PAE;
1593 cr4 |= host_cr4_mce;
1594 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1595 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1596 return 0;
1597 }
1598
1599 static void svm_set_segment(struct kvm_vcpu *vcpu,
1600 struct kvm_segment *var, int seg)
1601 {
1602 struct vcpu_svm *svm = to_svm(vcpu);
1603 struct vmcb_seg *s = svm_seg(vcpu, seg);
1604
1605 s->base = var->base;
1606 s->limit = var->limit;
1607 s->selector = var->selector;
1608 if (var->unusable)
1609 s->attrib = 0;
1610 else {
1611 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1612 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1613 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1614 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1615 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1616 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1617 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1618 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1619 }
1620
1621 /*
1622 * This is always accurate, except if SYSRET returned to a segment
1623 * with SS.DPL != 3. Intel does not have this quirk, and always
1624 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1625 * would entail passing the CPL to userspace and back.
1626 */
1627 if (seg == VCPU_SREG_SS)
1628 svm->vmcb->save.cpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1629
1630 mark_dirty(svm->vmcb, VMCB_SEG);
1631 }
1632
1633 static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
1634 {
1635 struct vcpu_svm *svm = to_svm(vcpu);
1636
1637 clr_exception_intercept(svm, DB_VECTOR);
1638 clr_exception_intercept(svm, BP_VECTOR);
1639
1640 if (svm->nmi_singlestep)
1641 set_exception_intercept(svm, DB_VECTOR);
1642
1643 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1644 if (vcpu->guest_debug &
1645 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1646 set_exception_intercept(svm, DB_VECTOR);
1647 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1648 set_exception_intercept(svm, BP_VECTOR);
1649 } else
1650 vcpu->guest_debug = 0;
1651 }
1652
1653 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1654 {
1655 if (sd->next_asid > sd->max_asid) {
1656 ++sd->asid_generation;
1657 sd->next_asid = 1;
1658 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1659 }
1660
1661 svm->asid_generation = sd->asid_generation;
1662 svm->vmcb->control.asid = sd->next_asid++;
1663
1664 mark_dirty(svm->vmcb, VMCB_ASID);
1665 }
1666
1667 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1668 {
1669 return to_svm(vcpu)->vmcb->save.dr6;
1670 }
1671
1672 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1673 {
1674 struct vcpu_svm *svm = to_svm(vcpu);
1675
1676 svm->vmcb->save.dr6 = value;
1677 mark_dirty(svm->vmcb, VMCB_DR);
1678 }
1679
1680 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1681 {
1682 struct vcpu_svm *svm = to_svm(vcpu);
1683
1684 get_debugreg(vcpu->arch.db[0], 0);
1685 get_debugreg(vcpu->arch.db[1], 1);
1686 get_debugreg(vcpu->arch.db[2], 2);
1687 get_debugreg(vcpu->arch.db[3], 3);
1688 vcpu->arch.dr6 = svm_get_dr6(vcpu);
1689 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1690
1691 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1692 set_dr_intercepts(svm);
1693 }
1694
1695 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1696 {
1697 struct vcpu_svm *svm = to_svm(vcpu);
1698
1699 svm->vmcb->save.dr7 = value;
1700 mark_dirty(svm->vmcb, VMCB_DR);
1701 }
1702
1703 static int pf_interception(struct vcpu_svm *svm)
1704 {
1705 u64 fault_address = svm->vmcb->control.exit_info_2;
1706 u32 error_code;
1707 int r = 1;
1708
1709 switch (svm->apf_reason) {
1710 default:
1711 error_code = svm->vmcb->control.exit_info_1;
1712
1713 trace_kvm_page_fault(fault_address, error_code);
1714 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1715 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1716 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1717 svm->vmcb->control.insn_bytes,
1718 svm->vmcb->control.insn_len);
1719 break;
1720 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1721 svm->apf_reason = 0;
1722 local_irq_disable();
1723 kvm_async_pf_task_wait(fault_address);
1724 local_irq_enable();
1725 break;
1726 case KVM_PV_REASON_PAGE_READY:
1727 svm->apf_reason = 0;
1728 local_irq_disable();
1729 kvm_async_pf_task_wake(fault_address);
1730 local_irq_enable();
1731 break;
1732 }
1733 return r;
1734 }
1735
1736 static int db_interception(struct vcpu_svm *svm)
1737 {
1738 struct kvm_run *kvm_run = svm->vcpu.run;
1739
1740 if (!(svm->vcpu.guest_debug &
1741 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1742 !svm->nmi_singlestep) {
1743 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1744 return 1;
1745 }
1746
1747 if (svm->nmi_singlestep) {
1748 svm->nmi_singlestep = false;
1749 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1750 svm->vmcb->save.rflags &=
1751 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1752 update_db_bp_intercept(&svm->vcpu);
1753 }
1754
1755 if (svm->vcpu.guest_debug &
1756 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1757 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1758 kvm_run->debug.arch.pc =
1759 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1760 kvm_run->debug.arch.exception = DB_VECTOR;
1761 return 0;
1762 }
1763
1764 return 1;
1765 }
1766
1767 static int bp_interception(struct vcpu_svm *svm)
1768 {
1769 struct kvm_run *kvm_run = svm->vcpu.run;
1770
1771 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1772 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1773 kvm_run->debug.arch.exception = BP_VECTOR;
1774 return 0;
1775 }
1776
1777 static int ud_interception(struct vcpu_svm *svm)
1778 {
1779 int er;
1780
1781 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1782 if (er != EMULATE_DONE)
1783 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1784 return 1;
1785 }
1786
1787 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1788 {
1789 struct vcpu_svm *svm = to_svm(vcpu);
1790
1791 clr_exception_intercept(svm, NM_VECTOR);
1792
1793 svm->vcpu.fpu_active = 1;
1794 update_cr0_intercept(svm);
1795 }
1796
1797 static int nm_interception(struct vcpu_svm *svm)
1798 {
1799 svm_fpu_activate(&svm->vcpu);
1800 return 1;
1801 }
1802
1803 static bool is_erratum_383(void)
1804 {
1805 int err, i;
1806 u64 value;
1807
1808 if (!erratum_383_found)
1809 return false;
1810
1811 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1812 if (err)
1813 return false;
1814
1815 /* Bit 62 may or may not be set for this mce */
1816 value &= ~(1ULL << 62);
1817
1818 if (value != 0xb600000000010015ULL)
1819 return false;
1820
1821 /* Clear MCi_STATUS registers */
1822 for (i = 0; i < 6; ++i)
1823 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1824
1825 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1826 if (!err) {
1827 u32 low, high;
1828
1829 value &= ~(1ULL << 2);
1830 low = lower_32_bits(value);
1831 high = upper_32_bits(value);
1832
1833 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1834 }
1835
1836 /* Flush tlb to evict multi-match entries */
1837 __flush_tlb_all();
1838
1839 return true;
1840 }
1841
1842 static void svm_handle_mce(struct vcpu_svm *svm)
1843 {
1844 if (is_erratum_383()) {
1845 /*
1846 * Erratum 383 triggered. Guest state is corrupt so kill the
1847 * guest.
1848 */
1849 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1850
1851 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1852
1853 return;
1854 }
1855
1856 /*
1857 * On an #MC intercept the MCE handler is not called automatically in
1858 * the host. So do it by hand here.
1859 */
1860 asm volatile (
1861 "int $0x12\n");
1862 /* not sure if we ever come back to this point */
1863
1864 return;
1865 }
1866
1867 static int mc_interception(struct vcpu_svm *svm)
1868 {
1869 return 1;
1870 }
1871
1872 static int shutdown_interception(struct vcpu_svm *svm)
1873 {
1874 struct kvm_run *kvm_run = svm->vcpu.run;
1875
1876 /*
1877 * VMCB is undefined after a SHUTDOWN intercept
1878 * so reinitialize it.
1879 */
1880 clear_page(svm->vmcb);
1881 init_vmcb(svm);
1882
1883 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1884 return 0;
1885 }
1886
1887 static int io_interception(struct vcpu_svm *svm)
1888 {
1889 struct kvm_vcpu *vcpu = &svm->vcpu;
1890 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1891 int size, in, string;
1892 unsigned port;
1893
1894 ++svm->vcpu.stat.io_exits;
1895 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1896 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1897 if (string || in)
1898 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1899
1900 port = io_info >> 16;
1901 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1902 svm->next_rip = svm->vmcb->control.exit_info_2;
1903 skip_emulated_instruction(&svm->vcpu);
1904
1905 return kvm_fast_pio_out(vcpu, size, port);
1906 }
1907
1908 static int nmi_interception(struct vcpu_svm *svm)
1909 {
1910 return 1;
1911 }
1912
1913 static int intr_interception(struct vcpu_svm *svm)
1914 {
1915 ++svm->vcpu.stat.irq_exits;
1916 return 1;
1917 }
1918
1919 static int nop_on_interception(struct vcpu_svm *svm)
1920 {
1921 return 1;
1922 }
1923
1924 static int halt_interception(struct vcpu_svm *svm)
1925 {
1926 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1927 skip_emulated_instruction(&svm->vcpu);
1928 return kvm_emulate_halt(&svm->vcpu);
1929 }
1930
1931 static int vmmcall_interception(struct vcpu_svm *svm)
1932 {
1933 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1934 skip_emulated_instruction(&svm->vcpu);
1935 kvm_emulate_hypercall(&svm->vcpu);
1936 return 1;
1937 }
1938
1939 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1940 {
1941 struct vcpu_svm *svm = to_svm(vcpu);
1942
1943 return svm->nested.nested_cr3;
1944 }
1945
1946 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
1947 {
1948 struct vcpu_svm *svm = to_svm(vcpu);
1949 u64 cr3 = svm->nested.nested_cr3;
1950 u64 pdpte;
1951 int ret;
1952
1953 ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
1954 offset_in_page(cr3) + index * 8, 8);
1955 if (ret)
1956 return 0;
1957 return pdpte;
1958 }
1959
1960 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1961 unsigned long root)
1962 {
1963 struct vcpu_svm *svm = to_svm(vcpu);
1964
1965 svm->vmcb->control.nested_cr3 = root;
1966 mark_dirty(svm->vmcb, VMCB_NPT);
1967 svm_flush_tlb(vcpu);
1968 }
1969
1970 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1971 struct x86_exception *fault)
1972 {
1973 struct vcpu_svm *svm = to_svm(vcpu);
1974
1975 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1976 svm->vmcb->control.exit_code_hi = 0;
1977 svm->vmcb->control.exit_info_1 = fault->error_code;
1978 svm->vmcb->control.exit_info_2 = fault->address;
1979
1980 nested_svm_vmexit(svm);
1981 }
1982
1983 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1984 {
1985 kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1986
1987 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1988 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1989 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
1990 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1991 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1992 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1993 }
1994
1995 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1996 {
1997 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1998 }
1999
2000 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2001 {
2002 if (!(svm->vcpu.arch.efer & EFER_SVME)
2003 || !is_paging(&svm->vcpu)) {
2004 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2005 return 1;
2006 }
2007
2008 if (svm->vmcb->save.cpl) {
2009 kvm_inject_gp(&svm->vcpu, 0);
2010 return 1;
2011 }
2012
2013 return 0;
2014 }
2015
2016 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2017 bool has_error_code, u32 error_code)
2018 {
2019 int vmexit;
2020
2021 if (!is_guest_mode(&svm->vcpu))
2022 return 0;
2023
2024 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2025 svm->vmcb->control.exit_code_hi = 0;
2026 svm->vmcb->control.exit_info_1 = error_code;
2027 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2028
2029 vmexit = nested_svm_intercept(svm);
2030 if (vmexit == NESTED_EXIT_DONE)
2031 svm->nested.exit_required = true;
2032
2033 return vmexit;
2034 }
2035
2036 /* This function returns true if it is save to enable the irq window */
2037 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2038 {
2039 if (!is_guest_mode(&svm->vcpu))
2040 return true;
2041
2042 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2043 return true;
2044
2045 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2046 return false;
2047
2048 /*
2049 * if vmexit was already requested (by intercepted exception
2050 * for instance) do not overwrite it with "external interrupt"
2051 * vmexit.
2052 */
2053 if (svm->nested.exit_required)
2054 return false;
2055
2056 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2057 svm->vmcb->control.exit_info_1 = 0;
2058 svm->vmcb->control.exit_info_2 = 0;
2059
2060 if (svm->nested.intercept & 1ULL) {
2061 /*
2062 * The #vmexit can't be emulated here directly because this
2063 * code path runs with irqs and preemption disabled. A
2064 * #vmexit emulation might sleep. Only signal request for
2065 * the #vmexit here.
2066 */
2067 svm->nested.exit_required = true;
2068 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2069 return false;
2070 }
2071
2072 return true;
2073 }
2074
2075 /* This function returns true if it is save to enable the nmi window */
2076 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2077 {
2078 if (!is_guest_mode(&svm->vcpu))
2079 return true;
2080
2081 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2082 return true;
2083
2084 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2085 svm->nested.exit_required = true;
2086
2087 return false;
2088 }
2089
2090 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2091 {
2092 struct page *page;
2093
2094 might_sleep();
2095
2096 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
2097 if (is_error_page(page))
2098 goto error;
2099
2100 *_page = page;
2101
2102 return kmap(page);
2103
2104 error:
2105 kvm_inject_gp(&svm->vcpu, 0);
2106
2107 return NULL;
2108 }
2109
2110 static void nested_svm_unmap(struct page *page)
2111 {
2112 kunmap(page);
2113 kvm_release_page_dirty(page);
2114 }
2115
2116 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2117 {
2118 unsigned port;
2119 u8 val, bit;
2120 u64 gpa;
2121
2122 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2123 return NESTED_EXIT_HOST;
2124
2125 port = svm->vmcb->control.exit_info_1 >> 16;
2126 gpa = svm->nested.vmcb_iopm + (port / 8);
2127 bit = port % 8;
2128 val = 0;
2129
2130 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
2131 val &= (1 << bit);
2132
2133 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2134 }
2135
2136 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2137 {
2138 u32 offset, msr, value;
2139 int write, mask;
2140
2141 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2142 return NESTED_EXIT_HOST;
2143
2144 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2145 offset = svm_msrpm_offset(msr);
2146 write = svm->vmcb->control.exit_info_1 & 1;
2147 mask = 1 << ((2 * (msr & 0xf)) + write);
2148
2149 if (offset == MSR_INVALID)
2150 return NESTED_EXIT_DONE;
2151
2152 /* Offset is in 32 bit units but need in 8 bit units */
2153 offset *= 4;
2154
2155 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
2156 return NESTED_EXIT_DONE;
2157
2158 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2159 }
2160
2161 static int nested_svm_exit_special(struct vcpu_svm *svm)
2162 {
2163 u32 exit_code = svm->vmcb->control.exit_code;
2164
2165 switch (exit_code) {
2166 case SVM_EXIT_INTR:
2167 case SVM_EXIT_NMI:
2168 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2169 return NESTED_EXIT_HOST;
2170 case SVM_EXIT_NPF:
2171 /* For now we are always handling NPFs when using them */
2172 if (npt_enabled)
2173 return NESTED_EXIT_HOST;
2174 break;
2175 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2176 /* When we're shadowing, trap PFs, but not async PF */
2177 if (!npt_enabled && svm->apf_reason == 0)
2178 return NESTED_EXIT_HOST;
2179 break;
2180 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
2181 nm_interception(svm);
2182 break;
2183 default:
2184 break;
2185 }
2186
2187 return NESTED_EXIT_CONTINUE;
2188 }
2189
2190 /*
2191 * If this function returns true, this #vmexit was already handled
2192 */
2193 static int nested_svm_intercept(struct vcpu_svm *svm)
2194 {
2195 u32 exit_code = svm->vmcb->control.exit_code;
2196 int vmexit = NESTED_EXIT_HOST;
2197
2198 switch (exit_code) {
2199 case SVM_EXIT_MSR:
2200 vmexit = nested_svm_exit_handled_msr(svm);
2201 break;
2202 case SVM_EXIT_IOIO:
2203 vmexit = nested_svm_intercept_ioio(svm);
2204 break;
2205 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2206 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2207 if (svm->nested.intercept_cr & bit)
2208 vmexit = NESTED_EXIT_DONE;
2209 break;
2210 }
2211 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2212 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2213 if (svm->nested.intercept_dr & bit)
2214 vmexit = NESTED_EXIT_DONE;
2215 break;
2216 }
2217 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2218 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2219 if (svm->nested.intercept_exceptions & excp_bits)
2220 vmexit = NESTED_EXIT_DONE;
2221 /* async page fault always cause vmexit */
2222 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2223 svm->apf_reason != 0)
2224 vmexit = NESTED_EXIT_DONE;
2225 break;
2226 }
2227 case SVM_EXIT_ERR: {
2228 vmexit = NESTED_EXIT_DONE;
2229 break;
2230 }
2231 default: {
2232 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2233 if (svm->nested.intercept & exit_bits)
2234 vmexit = NESTED_EXIT_DONE;
2235 }
2236 }
2237
2238 return vmexit;
2239 }
2240
2241 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2242 {
2243 int vmexit;
2244
2245 vmexit = nested_svm_intercept(svm);
2246
2247 if (vmexit == NESTED_EXIT_DONE)
2248 nested_svm_vmexit(svm);
2249
2250 return vmexit;
2251 }
2252
2253 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2254 {
2255 struct vmcb_control_area *dst = &dst_vmcb->control;
2256 struct vmcb_control_area *from = &from_vmcb->control;
2257
2258 dst->intercept_cr = from->intercept_cr;
2259 dst->intercept_dr = from->intercept_dr;
2260 dst->intercept_exceptions = from->intercept_exceptions;
2261 dst->intercept = from->intercept;
2262 dst->iopm_base_pa = from->iopm_base_pa;
2263 dst->msrpm_base_pa = from->msrpm_base_pa;
2264 dst->tsc_offset = from->tsc_offset;
2265 dst->asid = from->asid;
2266 dst->tlb_ctl = from->tlb_ctl;
2267 dst->int_ctl = from->int_ctl;
2268 dst->int_vector = from->int_vector;
2269 dst->int_state = from->int_state;
2270 dst->exit_code = from->exit_code;
2271 dst->exit_code_hi = from->exit_code_hi;
2272 dst->exit_info_1 = from->exit_info_1;
2273 dst->exit_info_2 = from->exit_info_2;
2274 dst->exit_int_info = from->exit_int_info;
2275 dst->exit_int_info_err = from->exit_int_info_err;
2276 dst->nested_ctl = from->nested_ctl;
2277 dst->event_inj = from->event_inj;
2278 dst->event_inj_err = from->event_inj_err;
2279 dst->nested_cr3 = from->nested_cr3;
2280 dst->lbr_ctl = from->lbr_ctl;
2281 }
2282
2283 static int nested_svm_vmexit(struct vcpu_svm *svm)
2284 {
2285 struct vmcb *nested_vmcb;
2286 struct vmcb *hsave = svm->nested.hsave;
2287 struct vmcb *vmcb = svm->vmcb;
2288 struct page *page;
2289
2290 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2291 vmcb->control.exit_info_1,
2292 vmcb->control.exit_info_2,
2293 vmcb->control.exit_int_info,
2294 vmcb->control.exit_int_info_err,
2295 KVM_ISA_SVM);
2296
2297 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2298 if (!nested_vmcb)
2299 return 1;
2300
2301 /* Exit Guest-Mode */
2302 leave_guest_mode(&svm->vcpu);
2303 svm->nested.vmcb = 0;
2304
2305 /* Give the current vmcb to the guest */
2306 disable_gif(svm);
2307
2308 nested_vmcb->save.es = vmcb->save.es;
2309 nested_vmcb->save.cs = vmcb->save.cs;
2310 nested_vmcb->save.ss = vmcb->save.ss;
2311 nested_vmcb->save.ds = vmcb->save.ds;
2312 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2313 nested_vmcb->save.idtr = vmcb->save.idtr;
2314 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2315 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2316 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2317 nested_vmcb->save.cr2 = vmcb->save.cr2;
2318 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2319 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2320 nested_vmcb->save.rip = vmcb->save.rip;
2321 nested_vmcb->save.rsp = vmcb->save.rsp;
2322 nested_vmcb->save.rax = vmcb->save.rax;
2323 nested_vmcb->save.dr7 = vmcb->save.dr7;
2324 nested_vmcb->save.dr6 = vmcb->save.dr6;
2325 nested_vmcb->save.cpl = vmcb->save.cpl;
2326
2327 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2328 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2329 nested_vmcb->control.int_state = vmcb->control.int_state;
2330 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2331 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2332 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2333 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2334 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2335 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2336 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2337
2338 /*
2339 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2340 * to make sure that we do not lose injected events. So check event_inj
2341 * here and copy it to exit_int_info if it is valid.
2342 * Exit_int_info and event_inj can't be both valid because the case
2343 * below only happens on a VMRUN instruction intercept which has
2344 * no valid exit_int_info set.
2345 */
2346 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2347 struct vmcb_control_area *nc = &nested_vmcb->control;
2348
2349 nc->exit_int_info = vmcb->control.event_inj;
2350 nc->exit_int_info_err = vmcb->control.event_inj_err;
2351 }
2352
2353 nested_vmcb->control.tlb_ctl = 0;
2354 nested_vmcb->control.event_inj = 0;
2355 nested_vmcb->control.event_inj_err = 0;
2356
2357 /* We always set V_INTR_MASKING and remember the old value in hflags */
2358 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2359 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2360
2361 /* Restore the original control entries */
2362 copy_vmcb_control_area(vmcb, hsave);
2363
2364 kvm_clear_exception_queue(&svm->vcpu);
2365 kvm_clear_interrupt_queue(&svm->vcpu);
2366
2367 svm->nested.nested_cr3 = 0;
2368
2369 /* Restore selected save entries */
2370 svm->vmcb->save.es = hsave->save.es;
2371 svm->vmcb->save.cs = hsave->save.cs;
2372 svm->vmcb->save.ss = hsave->save.ss;
2373 svm->vmcb->save.ds = hsave->save.ds;
2374 svm->vmcb->save.gdtr = hsave->save.gdtr;
2375 svm->vmcb->save.idtr = hsave->save.idtr;
2376 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2377 svm_set_efer(&svm->vcpu, hsave->save.efer);
2378 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2379 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2380 if (npt_enabled) {
2381 svm->vmcb->save.cr3 = hsave->save.cr3;
2382 svm->vcpu.arch.cr3 = hsave->save.cr3;
2383 } else {
2384 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2385 }
2386 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2387 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2388 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2389 svm->vmcb->save.dr7 = 0;
2390 svm->vmcb->save.cpl = 0;
2391 svm->vmcb->control.exit_int_info = 0;
2392
2393 mark_all_dirty(svm->vmcb);
2394
2395 nested_svm_unmap(page);
2396
2397 nested_svm_uninit_mmu_context(&svm->vcpu);
2398 kvm_mmu_reset_context(&svm->vcpu);
2399 kvm_mmu_load(&svm->vcpu);
2400
2401 return 0;
2402 }
2403
2404 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2405 {
2406 /*
2407 * This function merges the msr permission bitmaps of kvm and the
2408 * nested vmcb. It is optimized in that it only merges the parts where
2409 * the kvm msr permission bitmap may contain zero bits
2410 */
2411 int i;
2412
2413 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2414 return true;
2415
2416 for (i = 0; i < MSRPM_OFFSETS; i++) {
2417 u32 value, p;
2418 u64 offset;
2419
2420 if (msrpm_offsets[i] == 0xffffffff)
2421 break;
2422
2423 p = msrpm_offsets[i];
2424 offset = svm->nested.vmcb_msrpm + (p * 4);
2425
2426 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2427 return false;
2428
2429 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2430 }
2431
2432 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2433
2434 return true;
2435 }
2436
2437 static bool nested_vmcb_checks(struct vmcb *vmcb)
2438 {
2439 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2440 return false;
2441
2442 if (vmcb->control.asid == 0)
2443 return false;
2444
2445 if (vmcb->control.nested_ctl && !npt_enabled)
2446 return false;
2447
2448 return true;
2449 }
2450
2451 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2452 {
2453 struct vmcb *nested_vmcb;
2454 struct vmcb *hsave = svm->nested.hsave;
2455 struct vmcb *vmcb = svm->vmcb;
2456 struct page *page;
2457 u64 vmcb_gpa;
2458
2459 vmcb_gpa = svm->vmcb->save.rax;
2460
2461 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2462 if (!nested_vmcb)
2463 return false;
2464
2465 if (!nested_vmcb_checks(nested_vmcb)) {
2466 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2467 nested_vmcb->control.exit_code_hi = 0;
2468 nested_vmcb->control.exit_info_1 = 0;
2469 nested_vmcb->control.exit_info_2 = 0;
2470
2471 nested_svm_unmap(page);
2472
2473 return false;
2474 }
2475
2476 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2477 nested_vmcb->save.rip,
2478 nested_vmcb->control.int_ctl,
2479 nested_vmcb->control.event_inj,
2480 nested_vmcb->control.nested_ctl);
2481
2482 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2483 nested_vmcb->control.intercept_cr >> 16,
2484 nested_vmcb->control.intercept_exceptions,
2485 nested_vmcb->control.intercept);
2486
2487 /* Clear internal status */
2488 kvm_clear_exception_queue(&svm->vcpu);
2489 kvm_clear_interrupt_queue(&svm->vcpu);
2490
2491 /*
2492 * Save the old vmcb, so we don't need to pick what we save, but can
2493 * restore everything when a VMEXIT occurs
2494 */
2495 hsave->save.es = vmcb->save.es;
2496 hsave->save.cs = vmcb->save.cs;
2497 hsave->save.ss = vmcb->save.ss;
2498 hsave->save.ds = vmcb->save.ds;
2499 hsave->save.gdtr = vmcb->save.gdtr;
2500 hsave->save.idtr = vmcb->save.idtr;
2501 hsave->save.efer = svm->vcpu.arch.efer;
2502 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2503 hsave->save.cr4 = svm->vcpu.arch.cr4;
2504 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2505 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2506 hsave->save.rsp = vmcb->save.rsp;
2507 hsave->save.rax = vmcb->save.rax;
2508 if (npt_enabled)
2509 hsave->save.cr3 = vmcb->save.cr3;
2510 else
2511 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2512
2513 copy_vmcb_control_area(hsave, vmcb);
2514
2515 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2516 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2517 else
2518 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2519
2520 if (nested_vmcb->control.nested_ctl) {
2521 kvm_mmu_unload(&svm->vcpu);
2522 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2523 nested_svm_init_mmu_context(&svm->vcpu);
2524 }
2525
2526 /* Load the nested guest state */
2527 svm->vmcb->save.es = nested_vmcb->save.es;
2528 svm->vmcb->save.cs = nested_vmcb->save.cs;
2529 svm->vmcb->save.ss = nested_vmcb->save.ss;
2530 svm->vmcb->save.ds = nested_vmcb->save.ds;
2531 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2532 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2533 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2534 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2535 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2536 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2537 if (npt_enabled) {
2538 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2539 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2540 } else
2541 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2542
2543 /* Guest paging mode is active - reset mmu */
2544 kvm_mmu_reset_context(&svm->vcpu);
2545
2546 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2547 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2548 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2549 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2550
2551 /* In case we don't even reach vcpu_run, the fields are not updated */
2552 svm->vmcb->save.rax = nested_vmcb->save.rax;
2553 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2554 svm->vmcb->save.rip = nested_vmcb->save.rip;
2555 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2556 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2557 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2558
2559 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2560 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2561
2562 /* cache intercepts */
2563 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2564 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2565 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2566 svm->nested.intercept = nested_vmcb->control.intercept;
2567
2568 svm_flush_tlb(&svm->vcpu);
2569 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2570 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2571 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2572 else
2573 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2574
2575 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2576 /* We only want the cr8 intercept bits of the guest */
2577 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2578 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2579 }
2580
2581 /* We don't want to see VMMCALLs from a nested guest */
2582 clr_intercept(svm, INTERCEPT_VMMCALL);
2583
2584 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2585 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2586 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2587 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2588 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2589 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2590
2591 nested_svm_unmap(page);
2592
2593 /* Enter Guest-Mode */
2594 enter_guest_mode(&svm->vcpu);
2595
2596 /*
2597 * Merge guest and host intercepts - must be called with vcpu in
2598 * guest-mode to take affect here
2599 */
2600 recalc_intercepts(svm);
2601
2602 svm->nested.vmcb = vmcb_gpa;
2603
2604 enable_gif(svm);
2605
2606 mark_all_dirty(svm->vmcb);
2607
2608 return true;
2609 }
2610
2611 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2612 {
2613 to_vmcb->save.fs = from_vmcb->save.fs;
2614 to_vmcb->save.gs = from_vmcb->save.gs;
2615 to_vmcb->save.tr = from_vmcb->save.tr;
2616 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2617 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2618 to_vmcb->save.star = from_vmcb->save.star;
2619 to_vmcb->save.lstar = from_vmcb->save.lstar;
2620 to_vmcb->save.cstar = from_vmcb->save.cstar;
2621 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2622 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2623 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2624 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2625 }
2626
2627 static int vmload_interception(struct vcpu_svm *svm)
2628 {
2629 struct vmcb *nested_vmcb;
2630 struct page *page;
2631
2632 if (nested_svm_check_permissions(svm))
2633 return 1;
2634
2635 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2636 if (!nested_vmcb)
2637 return 1;
2638
2639 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2640 skip_emulated_instruction(&svm->vcpu);
2641
2642 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2643 nested_svm_unmap(page);
2644
2645 return 1;
2646 }
2647
2648 static int vmsave_interception(struct vcpu_svm *svm)
2649 {
2650 struct vmcb *nested_vmcb;
2651 struct page *page;
2652
2653 if (nested_svm_check_permissions(svm))
2654 return 1;
2655
2656 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2657 if (!nested_vmcb)
2658 return 1;
2659
2660 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2661 skip_emulated_instruction(&svm->vcpu);
2662
2663 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2664 nested_svm_unmap(page);
2665
2666 return 1;
2667 }
2668
2669 static int vmrun_interception(struct vcpu_svm *svm)
2670 {
2671 if (nested_svm_check_permissions(svm))
2672 return 1;
2673
2674 /* Save rip after vmrun instruction */
2675 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2676
2677 if (!nested_svm_vmrun(svm))
2678 return 1;
2679
2680 if (!nested_svm_vmrun_msrpm(svm))
2681 goto failed;
2682
2683 return 1;
2684
2685 failed:
2686
2687 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2688 svm->vmcb->control.exit_code_hi = 0;
2689 svm->vmcb->control.exit_info_1 = 0;
2690 svm->vmcb->control.exit_info_2 = 0;
2691
2692 nested_svm_vmexit(svm);
2693
2694 return 1;
2695 }
2696
2697 static int stgi_interception(struct vcpu_svm *svm)
2698 {
2699 if (nested_svm_check_permissions(svm))
2700 return 1;
2701
2702 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2703 skip_emulated_instruction(&svm->vcpu);
2704 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2705
2706 enable_gif(svm);
2707
2708 return 1;
2709 }
2710
2711 static int clgi_interception(struct vcpu_svm *svm)
2712 {
2713 if (nested_svm_check_permissions(svm))
2714 return 1;
2715
2716 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2717 skip_emulated_instruction(&svm->vcpu);
2718
2719 disable_gif(svm);
2720
2721 /* After a CLGI no interrupts should come */
2722 svm_clear_vintr(svm);
2723 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2724
2725 mark_dirty(svm->vmcb, VMCB_INTR);
2726
2727 return 1;
2728 }
2729
2730 static int invlpga_interception(struct vcpu_svm *svm)
2731 {
2732 struct kvm_vcpu *vcpu = &svm->vcpu;
2733
2734 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2735 vcpu->arch.regs[VCPU_REGS_RAX]);
2736
2737 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2738 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2739
2740 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2741 skip_emulated_instruction(&svm->vcpu);
2742 return 1;
2743 }
2744
2745 static int skinit_interception(struct vcpu_svm *svm)
2746 {
2747 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2748
2749 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2750 return 1;
2751 }
2752
2753 static int xsetbv_interception(struct vcpu_svm *svm)
2754 {
2755 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2756 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2757
2758 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2759 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2760 skip_emulated_instruction(&svm->vcpu);
2761 }
2762
2763 return 1;
2764 }
2765
2766 static int task_switch_interception(struct vcpu_svm *svm)
2767 {
2768 u16 tss_selector;
2769 int reason;
2770 int int_type = svm->vmcb->control.exit_int_info &
2771 SVM_EXITINTINFO_TYPE_MASK;
2772 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2773 uint32_t type =
2774 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2775 uint32_t idt_v =
2776 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2777 bool has_error_code = false;
2778 u32 error_code = 0;
2779
2780 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2781
2782 if (svm->vmcb->control.exit_info_2 &
2783 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2784 reason = TASK_SWITCH_IRET;
2785 else if (svm->vmcb->control.exit_info_2 &
2786 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2787 reason = TASK_SWITCH_JMP;
2788 else if (idt_v)
2789 reason = TASK_SWITCH_GATE;
2790 else
2791 reason = TASK_SWITCH_CALL;
2792
2793 if (reason == TASK_SWITCH_GATE) {
2794 switch (type) {
2795 case SVM_EXITINTINFO_TYPE_NMI:
2796 svm->vcpu.arch.nmi_injected = false;
2797 break;
2798 case SVM_EXITINTINFO_TYPE_EXEPT:
2799 if (svm->vmcb->control.exit_info_2 &
2800 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2801 has_error_code = true;
2802 error_code =
2803 (u32)svm->vmcb->control.exit_info_2;
2804 }
2805 kvm_clear_exception_queue(&svm->vcpu);
2806 break;
2807 case SVM_EXITINTINFO_TYPE_INTR:
2808 kvm_clear_interrupt_queue(&svm->vcpu);
2809 break;
2810 default:
2811 break;
2812 }
2813 }
2814
2815 if (reason != TASK_SWITCH_GATE ||
2816 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2817 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2818 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2819 skip_emulated_instruction(&svm->vcpu);
2820
2821 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2822 int_vec = -1;
2823
2824 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2825 has_error_code, error_code) == EMULATE_FAIL) {
2826 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2827 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2828 svm->vcpu.run->internal.ndata = 0;
2829 return 0;
2830 }
2831 return 1;
2832 }
2833
2834 static int cpuid_interception(struct vcpu_svm *svm)
2835 {
2836 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2837 kvm_emulate_cpuid(&svm->vcpu);
2838 return 1;
2839 }
2840
2841 static int iret_interception(struct vcpu_svm *svm)
2842 {
2843 ++svm->vcpu.stat.nmi_window_exits;
2844 clr_intercept(svm, INTERCEPT_IRET);
2845 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2846 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2847 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2848 return 1;
2849 }
2850
2851 static int invlpg_interception(struct vcpu_svm *svm)
2852 {
2853 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2854 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2855
2856 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2857 skip_emulated_instruction(&svm->vcpu);
2858 return 1;
2859 }
2860
2861 static int emulate_on_interception(struct vcpu_svm *svm)
2862 {
2863 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2864 }
2865
2866 static int rdpmc_interception(struct vcpu_svm *svm)
2867 {
2868 int err;
2869
2870 if (!static_cpu_has(X86_FEATURE_NRIPS))
2871 return emulate_on_interception(svm);
2872
2873 err = kvm_rdpmc(&svm->vcpu);
2874 kvm_complete_insn_gp(&svm->vcpu, err);
2875
2876 return 1;
2877 }
2878
2879 bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
2880 {
2881 unsigned long cr0 = svm->vcpu.arch.cr0;
2882 bool ret = false;
2883 u64 intercept;
2884
2885 intercept = svm->nested.intercept;
2886
2887 if (!is_guest_mode(&svm->vcpu) ||
2888 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2889 return false;
2890
2891 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2892 val &= ~SVM_CR0_SELECTIVE_MASK;
2893
2894 if (cr0 ^ val) {
2895 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2896 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2897 }
2898
2899 return ret;
2900 }
2901
2902 #define CR_VALID (1ULL << 63)
2903
2904 static int cr_interception(struct vcpu_svm *svm)
2905 {
2906 int reg, cr;
2907 unsigned long val;
2908 int err;
2909
2910 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2911 return emulate_on_interception(svm);
2912
2913 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2914 return emulate_on_interception(svm);
2915
2916 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2917 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2918
2919 err = 0;
2920 if (cr >= 16) { /* mov to cr */
2921 cr -= 16;
2922 val = kvm_register_read(&svm->vcpu, reg);
2923 switch (cr) {
2924 case 0:
2925 if (!check_selective_cr0_intercepted(svm, val))
2926 err = kvm_set_cr0(&svm->vcpu, val);
2927 else
2928 return 1;
2929
2930 break;
2931 case 3:
2932 err = kvm_set_cr3(&svm->vcpu, val);
2933 break;
2934 case 4:
2935 err = kvm_set_cr4(&svm->vcpu, val);
2936 break;
2937 case 8:
2938 err = kvm_set_cr8(&svm->vcpu, val);
2939 break;
2940 default:
2941 WARN(1, "unhandled write to CR%d", cr);
2942 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2943 return 1;
2944 }
2945 } else { /* mov from cr */
2946 switch (cr) {
2947 case 0:
2948 val = kvm_read_cr0(&svm->vcpu);
2949 break;
2950 case 2:
2951 val = svm->vcpu.arch.cr2;
2952 break;
2953 case 3:
2954 val = kvm_read_cr3(&svm->vcpu);
2955 break;
2956 case 4:
2957 val = kvm_read_cr4(&svm->vcpu);
2958 break;
2959 case 8:
2960 val = kvm_get_cr8(&svm->vcpu);
2961 break;
2962 default:
2963 WARN(1, "unhandled read from CR%d", cr);
2964 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2965 return 1;
2966 }
2967 kvm_register_write(&svm->vcpu, reg, val);
2968 }
2969 kvm_complete_insn_gp(&svm->vcpu, err);
2970
2971 return 1;
2972 }
2973
2974 static int dr_interception(struct vcpu_svm *svm)
2975 {
2976 int reg, dr;
2977 unsigned long val;
2978 int err;
2979
2980 if (svm->vcpu.guest_debug == 0) {
2981 /*
2982 * No more DR vmexits; force a reload of the debug registers
2983 * and reenter on this instruction. The next vmexit will
2984 * retrieve the full state of the debug registers.
2985 */
2986 clr_dr_intercepts(svm);
2987 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2988 return 1;
2989 }
2990
2991 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2992 return emulate_on_interception(svm);
2993
2994 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2995 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2996
2997 if (dr >= 16) { /* mov to DRn */
2998 val = kvm_register_read(&svm->vcpu, reg);
2999 kvm_set_dr(&svm->vcpu, dr - 16, val);
3000 } else {
3001 err = kvm_get_dr(&svm->vcpu, dr, &val);
3002 if (!err)
3003 kvm_register_write(&svm->vcpu, reg, val);
3004 }
3005
3006 skip_emulated_instruction(&svm->vcpu);
3007
3008 return 1;
3009 }
3010
3011 static int cr8_write_interception(struct vcpu_svm *svm)
3012 {
3013 struct kvm_run *kvm_run = svm->vcpu.run;
3014 int r;
3015
3016 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3017 /* instruction emulation calls kvm_set_cr8() */
3018 r = cr_interception(svm);
3019 if (irqchip_in_kernel(svm->vcpu.kvm))
3020 return r;
3021 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3022 return r;
3023 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3024 return 0;
3025 }
3026
3027 u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
3028 {
3029 struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
3030 return vmcb->control.tsc_offset +
3031 svm_scale_tsc(vcpu, host_tsc);
3032 }
3033
3034 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
3035 {
3036 struct vcpu_svm *svm = to_svm(vcpu);
3037
3038 switch (ecx) {
3039 case MSR_IA32_TSC: {
3040 *data = svm->vmcb->control.tsc_offset +
3041 svm_scale_tsc(vcpu, native_read_tsc());
3042
3043 break;
3044 }
3045 case MSR_STAR:
3046 *data = svm->vmcb->save.star;
3047 break;
3048 #ifdef CONFIG_X86_64
3049 case MSR_LSTAR:
3050 *data = svm->vmcb->save.lstar;
3051 break;
3052 case MSR_CSTAR:
3053 *data = svm->vmcb->save.cstar;
3054 break;
3055 case MSR_KERNEL_GS_BASE:
3056 *data = svm->vmcb->save.kernel_gs_base;
3057 break;
3058 case MSR_SYSCALL_MASK:
3059 *data = svm->vmcb->save.sfmask;
3060 break;
3061 #endif
3062 case MSR_IA32_SYSENTER_CS:
3063 *data = svm->vmcb->save.sysenter_cs;
3064 break;
3065 case MSR_IA32_SYSENTER_EIP:
3066 *data = svm->sysenter_eip;
3067 break;
3068 case MSR_IA32_SYSENTER_ESP:
3069 *data = svm->sysenter_esp;
3070 break;
3071 /*
3072 * Nobody will change the following 5 values in the VMCB so we can
3073 * safely return them on rdmsr. They will always be 0 until LBRV is
3074 * implemented.
3075 */
3076 case MSR_IA32_DEBUGCTLMSR:
3077 *data = svm->vmcb->save.dbgctl;
3078 break;
3079 case MSR_IA32_LASTBRANCHFROMIP:
3080 *data = svm->vmcb->save.br_from;
3081 break;
3082 case MSR_IA32_LASTBRANCHTOIP:
3083 *data = svm->vmcb->save.br_to;
3084 break;
3085 case MSR_IA32_LASTINTFROMIP:
3086 *data = svm->vmcb->save.last_excp_from;
3087 break;
3088 case MSR_IA32_LASTINTTOIP:
3089 *data = svm->vmcb->save.last_excp_to;
3090 break;
3091 case MSR_VM_HSAVE_PA:
3092 *data = svm->nested.hsave_msr;
3093 break;
3094 case MSR_VM_CR:
3095 *data = svm->nested.vm_cr_msr;
3096 break;
3097 case MSR_IA32_UCODE_REV:
3098 *data = 0x01000065;
3099 break;
3100 default:
3101 return kvm_get_msr_common(vcpu, ecx, data);
3102 }
3103 return 0;
3104 }
3105
3106 static int rdmsr_interception(struct vcpu_svm *svm)
3107 {
3108 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3109 u64 data;
3110
3111 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
3112 trace_kvm_msr_read_ex(ecx);
3113 kvm_inject_gp(&svm->vcpu, 0);
3114 } else {
3115 trace_kvm_msr_read(ecx, data);
3116
3117 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
3118 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
3119 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3120 skip_emulated_instruction(&svm->vcpu);
3121 }
3122 return 1;
3123 }
3124
3125 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3126 {
3127 struct vcpu_svm *svm = to_svm(vcpu);
3128 int svm_dis, chg_mask;
3129
3130 if (data & ~SVM_VM_CR_VALID_MASK)
3131 return 1;
3132
3133 chg_mask = SVM_VM_CR_VALID_MASK;
3134
3135 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3136 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3137
3138 svm->nested.vm_cr_msr &= ~chg_mask;
3139 svm->nested.vm_cr_msr |= (data & chg_mask);
3140
3141 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3142
3143 /* check for svm_disable while efer.svme is set */
3144 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3145 return 1;
3146
3147 return 0;
3148 }
3149
3150 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3151 {
3152 struct vcpu_svm *svm = to_svm(vcpu);
3153
3154 u32 ecx = msr->index;
3155 u64 data = msr->data;
3156 switch (ecx) {
3157 case MSR_IA32_TSC:
3158 kvm_write_tsc(vcpu, msr);
3159 break;
3160 case MSR_STAR:
3161 svm->vmcb->save.star = data;
3162 break;
3163 #ifdef CONFIG_X86_64
3164 case MSR_LSTAR:
3165 svm->vmcb->save.lstar = data;
3166 break;
3167 case MSR_CSTAR:
3168 svm->vmcb->save.cstar = data;
3169 break;
3170 case MSR_KERNEL_GS_BASE:
3171 svm->vmcb->save.kernel_gs_base = data;
3172 break;
3173 case MSR_SYSCALL_MASK:
3174 svm->vmcb->save.sfmask = data;
3175 break;
3176 #endif
3177 case MSR_IA32_SYSENTER_CS:
3178 svm->vmcb->save.sysenter_cs = data;
3179 break;
3180 case MSR_IA32_SYSENTER_EIP:
3181 svm->sysenter_eip = data;
3182 svm->vmcb->save.sysenter_eip = data;
3183 break;
3184 case MSR_IA32_SYSENTER_ESP:
3185 svm->sysenter_esp = data;
3186 svm->vmcb->save.sysenter_esp = data;
3187 break;
3188 case MSR_IA32_DEBUGCTLMSR:
3189 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3190 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3191 __func__, data);
3192 break;
3193 }
3194 if (data & DEBUGCTL_RESERVED_BITS)
3195 return 1;
3196
3197 svm->vmcb->save.dbgctl = data;
3198 mark_dirty(svm->vmcb, VMCB_LBR);
3199 if (data & (1ULL<<0))
3200 svm_enable_lbrv(svm);
3201 else
3202 svm_disable_lbrv(svm);
3203 break;
3204 case MSR_VM_HSAVE_PA:
3205 svm->nested.hsave_msr = data;
3206 break;
3207 case MSR_VM_CR:
3208 return svm_set_vm_cr(vcpu, data);
3209 case MSR_VM_IGNNE:
3210 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3211 break;
3212 default:
3213 return kvm_set_msr_common(vcpu, msr);
3214 }
3215 return 0;
3216 }
3217
3218 static int wrmsr_interception(struct vcpu_svm *svm)
3219 {
3220 struct msr_data msr;
3221 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
3222 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
3223 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3224
3225 msr.data = data;
3226 msr.index = ecx;
3227 msr.host_initiated = false;
3228
3229 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3230 if (svm_set_msr(&svm->vcpu, &msr)) {
3231 trace_kvm_msr_write_ex(ecx, data);
3232 kvm_inject_gp(&svm->vcpu, 0);
3233 } else {
3234 trace_kvm_msr_write(ecx, data);
3235 skip_emulated_instruction(&svm->vcpu);
3236 }
3237 return 1;
3238 }
3239
3240 static int msr_interception(struct vcpu_svm *svm)
3241 {
3242 if (svm->vmcb->control.exit_info_1)
3243 return wrmsr_interception(svm);
3244 else
3245 return rdmsr_interception(svm);
3246 }
3247
3248 static int interrupt_window_interception(struct vcpu_svm *svm)
3249 {
3250 struct kvm_run *kvm_run = svm->vcpu.run;
3251
3252 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3253 svm_clear_vintr(svm);
3254 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3255 mark_dirty(svm->vmcb, VMCB_INTR);
3256 ++svm->vcpu.stat.irq_window_exits;
3257 /*
3258 * If the user space waits to inject interrupts, exit as soon as
3259 * possible
3260 */
3261 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3262 kvm_run->request_interrupt_window &&
3263 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3264 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3265 return 0;
3266 }
3267
3268 return 1;
3269 }
3270
3271 static int pause_interception(struct vcpu_svm *svm)
3272 {
3273 kvm_vcpu_on_spin(&(svm->vcpu));
3274 return 1;
3275 }
3276
3277 static int nop_interception(struct vcpu_svm *svm)
3278 {
3279 skip_emulated_instruction(&(svm->vcpu));
3280 return 1;
3281 }
3282
3283 static int monitor_interception(struct vcpu_svm *svm)
3284 {
3285 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3286 return nop_interception(svm);
3287 }
3288
3289 static int mwait_interception(struct vcpu_svm *svm)
3290 {
3291 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3292 return nop_interception(svm);
3293 }
3294
3295 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3296 [SVM_EXIT_READ_CR0] = cr_interception,
3297 [SVM_EXIT_READ_CR3] = cr_interception,
3298 [SVM_EXIT_READ_CR4] = cr_interception,
3299 [SVM_EXIT_READ_CR8] = cr_interception,
3300 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3301 [SVM_EXIT_WRITE_CR0] = cr_interception,
3302 [SVM_EXIT_WRITE_CR3] = cr_interception,
3303 [SVM_EXIT_WRITE_CR4] = cr_interception,
3304 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3305 [SVM_EXIT_READ_DR0] = dr_interception,
3306 [SVM_EXIT_READ_DR1] = dr_interception,
3307 [SVM_EXIT_READ_DR2] = dr_interception,
3308 [SVM_EXIT_READ_DR3] = dr_interception,
3309 [SVM_EXIT_READ_DR4] = dr_interception,
3310 [SVM_EXIT_READ_DR5] = dr_interception,
3311 [SVM_EXIT_READ_DR6] = dr_interception,
3312 [SVM_EXIT_READ_DR7] = dr_interception,
3313 [SVM_EXIT_WRITE_DR0] = dr_interception,
3314 [SVM_EXIT_WRITE_DR1] = dr_interception,
3315 [SVM_EXIT_WRITE_DR2] = dr_interception,
3316 [SVM_EXIT_WRITE_DR3] = dr_interception,
3317 [SVM_EXIT_WRITE_DR4] = dr_interception,
3318 [SVM_EXIT_WRITE_DR5] = dr_interception,
3319 [SVM_EXIT_WRITE_DR6] = dr_interception,
3320 [SVM_EXIT_WRITE_DR7] = dr_interception,
3321 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3322 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3323 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3324 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3325 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3326 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3327 [SVM_EXIT_INTR] = intr_interception,
3328 [SVM_EXIT_NMI] = nmi_interception,
3329 [SVM_EXIT_SMI] = nop_on_interception,
3330 [SVM_EXIT_INIT] = nop_on_interception,
3331 [SVM_EXIT_VINTR] = interrupt_window_interception,
3332 [SVM_EXIT_RDPMC] = rdpmc_interception,
3333 [SVM_EXIT_CPUID] = cpuid_interception,
3334 [SVM_EXIT_IRET] = iret_interception,
3335 [SVM_EXIT_INVD] = emulate_on_interception,
3336 [SVM_EXIT_PAUSE] = pause_interception,
3337 [SVM_EXIT_HLT] = halt_interception,
3338 [SVM_EXIT_INVLPG] = invlpg_interception,
3339 [SVM_EXIT_INVLPGA] = invlpga_interception,
3340 [SVM_EXIT_IOIO] = io_interception,
3341 [SVM_EXIT_MSR] = msr_interception,
3342 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3343 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3344 [SVM_EXIT_VMRUN] = vmrun_interception,
3345 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3346 [SVM_EXIT_VMLOAD] = vmload_interception,
3347 [SVM_EXIT_VMSAVE] = vmsave_interception,
3348 [SVM_EXIT_STGI] = stgi_interception,
3349 [SVM_EXIT_CLGI] = clgi_interception,
3350 [SVM_EXIT_SKINIT] = skinit_interception,
3351 [SVM_EXIT_WBINVD] = emulate_on_interception,
3352 [SVM_EXIT_MONITOR] = monitor_interception,
3353 [SVM_EXIT_MWAIT] = mwait_interception,
3354 [SVM_EXIT_XSETBV] = xsetbv_interception,
3355 [SVM_EXIT_NPF] = pf_interception,
3356 };
3357
3358 static void dump_vmcb(struct kvm_vcpu *vcpu)
3359 {
3360 struct vcpu_svm *svm = to_svm(vcpu);
3361 struct vmcb_control_area *control = &svm->vmcb->control;
3362 struct vmcb_save_area *save = &svm->vmcb->save;
3363
3364 pr_err("VMCB Control Area:\n");
3365 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
3366 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
3367 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
3368 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
3369 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
3370 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
3371 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3372 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3373 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3374 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3375 pr_err("%-20s%d\n", "asid:", control->asid);
3376 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3377 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3378 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3379 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3380 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3381 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3382 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3383 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3384 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3385 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3386 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3387 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3388 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3389 pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
3390 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3391 pr_err("VMCB State Save Area:\n");
3392 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3393 "es:",
3394 save->es.selector, save->es.attrib,
3395 save->es.limit, save->es.base);
3396 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3397 "cs:",
3398 save->cs.selector, save->cs.attrib,
3399 save->cs.limit, save->cs.base);
3400 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3401 "ss:",
3402 save->ss.selector, save->ss.attrib,
3403 save->ss.limit, save->ss.base);
3404 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3405 "ds:",
3406 save->ds.selector, save->ds.attrib,
3407 save->ds.limit, save->ds.base);
3408 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3409 "fs:",
3410 save->fs.selector, save->fs.attrib,
3411 save->fs.limit, save->fs.base);
3412 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3413 "gs:",
3414 save->gs.selector, save->gs.attrib,
3415 save->gs.limit, save->gs.base);
3416 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3417 "gdtr:",
3418 save->gdtr.selector, save->gdtr.attrib,
3419 save->gdtr.limit, save->gdtr.base);
3420 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3421 "ldtr:",
3422 save->ldtr.selector, save->ldtr.attrib,
3423 save->ldtr.limit, save->ldtr.base);
3424 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3425 "idtr:",
3426 save->idtr.selector, save->idtr.attrib,
3427 save->idtr.limit, save->idtr.base);
3428 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3429 "tr:",
3430 save->tr.selector, save->tr.attrib,
3431 save->tr.limit, save->tr.base);
3432 pr_err("cpl: %d efer: %016llx\n",
3433 save->cpl, save->efer);
3434 pr_err("%-15s %016llx %-13s %016llx\n",
3435 "cr0:", save->cr0, "cr2:", save->cr2);
3436 pr_err("%-15s %016llx %-13s %016llx\n",
3437 "cr3:", save->cr3, "cr4:", save->cr4);
3438 pr_err("%-15s %016llx %-13s %016llx\n",
3439 "dr6:", save->dr6, "dr7:", save->dr7);
3440 pr_err("%-15s %016llx %-13s %016llx\n",
3441 "rip:", save->rip, "rflags:", save->rflags);
3442 pr_err("%-15s %016llx %-13s %016llx\n",
3443 "rsp:", save->rsp, "rax:", save->rax);
3444 pr_err("%-15s %016llx %-13s %016llx\n",
3445 "star:", save->star, "lstar:", save->lstar);
3446 pr_err("%-15s %016llx %-13s %016llx\n",
3447 "cstar:", save->cstar, "sfmask:", save->sfmask);
3448 pr_err("%-15s %016llx %-13s %016llx\n",
3449 "kernel_gs_base:", save->kernel_gs_base,
3450 "sysenter_cs:", save->sysenter_cs);
3451 pr_err("%-15s %016llx %-13s %016llx\n",
3452 "sysenter_esp:", save->sysenter_esp,
3453 "sysenter_eip:", save->sysenter_eip);
3454 pr_err("%-15s %016llx %-13s %016llx\n",
3455 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3456 pr_err("%-15s %016llx %-13s %016llx\n",
3457 "br_from:", save->br_from, "br_to:", save->br_to);
3458 pr_err("%-15s %016llx %-13s %016llx\n",
3459 "excp_from:", save->last_excp_from,
3460 "excp_to:", save->last_excp_to);
3461 }
3462
3463 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3464 {
3465 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3466
3467 *info1 = control->exit_info_1;
3468 *info2 = control->exit_info_2;
3469 }
3470
3471 static int handle_exit(struct kvm_vcpu *vcpu)
3472 {
3473 struct vcpu_svm *svm = to_svm(vcpu);
3474 struct kvm_run *kvm_run = vcpu->run;
3475 u32 exit_code = svm->vmcb->control.exit_code;
3476
3477 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3478 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3479 if (npt_enabled)
3480 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3481
3482 if (unlikely(svm->nested.exit_required)) {
3483 nested_svm_vmexit(svm);
3484 svm->nested.exit_required = false;
3485
3486 return 1;
3487 }
3488
3489 if (is_guest_mode(vcpu)) {
3490 int vmexit;
3491
3492 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3493 svm->vmcb->control.exit_info_1,
3494 svm->vmcb->control.exit_info_2,
3495 svm->vmcb->control.exit_int_info,
3496 svm->vmcb->control.exit_int_info_err,
3497 KVM_ISA_SVM);
3498
3499 vmexit = nested_svm_exit_special(svm);
3500
3501 if (vmexit == NESTED_EXIT_CONTINUE)
3502 vmexit = nested_svm_exit_handled(svm);
3503
3504 if (vmexit == NESTED_EXIT_DONE)
3505 return 1;
3506 }
3507
3508 svm_complete_interrupts(svm);
3509
3510 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3511 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3512 kvm_run->fail_entry.hardware_entry_failure_reason
3513 = svm->vmcb->control.exit_code;
3514 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3515 dump_vmcb(vcpu);
3516 return 0;
3517 }
3518
3519 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3520 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3521 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3522 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3523 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3524 "exit_code 0x%x\n",
3525 __func__, svm->vmcb->control.exit_int_info,
3526 exit_code);
3527
3528 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3529 || !svm_exit_handlers[exit_code]) {
3530 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3531 kvm_run->hw.hardware_exit_reason = exit_code;
3532 return 0;
3533 }
3534
3535 return svm_exit_handlers[exit_code](svm);
3536 }
3537
3538 static void reload_tss(struct kvm_vcpu *vcpu)
3539 {
3540 int cpu = raw_smp_processor_id();
3541
3542 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3543 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3544 load_TR_desc();
3545 }
3546
3547 static void pre_svm_run(struct vcpu_svm *svm)
3548 {
3549 int cpu = raw_smp_processor_id();
3550
3551 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3552
3553 /* FIXME: handle wraparound of asid_generation */
3554 if (svm->asid_generation != sd->asid_generation)
3555 new_asid(svm, sd);
3556 }
3557
3558 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3559 {
3560 struct vcpu_svm *svm = to_svm(vcpu);
3561
3562 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3563 vcpu->arch.hflags |= HF_NMI_MASK;
3564 set_intercept(svm, INTERCEPT_IRET);
3565 ++vcpu->stat.nmi_injections;
3566 }
3567
3568 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3569 {
3570 struct vmcb_control_area *control;
3571
3572 control = &svm->vmcb->control;
3573 control->int_vector = irq;
3574 control->int_ctl &= ~V_INTR_PRIO_MASK;
3575 control->int_ctl |= V_IRQ_MASK |
3576 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3577 mark_dirty(svm->vmcb, VMCB_INTR);
3578 }
3579
3580 static void svm_set_irq(struct kvm_vcpu *vcpu)
3581 {
3582 struct vcpu_svm *svm = to_svm(vcpu);
3583
3584 BUG_ON(!(gif_set(svm)));
3585
3586 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3587 ++vcpu->stat.irq_injections;
3588
3589 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3590 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3591 }
3592
3593 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3594 {
3595 struct vcpu_svm *svm = to_svm(vcpu);
3596
3597 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3598 return;
3599
3600 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3601
3602 if (irr == -1)
3603 return;
3604
3605 if (tpr >= irr)
3606 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3607 }
3608
3609 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
3610 {
3611 return;
3612 }
3613
3614 static int svm_vm_has_apicv(struct kvm *kvm)
3615 {
3616 return 0;
3617 }
3618
3619 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
3620 {
3621 return;
3622 }
3623
3624 static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
3625 {
3626 return;
3627 }
3628
3629 static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
3630 {
3631 return;
3632 }
3633
3634 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3635 {
3636 struct vcpu_svm *svm = to_svm(vcpu);
3637 struct vmcb *vmcb = svm->vmcb;
3638 int ret;
3639 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3640 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3641 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3642
3643 return ret;
3644 }
3645
3646 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3647 {
3648 struct vcpu_svm *svm = to_svm(vcpu);
3649
3650 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3651 }
3652
3653 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3654 {
3655 struct vcpu_svm *svm = to_svm(vcpu);
3656
3657 if (masked) {
3658 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3659 set_intercept(svm, INTERCEPT_IRET);
3660 } else {
3661 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3662 clr_intercept(svm, INTERCEPT_IRET);
3663 }
3664 }
3665
3666 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3667 {
3668 struct vcpu_svm *svm = to_svm(vcpu);
3669 struct vmcb *vmcb = svm->vmcb;
3670 int ret;
3671
3672 if (!gif_set(svm) ||
3673 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3674 return 0;
3675
3676 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3677
3678 if (is_guest_mode(vcpu))
3679 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3680
3681 return ret;
3682 }
3683
3684 static void enable_irq_window(struct kvm_vcpu *vcpu)
3685 {
3686 struct vcpu_svm *svm = to_svm(vcpu);
3687
3688 /*
3689 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3690 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3691 * get that intercept, this function will be called again though and
3692 * we'll get the vintr intercept.
3693 */
3694 if (gif_set(svm) && nested_svm_intr(svm)) {
3695 svm_set_vintr(svm);
3696 svm_inject_irq(svm, 0x0);
3697 }
3698 }
3699
3700 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3701 {
3702 struct vcpu_svm *svm = to_svm(vcpu);
3703
3704 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3705 == HF_NMI_MASK)
3706 return; /* IRET will cause a vm exit */
3707
3708 /*
3709 * Something prevents NMI from been injected. Single step over possible
3710 * problem (IRET or exception injection or interrupt shadow)
3711 */
3712 svm->nmi_singlestep = true;
3713 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3714 update_db_bp_intercept(vcpu);
3715 }
3716
3717 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3718 {
3719 return 0;
3720 }
3721
3722 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3723 {
3724 struct vcpu_svm *svm = to_svm(vcpu);
3725
3726 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3727 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3728 else
3729 svm->asid_generation--;
3730 }
3731
3732 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3733 {
3734 }
3735
3736 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3737 {
3738 struct vcpu_svm *svm = to_svm(vcpu);
3739
3740 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3741 return;
3742
3743 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3744 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3745 kvm_set_cr8(vcpu, cr8);
3746 }
3747 }
3748
3749 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3750 {
3751 struct vcpu_svm *svm = to_svm(vcpu);
3752 u64 cr8;
3753
3754 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3755 return;
3756
3757 cr8 = kvm_get_cr8(vcpu);
3758 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3759 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3760 }
3761
3762 static void svm_complete_interrupts(struct vcpu_svm *svm)
3763 {
3764 u8 vector;
3765 int type;
3766 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3767 unsigned int3_injected = svm->int3_injected;
3768
3769 svm->int3_injected = 0;
3770
3771 /*
3772 * If we've made progress since setting HF_IRET_MASK, we've
3773 * executed an IRET and can allow NMI injection.
3774 */
3775 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3776 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3777 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3778 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3779 }
3780
3781 svm->vcpu.arch.nmi_injected = false;
3782 kvm_clear_exception_queue(&svm->vcpu);
3783 kvm_clear_interrupt_queue(&svm->vcpu);
3784
3785 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3786 return;
3787
3788 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3789
3790 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3791 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3792
3793 switch (type) {
3794 case SVM_EXITINTINFO_TYPE_NMI:
3795 svm->vcpu.arch.nmi_injected = true;
3796 break;
3797 case SVM_EXITINTINFO_TYPE_EXEPT:
3798 /*
3799 * In case of software exceptions, do not reinject the vector,
3800 * but re-execute the instruction instead. Rewind RIP first
3801 * if we emulated INT3 before.
3802 */
3803 if (kvm_exception_is_soft(vector)) {
3804 if (vector == BP_VECTOR && int3_injected &&
3805 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3806 kvm_rip_write(&svm->vcpu,
3807 kvm_rip_read(&svm->vcpu) -
3808 int3_injected);
3809 break;
3810 }
3811 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3812 u32 err = svm->vmcb->control.exit_int_info_err;
3813 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3814
3815 } else
3816 kvm_requeue_exception(&svm->vcpu, vector);
3817 break;
3818 case SVM_EXITINTINFO_TYPE_INTR:
3819 kvm_queue_interrupt(&svm->vcpu, vector, false);
3820 break;
3821 default:
3822 break;
3823 }
3824 }
3825
3826 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3827 {
3828 struct vcpu_svm *svm = to_svm(vcpu);
3829 struct vmcb_control_area *control = &svm->vmcb->control;
3830
3831 control->exit_int_info = control->event_inj;
3832 control->exit_int_info_err = control->event_inj_err;
3833 control->event_inj = 0;
3834 svm_complete_interrupts(svm);
3835 }
3836
3837 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3838 {
3839 struct vcpu_svm *svm = to_svm(vcpu);
3840
3841 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3842 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3843 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3844
3845 /*
3846 * A vmexit emulation is required before the vcpu can be executed
3847 * again.
3848 */
3849 if (unlikely(svm->nested.exit_required))
3850 return;
3851
3852 pre_svm_run(svm);
3853
3854 sync_lapic_to_cr8(vcpu);
3855
3856 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3857
3858 clgi();
3859
3860 local_irq_enable();
3861
3862 asm volatile (
3863 "push %%" _ASM_BP "; \n\t"
3864 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
3865 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
3866 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
3867 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
3868 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
3869 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
3870 #ifdef CONFIG_X86_64
3871 "mov %c[r8](%[svm]), %%r8 \n\t"
3872 "mov %c[r9](%[svm]), %%r9 \n\t"
3873 "mov %c[r10](%[svm]), %%r10 \n\t"
3874 "mov %c[r11](%[svm]), %%r11 \n\t"
3875 "mov %c[r12](%[svm]), %%r12 \n\t"
3876 "mov %c[r13](%[svm]), %%r13 \n\t"
3877 "mov %c[r14](%[svm]), %%r14 \n\t"
3878 "mov %c[r15](%[svm]), %%r15 \n\t"
3879 #endif
3880
3881 /* Enter guest mode */
3882 "push %%" _ASM_AX " \n\t"
3883 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
3884 __ex(SVM_VMLOAD) "\n\t"
3885 __ex(SVM_VMRUN) "\n\t"
3886 __ex(SVM_VMSAVE) "\n\t"
3887 "pop %%" _ASM_AX " \n\t"
3888
3889 /* Save guest registers, load host registers */
3890 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
3891 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
3892 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
3893 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
3894 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
3895 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
3896 #ifdef CONFIG_X86_64
3897 "mov %%r8, %c[r8](%[svm]) \n\t"
3898 "mov %%r9, %c[r9](%[svm]) \n\t"
3899 "mov %%r10, %c[r10](%[svm]) \n\t"
3900 "mov %%r11, %c[r11](%[svm]) \n\t"
3901 "mov %%r12, %c[r12](%[svm]) \n\t"
3902 "mov %%r13, %c[r13](%[svm]) \n\t"
3903 "mov %%r14, %c[r14](%[svm]) \n\t"
3904 "mov %%r15, %c[r15](%[svm]) \n\t"
3905 #endif
3906 "pop %%" _ASM_BP
3907 :
3908 : [svm]"a"(svm),
3909 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3910 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3911 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3912 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3913 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3914 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3915 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3916 #ifdef CONFIG_X86_64
3917 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3918 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3919 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3920 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3921 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3922 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3923 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3924 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3925 #endif
3926 : "cc", "memory"
3927 #ifdef CONFIG_X86_64
3928 , "rbx", "rcx", "rdx", "rsi", "rdi"
3929 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3930 #else
3931 , "ebx", "ecx", "edx", "esi", "edi"
3932 #endif
3933 );
3934
3935 #ifdef CONFIG_X86_64
3936 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3937 #else
3938 loadsegment(fs, svm->host.fs);
3939 #ifndef CONFIG_X86_32_LAZY_GS
3940 loadsegment(gs, svm->host.gs);
3941 #endif
3942 #endif
3943
3944 reload_tss(vcpu);
3945
3946 local_irq_disable();
3947
3948 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3949 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3950 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3951 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3952
3953 trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
3954
3955 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3956 kvm_before_handle_nmi(&svm->vcpu);
3957
3958 stgi();
3959
3960 /* Any pending NMI will happen here */
3961
3962 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3963 kvm_after_handle_nmi(&svm->vcpu);
3964
3965 sync_cr8_to_lapic(vcpu);
3966
3967 svm->next_rip = 0;
3968
3969 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3970
3971 /* if exit due to PF check for async PF */
3972 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3973 svm->apf_reason = kvm_read_and_reset_pf_reason();
3974
3975 if (npt_enabled) {
3976 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3977 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3978 }
3979
3980 /*
3981 * We need to handle MC intercepts here before the vcpu has a chance to
3982 * change the physical cpu
3983 */
3984 if (unlikely(svm->vmcb->control.exit_code ==
3985 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3986 svm_handle_mce(svm);
3987
3988 mark_all_clean(svm->vmcb);
3989 }
3990
3991 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3992 {
3993 struct vcpu_svm *svm = to_svm(vcpu);
3994
3995 svm->vmcb->save.cr3 = root;
3996 mark_dirty(svm->vmcb, VMCB_CR);
3997 svm_flush_tlb(vcpu);
3998 }
3999
4000 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
4001 {
4002 struct vcpu_svm *svm = to_svm(vcpu);
4003
4004 svm->vmcb->control.nested_cr3 = root;
4005 mark_dirty(svm->vmcb, VMCB_NPT);
4006
4007 /* Also sync guest cr3 here in case we live migrate */
4008 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
4009 mark_dirty(svm->vmcb, VMCB_CR);
4010
4011 svm_flush_tlb(vcpu);
4012 }
4013
4014 static int is_disabled(void)
4015 {
4016 u64 vm_cr;
4017
4018 rdmsrl(MSR_VM_CR, vm_cr);
4019 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4020 return 1;
4021
4022 return 0;
4023 }
4024
4025 static void
4026 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4027 {
4028 /*
4029 * Patch in the VMMCALL instruction:
4030 */
4031 hypercall[0] = 0x0f;
4032 hypercall[1] = 0x01;
4033 hypercall[2] = 0xd9;
4034 }
4035
4036 static void svm_check_processor_compat(void *rtn)
4037 {
4038 *(int *)rtn = 0;
4039 }
4040
4041 static bool svm_cpu_has_accelerated_tpr(void)
4042 {
4043 return false;
4044 }
4045
4046 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4047 {
4048 return 0;
4049 }
4050
4051 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
4052 {
4053 }
4054
4055 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4056 {
4057 switch (func) {
4058 case 0x80000001:
4059 if (nested)
4060 entry->ecx |= (1 << 2); /* Set SVM bit */
4061 break;
4062 case 0x8000000A:
4063 entry->eax = 1; /* SVM revision 1 */
4064 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
4065 ASID emulation to nested SVM */
4066 entry->ecx = 0; /* Reserved */
4067 entry->edx = 0; /* Per default do not support any
4068 additional features */
4069
4070 /* Support next_rip if host supports it */
4071 if (boot_cpu_has(X86_FEATURE_NRIPS))
4072 entry->edx |= SVM_FEATURE_NRIP;
4073
4074 /* Support NPT for the guest if enabled */
4075 if (npt_enabled)
4076 entry->edx |= SVM_FEATURE_NPT;
4077
4078 break;
4079 }
4080 }
4081
4082 static int svm_get_lpage_level(void)
4083 {
4084 return PT_PDPE_LEVEL;
4085 }
4086
4087 static bool svm_rdtscp_supported(void)
4088 {
4089 return false;
4090 }
4091
4092 static bool svm_invpcid_supported(void)
4093 {
4094 return false;
4095 }
4096
4097 static bool svm_mpx_supported(void)
4098 {
4099 return false;
4100 }
4101
4102 static bool svm_has_wbinvd_exit(void)
4103 {
4104 return true;
4105 }
4106
4107 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
4108 {
4109 struct vcpu_svm *svm = to_svm(vcpu);
4110
4111 set_exception_intercept(svm, NM_VECTOR);
4112 update_cr0_intercept(svm);
4113 }
4114
4115 #define PRE_EX(exit) { .exit_code = (exit), \
4116 .stage = X86_ICPT_PRE_EXCEPT, }
4117 #define POST_EX(exit) { .exit_code = (exit), \
4118 .stage = X86_ICPT_POST_EXCEPT, }
4119 #define POST_MEM(exit) { .exit_code = (exit), \
4120 .stage = X86_ICPT_POST_MEMACCESS, }
4121
4122 static const struct __x86_intercept {
4123 u32 exit_code;
4124 enum x86_intercept_stage stage;
4125 } x86_intercept_map[] = {
4126 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4127 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4128 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4129 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4130 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4131 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4132 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4133 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4134 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4135 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4136 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4137 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4138 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4139 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4140 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4141 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4142 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4143 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4144 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4145 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4146 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4147 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4148 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4149 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4150 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4151 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4152 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4153 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4154 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4155 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4156 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4157 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4158 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4159 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4160 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4161 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4162 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4163 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4164 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4165 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4166 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4167 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4168 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4169 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4170 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4171 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4172 };
4173
4174 #undef PRE_EX
4175 #undef POST_EX
4176 #undef POST_MEM
4177
4178 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4179 struct x86_instruction_info *info,
4180 enum x86_intercept_stage stage)
4181 {
4182 struct vcpu_svm *svm = to_svm(vcpu);
4183 int vmexit, ret = X86EMUL_CONTINUE;
4184 struct __x86_intercept icpt_info;
4185 struct vmcb *vmcb = svm->vmcb;
4186
4187 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4188 goto out;
4189
4190 icpt_info = x86_intercept_map[info->intercept];
4191
4192 if (stage != icpt_info.stage)
4193 goto out;
4194
4195 switch (icpt_info.exit_code) {
4196 case SVM_EXIT_READ_CR0:
4197 if (info->intercept == x86_intercept_cr_read)
4198 icpt_info.exit_code += info->modrm_reg;
4199 break;
4200 case SVM_EXIT_WRITE_CR0: {
4201 unsigned long cr0, val;
4202 u64 intercept;
4203
4204 if (info->intercept == x86_intercept_cr_write)
4205 icpt_info.exit_code += info->modrm_reg;
4206
4207 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
4208 break;
4209
4210 intercept = svm->nested.intercept;
4211
4212 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
4213 break;
4214
4215 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4216 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4217
4218 if (info->intercept == x86_intercept_lmsw) {
4219 cr0 &= 0xfUL;
4220 val &= 0xfUL;
4221 /* lmsw can't clear PE - catch this here */
4222 if (cr0 & X86_CR0_PE)
4223 val |= X86_CR0_PE;
4224 }
4225
4226 if (cr0 ^ val)
4227 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4228
4229 break;
4230 }
4231 case SVM_EXIT_READ_DR0:
4232 case SVM_EXIT_WRITE_DR0:
4233 icpt_info.exit_code += info->modrm_reg;
4234 break;
4235 case SVM_EXIT_MSR:
4236 if (info->intercept == x86_intercept_wrmsr)
4237 vmcb->control.exit_info_1 = 1;
4238 else
4239 vmcb->control.exit_info_1 = 0;
4240 break;
4241 case SVM_EXIT_PAUSE:
4242 /*
4243 * We get this for NOP only, but pause
4244 * is rep not, check this here
4245 */
4246 if (info->rep_prefix != REPE_PREFIX)
4247 goto out;
4248 case SVM_EXIT_IOIO: {
4249 u64 exit_info;
4250 u32 bytes;
4251
4252 exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
4253
4254 if (info->intercept == x86_intercept_in ||
4255 info->intercept == x86_intercept_ins) {
4256 exit_info |= SVM_IOIO_TYPE_MASK;
4257 bytes = info->src_bytes;
4258 } else {
4259 bytes = info->dst_bytes;
4260 }
4261
4262 if (info->intercept == x86_intercept_outs ||
4263 info->intercept == x86_intercept_ins)
4264 exit_info |= SVM_IOIO_STR_MASK;
4265
4266 if (info->rep_prefix)
4267 exit_info |= SVM_IOIO_REP_MASK;
4268
4269 bytes = min(bytes, 4u);
4270
4271 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4272
4273 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4274
4275 vmcb->control.exit_info_1 = exit_info;
4276 vmcb->control.exit_info_2 = info->next_rip;
4277
4278 break;
4279 }
4280 default:
4281 break;
4282 }
4283
4284 vmcb->control.next_rip = info->next_rip;
4285 vmcb->control.exit_code = icpt_info.exit_code;
4286 vmexit = nested_svm_exit_handled(svm);
4287
4288 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4289 : X86EMUL_CONTINUE;
4290
4291 out:
4292 return ret;
4293 }
4294
4295 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
4296 {
4297 local_irq_enable();
4298 }
4299
4300 static struct kvm_x86_ops svm_x86_ops = {
4301 .cpu_has_kvm_support = has_svm,
4302 .disabled_by_bios = is_disabled,
4303 .hardware_setup = svm_hardware_setup,
4304 .hardware_unsetup = svm_hardware_unsetup,
4305 .check_processor_compatibility = svm_check_processor_compat,
4306 .hardware_enable = svm_hardware_enable,
4307 .hardware_disable = svm_hardware_disable,
4308 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4309
4310 .vcpu_create = svm_create_vcpu,
4311 .vcpu_free = svm_free_vcpu,
4312 .vcpu_reset = svm_vcpu_reset,
4313
4314 .prepare_guest_switch = svm_prepare_guest_switch,
4315 .vcpu_load = svm_vcpu_load,
4316 .vcpu_put = svm_vcpu_put,
4317
4318 .update_db_bp_intercept = update_db_bp_intercept,
4319 .get_msr = svm_get_msr,
4320 .set_msr = svm_set_msr,
4321 .get_segment_base = svm_get_segment_base,
4322 .get_segment = svm_get_segment,
4323 .set_segment = svm_set_segment,
4324 .get_cpl = svm_get_cpl,
4325 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4326 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
4327 .decache_cr3 = svm_decache_cr3,
4328 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
4329 .set_cr0 = svm_set_cr0,
4330 .set_cr3 = svm_set_cr3,
4331 .set_cr4 = svm_set_cr4,
4332 .set_efer = svm_set_efer,
4333 .get_idt = svm_get_idt,
4334 .set_idt = svm_set_idt,
4335 .get_gdt = svm_get_gdt,
4336 .set_gdt = svm_set_gdt,
4337 .get_dr6 = svm_get_dr6,
4338 .set_dr6 = svm_set_dr6,
4339 .set_dr7 = svm_set_dr7,
4340 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4341 .cache_reg = svm_cache_reg,
4342 .get_rflags = svm_get_rflags,
4343 .set_rflags = svm_set_rflags,
4344 .fpu_activate = svm_fpu_activate,
4345 .fpu_deactivate = svm_fpu_deactivate,
4346
4347 .tlb_flush = svm_flush_tlb,
4348
4349 .run = svm_vcpu_run,
4350 .handle_exit = handle_exit,
4351 .skip_emulated_instruction = skip_emulated_instruction,
4352 .set_interrupt_shadow = svm_set_interrupt_shadow,
4353 .get_interrupt_shadow = svm_get_interrupt_shadow,
4354 .patch_hypercall = svm_patch_hypercall,
4355 .set_irq = svm_set_irq,
4356 .set_nmi = svm_inject_nmi,
4357 .queue_exception = svm_queue_exception,
4358 .cancel_injection = svm_cancel_injection,
4359 .interrupt_allowed = svm_interrupt_allowed,
4360 .nmi_allowed = svm_nmi_allowed,
4361 .get_nmi_mask = svm_get_nmi_mask,
4362 .set_nmi_mask = svm_set_nmi_mask,
4363 .enable_nmi_window = enable_nmi_window,
4364 .enable_irq_window = enable_irq_window,
4365 .update_cr8_intercept = update_cr8_intercept,
4366 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
4367 .vm_has_apicv = svm_vm_has_apicv,
4368 .load_eoi_exitmap = svm_load_eoi_exitmap,
4369 .hwapic_isr_update = svm_hwapic_isr_update,
4370 .sync_pir_to_irr = svm_sync_pir_to_irr,
4371
4372 .set_tss_addr = svm_set_tss_addr,
4373 .get_tdp_level = get_npt_level,
4374 .get_mt_mask = svm_get_mt_mask,
4375
4376 .get_exit_info = svm_get_exit_info,
4377
4378 .get_lpage_level = svm_get_lpage_level,
4379
4380 .cpuid_update = svm_cpuid_update,
4381
4382 .rdtscp_supported = svm_rdtscp_supported,
4383 .invpcid_supported = svm_invpcid_supported,
4384 .mpx_supported = svm_mpx_supported,
4385
4386 .set_supported_cpuid = svm_set_supported_cpuid,
4387
4388 .has_wbinvd_exit = svm_has_wbinvd_exit,
4389
4390 .set_tsc_khz = svm_set_tsc_khz,
4391 .read_tsc_offset = svm_read_tsc_offset,
4392 .write_tsc_offset = svm_write_tsc_offset,
4393 .adjust_tsc_offset = svm_adjust_tsc_offset,
4394 .compute_tsc_offset = svm_compute_tsc_offset,
4395 .read_l1_tsc = svm_read_l1_tsc,
4396
4397 .set_tdp_cr3 = set_tdp_cr3,
4398
4399 .check_intercept = svm_check_intercept,
4400 .handle_external_intr = svm_handle_external_intr,
4401 };
4402
4403 static int __init svm_init(void)
4404 {
4405 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
4406 __alignof__(struct vcpu_svm), THIS_MODULE);
4407 }
4408
4409 static void __exit svm_exit(void)
4410 {
4411 kvm_exit();
4412 }
4413
4414 module_init(svm_init)
4415 module_exit(svm_exit)
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