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Merge tag 'for-linus-4.14b-rc2-tag' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48
49 #include <asm/virtext.h>
50 #include "trace.h"
51
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53
54 MODULE_AUTHOR("Qumranet");
55 MODULE_LICENSE("GPL");
56
57 static const struct x86_cpu_id svm_cpu_id[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_SVM),
59 {}
60 };
61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62
63 #define IOPM_ALLOC_ORDER 2
64 #define MSRPM_ALLOC_ORDER 1
65
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
68
69 #define SVM_FEATURE_NPT (1 << 0)
70 #define SVM_FEATURE_LBRV (1 << 1)
71 #define SVM_FEATURE_SVML (1 << 2)
72 #define SVM_FEATURE_NRIP (1 << 3)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78
79 #define SVM_AVIC_DOORBELL 0xc001011b
80
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
92
93 /*
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
96 */
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115
116 static bool erratum_383_found __read_mostly;
117
118 static const u32 host_save_user_msrs[] = {
119 #ifdef CONFIG_X86_64
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
121 MSR_FS_BASE,
122 #endif
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
124 MSR_TSC_AUX,
125 };
126
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
128
129 struct kvm_vcpu;
130
131 struct nested_state {
132 struct vmcb *hsave;
133 u64 hsave_msr;
134 u64 vm_cr_msr;
135 u64 vmcb;
136
137 /* These are the merged vectors */
138 u32 *msrpm;
139
140 /* gpa pointers to the real vectors */
141 u64 vmcb_msrpm;
142 u64 vmcb_iopm;
143
144 /* A VMEXIT is required but not yet emulated */
145 bool exit_required;
146
147 /* cache for intercepts of the guest */
148 u32 intercept_cr;
149 u32 intercept_dr;
150 u32 intercept_exceptions;
151 u64 intercept;
152
153 /* Nested Paging related state */
154 u64 nested_cr3;
155 };
156
157 #define MSRPM_OFFSETS 16
158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
159
160 /*
161 * Set osvw_len to higher value when updated Revision Guides
162 * are published and we know what the new status bits are
163 */
164 static uint64_t osvw_len = 4, osvw_status;
165
166 struct vcpu_svm {
167 struct kvm_vcpu vcpu;
168 struct vmcb *vmcb;
169 unsigned long vmcb_pa;
170 struct svm_cpu_data *svm_data;
171 uint64_t asid_generation;
172 uint64_t sysenter_esp;
173 uint64_t sysenter_eip;
174 uint64_t tsc_aux;
175
176 u64 next_rip;
177
178 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
179 struct {
180 u16 fs;
181 u16 gs;
182 u16 ldt;
183 u64 gs_base;
184 } host;
185
186 u32 *msrpm;
187
188 ulong nmi_iret_rip;
189
190 struct nested_state nested;
191
192 bool nmi_singlestep;
193 u64 nmi_singlestep_guest_rflags;
194
195 unsigned int3_injected;
196 unsigned long int3_rip;
197
198 /* cached guest cpuid flags for faster access */
199 bool nrips_enabled : 1;
200
201 u32 ldr_reg;
202 struct page *avic_backing_page;
203 u64 *avic_physical_id_cache;
204 bool avic_is_running;
205
206 /*
207 * Per-vcpu list of struct amd_svm_iommu_ir:
208 * This is used mainly to store interrupt remapping information used
209 * when update the vcpu affinity. This avoids the need to scan for
210 * IRTE and try to match ga_tag in the IOMMU driver.
211 */
212 struct list_head ir_list;
213 spinlock_t ir_list_lock;
214 };
215
216 /*
217 * This is a wrapper of struct amd_iommu_ir_data.
218 */
219 struct amd_svm_iommu_ir {
220 struct list_head node; /* Used by SVM for per-vcpu ir_list */
221 void *data; /* Storing pointer to struct amd_ir_data */
222 };
223
224 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
225 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226
227 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
228 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
229 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
230 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231
232 static DEFINE_PER_CPU(u64, current_tsc_ratio);
233 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234
235 #define MSR_INVALID 0xffffffffU
236
237 static const struct svm_direct_access_msrs {
238 u32 index; /* Index of the MSR */
239 bool always; /* True if intercept is always on */
240 } direct_access_msrs[] = {
241 { .index = MSR_STAR, .always = true },
242 { .index = MSR_IA32_SYSENTER_CS, .always = true },
243 #ifdef CONFIG_X86_64
244 { .index = MSR_GS_BASE, .always = true },
245 { .index = MSR_FS_BASE, .always = true },
246 { .index = MSR_KERNEL_GS_BASE, .always = true },
247 { .index = MSR_LSTAR, .always = true },
248 { .index = MSR_CSTAR, .always = true },
249 { .index = MSR_SYSCALL_MASK, .always = true },
250 #endif
251 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
252 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
253 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
254 { .index = MSR_IA32_LASTINTTOIP, .always = false },
255 { .index = MSR_INVALID, .always = false },
256 };
257
258 /* enable NPT for AMD64 and X86 with PAE */
259 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
260 static bool npt_enabled = true;
261 #else
262 static bool npt_enabled;
263 #endif
264
265 /* allow nested paging (virtualized MMU) for all guests */
266 static int npt = true;
267 module_param(npt, int, S_IRUGO);
268
269 /* allow nested virtualization in KVM/SVM */
270 static int nested = true;
271 module_param(nested, int, S_IRUGO);
272
273 /* enable / disable AVIC */
274 static int avic;
275 #ifdef CONFIG_X86_LOCAL_APIC
276 module_param(avic, int, S_IRUGO);
277 #endif
278
279 /* enable/disable Virtual VMLOAD VMSAVE */
280 static int vls = true;
281 module_param(vls, int, 0444);
282
283 /* enable/disable Virtual GIF */
284 static int vgif = true;
285 module_param(vgif, int, 0444);
286
287 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
288 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
289 static void svm_complete_interrupts(struct vcpu_svm *svm);
290
291 static int nested_svm_exit_handled(struct vcpu_svm *svm);
292 static int nested_svm_intercept(struct vcpu_svm *svm);
293 static int nested_svm_vmexit(struct vcpu_svm *svm);
294 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
295 bool has_error_code, u32 error_code);
296
297 enum {
298 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
299 pause filter count */
300 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
301 VMCB_ASID, /* ASID */
302 VMCB_INTR, /* int_ctl, int_vector */
303 VMCB_NPT, /* npt_en, nCR3, gPAT */
304 VMCB_CR, /* CR0, CR3, CR4, EFER */
305 VMCB_DR, /* DR6, DR7 */
306 VMCB_DT, /* GDT, IDT */
307 VMCB_SEG, /* CS, DS, SS, ES, CPL */
308 VMCB_CR2, /* CR2 only */
309 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
310 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
311 * AVIC PHYSICAL_TABLE pointer,
312 * AVIC LOGICAL_TABLE pointer
313 */
314 VMCB_DIRTY_MAX,
315 };
316
317 /* TPR and CR2 are always written before VMRUN */
318 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
319
320 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
321
322 static inline void mark_all_dirty(struct vmcb *vmcb)
323 {
324 vmcb->control.clean = 0;
325 }
326
327 static inline void mark_all_clean(struct vmcb *vmcb)
328 {
329 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
330 & ~VMCB_ALWAYS_DIRTY_MASK;
331 }
332
333 static inline void mark_dirty(struct vmcb *vmcb, int bit)
334 {
335 vmcb->control.clean &= ~(1 << bit);
336 }
337
338 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
339 {
340 return container_of(vcpu, struct vcpu_svm, vcpu);
341 }
342
343 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
344 {
345 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
346 mark_dirty(svm->vmcb, VMCB_AVIC);
347 }
348
349 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
350 {
351 struct vcpu_svm *svm = to_svm(vcpu);
352 u64 *entry = svm->avic_physical_id_cache;
353
354 if (!entry)
355 return false;
356
357 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
358 }
359
360 static void recalc_intercepts(struct vcpu_svm *svm)
361 {
362 struct vmcb_control_area *c, *h;
363 struct nested_state *g;
364
365 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
366
367 if (!is_guest_mode(&svm->vcpu))
368 return;
369
370 c = &svm->vmcb->control;
371 h = &svm->nested.hsave->control;
372 g = &svm->nested;
373
374 c->intercept_cr = h->intercept_cr | g->intercept_cr;
375 c->intercept_dr = h->intercept_dr | g->intercept_dr;
376 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
377 c->intercept = h->intercept | g->intercept;
378 }
379
380 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
381 {
382 if (is_guest_mode(&svm->vcpu))
383 return svm->nested.hsave;
384 else
385 return svm->vmcb;
386 }
387
388 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
389 {
390 struct vmcb *vmcb = get_host_vmcb(svm);
391
392 vmcb->control.intercept_cr |= (1U << bit);
393
394 recalc_intercepts(svm);
395 }
396
397 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
398 {
399 struct vmcb *vmcb = get_host_vmcb(svm);
400
401 vmcb->control.intercept_cr &= ~(1U << bit);
402
403 recalc_intercepts(svm);
404 }
405
406 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
407 {
408 struct vmcb *vmcb = get_host_vmcb(svm);
409
410 return vmcb->control.intercept_cr & (1U << bit);
411 }
412
413 static inline void set_dr_intercepts(struct vcpu_svm *svm)
414 {
415 struct vmcb *vmcb = get_host_vmcb(svm);
416
417 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
418 | (1 << INTERCEPT_DR1_READ)
419 | (1 << INTERCEPT_DR2_READ)
420 | (1 << INTERCEPT_DR3_READ)
421 | (1 << INTERCEPT_DR4_READ)
422 | (1 << INTERCEPT_DR5_READ)
423 | (1 << INTERCEPT_DR6_READ)
424 | (1 << INTERCEPT_DR7_READ)
425 | (1 << INTERCEPT_DR0_WRITE)
426 | (1 << INTERCEPT_DR1_WRITE)
427 | (1 << INTERCEPT_DR2_WRITE)
428 | (1 << INTERCEPT_DR3_WRITE)
429 | (1 << INTERCEPT_DR4_WRITE)
430 | (1 << INTERCEPT_DR5_WRITE)
431 | (1 << INTERCEPT_DR6_WRITE)
432 | (1 << INTERCEPT_DR7_WRITE);
433
434 recalc_intercepts(svm);
435 }
436
437 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
438 {
439 struct vmcb *vmcb = get_host_vmcb(svm);
440
441 vmcb->control.intercept_dr = 0;
442
443 recalc_intercepts(svm);
444 }
445
446 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
447 {
448 struct vmcb *vmcb = get_host_vmcb(svm);
449
450 vmcb->control.intercept_exceptions |= (1U << bit);
451
452 recalc_intercepts(svm);
453 }
454
455 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
456 {
457 struct vmcb *vmcb = get_host_vmcb(svm);
458
459 vmcb->control.intercept_exceptions &= ~(1U << bit);
460
461 recalc_intercepts(svm);
462 }
463
464 static inline void set_intercept(struct vcpu_svm *svm, int bit)
465 {
466 struct vmcb *vmcb = get_host_vmcb(svm);
467
468 vmcb->control.intercept |= (1ULL << bit);
469
470 recalc_intercepts(svm);
471 }
472
473 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
474 {
475 struct vmcb *vmcb = get_host_vmcb(svm);
476
477 vmcb->control.intercept &= ~(1ULL << bit);
478
479 recalc_intercepts(svm);
480 }
481
482 static inline bool vgif_enabled(struct vcpu_svm *svm)
483 {
484 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
485 }
486
487 static inline void enable_gif(struct vcpu_svm *svm)
488 {
489 if (vgif_enabled(svm))
490 svm->vmcb->control.int_ctl |= V_GIF_MASK;
491 else
492 svm->vcpu.arch.hflags |= HF_GIF_MASK;
493 }
494
495 static inline void disable_gif(struct vcpu_svm *svm)
496 {
497 if (vgif_enabled(svm))
498 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
499 else
500 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
501 }
502
503 static inline bool gif_set(struct vcpu_svm *svm)
504 {
505 if (vgif_enabled(svm))
506 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
507 else
508 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
509 }
510
511 static unsigned long iopm_base;
512
513 struct kvm_ldttss_desc {
514 u16 limit0;
515 u16 base0;
516 unsigned base1:8, type:5, dpl:2, p:1;
517 unsigned limit1:4, zero0:3, g:1, base2:8;
518 u32 base3;
519 u32 zero1;
520 } __attribute__((packed));
521
522 struct svm_cpu_data {
523 int cpu;
524
525 u64 asid_generation;
526 u32 max_asid;
527 u32 next_asid;
528 struct kvm_ldttss_desc *tss_desc;
529
530 struct page *save_area;
531 };
532
533 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
534
535 struct svm_init_data {
536 int cpu;
537 int r;
538 };
539
540 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
541
542 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
543 #define MSRS_RANGE_SIZE 2048
544 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
545
546 static u32 svm_msrpm_offset(u32 msr)
547 {
548 u32 offset;
549 int i;
550
551 for (i = 0; i < NUM_MSR_MAPS; i++) {
552 if (msr < msrpm_ranges[i] ||
553 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
554 continue;
555
556 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
557 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
558
559 /* Now we have the u8 offset - but need the u32 offset */
560 return offset / 4;
561 }
562
563 /* MSR not in any range */
564 return MSR_INVALID;
565 }
566
567 #define MAX_INST_SIZE 15
568
569 static inline void clgi(void)
570 {
571 asm volatile (__ex(SVM_CLGI));
572 }
573
574 static inline void stgi(void)
575 {
576 asm volatile (__ex(SVM_STGI));
577 }
578
579 static inline void invlpga(unsigned long addr, u32 asid)
580 {
581 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
582 }
583
584 static int get_npt_level(struct kvm_vcpu *vcpu)
585 {
586 #ifdef CONFIG_X86_64
587 return PT64_ROOT_4LEVEL;
588 #else
589 return PT32E_ROOT_LEVEL;
590 #endif
591 }
592
593 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
594 {
595 vcpu->arch.efer = efer;
596 if (!npt_enabled && !(efer & EFER_LMA))
597 efer &= ~EFER_LME;
598
599 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
600 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
601 }
602
603 static int is_external_interrupt(u32 info)
604 {
605 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
606 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
607 }
608
609 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
610 {
611 struct vcpu_svm *svm = to_svm(vcpu);
612 u32 ret = 0;
613
614 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
615 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
616 return ret;
617 }
618
619 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
620 {
621 struct vcpu_svm *svm = to_svm(vcpu);
622
623 if (mask == 0)
624 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
625 else
626 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
627
628 }
629
630 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
631 {
632 struct vcpu_svm *svm = to_svm(vcpu);
633
634 if (svm->vmcb->control.next_rip != 0) {
635 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
636 svm->next_rip = svm->vmcb->control.next_rip;
637 }
638
639 if (!svm->next_rip) {
640 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
641 EMULATE_DONE)
642 printk(KERN_DEBUG "%s: NOP\n", __func__);
643 return;
644 }
645 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
646 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
647 __func__, kvm_rip_read(vcpu), svm->next_rip);
648
649 kvm_rip_write(vcpu, svm->next_rip);
650 svm_set_interrupt_shadow(vcpu, 0);
651 }
652
653 static void svm_queue_exception(struct kvm_vcpu *vcpu)
654 {
655 struct vcpu_svm *svm = to_svm(vcpu);
656 unsigned nr = vcpu->arch.exception.nr;
657 bool has_error_code = vcpu->arch.exception.has_error_code;
658 bool reinject = vcpu->arch.exception.injected;
659 u32 error_code = vcpu->arch.exception.error_code;
660
661 /*
662 * If we are within a nested VM we'd better #VMEXIT and let the guest
663 * handle the exception
664 */
665 if (!reinject &&
666 nested_svm_check_exception(svm, nr, has_error_code, error_code))
667 return;
668
669 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
670 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
671
672 /*
673 * For guest debugging where we have to reinject #BP if some
674 * INT3 is guest-owned:
675 * Emulate nRIP by moving RIP forward. Will fail if injection
676 * raises a fault that is not intercepted. Still better than
677 * failing in all cases.
678 */
679 skip_emulated_instruction(&svm->vcpu);
680 rip = kvm_rip_read(&svm->vcpu);
681 svm->int3_rip = rip + svm->vmcb->save.cs.base;
682 svm->int3_injected = rip - old_rip;
683 }
684
685 svm->vmcb->control.event_inj = nr
686 | SVM_EVTINJ_VALID
687 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
688 | SVM_EVTINJ_TYPE_EXEPT;
689 svm->vmcb->control.event_inj_err = error_code;
690 }
691
692 static void svm_init_erratum_383(void)
693 {
694 u32 low, high;
695 int err;
696 u64 val;
697
698 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
699 return;
700
701 /* Use _safe variants to not break nested virtualization */
702 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
703 if (err)
704 return;
705
706 val |= (1ULL << 47);
707
708 low = lower_32_bits(val);
709 high = upper_32_bits(val);
710
711 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
712
713 erratum_383_found = true;
714 }
715
716 static void svm_init_osvw(struct kvm_vcpu *vcpu)
717 {
718 /*
719 * Guests should see errata 400 and 415 as fixed (assuming that
720 * HLT and IO instructions are intercepted).
721 */
722 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
723 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
724
725 /*
726 * By increasing VCPU's osvw.length to 3 we are telling the guest that
727 * all osvw.status bits inside that length, including bit 0 (which is
728 * reserved for erratum 298), are valid. However, if host processor's
729 * osvw_len is 0 then osvw_status[0] carries no information. We need to
730 * be conservative here and therefore we tell the guest that erratum 298
731 * is present (because we really don't know).
732 */
733 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
734 vcpu->arch.osvw.status |= 1;
735 }
736
737 static int has_svm(void)
738 {
739 const char *msg;
740
741 if (!cpu_has_svm(&msg)) {
742 printk(KERN_INFO "has_svm: %s\n", msg);
743 return 0;
744 }
745
746 return 1;
747 }
748
749 static void svm_hardware_disable(void)
750 {
751 /* Make sure we clean up behind us */
752 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
753 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
754
755 cpu_svm_disable();
756
757 amd_pmu_disable_virt();
758 }
759
760 static int svm_hardware_enable(void)
761 {
762
763 struct svm_cpu_data *sd;
764 uint64_t efer;
765 struct desc_struct *gdt;
766 int me = raw_smp_processor_id();
767
768 rdmsrl(MSR_EFER, efer);
769 if (efer & EFER_SVME)
770 return -EBUSY;
771
772 if (!has_svm()) {
773 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
774 return -EINVAL;
775 }
776 sd = per_cpu(svm_data, me);
777 if (!sd) {
778 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
779 return -EINVAL;
780 }
781
782 sd->asid_generation = 1;
783 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
784 sd->next_asid = sd->max_asid + 1;
785
786 gdt = get_current_gdt_rw();
787 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
788
789 wrmsrl(MSR_EFER, efer | EFER_SVME);
790
791 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
792
793 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
794 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
795 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
796 }
797
798
799 /*
800 * Get OSVW bits.
801 *
802 * Note that it is possible to have a system with mixed processor
803 * revisions and therefore different OSVW bits. If bits are not the same
804 * on different processors then choose the worst case (i.e. if erratum
805 * is present on one processor and not on another then assume that the
806 * erratum is present everywhere).
807 */
808 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
809 uint64_t len, status = 0;
810 int err;
811
812 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
813 if (!err)
814 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
815 &err);
816
817 if (err)
818 osvw_status = osvw_len = 0;
819 else {
820 if (len < osvw_len)
821 osvw_len = len;
822 osvw_status |= status;
823 osvw_status &= (1ULL << osvw_len) - 1;
824 }
825 } else
826 osvw_status = osvw_len = 0;
827
828 svm_init_erratum_383();
829
830 amd_pmu_enable_virt();
831
832 return 0;
833 }
834
835 static void svm_cpu_uninit(int cpu)
836 {
837 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
838
839 if (!sd)
840 return;
841
842 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
843 __free_page(sd->save_area);
844 kfree(sd);
845 }
846
847 static int svm_cpu_init(int cpu)
848 {
849 struct svm_cpu_data *sd;
850 int r;
851
852 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
853 if (!sd)
854 return -ENOMEM;
855 sd->cpu = cpu;
856 sd->save_area = alloc_page(GFP_KERNEL);
857 r = -ENOMEM;
858 if (!sd->save_area)
859 goto err_1;
860
861 per_cpu(svm_data, cpu) = sd;
862
863 return 0;
864
865 err_1:
866 kfree(sd);
867 return r;
868
869 }
870
871 static bool valid_msr_intercept(u32 index)
872 {
873 int i;
874
875 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
876 if (direct_access_msrs[i].index == index)
877 return true;
878
879 return false;
880 }
881
882 static void set_msr_interception(u32 *msrpm, unsigned msr,
883 int read, int write)
884 {
885 u8 bit_read, bit_write;
886 unsigned long tmp;
887 u32 offset;
888
889 /*
890 * If this warning triggers extend the direct_access_msrs list at the
891 * beginning of the file
892 */
893 WARN_ON(!valid_msr_intercept(msr));
894
895 offset = svm_msrpm_offset(msr);
896 bit_read = 2 * (msr & 0x0f);
897 bit_write = 2 * (msr & 0x0f) + 1;
898 tmp = msrpm[offset];
899
900 BUG_ON(offset == MSR_INVALID);
901
902 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
903 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
904
905 msrpm[offset] = tmp;
906 }
907
908 static void svm_vcpu_init_msrpm(u32 *msrpm)
909 {
910 int i;
911
912 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
913
914 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
915 if (!direct_access_msrs[i].always)
916 continue;
917
918 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
919 }
920 }
921
922 static void add_msr_offset(u32 offset)
923 {
924 int i;
925
926 for (i = 0; i < MSRPM_OFFSETS; ++i) {
927
928 /* Offset already in list? */
929 if (msrpm_offsets[i] == offset)
930 return;
931
932 /* Slot used by another offset? */
933 if (msrpm_offsets[i] != MSR_INVALID)
934 continue;
935
936 /* Add offset to list */
937 msrpm_offsets[i] = offset;
938
939 return;
940 }
941
942 /*
943 * If this BUG triggers the msrpm_offsets table has an overflow. Just
944 * increase MSRPM_OFFSETS in this case.
945 */
946 BUG();
947 }
948
949 static void init_msrpm_offsets(void)
950 {
951 int i;
952
953 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
954
955 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
956 u32 offset;
957
958 offset = svm_msrpm_offset(direct_access_msrs[i].index);
959 BUG_ON(offset == MSR_INVALID);
960
961 add_msr_offset(offset);
962 }
963 }
964
965 static void svm_enable_lbrv(struct vcpu_svm *svm)
966 {
967 u32 *msrpm = svm->msrpm;
968
969 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
970 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
971 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
972 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
973 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
974 }
975
976 static void svm_disable_lbrv(struct vcpu_svm *svm)
977 {
978 u32 *msrpm = svm->msrpm;
979
980 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
981 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
982 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
983 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
984 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
985 }
986
987 static void disable_nmi_singlestep(struct vcpu_svm *svm)
988 {
989 svm->nmi_singlestep = false;
990
991 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
992 /* Clear our flags if they were not set by the guest */
993 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
994 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
995 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
996 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
997 }
998 }
999
1000 /* Note:
1001 * This hash table is used to map VM_ID to a struct kvm_arch,
1002 * when handling AMD IOMMU GALOG notification to schedule in
1003 * a particular vCPU.
1004 */
1005 #define SVM_VM_DATA_HASH_BITS 8
1006 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1007 static u32 next_vm_id = 0;
1008 static bool next_vm_id_wrapped = 0;
1009 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1010
1011 /* Note:
1012 * This function is called from IOMMU driver to notify
1013 * SVM to schedule in a particular vCPU of a particular VM.
1014 */
1015 static int avic_ga_log_notifier(u32 ga_tag)
1016 {
1017 unsigned long flags;
1018 struct kvm_arch *ka = NULL;
1019 struct kvm_vcpu *vcpu = NULL;
1020 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1021 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1022
1023 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1024
1025 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1026 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1027 struct kvm *kvm = container_of(ka, struct kvm, arch);
1028 struct kvm_arch *vm_data = &kvm->arch;
1029
1030 if (vm_data->avic_vm_id != vm_id)
1031 continue;
1032 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1033 break;
1034 }
1035 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1036
1037 if (!vcpu)
1038 return 0;
1039
1040 /* Note:
1041 * At this point, the IOMMU should have already set the pending
1042 * bit in the vAPIC backing page. So, we just need to schedule
1043 * in the vcpu.
1044 */
1045 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1046 kvm_vcpu_wake_up(vcpu);
1047
1048 return 0;
1049 }
1050
1051 static __init int svm_hardware_setup(void)
1052 {
1053 int cpu;
1054 struct page *iopm_pages;
1055 void *iopm_va;
1056 int r;
1057
1058 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1059
1060 if (!iopm_pages)
1061 return -ENOMEM;
1062
1063 iopm_va = page_address(iopm_pages);
1064 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1065 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1066
1067 init_msrpm_offsets();
1068
1069 if (boot_cpu_has(X86_FEATURE_NX))
1070 kvm_enable_efer_bits(EFER_NX);
1071
1072 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1073 kvm_enable_efer_bits(EFER_FFXSR);
1074
1075 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1076 kvm_has_tsc_control = true;
1077 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1078 kvm_tsc_scaling_ratio_frac_bits = 32;
1079 }
1080
1081 if (nested) {
1082 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1083 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1084 }
1085
1086 for_each_possible_cpu(cpu) {
1087 r = svm_cpu_init(cpu);
1088 if (r)
1089 goto err;
1090 }
1091
1092 if (!boot_cpu_has(X86_FEATURE_NPT))
1093 npt_enabled = false;
1094
1095 if (npt_enabled && !npt) {
1096 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1097 npt_enabled = false;
1098 }
1099
1100 if (npt_enabled) {
1101 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1102 kvm_enable_tdp();
1103 } else
1104 kvm_disable_tdp();
1105
1106 if (avic) {
1107 if (!npt_enabled ||
1108 !boot_cpu_has(X86_FEATURE_AVIC) ||
1109 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1110 avic = false;
1111 } else {
1112 pr_info("AVIC enabled\n");
1113
1114 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1115 }
1116 }
1117
1118 if (vls) {
1119 if (!npt_enabled ||
1120 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1121 !IS_ENABLED(CONFIG_X86_64)) {
1122 vls = false;
1123 } else {
1124 pr_info("Virtual VMLOAD VMSAVE supported\n");
1125 }
1126 }
1127
1128 if (vgif) {
1129 if (!boot_cpu_has(X86_FEATURE_VGIF))
1130 vgif = false;
1131 else
1132 pr_info("Virtual GIF supported\n");
1133 }
1134
1135 return 0;
1136
1137 err:
1138 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1139 iopm_base = 0;
1140 return r;
1141 }
1142
1143 static __exit void svm_hardware_unsetup(void)
1144 {
1145 int cpu;
1146
1147 for_each_possible_cpu(cpu)
1148 svm_cpu_uninit(cpu);
1149
1150 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1151 iopm_base = 0;
1152 }
1153
1154 static void init_seg(struct vmcb_seg *seg)
1155 {
1156 seg->selector = 0;
1157 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1158 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1159 seg->limit = 0xffff;
1160 seg->base = 0;
1161 }
1162
1163 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1164 {
1165 seg->selector = 0;
1166 seg->attrib = SVM_SELECTOR_P_MASK | type;
1167 seg->limit = 0xffff;
1168 seg->base = 0;
1169 }
1170
1171 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1172 {
1173 struct vcpu_svm *svm = to_svm(vcpu);
1174 u64 g_tsc_offset = 0;
1175
1176 if (is_guest_mode(vcpu)) {
1177 g_tsc_offset = svm->vmcb->control.tsc_offset -
1178 svm->nested.hsave->control.tsc_offset;
1179 svm->nested.hsave->control.tsc_offset = offset;
1180 } else
1181 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1182 svm->vmcb->control.tsc_offset,
1183 offset);
1184
1185 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1186
1187 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1188 }
1189
1190 static void avic_init_vmcb(struct vcpu_svm *svm)
1191 {
1192 struct vmcb *vmcb = svm->vmcb;
1193 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1194 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1195 phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page));
1196 phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page));
1197
1198 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1199 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1200 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1201 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1202 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1203 }
1204
1205 static void init_vmcb(struct vcpu_svm *svm)
1206 {
1207 struct vmcb_control_area *control = &svm->vmcb->control;
1208 struct vmcb_save_area *save = &svm->vmcb->save;
1209
1210 svm->vcpu.arch.hflags = 0;
1211
1212 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1213 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1214 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1215 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1216 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1217 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1218 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1219 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1220
1221 set_dr_intercepts(svm);
1222
1223 set_exception_intercept(svm, PF_VECTOR);
1224 set_exception_intercept(svm, UD_VECTOR);
1225 set_exception_intercept(svm, MC_VECTOR);
1226 set_exception_intercept(svm, AC_VECTOR);
1227 set_exception_intercept(svm, DB_VECTOR);
1228
1229 set_intercept(svm, INTERCEPT_INTR);
1230 set_intercept(svm, INTERCEPT_NMI);
1231 set_intercept(svm, INTERCEPT_SMI);
1232 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1233 set_intercept(svm, INTERCEPT_RDPMC);
1234 set_intercept(svm, INTERCEPT_CPUID);
1235 set_intercept(svm, INTERCEPT_INVD);
1236 set_intercept(svm, INTERCEPT_HLT);
1237 set_intercept(svm, INTERCEPT_INVLPG);
1238 set_intercept(svm, INTERCEPT_INVLPGA);
1239 set_intercept(svm, INTERCEPT_IOIO_PROT);
1240 set_intercept(svm, INTERCEPT_MSR_PROT);
1241 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1242 set_intercept(svm, INTERCEPT_SHUTDOWN);
1243 set_intercept(svm, INTERCEPT_VMRUN);
1244 set_intercept(svm, INTERCEPT_VMMCALL);
1245 set_intercept(svm, INTERCEPT_VMLOAD);
1246 set_intercept(svm, INTERCEPT_VMSAVE);
1247 set_intercept(svm, INTERCEPT_STGI);
1248 set_intercept(svm, INTERCEPT_CLGI);
1249 set_intercept(svm, INTERCEPT_SKINIT);
1250 set_intercept(svm, INTERCEPT_WBINVD);
1251 set_intercept(svm, INTERCEPT_XSETBV);
1252
1253 if (!kvm_mwait_in_guest()) {
1254 set_intercept(svm, INTERCEPT_MONITOR);
1255 set_intercept(svm, INTERCEPT_MWAIT);
1256 }
1257
1258 control->iopm_base_pa = __sme_set(iopm_base);
1259 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1260 control->int_ctl = V_INTR_MASKING_MASK;
1261
1262 init_seg(&save->es);
1263 init_seg(&save->ss);
1264 init_seg(&save->ds);
1265 init_seg(&save->fs);
1266 init_seg(&save->gs);
1267
1268 save->cs.selector = 0xf000;
1269 save->cs.base = 0xffff0000;
1270 /* Executable/Readable Code Segment */
1271 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1272 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1273 save->cs.limit = 0xffff;
1274
1275 save->gdtr.limit = 0xffff;
1276 save->idtr.limit = 0xffff;
1277
1278 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1279 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1280
1281 svm_set_efer(&svm->vcpu, 0);
1282 save->dr6 = 0xffff0ff0;
1283 kvm_set_rflags(&svm->vcpu, 2);
1284 save->rip = 0x0000fff0;
1285 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1286
1287 /*
1288 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1289 * It also updates the guest-visible cr0 value.
1290 */
1291 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1292 kvm_mmu_reset_context(&svm->vcpu);
1293
1294 save->cr4 = X86_CR4_PAE;
1295 /* rdx = ?? */
1296
1297 if (npt_enabled) {
1298 /* Setup VMCB for Nested Paging */
1299 control->nested_ctl = 1;
1300 clr_intercept(svm, INTERCEPT_INVLPG);
1301 clr_exception_intercept(svm, PF_VECTOR);
1302 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1303 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1304 save->g_pat = svm->vcpu.arch.pat;
1305 save->cr3 = 0;
1306 save->cr4 = 0;
1307 }
1308 svm->asid_generation = 0;
1309
1310 svm->nested.vmcb = 0;
1311 svm->vcpu.arch.hflags = 0;
1312
1313 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1314 control->pause_filter_count = 3000;
1315 set_intercept(svm, INTERCEPT_PAUSE);
1316 }
1317
1318 if (kvm_vcpu_apicv_active(&svm->vcpu))
1319 avic_init_vmcb(svm);
1320
1321 /*
1322 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1323 * in VMCB and clear intercepts to avoid #VMEXIT.
1324 */
1325 if (vls) {
1326 clr_intercept(svm, INTERCEPT_VMLOAD);
1327 clr_intercept(svm, INTERCEPT_VMSAVE);
1328 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1329 }
1330
1331 if (vgif) {
1332 clr_intercept(svm, INTERCEPT_STGI);
1333 clr_intercept(svm, INTERCEPT_CLGI);
1334 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1335 }
1336
1337 mark_all_dirty(svm->vmcb);
1338
1339 enable_gif(svm);
1340
1341 }
1342
1343 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1344 unsigned int index)
1345 {
1346 u64 *avic_physical_id_table;
1347 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1348
1349 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1350 return NULL;
1351
1352 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1353
1354 return &avic_physical_id_table[index];
1355 }
1356
1357 /**
1358 * Note:
1359 * AVIC hardware walks the nested page table to check permissions,
1360 * but does not use the SPA address specified in the leaf page
1361 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1362 * field of the VMCB. Therefore, we set up the
1363 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1364 */
1365 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1366 {
1367 struct kvm *kvm = vcpu->kvm;
1368 int ret;
1369
1370 if (kvm->arch.apic_access_page_done)
1371 return 0;
1372
1373 ret = x86_set_memory_region(kvm,
1374 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1375 APIC_DEFAULT_PHYS_BASE,
1376 PAGE_SIZE);
1377 if (ret)
1378 return ret;
1379
1380 kvm->arch.apic_access_page_done = true;
1381 return 0;
1382 }
1383
1384 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1385 {
1386 int ret;
1387 u64 *entry, new_entry;
1388 int id = vcpu->vcpu_id;
1389 struct vcpu_svm *svm = to_svm(vcpu);
1390
1391 ret = avic_init_access_page(vcpu);
1392 if (ret)
1393 return ret;
1394
1395 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1396 return -EINVAL;
1397
1398 if (!svm->vcpu.arch.apic->regs)
1399 return -EINVAL;
1400
1401 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1402
1403 /* Setting AVIC backing page address in the phy APIC ID table */
1404 entry = avic_get_physical_id_entry(vcpu, id);
1405 if (!entry)
1406 return -EINVAL;
1407
1408 new_entry = READ_ONCE(*entry);
1409 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1410 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1411 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1412 WRITE_ONCE(*entry, new_entry);
1413
1414 svm->avic_physical_id_cache = entry;
1415
1416 return 0;
1417 }
1418
1419 static void avic_vm_destroy(struct kvm *kvm)
1420 {
1421 unsigned long flags;
1422 struct kvm_arch *vm_data = &kvm->arch;
1423
1424 if (!avic)
1425 return;
1426
1427 if (vm_data->avic_logical_id_table_page)
1428 __free_page(vm_data->avic_logical_id_table_page);
1429 if (vm_data->avic_physical_id_table_page)
1430 __free_page(vm_data->avic_physical_id_table_page);
1431
1432 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1433 hash_del(&vm_data->hnode);
1434 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1435 }
1436
1437 static int avic_vm_init(struct kvm *kvm)
1438 {
1439 unsigned long flags;
1440 int err = -ENOMEM;
1441 struct kvm_arch *vm_data = &kvm->arch;
1442 struct page *p_page;
1443 struct page *l_page;
1444 struct kvm_arch *ka;
1445 u32 vm_id;
1446
1447 if (!avic)
1448 return 0;
1449
1450 /* Allocating physical APIC ID table (4KB) */
1451 p_page = alloc_page(GFP_KERNEL);
1452 if (!p_page)
1453 goto free_avic;
1454
1455 vm_data->avic_physical_id_table_page = p_page;
1456 clear_page(page_address(p_page));
1457
1458 /* Allocating logical APIC ID table (4KB) */
1459 l_page = alloc_page(GFP_KERNEL);
1460 if (!l_page)
1461 goto free_avic;
1462
1463 vm_data->avic_logical_id_table_page = l_page;
1464 clear_page(page_address(l_page));
1465
1466 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1467 again:
1468 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1469 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1470 next_vm_id_wrapped = 1;
1471 goto again;
1472 }
1473 /* Is it still in use? Only possible if wrapped at least once */
1474 if (next_vm_id_wrapped) {
1475 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1476 struct kvm *k2 = container_of(ka, struct kvm, arch);
1477 struct kvm_arch *vd2 = &k2->arch;
1478 if (vd2->avic_vm_id == vm_id)
1479 goto again;
1480 }
1481 }
1482 vm_data->avic_vm_id = vm_id;
1483 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1484 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1485
1486 return 0;
1487
1488 free_avic:
1489 avic_vm_destroy(kvm);
1490 return err;
1491 }
1492
1493 static inline int
1494 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1495 {
1496 int ret = 0;
1497 unsigned long flags;
1498 struct amd_svm_iommu_ir *ir;
1499 struct vcpu_svm *svm = to_svm(vcpu);
1500
1501 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1502 return 0;
1503
1504 /*
1505 * Here, we go through the per-vcpu ir_list to update all existing
1506 * interrupt remapping table entry targeting this vcpu.
1507 */
1508 spin_lock_irqsave(&svm->ir_list_lock, flags);
1509
1510 if (list_empty(&svm->ir_list))
1511 goto out;
1512
1513 list_for_each_entry(ir, &svm->ir_list, node) {
1514 ret = amd_iommu_update_ga(cpu, r, ir->data);
1515 if (ret)
1516 break;
1517 }
1518 out:
1519 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1520 return ret;
1521 }
1522
1523 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1524 {
1525 u64 entry;
1526 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1527 int h_physical_id = kvm_cpu_get_apicid(cpu);
1528 struct vcpu_svm *svm = to_svm(vcpu);
1529
1530 if (!kvm_vcpu_apicv_active(vcpu))
1531 return;
1532
1533 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1534 return;
1535
1536 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1537 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1538
1539 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1540 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1541
1542 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1543 if (svm->avic_is_running)
1544 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1545
1546 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1547 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1548 svm->avic_is_running);
1549 }
1550
1551 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1552 {
1553 u64 entry;
1554 struct vcpu_svm *svm = to_svm(vcpu);
1555
1556 if (!kvm_vcpu_apicv_active(vcpu))
1557 return;
1558
1559 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1560 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1561 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1562
1563 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1564 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1565 }
1566
1567 /**
1568 * This function is called during VCPU halt/unhalt.
1569 */
1570 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1571 {
1572 struct vcpu_svm *svm = to_svm(vcpu);
1573
1574 svm->avic_is_running = is_run;
1575 if (is_run)
1576 avic_vcpu_load(vcpu, vcpu->cpu);
1577 else
1578 avic_vcpu_put(vcpu);
1579 }
1580
1581 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1582 {
1583 struct vcpu_svm *svm = to_svm(vcpu);
1584 u32 dummy;
1585 u32 eax = 1;
1586
1587 if (!init_event) {
1588 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1589 MSR_IA32_APICBASE_ENABLE;
1590 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1591 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1592 }
1593 init_vmcb(svm);
1594
1595 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
1596 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1597
1598 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1599 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1600 }
1601
1602 static int avic_init_vcpu(struct vcpu_svm *svm)
1603 {
1604 int ret;
1605
1606 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1607 return 0;
1608
1609 ret = avic_init_backing_page(&svm->vcpu);
1610 if (ret)
1611 return ret;
1612
1613 INIT_LIST_HEAD(&svm->ir_list);
1614 spin_lock_init(&svm->ir_list_lock);
1615
1616 return ret;
1617 }
1618
1619 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1620 {
1621 struct vcpu_svm *svm;
1622 struct page *page;
1623 struct page *msrpm_pages;
1624 struct page *hsave_page;
1625 struct page *nested_msrpm_pages;
1626 int err;
1627
1628 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1629 if (!svm) {
1630 err = -ENOMEM;
1631 goto out;
1632 }
1633
1634 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1635 if (err)
1636 goto free_svm;
1637
1638 err = -ENOMEM;
1639 page = alloc_page(GFP_KERNEL);
1640 if (!page)
1641 goto uninit;
1642
1643 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1644 if (!msrpm_pages)
1645 goto free_page1;
1646
1647 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1648 if (!nested_msrpm_pages)
1649 goto free_page2;
1650
1651 hsave_page = alloc_page(GFP_KERNEL);
1652 if (!hsave_page)
1653 goto free_page3;
1654
1655 err = avic_init_vcpu(svm);
1656 if (err)
1657 goto free_page4;
1658
1659 /* We initialize this flag to true to make sure that the is_running
1660 * bit would be set the first time the vcpu is loaded.
1661 */
1662 svm->avic_is_running = true;
1663
1664 svm->nested.hsave = page_address(hsave_page);
1665
1666 svm->msrpm = page_address(msrpm_pages);
1667 svm_vcpu_init_msrpm(svm->msrpm);
1668
1669 svm->nested.msrpm = page_address(nested_msrpm_pages);
1670 svm_vcpu_init_msrpm(svm->nested.msrpm);
1671
1672 svm->vmcb = page_address(page);
1673 clear_page(svm->vmcb);
1674 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1675 svm->asid_generation = 0;
1676 init_vmcb(svm);
1677
1678 svm_init_osvw(&svm->vcpu);
1679
1680 return &svm->vcpu;
1681
1682 free_page4:
1683 __free_page(hsave_page);
1684 free_page3:
1685 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1686 free_page2:
1687 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1688 free_page1:
1689 __free_page(page);
1690 uninit:
1691 kvm_vcpu_uninit(&svm->vcpu);
1692 free_svm:
1693 kmem_cache_free(kvm_vcpu_cache, svm);
1694 out:
1695 return ERR_PTR(err);
1696 }
1697
1698 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1699 {
1700 struct vcpu_svm *svm = to_svm(vcpu);
1701
1702 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1703 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1704 __free_page(virt_to_page(svm->nested.hsave));
1705 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1706 kvm_vcpu_uninit(vcpu);
1707 kmem_cache_free(kvm_vcpu_cache, svm);
1708 }
1709
1710 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1711 {
1712 struct vcpu_svm *svm = to_svm(vcpu);
1713 int i;
1714
1715 if (unlikely(cpu != vcpu->cpu)) {
1716 svm->asid_generation = 0;
1717 mark_all_dirty(svm->vmcb);
1718 }
1719
1720 #ifdef CONFIG_X86_64
1721 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1722 #endif
1723 savesegment(fs, svm->host.fs);
1724 savesegment(gs, svm->host.gs);
1725 svm->host.ldt = kvm_read_ldt();
1726
1727 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1728 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1729
1730 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1731 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1732 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1733 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1734 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1735 }
1736 }
1737 /* This assumes that the kernel never uses MSR_TSC_AUX */
1738 if (static_cpu_has(X86_FEATURE_RDTSCP))
1739 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1740
1741 avic_vcpu_load(vcpu, cpu);
1742 }
1743
1744 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1745 {
1746 struct vcpu_svm *svm = to_svm(vcpu);
1747 int i;
1748
1749 avic_vcpu_put(vcpu);
1750
1751 ++vcpu->stat.host_state_reload;
1752 kvm_load_ldt(svm->host.ldt);
1753 #ifdef CONFIG_X86_64
1754 loadsegment(fs, svm->host.fs);
1755 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1756 load_gs_index(svm->host.gs);
1757 #else
1758 #ifdef CONFIG_X86_32_LAZY_GS
1759 loadsegment(gs, svm->host.gs);
1760 #endif
1761 #endif
1762 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1763 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1764 }
1765
1766 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1767 {
1768 avic_set_running(vcpu, false);
1769 }
1770
1771 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1772 {
1773 avic_set_running(vcpu, true);
1774 }
1775
1776 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1777 {
1778 struct vcpu_svm *svm = to_svm(vcpu);
1779 unsigned long rflags = svm->vmcb->save.rflags;
1780
1781 if (svm->nmi_singlestep) {
1782 /* Hide our flags if they were not set by the guest */
1783 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1784 rflags &= ~X86_EFLAGS_TF;
1785 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1786 rflags &= ~X86_EFLAGS_RF;
1787 }
1788 return rflags;
1789 }
1790
1791 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1792 {
1793 if (to_svm(vcpu)->nmi_singlestep)
1794 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1795
1796 /*
1797 * Any change of EFLAGS.VM is accompanied by a reload of SS
1798 * (caused by either a task switch or an inter-privilege IRET),
1799 * so we do not need to update the CPL here.
1800 */
1801 to_svm(vcpu)->vmcb->save.rflags = rflags;
1802 }
1803
1804 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1805 {
1806 switch (reg) {
1807 case VCPU_EXREG_PDPTR:
1808 BUG_ON(!npt_enabled);
1809 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1810 break;
1811 default:
1812 BUG();
1813 }
1814 }
1815
1816 static void svm_set_vintr(struct vcpu_svm *svm)
1817 {
1818 set_intercept(svm, INTERCEPT_VINTR);
1819 }
1820
1821 static void svm_clear_vintr(struct vcpu_svm *svm)
1822 {
1823 clr_intercept(svm, INTERCEPT_VINTR);
1824 }
1825
1826 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1827 {
1828 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1829
1830 switch (seg) {
1831 case VCPU_SREG_CS: return &save->cs;
1832 case VCPU_SREG_DS: return &save->ds;
1833 case VCPU_SREG_ES: return &save->es;
1834 case VCPU_SREG_FS: return &save->fs;
1835 case VCPU_SREG_GS: return &save->gs;
1836 case VCPU_SREG_SS: return &save->ss;
1837 case VCPU_SREG_TR: return &save->tr;
1838 case VCPU_SREG_LDTR: return &save->ldtr;
1839 }
1840 BUG();
1841 return NULL;
1842 }
1843
1844 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1845 {
1846 struct vmcb_seg *s = svm_seg(vcpu, seg);
1847
1848 return s->base;
1849 }
1850
1851 static void svm_get_segment(struct kvm_vcpu *vcpu,
1852 struct kvm_segment *var, int seg)
1853 {
1854 struct vmcb_seg *s = svm_seg(vcpu, seg);
1855
1856 var->base = s->base;
1857 var->limit = s->limit;
1858 var->selector = s->selector;
1859 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1860 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1861 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1862 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1863 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1864 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1865 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1866
1867 /*
1868 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1869 * However, the SVM spec states that the G bit is not observed by the
1870 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1871 * So let's synthesize a legal G bit for all segments, this helps
1872 * running KVM nested. It also helps cross-vendor migration, because
1873 * Intel's vmentry has a check on the 'G' bit.
1874 */
1875 var->g = s->limit > 0xfffff;
1876
1877 /*
1878 * AMD's VMCB does not have an explicit unusable field, so emulate it
1879 * for cross vendor migration purposes by "not present"
1880 */
1881 var->unusable = !var->present;
1882
1883 switch (seg) {
1884 case VCPU_SREG_TR:
1885 /*
1886 * Work around a bug where the busy flag in the tr selector
1887 * isn't exposed
1888 */
1889 var->type |= 0x2;
1890 break;
1891 case VCPU_SREG_DS:
1892 case VCPU_SREG_ES:
1893 case VCPU_SREG_FS:
1894 case VCPU_SREG_GS:
1895 /*
1896 * The accessed bit must always be set in the segment
1897 * descriptor cache, although it can be cleared in the
1898 * descriptor, the cached bit always remains at 1. Since
1899 * Intel has a check on this, set it here to support
1900 * cross-vendor migration.
1901 */
1902 if (!var->unusable)
1903 var->type |= 0x1;
1904 break;
1905 case VCPU_SREG_SS:
1906 /*
1907 * On AMD CPUs sometimes the DB bit in the segment
1908 * descriptor is left as 1, although the whole segment has
1909 * been made unusable. Clear it here to pass an Intel VMX
1910 * entry check when cross vendor migrating.
1911 */
1912 if (var->unusable)
1913 var->db = 0;
1914 /* This is symmetric with svm_set_segment() */
1915 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1916 break;
1917 }
1918 }
1919
1920 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1921 {
1922 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1923
1924 return save->cpl;
1925 }
1926
1927 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1928 {
1929 struct vcpu_svm *svm = to_svm(vcpu);
1930
1931 dt->size = svm->vmcb->save.idtr.limit;
1932 dt->address = svm->vmcb->save.idtr.base;
1933 }
1934
1935 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1936 {
1937 struct vcpu_svm *svm = to_svm(vcpu);
1938
1939 svm->vmcb->save.idtr.limit = dt->size;
1940 svm->vmcb->save.idtr.base = dt->address ;
1941 mark_dirty(svm->vmcb, VMCB_DT);
1942 }
1943
1944 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1945 {
1946 struct vcpu_svm *svm = to_svm(vcpu);
1947
1948 dt->size = svm->vmcb->save.gdtr.limit;
1949 dt->address = svm->vmcb->save.gdtr.base;
1950 }
1951
1952 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1953 {
1954 struct vcpu_svm *svm = to_svm(vcpu);
1955
1956 svm->vmcb->save.gdtr.limit = dt->size;
1957 svm->vmcb->save.gdtr.base = dt->address ;
1958 mark_dirty(svm->vmcb, VMCB_DT);
1959 }
1960
1961 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1962 {
1963 }
1964
1965 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1966 {
1967 }
1968
1969 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1970 {
1971 }
1972
1973 static void update_cr0_intercept(struct vcpu_svm *svm)
1974 {
1975 ulong gcr0 = svm->vcpu.arch.cr0;
1976 u64 *hcr0 = &svm->vmcb->save.cr0;
1977
1978 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1979 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1980
1981 mark_dirty(svm->vmcb, VMCB_CR);
1982
1983 if (gcr0 == *hcr0) {
1984 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1985 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1986 } else {
1987 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1988 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1989 }
1990 }
1991
1992 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1993 {
1994 struct vcpu_svm *svm = to_svm(vcpu);
1995
1996 #ifdef CONFIG_X86_64
1997 if (vcpu->arch.efer & EFER_LME) {
1998 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1999 vcpu->arch.efer |= EFER_LMA;
2000 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
2001 }
2002
2003 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
2004 vcpu->arch.efer &= ~EFER_LMA;
2005 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
2006 }
2007 }
2008 #endif
2009 vcpu->arch.cr0 = cr0;
2010
2011 if (!npt_enabled)
2012 cr0 |= X86_CR0_PG | X86_CR0_WP;
2013
2014 /*
2015 * re-enable caching here because the QEMU bios
2016 * does not do it - this results in some delay at
2017 * reboot
2018 */
2019 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2020 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2021 svm->vmcb->save.cr0 = cr0;
2022 mark_dirty(svm->vmcb, VMCB_CR);
2023 update_cr0_intercept(svm);
2024 }
2025
2026 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2027 {
2028 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2029 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2030
2031 if (cr4 & X86_CR4_VMXE)
2032 return 1;
2033
2034 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2035 svm_flush_tlb(vcpu);
2036
2037 vcpu->arch.cr4 = cr4;
2038 if (!npt_enabled)
2039 cr4 |= X86_CR4_PAE;
2040 cr4 |= host_cr4_mce;
2041 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2042 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2043 return 0;
2044 }
2045
2046 static void svm_set_segment(struct kvm_vcpu *vcpu,
2047 struct kvm_segment *var, int seg)
2048 {
2049 struct vcpu_svm *svm = to_svm(vcpu);
2050 struct vmcb_seg *s = svm_seg(vcpu, seg);
2051
2052 s->base = var->base;
2053 s->limit = var->limit;
2054 s->selector = var->selector;
2055 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2056 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2057 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2058 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2059 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2060 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2061 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2062 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2063
2064 /*
2065 * This is always accurate, except if SYSRET returned to a segment
2066 * with SS.DPL != 3. Intel does not have this quirk, and always
2067 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2068 * would entail passing the CPL to userspace and back.
2069 */
2070 if (seg == VCPU_SREG_SS)
2071 /* This is symmetric with svm_get_segment() */
2072 svm->vmcb->save.cpl = (var->dpl & 3);
2073
2074 mark_dirty(svm->vmcb, VMCB_SEG);
2075 }
2076
2077 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2078 {
2079 struct vcpu_svm *svm = to_svm(vcpu);
2080
2081 clr_exception_intercept(svm, BP_VECTOR);
2082
2083 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2084 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2085 set_exception_intercept(svm, BP_VECTOR);
2086 } else
2087 vcpu->guest_debug = 0;
2088 }
2089
2090 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2091 {
2092 if (sd->next_asid > sd->max_asid) {
2093 ++sd->asid_generation;
2094 sd->next_asid = 1;
2095 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2096 }
2097
2098 svm->asid_generation = sd->asid_generation;
2099 svm->vmcb->control.asid = sd->next_asid++;
2100
2101 mark_dirty(svm->vmcb, VMCB_ASID);
2102 }
2103
2104 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2105 {
2106 return to_svm(vcpu)->vmcb->save.dr6;
2107 }
2108
2109 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2110 {
2111 struct vcpu_svm *svm = to_svm(vcpu);
2112
2113 svm->vmcb->save.dr6 = value;
2114 mark_dirty(svm->vmcb, VMCB_DR);
2115 }
2116
2117 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2118 {
2119 struct vcpu_svm *svm = to_svm(vcpu);
2120
2121 get_debugreg(vcpu->arch.db[0], 0);
2122 get_debugreg(vcpu->arch.db[1], 1);
2123 get_debugreg(vcpu->arch.db[2], 2);
2124 get_debugreg(vcpu->arch.db[3], 3);
2125 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2126 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2127
2128 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2129 set_dr_intercepts(svm);
2130 }
2131
2132 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2133 {
2134 struct vcpu_svm *svm = to_svm(vcpu);
2135
2136 svm->vmcb->save.dr7 = value;
2137 mark_dirty(svm->vmcb, VMCB_DR);
2138 }
2139
2140 static int pf_interception(struct vcpu_svm *svm)
2141 {
2142 u64 fault_address = svm->vmcb->control.exit_info_2;
2143 u64 error_code = svm->vmcb->control.exit_info_1;
2144
2145 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2146 svm->vmcb->control.insn_bytes,
2147 svm->vmcb->control.insn_len, !npt_enabled);
2148 }
2149
2150 static int db_interception(struct vcpu_svm *svm)
2151 {
2152 struct kvm_run *kvm_run = svm->vcpu.run;
2153
2154 if (!(svm->vcpu.guest_debug &
2155 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2156 !svm->nmi_singlestep) {
2157 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2158 return 1;
2159 }
2160
2161 if (svm->nmi_singlestep) {
2162 disable_nmi_singlestep(svm);
2163 }
2164
2165 if (svm->vcpu.guest_debug &
2166 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2167 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2168 kvm_run->debug.arch.pc =
2169 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2170 kvm_run->debug.arch.exception = DB_VECTOR;
2171 return 0;
2172 }
2173
2174 return 1;
2175 }
2176
2177 static int bp_interception(struct vcpu_svm *svm)
2178 {
2179 struct kvm_run *kvm_run = svm->vcpu.run;
2180
2181 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2182 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2183 kvm_run->debug.arch.exception = BP_VECTOR;
2184 return 0;
2185 }
2186
2187 static int ud_interception(struct vcpu_svm *svm)
2188 {
2189 int er;
2190
2191 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2192 if (er != EMULATE_DONE)
2193 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2194 return 1;
2195 }
2196
2197 static int ac_interception(struct vcpu_svm *svm)
2198 {
2199 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2200 return 1;
2201 }
2202
2203 static bool is_erratum_383(void)
2204 {
2205 int err, i;
2206 u64 value;
2207
2208 if (!erratum_383_found)
2209 return false;
2210
2211 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2212 if (err)
2213 return false;
2214
2215 /* Bit 62 may or may not be set for this mce */
2216 value &= ~(1ULL << 62);
2217
2218 if (value != 0xb600000000010015ULL)
2219 return false;
2220
2221 /* Clear MCi_STATUS registers */
2222 for (i = 0; i < 6; ++i)
2223 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2224
2225 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2226 if (!err) {
2227 u32 low, high;
2228
2229 value &= ~(1ULL << 2);
2230 low = lower_32_bits(value);
2231 high = upper_32_bits(value);
2232
2233 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2234 }
2235
2236 /* Flush tlb to evict multi-match entries */
2237 __flush_tlb_all();
2238
2239 return true;
2240 }
2241
2242 static void svm_handle_mce(struct vcpu_svm *svm)
2243 {
2244 if (is_erratum_383()) {
2245 /*
2246 * Erratum 383 triggered. Guest state is corrupt so kill the
2247 * guest.
2248 */
2249 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2250
2251 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2252
2253 return;
2254 }
2255
2256 /*
2257 * On an #MC intercept the MCE handler is not called automatically in
2258 * the host. So do it by hand here.
2259 */
2260 asm volatile (
2261 "int $0x12\n");
2262 /* not sure if we ever come back to this point */
2263
2264 return;
2265 }
2266
2267 static int mc_interception(struct vcpu_svm *svm)
2268 {
2269 return 1;
2270 }
2271
2272 static int shutdown_interception(struct vcpu_svm *svm)
2273 {
2274 struct kvm_run *kvm_run = svm->vcpu.run;
2275
2276 /*
2277 * VMCB is undefined after a SHUTDOWN intercept
2278 * so reinitialize it.
2279 */
2280 clear_page(svm->vmcb);
2281 init_vmcb(svm);
2282
2283 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2284 return 0;
2285 }
2286
2287 static int io_interception(struct vcpu_svm *svm)
2288 {
2289 struct kvm_vcpu *vcpu = &svm->vcpu;
2290 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2291 int size, in, string, ret;
2292 unsigned port;
2293
2294 ++svm->vcpu.stat.io_exits;
2295 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2296 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2297 if (string)
2298 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2299
2300 port = io_info >> 16;
2301 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2302 svm->next_rip = svm->vmcb->control.exit_info_2;
2303 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2304
2305 /*
2306 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2307 * KVM_EXIT_DEBUG here.
2308 */
2309 if (in)
2310 return kvm_fast_pio_in(vcpu, size, port) && ret;
2311 else
2312 return kvm_fast_pio_out(vcpu, size, port) && ret;
2313 }
2314
2315 static int nmi_interception(struct vcpu_svm *svm)
2316 {
2317 return 1;
2318 }
2319
2320 static int intr_interception(struct vcpu_svm *svm)
2321 {
2322 ++svm->vcpu.stat.irq_exits;
2323 return 1;
2324 }
2325
2326 static int nop_on_interception(struct vcpu_svm *svm)
2327 {
2328 return 1;
2329 }
2330
2331 static int halt_interception(struct vcpu_svm *svm)
2332 {
2333 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2334 return kvm_emulate_halt(&svm->vcpu);
2335 }
2336
2337 static int vmmcall_interception(struct vcpu_svm *svm)
2338 {
2339 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2340 return kvm_emulate_hypercall(&svm->vcpu);
2341 }
2342
2343 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2344 {
2345 struct vcpu_svm *svm = to_svm(vcpu);
2346
2347 return svm->nested.nested_cr3;
2348 }
2349
2350 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2351 {
2352 struct vcpu_svm *svm = to_svm(vcpu);
2353 u64 cr3 = svm->nested.nested_cr3;
2354 u64 pdpte;
2355 int ret;
2356
2357 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2358 offset_in_page(cr3) + index * 8, 8);
2359 if (ret)
2360 return 0;
2361 return pdpte;
2362 }
2363
2364 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2365 unsigned long root)
2366 {
2367 struct vcpu_svm *svm = to_svm(vcpu);
2368
2369 svm->vmcb->control.nested_cr3 = __sme_set(root);
2370 mark_dirty(svm->vmcb, VMCB_NPT);
2371 svm_flush_tlb(vcpu);
2372 }
2373
2374 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2375 struct x86_exception *fault)
2376 {
2377 struct vcpu_svm *svm = to_svm(vcpu);
2378
2379 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2380 /*
2381 * TODO: track the cause of the nested page fault, and
2382 * correctly fill in the high bits of exit_info_1.
2383 */
2384 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2385 svm->vmcb->control.exit_code_hi = 0;
2386 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2387 svm->vmcb->control.exit_info_2 = fault->address;
2388 }
2389
2390 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2391 svm->vmcb->control.exit_info_1 |= fault->error_code;
2392
2393 /*
2394 * The present bit is always zero for page structure faults on real
2395 * hardware.
2396 */
2397 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2398 svm->vmcb->control.exit_info_1 &= ~1;
2399
2400 nested_svm_vmexit(svm);
2401 }
2402
2403 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2404 {
2405 WARN_ON(mmu_is_nested(vcpu));
2406 kvm_init_shadow_mmu(vcpu);
2407 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2408 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2409 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2410 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2411 vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2412 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2413 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2414 }
2415
2416 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2417 {
2418 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2419 }
2420
2421 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2422 {
2423 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2424 !is_paging(&svm->vcpu)) {
2425 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2426 return 1;
2427 }
2428
2429 if (svm->vmcb->save.cpl) {
2430 kvm_inject_gp(&svm->vcpu, 0);
2431 return 1;
2432 }
2433
2434 return 0;
2435 }
2436
2437 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2438 bool has_error_code, u32 error_code)
2439 {
2440 int vmexit;
2441
2442 if (!is_guest_mode(&svm->vcpu))
2443 return 0;
2444
2445 vmexit = nested_svm_intercept(svm);
2446 if (vmexit != NESTED_EXIT_DONE)
2447 return 0;
2448
2449 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2450 svm->vmcb->control.exit_code_hi = 0;
2451 svm->vmcb->control.exit_info_1 = error_code;
2452
2453 /*
2454 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2455 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2456 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2457 * written only when inject_pending_event runs (DR6 would written here
2458 * too). This should be conditional on a new capability---if the
2459 * capability is disabled, kvm_multiple_exception would write the
2460 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2461 */
2462 if (svm->vcpu.arch.exception.nested_apf)
2463 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2464 else
2465 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2466
2467 svm->nested.exit_required = true;
2468 return vmexit;
2469 }
2470
2471 /* This function returns true if it is save to enable the irq window */
2472 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2473 {
2474 if (!is_guest_mode(&svm->vcpu))
2475 return true;
2476
2477 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2478 return true;
2479
2480 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2481 return false;
2482
2483 /*
2484 * if vmexit was already requested (by intercepted exception
2485 * for instance) do not overwrite it with "external interrupt"
2486 * vmexit.
2487 */
2488 if (svm->nested.exit_required)
2489 return false;
2490
2491 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2492 svm->vmcb->control.exit_info_1 = 0;
2493 svm->vmcb->control.exit_info_2 = 0;
2494
2495 if (svm->nested.intercept & 1ULL) {
2496 /*
2497 * The #vmexit can't be emulated here directly because this
2498 * code path runs with irqs and preemption disabled. A
2499 * #vmexit emulation might sleep. Only signal request for
2500 * the #vmexit here.
2501 */
2502 svm->nested.exit_required = true;
2503 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2504 return false;
2505 }
2506
2507 return true;
2508 }
2509
2510 /* This function returns true if it is save to enable the nmi window */
2511 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2512 {
2513 if (!is_guest_mode(&svm->vcpu))
2514 return true;
2515
2516 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2517 return true;
2518
2519 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2520 svm->nested.exit_required = true;
2521
2522 return false;
2523 }
2524
2525 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2526 {
2527 struct page *page;
2528
2529 might_sleep();
2530
2531 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2532 if (is_error_page(page))
2533 goto error;
2534
2535 *_page = page;
2536
2537 return kmap(page);
2538
2539 error:
2540 kvm_inject_gp(&svm->vcpu, 0);
2541
2542 return NULL;
2543 }
2544
2545 static void nested_svm_unmap(struct page *page)
2546 {
2547 kunmap(page);
2548 kvm_release_page_dirty(page);
2549 }
2550
2551 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2552 {
2553 unsigned port, size, iopm_len;
2554 u16 val, mask;
2555 u8 start_bit;
2556 u64 gpa;
2557
2558 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2559 return NESTED_EXIT_HOST;
2560
2561 port = svm->vmcb->control.exit_info_1 >> 16;
2562 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2563 SVM_IOIO_SIZE_SHIFT;
2564 gpa = svm->nested.vmcb_iopm + (port / 8);
2565 start_bit = port % 8;
2566 iopm_len = (start_bit + size > 8) ? 2 : 1;
2567 mask = (0xf >> (4 - size)) << start_bit;
2568 val = 0;
2569
2570 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2571 return NESTED_EXIT_DONE;
2572
2573 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2574 }
2575
2576 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2577 {
2578 u32 offset, msr, value;
2579 int write, mask;
2580
2581 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2582 return NESTED_EXIT_HOST;
2583
2584 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2585 offset = svm_msrpm_offset(msr);
2586 write = svm->vmcb->control.exit_info_1 & 1;
2587 mask = 1 << ((2 * (msr & 0xf)) + write);
2588
2589 if (offset == MSR_INVALID)
2590 return NESTED_EXIT_DONE;
2591
2592 /* Offset is in 32 bit units but need in 8 bit units */
2593 offset *= 4;
2594
2595 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2596 return NESTED_EXIT_DONE;
2597
2598 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2599 }
2600
2601 /* DB exceptions for our internal use must not cause vmexit */
2602 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2603 {
2604 unsigned long dr6;
2605
2606 /* if we're not singlestepping, it's not ours */
2607 if (!svm->nmi_singlestep)
2608 return NESTED_EXIT_DONE;
2609
2610 /* if it's not a singlestep exception, it's not ours */
2611 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2612 return NESTED_EXIT_DONE;
2613 if (!(dr6 & DR6_BS))
2614 return NESTED_EXIT_DONE;
2615
2616 /* if the guest is singlestepping, it should get the vmexit */
2617 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2618 disable_nmi_singlestep(svm);
2619 return NESTED_EXIT_DONE;
2620 }
2621
2622 /* it's ours, the nested hypervisor must not see this one */
2623 return NESTED_EXIT_HOST;
2624 }
2625
2626 static int nested_svm_exit_special(struct vcpu_svm *svm)
2627 {
2628 u32 exit_code = svm->vmcb->control.exit_code;
2629
2630 switch (exit_code) {
2631 case SVM_EXIT_INTR:
2632 case SVM_EXIT_NMI:
2633 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2634 return NESTED_EXIT_HOST;
2635 case SVM_EXIT_NPF:
2636 /* For now we are always handling NPFs when using them */
2637 if (npt_enabled)
2638 return NESTED_EXIT_HOST;
2639 break;
2640 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2641 /* When we're shadowing, trap PFs, but not async PF */
2642 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2643 return NESTED_EXIT_HOST;
2644 break;
2645 default:
2646 break;
2647 }
2648
2649 return NESTED_EXIT_CONTINUE;
2650 }
2651
2652 /*
2653 * If this function returns true, this #vmexit was already handled
2654 */
2655 static int nested_svm_intercept(struct vcpu_svm *svm)
2656 {
2657 u32 exit_code = svm->vmcb->control.exit_code;
2658 int vmexit = NESTED_EXIT_HOST;
2659
2660 switch (exit_code) {
2661 case SVM_EXIT_MSR:
2662 vmexit = nested_svm_exit_handled_msr(svm);
2663 break;
2664 case SVM_EXIT_IOIO:
2665 vmexit = nested_svm_intercept_ioio(svm);
2666 break;
2667 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2668 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2669 if (svm->nested.intercept_cr & bit)
2670 vmexit = NESTED_EXIT_DONE;
2671 break;
2672 }
2673 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2674 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2675 if (svm->nested.intercept_dr & bit)
2676 vmexit = NESTED_EXIT_DONE;
2677 break;
2678 }
2679 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2680 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2681 if (svm->nested.intercept_exceptions & excp_bits) {
2682 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2683 vmexit = nested_svm_intercept_db(svm);
2684 else
2685 vmexit = NESTED_EXIT_DONE;
2686 }
2687 /* async page fault always cause vmexit */
2688 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2689 svm->vcpu.arch.exception.nested_apf != 0)
2690 vmexit = NESTED_EXIT_DONE;
2691 break;
2692 }
2693 case SVM_EXIT_ERR: {
2694 vmexit = NESTED_EXIT_DONE;
2695 break;
2696 }
2697 default: {
2698 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2699 if (svm->nested.intercept & exit_bits)
2700 vmexit = NESTED_EXIT_DONE;
2701 }
2702 }
2703
2704 return vmexit;
2705 }
2706
2707 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2708 {
2709 int vmexit;
2710
2711 vmexit = nested_svm_intercept(svm);
2712
2713 if (vmexit == NESTED_EXIT_DONE)
2714 nested_svm_vmexit(svm);
2715
2716 return vmexit;
2717 }
2718
2719 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2720 {
2721 struct vmcb_control_area *dst = &dst_vmcb->control;
2722 struct vmcb_control_area *from = &from_vmcb->control;
2723
2724 dst->intercept_cr = from->intercept_cr;
2725 dst->intercept_dr = from->intercept_dr;
2726 dst->intercept_exceptions = from->intercept_exceptions;
2727 dst->intercept = from->intercept;
2728 dst->iopm_base_pa = from->iopm_base_pa;
2729 dst->msrpm_base_pa = from->msrpm_base_pa;
2730 dst->tsc_offset = from->tsc_offset;
2731 dst->asid = from->asid;
2732 dst->tlb_ctl = from->tlb_ctl;
2733 dst->int_ctl = from->int_ctl;
2734 dst->int_vector = from->int_vector;
2735 dst->int_state = from->int_state;
2736 dst->exit_code = from->exit_code;
2737 dst->exit_code_hi = from->exit_code_hi;
2738 dst->exit_info_1 = from->exit_info_1;
2739 dst->exit_info_2 = from->exit_info_2;
2740 dst->exit_int_info = from->exit_int_info;
2741 dst->exit_int_info_err = from->exit_int_info_err;
2742 dst->nested_ctl = from->nested_ctl;
2743 dst->event_inj = from->event_inj;
2744 dst->event_inj_err = from->event_inj_err;
2745 dst->nested_cr3 = from->nested_cr3;
2746 dst->virt_ext = from->virt_ext;
2747 }
2748
2749 static int nested_svm_vmexit(struct vcpu_svm *svm)
2750 {
2751 struct vmcb *nested_vmcb;
2752 struct vmcb *hsave = svm->nested.hsave;
2753 struct vmcb *vmcb = svm->vmcb;
2754 struct page *page;
2755
2756 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2757 vmcb->control.exit_info_1,
2758 vmcb->control.exit_info_2,
2759 vmcb->control.exit_int_info,
2760 vmcb->control.exit_int_info_err,
2761 KVM_ISA_SVM);
2762
2763 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2764 if (!nested_vmcb)
2765 return 1;
2766
2767 /* Exit Guest-Mode */
2768 leave_guest_mode(&svm->vcpu);
2769 svm->nested.vmcb = 0;
2770
2771 /* Give the current vmcb to the guest */
2772 disable_gif(svm);
2773
2774 nested_vmcb->save.es = vmcb->save.es;
2775 nested_vmcb->save.cs = vmcb->save.cs;
2776 nested_vmcb->save.ss = vmcb->save.ss;
2777 nested_vmcb->save.ds = vmcb->save.ds;
2778 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2779 nested_vmcb->save.idtr = vmcb->save.idtr;
2780 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2781 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2782 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2783 nested_vmcb->save.cr2 = vmcb->save.cr2;
2784 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2785 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2786 nested_vmcb->save.rip = vmcb->save.rip;
2787 nested_vmcb->save.rsp = vmcb->save.rsp;
2788 nested_vmcb->save.rax = vmcb->save.rax;
2789 nested_vmcb->save.dr7 = vmcb->save.dr7;
2790 nested_vmcb->save.dr6 = vmcb->save.dr6;
2791 nested_vmcb->save.cpl = vmcb->save.cpl;
2792
2793 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2794 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2795 nested_vmcb->control.int_state = vmcb->control.int_state;
2796 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2797 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2798 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2799 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2800 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2801 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2802
2803 if (svm->nrips_enabled)
2804 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2805
2806 /*
2807 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2808 * to make sure that we do not lose injected events. So check event_inj
2809 * here and copy it to exit_int_info if it is valid.
2810 * Exit_int_info and event_inj can't be both valid because the case
2811 * below only happens on a VMRUN instruction intercept which has
2812 * no valid exit_int_info set.
2813 */
2814 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2815 struct vmcb_control_area *nc = &nested_vmcb->control;
2816
2817 nc->exit_int_info = vmcb->control.event_inj;
2818 nc->exit_int_info_err = vmcb->control.event_inj_err;
2819 }
2820
2821 nested_vmcb->control.tlb_ctl = 0;
2822 nested_vmcb->control.event_inj = 0;
2823 nested_vmcb->control.event_inj_err = 0;
2824
2825 /* We always set V_INTR_MASKING and remember the old value in hflags */
2826 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2827 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2828
2829 /* Restore the original control entries */
2830 copy_vmcb_control_area(vmcb, hsave);
2831
2832 kvm_clear_exception_queue(&svm->vcpu);
2833 kvm_clear_interrupt_queue(&svm->vcpu);
2834
2835 svm->nested.nested_cr3 = 0;
2836
2837 /* Restore selected save entries */
2838 svm->vmcb->save.es = hsave->save.es;
2839 svm->vmcb->save.cs = hsave->save.cs;
2840 svm->vmcb->save.ss = hsave->save.ss;
2841 svm->vmcb->save.ds = hsave->save.ds;
2842 svm->vmcb->save.gdtr = hsave->save.gdtr;
2843 svm->vmcb->save.idtr = hsave->save.idtr;
2844 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2845 svm_set_efer(&svm->vcpu, hsave->save.efer);
2846 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2847 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2848 if (npt_enabled) {
2849 svm->vmcb->save.cr3 = hsave->save.cr3;
2850 svm->vcpu.arch.cr3 = hsave->save.cr3;
2851 } else {
2852 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2853 }
2854 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2855 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2856 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2857 svm->vmcb->save.dr7 = 0;
2858 svm->vmcb->save.cpl = 0;
2859 svm->vmcb->control.exit_int_info = 0;
2860
2861 mark_all_dirty(svm->vmcb);
2862
2863 nested_svm_unmap(page);
2864
2865 nested_svm_uninit_mmu_context(&svm->vcpu);
2866 kvm_mmu_reset_context(&svm->vcpu);
2867 kvm_mmu_load(&svm->vcpu);
2868
2869 return 0;
2870 }
2871
2872 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2873 {
2874 /*
2875 * This function merges the msr permission bitmaps of kvm and the
2876 * nested vmcb. It is optimized in that it only merges the parts where
2877 * the kvm msr permission bitmap may contain zero bits
2878 */
2879 int i;
2880
2881 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2882 return true;
2883
2884 for (i = 0; i < MSRPM_OFFSETS; i++) {
2885 u32 value, p;
2886 u64 offset;
2887
2888 if (msrpm_offsets[i] == 0xffffffff)
2889 break;
2890
2891 p = msrpm_offsets[i];
2892 offset = svm->nested.vmcb_msrpm + (p * 4);
2893
2894 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2895 return false;
2896
2897 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2898 }
2899
2900 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
2901
2902 return true;
2903 }
2904
2905 static bool nested_vmcb_checks(struct vmcb *vmcb)
2906 {
2907 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2908 return false;
2909
2910 if (vmcb->control.asid == 0)
2911 return false;
2912
2913 if (vmcb->control.nested_ctl && !npt_enabled)
2914 return false;
2915
2916 return true;
2917 }
2918
2919 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2920 {
2921 struct vmcb *nested_vmcb;
2922 struct vmcb *hsave = svm->nested.hsave;
2923 struct vmcb *vmcb = svm->vmcb;
2924 struct page *page;
2925 u64 vmcb_gpa;
2926
2927 vmcb_gpa = svm->vmcb->save.rax;
2928
2929 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2930 if (!nested_vmcb)
2931 return false;
2932
2933 if (!nested_vmcb_checks(nested_vmcb)) {
2934 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2935 nested_vmcb->control.exit_code_hi = 0;
2936 nested_vmcb->control.exit_info_1 = 0;
2937 nested_vmcb->control.exit_info_2 = 0;
2938
2939 nested_svm_unmap(page);
2940
2941 return false;
2942 }
2943
2944 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2945 nested_vmcb->save.rip,
2946 nested_vmcb->control.int_ctl,
2947 nested_vmcb->control.event_inj,
2948 nested_vmcb->control.nested_ctl);
2949
2950 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2951 nested_vmcb->control.intercept_cr >> 16,
2952 nested_vmcb->control.intercept_exceptions,
2953 nested_vmcb->control.intercept);
2954
2955 /* Clear internal status */
2956 kvm_clear_exception_queue(&svm->vcpu);
2957 kvm_clear_interrupt_queue(&svm->vcpu);
2958
2959 /*
2960 * Save the old vmcb, so we don't need to pick what we save, but can
2961 * restore everything when a VMEXIT occurs
2962 */
2963 hsave->save.es = vmcb->save.es;
2964 hsave->save.cs = vmcb->save.cs;
2965 hsave->save.ss = vmcb->save.ss;
2966 hsave->save.ds = vmcb->save.ds;
2967 hsave->save.gdtr = vmcb->save.gdtr;
2968 hsave->save.idtr = vmcb->save.idtr;
2969 hsave->save.efer = svm->vcpu.arch.efer;
2970 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2971 hsave->save.cr4 = svm->vcpu.arch.cr4;
2972 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2973 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2974 hsave->save.rsp = vmcb->save.rsp;
2975 hsave->save.rax = vmcb->save.rax;
2976 if (npt_enabled)
2977 hsave->save.cr3 = vmcb->save.cr3;
2978 else
2979 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2980
2981 copy_vmcb_control_area(hsave, vmcb);
2982
2983 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2984 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2985 else
2986 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2987
2988 if (nested_vmcb->control.nested_ctl) {
2989 kvm_mmu_unload(&svm->vcpu);
2990 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2991 nested_svm_init_mmu_context(&svm->vcpu);
2992 }
2993
2994 /* Load the nested guest state */
2995 svm->vmcb->save.es = nested_vmcb->save.es;
2996 svm->vmcb->save.cs = nested_vmcb->save.cs;
2997 svm->vmcb->save.ss = nested_vmcb->save.ss;
2998 svm->vmcb->save.ds = nested_vmcb->save.ds;
2999 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
3000 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
3001 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
3002 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
3003 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
3004 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
3005 if (npt_enabled) {
3006 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
3007 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
3008 } else
3009 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
3010
3011 /* Guest paging mode is active - reset mmu */
3012 kvm_mmu_reset_context(&svm->vcpu);
3013
3014 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3015 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3016 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3017 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3018
3019 /* In case we don't even reach vcpu_run, the fields are not updated */
3020 svm->vmcb->save.rax = nested_vmcb->save.rax;
3021 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3022 svm->vmcb->save.rip = nested_vmcb->save.rip;
3023 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3024 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3025 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3026
3027 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3028 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3029
3030 /* cache intercepts */
3031 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3032 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3033 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3034 svm->nested.intercept = nested_vmcb->control.intercept;
3035
3036 svm_flush_tlb(&svm->vcpu);
3037 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3038 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3039 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3040 else
3041 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3042
3043 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3044 /* We only want the cr8 intercept bits of the guest */
3045 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3046 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3047 }
3048
3049 /* We don't want to see VMMCALLs from a nested guest */
3050 clr_intercept(svm, INTERCEPT_VMMCALL);
3051
3052 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3053 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3054 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3055 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3056 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3057 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3058
3059 nested_svm_unmap(page);
3060
3061 /* Enter Guest-Mode */
3062 enter_guest_mode(&svm->vcpu);
3063
3064 /*
3065 * Merge guest and host intercepts - must be called with vcpu in
3066 * guest-mode to take affect here
3067 */
3068 recalc_intercepts(svm);
3069
3070 svm->nested.vmcb = vmcb_gpa;
3071
3072 enable_gif(svm);
3073
3074 mark_all_dirty(svm->vmcb);
3075
3076 return true;
3077 }
3078
3079 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3080 {
3081 to_vmcb->save.fs = from_vmcb->save.fs;
3082 to_vmcb->save.gs = from_vmcb->save.gs;
3083 to_vmcb->save.tr = from_vmcb->save.tr;
3084 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3085 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3086 to_vmcb->save.star = from_vmcb->save.star;
3087 to_vmcb->save.lstar = from_vmcb->save.lstar;
3088 to_vmcb->save.cstar = from_vmcb->save.cstar;
3089 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3090 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3091 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3092 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3093 }
3094
3095 static int vmload_interception(struct vcpu_svm *svm)
3096 {
3097 struct vmcb *nested_vmcb;
3098 struct page *page;
3099 int ret;
3100
3101 if (nested_svm_check_permissions(svm))
3102 return 1;
3103
3104 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3105 if (!nested_vmcb)
3106 return 1;
3107
3108 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3109 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3110
3111 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3112 nested_svm_unmap(page);
3113
3114 return ret;
3115 }
3116
3117 static int vmsave_interception(struct vcpu_svm *svm)
3118 {
3119 struct vmcb *nested_vmcb;
3120 struct page *page;
3121 int ret;
3122
3123 if (nested_svm_check_permissions(svm))
3124 return 1;
3125
3126 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3127 if (!nested_vmcb)
3128 return 1;
3129
3130 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3131 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3132
3133 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3134 nested_svm_unmap(page);
3135
3136 return ret;
3137 }
3138
3139 static int vmrun_interception(struct vcpu_svm *svm)
3140 {
3141 if (nested_svm_check_permissions(svm))
3142 return 1;
3143
3144 /* Save rip after vmrun instruction */
3145 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3146
3147 if (!nested_svm_vmrun(svm))
3148 return 1;
3149
3150 if (!nested_svm_vmrun_msrpm(svm))
3151 goto failed;
3152
3153 return 1;
3154
3155 failed:
3156
3157 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3158 svm->vmcb->control.exit_code_hi = 0;
3159 svm->vmcb->control.exit_info_1 = 0;
3160 svm->vmcb->control.exit_info_2 = 0;
3161
3162 nested_svm_vmexit(svm);
3163
3164 return 1;
3165 }
3166
3167 static int stgi_interception(struct vcpu_svm *svm)
3168 {
3169 int ret;
3170
3171 if (nested_svm_check_permissions(svm))
3172 return 1;
3173
3174 /*
3175 * If VGIF is enabled, the STGI intercept is only added to
3176 * detect the opening of the NMI window; remove it now.
3177 */
3178 if (vgif_enabled(svm))
3179 clr_intercept(svm, INTERCEPT_STGI);
3180
3181 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3182 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3183 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3184
3185 enable_gif(svm);
3186
3187 return ret;
3188 }
3189
3190 static int clgi_interception(struct vcpu_svm *svm)
3191 {
3192 int ret;
3193
3194 if (nested_svm_check_permissions(svm))
3195 return 1;
3196
3197 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3198 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3199
3200 disable_gif(svm);
3201
3202 /* After a CLGI no interrupts should come */
3203 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3204 svm_clear_vintr(svm);
3205 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3206 mark_dirty(svm->vmcb, VMCB_INTR);
3207 }
3208
3209 return ret;
3210 }
3211
3212 static int invlpga_interception(struct vcpu_svm *svm)
3213 {
3214 struct kvm_vcpu *vcpu = &svm->vcpu;
3215
3216 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3217 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3218
3219 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3220 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3221
3222 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3223 return kvm_skip_emulated_instruction(&svm->vcpu);
3224 }
3225
3226 static int skinit_interception(struct vcpu_svm *svm)
3227 {
3228 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3229
3230 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3231 return 1;
3232 }
3233
3234 static int wbinvd_interception(struct vcpu_svm *svm)
3235 {
3236 return kvm_emulate_wbinvd(&svm->vcpu);
3237 }
3238
3239 static int xsetbv_interception(struct vcpu_svm *svm)
3240 {
3241 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3242 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3243
3244 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3245 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3246 return kvm_skip_emulated_instruction(&svm->vcpu);
3247 }
3248
3249 return 1;
3250 }
3251
3252 static int task_switch_interception(struct vcpu_svm *svm)
3253 {
3254 u16 tss_selector;
3255 int reason;
3256 int int_type = svm->vmcb->control.exit_int_info &
3257 SVM_EXITINTINFO_TYPE_MASK;
3258 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3259 uint32_t type =
3260 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3261 uint32_t idt_v =
3262 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3263 bool has_error_code = false;
3264 u32 error_code = 0;
3265
3266 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3267
3268 if (svm->vmcb->control.exit_info_2 &
3269 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3270 reason = TASK_SWITCH_IRET;
3271 else if (svm->vmcb->control.exit_info_2 &
3272 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3273 reason = TASK_SWITCH_JMP;
3274 else if (idt_v)
3275 reason = TASK_SWITCH_GATE;
3276 else
3277 reason = TASK_SWITCH_CALL;
3278
3279 if (reason == TASK_SWITCH_GATE) {
3280 switch (type) {
3281 case SVM_EXITINTINFO_TYPE_NMI:
3282 svm->vcpu.arch.nmi_injected = false;
3283 break;
3284 case SVM_EXITINTINFO_TYPE_EXEPT:
3285 if (svm->vmcb->control.exit_info_2 &
3286 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3287 has_error_code = true;
3288 error_code =
3289 (u32)svm->vmcb->control.exit_info_2;
3290 }
3291 kvm_clear_exception_queue(&svm->vcpu);
3292 break;
3293 case SVM_EXITINTINFO_TYPE_INTR:
3294 kvm_clear_interrupt_queue(&svm->vcpu);
3295 break;
3296 default:
3297 break;
3298 }
3299 }
3300
3301 if (reason != TASK_SWITCH_GATE ||
3302 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3303 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3304 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3305 skip_emulated_instruction(&svm->vcpu);
3306
3307 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3308 int_vec = -1;
3309
3310 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3311 has_error_code, error_code) == EMULATE_FAIL) {
3312 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3313 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3314 svm->vcpu.run->internal.ndata = 0;
3315 return 0;
3316 }
3317 return 1;
3318 }
3319
3320 static int cpuid_interception(struct vcpu_svm *svm)
3321 {
3322 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3323 return kvm_emulate_cpuid(&svm->vcpu);
3324 }
3325
3326 static int iret_interception(struct vcpu_svm *svm)
3327 {
3328 ++svm->vcpu.stat.nmi_window_exits;
3329 clr_intercept(svm, INTERCEPT_IRET);
3330 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3331 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3332 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3333 return 1;
3334 }
3335
3336 static int invlpg_interception(struct vcpu_svm *svm)
3337 {
3338 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3339 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3340
3341 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3342 return kvm_skip_emulated_instruction(&svm->vcpu);
3343 }
3344
3345 static int emulate_on_interception(struct vcpu_svm *svm)
3346 {
3347 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3348 }
3349
3350 static int rdpmc_interception(struct vcpu_svm *svm)
3351 {
3352 int err;
3353
3354 if (!static_cpu_has(X86_FEATURE_NRIPS))
3355 return emulate_on_interception(svm);
3356
3357 err = kvm_rdpmc(&svm->vcpu);
3358 return kvm_complete_insn_gp(&svm->vcpu, err);
3359 }
3360
3361 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3362 unsigned long val)
3363 {
3364 unsigned long cr0 = svm->vcpu.arch.cr0;
3365 bool ret = false;
3366 u64 intercept;
3367
3368 intercept = svm->nested.intercept;
3369
3370 if (!is_guest_mode(&svm->vcpu) ||
3371 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3372 return false;
3373
3374 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3375 val &= ~SVM_CR0_SELECTIVE_MASK;
3376
3377 if (cr0 ^ val) {
3378 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3379 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3380 }
3381
3382 return ret;
3383 }
3384
3385 #define CR_VALID (1ULL << 63)
3386
3387 static int cr_interception(struct vcpu_svm *svm)
3388 {
3389 int reg, cr;
3390 unsigned long val;
3391 int err;
3392
3393 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3394 return emulate_on_interception(svm);
3395
3396 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3397 return emulate_on_interception(svm);
3398
3399 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3400 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3401 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3402 else
3403 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3404
3405 err = 0;
3406 if (cr >= 16) { /* mov to cr */
3407 cr -= 16;
3408 val = kvm_register_read(&svm->vcpu, reg);
3409 switch (cr) {
3410 case 0:
3411 if (!check_selective_cr0_intercepted(svm, val))
3412 err = kvm_set_cr0(&svm->vcpu, val);
3413 else
3414 return 1;
3415
3416 break;
3417 case 3:
3418 err = kvm_set_cr3(&svm->vcpu, val);
3419 break;
3420 case 4:
3421 err = kvm_set_cr4(&svm->vcpu, val);
3422 break;
3423 case 8:
3424 err = kvm_set_cr8(&svm->vcpu, val);
3425 break;
3426 default:
3427 WARN(1, "unhandled write to CR%d", cr);
3428 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3429 return 1;
3430 }
3431 } else { /* mov from cr */
3432 switch (cr) {
3433 case 0:
3434 val = kvm_read_cr0(&svm->vcpu);
3435 break;
3436 case 2:
3437 val = svm->vcpu.arch.cr2;
3438 break;
3439 case 3:
3440 val = kvm_read_cr3(&svm->vcpu);
3441 break;
3442 case 4:
3443 val = kvm_read_cr4(&svm->vcpu);
3444 break;
3445 case 8:
3446 val = kvm_get_cr8(&svm->vcpu);
3447 break;
3448 default:
3449 WARN(1, "unhandled read from CR%d", cr);
3450 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3451 return 1;
3452 }
3453 kvm_register_write(&svm->vcpu, reg, val);
3454 }
3455 return kvm_complete_insn_gp(&svm->vcpu, err);
3456 }
3457
3458 static int dr_interception(struct vcpu_svm *svm)
3459 {
3460 int reg, dr;
3461 unsigned long val;
3462
3463 if (svm->vcpu.guest_debug == 0) {
3464 /*
3465 * No more DR vmexits; force a reload of the debug registers
3466 * and reenter on this instruction. The next vmexit will
3467 * retrieve the full state of the debug registers.
3468 */
3469 clr_dr_intercepts(svm);
3470 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3471 return 1;
3472 }
3473
3474 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3475 return emulate_on_interception(svm);
3476
3477 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3478 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3479
3480 if (dr >= 16) { /* mov to DRn */
3481 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3482 return 1;
3483 val = kvm_register_read(&svm->vcpu, reg);
3484 kvm_set_dr(&svm->vcpu, dr - 16, val);
3485 } else {
3486 if (!kvm_require_dr(&svm->vcpu, dr))
3487 return 1;
3488 kvm_get_dr(&svm->vcpu, dr, &val);
3489 kvm_register_write(&svm->vcpu, reg, val);
3490 }
3491
3492 return kvm_skip_emulated_instruction(&svm->vcpu);
3493 }
3494
3495 static int cr8_write_interception(struct vcpu_svm *svm)
3496 {
3497 struct kvm_run *kvm_run = svm->vcpu.run;
3498 int r;
3499
3500 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3501 /* instruction emulation calls kvm_set_cr8() */
3502 r = cr_interception(svm);
3503 if (lapic_in_kernel(&svm->vcpu))
3504 return r;
3505 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3506 return r;
3507 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3508 return 0;
3509 }
3510
3511 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3512 {
3513 struct vcpu_svm *svm = to_svm(vcpu);
3514
3515 switch (msr_info->index) {
3516 case MSR_IA32_TSC: {
3517 msr_info->data = svm->vmcb->control.tsc_offset +
3518 kvm_scale_tsc(vcpu, rdtsc());
3519
3520 break;
3521 }
3522 case MSR_STAR:
3523 msr_info->data = svm->vmcb->save.star;
3524 break;
3525 #ifdef CONFIG_X86_64
3526 case MSR_LSTAR:
3527 msr_info->data = svm->vmcb->save.lstar;
3528 break;
3529 case MSR_CSTAR:
3530 msr_info->data = svm->vmcb->save.cstar;
3531 break;
3532 case MSR_KERNEL_GS_BASE:
3533 msr_info->data = svm->vmcb->save.kernel_gs_base;
3534 break;
3535 case MSR_SYSCALL_MASK:
3536 msr_info->data = svm->vmcb->save.sfmask;
3537 break;
3538 #endif
3539 case MSR_IA32_SYSENTER_CS:
3540 msr_info->data = svm->vmcb->save.sysenter_cs;
3541 break;
3542 case MSR_IA32_SYSENTER_EIP:
3543 msr_info->data = svm->sysenter_eip;
3544 break;
3545 case MSR_IA32_SYSENTER_ESP:
3546 msr_info->data = svm->sysenter_esp;
3547 break;
3548 case MSR_TSC_AUX:
3549 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3550 return 1;
3551 msr_info->data = svm->tsc_aux;
3552 break;
3553 /*
3554 * Nobody will change the following 5 values in the VMCB so we can
3555 * safely return them on rdmsr. They will always be 0 until LBRV is
3556 * implemented.
3557 */
3558 case MSR_IA32_DEBUGCTLMSR:
3559 msr_info->data = svm->vmcb->save.dbgctl;
3560 break;
3561 case MSR_IA32_LASTBRANCHFROMIP:
3562 msr_info->data = svm->vmcb->save.br_from;
3563 break;
3564 case MSR_IA32_LASTBRANCHTOIP:
3565 msr_info->data = svm->vmcb->save.br_to;
3566 break;
3567 case MSR_IA32_LASTINTFROMIP:
3568 msr_info->data = svm->vmcb->save.last_excp_from;
3569 break;
3570 case MSR_IA32_LASTINTTOIP:
3571 msr_info->data = svm->vmcb->save.last_excp_to;
3572 break;
3573 case MSR_VM_HSAVE_PA:
3574 msr_info->data = svm->nested.hsave_msr;
3575 break;
3576 case MSR_VM_CR:
3577 msr_info->data = svm->nested.vm_cr_msr;
3578 break;
3579 case MSR_IA32_UCODE_REV:
3580 msr_info->data = 0x01000065;
3581 break;
3582 case MSR_F15H_IC_CFG: {
3583
3584 int family, model;
3585
3586 family = guest_cpuid_family(vcpu);
3587 model = guest_cpuid_model(vcpu);
3588
3589 if (family < 0 || model < 0)
3590 return kvm_get_msr_common(vcpu, msr_info);
3591
3592 msr_info->data = 0;
3593
3594 if (family == 0x15 &&
3595 (model >= 0x2 && model < 0x20))
3596 msr_info->data = 0x1E;
3597 }
3598 break;
3599 default:
3600 return kvm_get_msr_common(vcpu, msr_info);
3601 }
3602 return 0;
3603 }
3604
3605 static int rdmsr_interception(struct vcpu_svm *svm)
3606 {
3607 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3608 struct msr_data msr_info;
3609
3610 msr_info.index = ecx;
3611 msr_info.host_initiated = false;
3612 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3613 trace_kvm_msr_read_ex(ecx);
3614 kvm_inject_gp(&svm->vcpu, 0);
3615 return 1;
3616 } else {
3617 trace_kvm_msr_read(ecx, msr_info.data);
3618
3619 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3620 msr_info.data & 0xffffffff);
3621 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3622 msr_info.data >> 32);
3623 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3624 return kvm_skip_emulated_instruction(&svm->vcpu);
3625 }
3626 }
3627
3628 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3629 {
3630 struct vcpu_svm *svm = to_svm(vcpu);
3631 int svm_dis, chg_mask;
3632
3633 if (data & ~SVM_VM_CR_VALID_MASK)
3634 return 1;
3635
3636 chg_mask = SVM_VM_CR_VALID_MASK;
3637
3638 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3639 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3640
3641 svm->nested.vm_cr_msr &= ~chg_mask;
3642 svm->nested.vm_cr_msr |= (data & chg_mask);
3643
3644 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3645
3646 /* check for svm_disable while efer.svme is set */
3647 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3648 return 1;
3649
3650 return 0;
3651 }
3652
3653 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3654 {
3655 struct vcpu_svm *svm = to_svm(vcpu);
3656
3657 u32 ecx = msr->index;
3658 u64 data = msr->data;
3659 switch (ecx) {
3660 case MSR_IA32_TSC:
3661 kvm_write_tsc(vcpu, msr);
3662 break;
3663 case MSR_STAR:
3664 svm->vmcb->save.star = data;
3665 break;
3666 #ifdef CONFIG_X86_64
3667 case MSR_LSTAR:
3668 svm->vmcb->save.lstar = data;
3669 break;
3670 case MSR_CSTAR:
3671 svm->vmcb->save.cstar = data;
3672 break;
3673 case MSR_KERNEL_GS_BASE:
3674 svm->vmcb->save.kernel_gs_base = data;
3675 break;
3676 case MSR_SYSCALL_MASK:
3677 svm->vmcb->save.sfmask = data;
3678 break;
3679 #endif
3680 case MSR_IA32_SYSENTER_CS:
3681 svm->vmcb->save.sysenter_cs = data;
3682 break;
3683 case MSR_IA32_SYSENTER_EIP:
3684 svm->sysenter_eip = data;
3685 svm->vmcb->save.sysenter_eip = data;
3686 break;
3687 case MSR_IA32_SYSENTER_ESP:
3688 svm->sysenter_esp = data;
3689 svm->vmcb->save.sysenter_esp = data;
3690 break;
3691 case MSR_TSC_AUX:
3692 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3693 return 1;
3694
3695 /*
3696 * This is rare, so we update the MSR here instead of using
3697 * direct_access_msrs. Doing that would require a rdmsr in
3698 * svm_vcpu_put.
3699 */
3700 svm->tsc_aux = data;
3701 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3702 break;
3703 case MSR_IA32_DEBUGCTLMSR:
3704 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3705 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3706 __func__, data);
3707 break;
3708 }
3709 if (data & DEBUGCTL_RESERVED_BITS)
3710 return 1;
3711
3712 svm->vmcb->save.dbgctl = data;
3713 mark_dirty(svm->vmcb, VMCB_LBR);
3714 if (data & (1ULL<<0))
3715 svm_enable_lbrv(svm);
3716 else
3717 svm_disable_lbrv(svm);
3718 break;
3719 case MSR_VM_HSAVE_PA:
3720 svm->nested.hsave_msr = data;
3721 break;
3722 case MSR_VM_CR:
3723 return svm_set_vm_cr(vcpu, data);
3724 case MSR_VM_IGNNE:
3725 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3726 break;
3727 case MSR_IA32_APICBASE:
3728 if (kvm_vcpu_apicv_active(vcpu))
3729 avic_update_vapic_bar(to_svm(vcpu), data);
3730 /* Follow through */
3731 default:
3732 return kvm_set_msr_common(vcpu, msr);
3733 }
3734 return 0;
3735 }
3736
3737 static int wrmsr_interception(struct vcpu_svm *svm)
3738 {
3739 struct msr_data msr;
3740 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3741 u64 data = kvm_read_edx_eax(&svm->vcpu);
3742
3743 msr.data = data;
3744 msr.index = ecx;
3745 msr.host_initiated = false;
3746
3747 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3748 if (kvm_set_msr(&svm->vcpu, &msr)) {
3749 trace_kvm_msr_write_ex(ecx, data);
3750 kvm_inject_gp(&svm->vcpu, 0);
3751 return 1;
3752 } else {
3753 trace_kvm_msr_write(ecx, data);
3754 return kvm_skip_emulated_instruction(&svm->vcpu);
3755 }
3756 }
3757
3758 static int msr_interception(struct vcpu_svm *svm)
3759 {
3760 if (svm->vmcb->control.exit_info_1)
3761 return wrmsr_interception(svm);
3762 else
3763 return rdmsr_interception(svm);
3764 }
3765
3766 static int interrupt_window_interception(struct vcpu_svm *svm)
3767 {
3768 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3769 svm_clear_vintr(svm);
3770 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3771 mark_dirty(svm->vmcb, VMCB_INTR);
3772 ++svm->vcpu.stat.irq_window_exits;
3773 return 1;
3774 }
3775
3776 static int pause_interception(struct vcpu_svm *svm)
3777 {
3778 struct kvm_vcpu *vcpu = &svm->vcpu;
3779 bool in_kernel = (svm_get_cpl(vcpu) == 0);
3780
3781 kvm_vcpu_on_spin(vcpu, in_kernel);
3782 return 1;
3783 }
3784
3785 static int nop_interception(struct vcpu_svm *svm)
3786 {
3787 return kvm_skip_emulated_instruction(&(svm->vcpu));
3788 }
3789
3790 static int monitor_interception(struct vcpu_svm *svm)
3791 {
3792 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3793 return nop_interception(svm);
3794 }
3795
3796 static int mwait_interception(struct vcpu_svm *svm)
3797 {
3798 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3799 return nop_interception(svm);
3800 }
3801
3802 enum avic_ipi_failure_cause {
3803 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3804 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3805 AVIC_IPI_FAILURE_INVALID_TARGET,
3806 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3807 };
3808
3809 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3810 {
3811 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3812 u32 icrl = svm->vmcb->control.exit_info_1;
3813 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3814 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3815 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3816
3817 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3818
3819 switch (id) {
3820 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3821 /*
3822 * AVIC hardware handles the generation of
3823 * IPIs when the specified Message Type is Fixed
3824 * (also known as fixed delivery mode) and
3825 * the Trigger Mode is edge-triggered. The hardware
3826 * also supports self and broadcast delivery modes
3827 * specified via the Destination Shorthand(DSH)
3828 * field of the ICRL. Logical and physical APIC ID
3829 * formats are supported. All other IPI types cause
3830 * a #VMEXIT, which needs to emulated.
3831 */
3832 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3833 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3834 break;
3835 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3836 int i;
3837 struct kvm_vcpu *vcpu;
3838 struct kvm *kvm = svm->vcpu.kvm;
3839 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3840
3841 /*
3842 * At this point, we expect that the AVIC HW has already
3843 * set the appropriate IRR bits on the valid target
3844 * vcpus. So, we just need to kick the appropriate vcpu.
3845 */
3846 kvm_for_each_vcpu(i, vcpu, kvm) {
3847 bool m = kvm_apic_match_dest(vcpu, apic,
3848 icrl & KVM_APIC_SHORT_MASK,
3849 GET_APIC_DEST_FIELD(icrh),
3850 icrl & KVM_APIC_DEST_MASK);
3851
3852 if (m && !avic_vcpu_is_running(vcpu))
3853 kvm_vcpu_wake_up(vcpu);
3854 }
3855 break;
3856 }
3857 case AVIC_IPI_FAILURE_INVALID_TARGET:
3858 break;
3859 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3860 WARN_ONCE(1, "Invalid backing page\n");
3861 break;
3862 default:
3863 pr_err("Unknown IPI interception\n");
3864 }
3865
3866 return 1;
3867 }
3868
3869 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3870 {
3871 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3872 int index;
3873 u32 *logical_apic_id_table;
3874 int dlid = GET_APIC_LOGICAL_ID(ldr);
3875
3876 if (!dlid)
3877 return NULL;
3878
3879 if (flat) { /* flat */
3880 index = ffs(dlid) - 1;
3881 if (index > 7)
3882 return NULL;
3883 } else { /* cluster */
3884 int cluster = (dlid & 0xf0) >> 4;
3885 int apic = ffs(dlid & 0x0f) - 1;
3886
3887 if ((apic < 0) || (apic > 7) ||
3888 (cluster >= 0xf))
3889 return NULL;
3890 index = (cluster << 2) + apic;
3891 }
3892
3893 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3894
3895 return &logical_apic_id_table[index];
3896 }
3897
3898 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3899 bool valid)
3900 {
3901 bool flat;
3902 u32 *entry, new_entry;
3903
3904 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3905 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3906 if (!entry)
3907 return -EINVAL;
3908
3909 new_entry = READ_ONCE(*entry);
3910 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3911 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3912 if (valid)
3913 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3914 else
3915 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3916 WRITE_ONCE(*entry, new_entry);
3917
3918 return 0;
3919 }
3920
3921 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3922 {
3923 int ret;
3924 struct vcpu_svm *svm = to_svm(vcpu);
3925 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3926
3927 if (!ldr)
3928 return 1;
3929
3930 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3931 if (ret && svm->ldr_reg) {
3932 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3933 svm->ldr_reg = 0;
3934 } else {
3935 svm->ldr_reg = ldr;
3936 }
3937 return ret;
3938 }
3939
3940 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3941 {
3942 u64 *old, *new;
3943 struct vcpu_svm *svm = to_svm(vcpu);
3944 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3945 u32 id = (apic_id_reg >> 24) & 0xff;
3946
3947 if (vcpu->vcpu_id == id)
3948 return 0;
3949
3950 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3951 new = avic_get_physical_id_entry(vcpu, id);
3952 if (!new || !old)
3953 return 1;
3954
3955 /* We need to move physical_id_entry to new offset */
3956 *new = *old;
3957 *old = 0ULL;
3958 to_svm(vcpu)->avic_physical_id_cache = new;
3959
3960 /*
3961 * Also update the guest physical APIC ID in the logical
3962 * APIC ID table entry if already setup the LDR.
3963 */
3964 if (svm->ldr_reg)
3965 avic_handle_ldr_update(vcpu);
3966
3967 return 0;
3968 }
3969
3970 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3971 {
3972 struct vcpu_svm *svm = to_svm(vcpu);
3973 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3974 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3975 u32 mod = (dfr >> 28) & 0xf;
3976
3977 /*
3978 * We assume that all local APICs are using the same type.
3979 * If this changes, we need to flush the AVIC logical
3980 * APID id table.
3981 */
3982 if (vm_data->ldr_mode == mod)
3983 return 0;
3984
3985 clear_page(page_address(vm_data->avic_logical_id_table_page));
3986 vm_data->ldr_mode = mod;
3987
3988 if (svm->ldr_reg)
3989 avic_handle_ldr_update(vcpu);
3990 return 0;
3991 }
3992
3993 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3994 {
3995 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3996 u32 offset = svm->vmcb->control.exit_info_1 &
3997 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3998
3999 switch (offset) {
4000 case APIC_ID:
4001 if (avic_handle_apic_id_update(&svm->vcpu))
4002 return 0;
4003 break;
4004 case APIC_LDR:
4005 if (avic_handle_ldr_update(&svm->vcpu))
4006 return 0;
4007 break;
4008 case APIC_DFR:
4009 avic_handle_dfr_update(&svm->vcpu);
4010 break;
4011 default:
4012 break;
4013 }
4014
4015 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4016
4017 return 1;
4018 }
4019
4020 static bool is_avic_unaccelerated_access_trap(u32 offset)
4021 {
4022 bool ret = false;
4023
4024 switch (offset) {
4025 case APIC_ID:
4026 case APIC_EOI:
4027 case APIC_RRR:
4028 case APIC_LDR:
4029 case APIC_DFR:
4030 case APIC_SPIV:
4031 case APIC_ESR:
4032 case APIC_ICR:
4033 case APIC_LVTT:
4034 case APIC_LVTTHMR:
4035 case APIC_LVTPC:
4036 case APIC_LVT0:
4037 case APIC_LVT1:
4038 case APIC_LVTERR:
4039 case APIC_TMICT:
4040 case APIC_TDCR:
4041 ret = true;
4042 break;
4043 default:
4044 break;
4045 }
4046 return ret;
4047 }
4048
4049 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4050 {
4051 int ret = 0;
4052 u32 offset = svm->vmcb->control.exit_info_1 &
4053 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4054 u32 vector = svm->vmcb->control.exit_info_2 &
4055 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4056 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4057 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4058 bool trap = is_avic_unaccelerated_access_trap(offset);
4059
4060 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4061 trap, write, vector);
4062 if (trap) {
4063 /* Handling Trap */
4064 WARN_ONCE(!write, "svm: Handling trap read.\n");
4065 ret = avic_unaccel_trap_write(svm);
4066 } else {
4067 /* Handling Fault */
4068 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4069 }
4070
4071 return ret;
4072 }
4073
4074 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4075 [SVM_EXIT_READ_CR0] = cr_interception,
4076 [SVM_EXIT_READ_CR3] = cr_interception,
4077 [SVM_EXIT_READ_CR4] = cr_interception,
4078 [SVM_EXIT_READ_CR8] = cr_interception,
4079 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4080 [SVM_EXIT_WRITE_CR0] = cr_interception,
4081 [SVM_EXIT_WRITE_CR3] = cr_interception,
4082 [SVM_EXIT_WRITE_CR4] = cr_interception,
4083 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4084 [SVM_EXIT_READ_DR0] = dr_interception,
4085 [SVM_EXIT_READ_DR1] = dr_interception,
4086 [SVM_EXIT_READ_DR2] = dr_interception,
4087 [SVM_EXIT_READ_DR3] = dr_interception,
4088 [SVM_EXIT_READ_DR4] = dr_interception,
4089 [SVM_EXIT_READ_DR5] = dr_interception,
4090 [SVM_EXIT_READ_DR6] = dr_interception,
4091 [SVM_EXIT_READ_DR7] = dr_interception,
4092 [SVM_EXIT_WRITE_DR0] = dr_interception,
4093 [SVM_EXIT_WRITE_DR1] = dr_interception,
4094 [SVM_EXIT_WRITE_DR2] = dr_interception,
4095 [SVM_EXIT_WRITE_DR3] = dr_interception,
4096 [SVM_EXIT_WRITE_DR4] = dr_interception,
4097 [SVM_EXIT_WRITE_DR5] = dr_interception,
4098 [SVM_EXIT_WRITE_DR6] = dr_interception,
4099 [SVM_EXIT_WRITE_DR7] = dr_interception,
4100 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4101 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4102 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4103 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4104 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4105 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4106 [SVM_EXIT_INTR] = intr_interception,
4107 [SVM_EXIT_NMI] = nmi_interception,
4108 [SVM_EXIT_SMI] = nop_on_interception,
4109 [SVM_EXIT_INIT] = nop_on_interception,
4110 [SVM_EXIT_VINTR] = interrupt_window_interception,
4111 [SVM_EXIT_RDPMC] = rdpmc_interception,
4112 [SVM_EXIT_CPUID] = cpuid_interception,
4113 [SVM_EXIT_IRET] = iret_interception,
4114 [SVM_EXIT_INVD] = emulate_on_interception,
4115 [SVM_EXIT_PAUSE] = pause_interception,
4116 [SVM_EXIT_HLT] = halt_interception,
4117 [SVM_EXIT_INVLPG] = invlpg_interception,
4118 [SVM_EXIT_INVLPGA] = invlpga_interception,
4119 [SVM_EXIT_IOIO] = io_interception,
4120 [SVM_EXIT_MSR] = msr_interception,
4121 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4122 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4123 [SVM_EXIT_VMRUN] = vmrun_interception,
4124 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4125 [SVM_EXIT_VMLOAD] = vmload_interception,
4126 [SVM_EXIT_VMSAVE] = vmsave_interception,
4127 [SVM_EXIT_STGI] = stgi_interception,
4128 [SVM_EXIT_CLGI] = clgi_interception,
4129 [SVM_EXIT_SKINIT] = skinit_interception,
4130 [SVM_EXIT_WBINVD] = wbinvd_interception,
4131 [SVM_EXIT_MONITOR] = monitor_interception,
4132 [SVM_EXIT_MWAIT] = mwait_interception,
4133 [SVM_EXIT_XSETBV] = xsetbv_interception,
4134 [SVM_EXIT_NPF] = pf_interception,
4135 [SVM_EXIT_RSM] = emulate_on_interception,
4136 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4137 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4138 };
4139
4140 static void dump_vmcb(struct kvm_vcpu *vcpu)
4141 {
4142 struct vcpu_svm *svm = to_svm(vcpu);
4143 struct vmcb_control_area *control = &svm->vmcb->control;
4144 struct vmcb_save_area *save = &svm->vmcb->save;
4145
4146 pr_err("VMCB Control Area:\n");
4147 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4148 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4149 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4150 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4151 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4152 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4153 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4154 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4155 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4156 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4157 pr_err("%-20s%d\n", "asid:", control->asid);
4158 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4159 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4160 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4161 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4162 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4163 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4164 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4165 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4166 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4167 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4168 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4169 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4170 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4171 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4172 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4173 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4174 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4175 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4176 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4177 pr_err("VMCB State Save Area:\n");
4178 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4179 "es:",
4180 save->es.selector, save->es.attrib,
4181 save->es.limit, save->es.base);
4182 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4183 "cs:",
4184 save->cs.selector, save->cs.attrib,
4185 save->cs.limit, save->cs.base);
4186 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4187 "ss:",
4188 save->ss.selector, save->ss.attrib,
4189 save->ss.limit, save->ss.base);
4190 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4191 "ds:",
4192 save->ds.selector, save->ds.attrib,
4193 save->ds.limit, save->ds.base);
4194 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4195 "fs:",
4196 save->fs.selector, save->fs.attrib,
4197 save->fs.limit, save->fs.base);
4198 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4199 "gs:",
4200 save->gs.selector, save->gs.attrib,
4201 save->gs.limit, save->gs.base);
4202 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4203 "gdtr:",
4204 save->gdtr.selector, save->gdtr.attrib,
4205 save->gdtr.limit, save->gdtr.base);
4206 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4207 "ldtr:",
4208 save->ldtr.selector, save->ldtr.attrib,
4209 save->ldtr.limit, save->ldtr.base);
4210 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4211 "idtr:",
4212 save->idtr.selector, save->idtr.attrib,
4213 save->idtr.limit, save->idtr.base);
4214 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4215 "tr:",
4216 save->tr.selector, save->tr.attrib,
4217 save->tr.limit, save->tr.base);
4218 pr_err("cpl: %d efer: %016llx\n",
4219 save->cpl, save->efer);
4220 pr_err("%-15s %016llx %-13s %016llx\n",
4221 "cr0:", save->cr0, "cr2:", save->cr2);
4222 pr_err("%-15s %016llx %-13s %016llx\n",
4223 "cr3:", save->cr3, "cr4:", save->cr4);
4224 pr_err("%-15s %016llx %-13s %016llx\n",
4225 "dr6:", save->dr6, "dr7:", save->dr7);
4226 pr_err("%-15s %016llx %-13s %016llx\n",
4227 "rip:", save->rip, "rflags:", save->rflags);
4228 pr_err("%-15s %016llx %-13s %016llx\n",
4229 "rsp:", save->rsp, "rax:", save->rax);
4230 pr_err("%-15s %016llx %-13s %016llx\n",
4231 "star:", save->star, "lstar:", save->lstar);
4232 pr_err("%-15s %016llx %-13s %016llx\n",
4233 "cstar:", save->cstar, "sfmask:", save->sfmask);
4234 pr_err("%-15s %016llx %-13s %016llx\n",
4235 "kernel_gs_base:", save->kernel_gs_base,
4236 "sysenter_cs:", save->sysenter_cs);
4237 pr_err("%-15s %016llx %-13s %016llx\n",
4238 "sysenter_esp:", save->sysenter_esp,
4239 "sysenter_eip:", save->sysenter_eip);
4240 pr_err("%-15s %016llx %-13s %016llx\n",
4241 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4242 pr_err("%-15s %016llx %-13s %016llx\n",
4243 "br_from:", save->br_from, "br_to:", save->br_to);
4244 pr_err("%-15s %016llx %-13s %016llx\n",
4245 "excp_from:", save->last_excp_from,
4246 "excp_to:", save->last_excp_to);
4247 }
4248
4249 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4250 {
4251 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4252
4253 *info1 = control->exit_info_1;
4254 *info2 = control->exit_info_2;
4255 }
4256
4257 static int handle_exit(struct kvm_vcpu *vcpu)
4258 {
4259 struct vcpu_svm *svm = to_svm(vcpu);
4260 struct kvm_run *kvm_run = vcpu->run;
4261 u32 exit_code = svm->vmcb->control.exit_code;
4262
4263 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4264
4265 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4266 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4267 if (npt_enabled)
4268 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4269
4270 if (unlikely(svm->nested.exit_required)) {
4271 nested_svm_vmexit(svm);
4272 svm->nested.exit_required = false;
4273
4274 return 1;
4275 }
4276
4277 if (is_guest_mode(vcpu)) {
4278 int vmexit;
4279
4280 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4281 svm->vmcb->control.exit_info_1,
4282 svm->vmcb->control.exit_info_2,
4283 svm->vmcb->control.exit_int_info,
4284 svm->vmcb->control.exit_int_info_err,
4285 KVM_ISA_SVM);
4286
4287 vmexit = nested_svm_exit_special(svm);
4288
4289 if (vmexit == NESTED_EXIT_CONTINUE)
4290 vmexit = nested_svm_exit_handled(svm);
4291
4292 if (vmexit == NESTED_EXIT_DONE)
4293 return 1;
4294 }
4295
4296 svm_complete_interrupts(svm);
4297
4298 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4299 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4300 kvm_run->fail_entry.hardware_entry_failure_reason
4301 = svm->vmcb->control.exit_code;
4302 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4303 dump_vmcb(vcpu);
4304 return 0;
4305 }
4306
4307 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4308 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4309 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4310 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4311 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4312 "exit_code 0x%x\n",
4313 __func__, svm->vmcb->control.exit_int_info,
4314 exit_code);
4315
4316 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4317 || !svm_exit_handlers[exit_code]) {
4318 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4319 kvm_queue_exception(vcpu, UD_VECTOR);
4320 return 1;
4321 }
4322
4323 return svm_exit_handlers[exit_code](svm);
4324 }
4325
4326 static void reload_tss(struct kvm_vcpu *vcpu)
4327 {
4328 int cpu = raw_smp_processor_id();
4329
4330 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4331 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4332 load_TR_desc();
4333 }
4334
4335 static void pre_svm_run(struct vcpu_svm *svm)
4336 {
4337 int cpu = raw_smp_processor_id();
4338
4339 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4340
4341 /* FIXME: handle wraparound of asid_generation */
4342 if (svm->asid_generation != sd->asid_generation)
4343 new_asid(svm, sd);
4344 }
4345
4346 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4347 {
4348 struct vcpu_svm *svm = to_svm(vcpu);
4349
4350 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4351 vcpu->arch.hflags |= HF_NMI_MASK;
4352 set_intercept(svm, INTERCEPT_IRET);
4353 ++vcpu->stat.nmi_injections;
4354 }
4355
4356 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4357 {
4358 struct vmcb_control_area *control;
4359
4360 /* The following fields are ignored when AVIC is enabled */
4361 control = &svm->vmcb->control;
4362 control->int_vector = irq;
4363 control->int_ctl &= ~V_INTR_PRIO_MASK;
4364 control->int_ctl |= V_IRQ_MASK |
4365 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4366 mark_dirty(svm->vmcb, VMCB_INTR);
4367 }
4368
4369 static void svm_set_irq(struct kvm_vcpu *vcpu)
4370 {
4371 struct vcpu_svm *svm = to_svm(vcpu);
4372
4373 BUG_ON(!(gif_set(svm)));
4374
4375 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4376 ++vcpu->stat.irq_injections;
4377
4378 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4379 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4380 }
4381
4382 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4383 {
4384 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4385 }
4386
4387 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4388 {
4389 struct vcpu_svm *svm = to_svm(vcpu);
4390
4391 if (svm_nested_virtualize_tpr(vcpu) ||
4392 kvm_vcpu_apicv_active(vcpu))
4393 return;
4394
4395 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4396
4397 if (irr == -1)
4398 return;
4399
4400 if (tpr >= irr)
4401 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4402 }
4403
4404 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4405 {
4406 return;
4407 }
4408
4409 static bool svm_get_enable_apicv(struct kvm_vcpu *vcpu)
4410 {
4411 return avic && irqchip_split(vcpu->kvm);
4412 }
4413
4414 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4415 {
4416 }
4417
4418 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4419 {
4420 }
4421
4422 /* Note: Currently only used by Hyper-V. */
4423 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4424 {
4425 struct vcpu_svm *svm = to_svm(vcpu);
4426 struct vmcb *vmcb = svm->vmcb;
4427
4428 if (!kvm_vcpu_apicv_active(&svm->vcpu))
4429 return;
4430
4431 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4432 mark_dirty(vmcb, VMCB_INTR);
4433 }
4434
4435 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4436 {
4437 return;
4438 }
4439
4440 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4441 {
4442 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4443 smp_mb__after_atomic();
4444
4445 if (avic_vcpu_is_running(vcpu))
4446 wrmsrl(SVM_AVIC_DOORBELL,
4447 kvm_cpu_get_apicid(vcpu->cpu));
4448 else
4449 kvm_vcpu_wake_up(vcpu);
4450 }
4451
4452 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4453 {
4454 unsigned long flags;
4455 struct amd_svm_iommu_ir *cur;
4456
4457 spin_lock_irqsave(&svm->ir_list_lock, flags);
4458 list_for_each_entry(cur, &svm->ir_list, node) {
4459 if (cur->data != pi->ir_data)
4460 continue;
4461 list_del(&cur->node);
4462 kfree(cur);
4463 break;
4464 }
4465 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4466 }
4467
4468 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4469 {
4470 int ret = 0;
4471 unsigned long flags;
4472 struct amd_svm_iommu_ir *ir;
4473
4474 /**
4475 * In some cases, the existing irte is updaed and re-set,
4476 * so we need to check here if it's already been * added
4477 * to the ir_list.
4478 */
4479 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4480 struct kvm *kvm = svm->vcpu.kvm;
4481 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4482 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4483 struct vcpu_svm *prev_svm;
4484
4485 if (!prev_vcpu) {
4486 ret = -EINVAL;
4487 goto out;
4488 }
4489
4490 prev_svm = to_svm(prev_vcpu);
4491 svm_ir_list_del(prev_svm, pi);
4492 }
4493
4494 /**
4495 * Allocating new amd_iommu_pi_data, which will get
4496 * add to the per-vcpu ir_list.
4497 */
4498 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4499 if (!ir) {
4500 ret = -ENOMEM;
4501 goto out;
4502 }
4503 ir->data = pi->ir_data;
4504
4505 spin_lock_irqsave(&svm->ir_list_lock, flags);
4506 list_add(&ir->node, &svm->ir_list);
4507 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4508 out:
4509 return ret;
4510 }
4511
4512 /**
4513 * Note:
4514 * The HW cannot support posting multicast/broadcast
4515 * interrupts to a vCPU. So, we still use legacy interrupt
4516 * remapping for these kind of interrupts.
4517 *
4518 * For lowest-priority interrupts, we only support
4519 * those with single CPU as the destination, e.g. user
4520 * configures the interrupts via /proc/irq or uses
4521 * irqbalance to make the interrupts single-CPU.
4522 */
4523 static int
4524 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4525 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4526 {
4527 struct kvm_lapic_irq irq;
4528 struct kvm_vcpu *vcpu = NULL;
4529
4530 kvm_set_msi_irq(kvm, e, &irq);
4531
4532 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4533 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4534 __func__, irq.vector);
4535 return -1;
4536 }
4537
4538 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4539 irq.vector);
4540 *svm = to_svm(vcpu);
4541 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
4542 vcpu_info->vector = irq.vector;
4543
4544 return 0;
4545 }
4546
4547 /*
4548 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4549 *
4550 * @kvm: kvm
4551 * @host_irq: host irq of the interrupt
4552 * @guest_irq: gsi of the interrupt
4553 * @set: set or unset PI
4554 * returns 0 on success, < 0 on failure
4555 */
4556 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4557 uint32_t guest_irq, bool set)
4558 {
4559 struct kvm_kernel_irq_routing_entry *e;
4560 struct kvm_irq_routing_table *irq_rt;
4561 int idx, ret = -EINVAL;
4562
4563 if (!kvm_arch_has_assigned_device(kvm) ||
4564 !irq_remapping_cap(IRQ_POSTING_CAP))
4565 return 0;
4566
4567 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4568 __func__, host_irq, guest_irq, set);
4569
4570 idx = srcu_read_lock(&kvm->irq_srcu);
4571 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4572 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4573
4574 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4575 struct vcpu_data vcpu_info;
4576 struct vcpu_svm *svm = NULL;
4577
4578 if (e->type != KVM_IRQ_ROUTING_MSI)
4579 continue;
4580
4581 /**
4582 * Here, we setup with legacy mode in the following cases:
4583 * 1. When cannot target interrupt to a specific vcpu.
4584 * 2. Unsetting posted interrupt.
4585 * 3. APIC virtialization is disabled for the vcpu.
4586 */
4587 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4588 kvm_vcpu_apicv_active(&svm->vcpu)) {
4589 struct amd_iommu_pi_data pi;
4590
4591 /* Try to enable guest_mode in IRTE */
4592 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
4593 AVIC_HPA_MASK);
4594 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4595 svm->vcpu.vcpu_id);
4596 pi.is_guest_mode = true;
4597 pi.vcpu_data = &vcpu_info;
4598 ret = irq_set_vcpu_affinity(host_irq, &pi);
4599
4600 /**
4601 * Here, we successfully setting up vcpu affinity in
4602 * IOMMU guest mode. Now, we need to store the posted
4603 * interrupt information in a per-vcpu ir_list so that
4604 * we can reference to them directly when we update vcpu
4605 * scheduling information in IOMMU irte.
4606 */
4607 if (!ret && pi.is_guest_mode)
4608 svm_ir_list_add(svm, &pi);
4609 } else {
4610 /* Use legacy mode in IRTE */
4611 struct amd_iommu_pi_data pi;
4612
4613 /**
4614 * Here, pi is used to:
4615 * - Tell IOMMU to use legacy mode for this interrupt.
4616 * - Retrieve ga_tag of prior interrupt remapping data.
4617 */
4618 pi.is_guest_mode = false;
4619 ret = irq_set_vcpu_affinity(host_irq, &pi);
4620
4621 /**
4622 * Check if the posted interrupt was previously
4623 * setup with the guest_mode by checking if the ga_tag
4624 * was cached. If so, we need to clean up the per-vcpu
4625 * ir_list.
4626 */
4627 if (!ret && pi.prev_ga_tag) {
4628 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4629 struct kvm_vcpu *vcpu;
4630
4631 vcpu = kvm_get_vcpu_by_id(kvm, id);
4632 if (vcpu)
4633 svm_ir_list_del(to_svm(vcpu), &pi);
4634 }
4635 }
4636
4637 if (!ret && svm) {
4638 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4639 host_irq, e->gsi,
4640 vcpu_info.vector,
4641 vcpu_info.pi_desc_addr, set);
4642 }
4643
4644 if (ret < 0) {
4645 pr_err("%s: failed to update PI IRTE\n", __func__);
4646 goto out;
4647 }
4648 }
4649
4650 ret = 0;
4651 out:
4652 srcu_read_unlock(&kvm->irq_srcu, idx);
4653 return ret;
4654 }
4655
4656 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4657 {
4658 struct vcpu_svm *svm = to_svm(vcpu);
4659 struct vmcb *vmcb = svm->vmcb;
4660 int ret;
4661 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4662 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4663 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4664
4665 return ret;
4666 }
4667
4668 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4669 {
4670 struct vcpu_svm *svm = to_svm(vcpu);
4671
4672 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4673 }
4674
4675 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4676 {
4677 struct vcpu_svm *svm = to_svm(vcpu);
4678
4679 if (masked) {
4680 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4681 set_intercept(svm, INTERCEPT_IRET);
4682 } else {
4683 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4684 clr_intercept(svm, INTERCEPT_IRET);
4685 }
4686 }
4687
4688 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4689 {
4690 struct vcpu_svm *svm = to_svm(vcpu);
4691 struct vmcb *vmcb = svm->vmcb;
4692 int ret;
4693
4694 if (!gif_set(svm) ||
4695 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4696 return 0;
4697
4698 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4699
4700 if (is_guest_mode(vcpu))
4701 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4702
4703 return ret;
4704 }
4705
4706 static void enable_irq_window(struct kvm_vcpu *vcpu)
4707 {
4708 struct vcpu_svm *svm = to_svm(vcpu);
4709
4710 if (kvm_vcpu_apicv_active(vcpu))
4711 return;
4712
4713 /*
4714 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4715 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4716 * get that intercept, this function will be called again though and
4717 * we'll get the vintr intercept. However, if the vGIF feature is
4718 * enabled, the STGI interception will not occur. Enable the irq
4719 * window under the assumption that the hardware will set the GIF.
4720 */
4721 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
4722 svm_set_vintr(svm);
4723 svm_inject_irq(svm, 0x0);
4724 }
4725 }
4726
4727 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4728 {
4729 struct vcpu_svm *svm = to_svm(vcpu);
4730
4731 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4732 == HF_NMI_MASK)
4733 return; /* IRET will cause a vm exit */
4734
4735 if (!gif_set(svm)) {
4736 if (vgif_enabled(svm))
4737 set_intercept(svm, INTERCEPT_STGI);
4738 return; /* STGI will cause a vm exit */
4739 }
4740
4741 if (svm->nested.exit_required)
4742 return; /* we're not going to run the guest yet */
4743
4744 /*
4745 * Something prevents NMI from been injected. Single step over possible
4746 * problem (IRET or exception injection or interrupt shadow)
4747 */
4748 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4749 svm->nmi_singlestep = true;
4750 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4751 }
4752
4753 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4754 {
4755 return 0;
4756 }
4757
4758 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4759 {
4760 struct vcpu_svm *svm = to_svm(vcpu);
4761
4762 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4763 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4764 else
4765 svm->asid_generation--;
4766 }
4767
4768 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4769 {
4770 }
4771
4772 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4773 {
4774 struct vcpu_svm *svm = to_svm(vcpu);
4775
4776 if (svm_nested_virtualize_tpr(vcpu))
4777 return;
4778
4779 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4780 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4781 kvm_set_cr8(vcpu, cr8);
4782 }
4783 }
4784
4785 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4786 {
4787 struct vcpu_svm *svm = to_svm(vcpu);
4788 u64 cr8;
4789
4790 if (svm_nested_virtualize_tpr(vcpu) ||
4791 kvm_vcpu_apicv_active(vcpu))
4792 return;
4793
4794 cr8 = kvm_get_cr8(vcpu);
4795 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4796 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4797 }
4798
4799 static void svm_complete_interrupts(struct vcpu_svm *svm)
4800 {
4801 u8 vector;
4802 int type;
4803 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4804 unsigned int3_injected = svm->int3_injected;
4805
4806 svm->int3_injected = 0;
4807
4808 /*
4809 * If we've made progress since setting HF_IRET_MASK, we've
4810 * executed an IRET and can allow NMI injection.
4811 */
4812 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4813 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4814 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4815 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4816 }
4817
4818 svm->vcpu.arch.nmi_injected = false;
4819 kvm_clear_exception_queue(&svm->vcpu);
4820 kvm_clear_interrupt_queue(&svm->vcpu);
4821
4822 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4823 return;
4824
4825 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4826
4827 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4828 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4829
4830 switch (type) {
4831 case SVM_EXITINTINFO_TYPE_NMI:
4832 svm->vcpu.arch.nmi_injected = true;
4833 break;
4834 case SVM_EXITINTINFO_TYPE_EXEPT:
4835 /*
4836 * In case of software exceptions, do not reinject the vector,
4837 * but re-execute the instruction instead. Rewind RIP first
4838 * if we emulated INT3 before.
4839 */
4840 if (kvm_exception_is_soft(vector)) {
4841 if (vector == BP_VECTOR && int3_injected &&
4842 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4843 kvm_rip_write(&svm->vcpu,
4844 kvm_rip_read(&svm->vcpu) -
4845 int3_injected);
4846 break;
4847 }
4848 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4849 u32 err = svm->vmcb->control.exit_int_info_err;
4850 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4851
4852 } else
4853 kvm_requeue_exception(&svm->vcpu, vector);
4854 break;
4855 case SVM_EXITINTINFO_TYPE_INTR:
4856 kvm_queue_interrupt(&svm->vcpu, vector, false);
4857 break;
4858 default:
4859 break;
4860 }
4861 }
4862
4863 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4864 {
4865 struct vcpu_svm *svm = to_svm(vcpu);
4866 struct vmcb_control_area *control = &svm->vmcb->control;
4867
4868 control->exit_int_info = control->event_inj;
4869 control->exit_int_info_err = control->event_inj_err;
4870 control->event_inj = 0;
4871 svm_complete_interrupts(svm);
4872 }
4873
4874 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4875 {
4876 struct vcpu_svm *svm = to_svm(vcpu);
4877
4878 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4879 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4880 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4881
4882 /*
4883 * A vmexit emulation is required before the vcpu can be executed
4884 * again.
4885 */
4886 if (unlikely(svm->nested.exit_required))
4887 return;
4888
4889 /*
4890 * Disable singlestep if we're injecting an interrupt/exception.
4891 * We don't want our modified rflags to be pushed on the stack where
4892 * we might not be able to easily reset them if we disabled NMI
4893 * singlestep later.
4894 */
4895 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4896 /*
4897 * Event injection happens before external interrupts cause a
4898 * vmexit and interrupts are disabled here, so smp_send_reschedule
4899 * is enough to force an immediate vmexit.
4900 */
4901 disable_nmi_singlestep(svm);
4902 smp_send_reschedule(vcpu->cpu);
4903 }
4904
4905 pre_svm_run(svm);
4906
4907 sync_lapic_to_cr8(vcpu);
4908
4909 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4910
4911 clgi();
4912
4913 local_irq_enable();
4914
4915 asm volatile (
4916 "push %%" _ASM_BP "; \n\t"
4917 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4918 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4919 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4920 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4921 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4922 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4923 #ifdef CONFIG_X86_64
4924 "mov %c[r8](%[svm]), %%r8 \n\t"
4925 "mov %c[r9](%[svm]), %%r9 \n\t"
4926 "mov %c[r10](%[svm]), %%r10 \n\t"
4927 "mov %c[r11](%[svm]), %%r11 \n\t"
4928 "mov %c[r12](%[svm]), %%r12 \n\t"
4929 "mov %c[r13](%[svm]), %%r13 \n\t"
4930 "mov %c[r14](%[svm]), %%r14 \n\t"
4931 "mov %c[r15](%[svm]), %%r15 \n\t"
4932 #endif
4933
4934 /* Enter guest mode */
4935 "push %%" _ASM_AX " \n\t"
4936 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4937 __ex(SVM_VMLOAD) "\n\t"
4938 __ex(SVM_VMRUN) "\n\t"
4939 __ex(SVM_VMSAVE) "\n\t"
4940 "pop %%" _ASM_AX " \n\t"
4941
4942 /* Save guest registers, load host registers */
4943 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4944 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4945 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4946 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4947 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4948 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4949 #ifdef CONFIG_X86_64
4950 "mov %%r8, %c[r8](%[svm]) \n\t"
4951 "mov %%r9, %c[r9](%[svm]) \n\t"
4952 "mov %%r10, %c[r10](%[svm]) \n\t"
4953 "mov %%r11, %c[r11](%[svm]) \n\t"
4954 "mov %%r12, %c[r12](%[svm]) \n\t"
4955 "mov %%r13, %c[r13](%[svm]) \n\t"
4956 "mov %%r14, %c[r14](%[svm]) \n\t"
4957 "mov %%r15, %c[r15](%[svm]) \n\t"
4958 #endif
4959 "pop %%" _ASM_BP
4960 :
4961 : [svm]"a"(svm),
4962 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4963 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4964 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4965 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4966 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4967 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4968 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4969 #ifdef CONFIG_X86_64
4970 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4971 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4972 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4973 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4974 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4975 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4976 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4977 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4978 #endif
4979 : "cc", "memory"
4980 #ifdef CONFIG_X86_64
4981 , "rbx", "rcx", "rdx", "rsi", "rdi"
4982 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4983 #else
4984 , "ebx", "ecx", "edx", "esi", "edi"
4985 #endif
4986 );
4987
4988 #ifdef CONFIG_X86_64
4989 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4990 #else
4991 loadsegment(fs, svm->host.fs);
4992 #ifndef CONFIG_X86_32_LAZY_GS
4993 loadsegment(gs, svm->host.gs);
4994 #endif
4995 #endif
4996
4997 reload_tss(vcpu);
4998
4999 local_irq_disable();
5000
5001 vcpu->arch.cr2 = svm->vmcb->save.cr2;
5002 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
5003 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
5004 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
5005
5006 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5007 kvm_before_handle_nmi(&svm->vcpu);
5008
5009 stgi();
5010
5011 /* Any pending NMI will happen here */
5012
5013 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5014 kvm_after_handle_nmi(&svm->vcpu);
5015
5016 sync_cr8_to_lapic(vcpu);
5017
5018 svm->next_rip = 0;
5019
5020 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5021
5022 /* if exit due to PF check for async PF */
5023 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5024 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5025
5026 if (npt_enabled) {
5027 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5028 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5029 }
5030
5031 /*
5032 * We need to handle MC intercepts here before the vcpu has a chance to
5033 * change the physical cpu
5034 */
5035 if (unlikely(svm->vmcb->control.exit_code ==
5036 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5037 svm_handle_mce(svm);
5038
5039 mark_all_clean(svm->vmcb);
5040 }
5041 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5042
5043 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5044 {
5045 struct vcpu_svm *svm = to_svm(vcpu);
5046
5047 svm->vmcb->save.cr3 = __sme_set(root);
5048 mark_dirty(svm->vmcb, VMCB_CR);
5049 svm_flush_tlb(vcpu);
5050 }
5051
5052 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5053 {
5054 struct vcpu_svm *svm = to_svm(vcpu);
5055
5056 svm->vmcb->control.nested_cr3 = __sme_set(root);
5057 mark_dirty(svm->vmcb, VMCB_NPT);
5058
5059 /* Also sync guest cr3 here in case we live migrate */
5060 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5061 mark_dirty(svm->vmcb, VMCB_CR);
5062
5063 svm_flush_tlb(vcpu);
5064 }
5065
5066 static int is_disabled(void)
5067 {
5068 u64 vm_cr;
5069
5070 rdmsrl(MSR_VM_CR, vm_cr);
5071 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5072 return 1;
5073
5074 return 0;
5075 }
5076
5077 static void
5078 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5079 {
5080 /*
5081 * Patch in the VMMCALL instruction:
5082 */
5083 hypercall[0] = 0x0f;
5084 hypercall[1] = 0x01;
5085 hypercall[2] = 0xd9;
5086 }
5087
5088 static void svm_check_processor_compat(void *rtn)
5089 {
5090 *(int *)rtn = 0;
5091 }
5092
5093 static bool svm_cpu_has_accelerated_tpr(void)
5094 {
5095 return false;
5096 }
5097
5098 static bool svm_has_high_real_mode_segbase(void)
5099 {
5100 return true;
5101 }
5102
5103 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5104 {
5105 return 0;
5106 }
5107
5108 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5109 {
5110 struct vcpu_svm *svm = to_svm(vcpu);
5111
5112 /* Update nrips enabled cache */
5113 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5114
5115 if (!kvm_vcpu_apicv_active(vcpu))
5116 return;
5117
5118 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5119 }
5120
5121 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5122 {
5123 switch (func) {
5124 case 0x1:
5125 if (avic)
5126 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5127 break;
5128 case 0x80000001:
5129 if (nested)
5130 entry->ecx |= (1 << 2); /* Set SVM bit */
5131 break;
5132 case 0x8000000A:
5133 entry->eax = 1; /* SVM revision 1 */
5134 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5135 ASID emulation to nested SVM */
5136 entry->ecx = 0; /* Reserved */
5137 entry->edx = 0; /* Per default do not support any
5138 additional features */
5139
5140 /* Support next_rip if host supports it */
5141 if (boot_cpu_has(X86_FEATURE_NRIPS))
5142 entry->edx |= SVM_FEATURE_NRIP;
5143
5144 /* Support NPT for the guest if enabled */
5145 if (npt_enabled)
5146 entry->edx |= SVM_FEATURE_NPT;
5147
5148 break;
5149 }
5150 }
5151
5152 static int svm_get_lpage_level(void)
5153 {
5154 return PT_PDPE_LEVEL;
5155 }
5156
5157 static bool svm_rdtscp_supported(void)
5158 {
5159 return boot_cpu_has(X86_FEATURE_RDTSCP);
5160 }
5161
5162 static bool svm_invpcid_supported(void)
5163 {
5164 return false;
5165 }
5166
5167 static bool svm_mpx_supported(void)
5168 {
5169 return false;
5170 }
5171
5172 static bool svm_xsaves_supported(void)
5173 {
5174 return false;
5175 }
5176
5177 static bool svm_has_wbinvd_exit(void)
5178 {
5179 return true;
5180 }
5181
5182 #define PRE_EX(exit) { .exit_code = (exit), \
5183 .stage = X86_ICPT_PRE_EXCEPT, }
5184 #define POST_EX(exit) { .exit_code = (exit), \
5185 .stage = X86_ICPT_POST_EXCEPT, }
5186 #define POST_MEM(exit) { .exit_code = (exit), \
5187 .stage = X86_ICPT_POST_MEMACCESS, }
5188
5189 static const struct __x86_intercept {
5190 u32 exit_code;
5191 enum x86_intercept_stage stage;
5192 } x86_intercept_map[] = {
5193 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5194 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5195 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5196 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5197 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5198 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5199 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5200 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5201 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5202 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5203 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5204 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5205 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5206 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5207 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5208 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5209 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5210 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5211 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5212 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5213 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5214 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5215 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5216 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5217 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5218 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5219 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5220 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5221 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5222 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5223 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5224 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5225 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5226 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5227 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5228 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5229 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5230 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5231 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5232 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5233 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5234 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5235 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5236 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5237 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5238 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5239 };
5240
5241 #undef PRE_EX
5242 #undef POST_EX
5243 #undef POST_MEM
5244
5245 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5246 struct x86_instruction_info *info,
5247 enum x86_intercept_stage stage)
5248 {
5249 struct vcpu_svm *svm = to_svm(vcpu);
5250 int vmexit, ret = X86EMUL_CONTINUE;
5251 struct __x86_intercept icpt_info;
5252 struct vmcb *vmcb = svm->vmcb;
5253
5254 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5255 goto out;
5256
5257 icpt_info = x86_intercept_map[info->intercept];
5258
5259 if (stage != icpt_info.stage)
5260 goto out;
5261
5262 switch (icpt_info.exit_code) {
5263 case SVM_EXIT_READ_CR0:
5264 if (info->intercept == x86_intercept_cr_read)
5265 icpt_info.exit_code += info->modrm_reg;
5266 break;
5267 case SVM_EXIT_WRITE_CR0: {
5268 unsigned long cr0, val;
5269 u64 intercept;
5270
5271 if (info->intercept == x86_intercept_cr_write)
5272 icpt_info.exit_code += info->modrm_reg;
5273
5274 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5275 info->intercept == x86_intercept_clts)
5276 break;
5277
5278 intercept = svm->nested.intercept;
5279
5280 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5281 break;
5282
5283 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5284 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5285
5286 if (info->intercept == x86_intercept_lmsw) {
5287 cr0 &= 0xfUL;
5288 val &= 0xfUL;
5289 /* lmsw can't clear PE - catch this here */
5290 if (cr0 & X86_CR0_PE)
5291 val |= X86_CR0_PE;
5292 }
5293
5294 if (cr0 ^ val)
5295 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5296
5297 break;
5298 }
5299 case SVM_EXIT_READ_DR0:
5300 case SVM_EXIT_WRITE_DR0:
5301 icpt_info.exit_code += info->modrm_reg;
5302 break;
5303 case SVM_EXIT_MSR:
5304 if (info->intercept == x86_intercept_wrmsr)
5305 vmcb->control.exit_info_1 = 1;
5306 else
5307 vmcb->control.exit_info_1 = 0;
5308 break;
5309 case SVM_EXIT_PAUSE:
5310 /*
5311 * We get this for NOP only, but pause
5312 * is rep not, check this here
5313 */
5314 if (info->rep_prefix != REPE_PREFIX)
5315 goto out;
5316 break;
5317 case SVM_EXIT_IOIO: {
5318 u64 exit_info;
5319 u32 bytes;
5320
5321 if (info->intercept == x86_intercept_in ||
5322 info->intercept == x86_intercept_ins) {
5323 exit_info = ((info->src_val & 0xffff) << 16) |
5324 SVM_IOIO_TYPE_MASK;
5325 bytes = info->dst_bytes;
5326 } else {
5327 exit_info = (info->dst_val & 0xffff) << 16;
5328 bytes = info->src_bytes;
5329 }
5330
5331 if (info->intercept == x86_intercept_outs ||
5332 info->intercept == x86_intercept_ins)
5333 exit_info |= SVM_IOIO_STR_MASK;
5334
5335 if (info->rep_prefix)
5336 exit_info |= SVM_IOIO_REP_MASK;
5337
5338 bytes = min(bytes, 4u);
5339
5340 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5341
5342 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5343
5344 vmcb->control.exit_info_1 = exit_info;
5345 vmcb->control.exit_info_2 = info->next_rip;
5346
5347 break;
5348 }
5349 default:
5350 break;
5351 }
5352
5353 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5354 if (static_cpu_has(X86_FEATURE_NRIPS))
5355 vmcb->control.next_rip = info->next_rip;
5356 vmcb->control.exit_code = icpt_info.exit_code;
5357 vmexit = nested_svm_exit_handled(svm);
5358
5359 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5360 : X86EMUL_CONTINUE;
5361
5362 out:
5363 return ret;
5364 }
5365
5366 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5367 {
5368 local_irq_enable();
5369 /*
5370 * We must have an instruction with interrupts enabled, so
5371 * the timer interrupt isn't delayed by the interrupt shadow.
5372 */
5373 asm("nop");
5374 local_irq_disable();
5375 }
5376
5377 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5378 {
5379 }
5380
5381 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5382 {
5383 if (avic_handle_apic_id_update(vcpu) != 0)
5384 return;
5385 if (avic_handle_dfr_update(vcpu) != 0)
5386 return;
5387 avic_handle_ldr_update(vcpu);
5388 }
5389
5390 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5391 {
5392 /* [63:9] are reserved. */
5393 vcpu->arch.mcg_cap &= 0x1ff;
5394 }
5395
5396 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5397 .cpu_has_kvm_support = has_svm,
5398 .disabled_by_bios = is_disabled,
5399 .hardware_setup = svm_hardware_setup,
5400 .hardware_unsetup = svm_hardware_unsetup,
5401 .check_processor_compatibility = svm_check_processor_compat,
5402 .hardware_enable = svm_hardware_enable,
5403 .hardware_disable = svm_hardware_disable,
5404 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5405 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5406
5407 .vcpu_create = svm_create_vcpu,
5408 .vcpu_free = svm_free_vcpu,
5409 .vcpu_reset = svm_vcpu_reset,
5410
5411 .vm_init = avic_vm_init,
5412 .vm_destroy = avic_vm_destroy,
5413
5414 .prepare_guest_switch = svm_prepare_guest_switch,
5415 .vcpu_load = svm_vcpu_load,
5416 .vcpu_put = svm_vcpu_put,
5417 .vcpu_blocking = svm_vcpu_blocking,
5418 .vcpu_unblocking = svm_vcpu_unblocking,
5419
5420 .update_bp_intercept = update_bp_intercept,
5421 .get_msr = svm_get_msr,
5422 .set_msr = svm_set_msr,
5423 .get_segment_base = svm_get_segment_base,
5424 .get_segment = svm_get_segment,
5425 .set_segment = svm_set_segment,
5426 .get_cpl = svm_get_cpl,
5427 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5428 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5429 .decache_cr3 = svm_decache_cr3,
5430 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5431 .set_cr0 = svm_set_cr0,
5432 .set_cr3 = svm_set_cr3,
5433 .set_cr4 = svm_set_cr4,
5434 .set_efer = svm_set_efer,
5435 .get_idt = svm_get_idt,
5436 .set_idt = svm_set_idt,
5437 .get_gdt = svm_get_gdt,
5438 .set_gdt = svm_set_gdt,
5439 .get_dr6 = svm_get_dr6,
5440 .set_dr6 = svm_set_dr6,
5441 .set_dr7 = svm_set_dr7,
5442 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5443 .cache_reg = svm_cache_reg,
5444 .get_rflags = svm_get_rflags,
5445 .set_rflags = svm_set_rflags,
5446
5447 .tlb_flush = svm_flush_tlb,
5448
5449 .run = svm_vcpu_run,
5450 .handle_exit = handle_exit,
5451 .skip_emulated_instruction = skip_emulated_instruction,
5452 .set_interrupt_shadow = svm_set_interrupt_shadow,
5453 .get_interrupt_shadow = svm_get_interrupt_shadow,
5454 .patch_hypercall = svm_patch_hypercall,
5455 .set_irq = svm_set_irq,
5456 .set_nmi = svm_inject_nmi,
5457 .queue_exception = svm_queue_exception,
5458 .cancel_injection = svm_cancel_injection,
5459 .interrupt_allowed = svm_interrupt_allowed,
5460 .nmi_allowed = svm_nmi_allowed,
5461 .get_nmi_mask = svm_get_nmi_mask,
5462 .set_nmi_mask = svm_set_nmi_mask,
5463 .enable_nmi_window = enable_nmi_window,
5464 .enable_irq_window = enable_irq_window,
5465 .update_cr8_intercept = update_cr8_intercept,
5466 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5467 .get_enable_apicv = svm_get_enable_apicv,
5468 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5469 .load_eoi_exitmap = svm_load_eoi_exitmap,
5470 .hwapic_irr_update = svm_hwapic_irr_update,
5471 .hwapic_isr_update = svm_hwapic_isr_update,
5472 .apicv_post_state_restore = avic_post_state_restore,
5473
5474 .set_tss_addr = svm_set_tss_addr,
5475 .get_tdp_level = get_npt_level,
5476 .get_mt_mask = svm_get_mt_mask,
5477
5478 .get_exit_info = svm_get_exit_info,
5479
5480 .get_lpage_level = svm_get_lpage_level,
5481
5482 .cpuid_update = svm_cpuid_update,
5483
5484 .rdtscp_supported = svm_rdtscp_supported,
5485 .invpcid_supported = svm_invpcid_supported,
5486 .mpx_supported = svm_mpx_supported,
5487 .xsaves_supported = svm_xsaves_supported,
5488
5489 .set_supported_cpuid = svm_set_supported_cpuid,
5490
5491 .has_wbinvd_exit = svm_has_wbinvd_exit,
5492
5493 .write_tsc_offset = svm_write_tsc_offset,
5494
5495 .set_tdp_cr3 = set_tdp_cr3,
5496
5497 .check_intercept = svm_check_intercept,
5498 .handle_external_intr = svm_handle_external_intr,
5499
5500 .sched_in = svm_sched_in,
5501
5502 .pmu_ops = &amd_pmu_ops,
5503 .deliver_posted_interrupt = svm_deliver_avic_intr,
5504 .update_pi_irte = svm_update_pi_irte,
5505 .setup_mce = svm_setup_mce,
5506 };
5507
5508 static int __init svm_init(void)
5509 {
5510 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5511 __alignof__(struct vcpu_svm), THIS_MODULE);
5512 }
5513
5514 static void __exit svm_exit(void)
5515 {
5516 kvm_exit();
5517 }
5518
5519 module_init(svm_init)
5520 module_exit(svm_exit)
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