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Merge branch 'core-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16 #include <linux/kvm_host.h>
17
18 #include "irq.h"
19 #include "mmu.h"
20 #include "kvm_cache_regs.h"
21 #include "x86.h"
22
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29
30 #include <asm/desc.h>
31
32 #include <asm/virtext.h>
33 #include "trace.h"
34
35 #define __ex(x) __kvm_handle_fault_on_reboot(x)
36
37 MODULE_AUTHOR("Qumranet");
38 MODULE_LICENSE("GPL");
39
40 #define IOPM_ALLOC_ORDER 2
41 #define MSRPM_ALLOC_ORDER 1
42
43 #define SEG_TYPE_LDT 2
44 #define SEG_TYPE_BUSY_TSS16 3
45
46 #define SVM_FEATURE_NPT (1 << 0)
47 #define SVM_FEATURE_LBRV (1 << 1)
48 #define SVM_FEATURE_SVML (1 << 2)
49 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
50
51 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
52 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
53 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
54
55 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
56
57 static const u32 host_save_user_msrs[] = {
58 #ifdef CONFIG_X86_64
59 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
60 MSR_FS_BASE,
61 #endif
62 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
63 };
64
65 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
66
67 struct kvm_vcpu;
68
69 struct nested_state {
70 struct vmcb *hsave;
71 u64 hsave_msr;
72 u64 vmcb;
73
74 /* These are the merged vectors */
75 u32 *msrpm;
76
77 /* gpa pointers to the real vectors */
78 u64 vmcb_msrpm;
79
80 /* A VMEXIT is required but not yet emulated */
81 bool exit_required;
82
83 /* cache for intercepts of the guest */
84 u16 intercept_cr_read;
85 u16 intercept_cr_write;
86 u16 intercept_dr_read;
87 u16 intercept_dr_write;
88 u32 intercept_exceptions;
89 u64 intercept;
90
91 };
92
93 struct vcpu_svm {
94 struct kvm_vcpu vcpu;
95 struct vmcb *vmcb;
96 unsigned long vmcb_pa;
97 struct svm_cpu_data *svm_data;
98 uint64_t asid_generation;
99 uint64_t sysenter_esp;
100 uint64_t sysenter_eip;
101
102 u64 next_rip;
103
104 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
105 u64 host_gs_base;
106
107 u32 *msrpm;
108
109 struct nested_state nested;
110
111 bool nmi_singlestep;
112 };
113
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 static bool npt_enabled = true;
117 #else
118 static bool npt_enabled = false;
119 #endif
120 static int npt = 1;
121
122 module_param(npt, int, S_IRUGO);
123
124 static int nested = 1;
125 module_param(nested, int, S_IRUGO);
126
127 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
128 static void svm_complete_interrupts(struct vcpu_svm *svm);
129
130 static int nested_svm_exit_handled(struct vcpu_svm *svm);
131 static int nested_svm_vmexit(struct vcpu_svm *svm);
132 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
133 bool has_error_code, u32 error_code);
134
135 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
136 {
137 return container_of(vcpu, struct vcpu_svm, vcpu);
138 }
139
140 static inline bool is_nested(struct vcpu_svm *svm)
141 {
142 return svm->nested.vmcb;
143 }
144
145 static inline void enable_gif(struct vcpu_svm *svm)
146 {
147 svm->vcpu.arch.hflags |= HF_GIF_MASK;
148 }
149
150 static inline void disable_gif(struct vcpu_svm *svm)
151 {
152 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
153 }
154
155 static inline bool gif_set(struct vcpu_svm *svm)
156 {
157 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
158 }
159
160 static unsigned long iopm_base;
161
162 struct kvm_ldttss_desc {
163 u16 limit0;
164 u16 base0;
165 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
166 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
167 u32 base3;
168 u32 zero1;
169 } __attribute__((packed));
170
171 struct svm_cpu_data {
172 int cpu;
173
174 u64 asid_generation;
175 u32 max_asid;
176 u32 next_asid;
177 struct kvm_ldttss_desc *tss_desc;
178
179 struct page *save_area;
180 };
181
182 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
183 static uint32_t svm_features;
184
185 struct svm_init_data {
186 int cpu;
187 int r;
188 };
189
190 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
191
192 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
193 #define MSRS_RANGE_SIZE 2048
194 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
195
196 #define MAX_INST_SIZE 15
197
198 static inline u32 svm_has(u32 feat)
199 {
200 return svm_features & feat;
201 }
202
203 static inline void clgi(void)
204 {
205 asm volatile (__ex(SVM_CLGI));
206 }
207
208 static inline void stgi(void)
209 {
210 asm volatile (__ex(SVM_STGI));
211 }
212
213 static inline void invlpga(unsigned long addr, u32 asid)
214 {
215 asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
216 }
217
218 static inline void force_new_asid(struct kvm_vcpu *vcpu)
219 {
220 to_svm(vcpu)->asid_generation--;
221 }
222
223 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
224 {
225 force_new_asid(vcpu);
226 }
227
228 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
229 {
230 if (!npt_enabled && !(efer & EFER_LMA))
231 efer &= ~EFER_LME;
232
233 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
234 vcpu->arch.shadow_efer = efer;
235 }
236
237 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
238 bool has_error_code, u32 error_code)
239 {
240 struct vcpu_svm *svm = to_svm(vcpu);
241
242 /* If we are within a nested VM we'd better #VMEXIT and let the
243 guest handle the exception */
244 if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
245 return;
246
247 svm->vmcb->control.event_inj = nr
248 | SVM_EVTINJ_VALID
249 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
250 | SVM_EVTINJ_TYPE_EXEPT;
251 svm->vmcb->control.event_inj_err = error_code;
252 }
253
254 static int is_external_interrupt(u32 info)
255 {
256 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
257 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
258 }
259
260 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
261 {
262 struct vcpu_svm *svm = to_svm(vcpu);
263 u32 ret = 0;
264
265 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
266 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
267 return ret & mask;
268 }
269
270 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
271 {
272 struct vcpu_svm *svm = to_svm(vcpu);
273
274 if (mask == 0)
275 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
276 else
277 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
278
279 }
280
281 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
282 {
283 struct vcpu_svm *svm = to_svm(vcpu);
284
285 if (!svm->next_rip) {
286 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
287 EMULATE_DONE)
288 printk(KERN_DEBUG "%s: NOP\n", __func__);
289 return;
290 }
291 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
292 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
293 __func__, kvm_rip_read(vcpu), svm->next_rip);
294
295 kvm_rip_write(vcpu, svm->next_rip);
296 svm_set_interrupt_shadow(vcpu, 0);
297 }
298
299 static int has_svm(void)
300 {
301 const char *msg;
302
303 if (!cpu_has_svm(&msg)) {
304 printk(KERN_INFO "has_svm: %s\n", msg);
305 return 0;
306 }
307
308 return 1;
309 }
310
311 static void svm_hardware_disable(void *garbage)
312 {
313 cpu_svm_disable();
314 }
315
316 static int svm_hardware_enable(void *garbage)
317 {
318
319 struct svm_cpu_data *sd;
320 uint64_t efer;
321 struct descriptor_table gdt_descr;
322 struct desc_struct *gdt;
323 int me = raw_smp_processor_id();
324
325 rdmsrl(MSR_EFER, efer);
326 if (efer & EFER_SVME)
327 return -EBUSY;
328
329 if (!has_svm()) {
330 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
331 me);
332 return -EINVAL;
333 }
334 sd = per_cpu(svm_data, me);
335
336 if (!sd) {
337 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
338 me);
339 return -EINVAL;
340 }
341
342 sd->asid_generation = 1;
343 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
344 sd->next_asid = sd->max_asid + 1;
345
346 kvm_get_gdt(&gdt_descr);
347 gdt = (struct desc_struct *)gdt_descr.base;
348 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
349
350 wrmsrl(MSR_EFER, efer | EFER_SVME);
351
352 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
353
354 return 0;
355 }
356
357 static void svm_cpu_uninit(int cpu)
358 {
359 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
360
361 if (!sd)
362 return;
363
364 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
365 __free_page(sd->save_area);
366 kfree(sd);
367 }
368
369 static int svm_cpu_init(int cpu)
370 {
371 struct svm_cpu_data *sd;
372 int r;
373
374 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
375 if (!sd)
376 return -ENOMEM;
377 sd->cpu = cpu;
378 sd->save_area = alloc_page(GFP_KERNEL);
379 r = -ENOMEM;
380 if (!sd->save_area)
381 goto err_1;
382
383 per_cpu(svm_data, cpu) = sd;
384
385 return 0;
386
387 err_1:
388 kfree(sd);
389 return r;
390
391 }
392
393 static void set_msr_interception(u32 *msrpm, unsigned msr,
394 int read, int write)
395 {
396 int i;
397
398 for (i = 0; i < NUM_MSR_MAPS; i++) {
399 if (msr >= msrpm_ranges[i] &&
400 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
401 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
402 msrpm_ranges[i]) * 2;
403
404 u32 *base = msrpm + (msr_offset / 32);
405 u32 msr_shift = msr_offset % 32;
406 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
407 *base = (*base & ~(0x3 << msr_shift)) |
408 (mask << msr_shift);
409 return;
410 }
411 }
412 BUG();
413 }
414
415 static void svm_vcpu_init_msrpm(u32 *msrpm)
416 {
417 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
418
419 #ifdef CONFIG_X86_64
420 set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
421 set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
422 set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
423 set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
424 set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
425 set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
426 #endif
427 set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
428 set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
429 }
430
431 static void svm_enable_lbrv(struct vcpu_svm *svm)
432 {
433 u32 *msrpm = svm->msrpm;
434
435 svm->vmcb->control.lbr_ctl = 1;
436 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
437 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
438 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
439 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
440 }
441
442 static void svm_disable_lbrv(struct vcpu_svm *svm)
443 {
444 u32 *msrpm = svm->msrpm;
445
446 svm->vmcb->control.lbr_ctl = 0;
447 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
448 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
449 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
450 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
451 }
452
453 static __init int svm_hardware_setup(void)
454 {
455 int cpu;
456 struct page *iopm_pages;
457 void *iopm_va;
458 int r;
459
460 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
461
462 if (!iopm_pages)
463 return -ENOMEM;
464
465 iopm_va = page_address(iopm_pages);
466 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
467 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
468
469 if (boot_cpu_has(X86_FEATURE_NX))
470 kvm_enable_efer_bits(EFER_NX);
471
472 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
473 kvm_enable_efer_bits(EFER_FFXSR);
474
475 if (nested) {
476 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
477 kvm_enable_efer_bits(EFER_SVME);
478 }
479
480 for_each_possible_cpu(cpu) {
481 r = svm_cpu_init(cpu);
482 if (r)
483 goto err;
484 }
485
486 svm_features = cpuid_edx(SVM_CPUID_FUNC);
487
488 if (!svm_has(SVM_FEATURE_NPT))
489 npt_enabled = false;
490
491 if (npt_enabled && !npt) {
492 printk(KERN_INFO "kvm: Nested Paging disabled\n");
493 npt_enabled = false;
494 }
495
496 if (npt_enabled) {
497 printk(KERN_INFO "kvm: Nested Paging enabled\n");
498 kvm_enable_tdp();
499 } else
500 kvm_disable_tdp();
501
502 return 0;
503
504 err:
505 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
506 iopm_base = 0;
507 return r;
508 }
509
510 static __exit void svm_hardware_unsetup(void)
511 {
512 int cpu;
513
514 for_each_possible_cpu(cpu)
515 svm_cpu_uninit(cpu);
516
517 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
518 iopm_base = 0;
519 }
520
521 static void init_seg(struct vmcb_seg *seg)
522 {
523 seg->selector = 0;
524 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
525 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
526 seg->limit = 0xffff;
527 seg->base = 0;
528 }
529
530 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
531 {
532 seg->selector = 0;
533 seg->attrib = SVM_SELECTOR_P_MASK | type;
534 seg->limit = 0xffff;
535 seg->base = 0;
536 }
537
538 static void init_vmcb(struct vcpu_svm *svm)
539 {
540 struct vmcb_control_area *control = &svm->vmcb->control;
541 struct vmcb_save_area *save = &svm->vmcb->save;
542
543 control->intercept_cr_read = INTERCEPT_CR0_MASK |
544 INTERCEPT_CR3_MASK |
545 INTERCEPT_CR4_MASK;
546
547 control->intercept_cr_write = INTERCEPT_CR0_MASK |
548 INTERCEPT_CR3_MASK |
549 INTERCEPT_CR4_MASK |
550 INTERCEPT_CR8_MASK;
551
552 control->intercept_dr_read = INTERCEPT_DR0_MASK |
553 INTERCEPT_DR1_MASK |
554 INTERCEPT_DR2_MASK |
555 INTERCEPT_DR3_MASK;
556
557 control->intercept_dr_write = INTERCEPT_DR0_MASK |
558 INTERCEPT_DR1_MASK |
559 INTERCEPT_DR2_MASK |
560 INTERCEPT_DR3_MASK |
561 INTERCEPT_DR5_MASK |
562 INTERCEPT_DR7_MASK;
563
564 control->intercept_exceptions = (1 << PF_VECTOR) |
565 (1 << UD_VECTOR) |
566 (1 << MC_VECTOR);
567
568
569 control->intercept = (1ULL << INTERCEPT_INTR) |
570 (1ULL << INTERCEPT_NMI) |
571 (1ULL << INTERCEPT_SMI) |
572 (1ULL << INTERCEPT_CPUID) |
573 (1ULL << INTERCEPT_INVD) |
574 (1ULL << INTERCEPT_HLT) |
575 (1ULL << INTERCEPT_INVLPG) |
576 (1ULL << INTERCEPT_INVLPGA) |
577 (1ULL << INTERCEPT_IOIO_PROT) |
578 (1ULL << INTERCEPT_MSR_PROT) |
579 (1ULL << INTERCEPT_TASK_SWITCH) |
580 (1ULL << INTERCEPT_SHUTDOWN) |
581 (1ULL << INTERCEPT_VMRUN) |
582 (1ULL << INTERCEPT_VMMCALL) |
583 (1ULL << INTERCEPT_VMLOAD) |
584 (1ULL << INTERCEPT_VMSAVE) |
585 (1ULL << INTERCEPT_STGI) |
586 (1ULL << INTERCEPT_CLGI) |
587 (1ULL << INTERCEPT_SKINIT) |
588 (1ULL << INTERCEPT_WBINVD) |
589 (1ULL << INTERCEPT_MONITOR) |
590 (1ULL << INTERCEPT_MWAIT);
591
592 control->iopm_base_pa = iopm_base;
593 control->msrpm_base_pa = __pa(svm->msrpm);
594 control->tsc_offset = 0;
595 control->int_ctl = V_INTR_MASKING_MASK;
596
597 init_seg(&save->es);
598 init_seg(&save->ss);
599 init_seg(&save->ds);
600 init_seg(&save->fs);
601 init_seg(&save->gs);
602
603 save->cs.selector = 0xf000;
604 /* Executable/Readable Code Segment */
605 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
606 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
607 save->cs.limit = 0xffff;
608 /*
609 * cs.base should really be 0xffff0000, but vmx can't handle that, so
610 * be consistent with it.
611 *
612 * Replace when we have real mode working for vmx.
613 */
614 save->cs.base = 0xf0000;
615
616 save->gdtr.limit = 0xffff;
617 save->idtr.limit = 0xffff;
618
619 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
620 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
621
622 save->efer = EFER_SVME;
623 save->dr6 = 0xffff0ff0;
624 save->dr7 = 0x400;
625 save->rflags = 2;
626 save->rip = 0x0000fff0;
627 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
628
629 /* This is the guest-visible cr0 value.
630 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
631 */
632 svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
633 kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
634
635 save->cr4 = X86_CR4_PAE;
636 /* rdx = ?? */
637
638 if (npt_enabled) {
639 /* Setup VMCB for Nested Paging */
640 control->nested_ctl = 1;
641 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
642 (1ULL << INTERCEPT_INVLPG));
643 control->intercept_exceptions &= ~(1 << PF_VECTOR);
644 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
645 INTERCEPT_CR3_MASK);
646 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
647 INTERCEPT_CR3_MASK);
648 save->g_pat = 0x0007040600070406ULL;
649 save->cr3 = 0;
650 save->cr4 = 0;
651 }
652 force_new_asid(&svm->vcpu);
653
654 svm->nested.vmcb = 0;
655 svm->vcpu.arch.hflags = 0;
656
657 if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
658 control->pause_filter_count = 3000;
659 control->intercept |= (1ULL << INTERCEPT_PAUSE);
660 }
661
662 enable_gif(svm);
663 }
664
665 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
666 {
667 struct vcpu_svm *svm = to_svm(vcpu);
668
669 init_vmcb(svm);
670
671 if (!kvm_vcpu_is_bsp(vcpu)) {
672 kvm_rip_write(vcpu, 0);
673 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
674 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
675 }
676 vcpu->arch.regs_avail = ~0;
677 vcpu->arch.regs_dirty = ~0;
678
679 return 0;
680 }
681
682 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
683 {
684 struct vcpu_svm *svm;
685 struct page *page;
686 struct page *msrpm_pages;
687 struct page *hsave_page;
688 struct page *nested_msrpm_pages;
689 int err;
690
691 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
692 if (!svm) {
693 err = -ENOMEM;
694 goto out;
695 }
696
697 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
698 if (err)
699 goto free_svm;
700
701 page = alloc_page(GFP_KERNEL);
702 if (!page) {
703 err = -ENOMEM;
704 goto uninit;
705 }
706
707 err = -ENOMEM;
708 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
709 if (!msrpm_pages)
710 goto uninit;
711
712 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
713 if (!nested_msrpm_pages)
714 goto uninit;
715
716 svm->msrpm = page_address(msrpm_pages);
717 svm_vcpu_init_msrpm(svm->msrpm);
718
719 hsave_page = alloc_page(GFP_KERNEL);
720 if (!hsave_page)
721 goto uninit;
722 svm->nested.hsave = page_address(hsave_page);
723
724 svm->nested.msrpm = page_address(nested_msrpm_pages);
725
726 svm->vmcb = page_address(page);
727 clear_page(svm->vmcb);
728 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
729 svm->asid_generation = 0;
730 init_vmcb(svm);
731
732 fx_init(&svm->vcpu);
733 svm->vcpu.fpu_active = 1;
734 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
735 if (kvm_vcpu_is_bsp(&svm->vcpu))
736 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
737
738 return &svm->vcpu;
739
740 uninit:
741 kvm_vcpu_uninit(&svm->vcpu);
742 free_svm:
743 kmem_cache_free(kvm_vcpu_cache, svm);
744 out:
745 return ERR_PTR(err);
746 }
747
748 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
749 {
750 struct vcpu_svm *svm = to_svm(vcpu);
751
752 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
753 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
754 __free_page(virt_to_page(svm->nested.hsave));
755 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
756 kvm_vcpu_uninit(vcpu);
757 kmem_cache_free(kvm_vcpu_cache, svm);
758 }
759
760 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
761 {
762 struct vcpu_svm *svm = to_svm(vcpu);
763 int i;
764
765 if (unlikely(cpu != vcpu->cpu)) {
766 u64 delta;
767
768 /*
769 * Make sure that the guest sees a monotonically
770 * increasing TSC.
771 */
772 delta = vcpu->arch.host_tsc - native_read_tsc();
773 svm->vmcb->control.tsc_offset += delta;
774 if (is_nested(svm))
775 svm->nested.hsave->control.tsc_offset += delta;
776 vcpu->cpu = cpu;
777 kvm_migrate_timers(vcpu);
778 svm->asid_generation = 0;
779 }
780
781 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
782 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
783 }
784
785 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
786 {
787 struct vcpu_svm *svm = to_svm(vcpu);
788 int i;
789
790 ++vcpu->stat.host_state_reload;
791 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
792 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
793
794 vcpu->arch.host_tsc = native_read_tsc();
795 }
796
797 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
798 {
799 return to_svm(vcpu)->vmcb->save.rflags;
800 }
801
802 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
803 {
804 to_svm(vcpu)->vmcb->save.rflags = rflags;
805 }
806
807 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
808 {
809 switch (reg) {
810 case VCPU_EXREG_PDPTR:
811 BUG_ON(!npt_enabled);
812 load_pdptrs(vcpu, vcpu->arch.cr3);
813 break;
814 default:
815 BUG();
816 }
817 }
818
819 static void svm_set_vintr(struct vcpu_svm *svm)
820 {
821 svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
822 }
823
824 static void svm_clear_vintr(struct vcpu_svm *svm)
825 {
826 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
827 }
828
829 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
830 {
831 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
832
833 switch (seg) {
834 case VCPU_SREG_CS: return &save->cs;
835 case VCPU_SREG_DS: return &save->ds;
836 case VCPU_SREG_ES: return &save->es;
837 case VCPU_SREG_FS: return &save->fs;
838 case VCPU_SREG_GS: return &save->gs;
839 case VCPU_SREG_SS: return &save->ss;
840 case VCPU_SREG_TR: return &save->tr;
841 case VCPU_SREG_LDTR: return &save->ldtr;
842 }
843 BUG();
844 return NULL;
845 }
846
847 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
848 {
849 struct vmcb_seg *s = svm_seg(vcpu, seg);
850
851 return s->base;
852 }
853
854 static void svm_get_segment(struct kvm_vcpu *vcpu,
855 struct kvm_segment *var, int seg)
856 {
857 struct vmcb_seg *s = svm_seg(vcpu, seg);
858
859 var->base = s->base;
860 var->limit = s->limit;
861 var->selector = s->selector;
862 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
863 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
864 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
865 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
866 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
867 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
868 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
869 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
870
871 /* AMD's VMCB does not have an explicit unusable field, so emulate it
872 * for cross vendor migration purposes by "not present"
873 */
874 var->unusable = !var->present || (var->type == 0);
875
876 switch (seg) {
877 case VCPU_SREG_CS:
878 /*
879 * SVM always stores 0 for the 'G' bit in the CS selector in
880 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
881 * Intel's VMENTRY has a check on the 'G' bit.
882 */
883 var->g = s->limit > 0xfffff;
884 break;
885 case VCPU_SREG_TR:
886 /*
887 * Work around a bug where the busy flag in the tr selector
888 * isn't exposed
889 */
890 var->type |= 0x2;
891 break;
892 case VCPU_SREG_DS:
893 case VCPU_SREG_ES:
894 case VCPU_SREG_FS:
895 case VCPU_SREG_GS:
896 /*
897 * The accessed bit must always be set in the segment
898 * descriptor cache, although it can be cleared in the
899 * descriptor, the cached bit always remains at 1. Since
900 * Intel has a check on this, set it here to support
901 * cross-vendor migration.
902 */
903 if (!var->unusable)
904 var->type |= 0x1;
905 break;
906 case VCPU_SREG_SS:
907 /* On AMD CPUs sometimes the DB bit in the segment
908 * descriptor is left as 1, although the whole segment has
909 * been made unusable. Clear it here to pass an Intel VMX
910 * entry check when cross vendor migrating.
911 */
912 if (var->unusable)
913 var->db = 0;
914 break;
915 }
916 }
917
918 static int svm_get_cpl(struct kvm_vcpu *vcpu)
919 {
920 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
921
922 return save->cpl;
923 }
924
925 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
926 {
927 struct vcpu_svm *svm = to_svm(vcpu);
928
929 dt->limit = svm->vmcb->save.idtr.limit;
930 dt->base = svm->vmcb->save.idtr.base;
931 }
932
933 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
934 {
935 struct vcpu_svm *svm = to_svm(vcpu);
936
937 svm->vmcb->save.idtr.limit = dt->limit;
938 svm->vmcb->save.idtr.base = dt->base ;
939 }
940
941 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
942 {
943 struct vcpu_svm *svm = to_svm(vcpu);
944
945 dt->limit = svm->vmcb->save.gdtr.limit;
946 dt->base = svm->vmcb->save.gdtr.base;
947 }
948
949 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
950 {
951 struct vcpu_svm *svm = to_svm(vcpu);
952
953 svm->vmcb->save.gdtr.limit = dt->limit;
954 svm->vmcb->save.gdtr.base = dt->base ;
955 }
956
957 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
958 {
959 }
960
961 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
962 {
963 struct vcpu_svm *svm = to_svm(vcpu);
964
965 #ifdef CONFIG_X86_64
966 if (vcpu->arch.shadow_efer & EFER_LME) {
967 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
968 vcpu->arch.shadow_efer |= EFER_LMA;
969 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
970 }
971
972 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
973 vcpu->arch.shadow_efer &= ~EFER_LMA;
974 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
975 }
976 }
977 #endif
978 if (npt_enabled)
979 goto set;
980
981 if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
982 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
983 vcpu->fpu_active = 1;
984 }
985
986 vcpu->arch.cr0 = cr0;
987 cr0 |= X86_CR0_PG | X86_CR0_WP;
988 if (!vcpu->fpu_active) {
989 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
990 cr0 |= X86_CR0_TS;
991 }
992 set:
993 /*
994 * re-enable caching here because the QEMU bios
995 * does not do it - this results in some delay at
996 * reboot
997 */
998 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
999 svm->vmcb->save.cr0 = cr0;
1000 }
1001
1002 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1003 {
1004 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1005 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1006
1007 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1008 force_new_asid(vcpu);
1009
1010 vcpu->arch.cr4 = cr4;
1011 if (!npt_enabled)
1012 cr4 |= X86_CR4_PAE;
1013 cr4 |= host_cr4_mce;
1014 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1015 }
1016
1017 static void svm_set_segment(struct kvm_vcpu *vcpu,
1018 struct kvm_segment *var, int seg)
1019 {
1020 struct vcpu_svm *svm = to_svm(vcpu);
1021 struct vmcb_seg *s = svm_seg(vcpu, seg);
1022
1023 s->base = var->base;
1024 s->limit = var->limit;
1025 s->selector = var->selector;
1026 if (var->unusable)
1027 s->attrib = 0;
1028 else {
1029 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1030 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1031 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1032 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1033 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1034 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1035 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1036 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1037 }
1038 if (seg == VCPU_SREG_CS)
1039 svm->vmcb->save.cpl
1040 = (svm->vmcb->save.cs.attrib
1041 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1042
1043 }
1044
1045 static void update_db_intercept(struct kvm_vcpu *vcpu)
1046 {
1047 struct vcpu_svm *svm = to_svm(vcpu);
1048
1049 svm->vmcb->control.intercept_exceptions &=
1050 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1051
1052 if (svm->nmi_singlestep)
1053 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1054
1055 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1056 if (vcpu->guest_debug &
1057 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1058 svm->vmcb->control.intercept_exceptions |=
1059 1 << DB_VECTOR;
1060 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1061 svm->vmcb->control.intercept_exceptions |=
1062 1 << BP_VECTOR;
1063 } else
1064 vcpu->guest_debug = 0;
1065 }
1066
1067 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1068 {
1069 struct vcpu_svm *svm = to_svm(vcpu);
1070
1071 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1072 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1073 else
1074 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1075
1076 update_db_intercept(vcpu);
1077 }
1078
1079 static void load_host_msrs(struct kvm_vcpu *vcpu)
1080 {
1081 #ifdef CONFIG_X86_64
1082 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1083 #endif
1084 }
1085
1086 static void save_host_msrs(struct kvm_vcpu *vcpu)
1087 {
1088 #ifdef CONFIG_X86_64
1089 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1090 #endif
1091 }
1092
1093 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1094 {
1095 if (sd->next_asid > sd->max_asid) {
1096 ++sd->asid_generation;
1097 sd->next_asid = 1;
1098 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1099 }
1100
1101 svm->asid_generation = sd->asid_generation;
1102 svm->vmcb->control.asid = sd->next_asid++;
1103 }
1104
1105 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1106 {
1107 struct vcpu_svm *svm = to_svm(vcpu);
1108 unsigned long val;
1109
1110 switch (dr) {
1111 case 0 ... 3:
1112 val = vcpu->arch.db[dr];
1113 break;
1114 case 6:
1115 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1116 val = vcpu->arch.dr6;
1117 else
1118 val = svm->vmcb->save.dr6;
1119 break;
1120 case 7:
1121 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1122 val = vcpu->arch.dr7;
1123 else
1124 val = svm->vmcb->save.dr7;
1125 break;
1126 default:
1127 val = 0;
1128 }
1129
1130 return val;
1131 }
1132
1133 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1134 int *exception)
1135 {
1136 struct vcpu_svm *svm = to_svm(vcpu);
1137
1138 *exception = 0;
1139
1140 switch (dr) {
1141 case 0 ... 3:
1142 vcpu->arch.db[dr] = value;
1143 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1144 vcpu->arch.eff_db[dr] = value;
1145 return;
1146 case 4 ... 5:
1147 if (vcpu->arch.cr4 & X86_CR4_DE)
1148 *exception = UD_VECTOR;
1149 return;
1150 case 6:
1151 if (value & 0xffffffff00000000ULL) {
1152 *exception = GP_VECTOR;
1153 return;
1154 }
1155 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1156 return;
1157 case 7:
1158 if (value & 0xffffffff00000000ULL) {
1159 *exception = GP_VECTOR;
1160 return;
1161 }
1162 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1163 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1164 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1165 vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1166 }
1167 return;
1168 default:
1169 /* FIXME: Possible case? */
1170 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1171 __func__, dr);
1172 *exception = UD_VECTOR;
1173 return;
1174 }
1175 }
1176
1177 static int pf_interception(struct vcpu_svm *svm)
1178 {
1179 u64 fault_address;
1180 u32 error_code;
1181
1182 fault_address = svm->vmcb->control.exit_info_2;
1183 error_code = svm->vmcb->control.exit_info_1;
1184
1185 trace_kvm_page_fault(fault_address, error_code);
1186 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1187 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1188 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1189 }
1190
1191 static int db_interception(struct vcpu_svm *svm)
1192 {
1193 struct kvm_run *kvm_run = svm->vcpu.run;
1194
1195 if (!(svm->vcpu.guest_debug &
1196 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1197 !svm->nmi_singlestep) {
1198 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1199 return 1;
1200 }
1201
1202 if (svm->nmi_singlestep) {
1203 svm->nmi_singlestep = false;
1204 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1205 svm->vmcb->save.rflags &=
1206 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1207 update_db_intercept(&svm->vcpu);
1208 }
1209
1210 if (svm->vcpu.guest_debug &
1211 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1212 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1213 kvm_run->debug.arch.pc =
1214 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1215 kvm_run->debug.arch.exception = DB_VECTOR;
1216 return 0;
1217 }
1218
1219 return 1;
1220 }
1221
1222 static int bp_interception(struct vcpu_svm *svm)
1223 {
1224 struct kvm_run *kvm_run = svm->vcpu.run;
1225
1226 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1227 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1228 kvm_run->debug.arch.exception = BP_VECTOR;
1229 return 0;
1230 }
1231
1232 static int ud_interception(struct vcpu_svm *svm)
1233 {
1234 int er;
1235
1236 er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1237 if (er != EMULATE_DONE)
1238 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1239 return 1;
1240 }
1241
1242 static int nm_interception(struct vcpu_svm *svm)
1243 {
1244 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1245 if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1246 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1247 svm->vcpu.fpu_active = 1;
1248
1249 return 1;
1250 }
1251
1252 static int mc_interception(struct vcpu_svm *svm)
1253 {
1254 /*
1255 * On an #MC intercept the MCE handler is not called automatically in
1256 * the host. So do it by hand here.
1257 */
1258 asm volatile (
1259 "int $0x12\n");
1260 /* not sure if we ever come back to this point */
1261
1262 return 1;
1263 }
1264
1265 static int shutdown_interception(struct vcpu_svm *svm)
1266 {
1267 struct kvm_run *kvm_run = svm->vcpu.run;
1268
1269 /*
1270 * VMCB is undefined after a SHUTDOWN intercept
1271 * so reinitialize it.
1272 */
1273 clear_page(svm->vmcb);
1274 init_vmcb(svm);
1275
1276 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1277 return 0;
1278 }
1279
1280 static int io_interception(struct vcpu_svm *svm)
1281 {
1282 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1283 int size, in, string;
1284 unsigned port;
1285
1286 ++svm->vcpu.stat.io_exits;
1287
1288 svm->next_rip = svm->vmcb->control.exit_info_2;
1289
1290 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1291
1292 if (string) {
1293 if (emulate_instruction(&svm->vcpu,
1294 0, 0, 0) == EMULATE_DO_MMIO)
1295 return 0;
1296 return 1;
1297 }
1298
1299 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1300 port = io_info >> 16;
1301 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1302
1303 skip_emulated_instruction(&svm->vcpu);
1304 return kvm_emulate_pio(&svm->vcpu, in, size, port);
1305 }
1306
1307 static int nmi_interception(struct vcpu_svm *svm)
1308 {
1309 return 1;
1310 }
1311
1312 static int intr_interception(struct vcpu_svm *svm)
1313 {
1314 ++svm->vcpu.stat.irq_exits;
1315 return 1;
1316 }
1317
1318 static int nop_on_interception(struct vcpu_svm *svm)
1319 {
1320 return 1;
1321 }
1322
1323 static int halt_interception(struct vcpu_svm *svm)
1324 {
1325 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1326 skip_emulated_instruction(&svm->vcpu);
1327 return kvm_emulate_halt(&svm->vcpu);
1328 }
1329
1330 static int vmmcall_interception(struct vcpu_svm *svm)
1331 {
1332 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1333 skip_emulated_instruction(&svm->vcpu);
1334 kvm_emulate_hypercall(&svm->vcpu);
1335 return 1;
1336 }
1337
1338 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1339 {
1340 if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1341 || !is_paging(&svm->vcpu)) {
1342 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1343 return 1;
1344 }
1345
1346 if (svm->vmcb->save.cpl) {
1347 kvm_inject_gp(&svm->vcpu, 0);
1348 return 1;
1349 }
1350
1351 return 0;
1352 }
1353
1354 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1355 bool has_error_code, u32 error_code)
1356 {
1357 if (!is_nested(svm))
1358 return 0;
1359
1360 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1361 svm->vmcb->control.exit_code_hi = 0;
1362 svm->vmcb->control.exit_info_1 = error_code;
1363 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1364
1365 return nested_svm_exit_handled(svm);
1366 }
1367
1368 static inline int nested_svm_intr(struct vcpu_svm *svm)
1369 {
1370 if (!is_nested(svm))
1371 return 0;
1372
1373 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1374 return 0;
1375
1376 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1377 return 0;
1378
1379 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1380
1381 if (svm->nested.intercept & 1ULL) {
1382 /*
1383 * The #vmexit can't be emulated here directly because this
1384 * code path runs with irqs and preemtion disabled. A
1385 * #vmexit emulation might sleep. Only signal request for
1386 * the #vmexit here.
1387 */
1388 svm->nested.exit_required = true;
1389 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1390 return 1;
1391 }
1392
1393 return 0;
1394 }
1395
1396 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
1397 {
1398 struct page *page;
1399
1400 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1401 if (is_error_page(page))
1402 goto error;
1403
1404 return kmap_atomic(page, idx);
1405
1406 error:
1407 kvm_release_page_clean(page);
1408 kvm_inject_gp(&svm->vcpu, 0);
1409
1410 return NULL;
1411 }
1412
1413 static void nested_svm_unmap(void *addr, enum km_type idx)
1414 {
1415 struct page *page;
1416
1417 if (!addr)
1418 return;
1419
1420 page = kmap_atomic_to_page(addr);
1421
1422 kunmap_atomic(addr, idx);
1423 kvm_release_page_dirty(page);
1424 }
1425
1426 static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1427 {
1428 u32 param = svm->vmcb->control.exit_info_1 & 1;
1429 u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1430 bool ret = false;
1431 u32 t0, t1;
1432 u8 *msrpm;
1433
1434 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1435 return false;
1436
1437 msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1438
1439 if (!msrpm)
1440 goto out;
1441
1442 switch (msr) {
1443 case 0 ... 0x1fff:
1444 t0 = (msr * 2) % 8;
1445 t1 = msr / 8;
1446 break;
1447 case 0xc0000000 ... 0xc0001fff:
1448 t0 = (8192 + msr - 0xc0000000) * 2;
1449 t1 = (t0 / 8);
1450 t0 %= 8;
1451 break;
1452 case 0xc0010000 ... 0xc0011fff:
1453 t0 = (16384 + msr - 0xc0010000) * 2;
1454 t1 = (t0 / 8);
1455 t0 %= 8;
1456 break;
1457 default:
1458 ret = true;
1459 goto out;
1460 }
1461
1462 ret = msrpm[t1] & ((1 << param) << t0);
1463
1464 out:
1465 nested_svm_unmap(msrpm, KM_USER0);
1466
1467 return ret;
1468 }
1469
1470 static int nested_svm_exit_special(struct vcpu_svm *svm)
1471 {
1472 u32 exit_code = svm->vmcb->control.exit_code;
1473
1474 switch (exit_code) {
1475 case SVM_EXIT_INTR:
1476 case SVM_EXIT_NMI:
1477 return NESTED_EXIT_HOST;
1478 /* For now we are always handling NPFs when using them */
1479 case SVM_EXIT_NPF:
1480 if (npt_enabled)
1481 return NESTED_EXIT_HOST;
1482 break;
1483 /* When we're shadowing, trap PFs */
1484 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1485 if (!npt_enabled)
1486 return NESTED_EXIT_HOST;
1487 break;
1488 default:
1489 break;
1490 }
1491
1492 return NESTED_EXIT_CONTINUE;
1493 }
1494
1495 /*
1496 * If this function returns true, this #vmexit was already handled
1497 */
1498 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1499 {
1500 u32 exit_code = svm->vmcb->control.exit_code;
1501 int vmexit = NESTED_EXIT_HOST;
1502
1503 switch (exit_code) {
1504 case SVM_EXIT_MSR:
1505 vmexit = nested_svm_exit_handled_msr(svm);
1506 break;
1507 case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1508 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1509 if (svm->nested.intercept_cr_read & cr_bits)
1510 vmexit = NESTED_EXIT_DONE;
1511 break;
1512 }
1513 case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1514 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1515 if (svm->nested.intercept_cr_write & cr_bits)
1516 vmexit = NESTED_EXIT_DONE;
1517 break;
1518 }
1519 case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1520 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1521 if (svm->nested.intercept_dr_read & dr_bits)
1522 vmexit = NESTED_EXIT_DONE;
1523 break;
1524 }
1525 case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1526 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1527 if (svm->nested.intercept_dr_write & dr_bits)
1528 vmexit = NESTED_EXIT_DONE;
1529 break;
1530 }
1531 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1532 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1533 if (svm->nested.intercept_exceptions & excp_bits)
1534 vmexit = NESTED_EXIT_DONE;
1535 break;
1536 }
1537 default: {
1538 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1539 if (svm->nested.intercept & exit_bits)
1540 vmexit = NESTED_EXIT_DONE;
1541 }
1542 }
1543
1544 if (vmexit == NESTED_EXIT_DONE) {
1545 nested_svm_vmexit(svm);
1546 }
1547
1548 return vmexit;
1549 }
1550
1551 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1552 {
1553 struct vmcb_control_area *dst = &dst_vmcb->control;
1554 struct vmcb_control_area *from = &from_vmcb->control;
1555
1556 dst->intercept_cr_read = from->intercept_cr_read;
1557 dst->intercept_cr_write = from->intercept_cr_write;
1558 dst->intercept_dr_read = from->intercept_dr_read;
1559 dst->intercept_dr_write = from->intercept_dr_write;
1560 dst->intercept_exceptions = from->intercept_exceptions;
1561 dst->intercept = from->intercept;
1562 dst->iopm_base_pa = from->iopm_base_pa;
1563 dst->msrpm_base_pa = from->msrpm_base_pa;
1564 dst->tsc_offset = from->tsc_offset;
1565 dst->asid = from->asid;
1566 dst->tlb_ctl = from->tlb_ctl;
1567 dst->int_ctl = from->int_ctl;
1568 dst->int_vector = from->int_vector;
1569 dst->int_state = from->int_state;
1570 dst->exit_code = from->exit_code;
1571 dst->exit_code_hi = from->exit_code_hi;
1572 dst->exit_info_1 = from->exit_info_1;
1573 dst->exit_info_2 = from->exit_info_2;
1574 dst->exit_int_info = from->exit_int_info;
1575 dst->exit_int_info_err = from->exit_int_info_err;
1576 dst->nested_ctl = from->nested_ctl;
1577 dst->event_inj = from->event_inj;
1578 dst->event_inj_err = from->event_inj_err;
1579 dst->nested_cr3 = from->nested_cr3;
1580 dst->lbr_ctl = from->lbr_ctl;
1581 }
1582
1583 static int nested_svm_vmexit(struct vcpu_svm *svm)
1584 {
1585 struct vmcb *nested_vmcb;
1586 struct vmcb *hsave = svm->nested.hsave;
1587 struct vmcb *vmcb = svm->vmcb;
1588
1589 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1590 vmcb->control.exit_info_1,
1591 vmcb->control.exit_info_2,
1592 vmcb->control.exit_int_info,
1593 vmcb->control.exit_int_info_err);
1594
1595 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
1596 if (!nested_vmcb)
1597 return 1;
1598
1599 /* Give the current vmcb to the guest */
1600 disable_gif(svm);
1601
1602 nested_vmcb->save.es = vmcb->save.es;
1603 nested_vmcb->save.cs = vmcb->save.cs;
1604 nested_vmcb->save.ss = vmcb->save.ss;
1605 nested_vmcb->save.ds = vmcb->save.ds;
1606 nested_vmcb->save.gdtr = vmcb->save.gdtr;
1607 nested_vmcb->save.idtr = vmcb->save.idtr;
1608 if (npt_enabled)
1609 nested_vmcb->save.cr3 = vmcb->save.cr3;
1610 nested_vmcb->save.cr2 = vmcb->save.cr2;
1611 nested_vmcb->save.rflags = vmcb->save.rflags;
1612 nested_vmcb->save.rip = vmcb->save.rip;
1613 nested_vmcb->save.rsp = vmcb->save.rsp;
1614 nested_vmcb->save.rax = vmcb->save.rax;
1615 nested_vmcb->save.dr7 = vmcb->save.dr7;
1616 nested_vmcb->save.dr6 = vmcb->save.dr6;
1617 nested_vmcb->save.cpl = vmcb->save.cpl;
1618
1619 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
1620 nested_vmcb->control.int_vector = vmcb->control.int_vector;
1621 nested_vmcb->control.int_state = vmcb->control.int_state;
1622 nested_vmcb->control.exit_code = vmcb->control.exit_code;
1623 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
1624 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
1625 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
1626 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
1627 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1628
1629 /*
1630 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1631 * to make sure that we do not lose injected events. So check event_inj
1632 * here and copy it to exit_int_info if it is valid.
1633 * Exit_int_info and event_inj can't be both valid because the case
1634 * below only happens on a VMRUN instruction intercept which has
1635 * no valid exit_int_info set.
1636 */
1637 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1638 struct vmcb_control_area *nc = &nested_vmcb->control;
1639
1640 nc->exit_int_info = vmcb->control.event_inj;
1641 nc->exit_int_info_err = vmcb->control.event_inj_err;
1642 }
1643
1644 nested_vmcb->control.tlb_ctl = 0;
1645 nested_vmcb->control.event_inj = 0;
1646 nested_vmcb->control.event_inj_err = 0;
1647
1648 /* We always set V_INTR_MASKING and remember the old value in hflags */
1649 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1650 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1651
1652 /* Restore the original control entries */
1653 copy_vmcb_control_area(vmcb, hsave);
1654
1655 kvm_clear_exception_queue(&svm->vcpu);
1656 kvm_clear_interrupt_queue(&svm->vcpu);
1657
1658 /* Restore selected save entries */
1659 svm->vmcb->save.es = hsave->save.es;
1660 svm->vmcb->save.cs = hsave->save.cs;
1661 svm->vmcb->save.ss = hsave->save.ss;
1662 svm->vmcb->save.ds = hsave->save.ds;
1663 svm->vmcb->save.gdtr = hsave->save.gdtr;
1664 svm->vmcb->save.idtr = hsave->save.idtr;
1665 svm->vmcb->save.rflags = hsave->save.rflags;
1666 svm_set_efer(&svm->vcpu, hsave->save.efer);
1667 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1668 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1669 if (npt_enabled) {
1670 svm->vmcb->save.cr3 = hsave->save.cr3;
1671 svm->vcpu.arch.cr3 = hsave->save.cr3;
1672 } else {
1673 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1674 }
1675 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1676 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1677 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1678 svm->vmcb->save.dr7 = 0;
1679 svm->vmcb->save.cpl = 0;
1680 svm->vmcb->control.exit_int_info = 0;
1681
1682 /* Exit nested SVM mode */
1683 svm->nested.vmcb = 0;
1684
1685 nested_svm_unmap(nested_vmcb, KM_USER0);
1686
1687 kvm_mmu_reset_context(&svm->vcpu);
1688 kvm_mmu_load(&svm->vcpu);
1689
1690 return 0;
1691 }
1692
1693 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1694 {
1695 u32 *nested_msrpm;
1696 int i;
1697
1698 nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
1699 if (!nested_msrpm)
1700 return false;
1701
1702 for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1703 svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1704
1705 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1706
1707 nested_svm_unmap(nested_msrpm, KM_USER0);
1708
1709 return true;
1710 }
1711
1712 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1713 {
1714 struct vmcb *nested_vmcb;
1715 struct vmcb *hsave = svm->nested.hsave;
1716 struct vmcb *vmcb = svm->vmcb;
1717
1718 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1719 if (!nested_vmcb)
1720 return false;
1721
1722 /* nested_vmcb is our indicator if nested SVM is activated */
1723 svm->nested.vmcb = svm->vmcb->save.rax;
1724
1725 trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, svm->nested.vmcb,
1726 nested_vmcb->save.rip,
1727 nested_vmcb->control.int_ctl,
1728 nested_vmcb->control.event_inj,
1729 nested_vmcb->control.nested_ctl);
1730
1731 /* Clear internal status */
1732 kvm_clear_exception_queue(&svm->vcpu);
1733 kvm_clear_interrupt_queue(&svm->vcpu);
1734
1735 /* Save the old vmcb, so we don't need to pick what we save, but
1736 can restore everything when a VMEXIT occurs */
1737 hsave->save.es = vmcb->save.es;
1738 hsave->save.cs = vmcb->save.cs;
1739 hsave->save.ss = vmcb->save.ss;
1740 hsave->save.ds = vmcb->save.ds;
1741 hsave->save.gdtr = vmcb->save.gdtr;
1742 hsave->save.idtr = vmcb->save.idtr;
1743 hsave->save.efer = svm->vcpu.arch.shadow_efer;
1744 hsave->save.cr0 = svm->vcpu.arch.cr0;
1745 hsave->save.cr4 = svm->vcpu.arch.cr4;
1746 hsave->save.rflags = vmcb->save.rflags;
1747 hsave->save.rip = svm->next_rip;
1748 hsave->save.rsp = vmcb->save.rsp;
1749 hsave->save.rax = vmcb->save.rax;
1750 if (npt_enabled)
1751 hsave->save.cr3 = vmcb->save.cr3;
1752 else
1753 hsave->save.cr3 = svm->vcpu.arch.cr3;
1754
1755 copy_vmcb_control_area(hsave, vmcb);
1756
1757 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1758 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1759 else
1760 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1761
1762 /* Load the nested guest state */
1763 svm->vmcb->save.es = nested_vmcb->save.es;
1764 svm->vmcb->save.cs = nested_vmcb->save.cs;
1765 svm->vmcb->save.ss = nested_vmcb->save.ss;
1766 svm->vmcb->save.ds = nested_vmcb->save.ds;
1767 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1768 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1769 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1770 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1771 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1772 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1773 if (npt_enabled) {
1774 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1775 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1776 } else {
1777 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1778 kvm_mmu_reset_context(&svm->vcpu);
1779 }
1780 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
1781 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1782 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1783 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1784 /* In case we don't even reach vcpu_run, the fields are not updated */
1785 svm->vmcb->save.rax = nested_vmcb->save.rax;
1786 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1787 svm->vmcb->save.rip = nested_vmcb->save.rip;
1788 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1789 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1790 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1791
1792 /* We don't want a nested guest to be more powerful than the guest,
1793 so all intercepts are ORed */
1794 svm->vmcb->control.intercept_cr_read |=
1795 nested_vmcb->control.intercept_cr_read;
1796 svm->vmcb->control.intercept_cr_write |=
1797 nested_vmcb->control.intercept_cr_write;
1798 svm->vmcb->control.intercept_dr_read |=
1799 nested_vmcb->control.intercept_dr_read;
1800 svm->vmcb->control.intercept_dr_write |=
1801 nested_vmcb->control.intercept_dr_write;
1802 svm->vmcb->control.intercept_exceptions |=
1803 nested_vmcb->control.intercept_exceptions;
1804
1805 svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1806
1807 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1808
1809 /* cache intercepts */
1810 svm->nested.intercept_cr_read = nested_vmcb->control.intercept_cr_read;
1811 svm->nested.intercept_cr_write = nested_vmcb->control.intercept_cr_write;
1812 svm->nested.intercept_dr_read = nested_vmcb->control.intercept_dr_read;
1813 svm->nested.intercept_dr_write = nested_vmcb->control.intercept_dr_write;
1814 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
1815 svm->nested.intercept = nested_vmcb->control.intercept;
1816
1817 force_new_asid(&svm->vcpu);
1818 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1819 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1820 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1821 else
1822 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1823
1824 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1825 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1826 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1827 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1828 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1829
1830 nested_svm_unmap(nested_vmcb, KM_USER0);
1831
1832 enable_gif(svm);
1833
1834 return true;
1835 }
1836
1837 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1838 {
1839 to_vmcb->save.fs = from_vmcb->save.fs;
1840 to_vmcb->save.gs = from_vmcb->save.gs;
1841 to_vmcb->save.tr = from_vmcb->save.tr;
1842 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1843 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1844 to_vmcb->save.star = from_vmcb->save.star;
1845 to_vmcb->save.lstar = from_vmcb->save.lstar;
1846 to_vmcb->save.cstar = from_vmcb->save.cstar;
1847 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1848 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1849 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1850 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1851 }
1852
1853 static int vmload_interception(struct vcpu_svm *svm)
1854 {
1855 struct vmcb *nested_vmcb;
1856
1857 if (nested_svm_check_permissions(svm))
1858 return 1;
1859
1860 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1861 skip_emulated_instruction(&svm->vcpu);
1862
1863 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1864 if (!nested_vmcb)
1865 return 1;
1866
1867 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1868 nested_svm_unmap(nested_vmcb, KM_USER0);
1869
1870 return 1;
1871 }
1872
1873 static int vmsave_interception(struct vcpu_svm *svm)
1874 {
1875 struct vmcb *nested_vmcb;
1876
1877 if (nested_svm_check_permissions(svm))
1878 return 1;
1879
1880 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1881 skip_emulated_instruction(&svm->vcpu);
1882
1883 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
1884 if (!nested_vmcb)
1885 return 1;
1886
1887 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1888 nested_svm_unmap(nested_vmcb, KM_USER0);
1889
1890 return 1;
1891 }
1892
1893 static int vmrun_interception(struct vcpu_svm *svm)
1894 {
1895 if (nested_svm_check_permissions(svm))
1896 return 1;
1897
1898 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1899 skip_emulated_instruction(&svm->vcpu);
1900
1901 if (!nested_svm_vmrun(svm))
1902 return 1;
1903
1904 if (!nested_svm_vmrun_msrpm(svm))
1905 goto failed;
1906
1907 return 1;
1908
1909 failed:
1910
1911 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
1912 svm->vmcb->control.exit_code_hi = 0;
1913 svm->vmcb->control.exit_info_1 = 0;
1914 svm->vmcb->control.exit_info_2 = 0;
1915
1916 nested_svm_vmexit(svm);
1917
1918 return 1;
1919 }
1920
1921 static int stgi_interception(struct vcpu_svm *svm)
1922 {
1923 if (nested_svm_check_permissions(svm))
1924 return 1;
1925
1926 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1927 skip_emulated_instruction(&svm->vcpu);
1928
1929 enable_gif(svm);
1930
1931 return 1;
1932 }
1933
1934 static int clgi_interception(struct vcpu_svm *svm)
1935 {
1936 if (nested_svm_check_permissions(svm))
1937 return 1;
1938
1939 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1940 skip_emulated_instruction(&svm->vcpu);
1941
1942 disable_gif(svm);
1943
1944 /* After a CLGI no interrupts should come */
1945 svm_clear_vintr(svm);
1946 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1947
1948 return 1;
1949 }
1950
1951 static int invlpga_interception(struct vcpu_svm *svm)
1952 {
1953 struct kvm_vcpu *vcpu = &svm->vcpu;
1954
1955 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
1956 vcpu->arch.regs[VCPU_REGS_RAX]);
1957
1958 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
1959 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
1960
1961 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1962 skip_emulated_instruction(&svm->vcpu);
1963 return 1;
1964 }
1965
1966 static int skinit_interception(struct vcpu_svm *svm)
1967 {
1968 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
1969
1970 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1971 return 1;
1972 }
1973
1974 static int invalid_op_interception(struct vcpu_svm *svm)
1975 {
1976 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1977 return 1;
1978 }
1979
1980 static int task_switch_interception(struct vcpu_svm *svm)
1981 {
1982 u16 tss_selector;
1983 int reason;
1984 int int_type = svm->vmcb->control.exit_int_info &
1985 SVM_EXITINTINFO_TYPE_MASK;
1986 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1987 uint32_t type =
1988 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1989 uint32_t idt_v =
1990 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1991
1992 tss_selector = (u16)svm->vmcb->control.exit_info_1;
1993
1994 if (svm->vmcb->control.exit_info_2 &
1995 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1996 reason = TASK_SWITCH_IRET;
1997 else if (svm->vmcb->control.exit_info_2 &
1998 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1999 reason = TASK_SWITCH_JMP;
2000 else if (idt_v)
2001 reason = TASK_SWITCH_GATE;
2002 else
2003 reason = TASK_SWITCH_CALL;
2004
2005 if (reason == TASK_SWITCH_GATE) {
2006 switch (type) {
2007 case SVM_EXITINTINFO_TYPE_NMI:
2008 svm->vcpu.arch.nmi_injected = false;
2009 break;
2010 case SVM_EXITINTINFO_TYPE_EXEPT:
2011 kvm_clear_exception_queue(&svm->vcpu);
2012 break;
2013 case SVM_EXITINTINFO_TYPE_INTR:
2014 kvm_clear_interrupt_queue(&svm->vcpu);
2015 break;
2016 default:
2017 break;
2018 }
2019 }
2020
2021 if (reason != TASK_SWITCH_GATE ||
2022 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2023 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2024 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2025 skip_emulated_instruction(&svm->vcpu);
2026
2027 return kvm_task_switch(&svm->vcpu, tss_selector, reason);
2028 }
2029
2030 static int cpuid_interception(struct vcpu_svm *svm)
2031 {
2032 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2033 kvm_emulate_cpuid(&svm->vcpu);
2034 return 1;
2035 }
2036
2037 static int iret_interception(struct vcpu_svm *svm)
2038 {
2039 ++svm->vcpu.stat.nmi_window_exits;
2040 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2041 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2042 return 1;
2043 }
2044
2045 static int invlpg_interception(struct vcpu_svm *svm)
2046 {
2047 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2048 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2049 return 1;
2050 }
2051
2052 static int emulate_on_interception(struct vcpu_svm *svm)
2053 {
2054 if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2055 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2056 return 1;
2057 }
2058
2059 static int cr8_write_interception(struct vcpu_svm *svm)
2060 {
2061 struct kvm_run *kvm_run = svm->vcpu.run;
2062
2063 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2064 /* instruction emulation calls kvm_set_cr8() */
2065 emulate_instruction(&svm->vcpu, 0, 0, 0);
2066 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2067 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2068 return 1;
2069 }
2070 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2071 return 1;
2072 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2073 return 0;
2074 }
2075
2076 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2077 {
2078 struct vcpu_svm *svm = to_svm(vcpu);
2079
2080 switch (ecx) {
2081 case MSR_IA32_TSC: {
2082 u64 tsc_offset;
2083
2084 if (is_nested(svm))
2085 tsc_offset = svm->nested.hsave->control.tsc_offset;
2086 else
2087 tsc_offset = svm->vmcb->control.tsc_offset;
2088
2089 *data = tsc_offset + native_read_tsc();
2090 break;
2091 }
2092 case MSR_K6_STAR:
2093 *data = svm->vmcb->save.star;
2094 break;
2095 #ifdef CONFIG_X86_64
2096 case MSR_LSTAR:
2097 *data = svm->vmcb->save.lstar;
2098 break;
2099 case MSR_CSTAR:
2100 *data = svm->vmcb->save.cstar;
2101 break;
2102 case MSR_KERNEL_GS_BASE:
2103 *data = svm->vmcb->save.kernel_gs_base;
2104 break;
2105 case MSR_SYSCALL_MASK:
2106 *data = svm->vmcb->save.sfmask;
2107 break;
2108 #endif
2109 case MSR_IA32_SYSENTER_CS:
2110 *data = svm->vmcb->save.sysenter_cs;
2111 break;
2112 case MSR_IA32_SYSENTER_EIP:
2113 *data = svm->sysenter_eip;
2114 break;
2115 case MSR_IA32_SYSENTER_ESP:
2116 *data = svm->sysenter_esp;
2117 break;
2118 /* Nobody will change the following 5 values in the VMCB so
2119 we can safely return them on rdmsr. They will always be 0
2120 until LBRV is implemented. */
2121 case MSR_IA32_DEBUGCTLMSR:
2122 *data = svm->vmcb->save.dbgctl;
2123 break;
2124 case MSR_IA32_LASTBRANCHFROMIP:
2125 *data = svm->vmcb->save.br_from;
2126 break;
2127 case MSR_IA32_LASTBRANCHTOIP:
2128 *data = svm->vmcb->save.br_to;
2129 break;
2130 case MSR_IA32_LASTINTFROMIP:
2131 *data = svm->vmcb->save.last_excp_from;
2132 break;
2133 case MSR_IA32_LASTINTTOIP:
2134 *data = svm->vmcb->save.last_excp_to;
2135 break;
2136 case MSR_VM_HSAVE_PA:
2137 *data = svm->nested.hsave_msr;
2138 break;
2139 case MSR_VM_CR:
2140 *data = 0;
2141 break;
2142 case MSR_IA32_UCODE_REV:
2143 *data = 0x01000065;
2144 break;
2145 default:
2146 return kvm_get_msr_common(vcpu, ecx, data);
2147 }
2148 return 0;
2149 }
2150
2151 static int rdmsr_interception(struct vcpu_svm *svm)
2152 {
2153 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2154 u64 data;
2155
2156 if (svm_get_msr(&svm->vcpu, ecx, &data))
2157 kvm_inject_gp(&svm->vcpu, 0);
2158 else {
2159 trace_kvm_msr_read(ecx, data);
2160
2161 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2162 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2163 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2164 skip_emulated_instruction(&svm->vcpu);
2165 }
2166 return 1;
2167 }
2168
2169 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2170 {
2171 struct vcpu_svm *svm = to_svm(vcpu);
2172
2173 switch (ecx) {
2174 case MSR_IA32_TSC: {
2175 u64 tsc_offset = data - native_read_tsc();
2176 u64 g_tsc_offset = 0;
2177
2178 if (is_nested(svm)) {
2179 g_tsc_offset = svm->vmcb->control.tsc_offset -
2180 svm->nested.hsave->control.tsc_offset;
2181 svm->nested.hsave->control.tsc_offset = tsc_offset;
2182 }
2183
2184 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2185
2186 break;
2187 }
2188 case MSR_K6_STAR:
2189 svm->vmcb->save.star = data;
2190 break;
2191 #ifdef CONFIG_X86_64
2192 case MSR_LSTAR:
2193 svm->vmcb->save.lstar = data;
2194 break;
2195 case MSR_CSTAR:
2196 svm->vmcb->save.cstar = data;
2197 break;
2198 case MSR_KERNEL_GS_BASE:
2199 svm->vmcb->save.kernel_gs_base = data;
2200 break;
2201 case MSR_SYSCALL_MASK:
2202 svm->vmcb->save.sfmask = data;
2203 break;
2204 #endif
2205 case MSR_IA32_SYSENTER_CS:
2206 svm->vmcb->save.sysenter_cs = data;
2207 break;
2208 case MSR_IA32_SYSENTER_EIP:
2209 svm->sysenter_eip = data;
2210 svm->vmcb->save.sysenter_eip = data;
2211 break;
2212 case MSR_IA32_SYSENTER_ESP:
2213 svm->sysenter_esp = data;
2214 svm->vmcb->save.sysenter_esp = data;
2215 break;
2216 case MSR_IA32_DEBUGCTLMSR:
2217 if (!svm_has(SVM_FEATURE_LBRV)) {
2218 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2219 __func__, data);
2220 break;
2221 }
2222 if (data & DEBUGCTL_RESERVED_BITS)
2223 return 1;
2224
2225 svm->vmcb->save.dbgctl = data;
2226 if (data & (1ULL<<0))
2227 svm_enable_lbrv(svm);
2228 else
2229 svm_disable_lbrv(svm);
2230 break;
2231 case MSR_VM_HSAVE_PA:
2232 svm->nested.hsave_msr = data;
2233 break;
2234 case MSR_VM_CR:
2235 case MSR_VM_IGNNE:
2236 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2237 break;
2238 default:
2239 return kvm_set_msr_common(vcpu, ecx, data);
2240 }
2241 return 0;
2242 }
2243
2244 static int wrmsr_interception(struct vcpu_svm *svm)
2245 {
2246 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2247 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2248 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2249
2250 trace_kvm_msr_write(ecx, data);
2251
2252 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2253 if (svm_set_msr(&svm->vcpu, ecx, data))
2254 kvm_inject_gp(&svm->vcpu, 0);
2255 else
2256 skip_emulated_instruction(&svm->vcpu);
2257 return 1;
2258 }
2259
2260 static int msr_interception(struct vcpu_svm *svm)
2261 {
2262 if (svm->vmcb->control.exit_info_1)
2263 return wrmsr_interception(svm);
2264 else
2265 return rdmsr_interception(svm);
2266 }
2267
2268 static int interrupt_window_interception(struct vcpu_svm *svm)
2269 {
2270 struct kvm_run *kvm_run = svm->vcpu.run;
2271
2272 svm_clear_vintr(svm);
2273 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2274 /*
2275 * If the user space waits to inject interrupts, exit as soon as
2276 * possible
2277 */
2278 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2279 kvm_run->request_interrupt_window &&
2280 !kvm_cpu_has_interrupt(&svm->vcpu)) {
2281 ++svm->vcpu.stat.irq_window_exits;
2282 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2283 return 0;
2284 }
2285
2286 return 1;
2287 }
2288
2289 static int pause_interception(struct vcpu_svm *svm)
2290 {
2291 kvm_vcpu_on_spin(&(svm->vcpu));
2292 return 1;
2293 }
2294
2295 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2296 [SVM_EXIT_READ_CR0] = emulate_on_interception,
2297 [SVM_EXIT_READ_CR3] = emulate_on_interception,
2298 [SVM_EXIT_READ_CR4] = emulate_on_interception,
2299 [SVM_EXIT_READ_CR8] = emulate_on_interception,
2300 /* for now: */
2301 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
2302 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
2303 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
2304 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2305 [SVM_EXIT_READ_DR0] = emulate_on_interception,
2306 [SVM_EXIT_READ_DR1] = emulate_on_interception,
2307 [SVM_EXIT_READ_DR2] = emulate_on_interception,
2308 [SVM_EXIT_READ_DR3] = emulate_on_interception,
2309 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
2310 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
2311 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
2312 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
2313 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
2314 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
2315 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2316 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2317 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2318 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2319 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
2320 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2321 [SVM_EXIT_INTR] = intr_interception,
2322 [SVM_EXIT_NMI] = nmi_interception,
2323 [SVM_EXIT_SMI] = nop_on_interception,
2324 [SVM_EXIT_INIT] = nop_on_interception,
2325 [SVM_EXIT_VINTR] = interrupt_window_interception,
2326 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
2327 [SVM_EXIT_CPUID] = cpuid_interception,
2328 [SVM_EXIT_IRET] = iret_interception,
2329 [SVM_EXIT_INVD] = emulate_on_interception,
2330 [SVM_EXIT_PAUSE] = pause_interception,
2331 [SVM_EXIT_HLT] = halt_interception,
2332 [SVM_EXIT_INVLPG] = invlpg_interception,
2333 [SVM_EXIT_INVLPGA] = invlpga_interception,
2334 [SVM_EXIT_IOIO] = io_interception,
2335 [SVM_EXIT_MSR] = msr_interception,
2336 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2337 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2338 [SVM_EXIT_VMRUN] = vmrun_interception,
2339 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2340 [SVM_EXIT_VMLOAD] = vmload_interception,
2341 [SVM_EXIT_VMSAVE] = vmsave_interception,
2342 [SVM_EXIT_STGI] = stgi_interception,
2343 [SVM_EXIT_CLGI] = clgi_interception,
2344 [SVM_EXIT_SKINIT] = skinit_interception,
2345 [SVM_EXIT_WBINVD] = emulate_on_interception,
2346 [SVM_EXIT_MONITOR] = invalid_op_interception,
2347 [SVM_EXIT_MWAIT] = invalid_op_interception,
2348 [SVM_EXIT_NPF] = pf_interception,
2349 };
2350
2351 static int handle_exit(struct kvm_vcpu *vcpu)
2352 {
2353 struct vcpu_svm *svm = to_svm(vcpu);
2354 struct kvm_run *kvm_run = vcpu->run;
2355 u32 exit_code = svm->vmcb->control.exit_code;
2356
2357 trace_kvm_exit(exit_code, svm->vmcb->save.rip);
2358
2359 if (unlikely(svm->nested.exit_required)) {
2360 nested_svm_vmexit(svm);
2361 svm->nested.exit_required = false;
2362
2363 return 1;
2364 }
2365
2366 if (is_nested(svm)) {
2367 int vmexit;
2368
2369 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2370 svm->vmcb->control.exit_info_1,
2371 svm->vmcb->control.exit_info_2,
2372 svm->vmcb->control.exit_int_info,
2373 svm->vmcb->control.exit_int_info_err);
2374
2375 vmexit = nested_svm_exit_special(svm);
2376
2377 if (vmexit == NESTED_EXIT_CONTINUE)
2378 vmexit = nested_svm_exit_handled(svm);
2379
2380 if (vmexit == NESTED_EXIT_DONE)
2381 return 1;
2382 }
2383
2384 svm_complete_interrupts(svm);
2385
2386 if (npt_enabled) {
2387 int mmu_reload = 0;
2388 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2389 svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2390 mmu_reload = 1;
2391 }
2392 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2393 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2394 if (mmu_reload) {
2395 kvm_mmu_reset_context(vcpu);
2396 kvm_mmu_load(vcpu);
2397 }
2398 }
2399
2400
2401 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2402 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2403 kvm_run->fail_entry.hardware_entry_failure_reason
2404 = svm->vmcb->control.exit_code;
2405 return 0;
2406 }
2407
2408 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2409 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2410 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2411 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2412 "exit_code 0x%x\n",
2413 __func__, svm->vmcb->control.exit_int_info,
2414 exit_code);
2415
2416 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2417 || !svm_exit_handlers[exit_code]) {
2418 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2419 kvm_run->hw.hardware_exit_reason = exit_code;
2420 return 0;
2421 }
2422
2423 return svm_exit_handlers[exit_code](svm);
2424 }
2425
2426 static void reload_tss(struct kvm_vcpu *vcpu)
2427 {
2428 int cpu = raw_smp_processor_id();
2429
2430 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2431 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2432 load_TR_desc();
2433 }
2434
2435 static void pre_svm_run(struct vcpu_svm *svm)
2436 {
2437 int cpu = raw_smp_processor_id();
2438
2439 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2440
2441 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2442 /* FIXME: handle wraparound of asid_generation */
2443 if (svm->asid_generation != sd->asid_generation)
2444 new_asid(svm, sd);
2445 }
2446
2447 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2448 {
2449 struct vcpu_svm *svm = to_svm(vcpu);
2450
2451 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2452 vcpu->arch.hflags |= HF_NMI_MASK;
2453 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2454 ++vcpu->stat.nmi_injections;
2455 }
2456
2457 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2458 {
2459 struct vmcb_control_area *control;
2460
2461 trace_kvm_inj_virq(irq);
2462
2463 ++svm->vcpu.stat.irq_injections;
2464 control = &svm->vmcb->control;
2465 control->int_vector = irq;
2466 control->int_ctl &= ~V_INTR_PRIO_MASK;
2467 control->int_ctl |= V_IRQ_MASK |
2468 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2469 }
2470
2471 static void svm_set_irq(struct kvm_vcpu *vcpu)
2472 {
2473 struct vcpu_svm *svm = to_svm(vcpu);
2474
2475 BUG_ON(!(gif_set(svm)));
2476
2477 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2478 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2479 }
2480
2481 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2482 {
2483 struct vcpu_svm *svm = to_svm(vcpu);
2484
2485 if (irr == -1)
2486 return;
2487
2488 if (tpr >= irr)
2489 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2490 }
2491
2492 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2493 {
2494 struct vcpu_svm *svm = to_svm(vcpu);
2495 struct vmcb *vmcb = svm->vmcb;
2496 return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2497 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2498 }
2499
2500 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2501 {
2502 struct vcpu_svm *svm = to_svm(vcpu);
2503
2504 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2505 }
2506
2507 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2508 {
2509 struct vcpu_svm *svm = to_svm(vcpu);
2510
2511 if (masked) {
2512 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2513 svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2514 } else {
2515 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2516 svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
2517 }
2518 }
2519
2520 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2521 {
2522 struct vcpu_svm *svm = to_svm(vcpu);
2523 struct vmcb *vmcb = svm->vmcb;
2524 int ret;
2525
2526 if (!gif_set(svm) ||
2527 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2528 return 0;
2529
2530 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2531
2532 if (is_nested(svm))
2533 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2534
2535 return ret;
2536 }
2537
2538 static void enable_irq_window(struct kvm_vcpu *vcpu)
2539 {
2540 struct vcpu_svm *svm = to_svm(vcpu);
2541
2542 nested_svm_intr(svm);
2543
2544 /* In case GIF=0 we can't rely on the CPU to tell us when
2545 * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
2546 * The next time we get that intercept, this function will be
2547 * called again though and we'll get the vintr intercept. */
2548 if (gif_set(svm)) {
2549 svm_set_vintr(svm);
2550 svm_inject_irq(svm, 0x0);
2551 }
2552 }
2553
2554 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2555 {
2556 struct vcpu_svm *svm = to_svm(vcpu);
2557
2558 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2559 == HF_NMI_MASK)
2560 return; /* IRET will cause a vm exit */
2561
2562 /* Something prevents NMI from been injected. Single step over
2563 possible problem (IRET or exception injection or interrupt
2564 shadow) */
2565 svm->nmi_singlestep = true;
2566 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2567 update_db_intercept(vcpu);
2568 }
2569
2570 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2571 {
2572 return 0;
2573 }
2574
2575 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2576 {
2577 force_new_asid(vcpu);
2578 }
2579
2580 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2581 {
2582 }
2583
2584 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2585 {
2586 struct vcpu_svm *svm = to_svm(vcpu);
2587
2588 if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2589 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2590 kvm_set_cr8(vcpu, cr8);
2591 }
2592 }
2593
2594 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2595 {
2596 struct vcpu_svm *svm = to_svm(vcpu);
2597 u64 cr8;
2598
2599 cr8 = kvm_get_cr8(vcpu);
2600 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2601 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2602 }
2603
2604 static void svm_complete_interrupts(struct vcpu_svm *svm)
2605 {
2606 u8 vector;
2607 int type;
2608 u32 exitintinfo = svm->vmcb->control.exit_int_info;
2609
2610 if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2611 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2612
2613 svm->vcpu.arch.nmi_injected = false;
2614 kvm_clear_exception_queue(&svm->vcpu);
2615 kvm_clear_interrupt_queue(&svm->vcpu);
2616
2617 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2618 return;
2619
2620 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2621 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2622
2623 switch (type) {
2624 case SVM_EXITINTINFO_TYPE_NMI:
2625 svm->vcpu.arch.nmi_injected = true;
2626 break;
2627 case SVM_EXITINTINFO_TYPE_EXEPT:
2628 /* In case of software exception do not reinject an exception
2629 vector, but re-execute and instruction instead */
2630 if (is_nested(svm))
2631 break;
2632 if (kvm_exception_is_soft(vector))
2633 break;
2634 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2635 u32 err = svm->vmcb->control.exit_int_info_err;
2636 kvm_queue_exception_e(&svm->vcpu, vector, err);
2637
2638 } else
2639 kvm_queue_exception(&svm->vcpu, vector);
2640 break;
2641 case SVM_EXITINTINFO_TYPE_INTR:
2642 kvm_queue_interrupt(&svm->vcpu, vector, false);
2643 break;
2644 default:
2645 break;
2646 }
2647 }
2648
2649 #ifdef CONFIG_X86_64
2650 #define R "r"
2651 #else
2652 #define R "e"
2653 #endif
2654
2655 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2656 {
2657 struct vcpu_svm *svm = to_svm(vcpu);
2658 u16 fs_selector;
2659 u16 gs_selector;
2660 u16 ldt_selector;
2661
2662 /*
2663 * A vmexit emulation is required before the vcpu can be executed
2664 * again.
2665 */
2666 if (unlikely(svm->nested.exit_required))
2667 return;
2668
2669 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2670 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2671 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2672
2673 pre_svm_run(svm);
2674
2675 sync_lapic_to_cr8(vcpu);
2676
2677 save_host_msrs(vcpu);
2678 fs_selector = kvm_read_fs();
2679 gs_selector = kvm_read_gs();
2680 ldt_selector = kvm_read_ldt();
2681 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2682 /* required for live migration with NPT */
2683 if (npt_enabled)
2684 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2685
2686 clgi();
2687
2688 local_irq_enable();
2689
2690 asm volatile (
2691 "push %%"R"bp; \n\t"
2692 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2693 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2694 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2695 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2696 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2697 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2698 #ifdef CONFIG_X86_64
2699 "mov %c[r8](%[svm]), %%r8 \n\t"
2700 "mov %c[r9](%[svm]), %%r9 \n\t"
2701 "mov %c[r10](%[svm]), %%r10 \n\t"
2702 "mov %c[r11](%[svm]), %%r11 \n\t"
2703 "mov %c[r12](%[svm]), %%r12 \n\t"
2704 "mov %c[r13](%[svm]), %%r13 \n\t"
2705 "mov %c[r14](%[svm]), %%r14 \n\t"
2706 "mov %c[r15](%[svm]), %%r15 \n\t"
2707 #endif
2708
2709 /* Enter guest mode */
2710 "push %%"R"ax \n\t"
2711 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2712 __ex(SVM_VMLOAD) "\n\t"
2713 __ex(SVM_VMRUN) "\n\t"
2714 __ex(SVM_VMSAVE) "\n\t"
2715 "pop %%"R"ax \n\t"
2716
2717 /* Save guest registers, load host registers */
2718 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2719 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2720 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2721 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2722 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2723 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2724 #ifdef CONFIG_X86_64
2725 "mov %%r8, %c[r8](%[svm]) \n\t"
2726 "mov %%r9, %c[r9](%[svm]) \n\t"
2727 "mov %%r10, %c[r10](%[svm]) \n\t"
2728 "mov %%r11, %c[r11](%[svm]) \n\t"
2729 "mov %%r12, %c[r12](%[svm]) \n\t"
2730 "mov %%r13, %c[r13](%[svm]) \n\t"
2731 "mov %%r14, %c[r14](%[svm]) \n\t"
2732 "mov %%r15, %c[r15](%[svm]) \n\t"
2733 #endif
2734 "pop %%"R"bp"
2735 :
2736 : [svm]"a"(svm),
2737 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2738 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2739 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2740 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2741 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2742 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2743 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2744 #ifdef CONFIG_X86_64
2745 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2746 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2747 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2748 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2749 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2750 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2751 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2752 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2753 #endif
2754 : "cc", "memory"
2755 , R"bx", R"cx", R"dx", R"si", R"di"
2756 #ifdef CONFIG_X86_64
2757 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2758 #endif
2759 );
2760
2761 vcpu->arch.cr2 = svm->vmcb->save.cr2;
2762 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2763 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2764 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2765
2766 kvm_load_fs(fs_selector);
2767 kvm_load_gs(gs_selector);
2768 kvm_load_ldt(ldt_selector);
2769 load_host_msrs(vcpu);
2770
2771 reload_tss(vcpu);
2772
2773 local_irq_disable();
2774
2775 stgi();
2776
2777 sync_cr8_to_lapic(vcpu);
2778
2779 svm->next_rip = 0;
2780
2781 if (npt_enabled) {
2782 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
2783 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
2784 }
2785 }
2786
2787 #undef R
2788
2789 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2790 {
2791 struct vcpu_svm *svm = to_svm(vcpu);
2792
2793 if (npt_enabled) {
2794 svm->vmcb->control.nested_cr3 = root;
2795 force_new_asid(vcpu);
2796 return;
2797 }
2798
2799 svm->vmcb->save.cr3 = root;
2800 force_new_asid(vcpu);
2801
2802 if (vcpu->fpu_active) {
2803 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2804 svm->vmcb->save.cr0 |= X86_CR0_TS;
2805 vcpu->fpu_active = 0;
2806 }
2807 }
2808
2809 static int is_disabled(void)
2810 {
2811 u64 vm_cr;
2812
2813 rdmsrl(MSR_VM_CR, vm_cr);
2814 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2815 return 1;
2816
2817 return 0;
2818 }
2819
2820 static void
2821 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2822 {
2823 /*
2824 * Patch in the VMMCALL instruction:
2825 */
2826 hypercall[0] = 0x0f;
2827 hypercall[1] = 0x01;
2828 hypercall[2] = 0xd9;
2829 }
2830
2831 static void svm_check_processor_compat(void *rtn)
2832 {
2833 *(int *)rtn = 0;
2834 }
2835
2836 static bool svm_cpu_has_accelerated_tpr(void)
2837 {
2838 return false;
2839 }
2840
2841 static int get_npt_level(void)
2842 {
2843 #ifdef CONFIG_X86_64
2844 return PT64_ROOT_LEVEL;
2845 #else
2846 return PT32E_ROOT_LEVEL;
2847 #endif
2848 }
2849
2850 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2851 {
2852 return 0;
2853 }
2854
2855 static const struct trace_print_flags svm_exit_reasons_str[] = {
2856 { SVM_EXIT_READ_CR0, "read_cr0" },
2857 { SVM_EXIT_READ_CR3, "read_cr3" },
2858 { SVM_EXIT_READ_CR4, "read_cr4" },
2859 { SVM_EXIT_READ_CR8, "read_cr8" },
2860 { SVM_EXIT_WRITE_CR0, "write_cr0" },
2861 { SVM_EXIT_WRITE_CR3, "write_cr3" },
2862 { SVM_EXIT_WRITE_CR4, "write_cr4" },
2863 { SVM_EXIT_WRITE_CR8, "write_cr8" },
2864 { SVM_EXIT_READ_DR0, "read_dr0" },
2865 { SVM_EXIT_READ_DR1, "read_dr1" },
2866 { SVM_EXIT_READ_DR2, "read_dr2" },
2867 { SVM_EXIT_READ_DR3, "read_dr3" },
2868 { SVM_EXIT_WRITE_DR0, "write_dr0" },
2869 { SVM_EXIT_WRITE_DR1, "write_dr1" },
2870 { SVM_EXIT_WRITE_DR2, "write_dr2" },
2871 { SVM_EXIT_WRITE_DR3, "write_dr3" },
2872 { SVM_EXIT_WRITE_DR5, "write_dr5" },
2873 { SVM_EXIT_WRITE_DR7, "write_dr7" },
2874 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
2875 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
2876 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
2877 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
2878 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
2879 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
2880 { SVM_EXIT_INTR, "interrupt" },
2881 { SVM_EXIT_NMI, "nmi" },
2882 { SVM_EXIT_SMI, "smi" },
2883 { SVM_EXIT_INIT, "init" },
2884 { SVM_EXIT_VINTR, "vintr" },
2885 { SVM_EXIT_CPUID, "cpuid" },
2886 { SVM_EXIT_INVD, "invd" },
2887 { SVM_EXIT_HLT, "hlt" },
2888 { SVM_EXIT_INVLPG, "invlpg" },
2889 { SVM_EXIT_INVLPGA, "invlpga" },
2890 { SVM_EXIT_IOIO, "io" },
2891 { SVM_EXIT_MSR, "msr" },
2892 { SVM_EXIT_TASK_SWITCH, "task_switch" },
2893 { SVM_EXIT_SHUTDOWN, "shutdown" },
2894 { SVM_EXIT_VMRUN, "vmrun" },
2895 { SVM_EXIT_VMMCALL, "hypercall" },
2896 { SVM_EXIT_VMLOAD, "vmload" },
2897 { SVM_EXIT_VMSAVE, "vmsave" },
2898 { SVM_EXIT_STGI, "stgi" },
2899 { SVM_EXIT_CLGI, "clgi" },
2900 { SVM_EXIT_SKINIT, "skinit" },
2901 { SVM_EXIT_WBINVD, "wbinvd" },
2902 { SVM_EXIT_MONITOR, "monitor" },
2903 { SVM_EXIT_MWAIT, "mwait" },
2904 { SVM_EXIT_NPF, "npf" },
2905 { -1, NULL }
2906 };
2907
2908 static bool svm_gb_page_enable(void)
2909 {
2910 return true;
2911 }
2912
2913 static struct kvm_x86_ops svm_x86_ops = {
2914 .cpu_has_kvm_support = has_svm,
2915 .disabled_by_bios = is_disabled,
2916 .hardware_setup = svm_hardware_setup,
2917 .hardware_unsetup = svm_hardware_unsetup,
2918 .check_processor_compatibility = svm_check_processor_compat,
2919 .hardware_enable = svm_hardware_enable,
2920 .hardware_disable = svm_hardware_disable,
2921 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2922
2923 .vcpu_create = svm_create_vcpu,
2924 .vcpu_free = svm_free_vcpu,
2925 .vcpu_reset = svm_vcpu_reset,
2926
2927 .prepare_guest_switch = svm_prepare_guest_switch,
2928 .vcpu_load = svm_vcpu_load,
2929 .vcpu_put = svm_vcpu_put,
2930
2931 .set_guest_debug = svm_guest_debug,
2932 .get_msr = svm_get_msr,
2933 .set_msr = svm_set_msr,
2934 .get_segment_base = svm_get_segment_base,
2935 .get_segment = svm_get_segment,
2936 .set_segment = svm_set_segment,
2937 .get_cpl = svm_get_cpl,
2938 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2939 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2940 .set_cr0 = svm_set_cr0,
2941 .set_cr3 = svm_set_cr3,
2942 .set_cr4 = svm_set_cr4,
2943 .set_efer = svm_set_efer,
2944 .get_idt = svm_get_idt,
2945 .set_idt = svm_set_idt,
2946 .get_gdt = svm_get_gdt,
2947 .set_gdt = svm_set_gdt,
2948 .get_dr = svm_get_dr,
2949 .set_dr = svm_set_dr,
2950 .cache_reg = svm_cache_reg,
2951 .get_rflags = svm_get_rflags,
2952 .set_rflags = svm_set_rflags,
2953
2954 .tlb_flush = svm_flush_tlb,
2955
2956 .run = svm_vcpu_run,
2957 .handle_exit = handle_exit,
2958 .skip_emulated_instruction = skip_emulated_instruction,
2959 .set_interrupt_shadow = svm_set_interrupt_shadow,
2960 .get_interrupt_shadow = svm_get_interrupt_shadow,
2961 .patch_hypercall = svm_patch_hypercall,
2962 .set_irq = svm_set_irq,
2963 .set_nmi = svm_inject_nmi,
2964 .queue_exception = svm_queue_exception,
2965 .interrupt_allowed = svm_interrupt_allowed,
2966 .nmi_allowed = svm_nmi_allowed,
2967 .get_nmi_mask = svm_get_nmi_mask,
2968 .set_nmi_mask = svm_set_nmi_mask,
2969 .enable_nmi_window = enable_nmi_window,
2970 .enable_irq_window = enable_irq_window,
2971 .update_cr8_intercept = update_cr8_intercept,
2972
2973 .set_tss_addr = svm_set_tss_addr,
2974 .get_tdp_level = get_npt_level,
2975 .get_mt_mask = svm_get_mt_mask,
2976
2977 .exit_reasons_str = svm_exit_reasons_str,
2978 .gb_page_enable = svm_gb_page_enable,
2979 };
2980
2981 static int __init svm_init(void)
2982 {
2983 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2984 THIS_MODULE);
2985 }
2986
2987 static void __exit svm_exit(void)
2988 {
2989 kvm_exit();
2990 }
2991
2992 module_init(svm_init)
2993 module_exit(svm_exit)
Ubuntu Artful kernel mirror