2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affilates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
35 #include <asm/virtext.h>
38 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40 MODULE_AUTHOR("Qumranet");
41 MODULE_LICENSE("GPL");
43 #define IOPM_ALLOC_ORDER 2
44 #define MSRPM_ALLOC_ORDER 1
46 #define SEG_TYPE_LDT 2
47 #define SEG_TYPE_BUSY_TSS16 3
49 #define SVM_FEATURE_NPT (1 << 0)
50 #define SVM_FEATURE_LBRV (1 << 1)
51 #define SVM_FEATURE_SVML (1 << 2)
52 #define SVM_FEATURE_NRIP (1 << 3)
53 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
55 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
56 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
57 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
59 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
61 static bool erratum_383_found __read_mostly
;
63 static const u32 host_save_user_msrs
[] = {
65 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
68 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
71 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
81 /* These are the merged vectors */
84 /* gpa pointers to the real vectors */
88 /* A VMEXIT is required but not yet emulated */
91 /* cache for intercepts of the guest */
92 u16 intercept_cr_read
;
93 u16 intercept_cr_write
;
94 u16 intercept_dr_read
;
95 u16 intercept_dr_write
;
96 u32 intercept_exceptions
;
101 #define MSRPM_OFFSETS 16
102 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
105 struct kvm_vcpu vcpu
;
107 unsigned long vmcb_pa
;
108 struct svm_cpu_data
*svm_data
;
109 uint64_t asid_generation
;
110 uint64_t sysenter_esp
;
111 uint64_t sysenter_eip
;
115 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
120 struct nested_state nested
;
124 unsigned int3_injected
;
125 unsigned long int3_rip
;
128 #define MSR_INVALID 0xffffffffU
130 static struct svm_direct_access_msrs
{
131 u32 index
; /* Index of the MSR */
132 bool always
; /* True if intercept is always on */
133 } direct_access_msrs
[] = {
134 { .index
= MSR_STAR
, .always
= true },
135 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
137 { .index
= MSR_GS_BASE
, .always
= true },
138 { .index
= MSR_FS_BASE
, .always
= true },
139 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
140 { .index
= MSR_LSTAR
, .always
= true },
141 { .index
= MSR_CSTAR
, .always
= true },
142 { .index
= MSR_SYSCALL_MASK
, .always
= true },
144 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
145 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
146 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
147 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
148 { .index
= MSR_INVALID
, .always
= false },
151 /* enable NPT for AMD64 and X86 with PAE */
152 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
153 static bool npt_enabled
= true;
155 static bool npt_enabled
;
159 module_param(npt
, int, S_IRUGO
);
161 static int nested
= 1;
162 module_param(nested
, int, S_IRUGO
);
164 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
165 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
167 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
168 static int nested_svm_intercept(struct vcpu_svm
*svm
);
169 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
170 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
171 bool has_error_code
, u32 error_code
);
173 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
175 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
178 static inline bool is_nested(struct vcpu_svm
*svm
)
180 return svm
->nested
.vmcb
;
183 static inline void enable_gif(struct vcpu_svm
*svm
)
185 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
188 static inline void disable_gif(struct vcpu_svm
*svm
)
190 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
193 static inline bool gif_set(struct vcpu_svm
*svm
)
195 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
198 static unsigned long iopm_base
;
200 struct kvm_ldttss_desc
{
203 unsigned base1
:8, type
:5, dpl
:2, p
:1;
204 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
207 } __attribute__((packed
));
209 struct svm_cpu_data
{
215 struct kvm_ldttss_desc
*tss_desc
;
217 struct page
*save_area
;
220 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
221 static uint32_t svm_features
;
223 struct svm_init_data
{
228 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
230 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
231 #define MSRS_RANGE_SIZE 2048
232 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
234 static u32
svm_msrpm_offset(u32 msr
)
239 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
240 if (msr
< msrpm_ranges
[i
] ||
241 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
244 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
245 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
247 /* Now we have the u8 offset - but need the u32 offset */
251 /* MSR not in any range */
255 #define MAX_INST_SIZE 15
257 static inline u32
svm_has(u32 feat
)
259 return svm_features
& feat
;
262 static inline void clgi(void)
264 asm volatile (__ex(SVM_CLGI
));
267 static inline void stgi(void)
269 asm volatile (__ex(SVM_STGI
));
272 static inline void invlpga(unsigned long addr
, u32 asid
)
274 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
277 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
279 to_svm(vcpu
)->asid_generation
--;
282 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
284 force_new_asid(vcpu
);
287 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
289 vcpu
->arch
.efer
= efer
;
290 if (!npt_enabled
&& !(efer
& EFER_LMA
))
293 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
296 static int is_external_interrupt(u32 info
)
298 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
299 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
302 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
304 struct vcpu_svm
*svm
= to_svm(vcpu
);
307 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
308 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
312 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
314 struct vcpu_svm
*svm
= to_svm(vcpu
);
317 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
319 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
323 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
325 struct vcpu_svm
*svm
= to_svm(vcpu
);
327 if (svm
->vmcb
->control
.next_rip
!= 0)
328 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
330 if (!svm
->next_rip
) {
331 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
333 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
336 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
337 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
338 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
340 kvm_rip_write(vcpu
, svm
->next_rip
);
341 svm_set_interrupt_shadow(vcpu
, 0);
344 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
345 bool has_error_code
, u32 error_code
,
348 struct vcpu_svm
*svm
= to_svm(vcpu
);
351 * If we are within a nested VM we'd better #VMEXIT and let the guest
352 * handle the exception
355 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
358 if (nr
== BP_VECTOR
&& !svm_has(SVM_FEATURE_NRIP
)) {
359 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
362 * For guest debugging where we have to reinject #BP if some
363 * INT3 is guest-owned:
364 * Emulate nRIP by moving RIP forward. Will fail if injection
365 * raises a fault that is not intercepted. Still better than
366 * failing in all cases.
368 skip_emulated_instruction(&svm
->vcpu
);
369 rip
= kvm_rip_read(&svm
->vcpu
);
370 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
371 svm
->int3_injected
= rip
- old_rip
;
374 svm
->vmcb
->control
.event_inj
= nr
376 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
377 | SVM_EVTINJ_TYPE_EXEPT
;
378 svm
->vmcb
->control
.event_inj_err
= error_code
;
381 static void svm_init_erratum_383(void)
387 if (!cpu_has_amd_erratum(amd_erratum_383
))
390 /* Use _safe variants to not break nested virtualization */
391 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
397 low
= lower_32_bits(val
);
398 high
= upper_32_bits(val
);
400 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
402 erratum_383_found
= true;
405 static int has_svm(void)
409 if (!cpu_has_svm(&msg
)) {
410 printk(KERN_INFO
"has_svm: %s\n", msg
);
417 static void svm_hardware_disable(void *garbage
)
422 static int svm_hardware_enable(void *garbage
)
425 struct svm_cpu_data
*sd
;
427 struct desc_ptr gdt_descr
;
428 struct desc_struct
*gdt
;
429 int me
= raw_smp_processor_id();
431 rdmsrl(MSR_EFER
, efer
);
432 if (efer
& EFER_SVME
)
436 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
440 sd
= per_cpu(svm_data
, me
);
443 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
448 sd
->asid_generation
= 1;
449 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
450 sd
->next_asid
= sd
->max_asid
+ 1;
452 native_store_gdt(&gdt_descr
);
453 gdt
= (struct desc_struct
*)gdt_descr
.address
;
454 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
456 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
458 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
460 svm_init_erratum_383();
465 static void svm_cpu_uninit(int cpu
)
467 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
472 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
473 __free_page(sd
->save_area
);
477 static int svm_cpu_init(int cpu
)
479 struct svm_cpu_data
*sd
;
482 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
486 sd
->save_area
= alloc_page(GFP_KERNEL
);
491 per_cpu(svm_data
, cpu
) = sd
;
501 static bool valid_msr_intercept(u32 index
)
505 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
506 if (direct_access_msrs
[i
].index
== index
)
512 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
515 u8 bit_read
, bit_write
;
520 * If this warning triggers extend the direct_access_msrs list at the
521 * beginning of the file
523 WARN_ON(!valid_msr_intercept(msr
));
525 offset
= svm_msrpm_offset(msr
);
526 bit_read
= 2 * (msr
& 0x0f);
527 bit_write
= 2 * (msr
& 0x0f) + 1;
530 BUG_ON(offset
== MSR_INVALID
);
532 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
533 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
538 static void svm_vcpu_init_msrpm(u32
*msrpm
)
542 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
544 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
545 if (!direct_access_msrs
[i
].always
)
548 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
552 static void add_msr_offset(u32 offset
)
556 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
558 /* Offset already in list? */
559 if (msrpm_offsets
[i
] == offset
)
562 /* Slot used by another offset? */
563 if (msrpm_offsets
[i
] != MSR_INVALID
)
566 /* Add offset to list */
567 msrpm_offsets
[i
] = offset
;
573 * If this BUG triggers the msrpm_offsets table has an overflow. Just
574 * increase MSRPM_OFFSETS in this case.
579 static void init_msrpm_offsets(void)
583 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
585 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
588 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
589 BUG_ON(offset
== MSR_INVALID
);
591 add_msr_offset(offset
);
595 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
597 u32
*msrpm
= svm
->msrpm
;
599 svm
->vmcb
->control
.lbr_ctl
= 1;
600 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
601 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
602 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
603 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
606 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
608 u32
*msrpm
= svm
->msrpm
;
610 svm
->vmcb
->control
.lbr_ctl
= 0;
611 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
612 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
613 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
614 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
617 static __init
int svm_hardware_setup(void)
620 struct page
*iopm_pages
;
624 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
629 iopm_va
= page_address(iopm_pages
);
630 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
631 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
633 init_msrpm_offsets();
635 if (boot_cpu_has(X86_FEATURE_NX
))
636 kvm_enable_efer_bits(EFER_NX
);
638 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
639 kvm_enable_efer_bits(EFER_FFXSR
);
642 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
643 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
646 for_each_possible_cpu(cpu
) {
647 r
= svm_cpu_init(cpu
);
652 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
654 if (!svm_has(SVM_FEATURE_NPT
))
657 if (npt_enabled
&& !npt
) {
658 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
663 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
671 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
676 static __exit
void svm_hardware_unsetup(void)
680 for_each_possible_cpu(cpu
)
683 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
687 static void init_seg(struct vmcb_seg
*seg
)
690 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
691 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
696 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
699 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
704 static void init_vmcb(struct vcpu_svm
*svm
)
706 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
707 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
709 svm
->vcpu
.fpu_active
= 1;
711 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
715 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
720 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
729 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
738 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
743 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
744 (1ULL << INTERCEPT_NMI
) |
745 (1ULL << INTERCEPT_SMI
) |
746 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
747 (1ULL << INTERCEPT_CPUID
) |
748 (1ULL << INTERCEPT_INVD
) |
749 (1ULL << INTERCEPT_HLT
) |
750 (1ULL << INTERCEPT_INVLPG
) |
751 (1ULL << INTERCEPT_INVLPGA
) |
752 (1ULL << INTERCEPT_IOIO_PROT
) |
753 (1ULL << INTERCEPT_MSR_PROT
) |
754 (1ULL << INTERCEPT_TASK_SWITCH
) |
755 (1ULL << INTERCEPT_SHUTDOWN
) |
756 (1ULL << INTERCEPT_VMRUN
) |
757 (1ULL << INTERCEPT_VMMCALL
) |
758 (1ULL << INTERCEPT_VMLOAD
) |
759 (1ULL << INTERCEPT_VMSAVE
) |
760 (1ULL << INTERCEPT_STGI
) |
761 (1ULL << INTERCEPT_CLGI
) |
762 (1ULL << INTERCEPT_SKINIT
) |
763 (1ULL << INTERCEPT_WBINVD
) |
764 (1ULL << INTERCEPT_MONITOR
) |
765 (1ULL << INTERCEPT_MWAIT
);
767 control
->iopm_base_pa
= iopm_base
;
768 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
769 control
->int_ctl
= V_INTR_MASKING_MASK
;
777 save
->cs
.selector
= 0xf000;
778 /* Executable/Readable Code Segment */
779 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
780 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
781 save
->cs
.limit
= 0xffff;
783 * cs.base should really be 0xffff0000, but vmx can't handle that, so
784 * be consistent with it.
786 * Replace when we have real mode working for vmx.
788 save
->cs
.base
= 0xf0000;
790 save
->gdtr
.limit
= 0xffff;
791 save
->idtr
.limit
= 0xffff;
793 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
794 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
796 save
->efer
= EFER_SVME
;
797 save
->dr6
= 0xffff0ff0;
800 save
->rip
= 0x0000fff0;
801 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
804 * This is the guest-visible cr0 value.
805 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
807 svm
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
808 (void)kvm_set_cr0(&svm
->vcpu
, svm
->vcpu
.arch
.cr0
);
810 save
->cr4
= X86_CR4_PAE
;
814 /* Setup VMCB for Nested Paging */
815 control
->nested_ctl
= 1;
816 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
817 (1ULL << INTERCEPT_INVLPG
));
818 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
819 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
820 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
821 save
->g_pat
= 0x0007040600070406ULL
;
825 force_new_asid(&svm
->vcpu
);
827 svm
->nested
.vmcb
= 0;
828 svm
->vcpu
.arch
.hflags
= 0;
830 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
831 control
->pause_filter_count
= 3000;
832 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
838 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
840 struct vcpu_svm
*svm
= to_svm(vcpu
);
844 if (!kvm_vcpu_is_bsp(vcpu
)) {
845 kvm_rip_write(vcpu
, 0);
846 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
847 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
849 vcpu
->arch
.regs_avail
= ~0;
850 vcpu
->arch
.regs_dirty
= ~0;
855 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
857 struct vcpu_svm
*svm
;
859 struct page
*msrpm_pages
;
860 struct page
*hsave_page
;
861 struct page
*nested_msrpm_pages
;
864 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
870 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
875 page
= alloc_page(GFP_KERNEL
);
879 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
883 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
884 if (!nested_msrpm_pages
)
887 hsave_page
= alloc_page(GFP_KERNEL
);
891 svm
->nested
.hsave
= page_address(hsave_page
);
893 svm
->msrpm
= page_address(msrpm_pages
);
894 svm_vcpu_init_msrpm(svm
->msrpm
);
896 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
897 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
899 svm
->vmcb
= page_address(page
);
900 clear_page(svm
->vmcb
);
901 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
902 svm
->asid_generation
= 0;
904 svm
->vmcb
->control
.tsc_offset
= 0-native_read_tsc();
906 err
= fx_init(&svm
->vcpu
);
910 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
911 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
912 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
917 __free_page(hsave_page
);
919 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
921 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
925 kvm_vcpu_uninit(&svm
->vcpu
);
927 kmem_cache_free(kvm_vcpu_cache
, svm
);
932 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
934 struct vcpu_svm
*svm
= to_svm(vcpu
);
936 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
937 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
938 __free_page(virt_to_page(svm
->nested
.hsave
));
939 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
940 kvm_vcpu_uninit(vcpu
);
941 kmem_cache_free(kvm_vcpu_cache
, svm
);
944 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
946 struct vcpu_svm
*svm
= to_svm(vcpu
);
949 if (unlikely(cpu
!= vcpu
->cpu
)) {
952 if (check_tsc_unstable()) {
954 * Make sure that the guest sees a monotonically
957 delta
= vcpu
->arch
.host_tsc
- native_read_tsc();
958 svm
->vmcb
->control
.tsc_offset
+= delta
;
960 svm
->nested
.hsave
->control
.tsc_offset
+= delta
;
963 kvm_migrate_timers(vcpu
);
964 svm
->asid_generation
= 0;
967 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
968 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
971 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
973 struct vcpu_svm
*svm
= to_svm(vcpu
);
976 ++vcpu
->stat
.host_state_reload
;
977 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
978 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
980 vcpu
->arch
.host_tsc
= native_read_tsc();
983 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
985 return to_svm(vcpu
)->vmcb
->save
.rflags
;
988 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
990 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
993 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
996 case VCPU_EXREG_PDPTR
:
997 BUG_ON(!npt_enabled
);
998 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
1005 static void svm_set_vintr(struct vcpu_svm
*svm
)
1007 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
1010 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1012 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
1015 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1017 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1020 case VCPU_SREG_CS
: return &save
->cs
;
1021 case VCPU_SREG_DS
: return &save
->ds
;
1022 case VCPU_SREG_ES
: return &save
->es
;
1023 case VCPU_SREG_FS
: return &save
->fs
;
1024 case VCPU_SREG_GS
: return &save
->gs
;
1025 case VCPU_SREG_SS
: return &save
->ss
;
1026 case VCPU_SREG_TR
: return &save
->tr
;
1027 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1033 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1035 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1040 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1041 struct kvm_segment
*var
, int seg
)
1043 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1045 var
->base
= s
->base
;
1046 var
->limit
= s
->limit
;
1047 var
->selector
= s
->selector
;
1048 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1049 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1050 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1051 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1052 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1053 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1054 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1055 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1058 * AMD's VMCB does not have an explicit unusable field, so emulate it
1059 * for cross vendor migration purposes by "not present"
1061 var
->unusable
= !var
->present
|| (var
->type
== 0);
1066 * SVM always stores 0 for the 'G' bit in the CS selector in
1067 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1068 * Intel's VMENTRY has a check on the 'G' bit.
1070 var
->g
= s
->limit
> 0xfffff;
1074 * Work around a bug where the busy flag in the tr selector
1084 * The accessed bit must always be set in the segment
1085 * descriptor cache, although it can be cleared in the
1086 * descriptor, the cached bit always remains at 1. Since
1087 * Intel has a check on this, set it here to support
1088 * cross-vendor migration.
1095 * On AMD CPUs sometimes the DB bit in the segment
1096 * descriptor is left as 1, although the whole segment has
1097 * been made unusable. Clear it here to pass an Intel VMX
1098 * entry check when cross vendor migrating.
1106 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1108 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1113 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1115 struct vcpu_svm
*svm
= to_svm(vcpu
);
1117 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1118 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1121 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1123 struct vcpu_svm
*svm
= to_svm(vcpu
);
1125 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1126 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1129 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1131 struct vcpu_svm
*svm
= to_svm(vcpu
);
1133 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1134 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1137 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1139 struct vcpu_svm
*svm
= to_svm(vcpu
);
1141 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1142 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1145 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1149 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1153 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1155 struct vmcb
*vmcb
= svm
->vmcb
;
1156 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1157 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1159 if (!svm
->vcpu
.fpu_active
)
1160 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1162 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1163 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1166 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1167 vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1168 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1169 if (is_nested(svm
)) {
1170 struct vmcb
*hsave
= svm
->nested
.hsave
;
1172 hsave
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1173 hsave
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1174 vmcb
->control
.intercept_cr_read
|= svm
->nested
.intercept_cr_read
;
1175 vmcb
->control
.intercept_cr_write
|= svm
->nested
.intercept_cr_write
;
1178 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1179 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1180 if (is_nested(svm
)) {
1181 struct vmcb
*hsave
= svm
->nested
.hsave
;
1183 hsave
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1184 hsave
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1189 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1191 struct vcpu_svm
*svm
= to_svm(vcpu
);
1193 if (is_nested(svm
)) {
1195 * We are here because we run in nested mode, the host kvm
1196 * intercepts cr0 writes but the l1 hypervisor does not.
1197 * But the L1 hypervisor may intercept selective cr0 writes.
1198 * This needs to be checked here.
1200 unsigned long old
, new;
1202 /* Remove bits that would trigger a real cr0 write intercept */
1203 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1204 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1207 /* cr0 write with ts and mp unchanged */
1208 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1209 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
)
1214 #ifdef CONFIG_X86_64
1215 if (vcpu
->arch
.efer
& EFER_LME
) {
1216 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1217 vcpu
->arch
.efer
|= EFER_LMA
;
1218 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1221 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1222 vcpu
->arch
.efer
&= ~EFER_LMA
;
1223 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1227 vcpu
->arch
.cr0
= cr0
;
1230 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1232 if (!vcpu
->fpu_active
)
1235 * re-enable caching here because the QEMU bios
1236 * does not do it - this results in some delay at
1239 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1240 svm
->vmcb
->save
.cr0
= cr0
;
1241 update_cr0_intercept(svm
);
1244 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1246 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1247 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1249 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1250 force_new_asid(vcpu
);
1252 vcpu
->arch
.cr4
= cr4
;
1255 cr4
|= host_cr4_mce
;
1256 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1259 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1260 struct kvm_segment
*var
, int seg
)
1262 struct vcpu_svm
*svm
= to_svm(vcpu
);
1263 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1265 s
->base
= var
->base
;
1266 s
->limit
= var
->limit
;
1267 s
->selector
= var
->selector
;
1271 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1272 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1273 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1274 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1275 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1276 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1277 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1278 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1280 if (seg
== VCPU_SREG_CS
)
1282 = (svm
->vmcb
->save
.cs
.attrib
1283 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1287 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1289 struct vcpu_svm
*svm
= to_svm(vcpu
);
1291 svm
->vmcb
->control
.intercept_exceptions
&=
1292 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1294 if (svm
->nmi_singlestep
)
1295 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1297 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1298 if (vcpu
->guest_debug
&
1299 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1300 svm
->vmcb
->control
.intercept_exceptions
|=
1302 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1303 svm
->vmcb
->control
.intercept_exceptions
|=
1306 vcpu
->guest_debug
= 0;
1309 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1311 struct vcpu_svm
*svm
= to_svm(vcpu
);
1313 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1314 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1316 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1318 update_db_intercept(vcpu
);
1321 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1323 #ifdef CONFIG_X86_64
1324 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1328 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1330 #ifdef CONFIG_X86_64
1331 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1335 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1337 if (sd
->next_asid
> sd
->max_asid
) {
1338 ++sd
->asid_generation
;
1340 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1343 svm
->asid_generation
= sd
->asid_generation
;
1344 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1347 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1349 struct vcpu_svm
*svm
= to_svm(vcpu
);
1351 svm
->vmcb
->save
.dr7
= value
;
1354 static int pf_interception(struct vcpu_svm
*svm
)
1359 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1360 error_code
= svm
->vmcb
->control
.exit_info_1
;
1362 trace_kvm_page_fault(fault_address
, error_code
);
1363 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1364 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1365 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1368 static int db_interception(struct vcpu_svm
*svm
)
1370 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1372 if (!(svm
->vcpu
.guest_debug
&
1373 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1374 !svm
->nmi_singlestep
) {
1375 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1379 if (svm
->nmi_singlestep
) {
1380 svm
->nmi_singlestep
= false;
1381 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1382 svm
->vmcb
->save
.rflags
&=
1383 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1384 update_db_intercept(&svm
->vcpu
);
1387 if (svm
->vcpu
.guest_debug
&
1388 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1389 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1390 kvm_run
->debug
.arch
.pc
=
1391 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1392 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1399 static int bp_interception(struct vcpu_svm
*svm
)
1401 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1403 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1404 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1405 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1409 static int ud_interception(struct vcpu_svm
*svm
)
1413 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1414 if (er
!= EMULATE_DONE
)
1415 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1419 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1421 struct vcpu_svm
*svm
= to_svm(vcpu
);
1424 if (is_nested(svm
)) {
1427 h_excp
= svm
->nested
.hsave
->control
.intercept_exceptions
;
1428 n_excp
= svm
->nested
.intercept_exceptions
;
1429 h_excp
&= ~(1 << NM_VECTOR
);
1430 excp
= h_excp
| n_excp
;
1432 excp
= svm
->vmcb
->control
.intercept_exceptions
;
1433 excp
&= ~(1 << NM_VECTOR
);
1436 svm
->vmcb
->control
.intercept_exceptions
= excp
;
1438 svm
->vcpu
.fpu_active
= 1;
1439 update_cr0_intercept(svm
);
1442 static int nm_interception(struct vcpu_svm
*svm
)
1444 svm_fpu_activate(&svm
->vcpu
);
1448 static bool is_erratum_383(void)
1453 if (!erratum_383_found
)
1456 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1460 /* Bit 62 may or may not be set for this mce */
1461 value
&= ~(1ULL << 62);
1463 if (value
!= 0xb600000000010015ULL
)
1466 /* Clear MCi_STATUS registers */
1467 for (i
= 0; i
< 6; ++i
)
1468 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1470 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1474 value
&= ~(1ULL << 2);
1475 low
= lower_32_bits(value
);
1476 high
= upper_32_bits(value
);
1478 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1481 /* Flush tlb to evict multi-match entries */
1487 static void svm_handle_mce(struct vcpu_svm
*svm
)
1489 if (is_erratum_383()) {
1491 * Erratum 383 triggered. Guest state is corrupt so kill the
1494 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1496 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1502 * On an #MC intercept the MCE handler is not called automatically in
1503 * the host. So do it by hand here.
1507 /* not sure if we ever come back to this point */
1512 static int mc_interception(struct vcpu_svm
*svm
)
1517 static int shutdown_interception(struct vcpu_svm
*svm
)
1519 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1522 * VMCB is undefined after a SHUTDOWN intercept
1523 * so reinitialize it.
1525 clear_page(svm
->vmcb
);
1528 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1532 static int io_interception(struct vcpu_svm
*svm
)
1534 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1535 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1536 int size
, in
, string
;
1539 ++svm
->vcpu
.stat
.io_exits
;
1540 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1541 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1543 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1545 port
= io_info
>> 16;
1546 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1547 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1548 skip_emulated_instruction(&svm
->vcpu
);
1550 return kvm_fast_pio_out(vcpu
, size
, port
);
1553 static int nmi_interception(struct vcpu_svm
*svm
)
1558 static int intr_interception(struct vcpu_svm
*svm
)
1560 ++svm
->vcpu
.stat
.irq_exits
;
1564 static int nop_on_interception(struct vcpu_svm
*svm
)
1569 static int halt_interception(struct vcpu_svm
*svm
)
1571 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1572 skip_emulated_instruction(&svm
->vcpu
);
1573 return kvm_emulate_halt(&svm
->vcpu
);
1576 static int vmmcall_interception(struct vcpu_svm
*svm
)
1578 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1579 skip_emulated_instruction(&svm
->vcpu
);
1580 kvm_emulate_hypercall(&svm
->vcpu
);
1584 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1586 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1587 || !is_paging(&svm
->vcpu
)) {
1588 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1592 if (svm
->vmcb
->save
.cpl
) {
1593 kvm_inject_gp(&svm
->vcpu
, 0);
1600 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1601 bool has_error_code
, u32 error_code
)
1605 if (!is_nested(svm
))
1608 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1609 svm
->vmcb
->control
.exit_code_hi
= 0;
1610 svm
->vmcb
->control
.exit_info_1
= error_code
;
1611 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1613 vmexit
= nested_svm_intercept(svm
);
1614 if (vmexit
== NESTED_EXIT_DONE
)
1615 svm
->nested
.exit_required
= true;
1620 /* This function returns true if it is save to enable the irq window */
1621 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1623 if (!is_nested(svm
))
1626 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1629 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1632 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1633 svm
->vmcb
->control
.exit_info_1
= 0;
1634 svm
->vmcb
->control
.exit_info_2
= 0;
1636 if (svm
->nested
.intercept
& 1ULL) {
1638 * The #vmexit can't be emulated here directly because this
1639 * code path runs with irqs and preemtion disabled. A
1640 * #vmexit emulation might sleep. Only signal request for
1643 svm
->nested
.exit_required
= true;
1644 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1651 /* This function returns true if it is save to enable the nmi window */
1652 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1654 if (!is_nested(svm
))
1657 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1660 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1661 svm
->nested
.exit_required
= true;
1666 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1672 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1673 if (is_error_page(page
))
1681 kvm_release_page_clean(page
);
1682 kvm_inject_gp(&svm
->vcpu
, 0);
1687 static void nested_svm_unmap(struct page
*page
)
1690 kvm_release_page_dirty(page
);
1693 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1699 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1700 return NESTED_EXIT_HOST
;
1702 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1703 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1707 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1710 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1713 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1715 u32 offset
, msr
, value
;
1718 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1719 return NESTED_EXIT_HOST
;
1721 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1722 offset
= svm_msrpm_offset(msr
);
1723 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1724 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1726 if (offset
== MSR_INVALID
)
1727 return NESTED_EXIT_DONE
;
1729 /* Offset is in 32 bit units but need in 8 bit units */
1732 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1733 return NESTED_EXIT_DONE
;
1735 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1738 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1740 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1742 switch (exit_code
) {
1745 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1746 return NESTED_EXIT_HOST
;
1748 /* For now we are always handling NPFs when using them */
1750 return NESTED_EXIT_HOST
;
1752 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1753 /* When we're shadowing, trap PFs */
1755 return NESTED_EXIT_HOST
;
1757 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1758 nm_interception(svm
);
1764 return NESTED_EXIT_CONTINUE
;
1768 * If this function returns true, this #vmexit was already handled
1770 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1772 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1773 int vmexit
= NESTED_EXIT_HOST
;
1775 switch (exit_code
) {
1777 vmexit
= nested_svm_exit_handled_msr(svm
);
1780 vmexit
= nested_svm_intercept_ioio(svm
);
1782 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1783 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1784 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1785 vmexit
= NESTED_EXIT_DONE
;
1788 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1789 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1790 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1791 vmexit
= NESTED_EXIT_DONE
;
1794 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1795 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1796 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1797 vmexit
= NESTED_EXIT_DONE
;
1800 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1801 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1802 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1803 vmexit
= NESTED_EXIT_DONE
;
1806 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1807 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1808 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1809 vmexit
= NESTED_EXIT_DONE
;
1812 case SVM_EXIT_ERR
: {
1813 vmexit
= NESTED_EXIT_DONE
;
1817 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1818 if (svm
->nested
.intercept
& exit_bits
)
1819 vmexit
= NESTED_EXIT_DONE
;
1826 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1830 vmexit
= nested_svm_intercept(svm
);
1832 if (vmexit
== NESTED_EXIT_DONE
)
1833 nested_svm_vmexit(svm
);
1838 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1840 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1841 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1843 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1844 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1845 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1846 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1847 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1848 dst
->intercept
= from
->intercept
;
1849 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1850 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1851 dst
->tsc_offset
= from
->tsc_offset
;
1852 dst
->asid
= from
->asid
;
1853 dst
->tlb_ctl
= from
->tlb_ctl
;
1854 dst
->int_ctl
= from
->int_ctl
;
1855 dst
->int_vector
= from
->int_vector
;
1856 dst
->int_state
= from
->int_state
;
1857 dst
->exit_code
= from
->exit_code
;
1858 dst
->exit_code_hi
= from
->exit_code_hi
;
1859 dst
->exit_info_1
= from
->exit_info_1
;
1860 dst
->exit_info_2
= from
->exit_info_2
;
1861 dst
->exit_int_info
= from
->exit_int_info
;
1862 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1863 dst
->nested_ctl
= from
->nested_ctl
;
1864 dst
->event_inj
= from
->event_inj
;
1865 dst
->event_inj_err
= from
->event_inj_err
;
1866 dst
->nested_cr3
= from
->nested_cr3
;
1867 dst
->lbr_ctl
= from
->lbr_ctl
;
1870 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1872 struct vmcb
*nested_vmcb
;
1873 struct vmcb
*hsave
= svm
->nested
.hsave
;
1874 struct vmcb
*vmcb
= svm
->vmcb
;
1877 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1878 vmcb
->control
.exit_info_1
,
1879 vmcb
->control
.exit_info_2
,
1880 vmcb
->control
.exit_int_info
,
1881 vmcb
->control
.exit_int_info_err
);
1883 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1887 /* Exit nested SVM mode */
1888 svm
->nested
.vmcb
= 0;
1890 /* Give the current vmcb to the guest */
1893 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1894 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1895 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1896 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1897 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1898 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1899 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1900 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1901 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1902 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1903 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1904 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1905 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1906 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1907 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1908 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1909 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1911 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1912 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
1913 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
1914 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
1915 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
1916 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
1917 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
1918 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
1919 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
1922 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1923 * to make sure that we do not lose injected events. So check event_inj
1924 * here and copy it to exit_int_info if it is valid.
1925 * Exit_int_info and event_inj can't be both valid because the case
1926 * below only happens on a VMRUN instruction intercept which has
1927 * no valid exit_int_info set.
1929 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
1930 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
1932 nc
->exit_int_info
= vmcb
->control
.event_inj
;
1933 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
1936 nested_vmcb
->control
.tlb_ctl
= 0;
1937 nested_vmcb
->control
.event_inj
= 0;
1938 nested_vmcb
->control
.event_inj_err
= 0;
1940 /* We always set V_INTR_MASKING and remember the old value in hflags */
1941 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1942 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1944 /* Restore the original control entries */
1945 copy_vmcb_control_area(vmcb
, hsave
);
1947 kvm_clear_exception_queue(&svm
->vcpu
);
1948 kvm_clear_interrupt_queue(&svm
->vcpu
);
1950 /* Restore selected save entries */
1951 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1952 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1953 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1954 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1955 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1956 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1957 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1958 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1959 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1960 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1962 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1963 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1965 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1967 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1968 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1969 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1970 svm
->vmcb
->save
.dr7
= 0;
1971 svm
->vmcb
->save
.cpl
= 0;
1972 svm
->vmcb
->control
.exit_int_info
= 0;
1974 nested_svm_unmap(page
);
1976 kvm_mmu_reset_context(&svm
->vcpu
);
1977 kvm_mmu_load(&svm
->vcpu
);
1982 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
1985 * This function merges the msr permission bitmaps of kvm and the
1986 * nested vmcb. It is omptimized in that it only merges the parts where
1987 * the kvm msr permission bitmap may contain zero bits
1991 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1994 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
1998 if (msrpm_offsets
[i
] == 0xffffffff)
2001 p
= msrpm_offsets
[i
];
2002 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2004 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2007 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2010 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2015 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2017 struct vmcb
*nested_vmcb
;
2018 struct vmcb
*hsave
= svm
->nested
.hsave
;
2019 struct vmcb
*vmcb
= svm
->vmcb
;
2023 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2025 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2029 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
- 3, vmcb_gpa
,
2030 nested_vmcb
->save
.rip
,
2031 nested_vmcb
->control
.int_ctl
,
2032 nested_vmcb
->control
.event_inj
,
2033 nested_vmcb
->control
.nested_ctl
);
2035 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr_read
,
2036 nested_vmcb
->control
.intercept_cr_write
,
2037 nested_vmcb
->control
.intercept_exceptions
,
2038 nested_vmcb
->control
.intercept
);
2040 /* Clear internal status */
2041 kvm_clear_exception_queue(&svm
->vcpu
);
2042 kvm_clear_interrupt_queue(&svm
->vcpu
);
2045 * Save the old vmcb, so we don't need to pick what we save, but can
2046 * restore everything when a VMEXIT occurs
2048 hsave
->save
.es
= vmcb
->save
.es
;
2049 hsave
->save
.cs
= vmcb
->save
.cs
;
2050 hsave
->save
.ss
= vmcb
->save
.ss
;
2051 hsave
->save
.ds
= vmcb
->save
.ds
;
2052 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2053 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2054 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2055 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2056 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2057 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2058 hsave
->save
.rip
= svm
->next_rip
;
2059 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2060 hsave
->save
.rax
= vmcb
->save
.rax
;
2062 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2064 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2066 copy_vmcb_control_area(hsave
, vmcb
);
2068 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2069 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2071 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2073 /* Load the nested guest state */
2074 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2075 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2076 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2077 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2078 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2079 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2080 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2081 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2082 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2083 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2085 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2086 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2088 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2090 /* Guest paging mode is active - reset mmu */
2091 kvm_mmu_reset_context(&svm
->vcpu
);
2093 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2094 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2095 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2096 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2098 /* In case we don't even reach vcpu_run, the fields are not updated */
2099 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2100 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2101 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2102 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2103 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2104 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2106 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2107 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2109 /* cache intercepts */
2110 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
2111 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
2112 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
2113 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
2114 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2115 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2117 force_new_asid(&svm
->vcpu
);
2118 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2119 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2120 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2122 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2124 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2125 /* We only want the cr8 intercept bits of the guest */
2126 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
2127 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2130 /* We don't want to see VMMCALLs from a nested guest */
2131 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VMMCALL
);
2134 * We don't want a nested guest to be more powerful than the guest, so
2135 * all intercepts are ORed
2137 svm
->vmcb
->control
.intercept_cr_read
|=
2138 nested_vmcb
->control
.intercept_cr_read
;
2139 svm
->vmcb
->control
.intercept_cr_write
|=
2140 nested_vmcb
->control
.intercept_cr_write
;
2141 svm
->vmcb
->control
.intercept_dr_read
|=
2142 nested_vmcb
->control
.intercept_dr_read
;
2143 svm
->vmcb
->control
.intercept_dr_write
|=
2144 nested_vmcb
->control
.intercept_dr_write
;
2145 svm
->vmcb
->control
.intercept_exceptions
|=
2146 nested_vmcb
->control
.intercept_exceptions
;
2148 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
2150 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2151 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2152 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2153 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2154 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2155 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2157 nested_svm_unmap(page
);
2159 /* nested_vmcb is our indicator if nested SVM is activated */
2160 svm
->nested
.vmcb
= vmcb_gpa
;
2167 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2169 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2170 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2171 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2172 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2173 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2174 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2175 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2176 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2177 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2178 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2179 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2180 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2183 static int vmload_interception(struct vcpu_svm
*svm
)
2185 struct vmcb
*nested_vmcb
;
2188 if (nested_svm_check_permissions(svm
))
2191 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2192 skip_emulated_instruction(&svm
->vcpu
);
2194 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2198 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2199 nested_svm_unmap(page
);
2204 static int vmsave_interception(struct vcpu_svm
*svm
)
2206 struct vmcb
*nested_vmcb
;
2209 if (nested_svm_check_permissions(svm
))
2212 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2213 skip_emulated_instruction(&svm
->vcpu
);
2215 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2219 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2220 nested_svm_unmap(page
);
2225 static int vmrun_interception(struct vcpu_svm
*svm
)
2227 if (nested_svm_check_permissions(svm
))
2230 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2231 skip_emulated_instruction(&svm
->vcpu
);
2233 if (!nested_svm_vmrun(svm
))
2236 if (!nested_svm_vmrun_msrpm(svm
))
2243 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2244 svm
->vmcb
->control
.exit_code_hi
= 0;
2245 svm
->vmcb
->control
.exit_info_1
= 0;
2246 svm
->vmcb
->control
.exit_info_2
= 0;
2248 nested_svm_vmexit(svm
);
2253 static int stgi_interception(struct vcpu_svm
*svm
)
2255 if (nested_svm_check_permissions(svm
))
2258 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2259 skip_emulated_instruction(&svm
->vcpu
);
2266 static int clgi_interception(struct vcpu_svm
*svm
)
2268 if (nested_svm_check_permissions(svm
))
2271 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2272 skip_emulated_instruction(&svm
->vcpu
);
2276 /* After a CLGI no interrupts should come */
2277 svm_clear_vintr(svm
);
2278 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2283 static int invlpga_interception(struct vcpu_svm
*svm
)
2285 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2287 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2288 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2290 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2291 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2293 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2294 skip_emulated_instruction(&svm
->vcpu
);
2298 static int skinit_interception(struct vcpu_svm
*svm
)
2300 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2302 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2306 static int invalid_op_interception(struct vcpu_svm
*svm
)
2308 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2312 static int task_switch_interception(struct vcpu_svm
*svm
)
2316 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2317 SVM_EXITINTINFO_TYPE_MASK
;
2318 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2320 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2322 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2323 bool has_error_code
= false;
2326 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2328 if (svm
->vmcb
->control
.exit_info_2
&
2329 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2330 reason
= TASK_SWITCH_IRET
;
2331 else if (svm
->vmcb
->control
.exit_info_2
&
2332 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2333 reason
= TASK_SWITCH_JMP
;
2335 reason
= TASK_SWITCH_GATE
;
2337 reason
= TASK_SWITCH_CALL
;
2339 if (reason
== TASK_SWITCH_GATE
) {
2341 case SVM_EXITINTINFO_TYPE_NMI
:
2342 svm
->vcpu
.arch
.nmi_injected
= false;
2344 case SVM_EXITINTINFO_TYPE_EXEPT
:
2345 if (svm
->vmcb
->control
.exit_info_2
&
2346 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2347 has_error_code
= true;
2349 (u32
)svm
->vmcb
->control
.exit_info_2
;
2351 kvm_clear_exception_queue(&svm
->vcpu
);
2353 case SVM_EXITINTINFO_TYPE_INTR
:
2354 kvm_clear_interrupt_queue(&svm
->vcpu
);
2361 if (reason
!= TASK_SWITCH_GATE
||
2362 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2363 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2364 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2365 skip_emulated_instruction(&svm
->vcpu
);
2367 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2368 has_error_code
, error_code
) == EMULATE_FAIL
) {
2369 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2370 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2371 svm
->vcpu
.run
->internal
.ndata
= 0;
2377 static int cpuid_interception(struct vcpu_svm
*svm
)
2379 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2380 kvm_emulate_cpuid(&svm
->vcpu
);
2384 static int iret_interception(struct vcpu_svm
*svm
)
2386 ++svm
->vcpu
.stat
.nmi_window_exits
;
2387 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
2388 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2392 static int invlpg_interception(struct vcpu_svm
*svm
)
2394 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2397 static int emulate_on_interception(struct vcpu_svm
*svm
)
2399 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2402 static int cr8_write_interception(struct vcpu_svm
*svm
)
2404 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2406 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2407 /* instruction emulation calls kvm_set_cr8() */
2408 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2409 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2410 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2413 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2415 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2419 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2421 struct vcpu_svm
*svm
= to_svm(vcpu
);
2424 case MSR_IA32_TSC
: {
2428 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2430 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2432 *data
= tsc_offset
+ native_read_tsc();
2436 *data
= svm
->vmcb
->save
.star
;
2438 #ifdef CONFIG_X86_64
2440 *data
= svm
->vmcb
->save
.lstar
;
2443 *data
= svm
->vmcb
->save
.cstar
;
2445 case MSR_KERNEL_GS_BASE
:
2446 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2448 case MSR_SYSCALL_MASK
:
2449 *data
= svm
->vmcb
->save
.sfmask
;
2452 case MSR_IA32_SYSENTER_CS
:
2453 *data
= svm
->vmcb
->save
.sysenter_cs
;
2455 case MSR_IA32_SYSENTER_EIP
:
2456 *data
= svm
->sysenter_eip
;
2458 case MSR_IA32_SYSENTER_ESP
:
2459 *data
= svm
->sysenter_esp
;
2462 * Nobody will change the following 5 values in the VMCB so we can
2463 * safely return them on rdmsr. They will always be 0 until LBRV is
2466 case MSR_IA32_DEBUGCTLMSR
:
2467 *data
= svm
->vmcb
->save
.dbgctl
;
2469 case MSR_IA32_LASTBRANCHFROMIP
:
2470 *data
= svm
->vmcb
->save
.br_from
;
2472 case MSR_IA32_LASTBRANCHTOIP
:
2473 *data
= svm
->vmcb
->save
.br_to
;
2475 case MSR_IA32_LASTINTFROMIP
:
2476 *data
= svm
->vmcb
->save
.last_excp_from
;
2478 case MSR_IA32_LASTINTTOIP
:
2479 *data
= svm
->vmcb
->save
.last_excp_to
;
2481 case MSR_VM_HSAVE_PA
:
2482 *data
= svm
->nested
.hsave_msr
;
2485 *data
= svm
->nested
.vm_cr_msr
;
2487 case MSR_IA32_UCODE_REV
:
2491 return kvm_get_msr_common(vcpu
, ecx
, data
);
2496 static int rdmsr_interception(struct vcpu_svm
*svm
)
2498 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2501 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2502 trace_kvm_msr_read_ex(ecx
);
2503 kvm_inject_gp(&svm
->vcpu
, 0);
2505 trace_kvm_msr_read(ecx
, data
);
2507 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2508 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2509 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2510 skip_emulated_instruction(&svm
->vcpu
);
2515 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2517 struct vcpu_svm
*svm
= to_svm(vcpu
);
2518 int svm_dis
, chg_mask
;
2520 if (data
& ~SVM_VM_CR_VALID_MASK
)
2523 chg_mask
= SVM_VM_CR_VALID_MASK
;
2525 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2526 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2528 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2529 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2531 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2533 /* check for svm_disable while efer.svme is set */
2534 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2540 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2542 struct vcpu_svm
*svm
= to_svm(vcpu
);
2545 case MSR_IA32_TSC
: {
2546 u64 tsc_offset
= data
- native_read_tsc();
2547 u64 g_tsc_offset
= 0;
2549 if (is_nested(svm
)) {
2550 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
2551 svm
->nested
.hsave
->control
.tsc_offset
;
2552 svm
->nested
.hsave
->control
.tsc_offset
= tsc_offset
;
2555 svm
->vmcb
->control
.tsc_offset
= tsc_offset
+ g_tsc_offset
;
2560 svm
->vmcb
->save
.star
= data
;
2562 #ifdef CONFIG_X86_64
2564 svm
->vmcb
->save
.lstar
= data
;
2567 svm
->vmcb
->save
.cstar
= data
;
2569 case MSR_KERNEL_GS_BASE
:
2570 svm
->vmcb
->save
.kernel_gs_base
= data
;
2572 case MSR_SYSCALL_MASK
:
2573 svm
->vmcb
->save
.sfmask
= data
;
2576 case MSR_IA32_SYSENTER_CS
:
2577 svm
->vmcb
->save
.sysenter_cs
= data
;
2579 case MSR_IA32_SYSENTER_EIP
:
2580 svm
->sysenter_eip
= data
;
2581 svm
->vmcb
->save
.sysenter_eip
= data
;
2583 case MSR_IA32_SYSENTER_ESP
:
2584 svm
->sysenter_esp
= data
;
2585 svm
->vmcb
->save
.sysenter_esp
= data
;
2587 case MSR_IA32_DEBUGCTLMSR
:
2588 if (!svm_has(SVM_FEATURE_LBRV
)) {
2589 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2593 if (data
& DEBUGCTL_RESERVED_BITS
)
2596 svm
->vmcb
->save
.dbgctl
= data
;
2597 if (data
& (1ULL<<0))
2598 svm_enable_lbrv(svm
);
2600 svm_disable_lbrv(svm
);
2602 case MSR_VM_HSAVE_PA
:
2603 svm
->nested
.hsave_msr
= data
;
2606 return svm_set_vm_cr(vcpu
, data
);
2608 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2611 return kvm_set_msr_common(vcpu
, ecx
, data
);
2616 static int wrmsr_interception(struct vcpu_svm
*svm
)
2618 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2619 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2620 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2623 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2624 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2625 trace_kvm_msr_write_ex(ecx
, data
);
2626 kvm_inject_gp(&svm
->vcpu
, 0);
2628 trace_kvm_msr_write(ecx
, data
);
2629 skip_emulated_instruction(&svm
->vcpu
);
2634 static int msr_interception(struct vcpu_svm
*svm
)
2636 if (svm
->vmcb
->control
.exit_info_1
)
2637 return wrmsr_interception(svm
);
2639 return rdmsr_interception(svm
);
2642 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2644 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2646 svm_clear_vintr(svm
);
2647 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2649 * If the user space waits to inject interrupts, exit as soon as
2652 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2653 kvm_run
->request_interrupt_window
&&
2654 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2655 ++svm
->vcpu
.stat
.irq_window_exits
;
2656 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2663 static int pause_interception(struct vcpu_svm
*svm
)
2665 kvm_vcpu_on_spin(&(svm
->vcpu
));
2669 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2670 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2671 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2672 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2673 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2674 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2675 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2676 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2677 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2678 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2679 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2680 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2681 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2682 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2683 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2684 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2685 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2686 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2687 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2688 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2689 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2690 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2691 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2692 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2693 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2694 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2695 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2696 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2697 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2698 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2699 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2700 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2701 [SVM_EXIT_INTR
] = intr_interception
,
2702 [SVM_EXIT_NMI
] = nmi_interception
,
2703 [SVM_EXIT_SMI
] = nop_on_interception
,
2704 [SVM_EXIT_INIT
] = nop_on_interception
,
2705 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2706 [SVM_EXIT_CPUID
] = cpuid_interception
,
2707 [SVM_EXIT_IRET
] = iret_interception
,
2708 [SVM_EXIT_INVD
] = emulate_on_interception
,
2709 [SVM_EXIT_PAUSE
] = pause_interception
,
2710 [SVM_EXIT_HLT
] = halt_interception
,
2711 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2712 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2713 [SVM_EXIT_IOIO
] = io_interception
,
2714 [SVM_EXIT_MSR
] = msr_interception
,
2715 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2716 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2717 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2718 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2719 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2720 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2721 [SVM_EXIT_STGI
] = stgi_interception
,
2722 [SVM_EXIT_CLGI
] = clgi_interception
,
2723 [SVM_EXIT_SKINIT
] = skinit_interception
,
2724 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2725 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2726 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2727 [SVM_EXIT_NPF
] = pf_interception
,
2730 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2732 struct vcpu_svm
*svm
= to_svm(vcpu
);
2733 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2734 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2736 pr_err("VMCB Control Area:\n");
2737 pr_err("cr_read: %04x\n", control
->intercept_cr_read
);
2738 pr_err("cr_write: %04x\n", control
->intercept_cr_write
);
2739 pr_err("dr_read: %04x\n", control
->intercept_dr_read
);
2740 pr_err("dr_write: %04x\n", control
->intercept_dr_write
);
2741 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
2742 pr_err("intercepts: %016llx\n", control
->intercept
);
2743 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
2744 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
2745 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
2746 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
2747 pr_err("asid: %d\n", control
->asid
);
2748 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
2749 pr_err("int_ctl: %08x\n", control
->int_ctl
);
2750 pr_err("int_vector: %08x\n", control
->int_vector
);
2751 pr_err("int_state: %08x\n", control
->int_state
);
2752 pr_err("exit_code: %08x\n", control
->exit_code
);
2753 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
2754 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
2755 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
2756 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
2757 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
2758 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
2759 pr_err("event_inj: %08x\n", control
->event_inj
);
2760 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
2761 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
2762 pr_err("next_rip: %016llx\n", control
->next_rip
);
2763 pr_err("VMCB State Save Area:\n");
2764 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2765 save
->es
.selector
, save
->es
.attrib
,
2766 save
->es
.limit
, save
->es
.base
);
2767 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2768 save
->cs
.selector
, save
->cs
.attrib
,
2769 save
->cs
.limit
, save
->cs
.base
);
2770 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2771 save
->ss
.selector
, save
->ss
.attrib
,
2772 save
->ss
.limit
, save
->ss
.base
);
2773 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2774 save
->ds
.selector
, save
->ds
.attrib
,
2775 save
->ds
.limit
, save
->ds
.base
);
2776 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2777 save
->fs
.selector
, save
->fs
.attrib
,
2778 save
->fs
.limit
, save
->fs
.base
);
2779 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
2780 save
->gs
.selector
, save
->gs
.attrib
,
2781 save
->gs
.limit
, save
->gs
.base
);
2782 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
2783 save
->gdtr
.selector
, save
->gdtr
.attrib
,
2784 save
->gdtr
.limit
, save
->gdtr
.base
);
2785 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
2786 save
->ldtr
.selector
, save
->ldtr
.attrib
,
2787 save
->ldtr
.limit
, save
->ldtr
.base
);
2788 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
2789 save
->idtr
.selector
, save
->idtr
.attrib
,
2790 save
->idtr
.limit
, save
->idtr
.base
);
2791 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
2792 save
->tr
.selector
, save
->tr
.attrib
,
2793 save
->tr
.limit
, save
->tr
.base
);
2794 pr_err("cpl: %d efer: %016llx\n",
2795 save
->cpl
, save
->efer
);
2796 pr_err("cr0: %016llx cr2: %016llx\n",
2797 save
->cr0
, save
->cr2
);
2798 pr_err("cr3: %016llx cr4: %016llx\n",
2799 save
->cr3
, save
->cr4
);
2800 pr_err("dr6: %016llx dr7: %016llx\n",
2801 save
->dr6
, save
->dr7
);
2802 pr_err("rip: %016llx rflags: %016llx\n",
2803 save
->rip
, save
->rflags
);
2804 pr_err("rsp: %016llx rax: %016llx\n",
2805 save
->rsp
, save
->rax
);
2806 pr_err("star: %016llx lstar: %016llx\n",
2807 save
->star
, save
->lstar
);
2808 pr_err("cstar: %016llx sfmask: %016llx\n",
2809 save
->cstar
, save
->sfmask
);
2810 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
2811 save
->kernel_gs_base
, save
->sysenter_cs
);
2812 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
2813 save
->sysenter_esp
, save
->sysenter_eip
);
2814 pr_err("gpat: %016llx dbgctl: %016llx\n",
2815 save
->g_pat
, save
->dbgctl
);
2816 pr_err("br_from: %016llx br_to: %016llx\n",
2817 save
->br_from
, save
->br_to
);
2818 pr_err("excp_from: %016llx excp_to: %016llx\n",
2819 save
->last_excp_from
, save
->last_excp_to
);
2823 static int handle_exit(struct kvm_vcpu
*vcpu
)
2825 struct vcpu_svm
*svm
= to_svm(vcpu
);
2826 struct kvm_run
*kvm_run
= vcpu
->run
;
2827 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2829 trace_kvm_exit(exit_code
, vcpu
);
2831 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2832 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2834 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2836 if (unlikely(svm
->nested
.exit_required
)) {
2837 nested_svm_vmexit(svm
);
2838 svm
->nested
.exit_required
= false;
2843 if (is_nested(svm
)) {
2846 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2847 svm
->vmcb
->control
.exit_info_1
,
2848 svm
->vmcb
->control
.exit_info_2
,
2849 svm
->vmcb
->control
.exit_int_info
,
2850 svm
->vmcb
->control
.exit_int_info_err
);
2852 vmexit
= nested_svm_exit_special(svm
);
2854 if (vmexit
== NESTED_EXIT_CONTINUE
)
2855 vmexit
= nested_svm_exit_handled(svm
);
2857 if (vmexit
== NESTED_EXIT_DONE
)
2861 svm_complete_interrupts(svm
);
2863 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2864 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2865 kvm_run
->fail_entry
.hardware_entry_failure_reason
2866 = svm
->vmcb
->control
.exit_code
;
2867 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
2872 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2873 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2874 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2875 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2877 __func__
, svm
->vmcb
->control
.exit_int_info
,
2880 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2881 || !svm_exit_handlers
[exit_code
]) {
2882 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2883 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2887 return svm_exit_handlers
[exit_code
](svm
);
2890 static void reload_tss(struct kvm_vcpu
*vcpu
)
2892 int cpu
= raw_smp_processor_id();
2894 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2895 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2899 static void pre_svm_run(struct vcpu_svm
*svm
)
2901 int cpu
= raw_smp_processor_id();
2903 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2905 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2906 /* FIXME: handle wraparound of asid_generation */
2907 if (svm
->asid_generation
!= sd
->asid_generation
)
2911 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2913 struct vcpu_svm
*svm
= to_svm(vcpu
);
2915 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2916 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2917 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
2918 ++vcpu
->stat
.nmi_injections
;
2921 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2923 struct vmcb_control_area
*control
;
2925 control
= &svm
->vmcb
->control
;
2926 control
->int_vector
= irq
;
2927 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2928 control
->int_ctl
|= V_IRQ_MASK
|
2929 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2932 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2934 struct vcpu_svm
*svm
= to_svm(vcpu
);
2936 BUG_ON(!(gif_set(svm
)));
2938 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
2939 ++vcpu
->stat
.irq_injections
;
2941 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2942 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2945 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2947 struct vcpu_svm
*svm
= to_svm(vcpu
);
2949 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2956 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2959 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2961 struct vcpu_svm
*svm
= to_svm(vcpu
);
2962 struct vmcb
*vmcb
= svm
->vmcb
;
2964 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2965 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2966 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
2971 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2973 struct vcpu_svm
*svm
= to_svm(vcpu
);
2975 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2978 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2980 struct vcpu_svm
*svm
= to_svm(vcpu
);
2983 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
2984 svm
->vmcb
->control
.intercept
|= (1ULL << INTERCEPT_IRET
);
2986 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
2987 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_IRET
);
2991 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2993 struct vcpu_svm
*svm
= to_svm(vcpu
);
2994 struct vmcb
*vmcb
= svm
->vmcb
;
2997 if (!gif_set(svm
) ||
2998 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3001 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3004 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3009 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3011 struct vcpu_svm
*svm
= to_svm(vcpu
);
3014 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3015 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3016 * get that intercept, this function will be called again though and
3017 * we'll get the vintr intercept.
3019 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3021 svm_inject_irq(svm
, 0x0);
3025 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3027 struct vcpu_svm
*svm
= to_svm(vcpu
);
3029 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3031 return; /* IRET will cause a vm exit */
3034 * Something prevents NMI from been injected. Single step over possible
3035 * problem (IRET or exception injection or interrupt shadow)
3037 svm
->nmi_singlestep
= true;
3038 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3039 update_db_intercept(vcpu
);
3042 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3047 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3049 force_new_asid(vcpu
);
3052 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3056 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3058 struct vcpu_svm
*svm
= to_svm(vcpu
);
3060 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3063 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
3064 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3065 kvm_set_cr8(vcpu
, cr8
);
3069 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3071 struct vcpu_svm
*svm
= to_svm(vcpu
);
3074 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3077 cr8
= kvm_get_cr8(vcpu
);
3078 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3079 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3082 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3086 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3087 unsigned int3_injected
= svm
->int3_injected
;
3089 svm
->int3_injected
= 0;
3091 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
3092 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3094 svm
->vcpu
.arch
.nmi_injected
= false;
3095 kvm_clear_exception_queue(&svm
->vcpu
);
3096 kvm_clear_interrupt_queue(&svm
->vcpu
);
3098 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3101 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3102 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3105 case SVM_EXITINTINFO_TYPE_NMI
:
3106 svm
->vcpu
.arch
.nmi_injected
= true;
3108 case SVM_EXITINTINFO_TYPE_EXEPT
:
3110 * In case of software exceptions, do not reinject the vector,
3111 * but re-execute the instruction instead. Rewind RIP first
3112 * if we emulated INT3 before.
3114 if (kvm_exception_is_soft(vector
)) {
3115 if (vector
== BP_VECTOR
&& int3_injected
&&
3116 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3117 kvm_rip_write(&svm
->vcpu
,
3118 kvm_rip_read(&svm
->vcpu
) -
3122 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3123 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3124 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3127 kvm_requeue_exception(&svm
->vcpu
, vector
);
3129 case SVM_EXITINTINFO_TYPE_INTR
:
3130 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3137 #ifdef CONFIG_X86_64
3143 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3145 struct vcpu_svm
*svm
= to_svm(vcpu
);
3150 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3151 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3152 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3155 * A vmexit emulation is required before the vcpu can be executed
3158 if (unlikely(svm
->nested
.exit_required
))
3163 sync_lapic_to_cr8(vcpu
);
3165 save_host_msrs(vcpu
);
3166 savesegment(fs
, fs_selector
);
3167 savesegment(gs
, gs_selector
);
3168 ldt_selector
= kvm_read_ldt();
3169 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3170 /* required for live migration with NPT */
3172 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3179 "push %%"R
"bp; \n\t"
3180 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3181 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3182 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3183 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3184 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3185 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3186 #ifdef CONFIG_X86_64
3187 "mov %c[r8](%[svm]), %%r8 \n\t"
3188 "mov %c[r9](%[svm]), %%r9 \n\t"
3189 "mov %c[r10](%[svm]), %%r10 \n\t"
3190 "mov %c[r11](%[svm]), %%r11 \n\t"
3191 "mov %c[r12](%[svm]), %%r12 \n\t"
3192 "mov %c[r13](%[svm]), %%r13 \n\t"
3193 "mov %c[r14](%[svm]), %%r14 \n\t"
3194 "mov %c[r15](%[svm]), %%r15 \n\t"
3197 /* Enter guest mode */
3199 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3200 __ex(SVM_VMLOAD
) "\n\t"
3201 __ex(SVM_VMRUN
) "\n\t"
3202 __ex(SVM_VMSAVE
) "\n\t"
3205 /* Save guest registers, load host registers */
3206 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3207 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3208 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3209 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3210 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3211 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3212 #ifdef CONFIG_X86_64
3213 "mov %%r8, %c[r8](%[svm]) \n\t"
3214 "mov %%r9, %c[r9](%[svm]) \n\t"
3215 "mov %%r10, %c[r10](%[svm]) \n\t"
3216 "mov %%r11, %c[r11](%[svm]) \n\t"
3217 "mov %%r12, %c[r12](%[svm]) \n\t"
3218 "mov %%r13, %c[r13](%[svm]) \n\t"
3219 "mov %%r14, %c[r14](%[svm]) \n\t"
3220 "mov %%r15, %c[r15](%[svm]) \n\t"
3225 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3226 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3227 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3228 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3229 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3230 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3231 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3232 #ifdef CONFIG_X86_64
3233 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3234 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3235 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3236 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3237 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3238 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3239 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3240 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3243 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3244 #ifdef CONFIG_X86_64
3245 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3249 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3250 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3251 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3252 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3254 load_host_msrs(vcpu
);
3255 loadsegment(fs
, fs_selector
);
3256 #ifdef CONFIG_X86_64
3257 load_gs_index(gs_selector
);
3258 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
3260 loadsegment(gs
, gs_selector
);
3262 kvm_load_ldt(ldt_selector
);
3266 local_irq_disable();
3270 sync_cr8_to_lapic(vcpu
);
3275 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3276 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3280 * We need to handle MC intercepts here before the vcpu has a chance to
3281 * change the physical cpu
3283 if (unlikely(svm
->vmcb
->control
.exit_code
==
3284 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3285 svm_handle_mce(svm
);
3290 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3292 struct vcpu_svm
*svm
= to_svm(vcpu
);
3295 svm
->vmcb
->control
.nested_cr3
= root
;
3296 force_new_asid(vcpu
);
3300 svm
->vmcb
->save
.cr3
= root
;
3301 force_new_asid(vcpu
);
3304 static int is_disabled(void)
3308 rdmsrl(MSR_VM_CR
, vm_cr
);
3309 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3316 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3319 * Patch in the VMMCALL instruction:
3321 hypercall
[0] = 0x0f;
3322 hypercall
[1] = 0x01;
3323 hypercall
[2] = 0xd9;
3326 static void svm_check_processor_compat(void *rtn
)
3331 static bool svm_cpu_has_accelerated_tpr(void)
3336 static int get_npt_level(void)
3338 #ifdef CONFIG_X86_64
3339 return PT64_ROOT_LEVEL
;
3341 return PT32E_ROOT_LEVEL
;
3345 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3350 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3354 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3358 entry
->eax
= 1; /* SVM revision 1 */
3359 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3360 ASID emulation to nested SVM */
3361 entry
->ecx
= 0; /* Reserved */
3362 entry
->edx
= 0; /* Do not support any additional features */
3368 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3369 { SVM_EXIT_READ_CR0
, "read_cr0" },
3370 { SVM_EXIT_READ_CR3
, "read_cr3" },
3371 { SVM_EXIT_READ_CR4
, "read_cr4" },
3372 { SVM_EXIT_READ_CR8
, "read_cr8" },
3373 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3374 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3375 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3376 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3377 { SVM_EXIT_READ_DR0
, "read_dr0" },
3378 { SVM_EXIT_READ_DR1
, "read_dr1" },
3379 { SVM_EXIT_READ_DR2
, "read_dr2" },
3380 { SVM_EXIT_READ_DR3
, "read_dr3" },
3381 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3382 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3383 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3384 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3385 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3386 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3387 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3388 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3389 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3390 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3391 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3392 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3393 { SVM_EXIT_INTR
, "interrupt" },
3394 { SVM_EXIT_NMI
, "nmi" },
3395 { SVM_EXIT_SMI
, "smi" },
3396 { SVM_EXIT_INIT
, "init" },
3397 { SVM_EXIT_VINTR
, "vintr" },
3398 { SVM_EXIT_CPUID
, "cpuid" },
3399 { SVM_EXIT_INVD
, "invd" },
3400 { SVM_EXIT_HLT
, "hlt" },
3401 { SVM_EXIT_INVLPG
, "invlpg" },
3402 { SVM_EXIT_INVLPGA
, "invlpga" },
3403 { SVM_EXIT_IOIO
, "io" },
3404 { SVM_EXIT_MSR
, "msr" },
3405 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3406 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3407 { SVM_EXIT_VMRUN
, "vmrun" },
3408 { SVM_EXIT_VMMCALL
, "hypercall" },
3409 { SVM_EXIT_VMLOAD
, "vmload" },
3410 { SVM_EXIT_VMSAVE
, "vmsave" },
3411 { SVM_EXIT_STGI
, "stgi" },
3412 { SVM_EXIT_CLGI
, "clgi" },
3413 { SVM_EXIT_SKINIT
, "skinit" },
3414 { SVM_EXIT_WBINVD
, "wbinvd" },
3415 { SVM_EXIT_MONITOR
, "monitor" },
3416 { SVM_EXIT_MWAIT
, "mwait" },
3417 { SVM_EXIT_NPF
, "npf" },
3421 static int svm_get_lpage_level(void)
3423 return PT_PDPE_LEVEL
;
3426 static bool svm_rdtscp_supported(void)
3431 static bool svm_has_wbinvd_exit(void)
3436 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3438 struct vcpu_svm
*svm
= to_svm(vcpu
);
3440 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3442 svm
->nested
.hsave
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3443 update_cr0_intercept(svm
);
3446 static struct kvm_x86_ops svm_x86_ops
= {
3447 .cpu_has_kvm_support
= has_svm
,
3448 .disabled_by_bios
= is_disabled
,
3449 .hardware_setup
= svm_hardware_setup
,
3450 .hardware_unsetup
= svm_hardware_unsetup
,
3451 .check_processor_compatibility
= svm_check_processor_compat
,
3452 .hardware_enable
= svm_hardware_enable
,
3453 .hardware_disable
= svm_hardware_disable
,
3454 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3456 .vcpu_create
= svm_create_vcpu
,
3457 .vcpu_free
= svm_free_vcpu
,
3458 .vcpu_reset
= svm_vcpu_reset
,
3460 .prepare_guest_switch
= svm_prepare_guest_switch
,
3461 .vcpu_load
= svm_vcpu_load
,
3462 .vcpu_put
= svm_vcpu_put
,
3464 .set_guest_debug
= svm_guest_debug
,
3465 .get_msr
= svm_get_msr
,
3466 .set_msr
= svm_set_msr
,
3467 .get_segment_base
= svm_get_segment_base
,
3468 .get_segment
= svm_get_segment
,
3469 .set_segment
= svm_set_segment
,
3470 .get_cpl
= svm_get_cpl
,
3471 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3472 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3473 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3474 .set_cr0
= svm_set_cr0
,
3475 .set_cr3
= svm_set_cr3
,
3476 .set_cr4
= svm_set_cr4
,
3477 .set_efer
= svm_set_efer
,
3478 .get_idt
= svm_get_idt
,
3479 .set_idt
= svm_set_idt
,
3480 .get_gdt
= svm_get_gdt
,
3481 .set_gdt
= svm_set_gdt
,
3482 .set_dr7
= svm_set_dr7
,
3483 .cache_reg
= svm_cache_reg
,
3484 .get_rflags
= svm_get_rflags
,
3485 .set_rflags
= svm_set_rflags
,
3486 .fpu_activate
= svm_fpu_activate
,
3487 .fpu_deactivate
= svm_fpu_deactivate
,
3489 .tlb_flush
= svm_flush_tlb
,
3491 .run
= svm_vcpu_run
,
3492 .handle_exit
= handle_exit
,
3493 .skip_emulated_instruction
= skip_emulated_instruction
,
3494 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3495 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3496 .patch_hypercall
= svm_patch_hypercall
,
3497 .set_irq
= svm_set_irq
,
3498 .set_nmi
= svm_inject_nmi
,
3499 .queue_exception
= svm_queue_exception
,
3500 .interrupt_allowed
= svm_interrupt_allowed
,
3501 .nmi_allowed
= svm_nmi_allowed
,
3502 .get_nmi_mask
= svm_get_nmi_mask
,
3503 .set_nmi_mask
= svm_set_nmi_mask
,
3504 .enable_nmi_window
= enable_nmi_window
,
3505 .enable_irq_window
= enable_irq_window
,
3506 .update_cr8_intercept
= update_cr8_intercept
,
3508 .set_tss_addr
= svm_set_tss_addr
,
3509 .get_tdp_level
= get_npt_level
,
3510 .get_mt_mask
= svm_get_mt_mask
,
3512 .exit_reasons_str
= svm_exit_reasons_str
,
3513 .get_lpage_level
= svm_get_lpage_level
,
3515 .cpuid_update
= svm_cpuid_update
,
3517 .rdtscp_supported
= svm_rdtscp_supported
,
3519 .set_supported_cpuid
= svm_set_supported_cpuid
,
3521 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3524 static int __init
svm_init(void)
3526 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3527 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3530 static void __exit
svm_exit(void)
3535 module_init(svm_init
)
3536 module_exit(svm_exit
)