2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
16 #include <linux/kvm_host.h>
20 #include "kvm_cache_regs.h"
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/vmalloc.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
33 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 #define IOPM_ALLOC_ORDER 2
42 #define MSRPM_ALLOC_ORDER 1
44 #define SEG_TYPE_LDT 2
45 #define SEG_TYPE_BUSY_TSS16 3
47 #define SVM_FEATURE_NPT (1 << 0)
48 #define SVM_FEATURE_LBRV (1 << 1)
49 #define SVM_FEATURE_SVML (1 << 2)
50 #define SVM_FEATURE_NRIP (1 << 3)
51 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
53 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
54 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
55 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
59 static const u32 host_save_user_msrs
[] = {
61 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
64 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77 /* These are the merged vectors */
80 /* gpa pointers to the real vectors */
84 /* A VMEXIT is required but not yet emulated */
87 /* cache for intercepts of the guest */
88 u16 intercept_cr_read
;
89 u16 intercept_cr_write
;
90 u16 intercept_dr_read
;
91 u16 intercept_dr_write
;
92 u32 intercept_exceptions
;
97 #define MSRPM_OFFSETS 16
98 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
101 struct kvm_vcpu vcpu
;
103 unsigned long vmcb_pa
;
104 struct svm_cpu_data
*svm_data
;
105 uint64_t asid_generation
;
106 uint64_t sysenter_esp
;
107 uint64_t sysenter_eip
;
111 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
116 struct nested_state nested
;
120 unsigned int3_injected
;
121 unsigned long int3_rip
;
124 #define MSR_INVALID 0xffffffffU
126 static struct svm_direct_access_msrs
{
127 u32 index
; /* Index of the MSR */
128 bool always
; /* True if intercept is always on */
129 } direct_access_msrs
[] = {
130 { .index
= MSR_K6_STAR
, .always
= true },
131 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
133 { .index
= MSR_GS_BASE
, .always
= true },
134 { .index
= MSR_FS_BASE
, .always
= true },
135 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
136 { .index
= MSR_LSTAR
, .always
= true },
137 { .index
= MSR_CSTAR
, .always
= true },
138 { .index
= MSR_SYSCALL_MASK
, .always
= true },
140 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
141 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
142 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
143 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
144 { .index
= MSR_INVALID
, .always
= false },
147 /* enable NPT for AMD64 and X86 with PAE */
148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
149 static bool npt_enabled
= true;
151 static bool npt_enabled
;
155 module_param(npt
, int, S_IRUGO
);
157 static int nested
= 1;
158 module_param(nested
, int, S_IRUGO
);
160 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
161 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
163 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
164 static int nested_svm_intercept(struct vcpu_svm
*svm
);
165 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
166 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
167 bool has_error_code
, u32 error_code
);
169 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
171 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
174 static inline bool is_nested(struct vcpu_svm
*svm
)
176 return svm
->nested
.vmcb
;
179 static inline void enable_gif(struct vcpu_svm
*svm
)
181 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
184 static inline void disable_gif(struct vcpu_svm
*svm
)
186 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
189 static inline bool gif_set(struct vcpu_svm
*svm
)
191 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
194 static unsigned long iopm_base
;
196 struct kvm_ldttss_desc
{
199 unsigned base1
:8, type
:5, dpl
:2, p
:1;
200 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
203 } __attribute__((packed
));
205 struct svm_cpu_data
{
211 struct kvm_ldttss_desc
*tss_desc
;
213 struct page
*save_area
;
216 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
217 static uint32_t svm_features
;
219 struct svm_init_data
{
224 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
227 #define MSRS_RANGE_SIZE 2048
228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
230 static u32
svm_msrpm_offset(u32 msr
)
235 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
236 if (msr
< msrpm_ranges
[i
] ||
237 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
240 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
241 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
243 /* Now we have the u8 offset - but need the u32 offset */
247 /* MSR not in any range */
251 #define MAX_INST_SIZE 15
253 static inline u32
svm_has(u32 feat
)
255 return svm_features
& feat
;
258 static inline void clgi(void)
260 asm volatile (__ex(SVM_CLGI
));
263 static inline void stgi(void)
265 asm volatile (__ex(SVM_STGI
));
268 static inline void invlpga(unsigned long addr
, u32 asid
)
270 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
273 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
275 to_svm(vcpu
)->asid_generation
--;
278 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
280 force_new_asid(vcpu
);
283 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
285 if (!npt_enabled
&& !(efer
& EFER_LMA
))
288 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
289 vcpu
->arch
.efer
= efer
;
292 static int is_external_interrupt(u32 info
)
294 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
295 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
298 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
300 struct vcpu_svm
*svm
= to_svm(vcpu
);
303 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
304 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
308 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
310 struct vcpu_svm
*svm
= to_svm(vcpu
);
313 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
315 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
319 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
321 struct vcpu_svm
*svm
= to_svm(vcpu
);
323 if (svm
->vmcb
->control
.next_rip
!= 0)
324 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
326 if (!svm
->next_rip
) {
327 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
329 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
332 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
333 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
334 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
336 kvm_rip_write(vcpu
, svm
->next_rip
);
337 svm_set_interrupt_shadow(vcpu
, 0);
340 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
341 bool has_error_code
, u32 error_code
)
343 struct vcpu_svm
*svm
= to_svm(vcpu
);
346 * If we are within a nested VM we'd better #VMEXIT and let the guest
347 * handle the exception
349 if (nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
352 if (nr
== BP_VECTOR
&& !svm_has(SVM_FEATURE_NRIP
)) {
353 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
356 * For guest debugging where we have to reinject #BP if some
357 * INT3 is guest-owned:
358 * Emulate nRIP by moving RIP forward. Will fail if injection
359 * raises a fault that is not intercepted. Still better than
360 * failing in all cases.
362 skip_emulated_instruction(&svm
->vcpu
);
363 rip
= kvm_rip_read(&svm
->vcpu
);
364 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
365 svm
->int3_injected
= rip
- old_rip
;
368 svm
->vmcb
->control
.event_inj
= nr
370 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
371 | SVM_EVTINJ_TYPE_EXEPT
;
372 svm
->vmcb
->control
.event_inj_err
= error_code
;
375 static int has_svm(void)
379 if (!cpu_has_svm(&msg
)) {
380 printk(KERN_INFO
"has_svm: %s\n", msg
);
387 static void svm_hardware_disable(void *garbage
)
392 static int svm_hardware_enable(void *garbage
)
395 struct svm_cpu_data
*sd
;
397 struct desc_ptr gdt_descr
;
398 struct desc_struct
*gdt
;
399 int me
= raw_smp_processor_id();
401 rdmsrl(MSR_EFER
, efer
);
402 if (efer
& EFER_SVME
)
406 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
410 sd
= per_cpu(svm_data
, me
);
413 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
418 sd
->asid_generation
= 1;
419 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
420 sd
->next_asid
= sd
->max_asid
+ 1;
422 native_store_gdt(&gdt_descr
);
423 gdt
= (struct desc_struct
*)gdt_descr
.address
;
424 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
426 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
428 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
433 static void svm_cpu_uninit(int cpu
)
435 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
440 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
441 __free_page(sd
->save_area
);
445 static int svm_cpu_init(int cpu
)
447 struct svm_cpu_data
*sd
;
450 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
454 sd
->save_area
= alloc_page(GFP_KERNEL
);
459 per_cpu(svm_data
, cpu
) = sd
;
469 static bool valid_msr_intercept(u32 index
)
473 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
474 if (direct_access_msrs
[i
].index
== index
)
480 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
483 u8 bit_read
, bit_write
;
488 * If this warning triggers extend the direct_access_msrs list at the
489 * beginning of the file
491 WARN_ON(!valid_msr_intercept(msr
));
493 offset
= svm_msrpm_offset(msr
);
494 bit_read
= 2 * (msr
& 0x0f);
495 bit_write
= 2 * (msr
& 0x0f) + 1;
498 BUG_ON(offset
== MSR_INVALID
);
500 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
501 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
506 static void svm_vcpu_init_msrpm(u32
*msrpm
)
510 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
512 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
513 if (!direct_access_msrs
[i
].always
)
516 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
520 static void add_msr_offset(u32 offset
)
524 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
526 /* Offset already in list? */
527 if (msrpm_offsets
[i
] == offset
)
530 /* Slot used by another offset? */
531 if (msrpm_offsets
[i
] != MSR_INVALID
)
534 /* Add offset to list */
535 msrpm_offsets
[i
] = offset
;
541 * If this BUG triggers the msrpm_offsets table has an overflow. Just
542 * increase MSRPM_OFFSETS in this case.
547 static void init_msrpm_offsets(void)
551 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
553 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
556 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
557 BUG_ON(offset
== MSR_INVALID
);
559 add_msr_offset(offset
);
563 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
565 u32
*msrpm
= svm
->msrpm
;
567 svm
->vmcb
->control
.lbr_ctl
= 1;
568 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
569 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
570 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
571 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
574 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
576 u32
*msrpm
= svm
->msrpm
;
578 svm
->vmcb
->control
.lbr_ctl
= 0;
579 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
580 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
581 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
582 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
585 static __init
int svm_hardware_setup(void)
588 struct page
*iopm_pages
;
592 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
597 iopm_va
= page_address(iopm_pages
);
598 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
599 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
601 init_msrpm_offsets();
603 if (boot_cpu_has(X86_FEATURE_NX
))
604 kvm_enable_efer_bits(EFER_NX
);
606 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
607 kvm_enable_efer_bits(EFER_FFXSR
);
610 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
611 kvm_enable_efer_bits(EFER_SVME
);
614 for_each_possible_cpu(cpu
) {
615 r
= svm_cpu_init(cpu
);
620 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
622 if (!svm_has(SVM_FEATURE_NPT
))
625 if (npt_enabled
&& !npt
) {
626 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
631 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
639 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
644 static __exit
void svm_hardware_unsetup(void)
648 for_each_possible_cpu(cpu
)
651 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
655 static void init_seg(struct vmcb_seg
*seg
)
658 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
659 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
664 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
667 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
672 static void init_vmcb(struct vcpu_svm
*svm
)
674 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
675 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
677 svm
->vcpu
.fpu_active
= 1;
679 control
->intercept_cr_read
= INTERCEPT_CR0_MASK
|
683 control
->intercept_cr_write
= INTERCEPT_CR0_MASK
|
688 control
->intercept_dr_read
= INTERCEPT_DR0_MASK
|
697 control
->intercept_dr_write
= INTERCEPT_DR0_MASK
|
706 control
->intercept_exceptions
= (1 << PF_VECTOR
) |
711 control
->intercept
= (1ULL << INTERCEPT_INTR
) |
712 (1ULL << INTERCEPT_NMI
) |
713 (1ULL << INTERCEPT_SMI
) |
714 (1ULL << INTERCEPT_SELECTIVE_CR0
) |
715 (1ULL << INTERCEPT_CPUID
) |
716 (1ULL << INTERCEPT_INVD
) |
717 (1ULL << INTERCEPT_HLT
) |
718 (1ULL << INTERCEPT_INVLPG
) |
719 (1ULL << INTERCEPT_INVLPGA
) |
720 (1ULL << INTERCEPT_IOIO_PROT
) |
721 (1ULL << INTERCEPT_MSR_PROT
) |
722 (1ULL << INTERCEPT_TASK_SWITCH
) |
723 (1ULL << INTERCEPT_SHUTDOWN
) |
724 (1ULL << INTERCEPT_VMRUN
) |
725 (1ULL << INTERCEPT_VMMCALL
) |
726 (1ULL << INTERCEPT_VMLOAD
) |
727 (1ULL << INTERCEPT_VMSAVE
) |
728 (1ULL << INTERCEPT_STGI
) |
729 (1ULL << INTERCEPT_CLGI
) |
730 (1ULL << INTERCEPT_SKINIT
) |
731 (1ULL << INTERCEPT_WBINVD
) |
732 (1ULL << INTERCEPT_MONITOR
) |
733 (1ULL << INTERCEPT_MWAIT
);
735 control
->iopm_base_pa
= iopm_base
;
736 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
737 control
->tsc_offset
= 0;
738 control
->int_ctl
= V_INTR_MASKING_MASK
;
746 save
->cs
.selector
= 0xf000;
747 /* Executable/Readable Code Segment */
748 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
749 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
750 save
->cs
.limit
= 0xffff;
752 * cs.base should really be 0xffff0000, but vmx can't handle that, so
753 * be consistent with it.
755 * Replace when we have real mode working for vmx.
757 save
->cs
.base
= 0xf0000;
759 save
->gdtr
.limit
= 0xffff;
760 save
->idtr
.limit
= 0xffff;
762 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
763 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
765 save
->efer
= EFER_SVME
;
766 save
->dr6
= 0xffff0ff0;
769 save
->rip
= 0x0000fff0;
770 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
773 * This is the guest-visible cr0 value.
774 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
776 svm
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
777 kvm_set_cr0(&svm
->vcpu
, svm
->vcpu
.arch
.cr0
);
779 save
->cr4
= X86_CR4_PAE
;
783 /* Setup VMCB for Nested Paging */
784 control
->nested_ctl
= 1;
785 control
->intercept
&= ~((1ULL << INTERCEPT_TASK_SWITCH
) |
786 (1ULL << INTERCEPT_INVLPG
));
787 control
->intercept_exceptions
&= ~(1 << PF_VECTOR
);
788 control
->intercept_cr_read
&= ~INTERCEPT_CR3_MASK
;
789 control
->intercept_cr_write
&= ~INTERCEPT_CR3_MASK
;
790 save
->g_pat
= 0x0007040600070406ULL
;
794 force_new_asid(&svm
->vcpu
);
796 svm
->nested
.vmcb
= 0;
797 svm
->vcpu
.arch
.hflags
= 0;
799 if (svm_has(SVM_FEATURE_PAUSE_FILTER
)) {
800 control
->pause_filter_count
= 3000;
801 control
->intercept
|= (1ULL << INTERCEPT_PAUSE
);
807 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
809 struct vcpu_svm
*svm
= to_svm(vcpu
);
813 if (!kvm_vcpu_is_bsp(vcpu
)) {
814 kvm_rip_write(vcpu
, 0);
815 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
816 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
818 vcpu
->arch
.regs_avail
= ~0;
819 vcpu
->arch
.regs_dirty
= ~0;
824 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
826 struct vcpu_svm
*svm
;
828 struct page
*msrpm_pages
;
829 struct page
*hsave_page
;
830 struct page
*nested_msrpm_pages
;
833 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
839 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
844 page
= alloc_page(GFP_KERNEL
);
848 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
852 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
853 if (!nested_msrpm_pages
)
856 hsave_page
= alloc_page(GFP_KERNEL
);
860 svm
->nested
.hsave
= page_address(hsave_page
);
862 svm
->msrpm
= page_address(msrpm_pages
);
863 svm_vcpu_init_msrpm(svm
->msrpm
);
865 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
866 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
868 svm
->vmcb
= page_address(page
);
869 clear_page(svm
->vmcb
);
870 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
871 svm
->asid_generation
= 0;
875 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
876 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
877 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
882 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
884 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
888 kvm_vcpu_uninit(&svm
->vcpu
);
890 kmem_cache_free(kvm_vcpu_cache
, svm
);
895 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
897 struct vcpu_svm
*svm
= to_svm(vcpu
);
899 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
900 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
901 __free_page(virt_to_page(svm
->nested
.hsave
));
902 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
903 kvm_vcpu_uninit(vcpu
);
904 kmem_cache_free(kvm_vcpu_cache
, svm
);
907 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
909 struct vcpu_svm
*svm
= to_svm(vcpu
);
912 if (unlikely(cpu
!= vcpu
->cpu
)) {
915 if (check_tsc_unstable()) {
917 * Make sure that the guest sees a monotonically
920 delta
= vcpu
->arch
.host_tsc
- native_read_tsc();
921 svm
->vmcb
->control
.tsc_offset
+= delta
;
923 svm
->nested
.hsave
->control
.tsc_offset
+= delta
;
926 kvm_migrate_timers(vcpu
);
927 svm
->asid_generation
= 0;
930 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
931 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
934 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
936 struct vcpu_svm
*svm
= to_svm(vcpu
);
939 ++vcpu
->stat
.host_state_reload
;
940 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
941 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
943 vcpu
->arch
.host_tsc
= native_read_tsc();
946 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
948 return to_svm(vcpu
)->vmcb
->save
.rflags
;
951 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
953 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
956 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
959 case VCPU_EXREG_PDPTR
:
960 BUG_ON(!npt_enabled
);
961 load_pdptrs(vcpu
, vcpu
->arch
.cr3
);
968 static void svm_set_vintr(struct vcpu_svm
*svm
)
970 svm
->vmcb
->control
.intercept
|= 1ULL << INTERCEPT_VINTR
;
973 static void svm_clear_vintr(struct vcpu_svm
*svm
)
975 svm
->vmcb
->control
.intercept
&= ~(1ULL << INTERCEPT_VINTR
);
978 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
980 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
983 case VCPU_SREG_CS
: return &save
->cs
;
984 case VCPU_SREG_DS
: return &save
->ds
;
985 case VCPU_SREG_ES
: return &save
->es
;
986 case VCPU_SREG_FS
: return &save
->fs
;
987 case VCPU_SREG_GS
: return &save
->gs
;
988 case VCPU_SREG_SS
: return &save
->ss
;
989 case VCPU_SREG_TR
: return &save
->tr
;
990 case VCPU_SREG_LDTR
: return &save
->ldtr
;
996 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
998 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1003 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1004 struct kvm_segment
*var
, int seg
)
1006 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1008 var
->base
= s
->base
;
1009 var
->limit
= s
->limit
;
1010 var
->selector
= s
->selector
;
1011 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1012 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1013 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1014 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1015 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1016 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1017 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1018 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1021 * AMD's VMCB does not have an explicit unusable field, so emulate it
1022 * for cross vendor migration purposes by "not present"
1024 var
->unusable
= !var
->present
|| (var
->type
== 0);
1029 * SVM always stores 0 for the 'G' bit in the CS selector in
1030 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1031 * Intel's VMENTRY has a check on the 'G' bit.
1033 var
->g
= s
->limit
> 0xfffff;
1037 * Work around a bug where the busy flag in the tr selector
1047 * The accessed bit must always be set in the segment
1048 * descriptor cache, although it can be cleared in the
1049 * descriptor, the cached bit always remains at 1. Since
1050 * Intel has a check on this, set it here to support
1051 * cross-vendor migration.
1058 * On AMD CPUs sometimes the DB bit in the segment
1059 * descriptor is left as 1, although the whole segment has
1060 * been made unusable. Clear it here to pass an Intel VMX
1061 * entry check when cross vendor migrating.
1069 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1071 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1076 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1078 struct vcpu_svm
*svm
= to_svm(vcpu
);
1080 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1081 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1084 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1086 struct vcpu_svm
*svm
= to_svm(vcpu
);
1088 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1089 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1092 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1094 struct vcpu_svm
*svm
= to_svm(vcpu
);
1096 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1097 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1100 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1102 struct vcpu_svm
*svm
= to_svm(vcpu
);
1104 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1105 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1108 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1112 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1116 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1118 struct vmcb
*vmcb
= svm
->vmcb
;
1119 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1120 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1122 if (!svm
->vcpu
.fpu_active
)
1123 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1125 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1126 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1129 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1130 vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1131 vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1132 if (is_nested(svm
)) {
1133 struct vmcb
*hsave
= svm
->nested
.hsave
;
1135 hsave
->control
.intercept_cr_read
&= ~INTERCEPT_CR0_MASK
;
1136 hsave
->control
.intercept_cr_write
&= ~INTERCEPT_CR0_MASK
;
1137 vmcb
->control
.intercept_cr_read
|= svm
->nested
.intercept_cr_read
;
1138 vmcb
->control
.intercept_cr_write
|= svm
->nested
.intercept_cr_write
;
1141 svm
->vmcb
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1142 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1143 if (is_nested(svm
)) {
1144 struct vmcb
*hsave
= svm
->nested
.hsave
;
1146 hsave
->control
.intercept_cr_read
|= INTERCEPT_CR0_MASK
;
1147 hsave
->control
.intercept_cr_write
|= INTERCEPT_CR0_MASK
;
1152 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1154 struct vcpu_svm
*svm
= to_svm(vcpu
);
1156 if (is_nested(svm
)) {
1158 * We are here because we run in nested mode, the host kvm
1159 * intercepts cr0 writes but the l1 hypervisor does not.
1160 * But the L1 hypervisor may intercept selective cr0 writes.
1161 * This needs to be checked here.
1163 unsigned long old
, new;
1165 /* Remove bits that would trigger a real cr0 write intercept */
1166 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1167 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1170 /* cr0 write with ts and mp unchanged */
1171 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1172 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
)
1177 #ifdef CONFIG_X86_64
1178 if (vcpu
->arch
.efer
& EFER_LME
) {
1179 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1180 vcpu
->arch
.efer
|= EFER_LMA
;
1181 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1184 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1185 vcpu
->arch
.efer
&= ~EFER_LMA
;
1186 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1190 vcpu
->arch
.cr0
= cr0
;
1193 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1195 if (!vcpu
->fpu_active
)
1198 * re-enable caching here because the QEMU bios
1199 * does not do it - this results in some delay at
1202 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1203 svm
->vmcb
->save
.cr0
= cr0
;
1204 update_cr0_intercept(svm
);
1207 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1209 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1210 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1212 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1213 force_new_asid(vcpu
);
1215 vcpu
->arch
.cr4
= cr4
;
1218 cr4
|= host_cr4_mce
;
1219 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1222 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1223 struct kvm_segment
*var
, int seg
)
1225 struct vcpu_svm
*svm
= to_svm(vcpu
);
1226 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1228 s
->base
= var
->base
;
1229 s
->limit
= var
->limit
;
1230 s
->selector
= var
->selector
;
1234 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1235 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1236 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1237 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1238 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1239 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1240 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1241 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1243 if (seg
== VCPU_SREG_CS
)
1245 = (svm
->vmcb
->save
.cs
.attrib
1246 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1250 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1252 struct vcpu_svm
*svm
= to_svm(vcpu
);
1254 svm
->vmcb
->control
.intercept_exceptions
&=
1255 ~((1 << DB_VECTOR
) | (1 << BP_VECTOR
));
1257 if (svm
->nmi_singlestep
)
1258 svm
->vmcb
->control
.intercept_exceptions
|= (1 << DB_VECTOR
);
1260 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1261 if (vcpu
->guest_debug
&
1262 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1263 svm
->vmcb
->control
.intercept_exceptions
|=
1265 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1266 svm
->vmcb
->control
.intercept_exceptions
|=
1269 vcpu
->guest_debug
= 0;
1272 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1274 struct vcpu_svm
*svm
= to_svm(vcpu
);
1276 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1277 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1279 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1281 update_db_intercept(vcpu
);
1284 static void load_host_msrs(struct kvm_vcpu
*vcpu
)
1286 #ifdef CONFIG_X86_64
1287 wrmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1291 static void save_host_msrs(struct kvm_vcpu
*vcpu
)
1293 #ifdef CONFIG_X86_64
1294 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host_gs_base
);
1298 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1300 if (sd
->next_asid
> sd
->max_asid
) {
1301 ++sd
->asid_generation
;
1303 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1306 svm
->asid_generation
= sd
->asid_generation
;
1307 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1310 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1312 struct vcpu_svm
*svm
= to_svm(vcpu
);
1314 svm
->vmcb
->save
.dr7
= value
;
1317 static int pf_interception(struct vcpu_svm
*svm
)
1322 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1323 error_code
= svm
->vmcb
->control
.exit_info_1
;
1325 trace_kvm_page_fault(fault_address
, error_code
);
1326 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1327 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1328 return kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1331 static int db_interception(struct vcpu_svm
*svm
)
1333 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1335 if (!(svm
->vcpu
.guest_debug
&
1336 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1337 !svm
->nmi_singlestep
) {
1338 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1342 if (svm
->nmi_singlestep
) {
1343 svm
->nmi_singlestep
= false;
1344 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1345 svm
->vmcb
->save
.rflags
&=
1346 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1347 update_db_intercept(&svm
->vcpu
);
1350 if (svm
->vcpu
.guest_debug
&
1351 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1352 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1353 kvm_run
->debug
.arch
.pc
=
1354 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1355 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1362 static int bp_interception(struct vcpu_svm
*svm
)
1364 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1366 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1367 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1368 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1372 static int ud_interception(struct vcpu_svm
*svm
)
1376 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1377 if (er
!= EMULATE_DONE
)
1378 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1382 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1384 struct vcpu_svm
*svm
= to_svm(vcpu
);
1387 if (is_nested(svm
)) {
1390 h_excp
= svm
->nested
.hsave
->control
.intercept_exceptions
;
1391 n_excp
= svm
->nested
.intercept_exceptions
;
1392 h_excp
&= ~(1 << NM_VECTOR
);
1393 excp
= h_excp
| n_excp
;
1395 excp
= svm
->vmcb
->control
.intercept_exceptions
;
1396 excp
&= ~(1 << NM_VECTOR
);
1399 svm
->vmcb
->control
.intercept_exceptions
= excp
;
1401 svm
->vcpu
.fpu_active
= 1;
1402 update_cr0_intercept(svm
);
1405 static int nm_interception(struct vcpu_svm
*svm
)
1407 svm_fpu_activate(&svm
->vcpu
);
1411 static int mc_interception(struct vcpu_svm
*svm
)
1414 * On an #MC intercept the MCE handler is not called automatically in
1415 * the host. So do it by hand here.
1419 /* not sure if we ever come back to this point */
1424 static int shutdown_interception(struct vcpu_svm
*svm
)
1426 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1429 * VMCB is undefined after a SHUTDOWN intercept
1430 * so reinitialize it.
1432 clear_page(svm
->vmcb
);
1435 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1439 static int io_interception(struct vcpu_svm
*svm
)
1441 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1442 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1443 int size
, in
, string
;
1446 ++svm
->vcpu
.stat
.io_exits
;
1447 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1448 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1450 return !(emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DO_MMIO
);
1452 port
= io_info
>> 16;
1453 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1454 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1455 skip_emulated_instruction(&svm
->vcpu
);
1457 return kvm_fast_pio_out(vcpu
, size
, port
);
1460 static int nmi_interception(struct vcpu_svm
*svm
)
1465 static int intr_interception(struct vcpu_svm
*svm
)
1467 ++svm
->vcpu
.stat
.irq_exits
;
1471 static int nop_on_interception(struct vcpu_svm
*svm
)
1476 static int halt_interception(struct vcpu_svm
*svm
)
1478 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1479 skip_emulated_instruction(&svm
->vcpu
);
1480 return kvm_emulate_halt(&svm
->vcpu
);
1483 static int vmmcall_interception(struct vcpu_svm
*svm
)
1485 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1486 skip_emulated_instruction(&svm
->vcpu
);
1487 kvm_emulate_hypercall(&svm
->vcpu
);
1491 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1493 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1494 || !is_paging(&svm
->vcpu
)) {
1495 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1499 if (svm
->vmcb
->save
.cpl
) {
1500 kvm_inject_gp(&svm
->vcpu
, 0);
1507 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1508 bool has_error_code
, u32 error_code
)
1512 if (!is_nested(svm
))
1515 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1516 svm
->vmcb
->control
.exit_code_hi
= 0;
1517 svm
->vmcb
->control
.exit_info_1
= error_code
;
1518 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1520 vmexit
= nested_svm_intercept(svm
);
1521 if (vmexit
== NESTED_EXIT_DONE
)
1522 svm
->nested
.exit_required
= true;
1527 /* This function returns true if it is save to enable the irq window */
1528 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1530 if (!is_nested(svm
))
1533 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1536 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1539 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1540 svm
->vmcb
->control
.exit_info_1
= 0;
1541 svm
->vmcb
->control
.exit_info_2
= 0;
1543 if (svm
->nested
.intercept
& 1ULL) {
1545 * The #vmexit can't be emulated here directly because this
1546 * code path runs with irqs and preemtion disabled. A
1547 * #vmexit emulation might sleep. Only signal request for
1550 svm
->nested
.exit_required
= true;
1551 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1558 /* This function returns true if it is save to enable the nmi window */
1559 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1561 if (!is_nested(svm
))
1564 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1567 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1568 svm
->nested
.exit_required
= true;
1573 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1579 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1580 if (is_error_page(page
))
1588 kvm_release_page_clean(page
);
1589 kvm_inject_gp(&svm
->vcpu
, 0);
1594 static void nested_svm_unmap(struct page
*page
)
1597 kvm_release_page_dirty(page
);
1600 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1606 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1607 return NESTED_EXIT_HOST
;
1609 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1610 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1614 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1617 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1620 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1622 u32 offset
, msr
, value
;
1625 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1626 return NESTED_EXIT_HOST
;
1628 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1629 offset
= svm_msrpm_offset(msr
);
1630 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1631 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1633 if (offset
== MSR_INVALID
)
1634 return NESTED_EXIT_DONE
;
1636 /* Offset is in 32 bit units but need in 8 bit units */
1639 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1640 return NESTED_EXIT_DONE
;
1642 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1645 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1647 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1649 switch (exit_code
) {
1652 return NESTED_EXIT_HOST
;
1654 /* For now we are always handling NPFs when using them */
1656 return NESTED_EXIT_HOST
;
1658 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1659 /* When we're shadowing, trap PFs */
1661 return NESTED_EXIT_HOST
;
1663 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1664 nm_interception(svm
);
1670 return NESTED_EXIT_CONTINUE
;
1674 * If this function returns true, this #vmexit was already handled
1676 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1678 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1679 int vmexit
= NESTED_EXIT_HOST
;
1681 switch (exit_code
) {
1683 vmexit
= nested_svm_exit_handled_msr(svm
);
1686 vmexit
= nested_svm_intercept_ioio(svm
);
1688 case SVM_EXIT_READ_CR0
... SVM_EXIT_READ_CR8
: {
1689 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_READ_CR0
);
1690 if (svm
->nested
.intercept_cr_read
& cr_bits
)
1691 vmexit
= NESTED_EXIT_DONE
;
1694 case SVM_EXIT_WRITE_CR0
... SVM_EXIT_WRITE_CR8
: {
1695 u32 cr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_CR0
);
1696 if (svm
->nested
.intercept_cr_write
& cr_bits
)
1697 vmexit
= NESTED_EXIT_DONE
;
1700 case SVM_EXIT_READ_DR0
... SVM_EXIT_READ_DR7
: {
1701 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_READ_DR0
);
1702 if (svm
->nested
.intercept_dr_read
& dr_bits
)
1703 vmexit
= NESTED_EXIT_DONE
;
1706 case SVM_EXIT_WRITE_DR0
... SVM_EXIT_WRITE_DR7
: {
1707 u32 dr_bits
= 1 << (exit_code
- SVM_EXIT_WRITE_DR0
);
1708 if (svm
->nested
.intercept_dr_write
& dr_bits
)
1709 vmexit
= NESTED_EXIT_DONE
;
1712 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1713 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1714 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1715 vmexit
= NESTED_EXIT_DONE
;
1719 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
1720 if (svm
->nested
.intercept
& exit_bits
)
1721 vmexit
= NESTED_EXIT_DONE
;
1728 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
1732 vmexit
= nested_svm_intercept(svm
);
1734 if (vmexit
== NESTED_EXIT_DONE
)
1735 nested_svm_vmexit(svm
);
1740 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
1742 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
1743 struct vmcb_control_area
*from
= &from_vmcb
->control
;
1745 dst
->intercept_cr_read
= from
->intercept_cr_read
;
1746 dst
->intercept_cr_write
= from
->intercept_cr_write
;
1747 dst
->intercept_dr_read
= from
->intercept_dr_read
;
1748 dst
->intercept_dr_write
= from
->intercept_dr_write
;
1749 dst
->intercept_exceptions
= from
->intercept_exceptions
;
1750 dst
->intercept
= from
->intercept
;
1751 dst
->iopm_base_pa
= from
->iopm_base_pa
;
1752 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
1753 dst
->tsc_offset
= from
->tsc_offset
;
1754 dst
->asid
= from
->asid
;
1755 dst
->tlb_ctl
= from
->tlb_ctl
;
1756 dst
->int_ctl
= from
->int_ctl
;
1757 dst
->int_vector
= from
->int_vector
;
1758 dst
->int_state
= from
->int_state
;
1759 dst
->exit_code
= from
->exit_code
;
1760 dst
->exit_code_hi
= from
->exit_code_hi
;
1761 dst
->exit_info_1
= from
->exit_info_1
;
1762 dst
->exit_info_2
= from
->exit_info_2
;
1763 dst
->exit_int_info
= from
->exit_int_info
;
1764 dst
->exit_int_info_err
= from
->exit_int_info_err
;
1765 dst
->nested_ctl
= from
->nested_ctl
;
1766 dst
->event_inj
= from
->event_inj
;
1767 dst
->event_inj_err
= from
->event_inj_err
;
1768 dst
->nested_cr3
= from
->nested_cr3
;
1769 dst
->lbr_ctl
= from
->lbr_ctl
;
1772 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
1774 struct vmcb
*nested_vmcb
;
1775 struct vmcb
*hsave
= svm
->nested
.hsave
;
1776 struct vmcb
*vmcb
= svm
->vmcb
;
1779 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
1780 vmcb
->control
.exit_info_1
,
1781 vmcb
->control
.exit_info_2
,
1782 vmcb
->control
.exit_int_info
,
1783 vmcb
->control
.exit_int_info_err
);
1785 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
1789 /* Exit nested SVM mode */
1790 svm
->nested
.vmcb
= 0;
1792 /* Give the current vmcb to the guest */
1795 nested_vmcb
->save
.es
= vmcb
->save
.es
;
1796 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
1797 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
1798 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
1799 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
1800 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
1801 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1803 nested_vmcb
->save
.cr3
= vmcb
->save
.cr3
;
1805 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1806 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
1807 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1808 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
1809 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
1810 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
1811 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
1812 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
1813 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
1814 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
1816 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
1817 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
1818 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
1819 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
1820 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
1821 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
1822 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
1823 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
1824 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
1827 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1828 * to make sure that we do not lose injected events. So check event_inj
1829 * here and copy it to exit_int_info if it is valid.
1830 * Exit_int_info and event_inj can't be both valid because the case
1831 * below only happens on a VMRUN instruction intercept which has
1832 * no valid exit_int_info set.
1834 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
1835 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
1837 nc
->exit_int_info
= vmcb
->control
.event_inj
;
1838 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
1841 nested_vmcb
->control
.tlb_ctl
= 0;
1842 nested_vmcb
->control
.event_inj
= 0;
1843 nested_vmcb
->control
.event_inj_err
= 0;
1845 /* We always set V_INTR_MASKING and remember the old value in hflags */
1846 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1847 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
1849 /* Restore the original control entries */
1850 copy_vmcb_control_area(vmcb
, hsave
);
1852 kvm_clear_exception_queue(&svm
->vcpu
);
1853 kvm_clear_interrupt_queue(&svm
->vcpu
);
1855 /* Restore selected save entries */
1856 svm
->vmcb
->save
.es
= hsave
->save
.es
;
1857 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
1858 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
1859 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
1860 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
1861 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
1862 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
1863 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
1864 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
1865 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
1867 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
1868 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
1870 kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
1872 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
1873 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
1874 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
1875 svm
->vmcb
->save
.dr7
= 0;
1876 svm
->vmcb
->save
.cpl
= 0;
1877 svm
->vmcb
->control
.exit_int_info
= 0;
1879 nested_svm_unmap(page
);
1881 kvm_mmu_reset_context(&svm
->vcpu
);
1882 kvm_mmu_load(&svm
->vcpu
);
1887 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
1890 * This function merges the msr permission bitmaps of kvm and the
1891 * nested vmcb. It is omptimized in that it only merges the parts where
1892 * the kvm msr permission bitmap may contain zero bits
1896 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1899 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
1903 if (msrpm_offsets
[i
] == 0xffffffff)
1906 p
= msrpm_offsets
[i
];
1907 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
1909 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
1912 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
1915 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
1920 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
1922 struct vmcb
*nested_vmcb
;
1923 struct vmcb
*hsave
= svm
->nested
.hsave
;
1924 struct vmcb
*vmcb
= svm
->vmcb
;
1928 vmcb_gpa
= svm
->vmcb
->save
.rax
;
1930 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
1934 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
- 3, vmcb_gpa
,
1935 nested_vmcb
->save
.rip
,
1936 nested_vmcb
->control
.int_ctl
,
1937 nested_vmcb
->control
.event_inj
,
1938 nested_vmcb
->control
.nested_ctl
);
1940 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr_read
,
1941 nested_vmcb
->control
.intercept_cr_write
,
1942 nested_vmcb
->control
.intercept_exceptions
,
1943 nested_vmcb
->control
.intercept
);
1945 /* Clear internal status */
1946 kvm_clear_exception_queue(&svm
->vcpu
);
1947 kvm_clear_interrupt_queue(&svm
->vcpu
);
1950 * Save the old vmcb, so we don't need to pick what we save, but can
1951 * restore everything when a VMEXIT occurs
1953 hsave
->save
.es
= vmcb
->save
.es
;
1954 hsave
->save
.cs
= vmcb
->save
.cs
;
1955 hsave
->save
.ss
= vmcb
->save
.ss
;
1956 hsave
->save
.ds
= vmcb
->save
.ds
;
1957 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
1958 hsave
->save
.idtr
= vmcb
->save
.idtr
;
1959 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
1960 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
1961 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
1962 hsave
->save
.rflags
= vmcb
->save
.rflags
;
1963 hsave
->save
.rip
= svm
->next_rip
;
1964 hsave
->save
.rsp
= vmcb
->save
.rsp
;
1965 hsave
->save
.rax
= vmcb
->save
.rax
;
1967 hsave
->save
.cr3
= vmcb
->save
.cr3
;
1969 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
1971 copy_vmcb_control_area(hsave
, vmcb
);
1973 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
1974 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
1976 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
1978 /* Load the nested guest state */
1979 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
1980 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
1981 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
1982 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
1983 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
1984 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
1985 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
1986 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
1987 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
1988 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
1990 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
1991 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
1993 kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
1995 /* Guest paging mode is active - reset mmu */
1996 kvm_mmu_reset_context(&svm
->vcpu
);
1998 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
1999 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2000 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2001 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2003 /* In case we don't even reach vcpu_run, the fields are not updated */
2004 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2005 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2006 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2007 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2008 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2009 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2011 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2012 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2014 /* cache intercepts */
2015 svm
->nested
.intercept_cr_read
= nested_vmcb
->control
.intercept_cr_read
;
2016 svm
->nested
.intercept_cr_write
= nested_vmcb
->control
.intercept_cr_write
;
2017 svm
->nested
.intercept_dr_read
= nested_vmcb
->control
.intercept_dr_read
;
2018 svm
->nested
.intercept_dr_write
= nested_vmcb
->control
.intercept_dr_write
;
2019 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2020 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2022 force_new_asid(&svm
->vcpu
);
2023 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2024 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2025 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2027 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2029 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2030 /* We only want the cr8 intercept bits of the guest */
2031 svm
->vmcb
->control
.intercept_cr_read
&= ~INTERCEPT_CR8_MASK
;
2032 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2036 * We don't want a nested guest to be more powerful than the guest, so
2037 * all intercepts are ORed
2039 svm
->vmcb
->control
.intercept_cr_read
|=
2040 nested_vmcb
->control
.intercept_cr_read
;
2041 svm
->vmcb
->control
.intercept_cr_write
|=
2042 nested_vmcb
->control
.intercept_cr_write
;
2043 svm
->vmcb
->control
.intercept_dr_read
|=
2044 nested_vmcb
->control
.intercept_dr_read
;
2045 svm
->vmcb
->control
.intercept_dr_write
|=
2046 nested_vmcb
->control
.intercept_dr_write
;
2047 svm
->vmcb
->control
.intercept_exceptions
|=
2048 nested_vmcb
->control
.intercept_exceptions
;
2050 svm
->vmcb
->control
.intercept
|= nested_vmcb
->control
.intercept
;
2052 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2053 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2054 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2055 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2056 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2057 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2059 nested_svm_unmap(page
);
2061 /* nested_vmcb is our indicator if nested SVM is activated */
2062 svm
->nested
.vmcb
= vmcb_gpa
;
2069 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2071 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2072 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2073 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2074 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2075 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2076 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2077 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2078 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2079 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2080 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2081 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2082 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2085 static int vmload_interception(struct vcpu_svm
*svm
)
2087 struct vmcb
*nested_vmcb
;
2090 if (nested_svm_check_permissions(svm
))
2093 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2094 skip_emulated_instruction(&svm
->vcpu
);
2096 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2100 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2101 nested_svm_unmap(page
);
2106 static int vmsave_interception(struct vcpu_svm
*svm
)
2108 struct vmcb
*nested_vmcb
;
2111 if (nested_svm_check_permissions(svm
))
2114 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2115 skip_emulated_instruction(&svm
->vcpu
);
2117 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2121 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2122 nested_svm_unmap(page
);
2127 static int vmrun_interception(struct vcpu_svm
*svm
)
2129 if (nested_svm_check_permissions(svm
))
2132 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2133 skip_emulated_instruction(&svm
->vcpu
);
2135 if (!nested_svm_vmrun(svm
))
2138 if (!nested_svm_vmrun_msrpm(svm
))
2145 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2146 svm
->vmcb
->control
.exit_code_hi
= 0;
2147 svm
->vmcb
->control
.exit_info_1
= 0;
2148 svm
->vmcb
->control
.exit_info_2
= 0;
2150 nested_svm_vmexit(svm
);
2155 static int stgi_interception(struct vcpu_svm
*svm
)
2157 if (nested_svm_check_permissions(svm
))
2160 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2161 skip_emulated_instruction(&svm
->vcpu
);
2168 static int clgi_interception(struct vcpu_svm
*svm
)
2170 if (nested_svm_check_permissions(svm
))
2173 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2174 skip_emulated_instruction(&svm
->vcpu
);
2178 /* After a CLGI no interrupts should come */
2179 svm_clear_vintr(svm
);
2180 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2185 static int invlpga_interception(struct vcpu_svm
*svm
)
2187 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2189 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2190 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2192 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2193 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2195 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2196 skip_emulated_instruction(&svm
->vcpu
);
2200 static int skinit_interception(struct vcpu_svm
*svm
)
2202 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2204 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2208 static int invalid_op_interception(struct vcpu_svm
*svm
)
2210 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2214 static int task_switch_interception(struct vcpu_svm
*svm
)
2218 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2219 SVM_EXITINTINFO_TYPE_MASK
;
2220 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2222 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2224 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2225 bool has_error_code
= false;
2228 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2230 if (svm
->vmcb
->control
.exit_info_2
&
2231 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2232 reason
= TASK_SWITCH_IRET
;
2233 else if (svm
->vmcb
->control
.exit_info_2
&
2234 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2235 reason
= TASK_SWITCH_JMP
;
2237 reason
= TASK_SWITCH_GATE
;
2239 reason
= TASK_SWITCH_CALL
;
2241 if (reason
== TASK_SWITCH_GATE
) {
2243 case SVM_EXITINTINFO_TYPE_NMI
:
2244 svm
->vcpu
.arch
.nmi_injected
= false;
2246 case SVM_EXITINTINFO_TYPE_EXEPT
:
2247 if (svm
->vmcb
->control
.exit_info_2
&
2248 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2249 has_error_code
= true;
2251 (u32
)svm
->vmcb
->control
.exit_info_2
;
2253 kvm_clear_exception_queue(&svm
->vcpu
);
2255 case SVM_EXITINTINFO_TYPE_INTR
:
2256 kvm_clear_interrupt_queue(&svm
->vcpu
);
2263 if (reason
!= TASK_SWITCH_GATE
||
2264 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2265 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2266 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2267 skip_emulated_instruction(&svm
->vcpu
);
2269 return kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2270 has_error_code
, error_code
);
2273 static int cpuid_interception(struct vcpu_svm
*svm
)
2275 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2276 kvm_emulate_cpuid(&svm
->vcpu
);
2280 static int iret_interception(struct vcpu_svm
*svm
)
2282 ++svm
->vcpu
.stat
.nmi_window_exits
;
2283 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2284 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2288 static int invlpg_interception(struct vcpu_svm
*svm
)
2290 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2291 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2295 static int emulate_on_interception(struct vcpu_svm
*svm
)
2297 if (emulate_instruction(&svm
->vcpu
, 0, 0, 0) != EMULATE_DONE
)
2298 pr_unimpl(&svm
->vcpu
, "%s: failed\n", __func__
);
2302 static int cr8_write_interception(struct vcpu_svm
*svm
)
2304 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2306 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2307 /* instruction emulation calls kvm_set_cr8() */
2308 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2309 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2310 svm
->vmcb
->control
.intercept_cr_write
&= ~INTERCEPT_CR8_MASK
;
2313 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2315 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2319 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2321 struct vcpu_svm
*svm
= to_svm(vcpu
);
2324 case MSR_IA32_TSC
: {
2328 tsc_offset
= svm
->nested
.hsave
->control
.tsc_offset
;
2330 tsc_offset
= svm
->vmcb
->control
.tsc_offset
;
2332 *data
= tsc_offset
+ native_read_tsc();
2336 *data
= svm
->vmcb
->save
.star
;
2338 #ifdef CONFIG_X86_64
2340 *data
= svm
->vmcb
->save
.lstar
;
2343 *data
= svm
->vmcb
->save
.cstar
;
2345 case MSR_KERNEL_GS_BASE
:
2346 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2348 case MSR_SYSCALL_MASK
:
2349 *data
= svm
->vmcb
->save
.sfmask
;
2352 case MSR_IA32_SYSENTER_CS
:
2353 *data
= svm
->vmcb
->save
.sysenter_cs
;
2355 case MSR_IA32_SYSENTER_EIP
:
2356 *data
= svm
->sysenter_eip
;
2358 case MSR_IA32_SYSENTER_ESP
:
2359 *data
= svm
->sysenter_esp
;
2362 * Nobody will change the following 5 values in the VMCB so we can
2363 * safely return them on rdmsr. They will always be 0 until LBRV is
2366 case MSR_IA32_DEBUGCTLMSR
:
2367 *data
= svm
->vmcb
->save
.dbgctl
;
2369 case MSR_IA32_LASTBRANCHFROMIP
:
2370 *data
= svm
->vmcb
->save
.br_from
;
2372 case MSR_IA32_LASTBRANCHTOIP
:
2373 *data
= svm
->vmcb
->save
.br_to
;
2375 case MSR_IA32_LASTINTFROMIP
:
2376 *data
= svm
->vmcb
->save
.last_excp_from
;
2378 case MSR_IA32_LASTINTTOIP
:
2379 *data
= svm
->vmcb
->save
.last_excp_to
;
2381 case MSR_VM_HSAVE_PA
:
2382 *data
= svm
->nested
.hsave_msr
;
2385 *data
= svm
->nested
.vm_cr_msr
;
2387 case MSR_IA32_UCODE_REV
:
2391 return kvm_get_msr_common(vcpu
, ecx
, data
);
2396 static int rdmsr_interception(struct vcpu_svm
*svm
)
2398 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2401 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2402 trace_kvm_msr_read_ex(ecx
);
2403 kvm_inject_gp(&svm
->vcpu
, 0);
2405 trace_kvm_msr_read(ecx
, data
);
2407 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2408 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2409 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2410 skip_emulated_instruction(&svm
->vcpu
);
2415 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2417 struct vcpu_svm
*svm
= to_svm(vcpu
);
2418 int svm_dis
, chg_mask
;
2420 if (data
& ~SVM_VM_CR_VALID_MASK
)
2423 chg_mask
= SVM_VM_CR_VALID_MASK
;
2425 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2426 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2428 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2429 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2431 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2433 /* check for svm_disable while efer.svme is set */
2434 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2440 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2442 struct vcpu_svm
*svm
= to_svm(vcpu
);
2445 case MSR_IA32_TSC
: {
2446 u64 tsc_offset
= data
- native_read_tsc();
2447 u64 g_tsc_offset
= 0;
2449 if (is_nested(svm
)) {
2450 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
2451 svm
->nested
.hsave
->control
.tsc_offset
;
2452 svm
->nested
.hsave
->control
.tsc_offset
= tsc_offset
;
2455 svm
->vmcb
->control
.tsc_offset
= tsc_offset
+ g_tsc_offset
;
2460 svm
->vmcb
->save
.star
= data
;
2462 #ifdef CONFIG_X86_64
2464 svm
->vmcb
->save
.lstar
= data
;
2467 svm
->vmcb
->save
.cstar
= data
;
2469 case MSR_KERNEL_GS_BASE
:
2470 svm
->vmcb
->save
.kernel_gs_base
= data
;
2472 case MSR_SYSCALL_MASK
:
2473 svm
->vmcb
->save
.sfmask
= data
;
2476 case MSR_IA32_SYSENTER_CS
:
2477 svm
->vmcb
->save
.sysenter_cs
= data
;
2479 case MSR_IA32_SYSENTER_EIP
:
2480 svm
->sysenter_eip
= data
;
2481 svm
->vmcb
->save
.sysenter_eip
= data
;
2483 case MSR_IA32_SYSENTER_ESP
:
2484 svm
->sysenter_esp
= data
;
2485 svm
->vmcb
->save
.sysenter_esp
= data
;
2487 case MSR_IA32_DEBUGCTLMSR
:
2488 if (!svm_has(SVM_FEATURE_LBRV
)) {
2489 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2493 if (data
& DEBUGCTL_RESERVED_BITS
)
2496 svm
->vmcb
->save
.dbgctl
= data
;
2497 if (data
& (1ULL<<0))
2498 svm_enable_lbrv(svm
);
2500 svm_disable_lbrv(svm
);
2502 case MSR_VM_HSAVE_PA
:
2503 svm
->nested
.hsave_msr
= data
;
2506 return svm_set_vm_cr(vcpu
, data
);
2508 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2511 return kvm_set_msr_common(vcpu
, ecx
, data
);
2516 static int wrmsr_interception(struct vcpu_svm
*svm
)
2518 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2519 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2520 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2523 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2524 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2525 trace_kvm_msr_write_ex(ecx
, data
);
2526 kvm_inject_gp(&svm
->vcpu
, 0);
2528 trace_kvm_msr_write(ecx
, data
);
2529 skip_emulated_instruction(&svm
->vcpu
);
2534 static int msr_interception(struct vcpu_svm
*svm
)
2536 if (svm
->vmcb
->control
.exit_info_1
)
2537 return wrmsr_interception(svm
);
2539 return rdmsr_interception(svm
);
2542 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2544 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2546 svm_clear_vintr(svm
);
2547 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2549 * If the user space waits to inject interrupts, exit as soon as
2552 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2553 kvm_run
->request_interrupt_window
&&
2554 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2555 ++svm
->vcpu
.stat
.irq_window_exits
;
2556 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2563 static int pause_interception(struct vcpu_svm
*svm
)
2565 kvm_vcpu_on_spin(&(svm
->vcpu
));
2569 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2570 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2571 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2572 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2573 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2574 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2575 [SVM_EXIT_WRITE_CR0
] = emulate_on_interception
,
2576 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2577 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2578 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2579 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2580 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2581 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2582 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2583 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2584 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2585 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2586 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2587 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2588 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2589 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2590 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2591 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2592 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2593 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2594 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2595 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2596 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2597 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2598 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2599 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2600 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2601 [SVM_EXIT_INTR
] = intr_interception
,
2602 [SVM_EXIT_NMI
] = nmi_interception
,
2603 [SVM_EXIT_SMI
] = nop_on_interception
,
2604 [SVM_EXIT_INIT
] = nop_on_interception
,
2605 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2606 [SVM_EXIT_CPUID
] = cpuid_interception
,
2607 [SVM_EXIT_IRET
] = iret_interception
,
2608 [SVM_EXIT_INVD
] = emulate_on_interception
,
2609 [SVM_EXIT_PAUSE
] = pause_interception
,
2610 [SVM_EXIT_HLT
] = halt_interception
,
2611 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2612 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2613 [SVM_EXIT_IOIO
] = io_interception
,
2614 [SVM_EXIT_MSR
] = msr_interception
,
2615 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2616 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2617 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2618 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2619 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2620 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2621 [SVM_EXIT_STGI
] = stgi_interception
,
2622 [SVM_EXIT_CLGI
] = clgi_interception
,
2623 [SVM_EXIT_SKINIT
] = skinit_interception
,
2624 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2625 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2626 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2627 [SVM_EXIT_NPF
] = pf_interception
,
2630 static int handle_exit(struct kvm_vcpu
*vcpu
)
2632 struct vcpu_svm
*svm
= to_svm(vcpu
);
2633 struct kvm_run
*kvm_run
= vcpu
->run
;
2634 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
2636 trace_kvm_exit(exit_code
, vcpu
);
2638 if (unlikely(svm
->nested
.exit_required
)) {
2639 nested_svm_vmexit(svm
);
2640 svm
->nested
.exit_required
= false;
2645 if (is_nested(svm
)) {
2648 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
2649 svm
->vmcb
->control
.exit_info_1
,
2650 svm
->vmcb
->control
.exit_info_2
,
2651 svm
->vmcb
->control
.exit_int_info
,
2652 svm
->vmcb
->control
.exit_int_info_err
);
2654 vmexit
= nested_svm_exit_special(svm
);
2656 if (vmexit
== NESTED_EXIT_CONTINUE
)
2657 vmexit
= nested_svm_exit_handled(svm
);
2659 if (vmexit
== NESTED_EXIT_DONE
)
2663 svm_complete_interrupts(svm
);
2665 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR0_MASK
))
2666 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
2668 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
2670 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
2671 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
2672 kvm_run
->fail_entry
.hardware_entry_failure_reason
2673 = svm
->vmcb
->control
.exit_code
;
2677 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
2678 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
2679 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
)
2680 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
2682 __func__
, svm
->vmcb
->control
.exit_int_info
,
2685 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
2686 || !svm_exit_handlers
[exit_code
]) {
2687 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
2688 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
2692 return svm_exit_handlers
[exit_code
](svm
);
2695 static void reload_tss(struct kvm_vcpu
*vcpu
)
2697 int cpu
= raw_smp_processor_id();
2699 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2700 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
2704 static void pre_svm_run(struct vcpu_svm
*svm
)
2706 int cpu
= raw_smp_processor_id();
2708 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
2710 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
2711 /* FIXME: handle wraparound of asid_generation */
2712 if (svm
->asid_generation
!= sd
->asid_generation
)
2716 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
2718 struct vcpu_svm
*svm
= to_svm(vcpu
);
2720 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
2721 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
2722 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2723 ++vcpu
->stat
.nmi_injections
;
2726 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
2728 struct vmcb_control_area
*control
;
2730 trace_kvm_inj_virq(irq
);
2732 ++svm
->vcpu
.stat
.irq_injections
;
2733 control
= &svm
->vmcb
->control
;
2734 control
->int_vector
= irq
;
2735 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
2736 control
->int_ctl
|= V_IRQ_MASK
|
2737 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
2740 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
2742 struct vcpu_svm
*svm
= to_svm(vcpu
);
2744 BUG_ON(!(gif_set(svm
)));
2746 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
2747 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
2750 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
2752 struct vcpu_svm
*svm
= to_svm(vcpu
);
2754 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2761 svm
->vmcb
->control
.intercept_cr_write
|= INTERCEPT_CR8_MASK
;
2764 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
2766 struct vcpu_svm
*svm
= to_svm(vcpu
);
2767 struct vmcb
*vmcb
= svm
->vmcb
;
2768 return !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
2769 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2772 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2774 struct vcpu_svm
*svm
= to_svm(vcpu
);
2776 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
2779 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2781 struct vcpu_svm
*svm
= to_svm(vcpu
);
2784 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
2785 svm
->vmcb
->control
.intercept
|= (1UL << INTERCEPT_IRET
);
2787 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
2788 svm
->vmcb
->control
.intercept
&= ~(1UL << INTERCEPT_IRET
);
2792 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2794 struct vcpu_svm
*svm
= to_svm(vcpu
);
2795 struct vmcb
*vmcb
= svm
->vmcb
;
2798 if (!gif_set(svm
) ||
2799 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
2802 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
2805 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
2810 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2812 struct vcpu_svm
*svm
= to_svm(vcpu
);
2815 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2816 * 1, because that's a separate STGI/VMRUN intercept. The next time we
2817 * get that intercept, this function will be called again though and
2818 * we'll get the vintr intercept.
2820 if (gif_set(svm
) && nested_svm_intr(svm
)) {
2822 svm_inject_irq(svm
, 0x0);
2826 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2828 struct vcpu_svm
*svm
= to_svm(vcpu
);
2830 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
2832 return; /* IRET will cause a vm exit */
2835 * Something prevents NMI from been injected. Single step over possible
2836 * problem (IRET or exception injection or interrupt shadow)
2838 if (gif_set(svm
) && nested_svm_nmi(svm
)) {
2839 svm
->nmi_singlestep
= true;
2840 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
2841 update_db_intercept(vcpu
);
2845 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2850 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
2852 force_new_asid(vcpu
);
2855 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
2859 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
2861 struct vcpu_svm
*svm
= to_svm(vcpu
);
2863 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2866 if (!(svm
->vmcb
->control
.intercept_cr_write
& INTERCEPT_CR8_MASK
)) {
2867 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
2868 kvm_set_cr8(vcpu
, cr8
);
2872 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
2874 struct vcpu_svm
*svm
= to_svm(vcpu
);
2877 if (is_nested(svm
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
2880 cr8
= kvm_get_cr8(vcpu
);
2881 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
2882 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
2885 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
2889 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
2890 unsigned int3_injected
= svm
->int3_injected
;
2892 svm
->int3_injected
= 0;
2894 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
)
2895 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
2897 svm
->vcpu
.arch
.nmi_injected
= false;
2898 kvm_clear_exception_queue(&svm
->vcpu
);
2899 kvm_clear_interrupt_queue(&svm
->vcpu
);
2901 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
2904 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
2905 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
2908 case SVM_EXITINTINFO_TYPE_NMI
:
2909 svm
->vcpu
.arch
.nmi_injected
= true;
2911 case SVM_EXITINTINFO_TYPE_EXEPT
:
2915 * In case of software exceptions, do not reinject the vector,
2916 * but re-execute the instruction instead. Rewind RIP first
2917 * if we emulated INT3 before.
2919 if (kvm_exception_is_soft(vector
)) {
2920 if (vector
== BP_VECTOR
&& int3_injected
&&
2921 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
2922 kvm_rip_write(&svm
->vcpu
,
2923 kvm_rip_read(&svm
->vcpu
) -
2927 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
2928 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
2929 kvm_queue_exception_e(&svm
->vcpu
, vector
, err
);
2932 kvm_queue_exception(&svm
->vcpu
, vector
);
2934 case SVM_EXITINTINFO_TYPE_INTR
:
2935 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
2942 #ifdef CONFIG_X86_64
2948 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
2950 struct vcpu_svm
*svm
= to_svm(vcpu
);
2956 * A vmexit emulation is required before the vcpu can be executed
2959 if (unlikely(svm
->nested
.exit_required
))
2962 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
2963 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
2964 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
2968 sync_lapic_to_cr8(vcpu
);
2970 save_host_msrs(vcpu
);
2971 fs_selector
= kvm_read_fs();
2972 gs_selector
= kvm_read_gs();
2973 ldt_selector
= kvm_read_ldt();
2974 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
2975 /* required for live migration with NPT */
2977 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
2984 "push %%"R
"bp; \n\t"
2985 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
2986 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
2987 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
2988 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
2989 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
2990 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
2991 #ifdef CONFIG_X86_64
2992 "mov %c[r8](%[svm]), %%r8 \n\t"
2993 "mov %c[r9](%[svm]), %%r9 \n\t"
2994 "mov %c[r10](%[svm]), %%r10 \n\t"
2995 "mov %c[r11](%[svm]), %%r11 \n\t"
2996 "mov %c[r12](%[svm]), %%r12 \n\t"
2997 "mov %c[r13](%[svm]), %%r13 \n\t"
2998 "mov %c[r14](%[svm]), %%r14 \n\t"
2999 "mov %c[r15](%[svm]), %%r15 \n\t"
3002 /* Enter guest mode */
3004 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3005 __ex(SVM_VMLOAD
) "\n\t"
3006 __ex(SVM_VMRUN
) "\n\t"
3007 __ex(SVM_VMSAVE
) "\n\t"
3010 /* Save guest registers, load host registers */
3011 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3012 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3013 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3014 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3015 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3016 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3017 #ifdef CONFIG_X86_64
3018 "mov %%r8, %c[r8](%[svm]) \n\t"
3019 "mov %%r9, %c[r9](%[svm]) \n\t"
3020 "mov %%r10, %c[r10](%[svm]) \n\t"
3021 "mov %%r11, %c[r11](%[svm]) \n\t"
3022 "mov %%r12, %c[r12](%[svm]) \n\t"
3023 "mov %%r13, %c[r13](%[svm]) \n\t"
3024 "mov %%r14, %c[r14](%[svm]) \n\t"
3025 "mov %%r15, %c[r15](%[svm]) \n\t"
3030 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3031 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3032 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3033 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3034 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3035 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3036 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3037 #ifdef CONFIG_X86_64
3038 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3039 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3040 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3041 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3042 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3043 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3044 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3045 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3048 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3049 #ifdef CONFIG_X86_64
3050 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3054 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3055 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3056 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3057 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3059 kvm_load_fs(fs_selector
);
3060 kvm_load_gs(gs_selector
);
3061 kvm_load_ldt(ldt_selector
);
3062 load_host_msrs(vcpu
);
3066 local_irq_disable();
3070 sync_cr8_to_lapic(vcpu
);
3075 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3076 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3082 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3084 struct vcpu_svm
*svm
= to_svm(vcpu
);
3087 svm
->vmcb
->control
.nested_cr3
= root
;
3088 force_new_asid(vcpu
);
3092 svm
->vmcb
->save
.cr3
= root
;
3093 force_new_asid(vcpu
);
3096 static int is_disabled(void)
3100 rdmsrl(MSR_VM_CR
, vm_cr
);
3101 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3108 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3111 * Patch in the VMMCALL instruction:
3113 hypercall
[0] = 0x0f;
3114 hypercall
[1] = 0x01;
3115 hypercall
[2] = 0xd9;
3118 static void svm_check_processor_compat(void *rtn
)
3123 static bool svm_cpu_has_accelerated_tpr(void)
3128 static int get_npt_level(void)
3130 #ifdef CONFIG_X86_64
3131 return PT64_ROOT_LEVEL
;
3133 return PT32E_ROOT_LEVEL
;
3137 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3142 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3146 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3147 { SVM_EXIT_READ_CR0
, "read_cr0" },
3148 { SVM_EXIT_READ_CR3
, "read_cr3" },
3149 { SVM_EXIT_READ_CR4
, "read_cr4" },
3150 { SVM_EXIT_READ_CR8
, "read_cr8" },
3151 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3152 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3153 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3154 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3155 { SVM_EXIT_READ_DR0
, "read_dr0" },
3156 { SVM_EXIT_READ_DR1
, "read_dr1" },
3157 { SVM_EXIT_READ_DR2
, "read_dr2" },
3158 { SVM_EXIT_READ_DR3
, "read_dr3" },
3159 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3160 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3161 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3162 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3163 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3164 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3165 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3166 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3167 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3168 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3169 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3170 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3171 { SVM_EXIT_INTR
, "interrupt" },
3172 { SVM_EXIT_NMI
, "nmi" },
3173 { SVM_EXIT_SMI
, "smi" },
3174 { SVM_EXIT_INIT
, "init" },
3175 { SVM_EXIT_VINTR
, "vintr" },
3176 { SVM_EXIT_CPUID
, "cpuid" },
3177 { SVM_EXIT_INVD
, "invd" },
3178 { SVM_EXIT_HLT
, "hlt" },
3179 { SVM_EXIT_INVLPG
, "invlpg" },
3180 { SVM_EXIT_INVLPGA
, "invlpga" },
3181 { SVM_EXIT_IOIO
, "io" },
3182 { SVM_EXIT_MSR
, "msr" },
3183 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3184 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3185 { SVM_EXIT_VMRUN
, "vmrun" },
3186 { SVM_EXIT_VMMCALL
, "hypercall" },
3187 { SVM_EXIT_VMLOAD
, "vmload" },
3188 { SVM_EXIT_VMSAVE
, "vmsave" },
3189 { SVM_EXIT_STGI
, "stgi" },
3190 { SVM_EXIT_CLGI
, "clgi" },
3191 { SVM_EXIT_SKINIT
, "skinit" },
3192 { SVM_EXIT_WBINVD
, "wbinvd" },
3193 { SVM_EXIT_MONITOR
, "monitor" },
3194 { SVM_EXIT_MWAIT
, "mwait" },
3195 { SVM_EXIT_NPF
, "npf" },
3199 static int svm_get_lpage_level(void)
3201 return PT_PDPE_LEVEL
;
3204 static bool svm_rdtscp_supported(void)
3209 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3211 struct vcpu_svm
*svm
= to_svm(vcpu
);
3213 svm
->vmcb
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3215 svm
->nested
.hsave
->control
.intercept_exceptions
|= 1 << NM_VECTOR
;
3216 update_cr0_intercept(svm
);
3219 static struct kvm_x86_ops svm_x86_ops
= {
3220 .cpu_has_kvm_support
= has_svm
,
3221 .disabled_by_bios
= is_disabled
,
3222 .hardware_setup
= svm_hardware_setup
,
3223 .hardware_unsetup
= svm_hardware_unsetup
,
3224 .check_processor_compatibility
= svm_check_processor_compat
,
3225 .hardware_enable
= svm_hardware_enable
,
3226 .hardware_disable
= svm_hardware_disable
,
3227 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3229 .vcpu_create
= svm_create_vcpu
,
3230 .vcpu_free
= svm_free_vcpu
,
3231 .vcpu_reset
= svm_vcpu_reset
,
3233 .prepare_guest_switch
= svm_prepare_guest_switch
,
3234 .vcpu_load
= svm_vcpu_load
,
3235 .vcpu_put
= svm_vcpu_put
,
3237 .set_guest_debug
= svm_guest_debug
,
3238 .get_msr
= svm_get_msr
,
3239 .set_msr
= svm_set_msr
,
3240 .get_segment_base
= svm_get_segment_base
,
3241 .get_segment
= svm_get_segment
,
3242 .set_segment
= svm_set_segment
,
3243 .get_cpl
= svm_get_cpl
,
3244 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3245 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3246 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3247 .set_cr0
= svm_set_cr0
,
3248 .set_cr3
= svm_set_cr3
,
3249 .set_cr4
= svm_set_cr4
,
3250 .set_efer
= svm_set_efer
,
3251 .get_idt
= svm_get_idt
,
3252 .set_idt
= svm_set_idt
,
3253 .get_gdt
= svm_get_gdt
,
3254 .set_gdt
= svm_set_gdt
,
3255 .set_dr7
= svm_set_dr7
,
3256 .cache_reg
= svm_cache_reg
,
3257 .get_rflags
= svm_get_rflags
,
3258 .set_rflags
= svm_set_rflags
,
3259 .fpu_activate
= svm_fpu_activate
,
3260 .fpu_deactivate
= svm_fpu_deactivate
,
3262 .tlb_flush
= svm_flush_tlb
,
3264 .run
= svm_vcpu_run
,
3265 .handle_exit
= handle_exit
,
3266 .skip_emulated_instruction
= skip_emulated_instruction
,
3267 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3268 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3269 .patch_hypercall
= svm_patch_hypercall
,
3270 .set_irq
= svm_set_irq
,
3271 .set_nmi
= svm_inject_nmi
,
3272 .queue_exception
= svm_queue_exception
,
3273 .interrupt_allowed
= svm_interrupt_allowed
,
3274 .nmi_allowed
= svm_nmi_allowed
,
3275 .get_nmi_mask
= svm_get_nmi_mask
,
3276 .set_nmi_mask
= svm_set_nmi_mask
,
3277 .enable_nmi_window
= enable_nmi_window
,
3278 .enable_irq_window
= enable_irq_window
,
3279 .update_cr8_intercept
= update_cr8_intercept
,
3281 .set_tss_addr
= svm_set_tss_addr
,
3282 .get_tdp_level
= get_npt_level
,
3283 .get_mt_mask
= svm_get_mt_mask
,
3285 .exit_reasons_str
= svm_exit_reasons_str
,
3286 .get_lpage_level
= svm_get_lpage_level
,
3288 .cpuid_update
= svm_cpuid_update
,
3290 .rdtscp_supported
= svm_rdtscp_supported
,
3293 static int __init
svm_init(void)
3295 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3299 static void __exit
svm_exit(void)
3304 module_init(svm_init
)
3305 module_exit(svm_exit
)