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Merge tag 'nfs-for-4.14-2' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / svm.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #define pr_fmt(fmt) "SVM: " fmt
19
20 #include <linux/kvm_host.h>
21
22 #include "irq.h"
23 #include "mmu.h"
24 #include "kvm_cache_regs.h"
25 #include "x86.h"
26 #include "cpuid.h"
27 #include "pmu.h"
28
29 #include <linux/module.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/kernel.h>
32 #include <linux/vmalloc.h>
33 #include <linux/highmem.h>
34 #include <linux/sched.h>
35 #include <linux/trace_events.h>
36 #include <linux/slab.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/hashtable.h>
39 #include <linux/frame.h>
40
41 #include <asm/apic.h>
42 #include <asm/perf_event.h>
43 #include <asm/tlbflush.h>
44 #include <asm/desc.h>
45 #include <asm/debugreg.h>
46 #include <asm/kvm_para.h>
47 #include <asm/irq_remapping.h>
48
49 #include <asm/virtext.h>
50 #include "trace.h"
51
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53
54 MODULE_AUTHOR("Qumranet");
55 MODULE_LICENSE("GPL");
56
57 static const struct x86_cpu_id svm_cpu_id[] = {
58 X86_FEATURE_MATCH(X86_FEATURE_SVM),
59 {}
60 };
61 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62
63 #define IOPM_ALLOC_ORDER 2
64 #define MSRPM_ALLOC_ORDER 1
65
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
68
69 #define SVM_FEATURE_NPT (1 << 0)
70 #define SVM_FEATURE_LBRV (1 << 1)
71 #define SVM_FEATURE_SVML (1 << 2)
72 #define SVM_FEATURE_NRIP (1 << 3)
73 #define SVM_FEATURE_TSC_RATE (1 << 4)
74 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
75 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
76 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
77 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
78
79 #define SVM_AVIC_DOORBELL 0xc001011b
80
81 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
82 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
83 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
84
85 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
86
87 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
88 #define TSC_RATIO_MIN 0x0000000000000001ULL
89 #define TSC_RATIO_MAX 0x000000ffffffffffULL
90
91 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
92
93 /*
94 * 0xff is broadcast, so the max index allowed for physical APIC ID
95 * table is 0xfe. APIC IDs above 0xff are reserved.
96 */
97 #define AVIC_MAX_PHYSICAL_ID_COUNT 255
98
99 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
100 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
101 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
102
103 /* AVIC GATAG is encoded using VM and VCPU IDs */
104 #define AVIC_VCPU_ID_BITS 8
105 #define AVIC_VCPU_ID_MASK ((1 << AVIC_VCPU_ID_BITS) - 1)
106
107 #define AVIC_VM_ID_BITS 24
108 #define AVIC_VM_ID_NR (1 << AVIC_VM_ID_BITS)
109 #define AVIC_VM_ID_MASK ((1 << AVIC_VM_ID_BITS) - 1)
110
111 #define AVIC_GATAG(x, y) (((x & AVIC_VM_ID_MASK) << AVIC_VCPU_ID_BITS) | \
112 (y & AVIC_VCPU_ID_MASK))
113 #define AVIC_GATAG_TO_VMID(x) ((x >> AVIC_VCPU_ID_BITS) & AVIC_VM_ID_MASK)
114 #define AVIC_GATAG_TO_VCPUID(x) (x & AVIC_VCPU_ID_MASK)
115
116 static bool erratum_383_found __read_mostly;
117
118 static const u32 host_save_user_msrs[] = {
119 #ifdef CONFIG_X86_64
120 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
121 MSR_FS_BASE,
122 #endif
123 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
124 MSR_TSC_AUX,
125 };
126
127 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
128
129 struct kvm_vcpu;
130
131 struct nested_state {
132 struct vmcb *hsave;
133 u64 hsave_msr;
134 u64 vm_cr_msr;
135 u64 vmcb;
136
137 /* These are the merged vectors */
138 u32 *msrpm;
139
140 /* gpa pointers to the real vectors */
141 u64 vmcb_msrpm;
142 u64 vmcb_iopm;
143
144 /* A VMEXIT is required but not yet emulated */
145 bool exit_required;
146
147 /* cache for intercepts of the guest */
148 u32 intercept_cr;
149 u32 intercept_dr;
150 u32 intercept_exceptions;
151 u64 intercept;
152
153 /* Nested Paging related state */
154 u64 nested_cr3;
155 };
156
157 #define MSRPM_OFFSETS 16
158 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
159
160 /*
161 * Set osvw_len to higher value when updated Revision Guides
162 * are published and we know what the new status bits are
163 */
164 static uint64_t osvw_len = 4, osvw_status;
165
166 struct vcpu_svm {
167 struct kvm_vcpu vcpu;
168 struct vmcb *vmcb;
169 unsigned long vmcb_pa;
170 struct svm_cpu_data *svm_data;
171 uint64_t asid_generation;
172 uint64_t sysenter_esp;
173 uint64_t sysenter_eip;
174 uint64_t tsc_aux;
175
176 u64 next_rip;
177
178 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
179 struct {
180 u16 fs;
181 u16 gs;
182 u16 ldt;
183 u64 gs_base;
184 } host;
185
186 u32 *msrpm;
187
188 ulong nmi_iret_rip;
189
190 struct nested_state nested;
191
192 bool nmi_singlestep;
193 u64 nmi_singlestep_guest_rflags;
194
195 unsigned int3_injected;
196 unsigned long int3_rip;
197
198 /* cached guest cpuid flags for faster access */
199 bool nrips_enabled : 1;
200
201 u32 ldr_reg;
202 struct page *avic_backing_page;
203 u64 *avic_physical_id_cache;
204 bool avic_is_running;
205
206 /*
207 * Per-vcpu list of struct amd_svm_iommu_ir:
208 * This is used mainly to store interrupt remapping information used
209 * when update the vcpu affinity. This avoids the need to scan for
210 * IRTE and try to match ga_tag in the IOMMU driver.
211 */
212 struct list_head ir_list;
213 spinlock_t ir_list_lock;
214 };
215
216 /*
217 * This is a wrapper of struct amd_iommu_ir_data.
218 */
219 struct amd_svm_iommu_ir {
220 struct list_head node; /* Used by SVM for per-vcpu ir_list */
221 void *data; /* Storing pointer to struct amd_ir_data */
222 };
223
224 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFF)
225 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
226
227 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK (0xFFULL)
228 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
229 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
230 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
231
232 static DEFINE_PER_CPU(u64, current_tsc_ratio);
233 #define TSC_RATIO_DEFAULT 0x0100000000ULL
234
235 #define MSR_INVALID 0xffffffffU
236
237 static const struct svm_direct_access_msrs {
238 u32 index; /* Index of the MSR */
239 bool always; /* True if intercept is always on */
240 } direct_access_msrs[] = {
241 { .index = MSR_STAR, .always = true },
242 { .index = MSR_IA32_SYSENTER_CS, .always = true },
243 #ifdef CONFIG_X86_64
244 { .index = MSR_GS_BASE, .always = true },
245 { .index = MSR_FS_BASE, .always = true },
246 { .index = MSR_KERNEL_GS_BASE, .always = true },
247 { .index = MSR_LSTAR, .always = true },
248 { .index = MSR_CSTAR, .always = true },
249 { .index = MSR_SYSCALL_MASK, .always = true },
250 #endif
251 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
252 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
253 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
254 { .index = MSR_IA32_LASTINTTOIP, .always = false },
255 { .index = MSR_INVALID, .always = false },
256 };
257
258 /* enable NPT for AMD64 and X86 with PAE */
259 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
260 static bool npt_enabled = true;
261 #else
262 static bool npt_enabled;
263 #endif
264
265 /* allow nested paging (virtualized MMU) for all guests */
266 static int npt = true;
267 module_param(npt, int, S_IRUGO);
268
269 /* allow nested virtualization in KVM/SVM */
270 static int nested = true;
271 module_param(nested, int, S_IRUGO);
272
273 /* enable / disable AVIC */
274 static int avic;
275 #ifdef CONFIG_X86_LOCAL_APIC
276 module_param(avic, int, S_IRUGO);
277 #endif
278
279 /* enable/disable Virtual VMLOAD VMSAVE */
280 static int vls = true;
281 module_param(vls, int, 0444);
282
283 /* enable/disable Virtual GIF */
284 static int vgif = true;
285 module_param(vgif, int, 0444);
286
287 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
288 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
289 static void svm_complete_interrupts(struct vcpu_svm *svm);
290
291 static int nested_svm_exit_handled(struct vcpu_svm *svm);
292 static int nested_svm_intercept(struct vcpu_svm *svm);
293 static int nested_svm_vmexit(struct vcpu_svm *svm);
294 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
295 bool has_error_code, u32 error_code);
296
297 enum {
298 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
299 pause filter count */
300 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
301 VMCB_ASID, /* ASID */
302 VMCB_INTR, /* int_ctl, int_vector */
303 VMCB_NPT, /* npt_en, nCR3, gPAT */
304 VMCB_CR, /* CR0, CR3, CR4, EFER */
305 VMCB_DR, /* DR6, DR7 */
306 VMCB_DT, /* GDT, IDT */
307 VMCB_SEG, /* CS, DS, SS, ES, CPL */
308 VMCB_CR2, /* CR2 only */
309 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
310 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
311 * AVIC PHYSICAL_TABLE pointer,
312 * AVIC LOGICAL_TABLE pointer
313 */
314 VMCB_DIRTY_MAX,
315 };
316
317 /* TPR and CR2 are always written before VMRUN */
318 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
319
320 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
321
322 static inline void mark_all_dirty(struct vmcb *vmcb)
323 {
324 vmcb->control.clean = 0;
325 }
326
327 static inline void mark_all_clean(struct vmcb *vmcb)
328 {
329 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
330 & ~VMCB_ALWAYS_DIRTY_MASK;
331 }
332
333 static inline void mark_dirty(struct vmcb *vmcb, int bit)
334 {
335 vmcb->control.clean &= ~(1 << bit);
336 }
337
338 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
339 {
340 return container_of(vcpu, struct vcpu_svm, vcpu);
341 }
342
343 static inline void avic_update_vapic_bar(struct vcpu_svm *svm, u64 data)
344 {
345 svm->vmcb->control.avic_vapic_bar = data & VMCB_AVIC_APIC_BAR_MASK;
346 mark_dirty(svm->vmcb, VMCB_AVIC);
347 }
348
349 static inline bool avic_vcpu_is_running(struct kvm_vcpu *vcpu)
350 {
351 struct vcpu_svm *svm = to_svm(vcpu);
352 u64 *entry = svm->avic_physical_id_cache;
353
354 if (!entry)
355 return false;
356
357 return (READ_ONCE(*entry) & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
358 }
359
360 static void recalc_intercepts(struct vcpu_svm *svm)
361 {
362 struct vmcb_control_area *c, *h;
363 struct nested_state *g;
364
365 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
366
367 if (!is_guest_mode(&svm->vcpu))
368 return;
369
370 c = &svm->vmcb->control;
371 h = &svm->nested.hsave->control;
372 g = &svm->nested;
373
374 c->intercept_cr = h->intercept_cr | g->intercept_cr;
375 c->intercept_dr = h->intercept_dr | g->intercept_dr;
376 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
377 c->intercept = h->intercept | g->intercept;
378 }
379
380 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
381 {
382 if (is_guest_mode(&svm->vcpu))
383 return svm->nested.hsave;
384 else
385 return svm->vmcb;
386 }
387
388 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
389 {
390 struct vmcb *vmcb = get_host_vmcb(svm);
391
392 vmcb->control.intercept_cr |= (1U << bit);
393
394 recalc_intercepts(svm);
395 }
396
397 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
398 {
399 struct vmcb *vmcb = get_host_vmcb(svm);
400
401 vmcb->control.intercept_cr &= ~(1U << bit);
402
403 recalc_intercepts(svm);
404 }
405
406 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
407 {
408 struct vmcb *vmcb = get_host_vmcb(svm);
409
410 return vmcb->control.intercept_cr & (1U << bit);
411 }
412
413 static inline void set_dr_intercepts(struct vcpu_svm *svm)
414 {
415 struct vmcb *vmcb = get_host_vmcb(svm);
416
417 vmcb->control.intercept_dr = (1 << INTERCEPT_DR0_READ)
418 | (1 << INTERCEPT_DR1_READ)
419 | (1 << INTERCEPT_DR2_READ)
420 | (1 << INTERCEPT_DR3_READ)
421 | (1 << INTERCEPT_DR4_READ)
422 | (1 << INTERCEPT_DR5_READ)
423 | (1 << INTERCEPT_DR6_READ)
424 | (1 << INTERCEPT_DR7_READ)
425 | (1 << INTERCEPT_DR0_WRITE)
426 | (1 << INTERCEPT_DR1_WRITE)
427 | (1 << INTERCEPT_DR2_WRITE)
428 | (1 << INTERCEPT_DR3_WRITE)
429 | (1 << INTERCEPT_DR4_WRITE)
430 | (1 << INTERCEPT_DR5_WRITE)
431 | (1 << INTERCEPT_DR6_WRITE)
432 | (1 << INTERCEPT_DR7_WRITE);
433
434 recalc_intercepts(svm);
435 }
436
437 static inline void clr_dr_intercepts(struct vcpu_svm *svm)
438 {
439 struct vmcb *vmcb = get_host_vmcb(svm);
440
441 vmcb->control.intercept_dr = 0;
442
443 recalc_intercepts(svm);
444 }
445
446 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
447 {
448 struct vmcb *vmcb = get_host_vmcb(svm);
449
450 vmcb->control.intercept_exceptions |= (1U << bit);
451
452 recalc_intercepts(svm);
453 }
454
455 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
456 {
457 struct vmcb *vmcb = get_host_vmcb(svm);
458
459 vmcb->control.intercept_exceptions &= ~(1U << bit);
460
461 recalc_intercepts(svm);
462 }
463
464 static inline void set_intercept(struct vcpu_svm *svm, int bit)
465 {
466 struct vmcb *vmcb = get_host_vmcb(svm);
467
468 vmcb->control.intercept |= (1ULL << bit);
469
470 recalc_intercepts(svm);
471 }
472
473 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
474 {
475 struct vmcb *vmcb = get_host_vmcb(svm);
476
477 vmcb->control.intercept &= ~(1ULL << bit);
478
479 recalc_intercepts(svm);
480 }
481
482 static inline bool vgif_enabled(struct vcpu_svm *svm)
483 {
484 return !!(svm->vmcb->control.int_ctl & V_GIF_ENABLE_MASK);
485 }
486
487 static inline void enable_gif(struct vcpu_svm *svm)
488 {
489 if (vgif_enabled(svm))
490 svm->vmcb->control.int_ctl |= V_GIF_MASK;
491 else
492 svm->vcpu.arch.hflags |= HF_GIF_MASK;
493 }
494
495 static inline void disable_gif(struct vcpu_svm *svm)
496 {
497 if (vgif_enabled(svm))
498 svm->vmcb->control.int_ctl &= ~V_GIF_MASK;
499 else
500 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
501 }
502
503 static inline bool gif_set(struct vcpu_svm *svm)
504 {
505 if (vgif_enabled(svm))
506 return !!(svm->vmcb->control.int_ctl & V_GIF_MASK);
507 else
508 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
509 }
510
511 static unsigned long iopm_base;
512
513 struct kvm_ldttss_desc {
514 u16 limit0;
515 u16 base0;
516 unsigned base1:8, type:5, dpl:2, p:1;
517 unsigned limit1:4, zero0:3, g:1, base2:8;
518 u32 base3;
519 u32 zero1;
520 } __attribute__((packed));
521
522 struct svm_cpu_data {
523 int cpu;
524
525 u64 asid_generation;
526 u32 max_asid;
527 u32 next_asid;
528 struct kvm_ldttss_desc *tss_desc;
529
530 struct page *save_area;
531 };
532
533 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
534
535 struct svm_init_data {
536 int cpu;
537 int r;
538 };
539
540 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
541
542 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
543 #define MSRS_RANGE_SIZE 2048
544 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
545
546 static u32 svm_msrpm_offset(u32 msr)
547 {
548 u32 offset;
549 int i;
550
551 for (i = 0; i < NUM_MSR_MAPS; i++) {
552 if (msr < msrpm_ranges[i] ||
553 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
554 continue;
555
556 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
557 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
558
559 /* Now we have the u8 offset - but need the u32 offset */
560 return offset / 4;
561 }
562
563 /* MSR not in any range */
564 return MSR_INVALID;
565 }
566
567 #define MAX_INST_SIZE 15
568
569 static inline void clgi(void)
570 {
571 asm volatile (__ex(SVM_CLGI));
572 }
573
574 static inline void stgi(void)
575 {
576 asm volatile (__ex(SVM_STGI));
577 }
578
579 static inline void invlpga(unsigned long addr, u32 asid)
580 {
581 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
582 }
583
584 static int get_npt_level(struct kvm_vcpu *vcpu)
585 {
586 #ifdef CONFIG_X86_64
587 return PT64_ROOT_4LEVEL;
588 #else
589 return PT32E_ROOT_LEVEL;
590 #endif
591 }
592
593 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
594 {
595 vcpu->arch.efer = efer;
596 if (!npt_enabled && !(efer & EFER_LMA))
597 efer &= ~EFER_LME;
598
599 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
600 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
601 }
602
603 static int is_external_interrupt(u32 info)
604 {
605 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
606 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
607 }
608
609 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
610 {
611 struct vcpu_svm *svm = to_svm(vcpu);
612 u32 ret = 0;
613
614 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
615 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
616 return ret;
617 }
618
619 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
620 {
621 struct vcpu_svm *svm = to_svm(vcpu);
622
623 if (mask == 0)
624 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
625 else
626 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
627
628 }
629
630 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
631 {
632 struct vcpu_svm *svm = to_svm(vcpu);
633
634 if (svm->vmcb->control.next_rip != 0) {
635 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
636 svm->next_rip = svm->vmcb->control.next_rip;
637 }
638
639 if (!svm->next_rip) {
640 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
641 EMULATE_DONE)
642 printk(KERN_DEBUG "%s: NOP\n", __func__);
643 return;
644 }
645 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
646 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
647 __func__, kvm_rip_read(vcpu), svm->next_rip);
648
649 kvm_rip_write(vcpu, svm->next_rip);
650 svm_set_interrupt_shadow(vcpu, 0);
651 }
652
653 static void svm_queue_exception(struct kvm_vcpu *vcpu)
654 {
655 struct vcpu_svm *svm = to_svm(vcpu);
656 unsigned nr = vcpu->arch.exception.nr;
657 bool has_error_code = vcpu->arch.exception.has_error_code;
658 bool reinject = vcpu->arch.exception.injected;
659 u32 error_code = vcpu->arch.exception.error_code;
660
661 /*
662 * If we are within a nested VM we'd better #VMEXIT and let the guest
663 * handle the exception
664 */
665 if (!reinject &&
666 nested_svm_check_exception(svm, nr, has_error_code, error_code))
667 return;
668
669 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
670 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
671
672 /*
673 * For guest debugging where we have to reinject #BP if some
674 * INT3 is guest-owned:
675 * Emulate nRIP by moving RIP forward. Will fail if injection
676 * raises a fault that is not intercepted. Still better than
677 * failing in all cases.
678 */
679 skip_emulated_instruction(&svm->vcpu);
680 rip = kvm_rip_read(&svm->vcpu);
681 svm->int3_rip = rip + svm->vmcb->save.cs.base;
682 svm->int3_injected = rip - old_rip;
683 }
684
685 svm->vmcb->control.event_inj = nr
686 | SVM_EVTINJ_VALID
687 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
688 | SVM_EVTINJ_TYPE_EXEPT;
689 svm->vmcb->control.event_inj_err = error_code;
690 }
691
692 static void svm_init_erratum_383(void)
693 {
694 u32 low, high;
695 int err;
696 u64 val;
697
698 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
699 return;
700
701 /* Use _safe variants to not break nested virtualization */
702 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
703 if (err)
704 return;
705
706 val |= (1ULL << 47);
707
708 low = lower_32_bits(val);
709 high = upper_32_bits(val);
710
711 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
712
713 erratum_383_found = true;
714 }
715
716 static void svm_init_osvw(struct kvm_vcpu *vcpu)
717 {
718 /*
719 * Guests should see errata 400 and 415 as fixed (assuming that
720 * HLT and IO instructions are intercepted).
721 */
722 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
723 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
724
725 /*
726 * By increasing VCPU's osvw.length to 3 we are telling the guest that
727 * all osvw.status bits inside that length, including bit 0 (which is
728 * reserved for erratum 298), are valid. However, if host processor's
729 * osvw_len is 0 then osvw_status[0] carries no information. We need to
730 * be conservative here and therefore we tell the guest that erratum 298
731 * is present (because we really don't know).
732 */
733 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
734 vcpu->arch.osvw.status |= 1;
735 }
736
737 static int has_svm(void)
738 {
739 const char *msg;
740
741 if (!cpu_has_svm(&msg)) {
742 printk(KERN_INFO "has_svm: %s\n", msg);
743 return 0;
744 }
745
746 return 1;
747 }
748
749 static void svm_hardware_disable(void)
750 {
751 /* Make sure we clean up behind us */
752 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
753 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
754
755 cpu_svm_disable();
756
757 amd_pmu_disable_virt();
758 }
759
760 static int svm_hardware_enable(void)
761 {
762
763 struct svm_cpu_data *sd;
764 uint64_t efer;
765 struct desc_struct *gdt;
766 int me = raw_smp_processor_id();
767
768 rdmsrl(MSR_EFER, efer);
769 if (efer & EFER_SVME)
770 return -EBUSY;
771
772 if (!has_svm()) {
773 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
774 return -EINVAL;
775 }
776 sd = per_cpu(svm_data, me);
777 if (!sd) {
778 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
779 return -EINVAL;
780 }
781
782 sd->asid_generation = 1;
783 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
784 sd->next_asid = sd->max_asid + 1;
785
786 gdt = get_current_gdt_rw();
787 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
788
789 wrmsrl(MSR_EFER, efer | EFER_SVME);
790
791 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
792
793 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
794 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
795 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
796 }
797
798
799 /*
800 * Get OSVW bits.
801 *
802 * Note that it is possible to have a system with mixed processor
803 * revisions and therefore different OSVW bits. If bits are not the same
804 * on different processors then choose the worst case (i.e. if erratum
805 * is present on one processor and not on another then assume that the
806 * erratum is present everywhere).
807 */
808 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
809 uint64_t len, status = 0;
810 int err;
811
812 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
813 if (!err)
814 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
815 &err);
816
817 if (err)
818 osvw_status = osvw_len = 0;
819 else {
820 if (len < osvw_len)
821 osvw_len = len;
822 osvw_status |= status;
823 osvw_status &= (1ULL << osvw_len) - 1;
824 }
825 } else
826 osvw_status = osvw_len = 0;
827
828 svm_init_erratum_383();
829
830 amd_pmu_enable_virt();
831
832 return 0;
833 }
834
835 static void svm_cpu_uninit(int cpu)
836 {
837 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
838
839 if (!sd)
840 return;
841
842 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
843 __free_page(sd->save_area);
844 kfree(sd);
845 }
846
847 static int svm_cpu_init(int cpu)
848 {
849 struct svm_cpu_data *sd;
850 int r;
851
852 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
853 if (!sd)
854 return -ENOMEM;
855 sd->cpu = cpu;
856 sd->save_area = alloc_page(GFP_KERNEL);
857 r = -ENOMEM;
858 if (!sd->save_area)
859 goto err_1;
860
861 per_cpu(svm_data, cpu) = sd;
862
863 return 0;
864
865 err_1:
866 kfree(sd);
867 return r;
868
869 }
870
871 static bool valid_msr_intercept(u32 index)
872 {
873 int i;
874
875 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
876 if (direct_access_msrs[i].index == index)
877 return true;
878
879 return false;
880 }
881
882 static void set_msr_interception(u32 *msrpm, unsigned msr,
883 int read, int write)
884 {
885 u8 bit_read, bit_write;
886 unsigned long tmp;
887 u32 offset;
888
889 /*
890 * If this warning triggers extend the direct_access_msrs list at the
891 * beginning of the file
892 */
893 WARN_ON(!valid_msr_intercept(msr));
894
895 offset = svm_msrpm_offset(msr);
896 bit_read = 2 * (msr & 0x0f);
897 bit_write = 2 * (msr & 0x0f) + 1;
898 tmp = msrpm[offset];
899
900 BUG_ON(offset == MSR_INVALID);
901
902 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
903 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
904
905 msrpm[offset] = tmp;
906 }
907
908 static void svm_vcpu_init_msrpm(u32 *msrpm)
909 {
910 int i;
911
912 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
913
914 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
915 if (!direct_access_msrs[i].always)
916 continue;
917
918 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
919 }
920 }
921
922 static void add_msr_offset(u32 offset)
923 {
924 int i;
925
926 for (i = 0; i < MSRPM_OFFSETS; ++i) {
927
928 /* Offset already in list? */
929 if (msrpm_offsets[i] == offset)
930 return;
931
932 /* Slot used by another offset? */
933 if (msrpm_offsets[i] != MSR_INVALID)
934 continue;
935
936 /* Add offset to list */
937 msrpm_offsets[i] = offset;
938
939 return;
940 }
941
942 /*
943 * If this BUG triggers the msrpm_offsets table has an overflow. Just
944 * increase MSRPM_OFFSETS in this case.
945 */
946 BUG();
947 }
948
949 static void init_msrpm_offsets(void)
950 {
951 int i;
952
953 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
954
955 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
956 u32 offset;
957
958 offset = svm_msrpm_offset(direct_access_msrs[i].index);
959 BUG_ON(offset == MSR_INVALID);
960
961 add_msr_offset(offset);
962 }
963 }
964
965 static void svm_enable_lbrv(struct vcpu_svm *svm)
966 {
967 u32 *msrpm = svm->msrpm;
968
969 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
970 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
971 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
972 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
973 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
974 }
975
976 static void svm_disable_lbrv(struct vcpu_svm *svm)
977 {
978 u32 *msrpm = svm->msrpm;
979
980 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
981 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
982 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
983 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
984 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
985 }
986
987 static void disable_nmi_singlestep(struct vcpu_svm *svm)
988 {
989 svm->nmi_singlestep = false;
990
991 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
992 /* Clear our flags if they were not set by the guest */
993 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
994 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
995 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
996 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
997 }
998 }
999
1000 /* Note:
1001 * This hash table is used to map VM_ID to a struct kvm_arch,
1002 * when handling AMD IOMMU GALOG notification to schedule in
1003 * a particular vCPU.
1004 */
1005 #define SVM_VM_DATA_HASH_BITS 8
1006 static DEFINE_HASHTABLE(svm_vm_data_hash, SVM_VM_DATA_HASH_BITS);
1007 static u32 next_vm_id = 0;
1008 static bool next_vm_id_wrapped = 0;
1009 static DEFINE_SPINLOCK(svm_vm_data_hash_lock);
1010
1011 /* Note:
1012 * This function is called from IOMMU driver to notify
1013 * SVM to schedule in a particular vCPU of a particular VM.
1014 */
1015 static int avic_ga_log_notifier(u32 ga_tag)
1016 {
1017 unsigned long flags;
1018 struct kvm_arch *ka = NULL;
1019 struct kvm_vcpu *vcpu = NULL;
1020 u32 vm_id = AVIC_GATAG_TO_VMID(ga_tag);
1021 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(ga_tag);
1022
1023 pr_debug("SVM: %s: vm_id=%#x, vcpu_id=%#x\n", __func__, vm_id, vcpu_id);
1024
1025 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1026 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1027 struct kvm *kvm = container_of(ka, struct kvm, arch);
1028 struct kvm_arch *vm_data = &kvm->arch;
1029
1030 if (vm_data->avic_vm_id != vm_id)
1031 continue;
1032 vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
1033 break;
1034 }
1035 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1036
1037 if (!vcpu)
1038 return 0;
1039
1040 /* Note:
1041 * At this point, the IOMMU should have already set the pending
1042 * bit in the vAPIC backing page. So, we just need to schedule
1043 * in the vcpu.
1044 */
1045 if (vcpu->mode == OUTSIDE_GUEST_MODE)
1046 kvm_vcpu_wake_up(vcpu);
1047
1048 return 0;
1049 }
1050
1051 static __init int svm_hardware_setup(void)
1052 {
1053 int cpu;
1054 struct page *iopm_pages;
1055 void *iopm_va;
1056 int r;
1057
1058 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
1059
1060 if (!iopm_pages)
1061 return -ENOMEM;
1062
1063 iopm_va = page_address(iopm_pages);
1064 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
1065 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
1066
1067 init_msrpm_offsets();
1068
1069 if (boot_cpu_has(X86_FEATURE_NX))
1070 kvm_enable_efer_bits(EFER_NX);
1071
1072 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
1073 kvm_enable_efer_bits(EFER_FFXSR);
1074
1075 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1076 kvm_has_tsc_control = true;
1077 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
1078 kvm_tsc_scaling_ratio_frac_bits = 32;
1079 }
1080
1081 if (nested) {
1082 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1083 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1084 }
1085
1086 for_each_possible_cpu(cpu) {
1087 r = svm_cpu_init(cpu);
1088 if (r)
1089 goto err;
1090 }
1091
1092 if (!boot_cpu_has(X86_FEATURE_NPT))
1093 npt_enabled = false;
1094
1095 if (npt_enabled && !npt) {
1096 printk(KERN_INFO "kvm: Nested Paging disabled\n");
1097 npt_enabled = false;
1098 }
1099
1100 if (npt_enabled) {
1101 printk(KERN_INFO "kvm: Nested Paging enabled\n");
1102 kvm_enable_tdp();
1103 } else
1104 kvm_disable_tdp();
1105
1106 if (avic) {
1107 if (!npt_enabled ||
1108 !boot_cpu_has(X86_FEATURE_AVIC) ||
1109 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1110 avic = false;
1111 } else {
1112 pr_info("AVIC enabled\n");
1113
1114 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1115 }
1116 }
1117
1118 if (vls) {
1119 if (!npt_enabled ||
1120 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1121 !IS_ENABLED(CONFIG_X86_64)) {
1122 vls = false;
1123 } else {
1124 pr_info("Virtual VMLOAD VMSAVE supported\n");
1125 }
1126 }
1127
1128 if (vgif) {
1129 if (!boot_cpu_has(X86_FEATURE_VGIF))
1130 vgif = false;
1131 else
1132 pr_info("Virtual GIF supported\n");
1133 }
1134
1135 return 0;
1136
1137 err:
1138 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
1139 iopm_base = 0;
1140 return r;
1141 }
1142
1143 static __exit void svm_hardware_unsetup(void)
1144 {
1145 int cpu;
1146
1147 for_each_possible_cpu(cpu)
1148 svm_cpu_uninit(cpu);
1149
1150 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
1151 iopm_base = 0;
1152 }
1153
1154 static void init_seg(struct vmcb_seg *seg)
1155 {
1156 seg->selector = 0;
1157 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1158 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1159 seg->limit = 0xffff;
1160 seg->base = 0;
1161 }
1162
1163 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1164 {
1165 seg->selector = 0;
1166 seg->attrib = SVM_SELECTOR_P_MASK | type;
1167 seg->limit = 0xffff;
1168 seg->base = 0;
1169 }
1170
1171 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1172 {
1173 struct vcpu_svm *svm = to_svm(vcpu);
1174 u64 g_tsc_offset = 0;
1175
1176 if (is_guest_mode(vcpu)) {
1177 g_tsc_offset = svm->vmcb->control.tsc_offset -
1178 svm->nested.hsave->control.tsc_offset;
1179 svm->nested.hsave->control.tsc_offset = offset;
1180 } else
1181 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1182 svm->vmcb->control.tsc_offset,
1183 offset);
1184
1185 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1186
1187 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1188 }
1189
1190 static void avic_init_vmcb(struct vcpu_svm *svm)
1191 {
1192 struct vmcb *vmcb = svm->vmcb;
1193 struct kvm_arch *vm_data = &svm->vcpu.kvm->arch;
1194 phys_addr_t bpa = __sme_set(page_to_phys(svm->avic_backing_page));
1195 phys_addr_t lpa = __sme_set(page_to_phys(vm_data->avic_logical_id_table_page));
1196 phys_addr_t ppa = __sme_set(page_to_phys(vm_data->avic_physical_id_table_page));
1197
1198 vmcb->control.avic_backing_page = bpa & AVIC_HPA_MASK;
1199 vmcb->control.avic_logical_id = lpa & AVIC_HPA_MASK;
1200 vmcb->control.avic_physical_id = ppa & AVIC_HPA_MASK;
1201 vmcb->control.avic_physical_id |= AVIC_MAX_PHYSICAL_ID_COUNT;
1202 vmcb->control.int_ctl |= AVIC_ENABLE_MASK;
1203 svm->vcpu.arch.apicv_active = true;
1204 }
1205
1206 static void init_vmcb(struct vcpu_svm *svm)
1207 {
1208 struct vmcb_control_area *control = &svm->vmcb->control;
1209 struct vmcb_save_area *save = &svm->vmcb->save;
1210
1211 svm->vcpu.arch.hflags = 0;
1212
1213 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1214 set_cr_intercept(svm, INTERCEPT_CR3_READ);
1215 set_cr_intercept(svm, INTERCEPT_CR4_READ);
1216 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1217 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1218 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1219 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1220 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1221
1222 set_dr_intercepts(svm);
1223
1224 set_exception_intercept(svm, PF_VECTOR);
1225 set_exception_intercept(svm, UD_VECTOR);
1226 set_exception_intercept(svm, MC_VECTOR);
1227 set_exception_intercept(svm, AC_VECTOR);
1228 set_exception_intercept(svm, DB_VECTOR);
1229
1230 set_intercept(svm, INTERCEPT_INTR);
1231 set_intercept(svm, INTERCEPT_NMI);
1232 set_intercept(svm, INTERCEPT_SMI);
1233 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1234 set_intercept(svm, INTERCEPT_RDPMC);
1235 set_intercept(svm, INTERCEPT_CPUID);
1236 set_intercept(svm, INTERCEPT_INVD);
1237 set_intercept(svm, INTERCEPT_HLT);
1238 set_intercept(svm, INTERCEPT_INVLPG);
1239 set_intercept(svm, INTERCEPT_INVLPGA);
1240 set_intercept(svm, INTERCEPT_IOIO_PROT);
1241 set_intercept(svm, INTERCEPT_MSR_PROT);
1242 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1243 set_intercept(svm, INTERCEPT_SHUTDOWN);
1244 set_intercept(svm, INTERCEPT_VMRUN);
1245 set_intercept(svm, INTERCEPT_VMMCALL);
1246 set_intercept(svm, INTERCEPT_VMLOAD);
1247 set_intercept(svm, INTERCEPT_VMSAVE);
1248 set_intercept(svm, INTERCEPT_STGI);
1249 set_intercept(svm, INTERCEPT_CLGI);
1250 set_intercept(svm, INTERCEPT_SKINIT);
1251 set_intercept(svm, INTERCEPT_WBINVD);
1252 set_intercept(svm, INTERCEPT_XSETBV);
1253
1254 if (!kvm_mwait_in_guest()) {
1255 set_intercept(svm, INTERCEPT_MONITOR);
1256 set_intercept(svm, INTERCEPT_MWAIT);
1257 }
1258
1259 control->iopm_base_pa = __sme_set(iopm_base);
1260 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1261 control->int_ctl = V_INTR_MASKING_MASK;
1262
1263 init_seg(&save->es);
1264 init_seg(&save->ss);
1265 init_seg(&save->ds);
1266 init_seg(&save->fs);
1267 init_seg(&save->gs);
1268
1269 save->cs.selector = 0xf000;
1270 save->cs.base = 0xffff0000;
1271 /* Executable/Readable Code Segment */
1272 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1273 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1274 save->cs.limit = 0xffff;
1275
1276 save->gdtr.limit = 0xffff;
1277 save->idtr.limit = 0xffff;
1278
1279 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1280 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1281
1282 svm_set_efer(&svm->vcpu, 0);
1283 save->dr6 = 0xffff0ff0;
1284 kvm_set_rflags(&svm->vcpu, 2);
1285 save->rip = 0x0000fff0;
1286 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1287
1288 /*
1289 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1290 * It also updates the guest-visible cr0 value.
1291 */
1292 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1293 kvm_mmu_reset_context(&svm->vcpu);
1294
1295 save->cr4 = X86_CR4_PAE;
1296 /* rdx = ?? */
1297
1298 if (npt_enabled) {
1299 /* Setup VMCB for Nested Paging */
1300 control->nested_ctl = 1;
1301 clr_intercept(svm, INTERCEPT_INVLPG);
1302 clr_exception_intercept(svm, PF_VECTOR);
1303 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1304 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1305 save->g_pat = svm->vcpu.arch.pat;
1306 save->cr3 = 0;
1307 save->cr4 = 0;
1308 }
1309 svm->asid_generation = 0;
1310
1311 svm->nested.vmcb = 0;
1312 svm->vcpu.arch.hflags = 0;
1313
1314 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1315 control->pause_filter_count = 3000;
1316 set_intercept(svm, INTERCEPT_PAUSE);
1317 }
1318
1319 if (avic)
1320 avic_init_vmcb(svm);
1321
1322 /*
1323 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1324 * in VMCB and clear intercepts to avoid #VMEXIT.
1325 */
1326 if (vls) {
1327 clr_intercept(svm, INTERCEPT_VMLOAD);
1328 clr_intercept(svm, INTERCEPT_VMSAVE);
1329 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1330 }
1331
1332 if (vgif) {
1333 clr_intercept(svm, INTERCEPT_STGI);
1334 clr_intercept(svm, INTERCEPT_CLGI);
1335 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1336 }
1337
1338 mark_all_dirty(svm->vmcb);
1339
1340 enable_gif(svm);
1341
1342 }
1343
1344 static u64 *avic_get_physical_id_entry(struct kvm_vcpu *vcpu,
1345 unsigned int index)
1346 {
1347 u64 *avic_physical_id_table;
1348 struct kvm_arch *vm_data = &vcpu->kvm->arch;
1349
1350 if (index >= AVIC_MAX_PHYSICAL_ID_COUNT)
1351 return NULL;
1352
1353 avic_physical_id_table = page_address(vm_data->avic_physical_id_table_page);
1354
1355 return &avic_physical_id_table[index];
1356 }
1357
1358 /**
1359 * Note:
1360 * AVIC hardware walks the nested page table to check permissions,
1361 * but does not use the SPA address specified in the leaf page
1362 * table entry since it uses address in the AVIC_BACKING_PAGE pointer
1363 * field of the VMCB. Therefore, we set up the
1364 * APIC_ACCESS_PAGE_PRIVATE_MEMSLOT (4KB) here.
1365 */
1366 static int avic_init_access_page(struct kvm_vcpu *vcpu)
1367 {
1368 struct kvm *kvm = vcpu->kvm;
1369 int ret;
1370
1371 if (kvm->arch.apic_access_page_done)
1372 return 0;
1373
1374 ret = x86_set_memory_region(kvm,
1375 APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
1376 APIC_DEFAULT_PHYS_BASE,
1377 PAGE_SIZE);
1378 if (ret)
1379 return ret;
1380
1381 kvm->arch.apic_access_page_done = true;
1382 return 0;
1383 }
1384
1385 static int avic_init_backing_page(struct kvm_vcpu *vcpu)
1386 {
1387 int ret;
1388 u64 *entry, new_entry;
1389 int id = vcpu->vcpu_id;
1390 struct vcpu_svm *svm = to_svm(vcpu);
1391
1392 ret = avic_init_access_page(vcpu);
1393 if (ret)
1394 return ret;
1395
1396 if (id >= AVIC_MAX_PHYSICAL_ID_COUNT)
1397 return -EINVAL;
1398
1399 if (!svm->vcpu.arch.apic->regs)
1400 return -EINVAL;
1401
1402 svm->avic_backing_page = virt_to_page(svm->vcpu.arch.apic->regs);
1403
1404 /* Setting AVIC backing page address in the phy APIC ID table */
1405 entry = avic_get_physical_id_entry(vcpu, id);
1406 if (!entry)
1407 return -EINVAL;
1408
1409 new_entry = READ_ONCE(*entry);
1410 new_entry = __sme_set((page_to_phys(svm->avic_backing_page) &
1411 AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK) |
1412 AVIC_PHYSICAL_ID_ENTRY_VALID_MASK);
1413 WRITE_ONCE(*entry, new_entry);
1414
1415 svm->avic_physical_id_cache = entry;
1416
1417 return 0;
1418 }
1419
1420 static void avic_vm_destroy(struct kvm *kvm)
1421 {
1422 unsigned long flags;
1423 struct kvm_arch *vm_data = &kvm->arch;
1424
1425 if (!avic)
1426 return;
1427
1428 if (vm_data->avic_logical_id_table_page)
1429 __free_page(vm_data->avic_logical_id_table_page);
1430 if (vm_data->avic_physical_id_table_page)
1431 __free_page(vm_data->avic_physical_id_table_page);
1432
1433 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1434 hash_del(&vm_data->hnode);
1435 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1436 }
1437
1438 static int avic_vm_init(struct kvm *kvm)
1439 {
1440 unsigned long flags;
1441 int err = -ENOMEM;
1442 struct kvm_arch *vm_data = &kvm->arch;
1443 struct page *p_page;
1444 struct page *l_page;
1445 struct kvm_arch *ka;
1446 u32 vm_id;
1447
1448 if (!avic)
1449 return 0;
1450
1451 /* Allocating physical APIC ID table (4KB) */
1452 p_page = alloc_page(GFP_KERNEL);
1453 if (!p_page)
1454 goto free_avic;
1455
1456 vm_data->avic_physical_id_table_page = p_page;
1457 clear_page(page_address(p_page));
1458
1459 /* Allocating logical APIC ID table (4KB) */
1460 l_page = alloc_page(GFP_KERNEL);
1461 if (!l_page)
1462 goto free_avic;
1463
1464 vm_data->avic_logical_id_table_page = l_page;
1465 clear_page(page_address(l_page));
1466
1467 spin_lock_irqsave(&svm_vm_data_hash_lock, flags);
1468 again:
1469 vm_id = next_vm_id = (next_vm_id + 1) & AVIC_VM_ID_MASK;
1470 if (vm_id == 0) { /* id is 1-based, zero is not okay */
1471 next_vm_id_wrapped = 1;
1472 goto again;
1473 }
1474 /* Is it still in use? Only possible if wrapped at least once */
1475 if (next_vm_id_wrapped) {
1476 hash_for_each_possible(svm_vm_data_hash, ka, hnode, vm_id) {
1477 struct kvm *k2 = container_of(ka, struct kvm, arch);
1478 struct kvm_arch *vd2 = &k2->arch;
1479 if (vd2->avic_vm_id == vm_id)
1480 goto again;
1481 }
1482 }
1483 vm_data->avic_vm_id = vm_id;
1484 hash_add(svm_vm_data_hash, &vm_data->hnode, vm_data->avic_vm_id);
1485 spin_unlock_irqrestore(&svm_vm_data_hash_lock, flags);
1486
1487 return 0;
1488
1489 free_avic:
1490 avic_vm_destroy(kvm);
1491 return err;
1492 }
1493
1494 static inline int
1495 avic_update_iommu_vcpu_affinity(struct kvm_vcpu *vcpu, int cpu, bool r)
1496 {
1497 int ret = 0;
1498 unsigned long flags;
1499 struct amd_svm_iommu_ir *ir;
1500 struct vcpu_svm *svm = to_svm(vcpu);
1501
1502 if (!kvm_arch_has_assigned_device(vcpu->kvm))
1503 return 0;
1504
1505 /*
1506 * Here, we go through the per-vcpu ir_list to update all existing
1507 * interrupt remapping table entry targeting this vcpu.
1508 */
1509 spin_lock_irqsave(&svm->ir_list_lock, flags);
1510
1511 if (list_empty(&svm->ir_list))
1512 goto out;
1513
1514 list_for_each_entry(ir, &svm->ir_list, node) {
1515 ret = amd_iommu_update_ga(cpu, r, ir->data);
1516 if (ret)
1517 break;
1518 }
1519 out:
1520 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
1521 return ret;
1522 }
1523
1524 static void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1525 {
1526 u64 entry;
1527 /* ID = 0xff (broadcast), ID > 0xff (reserved) */
1528 int h_physical_id = kvm_cpu_get_apicid(cpu);
1529 struct vcpu_svm *svm = to_svm(vcpu);
1530
1531 if (!kvm_vcpu_apicv_active(vcpu))
1532 return;
1533
1534 if (WARN_ON(h_physical_id >= AVIC_MAX_PHYSICAL_ID_COUNT))
1535 return;
1536
1537 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1538 WARN_ON(entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK);
1539
1540 entry &= ~AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK;
1541 entry |= (h_physical_id & AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK);
1542
1543 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1544 if (svm->avic_is_running)
1545 entry |= AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1546
1547 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1548 avic_update_iommu_vcpu_affinity(vcpu, h_physical_id,
1549 svm->avic_is_running);
1550 }
1551
1552 static void avic_vcpu_put(struct kvm_vcpu *vcpu)
1553 {
1554 u64 entry;
1555 struct vcpu_svm *svm = to_svm(vcpu);
1556
1557 if (!kvm_vcpu_apicv_active(vcpu))
1558 return;
1559
1560 entry = READ_ONCE(*(svm->avic_physical_id_cache));
1561 if (entry & AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK)
1562 avic_update_iommu_vcpu_affinity(vcpu, -1, 0);
1563
1564 entry &= ~AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK;
1565 WRITE_ONCE(*(svm->avic_physical_id_cache), entry);
1566 }
1567
1568 /**
1569 * This function is called during VCPU halt/unhalt.
1570 */
1571 static void avic_set_running(struct kvm_vcpu *vcpu, bool is_run)
1572 {
1573 struct vcpu_svm *svm = to_svm(vcpu);
1574
1575 svm->avic_is_running = is_run;
1576 if (is_run)
1577 avic_vcpu_load(vcpu, vcpu->cpu);
1578 else
1579 avic_vcpu_put(vcpu);
1580 }
1581
1582 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1583 {
1584 struct vcpu_svm *svm = to_svm(vcpu);
1585 u32 dummy;
1586 u32 eax = 1;
1587
1588 if (!init_event) {
1589 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1590 MSR_IA32_APICBASE_ENABLE;
1591 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1592 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1593 }
1594 init_vmcb(svm);
1595
1596 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, true);
1597 kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
1598
1599 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1600 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1601 }
1602
1603 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1604 {
1605 struct vcpu_svm *svm;
1606 struct page *page;
1607 struct page *msrpm_pages;
1608 struct page *hsave_page;
1609 struct page *nested_msrpm_pages;
1610 int err;
1611
1612 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1613 if (!svm) {
1614 err = -ENOMEM;
1615 goto out;
1616 }
1617
1618 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1619 if (err)
1620 goto free_svm;
1621
1622 err = -ENOMEM;
1623 page = alloc_page(GFP_KERNEL);
1624 if (!page)
1625 goto uninit;
1626
1627 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1628 if (!msrpm_pages)
1629 goto free_page1;
1630
1631 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1632 if (!nested_msrpm_pages)
1633 goto free_page2;
1634
1635 hsave_page = alloc_page(GFP_KERNEL);
1636 if (!hsave_page)
1637 goto free_page3;
1638
1639 if (avic) {
1640 err = avic_init_backing_page(&svm->vcpu);
1641 if (err)
1642 goto free_page4;
1643
1644 INIT_LIST_HEAD(&svm->ir_list);
1645 spin_lock_init(&svm->ir_list_lock);
1646 }
1647
1648 /* We initialize this flag to true to make sure that the is_running
1649 * bit would be set the first time the vcpu is loaded.
1650 */
1651 svm->avic_is_running = true;
1652
1653 svm->nested.hsave = page_address(hsave_page);
1654
1655 svm->msrpm = page_address(msrpm_pages);
1656 svm_vcpu_init_msrpm(svm->msrpm);
1657
1658 svm->nested.msrpm = page_address(nested_msrpm_pages);
1659 svm_vcpu_init_msrpm(svm->nested.msrpm);
1660
1661 svm->vmcb = page_address(page);
1662 clear_page(svm->vmcb);
1663 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1664 svm->asid_generation = 0;
1665 init_vmcb(svm);
1666
1667 svm_init_osvw(&svm->vcpu);
1668
1669 return &svm->vcpu;
1670
1671 free_page4:
1672 __free_page(hsave_page);
1673 free_page3:
1674 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1675 free_page2:
1676 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1677 free_page1:
1678 __free_page(page);
1679 uninit:
1680 kvm_vcpu_uninit(&svm->vcpu);
1681 free_svm:
1682 kmem_cache_free(kvm_vcpu_cache, svm);
1683 out:
1684 return ERR_PTR(err);
1685 }
1686
1687 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1688 {
1689 struct vcpu_svm *svm = to_svm(vcpu);
1690
1691 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1692 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1693 __free_page(virt_to_page(svm->nested.hsave));
1694 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1695 kvm_vcpu_uninit(vcpu);
1696 kmem_cache_free(kvm_vcpu_cache, svm);
1697 }
1698
1699 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1700 {
1701 struct vcpu_svm *svm = to_svm(vcpu);
1702 int i;
1703
1704 if (unlikely(cpu != vcpu->cpu)) {
1705 svm->asid_generation = 0;
1706 mark_all_dirty(svm->vmcb);
1707 }
1708
1709 #ifdef CONFIG_X86_64
1710 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1711 #endif
1712 savesegment(fs, svm->host.fs);
1713 savesegment(gs, svm->host.gs);
1714 svm->host.ldt = kvm_read_ldt();
1715
1716 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1717 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1718
1719 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1720 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1721 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1722 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1723 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1724 }
1725 }
1726 /* This assumes that the kernel never uses MSR_TSC_AUX */
1727 if (static_cpu_has(X86_FEATURE_RDTSCP))
1728 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1729
1730 avic_vcpu_load(vcpu, cpu);
1731 }
1732
1733 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1734 {
1735 struct vcpu_svm *svm = to_svm(vcpu);
1736 int i;
1737
1738 avic_vcpu_put(vcpu);
1739
1740 ++vcpu->stat.host_state_reload;
1741 kvm_load_ldt(svm->host.ldt);
1742 #ifdef CONFIG_X86_64
1743 loadsegment(fs, svm->host.fs);
1744 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1745 load_gs_index(svm->host.gs);
1746 #else
1747 #ifdef CONFIG_X86_32_LAZY_GS
1748 loadsegment(gs, svm->host.gs);
1749 #endif
1750 #endif
1751 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1752 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1753 }
1754
1755 static void svm_vcpu_blocking(struct kvm_vcpu *vcpu)
1756 {
1757 avic_set_running(vcpu, false);
1758 }
1759
1760 static void svm_vcpu_unblocking(struct kvm_vcpu *vcpu)
1761 {
1762 avic_set_running(vcpu, true);
1763 }
1764
1765 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1766 {
1767 struct vcpu_svm *svm = to_svm(vcpu);
1768 unsigned long rflags = svm->vmcb->save.rflags;
1769
1770 if (svm->nmi_singlestep) {
1771 /* Hide our flags if they were not set by the guest */
1772 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1773 rflags &= ~X86_EFLAGS_TF;
1774 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1775 rflags &= ~X86_EFLAGS_RF;
1776 }
1777 return rflags;
1778 }
1779
1780 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1781 {
1782 if (to_svm(vcpu)->nmi_singlestep)
1783 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1784
1785 /*
1786 * Any change of EFLAGS.VM is accompanied by a reload of SS
1787 * (caused by either a task switch or an inter-privilege IRET),
1788 * so we do not need to update the CPL here.
1789 */
1790 to_svm(vcpu)->vmcb->save.rflags = rflags;
1791 }
1792
1793 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1794 {
1795 switch (reg) {
1796 case VCPU_EXREG_PDPTR:
1797 BUG_ON(!npt_enabled);
1798 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1799 break;
1800 default:
1801 BUG();
1802 }
1803 }
1804
1805 static void svm_set_vintr(struct vcpu_svm *svm)
1806 {
1807 set_intercept(svm, INTERCEPT_VINTR);
1808 }
1809
1810 static void svm_clear_vintr(struct vcpu_svm *svm)
1811 {
1812 clr_intercept(svm, INTERCEPT_VINTR);
1813 }
1814
1815 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1816 {
1817 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1818
1819 switch (seg) {
1820 case VCPU_SREG_CS: return &save->cs;
1821 case VCPU_SREG_DS: return &save->ds;
1822 case VCPU_SREG_ES: return &save->es;
1823 case VCPU_SREG_FS: return &save->fs;
1824 case VCPU_SREG_GS: return &save->gs;
1825 case VCPU_SREG_SS: return &save->ss;
1826 case VCPU_SREG_TR: return &save->tr;
1827 case VCPU_SREG_LDTR: return &save->ldtr;
1828 }
1829 BUG();
1830 return NULL;
1831 }
1832
1833 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1834 {
1835 struct vmcb_seg *s = svm_seg(vcpu, seg);
1836
1837 return s->base;
1838 }
1839
1840 static void svm_get_segment(struct kvm_vcpu *vcpu,
1841 struct kvm_segment *var, int seg)
1842 {
1843 struct vmcb_seg *s = svm_seg(vcpu, seg);
1844
1845 var->base = s->base;
1846 var->limit = s->limit;
1847 var->selector = s->selector;
1848 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1849 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1850 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1851 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1852 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1853 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1854 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1855
1856 /*
1857 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1858 * However, the SVM spec states that the G bit is not observed by the
1859 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1860 * So let's synthesize a legal G bit for all segments, this helps
1861 * running KVM nested. It also helps cross-vendor migration, because
1862 * Intel's vmentry has a check on the 'G' bit.
1863 */
1864 var->g = s->limit > 0xfffff;
1865
1866 /*
1867 * AMD's VMCB does not have an explicit unusable field, so emulate it
1868 * for cross vendor migration purposes by "not present"
1869 */
1870 var->unusable = !var->present;
1871
1872 switch (seg) {
1873 case VCPU_SREG_TR:
1874 /*
1875 * Work around a bug where the busy flag in the tr selector
1876 * isn't exposed
1877 */
1878 var->type |= 0x2;
1879 break;
1880 case VCPU_SREG_DS:
1881 case VCPU_SREG_ES:
1882 case VCPU_SREG_FS:
1883 case VCPU_SREG_GS:
1884 /*
1885 * The accessed bit must always be set in the segment
1886 * descriptor cache, although it can be cleared in the
1887 * descriptor, the cached bit always remains at 1. Since
1888 * Intel has a check on this, set it here to support
1889 * cross-vendor migration.
1890 */
1891 if (!var->unusable)
1892 var->type |= 0x1;
1893 break;
1894 case VCPU_SREG_SS:
1895 /*
1896 * On AMD CPUs sometimes the DB bit in the segment
1897 * descriptor is left as 1, although the whole segment has
1898 * been made unusable. Clear it here to pass an Intel VMX
1899 * entry check when cross vendor migrating.
1900 */
1901 if (var->unusable)
1902 var->db = 0;
1903 /* This is symmetric with svm_set_segment() */
1904 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1905 break;
1906 }
1907 }
1908
1909 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1910 {
1911 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1912
1913 return save->cpl;
1914 }
1915
1916 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1917 {
1918 struct vcpu_svm *svm = to_svm(vcpu);
1919
1920 dt->size = svm->vmcb->save.idtr.limit;
1921 dt->address = svm->vmcb->save.idtr.base;
1922 }
1923
1924 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1925 {
1926 struct vcpu_svm *svm = to_svm(vcpu);
1927
1928 svm->vmcb->save.idtr.limit = dt->size;
1929 svm->vmcb->save.idtr.base = dt->address ;
1930 mark_dirty(svm->vmcb, VMCB_DT);
1931 }
1932
1933 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1934 {
1935 struct vcpu_svm *svm = to_svm(vcpu);
1936
1937 dt->size = svm->vmcb->save.gdtr.limit;
1938 dt->address = svm->vmcb->save.gdtr.base;
1939 }
1940
1941 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1942 {
1943 struct vcpu_svm *svm = to_svm(vcpu);
1944
1945 svm->vmcb->save.gdtr.limit = dt->size;
1946 svm->vmcb->save.gdtr.base = dt->address ;
1947 mark_dirty(svm->vmcb, VMCB_DT);
1948 }
1949
1950 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1951 {
1952 }
1953
1954 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1955 {
1956 }
1957
1958 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1959 {
1960 }
1961
1962 static void update_cr0_intercept(struct vcpu_svm *svm)
1963 {
1964 ulong gcr0 = svm->vcpu.arch.cr0;
1965 u64 *hcr0 = &svm->vmcb->save.cr0;
1966
1967 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1968 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1969
1970 mark_dirty(svm->vmcb, VMCB_CR);
1971
1972 if (gcr0 == *hcr0) {
1973 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1974 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1975 } else {
1976 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1977 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1978 }
1979 }
1980
1981 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1982 {
1983 struct vcpu_svm *svm = to_svm(vcpu);
1984
1985 #ifdef CONFIG_X86_64
1986 if (vcpu->arch.efer & EFER_LME) {
1987 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1988 vcpu->arch.efer |= EFER_LMA;
1989 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1990 }
1991
1992 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1993 vcpu->arch.efer &= ~EFER_LMA;
1994 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1995 }
1996 }
1997 #endif
1998 vcpu->arch.cr0 = cr0;
1999
2000 if (!npt_enabled)
2001 cr0 |= X86_CR0_PG | X86_CR0_WP;
2002
2003 /*
2004 * re-enable caching here because the QEMU bios
2005 * does not do it - this results in some delay at
2006 * reboot
2007 */
2008 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
2009 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
2010 svm->vmcb->save.cr0 = cr0;
2011 mark_dirty(svm->vmcb, VMCB_CR);
2012 update_cr0_intercept(svm);
2013 }
2014
2015 static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2016 {
2017 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
2018 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
2019
2020 if (cr4 & X86_CR4_VMXE)
2021 return 1;
2022
2023 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
2024 svm_flush_tlb(vcpu);
2025
2026 vcpu->arch.cr4 = cr4;
2027 if (!npt_enabled)
2028 cr4 |= X86_CR4_PAE;
2029 cr4 |= host_cr4_mce;
2030 to_svm(vcpu)->vmcb->save.cr4 = cr4;
2031 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
2032 return 0;
2033 }
2034
2035 static void svm_set_segment(struct kvm_vcpu *vcpu,
2036 struct kvm_segment *var, int seg)
2037 {
2038 struct vcpu_svm *svm = to_svm(vcpu);
2039 struct vmcb_seg *s = svm_seg(vcpu, seg);
2040
2041 s->base = var->base;
2042 s->limit = var->limit;
2043 s->selector = var->selector;
2044 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
2045 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
2046 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
2047 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
2048 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
2049 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
2050 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
2051 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
2052
2053 /*
2054 * This is always accurate, except if SYSRET returned to a segment
2055 * with SS.DPL != 3. Intel does not have this quirk, and always
2056 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
2057 * would entail passing the CPL to userspace and back.
2058 */
2059 if (seg == VCPU_SREG_SS)
2060 /* This is symmetric with svm_get_segment() */
2061 svm->vmcb->save.cpl = (var->dpl & 3);
2062
2063 mark_dirty(svm->vmcb, VMCB_SEG);
2064 }
2065
2066 static void update_bp_intercept(struct kvm_vcpu *vcpu)
2067 {
2068 struct vcpu_svm *svm = to_svm(vcpu);
2069
2070 clr_exception_intercept(svm, BP_VECTOR);
2071
2072 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
2073 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2074 set_exception_intercept(svm, BP_VECTOR);
2075 } else
2076 vcpu->guest_debug = 0;
2077 }
2078
2079 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
2080 {
2081 if (sd->next_asid > sd->max_asid) {
2082 ++sd->asid_generation;
2083 sd->next_asid = 1;
2084 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
2085 }
2086
2087 svm->asid_generation = sd->asid_generation;
2088 svm->vmcb->control.asid = sd->next_asid++;
2089
2090 mark_dirty(svm->vmcb, VMCB_ASID);
2091 }
2092
2093 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
2094 {
2095 return to_svm(vcpu)->vmcb->save.dr6;
2096 }
2097
2098 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
2099 {
2100 struct vcpu_svm *svm = to_svm(vcpu);
2101
2102 svm->vmcb->save.dr6 = value;
2103 mark_dirty(svm->vmcb, VMCB_DR);
2104 }
2105
2106 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2107 {
2108 struct vcpu_svm *svm = to_svm(vcpu);
2109
2110 get_debugreg(vcpu->arch.db[0], 0);
2111 get_debugreg(vcpu->arch.db[1], 1);
2112 get_debugreg(vcpu->arch.db[2], 2);
2113 get_debugreg(vcpu->arch.db[3], 3);
2114 vcpu->arch.dr6 = svm_get_dr6(vcpu);
2115 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2116
2117 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2118 set_dr_intercepts(svm);
2119 }
2120
2121 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2122 {
2123 struct vcpu_svm *svm = to_svm(vcpu);
2124
2125 svm->vmcb->save.dr7 = value;
2126 mark_dirty(svm->vmcb, VMCB_DR);
2127 }
2128
2129 static int pf_interception(struct vcpu_svm *svm)
2130 {
2131 u64 fault_address = svm->vmcb->control.exit_info_2;
2132 u64 error_code = svm->vmcb->control.exit_info_1;
2133
2134 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
2135 svm->vmcb->control.insn_bytes,
2136 svm->vmcb->control.insn_len, !npt_enabled);
2137 }
2138
2139 static int db_interception(struct vcpu_svm *svm)
2140 {
2141 struct kvm_run *kvm_run = svm->vcpu.run;
2142
2143 if (!(svm->vcpu.guest_debug &
2144 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2145 !svm->nmi_singlestep) {
2146 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
2147 return 1;
2148 }
2149
2150 if (svm->nmi_singlestep) {
2151 disable_nmi_singlestep(svm);
2152 }
2153
2154 if (svm->vcpu.guest_debug &
2155 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2156 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2157 kvm_run->debug.arch.pc =
2158 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2159 kvm_run->debug.arch.exception = DB_VECTOR;
2160 return 0;
2161 }
2162
2163 return 1;
2164 }
2165
2166 static int bp_interception(struct vcpu_svm *svm)
2167 {
2168 struct kvm_run *kvm_run = svm->vcpu.run;
2169
2170 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2171 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2172 kvm_run->debug.arch.exception = BP_VECTOR;
2173 return 0;
2174 }
2175
2176 static int ud_interception(struct vcpu_svm *svm)
2177 {
2178 int er;
2179
2180 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
2181 if (er != EMULATE_DONE)
2182 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2183 return 1;
2184 }
2185
2186 static int ac_interception(struct vcpu_svm *svm)
2187 {
2188 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
2189 return 1;
2190 }
2191
2192 static bool is_erratum_383(void)
2193 {
2194 int err, i;
2195 u64 value;
2196
2197 if (!erratum_383_found)
2198 return false;
2199
2200 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2201 if (err)
2202 return false;
2203
2204 /* Bit 62 may or may not be set for this mce */
2205 value &= ~(1ULL << 62);
2206
2207 if (value != 0xb600000000010015ULL)
2208 return false;
2209
2210 /* Clear MCi_STATUS registers */
2211 for (i = 0; i < 6; ++i)
2212 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2213
2214 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2215 if (!err) {
2216 u32 low, high;
2217
2218 value &= ~(1ULL << 2);
2219 low = lower_32_bits(value);
2220 high = upper_32_bits(value);
2221
2222 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2223 }
2224
2225 /* Flush tlb to evict multi-match entries */
2226 __flush_tlb_all();
2227
2228 return true;
2229 }
2230
2231 static void svm_handle_mce(struct vcpu_svm *svm)
2232 {
2233 if (is_erratum_383()) {
2234 /*
2235 * Erratum 383 triggered. Guest state is corrupt so kill the
2236 * guest.
2237 */
2238 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2239
2240 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2241
2242 return;
2243 }
2244
2245 /*
2246 * On an #MC intercept the MCE handler is not called automatically in
2247 * the host. So do it by hand here.
2248 */
2249 asm volatile (
2250 "int $0x12\n");
2251 /* not sure if we ever come back to this point */
2252
2253 return;
2254 }
2255
2256 static int mc_interception(struct vcpu_svm *svm)
2257 {
2258 return 1;
2259 }
2260
2261 static int shutdown_interception(struct vcpu_svm *svm)
2262 {
2263 struct kvm_run *kvm_run = svm->vcpu.run;
2264
2265 /*
2266 * VMCB is undefined after a SHUTDOWN intercept
2267 * so reinitialize it.
2268 */
2269 clear_page(svm->vmcb);
2270 init_vmcb(svm);
2271
2272 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2273 return 0;
2274 }
2275
2276 static int io_interception(struct vcpu_svm *svm)
2277 {
2278 struct kvm_vcpu *vcpu = &svm->vcpu;
2279 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2280 int size, in, string, ret;
2281 unsigned port;
2282
2283 ++svm->vcpu.stat.io_exits;
2284 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2285 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2286 if (string)
2287 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
2288
2289 port = io_info >> 16;
2290 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2291 svm->next_rip = svm->vmcb->control.exit_info_2;
2292 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2293
2294 /*
2295 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
2296 * KVM_EXIT_DEBUG here.
2297 */
2298 if (in)
2299 return kvm_fast_pio_in(vcpu, size, port) && ret;
2300 else
2301 return kvm_fast_pio_out(vcpu, size, port) && ret;
2302 }
2303
2304 static int nmi_interception(struct vcpu_svm *svm)
2305 {
2306 return 1;
2307 }
2308
2309 static int intr_interception(struct vcpu_svm *svm)
2310 {
2311 ++svm->vcpu.stat.irq_exits;
2312 return 1;
2313 }
2314
2315 static int nop_on_interception(struct vcpu_svm *svm)
2316 {
2317 return 1;
2318 }
2319
2320 static int halt_interception(struct vcpu_svm *svm)
2321 {
2322 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
2323 return kvm_emulate_halt(&svm->vcpu);
2324 }
2325
2326 static int vmmcall_interception(struct vcpu_svm *svm)
2327 {
2328 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2329 return kvm_emulate_hypercall(&svm->vcpu);
2330 }
2331
2332 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
2333 {
2334 struct vcpu_svm *svm = to_svm(vcpu);
2335
2336 return svm->nested.nested_cr3;
2337 }
2338
2339 static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
2340 {
2341 struct vcpu_svm *svm = to_svm(vcpu);
2342 u64 cr3 = svm->nested.nested_cr3;
2343 u64 pdpte;
2344 int ret;
2345
2346 ret = kvm_vcpu_read_guest_page(vcpu, gpa_to_gfn(__sme_clr(cr3)), &pdpte,
2347 offset_in_page(cr3) + index * 8, 8);
2348 if (ret)
2349 return 0;
2350 return pdpte;
2351 }
2352
2353 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
2354 unsigned long root)
2355 {
2356 struct vcpu_svm *svm = to_svm(vcpu);
2357
2358 svm->vmcb->control.nested_cr3 = __sme_set(root);
2359 mark_dirty(svm->vmcb, VMCB_NPT);
2360 svm_flush_tlb(vcpu);
2361 }
2362
2363 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
2364 struct x86_exception *fault)
2365 {
2366 struct vcpu_svm *svm = to_svm(vcpu);
2367
2368 if (svm->vmcb->control.exit_code != SVM_EXIT_NPF) {
2369 /*
2370 * TODO: track the cause of the nested page fault, and
2371 * correctly fill in the high bits of exit_info_1.
2372 */
2373 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
2374 svm->vmcb->control.exit_code_hi = 0;
2375 svm->vmcb->control.exit_info_1 = (1ULL << 32);
2376 svm->vmcb->control.exit_info_2 = fault->address;
2377 }
2378
2379 svm->vmcb->control.exit_info_1 &= ~0xffffffffULL;
2380 svm->vmcb->control.exit_info_1 |= fault->error_code;
2381
2382 /*
2383 * The present bit is always zero for page structure faults on real
2384 * hardware.
2385 */
2386 if (svm->vmcb->control.exit_info_1 & (2ULL << 32))
2387 svm->vmcb->control.exit_info_1 &= ~1;
2388
2389 nested_svm_vmexit(svm);
2390 }
2391
2392 static void nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
2393 {
2394 WARN_ON(mmu_is_nested(vcpu));
2395 kvm_init_shadow_mmu(vcpu);
2396 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
2397 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
2398 vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
2399 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
2400 vcpu->arch.mmu.shadow_root_level = get_npt_level(vcpu);
2401 reset_shadow_zero_bits_mask(vcpu, &vcpu->arch.mmu);
2402 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
2403 }
2404
2405 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
2406 {
2407 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
2408 }
2409
2410 static int nested_svm_check_permissions(struct vcpu_svm *svm)
2411 {
2412 if (!(svm->vcpu.arch.efer & EFER_SVME) ||
2413 !is_paging(&svm->vcpu)) {
2414 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2415 return 1;
2416 }
2417
2418 if (svm->vmcb->save.cpl) {
2419 kvm_inject_gp(&svm->vcpu, 0);
2420 return 1;
2421 }
2422
2423 return 0;
2424 }
2425
2426 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
2427 bool has_error_code, u32 error_code)
2428 {
2429 int vmexit;
2430
2431 if (!is_guest_mode(&svm->vcpu))
2432 return 0;
2433
2434 vmexit = nested_svm_intercept(svm);
2435 if (vmexit != NESTED_EXIT_DONE)
2436 return 0;
2437
2438 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
2439 svm->vmcb->control.exit_code_hi = 0;
2440 svm->vmcb->control.exit_info_1 = error_code;
2441
2442 /*
2443 * FIXME: we should not write CR2 when L1 intercepts an L2 #PF exception.
2444 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2445 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6 can be
2446 * written only when inject_pending_event runs (DR6 would written here
2447 * too). This should be conditional on a new capability---if the
2448 * capability is disabled, kvm_multiple_exception would write the
2449 * ancillary information to CR2 or DR6, for backwards ABI-compatibility.
2450 */
2451 if (svm->vcpu.arch.exception.nested_apf)
2452 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.apf.nested_apf_token;
2453 else
2454 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
2455
2456 svm->nested.exit_required = true;
2457 return vmexit;
2458 }
2459
2460 /* This function returns true if it is save to enable the irq window */
2461 static inline bool nested_svm_intr(struct vcpu_svm *svm)
2462 {
2463 if (!is_guest_mode(&svm->vcpu))
2464 return true;
2465
2466 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2467 return true;
2468
2469 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
2470 return false;
2471
2472 /*
2473 * if vmexit was already requested (by intercepted exception
2474 * for instance) do not overwrite it with "external interrupt"
2475 * vmexit.
2476 */
2477 if (svm->nested.exit_required)
2478 return false;
2479
2480 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
2481 svm->vmcb->control.exit_info_1 = 0;
2482 svm->vmcb->control.exit_info_2 = 0;
2483
2484 if (svm->nested.intercept & 1ULL) {
2485 /*
2486 * The #vmexit can't be emulated here directly because this
2487 * code path runs with irqs and preemption disabled. A
2488 * #vmexit emulation might sleep. Only signal request for
2489 * the #vmexit here.
2490 */
2491 svm->nested.exit_required = true;
2492 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
2493 return false;
2494 }
2495
2496 return true;
2497 }
2498
2499 /* This function returns true if it is save to enable the nmi window */
2500 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
2501 {
2502 if (!is_guest_mode(&svm->vcpu))
2503 return true;
2504
2505 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
2506 return true;
2507
2508 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
2509 svm->nested.exit_required = true;
2510
2511 return false;
2512 }
2513
2514 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
2515 {
2516 struct page *page;
2517
2518 might_sleep();
2519
2520 page = kvm_vcpu_gfn_to_page(&svm->vcpu, gpa >> PAGE_SHIFT);
2521 if (is_error_page(page))
2522 goto error;
2523
2524 *_page = page;
2525
2526 return kmap(page);
2527
2528 error:
2529 kvm_inject_gp(&svm->vcpu, 0);
2530
2531 return NULL;
2532 }
2533
2534 static void nested_svm_unmap(struct page *page)
2535 {
2536 kunmap(page);
2537 kvm_release_page_dirty(page);
2538 }
2539
2540 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
2541 {
2542 unsigned port, size, iopm_len;
2543 u16 val, mask;
2544 u8 start_bit;
2545 u64 gpa;
2546
2547 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
2548 return NESTED_EXIT_HOST;
2549
2550 port = svm->vmcb->control.exit_info_1 >> 16;
2551 size = (svm->vmcb->control.exit_info_1 & SVM_IOIO_SIZE_MASK) >>
2552 SVM_IOIO_SIZE_SHIFT;
2553 gpa = svm->nested.vmcb_iopm + (port / 8);
2554 start_bit = port % 8;
2555 iopm_len = (start_bit + size > 8) ? 2 : 1;
2556 mask = (0xf >> (4 - size)) << start_bit;
2557 val = 0;
2558
2559 if (kvm_vcpu_read_guest(&svm->vcpu, gpa, &val, iopm_len))
2560 return NESTED_EXIT_DONE;
2561
2562 return (val & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2563 }
2564
2565 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
2566 {
2567 u32 offset, msr, value;
2568 int write, mask;
2569
2570 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2571 return NESTED_EXIT_HOST;
2572
2573 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2574 offset = svm_msrpm_offset(msr);
2575 write = svm->vmcb->control.exit_info_1 & 1;
2576 mask = 1 << ((2 * (msr & 0xf)) + write);
2577
2578 if (offset == MSR_INVALID)
2579 return NESTED_EXIT_DONE;
2580
2581 /* Offset is in 32 bit units but need in 8 bit units */
2582 offset *= 4;
2583
2584 if (kvm_vcpu_read_guest(&svm->vcpu, svm->nested.vmcb_msrpm + offset, &value, 4))
2585 return NESTED_EXIT_DONE;
2586
2587 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
2588 }
2589
2590 /* DB exceptions for our internal use must not cause vmexit */
2591 static int nested_svm_intercept_db(struct vcpu_svm *svm)
2592 {
2593 unsigned long dr6;
2594
2595 /* if we're not singlestepping, it's not ours */
2596 if (!svm->nmi_singlestep)
2597 return NESTED_EXIT_DONE;
2598
2599 /* if it's not a singlestep exception, it's not ours */
2600 if (kvm_get_dr(&svm->vcpu, 6, &dr6))
2601 return NESTED_EXIT_DONE;
2602 if (!(dr6 & DR6_BS))
2603 return NESTED_EXIT_DONE;
2604
2605 /* if the guest is singlestepping, it should get the vmexit */
2606 if (svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF) {
2607 disable_nmi_singlestep(svm);
2608 return NESTED_EXIT_DONE;
2609 }
2610
2611 /* it's ours, the nested hypervisor must not see this one */
2612 return NESTED_EXIT_HOST;
2613 }
2614
2615 static int nested_svm_exit_special(struct vcpu_svm *svm)
2616 {
2617 u32 exit_code = svm->vmcb->control.exit_code;
2618
2619 switch (exit_code) {
2620 case SVM_EXIT_INTR:
2621 case SVM_EXIT_NMI:
2622 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
2623 return NESTED_EXIT_HOST;
2624 case SVM_EXIT_NPF:
2625 /* For now we are always handling NPFs when using them */
2626 if (npt_enabled)
2627 return NESTED_EXIT_HOST;
2628 break;
2629 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
2630 /* When we're shadowing, trap PFs, but not async PF */
2631 if (!npt_enabled && svm->vcpu.arch.apf.host_apf_reason == 0)
2632 return NESTED_EXIT_HOST;
2633 break;
2634 default:
2635 break;
2636 }
2637
2638 return NESTED_EXIT_CONTINUE;
2639 }
2640
2641 /*
2642 * If this function returns true, this #vmexit was already handled
2643 */
2644 static int nested_svm_intercept(struct vcpu_svm *svm)
2645 {
2646 u32 exit_code = svm->vmcb->control.exit_code;
2647 int vmexit = NESTED_EXIT_HOST;
2648
2649 switch (exit_code) {
2650 case SVM_EXIT_MSR:
2651 vmexit = nested_svm_exit_handled_msr(svm);
2652 break;
2653 case SVM_EXIT_IOIO:
2654 vmexit = nested_svm_intercept_ioio(svm);
2655 break;
2656 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2657 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2658 if (svm->nested.intercept_cr & bit)
2659 vmexit = NESTED_EXIT_DONE;
2660 break;
2661 }
2662 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2663 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2664 if (svm->nested.intercept_dr & bit)
2665 vmexit = NESTED_EXIT_DONE;
2666 break;
2667 }
2668 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2669 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2670 if (svm->nested.intercept_exceptions & excp_bits) {
2671 if (exit_code == SVM_EXIT_EXCP_BASE + DB_VECTOR)
2672 vmexit = nested_svm_intercept_db(svm);
2673 else
2674 vmexit = NESTED_EXIT_DONE;
2675 }
2676 /* async page fault always cause vmexit */
2677 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2678 svm->vcpu.arch.exception.nested_apf != 0)
2679 vmexit = NESTED_EXIT_DONE;
2680 break;
2681 }
2682 case SVM_EXIT_ERR: {
2683 vmexit = NESTED_EXIT_DONE;
2684 break;
2685 }
2686 default: {
2687 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2688 if (svm->nested.intercept & exit_bits)
2689 vmexit = NESTED_EXIT_DONE;
2690 }
2691 }
2692
2693 return vmexit;
2694 }
2695
2696 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2697 {
2698 int vmexit;
2699
2700 vmexit = nested_svm_intercept(svm);
2701
2702 if (vmexit == NESTED_EXIT_DONE)
2703 nested_svm_vmexit(svm);
2704
2705 return vmexit;
2706 }
2707
2708 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2709 {
2710 struct vmcb_control_area *dst = &dst_vmcb->control;
2711 struct vmcb_control_area *from = &from_vmcb->control;
2712
2713 dst->intercept_cr = from->intercept_cr;
2714 dst->intercept_dr = from->intercept_dr;
2715 dst->intercept_exceptions = from->intercept_exceptions;
2716 dst->intercept = from->intercept;
2717 dst->iopm_base_pa = from->iopm_base_pa;
2718 dst->msrpm_base_pa = from->msrpm_base_pa;
2719 dst->tsc_offset = from->tsc_offset;
2720 dst->asid = from->asid;
2721 dst->tlb_ctl = from->tlb_ctl;
2722 dst->int_ctl = from->int_ctl;
2723 dst->int_vector = from->int_vector;
2724 dst->int_state = from->int_state;
2725 dst->exit_code = from->exit_code;
2726 dst->exit_code_hi = from->exit_code_hi;
2727 dst->exit_info_1 = from->exit_info_1;
2728 dst->exit_info_2 = from->exit_info_2;
2729 dst->exit_int_info = from->exit_int_info;
2730 dst->exit_int_info_err = from->exit_int_info_err;
2731 dst->nested_ctl = from->nested_ctl;
2732 dst->event_inj = from->event_inj;
2733 dst->event_inj_err = from->event_inj_err;
2734 dst->nested_cr3 = from->nested_cr3;
2735 dst->virt_ext = from->virt_ext;
2736 }
2737
2738 static int nested_svm_vmexit(struct vcpu_svm *svm)
2739 {
2740 struct vmcb *nested_vmcb;
2741 struct vmcb *hsave = svm->nested.hsave;
2742 struct vmcb *vmcb = svm->vmcb;
2743 struct page *page;
2744
2745 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2746 vmcb->control.exit_info_1,
2747 vmcb->control.exit_info_2,
2748 vmcb->control.exit_int_info,
2749 vmcb->control.exit_int_info_err,
2750 KVM_ISA_SVM);
2751
2752 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2753 if (!nested_vmcb)
2754 return 1;
2755
2756 /* Exit Guest-Mode */
2757 leave_guest_mode(&svm->vcpu);
2758 svm->nested.vmcb = 0;
2759
2760 /* Give the current vmcb to the guest */
2761 disable_gif(svm);
2762
2763 nested_vmcb->save.es = vmcb->save.es;
2764 nested_vmcb->save.cs = vmcb->save.cs;
2765 nested_vmcb->save.ss = vmcb->save.ss;
2766 nested_vmcb->save.ds = vmcb->save.ds;
2767 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2768 nested_vmcb->save.idtr = vmcb->save.idtr;
2769 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2770 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2771 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2772 nested_vmcb->save.cr2 = vmcb->save.cr2;
2773 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2774 nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
2775 nested_vmcb->save.rip = vmcb->save.rip;
2776 nested_vmcb->save.rsp = vmcb->save.rsp;
2777 nested_vmcb->save.rax = vmcb->save.rax;
2778 nested_vmcb->save.dr7 = vmcb->save.dr7;
2779 nested_vmcb->save.dr6 = vmcb->save.dr6;
2780 nested_vmcb->save.cpl = vmcb->save.cpl;
2781
2782 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2783 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2784 nested_vmcb->control.int_state = vmcb->control.int_state;
2785 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2786 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2787 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2788 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2789 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2790 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2791
2792 if (svm->nrips_enabled)
2793 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2794
2795 /*
2796 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2797 * to make sure that we do not lose injected events. So check event_inj
2798 * here and copy it to exit_int_info if it is valid.
2799 * Exit_int_info and event_inj can't be both valid because the case
2800 * below only happens on a VMRUN instruction intercept which has
2801 * no valid exit_int_info set.
2802 */
2803 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2804 struct vmcb_control_area *nc = &nested_vmcb->control;
2805
2806 nc->exit_int_info = vmcb->control.event_inj;
2807 nc->exit_int_info_err = vmcb->control.event_inj_err;
2808 }
2809
2810 nested_vmcb->control.tlb_ctl = 0;
2811 nested_vmcb->control.event_inj = 0;
2812 nested_vmcb->control.event_inj_err = 0;
2813
2814 /* We always set V_INTR_MASKING and remember the old value in hflags */
2815 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2816 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2817
2818 /* Restore the original control entries */
2819 copy_vmcb_control_area(vmcb, hsave);
2820
2821 kvm_clear_exception_queue(&svm->vcpu);
2822 kvm_clear_interrupt_queue(&svm->vcpu);
2823
2824 svm->nested.nested_cr3 = 0;
2825
2826 /* Restore selected save entries */
2827 svm->vmcb->save.es = hsave->save.es;
2828 svm->vmcb->save.cs = hsave->save.cs;
2829 svm->vmcb->save.ss = hsave->save.ss;
2830 svm->vmcb->save.ds = hsave->save.ds;
2831 svm->vmcb->save.gdtr = hsave->save.gdtr;
2832 svm->vmcb->save.idtr = hsave->save.idtr;
2833 kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
2834 svm_set_efer(&svm->vcpu, hsave->save.efer);
2835 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2836 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2837 if (npt_enabled) {
2838 svm->vmcb->save.cr3 = hsave->save.cr3;
2839 svm->vcpu.arch.cr3 = hsave->save.cr3;
2840 } else {
2841 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2842 }
2843 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2844 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2845 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2846 svm->vmcb->save.dr7 = 0;
2847 svm->vmcb->save.cpl = 0;
2848 svm->vmcb->control.exit_int_info = 0;
2849
2850 mark_all_dirty(svm->vmcb);
2851
2852 nested_svm_unmap(page);
2853
2854 nested_svm_uninit_mmu_context(&svm->vcpu);
2855 kvm_mmu_reset_context(&svm->vcpu);
2856 kvm_mmu_load(&svm->vcpu);
2857
2858 return 0;
2859 }
2860
2861 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2862 {
2863 /*
2864 * This function merges the msr permission bitmaps of kvm and the
2865 * nested vmcb. It is optimized in that it only merges the parts where
2866 * the kvm msr permission bitmap may contain zero bits
2867 */
2868 int i;
2869
2870 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2871 return true;
2872
2873 for (i = 0; i < MSRPM_OFFSETS; i++) {
2874 u32 value, p;
2875 u64 offset;
2876
2877 if (msrpm_offsets[i] == 0xffffffff)
2878 break;
2879
2880 p = msrpm_offsets[i];
2881 offset = svm->nested.vmcb_msrpm + (p * 4);
2882
2883 if (kvm_vcpu_read_guest(&svm->vcpu, offset, &value, 4))
2884 return false;
2885
2886 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2887 }
2888
2889 svm->vmcb->control.msrpm_base_pa = __sme_set(__pa(svm->nested.msrpm));
2890
2891 return true;
2892 }
2893
2894 static bool nested_vmcb_checks(struct vmcb *vmcb)
2895 {
2896 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2897 return false;
2898
2899 if (vmcb->control.asid == 0)
2900 return false;
2901
2902 if (vmcb->control.nested_ctl && !npt_enabled)
2903 return false;
2904
2905 return true;
2906 }
2907
2908 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2909 {
2910 struct vmcb *nested_vmcb;
2911 struct vmcb *hsave = svm->nested.hsave;
2912 struct vmcb *vmcb = svm->vmcb;
2913 struct page *page;
2914 u64 vmcb_gpa;
2915
2916 vmcb_gpa = svm->vmcb->save.rax;
2917
2918 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2919 if (!nested_vmcb)
2920 return false;
2921
2922 if (!nested_vmcb_checks(nested_vmcb)) {
2923 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2924 nested_vmcb->control.exit_code_hi = 0;
2925 nested_vmcb->control.exit_info_1 = 0;
2926 nested_vmcb->control.exit_info_2 = 0;
2927
2928 nested_svm_unmap(page);
2929
2930 return false;
2931 }
2932
2933 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2934 nested_vmcb->save.rip,
2935 nested_vmcb->control.int_ctl,
2936 nested_vmcb->control.event_inj,
2937 nested_vmcb->control.nested_ctl);
2938
2939 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2940 nested_vmcb->control.intercept_cr >> 16,
2941 nested_vmcb->control.intercept_exceptions,
2942 nested_vmcb->control.intercept);
2943
2944 /* Clear internal status */
2945 kvm_clear_exception_queue(&svm->vcpu);
2946 kvm_clear_interrupt_queue(&svm->vcpu);
2947
2948 /*
2949 * Save the old vmcb, so we don't need to pick what we save, but can
2950 * restore everything when a VMEXIT occurs
2951 */
2952 hsave->save.es = vmcb->save.es;
2953 hsave->save.cs = vmcb->save.cs;
2954 hsave->save.ss = vmcb->save.ss;
2955 hsave->save.ds = vmcb->save.ds;
2956 hsave->save.gdtr = vmcb->save.gdtr;
2957 hsave->save.idtr = vmcb->save.idtr;
2958 hsave->save.efer = svm->vcpu.arch.efer;
2959 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2960 hsave->save.cr4 = svm->vcpu.arch.cr4;
2961 hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
2962 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2963 hsave->save.rsp = vmcb->save.rsp;
2964 hsave->save.rax = vmcb->save.rax;
2965 if (npt_enabled)
2966 hsave->save.cr3 = vmcb->save.cr3;
2967 else
2968 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2969
2970 copy_vmcb_control_area(hsave, vmcb);
2971
2972 if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
2973 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2974 else
2975 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2976
2977 if (nested_vmcb->control.nested_ctl) {
2978 kvm_mmu_unload(&svm->vcpu);
2979 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2980 nested_svm_init_mmu_context(&svm->vcpu);
2981 }
2982
2983 /* Load the nested guest state */
2984 svm->vmcb->save.es = nested_vmcb->save.es;
2985 svm->vmcb->save.cs = nested_vmcb->save.cs;
2986 svm->vmcb->save.ss = nested_vmcb->save.ss;
2987 svm->vmcb->save.ds = nested_vmcb->save.ds;
2988 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2989 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2990 kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
2991 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2992 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2993 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2994 if (npt_enabled) {
2995 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2996 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2997 } else
2998 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2999
3000 /* Guest paging mode is active - reset mmu */
3001 kvm_mmu_reset_context(&svm->vcpu);
3002
3003 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
3004 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
3005 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
3006 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
3007
3008 /* In case we don't even reach vcpu_run, the fields are not updated */
3009 svm->vmcb->save.rax = nested_vmcb->save.rax;
3010 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
3011 svm->vmcb->save.rip = nested_vmcb->save.rip;
3012 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
3013 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
3014 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
3015
3016 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
3017 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
3018
3019 /* cache intercepts */
3020 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
3021 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
3022 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
3023 svm->nested.intercept = nested_vmcb->control.intercept;
3024
3025 svm_flush_tlb(&svm->vcpu);
3026 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
3027 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
3028 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
3029 else
3030 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
3031
3032 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
3033 /* We only want the cr8 intercept bits of the guest */
3034 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
3035 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3036 }
3037
3038 /* We don't want to see VMMCALLs from a nested guest */
3039 clr_intercept(svm, INTERCEPT_VMMCALL);
3040
3041 svm->vmcb->control.virt_ext = nested_vmcb->control.virt_ext;
3042 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
3043 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
3044 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
3045 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
3046 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
3047
3048 nested_svm_unmap(page);
3049
3050 /* Enter Guest-Mode */
3051 enter_guest_mode(&svm->vcpu);
3052
3053 /*
3054 * Merge guest and host intercepts - must be called with vcpu in
3055 * guest-mode to take affect here
3056 */
3057 recalc_intercepts(svm);
3058
3059 svm->nested.vmcb = vmcb_gpa;
3060
3061 enable_gif(svm);
3062
3063 mark_all_dirty(svm->vmcb);
3064
3065 return true;
3066 }
3067
3068 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
3069 {
3070 to_vmcb->save.fs = from_vmcb->save.fs;
3071 to_vmcb->save.gs = from_vmcb->save.gs;
3072 to_vmcb->save.tr = from_vmcb->save.tr;
3073 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
3074 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
3075 to_vmcb->save.star = from_vmcb->save.star;
3076 to_vmcb->save.lstar = from_vmcb->save.lstar;
3077 to_vmcb->save.cstar = from_vmcb->save.cstar;
3078 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
3079 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
3080 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
3081 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
3082 }
3083
3084 static int vmload_interception(struct vcpu_svm *svm)
3085 {
3086 struct vmcb *nested_vmcb;
3087 struct page *page;
3088 int ret;
3089
3090 if (nested_svm_check_permissions(svm))
3091 return 1;
3092
3093 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3094 if (!nested_vmcb)
3095 return 1;
3096
3097 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3098 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3099
3100 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
3101 nested_svm_unmap(page);
3102
3103 return ret;
3104 }
3105
3106 static int vmsave_interception(struct vcpu_svm *svm)
3107 {
3108 struct vmcb *nested_vmcb;
3109 struct page *page;
3110 int ret;
3111
3112 if (nested_svm_check_permissions(svm))
3113 return 1;
3114
3115 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
3116 if (!nested_vmcb)
3117 return 1;
3118
3119 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3120 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3121
3122 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
3123 nested_svm_unmap(page);
3124
3125 return ret;
3126 }
3127
3128 static int vmrun_interception(struct vcpu_svm *svm)
3129 {
3130 if (nested_svm_check_permissions(svm))
3131 return 1;
3132
3133 /* Save rip after vmrun instruction */
3134 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
3135
3136 if (!nested_svm_vmrun(svm))
3137 return 1;
3138
3139 if (!nested_svm_vmrun_msrpm(svm))
3140 goto failed;
3141
3142 return 1;
3143
3144 failed:
3145
3146 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
3147 svm->vmcb->control.exit_code_hi = 0;
3148 svm->vmcb->control.exit_info_1 = 0;
3149 svm->vmcb->control.exit_info_2 = 0;
3150
3151 nested_svm_vmexit(svm);
3152
3153 return 1;
3154 }
3155
3156 static int stgi_interception(struct vcpu_svm *svm)
3157 {
3158 int ret;
3159
3160 if (nested_svm_check_permissions(svm))
3161 return 1;
3162
3163 /*
3164 * If VGIF is enabled, the STGI intercept is only added to
3165 * detect the opening of the NMI window; remove it now.
3166 */
3167 if (vgif_enabled(svm))
3168 clr_intercept(svm, INTERCEPT_STGI);
3169
3170 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3171 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3172 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3173
3174 enable_gif(svm);
3175
3176 return ret;
3177 }
3178
3179 static int clgi_interception(struct vcpu_svm *svm)
3180 {
3181 int ret;
3182
3183 if (nested_svm_check_permissions(svm))
3184 return 1;
3185
3186 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3187 ret = kvm_skip_emulated_instruction(&svm->vcpu);
3188
3189 disable_gif(svm);
3190
3191 /* After a CLGI no interrupts should come */
3192 if (!kvm_vcpu_apicv_active(&svm->vcpu)) {
3193 svm_clear_vintr(svm);
3194 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3195 mark_dirty(svm->vmcb, VMCB_INTR);
3196 }
3197
3198 return ret;
3199 }
3200
3201 static int invlpga_interception(struct vcpu_svm *svm)
3202 {
3203 struct kvm_vcpu *vcpu = &svm->vcpu;
3204
3205 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RCX),
3206 kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3207
3208 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
3209 kvm_mmu_invlpg(vcpu, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3210
3211 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3212 return kvm_skip_emulated_instruction(&svm->vcpu);
3213 }
3214
3215 static int skinit_interception(struct vcpu_svm *svm)
3216 {
3217 trace_kvm_skinit(svm->vmcb->save.rip, kvm_register_read(&svm->vcpu, VCPU_REGS_RAX));
3218
3219 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3220 return 1;
3221 }
3222
3223 static int wbinvd_interception(struct vcpu_svm *svm)
3224 {
3225 return kvm_emulate_wbinvd(&svm->vcpu);
3226 }
3227
3228 static int xsetbv_interception(struct vcpu_svm *svm)
3229 {
3230 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
3231 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3232
3233 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
3234 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
3235 return kvm_skip_emulated_instruction(&svm->vcpu);
3236 }
3237
3238 return 1;
3239 }
3240
3241 static int task_switch_interception(struct vcpu_svm *svm)
3242 {
3243 u16 tss_selector;
3244 int reason;
3245 int int_type = svm->vmcb->control.exit_int_info &
3246 SVM_EXITINTINFO_TYPE_MASK;
3247 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
3248 uint32_t type =
3249 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
3250 uint32_t idt_v =
3251 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
3252 bool has_error_code = false;
3253 u32 error_code = 0;
3254
3255 tss_selector = (u16)svm->vmcb->control.exit_info_1;
3256
3257 if (svm->vmcb->control.exit_info_2 &
3258 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
3259 reason = TASK_SWITCH_IRET;
3260 else if (svm->vmcb->control.exit_info_2 &
3261 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
3262 reason = TASK_SWITCH_JMP;
3263 else if (idt_v)
3264 reason = TASK_SWITCH_GATE;
3265 else
3266 reason = TASK_SWITCH_CALL;
3267
3268 if (reason == TASK_SWITCH_GATE) {
3269 switch (type) {
3270 case SVM_EXITINTINFO_TYPE_NMI:
3271 svm->vcpu.arch.nmi_injected = false;
3272 break;
3273 case SVM_EXITINTINFO_TYPE_EXEPT:
3274 if (svm->vmcb->control.exit_info_2 &
3275 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
3276 has_error_code = true;
3277 error_code =
3278 (u32)svm->vmcb->control.exit_info_2;
3279 }
3280 kvm_clear_exception_queue(&svm->vcpu);
3281 break;
3282 case SVM_EXITINTINFO_TYPE_INTR:
3283 kvm_clear_interrupt_queue(&svm->vcpu);
3284 break;
3285 default:
3286 break;
3287 }
3288 }
3289
3290 if (reason != TASK_SWITCH_GATE ||
3291 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
3292 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
3293 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
3294 skip_emulated_instruction(&svm->vcpu);
3295
3296 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
3297 int_vec = -1;
3298
3299 if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
3300 has_error_code, error_code) == EMULATE_FAIL) {
3301 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3302 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3303 svm->vcpu.run->internal.ndata = 0;
3304 return 0;
3305 }
3306 return 1;
3307 }
3308
3309 static int cpuid_interception(struct vcpu_svm *svm)
3310 {
3311 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3312 return kvm_emulate_cpuid(&svm->vcpu);
3313 }
3314
3315 static int iret_interception(struct vcpu_svm *svm)
3316 {
3317 ++svm->vcpu.stat.nmi_window_exits;
3318 clr_intercept(svm, INTERCEPT_IRET);
3319 svm->vcpu.arch.hflags |= HF_IRET_MASK;
3320 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
3321 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3322 return 1;
3323 }
3324
3325 static int invlpg_interception(struct vcpu_svm *svm)
3326 {
3327 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3328 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3329
3330 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
3331 return kvm_skip_emulated_instruction(&svm->vcpu);
3332 }
3333
3334 static int emulate_on_interception(struct vcpu_svm *svm)
3335 {
3336 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
3337 }
3338
3339 static int rdpmc_interception(struct vcpu_svm *svm)
3340 {
3341 int err;
3342
3343 if (!static_cpu_has(X86_FEATURE_NRIPS))
3344 return emulate_on_interception(svm);
3345
3346 err = kvm_rdpmc(&svm->vcpu);
3347 return kvm_complete_insn_gp(&svm->vcpu, err);
3348 }
3349
3350 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
3351 unsigned long val)
3352 {
3353 unsigned long cr0 = svm->vcpu.arch.cr0;
3354 bool ret = false;
3355 u64 intercept;
3356
3357 intercept = svm->nested.intercept;
3358
3359 if (!is_guest_mode(&svm->vcpu) ||
3360 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
3361 return false;
3362
3363 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
3364 val &= ~SVM_CR0_SELECTIVE_MASK;
3365
3366 if (cr0 ^ val) {
3367 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3368 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
3369 }
3370
3371 return ret;
3372 }
3373
3374 #define CR_VALID (1ULL << 63)
3375
3376 static int cr_interception(struct vcpu_svm *svm)
3377 {
3378 int reg, cr;
3379 unsigned long val;
3380 int err;
3381
3382 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
3383 return emulate_on_interception(svm);
3384
3385 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
3386 return emulate_on_interception(svm);
3387
3388 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3389 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
3390 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
3391 else
3392 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
3393
3394 err = 0;
3395 if (cr >= 16) { /* mov to cr */
3396 cr -= 16;
3397 val = kvm_register_read(&svm->vcpu, reg);
3398 switch (cr) {
3399 case 0:
3400 if (!check_selective_cr0_intercepted(svm, val))
3401 err = kvm_set_cr0(&svm->vcpu, val);
3402 else
3403 return 1;
3404
3405 break;
3406 case 3:
3407 err = kvm_set_cr3(&svm->vcpu, val);
3408 break;
3409 case 4:
3410 err = kvm_set_cr4(&svm->vcpu, val);
3411 break;
3412 case 8:
3413 err = kvm_set_cr8(&svm->vcpu, val);
3414 break;
3415 default:
3416 WARN(1, "unhandled write to CR%d", cr);
3417 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3418 return 1;
3419 }
3420 } else { /* mov from cr */
3421 switch (cr) {
3422 case 0:
3423 val = kvm_read_cr0(&svm->vcpu);
3424 break;
3425 case 2:
3426 val = svm->vcpu.arch.cr2;
3427 break;
3428 case 3:
3429 val = kvm_read_cr3(&svm->vcpu);
3430 break;
3431 case 4:
3432 val = kvm_read_cr4(&svm->vcpu);
3433 break;
3434 case 8:
3435 val = kvm_get_cr8(&svm->vcpu);
3436 break;
3437 default:
3438 WARN(1, "unhandled read from CR%d", cr);
3439 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
3440 return 1;
3441 }
3442 kvm_register_write(&svm->vcpu, reg, val);
3443 }
3444 return kvm_complete_insn_gp(&svm->vcpu, err);
3445 }
3446
3447 static int dr_interception(struct vcpu_svm *svm)
3448 {
3449 int reg, dr;
3450 unsigned long val;
3451
3452 if (svm->vcpu.guest_debug == 0) {
3453 /*
3454 * No more DR vmexits; force a reload of the debug registers
3455 * and reenter on this instruction. The next vmexit will
3456 * retrieve the full state of the debug registers.
3457 */
3458 clr_dr_intercepts(svm);
3459 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
3460 return 1;
3461 }
3462
3463 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
3464 return emulate_on_interception(svm);
3465
3466 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
3467 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
3468
3469 if (dr >= 16) { /* mov to DRn */
3470 if (!kvm_require_dr(&svm->vcpu, dr - 16))
3471 return 1;
3472 val = kvm_register_read(&svm->vcpu, reg);
3473 kvm_set_dr(&svm->vcpu, dr - 16, val);
3474 } else {
3475 if (!kvm_require_dr(&svm->vcpu, dr))
3476 return 1;
3477 kvm_get_dr(&svm->vcpu, dr, &val);
3478 kvm_register_write(&svm->vcpu, reg, val);
3479 }
3480
3481 return kvm_skip_emulated_instruction(&svm->vcpu);
3482 }
3483
3484 static int cr8_write_interception(struct vcpu_svm *svm)
3485 {
3486 struct kvm_run *kvm_run = svm->vcpu.run;
3487 int r;
3488
3489 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
3490 /* instruction emulation calls kvm_set_cr8() */
3491 r = cr_interception(svm);
3492 if (lapic_in_kernel(&svm->vcpu))
3493 return r;
3494 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
3495 return r;
3496 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
3497 return 0;
3498 }
3499
3500 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
3501 {
3502 struct vcpu_svm *svm = to_svm(vcpu);
3503
3504 switch (msr_info->index) {
3505 case MSR_IA32_TSC: {
3506 msr_info->data = svm->vmcb->control.tsc_offset +
3507 kvm_scale_tsc(vcpu, rdtsc());
3508
3509 break;
3510 }
3511 case MSR_STAR:
3512 msr_info->data = svm->vmcb->save.star;
3513 break;
3514 #ifdef CONFIG_X86_64
3515 case MSR_LSTAR:
3516 msr_info->data = svm->vmcb->save.lstar;
3517 break;
3518 case MSR_CSTAR:
3519 msr_info->data = svm->vmcb->save.cstar;
3520 break;
3521 case MSR_KERNEL_GS_BASE:
3522 msr_info->data = svm->vmcb->save.kernel_gs_base;
3523 break;
3524 case MSR_SYSCALL_MASK:
3525 msr_info->data = svm->vmcb->save.sfmask;
3526 break;
3527 #endif
3528 case MSR_IA32_SYSENTER_CS:
3529 msr_info->data = svm->vmcb->save.sysenter_cs;
3530 break;
3531 case MSR_IA32_SYSENTER_EIP:
3532 msr_info->data = svm->sysenter_eip;
3533 break;
3534 case MSR_IA32_SYSENTER_ESP:
3535 msr_info->data = svm->sysenter_esp;
3536 break;
3537 case MSR_TSC_AUX:
3538 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3539 return 1;
3540 msr_info->data = svm->tsc_aux;
3541 break;
3542 /*
3543 * Nobody will change the following 5 values in the VMCB so we can
3544 * safely return them on rdmsr. They will always be 0 until LBRV is
3545 * implemented.
3546 */
3547 case MSR_IA32_DEBUGCTLMSR:
3548 msr_info->data = svm->vmcb->save.dbgctl;
3549 break;
3550 case MSR_IA32_LASTBRANCHFROMIP:
3551 msr_info->data = svm->vmcb->save.br_from;
3552 break;
3553 case MSR_IA32_LASTBRANCHTOIP:
3554 msr_info->data = svm->vmcb->save.br_to;
3555 break;
3556 case MSR_IA32_LASTINTFROMIP:
3557 msr_info->data = svm->vmcb->save.last_excp_from;
3558 break;
3559 case MSR_IA32_LASTINTTOIP:
3560 msr_info->data = svm->vmcb->save.last_excp_to;
3561 break;
3562 case MSR_VM_HSAVE_PA:
3563 msr_info->data = svm->nested.hsave_msr;
3564 break;
3565 case MSR_VM_CR:
3566 msr_info->data = svm->nested.vm_cr_msr;
3567 break;
3568 case MSR_IA32_UCODE_REV:
3569 msr_info->data = 0x01000065;
3570 break;
3571 case MSR_F15H_IC_CFG: {
3572
3573 int family, model;
3574
3575 family = guest_cpuid_family(vcpu);
3576 model = guest_cpuid_model(vcpu);
3577
3578 if (family < 0 || model < 0)
3579 return kvm_get_msr_common(vcpu, msr_info);
3580
3581 msr_info->data = 0;
3582
3583 if (family == 0x15 &&
3584 (model >= 0x2 && model < 0x20))
3585 msr_info->data = 0x1E;
3586 }
3587 break;
3588 default:
3589 return kvm_get_msr_common(vcpu, msr_info);
3590 }
3591 return 0;
3592 }
3593
3594 static int rdmsr_interception(struct vcpu_svm *svm)
3595 {
3596 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3597 struct msr_data msr_info;
3598
3599 msr_info.index = ecx;
3600 msr_info.host_initiated = false;
3601 if (svm_get_msr(&svm->vcpu, &msr_info)) {
3602 trace_kvm_msr_read_ex(ecx);
3603 kvm_inject_gp(&svm->vcpu, 0);
3604 return 1;
3605 } else {
3606 trace_kvm_msr_read(ecx, msr_info.data);
3607
3608 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX,
3609 msr_info.data & 0xffffffff);
3610 kvm_register_write(&svm->vcpu, VCPU_REGS_RDX,
3611 msr_info.data >> 32);
3612 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3613 return kvm_skip_emulated_instruction(&svm->vcpu);
3614 }
3615 }
3616
3617 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
3618 {
3619 struct vcpu_svm *svm = to_svm(vcpu);
3620 int svm_dis, chg_mask;
3621
3622 if (data & ~SVM_VM_CR_VALID_MASK)
3623 return 1;
3624
3625 chg_mask = SVM_VM_CR_VALID_MASK;
3626
3627 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
3628 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
3629
3630 svm->nested.vm_cr_msr &= ~chg_mask;
3631 svm->nested.vm_cr_msr |= (data & chg_mask);
3632
3633 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
3634
3635 /* check for svm_disable while efer.svme is set */
3636 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
3637 return 1;
3638
3639 return 0;
3640 }
3641
3642 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
3643 {
3644 struct vcpu_svm *svm = to_svm(vcpu);
3645
3646 u32 ecx = msr->index;
3647 u64 data = msr->data;
3648 switch (ecx) {
3649 case MSR_IA32_TSC:
3650 kvm_write_tsc(vcpu, msr);
3651 break;
3652 case MSR_STAR:
3653 svm->vmcb->save.star = data;
3654 break;
3655 #ifdef CONFIG_X86_64
3656 case MSR_LSTAR:
3657 svm->vmcb->save.lstar = data;
3658 break;
3659 case MSR_CSTAR:
3660 svm->vmcb->save.cstar = data;
3661 break;
3662 case MSR_KERNEL_GS_BASE:
3663 svm->vmcb->save.kernel_gs_base = data;
3664 break;
3665 case MSR_SYSCALL_MASK:
3666 svm->vmcb->save.sfmask = data;
3667 break;
3668 #endif
3669 case MSR_IA32_SYSENTER_CS:
3670 svm->vmcb->save.sysenter_cs = data;
3671 break;
3672 case MSR_IA32_SYSENTER_EIP:
3673 svm->sysenter_eip = data;
3674 svm->vmcb->save.sysenter_eip = data;
3675 break;
3676 case MSR_IA32_SYSENTER_ESP:
3677 svm->sysenter_esp = data;
3678 svm->vmcb->save.sysenter_esp = data;
3679 break;
3680 case MSR_TSC_AUX:
3681 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
3682 return 1;
3683
3684 /*
3685 * This is rare, so we update the MSR here instead of using
3686 * direct_access_msrs. Doing that would require a rdmsr in
3687 * svm_vcpu_put.
3688 */
3689 svm->tsc_aux = data;
3690 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
3691 break;
3692 case MSR_IA32_DEBUGCTLMSR:
3693 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
3694 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3695 __func__, data);
3696 break;
3697 }
3698 if (data & DEBUGCTL_RESERVED_BITS)
3699 return 1;
3700
3701 svm->vmcb->save.dbgctl = data;
3702 mark_dirty(svm->vmcb, VMCB_LBR);
3703 if (data & (1ULL<<0))
3704 svm_enable_lbrv(svm);
3705 else
3706 svm_disable_lbrv(svm);
3707 break;
3708 case MSR_VM_HSAVE_PA:
3709 svm->nested.hsave_msr = data;
3710 break;
3711 case MSR_VM_CR:
3712 return svm_set_vm_cr(vcpu, data);
3713 case MSR_VM_IGNNE:
3714 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3715 break;
3716 case MSR_IA32_APICBASE:
3717 if (kvm_vcpu_apicv_active(vcpu))
3718 avic_update_vapic_bar(to_svm(vcpu), data);
3719 /* Follow through */
3720 default:
3721 return kvm_set_msr_common(vcpu, msr);
3722 }
3723 return 0;
3724 }
3725
3726 static int wrmsr_interception(struct vcpu_svm *svm)
3727 {
3728 struct msr_data msr;
3729 u32 ecx = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
3730 u64 data = kvm_read_edx_eax(&svm->vcpu);
3731
3732 msr.data = data;
3733 msr.index = ecx;
3734 msr.host_initiated = false;
3735
3736 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
3737 if (kvm_set_msr(&svm->vcpu, &msr)) {
3738 trace_kvm_msr_write_ex(ecx, data);
3739 kvm_inject_gp(&svm->vcpu, 0);
3740 return 1;
3741 } else {
3742 trace_kvm_msr_write(ecx, data);
3743 return kvm_skip_emulated_instruction(&svm->vcpu);
3744 }
3745 }
3746
3747 static int msr_interception(struct vcpu_svm *svm)
3748 {
3749 if (svm->vmcb->control.exit_info_1)
3750 return wrmsr_interception(svm);
3751 else
3752 return rdmsr_interception(svm);
3753 }
3754
3755 static int interrupt_window_interception(struct vcpu_svm *svm)
3756 {
3757 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3758 svm_clear_vintr(svm);
3759 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3760 mark_dirty(svm->vmcb, VMCB_INTR);
3761 ++svm->vcpu.stat.irq_window_exits;
3762 return 1;
3763 }
3764
3765 static int pause_interception(struct vcpu_svm *svm)
3766 {
3767 struct kvm_vcpu *vcpu = &svm->vcpu;
3768 bool in_kernel = (svm_get_cpl(vcpu) == 0);
3769
3770 kvm_vcpu_on_spin(vcpu, in_kernel);
3771 return 1;
3772 }
3773
3774 static int nop_interception(struct vcpu_svm *svm)
3775 {
3776 return kvm_skip_emulated_instruction(&(svm->vcpu));
3777 }
3778
3779 static int monitor_interception(struct vcpu_svm *svm)
3780 {
3781 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3782 return nop_interception(svm);
3783 }
3784
3785 static int mwait_interception(struct vcpu_svm *svm)
3786 {
3787 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3788 return nop_interception(svm);
3789 }
3790
3791 enum avic_ipi_failure_cause {
3792 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
3793 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
3794 AVIC_IPI_FAILURE_INVALID_TARGET,
3795 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
3796 };
3797
3798 static int avic_incomplete_ipi_interception(struct vcpu_svm *svm)
3799 {
3800 u32 icrh = svm->vmcb->control.exit_info_1 >> 32;
3801 u32 icrl = svm->vmcb->control.exit_info_1;
3802 u32 id = svm->vmcb->control.exit_info_2 >> 32;
3803 u32 index = svm->vmcb->control.exit_info_2 & 0xFF;
3804 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3805
3806 trace_kvm_avic_incomplete_ipi(svm->vcpu.vcpu_id, icrh, icrl, id, index);
3807
3808 switch (id) {
3809 case AVIC_IPI_FAILURE_INVALID_INT_TYPE:
3810 /*
3811 * AVIC hardware handles the generation of
3812 * IPIs when the specified Message Type is Fixed
3813 * (also known as fixed delivery mode) and
3814 * the Trigger Mode is edge-triggered. The hardware
3815 * also supports self and broadcast delivery modes
3816 * specified via the Destination Shorthand(DSH)
3817 * field of the ICRL. Logical and physical APIC ID
3818 * formats are supported. All other IPI types cause
3819 * a #VMEXIT, which needs to emulated.
3820 */
3821 kvm_lapic_reg_write(apic, APIC_ICR2, icrh);
3822 kvm_lapic_reg_write(apic, APIC_ICR, icrl);
3823 break;
3824 case AVIC_IPI_FAILURE_TARGET_NOT_RUNNING: {
3825 int i;
3826 struct kvm_vcpu *vcpu;
3827 struct kvm *kvm = svm->vcpu.kvm;
3828 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3829
3830 /*
3831 * At this point, we expect that the AVIC HW has already
3832 * set the appropriate IRR bits on the valid target
3833 * vcpus. So, we just need to kick the appropriate vcpu.
3834 */
3835 kvm_for_each_vcpu(i, vcpu, kvm) {
3836 bool m = kvm_apic_match_dest(vcpu, apic,
3837 icrl & KVM_APIC_SHORT_MASK,
3838 GET_APIC_DEST_FIELD(icrh),
3839 icrl & KVM_APIC_DEST_MASK);
3840
3841 if (m && !avic_vcpu_is_running(vcpu))
3842 kvm_vcpu_wake_up(vcpu);
3843 }
3844 break;
3845 }
3846 case AVIC_IPI_FAILURE_INVALID_TARGET:
3847 break;
3848 case AVIC_IPI_FAILURE_INVALID_BACKING_PAGE:
3849 WARN_ONCE(1, "Invalid backing page\n");
3850 break;
3851 default:
3852 pr_err("Unknown IPI interception\n");
3853 }
3854
3855 return 1;
3856 }
3857
3858 static u32 *avic_get_logical_id_entry(struct kvm_vcpu *vcpu, u32 ldr, bool flat)
3859 {
3860 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3861 int index;
3862 u32 *logical_apic_id_table;
3863 int dlid = GET_APIC_LOGICAL_ID(ldr);
3864
3865 if (!dlid)
3866 return NULL;
3867
3868 if (flat) { /* flat */
3869 index = ffs(dlid) - 1;
3870 if (index > 7)
3871 return NULL;
3872 } else { /* cluster */
3873 int cluster = (dlid & 0xf0) >> 4;
3874 int apic = ffs(dlid & 0x0f) - 1;
3875
3876 if ((apic < 0) || (apic > 7) ||
3877 (cluster >= 0xf))
3878 return NULL;
3879 index = (cluster << 2) + apic;
3880 }
3881
3882 logical_apic_id_table = (u32 *) page_address(vm_data->avic_logical_id_table_page);
3883
3884 return &logical_apic_id_table[index];
3885 }
3886
3887 static int avic_ldr_write(struct kvm_vcpu *vcpu, u8 g_physical_id, u32 ldr,
3888 bool valid)
3889 {
3890 bool flat;
3891 u32 *entry, new_entry;
3892
3893 flat = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR) == APIC_DFR_FLAT;
3894 entry = avic_get_logical_id_entry(vcpu, ldr, flat);
3895 if (!entry)
3896 return -EINVAL;
3897
3898 new_entry = READ_ONCE(*entry);
3899 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK;
3900 new_entry |= (g_physical_id & AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK);
3901 if (valid)
3902 new_entry |= AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3903 else
3904 new_entry &= ~AVIC_LOGICAL_ID_ENTRY_VALID_MASK;
3905 WRITE_ONCE(*entry, new_entry);
3906
3907 return 0;
3908 }
3909
3910 static int avic_handle_ldr_update(struct kvm_vcpu *vcpu)
3911 {
3912 int ret;
3913 struct vcpu_svm *svm = to_svm(vcpu);
3914 u32 ldr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LDR);
3915
3916 if (!ldr)
3917 return 1;
3918
3919 ret = avic_ldr_write(vcpu, vcpu->vcpu_id, ldr, true);
3920 if (ret && svm->ldr_reg) {
3921 avic_ldr_write(vcpu, 0, svm->ldr_reg, false);
3922 svm->ldr_reg = 0;
3923 } else {
3924 svm->ldr_reg = ldr;
3925 }
3926 return ret;
3927 }
3928
3929 static int avic_handle_apic_id_update(struct kvm_vcpu *vcpu)
3930 {
3931 u64 *old, *new;
3932 struct vcpu_svm *svm = to_svm(vcpu);
3933 u32 apic_id_reg = kvm_lapic_get_reg(vcpu->arch.apic, APIC_ID);
3934 u32 id = (apic_id_reg >> 24) & 0xff;
3935
3936 if (vcpu->vcpu_id == id)
3937 return 0;
3938
3939 old = avic_get_physical_id_entry(vcpu, vcpu->vcpu_id);
3940 new = avic_get_physical_id_entry(vcpu, id);
3941 if (!new || !old)
3942 return 1;
3943
3944 /* We need to move physical_id_entry to new offset */
3945 *new = *old;
3946 *old = 0ULL;
3947 to_svm(vcpu)->avic_physical_id_cache = new;
3948
3949 /*
3950 * Also update the guest physical APIC ID in the logical
3951 * APIC ID table entry if already setup the LDR.
3952 */
3953 if (svm->ldr_reg)
3954 avic_handle_ldr_update(vcpu);
3955
3956 return 0;
3957 }
3958
3959 static int avic_handle_dfr_update(struct kvm_vcpu *vcpu)
3960 {
3961 struct vcpu_svm *svm = to_svm(vcpu);
3962 struct kvm_arch *vm_data = &vcpu->kvm->arch;
3963 u32 dfr = kvm_lapic_get_reg(vcpu->arch.apic, APIC_DFR);
3964 u32 mod = (dfr >> 28) & 0xf;
3965
3966 /*
3967 * We assume that all local APICs are using the same type.
3968 * If this changes, we need to flush the AVIC logical
3969 * APID id table.
3970 */
3971 if (vm_data->ldr_mode == mod)
3972 return 0;
3973
3974 clear_page(page_address(vm_data->avic_logical_id_table_page));
3975 vm_data->ldr_mode = mod;
3976
3977 if (svm->ldr_reg)
3978 avic_handle_ldr_update(vcpu);
3979 return 0;
3980 }
3981
3982 static int avic_unaccel_trap_write(struct vcpu_svm *svm)
3983 {
3984 struct kvm_lapic *apic = svm->vcpu.arch.apic;
3985 u32 offset = svm->vmcb->control.exit_info_1 &
3986 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
3987
3988 switch (offset) {
3989 case APIC_ID:
3990 if (avic_handle_apic_id_update(&svm->vcpu))
3991 return 0;
3992 break;
3993 case APIC_LDR:
3994 if (avic_handle_ldr_update(&svm->vcpu))
3995 return 0;
3996 break;
3997 case APIC_DFR:
3998 avic_handle_dfr_update(&svm->vcpu);
3999 break;
4000 default:
4001 break;
4002 }
4003
4004 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
4005
4006 return 1;
4007 }
4008
4009 static bool is_avic_unaccelerated_access_trap(u32 offset)
4010 {
4011 bool ret = false;
4012
4013 switch (offset) {
4014 case APIC_ID:
4015 case APIC_EOI:
4016 case APIC_RRR:
4017 case APIC_LDR:
4018 case APIC_DFR:
4019 case APIC_SPIV:
4020 case APIC_ESR:
4021 case APIC_ICR:
4022 case APIC_LVTT:
4023 case APIC_LVTTHMR:
4024 case APIC_LVTPC:
4025 case APIC_LVT0:
4026 case APIC_LVT1:
4027 case APIC_LVTERR:
4028 case APIC_TMICT:
4029 case APIC_TDCR:
4030 ret = true;
4031 break;
4032 default:
4033 break;
4034 }
4035 return ret;
4036 }
4037
4038 static int avic_unaccelerated_access_interception(struct vcpu_svm *svm)
4039 {
4040 int ret = 0;
4041 u32 offset = svm->vmcb->control.exit_info_1 &
4042 AVIC_UNACCEL_ACCESS_OFFSET_MASK;
4043 u32 vector = svm->vmcb->control.exit_info_2 &
4044 AVIC_UNACCEL_ACCESS_VECTOR_MASK;
4045 bool write = (svm->vmcb->control.exit_info_1 >> 32) &
4046 AVIC_UNACCEL_ACCESS_WRITE_MASK;
4047 bool trap = is_avic_unaccelerated_access_trap(offset);
4048
4049 trace_kvm_avic_unaccelerated_access(svm->vcpu.vcpu_id, offset,
4050 trap, write, vector);
4051 if (trap) {
4052 /* Handling Trap */
4053 WARN_ONCE(!write, "svm: Handling trap read.\n");
4054 ret = avic_unaccel_trap_write(svm);
4055 } else {
4056 /* Handling Fault */
4057 ret = (emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE);
4058 }
4059
4060 return ret;
4061 }
4062
4063 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
4064 [SVM_EXIT_READ_CR0] = cr_interception,
4065 [SVM_EXIT_READ_CR3] = cr_interception,
4066 [SVM_EXIT_READ_CR4] = cr_interception,
4067 [SVM_EXIT_READ_CR8] = cr_interception,
4068 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
4069 [SVM_EXIT_WRITE_CR0] = cr_interception,
4070 [SVM_EXIT_WRITE_CR3] = cr_interception,
4071 [SVM_EXIT_WRITE_CR4] = cr_interception,
4072 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
4073 [SVM_EXIT_READ_DR0] = dr_interception,
4074 [SVM_EXIT_READ_DR1] = dr_interception,
4075 [SVM_EXIT_READ_DR2] = dr_interception,
4076 [SVM_EXIT_READ_DR3] = dr_interception,
4077 [SVM_EXIT_READ_DR4] = dr_interception,
4078 [SVM_EXIT_READ_DR5] = dr_interception,
4079 [SVM_EXIT_READ_DR6] = dr_interception,
4080 [SVM_EXIT_READ_DR7] = dr_interception,
4081 [SVM_EXIT_WRITE_DR0] = dr_interception,
4082 [SVM_EXIT_WRITE_DR1] = dr_interception,
4083 [SVM_EXIT_WRITE_DR2] = dr_interception,
4084 [SVM_EXIT_WRITE_DR3] = dr_interception,
4085 [SVM_EXIT_WRITE_DR4] = dr_interception,
4086 [SVM_EXIT_WRITE_DR5] = dr_interception,
4087 [SVM_EXIT_WRITE_DR6] = dr_interception,
4088 [SVM_EXIT_WRITE_DR7] = dr_interception,
4089 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
4090 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
4091 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
4092 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
4093 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
4094 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
4095 [SVM_EXIT_INTR] = intr_interception,
4096 [SVM_EXIT_NMI] = nmi_interception,
4097 [SVM_EXIT_SMI] = nop_on_interception,
4098 [SVM_EXIT_INIT] = nop_on_interception,
4099 [SVM_EXIT_VINTR] = interrupt_window_interception,
4100 [SVM_EXIT_RDPMC] = rdpmc_interception,
4101 [SVM_EXIT_CPUID] = cpuid_interception,
4102 [SVM_EXIT_IRET] = iret_interception,
4103 [SVM_EXIT_INVD] = emulate_on_interception,
4104 [SVM_EXIT_PAUSE] = pause_interception,
4105 [SVM_EXIT_HLT] = halt_interception,
4106 [SVM_EXIT_INVLPG] = invlpg_interception,
4107 [SVM_EXIT_INVLPGA] = invlpga_interception,
4108 [SVM_EXIT_IOIO] = io_interception,
4109 [SVM_EXIT_MSR] = msr_interception,
4110 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
4111 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
4112 [SVM_EXIT_VMRUN] = vmrun_interception,
4113 [SVM_EXIT_VMMCALL] = vmmcall_interception,
4114 [SVM_EXIT_VMLOAD] = vmload_interception,
4115 [SVM_EXIT_VMSAVE] = vmsave_interception,
4116 [SVM_EXIT_STGI] = stgi_interception,
4117 [SVM_EXIT_CLGI] = clgi_interception,
4118 [SVM_EXIT_SKINIT] = skinit_interception,
4119 [SVM_EXIT_WBINVD] = wbinvd_interception,
4120 [SVM_EXIT_MONITOR] = monitor_interception,
4121 [SVM_EXIT_MWAIT] = mwait_interception,
4122 [SVM_EXIT_XSETBV] = xsetbv_interception,
4123 [SVM_EXIT_NPF] = pf_interception,
4124 [SVM_EXIT_RSM] = emulate_on_interception,
4125 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
4126 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
4127 };
4128
4129 static void dump_vmcb(struct kvm_vcpu *vcpu)
4130 {
4131 struct vcpu_svm *svm = to_svm(vcpu);
4132 struct vmcb_control_area *control = &svm->vmcb->control;
4133 struct vmcb_save_area *save = &svm->vmcb->save;
4134
4135 pr_err("VMCB Control Area:\n");
4136 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
4137 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
4138 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
4139 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
4140 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
4141 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
4142 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
4143 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
4144 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
4145 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
4146 pr_err("%-20s%d\n", "asid:", control->asid);
4147 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
4148 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
4149 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
4150 pr_err("%-20s%08x\n", "int_state:", control->int_state);
4151 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
4152 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
4153 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
4154 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
4155 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
4156 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
4157 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
4158 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
4159 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
4160 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
4161 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
4162 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
4163 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
4164 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
4165 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
4166 pr_err("VMCB State Save Area:\n");
4167 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4168 "es:",
4169 save->es.selector, save->es.attrib,
4170 save->es.limit, save->es.base);
4171 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4172 "cs:",
4173 save->cs.selector, save->cs.attrib,
4174 save->cs.limit, save->cs.base);
4175 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4176 "ss:",
4177 save->ss.selector, save->ss.attrib,
4178 save->ss.limit, save->ss.base);
4179 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4180 "ds:",
4181 save->ds.selector, save->ds.attrib,
4182 save->ds.limit, save->ds.base);
4183 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4184 "fs:",
4185 save->fs.selector, save->fs.attrib,
4186 save->fs.limit, save->fs.base);
4187 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4188 "gs:",
4189 save->gs.selector, save->gs.attrib,
4190 save->gs.limit, save->gs.base);
4191 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4192 "gdtr:",
4193 save->gdtr.selector, save->gdtr.attrib,
4194 save->gdtr.limit, save->gdtr.base);
4195 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4196 "ldtr:",
4197 save->ldtr.selector, save->ldtr.attrib,
4198 save->ldtr.limit, save->ldtr.base);
4199 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4200 "idtr:",
4201 save->idtr.selector, save->idtr.attrib,
4202 save->idtr.limit, save->idtr.base);
4203 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
4204 "tr:",
4205 save->tr.selector, save->tr.attrib,
4206 save->tr.limit, save->tr.base);
4207 pr_err("cpl: %d efer: %016llx\n",
4208 save->cpl, save->efer);
4209 pr_err("%-15s %016llx %-13s %016llx\n",
4210 "cr0:", save->cr0, "cr2:", save->cr2);
4211 pr_err("%-15s %016llx %-13s %016llx\n",
4212 "cr3:", save->cr3, "cr4:", save->cr4);
4213 pr_err("%-15s %016llx %-13s %016llx\n",
4214 "dr6:", save->dr6, "dr7:", save->dr7);
4215 pr_err("%-15s %016llx %-13s %016llx\n",
4216 "rip:", save->rip, "rflags:", save->rflags);
4217 pr_err("%-15s %016llx %-13s %016llx\n",
4218 "rsp:", save->rsp, "rax:", save->rax);
4219 pr_err("%-15s %016llx %-13s %016llx\n",
4220 "star:", save->star, "lstar:", save->lstar);
4221 pr_err("%-15s %016llx %-13s %016llx\n",
4222 "cstar:", save->cstar, "sfmask:", save->sfmask);
4223 pr_err("%-15s %016llx %-13s %016llx\n",
4224 "kernel_gs_base:", save->kernel_gs_base,
4225 "sysenter_cs:", save->sysenter_cs);
4226 pr_err("%-15s %016llx %-13s %016llx\n",
4227 "sysenter_esp:", save->sysenter_esp,
4228 "sysenter_eip:", save->sysenter_eip);
4229 pr_err("%-15s %016llx %-13s %016llx\n",
4230 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
4231 pr_err("%-15s %016llx %-13s %016llx\n",
4232 "br_from:", save->br_from, "br_to:", save->br_to);
4233 pr_err("%-15s %016llx %-13s %016llx\n",
4234 "excp_from:", save->last_excp_from,
4235 "excp_to:", save->last_excp_to);
4236 }
4237
4238 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
4239 {
4240 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
4241
4242 *info1 = control->exit_info_1;
4243 *info2 = control->exit_info_2;
4244 }
4245
4246 static int handle_exit(struct kvm_vcpu *vcpu)
4247 {
4248 struct vcpu_svm *svm = to_svm(vcpu);
4249 struct kvm_run *kvm_run = vcpu->run;
4250 u32 exit_code = svm->vmcb->control.exit_code;
4251
4252 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
4253
4254 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
4255 vcpu->arch.cr0 = svm->vmcb->save.cr0;
4256 if (npt_enabled)
4257 vcpu->arch.cr3 = svm->vmcb->save.cr3;
4258
4259 if (unlikely(svm->nested.exit_required)) {
4260 nested_svm_vmexit(svm);
4261 svm->nested.exit_required = false;
4262
4263 return 1;
4264 }
4265
4266 if (is_guest_mode(vcpu)) {
4267 int vmexit;
4268
4269 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
4270 svm->vmcb->control.exit_info_1,
4271 svm->vmcb->control.exit_info_2,
4272 svm->vmcb->control.exit_int_info,
4273 svm->vmcb->control.exit_int_info_err,
4274 KVM_ISA_SVM);
4275
4276 vmexit = nested_svm_exit_special(svm);
4277
4278 if (vmexit == NESTED_EXIT_CONTINUE)
4279 vmexit = nested_svm_exit_handled(svm);
4280
4281 if (vmexit == NESTED_EXIT_DONE)
4282 return 1;
4283 }
4284
4285 svm_complete_interrupts(svm);
4286
4287 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
4288 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
4289 kvm_run->fail_entry.hardware_entry_failure_reason
4290 = svm->vmcb->control.exit_code;
4291 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
4292 dump_vmcb(vcpu);
4293 return 0;
4294 }
4295
4296 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
4297 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
4298 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
4299 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
4300 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
4301 "exit_code 0x%x\n",
4302 __func__, svm->vmcb->control.exit_int_info,
4303 exit_code);
4304
4305 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
4306 || !svm_exit_handlers[exit_code]) {
4307 WARN_ONCE(1, "svm: unexpected exit reason 0x%x\n", exit_code);
4308 kvm_queue_exception(vcpu, UD_VECTOR);
4309 return 1;
4310 }
4311
4312 return svm_exit_handlers[exit_code](svm);
4313 }
4314
4315 static void reload_tss(struct kvm_vcpu *vcpu)
4316 {
4317 int cpu = raw_smp_processor_id();
4318
4319 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4320 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
4321 load_TR_desc();
4322 }
4323
4324 static void pre_svm_run(struct vcpu_svm *svm)
4325 {
4326 int cpu = raw_smp_processor_id();
4327
4328 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
4329
4330 /* FIXME: handle wraparound of asid_generation */
4331 if (svm->asid_generation != sd->asid_generation)
4332 new_asid(svm, sd);
4333 }
4334
4335 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
4336 {
4337 struct vcpu_svm *svm = to_svm(vcpu);
4338
4339 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
4340 vcpu->arch.hflags |= HF_NMI_MASK;
4341 set_intercept(svm, INTERCEPT_IRET);
4342 ++vcpu->stat.nmi_injections;
4343 }
4344
4345 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
4346 {
4347 struct vmcb_control_area *control;
4348
4349 /* The following fields are ignored when AVIC is enabled */
4350 control = &svm->vmcb->control;
4351 control->int_vector = irq;
4352 control->int_ctl &= ~V_INTR_PRIO_MASK;
4353 control->int_ctl |= V_IRQ_MASK |
4354 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
4355 mark_dirty(svm->vmcb, VMCB_INTR);
4356 }
4357
4358 static void svm_set_irq(struct kvm_vcpu *vcpu)
4359 {
4360 struct vcpu_svm *svm = to_svm(vcpu);
4361
4362 BUG_ON(!(gif_set(svm)));
4363
4364 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
4365 ++vcpu->stat.irq_injections;
4366
4367 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
4368 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
4369 }
4370
4371 static inline bool svm_nested_virtualize_tpr(struct kvm_vcpu *vcpu)
4372 {
4373 return is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK);
4374 }
4375
4376 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
4377 {
4378 struct vcpu_svm *svm = to_svm(vcpu);
4379
4380 if (svm_nested_virtualize_tpr(vcpu) ||
4381 kvm_vcpu_apicv_active(vcpu))
4382 return;
4383
4384 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4385
4386 if (irr == -1)
4387 return;
4388
4389 if (tpr >= irr)
4390 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
4391 }
4392
4393 static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
4394 {
4395 return;
4396 }
4397
4398 static bool svm_get_enable_apicv(void)
4399 {
4400 return avic;
4401 }
4402
4403 static void svm_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
4404 {
4405 }
4406
4407 static void svm_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
4408 {
4409 }
4410
4411 /* Note: Currently only used by Hyper-V. */
4412 static void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4413 {
4414 struct vcpu_svm *svm = to_svm(vcpu);
4415 struct vmcb *vmcb = svm->vmcb;
4416
4417 if (!avic)
4418 return;
4419
4420 vmcb->control.int_ctl &= ~AVIC_ENABLE_MASK;
4421 mark_dirty(vmcb, VMCB_INTR);
4422 }
4423
4424 static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
4425 {
4426 return;
4427 }
4428
4429 static void svm_deliver_avic_intr(struct kvm_vcpu *vcpu, int vec)
4430 {
4431 kvm_lapic_set_irr(vec, vcpu->arch.apic);
4432 smp_mb__after_atomic();
4433
4434 if (avic_vcpu_is_running(vcpu))
4435 wrmsrl(SVM_AVIC_DOORBELL,
4436 kvm_cpu_get_apicid(vcpu->cpu));
4437 else
4438 kvm_vcpu_wake_up(vcpu);
4439 }
4440
4441 static void svm_ir_list_del(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4442 {
4443 unsigned long flags;
4444 struct amd_svm_iommu_ir *cur;
4445
4446 spin_lock_irqsave(&svm->ir_list_lock, flags);
4447 list_for_each_entry(cur, &svm->ir_list, node) {
4448 if (cur->data != pi->ir_data)
4449 continue;
4450 list_del(&cur->node);
4451 kfree(cur);
4452 break;
4453 }
4454 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4455 }
4456
4457 static int svm_ir_list_add(struct vcpu_svm *svm, struct amd_iommu_pi_data *pi)
4458 {
4459 int ret = 0;
4460 unsigned long flags;
4461 struct amd_svm_iommu_ir *ir;
4462
4463 /**
4464 * In some cases, the existing irte is updaed and re-set,
4465 * so we need to check here if it's already been * added
4466 * to the ir_list.
4467 */
4468 if (pi->ir_data && (pi->prev_ga_tag != 0)) {
4469 struct kvm *kvm = svm->vcpu.kvm;
4470 u32 vcpu_id = AVIC_GATAG_TO_VCPUID(pi->prev_ga_tag);
4471 struct kvm_vcpu *prev_vcpu = kvm_get_vcpu_by_id(kvm, vcpu_id);
4472 struct vcpu_svm *prev_svm;
4473
4474 if (!prev_vcpu) {
4475 ret = -EINVAL;
4476 goto out;
4477 }
4478
4479 prev_svm = to_svm(prev_vcpu);
4480 svm_ir_list_del(prev_svm, pi);
4481 }
4482
4483 /**
4484 * Allocating new amd_iommu_pi_data, which will get
4485 * add to the per-vcpu ir_list.
4486 */
4487 ir = kzalloc(sizeof(struct amd_svm_iommu_ir), GFP_KERNEL);
4488 if (!ir) {
4489 ret = -ENOMEM;
4490 goto out;
4491 }
4492 ir->data = pi->ir_data;
4493
4494 spin_lock_irqsave(&svm->ir_list_lock, flags);
4495 list_add(&ir->node, &svm->ir_list);
4496 spin_unlock_irqrestore(&svm->ir_list_lock, flags);
4497 out:
4498 return ret;
4499 }
4500
4501 /**
4502 * Note:
4503 * The HW cannot support posting multicast/broadcast
4504 * interrupts to a vCPU. So, we still use legacy interrupt
4505 * remapping for these kind of interrupts.
4506 *
4507 * For lowest-priority interrupts, we only support
4508 * those with single CPU as the destination, e.g. user
4509 * configures the interrupts via /proc/irq or uses
4510 * irqbalance to make the interrupts single-CPU.
4511 */
4512 static int
4513 get_pi_vcpu_info(struct kvm *kvm, struct kvm_kernel_irq_routing_entry *e,
4514 struct vcpu_data *vcpu_info, struct vcpu_svm **svm)
4515 {
4516 struct kvm_lapic_irq irq;
4517 struct kvm_vcpu *vcpu = NULL;
4518
4519 kvm_set_msi_irq(kvm, e, &irq);
4520
4521 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
4522 pr_debug("SVM: %s: use legacy intr remap mode for irq %u\n",
4523 __func__, irq.vector);
4524 return -1;
4525 }
4526
4527 pr_debug("SVM: %s: use GA mode for irq %u\n", __func__,
4528 irq.vector);
4529 *svm = to_svm(vcpu);
4530 vcpu_info->pi_desc_addr = __sme_set(page_to_phys((*svm)->avic_backing_page));
4531 vcpu_info->vector = irq.vector;
4532
4533 return 0;
4534 }
4535
4536 /*
4537 * svm_update_pi_irte - set IRTE for Posted-Interrupts
4538 *
4539 * @kvm: kvm
4540 * @host_irq: host irq of the interrupt
4541 * @guest_irq: gsi of the interrupt
4542 * @set: set or unset PI
4543 * returns 0 on success, < 0 on failure
4544 */
4545 static int svm_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
4546 uint32_t guest_irq, bool set)
4547 {
4548 struct kvm_kernel_irq_routing_entry *e;
4549 struct kvm_irq_routing_table *irq_rt;
4550 int idx, ret = -EINVAL;
4551
4552 if (!kvm_arch_has_assigned_device(kvm) ||
4553 !irq_remapping_cap(IRQ_POSTING_CAP))
4554 return 0;
4555
4556 pr_debug("SVM: %s: host_irq=%#x, guest_irq=%#x, set=%#x\n",
4557 __func__, host_irq, guest_irq, set);
4558
4559 idx = srcu_read_lock(&kvm->irq_srcu);
4560 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
4561 WARN_ON(guest_irq >= irq_rt->nr_rt_entries);
4562
4563 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
4564 struct vcpu_data vcpu_info;
4565 struct vcpu_svm *svm = NULL;
4566
4567 if (e->type != KVM_IRQ_ROUTING_MSI)
4568 continue;
4569
4570 /**
4571 * Here, we setup with legacy mode in the following cases:
4572 * 1. When cannot target interrupt to a specific vcpu.
4573 * 2. Unsetting posted interrupt.
4574 * 3. APIC virtialization is disabled for the vcpu.
4575 */
4576 if (!get_pi_vcpu_info(kvm, e, &vcpu_info, &svm) && set &&
4577 kvm_vcpu_apicv_active(&svm->vcpu)) {
4578 struct amd_iommu_pi_data pi;
4579
4580 /* Try to enable guest_mode in IRTE */
4581 pi.base = __sme_set(page_to_phys(svm->avic_backing_page) &
4582 AVIC_HPA_MASK);
4583 pi.ga_tag = AVIC_GATAG(kvm->arch.avic_vm_id,
4584 svm->vcpu.vcpu_id);
4585 pi.is_guest_mode = true;
4586 pi.vcpu_data = &vcpu_info;
4587 ret = irq_set_vcpu_affinity(host_irq, &pi);
4588
4589 /**
4590 * Here, we successfully setting up vcpu affinity in
4591 * IOMMU guest mode. Now, we need to store the posted
4592 * interrupt information in a per-vcpu ir_list so that
4593 * we can reference to them directly when we update vcpu
4594 * scheduling information in IOMMU irte.
4595 */
4596 if (!ret && pi.is_guest_mode)
4597 svm_ir_list_add(svm, &pi);
4598 } else {
4599 /* Use legacy mode in IRTE */
4600 struct amd_iommu_pi_data pi;
4601
4602 /**
4603 * Here, pi is used to:
4604 * - Tell IOMMU to use legacy mode for this interrupt.
4605 * - Retrieve ga_tag of prior interrupt remapping data.
4606 */
4607 pi.is_guest_mode = false;
4608 ret = irq_set_vcpu_affinity(host_irq, &pi);
4609
4610 /**
4611 * Check if the posted interrupt was previously
4612 * setup with the guest_mode by checking if the ga_tag
4613 * was cached. If so, we need to clean up the per-vcpu
4614 * ir_list.
4615 */
4616 if (!ret && pi.prev_ga_tag) {
4617 int id = AVIC_GATAG_TO_VCPUID(pi.prev_ga_tag);
4618 struct kvm_vcpu *vcpu;
4619
4620 vcpu = kvm_get_vcpu_by_id(kvm, id);
4621 if (vcpu)
4622 svm_ir_list_del(to_svm(vcpu), &pi);
4623 }
4624 }
4625
4626 if (!ret && svm) {
4627 trace_kvm_pi_irte_update(svm->vcpu.vcpu_id,
4628 host_irq, e->gsi,
4629 vcpu_info.vector,
4630 vcpu_info.pi_desc_addr, set);
4631 }
4632
4633 if (ret < 0) {
4634 pr_err("%s: failed to update PI IRTE\n", __func__);
4635 goto out;
4636 }
4637 }
4638
4639 ret = 0;
4640 out:
4641 srcu_read_unlock(&kvm->irq_srcu, idx);
4642 return ret;
4643 }
4644
4645 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
4646 {
4647 struct vcpu_svm *svm = to_svm(vcpu);
4648 struct vmcb *vmcb = svm->vmcb;
4649 int ret;
4650 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
4651 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
4652 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
4653
4654 return ret;
4655 }
4656
4657 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
4658 {
4659 struct vcpu_svm *svm = to_svm(vcpu);
4660
4661 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
4662 }
4663
4664 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4665 {
4666 struct vcpu_svm *svm = to_svm(vcpu);
4667
4668 if (masked) {
4669 svm->vcpu.arch.hflags |= HF_NMI_MASK;
4670 set_intercept(svm, INTERCEPT_IRET);
4671 } else {
4672 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
4673 clr_intercept(svm, INTERCEPT_IRET);
4674 }
4675 }
4676
4677 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
4678 {
4679 struct vcpu_svm *svm = to_svm(vcpu);
4680 struct vmcb *vmcb = svm->vmcb;
4681 int ret;
4682
4683 if (!gif_set(svm) ||
4684 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
4685 return 0;
4686
4687 ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
4688
4689 if (is_guest_mode(vcpu))
4690 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
4691
4692 return ret;
4693 }
4694
4695 static void enable_irq_window(struct kvm_vcpu *vcpu)
4696 {
4697 struct vcpu_svm *svm = to_svm(vcpu);
4698
4699 if (kvm_vcpu_apicv_active(vcpu))
4700 return;
4701
4702 /*
4703 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
4704 * 1, because that's a separate STGI/VMRUN intercept. The next time we
4705 * get that intercept, this function will be called again though and
4706 * we'll get the vintr intercept. However, if the vGIF feature is
4707 * enabled, the STGI interception will not occur. Enable the irq
4708 * window under the assumption that the hardware will set the GIF.
4709 */
4710 if ((vgif_enabled(svm) || gif_set(svm)) && nested_svm_intr(svm)) {
4711 svm_set_vintr(svm);
4712 svm_inject_irq(svm, 0x0);
4713 }
4714 }
4715
4716 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4717 {
4718 struct vcpu_svm *svm = to_svm(vcpu);
4719
4720 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
4721 == HF_NMI_MASK)
4722 return; /* IRET will cause a vm exit */
4723
4724 if (!gif_set(svm)) {
4725 if (vgif_enabled(svm))
4726 set_intercept(svm, INTERCEPT_STGI);
4727 return; /* STGI will cause a vm exit */
4728 }
4729
4730 if (svm->nested.exit_required)
4731 return; /* we're not going to run the guest yet */
4732
4733 /*
4734 * Something prevents NMI from been injected. Single step over possible
4735 * problem (IRET or exception injection or interrupt shadow)
4736 */
4737 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
4738 svm->nmi_singlestep = true;
4739 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
4740 }
4741
4742 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
4743 {
4744 return 0;
4745 }
4746
4747 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
4748 {
4749 struct vcpu_svm *svm = to_svm(vcpu);
4750
4751 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
4752 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
4753 else
4754 svm->asid_generation--;
4755 }
4756
4757 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
4758 {
4759 }
4760
4761 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
4762 {
4763 struct vcpu_svm *svm = to_svm(vcpu);
4764
4765 if (svm_nested_virtualize_tpr(vcpu))
4766 return;
4767
4768 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
4769 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
4770 kvm_set_cr8(vcpu, cr8);
4771 }
4772 }
4773
4774 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
4775 {
4776 struct vcpu_svm *svm = to_svm(vcpu);
4777 u64 cr8;
4778
4779 if (svm_nested_virtualize_tpr(vcpu) ||
4780 kvm_vcpu_apicv_active(vcpu))
4781 return;
4782
4783 cr8 = kvm_get_cr8(vcpu);
4784 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
4785 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
4786 }
4787
4788 static void svm_complete_interrupts(struct vcpu_svm *svm)
4789 {
4790 u8 vector;
4791 int type;
4792 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4793 unsigned int3_injected = svm->int3_injected;
4794
4795 svm->int3_injected = 0;
4796
4797 /*
4798 * If we've made progress since setting HF_IRET_MASK, we've
4799 * executed an IRET and can allow NMI injection.
4800 */
4801 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
4802 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
4803 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
4804 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4805 }
4806
4807 svm->vcpu.arch.nmi_injected = false;
4808 kvm_clear_exception_queue(&svm->vcpu);
4809 kvm_clear_interrupt_queue(&svm->vcpu);
4810
4811 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4812 return;
4813
4814 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
4815
4816 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4817 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4818
4819 switch (type) {
4820 case SVM_EXITINTINFO_TYPE_NMI:
4821 svm->vcpu.arch.nmi_injected = true;
4822 break;
4823 case SVM_EXITINTINFO_TYPE_EXEPT:
4824 /*
4825 * In case of software exceptions, do not reinject the vector,
4826 * but re-execute the instruction instead. Rewind RIP first
4827 * if we emulated INT3 before.
4828 */
4829 if (kvm_exception_is_soft(vector)) {
4830 if (vector == BP_VECTOR && int3_injected &&
4831 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
4832 kvm_rip_write(&svm->vcpu,
4833 kvm_rip_read(&svm->vcpu) -
4834 int3_injected);
4835 break;
4836 }
4837 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4838 u32 err = svm->vmcb->control.exit_int_info_err;
4839 kvm_requeue_exception_e(&svm->vcpu, vector, err);
4840
4841 } else
4842 kvm_requeue_exception(&svm->vcpu, vector);
4843 break;
4844 case SVM_EXITINTINFO_TYPE_INTR:
4845 kvm_queue_interrupt(&svm->vcpu, vector, false);
4846 break;
4847 default:
4848 break;
4849 }
4850 }
4851
4852 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4853 {
4854 struct vcpu_svm *svm = to_svm(vcpu);
4855 struct vmcb_control_area *control = &svm->vmcb->control;
4856
4857 control->exit_int_info = control->event_inj;
4858 control->exit_int_info_err = control->event_inj_err;
4859 control->event_inj = 0;
4860 svm_complete_interrupts(svm);
4861 }
4862
4863 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
4864 {
4865 struct vcpu_svm *svm = to_svm(vcpu);
4866
4867 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4868 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4869 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4870
4871 /*
4872 * A vmexit emulation is required before the vcpu can be executed
4873 * again.
4874 */
4875 if (unlikely(svm->nested.exit_required))
4876 return;
4877
4878 /*
4879 * Disable singlestep if we're injecting an interrupt/exception.
4880 * We don't want our modified rflags to be pushed on the stack where
4881 * we might not be able to easily reset them if we disabled NMI
4882 * singlestep later.
4883 */
4884 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4885 /*
4886 * Event injection happens before external interrupts cause a
4887 * vmexit and interrupts are disabled here, so smp_send_reschedule
4888 * is enough to force an immediate vmexit.
4889 */
4890 disable_nmi_singlestep(svm);
4891 smp_send_reschedule(vcpu->cpu);
4892 }
4893
4894 pre_svm_run(svm);
4895
4896 sync_lapic_to_cr8(vcpu);
4897
4898 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4899
4900 clgi();
4901
4902 local_irq_enable();
4903
4904 asm volatile (
4905 "push %%" _ASM_BP "; \n\t"
4906 "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
4907 "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
4908 "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
4909 "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
4910 "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
4911 "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
4912 #ifdef CONFIG_X86_64
4913 "mov %c[r8](%[svm]), %%r8 \n\t"
4914 "mov %c[r9](%[svm]), %%r9 \n\t"
4915 "mov %c[r10](%[svm]), %%r10 \n\t"
4916 "mov %c[r11](%[svm]), %%r11 \n\t"
4917 "mov %c[r12](%[svm]), %%r12 \n\t"
4918 "mov %c[r13](%[svm]), %%r13 \n\t"
4919 "mov %c[r14](%[svm]), %%r14 \n\t"
4920 "mov %c[r15](%[svm]), %%r15 \n\t"
4921 #endif
4922
4923 /* Enter guest mode */
4924 "push %%" _ASM_AX " \n\t"
4925 "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
4926 __ex(SVM_VMLOAD) "\n\t"
4927 __ex(SVM_VMRUN) "\n\t"
4928 __ex(SVM_VMSAVE) "\n\t"
4929 "pop %%" _ASM_AX " \n\t"
4930
4931 /* Save guest registers, load host registers */
4932 "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
4933 "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
4934 "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
4935 "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
4936 "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
4937 "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
4938 #ifdef CONFIG_X86_64
4939 "mov %%r8, %c[r8](%[svm]) \n\t"
4940 "mov %%r9, %c[r9](%[svm]) \n\t"
4941 "mov %%r10, %c[r10](%[svm]) \n\t"
4942 "mov %%r11, %c[r11](%[svm]) \n\t"
4943 "mov %%r12, %c[r12](%[svm]) \n\t"
4944 "mov %%r13, %c[r13](%[svm]) \n\t"
4945 "mov %%r14, %c[r14](%[svm]) \n\t"
4946 "mov %%r15, %c[r15](%[svm]) \n\t"
4947 #endif
4948 "pop %%" _ASM_BP
4949 :
4950 : [svm]"a"(svm),
4951 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
4952 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
4953 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
4954 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
4955 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
4956 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
4957 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
4958 #ifdef CONFIG_X86_64
4959 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
4960 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
4961 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
4962 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
4963 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
4964 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
4965 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
4966 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
4967 #endif
4968 : "cc", "memory"
4969 #ifdef CONFIG_X86_64
4970 , "rbx", "rcx", "rdx", "rsi", "rdi"
4971 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
4972 #else
4973 , "ebx", "ecx", "edx", "esi", "edi"
4974 #endif
4975 );
4976
4977 #ifdef CONFIG_X86_64
4978 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
4979 #else
4980 loadsegment(fs, svm->host.fs);
4981 #ifndef CONFIG_X86_32_LAZY_GS
4982 loadsegment(gs, svm->host.gs);
4983 #endif
4984 #endif
4985
4986 reload_tss(vcpu);
4987
4988 local_irq_disable();
4989
4990 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4991 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4992 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4993 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4994
4995 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4996 kvm_before_handle_nmi(&svm->vcpu);
4997
4998 stgi();
4999
5000 /* Any pending NMI will happen here */
5001
5002 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
5003 kvm_after_handle_nmi(&svm->vcpu);
5004
5005 sync_cr8_to_lapic(vcpu);
5006
5007 svm->next_rip = 0;
5008
5009 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
5010
5011 /* if exit due to PF check for async PF */
5012 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
5013 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
5014
5015 if (npt_enabled) {
5016 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
5017 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
5018 }
5019
5020 /*
5021 * We need to handle MC intercepts here before the vcpu has a chance to
5022 * change the physical cpu
5023 */
5024 if (unlikely(svm->vmcb->control.exit_code ==
5025 SVM_EXIT_EXCP_BASE + MC_VECTOR))
5026 svm_handle_mce(svm);
5027
5028 mark_all_clean(svm->vmcb);
5029 }
5030 STACK_FRAME_NON_STANDARD(svm_vcpu_run);
5031
5032 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5033 {
5034 struct vcpu_svm *svm = to_svm(vcpu);
5035
5036 svm->vmcb->save.cr3 = __sme_set(root);
5037 mark_dirty(svm->vmcb, VMCB_CR);
5038 svm_flush_tlb(vcpu);
5039 }
5040
5041 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
5042 {
5043 struct vcpu_svm *svm = to_svm(vcpu);
5044
5045 svm->vmcb->control.nested_cr3 = __sme_set(root);
5046 mark_dirty(svm->vmcb, VMCB_NPT);
5047
5048 /* Also sync guest cr3 here in case we live migrate */
5049 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
5050 mark_dirty(svm->vmcb, VMCB_CR);
5051
5052 svm_flush_tlb(vcpu);
5053 }
5054
5055 static int is_disabled(void)
5056 {
5057 u64 vm_cr;
5058
5059 rdmsrl(MSR_VM_CR, vm_cr);
5060 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
5061 return 1;
5062
5063 return 0;
5064 }
5065
5066 static void
5067 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5068 {
5069 /*
5070 * Patch in the VMMCALL instruction:
5071 */
5072 hypercall[0] = 0x0f;
5073 hypercall[1] = 0x01;
5074 hypercall[2] = 0xd9;
5075 }
5076
5077 static void svm_check_processor_compat(void *rtn)
5078 {
5079 *(int *)rtn = 0;
5080 }
5081
5082 static bool svm_cpu_has_accelerated_tpr(void)
5083 {
5084 return false;
5085 }
5086
5087 static bool svm_has_high_real_mode_segbase(void)
5088 {
5089 return true;
5090 }
5091
5092 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
5093 {
5094 return 0;
5095 }
5096
5097 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
5098 {
5099 struct vcpu_svm *svm = to_svm(vcpu);
5100
5101 /* Update nrips enabled cache */
5102 svm->nrips_enabled = !!guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
5103
5104 if (!kvm_vcpu_apicv_active(vcpu))
5105 return;
5106
5107 guest_cpuid_clear(vcpu, X86_FEATURE_X2APIC);
5108 }
5109
5110 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5111 {
5112 switch (func) {
5113 case 0x1:
5114 if (avic)
5115 entry->ecx &= ~bit(X86_FEATURE_X2APIC);
5116 break;
5117 case 0x80000001:
5118 if (nested)
5119 entry->ecx |= (1 << 2); /* Set SVM bit */
5120 break;
5121 case 0x8000000A:
5122 entry->eax = 1; /* SVM revision 1 */
5123 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
5124 ASID emulation to nested SVM */
5125 entry->ecx = 0; /* Reserved */
5126 entry->edx = 0; /* Per default do not support any
5127 additional features */
5128
5129 /* Support next_rip if host supports it */
5130 if (boot_cpu_has(X86_FEATURE_NRIPS))
5131 entry->edx |= SVM_FEATURE_NRIP;
5132
5133 /* Support NPT for the guest if enabled */
5134 if (npt_enabled)
5135 entry->edx |= SVM_FEATURE_NPT;
5136
5137 break;
5138 }
5139 }
5140
5141 static int svm_get_lpage_level(void)
5142 {
5143 return PT_PDPE_LEVEL;
5144 }
5145
5146 static bool svm_rdtscp_supported(void)
5147 {
5148 return boot_cpu_has(X86_FEATURE_RDTSCP);
5149 }
5150
5151 static bool svm_invpcid_supported(void)
5152 {
5153 return false;
5154 }
5155
5156 static bool svm_mpx_supported(void)
5157 {
5158 return false;
5159 }
5160
5161 static bool svm_xsaves_supported(void)
5162 {
5163 return false;
5164 }
5165
5166 static bool svm_has_wbinvd_exit(void)
5167 {
5168 return true;
5169 }
5170
5171 #define PRE_EX(exit) { .exit_code = (exit), \
5172 .stage = X86_ICPT_PRE_EXCEPT, }
5173 #define POST_EX(exit) { .exit_code = (exit), \
5174 .stage = X86_ICPT_POST_EXCEPT, }
5175 #define POST_MEM(exit) { .exit_code = (exit), \
5176 .stage = X86_ICPT_POST_MEMACCESS, }
5177
5178 static const struct __x86_intercept {
5179 u32 exit_code;
5180 enum x86_intercept_stage stage;
5181 } x86_intercept_map[] = {
5182 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
5183 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
5184 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
5185 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
5186 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
5187 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
5188 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
5189 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
5190 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
5191 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
5192 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
5193 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
5194 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
5195 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
5196 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
5197 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
5198 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
5199 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
5200 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
5201 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
5202 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
5203 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
5204 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
5205 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
5206 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
5207 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
5208 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
5209 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
5210 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
5211 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
5212 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
5213 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
5214 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
5215 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
5216 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
5217 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
5218 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
5219 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
5220 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
5221 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
5222 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
5223 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
5224 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
5225 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
5226 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
5227 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
5228 };
5229
5230 #undef PRE_EX
5231 #undef POST_EX
5232 #undef POST_MEM
5233
5234 static int svm_check_intercept(struct kvm_vcpu *vcpu,
5235 struct x86_instruction_info *info,
5236 enum x86_intercept_stage stage)
5237 {
5238 struct vcpu_svm *svm = to_svm(vcpu);
5239 int vmexit, ret = X86EMUL_CONTINUE;
5240 struct __x86_intercept icpt_info;
5241 struct vmcb *vmcb = svm->vmcb;
5242
5243 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
5244 goto out;
5245
5246 icpt_info = x86_intercept_map[info->intercept];
5247
5248 if (stage != icpt_info.stage)
5249 goto out;
5250
5251 switch (icpt_info.exit_code) {
5252 case SVM_EXIT_READ_CR0:
5253 if (info->intercept == x86_intercept_cr_read)
5254 icpt_info.exit_code += info->modrm_reg;
5255 break;
5256 case SVM_EXIT_WRITE_CR0: {
5257 unsigned long cr0, val;
5258 u64 intercept;
5259
5260 if (info->intercept == x86_intercept_cr_write)
5261 icpt_info.exit_code += info->modrm_reg;
5262
5263 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
5264 info->intercept == x86_intercept_clts)
5265 break;
5266
5267 intercept = svm->nested.intercept;
5268
5269 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
5270 break;
5271
5272 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
5273 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
5274
5275 if (info->intercept == x86_intercept_lmsw) {
5276 cr0 &= 0xfUL;
5277 val &= 0xfUL;
5278 /* lmsw can't clear PE - catch this here */
5279 if (cr0 & X86_CR0_PE)
5280 val |= X86_CR0_PE;
5281 }
5282
5283 if (cr0 ^ val)
5284 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
5285
5286 break;
5287 }
5288 case SVM_EXIT_READ_DR0:
5289 case SVM_EXIT_WRITE_DR0:
5290 icpt_info.exit_code += info->modrm_reg;
5291 break;
5292 case SVM_EXIT_MSR:
5293 if (info->intercept == x86_intercept_wrmsr)
5294 vmcb->control.exit_info_1 = 1;
5295 else
5296 vmcb->control.exit_info_1 = 0;
5297 break;
5298 case SVM_EXIT_PAUSE:
5299 /*
5300 * We get this for NOP only, but pause
5301 * is rep not, check this here
5302 */
5303 if (info->rep_prefix != REPE_PREFIX)
5304 goto out;
5305 case SVM_EXIT_IOIO: {
5306 u64 exit_info;
5307 u32 bytes;
5308
5309 if (info->intercept == x86_intercept_in ||
5310 info->intercept == x86_intercept_ins) {
5311 exit_info = ((info->src_val & 0xffff) << 16) |
5312 SVM_IOIO_TYPE_MASK;
5313 bytes = info->dst_bytes;
5314 } else {
5315 exit_info = (info->dst_val & 0xffff) << 16;
5316 bytes = info->src_bytes;
5317 }
5318
5319 if (info->intercept == x86_intercept_outs ||
5320 info->intercept == x86_intercept_ins)
5321 exit_info |= SVM_IOIO_STR_MASK;
5322
5323 if (info->rep_prefix)
5324 exit_info |= SVM_IOIO_REP_MASK;
5325
5326 bytes = min(bytes, 4u);
5327
5328 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
5329
5330 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
5331
5332 vmcb->control.exit_info_1 = exit_info;
5333 vmcb->control.exit_info_2 = info->next_rip;
5334
5335 break;
5336 }
5337 default:
5338 break;
5339 }
5340
5341 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
5342 if (static_cpu_has(X86_FEATURE_NRIPS))
5343 vmcb->control.next_rip = info->next_rip;
5344 vmcb->control.exit_code = icpt_info.exit_code;
5345 vmexit = nested_svm_exit_handled(svm);
5346
5347 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
5348 : X86EMUL_CONTINUE;
5349
5350 out:
5351 return ret;
5352 }
5353
5354 static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
5355 {
5356 local_irq_enable();
5357 /*
5358 * We must have an instruction with interrupts enabled, so
5359 * the timer interrupt isn't delayed by the interrupt shadow.
5360 */
5361 asm("nop");
5362 local_irq_disable();
5363 }
5364
5365 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
5366 {
5367 }
5368
5369 static inline void avic_post_state_restore(struct kvm_vcpu *vcpu)
5370 {
5371 if (avic_handle_apic_id_update(vcpu) != 0)
5372 return;
5373 if (avic_handle_dfr_update(vcpu) != 0)
5374 return;
5375 avic_handle_ldr_update(vcpu);
5376 }
5377
5378 static void svm_setup_mce(struct kvm_vcpu *vcpu)
5379 {
5380 /* [63:9] are reserved. */
5381 vcpu->arch.mcg_cap &= 0x1ff;
5382 }
5383
5384 static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
5385 .cpu_has_kvm_support = has_svm,
5386 .disabled_by_bios = is_disabled,
5387 .hardware_setup = svm_hardware_setup,
5388 .hardware_unsetup = svm_hardware_unsetup,
5389 .check_processor_compatibility = svm_check_processor_compat,
5390 .hardware_enable = svm_hardware_enable,
5391 .hardware_disable = svm_hardware_disable,
5392 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
5393 .cpu_has_high_real_mode_segbase = svm_has_high_real_mode_segbase,
5394
5395 .vcpu_create = svm_create_vcpu,
5396 .vcpu_free = svm_free_vcpu,
5397 .vcpu_reset = svm_vcpu_reset,
5398
5399 .vm_init = avic_vm_init,
5400 .vm_destroy = avic_vm_destroy,
5401
5402 .prepare_guest_switch = svm_prepare_guest_switch,
5403 .vcpu_load = svm_vcpu_load,
5404 .vcpu_put = svm_vcpu_put,
5405 .vcpu_blocking = svm_vcpu_blocking,
5406 .vcpu_unblocking = svm_vcpu_unblocking,
5407
5408 .update_bp_intercept = update_bp_intercept,
5409 .get_msr = svm_get_msr,
5410 .set_msr = svm_set_msr,
5411 .get_segment_base = svm_get_segment_base,
5412 .get_segment = svm_get_segment,
5413 .set_segment = svm_set_segment,
5414 .get_cpl = svm_get_cpl,
5415 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
5416 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
5417 .decache_cr3 = svm_decache_cr3,
5418 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
5419 .set_cr0 = svm_set_cr0,
5420 .set_cr3 = svm_set_cr3,
5421 .set_cr4 = svm_set_cr4,
5422 .set_efer = svm_set_efer,
5423 .get_idt = svm_get_idt,
5424 .set_idt = svm_set_idt,
5425 .get_gdt = svm_get_gdt,
5426 .set_gdt = svm_set_gdt,
5427 .get_dr6 = svm_get_dr6,
5428 .set_dr6 = svm_set_dr6,
5429 .set_dr7 = svm_set_dr7,
5430 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
5431 .cache_reg = svm_cache_reg,
5432 .get_rflags = svm_get_rflags,
5433 .set_rflags = svm_set_rflags,
5434
5435 .tlb_flush = svm_flush_tlb,
5436
5437 .run = svm_vcpu_run,
5438 .handle_exit = handle_exit,
5439 .skip_emulated_instruction = skip_emulated_instruction,
5440 .set_interrupt_shadow = svm_set_interrupt_shadow,
5441 .get_interrupt_shadow = svm_get_interrupt_shadow,
5442 .patch_hypercall = svm_patch_hypercall,
5443 .set_irq = svm_set_irq,
5444 .set_nmi = svm_inject_nmi,
5445 .queue_exception = svm_queue_exception,
5446 .cancel_injection = svm_cancel_injection,
5447 .interrupt_allowed = svm_interrupt_allowed,
5448 .nmi_allowed = svm_nmi_allowed,
5449 .get_nmi_mask = svm_get_nmi_mask,
5450 .set_nmi_mask = svm_set_nmi_mask,
5451 .enable_nmi_window = enable_nmi_window,
5452 .enable_irq_window = enable_irq_window,
5453 .update_cr8_intercept = update_cr8_intercept,
5454 .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
5455 .get_enable_apicv = svm_get_enable_apicv,
5456 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
5457 .load_eoi_exitmap = svm_load_eoi_exitmap,
5458 .hwapic_irr_update = svm_hwapic_irr_update,
5459 .hwapic_isr_update = svm_hwapic_isr_update,
5460 .apicv_post_state_restore = avic_post_state_restore,
5461
5462 .set_tss_addr = svm_set_tss_addr,
5463 .get_tdp_level = get_npt_level,
5464 .get_mt_mask = svm_get_mt_mask,
5465
5466 .get_exit_info = svm_get_exit_info,
5467
5468 .get_lpage_level = svm_get_lpage_level,
5469
5470 .cpuid_update = svm_cpuid_update,
5471
5472 .rdtscp_supported = svm_rdtscp_supported,
5473 .invpcid_supported = svm_invpcid_supported,
5474 .mpx_supported = svm_mpx_supported,
5475 .xsaves_supported = svm_xsaves_supported,
5476
5477 .set_supported_cpuid = svm_set_supported_cpuid,
5478
5479 .has_wbinvd_exit = svm_has_wbinvd_exit,
5480
5481 .write_tsc_offset = svm_write_tsc_offset,
5482
5483 .set_tdp_cr3 = set_tdp_cr3,
5484
5485 .check_intercept = svm_check_intercept,
5486 .handle_external_intr = svm_handle_external_intr,
5487
5488 .sched_in = svm_sched_in,
5489
5490 .pmu_ops = &amd_pmu_ops,
5491 .deliver_posted_interrupt = svm_deliver_avic_intr,
5492 .update_pi_irte = svm_update_pi_irte,
5493 .setup_mce = svm_setup_mce,
5494 };
5495
5496 static int __init svm_init(void)
5497 {
5498 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
5499 __alignof__(struct vcpu_svm), THIS_MODULE);
5500 }
5501
5502 static void __exit svm_exit(void)
5503 {
5504 kvm_exit();
5505 }
5506
5507 module_init(svm_init)
5508 module_exit(svm_exit)
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