2 * Kernel-based Virtual Machine driver for Linux
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
17 #include <linux/kvm_host.h>
21 #include "kvm_cache_regs.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
32 #include <asm/tlbflush.h>
34 #include <asm/kvm_para.h>
36 #include <asm/virtext.h>
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
56 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
57 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
58 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
60 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
62 static bool erratum_383_found __read_mostly
;
64 static const u32 host_save_user_msrs
[] = {
66 MSR_STAR
, MSR_LSTAR
, MSR_CSTAR
, MSR_SYSCALL_MASK
, MSR_KERNEL_GS_BASE
,
69 MSR_IA32_SYSENTER_CS
, MSR_IA32_SYSENTER_ESP
, MSR_IA32_SYSENTER_EIP
,
72 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
82 /* These are the merged vectors */
85 /* gpa pointers to the real vectors */
89 /* A VMEXIT is required but not yet emulated */
93 * If we vmexit during an instruction emulation we need this to restore
94 * the l1 guest rip after the emulation
96 unsigned long vmexit_rip
;
97 unsigned long vmexit_rsp
;
98 unsigned long vmexit_rax
;
100 /* cache for intercepts of the guest */
103 u32 intercept_exceptions
;
106 /* Nested Paging related state */
110 #define MSRPM_OFFSETS 16
111 static u32 msrpm_offsets
[MSRPM_OFFSETS
] __read_mostly
;
114 struct kvm_vcpu vcpu
;
116 unsigned long vmcb_pa
;
117 struct svm_cpu_data
*svm_data
;
118 uint64_t asid_generation
;
119 uint64_t sysenter_esp
;
120 uint64_t sysenter_eip
;
124 u64 host_user_msrs
[NR_HOST_SAVE_USER_MSRS
];
134 struct nested_state nested
;
138 unsigned int3_injected
;
139 unsigned long int3_rip
;
143 #define MSR_INVALID 0xffffffffU
145 static struct svm_direct_access_msrs
{
146 u32 index
; /* Index of the MSR */
147 bool always
; /* True if intercept is always on */
148 } direct_access_msrs
[] = {
149 { .index
= MSR_STAR
, .always
= true },
150 { .index
= MSR_IA32_SYSENTER_CS
, .always
= true },
152 { .index
= MSR_GS_BASE
, .always
= true },
153 { .index
= MSR_FS_BASE
, .always
= true },
154 { .index
= MSR_KERNEL_GS_BASE
, .always
= true },
155 { .index
= MSR_LSTAR
, .always
= true },
156 { .index
= MSR_CSTAR
, .always
= true },
157 { .index
= MSR_SYSCALL_MASK
, .always
= true },
159 { .index
= MSR_IA32_LASTBRANCHFROMIP
, .always
= false },
160 { .index
= MSR_IA32_LASTBRANCHTOIP
, .always
= false },
161 { .index
= MSR_IA32_LASTINTFROMIP
, .always
= false },
162 { .index
= MSR_IA32_LASTINTTOIP
, .always
= false },
163 { .index
= MSR_INVALID
, .always
= false },
166 /* enable NPT for AMD64 and X86 with PAE */
167 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
168 static bool npt_enabled
= true;
170 static bool npt_enabled
;
174 module_param(npt
, int, S_IRUGO
);
176 static int nested
= 1;
177 module_param(nested
, int, S_IRUGO
);
179 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
);
180 static void svm_complete_interrupts(struct vcpu_svm
*svm
);
182 static int nested_svm_exit_handled(struct vcpu_svm
*svm
);
183 static int nested_svm_intercept(struct vcpu_svm
*svm
);
184 static int nested_svm_vmexit(struct vcpu_svm
*svm
);
185 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
186 bool has_error_code
, u32 error_code
);
192 #define VMCB_ALWAYS_DIRTY_MASK 0U
194 static inline void mark_all_dirty(struct vmcb
*vmcb
)
196 vmcb
->control
.clean
= 0;
199 static inline void mark_all_clean(struct vmcb
*vmcb
)
201 vmcb
->control
.clean
= ((1 << VMCB_DIRTY_MAX
) - 1)
202 & ~VMCB_ALWAYS_DIRTY_MASK
;
205 static inline void mark_dirty(struct vmcb
*vmcb
, int bit
)
207 vmcb
->control
.clean
&= ~(1 << bit
);
210 static inline struct vcpu_svm
*to_svm(struct kvm_vcpu
*vcpu
)
212 return container_of(vcpu
, struct vcpu_svm
, vcpu
);
215 static void recalc_intercepts(struct vcpu_svm
*svm
)
217 struct vmcb_control_area
*c
, *h
;
218 struct nested_state
*g
;
220 if (!is_guest_mode(&svm
->vcpu
))
223 c
= &svm
->vmcb
->control
;
224 h
= &svm
->nested
.hsave
->control
;
227 c
->intercept_cr
= h
->intercept_cr
| g
->intercept_cr
;
228 c
->intercept_dr
= h
->intercept_dr
| g
->intercept_dr
;
229 c
->intercept_exceptions
= h
->intercept_exceptions
| g
->intercept_exceptions
;
230 c
->intercept
= h
->intercept
| g
->intercept
;
233 static inline struct vmcb
*get_host_vmcb(struct vcpu_svm
*svm
)
235 if (is_guest_mode(&svm
->vcpu
))
236 return svm
->nested
.hsave
;
241 static inline void set_cr_intercept(struct vcpu_svm
*svm
, int bit
)
243 struct vmcb
*vmcb
= get_host_vmcb(svm
);
245 vmcb
->control
.intercept_cr
|= (1U << bit
);
247 recalc_intercepts(svm
);
250 static inline void clr_cr_intercept(struct vcpu_svm
*svm
, int bit
)
252 struct vmcb
*vmcb
= get_host_vmcb(svm
);
254 vmcb
->control
.intercept_cr
&= ~(1U << bit
);
256 recalc_intercepts(svm
);
259 static inline bool is_cr_intercept(struct vcpu_svm
*svm
, int bit
)
261 struct vmcb
*vmcb
= get_host_vmcb(svm
);
263 return vmcb
->control
.intercept_cr
& (1U << bit
);
266 static inline void set_dr_intercept(struct vcpu_svm
*svm
, int bit
)
268 struct vmcb
*vmcb
= get_host_vmcb(svm
);
270 vmcb
->control
.intercept_dr
|= (1U << bit
);
272 recalc_intercepts(svm
);
275 static inline void clr_dr_intercept(struct vcpu_svm
*svm
, int bit
)
277 struct vmcb
*vmcb
= get_host_vmcb(svm
);
279 vmcb
->control
.intercept_dr
&= ~(1U << bit
);
281 recalc_intercepts(svm
);
284 static inline void set_exception_intercept(struct vcpu_svm
*svm
, int bit
)
286 struct vmcb
*vmcb
= get_host_vmcb(svm
);
288 vmcb
->control
.intercept_exceptions
|= (1U << bit
);
290 recalc_intercepts(svm
);
293 static inline void clr_exception_intercept(struct vcpu_svm
*svm
, int bit
)
295 struct vmcb
*vmcb
= get_host_vmcb(svm
);
297 vmcb
->control
.intercept_exceptions
&= ~(1U << bit
);
299 recalc_intercepts(svm
);
302 static inline void set_intercept(struct vcpu_svm
*svm
, int bit
)
304 struct vmcb
*vmcb
= get_host_vmcb(svm
);
306 vmcb
->control
.intercept
|= (1ULL << bit
);
308 recalc_intercepts(svm
);
311 static inline void clr_intercept(struct vcpu_svm
*svm
, int bit
)
313 struct vmcb
*vmcb
= get_host_vmcb(svm
);
315 vmcb
->control
.intercept
&= ~(1ULL << bit
);
317 recalc_intercepts(svm
);
320 static inline void enable_gif(struct vcpu_svm
*svm
)
322 svm
->vcpu
.arch
.hflags
|= HF_GIF_MASK
;
325 static inline void disable_gif(struct vcpu_svm
*svm
)
327 svm
->vcpu
.arch
.hflags
&= ~HF_GIF_MASK
;
330 static inline bool gif_set(struct vcpu_svm
*svm
)
332 return !!(svm
->vcpu
.arch
.hflags
& HF_GIF_MASK
);
335 static unsigned long iopm_base
;
337 struct kvm_ldttss_desc
{
340 unsigned base1
:8, type
:5, dpl
:2, p
:1;
341 unsigned limit1
:4, zero0
:3, g
:1, base2
:8;
344 } __attribute__((packed
));
346 struct svm_cpu_data
{
352 struct kvm_ldttss_desc
*tss_desc
;
354 struct page
*save_area
;
357 static DEFINE_PER_CPU(struct svm_cpu_data
*, svm_data
);
358 static uint32_t svm_features
;
360 struct svm_init_data
{
365 static u32 msrpm_ranges
[] = {0, 0xc0000000, 0xc0010000};
367 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
368 #define MSRS_RANGE_SIZE 2048
369 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
371 static u32
svm_msrpm_offset(u32 msr
)
376 for (i
= 0; i
< NUM_MSR_MAPS
; i
++) {
377 if (msr
< msrpm_ranges
[i
] ||
378 msr
>= msrpm_ranges
[i
] + MSRS_IN_RANGE
)
381 offset
= (msr
- msrpm_ranges
[i
]) / 4; /* 4 msrs per u8 */
382 offset
+= (i
* MSRS_RANGE_SIZE
); /* add range offset */
384 /* Now we have the u8 offset - but need the u32 offset */
388 /* MSR not in any range */
392 #define MAX_INST_SIZE 15
394 static inline void clgi(void)
396 asm volatile (__ex(SVM_CLGI
));
399 static inline void stgi(void)
401 asm volatile (__ex(SVM_STGI
));
404 static inline void invlpga(unsigned long addr
, u32 asid
)
406 asm volatile (__ex(SVM_INVLPGA
) : : "a"(addr
), "c"(asid
));
409 static inline void force_new_asid(struct kvm_vcpu
*vcpu
)
411 to_svm(vcpu
)->asid_generation
--;
414 static inline void flush_guest_tlb(struct kvm_vcpu
*vcpu
)
416 force_new_asid(vcpu
);
419 static int get_npt_level(void)
422 return PT64_ROOT_LEVEL
;
424 return PT32E_ROOT_LEVEL
;
428 static void svm_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
430 vcpu
->arch
.efer
= efer
;
431 if (!npt_enabled
&& !(efer
& EFER_LMA
))
434 to_svm(vcpu
)->vmcb
->save
.efer
= efer
| EFER_SVME
;
437 static int is_external_interrupt(u32 info
)
439 info
&= SVM_EVTINJ_TYPE_MASK
| SVM_EVTINJ_VALID
;
440 return info
== (SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
);
443 static u32
svm_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
445 struct vcpu_svm
*svm
= to_svm(vcpu
);
448 if (svm
->vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
)
449 ret
|= KVM_X86_SHADOW_INT_STI
| KVM_X86_SHADOW_INT_MOV_SS
;
453 static void svm_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
455 struct vcpu_svm
*svm
= to_svm(vcpu
);
458 svm
->vmcb
->control
.int_state
&= ~SVM_INTERRUPT_SHADOW_MASK
;
460 svm
->vmcb
->control
.int_state
|= SVM_INTERRUPT_SHADOW_MASK
;
464 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
466 struct vcpu_svm
*svm
= to_svm(vcpu
);
468 if (svm
->vmcb
->control
.next_rip
!= 0)
469 svm
->next_rip
= svm
->vmcb
->control
.next_rip
;
471 if (!svm
->next_rip
) {
472 if (emulate_instruction(vcpu
, 0, 0, EMULTYPE_SKIP
) !=
474 printk(KERN_DEBUG
"%s: NOP\n", __func__
);
477 if (svm
->next_rip
- kvm_rip_read(vcpu
) > MAX_INST_SIZE
)
478 printk(KERN_ERR
"%s: ip 0x%lx next 0x%llx\n",
479 __func__
, kvm_rip_read(vcpu
), svm
->next_rip
);
481 kvm_rip_write(vcpu
, svm
->next_rip
);
482 svm_set_interrupt_shadow(vcpu
, 0);
485 static void svm_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
486 bool has_error_code
, u32 error_code
,
489 struct vcpu_svm
*svm
= to_svm(vcpu
);
492 * If we are within a nested VM we'd better #VMEXIT and let the guest
493 * handle the exception
496 nested_svm_check_exception(svm
, nr
, has_error_code
, error_code
))
499 if (nr
== BP_VECTOR
&& !static_cpu_has(X86_FEATURE_NRIPS
)) {
500 unsigned long rip
, old_rip
= kvm_rip_read(&svm
->vcpu
);
503 * For guest debugging where we have to reinject #BP if some
504 * INT3 is guest-owned:
505 * Emulate nRIP by moving RIP forward. Will fail if injection
506 * raises a fault that is not intercepted. Still better than
507 * failing in all cases.
509 skip_emulated_instruction(&svm
->vcpu
);
510 rip
= kvm_rip_read(&svm
->vcpu
);
511 svm
->int3_rip
= rip
+ svm
->vmcb
->save
.cs
.base
;
512 svm
->int3_injected
= rip
- old_rip
;
515 svm
->vmcb
->control
.event_inj
= nr
517 | (has_error_code
? SVM_EVTINJ_VALID_ERR
: 0)
518 | SVM_EVTINJ_TYPE_EXEPT
;
519 svm
->vmcb
->control
.event_inj_err
= error_code
;
522 static void svm_init_erratum_383(void)
528 if (!cpu_has_amd_erratum(amd_erratum_383
))
531 /* Use _safe variants to not break nested virtualization */
532 val
= native_read_msr_safe(MSR_AMD64_DC_CFG
, &err
);
538 low
= lower_32_bits(val
);
539 high
= upper_32_bits(val
);
541 native_write_msr_safe(MSR_AMD64_DC_CFG
, low
, high
);
543 erratum_383_found
= true;
546 static int has_svm(void)
550 if (!cpu_has_svm(&msg
)) {
551 printk(KERN_INFO
"has_svm: %s\n", msg
);
558 static void svm_hardware_disable(void *garbage
)
563 static int svm_hardware_enable(void *garbage
)
566 struct svm_cpu_data
*sd
;
568 struct desc_ptr gdt_descr
;
569 struct desc_struct
*gdt
;
570 int me
= raw_smp_processor_id();
572 rdmsrl(MSR_EFER
, efer
);
573 if (efer
& EFER_SVME
)
577 printk(KERN_ERR
"svm_hardware_enable: err EOPNOTSUPP on %d\n",
581 sd
= per_cpu(svm_data
, me
);
584 printk(KERN_ERR
"svm_hardware_enable: svm_data is NULL on %d\n",
589 sd
->asid_generation
= 1;
590 sd
->max_asid
= cpuid_ebx(SVM_CPUID_FUNC
) - 1;
591 sd
->next_asid
= sd
->max_asid
+ 1;
593 native_store_gdt(&gdt_descr
);
594 gdt
= (struct desc_struct
*)gdt_descr
.address
;
595 sd
->tss_desc
= (struct kvm_ldttss_desc
*)(gdt
+ GDT_ENTRY_TSS
);
597 wrmsrl(MSR_EFER
, efer
| EFER_SVME
);
599 wrmsrl(MSR_VM_HSAVE_PA
, page_to_pfn(sd
->save_area
) << PAGE_SHIFT
);
601 svm_init_erratum_383();
606 static void svm_cpu_uninit(int cpu
)
608 struct svm_cpu_data
*sd
= per_cpu(svm_data
, raw_smp_processor_id());
613 per_cpu(svm_data
, raw_smp_processor_id()) = NULL
;
614 __free_page(sd
->save_area
);
618 static int svm_cpu_init(int cpu
)
620 struct svm_cpu_data
*sd
;
623 sd
= kzalloc(sizeof(struct svm_cpu_data
), GFP_KERNEL
);
627 sd
->save_area
= alloc_page(GFP_KERNEL
);
632 per_cpu(svm_data
, cpu
) = sd
;
642 static bool valid_msr_intercept(u32 index
)
646 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++)
647 if (direct_access_msrs
[i
].index
== index
)
653 static void set_msr_interception(u32
*msrpm
, unsigned msr
,
656 u8 bit_read
, bit_write
;
661 * If this warning triggers extend the direct_access_msrs list at the
662 * beginning of the file
664 WARN_ON(!valid_msr_intercept(msr
));
666 offset
= svm_msrpm_offset(msr
);
667 bit_read
= 2 * (msr
& 0x0f);
668 bit_write
= 2 * (msr
& 0x0f) + 1;
671 BUG_ON(offset
== MSR_INVALID
);
673 read
? clear_bit(bit_read
, &tmp
) : set_bit(bit_read
, &tmp
);
674 write
? clear_bit(bit_write
, &tmp
) : set_bit(bit_write
, &tmp
);
679 static void svm_vcpu_init_msrpm(u32
*msrpm
)
683 memset(msrpm
, 0xff, PAGE_SIZE
* (1 << MSRPM_ALLOC_ORDER
));
685 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
686 if (!direct_access_msrs
[i
].always
)
689 set_msr_interception(msrpm
, direct_access_msrs
[i
].index
, 1, 1);
693 static void add_msr_offset(u32 offset
)
697 for (i
= 0; i
< MSRPM_OFFSETS
; ++i
) {
699 /* Offset already in list? */
700 if (msrpm_offsets
[i
] == offset
)
703 /* Slot used by another offset? */
704 if (msrpm_offsets
[i
] != MSR_INVALID
)
707 /* Add offset to list */
708 msrpm_offsets
[i
] = offset
;
714 * If this BUG triggers the msrpm_offsets table has an overflow. Just
715 * increase MSRPM_OFFSETS in this case.
720 static void init_msrpm_offsets(void)
724 memset(msrpm_offsets
, 0xff, sizeof(msrpm_offsets
));
726 for (i
= 0; direct_access_msrs
[i
].index
!= MSR_INVALID
; i
++) {
729 offset
= svm_msrpm_offset(direct_access_msrs
[i
].index
);
730 BUG_ON(offset
== MSR_INVALID
);
732 add_msr_offset(offset
);
736 static void svm_enable_lbrv(struct vcpu_svm
*svm
)
738 u32
*msrpm
= svm
->msrpm
;
740 svm
->vmcb
->control
.lbr_ctl
= 1;
741 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 1, 1);
742 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 1, 1);
743 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 1, 1);
744 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 1, 1);
747 static void svm_disable_lbrv(struct vcpu_svm
*svm
)
749 u32
*msrpm
= svm
->msrpm
;
751 svm
->vmcb
->control
.lbr_ctl
= 0;
752 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHFROMIP
, 0, 0);
753 set_msr_interception(msrpm
, MSR_IA32_LASTBRANCHTOIP
, 0, 0);
754 set_msr_interception(msrpm
, MSR_IA32_LASTINTFROMIP
, 0, 0);
755 set_msr_interception(msrpm
, MSR_IA32_LASTINTTOIP
, 0, 0);
758 static __init
int svm_hardware_setup(void)
761 struct page
*iopm_pages
;
765 iopm_pages
= alloc_pages(GFP_KERNEL
, IOPM_ALLOC_ORDER
);
770 iopm_va
= page_address(iopm_pages
);
771 memset(iopm_va
, 0xff, PAGE_SIZE
* (1 << IOPM_ALLOC_ORDER
));
772 iopm_base
= page_to_pfn(iopm_pages
) << PAGE_SHIFT
;
774 init_msrpm_offsets();
776 if (boot_cpu_has(X86_FEATURE_NX
))
777 kvm_enable_efer_bits(EFER_NX
);
779 if (boot_cpu_has(X86_FEATURE_FXSR_OPT
))
780 kvm_enable_efer_bits(EFER_FFXSR
);
783 printk(KERN_INFO
"kvm: Nested Virtualization enabled\n");
784 kvm_enable_efer_bits(EFER_SVME
| EFER_LMSLE
);
787 for_each_possible_cpu(cpu
) {
788 r
= svm_cpu_init(cpu
);
793 svm_features
= cpuid_edx(SVM_CPUID_FUNC
);
795 if (!boot_cpu_has(X86_FEATURE_NPT
))
798 if (npt_enabled
&& !npt
) {
799 printk(KERN_INFO
"kvm: Nested Paging disabled\n");
804 printk(KERN_INFO
"kvm: Nested Paging enabled\n");
812 __free_pages(iopm_pages
, IOPM_ALLOC_ORDER
);
817 static __exit
void svm_hardware_unsetup(void)
821 for_each_possible_cpu(cpu
)
824 __free_pages(pfn_to_page(iopm_base
>> PAGE_SHIFT
), IOPM_ALLOC_ORDER
);
828 static void init_seg(struct vmcb_seg
*seg
)
831 seg
->attrib
= SVM_SELECTOR_P_MASK
| SVM_SELECTOR_S_MASK
|
832 SVM_SELECTOR_WRITE_MASK
; /* Read/Write Data Segment */
837 static void init_sys_seg(struct vmcb_seg
*seg
, uint32_t type
)
840 seg
->attrib
= SVM_SELECTOR_P_MASK
| type
;
845 static void svm_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
847 struct vcpu_svm
*svm
= to_svm(vcpu
);
848 u64 g_tsc_offset
= 0;
850 if (is_guest_mode(vcpu
)) {
851 g_tsc_offset
= svm
->vmcb
->control
.tsc_offset
-
852 svm
->nested
.hsave
->control
.tsc_offset
;
853 svm
->nested
.hsave
->control
.tsc_offset
= offset
;
856 svm
->vmcb
->control
.tsc_offset
= offset
+ g_tsc_offset
;
859 static void svm_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
861 struct vcpu_svm
*svm
= to_svm(vcpu
);
863 svm
->vmcb
->control
.tsc_offset
+= adjustment
;
864 if (is_guest_mode(vcpu
))
865 svm
->nested
.hsave
->control
.tsc_offset
+= adjustment
;
868 static void init_vmcb(struct vcpu_svm
*svm
)
870 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
871 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
873 svm
->vcpu
.fpu_active
= 1;
874 svm
->vcpu
.arch
.hflags
= 0;
876 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
877 set_cr_intercept(svm
, INTERCEPT_CR3_READ
);
878 set_cr_intercept(svm
, INTERCEPT_CR4_READ
);
879 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
880 set_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
881 set_cr_intercept(svm
, INTERCEPT_CR4_WRITE
);
882 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
884 set_dr_intercept(svm
, INTERCEPT_DR0_READ
);
885 set_dr_intercept(svm
, INTERCEPT_DR1_READ
);
886 set_dr_intercept(svm
, INTERCEPT_DR2_READ
);
887 set_dr_intercept(svm
, INTERCEPT_DR3_READ
);
888 set_dr_intercept(svm
, INTERCEPT_DR4_READ
);
889 set_dr_intercept(svm
, INTERCEPT_DR5_READ
);
890 set_dr_intercept(svm
, INTERCEPT_DR6_READ
);
891 set_dr_intercept(svm
, INTERCEPT_DR7_READ
);
893 set_dr_intercept(svm
, INTERCEPT_DR0_WRITE
);
894 set_dr_intercept(svm
, INTERCEPT_DR1_WRITE
);
895 set_dr_intercept(svm
, INTERCEPT_DR2_WRITE
);
896 set_dr_intercept(svm
, INTERCEPT_DR3_WRITE
);
897 set_dr_intercept(svm
, INTERCEPT_DR4_WRITE
);
898 set_dr_intercept(svm
, INTERCEPT_DR5_WRITE
);
899 set_dr_intercept(svm
, INTERCEPT_DR6_WRITE
);
900 set_dr_intercept(svm
, INTERCEPT_DR7_WRITE
);
902 set_exception_intercept(svm
, PF_VECTOR
);
903 set_exception_intercept(svm
, UD_VECTOR
);
904 set_exception_intercept(svm
, MC_VECTOR
);
906 set_intercept(svm
, INTERCEPT_INTR
);
907 set_intercept(svm
, INTERCEPT_NMI
);
908 set_intercept(svm
, INTERCEPT_SMI
);
909 set_intercept(svm
, INTERCEPT_SELECTIVE_CR0
);
910 set_intercept(svm
, INTERCEPT_CPUID
);
911 set_intercept(svm
, INTERCEPT_INVD
);
912 set_intercept(svm
, INTERCEPT_HLT
);
913 set_intercept(svm
, INTERCEPT_INVLPG
);
914 set_intercept(svm
, INTERCEPT_INVLPGA
);
915 set_intercept(svm
, INTERCEPT_IOIO_PROT
);
916 set_intercept(svm
, INTERCEPT_MSR_PROT
);
917 set_intercept(svm
, INTERCEPT_TASK_SWITCH
);
918 set_intercept(svm
, INTERCEPT_SHUTDOWN
);
919 set_intercept(svm
, INTERCEPT_VMRUN
);
920 set_intercept(svm
, INTERCEPT_VMMCALL
);
921 set_intercept(svm
, INTERCEPT_VMLOAD
);
922 set_intercept(svm
, INTERCEPT_VMSAVE
);
923 set_intercept(svm
, INTERCEPT_STGI
);
924 set_intercept(svm
, INTERCEPT_CLGI
);
925 set_intercept(svm
, INTERCEPT_SKINIT
);
926 set_intercept(svm
, INTERCEPT_WBINVD
);
927 set_intercept(svm
, INTERCEPT_MONITOR
);
928 set_intercept(svm
, INTERCEPT_MWAIT
);
930 control
->iopm_base_pa
= iopm_base
;
931 control
->msrpm_base_pa
= __pa(svm
->msrpm
);
932 control
->int_ctl
= V_INTR_MASKING_MASK
;
940 save
->cs
.selector
= 0xf000;
941 /* Executable/Readable Code Segment */
942 save
->cs
.attrib
= SVM_SELECTOR_READ_MASK
| SVM_SELECTOR_P_MASK
|
943 SVM_SELECTOR_S_MASK
| SVM_SELECTOR_CODE_MASK
;
944 save
->cs
.limit
= 0xffff;
946 * cs.base should really be 0xffff0000, but vmx can't handle that, so
947 * be consistent with it.
949 * Replace when we have real mode working for vmx.
951 save
->cs
.base
= 0xf0000;
953 save
->gdtr
.limit
= 0xffff;
954 save
->idtr
.limit
= 0xffff;
956 init_sys_seg(&save
->ldtr
, SEG_TYPE_LDT
);
957 init_sys_seg(&save
->tr
, SEG_TYPE_BUSY_TSS16
);
959 svm_set_efer(&svm
->vcpu
, 0);
960 save
->dr6
= 0xffff0ff0;
963 save
->rip
= 0x0000fff0;
964 svm
->vcpu
.arch
.regs
[VCPU_REGS_RIP
] = save
->rip
;
967 * This is the guest-visible cr0 value.
968 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
970 svm
->vcpu
.arch
.cr0
= 0;
971 (void)kvm_set_cr0(&svm
->vcpu
, X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
);
973 save
->cr4
= X86_CR4_PAE
;
977 /* Setup VMCB for Nested Paging */
978 control
->nested_ctl
= 1;
979 clr_intercept(svm
, INTERCEPT_TASK_SWITCH
);
980 clr_intercept(svm
, INTERCEPT_INVLPG
);
981 clr_exception_intercept(svm
, PF_VECTOR
);
982 clr_cr_intercept(svm
, INTERCEPT_CR3_READ
);
983 clr_cr_intercept(svm
, INTERCEPT_CR3_WRITE
);
984 save
->g_pat
= 0x0007040600070406ULL
;
988 force_new_asid(&svm
->vcpu
);
990 svm
->nested
.vmcb
= 0;
991 svm
->vcpu
.arch
.hflags
= 0;
993 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER
)) {
994 control
->pause_filter_count
= 3000;
995 set_intercept(svm
, INTERCEPT_PAUSE
);
998 mark_all_dirty(svm
->vmcb
);
1003 static int svm_vcpu_reset(struct kvm_vcpu
*vcpu
)
1005 struct vcpu_svm
*svm
= to_svm(vcpu
);
1009 if (!kvm_vcpu_is_bsp(vcpu
)) {
1010 kvm_rip_write(vcpu
, 0);
1011 svm
->vmcb
->save
.cs
.base
= svm
->vcpu
.arch
.sipi_vector
<< 12;
1012 svm
->vmcb
->save
.cs
.selector
= svm
->vcpu
.arch
.sipi_vector
<< 8;
1014 vcpu
->arch
.regs_avail
= ~0;
1015 vcpu
->arch
.regs_dirty
= ~0;
1020 static struct kvm_vcpu
*svm_create_vcpu(struct kvm
*kvm
, unsigned int id
)
1022 struct vcpu_svm
*svm
;
1024 struct page
*msrpm_pages
;
1025 struct page
*hsave_page
;
1026 struct page
*nested_msrpm_pages
;
1029 svm
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
1035 err
= kvm_vcpu_init(&svm
->vcpu
, kvm
, id
);
1040 page
= alloc_page(GFP_KERNEL
);
1044 msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1048 nested_msrpm_pages
= alloc_pages(GFP_KERNEL
, MSRPM_ALLOC_ORDER
);
1049 if (!nested_msrpm_pages
)
1052 hsave_page
= alloc_page(GFP_KERNEL
);
1056 svm
->nested
.hsave
= page_address(hsave_page
);
1058 svm
->msrpm
= page_address(msrpm_pages
);
1059 svm_vcpu_init_msrpm(svm
->msrpm
);
1061 svm
->nested
.msrpm
= page_address(nested_msrpm_pages
);
1062 svm_vcpu_init_msrpm(svm
->nested
.msrpm
);
1064 svm
->vmcb
= page_address(page
);
1065 clear_page(svm
->vmcb
);
1066 svm
->vmcb_pa
= page_to_pfn(page
) << PAGE_SHIFT
;
1067 svm
->asid_generation
= 0;
1069 kvm_write_tsc(&svm
->vcpu
, 0);
1071 err
= fx_init(&svm
->vcpu
);
1075 svm
->vcpu
.arch
.apic_base
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
1076 if (kvm_vcpu_is_bsp(&svm
->vcpu
))
1077 svm
->vcpu
.arch
.apic_base
|= MSR_IA32_APICBASE_BSP
;
1082 __free_page(hsave_page
);
1084 __free_pages(nested_msrpm_pages
, MSRPM_ALLOC_ORDER
);
1086 __free_pages(msrpm_pages
, MSRPM_ALLOC_ORDER
);
1090 kvm_vcpu_uninit(&svm
->vcpu
);
1092 kmem_cache_free(kvm_vcpu_cache
, svm
);
1094 return ERR_PTR(err
);
1097 static void svm_free_vcpu(struct kvm_vcpu
*vcpu
)
1099 struct vcpu_svm
*svm
= to_svm(vcpu
);
1101 __free_page(pfn_to_page(svm
->vmcb_pa
>> PAGE_SHIFT
));
1102 __free_pages(virt_to_page(svm
->msrpm
), MSRPM_ALLOC_ORDER
);
1103 __free_page(virt_to_page(svm
->nested
.hsave
));
1104 __free_pages(virt_to_page(svm
->nested
.msrpm
), MSRPM_ALLOC_ORDER
);
1105 kvm_vcpu_uninit(vcpu
);
1106 kmem_cache_free(kvm_vcpu_cache
, svm
);
1109 static void svm_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1111 struct vcpu_svm
*svm
= to_svm(vcpu
);
1114 if (unlikely(cpu
!= vcpu
->cpu
)) {
1115 svm
->asid_generation
= 0;
1116 mark_all_dirty(svm
->vmcb
);
1119 #ifdef CONFIG_X86_64
1120 rdmsrl(MSR_GS_BASE
, to_svm(vcpu
)->host
.gs_base
);
1122 savesegment(fs
, svm
->host
.fs
);
1123 savesegment(gs
, svm
->host
.gs
);
1124 svm
->host
.ldt
= kvm_read_ldt();
1126 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1127 rdmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1130 static void svm_vcpu_put(struct kvm_vcpu
*vcpu
)
1132 struct vcpu_svm
*svm
= to_svm(vcpu
);
1135 ++vcpu
->stat
.host_state_reload
;
1136 kvm_load_ldt(svm
->host
.ldt
);
1137 #ifdef CONFIG_X86_64
1138 loadsegment(fs
, svm
->host
.fs
);
1139 load_gs_index(svm
->host
.gs
);
1140 wrmsrl(MSR_KERNEL_GS_BASE
, current
->thread
.gs
);
1142 loadsegment(gs
, svm
->host
.gs
);
1144 for (i
= 0; i
< NR_HOST_SAVE_USER_MSRS
; i
++)
1145 wrmsrl(host_save_user_msrs
[i
], svm
->host_user_msrs
[i
]);
1148 static unsigned long svm_get_rflags(struct kvm_vcpu
*vcpu
)
1150 return to_svm(vcpu
)->vmcb
->save
.rflags
;
1153 static void svm_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1155 to_svm(vcpu
)->vmcb
->save
.rflags
= rflags
;
1158 static void svm_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1161 case VCPU_EXREG_PDPTR
:
1162 BUG_ON(!npt_enabled
);
1163 load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, vcpu
->arch
.cr3
);
1170 static void svm_set_vintr(struct vcpu_svm
*svm
)
1172 set_intercept(svm
, INTERCEPT_VINTR
);
1175 static void svm_clear_vintr(struct vcpu_svm
*svm
)
1177 clr_intercept(svm
, INTERCEPT_VINTR
);
1180 static struct vmcb_seg
*svm_seg(struct kvm_vcpu
*vcpu
, int seg
)
1182 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1185 case VCPU_SREG_CS
: return &save
->cs
;
1186 case VCPU_SREG_DS
: return &save
->ds
;
1187 case VCPU_SREG_ES
: return &save
->es
;
1188 case VCPU_SREG_FS
: return &save
->fs
;
1189 case VCPU_SREG_GS
: return &save
->gs
;
1190 case VCPU_SREG_SS
: return &save
->ss
;
1191 case VCPU_SREG_TR
: return &save
->tr
;
1192 case VCPU_SREG_LDTR
: return &save
->ldtr
;
1198 static u64
svm_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1200 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1205 static void svm_get_segment(struct kvm_vcpu
*vcpu
,
1206 struct kvm_segment
*var
, int seg
)
1208 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1210 var
->base
= s
->base
;
1211 var
->limit
= s
->limit
;
1212 var
->selector
= s
->selector
;
1213 var
->type
= s
->attrib
& SVM_SELECTOR_TYPE_MASK
;
1214 var
->s
= (s
->attrib
>> SVM_SELECTOR_S_SHIFT
) & 1;
1215 var
->dpl
= (s
->attrib
>> SVM_SELECTOR_DPL_SHIFT
) & 3;
1216 var
->present
= (s
->attrib
>> SVM_SELECTOR_P_SHIFT
) & 1;
1217 var
->avl
= (s
->attrib
>> SVM_SELECTOR_AVL_SHIFT
) & 1;
1218 var
->l
= (s
->attrib
>> SVM_SELECTOR_L_SHIFT
) & 1;
1219 var
->db
= (s
->attrib
>> SVM_SELECTOR_DB_SHIFT
) & 1;
1220 var
->g
= (s
->attrib
>> SVM_SELECTOR_G_SHIFT
) & 1;
1223 * AMD's VMCB does not have an explicit unusable field, so emulate it
1224 * for cross vendor migration purposes by "not present"
1226 var
->unusable
= !var
->present
|| (var
->type
== 0);
1231 * SVM always stores 0 for the 'G' bit in the CS selector in
1232 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1233 * Intel's VMENTRY has a check on the 'G' bit.
1235 var
->g
= s
->limit
> 0xfffff;
1239 * Work around a bug where the busy flag in the tr selector
1249 * The accessed bit must always be set in the segment
1250 * descriptor cache, although it can be cleared in the
1251 * descriptor, the cached bit always remains at 1. Since
1252 * Intel has a check on this, set it here to support
1253 * cross-vendor migration.
1260 * On AMD CPUs sometimes the DB bit in the segment
1261 * descriptor is left as 1, although the whole segment has
1262 * been made unusable. Clear it here to pass an Intel VMX
1263 * entry check when cross vendor migrating.
1271 static int svm_get_cpl(struct kvm_vcpu
*vcpu
)
1273 struct vmcb_save_area
*save
= &to_svm(vcpu
)->vmcb
->save
;
1278 static void svm_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1280 struct vcpu_svm
*svm
= to_svm(vcpu
);
1282 dt
->size
= svm
->vmcb
->save
.idtr
.limit
;
1283 dt
->address
= svm
->vmcb
->save
.idtr
.base
;
1286 static void svm_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1288 struct vcpu_svm
*svm
= to_svm(vcpu
);
1290 svm
->vmcb
->save
.idtr
.limit
= dt
->size
;
1291 svm
->vmcb
->save
.idtr
.base
= dt
->address
;
1294 static void svm_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1296 struct vcpu_svm
*svm
= to_svm(vcpu
);
1298 dt
->size
= svm
->vmcb
->save
.gdtr
.limit
;
1299 dt
->address
= svm
->vmcb
->save
.gdtr
.base
;
1302 static void svm_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
1304 struct vcpu_svm
*svm
= to_svm(vcpu
);
1306 svm
->vmcb
->save
.gdtr
.limit
= dt
->size
;
1307 svm
->vmcb
->save
.gdtr
.base
= dt
->address
;
1310 static void svm_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1314 static void svm_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1318 static void update_cr0_intercept(struct vcpu_svm
*svm
)
1320 ulong gcr0
= svm
->vcpu
.arch
.cr0
;
1321 u64
*hcr0
= &svm
->vmcb
->save
.cr0
;
1323 if (!svm
->vcpu
.fpu_active
)
1324 *hcr0
|= SVM_CR0_SELECTIVE_MASK
;
1326 *hcr0
= (*hcr0
& ~SVM_CR0_SELECTIVE_MASK
)
1327 | (gcr0
& SVM_CR0_SELECTIVE_MASK
);
1330 if (gcr0
== *hcr0
&& svm
->vcpu
.fpu_active
) {
1331 clr_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1332 clr_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1334 set_cr_intercept(svm
, INTERCEPT_CR0_READ
);
1335 set_cr_intercept(svm
, INTERCEPT_CR0_WRITE
);
1339 static void svm_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1341 struct vcpu_svm
*svm
= to_svm(vcpu
);
1343 if (is_guest_mode(vcpu
)) {
1345 * We are here because we run in nested mode, the host kvm
1346 * intercepts cr0 writes but the l1 hypervisor does not.
1347 * But the L1 hypervisor may intercept selective cr0 writes.
1348 * This needs to be checked here.
1350 unsigned long old
, new;
1352 /* Remove bits that would trigger a real cr0 write intercept */
1353 old
= vcpu
->arch
.cr0
& SVM_CR0_SELECTIVE_MASK
;
1354 new = cr0
& SVM_CR0_SELECTIVE_MASK
;
1357 /* cr0 write with ts and mp unchanged */
1358 svm
->vmcb
->control
.exit_code
= SVM_EXIT_CR0_SEL_WRITE
;
1359 if (nested_svm_exit_handled(svm
) == NESTED_EXIT_DONE
) {
1360 svm
->nested
.vmexit_rip
= kvm_rip_read(vcpu
);
1361 svm
->nested
.vmexit_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
1362 svm
->nested
.vmexit_rax
= kvm_register_read(vcpu
, VCPU_REGS_RAX
);
1368 #ifdef CONFIG_X86_64
1369 if (vcpu
->arch
.efer
& EFER_LME
) {
1370 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
)) {
1371 vcpu
->arch
.efer
|= EFER_LMA
;
1372 svm
->vmcb
->save
.efer
|= EFER_LMA
| EFER_LME
;
1375 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
)) {
1376 vcpu
->arch
.efer
&= ~EFER_LMA
;
1377 svm
->vmcb
->save
.efer
&= ~(EFER_LMA
| EFER_LME
);
1381 vcpu
->arch
.cr0
= cr0
;
1384 cr0
|= X86_CR0_PG
| X86_CR0_WP
;
1386 if (!vcpu
->fpu_active
)
1389 * re-enable caching here because the QEMU bios
1390 * does not do it - this results in some delay at
1393 cr0
&= ~(X86_CR0_CD
| X86_CR0_NW
);
1394 svm
->vmcb
->save
.cr0
= cr0
;
1395 update_cr0_intercept(svm
);
1398 static void svm_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1400 unsigned long host_cr4_mce
= read_cr4() & X86_CR4_MCE
;
1401 unsigned long old_cr4
= to_svm(vcpu
)->vmcb
->save
.cr4
;
1403 if (npt_enabled
&& ((old_cr4
^ cr4
) & X86_CR4_PGE
))
1404 force_new_asid(vcpu
);
1406 vcpu
->arch
.cr4
= cr4
;
1409 cr4
|= host_cr4_mce
;
1410 to_svm(vcpu
)->vmcb
->save
.cr4
= cr4
;
1413 static void svm_set_segment(struct kvm_vcpu
*vcpu
,
1414 struct kvm_segment
*var
, int seg
)
1416 struct vcpu_svm
*svm
= to_svm(vcpu
);
1417 struct vmcb_seg
*s
= svm_seg(vcpu
, seg
);
1419 s
->base
= var
->base
;
1420 s
->limit
= var
->limit
;
1421 s
->selector
= var
->selector
;
1425 s
->attrib
= (var
->type
& SVM_SELECTOR_TYPE_MASK
);
1426 s
->attrib
|= (var
->s
& 1) << SVM_SELECTOR_S_SHIFT
;
1427 s
->attrib
|= (var
->dpl
& 3) << SVM_SELECTOR_DPL_SHIFT
;
1428 s
->attrib
|= (var
->present
& 1) << SVM_SELECTOR_P_SHIFT
;
1429 s
->attrib
|= (var
->avl
& 1) << SVM_SELECTOR_AVL_SHIFT
;
1430 s
->attrib
|= (var
->l
& 1) << SVM_SELECTOR_L_SHIFT
;
1431 s
->attrib
|= (var
->db
& 1) << SVM_SELECTOR_DB_SHIFT
;
1432 s
->attrib
|= (var
->g
& 1) << SVM_SELECTOR_G_SHIFT
;
1434 if (seg
== VCPU_SREG_CS
)
1436 = (svm
->vmcb
->save
.cs
.attrib
1437 >> SVM_SELECTOR_DPL_SHIFT
) & 3;
1441 static void update_db_intercept(struct kvm_vcpu
*vcpu
)
1443 struct vcpu_svm
*svm
= to_svm(vcpu
);
1445 clr_exception_intercept(svm
, DB_VECTOR
);
1446 clr_exception_intercept(svm
, BP_VECTOR
);
1448 if (svm
->nmi_singlestep
)
1449 set_exception_intercept(svm
, DB_VECTOR
);
1451 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
1452 if (vcpu
->guest_debug
&
1453 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
1454 set_exception_intercept(svm
, DB_VECTOR
);
1455 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
1456 set_exception_intercept(svm
, BP_VECTOR
);
1458 vcpu
->guest_debug
= 0;
1461 static void svm_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1463 struct vcpu_svm
*svm
= to_svm(vcpu
);
1465 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1466 svm
->vmcb
->save
.dr7
= dbg
->arch
.debugreg
[7];
1468 svm
->vmcb
->save
.dr7
= vcpu
->arch
.dr7
;
1470 update_db_intercept(vcpu
);
1473 static void new_asid(struct vcpu_svm
*svm
, struct svm_cpu_data
*sd
)
1475 if (sd
->next_asid
> sd
->max_asid
) {
1476 ++sd
->asid_generation
;
1478 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_FLUSH_ALL_ASID
;
1481 svm
->asid_generation
= sd
->asid_generation
;
1482 svm
->vmcb
->control
.asid
= sd
->next_asid
++;
1485 static void svm_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long value
)
1487 struct vcpu_svm
*svm
= to_svm(vcpu
);
1489 svm
->vmcb
->save
.dr7
= value
;
1492 static int pf_interception(struct vcpu_svm
*svm
)
1494 u64 fault_address
= svm
->vmcb
->control
.exit_info_2
;
1498 switch (svm
->apf_reason
) {
1500 error_code
= svm
->vmcb
->control
.exit_info_1
;
1502 trace_kvm_page_fault(fault_address
, error_code
);
1503 if (!npt_enabled
&& kvm_event_needs_reinjection(&svm
->vcpu
))
1504 kvm_mmu_unprotect_page_virt(&svm
->vcpu
, fault_address
);
1505 r
= kvm_mmu_page_fault(&svm
->vcpu
, fault_address
, error_code
);
1507 case KVM_PV_REASON_PAGE_NOT_PRESENT
:
1508 svm
->apf_reason
= 0;
1509 local_irq_disable();
1510 kvm_async_pf_task_wait(fault_address
);
1513 case KVM_PV_REASON_PAGE_READY
:
1514 svm
->apf_reason
= 0;
1515 local_irq_disable();
1516 kvm_async_pf_task_wake(fault_address
);
1523 static int db_interception(struct vcpu_svm
*svm
)
1525 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1527 if (!(svm
->vcpu
.guest_debug
&
1528 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) &&
1529 !svm
->nmi_singlestep
) {
1530 kvm_queue_exception(&svm
->vcpu
, DB_VECTOR
);
1534 if (svm
->nmi_singlestep
) {
1535 svm
->nmi_singlestep
= false;
1536 if (!(svm
->vcpu
.guest_debug
& KVM_GUESTDBG_SINGLESTEP
))
1537 svm
->vmcb
->save
.rflags
&=
1538 ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1539 update_db_intercept(&svm
->vcpu
);
1542 if (svm
->vcpu
.guest_debug
&
1543 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
)) {
1544 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1545 kvm_run
->debug
.arch
.pc
=
1546 svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1547 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
1554 static int bp_interception(struct vcpu_svm
*svm
)
1556 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1558 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
1559 kvm_run
->debug
.arch
.pc
= svm
->vmcb
->save
.cs
.base
+ svm
->vmcb
->save
.rip
;
1560 kvm_run
->debug
.arch
.exception
= BP_VECTOR
;
1564 static int ud_interception(struct vcpu_svm
*svm
)
1568 er
= emulate_instruction(&svm
->vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
1569 if (er
!= EMULATE_DONE
)
1570 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1574 static void svm_fpu_activate(struct kvm_vcpu
*vcpu
)
1576 struct vcpu_svm
*svm
= to_svm(vcpu
);
1578 clr_exception_intercept(svm
, NM_VECTOR
);
1580 svm
->vcpu
.fpu_active
= 1;
1581 update_cr0_intercept(svm
);
1584 static int nm_interception(struct vcpu_svm
*svm
)
1586 svm_fpu_activate(&svm
->vcpu
);
1590 static bool is_erratum_383(void)
1595 if (!erratum_383_found
)
1598 value
= native_read_msr_safe(MSR_IA32_MC0_STATUS
, &err
);
1602 /* Bit 62 may or may not be set for this mce */
1603 value
&= ~(1ULL << 62);
1605 if (value
!= 0xb600000000010015ULL
)
1608 /* Clear MCi_STATUS registers */
1609 for (i
= 0; i
< 6; ++i
)
1610 native_write_msr_safe(MSR_IA32_MCx_STATUS(i
), 0, 0);
1612 value
= native_read_msr_safe(MSR_IA32_MCG_STATUS
, &err
);
1616 value
&= ~(1ULL << 2);
1617 low
= lower_32_bits(value
);
1618 high
= upper_32_bits(value
);
1620 native_write_msr_safe(MSR_IA32_MCG_STATUS
, low
, high
);
1623 /* Flush tlb to evict multi-match entries */
1629 static void svm_handle_mce(struct vcpu_svm
*svm
)
1631 if (is_erratum_383()) {
1633 * Erratum 383 triggered. Guest state is corrupt so kill the
1636 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1638 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, &svm
->vcpu
);
1644 * On an #MC intercept the MCE handler is not called automatically in
1645 * the host. So do it by hand here.
1649 /* not sure if we ever come back to this point */
1654 static int mc_interception(struct vcpu_svm
*svm
)
1659 static int shutdown_interception(struct vcpu_svm
*svm
)
1661 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
1664 * VMCB is undefined after a SHUTDOWN intercept
1665 * so reinitialize it.
1667 clear_page(svm
->vmcb
);
1670 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
1674 static int io_interception(struct vcpu_svm
*svm
)
1676 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
1677 u32 io_info
= svm
->vmcb
->control
.exit_info_1
; /* address size bug? */
1678 int size
, in
, string
;
1681 ++svm
->vcpu
.stat
.io_exits
;
1682 string
= (io_info
& SVM_IOIO_STR_MASK
) != 0;
1683 in
= (io_info
& SVM_IOIO_TYPE_MASK
) != 0;
1685 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
1687 port
= io_info
>> 16;
1688 size
= (io_info
& SVM_IOIO_SIZE_MASK
) >> SVM_IOIO_SIZE_SHIFT
;
1689 svm
->next_rip
= svm
->vmcb
->control
.exit_info_2
;
1690 skip_emulated_instruction(&svm
->vcpu
);
1692 return kvm_fast_pio_out(vcpu
, size
, port
);
1695 static int nmi_interception(struct vcpu_svm
*svm
)
1700 static int intr_interception(struct vcpu_svm
*svm
)
1702 ++svm
->vcpu
.stat
.irq_exits
;
1706 static int nop_on_interception(struct vcpu_svm
*svm
)
1711 static int halt_interception(struct vcpu_svm
*svm
)
1713 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 1;
1714 skip_emulated_instruction(&svm
->vcpu
);
1715 return kvm_emulate_halt(&svm
->vcpu
);
1718 static int vmmcall_interception(struct vcpu_svm
*svm
)
1720 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
1721 skip_emulated_instruction(&svm
->vcpu
);
1722 kvm_emulate_hypercall(&svm
->vcpu
);
1726 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu
*vcpu
)
1728 struct vcpu_svm
*svm
= to_svm(vcpu
);
1730 return svm
->nested
.nested_cr3
;
1733 static void nested_svm_set_tdp_cr3(struct kvm_vcpu
*vcpu
,
1736 struct vcpu_svm
*svm
= to_svm(vcpu
);
1738 svm
->vmcb
->control
.nested_cr3
= root
;
1739 force_new_asid(vcpu
);
1742 static void nested_svm_inject_npf_exit(struct kvm_vcpu
*vcpu
,
1743 struct x86_exception
*fault
)
1745 struct vcpu_svm
*svm
= to_svm(vcpu
);
1747 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NPF
;
1748 svm
->vmcb
->control
.exit_code_hi
= 0;
1749 svm
->vmcb
->control
.exit_info_1
= fault
->error_code
;
1750 svm
->vmcb
->control
.exit_info_2
= fault
->address
;
1752 nested_svm_vmexit(svm
);
1755 static int nested_svm_init_mmu_context(struct kvm_vcpu
*vcpu
)
1759 r
= kvm_init_shadow_mmu(vcpu
, &vcpu
->arch
.mmu
);
1761 vcpu
->arch
.mmu
.set_cr3
= nested_svm_set_tdp_cr3
;
1762 vcpu
->arch
.mmu
.get_cr3
= nested_svm_get_tdp_cr3
;
1763 vcpu
->arch
.mmu
.inject_page_fault
= nested_svm_inject_npf_exit
;
1764 vcpu
->arch
.mmu
.shadow_root_level
= get_npt_level();
1765 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
1770 static void nested_svm_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
1772 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
1775 static int nested_svm_check_permissions(struct vcpu_svm
*svm
)
1777 if (!(svm
->vcpu
.arch
.efer
& EFER_SVME
)
1778 || !is_paging(&svm
->vcpu
)) {
1779 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
1783 if (svm
->vmcb
->save
.cpl
) {
1784 kvm_inject_gp(&svm
->vcpu
, 0);
1791 static int nested_svm_check_exception(struct vcpu_svm
*svm
, unsigned nr
,
1792 bool has_error_code
, u32 error_code
)
1796 if (!is_guest_mode(&svm
->vcpu
))
1799 svm
->vmcb
->control
.exit_code
= SVM_EXIT_EXCP_BASE
+ nr
;
1800 svm
->vmcb
->control
.exit_code_hi
= 0;
1801 svm
->vmcb
->control
.exit_info_1
= error_code
;
1802 svm
->vmcb
->control
.exit_info_2
= svm
->vcpu
.arch
.cr2
;
1804 vmexit
= nested_svm_intercept(svm
);
1805 if (vmexit
== NESTED_EXIT_DONE
)
1806 svm
->nested
.exit_required
= true;
1811 /* This function returns true if it is save to enable the irq window */
1812 static inline bool nested_svm_intr(struct vcpu_svm
*svm
)
1814 if (!is_guest_mode(&svm
->vcpu
))
1817 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
1820 if (!(svm
->vcpu
.arch
.hflags
& HF_HIF_MASK
))
1824 * if vmexit was already requested (by intercepted exception
1825 * for instance) do not overwrite it with "external interrupt"
1828 if (svm
->nested
.exit_required
)
1831 svm
->vmcb
->control
.exit_code
= SVM_EXIT_INTR
;
1832 svm
->vmcb
->control
.exit_info_1
= 0;
1833 svm
->vmcb
->control
.exit_info_2
= 0;
1835 if (svm
->nested
.intercept
& 1ULL) {
1837 * The #vmexit can't be emulated here directly because this
1838 * code path runs with irqs and preemtion disabled. A
1839 * #vmexit emulation might sleep. Only signal request for
1842 svm
->nested
.exit_required
= true;
1843 trace_kvm_nested_intr_vmexit(svm
->vmcb
->save
.rip
);
1850 /* This function returns true if it is save to enable the nmi window */
1851 static inline bool nested_svm_nmi(struct vcpu_svm
*svm
)
1853 if (!is_guest_mode(&svm
->vcpu
))
1856 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_NMI
)))
1859 svm
->vmcb
->control
.exit_code
= SVM_EXIT_NMI
;
1860 svm
->nested
.exit_required
= true;
1865 static void *nested_svm_map(struct vcpu_svm
*svm
, u64 gpa
, struct page
**_page
)
1871 page
= gfn_to_page(svm
->vcpu
.kvm
, gpa
>> PAGE_SHIFT
);
1872 if (is_error_page(page
))
1880 kvm_release_page_clean(page
);
1881 kvm_inject_gp(&svm
->vcpu
, 0);
1886 static void nested_svm_unmap(struct page
*page
)
1889 kvm_release_page_dirty(page
);
1892 static int nested_svm_intercept_ioio(struct vcpu_svm
*svm
)
1898 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_IOIO_PROT
)))
1899 return NESTED_EXIT_HOST
;
1901 port
= svm
->vmcb
->control
.exit_info_1
>> 16;
1902 gpa
= svm
->nested
.vmcb_iopm
+ (port
/ 8);
1906 if (kvm_read_guest(svm
->vcpu
.kvm
, gpa
, &val
, 1))
1909 return val
? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1912 static int nested_svm_exit_handled_msr(struct vcpu_svm
*svm
)
1914 u32 offset
, msr
, value
;
1917 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
1918 return NESTED_EXIT_HOST
;
1920 msr
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
1921 offset
= svm_msrpm_offset(msr
);
1922 write
= svm
->vmcb
->control
.exit_info_1
& 1;
1923 mask
= 1 << ((2 * (msr
& 0xf)) + write
);
1925 if (offset
== MSR_INVALID
)
1926 return NESTED_EXIT_DONE
;
1928 /* Offset is in 32 bit units but need in 8 bit units */
1931 if (kvm_read_guest(svm
->vcpu
.kvm
, svm
->nested
.vmcb_msrpm
+ offset
, &value
, 4))
1932 return NESTED_EXIT_DONE
;
1934 return (value
& mask
) ? NESTED_EXIT_DONE
: NESTED_EXIT_HOST
;
1937 static int nested_svm_exit_special(struct vcpu_svm
*svm
)
1939 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1941 switch (exit_code
) {
1944 case SVM_EXIT_EXCP_BASE
+ MC_VECTOR
:
1945 return NESTED_EXIT_HOST
;
1947 /* For now we are always handling NPFs when using them */
1949 return NESTED_EXIT_HOST
;
1951 case SVM_EXIT_EXCP_BASE
+ PF_VECTOR
:
1952 /* When we're shadowing, trap PFs, but not async PF */
1953 if (!npt_enabled
&& svm
->apf_reason
== 0)
1954 return NESTED_EXIT_HOST
;
1956 case SVM_EXIT_EXCP_BASE
+ NM_VECTOR
:
1957 nm_interception(svm
);
1963 return NESTED_EXIT_CONTINUE
;
1967 * If this function returns true, this #vmexit was already handled
1969 static int nested_svm_intercept(struct vcpu_svm
*svm
)
1971 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
1972 int vmexit
= NESTED_EXIT_HOST
;
1974 switch (exit_code
) {
1976 vmexit
= nested_svm_exit_handled_msr(svm
);
1979 vmexit
= nested_svm_intercept_ioio(svm
);
1981 case SVM_EXIT_READ_CR0
... SVM_EXIT_WRITE_CR8
: {
1982 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_CR0
);
1983 if (svm
->nested
.intercept_cr
& bit
)
1984 vmexit
= NESTED_EXIT_DONE
;
1987 case SVM_EXIT_READ_DR0
... SVM_EXIT_WRITE_DR7
: {
1988 u32 bit
= 1U << (exit_code
- SVM_EXIT_READ_DR0
);
1989 if (svm
->nested
.intercept_dr
& bit
)
1990 vmexit
= NESTED_EXIT_DONE
;
1993 case SVM_EXIT_EXCP_BASE
... SVM_EXIT_EXCP_BASE
+ 0x1f: {
1994 u32 excp_bits
= 1 << (exit_code
- SVM_EXIT_EXCP_BASE
);
1995 if (svm
->nested
.intercept_exceptions
& excp_bits
)
1996 vmexit
= NESTED_EXIT_DONE
;
1997 /* async page fault always cause vmexit */
1998 else if ((exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
) &&
1999 svm
->apf_reason
!= 0)
2000 vmexit
= NESTED_EXIT_DONE
;
2003 case SVM_EXIT_ERR
: {
2004 vmexit
= NESTED_EXIT_DONE
;
2008 u64 exit_bits
= 1ULL << (exit_code
- SVM_EXIT_INTR
);
2009 if (svm
->nested
.intercept
& exit_bits
)
2010 vmexit
= NESTED_EXIT_DONE
;
2017 static int nested_svm_exit_handled(struct vcpu_svm
*svm
)
2021 vmexit
= nested_svm_intercept(svm
);
2023 if (vmexit
== NESTED_EXIT_DONE
)
2024 nested_svm_vmexit(svm
);
2029 static inline void copy_vmcb_control_area(struct vmcb
*dst_vmcb
, struct vmcb
*from_vmcb
)
2031 struct vmcb_control_area
*dst
= &dst_vmcb
->control
;
2032 struct vmcb_control_area
*from
= &from_vmcb
->control
;
2034 dst
->intercept_cr
= from
->intercept_cr
;
2035 dst
->intercept_dr
= from
->intercept_dr
;
2036 dst
->intercept_exceptions
= from
->intercept_exceptions
;
2037 dst
->intercept
= from
->intercept
;
2038 dst
->iopm_base_pa
= from
->iopm_base_pa
;
2039 dst
->msrpm_base_pa
= from
->msrpm_base_pa
;
2040 dst
->tsc_offset
= from
->tsc_offset
;
2041 dst
->asid
= from
->asid
;
2042 dst
->tlb_ctl
= from
->tlb_ctl
;
2043 dst
->int_ctl
= from
->int_ctl
;
2044 dst
->int_vector
= from
->int_vector
;
2045 dst
->int_state
= from
->int_state
;
2046 dst
->exit_code
= from
->exit_code
;
2047 dst
->exit_code_hi
= from
->exit_code_hi
;
2048 dst
->exit_info_1
= from
->exit_info_1
;
2049 dst
->exit_info_2
= from
->exit_info_2
;
2050 dst
->exit_int_info
= from
->exit_int_info
;
2051 dst
->exit_int_info_err
= from
->exit_int_info_err
;
2052 dst
->nested_ctl
= from
->nested_ctl
;
2053 dst
->event_inj
= from
->event_inj
;
2054 dst
->event_inj_err
= from
->event_inj_err
;
2055 dst
->nested_cr3
= from
->nested_cr3
;
2056 dst
->lbr_ctl
= from
->lbr_ctl
;
2059 static int nested_svm_vmexit(struct vcpu_svm
*svm
)
2061 struct vmcb
*nested_vmcb
;
2062 struct vmcb
*hsave
= svm
->nested
.hsave
;
2063 struct vmcb
*vmcb
= svm
->vmcb
;
2066 trace_kvm_nested_vmexit_inject(vmcb
->control
.exit_code
,
2067 vmcb
->control
.exit_info_1
,
2068 vmcb
->control
.exit_info_2
,
2069 vmcb
->control
.exit_int_info
,
2070 vmcb
->control
.exit_int_info_err
);
2072 nested_vmcb
= nested_svm_map(svm
, svm
->nested
.vmcb
, &page
);
2076 /* Exit Guest-Mode */
2077 leave_guest_mode(&svm
->vcpu
);
2078 svm
->nested
.vmcb
= 0;
2080 /* Give the current vmcb to the guest */
2083 nested_vmcb
->save
.es
= vmcb
->save
.es
;
2084 nested_vmcb
->save
.cs
= vmcb
->save
.cs
;
2085 nested_vmcb
->save
.ss
= vmcb
->save
.ss
;
2086 nested_vmcb
->save
.ds
= vmcb
->save
.ds
;
2087 nested_vmcb
->save
.gdtr
= vmcb
->save
.gdtr
;
2088 nested_vmcb
->save
.idtr
= vmcb
->save
.idtr
;
2089 nested_vmcb
->save
.efer
= svm
->vcpu
.arch
.efer
;
2090 nested_vmcb
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2091 nested_vmcb
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2092 nested_vmcb
->save
.cr2
= vmcb
->save
.cr2
;
2093 nested_vmcb
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2094 nested_vmcb
->save
.rflags
= vmcb
->save
.rflags
;
2095 nested_vmcb
->save
.rip
= vmcb
->save
.rip
;
2096 nested_vmcb
->save
.rsp
= vmcb
->save
.rsp
;
2097 nested_vmcb
->save
.rax
= vmcb
->save
.rax
;
2098 nested_vmcb
->save
.dr7
= vmcb
->save
.dr7
;
2099 nested_vmcb
->save
.dr6
= vmcb
->save
.dr6
;
2100 nested_vmcb
->save
.cpl
= vmcb
->save
.cpl
;
2102 nested_vmcb
->control
.int_ctl
= vmcb
->control
.int_ctl
;
2103 nested_vmcb
->control
.int_vector
= vmcb
->control
.int_vector
;
2104 nested_vmcb
->control
.int_state
= vmcb
->control
.int_state
;
2105 nested_vmcb
->control
.exit_code
= vmcb
->control
.exit_code
;
2106 nested_vmcb
->control
.exit_code_hi
= vmcb
->control
.exit_code_hi
;
2107 nested_vmcb
->control
.exit_info_1
= vmcb
->control
.exit_info_1
;
2108 nested_vmcb
->control
.exit_info_2
= vmcb
->control
.exit_info_2
;
2109 nested_vmcb
->control
.exit_int_info
= vmcb
->control
.exit_int_info
;
2110 nested_vmcb
->control
.exit_int_info_err
= vmcb
->control
.exit_int_info_err
;
2111 nested_vmcb
->control
.next_rip
= vmcb
->control
.next_rip
;
2114 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2115 * to make sure that we do not lose injected events. So check event_inj
2116 * here and copy it to exit_int_info if it is valid.
2117 * Exit_int_info and event_inj can't be both valid because the case
2118 * below only happens on a VMRUN instruction intercept which has
2119 * no valid exit_int_info set.
2121 if (vmcb
->control
.event_inj
& SVM_EVTINJ_VALID
) {
2122 struct vmcb_control_area
*nc
= &nested_vmcb
->control
;
2124 nc
->exit_int_info
= vmcb
->control
.event_inj
;
2125 nc
->exit_int_info_err
= vmcb
->control
.event_inj_err
;
2128 nested_vmcb
->control
.tlb_ctl
= 0;
2129 nested_vmcb
->control
.event_inj
= 0;
2130 nested_vmcb
->control
.event_inj_err
= 0;
2132 /* We always set V_INTR_MASKING and remember the old value in hflags */
2133 if (!(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
))
2134 nested_vmcb
->control
.int_ctl
&= ~V_INTR_MASKING_MASK
;
2136 /* Restore the original control entries */
2137 copy_vmcb_control_area(vmcb
, hsave
);
2139 kvm_clear_exception_queue(&svm
->vcpu
);
2140 kvm_clear_interrupt_queue(&svm
->vcpu
);
2142 svm
->nested
.nested_cr3
= 0;
2144 /* Restore selected save entries */
2145 svm
->vmcb
->save
.es
= hsave
->save
.es
;
2146 svm
->vmcb
->save
.cs
= hsave
->save
.cs
;
2147 svm
->vmcb
->save
.ss
= hsave
->save
.ss
;
2148 svm
->vmcb
->save
.ds
= hsave
->save
.ds
;
2149 svm
->vmcb
->save
.gdtr
= hsave
->save
.gdtr
;
2150 svm
->vmcb
->save
.idtr
= hsave
->save
.idtr
;
2151 svm
->vmcb
->save
.rflags
= hsave
->save
.rflags
;
2152 svm_set_efer(&svm
->vcpu
, hsave
->save
.efer
);
2153 svm_set_cr0(&svm
->vcpu
, hsave
->save
.cr0
| X86_CR0_PE
);
2154 svm_set_cr4(&svm
->vcpu
, hsave
->save
.cr4
);
2156 svm
->vmcb
->save
.cr3
= hsave
->save
.cr3
;
2157 svm
->vcpu
.arch
.cr3
= hsave
->save
.cr3
;
2159 (void)kvm_set_cr3(&svm
->vcpu
, hsave
->save
.cr3
);
2161 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, hsave
->save
.rax
);
2162 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, hsave
->save
.rsp
);
2163 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, hsave
->save
.rip
);
2164 svm
->vmcb
->save
.dr7
= 0;
2165 svm
->vmcb
->save
.cpl
= 0;
2166 svm
->vmcb
->control
.exit_int_info
= 0;
2168 mark_all_dirty(svm
->vmcb
);
2170 nested_svm_unmap(page
);
2172 nested_svm_uninit_mmu_context(&svm
->vcpu
);
2173 kvm_mmu_reset_context(&svm
->vcpu
);
2174 kvm_mmu_load(&svm
->vcpu
);
2179 static bool nested_svm_vmrun_msrpm(struct vcpu_svm
*svm
)
2182 * This function merges the msr permission bitmaps of kvm and the
2183 * nested vmcb. It is omptimized in that it only merges the parts where
2184 * the kvm msr permission bitmap may contain zero bits
2188 if (!(svm
->nested
.intercept
& (1ULL << INTERCEPT_MSR_PROT
)))
2191 for (i
= 0; i
< MSRPM_OFFSETS
; i
++) {
2195 if (msrpm_offsets
[i
] == 0xffffffff)
2198 p
= msrpm_offsets
[i
];
2199 offset
= svm
->nested
.vmcb_msrpm
+ (p
* 4);
2201 if (kvm_read_guest(svm
->vcpu
.kvm
, offset
, &value
, 4))
2204 svm
->nested
.msrpm
[p
] = svm
->msrpm
[p
] | value
;
2207 svm
->vmcb
->control
.msrpm_base_pa
= __pa(svm
->nested
.msrpm
);
2212 static bool nested_vmcb_checks(struct vmcb
*vmcb
)
2214 if ((vmcb
->control
.intercept
& (1ULL << INTERCEPT_VMRUN
)) == 0)
2217 if (vmcb
->control
.asid
== 0)
2220 if (vmcb
->control
.nested_ctl
&& !npt_enabled
)
2226 static bool nested_svm_vmrun(struct vcpu_svm
*svm
)
2228 struct vmcb
*nested_vmcb
;
2229 struct vmcb
*hsave
= svm
->nested
.hsave
;
2230 struct vmcb
*vmcb
= svm
->vmcb
;
2234 vmcb_gpa
= svm
->vmcb
->save
.rax
;
2236 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2240 if (!nested_vmcb_checks(nested_vmcb
)) {
2241 nested_vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2242 nested_vmcb
->control
.exit_code_hi
= 0;
2243 nested_vmcb
->control
.exit_info_1
= 0;
2244 nested_vmcb
->control
.exit_info_2
= 0;
2246 nested_svm_unmap(page
);
2251 trace_kvm_nested_vmrun(svm
->vmcb
->save
.rip
, vmcb_gpa
,
2252 nested_vmcb
->save
.rip
,
2253 nested_vmcb
->control
.int_ctl
,
2254 nested_vmcb
->control
.event_inj
,
2255 nested_vmcb
->control
.nested_ctl
);
2257 trace_kvm_nested_intercepts(nested_vmcb
->control
.intercept_cr
& 0xffff,
2258 nested_vmcb
->control
.intercept_cr
>> 16,
2259 nested_vmcb
->control
.intercept_exceptions
,
2260 nested_vmcb
->control
.intercept
);
2262 /* Clear internal status */
2263 kvm_clear_exception_queue(&svm
->vcpu
);
2264 kvm_clear_interrupt_queue(&svm
->vcpu
);
2267 * Save the old vmcb, so we don't need to pick what we save, but can
2268 * restore everything when a VMEXIT occurs
2270 hsave
->save
.es
= vmcb
->save
.es
;
2271 hsave
->save
.cs
= vmcb
->save
.cs
;
2272 hsave
->save
.ss
= vmcb
->save
.ss
;
2273 hsave
->save
.ds
= vmcb
->save
.ds
;
2274 hsave
->save
.gdtr
= vmcb
->save
.gdtr
;
2275 hsave
->save
.idtr
= vmcb
->save
.idtr
;
2276 hsave
->save
.efer
= svm
->vcpu
.arch
.efer
;
2277 hsave
->save
.cr0
= kvm_read_cr0(&svm
->vcpu
);
2278 hsave
->save
.cr4
= svm
->vcpu
.arch
.cr4
;
2279 hsave
->save
.rflags
= vmcb
->save
.rflags
;
2280 hsave
->save
.rip
= kvm_rip_read(&svm
->vcpu
);
2281 hsave
->save
.rsp
= vmcb
->save
.rsp
;
2282 hsave
->save
.rax
= vmcb
->save
.rax
;
2284 hsave
->save
.cr3
= vmcb
->save
.cr3
;
2286 hsave
->save
.cr3
= svm
->vcpu
.arch
.cr3
;
2288 copy_vmcb_control_area(hsave
, vmcb
);
2290 if (svm
->vmcb
->save
.rflags
& X86_EFLAGS_IF
)
2291 svm
->vcpu
.arch
.hflags
|= HF_HIF_MASK
;
2293 svm
->vcpu
.arch
.hflags
&= ~HF_HIF_MASK
;
2295 if (nested_vmcb
->control
.nested_ctl
) {
2296 kvm_mmu_unload(&svm
->vcpu
);
2297 svm
->nested
.nested_cr3
= nested_vmcb
->control
.nested_cr3
;
2298 nested_svm_init_mmu_context(&svm
->vcpu
);
2301 /* Load the nested guest state */
2302 svm
->vmcb
->save
.es
= nested_vmcb
->save
.es
;
2303 svm
->vmcb
->save
.cs
= nested_vmcb
->save
.cs
;
2304 svm
->vmcb
->save
.ss
= nested_vmcb
->save
.ss
;
2305 svm
->vmcb
->save
.ds
= nested_vmcb
->save
.ds
;
2306 svm
->vmcb
->save
.gdtr
= nested_vmcb
->save
.gdtr
;
2307 svm
->vmcb
->save
.idtr
= nested_vmcb
->save
.idtr
;
2308 svm
->vmcb
->save
.rflags
= nested_vmcb
->save
.rflags
;
2309 svm_set_efer(&svm
->vcpu
, nested_vmcb
->save
.efer
);
2310 svm_set_cr0(&svm
->vcpu
, nested_vmcb
->save
.cr0
);
2311 svm_set_cr4(&svm
->vcpu
, nested_vmcb
->save
.cr4
);
2313 svm
->vmcb
->save
.cr3
= nested_vmcb
->save
.cr3
;
2314 svm
->vcpu
.arch
.cr3
= nested_vmcb
->save
.cr3
;
2316 (void)kvm_set_cr3(&svm
->vcpu
, nested_vmcb
->save
.cr3
);
2318 /* Guest paging mode is active - reset mmu */
2319 kvm_mmu_reset_context(&svm
->vcpu
);
2321 svm
->vmcb
->save
.cr2
= svm
->vcpu
.arch
.cr2
= nested_vmcb
->save
.cr2
;
2322 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RAX
, nested_vmcb
->save
.rax
);
2323 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RSP
, nested_vmcb
->save
.rsp
);
2324 kvm_register_write(&svm
->vcpu
, VCPU_REGS_RIP
, nested_vmcb
->save
.rip
);
2326 /* In case we don't even reach vcpu_run, the fields are not updated */
2327 svm
->vmcb
->save
.rax
= nested_vmcb
->save
.rax
;
2328 svm
->vmcb
->save
.rsp
= nested_vmcb
->save
.rsp
;
2329 svm
->vmcb
->save
.rip
= nested_vmcb
->save
.rip
;
2330 svm
->vmcb
->save
.dr7
= nested_vmcb
->save
.dr7
;
2331 svm
->vmcb
->save
.dr6
= nested_vmcb
->save
.dr6
;
2332 svm
->vmcb
->save
.cpl
= nested_vmcb
->save
.cpl
;
2334 svm
->nested
.vmcb_msrpm
= nested_vmcb
->control
.msrpm_base_pa
& ~0x0fffULL
;
2335 svm
->nested
.vmcb_iopm
= nested_vmcb
->control
.iopm_base_pa
& ~0x0fffULL
;
2337 /* cache intercepts */
2338 svm
->nested
.intercept_cr
= nested_vmcb
->control
.intercept_cr
;
2339 svm
->nested
.intercept_dr
= nested_vmcb
->control
.intercept_dr
;
2340 svm
->nested
.intercept_exceptions
= nested_vmcb
->control
.intercept_exceptions
;
2341 svm
->nested
.intercept
= nested_vmcb
->control
.intercept
;
2343 force_new_asid(&svm
->vcpu
);
2344 svm
->vmcb
->control
.int_ctl
= nested_vmcb
->control
.int_ctl
| V_INTR_MASKING_MASK
;
2345 if (nested_vmcb
->control
.int_ctl
& V_INTR_MASKING_MASK
)
2346 svm
->vcpu
.arch
.hflags
|= HF_VINTR_MASK
;
2348 svm
->vcpu
.arch
.hflags
&= ~HF_VINTR_MASK
;
2350 if (svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
) {
2351 /* We only want the cr8 intercept bits of the guest */
2352 clr_cr_intercept(svm
, INTERCEPT_CR8_READ
);
2353 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2356 /* We don't want to see VMMCALLs from a nested guest */
2357 clr_intercept(svm
, INTERCEPT_VMMCALL
);
2359 svm
->vmcb
->control
.lbr_ctl
= nested_vmcb
->control
.lbr_ctl
;
2360 svm
->vmcb
->control
.int_vector
= nested_vmcb
->control
.int_vector
;
2361 svm
->vmcb
->control
.int_state
= nested_vmcb
->control
.int_state
;
2362 svm
->vmcb
->control
.tsc_offset
+= nested_vmcb
->control
.tsc_offset
;
2363 svm
->vmcb
->control
.event_inj
= nested_vmcb
->control
.event_inj
;
2364 svm
->vmcb
->control
.event_inj_err
= nested_vmcb
->control
.event_inj_err
;
2366 nested_svm_unmap(page
);
2368 /* Enter Guest-Mode */
2369 enter_guest_mode(&svm
->vcpu
);
2372 * Merge guest and host intercepts - must be called with vcpu in
2373 * guest-mode to take affect here
2375 recalc_intercepts(svm
);
2377 svm
->nested
.vmcb
= vmcb_gpa
;
2381 mark_all_dirty(svm
->vmcb
);
2386 static void nested_svm_vmloadsave(struct vmcb
*from_vmcb
, struct vmcb
*to_vmcb
)
2388 to_vmcb
->save
.fs
= from_vmcb
->save
.fs
;
2389 to_vmcb
->save
.gs
= from_vmcb
->save
.gs
;
2390 to_vmcb
->save
.tr
= from_vmcb
->save
.tr
;
2391 to_vmcb
->save
.ldtr
= from_vmcb
->save
.ldtr
;
2392 to_vmcb
->save
.kernel_gs_base
= from_vmcb
->save
.kernel_gs_base
;
2393 to_vmcb
->save
.star
= from_vmcb
->save
.star
;
2394 to_vmcb
->save
.lstar
= from_vmcb
->save
.lstar
;
2395 to_vmcb
->save
.cstar
= from_vmcb
->save
.cstar
;
2396 to_vmcb
->save
.sfmask
= from_vmcb
->save
.sfmask
;
2397 to_vmcb
->save
.sysenter_cs
= from_vmcb
->save
.sysenter_cs
;
2398 to_vmcb
->save
.sysenter_esp
= from_vmcb
->save
.sysenter_esp
;
2399 to_vmcb
->save
.sysenter_eip
= from_vmcb
->save
.sysenter_eip
;
2402 static int vmload_interception(struct vcpu_svm
*svm
)
2404 struct vmcb
*nested_vmcb
;
2407 if (nested_svm_check_permissions(svm
))
2410 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2411 skip_emulated_instruction(&svm
->vcpu
);
2413 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2417 nested_svm_vmloadsave(nested_vmcb
, svm
->vmcb
);
2418 nested_svm_unmap(page
);
2423 static int vmsave_interception(struct vcpu_svm
*svm
)
2425 struct vmcb
*nested_vmcb
;
2428 if (nested_svm_check_permissions(svm
))
2431 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2432 skip_emulated_instruction(&svm
->vcpu
);
2434 nested_vmcb
= nested_svm_map(svm
, svm
->vmcb
->save
.rax
, &page
);
2438 nested_svm_vmloadsave(svm
->vmcb
, nested_vmcb
);
2439 nested_svm_unmap(page
);
2444 static int vmrun_interception(struct vcpu_svm
*svm
)
2446 if (nested_svm_check_permissions(svm
))
2449 /* Save rip after vmrun instruction */
2450 kvm_rip_write(&svm
->vcpu
, kvm_rip_read(&svm
->vcpu
) + 3);
2452 if (!nested_svm_vmrun(svm
))
2455 if (!nested_svm_vmrun_msrpm(svm
))
2462 svm
->vmcb
->control
.exit_code
= SVM_EXIT_ERR
;
2463 svm
->vmcb
->control
.exit_code_hi
= 0;
2464 svm
->vmcb
->control
.exit_info_1
= 0;
2465 svm
->vmcb
->control
.exit_info_2
= 0;
2467 nested_svm_vmexit(svm
);
2472 static int stgi_interception(struct vcpu_svm
*svm
)
2474 if (nested_svm_check_permissions(svm
))
2477 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2478 skip_emulated_instruction(&svm
->vcpu
);
2479 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2486 static int clgi_interception(struct vcpu_svm
*svm
)
2488 if (nested_svm_check_permissions(svm
))
2491 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2492 skip_emulated_instruction(&svm
->vcpu
);
2496 /* After a CLGI no interrupts should come */
2497 svm_clear_vintr(svm
);
2498 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2503 static int invlpga_interception(struct vcpu_svm
*svm
)
2505 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2507 trace_kvm_invlpga(svm
->vmcb
->save
.rip
, vcpu
->arch
.regs
[VCPU_REGS_RCX
],
2508 vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2510 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2511 kvm_mmu_invlpg(vcpu
, vcpu
->arch
.regs
[VCPU_REGS_RAX
]);
2513 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 3;
2514 skip_emulated_instruction(&svm
->vcpu
);
2518 static int skinit_interception(struct vcpu_svm
*svm
)
2520 trace_kvm_skinit(svm
->vmcb
->save
.rip
, svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
]);
2522 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2526 static int invalid_op_interception(struct vcpu_svm
*svm
)
2528 kvm_queue_exception(&svm
->vcpu
, UD_VECTOR
);
2532 static int task_switch_interception(struct vcpu_svm
*svm
)
2536 int int_type
= svm
->vmcb
->control
.exit_int_info
&
2537 SVM_EXITINTINFO_TYPE_MASK
;
2538 int int_vec
= svm
->vmcb
->control
.exit_int_info
& SVM_EVTINJ_VEC_MASK
;
2540 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_TYPE_MASK
;
2542 svm
->vmcb
->control
.exit_int_info
& SVM_EXITINTINFO_VALID
;
2543 bool has_error_code
= false;
2546 tss_selector
= (u16
)svm
->vmcb
->control
.exit_info_1
;
2548 if (svm
->vmcb
->control
.exit_info_2
&
2549 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET
))
2550 reason
= TASK_SWITCH_IRET
;
2551 else if (svm
->vmcb
->control
.exit_info_2
&
2552 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP
))
2553 reason
= TASK_SWITCH_JMP
;
2555 reason
= TASK_SWITCH_GATE
;
2557 reason
= TASK_SWITCH_CALL
;
2559 if (reason
== TASK_SWITCH_GATE
) {
2561 case SVM_EXITINTINFO_TYPE_NMI
:
2562 svm
->vcpu
.arch
.nmi_injected
= false;
2564 case SVM_EXITINTINFO_TYPE_EXEPT
:
2565 if (svm
->vmcb
->control
.exit_info_2
&
2566 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE
)) {
2567 has_error_code
= true;
2569 (u32
)svm
->vmcb
->control
.exit_info_2
;
2571 kvm_clear_exception_queue(&svm
->vcpu
);
2573 case SVM_EXITINTINFO_TYPE_INTR
:
2574 kvm_clear_interrupt_queue(&svm
->vcpu
);
2581 if (reason
!= TASK_SWITCH_GATE
||
2582 int_type
== SVM_EXITINTINFO_TYPE_SOFT
||
2583 (int_type
== SVM_EXITINTINFO_TYPE_EXEPT
&&
2584 (int_vec
== OF_VECTOR
|| int_vec
== BP_VECTOR
)))
2585 skip_emulated_instruction(&svm
->vcpu
);
2587 if (kvm_task_switch(&svm
->vcpu
, tss_selector
, reason
,
2588 has_error_code
, error_code
) == EMULATE_FAIL
) {
2589 svm
->vcpu
.run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2590 svm
->vcpu
.run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
2591 svm
->vcpu
.run
->internal
.ndata
= 0;
2597 static int cpuid_interception(struct vcpu_svm
*svm
)
2599 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2600 kvm_emulate_cpuid(&svm
->vcpu
);
2604 static int iret_interception(struct vcpu_svm
*svm
)
2606 ++svm
->vcpu
.stat
.nmi_window_exits
;
2607 clr_intercept(svm
, INTERCEPT_IRET
);
2608 svm
->vcpu
.arch
.hflags
|= HF_IRET_MASK
;
2612 static int invlpg_interception(struct vcpu_svm
*svm
)
2614 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2617 static int emulate_on_interception(struct vcpu_svm
*svm
)
2619 return emulate_instruction(&svm
->vcpu
, 0, 0, 0) == EMULATE_DONE
;
2622 static int cr0_write_interception(struct vcpu_svm
*svm
)
2624 struct kvm_vcpu
*vcpu
= &svm
->vcpu
;
2627 r
= emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2629 if (svm
->nested
.vmexit_rip
) {
2630 kvm_register_write(vcpu
, VCPU_REGS_RIP
, svm
->nested
.vmexit_rip
);
2631 kvm_register_write(vcpu
, VCPU_REGS_RSP
, svm
->nested
.vmexit_rsp
);
2632 kvm_register_write(vcpu
, VCPU_REGS_RAX
, svm
->nested
.vmexit_rax
);
2633 svm
->nested
.vmexit_rip
= 0;
2636 return r
== EMULATE_DONE
;
2639 static int cr8_write_interception(struct vcpu_svm
*svm
)
2641 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2643 u8 cr8_prev
= kvm_get_cr8(&svm
->vcpu
);
2644 /* instruction emulation calls kvm_set_cr8() */
2645 emulate_instruction(&svm
->vcpu
, 0, 0, 0);
2646 if (irqchip_in_kernel(svm
->vcpu
.kvm
)) {
2647 clr_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
2650 if (cr8_prev
<= kvm_get_cr8(&svm
->vcpu
))
2652 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2656 static int svm_get_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64
*data
)
2658 struct vcpu_svm
*svm
= to_svm(vcpu
);
2661 case MSR_IA32_TSC
: {
2662 struct vmcb
*vmcb
= get_host_vmcb(svm
);
2664 *data
= vmcb
->control
.tsc_offset
+ native_read_tsc();
2668 *data
= svm
->vmcb
->save
.star
;
2670 #ifdef CONFIG_X86_64
2672 *data
= svm
->vmcb
->save
.lstar
;
2675 *data
= svm
->vmcb
->save
.cstar
;
2677 case MSR_KERNEL_GS_BASE
:
2678 *data
= svm
->vmcb
->save
.kernel_gs_base
;
2680 case MSR_SYSCALL_MASK
:
2681 *data
= svm
->vmcb
->save
.sfmask
;
2684 case MSR_IA32_SYSENTER_CS
:
2685 *data
= svm
->vmcb
->save
.sysenter_cs
;
2687 case MSR_IA32_SYSENTER_EIP
:
2688 *data
= svm
->sysenter_eip
;
2690 case MSR_IA32_SYSENTER_ESP
:
2691 *data
= svm
->sysenter_esp
;
2694 * Nobody will change the following 5 values in the VMCB so we can
2695 * safely return them on rdmsr. They will always be 0 until LBRV is
2698 case MSR_IA32_DEBUGCTLMSR
:
2699 *data
= svm
->vmcb
->save
.dbgctl
;
2701 case MSR_IA32_LASTBRANCHFROMIP
:
2702 *data
= svm
->vmcb
->save
.br_from
;
2704 case MSR_IA32_LASTBRANCHTOIP
:
2705 *data
= svm
->vmcb
->save
.br_to
;
2707 case MSR_IA32_LASTINTFROMIP
:
2708 *data
= svm
->vmcb
->save
.last_excp_from
;
2710 case MSR_IA32_LASTINTTOIP
:
2711 *data
= svm
->vmcb
->save
.last_excp_to
;
2713 case MSR_VM_HSAVE_PA
:
2714 *data
= svm
->nested
.hsave_msr
;
2717 *data
= svm
->nested
.vm_cr_msr
;
2719 case MSR_IA32_UCODE_REV
:
2723 return kvm_get_msr_common(vcpu
, ecx
, data
);
2728 static int rdmsr_interception(struct vcpu_svm
*svm
)
2730 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2733 if (svm_get_msr(&svm
->vcpu
, ecx
, &data
)) {
2734 trace_kvm_msr_read_ex(ecx
);
2735 kvm_inject_gp(&svm
->vcpu
, 0);
2737 trace_kvm_msr_read(ecx
, data
);
2739 svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] = data
& 0xffffffff;
2740 svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = data
>> 32;
2741 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2742 skip_emulated_instruction(&svm
->vcpu
);
2747 static int svm_set_vm_cr(struct kvm_vcpu
*vcpu
, u64 data
)
2749 struct vcpu_svm
*svm
= to_svm(vcpu
);
2750 int svm_dis
, chg_mask
;
2752 if (data
& ~SVM_VM_CR_VALID_MASK
)
2755 chg_mask
= SVM_VM_CR_VALID_MASK
;
2757 if (svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
)
2758 chg_mask
&= ~(SVM_VM_CR_SVM_LOCK_MASK
| SVM_VM_CR_SVM_DIS_MASK
);
2760 svm
->nested
.vm_cr_msr
&= ~chg_mask
;
2761 svm
->nested
.vm_cr_msr
|= (data
& chg_mask
);
2763 svm_dis
= svm
->nested
.vm_cr_msr
& SVM_VM_CR_SVM_DIS_MASK
;
2765 /* check for svm_disable while efer.svme is set */
2766 if (svm_dis
&& (vcpu
->arch
.efer
& EFER_SVME
))
2772 static int svm_set_msr(struct kvm_vcpu
*vcpu
, unsigned ecx
, u64 data
)
2774 struct vcpu_svm
*svm
= to_svm(vcpu
);
2778 kvm_write_tsc(vcpu
, data
);
2781 svm
->vmcb
->save
.star
= data
;
2783 #ifdef CONFIG_X86_64
2785 svm
->vmcb
->save
.lstar
= data
;
2788 svm
->vmcb
->save
.cstar
= data
;
2790 case MSR_KERNEL_GS_BASE
:
2791 svm
->vmcb
->save
.kernel_gs_base
= data
;
2793 case MSR_SYSCALL_MASK
:
2794 svm
->vmcb
->save
.sfmask
= data
;
2797 case MSR_IA32_SYSENTER_CS
:
2798 svm
->vmcb
->save
.sysenter_cs
= data
;
2800 case MSR_IA32_SYSENTER_EIP
:
2801 svm
->sysenter_eip
= data
;
2802 svm
->vmcb
->save
.sysenter_eip
= data
;
2804 case MSR_IA32_SYSENTER_ESP
:
2805 svm
->sysenter_esp
= data
;
2806 svm
->vmcb
->save
.sysenter_esp
= data
;
2808 case MSR_IA32_DEBUGCTLMSR
:
2809 if (!boot_cpu_has(X86_FEATURE_LBRV
)) {
2810 pr_unimpl(vcpu
, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2814 if (data
& DEBUGCTL_RESERVED_BITS
)
2817 svm
->vmcb
->save
.dbgctl
= data
;
2818 if (data
& (1ULL<<0))
2819 svm_enable_lbrv(svm
);
2821 svm_disable_lbrv(svm
);
2823 case MSR_VM_HSAVE_PA
:
2824 svm
->nested
.hsave_msr
= data
;
2827 return svm_set_vm_cr(vcpu
, data
);
2829 pr_unimpl(vcpu
, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx
, data
);
2832 return kvm_set_msr_common(vcpu
, ecx
, data
);
2837 static int wrmsr_interception(struct vcpu_svm
*svm
)
2839 u32 ecx
= svm
->vcpu
.arch
.regs
[VCPU_REGS_RCX
];
2840 u64 data
= (svm
->vcpu
.arch
.regs
[VCPU_REGS_RAX
] & -1u)
2841 | ((u64
)(svm
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2844 svm
->next_rip
= kvm_rip_read(&svm
->vcpu
) + 2;
2845 if (svm_set_msr(&svm
->vcpu
, ecx
, data
)) {
2846 trace_kvm_msr_write_ex(ecx
, data
);
2847 kvm_inject_gp(&svm
->vcpu
, 0);
2849 trace_kvm_msr_write(ecx
, data
);
2850 skip_emulated_instruction(&svm
->vcpu
);
2855 static int msr_interception(struct vcpu_svm
*svm
)
2857 if (svm
->vmcb
->control
.exit_info_1
)
2858 return wrmsr_interception(svm
);
2860 return rdmsr_interception(svm
);
2863 static int interrupt_window_interception(struct vcpu_svm
*svm
)
2865 struct kvm_run
*kvm_run
= svm
->vcpu
.run
;
2867 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
2868 svm_clear_vintr(svm
);
2869 svm
->vmcb
->control
.int_ctl
&= ~V_IRQ_MASK
;
2871 * If the user space waits to inject interrupts, exit as soon as
2874 if (!irqchip_in_kernel(svm
->vcpu
.kvm
) &&
2875 kvm_run
->request_interrupt_window
&&
2876 !kvm_cpu_has_interrupt(&svm
->vcpu
)) {
2877 ++svm
->vcpu
.stat
.irq_window_exits
;
2878 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2885 static int pause_interception(struct vcpu_svm
*svm
)
2887 kvm_vcpu_on_spin(&(svm
->vcpu
));
2891 static int (*svm_exit_handlers
[])(struct vcpu_svm
*svm
) = {
2892 [SVM_EXIT_READ_CR0
] = emulate_on_interception
,
2893 [SVM_EXIT_READ_CR3
] = emulate_on_interception
,
2894 [SVM_EXIT_READ_CR4
] = emulate_on_interception
,
2895 [SVM_EXIT_READ_CR8
] = emulate_on_interception
,
2896 [SVM_EXIT_CR0_SEL_WRITE
] = emulate_on_interception
,
2897 [SVM_EXIT_WRITE_CR0
] = cr0_write_interception
,
2898 [SVM_EXIT_WRITE_CR3
] = emulate_on_interception
,
2899 [SVM_EXIT_WRITE_CR4
] = emulate_on_interception
,
2900 [SVM_EXIT_WRITE_CR8
] = cr8_write_interception
,
2901 [SVM_EXIT_READ_DR0
] = emulate_on_interception
,
2902 [SVM_EXIT_READ_DR1
] = emulate_on_interception
,
2903 [SVM_EXIT_READ_DR2
] = emulate_on_interception
,
2904 [SVM_EXIT_READ_DR3
] = emulate_on_interception
,
2905 [SVM_EXIT_READ_DR4
] = emulate_on_interception
,
2906 [SVM_EXIT_READ_DR5
] = emulate_on_interception
,
2907 [SVM_EXIT_READ_DR6
] = emulate_on_interception
,
2908 [SVM_EXIT_READ_DR7
] = emulate_on_interception
,
2909 [SVM_EXIT_WRITE_DR0
] = emulate_on_interception
,
2910 [SVM_EXIT_WRITE_DR1
] = emulate_on_interception
,
2911 [SVM_EXIT_WRITE_DR2
] = emulate_on_interception
,
2912 [SVM_EXIT_WRITE_DR3
] = emulate_on_interception
,
2913 [SVM_EXIT_WRITE_DR4
] = emulate_on_interception
,
2914 [SVM_EXIT_WRITE_DR5
] = emulate_on_interception
,
2915 [SVM_EXIT_WRITE_DR6
] = emulate_on_interception
,
2916 [SVM_EXIT_WRITE_DR7
] = emulate_on_interception
,
2917 [SVM_EXIT_EXCP_BASE
+ DB_VECTOR
] = db_interception
,
2918 [SVM_EXIT_EXCP_BASE
+ BP_VECTOR
] = bp_interception
,
2919 [SVM_EXIT_EXCP_BASE
+ UD_VECTOR
] = ud_interception
,
2920 [SVM_EXIT_EXCP_BASE
+ PF_VECTOR
] = pf_interception
,
2921 [SVM_EXIT_EXCP_BASE
+ NM_VECTOR
] = nm_interception
,
2922 [SVM_EXIT_EXCP_BASE
+ MC_VECTOR
] = mc_interception
,
2923 [SVM_EXIT_INTR
] = intr_interception
,
2924 [SVM_EXIT_NMI
] = nmi_interception
,
2925 [SVM_EXIT_SMI
] = nop_on_interception
,
2926 [SVM_EXIT_INIT
] = nop_on_interception
,
2927 [SVM_EXIT_VINTR
] = interrupt_window_interception
,
2928 [SVM_EXIT_CPUID
] = cpuid_interception
,
2929 [SVM_EXIT_IRET
] = iret_interception
,
2930 [SVM_EXIT_INVD
] = emulate_on_interception
,
2931 [SVM_EXIT_PAUSE
] = pause_interception
,
2932 [SVM_EXIT_HLT
] = halt_interception
,
2933 [SVM_EXIT_INVLPG
] = invlpg_interception
,
2934 [SVM_EXIT_INVLPGA
] = invlpga_interception
,
2935 [SVM_EXIT_IOIO
] = io_interception
,
2936 [SVM_EXIT_MSR
] = msr_interception
,
2937 [SVM_EXIT_TASK_SWITCH
] = task_switch_interception
,
2938 [SVM_EXIT_SHUTDOWN
] = shutdown_interception
,
2939 [SVM_EXIT_VMRUN
] = vmrun_interception
,
2940 [SVM_EXIT_VMMCALL
] = vmmcall_interception
,
2941 [SVM_EXIT_VMLOAD
] = vmload_interception
,
2942 [SVM_EXIT_VMSAVE
] = vmsave_interception
,
2943 [SVM_EXIT_STGI
] = stgi_interception
,
2944 [SVM_EXIT_CLGI
] = clgi_interception
,
2945 [SVM_EXIT_SKINIT
] = skinit_interception
,
2946 [SVM_EXIT_WBINVD
] = emulate_on_interception
,
2947 [SVM_EXIT_MONITOR
] = invalid_op_interception
,
2948 [SVM_EXIT_MWAIT
] = invalid_op_interception
,
2949 [SVM_EXIT_NPF
] = pf_interception
,
2952 void dump_vmcb(struct kvm_vcpu
*vcpu
)
2954 struct vcpu_svm
*svm
= to_svm(vcpu
);
2955 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
2956 struct vmcb_save_area
*save
= &svm
->vmcb
->save
;
2958 pr_err("VMCB Control Area:\n");
2959 pr_err("cr_read: %04x\n", control
->intercept_cr
& 0xffff);
2960 pr_err("cr_write: %04x\n", control
->intercept_cr
>> 16);
2961 pr_err("dr_read: %04x\n", control
->intercept_dr
& 0xffff);
2962 pr_err("dr_write: %04x\n", control
->intercept_dr
>> 16);
2963 pr_err("exceptions: %08x\n", control
->intercept_exceptions
);
2964 pr_err("intercepts: %016llx\n", control
->intercept
);
2965 pr_err("pause filter count: %d\n", control
->pause_filter_count
);
2966 pr_err("iopm_base_pa: %016llx\n", control
->iopm_base_pa
);
2967 pr_err("msrpm_base_pa: %016llx\n", control
->msrpm_base_pa
);
2968 pr_err("tsc_offset: %016llx\n", control
->tsc_offset
);
2969 pr_err("asid: %d\n", control
->asid
);
2970 pr_err("tlb_ctl: %d\n", control
->tlb_ctl
);
2971 pr_err("int_ctl: %08x\n", control
->int_ctl
);
2972 pr_err("int_vector: %08x\n", control
->int_vector
);
2973 pr_err("int_state: %08x\n", control
->int_state
);
2974 pr_err("exit_code: %08x\n", control
->exit_code
);
2975 pr_err("exit_info1: %016llx\n", control
->exit_info_1
);
2976 pr_err("exit_info2: %016llx\n", control
->exit_info_2
);
2977 pr_err("exit_int_info: %08x\n", control
->exit_int_info
);
2978 pr_err("exit_int_info_err: %08x\n", control
->exit_int_info_err
);
2979 pr_err("nested_ctl: %lld\n", control
->nested_ctl
);
2980 pr_err("nested_cr3: %016llx\n", control
->nested_cr3
);
2981 pr_err("event_inj: %08x\n", control
->event_inj
);
2982 pr_err("event_inj_err: %08x\n", control
->event_inj_err
);
2983 pr_err("lbr_ctl: %lld\n", control
->lbr_ctl
);
2984 pr_err("next_rip: %016llx\n", control
->next_rip
);
2985 pr_err("VMCB State Save Area:\n");
2986 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
2987 save
->es
.selector
, save
->es
.attrib
,
2988 save
->es
.limit
, save
->es
.base
);
2989 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
2990 save
->cs
.selector
, save
->cs
.attrib
,
2991 save
->cs
.limit
, save
->cs
.base
);
2992 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
2993 save
->ss
.selector
, save
->ss
.attrib
,
2994 save
->ss
.limit
, save
->ss
.base
);
2995 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
2996 save
->ds
.selector
, save
->ds
.attrib
,
2997 save
->ds
.limit
, save
->ds
.base
);
2998 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
2999 save
->fs
.selector
, save
->fs
.attrib
,
3000 save
->fs
.limit
, save
->fs
.base
);
3001 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3002 save
->gs
.selector
, save
->gs
.attrib
,
3003 save
->gs
.limit
, save
->gs
.base
);
3004 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3005 save
->gdtr
.selector
, save
->gdtr
.attrib
,
3006 save
->gdtr
.limit
, save
->gdtr
.base
);
3007 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3008 save
->ldtr
.selector
, save
->ldtr
.attrib
,
3009 save
->ldtr
.limit
, save
->ldtr
.base
);
3010 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3011 save
->idtr
.selector
, save
->idtr
.attrib
,
3012 save
->idtr
.limit
, save
->idtr
.base
);
3013 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3014 save
->tr
.selector
, save
->tr
.attrib
,
3015 save
->tr
.limit
, save
->tr
.base
);
3016 pr_err("cpl: %d efer: %016llx\n",
3017 save
->cpl
, save
->efer
);
3018 pr_err("cr0: %016llx cr2: %016llx\n",
3019 save
->cr0
, save
->cr2
);
3020 pr_err("cr3: %016llx cr4: %016llx\n",
3021 save
->cr3
, save
->cr4
);
3022 pr_err("dr6: %016llx dr7: %016llx\n",
3023 save
->dr6
, save
->dr7
);
3024 pr_err("rip: %016llx rflags: %016llx\n",
3025 save
->rip
, save
->rflags
);
3026 pr_err("rsp: %016llx rax: %016llx\n",
3027 save
->rsp
, save
->rax
);
3028 pr_err("star: %016llx lstar: %016llx\n",
3029 save
->star
, save
->lstar
);
3030 pr_err("cstar: %016llx sfmask: %016llx\n",
3031 save
->cstar
, save
->sfmask
);
3032 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3033 save
->kernel_gs_base
, save
->sysenter_cs
);
3034 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3035 save
->sysenter_esp
, save
->sysenter_eip
);
3036 pr_err("gpat: %016llx dbgctl: %016llx\n",
3037 save
->g_pat
, save
->dbgctl
);
3038 pr_err("br_from: %016llx br_to: %016llx\n",
3039 save
->br_from
, save
->br_to
);
3040 pr_err("excp_from: %016llx excp_to: %016llx\n",
3041 save
->last_excp_from
, save
->last_excp_to
);
3045 static void svm_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3047 struct vmcb_control_area
*control
= &to_svm(vcpu
)->vmcb
->control
;
3049 *info1
= control
->exit_info_1
;
3050 *info2
= control
->exit_info_2
;
3053 static int handle_exit(struct kvm_vcpu
*vcpu
)
3055 struct vcpu_svm
*svm
= to_svm(vcpu
);
3056 struct kvm_run
*kvm_run
= vcpu
->run
;
3057 u32 exit_code
= svm
->vmcb
->control
.exit_code
;
3059 trace_kvm_exit(exit_code
, vcpu
, KVM_ISA_SVM
);
3061 if (!is_cr_intercept(svm
, INTERCEPT_CR0_WRITE
))
3062 vcpu
->arch
.cr0
= svm
->vmcb
->save
.cr0
;
3064 vcpu
->arch
.cr3
= svm
->vmcb
->save
.cr3
;
3066 if (unlikely(svm
->nested
.exit_required
)) {
3067 nested_svm_vmexit(svm
);
3068 svm
->nested
.exit_required
= false;
3073 if (is_guest_mode(vcpu
)) {
3076 trace_kvm_nested_vmexit(svm
->vmcb
->save
.rip
, exit_code
,
3077 svm
->vmcb
->control
.exit_info_1
,
3078 svm
->vmcb
->control
.exit_info_2
,
3079 svm
->vmcb
->control
.exit_int_info
,
3080 svm
->vmcb
->control
.exit_int_info_err
);
3082 vmexit
= nested_svm_exit_special(svm
);
3084 if (vmexit
== NESTED_EXIT_CONTINUE
)
3085 vmexit
= nested_svm_exit_handled(svm
);
3087 if (vmexit
== NESTED_EXIT_DONE
)
3091 svm_complete_interrupts(svm
);
3093 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_ERR
) {
3094 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3095 kvm_run
->fail_entry
.hardware_entry_failure_reason
3096 = svm
->vmcb
->control
.exit_code
;
3097 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3102 if (is_external_interrupt(svm
->vmcb
->control
.exit_int_info
) &&
3103 exit_code
!= SVM_EXIT_EXCP_BASE
+ PF_VECTOR
&&
3104 exit_code
!= SVM_EXIT_NPF
&& exit_code
!= SVM_EXIT_TASK_SWITCH
&&
3105 exit_code
!= SVM_EXIT_INTR
&& exit_code
!= SVM_EXIT_NMI
)
3106 printk(KERN_ERR
"%s: unexpected exit_ini_info 0x%x "
3108 __func__
, svm
->vmcb
->control
.exit_int_info
,
3111 if (exit_code
>= ARRAY_SIZE(svm_exit_handlers
)
3112 || !svm_exit_handlers
[exit_code
]) {
3113 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3114 kvm_run
->hw
.hardware_exit_reason
= exit_code
;
3118 return svm_exit_handlers
[exit_code
](svm
);
3121 static void reload_tss(struct kvm_vcpu
*vcpu
)
3123 int cpu
= raw_smp_processor_id();
3125 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3126 sd
->tss_desc
->type
= 9; /* available 32/64-bit TSS */
3130 static void pre_svm_run(struct vcpu_svm
*svm
)
3132 int cpu
= raw_smp_processor_id();
3134 struct svm_cpu_data
*sd
= per_cpu(svm_data
, cpu
);
3136 svm
->vmcb
->control
.tlb_ctl
= TLB_CONTROL_DO_NOTHING
;
3137 /* FIXME: handle wraparound of asid_generation */
3138 if (svm
->asid_generation
!= sd
->asid_generation
)
3142 static void svm_inject_nmi(struct kvm_vcpu
*vcpu
)
3144 struct vcpu_svm
*svm
= to_svm(vcpu
);
3146 svm
->vmcb
->control
.event_inj
= SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_NMI
;
3147 vcpu
->arch
.hflags
|= HF_NMI_MASK
;
3148 set_intercept(svm
, INTERCEPT_IRET
);
3149 ++vcpu
->stat
.nmi_injections
;
3152 static inline void svm_inject_irq(struct vcpu_svm
*svm
, int irq
)
3154 struct vmcb_control_area
*control
;
3156 control
= &svm
->vmcb
->control
;
3157 control
->int_vector
= irq
;
3158 control
->int_ctl
&= ~V_INTR_PRIO_MASK
;
3159 control
->int_ctl
|= V_IRQ_MASK
|
3160 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT
);
3163 static void svm_set_irq(struct kvm_vcpu
*vcpu
)
3165 struct vcpu_svm
*svm
= to_svm(vcpu
);
3167 BUG_ON(!(gif_set(svm
)));
3169 trace_kvm_inj_virq(vcpu
->arch
.interrupt
.nr
);
3170 ++vcpu
->stat
.irq_injections
;
3172 svm
->vmcb
->control
.event_inj
= vcpu
->arch
.interrupt
.nr
|
3173 SVM_EVTINJ_VALID
| SVM_EVTINJ_TYPE_INTR
;
3176 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3178 struct vcpu_svm
*svm
= to_svm(vcpu
);
3180 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3187 set_cr_intercept(svm
, INTERCEPT_CR8_WRITE
);
3190 static int svm_nmi_allowed(struct kvm_vcpu
*vcpu
)
3192 struct vcpu_svm
*svm
= to_svm(vcpu
);
3193 struct vmcb
*vmcb
= svm
->vmcb
;
3195 ret
= !(vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
) &&
3196 !(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3197 ret
= ret
&& gif_set(svm
) && nested_svm_nmi(svm
);
3202 static bool svm_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3204 struct vcpu_svm
*svm
= to_svm(vcpu
);
3206 return !!(svm
->vcpu
.arch
.hflags
& HF_NMI_MASK
);
3209 static void svm_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3211 struct vcpu_svm
*svm
= to_svm(vcpu
);
3214 svm
->vcpu
.arch
.hflags
|= HF_NMI_MASK
;
3215 set_intercept(svm
, INTERCEPT_IRET
);
3217 svm
->vcpu
.arch
.hflags
&= ~HF_NMI_MASK
;
3218 clr_intercept(svm
, INTERCEPT_IRET
);
3222 static int svm_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3224 struct vcpu_svm
*svm
= to_svm(vcpu
);
3225 struct vmcb
*vmcb
= svm
->vmcb
;
3228 if (!gif_set(svm
) ||
3229 (vmcb
->control
.int_state
& SVM_INTERRUPT_SHADOW_MASK
))
3232 ret
= !!(vmcb
->save
.rflags
& X86_EFLAGS_IF
);
3234 if (is_guest_mode(vcpu
))
3235 return ret
&& !(svm
->vcpu
.arch
.hflags
& HF_VINTR_MASK
);
3240 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3242 struct vcpu_svm
*svm
= to_svm(vcpu
);
3245 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3246 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3247 * get that intercept, this function will be called again though and
3248 * we'll get the vintr intercept.
3250 if (gif_set(svm
) && nested_svm_intr(svm
)) {
3252 svm_inject_irq(svm
, 0x0);
3256 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3258 struct vcpu_svm
*svm
= to_svm(vcpu
);
3260 if ((svm
->vcpu
.arch
.hflags
& (HF_NMI_MASK
| HF_IRET_MASK
))
3262 return; /* IRET will cause a vm exit */
3265 * Something prevents NMI from been injected. Single step over possible
3266 * problem (IRET or exception injection or interrupt shadow)
3268 svm
->nmi_singlestep
= true;
3269 svm
->vmcb
->save
.rflags
|= (X86_EFLAGS_TF
| X86_EFLAGS_RF
);
3270 update_db_intercept(vcpu
);
3273 static int svm_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3278 static void svm_flush_tlb(struct kvm_vcpu
*vcpu
)
3280 force_new_asid(vcpu
);
3283 static void svm_prepare_guest_switch(struct kvm_vcpu
*vcpu
)
3287 static inline void sync_cr8_to_lapic(struct kvm_vcpu
*vcpu
)
3289 struct vcpu_svm
*svm
= to_svm(vcpu
);
3291 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3294 if (!is_cr_intercept(svm
, INTERCEPT_CR8_WRITE
)) {
3295 int cr8
= svm
->vmcb
->control
.int_ctl
& V_TPR_MASK
;
3296 kvm_set_cr8(vcpu
, cr8
);
3300 static inline void sync_lapic_to_cr8(struct kvm_vcpu
*vcpu
)
3302 struct vcpu_svm
*svm
= to_svm(vcpu
);
3305 if (is_guest_mode(vcpu
) && (vcpu
->arch
.hflags
& HF_VINTR_MASK
))
3308 cr8
= kvm_get_cr8(vcpu
);
3309 svm
->vmcb
->control
.int_ctl
&= ~V_TPR_MASK
;
3310 svm
->vmcb
->control
.int_ctl
|= cr8
& V_TPR_MASK
;
3313 static void svm_complete_interrupts(struct vcpu_svm
*svm
)
3317 u32 exitintinfo
= svm
->vmcb
->control
.exit_int_info
;
3318 unsigned int3_injected
= svm
->int3_injected
;
3320 svm
->int3_injected
= 0;
3322 if (svm
->vcpu
.arch
.hflags
& HF_IRET_MASK
) {
3323 svm
->vcpu
.arch
.hflags
&= ~(HF_NMI_MASK
| HF_IRET_MASK
);
3324 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3327 svm
->vcpu
.arch
.nmi_injected
= false;
3328 kvm_clear_exception_queue(&svm
->vcpu
);
3329 kvm_clear_interrupt_queue(&svm
->vcpu
);
3331 if (!(exitintinfo
& SVM_EXITINTINFO_VALID
))
3334 kvm_make_request(KVM_REQ_EVENT
, &svm
->vcpu
);
3336 vector
= exitintinfo
& SVM_EXITINTINFO_VEC_MASK
;
3337 type
= exitintinfo
& SVM_EXITINTINFO_TYPE_MASK
;
3340 case SVM_EXITINTINFO_TYPE_NMI
:
3341 svm
->vcpu
.arch
.nmi_injected
= true;
3343 case SVM_EXITINTINFO_TYPE_EXEPT
:
3345 * In case of software exceptions, do not reinject the vector,
3346 * but re-execute the instruction instead. Rewind RIP first
3347 * if we emulated INT3 before.
3349 if (kvm_exception_is_soft(vector
)) {
3350 if (vector
== BP_VECTOR
&& int3_injected
&&
3351 kvm_is_linear_rip(&svm
->vcpu
, svm
->int3_rip
))
3352 kvm_rip_write(&svm
->vcpu
,
3353 kvm_rip_read(&svm
->vcpu
) -
3357 if (exitintinfo
& SVM_EXITINTINFO_VALID_ERR
) {
3358 u32 err
= svm
->vmcb
->control
.exit_int_info_err
;
3359 kvm_requeue_exception_e(&svm
->vcpu
, vector
, err
);
3362 kvm_requeue_exception(&svm
->vcpu
, vector
);
3364 case SVM_EXITINTINFO_TYPE_INTR
:
3365 kvm_queue_interrupt(&svm
->vcpu
, vector
, false);
3372 static void svm_cancel_injection(struct kvm_vcpu
*vcpu
)
3374 struct vcpu_svm
*svm
= to_svm(vcpu
);
3375 struct vmcb_control_area
*control
= &svm
->vmcb
->control
;
3377 control
->exit_int_info
= control
->event_inj
;
3378 control
->exit_int_info_err
= control
->event_inj_err
;
3379 control
->event_inj
= 0;
3380 svm_complete_interrupts(svm
);
3383 #ifdef CONFIG_X86_64
3389 static void svm_vcpu_run(struct kvm_vcpu
*vcpu
)
3391 struct vcpu_svm
*svm
= to_svm(vcpu
);
3393 svm
->vmcb
->save
.rax
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
3394 svm
->vmcb
->save
.rsp
= vcpu
->arch
.regs
[VCPU_REGS_RSP
];
3395 svm
->vmcb
->save
.rip
= vcpu
->arch
.regs
[VCPU_REGS_RIP
];
3398 * A vmexit emulation is required before the vcpu can be executed
3401 if (unlikely(svm
->nested
.exit_required
))
3406 sync_lapic_to_cr8(vcpu
);
3408 svm
->vmcb
->save
.cr2
= vcpu
->arch
.cr2
;
3415 "push %%"R
"bp; \n\t"
3416 "mov %c[rbx](%[svm]), %%"R
"bx \n\t"
3417 "mov %c[rcx](%[svm]), %%"R
"cx \n\t"
3418 "mov %c[rdx](%[svm]), %%"R
"dx \n\t"
3419 "mov %c[rsi](%[svm]), %%"R
"si \n\t"
3420 "mov %c[rdi](%[svm]), %%"R
"di \n\t"
3421 "mov %c[rbp](%[svm]), %%"R
"bp \n\t"
3422 #ifdef CONFIG_X86_64
3423 "mov %c[r8](%[svm]), %%r8 \n\t"
3424 "mov %c[r9](%[svm]), %%r9 \n\t"
3425 "mov %c[r10](%[svm]), %%r10 \n\t"
3426 "mov %c[r11](%[svm]), %%r11 \n\t"
3427 "mov %c[r12](%[svm]), %%r12 \n\t"
3428 "mov %c[r13](%[svm]), %%r13 \n\t"
3429 "mov %c[r14](%[svm]), %%r14 \n\t"
3430 "mov %c[r15](%[svm]), %%r15 \n\t"
3433 /* Enter guest mode */
3435 "mov %c[vmcb](%[svm]), %%"R
"ax \n\t"
3436 __ex(SVM_VMLOAD
) "\n\t"
3437 __ex(SVM_VMRUN
) "\n\t"
3438 __ex(SVM_VMSAVE
) "\n\t"
3441 /* Save guest registers, load host registers */
3442 "mov %%"R
"bx, %c[rbx](%[svm]) \n\t"
3443 "mov %%"R
"cx, %c[rcx](%[svm]) \n\t"
3444 "mov %%"R
"dx, %c[rdx](%[svm]) \n\t"
3445 "mov %%"R
"si, %c[rsi](%[svm]) \n\t"
3446 "mov %%"R
"di, %c[rdi](%[svm]) \n\t"
3447 "mov %%"R
"bp, %c[rbp](%[svm]) \n\t"
3448 #ifdef CONFIG_X86_64
3449 "mov %%r8, %c[r8](%[svm]) \n\t"
3450 "mov %%r9, %c[r9](%[svm]) \n\t"
3451 "mov %%r10, %c[r10](%[svm]) \n\t"
3452 "mov %%r11, %c[r11](%[svm]) \n\t"
3453 "mov %%r12, %c[r12](%[svm]) \n\t"
3454 "mov %%r13, %c[r13](%[svm]) \n\t"
3455 "mov %%r14, %c[r14](%[svm]) \n\t"
3456 "mov %%r15, %c[r15](%[svm]) \n\t"
3461 [vmcb
]"i"(offsetof(struct vcpu_svm
, vmcb_pa
)),
3462 [rbx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3463 [rcx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3464 [rdx
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3465 [rsi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3466 [rdi
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3467 [rbp
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_RBP
]))
3468 #ifdef CONFIG_X86_64
3469 , [r8
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3470 [r9
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3471 [r10
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3472 [r11
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3473 [r12
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3474 [r13
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3475 [r14
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3476 [r15
]"i"(offsetof(struct vcpu_svm
, vcpu
.arch
.regs
[VCPU_REGS_R15
]))
3479 , R
"bx", R
"cx", R
"dx", R
"si", R
"di"
3480 #ifdef CONFIG_X86_64
3481 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3485 #ifdef CONFIG_X86_64
3486 wrmsrl(MSR_GS_BASE
, svm
->host
.gs_base
);
3488 loadsegment(fs
, svm
->host
.fs
);
3493 local_irq_disable();
3497 vcpu
->arch
.cr2
= svm
->vmcb
->save
.cr2
;
3498 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = svm
->vmcb
->save
.rax
;
3499 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = svm
->vmcb
->save
.rsp
;
3500 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = svm
->vmcb
->save
.rip
;
3502 sync_cr8_to_lapic(vcpu
);
3506 /* if exit due to PF check for async PF */
3507 if (svm
->vmcb
->control
.exit_code
== SVM_EXIT_EXCP_BASE
+ PF_VECTOR
)
3508 svm
->apf_reason
= kvm_read_and_reset_pf_reason();
3511 vcpu
->arch
.regs_avail
&= ~(1 << VCPU_EXREG_PDPTR
);
3512 vcpu
->arch
.regs_dirty
&= ~(1 << VCPU_EXREG_PDPTR
);
3516 * We need to handle MC intercepts here before the vcpu has a chance to
3517 * change the physical cpu
3519 if (unlikely(svm
->vmcb
->control
.exit_code
==
3520 SVM_EXIT_EXCP_BASE
+ MC_VECTOR
))
3521 svm_handle_mce(svm
);
3523 mark_all_clean(svm
->vmcb
);
3528 static void svm_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3530 struct vcpu_svm
*svm
= to_svm(vcpu
);
3532 svm
->vmcb
->save
.cr3
= root
;
3533 force_new_asid(vcpu
);
3536 static void set_tdp_cr3(struct kvm_vcpu
*vcpu
, unsigned long root
)
3538 struct vcpu_svm
*svm
= to_svm(vcpu
);
3540 svm
->vmcb
->control
.nested_cr3
= root
;
3542 /* Also sync guest cr3 here in case we live migrate */
3543 svm
->vmcb
->save
.cr3
= vcpu
->arch
.cr3
;
3545 force_new_asid(vcpu
);
3548 static int is_disabled(void)
3552 rdmsrl(MSR_VM_CR
, vm_cr
);
3553 if (vm_cr
& (1 << SVM_VM_CR_SVM_DISABLE
))
3560 svm_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3563 * Patch in the VMMCALL instruction:
3565 hypercall
[0] = 0x0f;
3566 hypercall
[1] = 0x01;
3567 hypercall
[2] = 0xd9;
3570 static void svm_check_processor_compat(void *rtn
)
3575 static bool svm_cpu_has_accelerated_tpr(void)
3580 static u64
svm_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3585 static void svm_cpuid_update(struct kvm_vcpu
*vcpu
)
3589 static void svm_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
3593 /* Mask out xsave bit as long as it is not supported by SVM */
3594 entry
->ecx
&= ~(bit(X86_FEATURE_XSAVE
));
3598 entry
->ecx
|= (1 << 2); /* Set SVM bit */
3601 entry
->eax
= 1; /* SVM revision 1 */
3602 entry
->ebx
= 8; /* Lets support 8 ASIDs in case we add proper
3603 ASID emulation to nested SVM */
3604 entry
->ecx
= 0; /* Reserved */
3605 entry
->edx
= 0; /* Per default do not support any
3606 additional features */
3608 /* Support next_rip if host supports it */
3609 if (boot_cpu_has(X86_FEATURE_NRIPS
))
3610 entry
->edx
|= SVM_FEATURE_NRIP
;
3612 /* Support NPT for the guest if enabled */
3614 entry
->edx
|= SVM_FEATURE_NPT
;
3620 static const struct trace_print_flags svm_exit_reasons_str
[] = {
3621 { SVM_EXIT_READ_CR0
, "read_cr0" },
3622 { SVM_EXIT_READ_CR3
, "read_cr3" },
3623 { SVM_EXIT_READ_CR4
, "read_cr4" },
3624 { SVM_EXIT_READ_CR8
, "read_cr8" },
3625 { SVM_EXIT_WRITE_CR0
, "write_cr0" },
3626 { SVM_EXIT_WRITE_CR3
, "write_cr3" },
3627 { SVM_EXIT_WRITE_CR4
, "write_cr4" },
3628 { SVM_EXIT_WRITE_CR8
, "write_cr8" },
3629 { SVM_EXIT_READ_DR0
, "read_dr0" },
3630 { SVM_EXIT_READ_DR1
, "read_dr1" },
3631 { SVM_EXIT_READ_DR2
, "read_dr2" },
3632 { SVM_EXIT_READ_DR3
, "read_dr3" },
3633 { SVM_EXIT_WRITE_DR0
, "write_dr0" },
3634 { SVM_EXIT_WRITE_DR1
, "write_dr1" },
3635 { SVM_EXIT_WRITE_DR2
, "write_dr2" },
3636 { SVM_EXIT_WRITE_DR3
, "write_dr3" },
3637 { SVM_EXIT_WRITE_DR5
, "write_dr5" },
3638 { SVM_EXIT_WRITE_DR7
, "write_dr7" },
3639 { SVM_EXIT_EXCP_BASE
+ DB_VECTOR
, "DB excp" },
3640 { SVM_EXIT_EXCP_BASE
+ BP_VECTOR
, "BP excp" },
3641 { SVM_EXIT_EXCP_BASE
+ UD_VECTOR
, "UD excp" },
3642 { SVM_EXIT_EXCP_BASE
+ PF_VECTOR
, "PF excp" },
3643 { SVM_EXIT_EXCP_BASE
+ NM_VECTOR
, "NM excp" },
3644 { SVM_EXIT_EXCP_BASE
+ MC_VECTOR
, "MC excp" },
3645 { SVM_EXIT_INTR
, "interrupt" },
3646 { SVM_EXIT_NMI
, "nmi" },
3647 { SVM_EXIT_SMI
, "smi" },
3648 { SVM_EXIT_INIT
, "init" },
3649 { SVM_EXIT_VINTR
, "vintr" },
3650 { SVM_EXIT_CPUID
, "cpuid" },
3651 { SVM_EXIT_INVD
, "invd" },
3652 { SVM_EXIT_HLT
, "hlt" },
3653 { SVM_EXIT_INVLPG
, "invlpg" },
3654 { SVM_EXIT_INVLPGA
, "invlpga" },
3655 { SVM_EXIT_IOIO
, "io" },
3656 { SVM_EXIT_MSR
, "msr" },
3657 { SVM_EXIT_TASK_SWITCH
, "task_switch" },
3658 { SVM_EXIT_SHUTDOWN
, "shutdown" },
3659 { SVM_EXIT_VMRUN
, "vmrun" },
3660 { SVM_EXIT_VMMCALL
, "hypercall" },
3661 { SVM_EXIT_VMLOAD
, "vmload" },
3662 { SVM_EXIT_VMSAVE
, "vmsave" },
3663 { SVM_EXIT_STGI
, "stgi" },
3664 { SVM_EXIT_CLGI
, "clgi" },
3665 { SVM_EXIT_SKINIT
, "skinit" },
3666 { SVM_EXIT_WBINVD
, "wbinvd" },
3667 { SVM_EXIT_MONITOR
, "monitor" },
3668 { SVM_EXIT_MWAIT
, "mwait" },
3669 { SVM_EXIT_NPF
, "npf" },
3673 static int svm_get_lpage_level(void)
3675 return PT_PDPE_LEVEL
;
3678 static bool svm_rdtscp_supported(void)
3683 static bool svm_has_wbinvd_exit(void)
3688 static void svm_fpu_deactivate(struct kvm_vcpu
*vcpu
)
3690 struct vcpu_svm
*svm
= to_svm(vcpu
);
3692 set_exception_intercept(svm
, NM_VECTOR
);
3693 update_cr0_intercept(svm
);
3696 static struct kvm_x86_ops svm_x86_ops
= {
3697 .cpu_has_kvm_support
= has_svm
,
3698 .disabled_by_bios
= is_disabled
,
3699 .hardware_setup
= svm_hardware_setup
,
3700 .hardware_unsetup
= svm_hardware_unsetup
,
3701 .check_processor_compatibility
= svm_check_processor_compat
,
3702 .hardware_enable
= svm_hardware_enable
,
3703 .hardware_disable
= svm_hardware_disable
,
3704 .cpu_has_accelerated_tpr
= svm_cpu_has_accelerated_tpr
,
3706 .vcpu_create
= svm_create_vcpu
,
3707 .vcpu_free
= svm_free_vcpu
,
3708 .vcpu_reset
= svm_vcpu_reset
,
3710 .prepare_guest_switch
= svm_prepare_guest_switch
,
3711 .vcpu_load
= svm_vcpu_load
,
3712 .vcpu_put
= svm_vcpu_put
,
3714 .set_guest_debug
= svm_guest_debug
,
3715 .get_msr
= svm_get_msr
,
3716 .set_msr
= svm_set_msr
,
3717 .get_segment_base
= svm_get_segment_base
,
3718 .get_segment
= svm_get_segment
,
3719 .set_segment
= svm_set_segment
,
3720 .get_cpl
= svm_get_cpl
,
3721 .get_cs_db_l_bits
= kvm_get_cs_db_l_bits
,
3722 .decache_cr0_guest_bits
= svm_decache_cr0_guest_bits
,
3723 .decache_cr4_guest_bits
= svm_decache_cr4_guest_bits
,
3724 .set_cr0
= svm_set_cr0
,
3725 .set_cr3
= svm_set_cr3
,
3726 .set_cr4
= svm_set_cr4
,
3727 .set_efer
= svm_set_efer
,
3728 .get_idt
= svm_get_idt
,
3729 .set_idt
= svm_set_idt
,
3730 .get_gdt
= svm_get_gdt
,
3731 .set_gdt
= svm_set_gdt
,
3732 .set_dr7
= svm_set_dr7
,
3733 .cache_reg
= svm_cache_reg
,
3734 .get_rflags
= svm_get_rflags
,
3735 .set_rflags
= svm_set_rflags
,
3736 .fpu_activate
= svm_fpu_activate
,
3737 .fpu_deactivate
= svm_fpu_deactivate
,
3739 .tlb_flush
= svm_flush_tlb
,
3741 .run
= svm_vcpu_run
,
3742 .handle_exit
= handle_exit
,
3743 .skip_emulated_instruction
= skip_emulated_instruction
,
3744 .set_interrupt_shadow
= svm_set_interrupt_shadow
,
3745 .get_interrupt_shadow
= svm_get_interrupt_shadow
,
3746 .patch_hypercall
= svm_patch_hypercall
,
3747 .set_irq
= svm_set_irq
,
3748 .set_nmi
= svm_inject_nmi
,
3749 .queue_exception
= svm_queue_exception
,
3750 .cancel_injection
= svm_cancel_injection
,
3751 .interrupt_allowed
= svm_interrupt_allowed
,
3752 .nmi_allowed
= svm_nmi_allowed
,
3753 .get_nmi_mask
= svm_get_nmi_mask
,
3754 .set_nmi_mask
= svm_set_nmi_mask
,
3755 .enable_nmi_window
= enable_nmi_window
,
3756 .enable_irq_window
= enable_irq_window
,
3757 .update_cr8_intercept
= update_cr8_intercept
,
3759 .set_tss_addr
= svm_set_tss_addr
,
3760 .get_tdp_level
= get_npt_level
,
3761 .get_mt_mask
= svm_get_mt_mask
,
3763 .get_exit_info
= svm_get_exit_info
,
3764 .exit_reasons_str
= svm_exit_reasons_str
,
3766 .get_lpage_level
= svm_get_lpage_level
,
3768 .cpuid_update
= svm_cpuid_update
,
3770 .rdtscp_supported
= svm_rdtscp_supported
,
3772 .set_supported_cpuid
= svm_set_supported_cpuid
,
3774 .has_wbinvd_exit
= svm_has_wbinvd_exit
,
3776 .write_tsc_offset
= svm_write_tsc_offset
,
3777 .adjust_tsc_offset
= svm_adjust_tsc_offset
,
3779 .set_tdp_cr3
= set_tdp_cr3
,
3782 static int __init
svm_init(void)
3784 return kvm_init(&svm_x86_ops
, sizeof(struct vcpu_svm
),
3785 __alignof__(struct vcpu_svm
), THIS_MODULE
);
3788 static void __exit
svm_exit(void)
3793 module_init(svm_init
)
3794 module_exit(svm_exit
)