1 // SPDX-License-Identifier: GPL-2.0-only
3 * KVM PMU support for Intel CPUs
5 * Copyright 2011 Red Hat, Inc. and/or its affiliates.
8 * Avi Kivity <avi@redhat.com>
9 * Gleb Natapov <gleb@redhat.com>
11 #include <linux/types.h>
12 #include <linux/kvm_host.h>
13 #include <linux/perf_event.h>
14 #include <asm/perf_event.h>
20 static struct kvm_event_hw_type_mapping intel_arch_events
[] = {
21 /* Index must match CPUID 0x0A.EBX bit vector */
22 [0] = { 0x3c, 0x00, PERF_COUNT_HW_CPU_CYCLES
},
23 [1] = { 0xc0, 0x00, PERF_COUNT_HW_INSTRUCTIONS
},
24 [2] = { 0x3c, 0x01, PERF_COUNT_HW_BUS_CYCLES
},
25 [3] = { 0x2e, 0x4f, PERF_COUNT_HW_CACHE_REFERENCES
},
26 [4] = { 0x2e, 0x41, PERF_COUNT_HW_CACHE_MISSES
},
27 [5] = { 0xc4, 0x00, PERF_COUNT_HW_BRANCH_INSTRUCTIONS
},
28 [6] = { 0xc5, 0x00, PERF_COUNT_HW_BRANCH_MISSES
},
29 [7] = { 0x00, 0x30, PERF_COUNT_HW_REF_CPU_CYCLES
},
32 /* mapping between fixed pmc index and intel_arch_events array */
33 static int fixed_pmc_events
[] = {1, 0, 7};
35 static void reprogram_fixed_counters(struct kvm_pmu
*pmu
, u64 data
)
39 for (i
= 0; i
< pmu
->nr_arch_fixed_counters
; i
++) {
40 u8 new_ctrl
= fixed_ctrl_field(data
, i
);
41 u8 old_ctrl
= fixed_ctrl_field(pmu
->fixed_ctr_ctrl
, i
);
44 pmc
= get_fixed_pmc(pmu
, MSR_CORE_PERF_FIXED_CTR0
+ i
);
46 if (old_ctrl
== new_ctrl
)
49 reprogram_fixed_counter(pmc
, new_ctrl
, i
);
52 pmu
->fixed_ctr_ctrl
= data
;
55 /* function is called when global control register has been updated. */
56 static void global_ctrl_changed(struct kvm_pmu
*pmu
, u64 data
)
59 u64 diff
= pmu
->global_ctrl
^ data
;
61 pmu
->global_ctrl
= data
;
63 for_each_set_bit(bit
, (unsigned long *)&diff
, X86_PMC_IDX_MAX
)
64 reprogram_counter(pmu
, bit
);
67 static unsigned intel_find_arch_event(struct kvm_pmu
*pmu
,
73 for (i
= 0; i
< ARRAY_SIZE(intel_arch_events
); i
++)
74 if (intel_arch_events
[i
].eventsel
== event_select
75 && intel_arch_events
[i
].unit_mask
== unit_mask
76 && (pmu
->available_event_types
& (1 << i
)))
79 if (i
== ARRAY_SIZE(intel_arch_events
))
80 return PERF_COUNT_HW_MAX
;
82 return intel_arch_events
[i
].event_type
;
85 static unsigned intel_find_fixed_event(int idx
)
87 if (idx
>= ARRAY_SIZE(fixed_pmc_events
))
88 return PERF_COUNT_HW_MAX
;
90 return intel_arch_events
[fixed_pmc_events
[idx
]].event_type
;
93 /* check if a PMC is enabled by comparing it with globl_ctrl bits. */
94 static bool intel_pmc_is_enabled(struct kvm_pmc
*pmc
)
96 struct kvm_pmu
*pmu
= pmc_to_pmu(pmc
);
98 return test_bit(pmc
->idx
, (unsigned long *)&pmu
->global_ctrl
);
101 static struct kvm_pmc
*intel_pmc_idx_to_pmc(struct kvm_pmu
*pmu
, int pmc_idx
)
103 if (pmc_idx
< INTEL_PMC_IDX_FIXED
)
104 return get_gp_pmc(pmu
, MSR_P6_EVNTSEL0
+ pmc_idx
,
107 u32 idx
= pmc_idx
- INTEL_PMC_IDX_FIXED
;
109 return get_fixed_pmc(pmu
, idx
+ MSR_CORE_PERF_FIXED_CTR0
);
113 /* returns 0 if idx's corresponding MSR exists; otherwise returns 1. */
114 static int intel_is_valid_msr_idx(struct kvm_vcpu
*vcpu
, unsigned idx
)
116 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
117 bool fixed
= idx
& (1u << 30);
121 return (!fixed
&& idx
>= pmu
->nr_arch_gp_counters
) ||
122 (fixed
&& idx
>= pmu
->nr_arch_fixed_counters
);
125 static struct kvm_pmc
*intel_msr_idx_to_pmc(struct kvm_vcpu
*vcpu
,
126 unsigned idx
, u64
*mask
)
128 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
129 bool fixed
= idx
& (1u << 30);
130 struct kvm_pmc
*counters
;
133 if (!fixed
&& idx
>= pmu
->nr_arch_gp_counters
)
135 if (fixed
&& idx
>= pmu
->nr_arch_fixed_counters
)
137 counters
= fixed
? pmu
->fixed_counters
: pmu
->gp_counters
;
138 *mask
&= pmu
->counter_bitmask
[fixed
? KVM_PMC_FIXED
: KVM_PMC_GP
];
140 return &counters
[idx
];
143 static bool intel_is_valid_msr(struct kvm_vcpu
*vcpu
, u32 msr
)
145 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
149 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
150 case MSR_CORE_PERF_GLOBAL_STATUS
:
151 case MSR_CORE_PERF_GLOBAL_CTRL
:
152 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
153 ret
= pmu
->version
> 1;
156 ret
= get_gp_pmc(pmu
, msr
, MSR_IA32_PERFCTR0
) ||
157 get_gp_pmc(pmu
, msr
, MSR_P6_EVNTSEL0
) ||
158 get_fixed_pmc(pmu
, msr
);
165 static int intel_pmu_get_msr(struct kvm_vcpu
*vcpu
, u32 msr
, u64
*data
)
167 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
171 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
172 *data
= pmu
->fixed_ctr_ctrl
;
174 case MSR_CORE_PERF_GLOBAL_STATUS
:
175 *data
= pmu
->global_status
;
177 case MSR_CORE_PERF_GLOBAL_CTRL
:
178 *data
= pmu
->global_ctrl
;
180 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
181 *data
= pmu
->global_ovf_ctrl
;
184 if ((pmc
= get_gp_pmc(pmu
, msr
, MSR_IA32_PERFCTR0
))) {
185 u64 val
= pmc_read_counter(pmc
);
186 *data
= val
& pmu
->counter_bitmask
[KVM_PMC_GP
];
188 } else if ((pmc
= get_fixed_pmc(pmu
, msr
))) {
189 u64 val
= pmc_read_counter(pmc
);
190 *data
= val
& pmu
->counter_bitmask
[KVM_PMC_FIXED
];
192 } else if ((pmc
= get_gp_pmc(pmu
, msr
, MSR_P6_EVNTSEL0
))) {
193 *data
= pmc
->eventsel
;
201 static int intel_pmu_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
203 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
205 u32 msr
= msr_info
->index
;
206 u64 data
= msr_info
->data
;
209 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
210 if (pmu
->fixed_ctr_ctrl
== data
)
212 if (!(data
& 0xfffffffffffff444ull
)) {
213 reprogram_fixed_counters(pmu
, data
);
217 case MSR_CORE_PERF_GLOBAL_STATUS
:
218 if (msr_info
->host_initiated
) {
219 pmu
->global_status
= data
;
223 case MSR_CORE_PERF_GLOBAL_CTRL
:
224 if (pmu
->global_ctrl
== data
)
226 if (!(data
& pmu
->global_ctrl_mask
)) {
227 global_ctrl_changed(pmu
, data
);
231 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
232 if (!(data
& pmu
->global_ovf_ctrl_mask
)) {
233 if (!msr_info
->host_initiated
)
234 pmu
->global_status
&= ~data
;
235 pmu
->global_ovf_ctrl
= data
;
240 if ((pmc
= get_gp_pmc(pmu
, msr
, MSR_IA32_PERFCTR0
))) {
241 if (msr_info
->host_initiated
)
244 pmc
->counter
= (s32
)data
;
246 } else if ((pmc
= get_fixed_pmc(pmu
, msr
))) {
249 } else if ((pmc
= get_gp_pmc(pmu
, msr
, MSR_P6_EVNTSEL0
))) {
250 if (data
== pmc
->eventsel
)
252 if (!(data
& pmu
->reserved_bits
)) {
253 reprogram_gp_counter(pmc
, data
);
262 static void intel_pmu_refresh(struct kvm_vcpu
*vcpu
)
264 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
265 struct kvm_cpuid_entry2
*entry
;
266 union cpuid10_eax eax
;
267 union cpuid10_edx edx
;
269 pmu
->nr_arch_gp_counters
= 0;
270 pmu
->nr_arch_fixed_counters
= 0;
271 pmu
->counter_bitmask
[KVM_PMC_GP
] = 0;
272 pmu
->counter_bitmask
[KVM_PMC_FIXED
] = 0;
274 pmu
->reserved_bits
= 0xffffffff00200000ull
;
276 entry
= kvm_find_cpuid_entry(vcpu
, 0xa, 0);
279 eax
.full
= entry
->eax
;
280 edx
.full
= entry
->edx
;
282 pmu
->version
= eax
.split
.version_id
;
286 pmu
->nr_arch_gp_counters
= min_t(int, eax
.split
.num_counters
,
287 INTEL_PMC_MAX_GENERIC
);
288 pmu
->counter_bitmask
[KVM_PMC_GP
] = ((u64
)1 << eax
.split
.bit_width
) - 1;
289 pmu
->available_event_types
= ~entry
->ebx
&
290 ((1ull << eax
.split
.mask_length
) - 1);
292 if (pmu
->version
== 1) {
293 pmu
->nr_arch_fixed_counters
= 0;
295 pmu
->nr_arch_fixed_counters
=
296 min_t(int, edx
.split
.num_counters_fixed
,
297 INTEL_PMC_MAX_FIXED
);
298 pmu
->counter_bitmask
[KVM_PMC_FIXED
] =
299 ((u64
)1 << edx
.split
.bit_width_fixed
) - 1;
302 pmu
->global_ctrl
= ((1ull << pmu
->nr_arch_gp_counters
) - 1) |
303 (((1ull << pmu
->nr_arch_fixed_counters
) - 1) << INTEL_PMC_IDX_FIXED
);
304 pmu
->global_ctrl_mask
= ~pmu
->global_ctrl
;
305 pmu
->global_ovf_ctrl_mask
= pmu
->global_ctrl_mask
306 & ~(MSR_CORE_PERF_GLOBAL_OVF_CTRL_OVF_BUF
|
307 MSR_CORE_PERF_GLOBAL_OVF_CTRL_COND_CHGD
);
308 if (kvm_x86_ops
->pt_supported())
309 pmu
->global_ovf_ctrl_mask
&=
310 ~MSR_CORE_PERF_GLOBAL_OVF_CTRL_TRACE_TOPA_PMI
;
312 entry
= kvm_find_cpuid_entry(vcpu
, 7, 0);
314 (boot_cpu_has(X86_FEATURE_HLE
) || boot_cpu_has(X86_FEATURE_RTM
)) &&
315 (entry
->ebx
& (X86_FEATURE_HLE
|X86_FEATURE_RTM
)))
316 pmu
->reserved_bits
^= HSW_IN_TX
|HSW_IN_TX_CHECKPOINTED
;
319 static void intel_pmu_init(struct kvm_vcpu
*vcpu
)
322 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
324 for (i
= 0; i
< INTEL_PMC_MAX_GENERIC
; i
++) {
325 pmu
->gp_counters
[i
].type
= KVM_PMC_GP
;
326 pmu
->gp_counters
[i
].vcpu
= vcpu
;
327 pmu
->gp_counters
[i
].idx
= i
;
330 for (i
= 0; i
< INTEL_PMC_MAX_FIXED
; i
++) {
331 pmu
->fixed_counters
[i
].type
= KVM_PMC_FIXED
;
332 pmu
->fixed_counters
[i
].vcpu
= vcpu
;
333 pmu
->fixed_counters
[i
].idx
= i
+ INTEL_PMC_IDX_FIXED
;
337 static void intel_pmu_reset(struct kvm_vcpu
*vcpu
)
339 struct kvm_pmu
*pmu
= vcpu_to_pmu(vcpu
);
342 for (i
= 0; i
< INTEL_PMC_MAX_GENERIC
; i
++) {
343 struct kvm_pmc
*pmc
= &pmu
->gp_counters
[i
];
345 pmc_stop_counter(pmc
);
346 pmc
->counter
= pmc
->eventsel
= 0;
349 for (i
= 0; i
< INTEL_PMC_MAX_FIXED
; i
++)
350 pmc_stop_counter(&pmu
->fixed_counters
[i
]);
352 pmu
->fixed_ctr_ctrl
= pmu
->global_ctrl
= pmu
->global_status
=
353 pmu
->global_ovf_ctrl
= 0;
356 struct kvm_pmu_ops intel_pmu_ops
= {
357 .find_arch_event
= intel_find_arch_event
,
358 .find_fixed_event
= intel_find_fixed_event
,
359 .pmc_is_enabled
= intel_pmc_is_enabled
,
360 .pmc_idx_to_pmc
= intel_pmc_idx_to_pmc
,
361 .msr_idx_to_pmc
= intel_msr_idx_to_pmc
,
362 .is_valid_msr_idx
= intel_is_valid_msr_idx
,
363 .is_valid_msr
= intel_is_valid_msr
,
364 .get_msr
= intel_pmu_get_msr
,
365 .set_msr
= intel_pmu_set_msr
,
366 .refresh
= intel_pmu_refresh
,
367 .init
= intel_pmu_init
,
368 .reset
= intel_pmu_reset
,