1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
8 * Copyright (C) 2006 Qumranet, Inc.
9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
16 #include <linux/highmem.h>
17 #include <linux/hrtimer.h>
18 #include <linux/kernel.h>
19 #include <linux/kvm_host.h>
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/mod_devicetable.h>
24 #include <linux/objtool.h>
25 #include <linux/sched.h>
26 #include <linux/sched/smt.h>
27 #include <linux/slab.h>
28 #include <linux/tboot.h>
29 #include <linux/trace_events.h>
30 #include <linux/entry-kvm.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/debugreg.h>
38 #include <asm/fpu/api.h>
39 #include <asm/idtentry.h>
41 #include <asm/irq_remapping.h>
42 #include <asm/kexec.h>
43 #include <asm/perf_event.h>
44 #include <asm/mmu_context.h>
45 #include <asm/mshyperv.h>
46 #include <asm/mwait.h>
47 #include <asm/spec-ctrl.h>
48 #include <asm/virtext.h>
51 #include "capabilities.h"
55 #include "kvm_onhyperv.h"
57 #include "kvm_cache_regs.h"
69 MODULE_AUTHOR("Qumranet");
70 MODULE_LICENSE("GPL");
73 static const struct x86_cpu_id vmx_cpu_id
[] = {
74 X86_MATCH_FEATURE(X86_FEATURE_VMX
, NULL
),
77 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
80 bool __read_mostly enable_vpid
= 1;
81 module_param_named(vpid
, enable_vpid
, bool, 0444);
83 static bool __read_mostly enable_vnmi
= 1;
84 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
86 bool __read_mostly flexpriority_enabled
= 1;
87 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
89 bool __read_mostly enable_ept
= 1;
90 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
92 bool __read_mostly enable_unrestricted_guest
= 1;
93 module_param_named(unrestricted_guest
,
94 enable_unrestricted_guest
, bool, S_IRUGO
);
96 bool __read_mostly enable_ept_ad_bits
= 1;
97 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
99 static bool __read_mostly emulate_invalid_guest_state
= true;
100 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
102 static bool __read_mostly fasteoi
= 1;
103 module_param(fasteoi
, bool, S_IRUGO
);
105 module_param(enable_apicv
, bool, S_IRUGO
);
108 * If nested=1, nested virtualization is supported, i.e., guests may use
109 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
110 * use VMX instructions.
112 static bool __read_mostly nested
= 1;
113 module_param(nested
, bool, S_IRUGO
);
115 bool __read_mostly enable_pml
= 1;
116 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
118 static bool __read_mostly dump_invalid_vmcs
= 0;
119 module_param(dump_invalid_vmcs
, bool, 0644);
121 #define MSR_BITMAP_MODE_X2APIC 1
122 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
126 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
127 static int __read_mostly cpu_preemption_timer_multi
;
128 static bool __read_mostly enable_preemption_timer
= 1;
130 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
133 extern bool __read_mostly allow_smaller_maxphyaddr
;
134 module_param(allow_smaller_maxphyaddr
, bool, S_IRUGO
);
136 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
137 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
138 #define KVM_VM_CR0_ALWAYS_ON \
139 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
141 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
142 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
143 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
145 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
147 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \
148 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \
149 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \
150 RTIT_STATUS_BYTECNT))
153 * List of MSRs that can be directly passed to the guest.
154 * In addition to these x2apic and PT MSRs are handled specially.
156 static u32 vmx_possible_passthrough_msrs
[MAX_POSSIBLE_PASSTHROUGH_MSRS
] = {
165 MSR_IA32_SYSENTER_CS
,
166 MSR_IA32_SYSENTER_ESP
,
167 MSR_IA32_SYSENTER_EIP
,
169 MSR_CORE_C3_RESIDENCY
,
170 MSR_CORE_C6_RESIDENCY
,
171 MSR_CORE_C7_RESIDENCY
,
175 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
176 * ple_gap: upper bound on the amount of time between two successive
177 * executions of PAUSE in a loop. Also indicate if ple enabled.
178 * According to test, this time is usually smaller than 128 cycles.
179 * ple_window: upper bound on the amount of time a guest is allowed to execute
180 * in a PAUSE loop. Tests indicate that most spinlocks are held for
181 * less than 2^12 cycles
182 * Time is measured based on a counter that runs at the same rate as the TSC,
183 * refer SDM volume 3b section 21.6.13 & 22.1.3.
185 static unsigned int ple_gap
= KVM_DEFAULT_PLE_GAP
;
186 module_param(ple_gap
, uint
, 0444);
188 static unsigned int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
189 module_param(ple_window
, uint
, 0444);
191 /* Default doubles per-vcpu window every exit. */
192 static unsigned int ple_window_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
193 module_param(ple_window_grow
, uint
, 0444);
195 /* Default resets per-vcpu window every exit to ple_window. */
196 static unsigned int ple_window_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
197 module_param(ple_window_shrink
, uint
, 0444);
199 /* Default is to compute the maximum so we can never overflow. */
200 static unsigned int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
201 module_param(ple_window_max
, uint
, 0444);
203 /* Default is SYSTEM mode, 1 for host-guest mode */
204 int __read_mostly pt_mode
= PT_MODE_SYSTEM
;
205 module_param(pt_mode
, int, S_IRUGO
);
207 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush
);
208 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond
);
209 static DEFINE_MUTEX(vmx_l1d_flush_mutex
);
211 /* Storage for pre module init parameter parsing */
212 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param
= VMENTER_L1D_FLUSH_AUTO
;
214 static const struct {
217 } vmentry_l1d_param
[] = {
218 [VMENTER_L1D_FLUSH_AUTO
] = {"auto", true},
219 [VMENTER_L1D_FLUSH_NEVER
] = {"never", true},
220 [VMENTER_L1D_FLUSH_COND
] = {"cond", true},
221 [VMENTER_L1D_FLUSH_ALWAYS
] = {"always", true},
222 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = {"EPT disabled", false},
223 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = {"not required", false},
226 #define L1D_CACHE_ORDER 4
227 static void *vmx_l1d_flush_pages
;
229 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf
)
234 if (!boot_cpu_has_bug(X86_BUG_L1TF
)) {
235 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_NOT_REQUIRED
;
240 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_EPT_DISABLED
;
244 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
)) {
247 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, msr
);
248 if (msr
& ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
) {
249 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_NOT_REQUIRED
;
254 /* If set to auto use the default l1tf mitigation method */
255 if (l1tf
== VMENTER_L1D_FLUSH_AUTO
) {
256 switch (l1tf_mitigation
) {
257 case L1TF_MITIGATION_OFF
:
258 l1tf
= VMENTER_L1D_FLUSH_NEVER
;
260 case L1TF_MITIGATION_FLUSH_NOWARN
:
261 case L1TF_MITIGATION_FLUSH
:
262 case L1TF_MITIGATION_FLUSH_NOSMT
:
263 l1tf
= VMENTER_L1D_FLUSH_COND
;
265 case L1TF_MITIGATION_FULL
:
266 case L1TF_MITIGATION_FULL_FORCE
:
267 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
270 } else if (l1tf_mitigation
== L1TF_MITIGATION_FULL_FORCE
) {
271 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
274 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
&& !vmx_l1d_flush_pages
&&
275 !boot_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
277 * This allocation for vmx_l1d_flush_pages is not tied to a VM
278 * lifetime and so should not be charged to a memcg.
280 page
= alloc_pages(GFP_KERNEL
, L1D_CACHE_ORDER
);
283 vmx_l1d_flush_pages
= page_address(page
);
286 * Initialize each page with a different pattern in
287 * order to protect against KSM in the nested
288 * virtualization case.
290 for (i
= 0; i
< 1u << L1D_CACHE_ORDER
; ++i
) {
291 memset(vmx_l1d_flush_pages
+ i
* PAGE_SIZE
, i
+ 1,
296 l1tf_vmx_mitigation
= l1tf
;
298 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
)
299 static_branch_enable(&vmx_l1d_should_flush
);
301 static_branch_disable(&vmx_l1d_should_flush
);
303 if (l1tf
== VMENTER_L1D_FLUSH_COND
)
304 static_branch_enable(&vmx_l1d_flush_cond
);
306 static_branch_disable(&vmx_l1d_flush_cond
);
310 static int vmentry_l1d_flush_parse(const char *s
)
315 for (i
= 0; i
< ARRAY_SIZE(vmentry_l1d_param
); i
++) {
316 if (vmentry_l1d_param
[i
].for_parse
&&
317 sysfs_streq(s
, vmentry_l1d_param
[i
].option
))
324 static int vmentry_l1d_flush_set(const char *s
, const struct kernel_param
*kp
)
328 l1tf
= vmentry_l1d_flush_parse(s
);
332 if (!boot_cpu_has(X86_BUG_L1TF
))
336 * Has vmx_init() run already? If not then this is the pre init
337 * parameter parsing. In that case just store the value and let
338 * vmx_init() do the proper setup after enable_ept has been
341 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
) {
342 vmentry_l1d_flush_param
= l1tf
;
346 mutex_lock(&vmx_l1d_flush_mutex
);
347 ret
= vmx_setup_l1d_flush(l1tf
);
348 mutex_unlock(&vmx_l1d_flush_mutex
);
352 static int vmentry_l1d_flush_get(char *s
, const struct kernel_param
*kp
)
354 if (WARN_ON_ONCE(l1tf_vmx_mitigation
>= ARRAY_SIZE(vmentry_l1d_param
)))
355 return sprintf(s
, "???\n");
357 return sprintf(s
, "%s\n", vmentry_l1d_param
[l1tf_vmx_mitigation
].option
);
360 static const struct kernel_param_ops vmentry_l1d_flush_ops
= {
361 .set
= vmentry_l1d_flush_set
,
362 .get
= vmentry_l1d_flush_get
,
364 module_param_cb(vmentry_l1d_flush
, &vmentry_l1d_flush_ops
, NULL
, 0644);
366 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
368 void vmx_vmexit(void);
370 #define vmx_insn_failed(fmt...) \
373 pr_warn_ratelimited(fmt); \
376 asmlinkage
void vmread_error(unsigned long field
, bool fault
)
379 kvm_spurious_fault();
381 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field
);
384 noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
386 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n",
387 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
390 noinline
void vmclear_error(struct vmcs
*vmcs
, u64 phys_addr
)
392 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs
, phys_addr
);
395 noinline
void vmptrld_error(struct vmcs
*vmcs
, u64 phys_addr
)
397 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs
, phys_addr
);
400 noinline
void invvpid_error(unsigned long ext
, u16 vpid
, gva_t gva
)
402 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n",
406 noinline
void invept_error(unsigned long ext
, u64 eptp
, gpa_t gpa
)
408 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n",
412 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
413 DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
415 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
416 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
418 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
420 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
421 static DEFINE_SPINLOCK(vmx_vpid_lock
);
423 struct vmcs_config vmcs_config
;
424 struct vmx_capability vmx_capability
;
426 #define VMX_SEGMENT_FIELD(seg) \
427 [VCPU_SREG_##seg] = { \
428 .selector = GUEST_##seg##_SELECTOR, \
429 .base = GUEST_##seg##_BASE, \
430 .limit = GUEST_##seg##_LIMIT, \
431 .ar_bytes = GUEST_##seg##_AR_BYTES, \
434 static const struct kvm_vmx_segment_field
{
439 } kvm_vmx_segment_fields
[] = {
440 VMX_SEGMENT_FIELD(CS
),
441 VMX_SEGMENT_FIELD(DS
),
442 VMX_SEGMENT_FIELD(ES
),
443 VMX_SEGMENT_FIELD(FS
),
444 VMX_SEGMENT_FIELD(GS
),
445 VMX_SEGMENT_FIELD(SS
),
446 VMX_SEGMENT_FIELD(TR
),
447 VMX_SEGMENT_FIELD(LDTR
),
450 static inline void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
452 vmx
->segment_cache
.bitmask
= 0;
455 static unsigned long host_idt_base
;
457 #if IS_ENABLED(CONFIG_HYPERV)
458 static bool __read_mostly enlightened_vmcs
= true;
459 module_param(enlightened_vmcs
, bool, 0444);
461 static int hv_enable_direct_tlbflush(struct kvm_vcpu
*vcpu
)
463 struct hv_enlightened_vmcs
*evmcs
;
464 struct hv_partition_assist_pg
**p_hv_pa_pg
=
465 &to_kvm_hv(vcpu
->kvm
)->hv_pa_pg
;
467 * Synthetic VM-Exit is not enabled in current code and so All
468 * evmcs in singe VM shares same assist page.
471 *p_hv_pa_pg
= kzalloc(PAGE_SIZE
, GFP_KERNEL_ACCOUNT
);
476 evmcs
= (struct hv_enlightened_vmcs
*)to_vmx(vcpu
)->loaded_vmcs
->vmcs
;
478 evmcs
->partition_assist_page
=
480 evmcs
->hv_vm_id
= (unsigned long)vcpu
->kvm
;
481 evmcs
->hv_enlightenments_control
.nested_flush_hypercall
= 1;
486 #endif /* IS_ENABLED(CONFIG_HYPERV) */
489 * Comment's format: document - errata name - stepping - processor name.
491 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
493 static u32 vmx_preemption_cpu_tfms
[] = {
494 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
496 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
497 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
498 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
500 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
502 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
503 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
505 * 320767.pdf - AAP86 - B1 -
506 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
509 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
511 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
513 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
515 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
516 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
517 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
519 /* Xeon E3-1220 V2 */
523 static inline bool cpu_has_broken_vmx_preemption_timer(void)
525 u32 eax
= cpuid_eax(0x00000001), i
;
527 /* Clear the reserved bits */
528 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
529 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
530 if (eax
== vmx_preemption_cpu_tfms
[i
])
536 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
538 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
541 static inline bool report_flexpriority(void)
543 return flexpriority_enabled
;
546 static int possible_passthrough_msr_slot(u32 msr
)
550 for (i
= 0; i
< ARRAY_SIZE(vmx_possible_passthrough_msrs
); i
++)
551 if (vmx_possible_passthrough_msrs
[i
] == msr
)
557 static bool is_valid_passthrough_msr(u32 msr
)
562 case 0x800 ... 0x8ff:
563 /* x2APIC MSRs. These are handled in vmx_update_msr_bitmap_x2apic() */
565 case MSR_IA32_RTIT_STATUS
:
566 case MSR_IA32_RTIT_OUTPUT_BASE
:
567 case MSR_IA32_RTIT_OUTPUT_MASK
:
568 case MSR_IA32_RTIT_CR3_MATCH
:
569 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
570 /* PT MSRs. These are handled in pt_update_intercept_for_msr() */
573 case MSR_LBR_INFO_0
... MSR_LBR_INFO_0
+ 31:
574 case MSR_LBR_NHM_FROM
... MSR_LBR_NHM_FROM
+ 31:
575 case MSR_LBR_NHM_TO
... MSR_LBR_NHM_TO
+ 31:
576 case MSR_LBR_CORE_FROM
... MSR_LBR_CORE_FROM
+ 8:
577 case MSR_LBR_CORE_TO
... MSR_LBR_CORE_TO
+ 8:
578 /* LBR MSRs. These are handled in vmx_update_intercept_for_lbr_msrs() */
582 r
= possible_passthrough_msr_slot(msr
) != -ENOENT
;
584 WARN(!r
, "Invalid MSR %x, please adapt vmx_possible_passthrough_msrs[]", msr
);
589 struct vmx_uret_msr
*vmx_find_uret_msr(struct vcpu_vmx
*vmx
, u32 msr
)
593 i
= kvm_find_user_return_msr(msr
);
595 return &vmx
->guest_uret_msrs
[i
];
599 static int vmx_set_guest_uret_msr(struct vcpu_vmx
*vmx
,
600 struct vmx_uret_msr
*msr
, u64 data
)
602 unsigned int slot
= msr
- vmx
->guest_uret_msrs
;
605 u64 old_msr_data
= msr
->data
;
607 if (msr
->load_into_hardware
) {
609 ret
= kvm_set_user_return_msr(slot
, msr
->data
, msr
->mask
);
612 msr
->data
= old_msr_data
;
617 #ifdef CONFIG_KEXEC_CORE
618 static void crash_vmclear_local_loaded_vmcss(void)
620 int cpu
= raw_smp_processor_id();
621 struct loaded_vmcs
*v
;
623 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
624 loaded_vmcss_on_cpu_link
)
627 #endif /* CONFIG_KEXEC_CORE */
629 static void __loaded_vmcs_clear(void *arg
)
631 struct loaded_vmcs
*loaded_vmcs
= arg
;
632 int cpu
= raw_smp_processor_id();
634 if (loaded_vmcs
->cpu
!= cpu
)
635 return; /* vcpu migration can race with cpu offline */
636 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
637 per_cpu(current_vmcs
, cpu
) = NULL
;
639 vmcs_clear(loaded_vmcs
->vmcs
);
640 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
641 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
643 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
646 * Ensure all writes to loaded_vmcs, including deleting it from its
647 * current percpu list, complete before setting loaded_vmcs->vcpu to
648 * -1, otherwise a different cpu can see vcpu == -1 first and add
649 * loaded_vmcs to its percpu list before it's deleted from this cpu's
650 * list. Pairs with the smp_rmb() in vmx_vcpu_load_vmcs().
654 loaded_vmcs
->cpu
= -1;
655 loaded_vmcs
->launched
= 0;
658 void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
660 int cpu
= loaded_vmcs
->cpu
;
663 smp_call_function_single(cpu
,
664 __loaded_vmcs_clear
, loaded_vmcs
, 1);
667 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
671 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
673 if (!kvm_register_is_available(&vmx
->vcpu
, VCPU_EXREG_SEGMENTS
)) {
674 kvm_register_mark_available(&vmx
->vcpu
, VCPU_EXREG_SEGMENTS
);
675 vmx
->segment_cache
.bitmask
= 0;
677 ret
= vmx
->segment_cache
.bitmask
& mask
;
678 vmx
->segment_cache
.bitmask
|= mask
;
682 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
684 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
686 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
687 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
691 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
693 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
695 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
696 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
700 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
702 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
704 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
705 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
709 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
711 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
713 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
714 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
718 void vmx_update_exception_bitmap(struct kvm_vcpu
*vcpu
)
722 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
723 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
725 * Guest access to VMware backdoor ports could legitimately
726 * trigger #GP because of TSS I/O permission bitmap.
727 * We intercept those #GP and allow access to them anyway
730 if (enable_vmware_backdoor
)
731 eb
|= (1u << GP_VECTOR
);
732 if ((vcpu
->guest_debug
&
733 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
734 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
735 eb
|= 1u << BP_VECTOR
;
736 if (to_vmx(vcpu
)->rmode
.vm86_active
)
738 if (!vmx_need_pf_intercept(vcpu
))
739 eb
&= ~(1u << PF_VECTOR
);
741 /* When we are running a nested L2 guest and L1 specified for it a
742 * certain exception bitmap, we must trap the same exceptions and pass
743 * them to L1. When running L2, we will only handle the exceptions
744 * specified above if L1 did not want them.
746 if (is_guest_mode(vcpu
))
747 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
749 int mask
= 0, match
= 0;
751 if (enable_ept
&& (eb
& (1u << PF_VECTOR
))) {
753 * If EPT is enabled, #PF is currently only intercepted
754 * if MAXPHYADDR is smaller on the guest than on the
755 * host. In that case we only care about present,
756 * non-reserved faults. For vmcs02, however, PFEC_MASK
757 * and PFEC_MATCH are set in prepare_vmcs02_rare.
759 mask
= PFERR_PRESENT_MASK
| PFERR_RSVD_MASK
;
760 match
= PFERR_PRESENT_MASK
;
762 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, mask
);
763 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, match
);
766 vmcs_write32(EXCEPTION_BITMAP
, eb
);
770 * Check if MSR is intercepted for currently loaded MSR bitmap.
772 static bool msr_write_intercepted(struct vcpu_vmx
*vmx
, u32 msr
)
774 if (!(exec_controls_get(vmx
) & CPU_BASED_USE_MSR_BITMAPS
))
777 return vmx_test_msr_bitmap_write(vmx
->loaded_vmcs
->msr_bitmap
,
781 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
782 unsigned long entry
, unsigned long exit
)
784 vm_entry_controls_clearbit(vmx
, entry
);
785 vm_exit_controls_clearbit(vmx
, exit
);
788 int vmx_find_loadstore_msr_slot(struct vmx_msrs
*m
, u32 msr
)
792 for (i
= 0; i
< m
->nr
; ++i
) {
793 if (m
->val
[i
].index
== msr
)
799 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
802 struct msr_autoload
*m
= &vmx
->msr_autoload
;
806 if (cpu_has_load_ia32_efer()) {
807 clear_atomic_switch_msr_special(vmx
,
808 VM_ENTRY_LOAD_IA32_EFER
,
809 VM_EXIT_LOAD_IA32_EFER
);
813 case MSR_CORE_PERF_GLOBAL_CTRL
:
814 if (cpu_has_load_perf_global_ctrl()) {
815 clear_atomic_switch_msr_special(vmx
,
816 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
817 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
822 i
= vmx_find_loadstore_msr_slot(&m
->guest
, msr
);
826 m
->guest
.val
[i
] = m
->guest
.val
[m
->guest
.nr
];
827 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
830 i
= vmx_find_loadstore_msr_slot(&m
->host
, msr
);
835 m
->host
.val
[i
] = m
->host
.val
[m
->host
.nr
];
836 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
839 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
840 unsigned long entry
, unsigned long exit
,
841 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
842 u64 guest_val
, u64 host_val
)
844 vmcs_write64(guest_val_vmcs
, guest_val
);
845 if (host_val_vmcs
!= HOST_IA32_EFER
)
846 vmcs_write64(host_val_vmcs
, host_val
);
847 vm_entry_controls_setbit(vmx
, entry
);
848 vm_exit_controls_setbit(vmx
, exit
);
851 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
852 u64 guest_val
, u64 host_val
, bool entry_only
)
855 struct msr_autoload
*m
= &vmx
->msr_autoload
;
859 if (cpu_has_load_ia32_efer()) {
860 add_atomic_switch_msr_special(vmx
,
861 VM_ENTRY_LOAD_IA32_EFER
,
862 VM_EXIT_LOAD_IA32_EFER
,
865 guest_val
, host_val
);
869 case MSR_CORE_PERF_GLOBAL_CTRL
:
870 if (cpu_has_load_perf_global_ctrl()) {
871 add_atomic_switch_msr_special(vmx
,
872 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
873 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
874 GUEST_IA32_PERF_GLOBAL_CTRL
,
875 HOST_IA32_PERF_GLOBAL_CTRL
,
876 guest_val
, host_val
);
880 case MSR_IA32_PEBS_ENABLE
:
881 /* PEBS needs a quiescent period after being disabled (to write
882 * a record). Disabling PEBS through VMX MSR swapping doesn't
883 * provide that period, so a CPU could write host's record into
886 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
889 i
= vmx_find_loadstore_msr_slot(&m
->guest
, msr
);
891 j
= vmx_find_loadstore_msr_slot(&m
->host
, msr
);
893 if ((i
< 0 && m
->guest
.nr
== MAX_NR_LOADSTORE_MSRS
) ||
894 (j
< 0 && m
->host
.nr
== MAX_NR_LOADSTORE_MSRS
)) {
895 printk_once(KERN_WARNING
"Not enough msr switch entries. "
896 "Can't add msr %x\n", msr
);
901 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
903 m
->guest
.val
[i
].index
= msr
;
904 m
->guest
.val
[i
].value
= guest_val
;
911 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
913 m
->host
.val
[j
].index
= msr
;
914 m
->host
.val
[j
].value
= host_val
;
917 static bool update_transition_efer(struct vcpu_vmx
*vmx
)
919 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
923 /* Shadow paging assumes NX to be available. */
925 guest_efer
|= EFER_NX
;
928 * LMA and LME handled by hardware; SCE meaningless outside long mode.
930 ignore_bits
|= EFER_SCE
;
932 ignore_bits
|= EFER_LMA
| EFER_LME
;
933 /* SCE is meaningful only in long mode on Intel */
934 if (guest_efer
& EFER_LMA
)
935 ignore_bits
&= ~(u64
)EFER_SCE
;
939 * On EPT, we can't emulate NX, so we must switch EFER atomically.
940 * On CPUs that support "load IA32_EFER", always switch EFER
941 * atomically, since it's faster than switching it manually.
943 if (cpu_has_load_ia32_efer() ||
944 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
945 if (!(guest_efer
& EFER_LMA
))
946 guest_efer
&= ~EFER_LME
;
947 if (guest_efer
!= host_efer
)
948 add_atomic_switch_msr(vmx
, MSR_EFER
,
949 guest_efer
, host_efer
, false);
951 clear_atomic_switch_msr(vmx
, MSR_EFER
);
955 i
= kvm_find_user_return_msr(MSR_EFER
);
959 clear_atomic_switch_msr(vmx
, MSR_EFER
);
961 guest_efer
&= ~ignore_bits
;
962 guest_efer
|= host_efer
& ignore_bits
;
964 vmx
->guest_uret_msrs
[i
].data
= guest_efer
;
965 vmx
->guest_uret_msrs
[i
].mask
= ~ignore_bits
;
972 * On 32-bit kernels, VM exits still load the FS and GS bases from the
973 * VMCS rather than the segment table. KVM uses this helper to figure
974 * out the current bases to poke them into the VMCS before entry.
976 static unsigned long segment_base(u16 selector
)
978 struct desc_struct
*table
;
981 if (!(selector
& ~SEGMENT_RPL_MASK
))
984 table
= get_current_gdt_ro();
986 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
987 u16 ldt_selector
= kvm_read_ldt();
989 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
992 table
= (struct desc_struct
*)segment_base(ldt_selector
);
994 v
= get_desc_base(&table
[selector
>> 3]);
999 static inline bool pt_can_write_msr(struct vcpu_vmx
*vmx
)
1001 return vmx_pt_mode_is_host_guest() &&
1002 !(vmx
->pt_desc
.guest
.ctl
& RTIT_CTL_TRACEEN
);
1005 static inline bool pt_output_base_valid(struct kvm_vcpu
*vcpu
, u64 base
)
1007 /* The base must be 128-byte aligned and a legal physical address. */
1008 return kvm_vcpu_is_legal_aligned_gpa(vcpu
, base
, 128);
1011 static inline void pt_load_msr(struct pt_ctx
*ctx
, u32 addr_range
)
1015 wrmsrl(MSR_IA32_RTIT_STATUS
, ctx
->status
);
1016 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE
, ctx
->output_base
);
1017 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK
, ctx
->output_mask
);
1018 wrmsrl(MSR_IA32_RTIT_CR3_MATCH
, ctx
->cr3_match
);
1019 for (i
= 0; i
< addr_range
; i
++) {
1020 wrmsrl(MSR_IA32_RTIT_ADDR0_A
+ i
* 2, ctx
->addr_a
[i
]);
1021 wrmsrl(MSR_IA32_RTIT_ADDR0_B
+ i
* 2, ctx
->addr_b
[i
]);
1025 static inline void pt_save_msr(struct pt_ctx
*ctx
, u32 addr_range
)
1029 rdmsrl(MSR_IA32_RTIT_STATUS
, ctx
->status
);
1030 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE
, ctx
->output_base
);
1031 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK
, ctx
->output_mask
);
1032 rdmsrl(MSR_IA32_RTIT_CR3_MATCH
, ctx
->cr3_match
);
1033 for (i
= 0; i
< addr_range
; i
++) {
1034 rdmsrl(MSR_IA32_RTIT_ADDR0_A
+ i
* 2, ctx
->addr_a
[i
]);
1035 rdmsrl(MSR_IA32_RTIT_ADDR0_B
+ i
* 2, ctx
->addr_b
[i
]);
1039 static void pt_guest_enter(struct vcpu_vmx
*vmx
)
1041 if (vmx_pt_mode_is_system())
1045 * GUEST_IA32_RTIT_CTL is already set in the VMCS.
1046 * Save host state before VM entry.
1048 rdmsrl(MSR_IA32_RTIT_CTL
, vmx
->pt_desc
.host
.ctl
);
1049 if (vmx
->pt_desc
.guest
.ctl
& RTIT_CTL_TRACEEN
) {
1050 wrmsrl(MSR_IA32_RTIT_CTL
, 0);
1051 pt_save_msr(&vmx
->pt_desc
.host
, vmx
->pt_desc
.addr_range
);
1052 pt_load_msr(&vmx
->pt_desc
.guest
, vmx
->pt_desc
.addr_range
);
1056 static void pt_guest_exit(struct vcpu_vmx
*vmx
)
1058 if (vmx_pt_mode_is_system())
1061 if (vmx
->pt_desc
.guest
.ctl
& RTIT_CTL_TRACEEN
) {
1062 pt_save_msr(&vmx
->pt_desc
.guest
, vmx
->pt_desc
.addr_range
);
1063 pt_load_msr(&vmx
->pt_desc
.host
, vmx
->pt_desc
.addr_range
);
1066 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */
1067 wrmsrl(MSR_IA32_RTIT_CTL
, vmx
->pt_desc
.host
.ctl
);
1070 void vmx_set_host_fs_gs(struct vmcs_host_state
*host
, u16 fs_sel
, u16 gs_sel
,
1071 unsigned long fs_base
, unsigned long gs_base
)
1073 if (unlikely(fs_sel
!= host
->fs_sel
)) {
1075 vmcs_write16(HOST_FS_SELECTOR
, fs_sel
);
1077 vmcs_write16(HOST_FS_SELECTOR
, 0);
1078 host
->fs_sel
= fs_sel
;
1080 if (unlikely(gs_sel
!= host
->gs_sel
)) {
1082 vmcs_write16(HOST_GS_SELECTOR
, gs_sel
);
1084 vmcs_write16(HOST_GS_SELECTOR
, 0);
1085 host
->gs_sel
= gs_sel
;
1087 if (unlikely(fs_base
!= host
->fs_base
)) {
1088 vmcs_writel(HOST_FS_BASE
, fs_base
);
1089 host
->fs_base
= fs_base
;
1091 if (unlikely(gs_base
!= host
->gs_base
)) {
1092 vmcs_writel(HOST_GS_BASE
, gs_base
);
1093 host
->gs_base
= gs_base
;
1097 void vmx_prepare_switch_to_guest(struct kvm_vcpu
*vcpu
)
1099 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1100 struct vmcs_host_state
*host_state
;
1101 #ifdef CONFIG_X86_64
1102 int cpu
= raw_smp_processor_id();
1104 unsigned long fs_base
, gs_base
;
1108 vmx
->req_immediate_exit
= false;
1111 * Note that guest MSRs to be saved/restored can also be changed
1112 * when guest state is loaded. This happens when guest transitions
1113 * to/from long-mode by setting MSR_EFER.LMA.
1115 if (!vmx
->guest_uret_msrs_loaded
) {
1116 vmx
->guest_uret_msrs_loaded
= true;
1117 for (i
= 0; i
< kvm_nr_uret_msrs
; ++i
) {
1118 if (!vmx
->guest_uret_msrs
[i
].load_into_hardware
)
1121 kvm_set_user_return_msr(i
,
1122 vmx
->guest_uret_msrs
[i
].data
,
1123 vmx
->guest_uret_msrs
[i
].mask
);
1127 if (vmx
->nested
.need_vmcs12_to_shadow_sync
)
1128 nested_sync_vmcs12_to_shadow(vcpu
);
1130 if (vmx
->guest_state_loaded
)
1133 host_state
= &vmx
->loaded_vmcs
->host_state
;
1136 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1137 * allow segment selectors with cpl > 0 or ti == 1.
1139 host_state
->ldt_sel
= kvm_read_ldt();
1141 #ifdef CONFIG_X86_64
1142 savesegment(ds
, host_state
->ds_sel
);
1143 savesegment(es
, host_state
->es_sel
);
1145 gs_base
= cpu_kernelmode_gs_base(cpu
);
1146 if (likely(is_64bit_mm(current
->mm
))) {
1147 current_save_fsgs();
1148 fs_sel
= current
->thread
.fsindex
;
1149 gs_sel
= current
->thread
.gsindex
;
1150 fs_base
= current
->thread
.fsbase
;
1151 vmx
->msr_host_kernel_gs_base
= current
->thread
.gsbase
;
1153 savesegment(fs
, fs_sel
);
1154 savesegment(gs
, gs_sel
);
1155 fs_base
= read_msr(MSR_FS_BASE
);
1156 vmx
->msr_host_kernel_gs_base
= read_msr(MSR_KERNEL_GS_BASE
);
1159 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1161 savesegment(fs
, fs_sel
);
1162 savesegment(gs
, gs_sel
);
1163 fs_base
= segment_base(fs_sel
);
1164 gs_base
= segment_base(gs_sel
);
1167 vmx_set_host_fs_gs(host_state
, fs_sel
, gs_sel
, fs_base
, gs_base
);
1168 vmx
->guest_state_loaded
= true;
1171 static void vmx_prepare_switch_to_host(struct vcpu_vmx
*vmx
)
1173 struct vmcs_host_state
*host_state
;
1175 if (!vmx
->guest_state_loaded
)
1178 host_state
= &vmx
->loaded_vmcs
->host_state
;
1180 ++vmx
->vcpu
.stat
.host_state_reload
;
1182 #ifdef CONFIG_X86_64
1183 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1185 if (host_state
->ldt_sel
|| (host_state
->gs_sel
& 7)) {
1186 kvm_load_ldt(host_state
->ldt_sel
);
1187 #ifdef CONFIG_X86_64
1188 load_gs_index(host_state
->gs_sel
);
1190 loadsegment(gs
, host_state
->gs_sel
);
1193 if (host_state
->fs_sel
& 7)
1194 loadsegment(fs
, host_state
->fs_sel
);
1195 #ifdef CONFIG_X86_64
1196 if (unlikely(host_state
->ds_sel
| host_state
->es_sel
)) {
1197 loadsegment(ds
, host_state
->ds_sel
);
1198 loadsegment(es
, host_state
->es_sel
);
1201 invalidate_tss_limit();
1202 #ifdef CONFIG_X86_64
1203 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1205 load_fixmap_gdt(raw_smp_processor_id());
1206 vmx
->guest_state_loaded
= false;
1207 vmx
->guest_uret_msrs_loaded
= false;
1210 #ifdef CONFIG_X86_64
1211 static u64
vmx_read_guest_kernel_gs_base(struct vcpu_vmx
*vmx
)
1214 if (vmx
->guest_state_loaded
)
1215 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1217 return vmx
->msr_guest_kernel_gs_base
;
1220 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx
*vmx
, u64 data
)
1223 if (vmx
->guest_state_loaded
)
1224 wrmsrl(MSR_KERNEL_GS_BASE
, data
);
1226 vmx
->msr_guest_kernel_gs_base
= data
;
1230 void vmx_vcpu_load_vmcs(struct kvm_vcpu
*vcpu
, int cpu
,
1231 struct loaded_vmcs
*buddy
)
1233 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1234 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
1237 if (!already_loaded
) {
1238 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1239 local_irq_disable();
1242 * Ensure loaded_vmcs->cpu is read before adding loaded_vmcs to
1243 * this cpu's percpu list, otherwise it may not yet be deleted
1244 * from its previous cpu's percpu list. Pairs with the
1245 * smb_wmb() in __loaded_vmcs_clear().
1249 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1250 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1254 prev
= per_cpu(current_vmcs
, cpu
);
1255 if (prev
!= vmx
->loaded_vmcs
->vmcs
) {
1256 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1257 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1260 * No indirect branch prediction barrier needed when switching
1261 * the active VMCS within a guest, e.g. on nested VM-Enter.
1262 * The L1 VMM can protect itself with retpolines, IBPB or IBRS.
1264 if (!buddy
|| WARN_ON_ONCE(buddy
->vmcs
!= prev
))
1265 indirect_branch_prediction_barrier();
1268 if (!already_loaded
) {
1269 void *gdt
= get_current_gdt_ro();
1270 unsigned long sysenter_esp
;
1273 * Flush all EPTP/VPID contexts, the new pCPU may have stale
1274 * TLB entries from its previous association with the vCPU.
1276 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1279 * Linux uses per-cpu TSS and GDT, so set these when switching
1280 * processors. See 22.2.4.
1282 vmcs_writel(HOST_TR_BASE
,
1283 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
1284 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
1286 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1287 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1289 vmx
->loaded_vmcs
->cpu
= cpu
;
1294 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1295 * vcpu mutex is already taken.
1297 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1299 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1301 vmx_vcpu_load_vmcs(vcpu
, cpu
, NULL
);
1303 vmx_vcpu_pi_load(vcpu
, cpu
);
1305 vmx
->host_debugctlmsr
= get_debugctlmsr();
1308 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1310 vmx_vcpu_pi_put(vcpu
);
1312 vmx_prepare_switch_to_host(to_vmx(vcpu
));
1315 bool vmx_emulation_required(struct kvm_vcpu
*vcpu
)
1317 return emulate_invalid_guest_state
&& !vmx_guest_state_valid(vcpu
);
1320 unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1322 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1323 unsigned long rflags
, save_rflags
;
1325 if (!kvm_register_is_available(vcpu
, VCPU_EXREG_RFLAGS
)) {
1326 kvm_register_mark_available(vcpu
, VCPU_EXREG_RFLAGS
);
1327 rflags
= vmcs_readl(GUEST_RFLAGS
);
1328 if (vmx
->rmode
.vm86_active
) {
1329 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1330 save_rflags
= vmx
->rmode
.save_rflags
;
1331 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1333 vmx
->rflags
= rflags
;
1338 void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1340 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1341 unsigned long old_rflags
;
1343 if (is_unrestricted_guest(vcpu
)) {
1344 kvm_register_mark_available(vcpu
, VCPU_EXREG_RFLAGS
);
1345 vmx
->rflags
= rflags
;
1346 vmcs_writel(GUEST_RFLAGS
, rflags
);
1350 old_rflags
= vmx_get_rflags(vcpu
);
1351 vmx
->rflags
= rflags
;
1352 if (vmx
->rmode
.vm86_active
) {
1353 vmx
->rmode
.save_rflags
= rflags
;
1354 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1356 vmcs_writel(GUEST_RFLAGS
, rflags
);
1358 if ((old_rflags
^ vmx
->rflags
) & X86_EFLAGS_VM
)
1359 vmx
->emulation_required
= vmx_emulation_required(vcpu
);
1362 static bool vmx_get_if_flag(struct kvm_vcpu
*vcpu
)
1364 return vmx_get_rflags(vcpu
) & X86_EFLAGS_IF
;
1367 u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
1369 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1372 if (interruptibility
& GUEST_INTR_STATE_STI
)
1373 ret
|= KVM_X86_SHADOW_INT_STI
;
1374 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1375 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1380 void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1382 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1383 u32 interruptibility
= interruptibility_old
;
1385 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1387 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1388 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1389 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1390 interruptibility
|= GUEST_INTR_STATE_STI
;
1392 if ((interruptibility
!= interruptibility_old
))
1393 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1396 static int vmx_rtit_ctl_check(struct kvm_vcpu
*vcpu
, u64 data
)
1398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1399 unsigned long value
;
1402 * Any MSR write that attempts to change bits marked reserved will
1405 if (data
& vmx
->pt_desc
.ctl_bitmask
)
1409 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will
1410 * result in a #GP unless the same write also clears TraceEn.
1412 if ((vmx
->pt_desc
.guest
.ctl
& RTIT_CTL_TRACEEN
) &&
1413 ((vmx
->pt_desc
.guest
.ctl
^ data
) & ~RTIT_CTL_TRACEEN
))
1417 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit
1418 * and FabricEn would cause #GP, if
1419 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0
1421 if ((data
& RTIT_CTL_TRACEEN
) && !(data
& RTIT_CTL_TOPA
) &&
1422 !(data
& RTIT_CTL_FABRIC_EN
) &&
1423 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1424 PT_CAP_single_range_output
))
1428 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that
1429 * utilize encodings marked reserved will cause a #GP fault.
1431 value
= intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_mtc_periods
);
1432 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_mtc
) &&
1433 !test_bit((data
& RTIT_CTL_MTC_RANGE
) >>
1434 RTIT_CTL_MTC_RANGE_OFFSET
, &value
))
1436 value
= intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1437 PT_CAP_cycle_thresholds
);
1438 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_psb_cyc
) &&
1439 !test_bit((data
& RTIT_CTL_CYC_THRESH
) >>
1440 RTIT_CTL_CYC_THRESH_OFFSET
, &value
))
1442 value
= intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_psb_periods
);
1443 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_psb_cyc
) &&
1444 !test_bit((data
& RTIT_CTL_PSB_FREQ
) >>
1445 RTIT_CTL_PSB_FREQ_OFFSET
, &value
))
1449 * If ADDRx_CFG is reserved or the encodings is >2 will
1450 * cause a #GP fault.
1452 value
= (data
& RTIT_CTL_ADDR0
) >> RTIT_CTL_ADDR0_OFFSET
;
1453 if ((value
&& (vmx
->pt_desc
.addr_range
< 1)) || (value
> 2))
1455 value
= (data
& RTIT_CTL_ADDR1
) >> RTIT_CTL_ADDR1_OFFSET
;
1456 if ((value
&& (vmx
->pt_desc
.addr_range
< 2)) || (value
> 2))
1458 value
= (data
& RTIT_CTL_ADDR2
) >> RTIT_CTL_ADDR2_OFFSET
;
1459 if ((value
&& (vmx
->pt_desc
.addr_range
< 3)) || (value
> 2))
1461 value
= (data
& RTIT_CTL_ADDR3
) >> RTIT_CTL_ADDR3_OFFSET
;
1462 if ((value
&& (vmx
->pt_desc
.addr_range
< 4)) || (value
> 2))
1468 static bool vmx_can_emulate_instruction(struct kvm_vcpu
*vcpu
, void *insn
, int insn_len
)
1471 * Emulation of instructions in SGX enclaves is impossible as RIP does
1472 * not point tthe failing instruction, and even if it did, the code
1473 * stream is inaccessible. Inject #UD instead of exiting to userspace
1474 * so that guest userspace can't DoS the guest simply by triggering
1475 * emulation (enclaves are CPL3 only).
1477 if (to_vmx(vcpu
)->exit_reason
.enclave_mode
) {
1478 kvm_queue_exception(vcpu
, UD_VECTOR
);
1484 static int skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1486 union vmx_exit_reason exit_reason
= to_vmx(vcpu
)->exit_reason
;
1487 unsigned long rip
, orig_rip
;
1491 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on
1492 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be
1493 * set when EPT misconfig occurs. In practice, real hardware updates
1494 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors
1495 * (namely Hyper-V) don't set it due to it being undefined behavior,
1496 * i.e. we end up advancing IP with some random value.
1498 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
) ||
1499 exit_reason
.basic
!= EXIT_REASON_EPT_MISCONFIG
) {
1500 instr_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1503 * Emulating an enclave's instructions isn't supported as KVM
1504 * cannot access the enclave's memory or its true RIP, e.g. the
1505 * vmcs.GUEST_RIP points at the exit point of the enclave, not
1506 * the RIP that actually triggered the VM-Exit. But, because
1507 * most instructions that cause VM-Exit will #UD in an enclave,
1508 * most instruction-based VM-Exits simply do not occur.
1510 * There are a few exceptions, notably the debug instructions
1511 * INT1ICEBRK and INT3, as they are allowed in debug enclaves
1512 * and generate #DB/#BP as expected, which KVM might intercept.
1513 * But again, the CPU does the dirty work and saves an instr
1514 * length of zero so VMMs don't shoot themselves in the foot.
1515 * WARN if KVM tries to skip a non-zero length instruction on
1516 * a VM-Exit from an enclave.
1521 WARN(exit_reason
.enclave_mode
,
1522 "KVM: skipping instruction after SGX enclave VM-Exit");
1524 orig_rip
= kvm_rip_read(vcpu
);
1525 rip
= orig_rip
+ instr_len
;
1526 #ifdef CONFIG_X86_64
1528 * We need to mask out the high 32 bits of RIP if not in 64-bit
1529 * mode, but just finding out that we are in 64-bit mode is
1530 * quite expensive. Only do it if there was a carry.
1532 if (unlikely(((rip
^ orig_rip
) >> 31) == 3) && !is_64_bit_mode(vcpu
))
1535 kvm_rip_write(vcpu
, rip
);
1537 if (!kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
))
1542 /* skipping an emulated instruction also counts */
1543 vmx_set_interrupt_shadow(vcpu
, 0);
1549 * Recognizes a pending MTF VM-exit and records the nested state for later
1552 static void vmx_update_emulated_instruction(struct kvm_vcpu
*vcpu
)
1554 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1555 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1557 if (!is_guest_mode(vcpu
))
1561 * Per the SDM, MTF takes priority over debug-trap exceptions besides
1562 * T-bit traps. As instruction emulation is completed (i.e. at the
1563 * instruction boundary), any #DB exception pending delivery must be a
1564 * debug-trap. Record the pending MTF state to be delivered in
1565 * vmx_check_nested_events().
1567 if (nested_cpu_has_mtf(vmcs12
) &&
1568 (!vcpu
->arch
.exception
.pending
||
1569 vcpu
->arch
.exception
.nr
== DB_VECTOR
))
1570 vmx
->nested
.mtf_pending
= true;
1572 vmx
->nested
.mtf_pending
= false;
1575 static int vmx_skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1577 vmx_update_emulated_instruction(vcpu
);
1578 return skip_emulated_instruction(vcpu
);
1581 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1584 * Ensure that we clear the HLT state in the VMCS. We don't need to
1585 * explicitly skip the instruction because if the HLT state is set,
1586 * then the instruction is already executing and RIP has already been
1589 if (kvm_hlt_in_guest(vcpu
->kvm
) &&
1590 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1591 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1594 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
1596 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1597 unsigned nr
= vcpu
->arch
.exception
.nr
;
1598 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
1599 u32 error_code
= vcpu
->arch
.exception
.error_code
;
1600 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1602 kvm_deliver_exception_payload(vcpu
);
1604 if (has_error_code
) {
1605 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1606 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1609 if (vmx
->rmode
.vm86_active
) {
1611 if (kvm_exception_is_soft(nr
))
1612 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1613 kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
);
1617 WARN_ON_ONCE(vmx
->emulation_required
);
1619 if (kvm_exception_is_soft(nr
)) {
1620 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1621 vmx
->vcpu
.arch
.event_exit_inst_len
);
1622 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1624 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1626 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1628 vmx_clear_hlt(vcpu
);
1631 static void vmx_setup_uret_msr(struct vcpu_vmx
*vmx
, unsigned int msr
,
1632 bool load_into_hardware
)
1634 struct vmx_uret_msr
*uret_msr
;
1636 uret_msr
= vmx_find_uret_msr(vmx
, msr
);
1640 uret_msr
->load_into_hardware
= load_into_hardware
;
1644 * Configuring user return MSRs to automatically save, load, and restore MSRs
1645 * that need to be shoved into hardware when running the guest. Note, omitting
1646 * an MSR here does _NOT_ mean it's not emulated, only that it will not be
1647 * loaded into hardware when running the guest.
1649 static void vmx_setup_uret_msrs(struct vcpu_vmx
*vmx
)
1651 #ifdef CONFIG_X86_64
1652 bool load_syscall_msrs
;
1655 * The SYSCALL MSRs are only needed on long mode guests, and only
1656 * when EFER.SCE is set.
1658 load_syscall_msrs
= is_long_mode(&vmx
->vcpu
) &&
1659 (vmx
->vcpu
.arch
.efer
& EFER_SCE
);
1661 vmx_setup_uret_msr(vmx
, MSR_STAR
, load_syscall_msrs
);
1662 vmx_setup_uret_msr(vmx
, MSR_LSTAR
, load_syscall_msrs
);
1663 vmx_setup_uret_msr(vmx
, MSR_SYSCALL_MASK
, load_syscall_msrs
);
1665 vmx_setup_uret_msr(vmx
, MSR_EFER
, update_transition_efer(vmx
));
1667 vmx_setup_uret_msr(vmx
, MSR_TSC_AUX
,
1668 guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
) ||
1669 guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDPID
));
1672 * hle=0, rtm=0, tsx_ctrl=1 can be found with some combinations of new
1673 * kernel and old userspace. If those guests run on a tsx=off host, do
1674 * allow guests to use TSX_CTRL, but don't change the value in hardware
1675 * so that TSX remains always disabled.
1677 vmx_setup_uret_msr(vmx
, MSR_IA32_TSX_CTRL
, boot_cpu_has(X86_FEATURE_RTM
));
1680 * The set of MSRs to load may have changed, reload MSRs before the
1683 vmx
->guest_uret_msrs_loaded
= false;
1686 u64
vmx_get_l2_tsc_offset(struct kvm_vcpu
*vcpu
)
1688 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1690 if (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETTING
))
1691 return vmcs12
->tsc_offset
;
1696 u64
vmx_get_l2_tsc_multiplier(struct kvm_vcpu
*vcpu
)
1698 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1700 if (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETTING
) &&
1701 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_TSC_SCALING
))
1702 return vmcs12
->tsc_multiplier
;
1704 return kvm_default_tsc_scaling_ratio
;
1707 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1709 vmcs_write64(TSC_OFFSET
, offset
);
1712 static void vmx_write_tsc_multiplier(struct kvm_vcpu
*vcpu
, u64 multiplier
)
1714 vmcs_write64(TSC_MULTIPLIER
, multiplier
);
1718 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1719 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1720 * all guests if the "nested" module option is off, and can also be disabled
1721 * for a single guest by disabling its VMX cpuid bit.
1723 bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1725 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
1728 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
1731 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
1733 return !(val
& ~valid_bits
);
1736 static int vmx_get_msr_feature(struct kvm_msr_entry
*msr
)
1738 switch (msr
->index
) {
1739 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
1742 return vmx_get_vmx_msr(&vmcs_config
.nested
, msr
->index
, &msr
->data
);
1743 case MSR_IA32_PERF_CAPABILITIES
:
1744 msr
->data
= vmx_get_perf_capabilities();
1747 return KVM_MSR_RET_INVALID
;
1752 * Reads an msr value (of 'msr_index') into 'pdata'.
1753 * Returns 0 on success, non-0 otherwise.
1754 * Assumes vcpu_load() was already called.
1756 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
1758 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1759 struct vmx_uret_msr
*msr
;
1762 switch (msr_info
->index
) {
1763 #ifdef CONFIG_X86_64
1765 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
1768 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
1770 case MSR_KERNEL_GS_BASE
:
1771 msr_info
->data
= vmx_read_guest_kernel_gs_base(vmx
);
1775 return kvm_get_msr_common(vcpu
, msr_info
);
1776 case MSR_IA32_TSX_CTRL
:
1777 if (!msr_info
->host_initiated
&&
1778 !(vcpu
->arch
.arch_capabilities
& ARCH_CAP_TSX_CTRL_MSR
))
1781 case MSR_IA32_UMWAIT_CONTROL
:
1782 if (!msr_info
->host_initiated
&& !vmx_has_waitpkg(vmx
))
1785 msr_info
->data
= vmx
->msr_ia32_umwait_control
;
1787 case MSR_IA32_SPEC_CTRL
:
1788 if (!msr_info
->host_initiated
&&
1789 !guest_has_spec_ctrl_msr(vcpu
))
1792 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
1794 case MSR_IA32_SYSENTER_CS
:
1795 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
1797 case MSR_IA32_SYSENTER_EIP
:
1798 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1800 case MSR_IA32_SYSENTER_ESP
:
1801 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1803 case MSR_IA32_BNDCFGS
:
1804 if (!kvm_mpx_supported() ||
1805 (!msr_info
->host_initiated
&&
1806 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
1808 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
1810 case MSR_IA32_MCG_EXT_CTL
:
1811 if (!msr_info
->host_initiated
&&
1812 !(vmx
->msr_ia32_feature_control
&
1813 FEAT_CTL_LMCE_ENABLED
))
1815 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
1817 case MSR_IA32_FEAT_CTL
:
1818 msr_info
->data
= vmx
->msr_ia32_feature_control
;
1820 case MSR_IA32_SGXLEPUBKEYHASH0
... MSR_IA32_SGXLEPUBKEYHASH3
:
1821 if (!msr_info
->host_initiated
&&
1822 !guest_cpuid_has(vcpu
, X86_FEATURE_SGX_LC
))
1824 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_sgxlepubkeyhash
1825 [msr_info
->index
- MSR_IA32_SGXLEPUBKEYHASH0
];
1827 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
1828 if (!nested_vmx_allowed(vcpu
))
1830 if (vmx_get_vmx_msr(&vmx
->nested
.msrs
, msr_info
->index
,
1834 * Enlightened VMCS v1 doesn't have certain VMCS fields but
1835 * instead of just ignoring the features, different Hyper-V
1836 * versions are either trying to use them and fail or do some
1837 * sanity checking and refuse to boot. Filter all unsupported
1840 if (!msr_info
->host_initiated
&&
1841 vmx
->nested
.enlightened_vmcs_enabled
)
1842 nested_evmcs_filter_control_msr(msr_info
->index
,
1845 case MSR_IA32_RTIT_CTL
:
1846 if (!vmx_pt_mode_is_host_guest())
1848 msr_info
->data
= vmx
->pt_desc
.guest
.ctl
;
1850 case MSR_IA32_RTIT_STATUS
:
1851 if (!vmx_pt_mode_is_host_guest())
1853 msr_info
->data
= vmx
->pt_desc
.guest
.status
;
1855 case MSR_IA32_RTIT_CR3_MATCH
:
1856 if (!vmx_pt_mode_is_host_guest() ||
1857 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1858 PT_CAP_cr3_filtering
))
1860 msr_info
->data
= vmx
->pt_desc
.guest
.cr3_match
;
1862 case MSR_IA32_RTIT_OUTPUT_BASE
:
1863 if (!vmx_pt_mode_is_host_guest() ||
1864 (!intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1865 PT_CAP_topa_output
) &&
1866 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1867 PT_CAP_single_range_output
)))
1869 msr_info
->data
= vmx
->pt_desc
.guest
.output_base
;
1871 case MSR_IA32_RTIT_OUTPUT_MASK
:
1872 if (!vmx_pt_mode_is_host_guest() ||
1873 (!intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1874 PT_CAP_topa_output
) &&
1875 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1876 PT_CAP_single_range_output
)))
1878 msr_info
->data
= vmx
->pt_desc
.guest
.output_mask
;
1880 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
1881 index
= msr_info
->index
- MSR_IA32_RTIT_ADDR0_A
;
1882 if (!vmx_pt_mode_is_host_guest() ||
1883 (index
>= 2 * intel_pt_validate_cap(vmx
->pt_desc
.caps
,
1884 PT_CAP_num_address_ranges
)))
1887 msr_info
->data
= vmx
->pt_desc
.guest
.addr_b
[index
/ 2];
1889 msr_info
->data
= vmx
->pt_desc
.guest
.addr_a
[index
/ 2];
1891 case MSR_IA32_DEBUGCTLMSR
:
1892 msr_info
->data
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
1896 msr
= vmx_find_uret_msr(vmx
, msr_info
->index
);
1898 msr_info
->data
= msr
->data
;
1901 return kvm_get_msr_common(vcpu
, msr_info
);
1907 static u64
nested_vmx_truncate_sysenter_addr(struct kvm_vcpu
*vcpu
,
1910 #ifdef CONFIG_X86_64
1911 if (!guest_cpuid_has(vcpu
, X86_FEATURE_LM
))
1914 return (unsigned long)data
;
1917 static u64
vcpu_supported_debugctl(struct kvm_vcpu
*vcpu
)
1919 u64 debugctl
= vmx_supported_debugctl();
1921 if (!intel_pmu_lbr_is_enabled(vcpu
))
1922 debugctl
&= ~DEBUGCTLMSR_LBR_MASK
;
1924 if (!guest_cpuid_has(vcpu
, X86_FEATURE_BUS_LOCK_DETECT
))
1925 debugctl
&= ~DEBUGCTLMSR_BUS_LOCK_DETECT
;
1931 * Writes msr value into the appropriate "register".
1932 * Returns 0 on success, non-0 otherwise.
1933 * Assumes vcpu_load() was already called.
1935 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
1937 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1938 struct vmx_uret_msr
*msr
;
1940 u32 msr_index
= msr_info
->index
;
1941 u64 data
= msr_info
->data
;
1944 switch (msr_index
) {
1946 ret
= kvm_set_msr_common(vcpu
, msr_info
);
1948 #ifdef CONFIG_X86_64
1950 vmx_segment_cache_clear(vmx
);
1951 vmcs_writel(GUEST_FS_BASE
, data
);
1954 vmx_segment_cache_clear(vmx
);
1955 vmcs_writel(GUEST_GS_BASE
, data
);
1957 case MSR_KERNEL_GS_BASE
:
1958 vmx_write_guest_kernel_gs_base(vmx
, data
);
1961 case MSR_IA32_SYSENTER_CS
:
1962 if (is_guest_mode(vcpu
))
1963 get_vmcs12(vcpu
)->guest_sysenter_cs
= data
;
1964 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1966 case MSR_IA32_SYSENTER_EIP
:
1967 if (is_guest_mode(vcpu
)) {
1968 data
= nested_vmx_truncate_sysenter_addr(vcpu
, data
);
1969 get_vmcs12(vcpu
)->guest_sysenter_eip
= data
;
1971 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1973 case MSR_IA32_SYSENTER_ESP
:
1974 if (is_guest_mode(vcpu
)) {
1975 data
= nested_vmx_truncate_sysenter_addr(vcpu
, data
);
1976 get_vmcs12(vcpu
)->guest_sysenter_esp
= data
;
1978 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1980 case MSR_IA32_DEBUGCTLMSR
: {
1981 u64 invalid
= data
& ~vcpu_supported_debugctl(vcpu
);
1982 if (invalid
& (DEBUGCTLMSR_BTF
|DEBUGCTLMSR_LBR
)) {
1983 if (report_ignored_msrs
)
1984 vcpu_unimpl(vcpu
, "%s: BTF|LBR in IA32_DEBUGCTLMSR 0x%llx, nop\n",
1986 data
&= ~(DEBUGCTLMSR_BTF
|DEBUGCTLMSR_LBR
);
1987 invalid
&= ~(DEBUGCTLMSR_BTF
|DEBUGCTLMSR_LBR
);
1993 if (is_guest_mode(vcpu
) && get_vmcs12(vcpu
)->vm_exit_controls
&
1994 VM_EXIT_SAVE_DEBUG_CONTROLS
)
1995 get_vmcs12(vcpu
)->guest_ia32_debugctl
= data
;
1997 vmcs_write64(GUEST_IA32_DEBUGCTL
, data
);
1998 if (intel_pmu_lbr_is_enabled(vcpu
) && !to_vmx(vcpu
)->lbr_desc
.event
&&
1999 (data
& DEBUGCTLMSR_LBR
))
2000 intel_pmu_create_guest_lbr_event(vcpu
);
2003 case MSR_IA32_BNDCFGS
:
2004 if (!kvm_mpx_supported() ||
2005 (!msr_info
->host_initiated
&&
2006 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
2008 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
2009 (data
& MSR_IA32_BNDCFGS_RSVD
))
2011 vmcs_write64(GUEST_BNDCFGS
, data
);
2013 case MSR_IA32_UMWAIT_CONTROL
:
2014 if (!msr_info
->host_initiated
&& !vmx_has_waitpkg(vmx
))
2017 /* The reserved bit 1 and non-32 bit [63:32] should be zero */
2018 if (data
& (BIT_ULL(1) | GENMASK_ULL(63, 32)))
2021 vmx
->msr_ia32_umwait_control
= data
;
2023 case MSR_IA32_SPEC_CTRL
:
2024 if (!msr_info
->host_initiated
&&
2025 !guest_has_spec_ctrl_msr(vcpu
))
2028 if (kvm_spec_ctrl_test_value(data
))
2031 vmx
->spec_ctrl
= data
;
2037 * When it's written (to non-zero) for the first time, pass
2041 * The handling of the MSR bitmap for L2 guests is done in
2042 * nested_vmx_prepare_msr_bitmap. We should not touch the
2043 * vmcs02.msr_bitmap here since it gets completely overwritten
2044 * in the merging. We update the vmcs01 here for L1 as well
2045 * since it will end up touching the MSR anyway now.
2047 vmx_disable_intercept_for_msr(vcpu
,
2051 case MSR_IA32_TSX_CTRL
:
2052 if (!msr_info
->host_initiated
&&
2053 !(vcpu
->arch
.arch_capabilities
& ARCH_CAP_TSX_CTRL_MSR
))
2055 if (data
& ~(TSX_CTRL_RTM_DISABLE
| TSX_CTRL_CPUID_CLEAR
))
2058 case MSR_IA32_PRED_CMD
:
2059 if (!msr_info
->host_initiated
&&
2060 !guest_has_pred_cmd_msr(vcpu
))
2063 if (data
& ~PRED_CMD_IBPB
)
2065 if (!boot_cpu_has(X86_FEATURE_IBPB
))
2070 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
2074 * When it's written (to non-zero) for the first time, pass
2078 * The handling of the MSR bitmap for L2 guests is done in
2079 * nested_vmx_prepare_msr_bitmap. We should not touch the
2080 * vmcs02.msr_bitmap here since it gets completely overwritten
2083 vmx_disable_intercept_for_msr(vcpu
, MSR_IA32_PRED_CMD
, MSR_TYPE_W
);
2085 case MSR_IA32_CR_PAT
:
2086 if (!kvm_pat_valid(data
))
2089 if (is_guest_mode(vcpu
) &&
2090 get_vmcs12(vcpu
)->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
2091 get_vmcs12(vcpu
)->guest_ia32_pat
= data
;
2093 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2094 vmcs_write64(GUEST_IA32_PAT
, data
);
2095 vcpu
->arch
.pat
= data
;
2098 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2100 case MSR_IA32_TSC_ADJUST
:
2101 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2103 case MSR_IA32_MCG_EXT_CTL
:
2104 if ((!msr_info
->host_initiated
&&
2105 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
2106 FEAT_CTL_LMCE_ENABLED
)) ||
2107 (data
& ~MCG_EXT_CTL_LMCE_EN
))
2109 vcpu
->arch
.mcg_ext_ctl
= data
;
2111 case MSR_IA32_FEAT_CTL
:
2112 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
2113 (to_vmx(vcpu
)->msr_ia32_feature_control
&
2114 FEAT_CTL_LOCKED
&& !msr_info
->host_initiated
))
2116 vmx
->msr_ia32_feature_control
= data
;
2117 if (msr_info
->host_initiated
&& data
== 0)
2118 vmx_leave_nested(vcpu
);
2120 /* SGX may be enabled/disabled by guest's firmware */
2121 vmx_write_encls_bitmap(vcpu
, NULL
);
2123 case MSR_IA32_SGXLEPUBKEYHASH0
... MSR_IA32_SGXLEPUBKEYHASH3
:
2125 * On real hardware, the LE hash MSRs are writable before
2126 * the firmware sets bit 0 in MSR 0x7a ("activating" SGX),
2127 * at which point SGX related bits in IA32_FEATURE_CONTROL
2130 * KVM does not emulate SGX activation for simplicity, so
2131 * allow writes to the LE hash MSRs if IA32_FEATURE_CONTROL
2132 * is unlocked. This is technically not architectural
2133 * behavior, but it's close enough.
2135 if (!msr_info
->host_initiated
&&
2136 (!guest_cpuid_has(vcpu
, X86_FEATURE_SGX_LC
) ||
2137 ((vmx
->msr_ia32_feature_control
& FEAT_CTL_LOCKED
) &&
2138 !(vmx
->msr_ia32_feature_control
& FEAT_CTL_SGX_LC_ENABLED
))))
2140 vmx
->msr_ia32_sgxlepubkeyhash
2141 [msr_index
- MSR_IA32_SGXLEPUBKEYHASH0
] = data
;
2143 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2144 if (!msr_info
->host_initiated
)
2145 return 1; /* they are read-only */
2146 if (!nested_vmx_allowed(vcpu
))
2148 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
2149 case MSR_IA32_RTIT_CTL
:
2150 if (!vmx_pt_mode_is_host_guest() ||
2151 vmx_rtit_ctl_check(vcpu
, data
) ||
2154 vmcs_write64(GUEST_IA32_RTIT_CTL
, data
);
2155 vmx
->pt_desc
.guest
.ctl
= data
;
2156 pt_update_intercept_for_msr(vcpu
);
2158 case MSR_IA32_RTIT_STATUS
:
2159 if (!pt_can_write_msr(vmx
))
2161 if (data
& MSR_IA32_RTIT_STATUS_MASK
)
2163 vmx
->pt_desc
.guest
.status
= data
;
2165 case MSR_IA32_RTIT_CR3_MATCH
:
2166 if (!pt_can_write_msr(vmx
))
2168 if (!intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2169 PT_CAP_cr3_filtering
))
2171 vmx
->pt_desc
.guest
.cr3_match
= data
;
2173 case MSR_IA32_RTIT_OUTPUT_BASE
:
2174 if (!pt_can_write_msr(vmx
))
2176 if (!intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2177 PT_CAP_topa_output
) &&
2178 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2179 PT_CAP_single_range_output
))
2181 if (!pt_output_base_valid(vcpu
, data
))
2183 vmx
->pt_desc
.guest
.output_base
= data
;
2185 case MSR_IA32_RTIT_OUTPUT_MASK
:
2186 if (!pt_can_write_msr(vmx
))
2188 if (!intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2189 PT_CAP_topa_output
) &&
2190 !intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2191 PT_CAP_single_range_output
))
2193 vmx
->pt_desc
.guest
.output_mask
= data
;
2195 case MSR_IA32_RTIT_ADDR0_A
... MSR_IA32_RTIT_ADDR3_B
:
2196 if (!pt_can_write_msr(vmx
))
2198 index
= msr_info
->index
- MSR_IA32_RTIT_ADDR0_A
;
2199 if (index
>= 2 * intel_pt_validate_cap(vmx
->pt_desc
.caps
,
2200 PT_CAP_num_address_ranges
))
2202 if (is_noncanonical_address(data
, vcpu
))
2205 vmx
->pt_desc
.guest
.addr_b
[index
/ 2] = data
;
2207 vmx
->pt_desc
.guest
.addr_a
[index
/ 2] = data
;
2209 case MSR_IA32_PERF_CAPABILITIES
:
2210 if (data
&& !vcpu_to_pmu(vcpu
)->version
)
2212 if (data
& PMU_CAP_LBR_FMT
) {
2213 if ((data
& PMU_CAP_LBR_FMT
) !=
2214 (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT
))
2216 if (!intel_pmu_lbr_is_compatible(vcpu
))
2219 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2224 msr
= vmx_find_uret_msr(vmx
, msr_index
);
2226 ret
= vmx_set_guest_uret_msr(vmx
, msr
, data
);
2228 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2234 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2236 unsigned long guest_owned_bits
;
2238 kvm_register_mark_available(vcpu
, reg
);
2242 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2245 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2247 case VCPU_EXREG_PDPTR
:
2249 ept_save_pdptrs(vcpu
);
2251 case VCPU_EXREG_CR0
:
2252 guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2254 vcpu
->arch
.cr0
&= ~guest_owned_bits
;
2255 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & guest_owned_bits
;
2257 case VCPU_EXREG_CR3
:
2259 * When intercepting CR3 loads, e.g. for shadowing paging, KVM's
2260 * CR3 is loaded into hardware, not the guest's CR3.
2262 if (!(exec_controls_get(to_vmx(vcpu
)) & CPU_BASED_CR3_LOAD_EXITING
))
2263 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2265 case VCPU_EXREG_CR4
:
2266 guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2268 vcpu
->arch
.cr4
&= ~guest_owned_bits
;
2269 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & guest_owned_bits
;
2272 KVM_BUG_ON(1, vcpu
->kvm
);
2277 static __init
int cpu_has_kvm_support(void)
2279 return cpu_has_vmx();
2282 static __init
int vmx_disabled_by_bios(void)
2284 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL
) ||
2285 !boot_cpu_has(X86_FEATURE_VMX
);
2288 static int kvm_cpu_vmxon(u64 vmxon_pointer
)
2292 cr4_set_bits(X86_CR4_VMXE
);
2294 asm_volatile_goto("1: vmxon %[vmxon_pointer]\n\t"
2295 _ASM_EXTABLE(1b
, %l
[fault
])
2296 : : [vmxon_pointer
] "m"(vmxon_pointer
)
2301 WARN_ONCE(1, "VMXON faulted, MSR_IA32_FEAT_CTL (0x3a) = 0x%llx\n",
2302 rdmsrl_safe(MSR_IA32_FEAT_CTL
, &msr
) ? 0xdeadbeef : msr
);
2303 cr4_clear_bits(X86_CR4_VMXE
);
2308 static int hardware_enable(void)
2310 int cpu
= raw_smp_processor_id();
2311 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2314 if (cr4_read_shadow() & X86_CR4_VMXE
)
2318 * This can happen if we hot-added a CPU but failed to allocate
2319 * VP assist page for it.
2321 if (static_branch_unlikely(&enable_evmcs
) &&
2322 !hv_get_vp_assist_page(cpu
))
2325 intel_pt_handle_vmx(1);
2327 r
= kvm_cpu_vmxon(phys_addr
);
2329 intel_pt_handle_vmx(0);
2339 static void vmclear_local_loaded_vmcss(void)
2341 int cpu
= raw_smp_processor_id();
2342 struct loaded_vmcs
*v
, *n
;
2344 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2345 loaded_vmcss_on_cpu_link
)
2346 __loaded_vmcs_clear(v
);
2349 static void hardware_disable(void)
2351 vmclear_local_loaded_vmcss();
2354 kvm_spurious_fault();
2356 intel_pt_handle_vmx(0);
2360 * There is no X86_FEATURE for SGX yet, but anyway we need to query CPUID
2361 * directly instead of going through cpu_has(), to ensure KVM is trapping
2362 * ENCLS whenever it's supported in hardware. It does not matter whether
2363 * the host OS supports or has enabled SGX.
2365 static bool cpu_has_sgx(void)
2367 return cpuid_eax(0) >= 0x12 && (cpuid_eax(0x12) & BIT(0));
2370 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2371 u32 msr
, u32
*result
)
2373 u32 vmx_msr_low
, vmx_msr_high
;
2374 u32 ctl
= ctl_min
| ctl_opt
;
2376 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2378 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2379 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2381 /* Ensure minimum (required) set of control bits are supported. */
2389 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
,
2390 struct vmx_capability
*vmx_cap
)
2392 u32 vmx_msr_low
, vmx_msr_high
;
2393 u32 min
, opt
, min2
, opt2
;
2394 u32 _pin_based_exec_control
= 0;
2395 u32 _cpu_based_exec_control
= 0;
2396 u32 _cpu_based_2nd_exec_control
= 0;
2397 u32 _vmexit_control
= 0;
2398 u32 _vmentry_control
= 0;
2400 memset(vmcs_conf
, 0, sizeof(*vmcs_conf
));
2401 min
= CPU_BASED_HLT_EXITING
|
2402 #ifdef CONFIG_X86_64
2403 CPU_BASED_CR8_LOAD_EXITING
|
2404 CPU_BASED_CR8_STORE_EXITING
|
2406 CPU_BASED_CR3_LOAD_EXITING
|
2407 CPU_BASED_CR3_STORE_EXITING
|
2408 CPU_BASED_UNCOND_IO_EXITING
|
2409 CPU_BASED_MOV_DR_EXITING
|
2410 CPU_BASED_USE_TSC_OFFSETTING
|
2411 CPU_BASED_MWAIT_EXITING
|
2412 CPU_BASED_MONITOR_EXITING
|
2413 CPU_BASED_INVLPG_EXITING
|
2414 CPU_BASED_RDPMC_EXITING
;
2416 opt
= CPU_BASED_TPR_SHADOW
|
2417 CPU_BASED_USE_MSR_BITMAPS
|
2418 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2419 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2420 &_cpu_based_exec_control
) < 0)
2422 #ifdef CONFIG_X86_64
2423 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2424 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2425 ~CPU_BASED_CR8_STORE_EXITING
;
2427 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2429 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2430 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2431 SECONDARY_EXEC_WBINVD_EXITING
|
2432 SECONDARY_EXEC_ENABLE_VPID
|
2433 SECONDARY_EXEC_ENABLE_EPT
|
2434 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2435 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2436 SECONDARY_EXEC_DESC
|
2437 SECONDARY_EXEC_ENABLE_RDTSCP
|
2438 SECONDARY_EXEC_ENABLE_INVPCID
|
2439 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2440 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2441 SECONDARY_EXEC_SHADOW_VMCS
|
2442 SECONDARY_EXEC_XSAVES
|
2443 SECONDARY_EXEC_RDSEED_EXITING
|
2444 SECONDARY_EXEC_RDRAND_EXITING
|
2445 SECONDARY_EXEC_ENABLE_PML
|
2446 SECONDARY_EXEC_TSC_SCALING
|
2447 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE
|
2448 SECONDARY_EXEC_PT_USE_GPA
|
2449 SECONDARY_EXEC_PT_CONCEAL_VMX
|
2450 SECONDARY_EXEC_ENABLE_VMFUNC
|
2451 SECONDARY_EXEC_BUS_LOCK_DETECTION
;
2453 opt2
|= SECONDARY_EXEC_ENCLS_EXITING
;
2454 if (adjust_vmx_controls(min2
, opt2
,
2455 MSR_IA32_VMX_PROCBASED_CTLS2
,
2456 &_cpu_based_2nd_exec_control
) < 0)
2459 #ifndef CONFIG_X86_64
2460 if (!(_cpu_based_2nd_exec_control
&
2461 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2462 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2465 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2466 _cpu_based_2nd_exec_control
&= ~(
2467 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2468 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2469 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2471 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
2472 &vmx_cap
->ept
, &vmx_cap
->vpid
);
2474 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2475 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2477 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2478 CPU_BASED_CR3_STORE_EXITING
|
2479 CPU_BASED_INVLPG_EXITING
);
2480 } else if (vmx_cap
->ept
) {
2482 pr_warn_once("EPT CAP should not exist if not support "
2483 "1-setting enable EPT VM-execution control\n");
2485 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
2488 pr_warn_once("VPID CAP should not exist if not support "
2489 "1-setting enable VPID VM-execution control\n");
2492 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
2493 #ifdef CONFIG_X86_64
2494 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2496 opt
= VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
|
2497 VM_EXIT_LOAD_IA32_PAT
|
2498 VM_EXIT_LOAD_IA32_EFER
|
2499 VM_EXIT_CLEAR_BNDCFGS
|
2500 VM_EXIT_PT_CONCEAL_PIP
|
2501 VM_EXIT_CLEAR_IA32_RTIT_CTL
;
2502 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2503 &_vmexit_control
) < 0)
2506 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2507 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
2508 PIN_BASED_VMX_PREEMPTION_TIMER
;
2509 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2510 &_pin_based_exec_control
) < 0)
2513 if (cpu_has_broken_vmx_preemption_timer())
2514 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2515 if (!(_cpu_based_2nd_exec_control
&
2516 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
2517 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2519 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2520 opt
= VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
|
2521 VM_ENTRY_LOAD_IA32_PAT
|
2522 VM_ENTRY_LOAD_IA32_EFER
|
2523 VM_ENTRY_LOAD_BNDCFGS
|
2524 VM_ENTRY_PT_CONCEAL_PIP
|
2525 VM_ENTRY_LOAD_IA32_RTIT_CTL
;
2526 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2527 &_vmentry_control
) < 0)
2531 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2532 * can't be used due to an errata where VM Exit may incorrectly clear
2533 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2534 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2536 if (boot_cpu_data
.x86
== 0x6) {
2537 switch (boot_cpu_data
.x86_model
) {
2538 case 26: /* AAK155 */
2539 case 30: /* AAP115 */
2540 case 37: /* AAT100 */
2541 case 44: /* BC86,AAY89,BD102 */
2543 _vmentry_control
&= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
;
2544 _vmexit_control
&= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
;
2545 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2546 "does not work properly. Using workaround\n");
2554 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2556 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2557 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2560 #ifdef CONFIG_X86_64
2561 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2562 if (vmx_msr_high
& (1u<<16))
2566 /* Require Write-Back (WB) memory type for VMCS accesses. */
2567 if (((vmx_msr_high
>> 18) & 15) != 6)
2570 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2571 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
2572 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
2574 vmcs_conf
->revision_id
= vmx_msr_low
;
2576 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2577 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2578 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2579 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2580 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2582 #if IS_ENABLED(CONFIG_HYPERV)
2583 if (enlightened_vmcs
)
2584 evmcs_sanitize_exec_ctrls(vmcs_conf
);
2590 struct vmcs
*alloc_vmcs_cpu(bool shadow
, int cpu
, gfp_t flags
)
2592 int node
= cpu_to_node(cpu
);
2596 pages
= __alloc_pages_node(node
, flags
, vmcs_config
.order
);
2599 vmcs
= page_address(pages
);
2600 memset(vmcs
, 0, vmcs_config
.size
);
2602 /* KVM supports Enlightened VMCS v1 only */
2603 if (static_branch_unlikely(&enable_evmcs
))
2604 vmcs
->hdr
.revision_id
= KVM_EVMCS_VERSION
;
2606 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
2609 vmcs
->hdr
.shadow_vmcs
= 1;
2613 void free_vmcs(struct vmcs
*vmcs
)
2615 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2619 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2621 void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2623 if (!loaded_vmcs
->vmcs
)
2625 loaded_vmcs_clear(loaded_vmcs
);
2626 free_vmcs(loaded_vmcs
->vmcs
);
2627 loaded_vmcs
->vmcs
= NULL
;
2628 if (loaded_vmcs
->msr_bitmap
)
2629 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
2630 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
2633 int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2635 loaded_vmcs
->vmcs
= alloc_vmcs(false);
2636 if (!loaded_vmcs
->vmcs
)
2639 vmcs_clear(loaded_vmcs
->vmcs
);
2641 loaded_vmcs
->shadow_vmcs
= NULL
;
2642 loaded_vmcs
->hv_timer_soft_disabled
= false;
2643 loaded_vmcs
->cpu
= -1;
2644 loaded_vmcs
->launched
= 0;
2646 if (cpu_has_vmx_msr_bitmap()) {
2647 loaded_vmcs
->msr_bitmap
= (unsigned long *)
2648 __get_free_page(GFP_KERNEL_ACCOUNT
);
2649 if (!loaded_vmcs
->msr_bitmap
)
2651 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
2653 if (IS_ENABLED(CONFIG_HYPERV
) &&
2654 static_branch_unlikely(&enable_evmcs
) &&
2655 (ms_hyperv
.nested_features
& HV_X64_NESTED_MSR_BITMAP
)) {
2656 struct hv_enlightened_vmcs
*evmcs
=
2657 (struct hv_enlightened_vmcs
*)loaded_vmcs
->vmcs
;
2659 evmcs
->hv_enlightenments_control
.msr_bitmap
= 1;
2663 memset(&loaded_vmcs
->host_state
, 0, sizeof(struct vmcs_host_state
));
2664 memset(&loaded_vmcs
->controls_shadow
, 0,
2665 sizeof(struct vmcs_controls_shadow
));
2670 free_loaded_vmcs(loaded_vmcs
);
2674 static void free_kvm_area(void)
2678 for_each_possible_cpu(cpu
) {
2679 free_vmcs(per_cpu(vmxarea
, cpu
));
2680 per_cpu(vmxarea
, cpu
) = NULL
;
2684 static __init
int alloc_kvm_area(void)
2688 for_each_possible_cpu(cpu
) {
2691 vmcs
= alloc_vmcs_cpu(false, cpu
, GFP_KERNEL
);
2698 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2699 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2700 * revision_id reported by MSR_IA32_VMX_BASIC.
2702 * However, even though not explicitly documented by
2703 * TLFS, VMXArea passed as VMXON argument should
2704 * still be marked with revision_id reported by
2707 if (static_branch_unlikely(&enable_evmcs
))
2708 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
2710 per_cpu(vmxarea
, cpu
) = vmcs
;
2715 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
2716 struct kvm_segment
*save
)
2718 if (!emulate_invalid_guest_state
) {
2720 * CS and SS RPL should be equal during guest entry according
2721 * to VMX spec, but in reality it is not always so. Since vcpu
2722 * is in the middle of the transition from real mode to
2723 * protected mode it is safe to assume that RPL 0 is a good
2726 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
2727 save
->selector
&= ~SEGMENT_RPL_MASK
;
2728 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
2731 __vmx_set_segment(vcpu
, save
, seg
);
2734 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2736 unsigned long flags
;
2737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2740 * Update real mode segment cache. It may be not up-to-date if segment
2741 * register was written while vcpu was in a guest mode.
2743 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2744 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2745 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2746 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2747 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2748 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2750 vmx
->rmode
.vm86_active
= 0;
2752 __vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2754 flags
= vmcs_readl(GUEST_RFLAGS
);
2755 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2756 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2757 vmcs_writel(GUEST_RFLAGS
, flags
);
2759 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2760 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2762 vmx_update_exception_bitmap(vcpu
);
2764 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2765 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2766 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2767 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2768 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2769 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2772 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
2774 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2775 struct kvm_segment var
= *save
;
2778 if (seg
== VCPU_SREG_CS
)
2781 if (!emulate_invalid_guest_state
) {
2782 var
.selector
= var
.base
>> 4;
2783 var
.base
= var
.base
& 0xffff0;
2793 if (save
->base
& 0xf)
2794 printk_once(KERN_WARNING
"kvm: segment base is not "
2795 "paragraph aligned when entering "
2796 "protected mode (seg=%d)", seg
);
2799 vmcs_write16(sf
->selector
, var
.selector
);
2800 vmcs_writel(sf
->base
, var
.base
);
2801 vmcs_write32(sf
->limit
, var
.limit
);
2802 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
2805 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2807 unsigned long flags
;
2808 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2809 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(vcpu
->kvm
);
2811 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2812 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2813 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2814 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2815 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2816 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2817 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2819 vmx
->rmode
.vm86_active
= 1;
2822 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2823 * vcpu. Warn the user that an update is overdue.
2825 if (!kvm_vmx
->tss_addr
)
2826 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2827 "called before entering vcpu\n");
2829 vmx_segment_cache_clear(vmx
);
2831 vmcs_writel(GUEST_TR_BASE
, kvm_vmx
->tss_addr
);
2832 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2833 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2835 flags
= vmcs_readl(GUEST_RFLAGS
);
2836 vmx
->rmode
.save_rflags
= flags
;
2838 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2840 vmcs_writel(GUEST_RFLAGS
, flags
);
2841 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2842 vmx_update_exception_bitmap(vcpu
);
2844 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2845 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2846 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2847 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2848 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2849 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2852 int vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2854 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2855 struct vmx_uret_msr
*msr
= vmx_find_uret_msr(vmx
, MSR_EFER
);
2857 /* Nothing to do if hardware doesn't support EFER. */
2861 vcpu
->arch
.efer
= efer
;
2862 if (efer
& EFER_LMA
) {
2863 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
2866 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
2868 msr
->data
= efer
& ~EFER_LME
;
2870 vmx_setup_uret_msrs(vmx
);
2874 #ifdef CONFIG_X86_64
2876 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2880 vmx_segment_cache_clear(to_vmx(vcpu
));
2882 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2883 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
2884 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2886 vmcs_write32(GUEST_TR_AR_BYTES
,
2887 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
2888 | VMX_AR_TYPE_BUSY_64_TSS
);
2890 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2893 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2895 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
2896 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2901 static void vmx_flush_tlb_all(struct kvm_vcpu
*vcpu
)
2903 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2906 * INVEPT must be issued when EPT is enabled, irrespective of VPID, as
2907 * the CPU is not required to invalidate guest-physical mappings on
2908 * VM-Entry, even if VPID is disabled. Guest-physical mappings are
2909 * associated with the root EPT structure and not any particular VPID
2910 * (INVVPID also isn't required to invalidate guest-physical mappings).
2914 } else if (enable_vpid
) {
2915 if (cpu_has_vmx_invvpid_global()) {
2916 vpid_sync_vcpu_global();
2918 vpid_sync_vcpu_single(vmx
->vpid
);
2919 vpid_sync_vcpu_single(vmx
->nested
.vpid02
);
2924 static inline int vmx_get_current_vpid(struct kvm_vcpu
*vcpu
)
2926 if (is_guest_mode(vcpu
))
2927 return nested_get_vpid02(vcpu
);
2928 return to_vmx(vcpu
)->vpid
;
2931 static void vmx_flush_tlb_current(struct kvm_vcpu
*vcpu
)
2933 struct kvm_mmu
*mmu
= vcpu
->arch
.mmu
;
2934 u64 root_hpa
= mmu
->root_hpa
;
2936 /* No flush required if the current context is invalid. */
2937 if (!VALID_PAGE(root_hpa
))
2941 ept_sync_context(construct_eptp(vcpu
, root_hpa
,
2942 mmu
->shadow_root_level
));
2944 vpid_sync_context(vmx_get_current_vpid(vcpu
));
2947 static void vmx_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t addr
)
2950 * vpid_sync_vcpu_addr() is a nop if vpid==0, see the comment in
2951 * vmx_flush_tlb_guest() for an explanation of why this is ok.
2953 vpid_sync_vcpu_addr(vmx_get_current_vpid(vcpu
), addr
);
2956 static void vmx_flush_tlb_guest(struct kvm_vcpu
*vcpu
)
2959 * vpid_sync_context() is a nop if vpid==0, e.g. if enable_vpid==0 or a
2960 * vpid couldn't be allocated for this vCPU. VM-Enter and VM-Exit are
2961 * required to flush GVA->{G,H}PA mappings from the TLB if vpid is
2962 * disabled (VM-Enter with vpid enabled and vpid==0 is disallowed),
2963 * i.e. no explicit INVVPID is necessary.
2965 vpid_sync_context(vmx_get_current_vpid(vcpu
));
2968 void vmx_ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2970 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
2972 if (!kvm_register_is_dirty(vcpu
, VCPU_EXREG_PDPTR
))
2975 if (is_pae_paging(vcpu
)) {
2976 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
2977 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
2978 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
2979 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
2983 void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2985 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
2987 if (WARN_ON_ONCE(!is_pae_paging(vcpu
)))
2990 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2991 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2992 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2993 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2995 kvm_register_mark_dirty(vcpu
, VCPU_EXREG_PDPTR
);
2998 #define CR3_EXITING_BITS (CPU_BASED_CR3_LOAD_EXITING | \
2999 CPU_BASED_CR3_STORE_EXITING)
3001 void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3003 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3004 unsigned long hw_cr0
, old_cr0_pg
;
3007 old_cr0_pg
= kvm_read_cr0_bits(vcpu
, X86_CR0_PG
);
3009 hw_cr0
= (cr0
& ~KVM_VM_CR0_ALWAYS_OFF
);
3010 if (is_unrestricted_guest(vcpu
))
3011 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3013 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3015 hw_cr0
|= X86_CR0_WP
;
3017 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3020 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3024 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3025 vmcs_writel(GUEST_CR0
, hw_cr0
);
3026 vcpu
->arch
.cr0
= cr0
;
3027 kvm_register_mark_available(vcpu
, VCPU_EXREG_CR0
);
3029 #ifdef CONFIG_X86_64
3030 if (vcpu
->arch
.efer
& EFER_LME
) {
3031 if (!old_cr0_pg
&& (cr0
& X86_CR0_PG
))
3033 else if (old_cr0_pg
&& !(cr0
& X86_CR0_PG
))
3038 if (enable_ept
&& !is_unrestricted_guest(vcpu
)) {
3040 * Ensure KVM has an up-to-date snapshot of the guest's CR3. If
3041 * the below code _enables_ CR3 exiting, vmx_cache_reg() will
3042 * (correctly) stop reading vmcs.GUEST_CR3 because it thinks
3043 * KVM's CR3 is installed.
3045 if (!kvm_register_is_available(vcpu
, VCPU_EXREG_CR3
))
3046 vmx_cache_reg(vcpu
, VCPU_EXREG_CR3
);
3049 * When running with EPT but not unrestricted guest, KVM must
3050 * intercept CR3 accesses when paging is _disabled_. This is
3051 * necessary because restricted guests can't actually run with
3052 * paging disabled, and so KVM stuffs its own CR3 in order to
3053 * run the guest when identity mapped page tables.
3055 * Do _NOT_ check the old CR0.PG, e.g. to optimize away the
3056 * update, it may be stale with respect to CR3 interception,
3057 * e.g. after nested VM-Enter.
3059 * Lastly, honor L1's desires, i.e. intercept CR3 loads and/or
3060 * stores to forward them to L1, even if KVM does not need to
3061 * intercept them to preserve its identity mapped page tables.
3063 if (!(cr0
& X86_CR0_PG
)) {
3064 exec_controls_setbit(vmx
, CR3_EXITING_BITS
);
3065 } else if (!is_guest_mode(vcpu
)) {
3066 exec_controls_clearbit(vmx
, CR3_EXITING_BITS
);
3068 tmp
= exec_controls_get(vmx
);
3069 tmp
&= ~CR3_EXITING_BITS
;
3070 tmp
|= get_vmcs12(vcpu
)->cpu_based_vm_exec_control
& CR3_EXITING_BITS
;
3071 exec_controls_set(vmx
, tmp
);
3074 /* Note, vmx_set_cr4() consumes the new vcpu->arch.cr0. */
3075 if ((old_cr0_pg
^ cr0
) & X86_CR0_PG
)
3076 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3079 /* depends on vcpu->arch.cr0 to be set to a new value */
3080 vmx
->emulation_required
= vmx_emulation_required(vcpu
);
3083 static int vmx_get_max_tdp_level(void)
3085 if (cpu_has_vmx_ept_5levels())
3090 u64
construct_eptp(struct kvm_vcpu
*vcpu
, hpa_t root_hpa
, int root_level
)
3092 u64 eptp
= VMX_EPTP_MT_WB
;
3094 eptp
|= (root_level
== 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
3096 if (enable_ept_ad_bits
&&
3097 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
3098 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
3104 static void vmx_load_mmu_pgd(struct kvm_vcpu
*vcpu
, hpa_t root_hpa
,
3107 struct kvm
*kvm
= vcpu
->kvm
;
3108 bool update_guest_cr3
= true;
3109 unsigned long guest_cr3
;
3113 eptp
= construct_eptp(vcpu
, root_hpa
, root_level
);
3114 vmcs_write64(EPT_POINTER
, eptp
);
3116 hv_track_root_tdp(vcpu
, root_hpa
);
3118 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
3119 guest_cr3
= to_kvm_vmx(kvm
)->ept_identity_map_addr
;
3120 else if (test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3121 guest_cr3
= vcpu
->arch
.cr3
;
3122 else /* vmcs01.GUEST_CR3 is already up-to-date. */
3123 update_guest_cr3
= false;
3124 vmx_ept_load_pdptrs(vcpu
);
3126 guest_cr3
= root_hpa
| kvm_get_active_pcid(vcpu
);
3129 if (update_guest_cr3
)
3130 vmcs_writel(GUEST_CR3
, guest_cr3
);
3133 static bool vmx_is_valid_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3136 * We operate under the default treatment of SMM, so VMX cannot be
3137 * enabled under SMM. Note, whether or not VMXE is allowed at all is
3138 * handled by kvm_is_valid_cr4().
3140 if ((cr4
& X86_CR4_VMXE
) && is_smm(vcpu
))
3143 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
3149 void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3151 unsigned long old_cr4
= vcpu
->arch
.cr4
;
3152 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3154 * Pass through host's Machine Check Enable value to hw_cr4, which
3155 * is in force while we are in guest mode. Do not let guests control
3156 * this bit, even if host CR4.MCE == 0.
3158 unsigned long hw_cr4
;
3160 hw_cr4
= (cr4_read_shadow() & X86_CR4_MCE
) | (cr4
& ~X86_CR4_MCE
);
3161 if (is_unrestricted_guest(vcpu
))
3162 hw_cr4
|= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST
;
3163 else if (vmx
->rmode
.vm86_active
)
3164 hw_cr4
|= KVM_RMODE_VM_CR4_ALWAYS_ON
;
3166 hw_cr4
|= KVM_PMODE_VM_CR4_ALWAYS_ON
;
3168 if (!boot_cpu_has(X86_FEATURE_UMIP
) && vmx_umip_emulated()) {
3169 if (cr4
& X86_CR4_UMIP
) {
3170 secondary_exec_controls_setbit(vmx
, SECONDARY_EXEC_DESC
);
3171 hw_cr4
&= ~X86_CR4_UMIP
;
3172 } else if (!is_guest_mode(vcpu
) ||
3173 !nested_cpu_has2(get_vmcs12(vcpu
), SECONDARY_EXEC_DESC
)) {
3174 secondary_exec_controls_clearbit(vmx
, SECONDARY_EXEC_DESC
);
3178 vcpu
->arch
.cr4
= cr4
;
3179 kvm_register_mark_available(vcpu
, VCPU_EXREG_CR4
);
3181 if (!is_unrestricted_guest(vcpu
)) {
3183 if (!is_paging(vcpu
)) {
3184 hw_cr4
&= ~X86_CR4_PAE
;
3185 hw_cr4
|= X86_CR4_PSE
;
3186 } else if (!(cr4
& X86_CR4_PAE
)) {
3187 hw_cr4
&= ~X86_CR4_PAE
;
3192 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3193 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3194 * to be manually disabled when guest switches to non-paging
3197 * If !enable_unrestricted_guest, the CPU is always running
3198 * with CR0.PG=1 and CR4 needs to be modified.
3199 * If enable_unrestricted_guest, the CPU automatically
3200 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3202 if (!is_paging(vcpu
))
3203 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
3206 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3207 vmcs_writel(GUEST_CR4
, hw_cr4
);
3209 if ((cr4
^ old_cr4
) & (X86_CR4_OSXSAVE
| X86_CR4_PKE
))
3210 kvm_update_cpuid_runtime(vcpu
);
3213 void vmx_get_segment(struct kvm_vcpu
*vcpu
, struct kvm_segment
*var
, int seg
)
3215 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3218 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3219 *var
= vmx
->rmode
.segs
[seg
];
3220 if (seg
== VCPU_SREG_TR
3221 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3223 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3224 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3227 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3228 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3229 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3230 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3231 var
->unusable
= (ar
>> 16) & 1;
3232 var
->type
= ar
& 15;
3233 var
->s
= (ar
>> 4) & 1;
3234 var
->dpl
= (ar
>> 5) & 3;
3236 * Some userspaces do not preserve unusable property. Since usable
3237 * segment has to be present according to VMX spec we can use present
3238 * property to amend userspace bug by making unusable segment always
3239 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3240 * segment as unusable.
3242 var
->present
= !var
->unusable
;
3243 var
->avl
= (ar
>> 12) & 1;
3244 var
->l
= (ar
>> 13) & 1;
3245 var
->db
= (ar
>> 14) & 1;
3246 var
->g
= (ar
>> 15) & 1;
3249 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3251 struct kvm_segment s
;
3253 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3254 vmx_get_segment(vcpu
, &s
, seg
);
3257 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3260 int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3264 if (unlikely(vmx
->rmode
.vm86_active
))
3267 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3268 return VMX_AR_DPL(ar
);
3272 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3276 if (var
->unusable
|| !var
->present
)
3279 ar
= var
->type
& 15;
3280 ar
|= (var
->s
& 1) << 4;
3281 ar
|= (var
->dpl
& 3) << 5;
3282 ar
|= (var
->present
& 1) << 7;
3283 ar
|= (var
->avl
& 1) << 12;
3284 ar
|= (var
->l
& 1) << 13;
3285 ar
|= (var
->db
& 1) << 14;
3286 ar
|= (var
->g
& 1) << 15;
3292 void __vmx_set_segment(struct kvm_vcpu
*vcpu
, struct kvm_segment
*var
, int seg
)
3294 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3295 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3297 vmx_segment_cache_clear(vmx
);
3299 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3300 vmx
->rmode
.segs
[seg
] = *var
;
3301 if (seg
== VCPU_SREG_TR
)
3302 vmcs_write16(sf
->selector
, var
->selector
);
3304 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3308 vmcs_writel(sf
->base
, var
->base
);
3309 vmcs_write32(sf
->limit
, var
->limit
);
3310 vmcs_write16(sf
->selector
, var
->selector
);
3313 * Fix the "Accessed" bit in AR field of segment registers for older
3315 * IA32 arch specifies that at the time of processor reset the
3316 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3317 * is setting it to 0 in the userland code. This causes invalid guest
3318 * state vmexit when "unrestricted guest" mode is turned on.
3319 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3320 * tree. Newer qemu binaries with that qemu fix would not need this
3323 if (is_unrestricted_guest(vcpu
) && (seg
!= VCPU_SREG_LDTR
))
3324 var
->type
|= 0x1; /* Accessed */
3326 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3329 static void vmx_set_segment(struct kvm_vcpu
*vcpu
, struct kvm_segment
*var
, int seg
)
3331 __vmx_set_segment(vcpu
, var
, seg
);
3333 to_vmx(vcpu
)->emulation_required
= vmx_emulation_required(vcpu
);
3336 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3338 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3340 *db
= (ar
>> 14) & 1;
3341 *l
= (ar
>> 13) & 1;
3344 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3346 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3347 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3350 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3352 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3353 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3356 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3358 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3359 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3362 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3364 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3365 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3368 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3370 struct kvm_segment var
;
3373 vmx_get_segment(vcpu
, &var
, seg
);
3375 if (seg
== VCPU_SREG_CS
)
3377 ar
= vmx_segment_access_rights(&var
);
3379 if (var
.base
!= (var
.selector
<< 4))
3381 if (var
.limit
!= 0xffff)
3389 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3391 struct kvm_segment cs
;
3392 unsigned int cs_rpl
;
3394 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3395 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3399 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3403 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3404 if (cs
.dpl
> cs_rpl
)
3407 if (cs
.dpl
!= cs_rpl
)
3413 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3417 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3419 struct kvm_segment ss
;
3420 unsigned int ss_rpl
;
3422 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3423 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
3427 if (ss
.type
!= 3 && ss
.type
!= 7)
3431 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3439 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3441 struct kvm_segment var
;
3444 vmx_get_segment(vcpu
, &var
, seg
);
3445 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
3453 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
3454 if (var
.dpl
< rpl
) /* DPL < RPL */
3458 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3464 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3466 struct kvm_segment tr
;
3468 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3472 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3474 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3482 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3484 struct kvm_segment ldtr
;
3486 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3490 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3500 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3502 struct kvm_segment cs
, ss
;
3504 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3505 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3507 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
3508 (ss
.selector
& SEGMENT_RPL_MASK
));
3512 * Check if guest state is valid. Returns true if valid, false if
3514 * We assume that registers are always usable
3516 bool __vmx_guest_state_valid(struct kvm_vcpu
*vcpu
)
3518 /* real mode guest state checks */
3519 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3520 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3522 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3524 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3526 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3528 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3530 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3533 /* protected mode guest state checks */
3534 if (!cs_ss_rpl_check(vcpu
))
3536 if (!code_segment_valid(vcpu
))
3538 if (!stack_segment_valid(vcpu
))
3540 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3542 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3544 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3546 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3548 if (!tr_valid(vcpu
))
3550 if (!ldtr_valid(vcpu
))
3554 * - Add checks on RIP
3555 * - Add checks on RFLAGS
3561 static int init_rmode_tss(struct kvm
*kvm
, void __user
*ua
)
3563 const void *zero_page
= (const void *) __va(page_to_phys(ZERO_PAGE(0)));
3567 for (i
= 0; i
< 3; i
++) {
3568 if (__copy_to_user(ua
+ PAGE_SIZE
* i
, zero_page
, PAGE_SIZE
))
3572 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3573 if (__copy_to_user(ua
+ TSS_IOPB_BASE_OFFSET
, &data
, sizeof(u16
)))
3577 if (__copy_to_user(ua
+ RMODE_TSS_SIZE
- 1, &data
, sizeof(u8
)))
3583 static int init_rmode_identity_map(struct kvm
*kvm
)
3585 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(kvm
);
3590 /* Protect kvm_vmx->ept_identity_pagetable_done. */
3591 mutex_lock(&kvm
->slots_lock
);
3593 if (likely(kvm_vmx
->ept_identity_pagetable_done
))
3596 if (!kvm_vmx
->ept_identity_map_addr
)
3597 kvm_vmx
->ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
3599 uaddr
= __x86_set_memory_region(kvm
,
3600 IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
3601 kvm_vmx
->ept_identity_map_addr
,
3603 if (IS_ERR(uaddr
)) {
3608 /* Set up identity-mapping pagetable for EPT in real mode */
3609 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3610 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3611 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3612 if (__copy_to_user(uaddr
+ i
* sizeof(tmp
), &tmp
, sizeof(tmp
))) {
3617 kvm_vmx
->ept_identity_pagetable_done
= true;
3620 mutex_unlock(&kvm
->slots_lock
);
3624 static void seg_setup(int seg
)
3626 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3629 vmcs_write16(sf
->selector
, 0);
3630 vmcs_writel(sf
->base
, 0);
3631 vmcs_write32(sf
->limit
, 0xffff);
3633 if (seg
== VCPU_SREG_CS
)
3634 ar
|= 0x08; /* code segment */
3636 vmcs_write32(sf
->ar_bytes
, ar
);
3639 static int alloc_apic_access_page(struct kvm
*kvm
)
3645 mutex_lock(&kvm
->slots_lock
);
3646 if (kvm
->arch
.apic_access_memslot_enabled
)
3648 hva
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
3649 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
3655 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
3656 if (is_error_page(page
)) {
3662 * Do not pin the page in memory, so that memory hot-unplug
3663 * is able to migrate it.
3666 kvm
->arch
.apic_access_memslot_enabled
= true;
3668 mutex_unlock(&kvm
->slots_lock
);
3672 int allocate_vpid(void)
3678 spin_lock(&vmx_vpid_lock
);
3679 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3680 if (vpid
< VMX_NR_VPIDS
)
3681 __set_bit(vpid
, vmx_vpid_bitmap
);
3684 spin_unlock(&vmx_vpid_lock
);
3688 void free_vpid(int vpid
)
3690 if (!enable_vpid
|| vpid
== 0)
3692 spin_lock(&vmx_vpid_lock
);
3693 __clear_bit(vpid
, vmx_vpid_bitmap
);
3694 spin_unlock(&vmx_vpid_lock
);
3697 void vmx_disable_intercept_for_msr(struct kvm_vcpu
*vcpu
, u32 msr
, int type
)
3699 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3700 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
3702 if (!cpu_has_vmx_msr_bitmap())
3705 if (static_branch_unlikely(&enable_evmcs
))
3706 evmcs_touch_msr_bitmap();
3709 * Mark the desired intercept state in shadow bitmap, this is needed
3710 * for resync when the MSR filters change.
3712 if (is_valid_passthrough_msr(msr
)) {
3713 int idx
= possible_passthrough_msr_slot(msr
);
3715 if (idx
!= -ENOENT
) {
3716 if (type
& MSR_TYPE_R
)
3717 clear_bit(idx
, vmx
->shadow_msr_intercept
.read
);
3718 if (type
& MSR_TYPE_W
)
3719 clear_bit(idx
, vmx
->shadow_msr_intercept
.write
);
3723 if ((type
& MSR_TYPE_R
) &&
3724 !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_READ
)) {
3725 vmx_set_msr_bitmap_read(msr_bitmap
, msr
);
3726 type
&= ~MSR_TYPE_R
;
3729 if ((type
& MSR_TYPE_W
) &&
3730 !kvm_msr_allowed(vcpu
, msr
, KVM_MSR_FILTER_WRITE
)) {
3731 vmx_set_msr_bitmap_write(msr_bitmap
, msr
);
3732 type
&= ~MSR_TYPE_W
;
3735 if (type
& MSR_TYPE_R
)
3736 vmx_clear_msr_bitmap_read(msr_bitmap
, msr
);
3738 if (type
& MSR_TYPE_W
)
3739 vmx_clear_msr_bitmap_write(msr_bitmap
, msr
);
3742 void vmx_enable_intercept_for_msr(struct kvm_vcpu
*vcpu
, u32 msr
, int type
)
3744 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3745 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
3747 if (!cpu_has_vmx_msr_bitmap())
3750 if (static_branch_unlikely(&enable_evmcs
))
3751 evmcs_touch_msr_bitmap();
3754 * Mark the desired intercept state in shadow bitmap, this is needed
3755 * for resync when the MSR filter changes.
3757 if (is_valid_passthrough_msr(msr
)) {
3758 int idx
= possible_passthrough_msr_slot(msr
);
3760 if (idx
!= -ENOENT
) {
3761 if (type
& MSR_TYPE_R
)
3762 set_bit(idx
, vmx
->shadow_msr_intercept
.read
);
3763 if (type
& MSR_TYPE_W
)
3764 set_bit(idx
, vmx
->shadow_msr_intercept
.write
);
3768 if (type
& MSR_TYPE_R
)
3769 vmx_set_msr_bitmap_read(msr_bitmap
, msr
);
3771 if (type
& MSR_TYPE_W
)
3772 vmx_set_msr_bitmap_write(msr_bitmap
, msr
);
3775 static void vmx_reset_x2apic_msrs(struct kvm_vcpu
*vcpu
, u8 mode
)
3777 unsigned long *msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
3778 unsigned long read_intercept
;
3781 read_intercept
= (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
3783 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
3784 unsigned int read_idx
= msr
/ BITS_PER_LONG
;
3785 unsigned int write_idx
= read_idx
+ (0x800 / sizeof(long));
3787 msr_bitmap
[read_idx
] = read_intercept
;
3788 msr_bitmap
[write_idx
] = ~0ul;
3792 static void vmx_update_msr_bitmap_x2apic(struct kvm_vcpu
*vcpu
)
3794 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3797 if (!cpu_has_vmx_msr_bitmap())
3800 if (cpu_has_secondary_exec_ctrls() &&
3801 (secondary_exec_controls_get(vmx
) &
3802 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
3803 mode
= MSR_BITMAP_MODE_X2APIC
;
3804 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
3805 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
3810 if (mode
== vmx
->x2apic_msr_bitmap_mode
)
3813 vmx
->x2apic_msr_bitmap_mode
= mode
;
3815 vmx_reset_x2apic_msrs(vcpu
, mode
);
3818 * TPR reads and writes can be virtualized even if virtual interrupt
3819 * delivery is not in use.
3821 vmx_set_intercept_for_msr(vcpu
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
,
3822 !(mode
& MSR_BITMAP_MODE_X2APIC
));
3824 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
3825 vmx_enable_intercept_for_msr(vcpu
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_RW
);
3826 vmx_disable_intercept_for_msr(vcpu
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
3827 vmx_disable_intercept_for_msr(vcpu
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
3831 void pt_update_intercept_for_msr(struct kvm_vcpu
*vcpu
)
3833 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3834 bool flag
= !(vmx
->pt_desc
.guest
.ctl
& RTIT_CTL_TRACEEN
);
3837 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_STATUS
, MSR_TYPE_RW
, flag
);
3838 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_OUTPUT_BASE
, MSR_TYPE_RW
, flag
);
3839 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_OUTPUT_MASK
, MSR_TYPE_RW
, flag
);
3840 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_CR3_MATCH
, MSR_TYPE_RW
, flag
);
3841 for (i
= 0; i
< vmx
->pt_desc
.addr_range
; i
++) {
3842 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_ADDR0_A
+ i
* 2, MSR_TYPE_RW
, flag
);
3843 vmx_set_intercept_for_msr(vcpu
, MSR_IA32_RTIT_ADDR0_B
+ i
* 2, MSR_TYPE_RW
, flag
);
3847 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu
*vcpu
)
3849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3854 if (WARN_ON_ONCE(!is_guest_mode(vcpu
)) ||
3855 !nested_cpu_has_vid(get_vmcs12(vcpu
)) ||
3856 WARN_ON_ONCE(!vmx
->nested
.virtual_apic_map
.gfn
))
3859 rvi
= vmx_get_rvi();
3861 vapic_page
= vmx
->nested
.virtual_apic_map
.hva
;
3862 vppr
= *((u32
*)(vapic_page
+ APIC_PROCPRI
));
3864 return ((rvi
& 0xf0) > (vppr
& 0xf0));
3867 static void vmx_msr_filter_changed(struct kvm_vcpu
*vcpu
)
3869 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3873 * Set intercept permissions for all potentially passed through MSRs
3874 * again. They will automatically get filtered through the MSR filter,
3875 * so we are back in sync after this.
3877 for (i
= 0; i
< ARRAY_SIZE(vmx_possible_passthrough_msrs
); i
++) {
3878 u32 msr
= vmx_possible_passthrough_msrs
[i
];
3879 bool read
= test_bit(i
, vmx
->shadow_msr_intercept
.read
);
3880 bool write
= test_bit(i
, vmx
->shadow_msr_intercept
.write
);
3882 vmx_set_intercept_for_msr(vcpu
, msr
, MSR_TYPE_R
, read
);
3883 vmx_set_intercept_for_msr(vcpu
, msr
, MSR_TYPE_W
, write
);
3886 pt_update_intercept_for_msr(vcpu
);
3889 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
3893 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
3895 if (vcpu
->mode
== IN_GUEST_MODE
) {
3897 * The vector of interrupt to be delivered to vcpu had
3898 * been set in PIR before this function.
3900 * Following cases will be reached in this block, and
3901 * we always send a notification event in all cases as
3904 * Case 1: vcpu keeps in non-root mode. Sending a
3905 * notification event posts the interrupt to vcpu.
3907 * Case 2: vcpu exits to root mode and is still
3908 * runnable. PIR will be synced to vIRR before the
3909 * next vcpu entry. Sending a notification event in
3910 * this case has no effect, as vcpu is not in root
3913 * Case 3: vcpu exits to root mode and is blocked.
3914 * vcpu_block() has already synced PIR to vIRR and
3915 * never blocks vcpu if vIRR is not cleared. Therefore,
3916 * a blocked vcpu here does not wait for any requested
3917 * interrupts in PIR, and sending a notification event
3918 * which has no effect is safe here.
3921 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
3928 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
3931 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3933 if (is_guest_mode(vcpu
) &&
3934 vector
== vmx
->nested
.posted_intr_nv
) {
3936 * If a posted intr is not recognized by hardware,
3937 * we will accomplish it in the next vmentry.
3939 vmx
->nested
.pi_pending
= true;
3940 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3941 /* the PIR and ON have been set by L1. */
3942 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
3943 kvm_vcpu_kick(vcpu
);
3949 * Send interrupt to vcpu via posted interrupt way.
3950 * 1. If target vcpu is running(non-root mode), send posted interrupt
3951 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3952 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3953 * interrupt from PIR in next vmentry.
3955 static int vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
3957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3960 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
3964 if (!vcpu
->arch
.apicv_active
)
3967 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
3970 /* If a previous notification has sent the IPI, nothing to do. */
3971 if (pi_test_and_set_on(&vmx
->pi_desc
))
3974 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
3975 kvm_vcpu_kick(vcpu
);
3981 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3982 * will not change in the lifetime of the guest.
3983 * Note that host-state that does change is set elsewhere. E.g., host-state
3984 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3986 void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
3990 unsigned long cr0
, cr3
, cr4
;
3993 WARN_ON(cr0
& X86_CR0_TS
);
3994 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
3997 * Save the most likely value for this task's CR3 in the VMCS.
3998 * We can't use __get_current_cr3_fast() because we're not atomic.
4001 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
4002 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
4004 /* Save the most likely value for this task's CR4 in the VMCS. */
4005 cr4
= cr4_read_shadow();
4006 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4007 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
4009 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4010 #ifdef CONFIG_X86_64
4012 * Load null selectors, so we can avoid reloading them in
4013 * vmx_prepare_switch_to_host(), in case userspace uses
4014 * the null selectors too (the expected case).
4016 vmcs_write16(HOST_DS_SELECTOR
, 0);
4017 vmcs_write16(HOST_ES_SELECTOR
, 0);
4019 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4020 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4022 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4023 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4025 vmcs_writel(HOST_IDTR_BASE
, host_idt_base
); /* 22.2.4 */
4027 vmcs_writel(HOST_RIP
, (unsigned long)vmx_vmexit
); /* 22.2.5 */
4029 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4030 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4031 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4032 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4034 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4035 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4036 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4039 if (cpu_has_load_ia32_efer())
4040 vmcs_write64(HOST_IA32_EFER
, host_efer
);
4043 void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4045 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
4047 vcpu
->arch
.cr4_guest_owned_bits
= KVM_POSSIBLE_CR4_GUEST_BITS
&
4048 ~vcpu
->arch
.cr4_guest_rsvd_bits
;
4050 vcpu
->arch
.cr4_guest_owned_bits
&= ~X86_CR4_PGE
;
4051 if (is_guest_mode(&vmx
->vcpu
))
4052 vcpu
->arch
.cr4_guest_owned_bits
&=
4053 ~get_vmcs12(vcpu
)->cr4_guest_host_mask
;
4054 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vcpu
->arch
.cr4_guest_owned_bits
);
4057 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4059 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4061 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4062 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4065 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
4067 if (!enable_preemption_timer
)
4068 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4070 return pin_based_exec_ctrl
;
4073 static u32
vmx_vmentry_ctrl(void)
4075 u32 vmentry_ctrl
= vmcs_config
.vmentry_ctrl
;
4077 if (vmx_pt_mode_is_system())
4078 vmentry_ctrl
&= ~(VM_ENTRY_PT_CONCEAL_PIP
|
4079 VM_ENTRY_LOAD_IA32_RTIT_CTL
);
4080 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4081 return vmentry_ctrl
&
4082 ~(VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
| VM_ENTRY_LOAD_IA32_EFER
);
4085 static u32
vmx_vmexit_ctrl(void)
4087 u32 vmexit_ctrl
= vmcs_config
.vmexit_ctrl
;
4089 if (vmx_pt_mode_is_system())
4090 vmexit_ctrl
&= ~(VM_EXIT_PT_CONCEAL_PIP
|
4091 VM_EXIT_CLEAR_IA32_RTIT_CTL
);
4092 /* Loading of EFER and PERF_GLOBAL_CTRL are toggled dynamically */
4093 return vmexit_ctrl
&
4094 ~(VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
| VM_EXIT_LOAD_IA32_EFER
);
4097 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4099 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4101 pin_controls_set(vmx
, vmx_pin_based_exec_ctrl(vmx
));
4102 if (cpu_has_secondary_exec_ctrls()) {
4103 if (kvm_vcpu_apicv_active(vcpu
))
4104 secondary_exec_controls_setbit(vmx
,
4105 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4106 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4108 secondary_exec_controls_clearbit(vmx
,
4109 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4110 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4113 vmx_update_msr_bitmap_x2apic(vcpu
);
4116 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4118 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4120 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4121 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4123 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4124 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4125 #ifdef CONFIG_X86_64
4126 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4127 CPU_BASED_CR8_LOAD_EXITING
;
4131 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4132 CPU_BASED_CR3_LOAD_EXITING
|
4133 CPU_BASED_INVLPG_EXITING
;
4134 if (kvm_mwait_in_guest(vmx
->vcpu
.kvm
))
4135 exec_control
&= ~(CPU_BASED_MWAIT_EXITING
|
4136 CPU_BASED_MONITOR_EXITING
);
4137 if (kvm_hlt_in_guest(vmx
->vcpu
.kvm
))
4138 exec_control
&= ~CPU_BASED_HLT_EXITING
;
4139 return exec_control
;
4143 * Adjust a single secondary execution control bit to intercept/allow an
4144 * instruction in the guest. This is usually done based on whether or not a
4145 * feature has been exposed to the guest in order to correctly emulate faults.
4148 vmx_adjust_secondary_exec_control(struct vcpu_vmx
*vmx
, u32
*exec_control
,
4149 u32 control
, bool enabled
, bool exiting
)
4152 * If the control is for an opt-in feature, clear the control if the
4153 * feature is not exposed to the guest, i.e. not enabled. If the
4154 * control is opt-out, i.e. an exiting control, clear the control if
4155 * the feature _is_ exposed to the guest, i.e. exiting/interception is
4156 * disabled for the associated instruction. Note, the caller is
4157 * responsible presetting exec_control to set all supported bits.
4159 if (enabled
== exiting
)
4160 *exec_control
&= ~control
;
4163 * Update the nested MSR settings so that a nested VMM can/can't set
4164 * controls for features that are/aren't exposed to the guest.
4168 vmx
->nested
.msrs
.secondary_ctls_high
|= control
;
4170 vmx
->nested
.msrs
.secondary_ctls_high
&= ~control
;
4175 * Wrapper macro for the common case of adjusting a secondary execution control
4176 * based on a single guest CPUID bit, with a dedicated feature bit. This also
4177 * verifies that the control is actually supported by KVM and hardware.
4179 #define vmx_adjust_sec_exec_control(vmx, exec_control, name, feat_name, ctrl_name, exiting) \
4183 if (cpu_has_vmx_##name()) { \
4184 __enabled = guest_cpuid_has(&(vmx)->vcpu, \
4185 X86_FEATURE_##feat_name); \
4186 vmx_adjust_secondary_exec_control(vmx, exec_control, \
4187 SECONDARY_EXEC_##ctrl_name, __enabled, exiting); \
4191 /* More macro magic for ENABLE_/opt-in versus _EXITING/opt-out controls. */
4192 #define vmx_adjust_sec_exec_feature(vmx, exec_control, lname, uname) \
4193 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, ENABLE_##uname, false)
4195 #define vmx_adjust_sec_exec_exiting(vmx, exec_control, lname, uname) \
4196 vmx_adjust_sec_exec_control(vmx, exec_control, lname, uname, uname##_EXITING, true)
4198 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4200 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
4202 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4204 if (vmx_pt_mode_is_system())
4205 exec_control
&= ~(SECONDARY_EXEC_PT_USE_GPA
| SECONDARY_EXEC_PT_CONCEAL_VMX
);
4206 if (!cpu_need_virtualize_apic_accesses(vcpu
))
4207 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4209 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4211 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4212 enable_unrestricted_guest
= 0;
4214 if (!enable_unrestricted_guest
)
4215 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4216 if (kvm_pause_in_guest(vmx
->vcpu
.kvm
))
4217 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4218 if (!kvm_vcpu_apicv_active(vcpu
))
4219 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4220 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4221 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4223 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
4224 * in vmx_set_cr4. */
4225 exec_control
&= ~SECONDARY_EXEC_DESC
;
4227 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4229 We can NOT enable shadow_vmcs here because we don't have yet
4232 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4235 * PML is enabled/disabled when dirty logging of memsmlots changes, but
4236 * it needs to be set here when dirty logging is already active, e.g.
4237 * if this vCPU was created after dirty logging was enabled.
4239 if (!vcpu
->kvm
->arch
.cpu_dirty_logging_count
)
4240 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4242 if (cpu_has_vmx_xsaves()) {
4243 /* Exposing XSAVES only when XSAVE is exposed */
4244 bool xsaves_enabled
=
4245 boot_cpu_has(X86_FEATURE_XSAVE
) &&
4246 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
4247 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
4249 vcpu
->arch
.xsaves_enabled
= xsaves_enabled
;
4251 vmx_adjust_secondary_exec_control(vmx
, &exec_control
,
4252 SECONDARY_EXEC_XSAVES
,
4253 xsaves_enabled
, false);
4257 * RDPID is also gated by ENABLE_RDTSCP, turn on the control if either
4258 * feature is exposed to the guest. This creates a virtualization hole
4259 * if both are supported in hardware but only one is exposed to the
4260 * guest, but letting the guest execute RDTSCP or RDPID when either one
4261 * is advertised is preferable to emulating the advertised instruction
4262 * in KVM on #UD, and obviously better than incorrectly injecting #UD.
4264 if (cpu_has_vmx_rdtscp()) {
4265 bool rdpid_or_rdtscp_enabled
=
4266 guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
) ||
4267 guest_cpuid_has(vcpu
, X86_FEATURE_RDPID
);
4269 vmx_adjust_secondary_exec_control(vmx
, &exec_control
,
4270 SECONDARY_EXEC_ENABLE_RDTSCP
,
4271 rdpid_or_rdtscp_enabled
, false);
4273 vmx_adjust_sec_exec_feature(vmx
, &exec_control
, invpcid
, INVPCID
);
4275 vmx_adjust_sec_exec_exiting(vmx
, &exec_control
, rdrand
, RDRAND
);
4276 vmx_adjust_sec_exec_exiting(vmx
, &exec_control
, rdseed
, RDSEED
);
4278 vmx_adjust_sec_exec_control(vmx
, &exec_control
, waitpkg
, WAITPKG
,
4279 ENABLE_USR_WAIT_PAUSE
, false);
4281 if (!vcpu
->kvm
->arch
.bus_lock_detection_enabled
)
4282 exec_control
&= ~SECONDARY_EXEC_BUS_LOCK_DETECTION
;
4284 return exec_control
;
4287 #define VMX_XSS_EXIT_BITMAP 0
4290 * Noting that the initialization of Guest-state Area of VMCS is in
4293 static void init_vmcs(struct vcpu_vmx
*vmx
)
4296 nested_vmx_set_vmcs_shadowing_bitmap();
4298 if (cpu_has_vmx_msr_bitmap())
4299 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
4301 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4304 pin_controls_set(vmx
, vmx_pin_based_exec_ctrl(vmx
));
4306 exec_controls_set(vmx
, vmx_exec_control(vmx
));
4308 if (cpu_has_secondary_exec_ctrls())
4309 secondary_exec_controls_set(vmx
, vmx_secondary_exec_control(vmx
));
4311 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
4312 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4313 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4314 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4315 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4317 vmcs_write16(GUEST_INTR_STATUS
, 0);
4319 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4320 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4323 if (!kvm_pause_in_guest(vmx
->vcpu
.kvm
)) {
4324 vmcs_write32(PLE_GAP
, ple_gap
);
4325 vmx
->ple_window
= ple_window
;
4326 vmx
->ple_window_dirty
= true;
4329 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4330 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4331 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4333 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4334 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4335 vmx_set_constant_host_state(vmx
);
4336 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4337 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4339 if (cpu_has_vmx_vmfunc())
4340 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
4342 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4343 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4344 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
.val
));
4345 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4346 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
.val
));
4348 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4349 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4351 vm_exit_controls_set(vmx
, vmx_vmexit_ctrl());
4353 /* 22.2.1, 20.8.1 */
4354 vm_entry_controls_set(vmx
, vmx_vmentry_ctrl());
4356 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= KVM_POSSIBLE_CR0_GUEST_BITS
;
4357 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr0_guest_owned_bits
);
4359 set_cr4_guest_host_mask(vmx
);
4362 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4364 if (cpu_has_vmx_xsaves())
4365 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4368 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
4369 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
4372 vmx_write_encls_bitmap(&vmx
->vcpu
, NULL
);
4374 if (vmx_pt_mode_is_host_guest()) {
4375 memset(&vmx
->pt_desc
, 0, sizeof(vmx
->pt_desc
));
4376 /* Bit[6~0] are forced to 1, writes are ignored. */
4377 vmx
->pt_desc
.guest
.output_mask
= 0x7F;
4378 vmcs_write64(GUEST_IA32_RTIT_CTL
, 0);
4381 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4382 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4383 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4384 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4386 if (cpu_has_vmx_tpr_shadow()) {
4387 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4388 if (cpu_need_tpr_shadow(&vmx
->vcpu
))
4389 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4390 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4391 vmcs_write32(TPR_THRESHOLD
, 0);
4394 vmx_setup_uret_msrs(vmx
);
4397 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4399 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4401 vmx
->rmode
.vm86_active
= 0;
4404 vmx
->msr_ia32_umwait_control
= 0;
4406 vmx
->hv_deadline_tsc
= -1;
4407 kvm_set_cr8(vcpu
, 0);
4409 vmx_segment_cache_clear(vmx
);
4411 seg_setup(VCPU_SREG_CS
);
4412 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4413 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
4415 seg_setup(VCPU_SREG_DS
);
4416 seg_setup(VCPU_SREG_ES
);
4417 seg_setup(VCPU_SREG_FS
);
4418 seg_setup(VCPU_SREG_GS
);
4419 seg_setup(VCPU_SREG_SS
);
4421 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4422 vmcs_writel(GUEST_TR_BASE
, 0);
4423 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4424 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4426 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4427 vmcs_writel(GUEST_LDTR_BASE
, 0);
4428 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4429 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4431 vmcs_writel(GUEST_GDTR_BASE
, 0);
4432 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4434 vmcs_writel(GUEST_IDTR_BASE
, 0);
4435 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4437 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4438 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4439 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4440 if (kvm_mpx_supported())
4441 vmcs_write64(GUEST_BNDCFGS
, 0);
4443 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4445 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4447 vpid_sync_context(vmx
->vpid
);
4450 static void vmx_enable_irq_window(struct kvm_vcpu
*vcpu
)
4452 exec_controls_setbit(to_vmx(vcpu
), CPU_BASED_INTR_WINDOW_EXITING
);
4455 static void vmx_enable_nmi_window(struct kvm_vcpu
*vcpu
)
4458 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4459 vmx_enable_irq_window(vcpu
);
4463 exec_controls_setbit(to_vmx(vcpu
), CPU_BASED_NMI_WINDOW_EXITING
);
4466 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4470 int irq
= vcpu
->arch
.interrupt
.nr
;
4472 trace_kvm_inj_virq(irq
);
4474 ++vcpu
->stat
.irq_injections
;
4475 if (vmx
->rmode
.vm86_active
) {
4477 if (vcpu
->arch
.interrupt
.soft
)
4478 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4479 kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
);
4482 intr
= irq
| INTR_INFO_VALID_MASK
;
4483 if (vcpu
->arch
.interrupt
.soft
) {
4484 intr
|= INTR_TYPE_SOFT_INTR
;
4485 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4486 vmx
->vcpu
.arch
.event_exit_inst_len
);
4488 intr
|= INTR_TYPE_EXT_INTR
;
4489 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4491 vmx_clear_hlt(vcpu
);
4494 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4496 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4500 * Tracking the NMI-blocked state in software is built upon
4501 * finding the next open IRQ window. This, in turn, depends on
4502 * well-behaving guests: They have to keep IRQs disabled at
4503 * least as long as the NMI handler runs. Otherwise we may
4504 * cause NMI nesting, maybe breaking the guest. But as this is
4505 * highly unlikely, we can live with the residual risk.
4507 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
4508 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
4511 ++vcpu
->stat
.nmi_injections
;
4512 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
4514 if (vmx
->rmode
.vm86_active
) {
4515 kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0);
4519 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4520 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4522 vmx_clear_hlt(vcpu
);
4525 bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4527 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4531 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
4532 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
4534 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4535 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
4539 void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4544 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
4545 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
4546 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
4549 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
4551 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4552 GUEST_INTR_STATE_NMI
);
4554 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4555 GUEST_INTR_STATE_NMI
);
4559 bool vmx_nmi_blocked(struct kvm_vcpu
*vcpu
)
4561 if (is_guest_mode(vcpu
) && nested_exit_on_nmi(vcpu
))
4564 if (!enable_vnmi
&& to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
4567 return (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4568 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
|
4569 GUEST_INTR_STATE_NMI
));
4572 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
4574 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4577 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
4578 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_nmi(vcpu
))
4581 return !vmx_nmi_blocked(vcpu
);
4584 bool vmx_interrupt_blocked(struct kvm_vcpu
*vcpu
)
4586 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4589 return !(vmx_get_rflags(vcpu
) & X86_EFLAGS_IF
) ||
4590 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4591 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4594 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
4596 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4600 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
4601 * e.g. if the IRQ arrived asynchronously after checking nested events.
4603 if (for_injection
&& is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4606 return !vmx_interrupt_blocked(vcpu
);
4609 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4613 if (enable_unrestricted_guest
)
4616 mutex_lock(&kvm
->slots_lock
);
4617 ret
= __x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
4619 mutex_unlock(&kvm
->slots_lock
);
4622 return PTR_ERR(ret
);
4624 to_kvm_vmx(kvm
)->tss_addr
= addr
;
4626 return init_rmode_tss(kvm
, ret
);
4629 static int vmx_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
4631 to_kvm_vmx(kvm
)->ept_identity_map_addr
= ident_addr
;
4635 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4640 * Update instruction length as we may reinject the exception
4641 * from user space while in guest debugging mode.
4643 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4644 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4645 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4649 return !(vcpu
->guest_debug
&
4650 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
));
4664 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4665 int vec
, u32 err_code
)
4668 * Instruction with address size override prefix opcode 0x67
4669 * Cause the #SS fault with 0 error code in VM86 mode.
4671 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4672 if (kvm_emulate_instruction(vcpu
, 0)) {
4673 if (vcpu
->arch
.halt_request
) {
4674 vcpu
->arch
.halt_request
= 0;
4675 return kvm_vcpu_halt(vcpu
);
4683 * Forward all other exceptions that are valid in real mode.
4684 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4685 * the required debugging infrastructure rework.
4687 kvm_queue_exception(vcpu
, vec
);
4691 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4693 /* handled by vmx_vcpu_run() */
4698 * If the host has split lock detection disabled, then #AC is
4699 * unconditionally injected into the guest, which is the pre split lock
4700 * detection behaviour.
4702 * If the host has split lock detection enabled then #AC is
4703 * only injected into the guest when:
4704 * - Guest CPL == 3 (user mode)
4705 * - Guest has #AC detection enabled in CR0
4706 * - Guest EFLAGS has AC bit set
4708 bool vmx_guest_inject_ac(struct kvm_vcpu
*vcpu
)
4710 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT
))
4713 return vmx_get_cpl(vcpu
) == 3 && kvm_read_cr0_bits(vcpu
, X86_CR0_AM
) &&
4714 (kvm_get_rflags(vcpu
) & X86_EFLAGS_AC
);
4717 static int handle_exception_nmi(struct kvm_vcpu
*vcpu
)
4719 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4720 struct kvm_run
*kvm_run
= vcpu
->run
;
4721 u32 intr_info
, ex_no
, error_code
;
4722 unsigned long cr2
, dr6
;
4725 vect_info
= vmx
->idt_vectoring_info
;
4726 intr_info
= vmx_get_intr_info(vcpu
);
4728 if (is_machine_check(intr_info
) || is_nmi(intr_info
))
4729 return 1; /* handled by handle_exception_nmi_irqoff() */
4731 if (is_invalid_opcode(intr_info
))
4732 return handle_ud(vcpu
);
4735 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4736 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4738 if (!vmx
->rmode
.vm86_active
&& is_gp_fault(intr_info
)) {
4739 WARN_ON_ONCE(!enable_vmware_backdoor
);
4742 * VMware backdoor emulation on #GP interception only handles
4743 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero
4744 * error code on #GP.
4747 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
4750 return kvm_emulate_instruction(vcpu
, EMULTYPE_VMWARE_GP
);
4754 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4755 * MMIO, it is better to report an internal error.
4756 * See the comments in vmx_handle_exit.
4758 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4759 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4760 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4761 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4762 vcpu
->run
->internal
.ndata
= 4;
4763 vcpu
->run
->internal
.data
[0] = vect_info
;
4764 vcpu
->run
->internal
.data
[1] = intr_info
;
4765 vcpu
->run
->internal
.data
[2] = error_code
;
4766 vcpu
->run
->internal
.data
[3] = vcpu
->arch
.last_vmentry_cpu
;
4770 if (is_page_fault(intr_info
)) {
4771 cr2
= vmx_get_exit_qual(vcpu
);
4772 if (enable_ept
&& !vcpu
->arch
.apf
.host_apf_flags
) {
4774 * EPT will cause page fault only if we need to
4775 * detect illegal GPAs.
4777 WARN_ON_ONCE(!allow_smaller_maxphyaddr
);
4778 kvm_fixup_and_inject_pf_error(vcpu
, cr2
, error_code
);
4781 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
4784 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4786 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4787 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4791 dr6
= vmx_get_exit_qual(vcpu
);
4792 if (!(vcpu
->guest_debug
&
4793 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4795 * If the #DB was due to ICEBP, a.k.a. INT1, skip the
4796 * instruction. ICEBP generates a trap-like #DB, but
4797 * despite its interception control being tied to #DB,
4798 * is an instruction intercept, i.e. the VM-Exit occurs
4799 * on the ICEBP itself. Note, skipping ICEBP also
4800 * clears STI and MOVSS blocking.
4802 * For all other #DBs, set vmcs.PENDING_DBG_EXCEPTIONS.BS
4803 * if single-step is enabled in RFLAGS and STI or MOVSS
4804 * blocking is active, as the CPU doesn't set the bit
4805 * on VM-Exit due to #DB interception. VM-Entry has a
4806 * consistency check that a single-step #DB is pending
4807 * in this scenario as the previous instruction cannot
4808 * have toggled RFLAGS.TF 0=>1 (because STI and POP/MOV
4809 * don't modify RFLAGS), therefore the one instruction
4810 * delay when activating single-step breakpoints must
4811 * have already expired. Note, the CPU sets/clears BS
4812 * as appropriate for all other VM-Exits types.
4814 if (is_icebp(intr_info
))
4815 WARN_ON(!skip_emulated_instruction(vcpu
));
4816 else if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_TF
) &&
4817 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4818 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
)))
4819 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
4820 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
) | DR6_BS
);
4822 kvm_queue_exception_p(vcpu
, DB_VECTOR
, dr6
);
4825 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_ACTIVE_LOW
;
4826 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4830 * Update instruction length as we may reinject #BP from
4831 * user space while in guest debugging mode. Reading it for
4832 * #DB as well causes no harm, it is not used in that case.
4834 vmx
->vcpu
.arch
.event_exit_inst_len
=
4835 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4836 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4837 kvm_run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
4838 kvm_run
->debug
.arch
.exception
= ex_no
;
4841 if (vmx_guest_inject_ac(vcpu
)) {
4842 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
4847 * Handle split lock. Depending on detection mode this will
4848 * either warn and disable split lock detection for this
4849 * task or force SIGBUS on it.
4851 if (handle_guest_split_lock(kvm_rip_read(vcpu
)))
4855 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4856 kvm_run
->ex
.exception
= ex_no
;
4857 kvm_run
->ex
.error_code
= error_code
;
4863 static __always_inline
int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4865 ++vcpu
->stat
.irq_exits
;
4869 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4871 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4872 vcpu
->mmio_needed
= 0;
4876 static int handle_io(struct kvm_vcpu
*vcpu
)
4878 unsigned long exit_qualification
;
4879 int size
, in
, string
;
4882 exit_qualification
= vmx_get_exit_qual(vcpu
);
4883 string
= (exit_qualification
& 16) != 0;
4885 ++vcpu
->stat
.io_exits
;
4888 return kvm_emulate_instruction(vcpu
, 0);
4890 port
= exit_qualification
>> 16;
4891 size
= (exit_qualification
& 7) + 1;
4892 in
= (exit_qualification
& 8) != 0;
4894 return kvm_fast_pio(vcpu
, size
, port
, in
);
4898 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4901 * Patch in the VMCALL instruction:
4903 hypercall
[0] = 0x0f;
4904 hypercall
[1] = 0x01;
4905 hypercall
[2] = 0xc1;
4908 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4909 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4911 if (is_guest_mode(vcpu
)) {
4912 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4913 unsigned long orig_val
= val
;
4916 * We get here when L2 changed cr0 in a way that did not change
4917 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4918 * but did change L0 shadowed bits. So we first calculate the
4919 * effective cr0 value that L1 would like to write into the
4920 * hardware. It consists of the L2-owned bits from the new
4921 * value combined with the L1-owned bits from L1's guest_cr0.
4923 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4924 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4926 if (!nested_guest_cr0_valid(vcpu
, val
))
4929 if (kvm_set_cr0(vcpu
, val
))
4931 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4934 if (to_vmx(vcpu
)->nested
.vmxon
&&
4935 !nested_host_cr0_valid(vcpu
, val
))
4938 return kvm_set_cr0(vcpu
, val
);
4942 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4944 if (is_guest_mode(vcpu
)) {
4945 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4946 unsigned long orig_val
= val
;
4948 /* analogously to handle_set_cr0 */
4949 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4950 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4951 if (kvm_set_cr4(vcpu
, val
))
4953 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4956 return kvm_set_cr4(vcpu
, val
);
4959 static int handle_desc(struct kvm_vcpu
*vcpu
)
4961 WARN_ON(!(vcpu
->arch
.cr4
& X86_CR4_UMIP
));
4962 return kvm_emulate_instruction(vcpu
, 0);
4965 static int handle_cr(struct kvm_vcpu
*vcpu
)
4967 unsigned long exit_qualification
, val
;
4973 exit_qualification
= vmx_get_exit_qual(vcpu
);
4974 cr
= exit_qualification
& 15;
4975 reg
= (exit_qualification
>> 8) & 15;
4976 switch ((exit_qualification
>> 4) & 3) {
4977 case 0: /* mov to cr */
4978 val
= kvm_register_read(vcpu
, reg
);
4979 trace_kvm_cr_write(cr
, val
);
4982 err
= handle_set_cr0(vcpu
, val
);
4983 return kvm_complete_insn_gp(vcpu
, err
);
4985 WARN_ON_ONCE(enable_unrestricted_guest
);
4987 err
= kvm_set_cr3(vcpu
, val
);
4988 return kvm_complete_insn_gp(vcpu
, err
);
4990 err
= handle_set_cr4(vcpu
, val
);
4991 return kvm_complete_insn_gp(vcpu
, err
);
4993 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4995 err
= kvm_set_cr8(vcpu
, cr8
);
4996 ret
= kvm_complete_insn_gp(vcpu
, err
);
4997 if (lapic_in_kernel(vcpu
))
4999 if (cr8_prev
<= cr8
)
5002 * TODO: we might be squashing a
5003 * KVM_GUESTDBG_SINGLESTEP-triggered
5004 * KVM_EXIT_DEBUG here.
5006 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5012 KVM_BUG(1, vcpu
->kvm
, "Guest always owns CR0.TS");
5014 case 1: /*mov from cr*/
5017 WARN_ON_ONCE(enable_unrestricted_guest
);
5019 val
= kvm_read_cr3(vcpu
);
5020 kvm_register_write(vcpu
, reg
, val
);
5021 trace_kvm_cr_read(cr
, val
);
5022 return kvm_skip_emulated_instruction(vcpu
);
5024 val
= kvm_get_cr8(vcpu
);
5025 kvm_register_write(vcpu
, reg
, val
);
5026 trace_kvm_cr_read(cr
, val
);
5027 return kvm_skip_emulated_instruction(vcpu
);
5031 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5032 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5033 kvm_lmsw(vcpu
, val
);
5035 return kvm_skip_emulated_instruction(vcpu
);
5039 vcpu
->run
->exit_reason
= 0;
5040 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5041 (int)(exit_qualification
>> 4) & 3, cr
);
5045 static int handle_dr(struct kvm_vcpu
*vcpu
)
5047 unsigned long exit_qualification
;
5051 exit_qualification
= vmx_get_exit_qual(vcpu
);
5052 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5054 /* First, if DR does not exist, trigger UD */
5055 if (!kvm_require_dr(vcpu
, dr
))
5058 if (kvm_x86_ops
.get_cpl(vcpu
) > 0)
5061 dr7
= vmcs_readl(GUEST_DR7
);
5064 * As the vm-exit takes precedence over the debug trap, we
5065 * need to emulate the latter, either for the host or the
5066 * guest debugging itself.
5068 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5069 vcpu
->run
->debug
.arch
.dr6
= DR6_BD
| DR6_ACTIVE_LOW
;
5070 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5071 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5072 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5073 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5076 kvm_queue_exception_p(vcpu
, DB_VECTOR
, DR6_BD
);
5081 if (vcpu
->guest_debug
== 0) {
5082 exec_controls_clearbit(to_vmx(vcpu
), CPU_BASED_MOV_DR_EXITING
);
5085 * No more DR vmexits; force a reload of the debug registers
5086 * and reenter on this instruction. The next vmexit will
5087 * retrieve the full state of the debug registers.
5089 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5093 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5094 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5097 kvm_get_dr(vcpu
, dr
, &val
);
5098 kvm_register_write(vcpu
, reg
, val
);
5101 err
= kvm_set_dr(vcpu
, dr
, kvm_register_read(vcpu
, reg
));
5105 return kvm_complete_insn_gp(vcpu
, err
);
5108 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5110 get_debugreg(vcpu
->arch
.db
[0], 0);
5111 get_debugreg(vcpu
->arch
.db
[1], 1);
5112 get_debugreg(vcpu
->arch
.db
[2], 2);
5113 get_debugreg(vcpu
->arch
.db
[3], 3);
5114 get_debugreg(vcpu
->arch
.dr6
, 6);
5115 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5117 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5118 exec_controls_setbit(to_vmx(vcpu
), CPU_BASED_MOV_DR_EXITING
);
5121 * exc_debug expects dr6 to be cleared after it runs, avoid that it sees
5122 * a stale dr6 from the guest.
5124 set_debugreg(DR6_RESERVED
, 6);
5127 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5129 vmcs_writel(GUEST_DR7
, val
);
5132 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5134 kvm_apic_update_ppr(vcpu
);
5138 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5140 exec_controls_clearbit(to_vmx(vcpu
), CPU_BASED_INTR_WINDOW_EXITING
);
5142 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5144 ++vcpu
->stat
.irq_window_exits
;
5148 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5150 unsigned long exit_qualification
= vmx_get_exit_qual(vcpu
);
5152 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5153 return kvm_skip_emulated_instruction(vcpu
);
5156 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5158 if (likely(fasteoi
)) {
5159 unsigned long exit_qualification
= vmx_get_exit_qual(vcpu
);
5160 int access_type
, offset
;
5162 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5163 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5165 * Sane guest uses MOV to write EOI, with written value
5166 * not cared. So make a short-circuit here by avoiding
5167 * heavy instruction emulation.
5169 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5170 (offset
== APIC_EOI
)) {
5171 kvm_lapic_set_eoi(vcpu
);
5172 return kvm_skip_emulated_instruction(vcpu
);
5175 return kvm_emulate_instruction(vcpu
, 0);
5178 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5180 unsigned long exit_qualification
= vmx_get_exit_qual(vcpu
);
5181 int vector
= exit_qualification
& 0xff;
5183 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5184 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5188 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5190 unsigned long exit_qualification
= vmx_get_exit_qual(vcpu
);
5191 u32 offset
= exit_qualification
& 0xfff;
5193 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5194 kvm_apic_write_nodecode(vcpu
, offset
);
5198 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5200 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5201 unsigned long exit_qualification
;
5202 bool has_error_code
= false;
5205 int reason
, type
, idt_v
, idt_index
;
5207 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5208 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5209 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5211 exit_qualification
= vmx_get_exit_qual(vcpu
);
5213 reason
= (u32
)exit_qualification
>> 30;
5214 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5216 case INTR_TYPE_NMI_INTR
:
5217 vcpu
->arch
.nmi_injected
= false;
5218 vmx_set_nmi_mask(vcpu
, true);
5220 case INTR_TYPE_EXT_INTR
:
5221 case INTR_TYPE_SOFT_INTR
:
5222 kvm_clear_interrupt_queue(vcpu
);
5224 case INTR_TYPE_HARD_EXCEPTION
:
5225 if (vmx
->idt_vectoring_info
&
5226 VECTORING_INFO_DELIVER_CODE_MASK
) {
5227 has_error_code
= true;
5229 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5232 case INTR_TYPE_SOFT_EXCEPTION
:
5233 kvm_clear_exception_queue(vcpu
);
5239 tss_selector
= exit_qualification
;
5241 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5242 type
!= INTR_TYPE_EXT_INTR
&&
5243 type
!= INTR_TYPE_NMI_INTR
))
5244 WARN_ON(!skip_emulated_instruction(vcpu
));
5247 * TODO: What about debug traps on tss switch?
5248 * Are we supposed to inject them and update dr6?
5250 return kvm_task_switch(vcpu
, tss_selector
,
5251 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1,
5252 reason
, has_error_code
, error_code
);
5255 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5257 unsigned long exit_qualification
;
5261 exit_qualification
= vmx_get_exit_qual(vcpu
);
5264 * EPT violation happened while executing iret from NMI,
5265 * "blocked by NMI" bit has to be set before next VM entry.
5266 * There are errata that may cause this bit to not be set:
5269 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5271 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5272 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5274 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5275 trace_kvm_page_fault(gpa
, exit_qualification
);
5277 /* Is it a read fault? */
5278 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
5279 ? PFERR_USER_MASK
: 0;
5280 /* Is it a write fault? */
5281 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
5282 ? PFERR_WRITE_MASK
: 0;
5283 /* Is it a fetch fault? */
5284 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
5285 ? PFERR_FETCH_MASK
: 0;
5286 /* ept page table entry is present? */
5287 error_code
|= (exit_qualification
&
5288 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
5289 EPT_VIOLATION_EXECUTABLE
))
5290 ? PFERR_PRESENT_MASK
: 0;
5292 error_code
|= (exit_qualification
& EPT_VIOLATION_GVA_TRANSLATED
) != 0 ?
5293 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
5295 vcpu
->arch
.exit_qualification
= exit_qualification
;
5298 * Check that the GPA doesn't exceed physical memory limits, as that is
5299 * a guest page fault. We have to emulate the instruction here, because
5300 * if the illegal address is that of a paging structure, then
5301 * EPT_VIOLATION_ACC_WRITE bit is set. Alternatively, if supported we
5302 * would also use advanced VM-exit information for EPT violations to
5303 * reconstruct the page fault error code.
5305 if (unlikely(allow_smaller_maxphyaddr
&& kvm_vcpu_is_illegal_gpa(vcpu
, gpa
)))
5306 return kvm_emulate_instruction(vcpu
, 0);
5308 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5311 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5315 if (!vmx_can_emulate_instruction(vcpu
, NULL
, 0))
5319 * A nested guest cannot optimize MMIO vmexits, because we have an
5320 * nGPA here instead of the required GPA.
5322 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5323 if (!is_guest_mode(vcpu
) &&
5324 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5325 trace_kvm_fast_mmio(gpa
);
5326 return kvm_skip_emulated_instruction(vcpu
);
5329 return kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
5332 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5334 if (KVM_BUG_ON(!enable_vnmi
, vcpu
->kvm
))
5337 exec_controls_clearbit(to_vmx(vcpu
), CPU_BASED_NMI_WINDOW_EXITING
);
5338 ++vcpu
->stat
.nmi_window_exits
;
5339 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5344 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5346 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5347 bool intr_window_requested
;
5348 unsigned count
= 130;
5350 intr_window_requested
= exec_controls_get(vmx
) &
5351 CPU_BASED_INTR_WINDOW_EXITING
;
5353 while (vmx
->emulation_required
&& count
-- != 0) {
5354 if (intr_window_requested
&& !vmx_interrupt_blocked(vcpu
))
5355 return handle_interrupt_window(&vmx
->vcpu
);
5357 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
5360 if (!kvm_emulate_instruction(vcpu
, 0))
5363 if (vmx
->emulation_required
&& !vmx
->rmode
.vm86_active
&&
5364 vcpu
->arch
.exception
.pending
) {
5365 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5366 vcpu
->run
->internal
.suberror
=
5367 KVM_INTERNAL_ERROR_EMULATION
;
5368 vcpu
->run
->internal
.ndata
= 0;
5372 if (vcpu
->arch
.halt_request
) {
5373 vcpu
->arch
.halt_request
= 0;
5374 return kvm_vcpu_halt(vcpu
);
5378 * Note, return 1 and not 0, vcpu_run() will invoke
5379 * xfer_to_guest_mode() which will create a proper return
5382 if (__xfer_to_guest_mode_work_pending())
5389 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5391 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5392 unsigned int old
= vmx
->ple_window
;
5394 vmx
->ple_window
= __grow_ple_window(old
, ple_window
,
5398 if (vmx
->ple_window
!= old
) {
5399 vmx
->ple_window_dirty
= true;
5400 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
5401 vmx
->ple_window
, old
);
5405 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5408 unsigned int old
= vmx
->ple_window
;
5410 vmx
->ple_window
= __shrink_ple_window(old
, ple_window
,
5414 if (vmx
->ple_window
!= old
) {
5415 vmx
->ple_window_dirty
= true;
5416 trace_kvm_ple_window_update(vcpu
->vcpu_id
,
5417 vmx
->ple_window
, old
);
5422 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5423 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5425 static int handle_pause(struct kvm_vcpu
*vcpu
)
5427 if (!kvm_pause_in_guest(vcpu
->kvm
))
5428 grow_ple_window(vcpu
);
5431 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
5432 * VM-execution control is ignored if CPL > 0. OTOH, KVM
5433 * never set PAUSE_EXITING and just set PLE if supported,
5434 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
5436 kvm_vcpu_on_spin(vcpu
, true);
5437 return kvm_skip_emulated_instruction(vcpu
);
5440 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
5445 static int handle_invpcid(struct kvm_vcpu
*vcpu
)
5447 u32 vmx_instruction_info
;
5455 if (!guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
)) {
5456 kvm_queue_exception(vcpu
, UD_VECTOR
);
5460 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5461 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
5464 kvm_inject_gp(vcpu
, 0);
5468 /* According to the Intel instruction reference, the memory operand
5469 * is read even if it isn't needed (e.g., for type==all)
5471 if (get_vmx_mem_address(vcpu
, vmx_get_exit_qual(vcpu
),
5472 vmx_instruction_info
, false,
5473 sizeof(operand
), &gva
))
5476 return kvm_handle_invpcid(vcpu
, type
, gva
);
5479 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
5481 unsigned long exit_qualification
;
5483 trace_kvm_pml_full(vcpu
->vcpu_id
);
5485 exit_qualification
= vmx_get_exit_qual(vcpu
);
5488 * PML buffer FULL happened while executing iret from NMI,
5489 * "blocked by NMI" bit has to be set before next VM entry.
5491 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5493 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5494 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5495 GUEST_INTR_STATE_NMI
);
5498 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5499 * here.., and there's no userspace involvement needed for PML.
5504 static fastpath_t
handle_fastpath_preemption_timer(struct kvm_vcpu
*vcpu
)
5506 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5508 if (!vmx
->req_immediate_exit
&&
5509 !unlikely(vmx
->loaded_vmcs
->hv_timer_soft_disabled
)) {
5510 kvm_lapic_expired_hv_timer(vcpu
);
5511 return EXIT_FASTPATH_REENTER_GUEST
;
5514 return EXIT_FASTPATH_NONE
;
5517 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
5519 handle_fastpath_preemption_timer(vcpu
);
5524 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5525 * are overwritten by nested_vmx_setup() when nested=1.
5527 static int handle_vmx_instruction(struct kvm_vcpu
*vcpu
)
5529 kvm_queue_exception(vcpu
, UD_VECTOR
);
5533 #ifndef CONFIG_X86_SGX_KVM
5534 static int handle_encls(struct kvm_vcpu
*vcpu
)
5537 * SGX virtualization is disabled. There is no software enable bit for
5538 * SGX, so KVM intercepts all ENCLS leafs and injects a #UD to prevent
5539 * the guest from executing ENCLS (when SGX is supported by hardware).
5541 kvm_queue_exception(vcpu
, UD_VECTOR
);
5544 #endif /* CONFIG_X86_SGX_KVM */
5546 static int handle_bus_lock_vmexit(struct kvm_vcpu
*vcpu
)
5549 * Hardware may or may not set the BUS_LOCK_DETECTED flag on BUS_LOCK
5550 * VM-Exits. Unconditionally set the flag here and leave the handling to
5551 * vmx_handle_exit().
5553 to_vmx(vcpu
)->exit_reason
.bus_lock_detected
= true;
5558 * The exit handlers return 1 if the exit was handled fully and guest execution
5559 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5560 * to be done to userspace and return 0.
5562 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5563 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception_nmi
,
5564 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5565 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5566 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5567 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5568 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5569 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5570 [EXIT_REASON_CPUID
] = kvm_emulate_cpuid
,
5571 [EXIT_REASON_MSR_READ
] = kvm_emulate_rdmsr
,
5572 [EXIT_REASON_MSR_WRITE
] = kvm_emulate_wrmsr
,
5573 [EXIT_REASON_INTERRUPT_WINDOW
] = handle_interrupt_window
,
5574 [EXIT_REASON_HLT
] = kvm_emulate_halt
,
5575 [EXIT_REASON_INVD
] = kvm_emulate_invd
,
5576 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5577 [EXIT_REASON_RDPMC
] = kvm_emulate_rdpmc
,
5578 [EXIT_REASON_VMCALL
] = kvm_emulate_hypercall
,
5579 [EXIT_REASON_VMCLEAR
] = handle_vmx_instruction
,
5580 [EXIT_REASON_VMLAUNCH
] = handle_vmx_instruction
,
5581 [EXIT_REASON_VMPTRLD
] = handle_vmx_instruction
,
5582 [EXIT_REASON_VMPTRST
] = handle_vmx_instruction
,
5583 [EXIT_REASON_VMREAD
] = handle_vmx_instruction
,
5584 [EXIT_REASON_VMRESUME
] = handle_vmx_instruction
,
5585 [EXIT_REASON_VMWRITE
] = handle_vmx_instruction
,
5586 [EXIT_REASON_VMOFF
] = handle_vmx_instruction
,
5587 [EXIT_REASON_VMON
] = handle_vmx_instruction
,
5588 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5589 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5590 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
5591 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
5592 [EXIT_REASON_WBINVD
] = kvm_emulate_wbinvd
,
5593 [EXIT_REASON_XSETBV
] = kvm_emulate_xsetbv
,
5594 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5595 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5596 [EXIT_REASON_GDTR_IDTR
] = handle_desc
,
5597 [EXIT_REASON_LDTR_TR
] = handle_desc
,
5598 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5599 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5600 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5601 [EXIT_REASON_MWAIT_INSTRUCTION
] = kvm_emulate_mwait
,
5602 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
5603 [EXIT_REASON_MONITOR_INSTRUCTION
] = kvm_emulate_monitor
,
5604 [EXIT_REASON_INVEPT
] = handle_vmx_instruction
,
5605 [EXIT_REASON_INVVPID
] = handle_vmx_instruction
,
5606 [EXIT_REASON_RDRAND
] = kvm_handle_invalid_op
,
5607 [EXIT_REASON_RDSEED
] = kvm_handle_invalid_op
,
5608 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
5609 [EXIT_REASON_INVPCID
] = handle_invpcid
,
5610 [EXIT_REASON_VMFUNC
] = handle_vmx_instruction
,
5611 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
5612 [EXIT_REASON_ENCLS
] = handle_encls
,
5613 [EXIT_REASON_BUS_LOCK
] = handle_bus_lock_vmexit
,
5616 static const int kvm_vmx_max_exit_handlers
=
5617 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5619 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
,
5620 u32
*intr_info
, u32
*error_code
)
5622 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5624 *info1
= vmx_get_exit_qual(vcpu
);
5625 if (!(vmx
->exit_reason
.failed_vmentry
)) {
5626 *info2
= vmx
->idt_vectoring_info
;
5627 *intr_info
= vmx_get_intr_info(vcpu
);
5628 if (is_exception_with_error_code(*intr_info
))
5629 *error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5639 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
5642 __free_page(vmx
->pml_pg
);
5647 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
5649 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5653 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
5655 /* Do nothing if PML buffer is empty */
5656 if (pml_idx
== (PML_ENTITY_NUM
- 1))
5659 /* PML index always points to next available PML buffer entity */
5660 if (pml_idx
>= PML_ENTITY_NUM
)
5665 pml_buf
= page_address(vmx
->pml_pg
);
5666 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
5669 gpa
= pml_buf
[pml_idx
];
5670 WARN_ON(gpa
& (PAGE_SIZE
- 1));
5671 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
5674 /* reset PML index */
5675 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5678 static void vmx_dump_sel(char *name
, uint32_t sel
)
5680 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5681 name
, vmcs_read16(sel
),
5682 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
5683 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
5684 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
5687 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
5689 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5690 name
, vmcs_read32(limit
),
5691 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
5694 static void vmx_dump_msrs(char *name
, struct vmx_msrs
*m
)
5697 struct vmx_msr_entry
*e
;
5699 pr_err("MSR %s:\n", name
);
5700 for (i
= 0, e
= m
->val
; i
< m
->nr
; ++i
, ++e
)
5701 pr_err(" %2d: msr=0x%08x value=0x%016llx\n", i
, e
->index
, e
->value
);
5704 void dump_vmcs(struct kvm_vcpu
*vcpu
)
5706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5707 u32 vmentry_ctl
, vmexit_ctl
;
5708 u32 cpu_based_exec_ctrl
, pin_based_exec_ctrl
, secondary_exec_control
;
5712 if (!dump_invalid_vmcs
) {
5713 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n");
5717 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
5718 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
5719 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5720 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
5721 cr4
= vmcs_readl(GUEST_CR4
);
5722 secondary_exec_control
= 0;
5723 if (cpu_has_secondary_exec_ctrls())
5724 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5726 pr_err("VMCS %p, last attempted VM-entry on CPU %d\n",
5727 vmx
->loaded_vmcs
->vmcs
, vcpu
->arch
.last_vmentry_cpu
);
5728 pr_err("*** Guest State ***\n");
5729 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5730 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
5731 vmcs_readl(CR0_GUEST_HOST_MASK
));
5732 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5733 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
5734 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
5735 if (cpu_has_vmx_ept()) {
5736 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5737 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
5738 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5739 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
5741 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5742 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
5743 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5744 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
5745 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5746 vmcs_readl(GUEST_SYSENTER_ESP
),
5747 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
5748 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
5749 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
5750 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
5751 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
5752 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
5753 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
5754 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
5755 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
5756 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
5757 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
5758 efer_slot
= vmx_find_loadstore_msr_slot(&vmx
->msr_autoload
.guest
, MSR_EFER
);
5759 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_EFER
)
5760 pr_err("EFER= 0x%016llx\n", vmcs_read64(GUEST_IA32_EFER
));
5761 else if (efer_slot
>= 0)
5762 pr_err("EFER= 0x%016llx (autoload)\n",
5763 vmx
->msr_autoload
.guest
.val
[efer_slot
].value
);
5764 else if (vmentry_ctl
& VM_ENTRY_IA32E_MODE
)
5765 pr_err("EFER= 0x%016llx (effective)\n",
5766 vcpu
->arch
.efer
| (EFER_LMA
| EFER_LME
));
5768 pr_err("EFER= 0x%016llx (effective)\n",
5769 vcpu
->arch
.efer
& ~(EFER_LMA
| EFER_LME
));
5770 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PAT
)
5771 pr_err("PAT = 0x%016llx\n", vmcs_read64(GUEST_IA32_PAT
));
5772 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5773 vmcs_read64(GUEST_IA32_DEBUGCTL
),
5774 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
5775 if (cpu_has_load_perf_global_ctrl() &&
5776 vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
5777 pr_err("PerfGlobCtl = 0x%016llx\n",
5778 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
5779 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
5780 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
5781 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5782 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
5783 vmcs_read32(GUEST_ACTIVITY_STATE
));
5784 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
5785 pr_err("InterruptStatus = %04x\n",
5786 vmcs_read16(GUEST_INTR_STATUS
));
5787 if (vmcs_read32(VM_ENTRY_MSR_LOAD_COUNT
) > 0)
5788 vmx_dump_msrs("guest autoload", &vmx
->msr_autoload
.guest
);
5789 if (vmcs_read32(VM_EXIT_MSR_STORE_COUNT
) > 0)
5790 vmx_dump_msrs("guest autostore", &vmx
->msr_autostore
.guest
);
5792 pr_err("*** Host State ***\n");
5793 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5794 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
5795 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5796 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
5797 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
5798 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
5799 vmcs_read16(HOST_TR_SELECTOR
));
5800 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5801 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
5802 vmcs_readl(HOST_TR_BASE
));
5803 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5804 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
5805 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5806 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
5807 vmcs_readl(HOST_CR4
));
5808 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5809 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
5810 vmcs_read32(HOST_IA32_SYSENTER_CS
),
5811 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
5812 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_EFER
)
5813 pr_err("EFER= 0x%016llx\n", vmcs_read64(HOST_IA32_EFER
));
5814 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PAT
)
5815 pr_err("PAT = 0x%016llx\n", vmcs_read64(HOST_IA32_PAT
));
5816 if (cpu_has_load_perf_global_ctrl() &&
5817 vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
5818 pr_err("PerfGlobCtl = 0x%016llx\n",
5819 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
5820 if (vmcs_read32(VM_EXIT_MSR_LOAD_COUNT
) > 0)
5821 vmx_dump_msrs("host autoload", &vmx
->msr_autoload
.host
);
5823 pr_err("*** Control State ***\n");
5824 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5825 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
5826 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
5827 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5828 vmcs_read32(EXCEPTION_BITMAP
),
5829 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
5830 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
5831 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5832 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
5833 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
5834 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
5835 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5836 vmcs_read32(VM_EXIT_INTR_INFO
),
5837 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
5838 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
5839 pr_err(" reason=%08x qualification=%016lx\n",
5840 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
5841 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5842 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
5843 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
5844 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
5845 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
5846 pr_err("TSC Multiplier = 0x%016llx\n",
5847 vmcs_read64(TSC_MULTIPLIER
));
5848 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
) {
5849 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
5850 u16 status
= vmcs_read16(GUEST_INTR_STATUS
);
5851 pr_err("SVI|RVI = %02x|%02x ", status
>> 8, status
& 0xff);
5853 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
5854 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
5855 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR
));
5856 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR
));
5858 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
5859 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
5860 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
5861 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
5862 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
5863 pr_err("PLE Gap=%08x Window=%08x\n",
5864 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
5865 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
5866 pr_err("Virtual processor ID = 0x%04x\n",
5867 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
5871 * The guest has exited. See if we can fix it or if we need userspace
5874 static int __vmx_handle_exit(struct kvm_vcpu
*vcpu
, fastpath_t exit_fastpath
)
5876 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5877 union vmx_exit_reason exit_reason
= vmx
->exit_reason
;
5878 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5879 u16 exit_handler_index
;
5882 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5883 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5884 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5885 * mode as if vcpus is in root mode, the PML buffer must has been
5886 * flushed already. Note, PML is never enabled in hardware while
5889 if (enable_pml
&& !is_guest_mode(vcpu
))
5890 vmx_flush_pml_buffer(vcpu
);
5893 * KVM should never reach this point with a pending nested VM-Enter.
5894 * More specifically, short-circuiting VM-Entry to emulate L2 due to
5895 * invalid guest state should never happen as that means KVM knowingly
5896 * allowed a nested VM-Enter with an invalid vmcs12. More below.
5898 if (KVM_BUG_ON(vmx
->nested
.nested_run_pending
, vcpu
->kvm
))
5901 if (is_guest_mode(vcpu
)) {
5903 * PML is never enabled when running L2, bail immediately if a
5904 * PML full exit occurs as something is horribly wrong.
5906 if (exit_reason
.basic
== EXIT_REASON_PML_FULL
)
5907 goto unexpected_vmexit
;
5910 * The host physical addresses of some pages of guest memory
5911 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
5912 * Page). The CPU may write to these pages via their host
5913 * physical address while L2 is running, bypassing any
5914 * address-translation-based dirty tracking (e.g. EPT write
5917 * Mark them dirty on every exit from L2 to prevent them from
5918 * getting out of sync with dirty tracking.
5920 nested_mark_vmcs12_pages_dirty(vcpu
);
5923 * Synthesize a triple fault if L2 state is invalid. In normal
5924 * operation, nested VM-Enter rejects any attempt to enter L2
5925 * with invalid state. However, those checks are skipped if
5926 * state is being stuffed via RSM or KVM_SET_NESTED_STATE. If
5927 * L2 state is invalid, it means either L1 modified SMRAM state
5928 * or userspace provided bad state. Synthesize TRIPLE_FAULT as
5929 * doing so is architecturally allowed in the RSM case, and is
5930 * the least awful solution for the userspace case without
5931 * risking false positives.
5933 if (vmx
->emulation_required
) {
5934 nested_vmx_vmexit(vcpu
, EXIT_REASON_TRIPLE_FAULT
, 0, 0);
5938 if (nested_vmx_reflect_vmexit(vcpu
))
5942 /* If guest state is invalid, start emulating. L2 is handled above. */
5943 if (vmx
->emulation_required
)
5944 return handle_invalid_guest_state(vcpu
);
5946 if (exit_reason
.failed_vmentry
) {
5948 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5949 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5951 vcpu
->run
->fail_entry
.cpu
= vcpu
->arch
.last_vmentry_cpu
;
5955 if (unlikely(vmx
->fail
)) {
5957 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5958 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5959 = vmcs_read32(VM_INSTRUCTION_ERROR
);
5960 vcpu
->run
->fail_entry
.cpu
= vcpu
->arch
.last_vmentry_cpu
;
5966 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5967 * delivery event since it indicates guest is accessing MMIO.
5968 * The vm-exit can be triggered again after return to guest that
5969 * will cause infinite loop.
5971 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5972 (exit_reason
.basic
!= EXIT_REASON_EXCEPTION_NMI
&&
5973 exit_reason
.basic
!= EXIT_REASON_EPT_VIOLATION
&&
5974 exit_reason
.basic
!= EXIT_REASON_PML_FULL
&&
5975 exit_reason
.basic
!= EXIT_REASON_APIC_ACCESS
&&
5976 exit_reason
.basic
!= EXIT_REASON_TASK_SWITCH
)) {
5979 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5980 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
5981 vcpu
->run
->internal
.data
[0] = vectoring_info
;
5982 vcpu
->run
->internal
.data
[1] = exit_reason
.full
;
5983 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
5984 if (exit_reason
.basic
== EXIT_REASON_EPT_MISCONFIG
) {
5985 vcpu
->run
->internal
.data
[ndata
++] =
5986 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5988 vcpu
->run
->internal
.data
[ndata
++] = vcpu
->arch
.last_vmentry_cpu
;
5989 vcpu
->run
->internal
.ndata
= ndata
;
5993 if (unlikely(!enable_vnmi
&&
5994 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
5995 if (!vmx_interrupt_blocked(vcpu
)) {
5996 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
5997 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
5998 vcpu
->arch
.nmi_pending
) {
6000 * This CPU don't support us in finding the end of an
6001 * NMI-blocked window if the guest runs with IRQs
6002 * disabled. So we pull the trigger after 1 s of
6003 * futile waiting, but inform the user about this.
6005 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6006 "state on VCPU %d after 1 s timeout\n",
6007 __func__
, vcpu
->vcpu_id
);
6008 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
6012 if (exit_fastpath
!= EXIT_FASTPATH_NONE
)
6015 if (exit_reason
.basic
>= kvm_vmx_max_exit_handlers
)
6016 goto unexpected_vmexit
;
6017 #ifdef CONFIG_RETPOLINE
6018 if (exit_reason
.basic
== EXIT_REASON_MSR_WRITE
)
6019 return kvm_emulate_wrmsr(vcpu
);
6020 else if (exit_reason
.basic
== EXIT_REASON_PREEMPTION_TIMER
)
6021 return handle_preemption_timer(vcpu
);
6022 else if (exit_reason
.basic
== EXIT_REASON_INTERRUPT_WINDOW
)
6023 return handle_interrupt_window(vcpu
);
6024 else if (exit_reason
.basic
== EXIT_REASON_EXTERNAL_INTERRUPT
)
6025 return handle_external_interrupt(vcpu
);
6026 else if (exit_reason
.basic
== EXIT_REASON_HLT
)
6027 return kvm_emulate_halt(vcpu
);
6028 else if (exit_reason
.basic
== EXIT_REASON_EPT_MISCONFIG
)
6029 return handle_ept_misconfig(vcpu
);
6032 exit_handler_index
= array_index_nospec((u16
)exit_reason
.basic
,
6033 kvm_vmx_max_exit_handlers
);
6034 if (!kvm_vmx_exit_handlers
[exit_handler_index
])
6035 goto unexpected_vmexit
;
6037 return kvm_vmx_exit_handlers
[exit_handler_index
](vcpu
);
6040 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
6043 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6044 vcpu
->run
->internal
.suberror
=
6045 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON
;
6046 vcpu
->run
->internal
.ndata
= 2;
6047 vcpu
->run
->internal
.data
[0] = exit_reason
.full
;
6048 vcpu
->run
->internal
.data
[1] = vcpu
->arch
.last_vmentry_cpu
;
6052 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
, fastpath_t exit_fastpath
)
6054 int ret
= __vmx_handle_exit(vcpu
, exit_fastpath
);
6057 * Exit to user space when bus lock detected to inform that there is
6058 * a bus lock in guest.
6060 if (to_vmx(vcpu
)->exit_reason
.bus_lock_detected
) {
6062 vcpu
->run
->exit_reason
= KVM_EXIT_X86_BUS_LOCK
;
6064 vcpu
->run
->flags
|= KVM_RUN_X86_BUS_LOCK
;
6071 * Software based L1D cache flush which is used when microcode providing
6072 * the cache control MSR is not loaded.
6074 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
6075 * flush it is required to read in 64 KiB because the replacement algorithm
6076 * is not exactly LRU. This could be sized at runtime via topology
6077 * information but as all relevant affected CPUs have 32KiB L1D cache size
6078 * there is no point in doing so.
6080 static noinstr
void vmx_l1d_flush(struct kvm_vcpu
*vcpu
)
6082 int size
= PAGE_SIZE
<< L1D_CACHE_ORDER
;
6085 * This code is only executed when the the flush mode is 'cond' or
6088 if (static_branch_likely(&vmx_l1d_flush_cond
)) {
6092 * Clear the per-vcpu flush bit, it gets set again
6093 * either from vcpu_run() or from one of the unsafe
6096 flush_l1d
= vcpu
->arch
.l1tf_flush_l1d
;
6097 vcpu
->arch
.l1tf_flush_l1d
= false;
6100 * Clear the per-cpu flush bit, it gets set again from
6101 * the interrupt handlers.
6103 flush_l1d
|= kvm_get_cpu_l1tf_flush_l1d();
6104 kvm_clear_cpu_l1tf_flush_l1d();
6110 vcpu
->stat
.l1d_flush
++;
6112 if (static_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
6113 native_wrmsrl(MSR_IA32_FLUSH_CMD
, L1D_FLUSH
);
6118 /* First ensure the pages are in the TLB */
6119 "xorl %%eax, %%eax\n"
6120 ".Lpopulate_tlb:\n\t"
6121 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
6122 "addl $4096, %%eax\n\t"
6123 "cmpl %%eax, %[size]\n\t"
6124 "jne .Lpopulate_tlb\n\t"
6125 "xorl %%eax, %%eax\n\t"
6127 /* Now fill the cache */
6128 "xorl %%eax, %%eax\n"
6130 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
6131 "addl $64, %%eax\n\t"
6132 "cmpl %%eax, %[size]\n\t"
6133 "jne .Lfill_cache\n\t"
6135 :: [flush_pages
] "r" (vmx_l1d_flush_pages
),
6137 : "eax", "ebx", "ecx", "edx");
6140 static void vmx_update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6142 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6145 if (is_guest_mode(vcpu
) &&
6146 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
6149 tpr_threshold
= (irr
== -1 || tpr
< irr
) ? 0 : irr
;
6150 if (is_guest_mode(vcpu
))
6151 to_vmx(vcpu
)->nested
.l1_tpr_threshold
= tpr_threshold
;
6153 vmcs_write32(TPR_THRESHOLD
, tpr_threshold
);
6156 void vmx_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
6158 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6159 u32 sec_exec_control
;
6161 if (!lapic_in_kernel(vcpu
))
6164 if (!flexpriority_enabled
&&
6165 !cpu_has_vmx_virtualize_x2apic_mode())
6168 /* Postpone execution until vmcs01 is the current VMCS. */
6169 if (is_guest_mode(vcpu
)) {
6170 vmx
->nested
.change_vmcs01_virtual_apic_mode
= true;
6174 sec_exec_control
= secondary_exec_controls_get(vmx
);
6175 sec_exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
6176 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
6178 switch (kvm_get_apic_mode(vcpu
)) {
6179 case LAPIC_MODE_INVALID
:
6180 WARN_ONCE(true, "Invalid local APIC state");
6182 case LAPIC_MODE_DISABLED
:
6184 case LAPIC_MODE_XAPIC
:
6185 if (flexpriority_enabled
) {
6187 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6188 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
6191 * Flush the TLB, reloading the APIC access page will
6192 * only do so if its physical address has changed, but
6193 * the guest may have inserted a non-APIC mapping into
6194 * the TLB while the APIC access page was disabled.
6196 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT
, vcpu
);
6199 case LAPIC_MODE_X2APIC
:
6200 if (cpu_has_vmx_virtualize_x2apic_mode())
6202 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6205 secondary_exec_controls_set(vmx
, sec_exec_control
);
6207 vmx_update_msr_bitmap_x2apic(vcpu
);
6210 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
)
6214 /* Defer reload until vmcs01 is the current VMCS. */
6215 if (is_guest_mode(vcpu
)) {
6216 to_vmx(vcpu
)->nested
.reload_vmcs01_apic_access_page
= true;
6220 if (!(secondary_exec_controls_get(to_vmx(vcpu
)) &
6221 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
6224 page
= gfn_to_page(vcpu
->kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
6225 if (is_error_page(page
))
6228 vmcs_write64(APIC_ACCESS_ADDR
, page_to_phys(page
));
6229 vmx_flush_tlb_current(vcpu
);
6232 * Do not pin apic access page in memory, the MMU notifier
6233 * will call us again if it is migrated or swapped out.
6238 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
6246 status
= vmcs_read16(GUEST_INTR_STATUS
);
6248 if (max_isr
!= old
) {
6250 status
|= max_isr
<< 8;
6251 vmcs_write16(GUEST_INTR_STATUS
, status
);
6255 static void vmx_set_rvi(int vector
)
6263 status
= vmcs_read16(GUEST_INTR_STATUS
);
6264 old
= (u8
)status
& 0xff;
6265 if ((u8
)vector
!= old
) {
6267 status
|= (u8
)vector
;
6268 vmcs_write16(GUEST_INTR_STATUS
, status
);
6272 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6275 * When running L2, updating RVI is only relevant when
6276 * vmcs12 virtual-interrupt-delivery enabled.
6277 * However, it can be enabled only when L1 also
6278 * intercepts external-interrupts and in that case
6279 * we should not update vmcs02 RVI but instead intercept
6280 * interrupt. Therefore, do nothing when running L2.
6282 if (!is_guest_mode(vcpu
))
6283 vmx_set_rvi(max_irr
);
6286 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
6288 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6290 bool got_posted_interrupt
;
6292 if (KVM_BUG_ON(!enable_apicv
, vcpu
->kvm
))
6295 if (pi_test_on(&vmx
->pi_desc
)) {
6296 pi_clear_on(&vmx
->pi_desc
);
6298 * IOMMU can write to PID.ON, so the barrier matters even on UP.
6299 * But on x86 this is just a compiler barrier anyway.
6301 smp_mb__after_atomic();
6302 got_posted_interrupt
=
6303 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
, &max_irr
);
6305 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
6306 got_posted_interrupt
= false;
6310 * Newly recognized interrupts are injected via either virtual interrupt
6311 * delivery (RVI) or KVM_REQ_EVENT. Virtual interrupt delivery is
6312 * disabled in two cases:
6314 * 1) If L2 is running and the vCPU has a new pending interrupt. If L1
6315 * wants to exit on interrupts, KVM_REQ_EVENT is needed to synthesize a
6316 * VM-Exit to L1. If L1 doesn't want to exit, the interrupt is injected
6317 * into L2, but KVM doesn't use virtual interrupt delivery to inject
6318 * interrupts into L2, and so KVM_REQ_EVENT is again needed.
6320 * 2) If APICv is disabled for this vCPU, assigned devices may still
6321 * attempt to post interrupts. The posted interrupt vector will cause
6322 * a VM-Exit and the subsequent entry will call sync_pir_to_irr.
6324 if (!is_guest_mode(vcpu
) && kvm_vcpu_apicv_active(vcpu
))
6325 vmx_set_rvi(max_irr
);
6326 else if (got_posted_interrupt
)
6327 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6332 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6334 if (!kvm_vcpu_apicv_active(vcpu
))
6337 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6338 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6339 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6340 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6343 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
6345 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6347 pi_clear_on(&vmx
->pi_desc
);
6348 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
6351 void vmx_do_interrupt_nmi_irqoff(unsigned long entry
);
6353 static void handle_interrupt_nmi_irqoff(struct kvm_vcpu
*vcpu
,
6354 unsigned long entry
)
6356 kvm_before_interrupt(vcpu
);
6357 vmx_do_interrupt_nmi_irqoff(entry
);
6358 kvm_after_interrupt(vcpu
);
6361 static void handle_exception_nmi_irqoff(struct vcpu_vmx
*vmx
)
6363 const unsigned long nmi_entry
= (unsigned long)asm_exc_nmi_noist
;
6364 u32 intr_info
= vmx_get_intr_info(&vmx
->vcpu
);
6366 /* if exit due to PF check for async PF */
6367 if (is_page_fault(intr_info
))
6368 vmx
->vcpu
.arch
.apf
.host_apf_flags
= kvm_read_and_reset_apf_flags();
6369 /* Handle machine checks before interrupts are enabled */
6370 else if (is_machine_check(intr_info
))
6371 kvm_machine_check();
6372 /* We need to handle NMIs before interrupts are enabled */
6373 else if (is_nmi(intr_info
))
6374 handle_interrupt_nmi_irqoff(&vmx
->vcpu
, nmi_entry
);
6377 static void handle_external_interrupt_irqoff(struct kvm_vcpu
*vcpu
)
6379 u32 intr_info
= vmx_get_intr_info(vcpu
);
6380 unsigned int vector
= intr_info
& INTR_INFO_VECTOR_MASK
;
6381 gate_desc
*desc
= (gate_desc
*)host_idt_base
+ vector
;
6383 if (KVM_BUG(!is_external_intr(intr_info
), vcpu
->kvm
,
6384 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info
))
6387 handle_interrupt_nmi_irqoff(vcpu
, gate_offset(desc
));
6390 static void vmx_handle_exit_irqoff(struct kvm_vcpu
*vcpu
)
6392 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6394 if (vmx
->emulation_required
)
6397 if (vmx
->exit_reason
.basic
== EXIT_REASON_EXTERNAL_INTERRUPT
)
6398 handle_external_interrupt_irqoff(vcpu
);
6399 else if (vmx
->exit_reason
.basic
== EXIT_REASON_EXCEPTION_NMI
)
6400 handle_exception_nmi_irqoff(vmx
);
6404 * The kvm parameter can be NULL (module initialization, or invocation before
6405 * VM creation). Be sure to check the kvm parameter before using it.
6407 static bool vmx_has_emulated_msr(struct kvm
*kvm
, u32 index
)
6410 case MSR_IA32_SMBASE
:
6412 * We cannot do SMM unless we can run the guest in big
6415 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
6416 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
6418 case MSR_AMD64_VIRT_SPEC_CTRL
:
6419 /* This is AMD only. */
6426 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6431 bool idtv_info_valid
;
6433 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6436 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
6439 exit_intr_info
= vmx_get_intr_info(&vmx
->vcpu
);
6440 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6441 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6443 * SDM 3: 27.7.1.2 (September 2008)
6444 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6445 * a guest IRET fault.
6446 * SDM 3: 23.2.2 (September 2008)
6447 * Bit 12 is undefined in any of the following cases:
6448 * If the VM exit sets the valid bit in the IDT-vectoring
6449 * information field.
6450 * If the VM exit is due to a double fault.
6452 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6453 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6454 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6455 GUEST_INTR_STATE_NMI
);
6457 vmx
->loaded_vmcs
->nmi_known_unmasked
=
6458 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6459 & GUEST_INTR_STATE_NMI
);
6460 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
6461 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
6462 ktime_to_ns(ktime_sub(ktime_get(),
6463 vmx
->loaded_vmcs
->entry_time
));
6466 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
6467 u32 idt_vectoring_info
,
6468 int instr_len_field
,
6469 int error_code_field
)
6473 bool idtv_info_valid
;
6475 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6477 vcpu
->arch
.nmi_injected
= false;
6478 kvm_clear_exception_queue(vcpu
);
6479 kvm_clear_interrupt_queue(vcpu
);
6481 if (!idtv_info_valid
)
6484 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6486 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6487 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6490 case INTR_TYPE_NMI_INTR
:
6491 vcpu
->arch
.nmi_injected
= true;
6493 * SDM 3: 27.7.1.2 (September 2008)
6494 * Clear bit "block by NMI" before VM entry if a NMI
6497 vmx_set_nmi_mask(vcpu
, false);
6499 case INTR_TYPE_SOFT_EXCEPTION
:
6500 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6502 case INTR_TYPE_HARD_EXCEPTION
:
6503 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6504 u32 err
= vmcs_read32(error_code_field
);
6505 kvm_requeue_exception_e(vcpu
, vector
, err
);
6507 kvm_requeue_exception(vcpu
, vector
);
6509 case INTR_TYPE_SOFT_INTR
:
6510 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6512 case INTR_TYPE_EXT_INTR
:
6513 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
6520 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6522 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
6523 VM_EXIT_INSTRUCTION_LEN
,
6524 IDT_VECTORING_ERROR_CODE
);
6527 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6529 __vmx_complete_interrupts(vcpu
,
6530 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6531 VM_ENTRY_INSTRUCTION_LEN
,
6532 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6534 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6537 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6540 struct perf_guest_switch_msr
*msrs
;
6542 /* Note, nr_msrs may be garbage if perf_guest_get_msrs() returns NULL. */
6543 msrs
= perf_guest_get_msrs(&nr_msrs
);
6547 for (i
= 0; i
< nr_msrs
; i
++)
6548 if (msrs
[i
].host
== msrs
[i
].guest
)
6549 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6551 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6552 msrs
[i
].host
, false);
6555 static void vmx_update_hv_timer(struct kvm_vcpu
*vcpu
)
6557 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6561 if (vmx
->req_immediate_exit
) {
6562 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, 0);
6563 vmx
->loaded_vmcs
->hv_timer_soft_disabled
= false;
6564 } else if (vmx
->hv_deadline_tsc
!= -1) {
6566 if (vmx
->hv_deadline_tsc
> tscl
)
6567 /* set_hv_timer ensures the delta fits in 32-bits */
6568 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
6569 cpu_preemption_timer_multi
);
6573 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
6574 vmx
->loaded_vmcs
->hv_timer_soft_disabled
= false;
6575 } else if (!vmx
->loaded_vmcs
->hv_timer_soft_disabled
) {
6576 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, -1);
6577 vmx
->loaded_vmcs
->hv_timer_soft_disabled
= true;
6581 void noinstr
vmx_update_host_rsp(struct vcpu_vmx
*vmx
, unsigned long host_rsp
)
6583 if (unlikely(host_rsp
!= vmx
->loaded_vmcs
->host_state
.rsp
)) {
6584 vmx
->loaded_vmcs
->host_state
.rsp
= host_rsp
;
6585 vmcs_writel(HOST_RSP
, host_rsp
);
6589 static fastpath_t
vmx_exit_handlers_fastpath(struct kvm_vcpu
*vcpu
)
6591 switch (to_vmx(vcpu
)->exit_reason
.basic
) {
6592 case EXIT_REASON_MSR_WRITE
:
6593 return handle_fastpath_set_msr_irqoff(vcpu
);
6594 case EXIT_REASON_PREEMPTION_TIMER
:
6595 return handle_fastpath_preemption_timer(vcpu
);
6597 return EXIT_FASTPATH_NONE
;
6601 static noinstr
void vmx_vcpu_enter_exit(struct kvm_vcpu
*vcpu
,
6602 struct vcpu_vmx
*vmx
)
6604 kvm_guest_enter_irqoff();
6606 /* L1D Flush includes CPU buffer clear to mitigate MDS */
6607 if (static_branch_unlikely(&vmx_l1d_should_flush
))
6608 vmx_l1d_flush(vcpu
);
6609 else if (static_branch_unlikely(&mds_user_clear
))
6610 mds_clear_cpu_buffers();
6611 else if (static_branch_unlikely(&mmio_stale_data_clear
) &&
6612 kvm_arch_has_assigned_device(vcpu
->kvm
))
6613 mds_clear_cpu_buffers();
6615 if (vcpu
->arch
.cr2
!= native_read_cr2())
6616 native_write_cr2(vcpu
->arch
.cr2
);
6618 vmx
->fail
= __vmx_vcpu_run(vmx
, (unsigned long *)&vcpu
->arch
.regs
,
6619 vmx
->loaded_vmcs
->launched
);
6621 vcpu
->arch
.cr2
= native_read_cr2();
6623 kvm_guest_exit_irqoff();
6626 static fastpath_t
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6628 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6629 unsigned long cr3
, cr4
;
6631 /* Record the guest's net vcpu time for enforced NMI injections. */
6632 if (unlikely(!enable_vnmi
&&
6633 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
6634 vmx
->loaded_vmcs
->entry_time
= ktime_get();
6637 * Don't enter VMX if guest state is invalid, let the exit handler
6638 * start emulation until we arrive back to a valid state. Synthesize a
6639 * consistency check VM-Exit due to invalid guest state and bail.
6641 if (unlikely(vmx
->emulation_required
)) {
6644 vmx
->exit_reason
.full
= EXIT_REASON_INVALID_STATE
;
6645 vmx
->exit_reason
.failed_vmentry
= 1;
6646 kvm_register_mark_available(vcpu
, VCPU_EXREG_EXIT_INFO_1
);
6647 vmx
->exit_qualification
= ENTRY_FAIL_DEFAULT
;
6648 kvm_register_mark_available(vcpu
, VCPU_EXREG_EXIT_INFO_2
);
6649 vmx
->exit_intr_info
= 0;
6650 return EXIT_FASTPATH_NONE
;
6653 trace_kvm_entry(vcpu
);
6655 if (vmx
->ple_window_dirty
) {
6656 vmx
->ple_window_dirty
= false;
6657 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
6661 * We did this in prepare_switch_to_guest, because it needs to
6662 * be within srcu_read_lock.
6664 WARN_ON_ONCE(vmx
->nested
.need_vmcs12_to_shadow_sync
);
6666 if (kvm_register_is_dirty(vcpu
, VCPU_REGS_RSP
))
6667 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6668 if (kvm_register_is_dirty(vcpu
, VCPU_REGS_RIP
))
6669 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6671 cr3
= __get_current_cr3_fast();
6672 if (unlikely(cr3
!= vmx
->loaded_vmcs
->host_state
.cr3
)) {
6673 vmcs_writel(HOST_CR3
, cr3
);
6674 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
6677 cr4
= cr4_read_shadow();
6678 if (unlikely(cr4
!= vmx
->loaded_vmcs
->host_state
.cr4
)) {
6679 vmcs_writel(HOST_CR4
, cr4
);
6680 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
6683 /* When KVM_DEBUGREG_WONT_EXIT, dr6 is accessible in guest. */
6684 if (unlikely(vcpu
->arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
))
6685 set_debugreg(vcpu
->arch
.dr6
, 6);
6687 /* When single-stepping over STI and MOV SS, we must clear the
6688 * corresponding interruptibility bits in the guest state. Otherwise
6689 * vmentry fails as it then expects bit 14 (BS) in pending debug
6690 * exceptions being set, but that's not correct for the guest debugging
6692 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6693 vmx_set_interrupt_shadow(vcpu
, 0);
6695 kvm_load_guest_xsave_state(vcpu
);
6697 pt_guest_enter(vmx
);
6699 atomic_switch_perf_msrs(vmx
);
6700 if (intel_pmu_lbr_is_enabled(vcpu
))
6701 vmx_passthrough_lbr_msrs(vcpu
);
6703 if (enable_preemption_timer
)
6704 vmx_update_hv_timer(vcpu
);
6706 kvm_wait_lapic_expire(vcpu
);
6709 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6710 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6711 * is no need to worry about the conditional branch over the wrmsr
6712 * being speculatively taken.
6714 x86_spec_ctrl_set_guest(vmx
->spec_ctrl
, 0);
6716 /* The actual VMENTER/EXIT is in the .noinstr.text section. */
6717 vmx_vcpu_enter_exit(vcpu
, vmx
);
6720 * We do not use IBRS in the kernel. If this vCPU has used the
6721 * SPEC_CTRL MSR it may have left it on; save the value and
6722 * turn it off. This is much more efficient than blindly adding
6723 * it to the atomic save/restore list. Especially as the former
6724 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6726 * For non-nested case:
6727 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6731 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6734 if (unlikely(!msr_write_intercepted(vmx
, MSR_IA32_SPEC_CTRL
)))
6735 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
6737 x86_spec_ctrl_restore_host(vmx
->spec_ctrl
, 0);
6739 /* All fields are clean at this point */
6740 if (static_branch_unlikely(&enable_evmcs
)) {
6741 current_evmcs
->hv_clean_fields
|=
6742 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
;
6744 current_evmcs
->hv_vp_id
= kvm_hv_get_vpindex(vcpu
);
6747 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6748 if (vmx
->host_debugctlmsr
)
6749 update_debugctlmsr(vmx
->host_debugctlmsr
);
6751 #ifndef CONFIG_X86_64
6753 * The sysexit path does not restore ds/es, so we must set them to
6754 * a reasonable value ourselves.
6756 * We can't defer this to vmx_prepare_switch_to_host() since that
6757 * function may be executed in interrupt context, which saves and
6758 * restore segments around it, nullifying its effect.
6760 loadsegment(ds
, __USER_DS
);
6761 loadsegment(es
, __USER_DS
);
6764 vmx_register_cache_reset(vcpu
);
6768 kvm_load_host_xsave_state(vcpu
);
6770 if (is_guest_mode(vcpu
)) {
6772 * Track VMLAUNCH/VMRESUME that have made past guest state
6775 if (vmx
->nested
.nested_run_pending
&&
6776 !vmx
->exit_reason
.failed_vmentry
)
6777 ++vcpu
->stat
.nested_run
;
6779 vmx
->nested
.nested_run_pending
= 0;
6782 vmx
->idt_vectoring_info
= 0;
6784 if (unlikely(vmx
->fail
)) {
6785 vmx
->exit_reason
.full
= 0xdead;
6786 return EXIT_FASTPATH_NONE
;
6789 vmx
->exit_reason
.full
= vmcs_read32(VM_EXIT_REASON
);
6790 if (unlikely((u16
)vmx
->exit_reason
.basic
== EXIT_REASON_MCE_DURING_VMENTRY
))
6791 kvm_machine_check();
6793 if (likely(!vmx
->exit_reason
.failed_vmentry
))
6794 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6796 trace_kvm_exit(vmx
->exit_reason
.full
, vcpu
, KVM_ISA_VMX
);
6798 if (unlikely(vmx
->exit_reason
.failed_vmentry
))
6799 return EXIT_FASTPATH_NONE
;
6801 vmx
->loaded_vmcs
->launched
= 1;
6803 vmx_recover_nmi_blocking(vmx
);
6804 vmx_complete_interrupts(vmx
);
6806 if (is_guest_mode(vcpu
))
6807 return EXIT_FASTPATH_NONE
;
6809 return vmx_exit_handlers_fastpath(vcpu
);
6812 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6814 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6817 vmx_destroy_pml_buffer(vmx
);
6818 free_vpid(vmx
->vpid
);
6819 nested_vmx_free_vcpu(vcpu
);
6820 free_loaded_vmcs(vmx
->loaded_vmcs
);
6823 static int vmx_create_vcpu(struct kvm_vcpu
*vcpu
)
6825 struct vmx_uret_msr
*tsx_ctrl
;
6826 struct vcpu_vmx
*vmx
;
6829 BUILD_BUG_ON(offsetof(struct vcpu_vmx
, vcpu
) != 0);
6834 vmx
->vpid
= allocate_vpid();
6837 * If PML is turned on, failure on enabling PML just results in failure
6838 * of creating the vcpu, therefore we can simplify PML logic (by
6839 * avoiding dealing with cases, such as enabling PML partially on vcpus
6840 * for the guest), etc.
6843 vmx
->pml_pg
= alloc_page(GFP_KERNEL_ACCOUNT
| __GFP_ZERO
);
6848 for (i
= 0; i
< kvm_nr_uret_msrs
; ++i
) {
6849 vmx
->guest_uret_msrs
[i
].data
= 0;
6850 vmx
->guest_uret_msrs
[i
].mask
= -1ull;
6852 if (boot_cpu_has(X86_FEATURE_RTM
)) {
6854 * TSX_CTRL_CPUID_CLEAR is handled in the CPUID interception.
6855 * Keep the host value unchanged to avoid changing CPUID bits
6856 * under the host kernel's feet.
6858 tsx_ctrl
= vmx_find_uret_msr(vmx
, MSR_IA32_TSX_CTRL
);
6860 tsx_ctrl
->mask
= ~(u64
)TSX_CTRL_CPUID_CLEAR
;
6863 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
6867 /* The MSR bitmap starts with all ones */
6868 bitmap_fill(vmx
->shadow_msr_intercept
.read
, MAX_POSSIBLE_PASSTHROUGH_MSRS
);
6869 bitmap_fill(vmx
->shadow_msr_intercept
.write
, MAX_POSSIBLE_PASSTHROUGH_MSRS
);
6871 vmx_disable_intercept_for_msr(vcpu
, MSR_IA32_TSC
, MSR_TYPE_R
);
6872 #ifdef CONFIG_X86_64
6873 vmx_disable_intercept_for_msr(vcpu
, MSR_FS_BASE
, MSR_TYPE_RW
);
6874 vmx_disable_intercept_for_msr(vcpu
, MSR_GS_BASE
, MSR_TYPE_RW
);
6875 vmx_disable_intercept_for_msr(vcpu
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
6877 vmx_disable_intercept_for_msr(vcpu
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
6878 vmx_disable_intercept_for_msr(vcpu
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
6879 vmx_disable_intercept_for_msr(vcpu
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
6880 if (kvm_cstate_in_guest(vcpu
->kvm
)) {
6881 vmx_disable_intercept_for_msr(vcpu
, MSR_CORE_C1_RES
, MSR_TYPE_R
);
6882 vmx_disable_intercept_for_msr(vcpu
, MSR_CORE_C3_RESIDENCY
, MSR_TYPE_R
);
6883 vmx_disable_intercept_for_msr(vcpu
, MSR_CORE_C6_RESIDENCY
, MSR_TYPE_R
);
6884 vmx_disable_intercept_for_msr(vcpu
, MSR_CORE_C7_RESIDENCY
, MSR_TYPE_R
);
6887 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6889 vmx_vcpu_load(vcpu
, cpu
);
6894 if (cpu_need_virtualize_apic_accesses(vcpu
)) {
6895 err
= alloc_apic_access_page(vcpu
->kvm
);
6900 if (enable_ept
&& !enable_unrestricted_guest
) {
6901 err
= init_rmode_identity_map(vcpu
->kvm
);
6907 memcpy(&vmx
->nested
.msrs
, &vmcs_config
.nested
, sizeof(vmx
->nested
.msrs
));
6909 memset(&vmx
->nested
.msrs
, 0, sizeof(vmx
->nested
.msrs
));
6911 vcpu_setup_sgx_lepubkeyhash(vcpu
);
6913 vmx
->nested
.posted_intr_nv
= -1;
6914 vmx
->nested
.current_vmptr
= -1ull;
6915 vmx
->nested
.hv_evmcs_vmptr
= EVMPTR_INVALID
;
6917 vcpu
->arch
.microcode_version
= 0x100000000ULL
;
6918 vmx
->msr_ia32_feature_control_valid_bits
= FEAT_CTL_LOCKED
;
6921 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6922 * or POSTED_INTR_WAKEUP_VECTOR.
6924 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
6925 vmx
->pi_desc
.sn
= 1;
6930 free_loaded_vmcs(vmx
->loaded_vmcs
);
6932 vmx_destroy_pml_buffer(vmx
);
6934 free_vpid(vmx
->vpid
);
6938 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6939 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n"
6941 static int vmx_vm_init(struct kvm
*kvm
)
6944 kvm
->arch
.pause_in_guest
= true;
6946 if (boot_cpu_has(X86_BUG_L1TF
) && enable_ept
) {
6947 switch (l1tf_mitigation
) {
6948 case L1TF_MITIGATION_OFF
:
6949 case L1TF_MITIGATION_FLUSH_NOWARN
:
6950 /* 'I explicitly don't care' is set */
6952 case L1TF_MITIGATION_FLUSH
:
6953 case L1TF_MITIGATION_FLUSH_NOSMT
:
6954 case L1TF_MITIGATION_FULL
:
6956 * Warn upon starting the first VM in a potentially
6957 * insecure environment.
6959 if (sched_smt_active())
6960 pr_warn_once(L1TF_MSG_SMT
);
6961 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
)
6962 pr_warn_once(L1TF_MSG_L1D
);
6964 case L1TF_MITIGATION_FULL_FORCE
:
6965 /* Flush is enforced */
6972 static int __init
vmx_check_processor_compat(void)
6974 struct vmcs_config vmcs_conf
;
6975 struct vmx_capability vmx_cap
;
6977 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL
) ||
6978 !this_cpu_has(X86_FEATURE_VMX
)) {
6979 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id());
6983 if (setup_vmcs_config(&vmcs_conf
, &vmx_cap
) < 0)
6986 nested_vmx_setup_ctls_msrs(&vmcs_conf
.nested
, vmx_cap
.ept
);
6987 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6988 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6989 smp_processor_id());
6995 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7000 /* We wanted to honor guest CD/MTRR/PAT, but doing so could result in
7001 * memory aliases with conflicting memory types and sometimes MCEs.
7002 * We have to be careful as to what are honored and when.
7004 * For MMIO, guest CD/MTRR are ignored. The EPT memory type is set to
7005 * UC. The effective memory type is UC or WC depending on guest PAT.
7006 * This was historically the source of MCEs and we want to be
7009 * When there is no need to deal with noncoherent DMA (e.g., no VT-d
7010 * or VT-d has snoop control), guest CD/MTRR/PAT are all ignored. The
7011 * EPT memory type is set to WB. The effective memory type is forced
7014 * Otherwise, we trust guest. Guest CD/MTRR/PAT are all honored. The
7015 * EPT memory type is used to emulate guest CD/MTRR.
7019 cache
= MTRR_TYPE_UNCACHABLE
;
7023 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
7024 ipat
= VMX_EPT_IPAT_BIT
;
7025 cache
= MTRR_TYPE_WRBACK
;
7029 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
7030 ipat
= VMX_EPT_IPAT_BIT
;
7031 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
7032 cache
= MTRR_TYPE_WRBACK
;
7034 cache
= MTRR_TYPE_UNCACHABLE
;
7038 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
7041 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
7044 static void vmcs_set_secondary_exec_control(struct vcpu_vmx
*vmx
, u32 new_ctl
)
7047 * These bits in the secondary execution controls field
7048 * are dynamic, the others are mostly based on the hypervisor
7049 * architecture and the guest's CPUID. Do not touch the
7053 SECONDARY_EXEC_SHADOW_VMCS
|
7054 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
7055 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
7056 SECONDARY_EXEC_DESC
;
7058 u32 cur_ctl
= secondary_exec_controls_get(vmx
);
7060 secondary_exec_controls_set(vmx
, (new_ctl
& ~mask
) | (cur_ctl
& mask
));
7064 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
7065 * (indicating "allowed-1") if they are supported in the guest's CPUID.
7067 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
7069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7070 struct kvm_cpuid_entry2
*entry
;
7072 vmx
->nested
.msrs
.cr0_fixed1
= 0xffffffff;
7073 vmx
->nested
.msrs
.cr4_fixed1
= X86_CR4_PCE
;
7075 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
7076 if (entry && (entry->_reg & (_cpuid_mask))) \
7077 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
7080 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
7081 cr4_fixed1_update(X86_CR4_VME
, edx
, feature_bit(VME
));
7082 cr4_fixed1_update(X86_CR4_PVI
, edx
, feature_bit(VME
));
7083 cr4_fixed1_update(X86_CR4_TSD
, edx
, feature_bit(TSC
));
7084 cr4_fixed1_update(X86_CR4_DE
, edx
, feature_bit(DE
));
7085 cr4_fixed1_update(X86_CR4_PSE
, edx
, feature_bit(PSE
));
7086 cr4_fixed1_update(X86_CR4_PAE
, edx
, feature_bit(PAE
));
7087 cr4_fixed1_update(X86_CR4_MCE
, edx
, feature_bit(MCE
));
7088 cr4_fixed1_update(X86_CR4_PGE
, edx
, feature_bit(PGE
));
7089 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, feature_bit(FXSR
));
7090 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, feature_bit(XMM
));
7091 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, feature_bit(VMX
));
7092 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, feature_bit(SMX
));
7093 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, feature_bit(PCID
));
7094 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, feature_bit(XSAVE
));
7096 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7097 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, feature_bit(FSGSBASE
));
7098 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, feature_bit(SMEP
));
7099 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, feature_bit(SMAP
));
7100 cr4_fixed1_update(X86_CR4_PKE
, ecx
, feature_bit(PKU
));
7101 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, feature_bit(UMIP
));
7102 cr4_fixed1_update(X86_CR4_LA57
, ecx
, feature_bit(LA57
));
7104 #undef cr4_fixed1_update
7107 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu
*vcpu
)
7109 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7111 if (kvm_mpx_supported()) {
7112 bool mpx_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_MPX
);
7115 vmx
->nested
.msrs
.entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
7116 vmx
->nested
.msrs
.exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
7118 vmx
->nested
.msrs
.entry_ctls_high
&= ~VM_ENTRY_LOAD_BNDCFGS
;
7119 vmx
->nested
.msrs
.exit_ctls_high
&= ~VM_EXIT_CLEAR_BNDCFGS
;
7124 static void update_intel_pt_cfg(struct kvm_vcpu
*vcpu
)
7126 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7127 struct kvm_cpuid_entry2
*best
= NULL
;
7130 for (i
= 0; i
< PT_CPUID_LEAVES
; i
++) {
7131 best
= kvm_find_cpuid_entry(vcpu
, 0x14, i
);
7134 vmx
->pt_desc
.caps
[CPUID_EAX
+ i
*PT_CPUID_REGS_NUM
] = best
->eax
;
7135 vmx
->pt_desc
.caps
[CPUID_EBX
+ i
*PT_CPUID_REGS_NUM
] = best
->ebx
;
7136 vmx
->pt_desc
.caps
[CPUID_ECX
+ i
*PT_CPUID_REGS_NUM
] = best
->ecx
;
7137 vmx
->pt_desc
.caps
[CPUID_EDX
+ i
*PT_CPUID_REGS_NUM
] = best
->edx
;
7140 /* Get the number of configurable Address Ranges for filtering */
7141 vmx
->pt_desc
.addr_range
= intel_pt_validate_cap(vmx
->pt_desc
.caps
,
7142 PT_CAP_num_address_ranges
);
7144 /* Initialize and clear the no dependency bits */
7145 vmx
->pt_desc
.ctl_bitmask
= ~(RTIT_CTL_TRACEEN
| RTIT_CTL_OS
|
7146 RTIT_CTL_USR
| RTIT_CTL_TSC_EN
| RTIT_CTL_DISRETC
);
7149 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise
7150 * will inject an #GP
7152 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_cr3_filtering
))
7153 vmx
->pt_desc
.ctl_bitmask
&= ~RTIT_CTL_CR3EN
;
7156 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and
7157 * PSBFreq can be set
7159 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_psb_cyc
))
7160 vmx
->pt_desc
.ctl_bitmask
&= ~(RTIT_CTL_CYCLEACC
|
7161 RTIT_CTL_CYC_THRESH
| RTIT_CTL_PSB_FREQ
);
7164 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and
7165 * MTCFreq can be set
7167 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_mtc
))
7168 vmx
->pt_desc
.ctl_bitmask
&= ~(RTIT_CTL_MTC_EN
|
7169 RTIT_CTL_BRANCH_EN
| RTIT_CTL_MTC_RANGE
);
7171 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */
7172 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_ptwrite
))
7173 vmx
->pt_desc
.ctl_bitmask
&= ~(RTIT_CTL_FUP_ON_PTW
|
7176 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */
7177 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_power_event_trace
))
7178 vmx
->pt_desc
.ctl_bitmask
&= ~RTIT_CTL_PWR_EVT_EN
;
7180 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */
7181 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_topa_output
))
7182 vmx
->pt_desc
.ctl_bitmask
&= ~RTIT_CTL_TOPA
;
7184 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabricEn can be set */
7185 if (intel_pt_validate_cap(vmx
->pt_desc
.caps
, PT_CAP_output_subsys
))
7186 vmx
->pt_desc
.ctl_bitmask
&= ~RTIT_CTL_FABRIC_EN
;
7188 /* unmask address range configure area */
7189 for (i
= 0; i
< vmx
->pt_desc
.addr_range
; i
++)
7190 vmx
->pt_desc
.ctl_bitmask
&= ~(0xfULL
<< (32 + i
* 4));
7193 static void vmx_vcpu_after_set_cpuid(struct kvm_vcpu
*vcpu
)
7195 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7197 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */
7198 vcpu
->arch
.xsaves_enabled
= false;
7200 vmx_setup_uret_msrs(vmx
);
7202 if (cpu_has_secondary_exec_ctrls())
7203 vmcs_set_secondary_exec_control(vmx
,
7204 vmx_secondary_exec_control(vmx
));
7206 if (nested_vmx_allowed(vcpu
))
7207 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
7208 FEAT_CTL_VMX_ENABLED_INSIDE_SMX
|
7209 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX
;
7211 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
7212 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX
|
7213 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX
);
7215 if (nested_vmx_allowed(vcpu
)) {
7216 nested_vmx_cr_fixed1_bits_update(vcpu
);
7217 nested_vmx_entry_exit_ctls_update(vcpu
);
7220 if (boot_cpu_has(X86_FEATURE_INTEL_PT
) &&
7221 guest_cpuid_has(vcpu
, X86_FEATURE_INTEL_PT
))
7222 update_intel_pt_cfg(vcpu
);
7224 if (boot_cpu_has(X86_FEATURE_RTM
)) {
7225 struct vmx_uret_msr
*msr
;
7226 msr
= vmx_find_uret_msr(vmx
, MSR_IA32_TSX_CTRL
);
7228 bool enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RTM
);
7229 vmx_set_guest_uret_msr(vmx
, msr
, enabled
? 0 : TSX_CTRL_RTM_DISABLE
);
7233 set_cr4_guest_host_mask(vmx
);
7235 vmx_write_encls_bitmap(vcpu
, NULL
);
7236 if (guest_cpuid_has(vcpu
, X86_FEATURE_SGX
))
7237 vmx
->msr_ia32_feature_control_valid_bits
|= FEAT_CTL_SGX_ENABLED
;
7239 vmx
->msr_ia32_feature_control_valid_bits
&= ~FEAT_CTL_SGX_ENABLED
;
7241 if (guest_cpuid_has(vcpu
, X86_FEATURE_SGX_LC
))
7242 vmx
->msr_ia32_feature_control_valid_bits
|=
7243 FEAT_CTL_SGX_LC_ENABLED
;
7245 vmx
->msr_ia32_feature_control_valid_bits
&=
7246 ~FEAT_CTL_SGX_LC_ENABLED
;
7248 /* Refresh #PF interception to account for MAXPHYADDR changes. */
7249 vmx_update_exception_bitmap(vcpu
);
7252 static __init
void vmx_set_cpu_caps(void)
7258 kvm_cpu_cap_set(X86_FEATURE_VMX
);
7261 if (kvm_mpx_supported())
7262 kvm_cpu_cap_check_and_set(X86_FEATURE_MPX
);
7263 if (!cpu_has_vmx_invpcid())
7264 kvm_cpu_cap_clear(X86_FEATURE_INVPCID
);
7265 if (vmx_pt_mode_is_host_guest())
7266 kvm_cpu_cap_check_and_set(X86_FEATURE_INTEL_PT
);
7269 kvm_cpu_cap_clear(X86_FEATURE_SGX
);
7270 kvm_cpu_cap_clear(X86_FEATURE_SGX_LC
);
7271 kvm_cpu_cap_clear(X86_FEATURE_SGX1
);
7272 kvm_cpu_cap_clear(X86_FEATURE_SGX2
);
7275 if (vmx_umip_emulated())
7276 kvm_cpu_cap_set(X86_FEATURE_UMIP
);
7280 if (!cpu_has_vmx_xsaves())
7281 kvm_cpu_cap_clear(X86_FEATURE_XSAVES
);
7283 /* CPUID 0x80000001 and 0x7 (RDPID) */
7284 if (!cpu_has_vmx_rdtscp()) {
7285 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP
);
7286 kvm_cpu_cap_clear(X86_FEATURE_RDPID
);
7289 if (cpu_has_vmx_waitpkg())
7290 kvm_cpu_cap_check_and_set(X86_FEATURE_WAITPKG
);
7293 static void vmx_request_immediate_exit(struct kvm_vcpu
*vcpu
)
7295 to_vmx(vcpu
)->req_immediate_exit
= true;
7298 static int vmx_check_intercept_io(struct kvm_vcpu
*vcpu
,
7299 struct x86_instruction_info
*info
)
7301 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7302 unsigned short port
;
7306 if (info
->intercept
== x86_intercept_in
||
7307 info
->intercept
== x86_intercept_ins
) {
7308 port
= info
->src_val
;
7309 size
= info
->dst_bytes
;
7311 port
= info
->dst_val
;
7312 size
= info
->src_bytes
;
7316 * If the 'use IO bitmaps' VM-execution control is 0, IO instruction
7317 * VM-exits depend on the 'unconditional IO exiting' VM-execution
7320 * Otherwise, IO instruction VM-exits are controlled by the IO bitmaps.
7322 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7323 intercept
= nested_cpu_has(vmcs12
,
7324 CPU_BASED_UNCOND_IO_EXITING
);
7326 intercept
= nested_vmx_check_io_bitmaps(vcpu
, port
, size
);
7328 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7329 return intercept
? X86EMUL_UNHANDLEABLE
: X86EMUL_CONTINUE
;
7332 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7333 struct x86_instruction_info
*info
,
7334 enum x86_intercept_stage stage
,
7335 struct x86_exception
*exception
)
7337 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7339 switch (info
->intercept
) {
7341 * RDPID causes #UD if disabled through secondary execution controls.
7342 * Because it is marked as EmulateOnUD, we need to intercept it here.
7343 * Note, RDPID is hidden behind ENABLE_RDTSCP.
7345 case x86_intercept_rdpid
:
7346 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_RDTSCP
)) {
7347 exception
->vector
= UD_VECTOR
;
7348 exception
->error_code_valid
= false;
7349 return X86EMUL_PROPAGATE_FAULT
;
7353 case x86_intercept_in
:
7354 case x86_intercept_ins
:
7355 case x86_intercept_out
:
7356 case x86_intercept_outs
:
7357 return vmx_check_intercept_io(vcpu
, info
);
7359 case x86_intercept_lgdt
:
7360 case x86_intercept_lidt
:
7361 case x86_intercept_lldt
:
7362 case x86_intercept_ltr
:
7363 case x86_intercept_sgdt
:
7364 case x86_intercept_sidt
:
7365 case x86_intercept_sldt
:
7366 case x86_intercept_str
:
7367 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
))
7368 return X86EMUL_CONTINUE
;
7370 /* FIXME: produce nested vmexit and return X86EMUL_INTERCEPTED. */
7373 /* TODO: check more intercepts... */
7378 return X86EMUL_UNHANDLEABLE
;
7381 #ifdef CONFIG_X86_64
7382 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
7383 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
7384 u64 divisor
, u64
*result
)
7386 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
7388 /* To avoid the overflow on divq */
7389 if (high
>= divisor
)
7392 /* Low hold the result, high hold rem which is discarded */
7393 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
7394 "rm" (divisor
), "0" (low
), "1" (high
));
7400 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
,
7403 struct vcpu_vmx
*vmx
;
7404 u64 tscl
, guest_tscl
, delta_tsc
, lapic_timer_advance_cycles
;
7405 struct kvm_timer
*ktimer
= &vcpu
->arch
.apic
->lapic_timer
;
7409 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
7410 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
7411 lapic_timer_advance_cycles
= nsec_to_cycles(vcpu
,
7412 ktimer
->timer_advance_ns
);
7414 if (delta_tsc
> lapic_timer_advance_cycles
)
7415 delta_tsc
-= lapic_timer_advance_cycles
;
7419 /* Convert to host delta tsc if tsc scaling is enabled */
7420 if (vcpu
->arch
.l1_tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
7421 delta_tsc
&& u64_shl_div_u64(delta_tsc
,
7422 kvm_tsc_scaling_ratio_frac_bits
,
7423 vcpu
->arch
.l1_tsc_scaling_ratio
, &delta_tsc
))
7427 * If the delta tsc can't fit in the 32 bit after the multi shift,
7428 * we can't use the preemption timer.
7429 * It's possible that it fits on later vmentries, but checking
7430 * on every vmentry is costly so we just use an hrtimer.
7432 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
7435 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
7436 *expired
= !delta_tsc
;
7440 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
7442 to_vmx(vcpu
)->hv_deadline_tsc
= -1;
7446 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
7448 if (!kvm_pause_in_guest(vcpu
->kvm
))
7449 shrink_ple_window(vcpu
);
7452 void vmx_update_cpu_dirty_logging(struct kvm_vcpu
*vcpu
)
7454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7456 if (is_guest_mode(vcpu
)) {
7457 vmx
->nested
.update_vmcs01_cpu_dirty_logging
= true;
7462 * Note, cpu_dirty_logging_count can be changed concurrent with this
7463 * code, but in that case another update request will be made and so
7464 * the guest will never run with a stale PML value.
7466 if (vcpu
->kvm
->arch
.cpu_dirty_logging_count
)
7467 secondary_exec_controls_setbit(vmx
, SECONDARY_EXEC_ENABLE_PML
);
7469 secondary_exec_controls_clearbit(vmx
, SECONDARY_EXEC_ENABLE_PML
);
7472 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
7474 if (pi_pre_block(vcpu
))
7477 if (kvm_lapic_hv_timer_in_use(vcpu
))
7478 kvm_lapic_switch_to_sw_timer(vcpu
);
7483 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
7485 if (kvm_x86_ops
.set_hv_timer
)
7486 kvm_lapic_switch_to_hv_timer(vcpu
);
7488 pi_post_block(vcpu
);
7491 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
7493 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
7494 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
7495 FEAT_CTL_LMCE_ENABLED
;
7497 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
7498 ~FEAT_CTL_LMCE_ENABLED
;
7501 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
, bool for_injection
)
7503 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7504 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
7506 return !is_smm(vcpu
);
7509 static int vmx_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
7511 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7513 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
7514 if (vmx
->nested
.smm
.guest_mode
)
7515 nested_vmx_vmexit(vcpu
, -1, 0, 0);
7517 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
7518 vmx
->nested
.vmxon
= false;
7519 vmx_clear_hlt(vcpu
);
7523 static int vmx_leave_smm(struct kvm_vcpu
*vcpu
, const char *smstate
)
7525 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7528 if (vmx
->nested
.smm
.vmxon
) {
7529 vmx
->nested
.vmxon
= true;
7530 vmx
->nested
.smm
.vmxon
= false;
7533 if (vmx
->nested
.smm
.guest_mode
) {
7534 ret
= nested_vmx_enter_non_root_mode(vcpu
, false);
7538 vmx
->nested
.nested_run_pending
= 1;
7539 vmx
->nested
.smm
.guest_mode
= false;
7544 static void vmx_enable_smi_window(struct kvm_vcpu
*vcpu
)
7546 /* RSM will cause a vmexit anyway. */
7549 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu
*vcpu
)
7551 return to_vmx(vcpu
)->nested
.vmxon
&& !is_guest_mode(vcpu
);
7554 static void vmx_migrate_timers(struct kvm_vcpu
*vcpu
)
7556 if (is_guest_mode(vcpu
)) {
7557 struct hrtimer
*timer
= &to_vmx(vcpu
)->nested
.preemption_timer
;
7559 if (hrtimer_try_to_cancel(timer
) == 1)
7560 hrtimer_start_expires(timer
, HRTIMER_MODE_ABS_PINNED
);
7564 static void hardware_unsetup(void)
7566 kvm_set_posted_intr_wakeup_handler(NULL
);
7569 nested_vmx_hardware_unsetup();
7574 static bool vmx_check_apicv_inhibit_reasons(ulong bit
)
7576 ulong supported
= BIT(APICV_INHIBIT_REASON_DISABLE
) |
7577 BIT(APICV_INHIBIT_REASON_HYPERV
);
7579 return supported
& BIT(bit
);
7582 static struct kvm_x86_ops vmx_x86_ops __initdata
= {
7583 .hardware_unsetup
= hardware_unsetup
,
7585 .hardware_enable
= hardware_enable
,
7586 .hardware_disable
= hardware_disable
,
7587 .cpu_has_accelerated_tpr
= report_flexpriority
,
7588 .has_emulated_msr
= vmx_has_emulated_msr
,
7590 .vm_size
= sizeof(struct kvm_vmx
),
7591 .vm_init
= vmx_vm_init
,
7593 .vcpu_create
= vmx_create_vcpu
,
7594 .vcpu_free
= vmx_free_vcpu
,
7595 .vcpu_reset
= vmx_vcpu_reset
,
7597 .prepare_guest_switch
= vmx_prepare_switch_to_guest
,
7598 .vcpu_load
= vmx_vcpu_load
,
7599 .vcpu_put
= vmx_vcpu_put
,
7601 .update_exception_bitmap
= vmx_update_exception_bitmap
,
7602 .get_msr_feature
= vmx_get_msr_feature
,
7603 .get_msr
= vmx_get_msr
,
7604 .set_msr
= vmx_set_msr
,
7605 .get_segment_base
= vmx_get_segment_base
,
7606 .get_segment
= vmx_get_segment
,
7607 .set_segment
= vmx_set_segment
,
7608 .get_cpl
= vmx_get_cpl
,
7609 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7610 .set_cr0
= vmx_set_cr0
,
7611 .is_valid_cr4
= vmx_is_valid_cr4
,
7612 .set_cr4
= vmx_set_cr4
,
7613 .set_efer
= vmx_set_efer
,
7614 .get_idt
= vmx_get_idt
,
7615 .set_idt
= vmx_set_idt
,
7616 .get_gdt
= vmx_get_gdt
,
7617 .set_gdt
= vmx_set_gdt
,
7618 .set_dr7
= vmx_set_dr7
,
7619 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
7620 .cache_reg
= vmx_cache_reg
,
7621 .get_rflags
= vmx_get_rflags
,
7622 .set_rflags
= vmx_set_rflags
,
7623 .get_if_flag
= vmx_get_if_flag
,
7625 .tlb_flush_all
= vmx_flush_tlb_all
,
7626 .tlb_flush_current
= vmx_flush_tlb_current
,
7627 .tlb_flush_gva
= vmx_flush_tlb_gva
,
7628 .tlb_flush_guest
= vmx_flush_tlb_guest
,
7630 .run
= vmx_vcpu_run
,
7631 .handle_exit
= vmx_handle_exit
,
7632 .skip_emulated_instruction
= vmx_skip_emulated_instruction
,
7633 .update_emulated_instruction
= vmx_update_emulated_instruction
,
7634 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7635 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7636 .patch_hypercall
= vmx_patch_hypercall
,
7637 .set_irq
= vmx_inject_irq
,
7638 .set_nmi
= vmx_inject_nmi
,
7639 .queue_exception
= vmx_queue_exception
,
7640 .cancel_injection
= vmx_cancel_injection
,
7641 .interrupt_allowed
= vmx_interrupt_allowed
,
7642 .nmi_allowed
= vmx_nmi_allowed
,
7643 .get_nmi_mask
= vmx_get_nmi_mask
,
7644 .set_nmi_mask
= vmx_set_nmi_mask
,
7645 .enable_nmi_window
= vmx_enable_nmi_window
,
7646 .enable_irq_window
= vmx_enable_irq_window
,
7647 .update_cr8_intercept
= vmx_update_cr8_intercept
,
7648 .set_virtual_apic_mode
= vmx_set_virtual_apic_mode
,
7649 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
7650 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
7651 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
7652 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
7653 .check_apicv_inhibit_reasons
= vmx_check_apicv_inhibit_reasons
,
7654 .hwapic_irr_update
= vmx_hwapic_irr_update
,
7655 .hwapic_isr_update
= vmx_hwapic_isr_update
,
7656 .guest_apic_has_interrupt
= vmx_guest_apic_has_interrupt
,
7657 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
7658 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
7659 .dy_apicv_has_pending_interrupt
= pi_has_pending_interrupt
,
7661 .set_tss_addr
= vmx_set_tss_addr
,
7662 .set_identity_map_addr
= vmx_set_identity_map_addr
,
7663 .get_mt_mask
= vmx_get_mt_mask
,
7665 .get_exit_info
= vmx_get_exit_info
,
7667 .vcpu_after_set_cpuid
= vmx_vcpu_after_set_cpuid
,
7669 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7671 .get_l2_tsc_offset
= vmx_get_l2_tsc_offset
,
7672 .get_l2_tsc_multiplier
= vmx_get_l2_tsc_multiplier
,
7673 .write_tsc_offset
= vmx_write_tsc_offset
,
7674 .write_tsc_multiplier
= vmx_write_tsc_multiplier
,
7676 .load_mmu_pgd
= vmx_load_mmu_pgd
,
7678 .check_intercept
= vmx_check_intercept
,
7679 .handle_exit_irqoff
= vmx_handle_exit_irqoff
,
7681 .request_immediate_exit
= vmx_request_immediate_exit
,
7683 .sched_in
= vmx_sched_in
,
7685 .cpu_dirty_log_size
= PML_ENTITY_NUM
,
7686 .update_cpu_dirty_logging
= vmx_update_cpu_dirty_logging
,
7688 .pre_block
= vmx_pre_block
,
7689 .post_block
= vmx_post_block
,
7691 .pmu_ops
= &intel_pmu_ops
,
7692 .nested_ops
= &vmx_nested_ops
,
7694 .update_pi_irte
= pi_update_irte
,
7695 .start_assignment
= vmx_pi_start_assignment
,
7697 #ifdef CONFIG_X86_64
7698 .set_hv_timer
= vmx_set_hv_timer
,
7699 .cancel_hv_timer
= vmx_cancel_hv_timer
,
7702 .setup_mce
= vmx_setup_mce
,
7704 .smi_allowed
= vmx_smi_allowed
,
7705 .enter_smm
= vmx_enter_smm
,
7706 .leave_smm
= vmx_leave_smm
,
7707 .enable_smi_window
= vmx_enable_smi_window
,
7709 .can_emulate_instruction
= vmx_can_emulate_instruction
,
7710 .apic_init_signal_blocked
= vmx_apic_init_signal_blocked
,
7711 .migrate_timers
= vmx_migrate_timers
,
7713 .msr_filter_changed
= vmx_msr_filter_changed
,
7714 .complete_emulated_msr
= kvm_complete_insn_gp
,
7716 .vcpu_deliver_sipi_vector
= kvm_vcpu_deliver_sipi_vector
,
7719 static __init
void vmx_setup_user_return_msrs(void)
7723 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
7724 * will emulate SYSCALL in legacy mode if the vendor string in guest
7725 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
7726 * support this emulation, MSR_STAR is included in the list for i386,
7727 * but is never loaded into hardware. MSR_CSTAR is also never loaded
7728 * into hardware and is here purely for emulation purposes.
7730 const u32 vmx_uret_msrs_list
[] = {
7731 #ifdef CONFIG_X86_64
7732 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
7734 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
7739 BUILD_BUG_ON(ARRAY_SIZE(vmx_uret_msrs_list
) != MAX_NR_USER_RETURN_MSRS
);
7741 for (i
= 0; i
< ARRAY_SIZE(vmx_uret_msrs_list
); ++i
)
7742 kvm_add_user_return_msr(vmx_uret_msrs_list
[i
]);
7745 static __init
int hardware_setup(void)
7747 unsigned long host_bndcfgs
;
7749 int r
, ept_lpage_level
;
7752 host_idt_base
= dt
.address
;
7754 vmx_setup_user_return_msrs();
7756 if (setup_vmcs_config(&vmcs_config
, &vmx_capability
) < 0)
7759 if (boot_cpu_has(X86_FEATURE_NX
))
7760 kvm_enable_efer_bits(EFER_NX
);
7762 if (boot_cpu_has(X86_FEATURE_MPX
)) {
7763 rdmsrl(MSR_IA32_BNDCFGS
, host_bndcfgs
);
7764 WARN_ONCE(host_bndcfgs
, "KVM: BNDCFGS in host will be lost");
7767 if (!cpu_has_vmx_mpx())
7768 supported_xcr0
&= ~(XFEATURE_MASK_BNDREGS
|
7769 XFEATURE_MASK_BNDCSR
);
7771 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7772 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7775 if (!cpu_has_vmx_ept() ||
7776 !cpu_has_vmx_ept_4levels() ||
7777 !cpu_has_vmx_ept_mt_wb() ||
7778 !cpu_has_vmx_invept_global())
7781 /* NX support is required for shadow paging. */
7782 if (!enable_ept
&& !boot_cpu_has(X86_FEATURE_NX
)) {
7783 pr_err_ratelimited("kvm: NX (Execute Disable) not supported\n");
7787 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
7788 enable_ept_ad_bits
= 0;
7790 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
7791 enable_unrestricted_guest
= 0;
7793 if (!cpu_has_vmx_flexpriority())
7794 flexpriority_enabled
= 0;
7796 if (!cpu_has_virtual_nmis())
7800 * set_apic_access_page_addr() is used to reload apic access
7801 * page upon invalidation. No need to do anything if not
7802 * using the APIC_ACCESS_ADDR VMCS field.
7804 if (!flexpriority_enabled
)
7805 vmx_x86_ops
.set_apic_access_page_addr
= NULL
;
7807 if (!cpu_has_vmx_tpr_shadow())
7808 vmx_x86_ops
.update_cr8_intercept
= NULL
;
7810 #if IS_ENABLED(CONFIG_HYPERV)
7811 if (ms_hyperv
.nested_features
& HV_X64_NESTED_GUEST_MAPPING_FLUSH
7813 vmx_x86_ops
.tlb_remote_flush
= hv_remote_flush_tlb
;
7814 vmx_x86_ops
.tlb_remote_flush_with_range
=
7815 hv_remote_flush_tlb_with_range
;
7819 if (!cpu_has_vmx_ple()) {
7822 ple_window_grow
= 0;
7824 ple_window_shrink
= 0;
7827 if (!cpu_has_vmx_apicv())
7830 vmx_x86_ops
.sync_pir_to_irr
= NULL
;
7832 if (cpu_has_vmx_tsc_scaling()) {
7833 kvm_has_tsc_control
= true;
7834 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
7835 kvm_tsc_scaling_ratio_frac_bits
= 48;
7838 kvm_has_bus_lock_exit
= cpu_has_vmx_bus_lock_detection();
7840 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7843 kvm_mmu_set_ept_masks(enable_ept_ad_bits
,
7844 cpu_has_vmx_ept_execute_only());
7847 ept_lpage_level
= 0;
7848 else if (cpu_has_vmx_ept_1g_page())
7849 ept_lpage_level
= PG_LEVEL_1G
;
7850 else if (cpu_has_vmx_ept_2m_page())
7851 ept_lpage_level
= PG_LEVEL_2M
;
7853 ept_lpage_level
= PG_LEVEL_4K
;
7854 kvm_configure_mmu(enable_ept
, 0, vmx_get_max_tdp_level(),
7858 * Only enable PML when hardware supports PML feature, and both EPT
7859 * and EPT A/D bit features are enabled -- PML depends on them to work.
7861 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
7865 vmx_x86_ops
.cpu_dirty_log_size
= 0;
7867 if (!cpu_has_vmx_preemption_timer())
7868 enable_preemption_timer
= false;
7870 if (enable_preemption_timer
) {
7871 u64 use_timer_freq
= 5000ULL * 1000 * 1000;
7874 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
7875 cpu_preemption_timer_multi
=
7876 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
7879 use_timer_freq
= (u64
)tsc_khz
* 1000;
7880 use_timer_freq
>>= cpu_preemption_timer_multi
;
7883 * KVM "disables" the preemption timer by setting it to its max
7884 * value. Don't use the timer if it might cause spurious exits
7885 * at a rate faster than 0.1 Hz (of uninterrupted guest time).
7887 if (use_timer_freq
> 0xffffffffu
/ 10)
7888 enable_preemption_timer
= false;
7891 if (!enable_preemption_timer
) {
7892 vmx_x86_ops
.set_hv_timer
= NULL
;
7893 vmx_x86_ops
.cancel_hv_timer
= NULL
;
7894 vmx_x86_ops
.request_immediate_exit
= __kvm_request_immediate_exit
;
7897 kvm_mce_cap_supported
|= MCG_LMCE_P
;
7899 if (pt_mode
!= PT_MODE_SYSTEM
&& pt_mode
!= PT_MODE_HOST_GUEST
)
7901 if (!enable_ept
|| !cpu_has_vmx_intel_pt())
7902 pt_mode
= PT_MODE_SYSTEM
;
7904 setup_default_sgx_lepubkeyhash();
7907 nested_vmx_setup_ctls_msrs(&vmcs_config
.nested
,
7908 vmx_capability
.ept
);
7910 r
= nested_vmx_hardware_setup(kvm_vmx_exit_handlers
);
7917 r
= alloc_kvm_area();
7919 nested_vmx_hardware_unsetup();
7921 kvm_set_posted_intr_wakeup_handler(pi_wakeup_handler
);
7926 static struct kvm_x86_init_ops vmx_init_ops __initdata
= {
7927 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7928 .disabled_by_bios
= vmx_disabled_by_bios
,
7929 .check_processor_compatibility
= vmx_check_processor_compat
,
7930 .hardware_setup
= hardware_setup
,
7931 .intel_pt_intr_in_guest
= vmx_pt_mode_is_host_guest
,
7933 .runtime_ops
= &vmx_x86_ops
,
7936 static void vmx_cleanup_l1d_flush(void)
7938 if (vmx_l1d_flush_pages
) {
7939 free_pages((unsigned long)vmx_l1d_flush_pages
, L1D_CACHE_ORDER
);
7940 vmx_l1d_flush_pages
= NULL
;
7942 /* Restore state so sysfs ignores VMX */
7943 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
7946 static void vmx_exit(void)
7948 #ifdef CONFIG_KEXEC_CORE
7949 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
7955 #if IS_ENABLED(CONFIG_HYPERV)
7956 if (static_branch_unlikely(&enable_evmcs
)) {
7958 struct hv_vp_assist_page
*vp_ap
;
7960 * Reset everything to support using non-enlightened VMCS
7961 * access later (e.g. when we reload the module with
7962 * enlightened_vmcs=0)
7964 for_each_online_cpu(cpu
) {
7965 vp_ap
= hv_get_vp_assist_page(cpu
);
7970 vp_ap
->nested_control
.features
.directhypercall
= 0;
7971 vp_ap
->current_nested_vmcs
= 0;
7972 vp_ap
->enlighten_vmentry
= 0;
7975 static_branch_disable(&enable_evmcs
);
7978 vmx_cleanup_l1d_flush();
7980 allow_smaller_maxphyaddr
= false;
7982 module_exit(vmx_exit
);
7984 static int __init
vmx_init(void)
7988 #if IS_ENABLED(CONFIG_HYPERV)
7990 * Enlightened VMCS usage should be recommended and the host needs
7991 * to support eVMCS v1 or above. We can also disable eVMCS support
7992 * with module parameter.
7994 if (enlightened_vmcs
&&
7995 ms_hyperv
.hints
& HV_X64_ENLIGHTENED_VMCS_RECOMMENDED
&&
7996 (ms_hyperv
.nested_features
& HV_X64_ENLIGHTENED_VMCS_VERSION
) >=
7997 KVM_EVMCS_VERSION
) {
8000 /* Check that we have assist pages on all online CPUs */
8001 for_each_online_cpu(cpu
) {
8002 if (!hv_get_vp_assist_page(cpu
)) {
8003 enlightened_vmcs
= false;
8008 if (enlightened_vmcs
) {
8009 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
8010 static_branch_enable(&enable_evmcs
);
8013 if (ms_hyperv
.nested_features
& HV_X64_NESTED_DIRECT_FLUSH
)
8014 vmx_x86_ops
.enable_direct_tlbflush
8015 = hv_enable_direct_tlbflush
;
8018 enlightened_vmcs
= false;
8022 r
= kvm_init(&vmx_init_ops
, sizeof(struct vcpu_vmx
),
8023 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8028 * Must be called after kvm_init() so enable_ept is properly set
8029 * up. Hand the parameter mitigation value in which was stored in
8030 * the pre module init parser. If no parameter was given, it will
8031 * contain 'auto' which will be turned into the default 'cond'
8034 r
= vmx_setup_l1d_flush(vmentry_l1d_flush_param
);
8040 for_each_possible_cpu(cpu
) {
8041 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
8046 #ifdef CONFIG_KEXEC_CORE
8047 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8048 crash_vmclear_local_loaded_vmcss
);
8050 vmx_check_vmcs12_offsets();
8053 * Shadow paging doesn't have a (further) performance penalty
8054 * from GUEST_MAXPHYADDR < HOST_MAXPHYADDR so enable it
8058 allow_smaller_maxphyaddr
= true;
8062 module_init(vmx_init
);