arch/x86/kvm/vmx/vmx.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __KVM_X86_VMX_H
   3 #define __KVM_X86_VMX_H
   4
   5 #include <linux/kvm_host.h>
   6
   7 #include <asm/kvm.h>
   8 #include <asm/intel_pt.h>
   9
  10 #include "capabilities.h"
  11 #include "kvm_cache_regs.h"
  12 #include "posted_intr.h"
  13 #include "vmcs.h"
  14 #include "vmx_ops.h"
  15 #include "cpuid.h"
  16 #include "run_flags.h"
  17
  18 #define MSR_TYPE_R      1
  19 #define MSR_TYPE_W      2
  20 #define MSR_TYPE_RW     3
  21
  22 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
  23
  24 #ifdef CONFIG_X86_64
  25 #define MAX_NR_USER_RETURN_MSRS 7
  26 #else
  27 #define MAX_NR_USER_RETURN_MSRS 4
  28 #endif
  29
  30 #define MAX_NR_LOADSTORE_MSRS   8
  31
  32 struct vmx_msrs {
  33         unsigned int            nr;
  34         struct vmx_msr_entry    val[MAX_NR_LOADSTORE_MSRS];
  35 };
  36
  37 struct vmx_uret_msr {
  38         bool load_into_hardware;
  39         u64 data;
  40         u64 mask;
  41 };
  42
  43 enum segment_cache_field {
  44         SEG_FIELD_SEL = 0,
  45         SEG_FIELD_BASE = 1,
  46         SEG_FIELD_LIMIT = 2,
  47         SEG_FIELD_AR = 3,
  48
  49         SEG_FIELD_NR = 4
  50 };
  51
  52 #define RTIT_ADDR_RANGE         4
  53
  54 struct pt_ctx {
  55         u64 ctl;
  56         u64 status;
  57         u64 output_base;
  58         u64 output_mask;
  59         u64 cr3_match;
  60         u64 addr_a[RTIT_ADDR_RANGE];
  61         u64 addr_b[RTIT_ADDR_RANGE];
  62 };
  63
  64 struct pt_desc {
  65         u64 ctl_bitmask;
  66         u32 addr_range;
  67         u32 caps[PT_CPUID_REGS_NUM * PT_CPUID_LEAVES];
  68         struct pt_ctx host;
  69         struct pt_ctx guest;
  70 };
  71
  72 union vmx_exit_reason {
  73         struct {
  74                 u32     basic                   : 16;
  75                 u32     reserved16              : 1;
  76                 u32     reserved17              : 1;
  77                 u32     reserved18              : 1;
  78                 u32     reserved19              : 1;
  79                 u32     reserved20              : 1;
  80                 u32     reserved21              : 1;
  81                 u32     reserved22              : 1;
  82                 u32     reserved23              : 1;
  83                 u32     reserved24              : 1;
  84                 u32     reserved25              : 1;
  85                 u32     bus_lock_detected       : 1;
  86                 u32     enclave_mode            : 1;
  87                 u32     smi_pending_mtf         : 1;
  88                 u32     smi_from_vmx_root       : 1;
  89                 u32     reserved30              : 1;
  90                 u32     failed_vmentry          : 1;
  91         };
  92         u32 full;
  93 };
  94
  95 #define vcpu_to_lbr_desc(vcpu) (&to_vmx(vcpu)->lbr_desc)
  96 #define vcpu_to_lbr_records(vcpu) (&to_vmx(vcpu)->lbr_desc.records)
  97
  98 bool intel_pmu_lbr_is_compatible(struct kvm_vcpu *vcpu);
  99 bool intel_pmu_lbr_is_enabled(struct kvm_vcpu *vcpu);
 100
 101 int intel_pmu_create_guest_lbr_event(struct kvm_vcpu *vcpu);
 102 void vmx_passthrough_lbr_msrs(struct kvm_vcpu *vcpu);
 103
 104 struct lbr_desc {
 105         /* Basic info about guest LBR records. */
 106         struct x86_pmu_lbr records;
 107
 108         /*
 109          * Emulate LBR feature via passthrough LBR registers when the
 110          * per-vcpu guest LBR event is scheduled on the current pcpu.
 111          *
 112          * The records may be inaccurate if the host reclaims the LBR.
 113          */
 114         struct perf_event *event;
 115
 116         /* True if LBRs are marked as not intercepted in the MSR bitmap */
 117         bool msr_passthrough;
 118 };
 119
 120 /*
 121  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 122  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 123  */
 124 struct nested_vmx {
 125         /* Has the level1 guest done vmxon? */
 126         bool vmxon;
 127         gpa_t vmxon_ptr;
 128         bool pml_full;
 129
 130         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 131         gpa_t current_vmptr;
 132         /*
 133          * Cache of the guest's VMCS, existing outside of guest memory.
 134          * Loaded from guest memory during VMPTRLD. Flushed to guest
 135          * memory during VMCLEAR and VMPTRLD.
 136          */
 137         struct vmcs12 *cached_vmcs12;
 138         /*
 139          * Cache of the guest's shadow VMCS, existing outside of guest
 140          * memory. Loaded from guest memory during VM entry. Flushed
 141          * to guest memory during VM exit.
 142          */
 143         struct vmcs12 *cached_shadow_vmcs12;
 144
 145         /*
 146          * Indicates if the shadow vmcs or enlightened vmcs must be updated
 147          * with the data held by struct vmcs12.
 148          */
 149         bool need_vmcs12_to_shadow_sync;
 150         bool dirty_vmcs12;
 151
 152         /*
 153          * Indicates lazily loaded guest state has not yet been decached from
 154          * vmcs02.
 155          */
 156         bool need_sync_vmcs02_to_vmcs12_rare;
 157
 158         /*
 159          * vmcs02 has been initialized, i.e. state that is constant for
 160          * vmcs02 has been written to the backing VMCS.  Initialization
 161          * is delayed until L1 actually attempts to run a nested VM.
 162          */
 163         bool vmcs02_initialized;
 164
 165         bool change_vmcs01_virtual_apic_mode;
 166         bool reload_vmcs01_apic_access_page;
 167         bool update_vmcs01_cpu_dirty_logging;
 168         bool update_vmcs01_apicv_status;
 169
 170         /*
 171          * Enlightened VMCS has been enabled. It does not mean that L1 has to
 172          * use it. However, VMX features available to L1 will be limited based
 173          * on what the enlightened VMCS supports.
 174          */
 175         bool enlightened_vmcs_enabled;
 176
 177         /* L2 must run next, and mustn't decide to exit to L1. */
 178         bool nested_run_pending;
 179
 180         /* Pending MTF VM-exit into L1.  */
 181         bool mtf_pending;
 182
 183         struct loaded_vmcs vmcs02;
 184
 185         /*
 186          * Guest pages referred to in the vmcs02 with host-physical
 187          * pointers, so we must keep them pinned while L2 runs.
 188          */
 189         struct page *apic_access_page;
 190         struct kvm_host_map virtual_apic_map;
 191         struct kvm_host_map pi_desc_map;
 192
 193         struct kvm_host_map msr_bitmap_map;
 194
 195         struct pi_desc *pi_desc;
 196         bool pi_pending;
 197         u16 posted_intr_nv;
 198
 199         struct hrtimer preemption_timer;
 200         u64 preemption_timer_deadline;
 201         bool has_preemption_timer_deadline;
 202         bool preemption_timer_expired;
 203
 204         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 205         u64 vmcs01_debugctl;
 206         u64 vmcs01_guest_bndcfgs;
 207
 208         /* to migrate it to L1 if L2 writes to L1's CR8 directly */
 209         int l1_tpr_threshold;
 210
 211         u16 vpid02;
 212         u16 last_vpid;
 213
 214         struct nested_vmx_msrs msrs;
 215
 216         /* SMM related state */
 217         struct {
 218                 /* in VMX operation on SMM entry? */
 219                 bool vmxon;
 220                 /* in guest mode on SMM entry? */
 221                 bool guest_mode;
 222         } smm;
 223
 224         gpa_t hv_evmcs_vmptr;
 225         struct kvm_host_map hv_evmcs_map;
 226         struct hv_enlightened_vmcs *hv_evmcs;
 227 };
 228
 229 struct vcpu_vmx {
 230         struct kvm_vcpu       vcpu;
 231         u8                    fail;
 232         u8                    x2apic_msr_bitmap_mode;
 233
 234         /*
 235          * If true, host state has been stored in vmx->loaded_vmcs for
 236          * the CPU registers that only need to be switched when transitioning
 237          * to/from the kernel, and the registers have been loaded with guest
 238          * values.  If false, host state is loaded in the CPU registers
 239          * and vmx->loaded_vmcs->host_state is invalid.
 240          */
 241         bool                  guest_state_loaded;
 242
 243         unsigned long         exit_qualification;
 244         u32                   exit_intr_info;
 245         u32                   idt_vectoring_info;
 246         ulong                 rflags;
 247
 248         /*
 249          * User return MSRs are always emulated when enabled in the guest, but
 250          * only loaded into hardware when necessary, e.g. SYSCALL #UDs outside
 251          * of 64-bit mode or if EFER.SCE=1, thus the SYSCALL MSRs don't need to
 252          * be loaded into hardware if those conditions aren't met.
 253          */
 254         struct vmx_uret_msr   guest_uret_msrs[MAX_NR_USER_RETURN_MSRS];
 255         bool                  guest_uret_msrs_loaded;
 256 #ifdef CONFIG_X86_64
 257         u64                   msr_host_kernel_gs_base;
 258         u64                   msr_guest_kernel_gs_base;
 259 #endif
 260
 261         u64                   spec_ctrl;
 262         u32                   msr_ia32_umwait_control;
 263
 264         /*
 265          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 266          * non-nested (L1) guest, it always points to vmcs01. For a nested
 267          * guest (L2), it points to a different VMCS.
 268          */
 269         struct loaded_vmcs    vmcs01;
 270         struct loaded_vmcs   *loaded_vmcs;
 271
 272         struct msr_autoload {
 273                 struct vmx_msrs guest;
 274                 struct vmx_msrs host;
 275         } msr_autoload;
 276
 277         struct msr_autostore {
 278                 struct vmx_msrs guest;
 279         } msr_autostore;
 280
 281         struct {
 282                 int vm86_active;
 283                 ulong save_rflags;
 284                 struct kvm_segment segs[8];
 285         } rmode;
 286         struct {
 287                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 288                 struct kvm_save_segment {
 289                         u16 selector;
 290                         unsigned long base;
 291                         u32 limit;
 292                         u32 ar;
 293                 } seg[8];
 294         } segment_cache;
 295         int vpid;
 296         bool emulation_required;
 297
 298         union vmx_exit_reason exit_reason;
 299
 300         /* Posted interrupt descriptor */
 301         struct pi_desc pi_desc;
 302
 303         /* Support for a guest hypervisor (nested VMX) */
 304         struct nested_vmx nested;
 305
 306         /* Dynamic PLE window. */
 307         unsigned int ple_window;
 308         bool ple_window_dirty;
 309
 310         bool req_immediate_exit;
 311
 312         /* Support for PML */
 313 #define PML_ENTITY_NUM          512
 314         struct page *pml_pg;
 315
 316         /* apic deadline value in host tsc */
 317         u64 hv_deadline_tsc;
 318
 319         unsigned long host_debugctlmsr;
 320
 321         /*
 322          * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
 323          * msr_ia32_feature_control. FEAT_CTL_LOCKED is always included
 324          * in msr_ia32_feature_control_valid_bits.
 325          */
 326         u64 msr_ia32_feature_control;
 327         u64 msr_ia32_feature_control_valid_bits;
 328         /* SGX Launch Control public key hash */
 329         u64 msr_ia32_sgxlepubkeyhash[4];
 330         u64 msr_ia32_mcu_opt_ctrl;
 331         bool disable_fb_clear;
 332
 333         struct pt_desc pt_desc;
 334         struct lbr_desc lbr_desc;
 335
 336         /* Save desired MSR intercept (read: pass-through) state */
 337 #define MAX_POSSIBLE_PASSTHROUGH_MSRS   13
 338         struct {
 339                 DECLARE_BITMAP(read, MAX_POSSIBLE_PASSTHROUGH_MSRS);
 340                 DECLARE_BITMAP(write, MAX_POSSIBLE_PASSTHROUGH_MSRS);
 341         } shadow_msr_intercept;
 342 };
 343
 344 struct kvm_vmx {
 345         struct kvm kvm;
 346
 347         unsigned int tss_addr;
 348         bool ept_identity_pagetable_done;
 349         gpa_t ept_identity_map_addr;
 350 };
 351
 352 bool nested_vmx_allowed(struct kvm_vcpu *vcpu);
 353 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu,
 354                         struct loaded_vmcs *buddy);
 355 int allocate_vpid(void);
 356 void free_vpid(int vpid);
 357 void vmx_set_constant_host_state(struct vcpu_vmx *vmx);
 358 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu);
 359 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel,
 360                         unsigned long fs_base, unsigned long gs_base);
 361 int vmx_get_cpl(struct kvm_vcpu *vcpu);
 362 bool vmx_emulation_required(struct kvm_vcpu *vcpu);
 363 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu);
 364 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags);
 365 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu);
 366 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask);
 367 int vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer);
 368 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
 369 void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 370 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx);
 371 void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 372 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 373 void __vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg);
 374 u64 construct_eptp(struct kvm_vcpu *vcpu, hpa_t root_hpa, int root_level);
 375
 376 bool vmx_guest_inject_ac(struct kvm_vcpu *vcpu);
 377 void vmx_update_exception_bitmap(struct kvm_vcpu *vcpu);
 378 bool vmx_nmi_blocked(struct kvm_vcpu *vcpu);
 379 bool vmx_interrupt_blocked(struct kvm_vcpu *vcpu);
 380 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu);
 381 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked);
 382 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu);
 383 struct vmx_uret_msr *vmx_find_uret_msr(struct vcpu_vmx *vmx, u32 msr);
 384 void pt_update_intercept_for_msr(struct kvm_vcpu *vcpu);
 385 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp);
 386 void vmx_spec_ctrl_restore_host(struct vcpu_vmx *vmx, unsigned int flags);
 387 unsigned int __vmx_vcpu_run_flags(struct vcpu_vmx *vmx);
 388 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs,
 389                     unsigned int flags);
 390 int vmx_find_loadstore_msr_slot(struct vmx_msrs *m, u32 msr);
 391 void vmx_ept_load_pdptrs(struct kvm_vcpu *vcpu);
 392
 393 void vmx_disable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
 394 void vmx_enable_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr, int type);
 395
 396 u64 vmx_get_l2_tsc_offset(struct kvm_vcpu *vcpu);
 397 u64 vmx_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu);
 398
 399 static inline void vmx_set_intercept_for_msr(struct kvm_vcpu *vcpu, u32 msr,
 400                                              int type, bool value)
 401 {
 402         if (value)
 403                 vmx_enable_intercept_for_msr(vcpu, msr, type);
 404         else
 405                 vmx_disable_intercept_for_msr(vcpu, msr, type);
 406 }
 407
 408 void vmx_update_cpu_dirty_logging(struct kvm_vcpu *vcpu);
 409
 410 static inline bool vmx_test_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
 411 {
 412         int f = sizeof(unsigned long);
 413
 414         if (msr <= 0x1fff)
 415                 return test_bit(msr, msr_bitmap + 0x000 / f);
 416         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 417                 return test_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
 418         return true;
 419 }
 420
 421 static inline bool vmx_test_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
 422 {
 423         int f = sizeof(unsigned long);
 424
 425         if (msr <= 0x1fff)
 426                 return test_bit(msr, msr_bitmap + 0x800 / f);
 427         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 428                 return test_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
 429         return true;
 430 }
 431
 432 static inline void vmx_clear_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
 433 {
 434         int f = sizeof(unsigned long);
 435
 436         if (msr <= 0x1fff)
 437                 __clear_bit(msr, msr_bitmap + 0x000 / f);
 438         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 439                 __clear_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
 440 }
 441
 442 static inline void vmx_clear_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
 443 {
 444         int f = sizeof(unsigned long);
 445
 446         if (msr <= 0x1fff)
 447                 __clear_bit(msr, msr_bitmap + 0x800 / f);
 448         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 449                 __clear_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
 450 }
 451
 452 static inline void vmx_set_msr_bitmap_read(ulong *msr_bitmap, u32 msr)
 453 {
 454         int f = sizeof(unsigned long);
 455
 456         if (msr <= 0x1fff)
 457                 __set_bit(msr, msr_bitmap + 0x000 / f);
 458         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 459                 __set_bit(msr & 0x1fff, msr_bitmap + 0x400 / f);
 460 }
 461
 462 static inline void vmx_set_msr_bitmap_write(ulong *msr_bitmap, u32 msr)
 463 {
 464         int f = sizeof(unsigned long);
 465
 466         if (msr <= 0x1fff)
 467                 __set_bit(msr, msr_bitmap + 0x800 / f);
 468         else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff))
 469                 __set_bit(msr & 0x1fff, msr_bitmap + 0xc00 / f);
 470 }
 471
 472
 473 static inline u8 vmx_get_rvi(void)
 474 {
 475         return vmcs_read16(GUEST_INTR_STATUS) & 0xff;
 476 }
 477
 478 #define BUILD_CONTROLS_SHADOW(lname, uname)                                 \
 479 static inline void lname##_controls_set(struct vcpu_vmx *vmx, u32 val)      \
 480 {                                                                           \
 481         if (vmx->loaded_vmcs->controls_shadow.lname != val) {               \
 482                 vmcs_write32(uname, val);                                   \
 483                 vmx->loaded_vmcs->controls_shadow.lname = val;              \
 484         }                                                                   \
 485 }                                                                           \
 486 static inline u32 __##lname##_controls_get(struct loaded_vmcs *vmcs)        \
 487 {                                                                           \
 488         return vmcs->controls_shadow.lname;                                 \
 489 }                                                                           \
 490 static inline u32 lname##_controls_get(struct vcpu_vmx *vmx)                \
 491 {                                                                           \
 492         return __##lname##_controls_get(vmx->loaded_vmcs);                  \
 493 }                                                                           \
 494 static inline void lname##_controls_setbit(struct vcpu_vmx *vmx, u32 val)   \
 495 {                                                                           \
 496         lname##_controls_set(vmx, lname##_controls_get(vmx) | val);         \
 497 }                                                                           \
 498 static inline void lname##_controls_clearbit(struct vcpu_vmx *vmx, u32 val) \
 499 {                                                                           \
 500         lname##_controls_set(vmx, lname##_controls_get(vmx) & ~val);        \
 501 }
 502 BUILD_CONTROLS_SHADOW(vm_entry, VM_ENTRY_CONTROLS)
 503 BUILD_CONTROLS_SHADOW(vm_exit, VM_EXIT_CONTROLS)
 504 BUILD_CONTROLS_SHADOW(pin, PIN_BASED_VM_EXEC_CONTROL)
 505 BUILD_CONTROLS_SHADOW(exec, CPU_BASED_VM_EXEC_CONTROL)
 506 BUILD_CONTROLS_SHADOW(secondary_exec, SECONDARY_VM_EXEC_CONTROL)
 507
 508 static inline void vmx_register_cache_reset(struct kvm_vcpu *vcpu)
 509 {
 510         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
 511                                   | (1 << VCPU_EXREG_RFLAGS)
 512                                   | (1 << VCPU_EXREG_PDPTR)
 513                                   | (1 << VCPU_EXREG_SEGMENTS)
 514                                   | (1 << VCPU_EXREG_CR0)
 515                                   | (1 << VCPU_EXREG_CR3)
 516                                   | (1 << VCPU_EXREG_CR4)
 517                                   | (1 << VCPU_EXREG_EXIT_INFO_1)
 518                                   | (1 << VCPU_EXREG_EXIT_INFO_2));
 519         vcpu->arch.regs_dirty = 0;
 520 }
 521
 522 static inline struct kvm_vmx *to_kvm_vmx(struct kvm *kvm)
 523 {
 524         return container_of(kvm, struct kvm_vmx, kvm);
 525 }
 526
 527 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 528 {
 529         return container_of(vcpu, struct vcpu_vmx, vcpu);
 530 }
 531
 532 static inline unsigned long vmx_get_exit_qual(struct kvm_vcpu *vcpu)
 533 {
 534         struct vcpu_vmx *vmx = to_vmx(vcpu);
 535
 536         if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_1)) {
 537                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_1);
 538                 vmx->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
 539         }
 540         return vmx->exit_qualification;
 541 }
 542
 543 static inline u32 vmx_get_intr_info(struct kvm_vcpu *vcpu)
 544 {
 545         struct vcpu_vmx *vmx = to_vmx(vcpu);
 546
 547         if (!kvm_register_is_available(vcpu, VCPU_EXREG_EXIT_INFO_2)) {
 548                 kvm_register_mark_available(vcpu, VCPU_EXREG_EXIT_INFO_2);
 549                 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
 550         }
 551         return vmx->exit_intr_info;
 552 }
 553
 554 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags);
 555 void free_vmcs(struct vmcs *vmcs);
 556 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 557 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs);
 558 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs);
 559
 560 static inline struct vmcs *alloc_vmcs(bool shadow)
 561 {
 562         return alloc_vmcs_cpu(shadow, raw_smp_processor_id(),
 563                               GFP_KERNEL_ACCOUNT);
 564 }
 565
 566 static inline bool vmx_has_waitpkg(struct vcpu_vmx *vmx)
 567 {
 568         return secondary_exec_controls_get(vmx) &
 569                 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE;
 570 }
 571
 572 static inline bool vmx_need_pf_intercept(struct kvm_vcpu *vcpu)
 573 {
 574         if (!enable_ept)
 575                 return true;
 576
 577         return allow_smaller_maxphyaddr && cpuid_maxphyaddr(vcpu) < boot_cpu_data.x86_phys_bits;
 578 }
 579
 580 static inline bool is_unrestricted_guest(struct kvm_vcpu *vcpu)
 581 {
 582         return enable_unrestricted_guest && (!is_guest_mode(vcpu) ||
 583             (secondary_exec_controls_get(to_vmx(vcpu)) &
 584             SECONDARY_EXEC_UNRESTRICTED_GUEST));
 585 }
 586
 587 bool __vmx_guest_state_valid(struct kvm_vcpu *vcpu);
 588 static inline bool vmx_guest_state_valid(struct kvm_vcpu *vcpu)
 589 {
 590         return is_unrestricted_guest(vcpu) || __vmx_guest_state_valid(vcpu);
 591 }
 592
 593 void dump_vmcs(struct kvm_vcpu *vcpu);
 594
 595 #endif /* __KVM_X86_VMX_H */