2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
246 u64 vm_function_control
;
248 u64 eoi_exit_bitmap0
;
249 u64 eoi_exit_bitmap1
;
250 u64 eoi_exit_bitmap2
;
251 u64 eoi_exit_bitmap3
;
252 u64 eptp_list_address
;
254 u64 guest_physical_address
;
255 u64 vmcs_link_pointer
;
257 u64 guest_ia32_debugctl
;
260 u64 guest_ia32_perf_global_ctrl
;
268 u64 host_ia32_perf_global_ctrl
;
269 u64 padding64
[8]; /* room for future expansion */
271 * To allow migration of L1 (complete with its L2 guests) between
272 * machines of different natural widths (32 or 64 bit), we cannot have
273 * unsigned long fields with no explict size. We use u64 (aliased
274 * natural_width) instead. Luckily, x86 is little-endian.
276 natural_width cr0_guest_host_mask
;
277 natural_width cr4_guest_host_mask
;
278 natural_width cr0_read_shadow
;
279 natural_width cr4_read_shadow
;
280 natural_width cr3_target_value0
;
281 natural_width cr3_target_value1
;
282 natural_width cr3_target_value2
;
283 natural_width cr3_target_value3
;
284 natural_width exit_qualification
;
285 natural_width guest_linear_address
;
286 natural_width guest_cr0
;
287 natural_width guest_cr3
;
288 natural_width guest_cr4
;
289 natural_width guest_es_base
;
290 natural_width guest_cs_base
;
291 natural_width guest_ss_base
;
292 natural_width guest_ds_base
;
293 natural_width guest_fs_base
;
294 natural_width guest_gs_base
;
295 natural_width guest_ldtr_base
;
296 natural_width guest_tr_base
;
297 natural_width guest_gdtr_base
;
298 natural_width guest_idtr_base
;
299 natural_width guest_dr7
;
300 natural_width guest_rsp
;
301 natural_width guest_rip
;
302 natural_width guest_rflags
;
303 natural_width guest_pending_dbg_exceptions
;
304 natural_width guest_sysenter_esp
;
305 natural_width guest_sysenter_eip
;
306 natural_width host_cr0
;
307 natural_width host_cr3
;
308 natural_width host_cr4
;
309 natural_width host_fs_base
;
310 natural_width host_gs_base
;
311 natural_width host_tr_base
;
312 natural_width host_gdtr_base
;
313 natural_width host_idtr_base
;
314 natural_width host_ia32_sysenter_esp
;
315 natural_width host_ia32_sysenter_eip
;
316 natural_width host_rsp
;
317 natural_width host_rip
;
318 natural_width paddingl
[8]; /* room for future expansion */
319 u32 pin_based_vm_exec_control
;
320 u32 cpu_based_vm_exec_control
;
321 u32 exception_bitmap
;
322 u32 page_fault_error_code_mask
;
323 u32 page_fault_error_code_match
;
324 u32 cr3_target_count
;
325 u32 vm_exit_controls
;
326 u32 vm_exit_msr_store_count
;
327 u32 vm_exit_msr_load_count
;
328 u32 vm_entry_controls
;
329 u32 vm_entry_msr_load_count
;
330 u32 vm_entry_intr_info_field
;
331 u32 vm_entry_exception_error_code
;
332 u32 vm_entry_instruction_len
;
334 u32 secondary_vm_exec_control
;
335 u32 vm_instruction_error
;
337 u32 vm_exit_intr_info
;
338 u32 vm_exit_intr_error_code
;
339 u32 idt_vectoring_info_field
;
340 u32 idt_vectoring_error_code
;
341 u32 vm_exit_instruction_len
;
342 u32 vmx_instruction_info
;
349 u32 guest_ldtr_limit
;
351 u32 guest_gdtr_limit
;
352 u32 guest_idtr_limit
;
353 u32 guest_es_ar_bytes
;
354 u32 guest_cs_ar_bytes
;
355 u32 guest_ss_ar_bytes
;
356 u32 guest_ds_ar_bytes
;
357 u32 guest_fs_ar_bytes
;
358 u32 guest_gs_ar_bytes
;
359 u32 guest_ldtr_ar_bytes
;
360 u32 guest_tr_ar_bytes
;
361 u32 guest_interruptibility_info
;
362 u32 guest_activity_state
;
363 u32 guest_sysenter_cs
;
364 u32 host_ia32_sysenter_cs
;
365 u32 vmx_preemption_timer_value
;
366 u32 padding32
[7]; /* room for future expansion */
367 u16 virtual_processor_id
;
369 u16 guest_es_selector
;
370 u16 guest_cs_selector
;
371 u16 guest_ss_selector
;
372 u16 guest_ds_selector
;
373 u16 guest_fs_selector
;
374 u16 guest_gs_selector
;
375 u16 guest_ldtr_selector
;
376 u16 guest_tr_selector
;
377 u16 guest_intr_status
;
379 u16 host_es_selector
;
380 u16 host_cs_selector
;
381 u16 host_ss_selector
;
382 u16 host_ds_selector
;
383 u16 host_fs_selector
;
384 u16 host_gs_selector
;
385 u16 host_tr_selector
;
389 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
390 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
391 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
393 #define VMCS12_REVISION 0x11e57ed0
396 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
397 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
398 * current implementation, 4K are reserved to avoid future complications.
400 #define VMCS12_SIZE 0x1000
402 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
404 struct list_head list
;
406 struct loaded_vmcs vmcs02
;
410 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
411 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
414 /* Has the level1 guest done vmxon? */
419 /* The guest-physical address of the current VMCS L1 keeps for L2 */
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMCLEAR and VMPTRLD.
426 struct vmcs12
*cached_vmcs12
;
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
431 bool sync_shadow_vmcs
;
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool
;
436 bool change_vmcs01_virtual_x2apic_mode
;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending
;
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
443 struct page
*apic_access_page
;
444 struct page
*virtual_apic_page
;
445 struct page
*pi_desc_page
;
446 struct pi_desc
*pi_desc
;
450 unsigned long *msr_bitmap
;
452 struct hrtimer preemption_timer
;
453 bool preemption_timer_expired
;
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
466 u32 nested_vmx_procbased_ctls_low
;
467 u32 nested_vmx_procbased_ctls_high
;
468 u32 nested_vmx_secondary_ctls_low
;
469 u32 nested_vmx_secondary_ctls_high
;
470 u32 nested_vmx_pinbased_ctls_low
;
471 u32 nested_vmx_pinbased_ctls_high
;
472 u32 nested_vmx_exit_ctls_low
;
473 u32 nested_vmx_exit_ctls_high
;
474 u32 nested_vmx_entry_ctls_low
;
475 u32 nested_vmx_entry_ctls_high
;
476 u32 nested_vmx_misc_low
;
477 u32 nested_vmx_misc_high
;
478 u32 nested_vmx_ept_caps
;
479 u32 nested_vmx_vpid_caps
;
480 u64 nested_vmx_basic
;
481 u64 nested_vmx_cr0_fixed0
;
482 u64 nested_vmx_cr0_fixed1
;
483 u64 nested_vmx_cr4_fixed0
;
484 u64 nested_vmx_cr4_fixed1
;
485 u64 nested_vmx_vmcs_enum
;
486 u64 nested_vmx_vmfunc_controls
;
489 #define POSTED_INTR_ON 0
490 #define POSTED_INTR_SN 1
492 /* Posted-Interrupt Descriptor */
494 u32 pir
[8]; /* Posted interrupt requested */
497 /* bit 256 - Outstanding Notification */
499 /* bit 257 - Suppress Notification */
501 /* bit 271:258 - Reserved */
503 /* bit 279:272 - Notification Vector */
505 /* bit 287:280 - Reserved */
507 /* bit 319:288 - Notification Destination */
515 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
517 return test_and_set_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
523 return test_and_clear_bit(POSTED_INTR_ON
,
524 (unsigned long *)&pi_desc
->control
);
527 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
529 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
532 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
534 return clear_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
540 return set_bit(POSTED_INTR_SN
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
546 clear_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_on(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_ON
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
558 return test_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
563 struct kvm_vcpu vcpu
;
564 unsigned long host_rsp
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
579 u32 secondary_exec_control
;
582 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
583 * non-nested (L1) guest, it always points to vmcs01. For a nested
584 * guest (L2), it points to a different VMCS.
586 struct loaded_vmcs vmcs01
;
587 struct loaded_vmcs
*loaded_vmcs
;
588 bool __launched
; /* temporary, used in vmx_vcpu_run */
589 struct msr_autoload
{
591 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
592 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
596 u16 fs_sel
, gs_sel
, ldt_sel
;
600 int gs_ldt_reload_needed
;
601 int fs_reload_needed
;
602 u64 msr_host_bndcfgs
;
603 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
604 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
609 struct kvm_segment segs
[8];
612 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
613 struct kvm_save_segment
{
621 bool emulation_required
;
625 /* Posted interrupt descriptor */
626 struct pi_desc pi_desc
;
628 /* Support for a guest hypervisor (nested VMX) */
629 struct nested_vmx nested
;
631 /* Dynamic PLE window. */
633 bool ple_window_dirty
;
635 /* Support for PML */
636 #define PML_ENTITY_NUM 512
639 /* apic deadline value in host tsc */
642 u64 current_tsc_ratio
;
647 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
648 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
649 * in msr_ia32_feature_control_valid_bits.
651 u64 msr_ia32_feature_control
;
652 u64 msr_ia32_feature_control_valid_bits
;
655 enum segment_cache_field
{
664 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
666 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
669 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
671 return &(to_vmx(vcpu
)->pi_desc
);
674 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
675 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
676 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
677 [number##_HIGH] = VMCS12_OFFSET(name)+4
680 static unsigned long shadow_read_only_fields
[] = {
682 * We do NOT shadow fields that are modified when L0
683 * traps and emulates any vmx instruction (e.g. VMPTRLD,
684 * VMXON...) executed by L1.
685 * For example, VM_INSTRUCTION_ERROR is read
686 * by L1 if a vmx instruction fails (part of the error path).
687 * Note the code assumes this logic. If for some reason
688 * we start shadowing these fields then we need to
689 * force a shadow sync when L0 emulates vmx instructions
690 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
691 * by nested_vmx_failValid)
695 VM_EXIT_INSTRUCTION_LEN
,
696 IDT_VECTORING_INFO_FIELD
,
697 IDT_VECTORING_ERROR_CODE
,
698 VM_EXIT_INTR_ERROR_CODE
,
700 GUEST_LINEAR_ADDRESS
,
701 GUEST_PHYSICAL_ADDRESS
703 static int max_shadow_read_only_fields
=
704 ARRAY_SIZE(shadow_read_only_fields
);
706 static unsigned long shadow_read_write_fields
[] = {
713 GUEST_INTERRUPTIBILITY_INFO
,
726 CPU_BASED_VM_EXEC_CONTROL
,
727 VM_ENTRY_EXCEPTION_ERROR_CODE
,
728 VM_ENTRY_INTR_INFO_FIELD
,
729 VM_ENTRY_INSTRUCTION_LEN
,
730 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 static int max_shadow_read_write_fields
=
737 ARRAY_SIZE(shadow_read_write_fields
);
739 static const unsigned short vmcs_field_to_offset_table
[] = {
740 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
741 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
742 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
743 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
744 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
745 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
746 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
747 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
748 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
749 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
750 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
751 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
770 FIELD64(EPT_POINTER
, ept_pointer
),
771 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
772 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
773 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
774 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
775 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
776 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
777 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
778 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
779 FIELD64(PML_ADDRESS
, pml_address
),
780 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
781 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
782 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
783 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
784 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
785 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
786 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
787 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
788 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
789 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
790 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
791 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
792 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
793 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
794 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
795 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
796 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
797 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
798 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
799 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
800 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
801 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
802 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
803 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
804 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
805 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
806 FIELD(TPR_THRESHOLD
, tpr_threshold
),
807 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
808 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
809 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
810 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
811 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
812 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
813 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
814 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
815 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
816 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
817 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
818 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
819 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
820 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
821 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
822 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
823 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
824 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
825 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
826 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
827 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
828 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
829 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
830 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
831 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
832 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
833 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
834 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
835 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
836 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
837 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
838 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
839 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
840 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
841 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
842 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
843 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
844 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
845 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
846 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
847 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
848 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
849 FIELD(GUEST_CR0
, guest_cr0
),
850 FIELD(GUEST_CR3
, guest_cr3
),
851 FIELD(GUEST_CR4
, guest_cr4
),
852 FIELD(GUEST_ES_BASE
, guest_es_base
),
853 FIELD(GUEST_CS_BASE
, guest_cs_base
),
854 FIELD(GUEST_SS_BASE
, guest_ss_base
),
855 FIELD(GUEST_DS_BASE
, guest_ds_base
),
856 FIELD(GUEST_FS_BASE
, guest_fs_base
),
857 FIELD(GUEST_GS_BASE
, guest_gs_base
),
858 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
859 FIELD(GUEST_TR_BASE
, guest_tr_base
),
860 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
861 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
862 FIELD(GUEST_DR7
, guest_dr7
),
863 FIELD(GUEST_RSP
, guest_rsp
),
864 FIELD(GUEST_RIP
, guest_rip
),
865 FIELD(GUEST_RFLAGS
, guest_rflags
),
866 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
867 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
868 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
869 FIELD(HOST_CR0
, host_cr0
),
870 FIELD(HOST_CR3
, host_cr3
),
871 FIELD(HOST_CR4
, host_cr4
),
872 FIELD(HOST_FS_BASE
, host_fs_base
),
873 FIELD(HOST_GS_BASE
, host_gs_base
),
874 FIELD(HOST_TR_BASE
, host_tr_base
),
875 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
876 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
877 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
878 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
879 FIELD(HOST_RSP
, host_rsp
),
880 FIELD(HOST_RIP
, host_rip
),
883 static inline short vmcs_field_to_offset(unsigned long field
)
885 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
887 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
888 vmcs_field_to_offset_table
[field
] == 0)
891 return vmcs_field_to_offset_table
[field
];
894 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
896 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
899 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
900 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
901 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
902 static bool vmx_xsaves_supported(void);
903 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
904 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
905 struct kvm_segment
*var
, int seg
);
906 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
907 struct kvm_segment
*var
, int seg
);
908 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
909 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
910 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
911 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
912 static int alloc_identity_pagetable(struct kvm
*kvm
);
913 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
914 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
915 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
918 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
919 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
921 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
922 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
924 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
927 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
928 * can find which vCPU should be waken up.
930 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
931 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
936 VMX_MSR_BITMAP_LEGACY
,
937 VMX_MSR_BITMAP_LONGMODE
,
938 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
939 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
940 VMX_MSR_BITMAP_LEGACY_X2APIC
,
941 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
947 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
949 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
950 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
951 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
952 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
953 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
954 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
955 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
956 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
957 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
958 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
960 static bool cpu_has_load_ia32_efer
;
961 static bool cpu_has_load_perf_global_ctrl
;
963 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
964 static DEFINE_SPINLOCK(vmx_vpid_lock
);
966 static struct vmcs_config
{
971 u32 pin_based_exec_ctrl
;
972 u32 cpu_based_exec_ctrl
;
973 u32 cpu_based_2nd_exec_ctrl
;
978 static struct vmx_capability
{
983 #define VMX_SEGMENT_FIELD(seg) \
984 [VCPU_SREG_##seg] = { \
985 .selector = GUEST_##seg##_SELECTOR, \
986 .base = GUEST_##seg##_BASE, \
987 .limit = GUEST_##seg##_LIMIT, \
988 .ar_bytes = GUEST_##seg##_AR_BYTES, \
991 static const struct kvm_vmx_segment_field
{
996 } kvm_vmx_segment_fields
[] = {
997 VMX_SEGMENT_FIELD(CS
),
998 VMX_SEGMENT_FIELD(DS
),
999 VMX_SEGMENT_FIELD(ES
),
1000 VMX_SEGMENT_FIELD(FS
),
1001 VMX_SEGMENT_FIELD(GS
),
1002 VMX_SEGMENT_FIELD(SS
),
1003 VMX_SEGMENT_FIELD(TR
),
1004 VMX_SEGMENT_FIELD(LDTR
),
1007 static u64 host_efer
;
1009 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1012 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1013 * away by decrementing the array size.
1015 static const u32 vmx_msr_index
[] = {
1016 #ifdef CONFIG_X86_64
1017 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1019 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1022 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1024 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1025 INTR_INFO_VALID_MASK
)) ==
1026 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1029 static inline bool is_debug(u32 intr_info
)
1031 return is_exception_n(intr_info
, DB_VECTOR
);
1034 static inline bool is_breakpoint(u32 intr_info
)
1036 return is_exception_n(intr_info
, BP_VECTOR
);
1039 static inline bool is_page_fault(u32 intr_info
)
1041 return is_exception_n(intr_info
, PF_VECTOR
);
1044 static inline bool is_no_device(u32 intr_info
)
1046 return is_exception_n(intr_info
, NM_VECTOR
);
1049 static inline bool is_invalid_opcode(u32 intr_info
)
1051 return is_exception_n(intr_info
, UD_VECTOR
);
1054 static inline bool is_external_interrupt(u32 intr_info
)
1056 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1057 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1060 static inline bool is_machine_check(u32 intr_info
)
1062 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1063 INTR_INFO_VALID_MASK
)) ==
1064 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1067 static inline bool cpu_has_vmx_msr_bitmap(void)
1069 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1072 static inline bool cpu_has_vmx_tpr_shadow(void)
1074 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1077 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1079 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1082 static inline bool cpu_has_secondary_exec_ctrls(void)
1084 return vmcs_config
.cpu_based_exec_ctrl
&
1085 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1088 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1090 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1091 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1094 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1096 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1097 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1100 static inline bool cpu_has_vmx_apic_register_virt(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1106 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1113 * Comment's format: document - errata name - stepping - processor name.
1115 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1117 static u32 vmx_preemption_cpu_tfms
[] = {
1118 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1120 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1121 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1122 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1124 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1127 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1129 * 320767.pdf - AAP86 - B1 -
1130 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1133 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1135 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1137 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1139 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1140 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1141 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1145 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1147 u32 eax
= cpuid_eax(0x00000001), i
;
1149 /* Clear the reserved bits */
1150 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1151 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1152 if (eax
== vmx_preemption_cpu_tfms
[i
])
1158 static inline bool cpu_has_vmx_preemption_timer(void)
1160 return vmcs_config
.pin_based_exec_ctrl
&
1161 PIN_BASED_VMX_PREEMPTION_TIMER
;
1164 static inline bool cpu_has_vmx_posted_intr(void)
1166 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1167 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1170 static inline bool cpu_has_vmx_apicv(void)
1172 return cpu_has_vmx_apic_register_virt() &&
1173 cpu_has_vmx_virtual_intr_delivery() &&
1174 cpu_has_vmx_posted_intr();
1177 static inline bool cpu_has_vmx_flexpriority(void)
1179 return cpu_has_vmx_tpr_shadow() &&
1180 cpu_has_vmx_virtualize_apic_accesses();
1183 static inline bool cpu_has_vmx_ept_execute_only(void)
1185 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1188 static inline bool cpu_has_vmx_ept_2m_page(void)
1190 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1193 static inline bool cpu_has_vmx_ept_1g_page(void)
1195 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1198 static inline bool cpu_has_vmx_ept_4levels(void)
1200 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1203 static inline bool cpu_has_vmx_ept_mt_wb(void)
1205 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1208 static inline bool cpu_has_vmx_ept_5levels(void)
1210 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1213 static inline bool cpu_has_vmx_ept_ad_bits(void)
1215 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1218 static inline bool cpu_has_vmx_invept_context(void)
1220 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1223 static inline bool cpu_has_vmx_invept_global(void)
1225 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1228 static inline bool cpu_has_vmx_invvpid_single(void)
1230 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1233 static inline bool cpu_has_vmx_invvpid_global(void)
1235 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1238 static inline bool cpu_has_vmx_invvpid(void)
1240 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1243 static inline bool cpu_has_vmx_ept(void)
1245 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1246 SECONDARY_EXEC_ENABLE_EPT
;
1249 static inline bool cpu_has_vmx_unrestricted_guest(void)
1251 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1252 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1255 static inline bool cpu_has_vmx_ple(void)
1257 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1258 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1261 static inline bool cpu_has_vmx_basic_inout(void)
1263 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1266 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1268 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1271 static inline bool cpu_has_vmx_vpid(void)
1273 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1274 SECONDARY_EXEC_ENABLE_VPID
;
1277 static inline bool cpu_has_vmx_rdtscp(void)
1279 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1280 SECONDARY_EXEC_RDTSCP
;
1283 static inline bool cpu_has_vmx_invpcid(void)
1285 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1286 SECONDARY_EXEC_ENABLE_INVPCID
;
1289 static inline bool cpu_has_vmx_wbinvd_exit(void)
1291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1292 SECONDARY_EXEC_WBINVD_EXITING
;
1295 static inline bool cpu_has_vmx_shadow_vmcs(void)
1298 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1299 /* check if the cpu supports writing r/o exit information fields */
1300 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1303 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1304 SECONDARY_EXEC_SHADOW_VMCS
;
1307 static inline bool cpu_has_vmx_pml(void)
1309 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1312 static inline bool cpu_has_vmx_tsc_scaling(void)
1314 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1315 SECONDARY_EXEC_TSC_SCALING
;
1318 static inline bool cpu_has_vmx_vmfunc(void)
1320 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1321 SECONDARY_EXEC_ENABLE_VMFUNC
;
1324 static inline bool report_flexpriority(void)
1326 return flexpriority_enabled
;
1329 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1331 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1334 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1336 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1339 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1341 return (vmcs12
->cpu_based_vm_exec_control
&
1342 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1343 (vmcs12
->secondary_vm_exec_control
& bit
);
1346 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1348 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1351 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1353 return vmcs12
->pin_based_vm_exec_control
&
1354 PIN_BASED_VMX_PREEMPTION_TIMER
;
1357 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1359 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1362 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1364 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1367 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1369 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1372 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1374 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1377 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1379 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1382 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1384 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1387 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1389 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1392 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1394 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1397 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1399 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1402 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1404 return nested_cpu_has_vmfunc(vmcs12
) &&
1405 (vmcs12
->vm_function_control
&
1406 VMX_VMFUNC_EPTP_SWITCHING
);
1409 static inline bool is_nmi(u32 intr_info
)
1411 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1412 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1415 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1417 unsigned long exit_qualification
);
1418 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1419 struct vmcs12
*vmcs12
,
1420 u32 reason
, unsigned long qualification
);
1422 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1426 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1427 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1432 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1438 } operand
= { vpid
, 0, gva
};
1440 asm volatile (__ex(ASM_VMX_INVVPID
)
1441 /* CF==1 or ZF==1 --> rc = -1 */
1442 "; ja 1f ; ud2 ; 1:"
1443 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1446 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1450 } operand
= {eptp
, gpa
};
1452 asm volatile (__ex(ASM_VMX_INVEPT
)
1453 /* CF==1 or ZF==1 --> rc = -1 */
1454 "; ja 1f ; ud2 ; 1:\n"
1455 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1458 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1462 i
= __find_msr_index(vmx
, msr
);
1464 return &vmx
->guest_msrs
[i
];
1468 static void vmcs_clear(struct vmcs
*vmcs
)
1470 u64 phys_addr
= __pa(vmcs
);
1473 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1474 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1477 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1481 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1483 vmcs_clear(loaded_vmcs
->vmcs
);
1484 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1485 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1486 loaded_vmcs
->cpu
= -1;
1487 loaded_vmcs
->launched
= 0;
1490 static void vmcs_load(struct vmcs
*vmcs
)
1492 u64 phys_addr
= __pa(vmcs
);
1495 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1496 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1499 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1503 #ifdef CONFIG_KEXEC_CORE
1505 * This bitmap is used to indicate whether the vmclear
1506 * operation is enabled on all cpus. All disabled by
1509 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1511 static inline void crash_enable_local_vmclear(int cpu
)
1513 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1516 static inline void crash_disable_local_vmclear(int cpu
)
1518 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1521 static inline int crash_local_vmclear_enabled(int cpu
)
1523 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1526 static void crash_vmclear_local_loaded_vmcss(void)
1528 int cpu
= raw_smp_processor_id();
1529 struct loaded_vmcs
*v
;
1531 if (!crash_local_vmclear_enabled(cpu
))
1534 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1535 loaded_vmcss_on_cpu_link
)
1536 vmcs_clear(v
->vmcs
);
1539 static inline void crash_enable_local_vmclear(int cpu
) { }
1540 static inline void crash_disable_local_vmclear(int cpu
) { }
1541 #endif /* CONFIG_KEXEC_CORE */
1543 static void __loaded_vmcs_clear(void *arg
)
1545 struct loaded_vmcs
*loaded_vmcs
= arg
;
1546 int cpu
= raw_smp_processor_id();
1548 if (loaded_vmcs
->cpu
!= cpu
)
1549 return; /* vcpu migration can race with cpu offline */
1550 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1551 per_cpu(current_vmcs
, cpu
) = NULL
;
1552 crash_disable_local_vmclear(cpu
);
1553 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1556 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1557 * is before setting loaded_vmcs->vcpu to -1 which is done in
1558 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1559 * then adds the vmcs into percpu list before it is deleted.
1563 loaded_vmcs_init(loaded_vmcs
);
1564 crash_enable_local_vmclear(cpu
);
1567 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1569 int cpu
= loaded_vmcs
->cpu
;
1572 smp_call_function_single(cpu
,
1573 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1576 static inline void vpid_sync_vcpu_single(int vpid
)
1581 if (cpu_has_vmx_invvpid_single())
1582 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1585 static inline void vpid_sync_vcpu_global(void)
1587 if (cpu_has_vmx_invvpid_global())
1588 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1591 static inline void vpid_sync_context(int vpid
)
1593 if (cpu_has_vmx_invvpid_single())
1594 vpid_sync_vcpu_single(vpid
);
1596 vpid_sync_vcpu_global();
1599 static inline void ept_sync_global(void)
1601 if (cpu_has_vmx_invept_global())
1602 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1605 static inline void ept_sync_context(u64 eptp
)
1608 if (cpu_has_vmx_invept_context())
1609 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1615 static __always_inline
void vmcs_check16(unsigned long field
)
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1618 "16-bit accessor invalid for 64-bit field");
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1620 "16-bit accessor invalid for 64-bit high field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1622 "16-bit accessor invalid for 32-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1624 "16-bit accessor invalid for natural width field");
1627 static __always_inline
void vmcs_check32(unsigned long field
)
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1630 "32-bit accessor invalid for 16-bit field");
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1632 "32-bit accessor invalid for natural width field");
1635 static __always_inline
void vmcs_check64(unsigned long field
)
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1638 "64-bit accessor invalid for 16-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1640 "64-bit accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1642 "64-bit accessor invalid for 32-bit field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1644 "64-bit accessor invalid for natural width field");
1647 static __always_inline
void vmcs_checkl(unsigned long field
)
1649 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1650 "Natural width accessor invalid for 16-bit field");
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1652 "Natural width accessor invalid for 64-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1654 "Natural width accessor invalid for 64-bit high field");
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1656 "Natural width accessor invalid for 32-bit field");
1659 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1661 unsigned long value
;
1663 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1664 : "=a"(value
) : "d"(field
) : "cc");
1668 static __always_inline u16
vmcs_read16(unsigned long field
)
1670 vmcs_check16(field
);
1671 return __vmcs_readl(field
);
1674 static __always_inline u32
vmcs_read32(unsigned long field
)
1676 vmcs_check32(field
);
1677 return __vmcs_readl(field
);
1680 static __always_inline u64
vmcs_read64(unsigned long field
)
1682 vmcs_check64(field
);
1683 #ifdef CONFIG_X86_64
1684 return __vmcs_readl(field
);
1686 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1690 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1693 return __vmcs_readl(field
);
1696 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1698 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1699 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1703 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1707 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1708 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1709 if (unlikely(error
))
1710 vmwrite_error(field
, value
);
1713 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1715 vmcs_check16(field
);
1716 __vmcs_writel(field
, value
);
1719 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1721 vmcs_check32(field
);
1722 __vmcs_writel(field
, value
);
1725 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1727 vmcs_check64(field
);
1728 __vmcs_writel(field
, value
);
1729 #ifndef CONFIG_X86_64
1731 __vmcs_writel(field
+1, value
>> 32);
1735 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1738 __vmcs_writel(field
, value
);
1741 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1743 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1744 "vmcs_clear_bits does not support 64-bit fields");
1745 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1748 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1750 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1751 "vmcs_set_bits does not support 64-bit fields");
1752 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1755 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1757 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1760 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1762 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1763 vmx
->vm_entry_controls_shadow
= val
;
1766 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1768 if (vmx
->vm_entry_controls_shadow
!= val
)
1769 vm_entry_controls_init(vmx
, val
);
1772 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1774 return vmx
->vm_entry_controls_shadow
;
1778 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1780 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1783 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1785 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1788 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1790 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1793 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1795 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1796 vmx
->vm_exit_controls_shadow
= val
;
1799 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1801 if (vmx
->vm_exit_controls_shadow
!= val
)
1802 vm_exit_controls_init(vmx
, val
);
1805 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1807 return vmx
->vm_exit_controls_shadow
;
1811 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1813 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1816 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1818 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1821 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1823 vmx
->segment_cache
.bitmask
= 0;
1826 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1830 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1832 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1833 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1834 vmx
->segment_cache
.bitmask
= 0;
1836 ret
= vmx
->segment_cache
.bitmask
& mask
;
1837 vmx
->segment_cache
.bitmask
|= mask
;
1841 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1843 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1845 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1846 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1850 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1855 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1859 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1861 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1863 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1864 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1868 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1870 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1872 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1873 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1877 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1881 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1882 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1883 if ((vcpu
->guest_debug
&
1884 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1885 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1886 eb
|= 1u << BP_VECTOR
;
1887 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1890 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1892 /* When we are running a nested L2 guest and L1 specified for it a
1893 * certain exception bitmap, we must trap the same exceptions and pass
1894 * them to L1. When running L2, we will only handle the exceptions
1895 * specified above if L1 did not want them.
1897 if (is_guest_mode(vcpu
))
1898 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1900 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1903 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1904 unsigned long entry
, unsigned long exit
)
1906 vm_entry_controls_clearbit(vmx
, entry
);
1907 vm_exit_controls_clearbit(vmx
, exit
);
1910 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1913 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1917 if (cpu_has_load_ia32_efer
) {
1918 clear_atomic_switch_msr_special(vmx
,
1919 VM_ENTRY_LOAD_IA32_EFER
,
1920 VM_EXIT_LOAD_IA32_EFER
);
1924 case MSR_CORE_PERF_GLOBAL_CTRL
:
1925 if (cpu_has_load_perf_global_ctrl
) {
1926 clear_atomic_switch_msr_special(vmx
,
1927 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1928 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1934 for (i
= 0; i
< m
->nr
; ++i
)
1935 if (m
->guest
[i
].index
== msr
)
1941 m
->guest
[i
] = m
->guest
[m
->nr
];
1942 m
->host
[i
] = m
->host
[m
->nr
];
1943 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1944 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1947 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1948 unsigned long entry
, unsigned long exit
,
1949 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1950 u64 guest_val
, u64 host_val
)
1952 vmcs_write64(guest_val_vmcs
, guest_val
);
1953 vmcs_write64(host_val_vmcs
, host_val
);
1954 vm_entry_controls_setbit(vmx
, entry
);
1955 vm_exit_controls_setbit(vmx
, exit
);
1958 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1959 u64 guest_val
, u64 host_val
)
1962 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1966 if (cpu_has_load_ia32_efer
) {
1967 add_atomic_switch_msr_special(vmx
,
1968 VM_ENTRY_LOAD_IA32_EFER
,
1969 VM_EXIT_LOAD_IA32_EFER
,
1972 guest_val
, host_val
);
1976 case MSR_CORE_PERF_GLOBAL_CTRL
:
1977 if (cpu_has_load_perf_global_ctrl
) {
1978 add_atomic_switch_msr_special(vmx
,
1979 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1980 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1981 GUEST_IA32_PERF_GLOBAL_CTRL
,
1982 HOST_IA32_PERF_GLOBAL_CTRL
,
1983 guest_val
, host_val
);
1987 case MSR_IA32_PEBS_ENABLE
:
1988 /* PEBS needs a quiescent period after being disabled (to write
1989 * a record). Disabling PEBS through VMX MSR swapping doesn't
1990 * provide that period, so a CPU could write host's record into
1993 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1996 for (i
= 0; i
< m
->nr
; ++i
)
1997 if (m
->guest
[i
].index
== msr
)
2000 if (i
== NR_AUTOLOAD_MSRS
) {
2001 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2002 "Can't add msr %x\n", msr
);
2004 } else if (i
== m
->nr
) {
2006 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2007 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2010 m
->guest
[i
].index
= msr
;
2011 m
->guest
[i
].value
= guest_val
;
2012 m
->host
[i
].index
= msr
;
2013 m
->host
[i
].value
= host_val
;
2016 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2018 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2019 u64 ignore_bits
= 0;
2023 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2024 * host CPUID is more efficient than testing guest CPUID
2025 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2027 if (boot_cpu_has(X86_FEATURE_SMEP
))
2028 guest_efer
|= EFER_NX
;
2029 else if (!(guest_efer
& EFER_NX
))
2030 ignore_bits
|= EFER_NX
;
2034 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2036 ignore_bits
|= EFER_SCE
;
2037 #ifdef CONFIG_X86_64
2038 ignore_bits
|= EFER_LMA
| EFER_LME
;
2039 /* SCE is meaningful only in long mode on Intel */
2040 if (guest_efer
& EFER_LMA
)
2041 ignore_bits
&= ~(u64
)EFER_SCE
;
2044 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2047 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2048 * On CPUs that support "load IA32_EFER", always switch EFER
2049 * atomically, since it's faster than switching it manually.
2051 if (cpu_has_load_ia32_efer
||
2052 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2053 if (!(guest_efer
& EFER_LMA
))
2054 guest_efer
&= ~EFER_LME
;
2055 if (guest_efer
!= host_efer
)
2056 add_atomic_switch_msr(vmx
, MSR_EFER
,
2057 guest_efer
, host_efer
);
2060 guest_efer
&= ~ignore_bits
;
2061 guest_efer
|= host_efer
& ignore_bits
;
2063 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2064 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2070 #ifdef CONFIG_X86_32
2072 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2073 * VMCS rather than the segment table. KVM uses this helper to figure
2074 * out the current bases to poke them into the VMCS before entry.
2076 static unsigned long segment_base(u16 selector
)
2078 struct desc_struct
*table
;
2081 if (!(selector
& ~SEGMENT_RPL_MASK
))
2084 table
= get_current_gdt_ro();
2086 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2087 u16 ldt_selector
= kvm_read_ldt();
2089 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2092 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2094 v
= get_desc_base(&table
[selector
>> 3]);
2099 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2101 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2104 if (vmx
->host_state
.loaded
)
2107 vmx
->host_state
.loaded
= 1;
2109 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2110 * allow segment selectors with cpl > 0 or ti == 1.
2112 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2113 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2114 savesegment(fs
, vmx
->host_state
.fs_sel
);
2115 if (!(vmx
->host_state
.fs_sel
& 7)) {
2116 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2117 vmx
->host_state
.fs_reload_needed
= 0;
2119 vmcs_write16(HOST_FS_SELECTOR
, 0);
2120 vmx
->host_state
.fs_reload_needed
= 1;
2122 savesegment(gs
, vmx
->host_state
.gs_sel
);
2123 if (!(vmx
->host_state
.gs_sel
& 7))
2124 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2126 vmcs_write16(HOST_GS_SELECTOR
, 0);
2127 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2130 #ifdef CONFIG_X86_64
2131 savesegment(ds
, vmx
->host_state
.ds_sel
);
2132 savesegment(es
, vmx
->host_state
.es_sel
);
2135 #ifdef CONFIG_X86_64
2136 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2137 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2139 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2140 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2143 #ifdef CONFIG_X86_64
2144 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2145 if (is_long_mode(&vmx
->vcpu
))
2146 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2148 if (boot_cpu_has(X86_FEATURE_MPX
))
2149 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2150 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2151 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2152 vmx
->guest_msrs
[i
].data
,
2153 vmx
->guest_msrs
[i
].mask
);
2156 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2158 if (!vmx
->host_state
.loaded
)
2161 ++vmx
->vcpu
.stat
.host_state_reload
;
2162 vmx
->host_state
.loaded
= 0;
2163 #ifdef CONFIG_X86_64
2164 if (is_long_mode(&vmx
->vcpu
))
2165 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2167 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2168 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2169 #ifdef CONFIG_X86_64
2170 load_gs_index(vmx
->host_state
.gs_sel
);
2172 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2175 if (vmx
->host_state
.fs_reload_needed
)
2176 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2177 #ifdef CONFIG_X86_64
2178 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2179 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2180 loadsegment(es
, vmx
->host_state
.es_sel
);
2183 invalidate_tss_limit();
2184 #ifdef CONFIG_X86_64
2185 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2187 if (vmx
->host_state
.msr_host_bndcfgs
)
2188 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2189 load_fixmap_gdt(raw_smp_processor_id());
2192 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2195 __vmx_load_host_state(vmx
);
2199 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2201 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2202 struct pi_desc old
, new;
2205 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2206 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2207 !kvm_vcpu_apicv_active(vcpu
))
2211 old
.control
= new.control
= pi_desc
->control
;
2214 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2215 * are two possible cases:
2216 * 1. After running 'pre_block', context switch
2217 * happened. For this case, 'sn' was set in
2218 * vmx_vcpu_put(), so we need to clear it here.
2219 * 2. After running 'pre_block', we were blocked,
2220 * and woken up by some other guy. For this case,
2221 * we don't need to do anything, 'pi_post_block'
2222 * will do everything for us. However, we cannot
2223 * check whether it is case #1 or case #2 here
2224 * (maybe, not needed), so we also clear sn here,
2225 * I think it is not a big deal.
2227 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2228 if (vcpu
->cpu
!= cpu
) {
2229 dest
= cpu_physical_id(cpu
);
2231 if (x2apic_enabled())
2234 new.ndst
= (dest
<< 8) & 0xFF00;
2237 /* set 'NV' to 'notification vector' */
2238 new.nv
= POSTED_INTR_VECTOR
;
2241 /* Allow posting non-urgent interrupts */
2243 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2244 new.control
) != old
.control
);
2247 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2249 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2250 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2254 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2255 * vcpu mutex is already taken.
2257 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2259 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2260 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2262 if (!already_loaded
) {
2263 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2264 local_irq_disable();
2265 crash_disable_local_vmclear(cpu
);
2268 * Read loaded_vmcs->cpu should be before fetching
2269 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2270 * See the comments in __loaded_vmcs_clear().
2274 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2275 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2276 crash_enable_local_vmclear(cpu
);
2280 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2281 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2282 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2285 if (!already_loaded
) {
2286 void *gdt
= get_current_gdt_ro();
2287 unsigned long sysenter_esp
;
2289 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2292 * Linux uses per-cpu TSS and GDT, so set these when switching
2293 * processors. See 22.2.4.
2295 vmcs_writel(HOST_TR_BASE
,
2296 (unsigned long)this_cpu_ptr(&cpu_tss
));
2297 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2300 * VM exits change the host TR limit to 0x67 after a VM
2301 * exit. This is okay, since 0x67 covers everything except
2302 * the IO bitmap and have have code to handle the IO bitmap
2303 * being lost after a VM exit.
2305 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2307 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2308 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2310 vmx
->loaded_vmcs
->cpu
= cpu
;
2313 /* Setup TSC multiplier */
2314 if (kvm_has_tsc_control
&&
2315 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2316 decache_tsc_multiplier(vmx
);
2318 vmx_vcpu_pi_load(vcpu
, cpu
);
2319 vmx
->host_pkru
= read_pkru();
2322 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2324 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2326 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2327 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2328 !kvm_vcpu_apicv_active(vcpu
))
2331 /* Set SN when the vCPU is preempted */
2332 if (vcpu
->preempted
)
2336 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2338 vmx_vcpu_pi_put(vcpu
);
2340 __vmx_load_host_state(to_vmx(vcpu
));
2343 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2345 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2348 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2351 * Return the cr0 value that a nested guest would read. This is a combination
2352 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2353 * its hypervisor (cr0_read_shadow).
2355 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2357 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2358 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2360 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2362 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2363 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2366 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2368 unsigned long rflags
, save_rflags
;
2370 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2371 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2372 rflags
= vmcs_readl(GUEST_RFLAGS
);
2373 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2374 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2375 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2376 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2378 to_vmx(vcpu
)->rflags
= rflags
;
2380 return to_vmx(vcpu
)->rflags
;
2383 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2385 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2387 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2388 to_vmx(vcpu
)->rflags
= rflags
;
2389 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2390 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2391 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2393 vmcs_writel(GUEST_RFLAGS
, rflags
);
2395 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2396 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2399 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2401 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2404 if (interruptibility
& GUEST_INTR_STATE_STI
)
2405 ret
|= KVM_X86_SHADOW_INT_STI
;
2406 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2407 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2412 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2414 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2415 u32 interruptibility
= interruptibility_old
;
2417 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2419 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2420 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2421 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2422 interruptibility
|= GUEST_INTR_STATE_STI
;
2424 if ((interruptibility
!= interruptibility_old
))
2425 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2428 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2432 rip
= kvm_rip_read(vcpu
);
2433 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2434 kvm_rip_write(vcpu
, rip
);
2436 /* skipping an emulated instruction also counts */
2437 vmx_set_interrupt_shadow(vcpu
, 0);
2440 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2441 unsigned long exit_qual
)
2443 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2444 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2445 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2447 if (vcpu
->arch
.exception
.has_error_code
) {
2448 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2449 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2452 if (kvm_exception_is_soft(nr
))
2453 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2455 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2457 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2458 vmx_get_nmi_mask(vcpu
))
2459 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2461 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2465 * KVM wants to inject page-faults which it got to the guest. This function
2466 * checks whether in a nested guest, we need to inject them to L1 or L2.
2468 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2470 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2471 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2473 if (nr
== PF_VECTOR
) {
2474 if (vcpu
->arch
.exception
.nested_apf
) {
2475 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2479 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2480 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2481 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2482 * can be written only when inject_pending_event runs. This should be
2483 * conditional on a new capability---if the capability is disabled,
2484 * kvm_multiple_exception would write the ancillary information to
2485 * CR2 or DR6, for backwards ABI-compatibility.
2487 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2488 vcpu
->arch
.exception
.error_code
)) {
2489 *exit_qual
= vcpu
->arch
.cr2
;
2493 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2494 if (nr
== DB_VECTOR
)
2495 *exit_qual
= vcpu
->arch
.dr6
;
2505 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2507 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2508 unsigned nr
= vcpu
->arch
.exception
.nr
;
2509 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2510 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2511 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2513 if (has_error_code
) {
2514 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2515 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2518 if (vmx
->rmode
.vm86_active
) {
2520 if (kvm_exception_is_soft(nr
))
2521 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2522 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2523 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2527 if (kvm_exception_is_soft(nr
)) {
2528 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2529 vmx
->vcpu
.arch
.event_exit_inst_len
);
2530 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2532 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2534 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2537 static bool vmx_rdtscp_supported(void)
2539 return cpu_has_vmx_rdtscp();
2542 static bool vmx_invpcid_supported(void)
2544 return cpu_has_vmx_invpcid() && enable_ept
;
2548 * Swap MSR entry in host/guest MSR entry array.
2550 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2552 struct shared_msr_entry tmp
;
2554 tmp
= vmx
->guest_msrs
[to
];
2555 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2556 vmx
->guest_msrs
[from
] = tmp
;
2559 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2561 unsigned long *msr_bitmap
;
2563 if (is_guest_mode(vcpu
))
2564 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2565 else if (cpu_has_secondary_exec_ctrls() &&
2566 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2567 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2568 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2569 if (is_long_mode(vcpu
))
2570 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2572 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2574 if (is_long_mode(vcpu
))
2575 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2577 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2580 if (is_long_mode(vcpu
))
2581 msr_bitmap
= vmx_msr_bitmap_longmode
;
2583 msr_bitmap
= vmx_msr_bitmap_legacy
;
2586 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2590 * Set up the vmcs to automatically save and restore system
2591 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2592 * mode, as fiddling with msrs is very expensive.
2594 static void setup_msrs(struct vcpu_vmx
*vmx
)
2596 int save_nmsrs
, index
;
2599 #ifdef CONFIG_X86_64
2600 if (is_long_mode(&vmx
->vcpu
)) {
2601 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2603 move_msr_up(vmx
, index
, save_nmsrs
++);
2604 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2606 move_msr_up(vmx
, index
, save_nmsrs
++);
2607 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2609 move_msr_up(vmx
, index
, save_nmsrs
++);
2610 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2611 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2612 move_msr_up(vmx
, index
, save_nmsrs
++);
2614 * MSR_STAR is only needed on long mode guests, and only
2615 * if efer.sce is enabled.
2617 index
= __find_msr_index(vmx
, MSR_STAR
);
2618 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2622 index
= __find_msr_index(vmx
, MSR_EFER
);
2623 if (index
>= 0 && update_transition_efer(vmx
, index
))
2624 move_msr_up(vmx
, index
, save_nmsrs
++);
2626 vmx
->save_nmsrs
= save_nmsrs
;
2628 if (cpu_has_vmx_msr_bitmap())
2629 vmx_set_msr_bitmap(&vmx
->vcpu
);
2633 * reads and returns guest's timestamp counter "register"
2634 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2635 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2637 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2639 u64 host_tsc
, tsc_offset
;
2642 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2643 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2647 * writes 'offset' into guest's timestamp counter offset register
2649 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2651 if (is_guest_mode(vcpu
)) {
2653 * We're here if L1 chose not to trap WRMSR to TSC. According
2654 * to the spec, this should set L1's TSC; The offset that L1
2655 * set for L2 remains unchanged, and still needs to be added
2656 * to the newly set TSC to get L2's TSC.
2658 struct vmcs12
*vmcs12
;
2659 /* recalculate vmcs02.TSC_OFFSET: */
2660 vmcs12
= get_vmcs12(vcpu
);
2661 vmcs_write64(TSC_OFFSET
, offset
+
2662 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2663 vmcs12
->tsc_offset
: 0));
2665 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2666 vmcs_read64(TSC_OFFSET
), offset
);
2667 vmcs_write64(TSC_OFFSET
, offset
);
2672 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2673 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2674 * all guests if the "nested" module option is off, and can also be disabled
2675 * for a single guest by disabling its VMX cpuid bit.
2677 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2679 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2683 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2684 * returned for the various VMX controls MSRs when nested VMX is enabled.
2685 * The same values should also be used to verify that vmcs12 control fields are
2686 * valid during nested entry from L1 to L2.
2687 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2688 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2689 * bit in the high half is on if the corresponding bit in the control field
2690 * may be on. See also vmx_control_verify().
2692 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2695 * Note that as a general rule, the high half of the MSRs (bits in
2696 * the control fields which may be 1) should be initialized by the
2697 * intersection of the underlying hardware's MSR (i.e., features which
2698 * can be supported) and the list of features we want to expose -
2699 * because they are known to be properly supported in our code.
2700 * Also, usually, the low half of the MSRs (bits which must be 1) can
2701 * be set to 0, meaning that L1 may turn off any of these bits. The
2702 * reason is that if one of these bits is necessary, it will appear
2703 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2704 * fields of vmcs01 and vmcs02, will turn these bits off - and
2705 * nested_vmx_exit_reflected() will not pass related exits to L1.
2706 * These rules have exceptions below.
2709 /* pin-based controls */
2710 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2711 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2712 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2713 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2714 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2716 PIN_BASED_EXT_INTR_MASK
|
2717 PIN_BASED_NMI_EXITING
|
2718 PIN_BASED_VIRTUAL_NMIS
;
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2720 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2721 PIN_BASED_VMX_PREEMPTION_TIMER
;
2722 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2723 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2724 PIN_BASED_POSTED_INTR
;
2727 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2728 vmx
->nested
.nested_vmx_exit_ctls_low
,
2729 vmx
->nested
.nested_vmx_exit_ctls_high
);
2730 vmx
->nested
.nested_vmx_exit_ctls_low
=
2731 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2733 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2734 #ifdef CONFIG_X86_64
2735 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2737 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2738 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2740 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2741 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2743 if (kvm_mpx_supported())
2744 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2746 /* We support free control of debug control saving. */
2747 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2749 /* entry controls */
2750 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2751 vmx
->nested
.nested_vmx_entry_ctls_low
,
2752 vmx
->nested
.nested_vmx_entry_ctls_high
);
2753 vmx
->nested
.nested_vmx_entry_ctls_low
=
2754 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2755 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2756 #ifdef CONFIG_X86_64
2757 VM_ENTRY_IA32E_MODE
|
2759 VM_ENTRY_LOAD_IA32_PAT
;
2760 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2761 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2762 if (kvm_mpx_supported())
2763 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2765 /* We support free control of debug control loading. */
2766 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2768 /* cpu-based controls */
2769 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2772 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2773 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2775 CPU_BASED_VIRTUAL_INTR_PENDING
|
2776 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2777 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2778 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 #ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2784 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2785 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2786 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2787 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2789 * We can allow some features even when not supported by the
2790 * hardware. For example, L1 can specify an MSR bitmap - and we
2791 * can use it to avoid exits to L1 - even when L0 runs L2
2792 * without MSR bitmaps.
2794 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2795 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2796 CPU_BASED_USE_MSR_BITMAPS
;
2798 /* We support free control of CR3 access interception. */
2799 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2800 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2803 * secondary cpu-based controls. Do not include those that
2804 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2806 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2809 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2810 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2811 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2812 SECONDARY_EXEC_DESC
|
2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2814 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2816 SECONDARY_EXEC_WBINVD_EXITING
;
2819 /* nested EPT: emulate EPT also to L1 */
2820 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2821 SECONDARY_EXEC_ENABLE_EPT
;
2822 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2823 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2824 if (cpu_has_vmx_ept_execute_only())
2825 vmx
->nested
.nested_vmx_ept_caps
|=
2826 VMX_EPT_EXECUTE_ONLY_BIT
;
2827 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2828 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2829 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2830 VMX_EPT_1GB_PAGE_BIT
;
2831 if (enable_ept_ad_bits
) {
2832 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2833 SECONDARY_EXEC_ENABLE_PML
;
2834 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2837 vmx
->nested
.nested_vmx_ept_caps
= 0;
2839 if (cpu_has_vmx_vmfunc()) {
2840 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2841 SECONDARY_EXEC_ENABLE_VMFUNC
;
2843 * Advertise EPTP switching unconditionally
2844 * since we emulate it
2846 vmx
->nested
.nested_vmx_vmfunc_controls
=
2847 VMX_VMFUNC_EPTP_SWITCHING
;
2851 * Old versions of KVM use the single-context version without
2852 * checking for support, so declare that it is supported even
2853 * though it is treated as global context. The alternative is
2854 * not failing the single-context invvpid, and it is worse.
2857 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2858 SECONDARY_EXEC_ENABLE_VPID
;
2859 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2860 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2862 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2864 if (enable_unrestricted_guest
)
2865 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2866 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2868 /* miscellaneous data */
2869 rdmsr(MSR_IA32_VMX_MISC
,
2870 vmx
->nested
.nested_vmx_misc_low
,
2871 vmx
->nested
.nested_vmx_misc_high
);
2872 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2873 vmx
->nested
.nested_vmx_misc_low
|=
2874 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2875 VMX_MISC_ACTIVITY_HLT
;
2876 vmx
->nested
.nested_vmx_misc_high
= 0;
2879 * This MSR reports some information about VMX support. We
2880 * should return information about the VMX we emulate for the
2881 * guest, and the VMCS structure we give it - not about the
2882 * VMX support of the underlying hardware.
2884 vmx
->nested
.nested_vmx_basic
=
2886 VMX_BASIC_TRUE_CTLS
|
2887 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2888 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2890 if (cpu_has_vmx_basic_inout())
2891 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2894 * These MSRs specify bits which the guest must keep fixed on
2895 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2896 * We picked the standard core2 setting.
2898 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2899 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2900 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2901 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2903 /* These MSRs specify bits which the guest must keep fixed off. */
2904 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2905 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2907 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2908 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2912 * if fixed0[i] == 1: val[i] must be 1
2913 * if fixed1[i] == 0: val[i] must be 0
2915 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2917 return ((val
& fixed1
) | fixed0
) == val
;
2920 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2922 return fixed_bits_valid(control
, low
, high
);
2925 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2927 return low
| ((u64
)high
<< 32);
2930 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2935 return (superset
| subset
) == superset
;
2938 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2940 const u64 feature_and_reserved
=
2941 /* feature (except bit 48; see below) */
2942 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2944 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2945 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2947 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2951 * KVM does not emulate a version of VMX that constrains physical
2952 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2954 if (data
& BIT_ULL(48))
2957 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2958 vmx_basic_vmcs_revision_id(data
))
2961 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2964 vmx
->nested
.nested_vmx_basic
= data
;
2969 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2974 switch (msr_index
) {
2975 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2976 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2977 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2979 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2980 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2981 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2983 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2984 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2985 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2987 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2988 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2989 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2991 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2992 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2993 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2999 supported
= vmx_control_msr(*lowp
, *highp
);
3001 /* Check must-be-1 bits are still 1. */
3002 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3005 /* Check must-be-0 bits are still 0. */
3006 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3010 *highp
= data
>> 32;
3014 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3016 const u64 feature_and_reserved_bits
=
3018 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3019 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3021 GENMASK_ULL(13, 9) | BIT_ULL(31);
3024 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3025 vmx
->nested
.nested_vmx_misc_high
);
3027 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3030 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3031 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3032 vmx_misc_preemption_timer_rate(data
) !=
3033 vmx_misc_preemption_timer_rate(vmx_misc
))
3036 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3039 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3042 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3045 vmx
->nested
.nested_vmx_misc_low
= data
;
3046 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3050 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3052 u64 vmx_ept_vpid_cap
;
3054 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3055 vmx
->nested
.nested_vmx_vpid_caps
);
3057 /* Every bit is either reserved or a feature bit. */
3058 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3061 vmx
->nested
.nested_vmx_ept_caps
= data
;
3062 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3066 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3070 switch (msr_index
) {
3071 case MSR_IA32_VMX_CR0_FIXED0
:
3072 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3074 case MSR_IA32_VMX_CR4_FIXED0
:
3075 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3082 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3083 * must be 1 in the restored value.
3085 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3093 * Called when userspace is restoring VMX MSRs.
3095 * Returns 0 on success, non-0 otherwise.
3097 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3099 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3101 switch (msr_index
) {
3102 case MSR_IA32_VMX_BASIC
:
3103 return vmx_restore_vmx_basic(vmx
, data
);
3104 case MSR_IA32_VMX_PINBASED_CTLS
:
3105 case MSR_IA32_VMX_PROCBASED_CTLS
:
3106 case MSR_IA32_VMX_EXIT_CTLS
:
3107 case MSR_IA32_VMX_ENTRY_CTLS
:
3109 * The "non-true" VMX capability MSRs are generated from the
3110 * "true" MSRs, so we do not support restoring them directly.
3112 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3113 * should restore the "true" MSRs with the must-be-1 bits
3114 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3115 * DEFAULT SETTINGS".
3118 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3119 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3120 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3121 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3122 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3123 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3124 case MSR_IA32_VMX_MISC
:
3125 return vmx_restore_vmx_misc(vmx
, data
);
3126 case MSR_IA32_VMX_CR0_FIXED0
:
3127 case MSR_IA32_VMX_CR4_FIXED0
:
3128 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3129 case MSR_IA32_VMX_CR0_FIXED1
:
3130 case MSR_IA32_VMX_CR4_FIXED1
:
3132 * These MSRs are generated based on the vCPU's CPUID, so we
3133 * do not support restoring them directly.
3136 case MSR_IA32_VMX_EPT_VPID_CAP
:
3137 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3138 case MSR_IA32_VMX_VMCS_ENUM
:
3139 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3143 * The rest of the VMX capability MSRs do not support restore.
3149 /* Returns 0 on success, non-0 otherwise. */
3150 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3152 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3154 switch (msr_index
) {
3155 case MSR_IA32_VMX_BASIC
:
3156 *pdata
= vmx
->nested
.nested_vmx_basic
;
3158 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3159 case MSR_IA32_VMX_PINBASED_CTLS
:
3160 *pdata
= vmx_control_msr(
3161 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3162 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3163 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3164 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3166 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3167 case MSR_IA32_VMX_PROCBASED_CTLS
:
3168 *pdata
= vmx_control_msr(
3169 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3170 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3171 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3172 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3174 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3175 case MSR_IA32_VMX_EXIT_CTLS
:
3176 *pdata
= vmx_control_msr(
3177 vmx
->nested
.nested_vmx_exit_ctls_low
,
3178 vmx
->nested
.nested_vmx_exit_ctls_high
);
3179 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3180 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3182 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3183 case MSR_IA32_VMX_ENTRY_CTLS
:
3184 *pdata
= vmx_control_msr(
3185 vmx
->nested
.nested_vmx_entry_ctls_low
,
3186 vmx
->nested
.nested_vmx_entry_ctls_high
);
3187 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3188 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3190 case MSR_IA32_VMX_MISC
:
3191 *pdata
= vmx_control_msr(
3192 vmx
->nested
.nested_vmx_misc_low
,
3193 vmx
->nested
.nested_vmx_misc_high
);
3195 case MSR_IA32_VMX_CR0_FIXED0
:
3196 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3198 case MSR_IA32_VMX_CR0_FIXED1
:
3199 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3201 case MSR_IA32_VMX_CR4_FIXED0
:
3202 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3204 case MSR_IA32_VMX_CR4_FIXED1
:
3205 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3207 case MSR_IA32_VMX_VMCS_ENUM
:
3208 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3210 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3211 *pdata
= vmx_control_msr(
3212 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3213 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3215 case MSR_IA32_VMX_EPT_VPID_CAP
:
3216 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3217 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3219 case MSR_IA32_VMX_VMFUNC
:
3220 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3229 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3232 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3234 return !(val
& ~valid_bits
);
3238 * Reads an msr value (of 'msr_index') into 'pdata'.
3239 * Returns 0 on success, non-0 otherwise.
3240 * Assumes vcpu_load() was already called.
3242 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3244 struct shared_msr_entry
*msr
;
3246 switch (msr_info
->index
) {
3247 #ifdef CONFIG_X86_64
3249 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3252 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3254 case MSR_KERNEL_GS_BASE
:
3255 vmx_load_host_state(to_vmx(vcpu
));
3256 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3260 return kvm_get_msr_common(vcpu
, msr_info
);
3262 msr_info
->data
= guest_read_tsc(vcpu
);
3264 case MSR_IA32_SYSENTER_CS
:
3265 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3267 case MSR_IA32_SYSENTER_EIP
:
3268 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3270 case MSR_IA32_SYSENTER_ESP
:
3271 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3273 case MSR_IA32_BNDCFGS
:
3274 if (!kvm_mpx_supported() ||
3275 (!msr_info
->host_initiated
&&
3276 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3278 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3280 case MSR_IA32_MCG_EXT_CTL
:
3281 if (!msr_info
->host_initiated
&&
3282 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3283 FEATURE_CONTROL_LMCE
))
3285 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3287 case MSR_IA32_FEATURE_CONTROL
:
3288 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3290 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3291 if (!nested_vmx_allowed(vcpu
))
3293 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3295 if (!vmx_xsaves_supported())
3297 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3300 if (!msr_info
->host_initiated
&&
3301 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3303 /* Otherwise falls through */
3305 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3307 msr_info
->data
= msr
->data
;
3310 return kvm_get_msr_common(vcpu
, msr_info
);
3316 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3319 * Writes msr value into into the appropriate "register".
3320 * Returns 0 on success, non-0 otherwise.
3321 * Assumes vcpu_load() was already called.
3323 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3325 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3326 struct shared_msr_entry
*msr
;
3328 u32 msr_index
= msr_info
->index
;
3329 u64 data
= msr_info
->data
;
3331 switch (msr_index
) {
3333 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3335 #ifdef CONFIG_X86_64
3337 vmx_segment_cache_clear(vmx
);
3338 vmcs_writel(GUEST_FS_BASE
, data
);
3341 vmx_segment_cache_clear(vmx
);
3342 vmcs_writel(GUEST_GS_BASE
, data
);
3344 case MSR_KERNEL_GS_BASE
:
3345 vmx_load_host_state(vmx
);
3346 vmx
->msr_guest_kernel_gs_base
= data
;
3349 case MSR_IA32_SYSENTER_CS
:
3350 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3352 case MSR_IA32_SYSENTER_EIP
:
3353 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3355 case MSR_IA32_SYSENTER_ESP
:
3356 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3358 case MSR_IA32_BNDCFGS
:
3359 if (!kvm_mpx_supported() ||
3360 (!msr_info
->host_initiated
&&
3361 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3363 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3364 (data
& MSR_IA32_BNDCFGS_RSVD
))
3366 vmcs_write64(GUEST_BNDCFGS
, data
);
3369 kvm_write_tsc(vcpu
, msr_info
);
3371 case MSR_IA32_CR_PAT
:
3372 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3373 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3375 vmcs_write64(GUEST_IA32_PAT
, data
);
3376 vcpu
->arch
.pat
= data
;
3379 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3381 case MSR_IA32_TSC_ADJUST
:
3382 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3384 case MSR_IA32_MCG_EXT_CTL
:
3385 if ((!msr_info
->host_initiated
&&
3386 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3387 FEATURE_CONTROL_LMCE
)) ||
3388 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3390 vcpu
->arch
.mcg_ext_ctl
= data
;
3392 case MSR_IA32_FEATURE_CONTROL
:
3393 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3394 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3395 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3397 vmx
->msr_ia32_feature_control
= data
;
3398 if (msr_info
->host_initiated
&& data
== 0)
3399 vmx_leave_nested(vcpu
);
3401 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3402 if (!msr_info
->host_initiated
)
3403 return 1; /* they are read-only */
3404 if (!nested_vmx_allowed(vcpu
))
3406 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3408 if (!vmx_xsaves_supported())
3411 * The only supported bit as of Skylake is bit 8, but
3412 * it is not supported on KVM.
3416 vcpu
->arch
.ia32_xss
= data
;
3417 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3418 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3419 vcpu
->arch
.ia32_xss
, host_xss
);
3421 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3424 if (!msr_info
->host_initiated
&&
3425 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3427 /* Check reserved bit, higher 32 bits should be zero */
3428 if ((data
>> 32) != 0)
3430 /* Otherwise falls through */
3432 msr
= find_msr_entry(vmx
, msr_index
);
3434 u64 old_msr_data
= msr
->data
;
3436 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3438 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3442 msr
->data
= old_msr_data
;
3446 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3452 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3454 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3457 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3460 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3462 case VCPU_EXREG_PDPTR
:
3464 ept_save_pdptrs(vcpu
);
3471 static __init
int cpu_has_kvm_support(void)
3473 return cpu_has_vmx();
3476 static __init
int vmx_disabled_by_bios(void)
3480 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3481 if (msr
& FEATURE_CONTROL_LOCKED
) {
3482 /* launched w/ TXT and VMX disabled */
3483 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3486 /* launched w/o TXT and VMX only enabled w/ TXT */
3487 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3488 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3489 && !tboot_enabled()) {
3490 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3491 "activate TXT before enabling KVM\n");
3494 /* launched w/o TXT and VMX disabled */
3495 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3496 && !tboot_enabled())
3503 static void kvm_cpu_vmxon(u64 addr
)
3505 cr4_set_bits(X86_CR4_VMXE
);
3506 intel_pt_handle_vmx(1);
3508 asm volatile (ASM_VMX_VMXON_RAX
3509 : : "a"(&addr
), "m"(addr
)
3513 static int hardware_enable(void)
3515 int cpu
= raw_smp_processor_id();
3516 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3519 if (cr4_read_shadow() & X86_CR4_VMXE
)
3522 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3523 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3524 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3527 * Now we can enable the vmclear operation in kdump
3528 * since the loaded_vmcss_on_cpu list on this cpu
3529 * has been initialized.
3531 * Though the cpu is not in VMX operation now, there
3532 * is no problem to enable the vmclear operation
3533 * for the loaded_vmcss_on_cpu list is empty!
3535 crash_enable_local_vmclear(cpu
);
3537 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3539 test_bits
= FEATURE_CONTROL_LOCKED
;
3540 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3541 if (tboot_enabled())
3542 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3544 if ((old
& test_bits
) != test_bits
) {
3545 /* enable and lock */
3546 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3548 kvm_cpu_vmxon(phys_addr
);
3554 static void vmclear_local_loaded_vmcss(void)
3556 int cpu
= raw_smp_processor_id();
3557 struct loaded_vmcs
*v
, *n
;
3559 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3560 loaded_vmcss_on_cpu_link
)
3561 __loaded_vmcs_clear(v
);
3565 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3568 static void kvm_cpu_vmxoff(void)
3570 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3572 intel_pt_handle_vmx(0);
3573 cr4_clear_bits(X86_CR4_VMXE
);
3576 static void hardware_disable(void)
3578 vmclear_local_loaded_vmcss();
3582 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3583 u32 msr
, u32
*result
)
3585 u32 vmx_msr_low
, vmx_msr_high
;
3586 u32 ctl
= ctl_min
| ctl_opt
;
3588 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3590 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3591 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3593 /* Ensure minimum (required) set of control bits are supported. */
3601 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3603 u32 vmx_msr_low
, vmx_msr_high
;
3605 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3606 return vmx_msr_high
& ctl
;
3609 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3611 u32 vmx_msr_low
, vmx_msr_high
;
3612 u32 min
, opt
, min2
, opt2
;
3613 u32 _pin_based_exec_control
= 0;
3614 u32 _cpu_based_exec_control
= 0;
3615 u32 _cpu_based_2nd_exec_control
= 0;
3616 u32 _vmexit_control
= 0;
3617 u32 _vmentry_control
= 0;
3619 min
= CPU_BASED_HLT_EXITING
|
3620 #ifdef CONFIG_X86_64
3621 CPU_BASED_CR8_LOAD_EXITING
|
3622 CPU_BASED_CR8_STORE_EXITING
|
3624 CPU_BASED_CR3_LOAD_EXITING
|
3625 CPU_BASED_CR3_STORE_EXITING
|
3626 CPU_BASED_USE_IO_BITMAPS
|
3627 CPU_BASED_MOV_DR_EXITING
|
3628 CPU_BASED_USE_TSC_OFFSETING
|
3629 CPU_BASED_INVLPG_EXITING
|
3630 CPU_BASED_RDPMC_EXITING
;
3632 if (!kvm_mwait_in_guest())
3633 min
|= CPU_BASED_MWAIT_EXITING
|
3634 CPU_BASED_MONITOR_EXITING
;
3636 opt
= CPU_BASED_TPR_SHADOW
|
3637 CPU_BASED_USE_MSR_BITMAPS
|
3638 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3639 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3640 &_cpu_based_exec_control
) < 0)
3642 #ifdef CONFIG_X86_64
3643 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3644 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3645 ~CPU_BASED_CR8_STORE_EXITING
;
3647 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3649 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3650 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3651 SECONDARY_EXEC_WBINVD_EXITING
|
3652 SECONDARY_EXEC_ENABLE_VPID
|
3653 SECONDARY_EXEC_ENABLE_EPT
|
3654 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3655 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3656 SECONDARY_EXEC_RDTSCP
|
3657 SECONDARY_EXEC_ENABLE_INVPCID
|
3658 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3659 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3660 SECONDARY_EXEC_SHADOW_VMCS
|
3661 SECONDARY_EXEC_XSAVES
|
3662 SECONDARY_EXEC_RDSEED
|
3663 SECONDARY_EXEC_RDRAND
|
3664 SECONDARY_EXEC_ENABLE_PML
|
3665 SECONDARY_EXEC_TSC_SCALING
|
3666 SECONDARY_EXEC_ENABLE_VMFUNC
;
3667 if (adjust_vmx_controls(min2
, opt2
,
3668 MSR_IA32_VMX_PROCBASED_CTLS2
,
3669 &_cpu_based_2nd_exec_control
) < 0)
3672 #ifndef CONFIG_X86_64
3673 if (!(_cpu_based_2nd_exec_control
&
3674 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3675 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3678 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3679 _cpu_based_2nd_exec_control
&= ~(
3680 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3681 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3682 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3684 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3685 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3687 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3688 CPU_BASED_CR3_STORE_EXITING
|
3689 CPU_BASED_INVLPG_EXITING
);
3690 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3691 vmx_capability
.ept
, vmx_capability
.vpid
);
3694 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3695 #ifdef CONFIG_X86_64
3696 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3698 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3699 VM_EXIT_CLEAR_BNDCFGS
;
3700 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3701 &_vmexit_control
) < 0)
3704 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3705 PIN_BASED_VIRTUAL_NMIS
;
3706 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3707 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3708 &_pin_based_exec_control
) < 0)
3711 if (cpu_has_broken_vmx_preemption_timer())
3712 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3713 if (!(_cpu_based_2nd_exec_control
&
3714 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3715 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3717 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3718 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3719 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3720 &_vmentry_control
) < 0)
3723 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3725 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3726 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3729 #ifdef CONFIG_X86_64
3730 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3731 if (vmx_msr_high
& (1u<<16))
3735 /* Require Write-Back (WB) memory type for VMCS accesses. */
3736 if (((vmx_msr_high
>> 18) & 15) != 6)
3739 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3740 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3741 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3742 vmcs_conf
->revision_id
= vmx_msr_low
;
3744 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3745 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3746 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3747 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3748 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3750 cpu_has_load_ia32_efer
=
3751 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3752 VM_ENTRY_LOAD_IA32_EFER
)
3753 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3754 VM_EXIT_LOAD_IA32_EFER
);
3756 cpu_has_load_perf_global_ctrl
=
3757 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3758 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3759 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3760 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3763 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3764 * but due to errata below it can't be used. Workaround is to use
3765 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3767 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3772 * BC86,AAY89,BD102 (model 44)
3776 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3777 switch (boot_cpu_data
.x86_model
) {
3783 cpu_has_load_perf_global_ctrl
= false;
3784 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3785 "does not work properly. Using workaround\n");
3792 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3793 rdmsrl(MSR_IA32_XSS
, host_xss
);
3798 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3800 int node
= cpu_to_node(cpu
);
3804 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3807 vmcs
= page_address(pages
);
3808 memset(vmcs
, 0, vmcs_config
.size
);
3809 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3813 static struct vmcs
*alloc_vmcs(void)
3815 return alloc_vmcs_cpu(raw_smp_processor_id());
3818 static void free_vmcs(struct vmcs
*vmcs
)
3820 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3824 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3826 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3828 if (!loaded_vmcs
->vmcs
)
3830 loaded_vmcs_clear(loaded_vmcs
);
3831 free_vmcs(loaded_vmcs
->vmcs
);
3832 loaded_vmcs
->vmcs
= NULL
;
3833 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3836 static void free_kvm_area(void)
3840 for_each_possible_cpu(cpu
) {
3841 free_vmcs(per_cpu(vmxarea
, cpu
));
3842 per_cpu(vmxarea
, cpu
) = NULL
;
3846 enum vmcs_field_type
{
3847 VMCS_FIELD_TYPE_U16
= 0,
3848 VMCS_FIELD_TYPE_U64
= 1,
3849 VMCS_FIELD_TYPE_U32
= 2,
3850 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3853 static inline int vmcs_field_type(unsigned long field
)
3855 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3856 return VMCS_FIELD_TYPE_U32
;
3857 return (field
>> 13) & 0x3 ;
3860 static inline int vmcs_field_readonly(unsigned long field
)
3862 return (((field
>> 10) & 0x3) == 1);
3865 static void init_vmcs_shadow_fields(void)
3869 /* No checks for read only fields yet */
3871 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3872 switch (shadow_read_write_fields
[i
]) {
3874 if (!kvm_mpx_supported())
3882 shadow_read_write_fields
[j
] =
3883 shadow_read_write_fields
[i
];
3886 max_shadow_read_write_fields
= j
;
3888 /* shadowed fields guest access without vmexit */
3889 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3890 unsigned long field
= shadow_read_write_fields
[i
];
3892 clear_bit(field
, vmx_vmwrite_bitmap
);
3893 clear_bit(field
, vmx_vmread_bitmap
);
3894 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3895 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3896 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3899 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3900 unsigned long field
= shadow_read_only_fields
[i
];
3902 clear_bit(field
, vmx_vmread_bitmap
);
3903 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3904 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3908 static __init
int alloc_kvm_area(void)
3912 for_each_possible_cpu(cpu
) {
3915 vmcs
= alloc_vmcs_cpu(cpu
);
3921 per_cpu(vmxarea
, cpu
) = vmcs
;
3926 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3927 struct kvm_segment
*save
)
3929 if (!emulate_invalid_guest_state
) {
3931 * CS and SS RPL should be equal during guest entry according
3932 * to VMX spec, but in reality it is not always so. Since vcpu
3933 * is in the middle of the transition from real mode to
3934 * protected mode it is safe to assume that RPL 0 is a good
3937 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3938 save
->selector
&= ~SEGMENT_RPL_MASK
;
3939 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3942 vmx_set_segment(vcpu
, save
, seg
);
3945 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3947 unsigned long flags
;
3948 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3951 * Update real mode segment cache. It may be not up-to-date if sement
3952 * register was written while vcpu was in a guest mode.
3954 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3955 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3956 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3957 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3958 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3959 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3961 vmx
->rmode
.vm86_active
= 0;
3963 vmx_segment_cache_clear(vmx
);
3965 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3967 flags
= vmcs_readl(GUEST_RFLAGS
);
3968 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3969 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3970 vmcs_writel(GUEST_RFLAGS
, flags
);
3972 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3973 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3975 update_exception_bitmap(vcpu
);
3977 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3978 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3979 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3980 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3981 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3982 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3985 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3987 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3988 struct kvm_segment var
= *save
;
3991 if (seg
== VCPU_SREG_CS
)
3994 if (!emulate_invalid_guest_state
) {
3995 var
.selector
= var
.base
>> 4;
3996 var
.base
= var
.base
& 0xffff0;
4006 if (save
->base
& 0xf)
4007 printk_once(KERN_WARNING
"kvm: segment base is not "
4008 "paragraph aligned when entering "
4009 "protected mode (seg=%d)", seg
);
4012 vmcs_write16(sf
->selector
, var
.selector
);
4013 vmcs_writel(sf
->base
, var
.base
);
4014 vmcs_write32(sf
->limit
, var
.limit
);
4015 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4018 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4020 unsigned long flags
;
4021 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4023 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4024 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4025 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4026 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4027 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4028 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4029 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4031 vmx
->rmode
.vm86_active
= 1;
4034 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4035 * vcpu. Warn the user that an update is overdue.
4037 if (!vcpu
->kvm
->arch
.tss_addr
)
4038 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4039 "called before entering vcpu\n");
4041 vmx_segment_cache_clear(vmx
);
4043 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4044 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4045 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4047 flags
= vmcs_readl(GUEST_RFLAGS
);
4048 vmx
->rmode
.save_rflags
= flags
;
4050 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4052 vmcs_writel(GUEST_RFLAGS
, flags
);
4053 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4054 update_exception_bitmap(vcpu
);
4056 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4057 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4058 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4059 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4060 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4061 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4063 kvm_mmu_reset_context(vcpu
);
4066 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4068 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4069 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4075 * Force kernel_gs_base reloading before EFER changes, as control
4076 * of this msr depends on is_long_mode().
4078 vmx_load_host_state(to_vmx(vcpu
));
4079 vcpu
->arch
.efer
= efer
;
4080 if (efer
& EFER_LMA
) {
4081 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4084 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4086 msr
->data
= efer
& ~EFER_LME
;
4091 #ifdef CONFIG_X86_64
4093 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4097 vmx_segment_cache_clear(to_vmx(vcpu
));
4099 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4100 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4101 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4103 vmcs_write32(GUEST_TR_AR_BYTES
,
4104 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4105 | VMX_AR_TYPE_BUSY_64_TSS
);
4107 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4110 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4112 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4113 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4118 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4121 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4123 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4125 vpid_sync_context(vpid
);
4129 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4131 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4134 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4137 vmx_flush_tlb(vcpu
);
4140 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4142 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4144 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4145 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4148 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4150 if (enable_ept
&& is_paging(vcpu
))
4151 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4152 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4155 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4157 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4159 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4160 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4163 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4165 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4167 if (!test_bit(VCPU_EXREG_PDPTR
,
4168 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4171 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4172 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4173 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4174 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4175 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4179 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4181 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4183 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4184 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4185 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4186 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4187 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4190 __set_bit(VCPU_EXREG_PDPTR
,
4191 (unsigned long *)&vcpu
->arch
.regs_avail
);
4192 __set_bit(VCPU_EXREG_PDPTR
,
4193 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4196 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4198 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4199 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4200 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4202 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4203 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4204 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4205 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4207 return fixed_bits_valid(val
, fixed0
, fixed1
);
4210 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4212 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4213 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4215 return fixed_bits_valid(val
, fixed0
, fixed1
);
4218 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4220 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4221 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4223 return fixed_bits_valid(val
, fixed0
, fixed1
);
4226 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4227 #define nested_guest_cr4_valid nested_cr4_valid
4228 #define nested_host_cr4_valid nested_cr4_valid
4230 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4232 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4234 struct kvm_vcpu
*vcpu
)
4236 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4237 vmx_decache_cr3(vcpu
);
4238 if (!(cr0
& X86_CR0_PG
)) {
4239 /* From paging/starting to nonpaging */
4240 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4241 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4242 (CPU_BASED_CR3_LOAD_EXITING
|
4243 CPU_BASED_CR3_STORE_EXITING
));
4244 vcpu
->arch
.cr0
= cr0
;
4245 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4246 } else if (!is_paging(vcpu
)) {
4247 /* From nonpaging to paging */
4248 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4249 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4250 ~(CPU_BASED_CR3_LOAD_EXITING
|
4251 CPU_BASED_CR3_STORE_EXITING
));
4252 vcpu
->arch
.cr0
= cr0
;
4253 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4256 if (!(cr0
& X86_CR0_WP
))
4257 *hw_cr0
&= ~X86_CR0_WP
;
4260 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4263 unsigned long hw_cr0
;
4265 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4266 if (enable_unrestricted_guest
)
4267 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4269 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4271 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4274 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4278 #ifdef CONFIG_X86_64
4279 if (vcpu
->arch
.efer
& EFER_LME
) {
4280 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4282 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4288 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4290 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4291 vmcs_writel(GUEST_CR0
, hw_cr0
);
4292 vcpu
->arch
.cr0
= cr0
;
4294 /* depends on vcpu->arch.cr0 to be set to a new value */
4295 vmx
->emulation_required
= emulation_required(vcpu
);
4298 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4300 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4305 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4307 u64 eptp
= VMX_EPTP_MT_WB
;
4309 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4311 if (enable_ept_ad_bits
&&
4312 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4313 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4314 eptp
|= (root_hpa
& PAGE_MASK
);
4319 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4321 unsigned long guest_cr3
;
4326 eptp
= construct_eptp(vcpu
, cr3
);
4327 vmcs_write64(EPT_POINTER
, eptp
);
4328 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4329 guest_cr3
= kvm_read_cr3(vcpu
);
4331 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4332 ept_load_pdptrs(vcpu
);
4335 vmx_flush_tlb(vcpu
);
4336 vmcs_writel(GUEST_CR3
, guest_cr3
);
4339 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4342 * Pass through host's Machine Check Enable value to hw_cr4, which
4343 * is in force while we are in guest mode. Do not let guests control
4344 * this bit, even if host CR4.MCE == 0.
4346 unsigned long hw_cr4
=
4347 (cr4_read_shadow() & X86_CR4_MCE
) |
4348 (cr4
& ~X86_CR4_MCE
) |
4349 (to_vmx(vcpu
)->rmode
.vm86_active
?
4350 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4352 if (cr4
& X86_CR4_VMXE
) {
4354 * To use VMXON (and later other VMX instructions), a guest
4355 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4356 * So basically the check on whether to allow nested VMX
4359 if (!nested_vmx_allowed(vcpu
))
4363 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4366 vcpu
->arch
.cr4
= cr4
;
4368 if (!is_paging(vcpu
)) {
4369 hw_cr4
&= ~X86_CR4_PAE
;
4370 hw_cr4
|= X86_CR4_PSE
;
4371 } else if (!(cr4
& X86_CR4_PAE
)) {
4372 hw_cr4
&= ~X86_CR4_PAE
;
4376 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4378 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4379 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4380 * to be manually disabled when guest switches to non-paging
4383 * If !enable_unrestricted_guest, the CPU is always running
4384 * with CR0.PG=1 and CR4 needs to be modified.
4385 * If enable_unrestricted_guest, the CPU automatically
4386 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4388 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4390 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4391 vmcs_writel(GUEST_CR4
, hw_cr4
);
4395 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4396 struct kvm_segment
*var
, int seg
)
4398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4401 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4402 *var
= vmx
->rmode
.segs
[seg
];
4403 if (seg
== VCPU_SREG_TR
4404 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4406 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4407 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4410 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4411 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4412 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4413 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4414 var
->unusable
= (ar
>> 16) & 1;
4415 var
->type
= ar
& 15;
4416 var
->s
= (ar
>> 4) & 1;
4417 var
->dpl
= (ar
>> 5) & 3;
4419 * Some userspaces do not preserve unusable property. Since usable
4420 * segment has to be present according to VMX spec we can use present
4421 * property to amend userspace bug by making unusable segment always
4422 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4423 * segment as unusable.
4425 var
->present
= !var
->unusable
;
4426 var
->avl
= (ar
>> 12) & 1;
4427 var
->l
= (ar
>> 13) & 1;
4428 var
->db
= (ar
>> 14) & 1;
4429 var
->g
= (ar
>> 15) & 1;
4432 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4434 struct kvm_segment s
;
4436 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4437 vmx_get_segment(vcpu
, &s
, seg
);
4440 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4443 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4445 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4447 if (unlikely(vmx
->rmode
.vm86_active
))
4450 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4451 return VMX_AR_DPL(ar
);
4455 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4459 if (var
->unusable
|| !var
->present
)
4462 ar
= var
->type
& 15;
4463 ar
|= (var
->s
& 1) << 4;
4464 ar
|= (var
->dpl
& 3) << 5;
4465 ar
|= (var
->present
& 1) << 7;
4466 ar
|= (var
->avl
& 1) << 12;
4467 ar
|= (var
->l
& 1) << 13;
4468 ar
|= (var
->db
& 1) << 14;
4469 ar
|= (var
->g
& 1) << 15;
4475 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4476 struct kvm_segment
*var
, int seg
)
4478 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4479 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4481 vmx_segment_cache_clear(vmx
);
4483 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4484 vmx
->rmode
.segs
[seg
] = *var
;
4485 if (seg
== VCPU_SREG_TR
)
4486 vmcs_write16(sf
->selector
, var
->selector
);
4488 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4492 vmcs_writel(sf
->base
, var
->base
);
4493 vmcs_write32(sf
->limit
, var
->limit
);
4494 vmcs_write16(sf
->selector
, var
->selector
);
4497 * Fix the "Accessed" bit in AR field of segment registers for older
4499 * IA32 arch specifies that at the time of processor reset the
4500 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4501 * is setting it to 0 in the userland code. This causes invalid guest
4502 * state vmexit when "unrestricted guest" mode is turned on.
4503 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4504 * tree. Newer qemu binaries with that qemu fix would not need this
4507 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4508 var
->type
|= 0x1; /* Accessed */
4510 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4513 vmx
->emulation_required
= emulation_required(vcpu
);
4516 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4518 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4520 *db
= (ar
>> 14) & 1;
4521 *l
= (ar
>> 13) & 1;
4524 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4526 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4527 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4530 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4532 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4533 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4536 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4538 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4539 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4542 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4544 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4545 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4548 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4550 struct kvm_segment var
;
4553 vmx_get_segment(vcpu
, &var
, seg
);
4555 if (seg
== VCPU_SREG_CS
)
4557 ar
= vmx_segment_access_rights(&var
);
4559 if (var
.base
!= (var
.selector
<< 4))
4561 if (var
.limit
!= 0xffff)
4569 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4571 struct kvm_segment cs
;
4572 unsigned int cs_rpl
;
4574 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4575 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4579 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4583 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4584 if (cs
.dpl
> cs_rpl
)
4587 if (cs
.dpl
!= cs_rpl
)
4593 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4597 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4599 struct kvm_segment ss
;
4600 unsigned int ss_rpl
;
4602 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4603 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4607 if (ss
.type
!= 3 && ss
.type
!= 7)
4611 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4619 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4621 struct kvm_segment var
;
4624 vmx_get_segment(vcpu
, &var
, seg
);
4625 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4633 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4634 if (var
.dpl
< rpl
) /* DPL < RPL */
4638 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4644 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4646 struct kvm_segment tr
;
4648 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4652 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4654 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4662 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4664 struct kvm_segment ldtr
;
4666 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4670 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4680 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4682 struct kvm_segment cs
, ss
;
4684 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4685 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4687 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4688 (ss
.selector
& SEGMENT_RPL_MASK
));
4692 * Check if guest state is valid. Returns true if valid, false if
4694 * We assume that registers are always usable
4696 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4698 if (enable_unrestricted_guest
)
4701 /* real mode guest state checks */
4702 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4703 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4705 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4707 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4709 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4711 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4713 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4716 /* protected mode guest state checks */
4717 if (!cs_ss_rpl_check(vcpu
))
4719 if (!code_segment_valid(vcpu
))
4721 if (!stack_segment_valid(vcpu
))
4723 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4725 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4727 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4729 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4731 if (!tr_valid(vcpu
))
4733 if (!ldtr_valid(vcpu
))
4737 * - Add checks on RIP
4738 * - Add checks on RFLAGS
4744 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4746 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4749 static int init_rmode_tss(struct kvm
*kvm
)
4755 idx
= srcu_read_lock(&kvm
->srcu
);
4756 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4757 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4760 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4761 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4762 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4765 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4768 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4772 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4773 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4776 srcu_read_unlock(&kvm
->srcu
, idx
);
4780 static int init_rmode_identity_map(struct kvm
*kvm
)
4783 kvm_pfn_t identity_map_pfn
;
4789 /* Protect kvm->arch.ept_identity_pagetable_done. */
4790 mutex_lock(&kvm
->slots_lock
);
4792 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4795 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4797 r
= alloc_identity_pagetable(kvm
);
4801 idx
= srcu_read_lock(&kvm
->srcu
);
4802 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4805 /* Set up identity-mapping pagetable for EPT in real mode */
4806 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4807 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4808 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4809 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4810 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4814 kvm
->arch
.ept_identity_pagetable_done
= true;
4817 srcu_read_unlock(&kvm
->srcu
, idx
);
4820 mutex_unlock(&kvm
->slots_lock
);
4824 static void seg_setup(int seg
)
4826 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4829 vmcs_write16(sf
->selector
, 0);
4830 vmcs_writel(sf
->base
, 0);
4831 vmcs_write32(sf
->limit
, 0xffff);
4833 if (seg
== VCPU_SREG_CS
)
4834 ar
|= 0x08; /* code segment */
4836 vmcs_write32(sf
->ar_bytes
, ar
);
4839 static int alloc_apic_access_page(struct kvm
*kvm
)
4844 mutex_lock(&kvm
->slots_lock
);
4845 if (kvm
->arch
.apic_access_page_done
)
4847 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4848 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4852 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4853 if (is_error_page(page
)) {
4859 * Do not pin the page in memory, so that memory hot-unplug
4860 * is able to migrate it.
4863 kvm
->arch
.apic_access_page_done
= true;
4865 mutex_unlock(&kvm
->slots_lock
);
4869 static int alloc_identity_pagetable(struct kvm
*kvm
)
4871 /* Called with kvm->slots_lock held. */
4875 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4877 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4878 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4883 static int allocate_vpid(void)
4889 spin_lock(&vmx_vpid_lock
);
4890 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4891 if (vpid
< VMX_NR_VPIDS
)
4892 __set_bit(vpid
, vmx_vpid_bitmap
);
4895 spin_unlock(&vmx_vpid_lock
);
4899 static void free_vpid(int vpid
)
4901 if (!enable_vpid
|| vpid
== 0)
4903 spin_lock(&vmx_vpid_lock
);
4904 __clear_bit(vpid
, vmx_vpid_bitmap
);
4905 spin_unlock(&vmx_vpid_lock
);
4908 #define MSR_TYPE_R 1
4909 #define MSR_TYPE_W 2
4910 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4913 int f
= sizeof(unsigned long);
4915 if (!cpu_has_vmx_msr_bitmap())
4919 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4920 * have the write-low and read-high bitmap offsets the wrong way round.
4921 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4923 if (msr
<= 0x1fff) {
4924 if (type
& MSR_TYPE_R
)
4926 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4928 if (type
& MSR_TYPE_W
)
4930 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4932 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4934 if (type
& MSR_TYPE_R
)
4936 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4938 if (type
& MSR_TYPE_W
)
4940 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4946 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4947 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4949 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4950 unsigned long *msr_bitmap_nested
,
4953 int f
= sizeof(unsigned long);
4955 if (!cpu_has_vmx_msr_bitmap()) {
4961 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4962 * have the write-low and read-high bitmap offsets the wrong way round.
4963 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4965 if (msr
<= 0x1fff) {
4966 if (type
& MSR_TYPE_R
&&
4967 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4969 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4971 if (type
& MSR_TYPE_W
&&
4972 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4974 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4976 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4978 if (type
& MSR_TYPE_R
&&
4979 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4981 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4983 if (type
& MSR_TYPE_W
&&
4984 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4986 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4991 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4994 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4995 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4996 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4997 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5000 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5003 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5005 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5010 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5015 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5017 return enable_apicv
;
5020 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5022 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5026 * Don't need to mark the APIC access page dirty; it is never
5027 * written to by the CPU during APIC virtualization.
5030 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5031 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5032 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5035 if (nested_cpu_has_posted_intr(vmcs12
)) {
5036 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5037 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5042 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5049 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5052 vmx
->nested
.pi_pending
= false;
5053 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5056 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5057 if (max_irr
!= 256) {
5058 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5059 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5060 kunmap(vmx
->nested
.virtual_apic_page
);
5062 status
= vmcs_read16(GUEST_INTR_STATUS
);
5063 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5065 status
|= (u8
)max_irr
;
5066 vmcs_write16(GUEST_INTR_STATUS
, status
);
5070 nested_mark_vmcs12_pages_dirty(vcpu
);
5073 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5077 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5079 if (vcpu
->mode
== IN_GUEST_MODE
) {
5080 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5083 * Currently, we don't support urgent interrupt,
5084 * all interrupts are recognized as non-urgent
5085 * interrupt, so we cannot post interrupts when
5088 * If the vcpu is in guest mode, it means it is
5089 * running instead of being scheduled out and
5090 * waiting in the run queue, and that's the only
5091 * case when 'SN' is set currently, warning if
5094 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
5096 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5103 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5106 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5108 if (is_guest_mode(vcpu
) &&
5109 vector
== vmx
->nested
.posted_intr_nv
) {
5110 /* the PIR and ON have been set by L1. */
5111 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5113 * If a posted intr is not recognized by hardware,
5114 * we will accomplish it in the next vmentry.
5116 vmx
->nested
.pi_pending
= true;
5117 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5123 * Send interrupt to vcpu via posted interrupt way.
5124 * 1. If target vcpu is running(non-root mode), send posted interrupt
5125 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5126 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5127 * interrupt from PIR in next vmentry.
5129 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5131 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5134 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5138 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5141 /* If a previous notification has sent the IPI, nothing to do. */
5142 if (pi_test_and_set_on(&vmx
->pi_desc
))
5145 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5146 kvm_vcpu_kick(vcpu
);
5150 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5151 * will not change in the lifetime of the guest.
5152 * Note that host-state that does change is set elsewhere. E.g., host-state
5153 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5155 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5160 unsigned long cr0
, cr3
, cr4
;
5163 WARN_ON(cr0
& X86_CR0_TS
);
5164 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5167 * Save the most likely value for this task's CR3 in the VMCS.
5168 * We can't use __get_current_cr3_fast() because we're not atomic.
5171 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5172 vmx
->host_state
.vmcs_host_cr3
= cr3
;
5174 /* Save the most likely value for this task's CR4 in the VMCS. */
5175 cr4
= cr4_read_shadow();
5176 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5177 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5179 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5180 #ifdef CONFIG_X86_64
5182 * Load null selectors, so we can avoid reloading them in
5183 * __vmx_load_host_state(), in case userspace uses the null selectors
5184 * too (the expected case).
5186 vmcs_write16(HOST_DS_SELECTOR
, 0);
5187 vmcs_write16(HOST_ES_SELECTOR
, 0);
5189 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5190 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5192 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5193 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5196 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5197 vmx
->host_idt_base
= dt
.address
;
5199 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5201 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5202 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5203 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5204 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5206 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5207 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5208 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5212 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5214 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5216 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5217 if (is_guest_mode(&vmx
->vcpu
))
5218 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5219 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5220 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5223 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5225 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5227 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5228 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5229 /* Enable the preemption timer dynamically */
5230 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5231 return pin_based_exec_ctrl
;
5234 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5238 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5239 if (cpu_has_secondary_exec_ctrls()) {
5240 if (kvm_vcpu_apicv_active(vcpu
))
5241 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5242 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5243 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5245 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5246 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5247 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5250 if (cpu_has_vmx_msr_bitmap())
5251 vmx_set_msr_bitmap(vcpu
);
5254 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5256 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5258 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5259 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5261 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5262 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5263 #ifdef CONFIG_X86_64
5264 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5265 CPU_BASED_CR8_LOAD_EXITING
;
5269 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5270 CPU_BASED_CR3_LOAD_EXITING
|
5271 CPU_BASED_INVLPG_EXITING
;
5272 return exec_control
;
5275 static bool vmx_rdrand_supported(void)
5277 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5278 SECONDARY_EXEC_RDRAND
;
5281 static bool vmx_rdseed_supported(void)
5283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5284 SECONDARY_EXEC_RDSEED
;
5287 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5289 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5291 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5292 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5293 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5295 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5297 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5298 enable_unrestricted_guest
= 0;
5299 /* Enable INVPCID for non-ept guests may cause performance regression. */
5300 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5302 if (!enable_unrestricted_guest
)
5303 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5305 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5306 if (!kvm_vcpu_apicv_active(vcpu
))
5307 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5308 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5309 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5310 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5312 We can NOT enable shadow_vmcs here because we don't have yet
5315 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5318 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5320 if (vmx_xsaves_supported()) {
5321 /* Exposing XSAVES only when XSAVE is exposed */
5322 bool xsaves_enabled
=
5323 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5324 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5326 if (!xsaves_enabled
)
5327 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5331 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5332 SECONDARY_EXEC_XSAVES
;
5334 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5335 ~SECONDARY_EXEC_XSAVES
;
5339 if (vmx_rdtscp_supported()) {
5340 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5341 if (!rdtscp_enabled
)
5342 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5346 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5347 SECONDARY_EXEC_RDTSCP
;
5349 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5350 ~SECONDARY_EXEC_RDTSCP
;
5354 if (vmx_invpcid_supported()) {
5355 /* Exposing INVPCID only when PCID is exposed */
5356 bool invpcid_enabled
=
5357 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5358 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5360 if (!invpcid_enabled
) {
5361 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5362 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5366 if (invpcid_enabled
)
5367 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5368 SECONDARY_EXEC_ENABLE_INVPCID
;
5370 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5371 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5375 if (vmx_rdrand_supported()) {
5376 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5378 exec_control
&= ~SECONDARY_EXEC_RDRAND
;
5382 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5383 SECONDARY_EXEC_RDRAND
;
5385 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5386 ~SECONDARY_EXEC_RDRAND
;
5390 if (vmx_rdseed_supported()) {
5391 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5393 exec_control
&= ~SECONDARY_EXEC_RDSEED
;
5397 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5398 SECONDARY_EXEC_RDSEED
;
5400 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5401 ~SECONDARY_EXEC_RDSEED
;
5405 vmx
->secondary_exec_control
= exec_control
;
5408 static void ept_set_mmio_spte_mask(void)
5411 * EPT Misconfigurations can be generated if the value of bits 2:0
5412 * of an EPT paging-structure entry is 110b (write/execute).
5414 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5415 VMX_EPT_MISCONFIG_WX_VALUE
);
5418 #define VMX_XSS_EXIT_BITMAP 0
5420 * Sets up the vmcs for emulated real mode.
5422 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5424 #ifdef CONFIG_X86_64
5430 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5431 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5433 if (enable_shadow_vmcs
) {
5434 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5435 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5437 if (cpu_has_vmx_msr_bitmap())
5438 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5440 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5443 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5444 vmx
->hv_deadline_tsc
= -1;
5446 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5448 if (cpu_has_secondary_exec_ctrls()) {
5449 vmx_compute_secondary_exec_control(vmx
);
5450 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5451 vmx
->secondary_exec_control
);
5454 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5455 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5456 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5457 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5458 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5460 vmcs_write16(GUEST_INTR_STATUS
, 0);
5462 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5463 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5467 vmcs_write32(PLE_GAP
, ple_gap
);
5468 vmx
->ple_window
= ple_window
;
5469 vmx
->ple_window_dirty
= true;
5472 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5473 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5474 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5476 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5477 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5478 vmx_set_constant_host_state(vmx
);
5479 #ifdef CONFIG_X86_64
5480 rdmsrl(MSR_FS_BASE
, a
);
5481 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5482 rdmsrl(MSR_GS_BASE
, a
);
5483 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5485 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5486 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5489 if (cpu_has_vmx_vmfunc())
5490 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5492 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5493 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5494 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5495 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5496 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5498 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5499 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5501 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5502 u32 index
= vmx_msr_index
[i
];
5503 u32 data_low
, data_high
;
5506 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5508 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5510 vmx
->guest_msrs
[j
].index
= i
;
5511 vmx
->guest_msrs
[j
].data
= 0;
5512 vmx
->guest_msrs
[j
].mask
= -1ull;
5517 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5519 /* 22.2.1, 20.8.1 */
5520 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5522 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5523 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5525 set_cr4_guest_host_mask(vmx
);
5527 if (vmx_xsaves_supported())
5528 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5531 ASSERT(vmx
->pml_pg
);
5532 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5533 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5539 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5542 struct msr_data apic_base_msr
;
5545 vmx
->rmode
.vm86_active
= 0;
5547 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5548 kvm_set_cr8(vcpu
, 0);
5551 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5552 MSR_IA32_APICBASE_ENABLE
;
5553 if (kvm_vcpu_is_reset_bsp(vcpu
))
5554 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5555 apic_base_msr
.host_initiated
= true;
5556 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5559 vmx_segment_cache_clear(vmx
);
5561 seg_setup(VCPU_SREG_CS
);
5562 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5563 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5565 seg_setup(VCPU_SREG_DS
);
5566 seg_setup(VCPU_SREG_ES
);
5567 seg_setup(VCPU_SREG_FS
);
5568 seg_setup(VCPU_SREG_GS
);
5569 seg_setup(VCPU_SREG_SS
);
5571 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5572 vmcs_writel(GUEST_TR_BASE
, 0);
5573 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5574 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5576 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5577 vmcs_writel(GUEST_LDTR_BASE
, 0);
5578 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5579 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5582 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5583 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5584 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5585 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5588 vmcs_writel(GUEST_RFLAGS
, 0x02);
5589 kvm_rip_write(vcpu
, 0xfff0);
5591 vmcs_writel(GUEST_GDTR_BASE
, 0);
5592 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5594 vmcs_writel(GUEST_IDTR_BASE
, 0);
5595 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5597 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5598 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5599 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5603 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5605 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5606 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5607 if (cpu_need_tpr_shadow(vcpu
))
5608 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5609 __pa(vcpu
->arch
.apic
->regs
));
5610 vmcs_write32(TPR_THRESHOLD
, 0);
5613 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5615 if (kvm_vcpu_apicv_active(vcpu
))
5616 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5619 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5621 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5622 vmx
->vcpu
.arch
.cr0
= cr0
;
5623 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5624 vmx_set_cr4(vcpu
, 0);
5625 vmx_set_efer(vcpu
, 0);
5627 update_exception_bitmap(vcpu
);
5629 vpid_sync_context(vmx
->vpid
);
5633 * In nested virtualization, check if L1 asked to exit on external interrupts.
5634 * For most existing hypervisors, this will always return true.
5636 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5638 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5639 PIN_BASED_EXT_INTR_MASK
;
5643 * In nested virtualization, check if L1 has set
5644 * VM_EXIT_ACK_INTR_ON_EXIT
5646 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5648 return get_vmcs12(vcpu
)->vm_exit_controls
&
5649 VM_EXIT_ACK_INTR_ON_EXIT
;
5652 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5654 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5655 PIN_BASED_NMI_EXITING
;
5658 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5660 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5661 CPU_BASED_VIRTUAL_INTR_PENDING
);
5664 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5666 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5667 enable_irq_window(vcpu
);
5671 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5672 CPU_BASED_VIRTUAL_NMI_PENDING
);
5675 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5679 int irq
= vcpu
->arch
.interrupt
.nr
;
5681 trace_kvm_inj_virq(irq
);
5683 ++vcpu
->stat
.irq_injections
;
5684 if (vmx
->rmode
.vm86_active
) {
5686 if (vcpu
->arch
.interrupt
.soft
)
5687 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5688 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5689 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5692 intr
= irq
| INTR_INFO_VALID_MASK
;
5693 if (vcpu
->arch
.interrupt
.soft
) {
5694 intr
|= INTR_TYPE_SOFT_INTR
;
5695 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5696 vmx
->vcpu
.arch
.event_exit_inst_len
);
5698 intr
|= INTR_TYPE_EXT_INTR
;
5699 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5702 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5704 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5706 ++vcpu
->stat
.nmi_injections
;
5707 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5709 if (vmx
->rmode
.vm86_active
) {
5710 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5711 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5715 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5716 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5719 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5721 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5724 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5726 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5727 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5731 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5735 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5737 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5738 GUEST_INTR_STATE_NMI
);
5740 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5741 GUEST_INTR_STATE_NMI
);
5744 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5746 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5749 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5750 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5751 | GUEST_INTR_STATE_NMI
));
5754 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5756 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5757 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5758 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5759 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5762 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5766 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5770 kvm
->arch
.tss_addr
= addr
;
5771 return init_rmode_tss(kvm
);
5774 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5779 * Update instruction length as we may reinject the exception
5780 * from user space while in guest debugging mode.
5782 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5783 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5784 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5788 if (vcpu
->guest_debug
&
5789 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5806 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5807 int vec
, u32 err_code
)
5810 * Instruction with address size override prefix opcode 0x67
5811 * Cause the #SS fault with 0 error code in VM86 mode.
5813 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5814 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5815 if (vcpu
->arch
.halt_request
) {
5816 vcpu
->arch
.halt_request
= 0;
5817 return kvm_vcpu_halt(vcpu
);
5825 * Forward all other exceptions that are valid in real mode.
5826 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5827 * the required debugging infrastructure rework.
5829 kvm_queue_exception(vcpu
, vec
);
5834 * Trigger machine check on the host. We assume all the MSRs are already set up
5835 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5836 * We pass a fake environment to the machine check handler because we want
5837 * the guest to be always treated like user space, no matter what context
5838 * it used internally.
5840 static void kvm_machine_check(void)
5842 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5843 struct pt_regs regs
= {
5844 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5845 .flags
= X86_EFLAGS_IF
,
5848 do_machine_check(®s
, 0);
5852 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5854 /* already handled by vcpu_run */
5858 static int handle_exception(struct kvm_vcpu
*vcpu
)
5860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5861 struct kvm_run
*kvm_run
= vcpu
->run
;
5862 u32 intr_info
, ex_no
, error_code
;
5863 unsigned long cr2
, rip
, dr6
;
5865 enum emulation_result er
;
5867 vect_info
= vmx
->idt_vectoring_info
;
5868 intr_info
= vmx
->exit_intr_info
;
5870 if (is_machine_check(intr_info
))
5871 return handle_machine_check(vcpu
);
5873 if (is_nmi(intr_info
))
5874 return 1; /* already handled by vmx_vcpu_run() */
5876 if (is_invalid_opcode(intr_info
)) {
5877 if (is_guest_mode(vcpu
)) {
5878 kvm_queue_exception(vcpu
, UD_VECTOR
);
5881 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5882 if (er
!= EMULATE_DONE
)
5883 kvm_queue_exception(vcpu
, UD_VECTOR
);
5888 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5889 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5892 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5893 * MMIO, it is better to report an internal error.
5894 * See the comments in vmx_handle_exit.
5896 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5897 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5898 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5899 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5900 vcpu
->run
->internal
.ndata
= 3;
5901 vcpu
->run
->internal
.data
[0] = vect_info
;
5902 vcpu
->run
->internal
.data
[1] = intr_info
;
5903 vcpu
->run
->internal
.data
[2] = error_code
;
5907 if (is_page_fault(intr_info
)) {
5908 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5909 /* EPT won't cause page fault directly */
5910 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5911 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5915 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5917 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5918 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5922 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5925 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5926 if (!(vcpu
->guest_debug
&
5927 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5928 vcpu
->arch
.dr6
&= ~15;
5929 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5930 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5931 skip_emulated_instruction(vcpu
);
5933 kvm_queue_exception(vcpu
, DB_VECTOR
);
5936 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5937 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5941 * Update instruction length as we may reinject #BP from
5942 * user space while in guest debugging mode. Reading it for
5943 * #DB as well causes no harm, it is not used in that case.
5945 vmx
->vcpu
.arch
.event_exit_inst_len
=
5946 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5947 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5948 rip
= kvm_rip_read(vcpu
);
5949 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5950 kvm_run
->debug
.arch
.exception
= ex_no
;
5953 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5954 kvm_run
->ex
.exception
= ex_no
;
5955 kvm_run
->ex
.error_code
= error_code
;
5961 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5963 ++vcpu
->stat
.irq_exits
;
5967 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5969 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5970 vcpu
->mmio_needed
= 0;
5974 static int handle_io(struct kvm_vcpu
*vcpu
)
5976 unsigned long exit_qualification
;
5977 int size
, in
, string
, ret
;
5980 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5981 string
= (exit_qualification
& 16) != 0;
5982 in
= (exit_qualification
& 8) != 0;
5984 ++vcpu
->stat
.io_exits
;
5987 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5989 port
= exit_qualification
>> 16;
5990 size
= (exit_qualification
& 7) + 1;
5992 ret
= kvm_skip_emulated_instruction(vcpu
);
5995 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5996 * KVM_EXIT_DEBUG here.
5998 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6002 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6005 * Patch in the VMCALL instruction:
6007 hypercall
[0] = 0x0f;
6008 hypercall
[1] = 0x01;
6009 hypercall
[2] = 0xc1;
6012 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6013 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6015 if (is_guest_mode(vcpu
)) {
6016 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6017 unsigned long orig_val
= val
;
6020 * We get here when L2 changed cr0 in a way that did not change
6021 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6022 * but did change L0 shadowed bits. So we first calculate the
6023 * effective cr0 value that L1 would like to write into the
6024 * hardware. It consists of the L2-owned bits from the new
6025 * value combined with the L1-owned bits from L1's guest_cr0.
6027 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6028 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6030 if (!nested_guest_cr0_valid(vcpu
, val
))
6033 if (kvm_set_cr0(vcpu
, val
))
6035 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6038 if (to_vmx(vcpu
)->nested
.vmxon
&&
6039 !nested_host_cr0_valid(vcpu
, val
))
6042 return kvm_set_cr0(vcpu
, val
);
6046 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6048 if (is_guest_mode(vcpu
)) {
6049 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6050 unsigned long orig_val
= val
;
6052 /* analogously to handle_set_cr0 */
6053 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6054 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6055 if (kvm_set_cr4(vcpu
, val
))
6057 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6060 return kvm_set_cr4(vcpu
, val
);
6063 static int handle_cr(struct kvm_vcpu
*vcpu
)
6065 unsigned long exit_qualification
, val
;
6071 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6072 cr
= exit_qualification
& 15;
6073 reg
= (exit_qualification
>> 8) & 15;
6074 switch ((exit_qualification
>> 4) & 3) {
6075 case 0: /* mov to cr */
6076 val
= kvm_register_readl(vcpu
, reg
);
6077 trace_kvm_cr_write(cr
, val
);
6080 err
= handle_set_cr0(vcpu
, val
);
6081 return kvm_complete_insn_gp(vcpu
, err
);
6083 err
= kvm_set_cr3(vcpu
, val
);
6084 return kvm_complete_insn_gp(vcpu
, err
);
6086 err
= handle_set_cr4(vcpu
, val
);
6087 return kvm_complete_insn_gp(vcpu
, err
);
6089 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6091 err
= kvm_set_cr8(vcpu
, cr8
);
6092 ret
= kvm_complete_insn_gp(vcpu
, err
);
6093 if (lapic_in_kernel(vcpu
))
6095 if (cr8_prev
<= cr8
)
6098 * TODO: we might be squashing a
6099 * KVM_GUESTDBG_SINGLESTEP-triggered
6100 * KVM_EXIT_DEBUG here.
6102 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6108 WARN_ONCE(1, "Guest should always own CR0.TS");
6109 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6110 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6111 return kvm_skip_emulated_instruction(vcpu
);
6112 case 1: /*mov from cr*/
6115 val
= kvm_read_cr3(vcpu
);
6116 kvm_register_write(vcpu
, reg
, val
);
6117 trace_kvm_cr_read(cr
, val
);
6118 return kvm_skip_emulated_instruction(vcpu
);
6120 val
= kvm_get_cr8(vcpu
);
6121 kvm_register_write(vcpu
, reg
, val
);
6122 trace_kvm_cr_read(cr
, val
);
6123 return kvm_skip_emulated_instruction(vcpu
);
6127 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6128 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6129 kvm_lmsw(vcpu
, val
);
6131 return kvm_skip_emulated_instruction(vcpu
);
6135 vcpu
->run
->exit_reason
= 0;
6136 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6137 (int)(exit_qualification
>> 4) & 3, cr
);
6141 static int handle_dr(struct kvm_vcpu
*vcpu
)
6143 unsigned long exit_qualification
;
6146 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6147 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6149 /* First, if DR does not exist, trigger UD */
6150 if (!kvm_require_dr(vcpu
, dr
))
6153 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6154 if (!kvm_require_cpl(vcpu
, 0))
6156 dr7
= vmcs_readl(GUEST_DR7
);
6159 * As the vm-exit takes precedence over the debug trap, we
6160 * need to emulate the latter, either for the host or the
6161 * guest debugging itself.
6163 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6164 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6165 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6166 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6167 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6168 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6171 vcpu
->arch
.dr6
&= ~15;
6172 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6173 kvm_queue_exception(vcpu
, DB_VECTOR
);
6178 if (vcpu
->guest_debug
== 0) {
6179 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6180 CPU_BASED_MOV_DR_EXITING
);
6183 * No more DR vmexits; force a reload of the debug registers
6184 * and reenter on this instruction. The next vmexit will
6185 * retrieve the full state of the debug registers.
6187 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6191 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6192 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6195 if (kvm_get_dr(vcpu
, dr
, &val
))
6197 kvm_register_write(vcpu
, reg
, val
);
6199 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6202 return kvm_skip_emulated_instruction(vcpu
);
6205 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6207 return vcpu
->arch
.dr6
;
6210 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6214 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6216 get_debugreg(vcpu
->arch
.db
[0], 0);
6217 get_debugreg(vcpu
->arch
.db
[1], 1);
6218 get_debugreg(vcpu
->arch
.db
[2], 2);
6219 get_debugreg(vcpu
->arch
.db
[3], 3);
6220 get_debugreg(vcpu
->arch
.dr6
, 6);
6221 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6223 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6224 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6227 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6229 vmcs_writel(GUEST_DR7
, val
);
6232 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6234 return kvm_emulate_cpuid(vcpu
);
6237 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6239 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6240 struct msr_data msr_info
;
6242 msr_info
.index
= ecx
;
6243 msr_info
.host_initiated
= false;
6244 if (vmx_get_msr(vcpu
, &msr_info
)) {
6245 trace_kvm_msr_read_ex(ecx
);
6246 kvm_inject_gp(vcpu
, 0);
6250 trace_kvm_msr_read(ecx
, msr_info
.data
);
6252 /* FIXME: handling of bits 32:63 of rax, rdx */
6253 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6254 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6255 return kvm_skip_emulated_instruction(vcpu
);
6258 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6260 struct msr_data msr
;
6261 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6262 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6263 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6267 msr
.host_initiated
= false;
6268 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6269 trace_kvm_msr_write_ex(ecx
, data
);
6270 kvm_inject_gp(vcpu
, 0);
6274 trace_kvm_msr_write(ecx
, data
);
6275 return kvm_skip_emulated_instruction(vcpu
);
6278 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6280 kvm_apic_update_ppr(vcpu
);
6284 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6286 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6287 CPU_BASED_VIRTUAL_INTR_PENDING
);
6289 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6291 ++vcpu
->stat
.irq_window_exits
;
6295 static int handle_halt(struct kvm_vcpu
*vcpu
)
6297 return kvm_emulate_halt(vcpu
);
6300 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6302 return kvm_emulate_hypercall(vcpu
);
6305 static int handle_invd(struct kvm_vcpu
*vcpu
)
6307 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6310 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6312 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6314 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6315 return kvm_skip_emulated_instruction(vcpu
);
6318 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6322 err
= kvm_rdpmc(vcpu
);
6323 return kvm_complete_insn_gp(vcpu
, err
);
6326 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6328 return kvm_emulate_wbinvd(vcpu
);
6331 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6333 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6334 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6336 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6337 return kvm_skip_emulated_instruction(vcpu
);
6341 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6343 kvm_skip_emulated_instruction(vcpu
);
6344 WARN(1, "this should never happen\n");
6348 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6350 kvm_skip_emulated_instruction(vcpu
);
6351 WARN(1, "this should never happen\n");
6355 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6357 if (likely(fasteoi
)) {
6358 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6359 int access_type
, offset
;
6361 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6362 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6364 * Sane guest uses MOV to write EOI, with written value
6365 * not cared. So make a short-circuit here by avoiding
6366 * heavy instruction emulation.
6368 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6369 (offset
== APIC_EOI
)) {
6370 kvm_lapic_set_eoi(vcpu
);
6371 return kvm_skip_emulated_instruction(vcpu
);
6374 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6377 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6379 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6380 int vector
= exit_qualification
& 0xff;
6382 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6383 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6387 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6389 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6390 u32 offset
= exit_qualification
& 0xfff;
6392 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6393 kvm_apic_write_nodecode(vcpu
, offset
);
6397 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6399 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6400 unsigned long exit_qualification
;
6401 bool has_error_code
= false;
6404 int reason
, type
, idt_v
, idt_index
;
6406 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6407 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6408 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6410 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6412 reason
= (u32
)exit_qualification
>> 30;
6413 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6415 case INTR_TYPE_NMI_INTR
:
6416 vcpu
->arch
.nmi_injected
= false;
6417 vmx_set_nmi_mask(vcpu
, true);
6419 case INTR_TYPE_EXT_INTR
:
6420 case INTR_TYPE_SOFT_INTR
:
6421 kvm_clear_interrupt_queue(vcpu
);
6423 case INTR_TYPE_HARD_EXCEPTION
:
6424 if (vmx
->idt_vectoring_info
&
6425 VECTORING_INFO_DELIVER_CODE_MASK
) {
6426 has_error_code
= true;
6428 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6431 case INTR_TYPE_SOFT_EXCEPTION
:
6432 kvm_clear_exception_queue(vcpu
);
6438 tss_selector
= exit_qualification
;
6440 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6441 type
!= INTR_TYPE_EXT_INTR
&&
6442 type
!= INTR_TYPE_NMI_INTR
))
6443 skip_emulated_instruction(vcpu
);
6445 if (kvm_task_switch(vcpu
, tss_selector
,
6446 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6447 has_error_code
, error_code
) == EMULATE_FAIL
) {
6448 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6449 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6450 vcpu
->run
->internal
.ndata
= 0;
6455 * TODO: What about debug traps on tss switch?
6456 * Are we supposed to inject them and update dr6?
6462 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6464 unsigned long exit_qualification
;
6468 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6471 * EPT violation happened while executing iret from NMI,
6472 * "blocked by NMI" bit has to be set before next VM entry.
6473 * There are errata that may cause this bit to not be set:
6476 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6477 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6478 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6480 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6481 trace_kvm_page_fault(gpa
, exit_qualification
);
6483 /* Is it a read fault? */
6484 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6485 ? PFERR_USER_MASK
: 0;
6486 /* Is it a write fault? */
6487 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6488 ? PFERR_WRITE_MASK
: 0;
6489 /* Is it a fetch fault? */
6490 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6491 ? PFERR_FETCH_MASK
: 0;
6492 /* ept page table entry is present? */
6493 error_code
|= (exit_qualification
&
6494 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6495 EPT_VIOLATION_EXECUTABLE
))
6496 ? PFERR_PRESENT_MASK
: 0;
6498 error_code
|= (exit_qualification
& 0x100) != 0 ?
6499 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6501 vcpu
->arch
.exit_qualification
= exit_qualification
;
6502 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6505 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6511 * A nested guest cannot optimize MMIO vmexits, because we have an
6512 * nGPA here instead of the required GPA.
6514 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6515 if (!is_guest_mode(vcpu
) &&
6516 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6517 trace_kvm_fast_mmio(gpa
);
6518 return kvm_skip_emulated_instruction(vcpu
);
6521 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6525 /* It is the real ept misconfig */
6528 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6529 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6534 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6536 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6537 CPU_BASED_VIRTUAL_NMI_PENDING
);
6538 ++vcpu
->stat
.nmi_window_exits
;
6539 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6544 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6546 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6547 enum emulation_result err
= EMULATE_DONE
;
6550 bool intr_window_requested
;
6551 unsigned count
= 130;
6553 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6554 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6556 while (vmx
->emulation_required
&& count
-- != 0) {
6557 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6558 return handle_interrupt_window(&vmx
->vcpu
);
6560 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6563 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6565 if (err
== EMULATE_USER_EXIT
) {
6566 ++vcpu
->stat
.mmio_exits
;
6571 if (err
!= EMULATE_DONE
) {
6572 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6573 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6574 vcpu
->run
->internal
.ndata
= 0;
6578 if (vcpu
->arch
.halt_request
) {
6579 vcpu
->arch
.halt_request
= 0;
6580 ret
= kvm_vcpu_halt(vcpu
);
6584 if (signal_pending(current
))
6594 static int __grow_ple_window(int val
)
6596 if (ple_window_grow
< 1)
6599 val
= min(val
, ple_window_actual_max
);
6601 if (ple_window_grow
< ple_window
)
6602 val
*= ple_window_grow
;
6604 val
+= ple_window_grow
;
6609 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6614 if (modifier
< ple_window
)
6619 return max(val
, minimum
);
6622 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6624 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6625 int old
= vmx
->ple_window
;
6627 vmx
->ple_window
= __grow_ple_window(old
);
6629 if (vmx
->ple_window
!= old
)
6630 vmx
->ple_window_dirty
= true;
6632 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6635 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6637 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6638 int old
= vmx
->ple_window
;
6640 vmx
->ple_window
= __shrink_ple_window(old
,
6641 ple_window_shrink
, ple_window
);
6643 if (vmx
->ple_window
!= old
)
6644 vmx
->ple_window_dirty
= true;
6646 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6650 * ple_window_actual_max is computed to be one grow_ple_window() below
6651 * ple_window_max. (See __grow_ple_window for the reason.)
6652 * This prevents overflows, because ple_window_max is int.
6653 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6655 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6657 static void update_ple_window_actual_max(void)
6659 ple_window_actual_max
=
6660 __shrink_ple_window(max(ple_window_max
, ple_window
),
6661 ple_window_grow
, INT_MIN
);
6665 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6667 static void wakeup_handler(void)
6669 struct kvm_vcpu
*vcpu
;
6670 int cpu
= smp_processor_id();
6672 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6673 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6674 blocked_vcpu_list
) {
6675 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6677 if (pi_test_on(pi_desc
) == 1)
6678 kvm_vcpu_kick(vcpu
);
6680 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6683 void vmx_enable_tdp(void)
6685 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6686 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6687 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6688 0ull, VMX_EPT_EXECUTABLE_MASK
,
6689 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6690 VMX_EPT_RWX_MASK
, 0ull);
6692 ept_set_mmio_spte_mask();
6696 static __init
int hardware_setup(void)
6698 int r
= -ENOMEM
, i
, msr
;
6700 rdmsrl_safe(MSR_EFER
, &host_efer
);
6702 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6703 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6705 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6706 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6711 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6712 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6713 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6716 * Allow direct access to the PC debug port (it is often used for I/O
6717 * delays, but the vmexits simply slow things down).
6719 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6720 clear_bit(0x80, vmx_io_bitmap_a
);
6722 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6724 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6725 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6727 if (setup_vmcs_config(&vmcs_config
) < 0) {
6732 if (boot_cpu_has(X86_FEATURE_NX
))
6733 kvm_enable_efer_bits(EFER_NX
);
6735 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6736 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6739 if (!cpu_has_vmx_shadow_vmcs())
6740 enable_shadow_vmcs
= 0;
6741 if (enable_shadow_vmcs
)
6742 init_vmcs_shadow_fields();
6744 if (!cpu_has_vmx_ept() ||
6745 !cpu_has_vmx_ept_4levels() ||
6746 !cpu_has_vmx_ept_mt_wb()) {
6748 enable_unrestricted_guest
= 0;
6749 enable_ept_ad_bits
= 0;
6752 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6753 enable_ept_ad_bits
= 0;
6755 if (!cpu_has_vmx_unrestricted_guest())
6756 enable_unrestricted_guest
= 0;
6758 if (!cpu_has_vmx_flexpriority())
6759 flexpriority_enabled
= 0;
6762 * set_apic_access_page_addr() is used to reload apic access
6763 * page upon invalidation. No need to do anything if not
6764 * using the APIC_ACCESS_ADDR VMCS field.
6766 if (!flexpriority_enabled
)
6767 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6769 if (!cpu_has_vmx_tpr_shadow())
6770 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6772 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6773 kvm_disable_largepages();
6775 if (!cpu_has_vmx_ple())
6778 if (!cpu_has_vmx_apicv()) {
6780 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6783 if (cpu_has_vmx_tsc_scaling()) {
6784 kvm_has_tsc_control
= true;
6785 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6786 kvm_tsc_scaling_ratio_frac_bits
= 48;
6789 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6790 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6791 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6792 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6793 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6794 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6796 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6797 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6798 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6799 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6800 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6801 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6802 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6803 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6805 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6807 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6808 if (msr
== 0x839 /* TMCCT */)
6810 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6814 * TPR reads and writes can be virtualized even if virtual interrupt
6815 * delivery is not in use.
6817 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6818 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6821 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6823 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6830 update_ple_window_actual_max();
6833 * Only enable PML when hardware supports PML feature, and both EPT
6834 * and EPT A/D bit features are enabled -- PML depends on them to work.
6836 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6840 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6841 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6842 kvm_x86_ops
->flush_log_dirty
= NULL
;
6843 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6846 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6849 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6850 cpu_preemption_timer_multi
=
6851 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6853 kvm_x86_ops
->set_hv_timer
= NULL
;
6854 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6857 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6859 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6861 return alloc_kvm_area();
6864 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6865 free_page((unsigned long)vmx_bitmap
[i
]);
6870 static __exit
void hardware_unsetup(void)
6874 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6875 free_page((unsigned long)vmx_bitmap
[i
]);
6881 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6882 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6884 static int handle_pause(struct kvm_vcpu
*vcpu
)
6887 grow_ple_window(vcpu
);
6890 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6891 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6892 * never set PAUSE_EXITING and just set PLE if supported,
6893 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6895 kvm_vcpu_on_spin(vcpu
, true);
6896 return kvm_skip_emulated_instruction(vcpu
);
6899 static int handle_nop(struct kvm_vcpu
*vcpu
)
6901 return kvm_skip_emulated_instruction(vcpu
);
6904 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6906 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6907 return handle_nop(vcpu
);
6910 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6912 kvm_queue_exception(vcpu
, UD_VECTOR
);
6916 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6921 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6923 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6924 return handle_nop(vcpu
);
6928 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6929 * We could reuse a single VMCS for all the L2 guests, but we also want the
6930 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6931 * allows keeping them loaded on the processor, and in the future will allow
6932 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6933 * every entry if they never change.
6934 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6935 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6937 * The following functions allocate and free a vmcs02 in this pool.
6940 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6941 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6943 struct vmcs02_list
*item
;
6944 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6945 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6946 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6947 return &item
->vmcs02
;
6950 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6951 /* Recycle the least recently used VMCS. */
6952 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6953 struct vmcs02_list
, list
);
6954 item
->vmptr
= vmx
->nested
.current_vmptr
;
6955 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6956 return &item
->vmcs02
;
6959 /* Create a new VMCS */
6960 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6963 item
->vmcs02
.vmcs
= alloc_vmcs();
6964 item
->vmcs02
.shadow_vmcs
= NULL
;
6965 if (!item
->vmcs02
.vmcs
) {
6969 loaded_vmcs_init(&item
->vmcs02
);
6970 item
->vmptr
= vmx
->nested
.current_vmptr
;
6971 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6972 vmx
->nested
.vmcs02_num
++;
6973 return &item
->vmcs02
;
6976 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6977 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6979 struct vmcs02_list
*item
;
6980 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6981 if (item
->vmptr
== vmptr
) {
6982 free_loaded_vmcs(&item
->vmcs02
);
6983 list_del(&item
->list
);
6985 vmx
->nested
.vmcs02_num
--;
6991 * Free all VMCSs saved for this vcpu, except the one pointed by
6992 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6993 * must be &vmx->vmcs01.
6995 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6997 struct vmcs02_list
*item
, *n
;
6999 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7000 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7002 * Something will leak if the above WARN triggers. Better than
7005 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7008 free_loaded_vmcs(&item
->vmcs02
);
7009 list_del(&item
->list
);
7011 vmx
->nested
.vmcs02_num
--;
7016 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7017 * set the success or error code of an emulated VMX instruction, as specified
7018 * by Vol 2B, VMX Instruction Reference, "Conventions".
7020 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7022 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7023 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7024 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7027 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7029 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7030 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7031 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7035 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7036 u32 vm_instruction_error
)
7038 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7040 * failValid writes the error number to the current VMCS, which
7041 * can't be done there isn't a current VMCS.
7043 nested_vmx_failInvalid(vcpu
);
7046 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7047 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7048 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7050 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7052 * We don't need to force a shadow sync because
7053 * VM_INSTRUCTION_ERROR is not shadowed
7057 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7059 /* TODO: not to reset guest simply here. */
7060 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7061 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7064 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7066 struct vcpu_vmx
*vmx
=
7067 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7069 vmx
->nested
.preemption_timer_expired
= true;
7070 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7071 kvm_vcpu_kick(&vmx
->vcpu
);
7073 return HRTIMER_NORESTART
;
7077 * Decode the memory-address operand of a vmx instruction, as recorded on an
7078 * exit caused by such an instruction (run by a guest hypervisor).
7079 * On success, returns 0. When the operand is invalid, returns 1 and throws
7082 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7083 unsigned long exit_qualification
,
7084 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7088 struct kvm_segment s
;
7091 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7092 * Execution", on an exit, vmx_instruction_info holds most of the
7093 * addressing components of the operand. Only the displacement part
7094 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7095 * For how an actual address is calculated from all these components,
7096 * refer to Vol. 1, "Operand Addressing".
7098 int scaling
= vmx_instruction_info
& 3;
7099 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7100 bool is_reg
= vmx_instruction_info
& (1u << 10);
7101 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7102 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7103 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7104 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7105 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7108 kvm_queue_exception(vcpu
, UD_VECTOR
);
7112 /* Addr = segment_base + offset */
7113 /* offset = base + [index * scale] + displacement */
7114 off
= exit_qualification
; /* holds the displacement */
7116 off
+= kvm_register_read(vcpu
, base_reg
);
7118 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7119 vmx_get_segment(vcpu
, &s
, seg_reg
);
7120 *ret
= s
.base
+ off
;
7122 if (addr_size
== 1) /* 32 bit */
7125 /* Checks for #GP/#SS exceptions. */
7127 if (is_long_mode(vcpu
)) {
7128 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7129 * non-canonical form. This is the only check on the memory
7130 * destination for long mode!
7132 exn
= is_noncanonical_address(*ret
, vcpu
);
7133 } else if (is_protmode(vcpu
)) {
7134 /* Protected mode: apply checks for segment validity in the
7136 * - segment type check (#GP(0) may be thrown)
7137 * - usability check (#GP(0)/#SS(0))
7138 * - limit check (#GP(0)/#SS(0))
7141 /* #GP(0) if the destination operand is located in a
7142 * read-only data segment or any code segment.
7144 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7146 /* #GP(0) if the source operand is located in an
7147 * execute-only code segment
7149 exn
= ((s
.type
& 0xa) == 8);
7151 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7154 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7156 exn
= (s
.unusable
!= 0);
7157 /* Protected mode: #GP(0)/#SS(0) if the memory
7158 * operand is outside the segment limit.
7160 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7163 kvm_queue_exception_e(vcpu
,
7164 seg_reg
== VCPU_SREG_SS
?
7165 SS_VECTOR
: GP_VECTOR
,
7173 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7176 struct x86_exception e
;
7178 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7179 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7182 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7183 sizeof(*vmpointer
), &e
)) {
7184 kvm_inject_page_fault(vcpu
, &e
);
7191 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7194 struct vmcs
*shadow_vmcs
;
7196 if (cpu_has_vmx_msr_bitmap()) {
7197 vmx
->nested
.msr_bitmap
=
7198 (unsigned long *)__get_free_page(GFP_KERNEL
);
7199 if (!vmx
->nested
.msr_bitmap
)
7200 goto out_msr_bitmap
;
7203 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7204 if (!vmx
->nested
.cached_vmcs12
)
7205 goto out_cached_vmcs12
;
7207 if (enable_shadow_vmcs
) {
7208 shadow_vmcs
= alloc_vmcs();
7210 goto out_shadow_vmcs
;
7211 /* mark vmcs as shadow */
7212 shadow_vmcs
->revision_id
|= (1u << 31);
7213 /* init shadow vmcs */
7214 vmcs_clear(shadow_vmcs
);
7215 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7218 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7219 vmx
->nested
.vmcs02_num
= 0;
7221 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7222 HRTIMER_MODE_REL_PINNED
);
7223 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7225 vmx
->nested
.vmxon
= true;
7229 kfree(vmx
->nested
.cached_vmcs12
);
7232 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7239 * Emulate the VMXON instruction.
7240 * Currently, we just remember that VMX is active, and do not save or even
7241 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7242 * do not currently need to store anything in that guest-allocated memory
7243 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7244 * argument is different from the VMXON pointer (which the spec says they do).
7246 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7251 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7252 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7253 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7256 * The Intel VMX Instruction Reference lists a bunch of bits that are
7257 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7258 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7259 * Otherwise, we should fail with #UD. But most faulting conditions
7260 * have already been checked by hardware, prior to the VM-exit for
7261 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7262 * that bit set to 1 in non-root mode.
7264 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7265 kvm_queue_exception(vcpu
, UD_VECTOR
);
7269 if (vmx
->nested
.vmxon
) {
7270 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7271 return kvm_skip_emulated_instruction(vcpu
);
7274 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7275 != VMXON_NEEDED_FEATURES
) {
7276 kvm_inject_gp(vcpu
, 0);
7280 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7285 * The first 4 bytes of VMXON region contain the supported
7286 * VMCS revision identifier
7288 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7289 * which replaces physical address width with 32
7291 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7292 nested_vmx_failInvalid(vcpu
);
7293 return kvm_skip_emulated_instruction(vcpu
);
7296 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7297 if (is_error_page(page
)) {
7298 nested_vmx_failInvalid(vcpu
);
7299 return kvm_skip_emulated_instruction(vcpu
);
7301 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7303 kvm_release_page_clean(page
);
7304 nested_vmx_failInvalid(vcpu
);
7305 return kvm_skip_emulated_instruction(vcpu
);
7308 kvm_release_page_clean(page
);
7310 vmx
->nested
.vmxon_ptr
= vmptr
;
7311 ret
= enter_vmx_operation(vcpu
);
7315 nested_vmx_succeed(vcpu
);
7316 return kvm_skip_emulated_instruction(vcpu
);
7320 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7321 * for running VMX instructions (except VMXON, whose prerequisites are
7322 * slightly different). It also specifies what exception to inject otherwise.
7323 * Note that many of these exceptions have priority over VM exits, so they
7324 * don't have to be checked again here.
7326 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7328 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7329 kvm_queue_exception(vcpu
, UD_VECTOR
);
7335 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7337 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7338 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7341 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7343 if (vmx
->nested
.current_vmptr
== -1ull)
7346 if (enable_shadow_vmcs
) {
7347 /* copy to memory all shadowed fields in case
7348 they were modified */
7349 copy_shadow_to_vmcs12(vmx
);
7350 vmx
->nested
.sync_shadow_vmcs
= false;
7351 vmx_disable_shadow_vmcs(vmx
);
7353 vmx
->nested
.posted_intr_nv
= -1;
7355 /* Flush VMCS12 to guest memory */
7356 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7357 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7358 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7360 vmx
->nested
.current_vmptr
= -1ull;
7364 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7365 * just stops using VMX.
7367 static void free_nested(struct vcpu_vmx
*vmx
)
7369 if (!vmx
->nested
.vmxon
)
7372 vmx
->nested
.vmxon
= false;
7373 free_vpid(vmx
->nested
.vpid02
);
7374 vmx
->nested
.posted_intr_nv
= -1;
7375 vmx
->nested
.current_vmptr
= -1ull;
7376 if (vmx
->nested
.msr_bitmap
) {
7377 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7378 vmx
->nested
.msr_bitmap
= NULL
;
7380 if (enable_shadow_vmcs
) {
7381 vmx_disable_shadow_vmcs(vmx
);
7382 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7383 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7384 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7386 kfree(vmx
->nested
.cached_vmcs12
);
7387 /* Unpin physical memory we referred to in current vmcs02 */
7388 if (vmx
->nested
.apic_access_page
) {
7389 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7390 vmx
->nested
.apic_access_page
= NULL
;
7392 if (vmx
->nested
.virtual_apic_page
) {
7393 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7394 vmx
->nested
.virtual_apic_page
= NULL
;
7396 if (vmx
->nested
.pi_desc_page
) {
7397 kunmap(vmx
->nested
.pi_desc_page
);
7398 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7399 vmx
->nested
.pi_desc_page
= NULL
;
7400 vmx
->nested
.pi_desc
= NULL
;
7403 nested_free_all_saved_vmcss(vmx
);
7406 /* Emulate the VMXOFF instruction */
7407 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7409 if (!nested_vmx_check_permission(vcpu
))
7411 free_nested(to_vmx(vcpu
));
7412 nested_vmx_succeed(vcpu
);
7413 return kvm_skip_emulated_instruction(vcpu
);
7416 /* Emulate the VMCLEAR instruction */
7417 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7419 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7423 if (!nested_vmx_check_permission(vcpu
))
7426 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7429 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7430 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7431 return kvm_skip_emulated_instruction(vcpu
);
7434 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7435 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7436 return kvm_skip_emulated_instruction(vcpu
);
7439 if (vmptr
== vmx
->nested
.current_vmptr
)
7440 nested_release_vmcs12(vmx
);
7442 kvm_vcpu_write_guest(vcpu
,
7443 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7444 &zero
, sizeof(zero
));
7446 nested_free_vmcs02(vmx
, vmptr
);
7448 nested_vmx_succeed(vcpu
);
7449 return kvm_skip_emulated_instruction(vcpu
);
7452 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7454 /* Emulate the VMLAUNCH instruction */
7455 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7457 return nested_vmx_run(vcpu
, true);
7460 /* Emulate the VMRESUME instruction */
7461 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7464 return nested_vmx_run(vcpu
, false);
7468 * Read a vmcs12 field. Since these can have varying lengths and we return
7469 * one type, we chose the biggest type (u64) and zero-extend the return value
7470 * to that size. Note that the caller, handle_vmread, might need to use only
7471 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7472 * 64-bit fields are to be returned).
7474 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7475 unsigned long field
, u64
*ret
)
7477 short offset
= vmcs_field_to_offset(field
);
7483 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7485 switch (vmcs_field_type(field
)) {
7486 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7487 *ret
= *((natural_width
*)p
);
7489 case VMCS_FIELD_TYPE_U16
:
7492 case VMCS_FIELD_TYPE_U32
:
7495 case VMCS_FIELD_TYPE_U64
:
7505 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7506 unsigned long field
, u64 field_value
){
7507 short offset
= vmcs_field_to_offset(field
);
7508 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7512 switch (vmcs_field_type(field
)) {
7513 case VMCS_FIELD_TYPE_U16
:
7514 *(u16
*)p
= field_value
;
7516 case VMCS_FIELD_TYPE_U32
:
7517 *(u32
*)p
= field_value
;
7519 case VMCS_FIELD_TYPE_U64
:
7520 *(u64
*)p
= field_value
;
7522 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7523 *(natural_width
*)p
= field_value
;
7532 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7535 unsigned long field
;
7537 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7538 const unsigned long *fields
= shadow_read_write_fields
;
7539 const int num_fields
= max_shadow_read_write_fields
;
7543 vmcs_load(shadow_vmcs
);
7545 for (i
= 0; i
< num_fields
; i
++) {
7547 switch (vmcs_field_type(field
)) {
7548 case VMCS_FIELD_TYPE_U16
:
7549 field_value
= vmcs_read16(field
);
7551 case VMCS_FIELD_TYPE_U32
:
7552 field_value
= vmcs_read32(field
);
7554 case VMCS_FIELD_TYPE_U64
:
7555 field_value
= vmcs_read64(field
);
7557 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7558 field_value
= vmcs_readl(field
);
7564 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7567 vmcs_clear(shadow_vmcs
);
7568 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7573 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7575 const unsigned long *fields
[] = {
7576 shadow_read_write_fields
,
7577 shadow_read_only_fields
7579 const int max_fields
[] = {
7580 max_shadow_read_write_fields
,
7581 max_shadow_read_only_fields
7584 unsigned long field
;
7585 u64 field_value
= 0;
7586 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7588 vmcs_load(shadow_vmcs
);
7590 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7591 for (i
= 0; i
< max_fields
[q
]; i
++) {
7592 field
= fields
[q
][i
];
7593 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7595 switch (vmcs_field_type(field
)) {
7596 case VMCS_FIELD_TYPE_U16
:
7597 vmcs_write16(field
, (u16
)field_value
);
7599 case VMCS_FIELD_TYPE_U32
:
7600 vmcs_write32(field
, (u32
)field_value
);
7602 case VMCS_FIELD_TYPE_U64
:
7603 vmcs_write64(field
, (u64
)field_value
);
7605 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7606 vmcs_writel(field
, (long)field_value
);
7615 vmcs_clear(shadow_vmcs
);
7616 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7620 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7621 * used before) all generate the same failure when it is missing.
7623 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7625 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7626 if (vmx
->nested
.current_vmptr
== -1ull) {
7627 nested_vmx_failInvalid(vcpu
);
7633 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7635 unsigned long field
;
7637 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7638 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7641 if (!nested_vmx_check_permission(vcpu
))
7644 if (!nested_vmx_check_vmcs12(vcpu
))
7645 return kvm_skip_emulated_instruction(vcpu
);
7647 /* Decode instruction info and find the field to read */
7648 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7649 /* Read the field, zero-extended to a u64 field_value */
7650 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7651 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7652 return kvm_skip_emulated_instruction(vcpu
);
7655 * Now copy part of this value to register or memory, as requested.
7656 * Note that the number of bits actually copied is 32 or 64 depending
7657 * on the guest's mode (32 or 64 bit), not on the given field's length.
7659 if (vmx_instruction_info
& (1u << 10)) {
7660 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7663 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7664 vmx_instruction_info
, true, &gva
))
7666 /* _system ok, as hardware has verified cpl=0 */
7667 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7668 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7671 nested_vmx_succeed(vcpu
);
7672 return kvm_skip_emulated_instruction(vcpu
);
7676 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7678 unsigned long field
;
7680 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7681 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7682 /* The value to write might be 32 or 64 bits, depending on L1's long
7683 * mode, and eventually we need to write that into a field of several
7684 * possible lengths. The code below first zero-extends the value to 64
7685 * bit (field_value), and then copies only the appropriate number of
7686 * bits into the vmcs12 field.
7688 u64 field_value
= 0;
7689 struct x86_exception e
;
7691 if (!nested_vmx_check_permission(vcpu
))
7694 if (!nested_vmx_check_vmcs12(vcpu
))
7695 return kvm_skip_emulated_instruction(vcpu
);
7697 if (vmx_instruction_info
& (1u << 10))
7698 field_value
= kvm_register_readl(vcpu
,
7699 (((vmx_instruction_info
) >> 3) & 0xf));
7701 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7702 vmx_instruction_info
, false, &gva
))
7704 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7705 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7706 kvm_inject_page_fault(vcpu
, &e
);
7712 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7713 if (vmcs_field_readonly(field
)) {
7714 nested_vmx_failValid(vcpu
,
7715 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7716 return kvm_skip_emulated_instruction(vcpu
);
7719 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7720 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7721 return kvm_skip_emulated_instruction(vcpu
);
7724 nested_vmx_succeed(vcpu
);
7725 return kvm_skip_emulated_instruction(vcpu
);
7728 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7730 vmx
->nested
.current_vmptr
= vmptr
;
7731 if (enable_shadow_vmcs
) {
7732 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7733 SECONDARY_EXEC_SHADOW_VMCS
);
7734 vmcs_write64(VMCS_LINK_POINTER
,
7735 __pa(vmx
->vmcs01
.shadow_vmcs
));
7736 vmx
->nested
.sync_shadow_vmcs
= true;
7740 /* Emulate the VMPTRLD instruction */
7741 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7743 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7746 if (!nested_vmx_check_permission(vcpu
))
7749 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7752 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7753 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7754 return kvm_skip_emulated_instruction(vcpu
);
7757 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7758 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7759 return kvm_skip_emulated_instruction(vcpu
);
7762 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7763 struct vmcs12
*new_vmcs12
;
7765 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7766 if (is_error_page(page
)) {
7767 nested_vmx_failInvalid(vcpu
);
7768 return kvm_skip_emulated_instruction(vcpu
);
7770 new_vmcs12
= kmap(page
);
7771 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7773 kvm_release_page_clean(page
);
7774 nested_vmx_failValid(vcpu
,
7775 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7776 return kvm_skip_emulated_instruction(vcpu
);
7779 nested_release_vmcs12(vmx
);
7781 * Load VMCS12 from guest memory since it is not already
7784 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7786 kvm_release_page_clean(page
);
7788 set_current_vmptr(vmx
, vmptr
);
7791 nested_vmx_succeed(vcpu
);
7792 return kvm_skip_emulated_instruction(vcpu
);
7795 /* Emulate the VMPTRST instruction */
7796 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7798 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7799 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7801 struct x86_exception e
;
7803 if (!nested_vmx_check_permission(vcpu
))
7806 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7807 vmx_instruction_info
, true, &vmcs_gva
))
7809 /* ok to use *_system, as hardware has verified cpl=0 */
7810 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7811 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7813 kvm_inject_page_fault(vcpu
, &e
);
7816 nested_vmx_succeed(vcpu
);
7817 return kvm_skip_emulated_instruction(vcpu
);
7820 /* Emulate the INVEPT instruction */
7821 static int handle_invept(struct kvm_vcpu
*vcpu
)
7823 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7824 u32 vmx_instruction_info
, types
;
7827 struct x86_exception e
;
7832 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7833 SECONDARY_EXEC_ENABLE_EPT
) ||
7834 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7835 kvm_queue_exception(vcpu
, UD_VECTOR
);
7839 if (!nested_vmx_check_permission(vcpu
))
7842 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7843 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7845 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7847 if (type
>= 32 || !(types
& (1 << type
))) {
7848 nested_vmx_failValid(vcpu
,
7849 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7850 return kvm_skip_emulated_instruction(vcpu
);
7853 /* According to the Intel VMX instruction reference, the memory
7854 * operand is read even if it isn't needed (e.g., for type==global)
7856 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7857 vmx_instruction_info
, false, &gva
))
7859 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7860 sizeof(operand
), &e
)) {
7861 kvm_inject_page_fault(vcpu
, &e
);
7866 case VMX_EPT_EXTENT_GLOBAL
:
7868 * TODO: track mappings and invalidate
7869 * single context requests appropriately
7871 case VMX_EPT_EXTENT_CONTEXT
:
7872 kvm_mmu_sync_roots(vcpu
);
7873 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7874 nested_vmx_succeed(vcpu
);
7881 return kvm_skip_emulated_instruction(vcpu
);
7884 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7886 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7887 u32 vmx_instruction_info
;
7888 unsigned long type
, types
;
7890 struct x86_exception e
;
7896 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7897 SECONDARY_EXEC_ENABLE_VPID
) ||
7898 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7899 kvm_queue_exception(vcpu
, UD_VECTOR
);
7903 if (!nested_vmx_check_permission(vcpu
))
7906 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7907 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7909 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7910 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7912 if (type
>= 32 || !(types
& (1 << type
))) {
7913 nested_vmx_failValid(vcpu
,
7914 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7915 return kvm_skip_emulated_instruction(vcpu
);
7918 /* according to the intel vmx instruction reference, the memory
7919 * operand is read even if it isn't needed (e.g., for type==global)
7921 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7922 vmx_instruction_info
, false, &gva
))
7924 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7925 sizeof(operand
), &e
)) {
7926 kvm_inject_page_fault(vcpu
, &e
);
7929 if (operand
.vpid
>> 16) {
7930 nested_vmx_failValid(vcpu
,
7931 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7932 return kvm_skip_emulated_instruction(vcpu
);
7936 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7937 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7938 nested_vmx_failValid(vcpu
,
7939 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7940 return kvm_skip_emulated_instruction(vcpu
);
7943 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7944 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7945 if (!operand
.vpid
) {
7946 nested_vmx_failValid(vcpu
,
7947 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7948 return kvm_skip_emulated_instruction(vcpu
);
7951 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7955 return kvm_skip_emulated_instruction(vcpu
);
7958 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7959 nested_vmx_succeed(vcpu
);
7961 return kvm_skip_emulated_instruction(vcpu
);
7964 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7966 unsigned long exit_qualification
;
7968 trace_kvm_pml_full(vcpu
->vcpu_id
);
7970 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7973 * PML buffer FULL happened while executing iret from NMI,
7974 * "blocked by NMI" bit has to be set before next VM entry.
7976 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7977 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7978 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7979 GUEST_INTR_STATE_NMI
);
7982 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7983 * here.., and there's no userspace involvement needed for PML.
7988 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7990 kvm_lapic_expired_hv_timer(vcpu
);
7994 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
7996 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7997 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
7999 /* Check for memory type validity */
8000 switch (address
& VMX_EPTP_MT_MASK
) {
8001 case VMX_EPTP_MT_UC
:
8002 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8005 case VMX_EPTP_MT_WB
:
8006 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8013 /* only 4 levels page-walk length are valid */
8014 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8017 /* Reserved bits should not be set */
8018 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8021 /* AD, if set, should be supported */
8022 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8023 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8030 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8031 struct vmcs12
*vmcs12
)
8033 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8035 bool accessed_dirty
;
8036 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8038 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8039 !nested_cpu_has_ept(vmcs12
))
8042 if (index
>= VMFUNC_EPTP_ENTRIES
)
8046 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8047 &address
, index
* 8, 8))
8050 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8053 * If the (L2) guest does a vmfunc to the currently
8054 * active ept pointer, we don't have to do anything else
8056 if (vmcs12
->ept_pointer
!= address
) {
8057 if (!valid_ept_address(vcpu
, address
))
8060 kvm_mmu_unload(vcpu
);
8061 mmu
->ept_ad
= accessed_dirty
;
8062 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8063 vmcs12
->ept_pointer
= address
;
8065 * TODO: Check what's the correct approach in case
8066 * mmu reload fails. Currently, we just let the next
8067 * reload potentially fail
8069 kvm_mmu_reload(vcpu
);
8075 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8077 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8078 struct vmcs12
*vmcs12
;
8079 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8082 * VMFUNC is only supported for nested guests, but we always enable the
8083 * secondary control for simplicity; for non-nested mode, fake that we
8084 * didn't by injecting #UD.
8086 if (!is_guest_mode(vcpu
)) {
8087 kvm_queue_exception(vcpu
, UD_VECTOR
);
8091 vmcs12
= get_vmcs12(vcpu
);
8092 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8097 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8103 return kvm_skip_emulated_instruction(vcpu
);
8106 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8107 vmcs_read32(VM_EXIT_INTR_INFO
),
8108 vmcs_readl(EXIT_QUALIFICATION
));
8113 * The exit handlers return 1 if the exit was handled fully and guest execution
8114 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8115 * to be done to userspace and return 0.
8117 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8118 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8119 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8120 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8121 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8122 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8123 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8124 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8125 [EXIT_REASON_CPUID
] = handle_cpuid
,
8126 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8127 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8128 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8129 [EXIT_REASON_HLT
] = handle_halt
,
8130 [EXIT_REASON_INVD
] = handle_invd
,
8131 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8132 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8133 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8134 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8135 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8136 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8137 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8138 [EXIT_REASON_VMREAD
] = handle_vmread
,
8139 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8140 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8141 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8142 [EXIT_REASON_VMON
] = handle_vmon
,
8143 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8144 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8145 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8146 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8147 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8148 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8149 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8150 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8151 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8152 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8153 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8154 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8155 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8156 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8157 [EXIT_REASON_INVEPT
] = handle_invept
,
8158 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8159 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8160 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8161 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8162 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8163 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8164 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8165 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8168 static const int kvm_vmx_max_exit_handlers
=
8169 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8171 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8172 struct vmcs12
*vmcs12
)
8174 unsigned long exit_qualification
;
8175 gpa_t bitmap
, last_bitmap
;
8180 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8181 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8183 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8185 port
= exit_qualification
>> 16;
8186 size
= (exit_qualification
& 7) + 1;
8188 last_bitmap
= (gpa_t
)-1;
8193 bitmap
= vmcs12
->io_bitmap_a
;
8194 else if (port
< 0x10000)
8195 bitmap
= vmcs12
->io_bitmap_b
;
8198 bitmap
+= (port
& 0x7fff) / 8;
8200 if (last_bitmap
!= bitmap
)
8201 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8203 if (b
& (1 << (port
& 7)))
8208 last_bitmap
= bitmap
;
8215 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8216 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8217 * disinterest in the current event (read or write a specific MSR) by using an
8218 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8220 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8221 struct vmcs12
*vmcs12
, u32 exit_reason
)
8223 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8226 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8230 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8231 * for the four combinations of read/write and low/high MSR numbers.
8232 * First we need to figure out which of the four to use:
8234 bitmap
= vmcs12
->msr_bitmap
;
8235 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8237 if (msr_index
>= 0xc0000000) {
8238 msr_index
-= 0xc0000000;
8242 /* Then read the msr_index'th bit from this bitmap: */
8243 if (msr_index
< 1024*8) {
8245 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8247 return 1 & (b
>> (msr_index
& 7));
8249 return true; /* let L1 handle the wrong parameter */
8253 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8254 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8255 * intercept (via guest_host_mask etc.) the current event.
8257 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8258 struct vmcs12
*vmcs12
)
8260 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8261 int cr
= exit_qualification
& 15;
8265 switch ((exit_qualification
>> 4) & 3) {
8266 case 0: /* mov to cr */
8267 reg
= (exit_qualification
>> 8) & 15;
8268 val
= kvm_register_readl(vcpu
, reg
);
8271 if (vmcs12
->cr0_guest_host_mask
&
8272 (val
^ vmcs12
->cr0_read_shadow
))
8276 if ((vmcs12
->cr3_target_count
>= 1 &&
8277 vmcs12
->cr3_target_value0
== val
) ||
8278 (vmcs12
->cr3_target_count
>= 2 &&
8279 vmcs12
->cr3_target_value1
== val
) ||
8280 (vmcs12
->cr3_target_count
>= 3 &&
8281 vmcs12
->cr3_target_value2
== val
) ||
8282 (vmcs12
->cr3_target_count
>= 4 &&
8283 vmcs12
->cr3_target_value3
== val
))
8285 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8289 if (vmcs12
->cr4_guest_host_mask
&
8290 (vmcs12
->cr4_read_shadow
^ val
))
8294 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8300 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8301 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8304 case 1: /* mov from cr */
8307 if (vmcs12
->cpu_based_vm_exec_control
&
8308 CPU_BASED_CR3_STORE_EXITING
)
8312 if (vmcs12
->cpu_based_vm_exec_control
&
8313 CPU_BASED_CR8_STORE_EXITING
)
8320 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8321 * cr0. Other attempted changes are ignored, with no exit.
8323 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8324 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8325 (val
^ vmcs12
->cr0_read_shadow
))
8327 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8328 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8337 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8338 * should handle it ourselves in L0 (and then continue L2). Only call this
8339 * when in is_guest_mode (L2).
8341 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8343 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8344 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8345 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8347 if (vmx
->nested
.nested_run_pending
)
8350 if (unlikely(vmx
->fail
)) {
8351 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8352 vmcs_read32(VM_INSTRUCTION_ERROR
));
8357 * The host physical addresses of some pages of guest memory
8358 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8359 * may write to these pages via their host physical address while
8360 * L2 is running, bypassing any address-translation-based dirty
8361 * tracking (e.g. EPT write protection).
8363 * Mark them dirty on every exit from L2 to prevent them from
8364 * getting out of sync with dirty tracking.
8366 nested_mark_vmcs12_pages_dirty(vcpu
);
8368 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8369 vmcs_readl(EXIT_QUALIFICATION
),
8370 vmx
->idt_vectoring_info
,
8372 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8375 switch (exit_reason
) {
8376 case EXIT_REASON_EXCEPTION_NMI
:
8377 if (is_nmi(intr_info
))
8379 else if (is_page_fault(intr_info
))
8380 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8381 else if (is_no_device(intr_info
) &&
8382 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8384 else if (is_debug(intr_info
) &&
8386 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8388 else if (is_breakpoint(intr_info
) &&
8389 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8391 return vmcs12
->exception_bitmap
&
8392 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8393 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8395 case EXIT_REASON_TRIPLE_FAULT
:
8397 case EXIT_REASON_PENDING_INTERRUPT
:
8398 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8399 case EXIT_REASON_NMI_WINDOW
:
8400 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8401 case EXIT_REASON_TASK_SWITCH
:
8403 case EXIT_REASON_CPUID
:
8405 case EXIT_REASON_HLT
:
8406 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8407 case EXIT_REASON_INVD
:
8409 case EXIT_REASON_INVLPG
:
8410 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8411 case EXIT_REASON_RDPMC
:
8412 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8413 case EXIT_REASON_RDRAND
:
8414 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8415 case EXIT_REASON_RDSEED
:
8416 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8417 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8418 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8419 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8420 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8421 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8422 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8423 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8424 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8426 * VMX instructions trap unconditionally. This allows L1 to
8427 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8430 case EXIT_REASON_CR_ACCESS
:
8431 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8432 case EXIT_REASON_DR_ACCESS
:
8433 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8434 case EXIT_REASON_IO_INSTRUCTION
:
8435 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8436 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8437 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8438 case EXIT_REASON_MSR_READ
:
8439 case EXIT_REASON_MSR_WRITE
:
8440 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8441 case EXIT_REASON_INVALID_STATE
:
8443 case EXIT_REASON_MWAIT_INSTRUCTION
:
8444 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8445 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8446 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8447 case EXIT_REASON_MONITOR_INSTRUCTION
:
8448 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8449 case EXIT_REASON_PAUSE_INSTRUCTION
:
8450 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8451 nested_cpu_has2(vmcs12
,
8452 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8453 case EXIT_REASON_MCE_DURING_VMENTRY
:
8455 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8456 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8457 case EXIT_REASON_APIC_ACCESS
:
8458 return nested_cpu_has2(vmcs12
,
8459 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8460 case EXIT_REASON_APIC_WRITE
:
8461 case EXIT_REASON_EOI_INDUCED
:
8462 /* apic_write and eoi_induced should exit unconditionally. */
8464 case EXIT_REASON_EPT_VIOLATION
:
8466 * L0 always deals with the EPT violation. If nested EPT is
8467 * used, and the nested mmu code discovers that the address is
8468 * missing in the guest EPT table (EPT12), the EPT violation
8469 * will be injected with nested_ept_inject_page_fault()
8472 case EXIT_REASON_EPT_MISCONFIG
:
8474 * L2 never uses directly L1's EPT, but rather L0's own EPT
8475 * table (shadow on EPT) or a merged EPT table that L0 built
8476 * (EPT on EPT). So any problems with the structure of the
8477 * table is L0's fault.
8480 case EXIT_REASON_INVPCID
:
8482 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8483 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8484 case EXIT_REASON_WBINVD
:
8485 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8486 case EXIT_REASON_XSETBV
:
8488 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8490 * This should never happen, since it is not possible to
8491 * set XSS to a non-zero value---neither in L1 nor in L2.
8492 * If if it were, XSS would have to be checked against
8493 * the XSS exit bitmap in vmcs12.
8495 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8496 case EXIT_REASON_PREEMPTION_TIMER
:
8498 case EXIT_REASON_PML_FULL
:
8499 /* We emulate PML support to L1. */
8501 case EXIT_REASON_VMFUNC
:
8502 /* VM functions are emulated through L2->L0 vmexits. */
8509 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8511 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8514 * At this point, the exit interruption info in exit_intr_info
8515 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8516 * we need to query the in-kernel LAPIC.
8518 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8519 if ((exit_intr_info
&
8520 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8521 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8522 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8523 vmcs12
->vm_exit_intr_error_code
=
8524 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8527 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8528 vmcs_readl(EXIT_QUALIFICATION
));
8532 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8534 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8535 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8538 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8541 __free_page(vmx
->pml_pg
);
8546 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8552 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8554 /* Do nothing if PML buffer is empty */
8555 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8558 /* PML index always points to next available PML buffer entity */
8559 if (pml_idx
>= PML_ENTITY_NUM
)
8564 pml_buf
= page_address(vmx
->pml_pg
);
8565 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8568 gpa
= pml_buf
[pml_idx
];
8569 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8570 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8573 /* reset PML index */
8574 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8578 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8579 * Called before reporting dirty_bitmap to userspace.
8581 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8584 struct kvm_vcpu
*vcpu
;
8586 * We only need to kick vcpu out of guest mode here, as PML buffer
8587 * is flushed at beginning of all VMEXITs, and it's obvious that only
8588 * vcpus running in guest are possible to have unflushed GPAs in PML
8591 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8592 kvm_vcpu_kick(vcpu
);
8595 static void vmx_dump_sel(char *name
, uint32_t sel
)
8597 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8598 name
, vmcs_read16(sel
),
8599 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8600 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8601 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8604 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8606 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8607 name
, vmcs_read32(limit
),
8608 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8611 static void dump_vmcs(void)
8613 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8614 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8615 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8616 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8617 u32 secondary_exec_control
= 0;
8618 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8619 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8622 if (cpu_has_secondary_exec_ctrls())
8623 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8625 pr_err("*** Guest State ***\n");
8626 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8627 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8628 vmcs_readl(CR0_GUEST_HOST_MASK
));
8629 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8630 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8631 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8632 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8633 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8635 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8636 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8637 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8638 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8640 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8641 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8642 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8643 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8644 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8645 vmcs_readl(GUEST_SYSENTER_ESP
),
8646 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8647 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8648 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8649 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8650 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8651 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8652 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8653 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8654 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8655 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8656 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8657 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8658 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8659 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8660 efer
, vmcs_read64(GUEST_IA32_PAT
));
8661 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8662 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8663 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8664 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8665 pr_err("PerfGlobCtl = 0x%016llx\n",
8666 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8667 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8668 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8669 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8670 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8671 vmcs_read32(GUEST_ACTIVITY_STATE
));
8672 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8673 pr_err("InterruptStatus = %04x\n",
8674 vmcs_read16(GUEST_INTR_STATUS
));
8676 pr_err("*** Host State ***\n");
8677 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8678 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8679 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8680 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8681 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8682 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8683 vmcs_read16(HOST_TR_SELECTOR
));
8684 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8685 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8686 vmcs_readl(HOST_TR_BASE
));
8687 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8688 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8689 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8690 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8691 vmcs_readl(HOST_CR4
));
8692 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8693 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8694 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8695 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8696 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8697 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8698 vmcs_read64(HOST_IA32_EFER
),
8699 vmcs_read64(HOST_IA32_PAT
));
8700 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8701 pr_err("PerfGlobCtl = 0x%016llx\n",
8702 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8704 pr_err("*** Control State ***\n");
8705 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8706 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8707 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8708 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8709 vmcs_read32(EXCEPTION_BITMAP
),
8710 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8711 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8712 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8713 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8714 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8715 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8716 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8717 vmcs_read32(VM_EXIT_INTR_INFO
),
8718 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8719 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8720 pr_err(" reason=%08x qualification=%016lx\n",
8721 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8722 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8723 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8724 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8725 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8726 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8727 pr_err("TSC Multiplier = 0x%016llx\n",
8728 vmcs_read64(TSC_MULTIPLIER
));
8729 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8730 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8731 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8732 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8733 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8734 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8735 n
= vmcs_read32(CR3_TARGET_COUNT
);
8736 for (i
= 0; i
+ 1 < n
; i
+= 4)
8737 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8738 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8739 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8741 pr_err("CR3 target%u=%016lx\n",
8742 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8743 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8744 pr_err("PLE Gap=%08x Window=%08x\n",
8745 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8746 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8747 pr_err("Virtual processor ID = 0x%04x\n",
8748 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8752 * The guest has exited. See if we can fix it or if we need userspace
8755 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8757 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8758 u32 exit_reason
= vmx
->exit_reason
;
8759 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8761 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8764 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8765 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8766 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8767 * mode as if vcpus is in root mode, the PML buffer must has been
8771 vmx_flush_pml_buffer(vcpu
);
8773 /* If guest state is invalid, start emulating */
8774 if (vmx
->emulation_required
)
8775 return handle_invalid_guest_state(vcpu
);
8777 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8778 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8780 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8782 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8783 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8788 if (unlikely(vmx
->fail
)) {
8789 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8790 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8791 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8797 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8798 * delivery event since it indicates guest is accessing MMIO.
8799 * The vm-exit can be triggered again after return to guest that
8800 * will cause infinite loop.
8802 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8803 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8804 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8805 exit_reason
!= EXIT_REASON_PML_FULL
&&
8806 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8807 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8808 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8809 vcpu
->run
->internal
.ndata
= 3;
8810 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8811 vcpu
->run
->internal
.data
[1] = exit_reason
;
8812 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8813 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8814 vcpu
->run
->internal
.ndata
++;
8815 vcpu
->run
->internal
.data
[3] =
8816 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8821 if (exit_reason
< kvm_vmx_max_exit_handlers
8822 && kvm_vmx_exit_handlers
[exit_reason
])
8823 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8825 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8827 kvm_queue_exception(vcpu
, UD_VECTOR
);
8832 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8834 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8836 if (is_guest_mode(vcpu
) &&
8837 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8840 if (irr
== -1 || tpr
< irr
) {
8841 vmcs_write32(TPR_THRESHOLD
, 0);
8845 vmcs_write32(TPR_THRESHOLD
, irr
);
8848 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8850 u32 sec_exec_control
;
8852 /* Postpone execution until vmcs01 is the current VMCS. */
8853 if (is_guest_mode(vcpu
)) {
8854 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8858 if (!cpu_has_vmx_virtualize_x2apic_mode())
8861 if (!cpu_need_tpr_shadow(vcpu
))
8864 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8867 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8868 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8870 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8871 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8872 vmx_flush_tlb_ept_only(vcpu
);
8874 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8876 vmx_set_msr_bitmap(vcpu
);
8879 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8881 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8884 * Currently we do not handle the nested case where L2 has an
8885 * APIC access page of its own; that page is still pinned.
8886 * Hence, we skip the case where the VCPU is in guest mode _and_
8887 * L1 prepared an APIC access page for L2.
8889 * For the case where L1 and L2 share the same APIC access page
8890 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8891 * in the vmcs12), this function will only update either the vmcs01
8892 * or the vmcs02. If the former, the vmcs02 will be updated by
8893 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8894 * the next L2->L1 exit.
8896 if (!is_guest_mode(vcpu
) ||
8897 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8898 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8899 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8900 vmx_flush_tlb_ept_only(vcpu
);
8904 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8912 status
= vmcs_read16(GUEST_INTR_STATUS
);
8914 if (max_isr
!= old
) {
8916 status
|= max_isr
<< 8;
8917 vmcs_write16(GUEST_INTR_STATUS
, status
);
8921 static void vmx_set_rvi(int vector
)
8929 status
= vmcs_read16(GUEST_INTR_STATUS
);
8930 old
= (u8
)status
& 0xff;
8931 if ((u8
)vector
!= old
) {
8933 status
|= (u8
)vector
;
8934 vmcs_write16(GUEST_INTR_STATUS
, status
);
8938 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8940 if (!is_guest_mode(vcpu
)) {
8941 vmx_set_rvi(max_irr
);
8949 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8952 if (nested_exit_on_intr(vcpu
))
8956 * Else, fall back to pre-APICv interrupt injection since L2
8957 * is run without virtual interrupt delivery.
8959 if (!kvm_event_needs_reinjection(vcpu
) &&
8960 vmx_interrupt_allowed(vcpu
)) {
8961 kvm_queue_interrupt(vcpu
, max_irr
, false);
8962 vmx_inject_irq(vcpu
);
8966 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8968 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8971 WARN_ON(!vcpu
->arch
.apicv_active
);
8972 if (pi_test_on(&vmx
->pi_desc
)) {
8973 pi_clear_on(&vmx
->pi_desc
);
8975 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8976 * But on x86 this is just a compiler barrier anyway.
8978 smp_mb__after_atomic();
8979 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8981 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8983 vmx_hwapic_irr_update(vcpu
, max_irr
);
8987 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8989 if (!kvm_vcpu_apicv_active(vcpu
))
8992 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8993 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8994 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8995 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8998 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9000 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9002 pi_clear_on(&vmx
->pi_desc
);
9003 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9006 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9008 u32 exit_intr_info
= 0;
9009 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9011 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9012 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9015 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9016 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9017 vmx
->exit_intr_info
= exit_intr_info
;
9019 /* if exit due to PF check for async PF */
9020 if (is_page_fault(exit_intr_info
))
9021 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9023 /* Handle machine checks before interrupts are enabled */
9024 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9025 is_machine_check(exit_intr_info
))
9026 kvm_machine_check();
9028 /* We need to handle NMIs before interrupts are enabled */
9029 if (is_nmi(exit_intr_info
)) {
9030 kvm_before_handle_nmi(&vmx
->vcpu
);
9032 kvm_after_handle_nmi(&vmx
->vcpu
);
9036 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9038 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9039 register void *__sp
asm(_ASM_SP
);
9041 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9042 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9043 unsigned int vector
;
9044 unsigned long entry
;
9046 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9047 #ifdef CONFIG_X86_64
9051 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9052 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9053 entry
= gate_offset(desc
);
9055 #ifdef CONFIG_X86_64
9056 "mov %%" _ASM_SP
", %[sp]\n\t"
9057 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9062 __ASM_SIZE(push
) " $%c[cs]\n\t"
9063 "call *%[entry]\n\t"
9065 #ifdef CONFIG_X86_64
9071 [ss
]"i"(__KERNEL_DS
),
9072 [cs
]"i"(__KERNEL_CS
)
9076 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9078 static bool vmx_has_high_real_mode_segbase(void)
9080 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9083 static bool vmx_mpx_supported(void)
9085 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9086 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9089 static bool vmx_xsaves_supported(void)
9091 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9092 SECONDARY_EXEC_XSAVES
;
9095 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9100 bool idtv_info_valid
;
9102 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9104 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9107 * Can't use vmx->exit_intr_info since we're not sure what
9108 * the exit reason is.
9110 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9111 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9112 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9114 * SDM 3: 27.7.1.2 (September 2008)
9115 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9116 * a guest IRET fault.
9117 * SDM 3: 23.2.2 (September 2008)
9118 * Bit 12 is undefined in any of the following cases:
9119 * If the VM exit sets the valid bit in the IDT-vectoring
9120 * information field.
9121 * If the VM exit is due to a double fault.
9123 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9124 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9125 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9126 GUEST_INTR_STATE_NMI
);
9128 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9129 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9130 & GUEST_INTR_STATE_NMI
);
9133 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9134 u32 idt_vectoring_info
,
9135 int instr_len_field
,
9136 int error_code_field
)
9140 bool idtv_info_valid
;
9142 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9144 vcpu
->arch
.nmi_injected
= false;
9145 kvm_clear_exception_queue(vcpu
);
9146 kvm_clear_interrupt_queue(vcpu
);
9148 if (!idtv_info_valid
)
9151 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9153 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9154 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9157 case INTR_TYPE_NMI_INTR
:
9158 vcpu
->arch
.nmi_injected
= true;
9160 * SDM 3: 27.7.1.2 (September 2008)
9161 * Clear bit "block by NMI" before VM entry if a NMI
9164 vmx_set_nmi_mask(vcpu
, false);
9166 case INTR_TYPE_SOFT_EXCEPTION
:
9167 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9169 case INTR_TYPE_HARD_EXCEPTION
:
9170 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9171 u32 err
= vmcs_read32(error_code_field
);
9172 kvm_requeue_exception_e(vcpu
, vector
, err
);
9174 kvm_requeue_exception(vcpu
, vector
);
9176 case INTR_TYPE_SOFT_INTR
:
9177 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9179 case INTR_TYPE_EXT_INTR
:
9180 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9187 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9189 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9190 VM_EXIT_INSTRUCTION_LEN
,
9191 IDT_VECTORING_ERROR_CODE
);
9194 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9196 __vmx_complete_interrupts(vcpu
,
9197 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9198 VM_ENTRY_INSTRUCTION_LEN
,
9199 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9201 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9204 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9207 struct perf_guest_switch_msr
*msrs
;
9209 msrs
= perf_guest_get_msrs(&nr_msrs
);
9214 for (i
= 0; i
< nr_msrs
; i
++)
9215 if (msrs
[i
].host
== msrs
[i
].guest
)
9216 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9218 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9222 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9224 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9228 if (vmx
->hv_deadline_tsc
== -1)
9232 if (vmx
->hv_deadline_tsc
> tscl
)
9233 /* sure to be 32 bit only because checked on set_hv_timer */
9234 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9235 cpu_preemption_timer_multi
);
9239 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9242 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9245 unsigned long debugctlmsr
, cr3
, cr4
;
9247 /* Don't enter VMX if guest state is invalid, let the exit handler
9248 start emulation until we arrive back to a valid state */
9249 if (vmx
->emulation_required
)
9252 if (vmx
->ple_window_dirty
) {
9253 vmx
->ple_window_dirty
= false;
9254 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9257 if (vmx
->nested
.sync_shadow_vmcs
) {
9258 copy_vmcs12_to_shadow(vmx
);
9259 vmx
->nested
.sync_shadow_vmcs
= false;
9262 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9263 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9264 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9265 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9267 cr3
= __get_current_cr3_fast();
9268 if (unlikely(cr3
!= vmx
->host_state
.vmcs_host_cr3
)) {
9269 vmcs_writel(HOST_CR3
, cr3
);
9270 vmx
->host_state
.vmcs_host_cr3
= cr3
;
9273 cr4
= cr4_read_shadow();
9274 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
9275 vmcs_writel(HOST_CR4
, cr4
);
9276 vmx
->host_state
.vmcs_host_cr4
= cr4
;
9279 /* When single-stepping over STI and MOV SS, we must clear the
9280 * corresponding interruptibility bits in the guest state. Otherwise
9281 * vmentry fails as it then expects bit 14 (BS) in pending debug
9282 * exceptions being set, but that's not correct for the guest debugging
9284 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9285 vmx_set_interrupt_shadow(vcpu
, 0);
9287 if (static_cpu_has(X86_FEATURE_PKU
) &&
9288 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9289 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9290 __write_pkru(vcpu
->arch
.pkru
);
9292 atomic_switch_perf_msrs(vmx
);
9293 debugctlmsr
= get_debugctlmsr();
9295 vmx_arm_hv_timer(vcpu
);
9297 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9299 /* Store host registers */
9300 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9301 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9302 "push %%" _ASM_CX
" \n\t"
9303 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9305 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9306 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9308 /* Reload cr2 if changed */
9309 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9310 "mov %%cr2, %%" _ASM_DX
" \n\t"
9311 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9313 "mov %%" _ASM_AX
", %%cr2 \n\t"
9315 /* Check if vmlaunch of vmresume is needed */
9316 "cmpl $0, %c[launched](%0) \n\t"
9317 /* Load guest registers. Don't clobber flags. */
9318 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9319 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9320 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9321 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9322 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9323 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9324 #ifdef CONFIG_X86_64
9325 "mov %c[r8](%0), %%r8 \n\t"
9326 "mov %c[r9](%0), %%r9 \n\t"
9327 "mov %c[r10](%0), %%r10 \n\t"
9328 "mov %c[r11](%0), %%r11 \n\t"
9329 "mov %c[r12](%0), %%r12 \n\t"
9330 "mov %c[r13](%0), %%r13 \n\t"
9331 "mov %c[r14](%0), %%r14 \n\t"
9332 "mov %c[r15](%0), %%r15 \n\t"
9334 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9336 /* Enter guest mode */
9338 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9340 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9342 /* Save guest registers, load host registers, keep flags */
9343 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9345 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9346 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9347 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9348 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9349 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9350 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9351 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9352 #ifdef CONFIG_X86_64
9353 "mov %%r8, %c[r8](%0) \n\t"
9354 "mov %%r9, %c[r9](%0) \n\t"
9355 "mov %%r10, %c[r10](%0) \n\t"
9356 "mov %%r11, %c[r11](%0) \n\t"
9357 "mov %%r12, %c[r12](%0) \n\t"
9358 "mov %%r13, %c[r13](%0) \n\t"
9359 "mov %%r14, %c[r14](%0) \n\t"
9360 "mov %%r15, %c[r15](%0) \n\t"
9362 "mov %%cr2, %%" _ASM_AX
" \n\t"
9363 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9365 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9366 "setbe %c[fail](%0) \n\t"
9367 ".pushsection .rodata \n\t"
9368 ".global vmx_return \n\t"
9369 "vmx_return: " _ASM_PTR
" 2b \n\t"
9371 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9372 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9373 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9374 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9375 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9376 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9377 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9378 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9379 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9380 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9381 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9382 #ifdef CONFIG_X86_64
9383 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9384 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9385 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9386 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9387 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9388 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9389 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9390 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9392 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9393 [wordsize
]"i"(sizeof(ulong
))
9395 #ifdef CONFIG_X86_64
9396 , "rax", "rbx", "rdi", "rsi"
9397 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9399 , "eax", "ebx", "edi", "esi"
9403 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9405 update_debugctlmsr(debugctlmsr
);
9407 #ifndef CONFIG_X86_64
9409 * The sysexit path does not restore ds/es, so we must set them to
9410 * a reasonable value ourselves.
9412 * We can't defer this to vmx_load_host_state() since that function
9413 * may be executed in interrupt context, which saves and restore segments
9414 * around it, nullifying its effect.
9416 loadsegment(ds
, __USER_DS
);
9417 loadsegment(es
, __USER_DS
);
9420 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9421 | (1 << VCPU_EXREG_RFLAGS
)
9422 | (1 << VCPU_EXREG_PDPTR
)
9423 | (1 << VCPU_EXREG_SEGMENTS
)
9424 | (1 << VCPU_EXREG_CR3
));
9425 vcpu
->arch
.regs_dirty
= 0;
9428 * eager fpu is enabled if PKEY is supported and CR4 is switched
9429 * back on host, so it is safe to read guest PKRU from current
9432 if (static_cpu_has(X86_FEATURE_PKU
) &&
9433 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9434 vcpu
->arch
.pkru
= __read_pkru();
9435 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9436 __write_pkru(vmx
->host_pkru
);
9440 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9441 * we did not inject a still-pending event to L1 now because of
9442 * nested_run_pending, we need to re-enable this bit.
9444 if (vmx
->nested
.nested_run_pending
)
9445 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9447 vmx
->nested
.nested_run_pending
= 0;
9448 vmx
->idt_vectoring_info
= 0;
9450 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9451 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9454 vmx
->loaded_vmcs
->launched
= 1;
9455 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9457 vmx_complete_atomic_exit(vmx
);
9458 vmx_recover_nmi_blocking(vmx
);
9459 vmx_complete_interrupts(vmx
);
9461 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9463 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9465 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9468 if (vmx
->loaded_vmcs
== vmcs
)
9472 vmx
->loaded_vmcs
= vmcs
;
9474 vmx_vcpu_load(vcpu
, cpu
);
9480 * Ensure that the current vmcs of the logical processor is the
9481 * vmcs01 of the vcpu before calling free_nested().
9483 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9485 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9488 r
= vcpu_load(vcpu
);
9490 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9495 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9497 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9500 vmx_destroy_pml_buffer(vmx
);
9501 free_vpid(vmx
->vpid
);
9502 leave_guest_mode(vcpu
);
9503 vmx_free_vcpu_nested(vcpu
);
9504 free_loaded_vmcs(vmx
->loaded_vmcs
);
9505 kfree(vmx
->guest_msrs
);
9506 kvm_vcpu_uninit(vcpu
);
9507 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9510 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9513 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9517 return ERR_PTR(-ENOMEM
);
9519 vmx
->vpid
= allocate_vpid();
9521 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9528 * If PML is turned on, failure on enabling PML just results in failure
9529 * of creating the vcpu, therefore we can simplify PML logic (by
9530 * avoiding dealing with cases, such as enabling PML partially on vcpus
9531 * for the guest, etc.
9534 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9539 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9540 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9543 if (!vmx
->guest_msrs
)
9546 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9547 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9548 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9549 if (!vmx
->loaded_vmcs
->vmcs
)
9551 loaded_vmcs_init(vmx
->loaded_vmcs
);
9554 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9555 vmx
->vcpu
.cpu
= cpu
;
9556 err
= vmx_vcpu_setup(vmx
);
9557 vmx_vcpu_put(&vmx
->vcpu
);
9561 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9562 err
= alloc_apic_access_page(kvm
);
9568 if (!kvm
->arch
.ept_identity_map_addr
)
9569 kvm
->arch
.ept_identity_map_addr
=
9570 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9571 err
= init_rmode_identity_map(kvm
);
9577 nested_vmx_setup_ctls_msrs(vmx
);
9578 vmx
->nested
.vpid02
= allocate_vpid();
9581 vmx
->nested
.posted_intr_nv
= -1;
9582 vmx
->nested
.current_vmptr
= -1ull;
9584 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9589 free_vpid(vmx
->nested
.vpid02
);
9590 free_loaded_vmcs(vmx
->loaded_vmcs
);
9592 kfree(vmx
->guest_msrs
);
9594 vmx_destroy_pml_buffer(vmx
);
9596 kvm_vcpu_uninit(&vmx
->vcpu
);
9598 free_vpid(vmx
->vpid
);
9599 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9600 return ERR_PTR(err
);
9603 static void __init
vmx_check_processor_compat(void *rtn
)
9605 struct vmcs_config vmcs_conf
;
9608 if (setup_vmcs_config(&vmcs_conf
) < 0)
9610 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9611 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9612 smp_processor_id());
9617 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9622 /* For VT-d and EPT combination
9623 * 1. MMIO: always map as UC
9625 * a. VT-d without snooping control feature: can't guarantee the
9626 * result, try to trust guest.
9627 * b. VT-d with snooping control feature: snooping control feature of
9628 * VT-d engine can guarantee the cache correctness. Just set it
9629 * to WB to keep consistent with host. So the same as item 3.
9630 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9631 * consistent with host MTRR
9634 cache
= MTRR_TYPE_UNCACHABLE
;
9638 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9639 ipat
= VMX_EPT_IPAT_BIT
;
9640 cache
= MTRR_TYPE_WRBACK
;
9644 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9645 ipat
= VMX_EPT_IPAT_BIT
;
9646 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9647 cache
= MTRR_TYPE_WRBACK
;
9649 cache
= MTRR_TYPE_UNCACHABLE
;
9653 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9656 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9659 static int vmx_get_lpage_level(void)
9661 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9662 return PT_DIRECTORY_LEVEL
;
9664 /* For shadow and EPT supported 1GB page */
9665 return PT_PDPE_LEVEL
;
9668 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9671 * These bits in the secondary execution controls field
9672 * are dynamic, the others are mostly based on the hypervisor
9673 * architecture and the guest's CPUID. Do not touch the
9677 SECONDARY_EXEC_SHADOW_VMCS
|
9678 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9679 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9681 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9683 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9684 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9688 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9689 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9691 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9693 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9694 struct kvm_cpuid_entry2
*entry
;
9696 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9697 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9699 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9700 if (entry && (entry->_reg & (_cpuid_mask))) \
9701 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9704 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9705 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9706 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9707 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9708 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9709 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9710 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9711 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9712 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9713 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9714 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9715 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9716 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9717 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9718 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9720 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9721 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9722 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9723 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9724 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9725 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9726 cr4_fixed1_update(bit(11), ecx
, bit(2));
9728 #undef cr4_fixed1_update
9731 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9735 if (cpu_has_secondary_exec_ctrls()) {
9736 vmx_compute_secondary_exec_control(vmx
);
9737 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9740 if (nested_vmx_allowed(vcpu
))
9741 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9742 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9744 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9745 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9747 if (nested_vmx_allowed(vcpu
))
9748 nested_vmx_cr_fixed1_bits_update(vcpu
);
9751 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9753 if (func
== 1 && nested
)
9754 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9757 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9758 struct x86_exception
*fault
)
9760 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9761 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9763 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9765 if (vmx
->nested
.pml_full
) {
9766 exit_reason
= EXIT_REASON_PML_FULL
;
9767 vmx
->nested
.pml_full
= false;
9768 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9769 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9770 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9772 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9774 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9775 vmcs12
->guest_physical_address
= fault
->address
;
9778 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9780 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9783 /* Callbacks for nested_ept_init_mmu_context: */
9785 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9787 /* return the page table to be shadowed - in our case, EPT12 */
9788 return get_vmcs12(vcpu
)->ept_pointer
;
9791 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9793 WARN_ON(mmu_is_nested(vcpu
));
9794 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9797 kvm_mmu_unload(vcpu
);
9798 kvm_init_shadow_ept_mmu(vcpu
,
9799 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9800 VMX_EPT_EXECUTE_ONLY_BIT
,
9801 nested_ept_ad_enabled(vcpu
));
9802 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9803 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9804 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9806 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9810 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9812 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9815 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9818 bool inequality
, bit
;
9820 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9822 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9823 vmcs12
->page_fault_error_code_match
;
9824 return inequality
^ bit
;
9827 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9828 struct x86_exception
*fault
)
9830 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9832 WARN_ON(!is_guest_mode(vcpu
));
9834 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9835 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9836 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9837 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9838 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9841 kvm_inject_page_fault(vcpu
, fault
);
9845 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9846 struct vmcs12
*vmcs12
);
9848 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9849 struct vmcs12
*vmcs12
)
9851 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9855 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9857 * Translate L1 physical address to host physical
9858 * address for vmcs02. Keep the page pinned, so this
9859 * physical address remains valid. We keep a reference
9860 * to it so we can release it later.
9862 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9863 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9864 vmx
->nested
.apic_access_page
= NULL
;
9866 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9868 * If translation failed, no matter: This feature asks
9869 * to exit when accessing the given address, and if it
9870 * can never be accessed, this feature won't do
9873 if (!is_error_page(page
)) {
9874 vmx
->nested
.apic_access_page
= page
;
9875 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9876 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9878 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9879 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9881 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9882 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9883 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9884 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9885 kvm_vcpu_reload_apic_access_page(vcpu
);
9888 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9889 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9890 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9891 vmx
->nested
.virtual_apic_page
= NULL
;
9893 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9896 * If translation failed, VM entry will fail because
9897 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9898 * Failing the vm entry is _not_ what the processor
9899 * does but it's basically the only possibility we
9900 * have. We could still enter the guest if CR8 load
9901 * exits are enabled, CR8 store exits are enabled, and
9902 * virtualize APIC access is disabled; in this case
9903 * the processor would never use the TPR shadow and we
9904 * could simply clear the bit from the execution
9905 * control. But such a configuration is useless, so
9906 * let's keep the code simple.
9908 if (!is_error_page(page
)) {
9909 vmx
->nested
.virtual_apic_page
= page
;
9910 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9911 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9915 if (nested_cpu_has_posted_intr(vmcs12
)) {
9916 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9917 kunmap(vmx
->nested
.pi_desc_page
);
9918 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9919 vmx
->nested
.pi_desc_page
= NULL
;
9921 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9922 if (is_error_page(page
))
9924 vmx
->nested
.pi_desc_page
= page
;
9925 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9926 vmx
->nested
.pi_desc
=
9927 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9928 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9930 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9931 page_to_phys(vmx
->nested
.pi_desc_page
) +
9932 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9935 if (cpu_has_vmx_msr_bitmap() &&
9936 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9937 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9940 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9941 CPU_BASED_USE_MSR_BITMAPS
);
9944 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9946 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9949 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9952 /* Make sure short timeouts reliably trigger an immediate vmexit.
9953 * hrtimer_start does not guarantee this. */
9954 if (preemption_timeout
<= 1) {
9955 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9959 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9960 preemption_timeout
*= 1000000;
9961 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9962 hrtimer_start(&vmx
->nested
.preemption_timer
,
9963 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9966 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9967 struct vmcs12
*vmcs12
)
9969 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9972 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9973 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9979 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9980 struct vmcs12
*vmcs12
)
9982 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9985 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9991 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
9992 struct vmcs12
*vmcs12
)
9994 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9997 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10004 * Merge L0's and L1's MSR bitmap, return false to indicate that
10005 * we do not use the hardware.
10007 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10008 struct vmcs12
*vmcs12
)
10012 unsigned long *msr_bitmap_l1
;
10013 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10015 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10016 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10019 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10020 if (is_error_page(page
))
10022 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10024 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10026 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10027 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10028 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10029 nested_vmx_disable_intercept_for_msr(
10030 msr_bitmap_l1
, msr_bitmap_l0
,
10033 nested_vmx_disable_intercept_for_msr(
10034 msr_bitmap_l1
, msr_bitmap_l0
,
10035 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10036 MSR_TYPE_R
| MSR_TYPE_W
);
10038 if (nested_cpu_has_vid(vmcs12
)) {
10039 nested_vmx_disable_intercept_for_msr(
10040 msr_bitmap_l1
, msr_bitmap_l0
,
10041 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10043 nested_vmx_disable_intercept_for_msr(
10044 msr_bitmap_l1
, msr_bitmap_l0
,
10045 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10050 kvm_release_page_clean(page
);
10055 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10056 struct vmcs12
*vmcs12
)
10058 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10059 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10060 !nested_cpu_has_vid(vmcs12
) &&
10061 !nested_cpu_has_posted_intr(vmcs12
))
10065 * If virtualize x2apic mode is enabled,
10066 * virtualize apic access must be disabled.
10068 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10069 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10073 * If virtual interrupt delivery is enabled,
10074 * we must exit on external interrupts.
10076 if (nested_cpu_has_vid(vmcs12
) &&
10077 !nested_exit_on_intr(vcpu
))
10081 * bits 15:8 should be zero in posted_intr_nv,
10082 * the descriptor address has been already checked
10083 * in nested_get_vmcs12_pages.
10085 if (nested_cpu_has_posted_intr(vmcs12
) &&
10086 (!nested_cpu_has_vid(vmcs12
) ||
10087 !nested_exit_intr_ack_set(vcpu
) ||
10088 vmcs12
->posted_intr_nv
& 0xff00))
10091 /* tpr shadow is needed by all apicv features. */
10092 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10098 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10099 unsigned long count_field
,
10100 unsigned long addr_field
)
10105 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10106 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10112 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10113 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10114 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10115 pr_debug_ratelimited(
10116 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10117 addr_field
, maxphyaddr
, count
, addr
);
10123 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10124 struct vmcs12
*vmcs12
)
10126 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10127 vmcs12
->vm_exit_msr_store_count
== 0 &&
10128 vmcs12
->vm_entry_msr_load_count
== 0)
10129 return 0; /* Fast path */
10130 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10131 VM_EXIT_MSR_LOAD_ADDR
) ||
10132 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10133 VM_EXIT_MSR_STORE_ADDR
) ||
10134 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10135 VM_ENTRY_MSR_LOAD_ADDR
))
10140 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10141 struct vmcs12
*vmcs12
)
10143 u64 address
= vmcs12
->pml_address
;
10144 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10146 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10147 if (!nested_cpu_has_ept(vmcs12
) ||
10148 !IS_ALIGNED(address
, 4096) ||
10149 address
>> maxphyaddr
)
10156 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10157 struct vmx_msr_entry
*e
)
10159 /* x2APIC MSR accesses are not allowed */
10160 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10162 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10163 e
->index
== MSR_IA32_UCODE_REV
)
10165 if (e
->reserved
!= 0)
10170 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10171 struct vmx_msr_entry
*e
)
10173 if (e
->index
== MSR_FS_BASE
||
10174 e
->index
== MSR_GS_BASE
||
10175 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10176 nested_vmx_msr_check_common(vcpu
, e
))
10181 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10182 struct vmx_msr_entry
*e
)
10184 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10185 nested_vmx_msr_check_common(vcpu
, e
))
10191 * Load guest's/host's msr at nested entry/exit.
10192 * return 0 for success, entry index for failure.
10194 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10197 struct vmx_msr_entry e
;
10198 struct msr_data msr
;
10200 msr
.host_initiated
= false;
10201 for (i
= 0; i
< count
; i
++) {
10202 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10204 pr_debug_ratelimited(
10205 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10206 __func__
, i
, gpa
+ i
* sizeof(e
));
10209 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10210 pr_debug_ratelimited(
10211 "%s check failed (%u, 0x%x, 0x%x)\n",
10212 __func__
, i
, e
.index
, e
.reserved
);
10215 msr
.index
= e
.index
;
10216 msr
.data
= e
.value
;
10217 if (kvm_set_msr(vcpu
, &msr
)) {
10218 pr_debug_ratelimited(
10219 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10220 __func__
, i
, e
.index
, e
.value
);
10229 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10232 struct vmx_msr_entry e
;
10234 for (i
= 0; i
< count
; i
++) {
10235 struct msr_data msr_info
;
10236 if (kvm_vcpu_read_guest(vcpu
,
10237 gpa
+ i
* sizeof(e
),
10238 &e
, 2 * sizeof(u32
))) {
10239 pr_debug_ratelimited(
10240 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10241 __func__
, i
, gpa
+ i
* sizeof(e
));
10244 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10245 pr_debug_ratelimited(
10246 "%s check failed (%u, 0x%x, 0x%x)\n",
10247 __func__
, i
, e
.index
, e
.reserved
);
10250 msr_info
.host_initiated
= false;
10251 msr_info
.index
= e
.index
;
10252 if (kvm_get_msr(vcpu
, &msr_info
)) {
10253 pr_debug_ratelimited(
10254 "%s cannot read MSR (%u, 0x%x)\n",
10255 __func__
, i
, e
.index
);
10258 if (kvm_vcpu_write_guest(vcpu
,
10259 gpa
+ i
* sizeof(e
) +
10260 offsetof(struct vmx_msr_entry
, value
),
10261 &msr_info
.data
, sizeof(msr_info
.data
))) {
10262 pr_debug_ratelimited(
10263 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10264 __func__
, i
, e
.index
, msr_info
.data
);
10271 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10273 unsigned long invalid_mask
;
10275 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10276 return (val
& invalid_mask
) == 0;
10280 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10281 * emulating VM entry into a guest with EPT enabled.
10282 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10283 * is assigned to entry_failure_code on failure.
10285 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10286 u32
*entry_failure_code
)
10288 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10289 if (!nested_cr3_valid(vcpu
, cr3
)) {
10290 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10295 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10296 * must not be dereferenced.
10298 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10300 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10301 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10306 vcpu
->arch
.cr3
= cr3
;
10307 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10310 kvm_mmu_reset_context(vcpu
);
10315 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10316 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10317 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10318 * guest in a way that will both be appropriate to L1's requests, and our
10319 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10320 * function also has additional necessary side-effects, like setting various
10321 * vcpu->arch fields.
10322 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10323 * is assigned to entry_failure_code on failure.
10325 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10326 bool from_vmentry
, u32
*entry_failure_code
)
10328 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10329 u32 exec_control
, vmcs12_exec_ctrl
;
10331 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10332 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10333 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10334 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10335 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10336 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10337 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10338 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10339 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10340 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10341 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10342 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10343 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10344 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10345 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10346 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10347 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10348 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10349 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10350 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10351 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10352 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10353 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10354 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10355 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10356 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10357 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10358 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10359 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10360 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10361 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10362 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10363 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10364 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10365 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10366 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10368 if (from_vmentry
&&
10369 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10370 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10371 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10373 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10374 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10376 if (from_vmentry
) {
10377 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10378 vmcs12
->vm_entry_intr_info_field
);
10379 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10380 vmcs12
->vm_entry_exception_error_code
);
10381 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10382 vmcs12
->vm_entry_instruction_len
);
10383 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10384 vmcs12
->guest_interruptibility_info
);
10385 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10386 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10388 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10390 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10391 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10392 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10393 vmcs12
->guest_pending_dbg_exceptions
);
10394 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10395 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10397 if (nested_cpu_has_xsaves(vmcs12
))
10398 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10399 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10401 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10403 /* Preemption timer setting is only taken from vmcs01. */
10404 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10405 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10406 if (vmx
->hv_deadline_tsc
== -1)
10407 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10409 /* Posted interrupts setting is only taken from vmcs12. */
10410 if (nested_cpu_has_posted_intr(vmcs12
)) {
10411 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10412 vmx
->nested
.pi_pending
= false;
10413 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10415 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10418 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10420 vmx
->nested
.preemption_timer_expired
= false;
10421 if (nested_cpu_has_preemption_timer(vmcs12
))
10422 vmx_start_preemption_timer(vcpu
);
10425 * Whether page-faults are trapped is determined by a combination of
10426 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10427 * If enable_ept, L0 doesn't care about page faults and we should
10428 * set all of these to L1's desires. However, if !enable_ept, L0 does
10429 * care about (at least some) page faults, and because it is not easy
10430 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10431 * to exit on each and every L2 page fault. This is done by setting
10432 * MASK=MATCH=0 and (see below) EB.PF=1.
10433 * Note that below we don't need special code to set EB.PF beyond the
10434 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10435 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10436 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10438 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10439 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10440 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10441 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10443 if (cpu_has_secondary_exec_ctrls()) {
10444 exec_control
= vmx
->secondary_exec_control
;
10446 /* Take the following fields only from vmcs12 */
10447 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10448 SECONDARY_EXEC_ENABLE_INVPCID
|
10449 SECONDARY_EXEC_RDTSCP
|
10450 SECONDARY_EXEC_XSAVES
|
10451 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10452 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10453 SECONDARY_EXEC_ENABLE_VMFUNC
);
10454 if (nested_cpu_has(vmcs12
,
10455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10456 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10457 ~SECONDARY_EXEC_ENABLE_PML
;
10458 exec_control
|= vmcs12_exec_ctrl
;
10461 /* All VMFUNCs are currently emulated through L0 vmexits. */
10462 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10463 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10465 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10466 vmcs_write64(EOI_EXIT_BITMAP0
,
10467 vmcs12
->eoi_exit_bitmap0
);
10468 vmcs_write64(EOI_EXIT_BITMAP1
,
10469 vmcs12
->eoi_exit_bitmap1
);
10470 vmcs_write64(EOI_EXIT_BITMAP2
,
10471 vmcs12
->eoi_exit_bitmap2
);
10472 vmcs_write64(EOI_EXIT_BITMAP3
,
10473 vmcs12
->eoi_exit_bitmap3
);
10474 vmcs_write16(GUEST_INTR_STATUS
,
10475 vmcs12
->guest_intr_status
);
10479 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10480 * nested_get_vmcs12_pages will either fix it up or
10481 * remove the VM execution control.
10483 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10484 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10486 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10491 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10492 * Some constant fields are set here by vmx_set_constant_host_state().
10493 * Other fields are different per CPU, and will be set later when
10494 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10496 vmx_set_constant_host_state(vmx
);
10499 * Set the MSR load/store lists to match L0's settings.
10501 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10502 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10503 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10504 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10505 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10508 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10509 * entry, but only if the current (host) sp changed from the value
10510 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10511 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10512 * here we just force the write to happen on entry.
10516 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10517 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10518 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10519 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10520 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10523 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10524 * nested_get_vmcs12_pages can't fix it up, the illegal value
10525 * will result in a VM entry failure.
10527 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10528 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10529 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10531 #ifdef CONFIG_X86_64
10532 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10533 CPU_BASED_CR8_STORE_EXITING
;
10538 * Merging of IO bitmap not currently supported.
10539 * Rather, exit every time.
10541 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10542 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10544 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10546 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10547 * bitwise-or of what L1 wants to trap for L2, and what we want to
10548 * trap. Note that CR0.TS also needs updating - we do this later.
10550 update_exception_bitmap(vcpu
);
10551 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10552 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10554 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10555 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10556 * bits are further modified by vmx_set_efer() below.
10558 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10560 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10561 * emulated by vmx_set_efer(), below.
10563 vm_entry_controls_init(vmx
,
10564 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10565 ~VM_ENTRY_IA32E_MODE
) |
10566 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10568 if (from_vmentry
&&
10569 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10570 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10571 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10572 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10573 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10576 set_cr4_guest_host_mask(vmx
);
10578 if (from_vmentry
&&
10579 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10580 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10582 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10583 vmcs_write64(TSC_OFFSET
,
10584 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10586 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10587 if (kvm_has_tsc_control
)
10588 decache_tsc_multiplier(vmx
);
10592 * There is no direct mapping between vpid02 and vpid12, the
10593 * vpid02 is per-vCPU for L0 and reused while the value of
10594 * vpid12 is changed w/ one invvpid during nested vmentry.
10595 * The vpid12 is allocated by L1 for L2, so it will not
10596 * influence global bitmap(for vpid01 and vpid02 allocation)
10597 * even if spawn a lot of nested vCPUs.
10599 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10600 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10601 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10602 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10603 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10606 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10607 vmx_flush_tlb(vcpu
);
10614 * Conceptually we want to copy the PML address and index from
10615 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10616 * since we always flush the log on each vmexit, this happens
10617 * to be equivalent to simply resetting the fields in vmcs02.
10619 ASSERT(vmx
->pml_pg
);
10620 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10621 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10624 if (nested_cpu_has_ept(vmcs12
)) {
10625 if (nested_ept_init_mmu_context(vcpu
)) {
10626 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10629 } else if (nested_cpu_has2(vmcs12
,
10630 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10631 vmx_flush_tlb_ept_only(vcpu
);
10635 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10636 * bits which we consider mandatory enabled.
10637 * The CR0_READ_SHADOW is what L2 should have expected to read given
10638 * the specifications by L1; It's not enough to take
10639 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10640 * have more bits than L1 expected.
10642 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10643 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10645 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10646 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10648 if (from_vmentry
&&
10649 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10650 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10651 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10652 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10654 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10655 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10656 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10658 /* Shadow page tables on either EPT or shadow page tables. */
10659 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10660 entry_failure_code
))
10664 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10667 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10670 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10671 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10672 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10673 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10676 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10677 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10681 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10683 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10685 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10686 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10687 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10689 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10690 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10692 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10693 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10695 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10696 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10698 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10699 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10701 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10702 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10704 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10705 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10707 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10708 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10709 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10710 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10711 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10712 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10713 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10714 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10715 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10716 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10717 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10718 vmx
->nested
.nested_vmx_exit_ctls_low
,
10719 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10720 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10721 vmx
->nested
.nested_vmx_entry_ctls_low
,
10722 vmx
->nested
.nested_vmx_entry_ctls_high
))
10723 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10725 if (nested_cpu_has_vmfunc(vmcs12
)) {
10726 if (vmcs12
->vm_function_control
&
10727 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10728 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10730 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10731 if (!nested_cpu_has_ept(vmcs12
) ||
10732 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10733 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10737 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10738 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10740 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10741 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10742 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10743 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10748 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10753 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10755 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10756 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10759 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10760 vmcs12
->vmcs_link_pointer
!= -1ull) {
10761 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10766 * If the load IA32_EFER VM-entry control is 1, the following checks
10767 * are performed on the field for the IA32_EFER MSR:
10768 * - Bits reserved in the IA32_EFER MSR must be 0.
10769 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10770 * the IA-32e mode guest VM-exit control. It must also be identical
10771 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10774 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10775 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10776 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10777 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10778 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10779 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10780 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10785 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10786 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10787 * the values of the LMA and LME bits in the field must each be that of
10788 * the host address-space size VM-exit control.
10790 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10791 ia32e
= (vmcs12
->vm_exit_controls
&
10792 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10793 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10794 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10795 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10802 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10804 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10805 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10806 struct loaded_vmcs
*vmcs02
;
10810 vmcs02
= nested_get_current_vmcs02(vmx
);
10814 enter_guest_mode(vcpu
);
10816 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10817 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10819 vmx_switch_vmcs(vcpu
, vmcs02
);
10820 vmx_segment_cache_clear(vmx
);
10822 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10823 leave_guest_mode(vcpu
);
10824 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10825 nested_vmx_entry_failure(vcpu
, vmcs12
,
10826 EXIT_REASON_INVALID_STATE
, exit_qual
);
10830 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10832 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10833 vmcs12
->vm_entry_msr_load_addr
,
10834 vmcs12
->vm_entry_msr_load_count
);
10835 if (msr_entry_idx
) {
10836 leave_guest_mode(vcpu
);
10837 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10838 nested_vmx_entry_failure(vcpu
, vmcs12
,
10839 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10844 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10845 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10846 * returned as far as L1 is concerned. It will only return (and set
10847 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10853 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10854 * for running an L2 nested guest.
10856 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10858 struct vmcs12
*vmcs12
;
10859 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10860 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10864 if (!nested_vmx_check_permission(vcpu
))
10867 if (!nested_vmx_check_vmcs12(vcpu
))
10870 vmcs12
= get_vmcs12(vcpu
);
10872 if (enable_shadow_vmcs
)
10873 copy_shadow_to_vmcs12(vmx
);
10876 * The nested entry process starts with enforcing various prerequisites
10877 * on vmcs12 as required by the Intel SDM, and act appropriately when
10878 * they fail: As the SDM explains, some conditions should cause the
10879 * instruction to fail, while others will cause the instruction to seem
10880 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10881 * To speed up the normal (success) code path, we should avoid checking
10882 * for misconfigurations which will anyway be caught by the processor
10883 * when using the merged vmcs02.
10885 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10886 nested_vmx_failValid(vcpu
,
10887 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10891 if (vmcs12
->launch_state
== launch
) {
10892 nested_vmx_failValid(vcpu
,
10893 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10894 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10898 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10900 nested_vmx_failValid(vcpu
, ret
);
10905 * After this point, the trap flag no longer triggers a singlestep trap
10906 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10907 * This is not 100% correct; for performance reasons, we delegate most
10908 * of the checks on host state to the processor. If those fail,
10909 * the singlestep trap is missed.
10911 skip_emulated_instruction(vcpu
);
10913 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10915 nested_vmx_entry_failure(vcpu
, vmcs12
,
10916 EXIT_REASON_INVALID_STATE
, exit_qual
);
10921 * We're finally done with prerequisite checking, and can start with
10922 * the nested entry.
10925 ret
= enter_vmx_non_root_mode(vcpu
, true);
10929 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10930 return kvm_vcpu_halt(vcpu
);
10932 vmx
->nested
.nested_run_pending
= 1;
10937 return kvm_skip_emulated_instruction(vcpu
);
10941 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10942 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10943 * This function returns the new value we should put in vmcs12.guest_cr0.
10944 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10945 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10946 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10947 * didn't trap the bit, because if L1 did, so would L0).
10948 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10949 * been modified by L2, and L1 knows it. So just leave the old value of
10950 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10951 * isn't relevant, because if L0 traps this bit it can set it to anything.
10952 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10953 * changed these bits, and therefore they need to be updated, but L0
10954 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10955 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10957 static inline unsigned long
10958 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10961 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10962 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10963 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10964 vcpu
->arch
.cr0_guest_owned_bits
));
10967 static inline unsigned long
10968 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10971 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10972 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10973 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10974 vcpu
->arch
.cr4_guest_owned_bits
));
10977 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10978 struct vmcs12
*vmcs12
)
10983 if (vcpu
->arch
.exception
.injected
) {
10984 nr
= vcpu
->arch
.exception
.nr
;
10985 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10987 if (kvm_exception_is_soft(nr
)) {
10988 vmcs12
->vm_exit_instruction_len
=
10989 vcpu
->arch
.event_exit_inst_len
;
10990 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10992 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10994 if (vcpu
->arch
.exception
.has_error_code
) {
10995 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10996 vmcs12
->idt_vectoring_error_code
=
10997 vcpu
->arch
.exception
.error_code
;
11000 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11001 } else if (vcpu
->arch
.nmi_injected
) {
11002 vmcs12
->idt_vectoring_info_field
=
11003 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11004 } else if (vcpu
->arch
.interrupt
.pending
) {
11005 nr
= vcpu
->arch
.interrupt
.nr
;
11006 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11008 if (vcpu
->arch
.interrupt
.soft
) {
11009 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11010 vmcs12
->vm_entry_instruction_len
=
11011 vcpu
->arch
.event_exit_inst_len
;
11013 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11015 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11019 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11021 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11022 unsigned long exit_qual
;
11024 if (kvm_event_needs_reinjection(vcpu
))
11027 if (vcpu
->arch
.exception
.pending
&&
11028 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11029 if (vmx
->nested
.nested_run_pending
)
11031 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11032 vcpu
->arch
.exception
.pending
= false;
11036 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11037 vmx
->nested
.preemption_timer_expired
) {
11038 if (vmx
->nested
.nested_run_pending
)
11040 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11044 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11045 if (vmx
->nested
.nested_run_pending
)
11047 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11048 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11049 INTR_INFO_VALID_MASK
, 0);
11051 * The NMI-triggered VM exit counts as injection:
11052 * clear this one and block further NMIs.
11054 vcpu
->arch
.nmi_pending
= 0;
11055 vmx_set_nmi_mask(vcpu
, true);
11059 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11060 nested_exit_on_intr(vcpu
)) {
11061 if (vmx
->nested
.nested_run_pending
)
11063 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11067 vmx_complete_nested_posted_interrupt(vcpu
);
11071 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11073 ktime_t remaining
=
11074 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11077 if (ktime_to_ns(remaining
) <= 0)
11080 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11081 do_div(value
, 1000000);
11082 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11086 * Update the guest state fields of vmcs12 to reflect changes that
11087 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11088 * VM-entry controls is also updated, since this is really a guest
11091 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11093 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11094 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11096 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11097 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11098 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11100 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11101 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11102 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11103 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11104 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11105 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11106 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11107 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11108 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11109 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11110 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11111 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11112 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11113 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11114 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11115 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11116 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11117 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11118 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11119 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11120 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11121 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11122 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11123 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11124 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11125 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11126 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11127 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11128 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11129 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11130 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11131 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11132 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11133 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11134 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11135 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11137 vmcs12
->guest_interruptibility_info
=
11138 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11139 vmcs12
->guest_pending_dbg_exceptions
=
11140 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11141 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11142 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11144 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11146 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11147 if (vmcs12
->vm_exit_controls
&
11148 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11149 vmcs12
->vmx_preemption_timer_value
=
11150 vmx_get_preemption_timer_value(vcpu
);
11151 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11155 * In some cases (usually, nested EPT), L2 is allowed to change its
11156 * own CR3 without exiting. If it has changed it, we must keep it.
11157 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11158 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11160 * Additionally, restore L2's PDPTR to vmcs12.
11163 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11164 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11165 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11166 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11167 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11170 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11172 if (nested_cpu_has_vid(vmcs12
))
11173 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11175 vmcs12
->vm_entry_controls
=
11176 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11177 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11179 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11180 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11181 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11184 /* TODO: These cannot have changed unless we have MSR bitmaps and
11185 * the relevant bit asks not to trap the change */
11186 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11187 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11188 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11189 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11190 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11191 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11192 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11193 if (kvm_mpx_supported())
11194 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11198 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11199 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11200 * and this function updates it to reflect the changes to the guest state while
11201 * L2 was running (and perhaps made some exits which were handled directly by L0
11202 * without going back to L1), and to reflect the exit reason.
11203 * Note that we do not have to copy here all VMCS fields, just those that
11204 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11205 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11206 * which already writes to vmcs12 directly.
11208 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11209 u32 exit_reason
, u32 exit_intr_info
,
11210 unsigned long exit_qualification
)
11212 /* update guest state fields: */
11213 sync_vmcs12(vcpu
, vmcs12
);
11215 /* update exit information fields: */
11217 vmcs12
->vm_exit_reason
= exit_reason
;
11218 vmcs12
->exit_qualification
= exit_qualification
;
11219 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11221 vmcs12
->idt_vectoring_info_field
= 0;
11222 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11223 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11225 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11226 vmcs12
->launch_state
= 1;
11228 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11229 * instead of reading the real value. */
11230 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11233 * Transfer the event that L0 or L1 may wanted to inject into
11234 * L2 to IDT_VECTORING_INFO_FIELD.
11236 vmcs12_save_pending_event(vcpu
, vmcs12
);
11240 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11241 * preserved above and would only end up incorrectly in L1.
11243 vcpu
->arch
.nmi_injected
= false;
11244 kvm_clear_exception_queue(vcpu
);
11245 kvm_clear_interrupt_queue(vcpu
);
11249 * A part of what we need to when the nested L2 guest exits and we want to
11250 * run its L1 parent, is to reset L1's guest state to the host state specified
11252 * This function is to be called not only on normal nested exit, but also on
11253 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11254 * Failures During or After Loading Guest State").
11255 * This function should be called when the active VMCS is L1's (vmcs01).
11257 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11258 struct vmcs12
*vmcs12
)
11260 struct kvm_segment seg
;
11261 u32 entry_failure_code
;
11263 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11264 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11265 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11266 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11268 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11269 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11271 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11272 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11273 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11275 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11276 * actually changed, because vmx_set_cr0 refers to efer set above.
11278 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11279 * (KVM doesn't change it);
11281 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11282 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11284 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11285 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11286 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
11288 nested_ept_uninit_mmu_context(vcpu
);
11291 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11292 * couldn't have changed.
11294 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11295 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11298 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11302 * Trivially support vpid by letting L2s share their parent
11303 * L1's vpid. TODO: move to a more elaborate solution, giving
11304 * each L2 its own vpid and exposing the vpid feature to L1.
11306 vmx_flush_tlb(vcpu
);
11308 /* Restore posted intr vector. */
11309 if (nested_cpu_has_posted_intr(vmcs12
))
11310 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11312 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11313 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11314 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11315 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11316 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11318 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11319 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11320 vmcs_write64(GUEST_BNDCFGS
, 0);
11322 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11323 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11324 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11326 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11327 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11328 vmcs12
->host_ia32_perf_global_ctrl
);
11330 /* Set L1 segment info according to Intel SDM
11331 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11332 seg
= (struct kvm_segment
) {
11334 .limit
= 0xFFFFFFFF,
11335 .selector
= vmcs12
->host_cs_selector
,
11341 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11345 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11346 seg
= (struct kvm_segment
) {
11348 .limit
= 0xFFFFFFFF,
11355 seg
.selector
= vmcs12
->host_ds_selector
;
11356 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11357 seg
.selector
= vmcs12
->host_es_selector
;
11358 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11359 seg
.selector
= vmcs12
->host_ss_selector
;
11360 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11361 seg
.selector
= vmcs12
->host_fs_selector
;
11362 seg
.base
= vmcs12
->host_fs_base
;
11363 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11364 seg
.selector
= vmcs12
->host_gs_selector
;
11365 seg
.base
= vmcs12
->host_gs_base
;
11366 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11367 seg
= (struct kvm_segment
) {
11368 .base
= vmcs12
->host_tr_base
,
11370 .selector
= vmcs12
->host_tr_selector
,
11374 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11376 kvm_set_dr(vcpu
, 7, 0x400);
11377 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11379 if (cpu_has_vmx_msr_bitmap())
11380 vmx_set_msr_bitmap(vcpu
);
11382 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11383 vmcs12
->vm_exit_msr_load_count
))
11384 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11388 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11389 * and modify vmcs12 to make it see what it would expect to see there if
11390 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11392 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11393 u32 exit_intr_info
,
11394 unsigned long exit_qualification
)
11396 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11397 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11399 /* trying to cancel vmlaunch/vmresume is a bug */
11400 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11403 * The only expected VM-instruction error is "VM entry with
11404 * invalid control field(s)." Anything else indicates a
11407 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11408 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11410 leave_guest_mode(vcpu
);
11412 if (likely(!vmx
->fail
)) {
11413 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11414 exit_qualification
);
11416 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11417 vmcs12
->vm_exit_msr_store_count
))
11418 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11421 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11422 vm_entry_controls_reset_shadow(vmx
);
11423 vm_exit_controls_reset_shadow(vmx
);
11424 vmx_segment_cache_clear(vmx
);
11426 /* if no vmcs02 cache requested, remove the one we used */
11427 if (VMCS02_POOL_SIZE
== 0)
11428 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11430 /* Update any VMCS fields that might have changed while L2 ran */
11431 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11432 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11433 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11434 if (vmx
->hv_deadline_tsc
== -1)
11435 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11436 PIN_BASED_VMX_PREEMPTION_TIMER
);
11438 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11439 PIN_BASED_VMX_PREEMPTION_TIMER
);
11440 if (kvm_has_tsc_control
)
11441 decache_tsc_multiplier(vmx
);
11443 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11444 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11445 vmx_set_virtual_x2apic_mode(vcpu
,
11446 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11447 } else if (!nested_cpu_has_ept(vmcs12
) &&
11448 nested_cpu_has2(vmcs12
,
11449 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11450 vmx_flush_tlb_ept_only(vcpu
);
11453 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11456 /* Unpin physical memory we referred to in vmcs02 */
11457 if (vmx
->nested
.apic_access_page
) {
11458 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11459 vmx
->nested
.apic_access_page
= NULL
;
11461 if (vmx
->nested
.virtual_apic_page
) {
11462 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11463 vmx
->nested
.virtual_apic_page
= NULL
;
11465 if (vmx
->nested
.pi_desc_page
) {
11466 kunmap(vmx
->nested
.pi_desc_page
);
11467 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11468 vmx
->nested
.pi_desc_page
= NULL
;
11469 vmx
->nested
.pi_desc
= NULL
;
11473 * We are now running in L2, mmu_notifier will force to reload the
11474 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11476 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11478 if (enable_shadow_vmcs
)
11479 vmx
->nested
.sync_shadow_vmcs
= true;
11481 /* in case we halted in L2 */
11482 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11484 if (likely(!vmx
->fail
)) {
11486 * TODO: SDM says that with acknowledge interrupt on
11487 * exit, bit 31 of the VM-exit interrupt information
11488 * (valid interrupt) is always set to 1 on
11489 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11490 * need kvm_cpu_has_interrupt(). See the commit
11491 * message for details.
11493 if (nested_exit_intr_ack_set(vcpu
) &&
11494 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11495 kvm_cpu_has_interrupt(vcpu
)) {
11496 int irq
= kvm_cpu_get_interrupt(vcpu
);
11498 vmcs12
->vm_exit_intr_info
= irq
|
11499 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11502 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11503 vmcs12
->exit_qualification
,
11504 vmcs12
->idt_vectoring_info_field
,
11505 vmcs12
->vm_exit_intr_info
,
11506 vmcs12
->vm_exit_intr_error_code
,
11509 load_vmcs12_host_state(vcpu
, vmcs12
);
11515 * After an early L2 VM-entry failure, we're now back
11516 * in L1 which thinks it just finished a VMLAUNCH or
11517 * VMRESUME instruction, so we need to set the failure
11518 * flag and the VM-instruction error field of the VMCS
11521 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11523 * The emulated instruction was already skipped in
11524 * nested_vmx_run, but the updated RIP was never
11525 * written back to the vmcs01.
11527 skip_emulated_instruction(vcpu
);
11532 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11534 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11536 if (is_guest_mode(vcpu
)) {
11537 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11538 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11540 free_nested(to_vmx(vcpu
));
11544 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11545 * 23.7 "VM-entry failures during or after loading guest state" (this also
11546 * lists the acceptable exit-reason and exit-qualification parameters).
11547 * It should only be called before L2 actually succeeded to run, and when
11548 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11550 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11551 struct vmcs12
*vmcs12
,
11552 u32 reason
, unsigned long qualification
)
11554 load_vmcs12_host_state(vcpu
, vmcs12
);
11555 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11556 vmcs12
->exit_qualification
= qualification
;
11557 nested_vmx_succeed(vcpu
);
11558 if (enable_shadow_vmcs
)
11559 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11562 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11563 struct x86_instruction_info
*info
,
11564 enum x86_intercept_stage stage
)
11566 return X86EMUL_CONTINUE
;
11569 #ifdef CONFIG_X86_64
11570 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11571 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11572 u64 divisor
, u64
*result
)
11574 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11576 /* To avoid the overflow on divq */
11577 if (high
>= divisor
)
11580 /* Low hold the result, high hold rem which is discarded */
11581 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11582 "rm" (divisor
), "0" (low
), "1" (high
));
11588 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11591 u64 tscl
= rdtsc();
11592 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11593 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11595 /* Convert to host delta tsc if tsc scaling is enabled */
11596 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11597 u64_shl_div_u64(delta_tsc
,
11598 kvm_tsc_scaling_ratio_frac_bits
,
11599 vcpu
->arch
.tsc_scaling_ratio
,
11604 * If the delta tsc can't fit in the 32 bit after the multi shift,
11605 * we can't use the preemption timer.
11606 * It's possible that it fits on later vmentries, but checking
11607 * on every vmentry is costly so we just use an hrtimer.
11609 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11612 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11613 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11614 PIN_BASED_VMX_PREEMPTION_TIMER
);
11616 return delta_tsc
== 0;
11619 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11621 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11622 vmx
->hv_deadline_tsc
= -1;
11623 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11624 PIN_BASED_VMX_PREEMPTION_TIMER
);
11628 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11631 shrink_ple_window(vcpu
);
11634 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11635 struct kvm_memory_slot
*slot
)
11637 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11638 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11641 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11642 struct kvm_memory_slot
*slot
)
11644 kvm_mmu_slot_set_dirty(kvm
, slot
);
11647 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11649 kvm_flush_pml_buffers(kvm
);
11652 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11654 struct vmcs12
*vmcs12
;
11655 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11657 struct page
*page
= NULL
;
11660 if (is_guest_mode(vcpu
)) {
11661 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11664 * Check if PML is enabled for the nested guest.
11665 * Whether eptp bit 6 is set is already checked
11666 * as part of A/D emulation.
11668 vmcs12
= get_vmcs12(vcpu
);
11669 if (!nested_cpu_has_pml(vmcs12
))
11672 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11673 vmx
->nested
.pml_full
= true;
11677 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11679 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11680 if (is_error_page(page
))
11683 pml_address
= kmap(page
);
11684 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11686 kvm_release_page_clean(page
);
11692 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11693 struct kvm_memory_slot
*memslot
,
11694 gfn_t offset
, unsigned long mask
)
11696 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11700 * This routine does the following things for vCPU which is going
11701 * to be blocked if VT-d PI is enabled.
11702 * - Store the vCPU to the wakeup list, so when interrupts happen
11703 * we can find the right vCPU to wake up.
11704 * - Change the Posted-interrupt descriptor as below:
11705 * 'NDST' <-- vcpu->pre_pcpu
11706 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11707 * - If 'ON' is set during this process, which means at least one
11708 * interrupt is posted for this vCPU, we cannot block it, in
11709 * this case, return 1, otherwise, return 0.
11712 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11714 unsigned long flags
;
11716 struct pi_desc old
, new;
11717 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11719 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11720 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11721 !kvm_vcpu_apicv_active(vcpu
))
11724 vcpu
->pre_pcpu
= vcpu
->cpu
;
11725 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11726 vcpu
->pre_pcpu
), flags
);
11727 list_add_tail(&vcpu
->blocked_vcpu_list
,
11728 &per_cpu(blocked_vcpu_on_cpu
,
11730 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11731 vcpu
->pre_pcpu
), flags
);
11734 old
.control
= new.control
= pi_desc
->control
;
11737 * We should not block the vCPU if
11738 * an interrupt is posted for it.
11740 if (pi_test_on(pi_desc
) == 1) {
11741 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11742 vcpu
->pre_pcpu
), flags
);
11743 list_del(&vcpu
->blocked_vcpu_list
);
11744 spin_unlock_irqrestore(
11745 &per_cpu(blocked_vcpu_on_cpu_lock
,
11746 vcpu
->pre_pcpu
), flags
);
11747 vcpu
->pre_pcpu
= -1;
11752 WARN((pi_desc
->sn
== 1),
11753 "Warning: SN field of posted-interrupts "
11754 "is set before blocking\n");
11757 * Since vCPU can be preempted during this process,
11758 * vcpu->cpu could be different with pre_pcpu, we
11759 * need to set pre_pcpu as the destination of wakeup
11760 * notification event, then we can find the right vCPU
11761 * to wakeup in wakeup handler if interrupts happen
11762 * when the vCPU is in blocked state.
11764 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11766 if (x2apic_enabled())
11769 new.ndst
= (dest
<< 8) & 0xFF00;
11771 /* set 'NV' to 'wakeup vector' */
11772 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11773 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11774 new.control
) != old
.control
);
11779 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11781 if (pi_pre_block(vcpu
))
11784 if (kvm_lapic_hv_timer_in_use(vcpu
))
11785 kvm_lapic_switch_to_sw_timer(vcpu
);
11790 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11792 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11793 struct pi_desc old
, new;
11795 unsigned long flags
;
11797 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11798 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11799 !kvm_vcpu_apicv_active(vcpu
))
11803 old
.control
= new.control
= pi_desc
->control
;
11805 dest
= cpu_physical_id(vcpu
->cpu
);
11807 if (x2apic_enabled())
11810 new.ndst
= (dest
<< 8) & 0xFF00;
11812 /* Allow posting non-urgent interrupts */
11815 /* set 'NV' to 'notification vector' */
11816 new.nv
= POSTED_INTR_VECTOR
;
11817 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11818 new.control
) != old
.control
);
11820 if(vcpu
->pre_pcpu
!= -1) {
11822 &per_cpu(blocked_vcpu_on_cpu_lock
,
11823 vcpu
->pre_pcpu
), flags
);
11824 list_del(&vcpu
->blocked_vcpu_list
);
11825 spin_unlock_irqrestore(
11826 &per_cpu(blocked_vcpu_on_cpu_lock
,
11827 vcpu
->pre_pcpu
), flags
);
11828 vcpu
->pre_pcpu
= -1;
11832 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11834 if (kvm_x86_ops
->set_hv_timer
)
11835 kvm_lapic_switch_to_hv_timer(vcpu
);
11837 pi_post_block(vcpu
);
11841 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11844 * @host_irq: host irq of the interrupt
11845 * @guest_irq: gsi of the interrupt
11846 * @set: set or unset PI
11847 * returns 0 on success, < 0 on failure
11849 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11850 uint32_t guest_irq
, bool set
)
11852 struct kvm_kernel_irq_routing_entry
*e
;
11853 struct kvm_irq_routing_table
*irq_rt
;
11854 struct kvm_lapic_irq irq
;
11855 struct kvm_vcpu
*vcpu
;
11856 struct vcpu_data vcpu_info
;
11859 if (!kvm_arch_has_assigned_device(kvm
) ||
11860 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11861 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11864 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11865 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11866 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11867 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11868 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11869 guest_irq
, irq_rt
->nr_rt_entries
);
11873 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11874 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11877 * VT-d PI cannot support posting multicast/broadcast
11878 * interrupts to a vCPU, we still use interrupt remapping
11879 * for these kind of interrupts.
11881 * For lowest-priority interrupts, we only support
11882 * those with single CPU as the destination, e.g. user
11883 * configures the interrupts via /proc/irq or uses
11884 * irqbalance to make the interrupts single-CPU.
11886 * We will support full lowest-priority interrupt later.
11889 kvm_set_msi_irq(kvm
, e
, &irq
);
11890 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11892 * Make sure the IRTE is in remapped mode if
11893 * we don't handle it in posted mode.
11895 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11898 "failed to back to remapped mode, irq: %u\n",
11906 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11907 vcpu_info
.vector
= irq
.vector
;
11909 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11910 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11913 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11915 /* suppress notification event before unposting */
11916 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11917 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11918 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11922 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11930 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11934 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11936 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11937 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11938 FEATURE_CONTROL_LMCE
;
11940 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11941 ~FEATURE_CONTROL_LMCE
;
11944 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11945 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11946 .disabled_by_bios
= vmx_disabled_by_bios
,
11947 .hardware_setup
= hardware_setup
,
11948 .hardware_unsetup
= hardware_unsetup
,
11949 .check_processor_compatibility
= vmx_check_processor_compat
,
11950 .hardware_enable
= hardware_enable
,
11951 .hardware_disable
= hardware_disable
,
11952 .cpu_has_accelerated_tpr
= report_flexpriority
,
11953 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11955 .vcpu_create
= vmx_create_vcpu
,
11956 .vcpu_free
= vmx_free_vcpu
,
11957 .vcpu_reset
= vmx_vcpu_reset
,
11959 .prepare_guest_switch
= vmx_save_host_state
,
11960 .vcpu_load
= vmx_vcpu_load
,
11961 .vcpu_put
= vmx_vcpu_put
,
11963 .update_bp_intercept
= update_exception_bitmap
,
11964 .get_msr
= vmx_get_msr
,
11965 .set_msr
= vmx_set_msr
,
11966 .get_segment_base
= vmx_get_segment_base
,
11967 .get_segment
= vmx_get_segment
,
11968 .set_segment
= vmx_set_segment
,
11969 .get_cpl
= vmx_get_cpl
,
11970 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11971 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11972 .decache_cr3
= vmx_decache_cr3
,
11973 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11974 .set_cr0
= vmx_set_cr0
,
11975 .set_cr3
= vmx_set_cr3
,
11976 .set_cr4
= vmx_set_cr4
,
11977 .set_efer
= vmx_set_efer
,
11978 .get_idt
= vmx_get_idt
,
11979 .set_idt
= vmx_set_idt
,
11980 .get_gdt
= vmx_get_gdt
,
11981 .set_gdt
= vmx_set_gdt
,
11982 .get_dr6
= vmx_get_dr6
,
11983 .set_dr6
= vmx_set_dr6
,
11984 .set_dr7
= vmx_set_dr7
,
11985 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11986 .cache_reg
= vmx_cache_reg
,
11987 .get_rflags
= vmx_get_rflags
,
11988 .set_rflags
= vmx_set_rflags
,
11990 .tlb_flush
= vmx_flush_tlb
,
11992 .run
= vmx_vcpu_run
,
11993 .handle_exit
= vmx_handle_exit
,
11994 .skip_emulated_instruction
= skip_emulated_instruction
,
11995 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11996 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11997 .patch_hypercall
= vmx_patch_hypercall
,
11998 .set_irq
= vmx_inject_irq
,
11999 .set_nmi
= vmx_inject_nmi
,
12000 .queue_exception
= vmx_queue_exception
,
12001 .cancel_injection
= vmx_cancel_injection
,
12002 .interrupt_allowed
= vmx_interrupt_allowed
,
12003 .nmi_allowed
= vmx_nmi_allowed
,
12004 .get_nmi_mask
= vmx_get_nmi_mask
,
12005 .set_nmi_mask
= vmx_set_nmi_mask
,
12006 .enable_nmi_window
= enable_nmi_window
,
12007 .enable_irq_window
= enable_irq_window
,
12008 .update_cr8_intercept
= update_cr8_intercept
,
12009 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12010 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12011 .get_enable_apicv
= vmx_get_enable_apicv
,
12012 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12013 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12014 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12015 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12016 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12017 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12018 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12020 .set_tss_addr
= vmx_set_tss_addr
,
12021 .get_tdp_level
= get_ept_level
,
12022 .get_mt_mask
= vmx_get_mt_mask
,
12024 .get_exit_info
= vmx_get_exit_info
,
12026 .get_lpage_level
= vmx_get_lpage_level
,
12028 .cpuid_update
= vmx_cpuid_update
,
12030 .rdtscp_supported
= vmx_rdtscp_supported
,
12031 .invpcid_supported
= vmx_invpcid_supported
,
12033 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12035 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12037 .write_tsc_offset
= vmx_write_tsc_offset
,
12039 .set_tdp_cr3
= vmx_set_cr3
,
12041 .check_intercept
= vmx_check_intercept
,
12042 .handle_external_intr
= vmx_handle_external_intr
,
12043 .mpx_supported
= vmx_mpx_supported
,
12044 .xsaves_supported
= vmx_xsaves_supported
,
12046 .check_nested_events
= vmx_check_nested_events
,
12048 .sched_in
= vmx_sched_in
,
12050 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12051 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12052 .flush_log_dirty
= vmx_flush_log_dirty
,
12053 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12054 .write_log_dirty
= vmx_write_pml_buffer
,
12056 .pre_block
= vmx_pre_block
,
12057 .post_block
= vmx_post_block
,
12059 .pmu_ops
= &intel_pmu_ops
,
12061 .update_pi_irte
= vmx_update_pi_irte
,
12063 #ifdef CONFIG_X86_64
12064 .set_hv_timer
= vmx_set_hv_timer
,
12065 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12068 .setup_mce
= vmx_setup_mce
,
12071 static int __init
vmx_init(void)
12073 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12074 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12078 #ifdef CONFIG_KEXEC_CORE
12079 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12080 crash_vmclear_local_loaded_vmcss
);
12086 static void __exit
vmx_exit(void)
12088 #ifdef CONFIG_KEXEC_CORE
12089 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12096 module_init(vmx_init
)
12097 module_exit(vmx_exit
)