2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
136 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
137 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
138 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
139 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
142 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
143 * ple_gap: upper bound on the amount of time between two successive
144 * executions of PAUSE in a loop. Also indicate if ple enabled.
145 * According to test, this time is usually smaller than 128 cycles.
146 * ple_window: upper bound on the amount of time a guest is allowed to execute
147 * in a PAUSE loop. Tests indicate that most spinlocks are held for
148 * less than 2^12 cycles
149 * Time is measured based on a counter that runs at the same rate as the TSC,
150 * refer SDM volume 3b section 21.6.13 & 22.1.3.
152 #define KVM_VMX_DEFAULT_PLE_GAP 128
153 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
154 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
155 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
156 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
157 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
159 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
160 module_param(ple_gap
, int, S_IRUGO
);
162 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
163 module_param(ple_window
, int, S_IRUGO
);
165 /* Default doubles per-vcpu window every exit. */
166 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
167 module_param(ple_window_grow
, int, S_IRUGO
);
169 /* Default resets per-vcpu window every exit to ple_window. */
170 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
171 module_param(ple_window_shrink
, int, S_IRUGO
);
173 /* Default is to compute the maximum so we can never overflow. */
174 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
175 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
176 module_param(ple_window_max
, int, S_IRUGO
);
178 extern const ulong vmx_return
;
180 #define NR_AUTOLOAD_MSRS 8
181 #define VMCS02_POOL_SIZE 1
190 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
191 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
192 * loaded on this CPU (so we can clear them if the CPU goes down).
196 struct vmcs
*shadow_vmcs
;
199 struct list_head loaded_vmcss_on_cpu_link
;
202 struct shared_msr_entry
{
209 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
210 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
211 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
212 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
213 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
214 * More than one of these structures may exist, if L1 runs multiple L2 guests.
215 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
216 * underlying hardware which will be used to run L2.
217 * This structure is packed to ensure that its layout is identical across
218 * machines (necessary for live migration).
219 * If there are changes in this struct, VMCS12_REVISION must be changed.
221 typedef u64 natural_width
;
222 struct __packed vmcs12
{
223 /* According to the Intel spec, a VMCS region must start with the
224 * following two fields. Then follow implementation-specific data.
229 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
230 u32 padding
[7]; /* room for future expansion */
235 u64 vm_exit_msr_store_addr
;
236 u64 vm_exit_msr_load_addr
;
237 u64 vm_entry_msr_load_addr
;
239 u64 virtual_apic_page_addr
;
240 u64 apic_access_addr
;
241 u64 posted_intr_desc_addr
;
243 u64 eoi_exit_bitmap0
;
244 u64 eoi_exit_bitmap1
;
245 u64 eoi_exit_bitmap2
;
246 u64 eoi_exit_bitmap3
;
248 u64 guest_physical_address
;
249 u64 vmcs_link_pointer
;
250 u64 guest_ia32_debugctl
;
253 u64 guest_ia32_perf_global_ctrl
;
261 u64 host_ia32_perf_global_ctrl
;
262 u64 padding64
[8]; /* room for future expansion */
264 * To allow migration of L1 (complete with its L2 guests) between
265 * machines of different natural widths (32 or 64 bit), we cannot have
266 * unsigned long fields with no explict size. We use u64 (aliased
267 * natural_width) instead. Luckily, x86 is little-endian.
269 natural_width cr0_guest_host_mask
;
270 natural_width cr4_guest_host_mask
;
271 natural_width cr0_read_shadow
;
272 natural_width cr4_read_shadow
;
273 natural_width cr3_target_value0
;
274 natural_width cr3_target_value1
;
275 natural_width cr3_target_value2
;
276 natural_width cr3_target_value3
;
277 natural_width exit_qualification
;
278 natural_width guest_linear_address
;
279 natural_width guest_cr0
;
280 natural_width guest_cr3
;
281 natural_width guest_cr4
;
282 natural_width guest_es_base
;
283 natural_width guest_cs_base
;
284 natural_width guest_ss_base
;
285 natural_width guest_ds_base
;
286 natural_width guest_fs_base
;
287 natural_width guest_gs_base
;
288 natural_width guest_ldtr_base
;
289 natural_width guest_tr_base
;
290 natural_width guest_gdtr_base
;
291 natural_width guest_idtr_base
;
292 natural_width guest_dr7
;
293 natural_width guest_rsp
;
294 natural_width guest_rip
;
295 natural_width guest_rflags
;
296 natural_width guest_pending_dbg_exceptions
;
297 natural_width guest_sysenter_esp
;
298 natural_width guest_sysenter_eip
;
299 natural_width host_cr0
;
300 natural_width host_cr3
;
301 natural_width host_cr4
;
302 natural_width host_fs_base
;
303 natural_width host_gs_base
;
304 natural_width host_tr_base
;
305 natural_width host_gdtr_base
;
306 natural_width host_idtr_base
;
307 natural_width host_ia32_sysenter_esp
;
308 natural_width host_ia32_sysenter_eip
;
309 natural_width host_rsp
;
310 natural_width host_rip
;
311 natural_width paddingl
[8]; /* room for future expansion */
312 u32 pin_based_vm_exec_control
;
313 u32 cpu_based_vm_exec_control
;
314 u32 exception_bitmap
;
315 u32 page_fault_error_code_mask
;
316 u32 page_fault_error_code_match
;
317 u32 cr3_target_count
;
318 u32 vm_exit_controls
;
319 u32 vm_exit_msr_store_count
;
320 u32 vm_exit_msr_load_count
;
321 u32 vm_entry_controls
;
322 u32 vm_entry_msr_load_count
;
323 u32 vm_entry_intr_info_field
;
324 u32 vm_entry_exception_error_code
;
325 u32 vm_entry_instruction_len
;
327 u32 secondary_vm_exec_control
;
328 u32 vm_instruction_error
;
330 u32 vm_exit_intr_info
;
331 u32 vm_exit_intr_error_code
;
332 u32 idt_vectoring_info_field
;
333 u32 idt_vectoring_error_code
;
334 u32 vm_exit_instruction_len
;
335 u32 vmx_instruction_info
;
342 u32 guest_ldtr_limit
;
344 u32 guest_gdtr_limit
;
345 u32 guest_idtr_limit
;
346 u32 guest_es_ar_bytes
;
347 u32 guest_cs_ar_bytes
;
348 u32 guest_ss_ar_bytes
;
349 u32 guest_ds_ar_bytes
;
350 u32 guest_fs_ar_bytes
;
351 u32 guest_gs_ar_bytes
;
352 u32 guest_ldtr_ar_bytes
;
353 u32 guest_tr_ar_bytes
;
354 u32 guest_interruptibility_info
;
355 u32 guest_activity_state
;
356 u32 guest_sysenter_cs
;
357 u32 host_ia32_sysenter_cs
;
358 u32 vmx_preemption_timer_value
;
359 u32 padding32
[7]; /* room for future expansion */
360 u16 virtual_processor_id
;
362 u16 guest_es_selector
;
363 u16 guest_cs_selector
;
364 u16 guest_ss_selector
;
365 u16 guest_ds_selector
;
366 u16 guest_fs_selector
;
367 u16 guest_gs_selector
;
368 u16 guest_ldtr_selector
;
369 u16 guest_tr_selector
;
370 u16 guest_intr_status
;
371 u16 host_es_selector
;
372 u16 host_cs_selector
;
373 u16 host_ss_selector
;
374 u16 host_ds_selector
;
375 u16 host_fs_selector
;
376 u16 host_gs_selector
;
377 u16 host_tr_selector
;
381 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
382 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
383 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
385 #define VMCS12_REVISION 0x11e57ed0
388 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
389 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
390 * current implementation, 4K are reserved to avoid future complications.
392 #define VMCS12_SIZE 0x1000
394 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
396 struct list_head list
;
398 struct loaded_vmcs vmcs02
;
402 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
403 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
406 /* Has the level1 guest done vmxon? */
410 /* The guest-physical address of the current VMCS L1 keeps for L2 */
412 /* The host-usable pointer to the above */
413 struct page
*current_vmcs12_page
;
414 struct vmcs12
*current_vmcs12
;
416 * Cache of the guest's VMCS, existing outside of guest memory.
417 * Loaded from guest memory during VMPTRLD. Flushed to guest
418 * memory during VMXOFF, VMCLEAR, VMPTRLD.
420 struct vmcs12
*cached_vmcs12
;
422 * Indicates if the shadow vmcs must be updated with the
423 * data hold by vmcs12
425 bool sync_shadow_vmcs
;
427 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
428 struct list_head vmcs02_pool
;
430 bool change_vmcs01_virtual_x2apic_mode
;
431 /* L2 must run next, and mustn't decide to exit to L1. */
432 bool nested_run_pending
;
434 * Guest pages referred to in vmcs02 with host-physical pointers, so
435 * we must keep them pinned while L2 runs.
437 struct page
*apic_access_page
;
438 struct page
*virtual_apic_page
;
439 struct page
*pi_desc_page
;
440 struct pi_desc
*pi_desc
;
444 unsigned long *msr_bitmap
;
446 struct hrtimer preemption_timer
;
447 bool preemption_timer_expired
;
449 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
455 u32 nested_vmx_procbased_ctls_low
;
456 u32 nested_vmx_procbased_ctls_high
;
457 u32 nested_vmx_true_procbased_ctls_low
;
458 u32 nested_vmx_secondary_ctls_low
;
459 u32 nested_vmx_secondary_ctls_high
;
460 u32 nested_vmx_pinbased_ctls_low
;
461 u32 nested_vmx_pinbased_ctls_high
;
462 u32 nested_vmx_exit_ctls_low
;
463 u32 nested_vmx_exit_ctls_high
;
464 u32 nested_vmx_true_exit_ctls_low
;
465 u32 nested_vmx_entry_ctls_low
;
466 u32 nested_vmx_entry_ctls_high
;
467 u32 nested_vmx_true_entry_ctls_low
;
468 u32 nested_vmx_misc_low
;
469 u32 nested_vmx_misc_high
;
470 u32 nested_vmx_ept_caps
;
471 u32 nested_vmx_vpid_caps
;
474 #define POSTED_INTR_ON 0
475 #define POSTED_INTR_SN 1
477 /* Posted-Interrupt Descriptor */
479 u32 pir
[8]; /* Posted interrupt requested */
482 /* bit 256 - Outstanding Notification */
484 /* bit 257 - Suppress Notification */
486 /* bit 271:258 - Reserved */
488 /* bit 279:272 - Notification Vector */
490 /* bit 287:280 - Reserved */
492 /* bit 319:288 - Notification Destination */
500 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
502 return test_and_set_bit(POSTED_INTR_ON
,
503 (unsigned long *)&pi_desc
->control
);
506 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
508 return test_and_clear_bit(POSTED_INTR_ON
,
509 (unsigned long *)&pi_desc
->control
);
512 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
514 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
517 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
519 return clear_bit(POSTED_INTR_SN
,
520 (unsigned long *)&pi_desc
->control
);
523 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
525 return set_bit(POSTED_INTR_SN
,
526 (unsigned long *)&pi_desc
->control
);
529 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
531 clear_bit(POSTED_INTR_ON
,
532 (unsigned long *)&pi_desc
->control
);
535 static inline int pi_test_on(struct pi_desc
*pi_desc
)
537 return test_bit(POSTED_INTR_ON
,
538 (unsigned long *)&pi_desc
->control
);
541 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
543 return test_bit(POSTED_INTR_SN
,
544 (unsigned long *)&pi_desc
->control
);
548 struct kvm_vcpu vcpu
;
549 unsigned long host_rsp
;
551 bool nmi_known_unmasked
;
553 u32 idt_vectoring_info
;
555 struct shared_msr_entry
*guest_msrs
;
558 unsigned long host_idt_base
;
560 u64 msr_host_kernel_gs_base
;
561 u64 msr_guest_kernel_gs_base
;
563 u32 vm_entry_controls_shadow
;
564 u32 vm_exit_controls_shadow
;
566 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
567 * non-nested (L1) guest, it always points to vmcs01. For a nested
568 * guest (L2), it points to a different VMCS.
570 struct loaded_vmcs vmcs01
;
571 struct loaded_vmcs
*loaded_vmcs
;
572 bool __launched
; /* temporary, used in vmx_vcpu_run */
573 struct msr_autoload
{
575 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
576 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
580 u16 fs_sel
, gs_sel
, ldt_sel
;
584 int gs_ldt_reload_needed
;
585 int fs_reload_needed
;
586 u64 msr_host_bndcfgs
;
587 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
592 struct kvm_segment segs
[8];
595 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
596 struct kvm_save_segment
{
604 bool emulation_required
;
606 /* Support for vnmi-less CPUs */
607 int soft_vnmi_blocked
;
609 s64 vnmi_blocked_time
;
612 /* Posted interrupt descriptor */
613 struct pi_desc pi_desc
;
615 /* Support for a guest hypervisor (nested VMX) */
616 struct nested_vmx nested
;
618 /* Dynamic PLE window. */
620 bool ple_window_dirty
;
622 /* Support for PML */
623 #define PML_ENTITY_NUM 512
626 /* apic deadline value in host tsc */
629 u64 current_tsc_ratio
;
631 bool guest_pkru_valid
;
636 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
637 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
638 * in msr_ia32_feature_control_valid_bits.
640 u64 msr_ia32_feature_control
;
641 u64 msr_ia32_feature_control_valid_bits
;
644 enum segment_cache_field
{
653 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
655 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
658 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
660 return &(to_vmx(vcpu
)->pi_desc
);
663 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
664 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
665 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
666 [number##_HIGH] = VMCS12_OFFSET(name)+4
669 static unsigned long shadow_read_only_fields
[] = {
671 * We do NOT shadow fields that are modified when L0
672 * traps and emulates any vmx instruction (e.g. VMPTRLD,
673 * VMXON...) executed by L1.
674 * For example, VM_INSTRUCTION_ERROR is read
675 * by L1 if a vmx instruction fails (part of the error path).
676 * Note the code assumes this logic. If for some reason
677 * we start shadowing these fields then we need to
678 * force a shadow sync when L0 emulates vmx instructions
679 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
680 * by nested_vmx_failValid)
684 VM_EXIT_INSTRUCTION_LEN
,
685 IDT_VECTORING_INFO_FIELD
,
686 IDT_VECTORING_ERROR_CODE
,
687 VM_EXIT_INTR_ERROR_CODE
,
689 GUEST_LINEAR_ADDRESS
,
690 GUEST_PHYSICAL_ADDRESS
692 static int max_shadow_read_only_fields
=
693 ARRAY_SIZE(shadow_read_only_fields
);
695 static unsigned long shadow_read_write_fields
[] = {
702 GUEST_INTERRUPTIBILITY_INFO
,
715 CPU_BASED_VM_EXEC_CONTROL
,
716 VM_ENTRY_EXCEPTION_ERROR_CODE
,
717 VM_ENTRY_INTR_INFO_FIELD
,
718 VM_ENTRY_INSTRUCTION_LEN
,
719 VM_ENTRY_EXCEPTION_ERROR_CODE
,
725 static int max_shadow_read_write_fields
=
726 ARRAY_SIZE(shadow_read_write_fields
);
728 static const unsigned short vmcs_field_to_offset_table
[] = {
729 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
730 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
731 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
732 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
733 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
734 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
735 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
736 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
737 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
738 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
739 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
740 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
741 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
742 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
743 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
744 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
745 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
746 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
747 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
748 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
749 FIELD64(MSR_BITMAP
, msr_bitmap
),
750 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
751 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
752 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
753 FIELD64(TSC_OFFSET
, tsc_offset
),
754 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
755 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
756 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
757 FIELD64(EPT_POINTER
, ept_pointer
),
758 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
759 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
760 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
761 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
762 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
763 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
764 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
765 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
766 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
767 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
768 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
769 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
770 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
771 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
772 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
773 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
774 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
775 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
776 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
777 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
778 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
779 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
780 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
781 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
782 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
783 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
784 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
785 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
786 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
787 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
788 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
789 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
790 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
791 FIELD(TPR_THRESHOLD
, tpr_threshold
),
792 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
793 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
794 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
795 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
796 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
797 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
798 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
799 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
800 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
801 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
802 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
803 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
804 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
805 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
806 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
807 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
808 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
809 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
810 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
811 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
812 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
813 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
814 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
815 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
816 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
817 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
818 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
819 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
820 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
821 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
822 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
823 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
824 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
825 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
826 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
827 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
828 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
829 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
830 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
831 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
832 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
833 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
834 FIELD(GUEST_CR0
, guest_cr0
),
835 FIELD(GUEST_CR3
, guest_cr3
),
836 FIELD(GUEST_CR4
, guest_cr4
),
837 FIELD(GUEST_ES_BASE
, guest_es_base
),
838 FIELD(GUEST_CS_BASE
, guest_cs_base
),
839 FIELD(GUEST_SS_BASE
, guest_ss_base
),
840 FIELD(GUEST_DS_BASE
, guest_ds_base
),
841 FIELD(GUEST_FS_BASE
, guest_fs_base
),
842 FIELD(GUEST_GS_BASE
, guest_gs_base
),
843 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
844 FIELD(GUEST_TR_BASE
, guest_tr_base
),
845 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
846 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
847 FIELD(GUEST_DR7
, guest_dr7
),
848 FIELD(GUEST_RSP
, guest_rsp
),
849 FIELD(GUEST_RIP
, guest_rip
),
850 FIELD(GUEST_RFLAGS
, guest_rflags
),
851 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
852 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
853 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
854 FIELD(HOST_CR0
, host_cr0
),
855 FIELD(HOST_CR3
, host_cr3
),
856 FIELD(HOST_CR4
, host_cr4
),
857 FIELD(HOST_FS_BASE
, host_fs_base
),
858 FIELD(HOST_GS_BASE
, host_gs_base
),
859 FIELD(HOST_TR_BASE
, host_tr_base
),
860 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
861 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
862 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
863 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
864 FIELD(HOST_RSP
, host_rsp
),
865 FIELD(HOST_RIP
, host_rip
),
868 static inline short vmcs_field_to_offset(unsigned long field
)
870 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
872 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
873 vmcs_field_to_offset_table
[field
] == 0)
876 return vmcs_field_to_offset_table
[field
];
879 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
881 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
884 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
886 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
887 if (is_error_page(page
))
893 static void nested_release_page(struct page
*page
)
895 kvm_release_page_dirty(page
);
898 static void nested_release_page_clean(struct page
*page
)
900 kvm_release_page_clean(page
);
903 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
904 static u64
construct_eptp(unsigned long root_hpa
);
905 static void kvm_cpu_vmxon(u64 addr
);
906 static void kvm_cpu_vmxoff(void);
907 static bool vmx_xsaves_supported(void);
908 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
909 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
910 struct kvm_segment
*var
, int seg
);
911 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
912 struct kvm_segment
*var
, int seg
);
913 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
914 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
915 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
916 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
917 static int alloc_identity_pagetable(struct kvm
*kvm
);
919 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
920 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
922 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
923 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
925 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
926 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
929 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
930 * can find which vCPU should be waken up.
932 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
933 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
938 VMX_MSR_BITMAP_LEGACY
,
939 VMX_MSR_BITMAP_LONGMODE
,
940 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
941 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
942 VMX_MSR_BITMAP_LEGACY_X2APIC
,
943 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
949 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
951 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
952 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
953 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
954 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
955 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
956 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
957 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
958 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
959 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
960 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
962 static bool cpu_has_load_ia32_efer
;
963 static bool cpu_has_load_perf_global_ctrl
;
965 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
966 static DEFINE_SPINLOCK(vmx_vpid_lock
);
968 static struct vmcs_config
{
973 u32 pin_based_exec_ctrl
;
974 u32 cpu_based_exec_ctrl
;
975 u32 cpu_based_2nd_exec_ctrl
;
980 static struct vmx_capability
{
985 #define VMX_SEGMENT_FIELD(seg) \
986 [VCPU_SREG_##seg] = { \
987 .selector = GUEST_##seg##_SELECTOR, \
988 .base = GUEST_##seg##_BASE, \
989 .limit = GUEST_##seg##_LIMIT, \
990 .ar_bytes = GUEST_##seg##_AR_BYTES, \
993 static const struct kvm_vmx_segment_field
{
998 } kvm_vmx_segment_fields
[] = {
999 VMX_SEGMENT_FIELD(CS
),
1000 VMX_SEGMENT_FIELD(DS
),
1001 VMX_SEGMENT_FIELD(ES
),
1002 VMX_SEGMENT_FIELD(FS
),
1003 VMX_SEGMENT_FIELD(GS
),
1004 VMX_SEGMENT_FIELD(SS
),
1005 VMX_SEGMENT_FIELD(TR
),
1006 VMX_SEGMENT_FIELD(LDTR
),
1009 static u64 host_efer
;
1011 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1014 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1015 * away by decrementing the array size.
1017 static const u32 vmx_msr_index
[] = {
1018 #ifdef CONFIG_X86_64
1019 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1021 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1024 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1026 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1027 INTR_INFO_VALID_MASK
)) ==
1028 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1031 static inline bool is_debug(u32 intr_info
)
1033 return is_exception_n(intr_info
, DB_VECTOR
);
1036 static inline bool is_breakpoint(u32 intr_info
)
1038 return is_exception_n(intr_info
, BP_VECTOR
);
1041 static inline bool is_page_fault(u32 intr_info
)
1043 return is_exception_n(intr_info
, PF_VECTOR
);
1046 static inline bool is_no_device(u32 intr_info
)
1048 return is_exception_n(intr_info
, NM_VECTOR
);
1051 static inline bool is_invalid_opcode(u32 intr_info
)
1053 return is_exception_n(intr_info
, UD_VECTOR
);
1056 static inline bool is_external_interrupt(u32 intr_info
)
1058 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1059 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1062 static inline bool is_machine_check(u32 intr_info
)
1064 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1065 INTR_INFO_VALID_MASK
)) ==
1066 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1069 static inline bool cpu_has_vmx_msr_bitmap(void)
1071 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1074 static inline bool cpu_has_vmx_tpr_shadow(void)
1076 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1079 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1081 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1084 static inline bool cpu_has_secondary_exec_ctrls(void)
1086 return vmcs_config
.cpu_based_exec_ctrl
&
1087 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1090 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1092 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1093 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1096 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1098 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1099 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1102 static inline bool cpu_has_vmx_apic_register_virt(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1108 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1115 * Comment's format: document - errata name - stepping - processor name.
1117 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1119 static u32 vmx_preemption_cpu_tfms
[] = {
1120 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1122 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1123 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1124 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1128 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1129 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1131 * 320767.pdf - AAP86 - B1 -
1132 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1135 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1137 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1139 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1141 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1142 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1143 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1147 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1149 u32 eax
= cpuid_eax(0x00000001), i
;
1151 /* Clear the reserved bits */
1152 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1153 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1154 if (eax
== vmx_preemption_cpu_tfms
[i
])
1160 static inline bool cpu_has_vmx_preemption_timer(void)
1162 return vmcs_config
.pin_based_exec_ctrl
&
1163 PIN_BASED_VMX_PREEMPTION_TIMER
;
1166 static inline bool cpu_has_vmx_posted_intr(void)
1168 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1169 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1172 static inline bool cpu_has_vmx_apicv(void)
1174 return cpu_has_vmx_apic_register_virt() &&
1175 cpu_has_vmx_virtual_intr_delivery() &&
1176 cpu_has_vmx_posted_intr();
1179 static inline bool cpu_has_vmx_flexpriority(void)
1181 return cpu_has_vmx_tpr_shadow() &&
1182 cpu_has_vmx_virtualize_apic_accesses();
1185 static inline bool cpu_has_vmx_ept_execute_only(void)
1187 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1190 static inline bool cpu_has_vmx_ept_2m_page(void)
1192 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1195 static inline bool cpu_has_vmx_ept_1g_page(void)
1197 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1200 static inline bool cpu_has_vmx_ept_4levels(void)
1202 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1205 static inline bool cpu_has_vmx_ept_ad_bits(void)
1207 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1210 static inline bool cpu_has_vmx_invept_context(void)
1212 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1215 static inline bool cpu_has_vmx_invept_global(void)
1217 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1220 static inline bool cpu_has_vmx_invvpid_single(void)
1222 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1225 static inline bool cpu_has_vmx_invvpid_global(void)
1227 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1230 static inline bool cpu_has_vmx_ept(void)
1232 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1233 SECONDARY_EXEC_ENABLE_EPT
;
1236 static inline bool cpu_has_vmx_unrestricted_guest(void)
1238 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1239 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1242 static inline bool cpu_has_vmx_ple(void)
1244 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1245 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1248 static inline bool cpu_has_vmx_basic_inout(void)
1250 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1253 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1255 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1258 static inline bool cpu_has_vmx_vpid(void)
1260 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1261 SECONDARY_EXEC_ENABLE_VPID
;
1264 static inline bool cpu_has_vmx_rdtscp(void)
1266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1267 SECONDARY_EXEC_RDTSCP
;
1270 static inline bool cpu_has_vmx_invpcid(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1273 SECONDARY_EXEC_ENABLE_INVPCID
;
1276 static inline bool cpu_has_virtual_nmis(void)
1278 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1281 static inline bool cpu_has_vmx_wbinvd_exit(void)
1283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1284 SECONDARY_EXEC_WBINVD_EXITING
;
1287 static inline bool cpu_has_vmx_shadow_vmcs(void)
1290 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1291 /* check if the cpu supports writing r/o exit information fields */
1292 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1295 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1296 SECONDARY_EXEC_SHADOW_VMCS
;
1299 static inline bool cpu_has_vmx_pml(void)
1301 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1304 static inline bool cpu_has_vmx_tsc_scaling(void)
1306 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1307 SECONDARY_EXEC_TSC_SCALING
;
1310 static inline bool report_flexpriority(void)
1312 return flexpriority_enabled
;
1315 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1317 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1320 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1322 return (vmcs12
->cpu_based_vm_exec_control
&
1323 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1324 (vmcs12
->secondary_vm_exec_control
& bit
);
1327 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1329 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1332 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1334 return vmcs12
->pin_based_vm_exec_control
&
1335 PIN_BASED_VMX_PREEMPTION_TIMER
;
1338 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1340 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1343 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1345 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1346 vmx_xsaves_supported();
1349 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1351 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1354 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1356 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1359 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1361 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1364 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1366 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1369 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1371 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1374 static inline bool is_exception(u32 intr_info
)
1376 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1377 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1380 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1382 unsigned long exit_qualification
);
1383 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1384 struct vmcs12
*vmcs12
,
1385 u32 reason
, unsigned long qualification
);
1387 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1391 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1392 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1397 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1403 } operand
= { vpid
, 0, gva
};
1405 asm volatile (__ex(ASM_VMX_INVVPID
)
1406 /* CF==1 or ZF==1 --> rc = -1 */
1407 "; ja 1f ; ud2 ; 1:"
1408 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1411 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1415 } operand
= {eptp
, gpa
};
1417 asm volatile (__ex(ASM_VMX_INVEPT
)
1418 /* CF==1 or ZF==1 --> rc = -1 */
1419 "; ja 1f ; ud2 ; 1:\n"
1420 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1423 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1427 i
= __find_msr_index(vmx
, msr
);
1429 return &vmx
->guest_msrs
[i
];
1433 static void vmcs_clear(struct vmcs
*vmcs
)
1435 u64 phys_addr
= __pa(vmcs
);
1438 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1439 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1442 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1446 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1448 vmcs_clear(loaded_vmcs
->vmcs
);
1449 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1450 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1451 loaded_vmcs
->cpu
= -1;
1452 loaded_vmcs
->launched
= 0;
1455 static void vmcs_load(struct vmcs
*vmcs
)
1457 u64 phys_addr
= __pa(vmcs
);
1460 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1461 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1464 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1468 #ifdef CONFIG_KEXEC_CORE
1470 * This bitmap is used to indicate whether the vmclear
1471 * operation is enabled on all cpus. All disabled by
1474 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1476 static inline void crash_enable_local_vmclear(int cpu
)
1478 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1481 static inline void crash_disable_local_vmclear(int cpu
)
1483 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1486 static inline int crash_local_vmclear_enabled(int cpu
)
1488 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1491 static void crash_vmclear_local_loaded_vmcss(void)
1493 int cpu
= raw_smp_processor_id();
1494 struct loaded_vmcs
*v
;
1496 if (!crash_local_vmclear_enabled(cpu
))
1499 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1500 loaded_vmcss_on_cpu_link
)
1501 vmcs_clear(v
->vmcs
);
1504 static inline void crash_enable_local_vmclear(int cpu
) { }
1505 static inline void crash_disable_local_vmclear(int cpu
) { }
1506 #endif /* CONFIG_KEXEC_CORE */
1508 static void __loaded_vmcs_clear(void *arg
)
1510 struct loaded_vmcs
*loaded_vmcs
= arg
;
1511 int cpu
= raw_smp_processor_id();
1513 if (loaded_vmcs
->cpu
!= cpu
)
1514 return; /* vcpu migration can race with cpu offline */
1515 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1516 per_cpu(current_vmcs
, cpu
) = NULL
;
1517 crash_disable_local_vmclear(cpu
);
1518 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1521 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1522 * is before setting loaded_vmcs->vcpu to -1 which is done in
1523 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1524 * then adds the vmcs into percpu list before it is deleted.
1528 loaded_vmcs_init(loaded_vmcs
);
1529 crash_enable_local_vmclear(cpu
);
1532 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1534 int cpu
= loaded_vmcs
->cpu
;
1537 smp_call_function_single(cpu
,
1538 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1541 static inline void vpid_sync_vcpu_single(int vpid
)
1546 if (cpu_has_vmx_invvpid_single())
1547 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1550 static inline void vpid_sync_vcpu_global(void)
1552 if (cpu_has_vmx_invvpid_global())
1553 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1556 static inline void vpid_sync_context(int vpid
)
1558 if (cpu_has_vmx_invvpid_single())
1559 vpid_sync_vcpu_single(vpid
);
1561 vpid_sync_vcpu_global();
1564 static inline void ept_sync_global(void)
1566 if (cpu_has_vmx_invept_global())
1567 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1570 static inline void ept_sync_context(u64 eptp
)
1573 if (cpu_has_vmx_invept_context())
1574 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1580 static __always_inline
void vmcs_check16(unsigned long field
)
1582 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1583 "16-bit accessor invalid for 64-bit field");
1584 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1585 "16-bit accessor invalid for 64-bit high field");
1586 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1587 "16-bit accessor invalid for 32-bit high field");
1588 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1589 "16-bit accessor invalid for natural width field");
1592 static __always_inline
void vmcs_check32(unsigned long field
)
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1595 "32-bit accessor invalid for 16-bit field");
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1597 "32-bit accessor invalid for natural width field");
1600 static __always_inline
void vmcs_check64(unsigned long field
)
1602 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1603 "64-bit accessor invalid for 16-bit field");
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1605 "64-bit accessor invalid for 64-bit high field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1607 "64-bit accessor invalid for 32-bit field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1609 "64-bit accessor invalid for natural width field");
1612 static __always_inline
void vmcs_checkl(unsigned long field
)
1614 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1615 "Natural width accessor invalid for 16-bit field");
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1617 "Natural width accessor invalid for 64-bit field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1619 "Natural width accessor invalid for 64-bit high field");
1620 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1621 "Natural width accessor invalid for 32-bit field");
1624 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1626 unsigned long value
;
1628 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1629 : "=a"(value
) : "d"(field
) : "cc");
1633 static __always_inline u16
vmcs_read16(unsigned long field
)
1635 vmcs_check16(field
);
1636 return __vmcs_readl(field
);
1639 static __always_inline u32
vmcs_read32(unsigned long field
)
1641 vmcs_check32(field
);
1642 return __vmcs_readl(field
);
1645 static __always_inline u64
vmcs_read64(unsigned long field
)
1647 vmcs_check64(field
);
1648 #ifdef CONFIG_X86_64
1649 return __vmcs_readl(field
);
1651 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1655 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1658 return __vmcs_readl(field
);
1661 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1663 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1664 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1668 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1672 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1673 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1674 if (unlikely(error
))
1675 vmwrite_error(field
, value
);
1678 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1680 vmcs_check16(field
);
1681 __vmcs_writel(field
, value
);
1684 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1686 vmcs_check32(field
);
1687 __vmcs_writel(field
, value
);
1690 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1692 vmcs_check64(field
);
1693 __vmcs_writel(field
, value
);
1694 #ifndef CONFIG_X86_64
1696 __vmcs_writel(field
+1, value
>> 32);
1700 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1703 __vmcs_writel(field
, value
);
1706 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1708 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1709 "vmcs_clear_bits does not support 64-bit fields");
1710 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1713 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1715 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1716 "vmcs_set_bits does not support 64-bit fields");
1717 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1720 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1722 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1725 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1727 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1728 vmx
->vm_entry_controls_shadow
= val
;
1731 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1733 if (vmx
->vm_entry_controls_shadow
!= val
)
1734 vm_entry_controls_init(vmx
, val
);
1737 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1739 return vmx
->vm_entry_controls_shadow
;
1743 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1745 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1748 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1750 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1753 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1755 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1758 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1760 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1761 vmx
->vm_exit_controls_shadow
= val
;
1764 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1766 if (vmx
->vm_exit_controls_shadow
!= val
)
1767 vm_exit_controls_init(vmx
, val
);
1770 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1772 return vmx
->vm_exit_controls_shadow
;
1776 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1778 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1781 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1783 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1786 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1788 vmx
->segment_cache
.bitmask
= 0;
1791 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1795 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1797 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1798 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1799 vmx
->segment_cache
.bitmask
= 0;
1801 ret
= vmx
->segment_cache
.bitmask
& mask
;
1802 vmx
->segment_cache
.bitmask
|= mask
;
1806 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1808 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1810 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1811 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1815 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1817 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1819 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1820 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1824 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1826 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1828 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1829 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1833 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1835 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1837 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1838 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1842 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1846 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1847 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1848 if ((vcpu
->guest_debug
&
1849 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1850 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1851 eb
|= 1u << BP_VECTOR
;
1852 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1855 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1856 if (vcpu
->fpu_active
)
1857 eb
&= ~(1u << NM_VECTOR
);
1859 /* When we are running a nested L2 guest and L1 specified for it a
1860 * certain exception bitmap, we must trap the same exceptions and pass
1861 * them to L1. When running L2, we will only handle the exceptions
1862 * specified above if L1 did not want them.
1864 if (is_guest_mode(vcpu
))
1865 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1867 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1870 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1871 unsigned long entry
, unsigned long exit
)
1873 vm_entry_controls_clearbit(vmx
, entry
);
1874 vm_exit_controls_clearbit(vmx
, exit
);
1877 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1880 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1884 if (cpu_has_load_ia32_efer
) {
1885 clear_atomic_switch_msr_special(vmx
,
1886 VM_ENTRY_LOAD_IA32_EFER
,
1887 VM_EXIT_LOAD_IA32_EFER
);
1891 case MSR_CORE_PERF_GLOBAL_CTRL
:
1892 if (cpu_has_load_perf_global_ctrl
) {
1893 clear_atomic_switch_msr_special(vmx
,
1894 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1895 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1901 for (i
= 0; i
< m
->nr
; ++i
)
1902 if (m
->guest
[i
].index
== msr
)
1908 m
->guest
[i
] = m
->guest
[m
->nr
];
1909 m
->host
[i
] = m
->host
[m
->nr
];
1910 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1911 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1914 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1915 unsigned long entry
, unsigned long exit
,
1916 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1917 u64 guest_val
, u64 host_val
)
1919 vmcs_write64(guest_val_vmcs
, guest_val
);
1920 vmcs_write64(host_val_vmcs
, host_val
);
1921 vm_entry_controls_setbit(vmx
, entry
);
1922 vm_exit_controls_setbit(vmx
, exit
);
1925 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1926 u64 guest_val
, u64 host_val
)
1929 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1933 if (cpu_has_load_ia32_efer
) {
1934 add_atomic_switch_msr_special(vmx
,
1935 VM_ENTRY_LOAD_IA32_EFER
,
1936 VM_EXIT_LOAD_IA32_EFER
,
1939 guest_val
, host_val
);
1943 case MSR_CORE_PERF_GLOBAL_CTRL
:
1944 if (cpu_has_load_perf_global_ctrl
) {
1945 add_atomic_switch_msr_special(vmx
,
1946 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1947 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1948 GUEST_IA32_PERF_GLOBAL_CTRL
,
1949 HOST_IA32_PERF_GLOBAL_CTRL
,
1950 guest_val
, host_val
);
1954 case MSR_IA32_PEBS_ENABLE
:
1955 /* PEBS needs a quiescent period after being disabled (to write
1956 * a record). Disabling PEBS through VMX MSR swapping doesn't
1957 * provide that period, so a CPU could write host's record into
1960 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1963 for (i
= 0; i
< m
->nr
; ++i
)
1964 if (m
->guest
[i
].index
== msr
)
1967 if (i
== NR_AUTOLOAD_MSRS
) {
1968 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1969 "Can't add msr %x\n", msr
);
1971 } else if (i
== m
->nr
) {
1973 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1974 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1977 m
->guest
[i
].index
= msr
;
1978 m
->guest
[i
].value
= guest_val
;
1979 m
->host
[i
].index
= msr
;
1980 m
->host
[i
].value
= host_val
;
1983 static void reload_tss(void)
1986 * VT restores TR but not its size. Useless.
1988 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1989 struct desc_struct
*descs
;
1991 descs
= (void *)gdt
->address
;
1992 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1996 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1998 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1999 u64 ignore_bits
= 0;
2003 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2004 * host CPUID is more efficient than testing guest CPUID
2005 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2007 if (boot_cpu_has(X86_FEATURE_SMEP
))
2008 guest_efer
|= EFER_NX
;
2009 else if (!(guest_efer
& EFER_NX
))
2010 ignore_bits
|= EFER_NX
;
2014 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2016 ignore_bits
|= EFER_SCE
;
2017 #ifdef CONFIG_X86_64
2018 ignore_bits
|= EFER_LMA
| EFER_LME
;
2019 /* SCE is meaningful only in long mode on Intel */
2020 if (guest_efer
& EFER_LMA
)
2021 ignore_bits
&= ~(u64
)EFER_SCE
;
2024 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2027 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2028 * On CPUs that support "load IA32_EFER", always switch EFER
2029 * atomically, since it's faster than switching it manually.
2031 if (cpu_has_load_ia32_efer
||
2032 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2033 if (!(guest_efer
& EFER_LMA
))
2034 guest_efer
&= ~EFER_LME
;
2035 if (guest_efer
!= host_efer
)
2036 add_atomic_switch_msr(vmx
, MSR_EFER
,
2037 guest_efer
, host_efer
);
2040 guest_efer
&= ~ignore_bits
;
2041 guest_efer
|= host_efer
& ignore_bits
;
2043 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2044 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2050 static unsigned long segment_base(u16 selector
)
2052 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2053 struct desc_struct
*d
;
2054 unsigned long table_base
;
2057 if (!(selector
& ~3))
2060 table_base
= gdt
->address
;
2062 if (selector
& 4) { /* from ldt */
2063 u16 ldt_selector
= kvm_read_ldt();
2065 if (!(ldt_selector
& ~3))
2068 table_base
= segment_base(ldt_selector
);
2070 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
2071 v
= get_desc_base(d
);
2072 #ifdef CONFIG_X86_64
2073 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
2074 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
2079 static inline unsigned long kvm_read_tr_base(void)
2082 asm("str %0" : "=g"(tr
));
2083 return segment_base(tr
);
2086 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2091 if (vmx
->host_state
.loaded
)
2094 vmx
->host_state
.loaded
= 1;
2096 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2097 * allow segment selectors with cpl > 0 or ti == 1.
2099 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2100 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2101 savesegment(fs
, vmx
->host_state
.fs_sel
);
2102 if (!(vmx
->host_state
.fs_sel
& 7)) {
2103 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2104 vmx
->host_state
.fs_reload_needed
= 0;
2106 vmcs_write16(HOST_FS_SELECTOR
, 0);
2107 vmx
->host_state
.fs_reload_needed
= 1;
2109 savesegment(gs
, vmx
->host_state
.gs_sel
);
2110 if (!(vmx
->host_state
.gs_sel
& 7))
2111 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2113 vmcs_write16(HOST_GS_SELECTOR
, 0);
2114 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2117 #ifdef CONFIG_X86_64
2118 savesegment(ds
, vmx
->host_state
.ds_sel
);
2119 savesegment(es
, vmx
->host_state
.es_sel
);
2122 #ifdef CONFIG_X86_64
2123 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2124 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2126 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2127 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2130 #ifdef CONFIG_X86_64
2131 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2132 if (is_long_mode(&vmx
->vcpu
))
2133 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2135 if (boot_cpu_has(X86_FEATURE_MPX
))
2136 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2137 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2138 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2139 vmx
->guest_msrs
[i
].data
,
2140 vmx
->guest_msrs
[i
].mask
);
2143 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2145 if (!vmx
->host_state
.loaded
)
2148 ++vmx
->vcpu
.stat
.host_state_reload
;
2149 vmx
->host_state
.loaded
= 0;
2150 #ifdef CONFIG_X86_64
2151 if (is_long_mode(&vmx
->vcpu
))
2152 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2154 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2155 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2156 #ifdef CONFIG_X86_64
2157 load_gs_index(vmx
->host_state
.gs_sel
);
2159 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2162 if (vmx
->host_state
.fs_reload_needed
)
2163 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2164 #ifdef CONFIG_X86_64
2165 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2166 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2167 loadsegment(es
, vmx
->host_state
.es_sel
);
2171 #ifdef CONFIG_X86_64
2172 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2174 if (vmx
->host_state
.msr_host_bndcfgs
)
2175 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2177 * If the FPU is not active (through the host task or
2178 * the guest vcpu), then restore the cr0.TS bit.
2180 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2182 load_gdt(this_cpu_ptr(&host_gdt
));
2185 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2188 __vmx_load_host_state(vmx
);
2192 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2194 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2195 struct pi_desc old
, new;
2198 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2199 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2200 !kvm_vcpu_apicv_active(vcpu
))
2204 old
.control
= new.control
= pi_desc
->control
;
2207 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2208 * are two possible cases:
2209 * 1. After running 'pre_block', context switch
2210 * happened. For this case, 'sn' was set in
2211 * vmx_vcpu_put(), so we need to clear it here.
2212 * 2. After running 'pre_block', we were blocked,
2213 * and woken up by some other guy. For this case,
2214 * we don't need to do anything, 'pi_post_block'
2215 * will do everything for us. However, we cannot
2216 * check whether it is case #1 or case #2 here
2217 * (maybe, not needed), so we also clear sn here,
2218 * I think it is not a big deal.
2220 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2221 if (vcpu
->cpu
!= cpu
) {
2222 dest
= cpu_physical_id(cpu
);
2224 if (x2apic_enabled())
2227 new.ndst
= (dest
<< 8) & 0xFF00;
2230 /* set 'NV' to 'notification vector' */
2231 new.nv
= POSTED_INTR_VECTOR
;
2234 /* Allow posting non-urgent interrupts */
2236 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2237 new.control
) != old
.control
);
2240 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2242 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2243 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2247 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2248 * vcpu mutex is already taken.
2250 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2252 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2253 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2254 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2257 kvm_cpu_vmxon(phys_addr
);
2258 else if (!already_loaded
)
2259 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2261 if (!already_loaded
) {
2262 local_irq_disable();
2263 crash_disable_local_vmclear(cpu
);
2266 * Read loaded_vmcs->cpu should be before fetching
2267 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2268 * See the comments in __loaded_vmcs_clear().
2272 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2273 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2274 crash_enable_local_vmclear(cpu
);
2278 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2279 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2280 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2283 if (!already_loaded
) {
2284 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2285 unsigned long sysenter_esp
;
2287 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2290 * Linux uses per-cpu TSS and GDT, so set these when switching
2293 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2294 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2296 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2297 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2299 vmx
->loaded_vmcs
->cpu
= cpu
;
2302 /* Setup TSC multiplier */
2303 if (kvm_has_tsc_control
&&
2304 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2305 decache_tsc_multiplier(vmx
);
2307 vmx_vcpu_pi_load(vcpu
, cpu
);
2308 vmx
->host_pkru
= read_pkru();
2311 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2313 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2315 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2316 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2317 !kvm_vcpu_apicv_active(vcpu
))
2320 /* Set SN when the vCPU is preempted */
2321 if (vcpu
->preempted
)
2325 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2327 vmx_vcpu_pi_put(vcpu
);
2329 __vmx_load_host_state(to_vmx(vcpu
));
2330 if (!vmm_exclusive
) {
2331 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2337 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2341 if (vcpu
->fpu_active
)
2343 vcpu
->fpu_active
= 1;
2344 cr0
= vmcs_readl(GUEST_CR0
);
2345 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2346 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2347 vmcs_writel(GUEST_CR0
, cr0
);
2348 update_exception_bitmap(vcpu
);
2349 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2350 if (is_guest_mode(vcpu
))
2351 vcpu
->arch
.cr0_guest_owned_bits
&=
2352 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2353 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2356 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2359 * Return the cr0 value that a nested guest would read. This is a combination
2360 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2361 * its hypervisor (cr0_read_shadow).
2363 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2365 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2366 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2368 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2370 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2371 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2374 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2376 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2377 * set this *before* calling this function.
2379 vmx_decache_cr0_guest_bits(vcpu
);
2380 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2381 update_exception_bitmap(vcpu
);
2382 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2383 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2384 if (is_guest_mode(vcpu
)) {
2386 * L1's specified read shadow might not contain the TS bit,
2387 * so now that we turned on shadowing of this bit, we need to
2388 * set this bit of the shadow. Like in nested_vmx_run we need
2389 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2390 * up-to-date here because we just decached cr0.TS (and we'll
2391 * only update vmcs12->guest_cr0 on nested exit).
2393 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2394 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2395 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2396 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2398 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2401 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2403 unsigned long rflags
, save_rflags
;
2405 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2406 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2407 rflags
= vmcs_readl(GUEST_RFLAGS
);
2408 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2409 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2410 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2411 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2413 to_vmx(vcpu
)->rflags
= rflags
;
2415 return to_vmx(vcpu
)->rflags
;
2418 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2420 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2421 to_vmx(vcpu
)->rflags
= rflags
;
2422 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2423 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2424 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2426 vmcs_writel(GUEST_RFLAGS
, rflags
);
2429 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2431 return to_vmx(vcpu
)->guest_pkru
;
2434 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2436 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2439 if (interruptibility
& GUEST_INTR_STATE_STI
)
2440 ret
|= KVM_X86_SHADOW_INT_STI
;
2441 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2442 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2447 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2449 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2450 u32 interruptibility
= interruptibility_old
;
2452 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2454 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2455 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2456 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2457 interruptibility
|= GUEST_INTR_STATE_STI
;
2459 if ((interruptibility
!= interruptibility_old
))
2460 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2463 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2467 rip
= kvm_rip_read(vcpu
);
2468 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2469 kvm_rip_write(vcpu
, rip
);
2471 /* skipping an emulated instruction also counts */
2472 vmx_set_interrupt_shadow(vcpu
, 0);
2476 * KVM wants to inject page-faults which it got to the guest. This function
2477 * checks whether in a nested guest, we need to inject them to L1 or L2.
2479 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2481 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2483 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2486 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2487 vmcs_read32(VM_EXIT_INTR_INFO
),
2488 vmcs_readl(EXIT_QUALIFICATION
));
2492 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2493 bool has_error_code
, u32 error_code
,
2496 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2497 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2499 if (!reinject
&& is_guest_mode(vcpu
) &&
2500 nested_vmx_check_exception(vcpu
, nr
))
2503 if (has_error_code
) {
2504 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2505 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2508 if (vmx
->rmode
.vm86_active
) {
2510 if (kvm_exception_is_soft(nr
))
2511 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2512 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2513 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2517 if (kvm_exception_is_soft(nr
)) {
2518 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2519 vmx
->vcpu
.arch
.event_exit_inst_len
);
2520 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2522 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2524 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2527 static bool vmx_rdtscp_supported(void)
2529 return cpu_has_vmx_rdtscp();
2532 static bool vmx_invpcid_supported(void)
2534 return cpu_has_vmx_invpcid() && enable_ept
;
2538 * Swap MSR entry in host/guest MSR entry array.
2540 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2542 struct shared_msr_entry tmp
;
2544 tmp
= vmx
->guest_msrs
[to
];
2545 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2546 vmx
->guest_msrs
[from
] = tmp
;
2549 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2551 unsigned long *msr_bitmap
;
2553 if (is_guest_mode(vcpu
))
2554 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2555 else if (cpu_has_secondary_exec_ctrls() &&
2556 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2557 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2558 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2559 if (is_long_mode(vcpu
))
2560 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2562 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2564 if (is_long_mode(vcpu
))
2565 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2567 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2570 if (is_long_mode(vcpu
))
2571 msr_bitmap
= vmx_msr_bitmap_longmode
;
2573 msr_bitmap
= vmx_msr_bitmap_legacy
;
2576 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2580 * Set up the vmcs to automatically save and restore system
2581 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2582 * mode, as fiddling with msrs is very expensive.
2584 static void setup_msrs(struct vcpu_vmx
*vmx
)
2586 int save_nmsrs
, index
;
2589 #ifdef CONFIG_X86_64
2590 if (is_long_mode(&vmx
->vcpu
)) {
2591 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2593 move_msr_up(vmx
, index
, save_nmsrs
++);
2594 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2596 move_msr_up(vmx
, index
, save_nmsrs
++);
2597 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2599 move_msr_up(vmx
, index
, save_nmsrs
++);
2600 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2601 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2602 move_msr_up(vmx
, index
, save_nmsrs
++);
2604 * MSR_STAR is only needed on long mode guests, and only
2605 * if efer.sce is enabled.
2607 index
= __find_msr_index(vmx
, MSR_STAR
);
2608 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2609 move_msr_up(vmx
, index
, save_nmsrs
++);
2612 index
= __find_msr_index(vmx
, MSR_EFER
);
2613 if (index
>= 0 && update_transition_efer(vmx
, index
))
2614 move_msr_up(vmx
, index
, save_nmsrs
++);
2616 vmx
->save_nmsrs
= save_nmsrs
;
2618 if (cpu_has_vmx_msr_bitmap())
2619 vmx_set_msr_bitmap(&vmx
->vcpu
);
2623 * reads and returns guest's timestamp counter "register"
2624 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2625 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2627 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2629 u64 host_tsc
, tsc_offset
;
2632 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2633 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2637 * writes 'offset' into guest's timestamp counter offset register
2639 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2641 if (is_guest_mode(vcpu
)) {
2643 * We're here if L1 chose not to trap WRMSR to TSC. According
2644 * to the spec, this should set L1's TSC; The offset that L1
2645 * set for L2 remains unchanged, and still needs to be added
2646 * to the newly set TSC to get L2's TSC.
2648 struct vmcs12
*vmcs12
;
2649 /* recalculate vmcs02.TSC_OFFSET: */
2650 vmcs12
= get_vmcs12(vcpu
);
2651 vmcs_write64(TSC_OFFSET
, offset
+
2652 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2653 vmcs12
->tsc_offset
: 0));
2655 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2656 vmcs_read64(TSC_OFFSET
), offset
);
2657 vmcs_write64(TSC_OFFSET
, offset
);
2661 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2663 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2664 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2668 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2669 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2670 * all guests if the "nested" module option is off, and can also be disabled
2671 * for a single guest by disabling its VMX cpuid bit.
2673 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2675 return nested
&& guest_cpuid_has_vmx(vcpu
);
2679 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2680 * returned for the various VMX controls MSRs when nested VMX is enabled.
2681 * The same values should also be used to verify that vmcs12 control fields are
2682 * valid during nested entry from L1 to L2.
2683 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2684 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2685 * bit in the high half is on if the corresponding bit in the control field
2686 * may be on. See also vmx_control_verify().
2688 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2691 * Note that as a general rule, the high half of the MSRs (bits in
2692 * the control fields which may be 1) should be initialized by the
2693 * intersection of the underlying hardware's MSR (i.e., features which
2694 * can be supported) and the list of features we want to expose -
2695 * because they are known to be properly supported in our code.
2696 * Also, usually, the low half of the MSRs (bits which must be 1) can
2697 * be set to 0, meaning that L1 may turn off any of these bits. The
2698 * reason is that if one of these bits is necessary, it will appear
2699 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2700 * fields of vmcs01 and vmcs02, will turn these bits off - and
2701 * nested_vmx_exit_handled() will not pass related exits to L1.
2702 * These rules have exceptions below.
2705 /* pin-based controls */
2706 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2707 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2708 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2709 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2710 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2711 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2712 PIN_BASED_EXT_INTR_MASK
|
2713 PIN_BASED_NMI_EXITING
|
2714 PIN_BASED_VIRTUAL_NMIS
;
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2716 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2717 PIN_BASED_VMX_PREEMPTION_TIMER
;
2718 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2720 PIN_BASED_POSTED_INTR
;
2723 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2724 vmx
->nested
.nested_vmx_exit_ctls_low
,
2725 vmx
->nested
.nested_vmx_exit_ctls_high
);
2726 vmx
->nested
.nested_vmx_exit_ctls_low
=
2727 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2729 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2730 #ifdef CONFIG_X86_64
2731 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2733 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2734 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2735 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2736 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2737 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2739 if (kvm_mpx_supported())
2740 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2742 /* We support free control of debug control saving. */
2743 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2744 vmx
->nested
.nested_vmx_exit_ctls_low
&
2745 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2747 /* entry controls */
2748 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2749 vmx
->nested
.nested_vmx_entry_ctls_low
,
2750 vmx
->nested
.nested_vmx_entry_ctls_high
);
2751 vmx
->nested
.nested_vmx_entry_ctls_low
=
2752 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2753 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2754 #ifdef CONFIG_X86_64
2755 VM_ENTRY_IA32E_MODE
|
2757 VM_ENTRY_LOAD_IA32_PAT
;
2758 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2759 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2760 if (kvm_mpx_supported())
2761 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2763 /* We support free control of debug control loading. */
2764 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2765 vmx
->nested
.nested_vmx_entry_ctls_low
&
2766 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2768 /* cpu-based controls */
2769 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2772 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2773 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2775 CPU_BASED_VIRTUAL_INTR_PENDING
|
2776 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2777 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2778 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 #ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2784 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2785 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2786 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2787 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2789 * We can allow some features even when not supported by the
2790 * hardware. For example, L1 can specify an MSR bitmap - and we
2791 * can use it to avoid exits to L1 - even when L0 runs L2
2792 * without MSR bitmaps.
2794 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2795 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2796 CPU_BASED_USE_MSR_BITMAPS
;
2798 /* We support free control of CR3 access interception. */
2799 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2800 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2801 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2803 /* secondary cpu-based controls */
2804 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2805 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2806 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2809 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2810 SECONDARY_EXEC_RDTSCP
|
2811 SECONDARY_EXEC_DESC
|
2812 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2813 SECONDARY_EXEC_ENABLE_VPID
|
2814 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2816 SECONDARY_EXEC_WBINVD_EXITING
|
2817 SECONDARY_EXEC_XSAVES
;
2820 /* nested EPT: emulate EPT also to L1 */
2821 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2822 SECONDARY_EXEC_ENABLE_EPT
;
2823 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2824 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2826 if (cpu_has_vmx_ept_execute_only())
2827 vmx
->nested
.nested_vmx_ept_caps
|=
2828 VMX_EPT_EXECUTE_ONLY_BIT
;
2829 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2830 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2831 VMX_EPT_EXTENT_CONTEXT_BIT
;
2833 vmx
->nested
.nested_vmx_ept_caps
= 0;
2836 * Old versions of KVM use the single-context version without
2837 * checking for support, so declare that it is supported even
2838 * though it is treated as global context. The alternative is
2839 * not failing the single-context invvpid, and it is worse.
2842 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2843 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2845 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2847 if (enable_unrestricted_guest
)
2848 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2849 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2851 /* miscellaneous data */
2852 rdmsr(MSR_IA32_VMX_MISC
,
2853 vmx
->nested
.nested_vmx_misc_low
,
2854 vmx
->nested
.nested_vmx_misc_high
);
2855 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2856 vmx
->nested
.nested_vmx_misc_low
|=
2857 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2858 VMX_MISC_ACTIVITY_HLT
;
2859 vmx
->nested
.nested_vmx_misc_high
= 0;
2862 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2865 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2867 return ((control
& high
) | low
) == control
;
2870 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2872 return low
| ((u64
)high
<< 32);
2875 /* Returns 0 on success, non-0 otherwise. */
2876 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2878 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2880 switch (msr_index
) {
2881 case MSR_IA32_VMX_BASIC
:
2883 * This MSR reports some information about VMX support. We
2884 * should return information about the VMX we emulate for the
2885 * guest, and the VMCS structure we give it - not about the
2886 * VMX support of the underlying hardware.
2888 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2889 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2890 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2891 if (cpu_has_vmx_basic_inout())
2892 *pdata
|= VMX_BASIC_INOUT
;
2894 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2895 case MSR_IA32_VMX_PINBASED_CTLS
:
2896 *pdata
= vmx_control_msr(
2897 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2898 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2900 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2901 *pdata
= vmx_control_msr(
2902 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2903 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2905 case MSR_IA32_VMX_PROCBASED_CTLS
:
2906 *pdata
= vmx_control_msr(
2907 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2908 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2910 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2911 *pdata
= vmx_control_msr(
2912 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2913 vmx
->nested
.nested_vmx_exit_ctls_high
);
2915 case MSR_IA32_VMX_EXIT_CTLS
:
2916 *pdata
= vmx_control_msr(
2917 vmx
->nested
.nested_vmx_exit_ctls_low
,
2918 vmx
->nested
.nested_vmx_exit_ctls_high
);
2920 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2921 *pdata
= vmx_control_msr(
2922 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2923 vmx
->nested
.nested_vmx_entry_ctls_high
);
2925 case MSR_IA32_VMX_ENTRY_CTLS
:
2926 *pdata
= vmx_control_msr(
2927 vmx
->nested
.nested_vmx_entry_ctls_low
,
2928 vmx
->nested
.nested_vmx_entry_ctls_high
);
2930 case MSR_IA32_VMX_MISC
:
2931 *pdata
= vmx_control_msr(
2932 vmx
->nested
.nested_vmx_misc_low
,
2933 vmx
->nested
.nested_vmx_misc_high
);
2936 * These MSRs specify bits which the guest must keep fixed (on or off)
2937 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2938 * We picked the standard core2 setting.
2940 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2941 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2942 case MSR_IA32_VMX_CR0_FIXED0
:
2943 *pdata
= VMXON_CR0_ALWAYSON
;
2945 case MSR_IA32_VMX_CR0_FIXED1
:
2948 case MSR_IA32_VMX_CR4_FIXED0
:
2949 *pdata
= VMXON_CR4_ALWAYSON
;
2951 case MSR_IA32_VMX_CR4_FIXED1
:
2954 case MSR_IA32_VMX_VMCS_ENUM
:
2955 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2957 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2958 *pdata
= vmx_control_msr(
2959 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2960 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2962 case MSR_IA32_VMX_EPT_VPID_CAP
:
2963 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2964 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2973 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
2976 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
2978 return !(val
& ~valid_bits
);
2982 * Reads an msr value (of 'msr_index') into 'pdata'.
2983 * Returns 0 on success, non-0 otherwise.
2984 * Assumes vcpu_load() was already called.
2986 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2988 struct shared_msr_entry
*msr
;
2990 switch (msr_info
->index
) {
2991 #ifdef CONFIG_X86_64
2993 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2996 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2998 case MSR_KERNEL_GS_BASE
:
2999 vmx_load_host_state(to_vmx(vcpu
));
3000 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3004 return kvm_get_msr_common(vcpu
, msr_info
);
3006 msr_info
->data
= guest_read_tsc(vcpu
);
3008 case MSR_IA32_SYSENTER_CS
:
3009 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3011 case MSR_IA32_SYSENTER_EIP
:
3012 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3014 case MSR_IA32_SYSENTER_ESP
:
3015 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3017 case MSR_IA32_BNDCFGS
:
3018 if (!kvm_mpx_supported())
3020 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3022 case MSR_IA32_MCG_EXT_CTL
:
3023 if (!msr_info
->host_initiated
&&
3024 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3025 FEATURE_CONTROL_LMCE
))
3027 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3029 case MSR_IA32_FEATURE_CONTROL
:
3030 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3032 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3033 if (!nested_vmx_allowed(vcpu
))
3035 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3037 if (!vmx_xsaves_supported())
3039 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3042 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3044 /* Otherwise falls through */
3046 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3048 msr_info
->data
= msr
->data
;
3051 return kvm_get_msr_common(vcpu
, msr_info
);
3057 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3060 * Writes msr value into into the appropriate "register".
3061 * Returns 0 on success, non-0 otherwise.
3062 * Assumes vcpu_load() was already called.
3064 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3067 struct shared_msr_entry
*msr
;
3069 u32 msr_index
= msr_info
->index
;
3070 u64 data
= msr_info
->data
;
3072 switch (msr_index
) {
3074 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3076 #ifdef CONFIG_X86_64
3078 vmx_segment_cache_clear(vmx
);
3079 vmcs_writel(GUEST_FS_BASE
, data
);
3082 vmx_segment_cache_clear(vmx
);
3083 vmcs_writel(GUEST_GS_BASE
, data
);
3085 case MSR_KERNEL_GS_BASE
:
3086 vmx_load_host_state(vmx
);
3087 vmx
->msr_guest_kernel_gs_base
= data
;
3090 case MSR_IA32_SYSENTER_CS
:
3091 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3093 case MSR_IA32_SYSENTER_EIP
:
3094 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3096 case MSR_IA32_SYSENTER_ESP
:
3097 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3099 case MSR_IA32_BNDCFGS
:
3100 if (!kvm_mpx_supported())
3102 vmcs_write64(GUEST_BNDCFGS
, data
);
3105 kvm_write_tsc(vcpu
, msr_info
);
3107 case MSR_IA32_CR_PAT
:
3108 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3109 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3111 vmcs_write64(GUEST_IA32_PAT
, data
);
3112 vcpu
->arch
.pat
= data
;
3115 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3117 case MSR_IA32_TSC_ADJUST
:
3118 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3120 case MSR_IA32_MCG_EXT_CTL
:
3121 if ((!msr_info
->host_initiated
&&
3122 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3123 FEATURE_CONTROL_LMCE
)) ||
3124 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3126 vcpu
->arch
.mcg_ext_ctl
= data
;
3128 case MSR_IA32_FEATURE_CONTROL
:
3129 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3130 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3131 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3133 vmx
->msr_ia32_feature_control
= data
;
3134 if (msr_info
->host_initiated
&& data
== 0)
3135 vmx_leave_nested(vcpu
);
3137 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3138 return 1; /* they are read-only */
3140 if (!vmx_xsaves_supported())
3143 * The only supported bit as of Skylake is bit 8, but
3144 * it is not supported on KVM.
3148 vcpu
->arch
.ia32_xss
= data
;
3149 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3150 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3151 vcpu
->arch
.ia32_xss
, host_xss
);
3153 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3156 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3158 /* Check reserved bit, higher 32 bits should be zero */
3159 if ((data
>> 32) != 0)
3161 /* Otherwise falls through */
3163 msr
= find_msr_entry(vmx
, msr_index
);
3165 u64 old_msr_data
= msr
->data
;
3167 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3169 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3173 msr
->data
= old_msr_data
;
3177 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3183 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3185 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3188 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3191 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3193 case VCPU_EXREG_PDPTR
:
3195 ept_save_pdptrs(vcpu
);
3202 static __init
int cpu_has_kvm_support(void)
3204 return cpu_has_vmx();
3207 static __init
int vmx_disabled_by_bios(void)
3211 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3212 if (msr
& FEATURE_CONTROL_LOCKED
) {
3213 /* launched w/ TXT and VMX disabled */
3214 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3217 /* launched w/o TXT and VMX only enabled w/ TXT */
3218 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3219 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3220 && !tboot_enabled()) {
3221 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3222 "activate TXT before enabling KVM\n");
3225 /* launched w/o TXT and VMX disabled */
3226 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3227 && !tboot_enabled())
3234 static void kvm_cpu_vmxon(u64 addr
)
3236 intel_pt_handle_vmx(1);
3238 asm volatile (ASM_VMX_VMXON_RAX
3239 : : "a"(&addr
), "m"(addr
)
3243 static int hardware_enable(void)
3245 int cpu
= raw_smp_processor_id();
3246 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3249 if (cr4_read_shadow() & X86_CR4_VMXE
)
3252 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3253 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3254 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3257 * Now we can enable the vmclear operation in kdump
3258 * since the loaded_vmcss_on_cpu list on this cpu
3259 * has been initialized.
3261 * Though the cpu is not in VMX operation now, there
3262 * is no problem to enable the vmclear operation
3263 * for the loaded_vmcss_on_cpu list is empty!
3265 crash_enable_local_vmclear(cpu
);
3267 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3269 test_bits
= FEATURE_CONTROL_LOCKED
;
3270 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3271 if (tboot_enabled())
3272 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3274 if ((old
& test_bits
) != test_bits
) {
3275 /* enable and lock */
3276 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3278 cr4_set_bits(X86_CR4_VMXE
);
3280 if (vmm_exclusive
) {
3281 kvm_cpu_vmxon(phys_addr
);
3285 native_store_gdt(this_cpu_ptr(&host_gdt
));
3290 static void vmclear_local_loaded_vmcss(void)
3292 int cpu
= raw_smp_processor_id();
3293 struct loaded_vmcs
*v
, *n
;
3295 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3296 loaded_vmcss_on_cpu_link
)
3297 __loaded_vmcs_clear(v
);
3301 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3304 static void kvm_cpu_vmxoff(void)
3306 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3308 intel_pt_handle_vmx(0);
3311 static void hardware_disable(void)
3313 if (vmm_exclusive
) {
3314 vmclear_local_loaded_vmcss();
3317 cr4_clear_bits(X86_CR4_VMXE
);
3320 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3321 u32 msr
, u32
*result
)
3323 u32 vmx_msr_low
, vmx_msr_high
;
3324 u32 ctl
= ctl_min
| ctl_opt
;
3326 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3328 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3329 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3331 /* Ensure minimum (required) set of control bits are supported. */
3339 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3341 u32 vmx_msr_low
, vmx_msr_high
;
3343 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3344 return vmx_msr_high
& ctl
;
3347 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3349 u32 vmx_msr_low
, vmx_msr_high
;
3350 u32 min
, opt
, min2
, opt2
;
3351 u32 _pin_based_exec_control
= 0;
3352 u32 _cpu_based_exec_control
= 0;
3353 u32 _cpu_based_2nd_exec_control
= 0;
3354 u32 _vmexit_control
= 0;
3355 u32 _vmentry_control
= 0;
3357 min
= CPU_BASED_HLT_EXITING
|
3358 #ifdef CONFIG_X86_64
3359 CPU_BASED_CR8_LOAD_EXITING
|
3360 CPU_BASED_CR8_STORE_EXITING
|
3362 CPU_BASED_CR3_LOAD_EXITING
|
3363 CPU_BASED_CR3_STORE_EXITING
|
3364 CPU_BASED_USE_IO_BITMAPS
|
3365 CPU_BASED_MOV_DR_EXITING
|
3366 CPU_BASED_USE_TSC_OFFSETING
|
3367 CPU_BASED_MWAIT_EXITING
|
3368 CPU_BASED_MONITOR_EXITING
|
3369 CPU_BASED_INVLPG_EXITING
|
3370 CPU_BASED_RDPMC_EXITING
;
3372 opt
= CPU_BASED_TPR_SHADOW
|
3373 CPU_BASED_USE_MSR_BITMAPS
|
3374 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3375 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3376 &_cpu_based_exec_control
) < 0)
3378 #ifdef CONFIG_X86_64
3379 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3380 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3381 ~CPU_BASED_CR8_STORE_EXITING
;
3383 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3385 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3386 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3387 SECONDARY_EXEC_WBINVD_EXITING
|
3388 SECONDARY_EXEC_ENABLE_VPID
|
3389 SECONDARY_EXEC_ENABLE_EPT
|
3390 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3391 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3392 SECONDARY_EXEC_RDTSCP
|
3393 SECONDARY_EXEC_ENABLE_INVPCID
|
3394 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3395 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3396 SECONDARY_EXEC_SHADOW_VMCS
|
3397 SECONDARY_EXEC_XSAVES
|
3398 SECONDARY_EXEC_ENABLE_PML
|
3399 SECONDARY_EXEC_TSC_SCALING
;
3400 if (adjust_vmx_controls(min2
, opt2
,
3401 MSR_IA32_VMX_PROCBASED_CTLS2
,
3402 &_cpu_based_2nd_exec_control
) < 0)
3405 #ifndef CONFIG_X86_64
3406 if (!(_cpu_based_2nd_exec_control
&
3407 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3408 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3411 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3412 _cpu_based_2nd_exec_control
&= ~(
3413 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3414 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3415 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3417 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3418 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3420 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3421 CPU_BASED_CR3_STORE_EXITING
|
3422 CPU_BASED_INVLPG_EXITING
);
3423 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3424 vmx_capability
.ept
, vmx_capability
.vpid
);
3427 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3428 #ifdef CONFIG_X86_64
3429 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3431 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3432 VM_EXIT_CLEAR_BNDCFGS
;
3433 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3434 &_vmexit_control
) < 0)
3437 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3438 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3439 PIN_BASED_VMX_PREEMPTION_TIMER
;
3440 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3441 &_pin_based_exec_control
) < 0)
3444 if (cpu_has_broken_vmx_preemption_timer())
3445 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3446 if (!(_cpu_based_2nd_exec_control
&
3447 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3448 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3450 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3451 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3452 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3453 &_vmentry_control
) < 0)
3456 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3458 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3459 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3462 #ifdef CONFIG_X86_64
3463 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3464 if (vmx_msr_high
& (1u<<16))
3468 /* Require Write-Back (WB) memory type for VMCS accesses. */
3469 if (((vmx_msr_high
>> 18) & 15) != 6)
3472 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3473 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3474 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3475 vmcs_conf
->revision_id
= vmx_msr_low
;
3477 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3478 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3479 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3480 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3481 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3483 cpu_has_load_ia32_efer
=
3484 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3485 VM_ENTRY_LOAD_IA32_EFER
)
3486 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3487 VM_EXIT_LOAD_IA32_EFER
);
3489 cpu_has_load_perf_global_ctrl
=
3490 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3491 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3492 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3493 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3496 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3497 * but due to errata below it can't be used. Workaround is to use
3498 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3500 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3505 * BC86,AAY89,BD102 (model 44)
3509 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3510 switch (boot_cpu_data
.x86_model
) {
3516 cpu_has_load_perf_global_ctrl
= false;
3517 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3518 "does not work properly. Using workaround\n");
3525 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3526 rdmsrl(MSR_IA32_XSS
, host_xss
);
3531 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3533 int node
= cpu_to_node(cpu
);
3537 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3540 vmcs
= page_address(pages
);
3541 memset(vmcs
, 0, vmcs_config
.size
);
3542 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3546 static struct vmcs
*alloc_vmcs(void)
3548 return alloc_vmcs_cpu(raw_smp_processor_id());
3551 static void free_vmcs(struct vmcs
*vmcs
)
3553 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3557 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3559 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3561 if (!loaded_vmcs
->vmcs
)
3563 loaded_vmcs_clear(loaded_vmcs
);
3564 free_vmcs(loaded_vmcs
->vmcs
);
3565 loaded_vmcs
->vmcs
= NULL
;
3566 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3569 static void free_kvm_area(void)
3573 for_each_possible_cpu(cpu
) {
3574 free_vmcs(per_cpu(vmxarea
, cpu
));
3575 per_cpu(vmxarea
, cpu
) = NULL
;
3579 static void init_vmcs_shadow_fields(void)
3583 /* No checks for read only fields yet */
3585 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3586 switch (shadow_read_write_fields
[i
]) {
3588 if (!kvm_mpx_supported())
3596 shadow_read_write_fields
[j
] =
3597 shadow_read_write_fields
[i
];
3600 max_shadow_read_write_fields
= j
;
3602 /* shadowed fields guest access without vmexit */
3603 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3604 clear_bit(shadow_read_write_fields
[i
],
3605 vmx_vmwrite_bitmap
);
3606 clear_bit(shadow_read_write_fields
[i
],
3609 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3610 clear_bit(shadow_read_only_fields
[i
],
3614 static __init
int alloc_kvm_area(void)
3618 for_each_possible_cpu(cpu
) {
3621 vmcs
= alloc_vmcs_cpu(cpu
);
3627 per_cpu(vmxarea
, cpu
) = vmcs
;
3632 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3634 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3637 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3638 struct kvm_segment
*save
)
3640 if (!emulate_invalid_guest_state
) {
3642 * CS and SS RPL should be equal during guest entry according
3643 * to VMX spec, but in reality it is not always so. Since vcpu
3644 * is in the middle of the transition from real mode to
3645 * protected mode it is safe to assume that RPL 0 is a good
3648 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3649 save
->selector
&= ~SEGMENT_RPL_MASK
;
3650 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3653 vmx_set_segment(vcpu
, save
, seg
);
3656 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3658 unsigned long flags
;
3659 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3662 * Update real mode segment cache. It may be not up-to-date if sement
3663 * register was written while vcpu was in a guest mode.
3665 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3666 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3667 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3668 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3669 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3670 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3672 vmx
->rmode
.vm86_active
= 0;
3674 vmx_segment_cache_clear(vmx
);
3676 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3678 flags
= vmcs_readl(GUEST_RFLAGS
);
3679 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3680 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3681 vmcs_writel(GUEST_RFLAGS
, flags
);
3683 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3684 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3686 update_exception_bitmap(vcpu
);
3688 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3689 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3690 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3691 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3692 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3693 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3696 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3698 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3699 struct kvm_segment var
= *save
;
3702 if (seg
== VCPU_SREG_CS
)
3705 if (!emulate_invalid_guest_state
) {
3706 var
.selector
= var
.base
>> 4;
3707 var
.base
= var
.base
& 0xffff0;
3717 if (save
->base
& 0xf)
3718 printk_once(KERN_WARNING
"kvm: segment base is not "
3719 "paragraph aligned when entering "
3720 "protected mode (seg=%d)", seg
);
3723 vmcs_write16(sf
->selector
, var
.selector
);
3724 vmcs_write32(sf
->base
, var
.base
);
3725 vmcs_write32(sf
->limit
, var
.limit
);
3726 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3729 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3731 unsigned long flags
;
3732 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3734 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3735 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3736 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3737 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3738 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3739 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3740 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3742 vmx
->rmode
.vm86_active
= 1;
3745 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3746 * vcpu. Warn the user that an update is overdue.
3748 if (!vcpu
->kvm
->arch
.tss_addr
)
3749 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3750 "called before entering vcpu\n");
3752 vmx_segment_cache_clear(vmx
);
3754 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3755 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3756 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3758 flags
= vmcs_readl(GUEST_RFLAGS
);
3759 vmx
->rmode
.save_rflags
= flags
;
3761 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3763 vmcs_writel(GUEST_RFLAGS
, flags
);
3764 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3765 update_exception_bitmap(vcpu
);
3767 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3768 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3769 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3770 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3771 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3772 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3774 kvm_mmu_reset_context(vcpu
);
3777 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3779 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3780 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3786 * Force kernel_gs_base reloading before EFER changes, as control
3787 * of this msr depends on is_long_mode().
3789 vmx_load_host_state(to_vmx(vcpu
));
3790 vcpu
->arch
.efer
= efer
;
3791 if (efer
& EFER_LMA
) {
3792 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3795 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3797 msr
->data
= efer
& ~EFER_LME
;
3802 #ifdef CONFIG_X86_64
3804 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3808 vmx_segment_cache_clear(to_vmx(vcpu
));
3810 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3811 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3812 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3814 vmcs_write32(GUEST_TR_AR_BYTES
,
3815 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3816 | VMX_AR_TYPE_BUSY_64_TSS
);
3818 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3821 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3823 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3824 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3829 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3831 vpid_sync_context(vpid
);
3833 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3835 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3839 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3841 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3844 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3846 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3848 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3849 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3852 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3854 if (enable_ept
&& is_paging(vcpu
))
3855 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3856 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3859 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3861 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3863 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3864 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3867 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3869 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3871 if (!test_bit(VCPU_EXREG_PDPTR
,
3872 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3875 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3876 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3877 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3878 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3879 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3883 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3885 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3887 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3888 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3889 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3890 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3891 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3894 __set_bit(VCPU_EXREG_PDPTR
,
3895 (unsigned long *)&vcpu
->arch
.regs_avail
);
3896 __set_bit(VCPU_EXREG_PDPTR
,
3897 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3900 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3902 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3904 struct kvm_vcpu
*vcpu
)
3906 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3907 vmx_decache_cr3(vcpu
);
3908 if (!(cr0
& X86_CR0_PG
)) {
3909 /* From paging/starting to nonpaging */
3910 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3911 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3912 (CPU_BASED_CR3_LOAD_EXITING
|
3913 CPU_BASED_CR3_STORE_EXITING
));
3914 vcpu
->arch
.cr0
= cr0
;
3915 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3916 } else if (!is_paging(vcpu
)) {
3917 /* From nonpaging to paging */
3918 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3919 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3920 ~(CPU_BASED_CR3_LOAD_EXITING
|
3921 CPU_BASED_CR3_STORE_EXITING
));
3922 vcpu
->arch
.cr0
= cr0
;
3923 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3926 if (!(cr0
& X86_CR0_WP
))
3927 *hw_cr0
&= ~X86_CR0_WP
;
3930 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3932 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3933 unsigned long hw_cr0
;
3935 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3936 if (enable_unrestricted_guest
)
3937 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3939 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3941 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3944 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3948 #ifdef CONFIG_X86_64
3949 if (vcpu
->arch
.efer
& EFER_LME
) {
3950 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3952 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3958 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3960 if (!vcpu
->fpu_active
)
3961 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3963 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3964 vmcs_writel(GUEST_CR0
, hw_cr0
);
3965 vcpu
->arch
.cr0
= cr0
;
3967 /* depends on vcpu->arch.cr0 to be set to a new value */
3968 vmx
->emulation_required
= emulation_required(vcpu
);
3971 static u64
construct_eptp(unsigned long root_hpa
)
3975 /* TODO write the value reading from MSR */
3976 eptp
= VMX_EPT_DEFAULT_MT
|
3977 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3978 if (enable_ept_ad_bits
)
3979 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3980 eptp
|= (root_hpa
& PAGE_MASK
);
3985 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3987 unsigned long guest_cr3
;
3992 eptp
= construct_eptp(cr3
);
3993 vmcs_write64(EPT_POINTER
, eptp
);
3994 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3995 guest_cr3
= kvm_read_cr3(vcpu
);
3997 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3998 ept_load_pdptrs(vcpu
);
4001 vmx_flush_tlb(vcpu
);
4002 vmcs_writel(GUEST_CR3
, guest_cr3
);
4005 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4008 * Pass through host's Machine Check Enable value to hw_cr4, which
4009 * is in force while we are in guest mode. Do not let guests control
4010 * this bit, even if host CR4.MCE == 0.
4012 unsigned long hw_cr4
=
4013 (cr4_read_shadow() & X86_CR4_MCE
) |
4014 (cr4
& ~X86_CR4_MCE
) |
4015 (to_vmx(vcpu
)->rmode
.vm86_active
?
4016 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4018 if (cr4
& X86_CR4_VMXE
) {
4020 * To use VMXON (and later other VMX instructions), a guest
4021 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4022 * So basically the check on whether to allow nested VMX
4025 if (!nested_vmx_allowed(vcpu
))
4028 if (to_vmx(vcpu
)->nested
.vmxon
&&
4029 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
4032 vcpu
->arch
.cr4
= cr4
;
4034 if (!is_paging(vcpu
)) {
4035 hw_cr4
&= ~X86_CR4_PAE
;
4036 hw_cr4
|= X86_CR4_PSE
;
4037 } else if (!(cr4
& X86_CR4_PAE
)) {
4038 hw_cr4
&= ~X86_CR4_PAE
;
4042 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4044 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4045 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4046 * to be manually disabled when guest switches to non-paging
4049 * If !enable_unrestricted_guest, the CPU is always running
4050 * with CR0.PG=1 and CR4 needs to be modified.
4051 * If enable_unrestricted_guest, the CPU automatically
4052 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4054 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4056 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4057 vmcs_writel(GUEST_CR4
, hw_cr4
);
4061 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4062 struct kvm_segment
*var
, int seg
)
4064 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4067 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4068 *var
= vmx
->rmode
.segs
[seg
];
4069 if (seg
== VCPU_SREG_TR
4070 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4072 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4073 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4076 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4077 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4078 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4079 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4080 var
->unusable
= (ar
>> 16) & 1;
4081 var
->type
= ar
& 15;
4082 var
->s
= (ar
>> 4) & 1;
4083 var
->dpl
= (ar
>> 5) & 3;
4085 * Some userspaces do not preserve unusable property. Since usable
4086 * segment has to be present according to VMX spec we can use present
4087 * property to amend userspace bug by making unusable segment always
4088 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4089 * segment as unusable.
4091 var
->present
= !var
->unusable
;
4092 var
->avl
= (ar
>> 12) & 1;
4093 var
->l
= (ar
>> 13) & 1;
4094 var
->db
= (ar
>> 14) & 1;
4095 var
->g
= (ar
>> 15) & 1;
4098 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4100 struct kvm_segment s
;
4102 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4103 vmx_get_segment(vcpu
, &s
, seg
);
4106 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4109 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4111 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4113 if (unlikely(vmx
->rmode
.vm86_active
))
4116 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4117 return VMX_AR_DPL(ar
);
4121 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4125 if (var
->unusable
|| !var
->present
)
4128 ar
= var
->type
& 15;
4129 ar
|= (var
->s
& 1) << 4;
4130 ar
|= (var
->dpl
& 3) << 5;
4131 ar
|= (var
->present
& 1) << 7;
4132 ar
|= (var
->avl
& 1) << 12;
4133 ar
|= (var
->l
& 1) << 13;
4134 ar
|= (var
->db
& 1) << 14;
4135 ar
|= (var
->g
& 1) << 15;
4141 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4142 struct kvm_segment
*var
, int seg
)
4144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4145 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4147 vmx_segment_cache_clear(vmx
);
4149 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4150 vmx
->rmode
.segs
[seg
] = *var
;
4151 if (seg
== VCPU_SREG_TR
)
4152 vmcs_write16(sf
->selector
, var
->selector
);
4154 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4158 vmcs_writel(sf
->base
, var
->base
);
4159 vmcs_write32(sf
->limit
, var
->limit
);
4160 vmcs_write16(sf
->selector
, var
->selector
);
4163 * Fix the "Accessed" bit in AR field of segment registers for older
4165 * IA32 arch specifies that at the time of processor reset the
4166 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4167 * is setting it to 0 in the userland code. This causes invalid guest
4168 * state vmexit when "unrestricted guest" mode is turned on.
4169 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4170 * tree. Newer qemu binaries with that qemu fix would not need this
4173 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4174 var
->type
|= 0x1; /* Accessed */
4176 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4179 vmx
->emulation_required
= emulation_required(vcpu
);
4182 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4184 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4186 *db
= (ar
>> 14) & 1;
4187 *l
= (ar
>> 13) & 1;
4190 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4192 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4193 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4196 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4198 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4199 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4202 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4204 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4205 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4208 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4210 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4211 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4214 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4216 struct kvm_segment var
;
4219 vmx_get_segment(vcpu
, &var
, seg
);
4221 if (seg
== VCPU_SREG_CS
)
4223 ar
= vmx_segment_access_rights(&var
);
4225 if (var
.base
!= (var
.selector
<< 4))
4227 if (var
.limit
!= 0xffff)
4235 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4237 struct kvm_segment cs
;
4238 unsigned int cs_rpl
;
4240 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4241 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4245 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4249 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4250 if (cs
.dpl
> cs_rpl
)
4253 if (cs
.dpl
!= cs_rpl
)
4259 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4263 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4265 struct kvm_segment ss
;
4266 unsigned int ss_rpl
;
4268 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4269 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4273 if (ss
.type
!= 3 && ss
.type
!= 7)
4277 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4285 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4287 struct kvm_segment var
;
4290 vmx_get_segment(vcpu
, &var
, seg
);
4291 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4299 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4300 if (var
.dpl
< rpl
) /* DPL < RPL */
4304 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4310 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4312 struct kvm_segment tr
;
4314 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4318 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4320 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4328 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4330 struct kvm_segment ldtr
;
4332 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4336 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4346 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4348 struct kvm_segment cs
, ss
;
4350 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4351 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4353 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4354 (ss
.selector
& SEGMENT_RPL_MASK
));
4358 * Check if guest state is valid. Returns true if valid, false if
4360 * We assume that registers are always usable
4362 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4364 if (enable_unrestricted_guest
)
4367 /* real mode guest state checks */
4368 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4369 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4371 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4373 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4375 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4377 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4379 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4382 /* protected mode guest state checks */
4383 if (!cs_ss_rpl_check(vcpu
))
4385 if (!code_segment_valid(vcpu
))
4387 if (!stack_segment_valid(vcpu
))
4389 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4391 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4393 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4395 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4397 if (!tr_valid(vcpu
))
4399 if (!ldtr_valid(vcpu
))
4403 * - Add checks on RIP
4404 * - Add checks on RFLAGS
4410 static int init_rmode_tss(struct kvm
*kvm
)
4416 idx
= srcu_read_lock(&kvm
->srcu
);
4417 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4418 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4421 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4422 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4423 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4426 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4429 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4433 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4434 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4437 srcu_read_unlock(&kvm
->srcu
, idx
);
4441 static int init_rmode_identity_map(struct kvm
*kvm
)
4444 kvm_pfn_t identity_map_pfn
;
4450 /* Protect kvm->arch.ept_identity_pagetable_done. */
4451 mutex_lock(&kvm
->slots_lock
);
4453 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4456 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4458 r
= alloc_identity_pagetable(kvm
);
4462 idx
= srcu_read_lock(&kvm
->srcu
);
4463 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4466 /* Set up identity-mapping pagetable for EPT in real mode */
4467 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4468 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4469 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4470 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4471 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4475 kvm
->arch
.ept_identity_pagetable_done
= true;
4478 srcu_read_unlock(&kvm
->srcu
, idx
);
4481 mutex_unlock(&kvm
->slots_lock
);
4485 static void seg_setup(int seg
)
4487 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4490 vmcs_write16(sf
->selector
, 0);
4491 vmcs_writel(sf
->base
, 0);
4492 vmcs_write32(sf
->limit
, 0xffff);
4494 if (seg
== VCPU_SREG_CS
)
4495 ar
|= 0x08; /* code segment */
4497 vmcs_write32(sf
->ar_bytes
, ar
);
4500 static int alloc_apic_access_page(struct kvm
*kvm
)
4505 mutex_lock(&kvm
->slots_lock
);
4506 if (kvm
->arch
.apic_access_page_done
)
4508 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4509 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4513 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4514 if (is_error_page(page
)) {
4520 * Do not pin the page in memory, so that memory hot-unplug
4521 * is able to migrate it.
4524 kvm
->arch
.apic_access_page_done
= true;
4526 mutex_unlock(&kvm
->slots_lock
);
4530 static int alloc_identity_pagetable(struct kvm
*kvm
)
4532 /* Called with kvm->slots_lock held. */
4536 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4538 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4539 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4544 static int allocate_vpid(void)
4550 spin_lock(&vmx_vpid_lock
);
4551 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4552 if (vpid
< VMX_NR_VPIDS
)
4553 __set_bit(vpid
, vmx_vpid_bitmap
);
4556 spin_unlock(&vmx_vpid_lock
);
4560 static void free_vpid(int vpid
)
4562 if (!enable_vpid
|| vpid
== 0)
4564 spin_lock(&vmx_vpid_lock
);
4565 __clear_bit(vpid
, vmx_vpid_bitmap
);
4566 spin_unlock(&vmx_vpid_lock
);
4569 #define MSR_TYPE_R 1
4570 #define MSR_TYPE_W 2
4571 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4574 int f
= sizeof(unsigned long);
4576 if (!cpu_has_vmx_msr_bitmap())
4580 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4581 * have the write-low and read-high bitmap offsets the wrong way round.
4582 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4584 if (msr
<= 0x1fff) {
4585 if (type
& MSR_TYPE_R
)
4587 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4589 if (type
& MSR_TYPE_W
)
4591 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4593 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4595 if (type
& MSR_TYPE_R
)
4597 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4599 if (type
& MSR_TYPE_W
)
4601 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4607 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4608 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4610 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4611 unsigned long *msr_bitmap_nested
,
4614 int f
= sizeof(unsigned long);
4616 if (!cpu_has_vmx_msr_bitmap()) {
4622 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4623 * have the write-low and read-high bitmap offsets the wrong way round.
4624 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4626 if (msr
<= 0x1fff) {
4627 if (type
& MSR_TYPE_R
&&
4628 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4630 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4632 if (type
& MSR_TYPE_W
&&
4633 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4635 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4637 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4639 if (type
& MSR_TYPE_R
&&
4640 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4642 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4644 if (type
& MSR_TYPE_W
&&
4645 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4647 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4652 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4655 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4656 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4657 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4658 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4661 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4664 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4666 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4669 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4671 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4676 static bool vmx_get_enable_apicv(void)
4678 return enable_apicv
;
4681 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4683 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4688 if (vmx
->nested
.pi_desc
&&
4689 vmx
->nested
.pi_pending
) {
4690 vmx
->nested
.pi_pending
= false;
4691 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4694 max_irr
= find_last_bit(
4695 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4700 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4705 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4706 kunmap(vmx
->nested
.virtual_apic_page
);
4708 status
= vmcs_read16(GUEST_INTR_STATUS
);
4709 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4711 status
|= (u8
)max_irr
;
4712 vmcs_write16(GUEST_INTR_STATUS
, status
);
4718 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4721 if (vcpu
->mode
== IN_GUEST_MODE
) {
4722 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4725 * Currently, we don't support urgent interrupt,
4726 * all interrupts are recognized as non-urgent
4727 * interrupt, so we cannot post interrupts when
4730 * If the vcpu is in guest mode, it means it is
4731 * running instead of being scheduled out and
4732 * waiting in the run queue, and that's the only
4733 * case when 'SN' is set currently, warning if
4736 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4738 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4739 POSTED_INTR_VECTOR
);
4746 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4749 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4751 if (is_guest_mode(vcpu
) &&
4752 vector
== vmx
->nested
.posted_intr_nv
) {
4753 /* the PIR and ON have been set by L1. */
4754 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4756 * If a posted intr is not recognized by hardware,
4757 * we will accomplish it in the next vmentry.
4759 vmx
->nested
.pi_pending
= true;
4760 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4766 * Send interrupt to vcpu via posted interrupt way.
4767 * 1. If target vcpu is running(non-root mode), send posted interrupt
4768 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4769 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4770 * interrupt from PIR in next vmentry.
4772 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4774 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4777 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4781 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4784 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4785 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4786 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4787 kvm_vcpu_kick(vcpu
);
4790 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4792 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4794 if (!pi_test_on(&vmx
->pi_desc
))
4797 pi_clear_on(&vmx
->pi_desc
);
4799 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
4800 * But on x86 this is just a compiler barrier anyway.
4802 smp_mb__after_atomic();
4803 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4807 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4808 * will not change in the lifetime of the guest.
4809 * Note that host-state that does change is set elsewhere. E.g., host-state
4810 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4812 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4819 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4820 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4822 /* Save the most likely value for this task's CR4 in the VMCS. */
4823 cr4
= cr4_read_shadow();
4824 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4825 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4827 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4828 #ifdef CONFIG_X86_64
4830 * Load null selectors, so we can avoid reloading them in
4831 * __vmx_load_host_state(), in case userspace uses the null selectors
4832 * too (the expected case).
4834 vmcs_write16(HOST_DS_SELECTOR
, 0);
4835 vmcs_write16(HOST_ES_SELECTOR
, 0);
4837 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4838 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4840 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4841 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4843 native_store_idt(&dt
);
4844 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4845 vmx
->host_idt_base
= dt
.address
;
4847 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4849 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4850 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4851 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4852 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4854 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4855 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4856 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4860 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4862 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4864 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4865 if (is_guest_mode(&vmx
->vcpu
))
4866 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4867 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4868 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4871 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4873 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4875 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4876 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4877 /* Enable the preemption timer dynamically */
4878 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4879 return pin_based_exec_ctrl
;
4882 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4884 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4886 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4887 if (cpu_has_secondary_exec_ctrls()) {
4888 if (kvm_vcpu_apicv_active(vcpu
))
4889 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4890 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4891 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4893 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4894 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4895 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4898 if (cpu_has_vmx_msr_bitmap())
4899 vmx_set_msr_bitmap(vcpu
);
4902 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4904 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4906 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4907 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4909 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4910 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4911 #ifdef CONFIG_X86_64
4912 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4913 CPU_BASED_CR8_LOAD_EXITING
;
4917 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4918 CPU_BASED_CR3_LOAD_EXITING
|
4919 CPU_BASED_INVLPG_EXITING
;
4920 return exec_control
;
4923 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4925 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4926 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4927 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4929 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4931 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4932 enable_unrestricted_guest
= 0;
4933 /* Enable INVPCID for non-ept guests may cause performance regression. */
4934 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4936 if (!enable_unrestricted_guest
)
4937 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4939 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4940 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4941 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4942 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4943 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4944 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4946 We can NOT enable shadow_vmcs here because we don't have yet
4949 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4952 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4954 return exec_control
;
4957 static void ept_set_mmio_spte_mask(void)
4960 * EPT Misconfigurations can be generated if the value of bits 2:0
4961 * of an EPT paging-structure entry is 110b (write/execute).
4962 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4965 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4968 #define VMX_XSS_EXIT_BITMAP 0
4970 * Sets up the vmcs for emulated real mode.
4972 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4974 #ifdef CONFIG_X86_64
4980 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4981 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4983 if (enable_shadow_vmcs
) {
4984 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4985 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4987 if (cpu_has_vmx_msr_bitmap())
4988 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4990 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4993 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4994 vmx
->hv_deadline_tsc
= -1;
4996 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4998 if (cpu_has_secondary_exec_ctrls()) {
4999 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5000 vmx_secondary_exec_control(vmx
));
5003 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5004 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5005 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5006 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5007 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5009 vmcs_write16(GUEST_INTR_STATUS
, 0);
5011 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5012 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5016 vmcs_write32(PLE_GAP
, ple_gap
);
5017 vmx
->ple_window
= ple_window
;
5018 vmx
->ple_window_dirty
= true;
5021 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5022 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5023 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5025 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5026 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5027 vmx_set_constant_host_state(vmx
);
5028 #ifdef CONFIG_X86_64
5029 rdmsrl(MSR_FS_BASE
, a
);
5030 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5031 rdmsrl(MSR_GS_BASE
, a
);
5032 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5034 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5035 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5038 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5039 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5040 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5041 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5042 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5044 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5045 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5047 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5048 u32 index
= vmx_msr_index
[i
];
5049 u32 data_low
, data_high
;
5052 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5054 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5056 vmx
->guest_msrs
[j
].index
= i
;
5057 vmx
->guest_msrs
[j
].data
= 0;
5058 vmx
->guest_msrs
[j
].mask
= -1ull;
5063 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5065 /* 22.2.1, 20.8.1 */
5066 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5068 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
5069 set_cr4_guest_host_mask(vmx
);
5071 if (vmx_xsaves_supported())
5072 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5075 ASSERT(vmx
->pml_pg
);
5076 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5077 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5083 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5085 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5086 struct msr_data apic_base_msr
;
5089 vmx
->rmode
.vm86_active
= 0;
5091 vmx
->soft_vnmi_blocked
= 0;
5093 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5094 kvm_set_cr8(vcpu
, 0);
5097 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5098 MSR_IA32_APICBASE_ENABLE
;
5099 if (kvm_vcpu_is_reset_bsp(vcpu
))
5100 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5101 apic_base_msr
.host_initiated
= true;
5102 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5105 vmx_segment_cache_clear(vmx
);
5107 seg_setup(VCPU_SREG_CS
);
5108 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5109 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5111 seg_setup(VCPU_SREG_DS
);
5112 seg_setup(VCPU_SREG_ES
);
5113 seg_setup(VCPU_SREG_FS
);
5114 seg_setup(VCPU_SREG_GS
);
5115 seg_setup(VCPU_SREG_SS
);
5117 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5118 vmcs_writel(GUEST_TR_BASE
, 0);
5119 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5120 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5122 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5123 vmcs_writel(GUEST_LDTR_BASE
, 0);
5124 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5125 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5128 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5129 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5130 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5131 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5134 vmcs_writel(GUEST_RFLAGS
, 0x02);
5135 kvm_rip_write(vcpu
, 0xfff0);
5137 vmcs_writel(GUEST_GDTR_BASE
, 0);
5138 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5140 vmcs_writel(GUEST_IDTR_BASE
, 0);
5141 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5143 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5144 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5145 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5149 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5151 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5152 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5153 if (cpu_need_tpr_shadow(vcpu
))
5154 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5155 __pa(vcpu
->arch
.apic
->regs
));
5156 vmcs_write32(TPR_THRESHOLD
, 0);
5159 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5161 if (kvm_vcpu_apicv_active(vcpu
))
5162 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5165 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5167 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5168 vmx
->vcpu
.arch
.cr0
= cr0
;
5169 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5170 vmx_set_cr4(vcpu
, 0);
5171 vmx_set_efer(vcpu
, 0);
5172 vmx_fpu_activate(vcpu
);
5173 update_exception_bitmap(vcpu
);
5175 vpid_sync_context(vmx
->vpid
);
5179 * In nested virtualization, check if L1 asked to exit on external interrupts.
5180 * For most existing hypervisors, this will always return true.
5182 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5184 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5185 PIN_BASED_EXT_INTR_MASK
;
5189 * In nested virtualization, check if L1 has set
5190 * VM_EXIT_ACK_INTR_ON_EXIT
5192 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5194 return get_vmcs12(vcpu
)->vm_exit_controls
&
5195 VM_EXIT_ACK_INTR_ON_EXIT
;
5198 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5200 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5201 PIN_BASED_NMI_EXITING
;
5204 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5206 u32 cpu_based_vm_exec_control
;
5208 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5209 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5210 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5213 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5215 u32 cpu_based_vm_exec_control
;
5217 if (!cpu_has_virtual_nmis() ||
5218 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5219 enable_irq_window(vcpu
);
5223 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5224 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5225 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5228 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5230 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5232 int irq
= vcpu
->arch
.interrupt
.nr
;
5234 trace_kvm_inj_virq(irq
);
5236 ++vcpu
->stat
.irq_injections
;
5237 if (vmx
->rmode
.vm86_active
) {
5239 if (vcpu
->arch
.interrupt
.soft
)
5240 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5241 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5242 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5245 intr
= irq
| INTR_INFO_VALID_MASK
;
5246 if (vcpu
->arch
.interrupt
.soft
) {
5247 intr
|= INTR_TYPE_SOFT_INTR
;
5248 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5249 vmx
->vcpu
.arch
.event_exit_inst_len
);
5251 intr
|= INTR_TYPE_EXT_INTR
;
5252 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5255 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5257 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5259 if (!is_guest_mode(vcpu
)) {
5260 if (!cpu_has_virtual_nmis()) {
5262 * Tracking the NMI-blocked state in software is built upon
5263 * finding the next open IRQ window. This, in turn, depends on
5264 * well-behaving guests: They have to keep IRQs disabled at
5265 * least as long as the NMI handler runs. Otherwise we may
5266 * cause NMI nesting, maybe breaking the guest. But as this is
5267 * highly unlikely, we can live with the residual risk.
5269 vmx
->soft_vnmi_blocked
= 1;
5270 vmx
->vnmi_blocked_time
= 0;
5273 ++vcpu
->stat
.nmi_injections
;
5274 vmx
->nmi_known_unmasked
= false;
5277 if (vmx
->rmode
.vm86_active
) {
5278 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5279 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5283 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5284 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5287 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5289 if (!cpu_has_virtual_nmis())
5290 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5291 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5293 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5296 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5298 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5300 if (!cpu_has_virtual_nmis()) {
5301 if (vmx
->soft_vnmi_blocked
!= masked
) {
5302 vmx
->soft_vnmi_blocked
= masked
;
5303 vmx
->vnmi_blocked_time
= 0;
5306 vmx
->nmi_known_unmasked
= !masked
;
5308 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5309 GUEST_INTR_STATE_NMI
);
5311 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5312 GUEST_INTR_STATE_NMI
);
5316 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5318 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5321 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5324 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5325 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5326 | GUEST_INTR_STATE_NMI
));
5329 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5331 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5332 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5333 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5334 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5337 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5341 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5345 kvm
->arch
.tss_addr
= addr
;
5346 return init_rmode_tss(kvm
);
5349 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5354 * Update instruction length as we may reinject the exception
5355 * from user space while in guest debugging mode.
5357 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5358 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5359 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5363 if (vcpu
->guest_debug
&
5364 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5381 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5382 int vec
, u32 err_code
)
5385 * Instruction with address size override prefix opcode 0x67
5386 * Cause the #SS fault with 0 error code in VM86 mode.
5388 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5389 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5390 if (vcpu
->arch
.halt_request
) {
5391 vcpu
->arch
.halt_request
= 0;
5392 return kvm_vcpu_halt(vcpu
);
5400 * Forward all other exceptions that are valid in real mode.
5401 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5402 * the required debugging infrastructure rework.
5404 kvm_queue_exception(vcpu
, vec
);
5409 * Trigger machine check on the host. We assume all the MSRs are already set up
5410 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5411 * We pass a fake environment to the machine check handler because we want
5412 * the guest to be always treated like user space, no matter what context
5413 * it used internally.
5415 static void kvm_machine_check(void)
5417 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5418 struct pt_regs regs
= {
5419 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5420 .flags
= X86_EFLAGS_IF
,
5423 do_machine_check(®s
, 0);
5427 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5429 /* already handled by vcpu_run */
5433 static int handle_exception(struct kvm_vcpu
*vcpu
)
5435 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5436 struct kvm_run
*kvm_run
= vcpu
->run
;
5437 u32 intr_info
, ex_no
, error_code
;
5438 unsigned long cr2
, rip
, dr6
;
5440 enum emulation_result er
;
5442 vect_info
= vmx
->idt_vectoring_info
;
5443 intr_info
= vmx
->exit_intr_info
;
5445 if (is_machine_check(intr_info
))
5446 return handle_machine_check(vcpu
);
5448 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5449 return 1; /* already handled by vmx_vcpu_run() */
5451 if (is_no_device(intr_info
)) {
5452 vmx_fpu_activate(vcpu
);
5456 if (is_invalid_opcode(intr_info
)) {
5457 if (is_guest_mode(vcpu
)) {
5458 kvm_queue_exception(vcpu
, UD_VECTOR
);
5461 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5462 if (er
!= EMULATE_DONE
)
5463 kvm_queue_exception(vcpu
, UD_VECTOR
);
5468 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5469 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5472 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5473 * MMIO, it is better to report an internal error.
5474 * See the comments in vmx_handle_exit.
5476 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5477 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5478 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5479 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5480 vcpu
->run
->internal
.ndata
= 3;
5481 vcpu
->run
->internal
.data
[0] = vect_info
;
5482 vcpu
->run
->internal
.data
[1] = intr_info
;
5483 vcpu
->run
->internal
.data
[2] = error_code
;
5487 if (is_page_fault(intr_info
)) {
5488 /* EPT won't cause page fault directly */
5490 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5491 trace_kvm_page_fault(cr2
, error_code
);
5493 if (kvm_event_needs_reinjection(vcpu
))
5494 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5495 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5498 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5500 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5501 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5505 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5508 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5509 if (!(vcpu
->guest_debug
&
5510 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5511 vcpu
->arch
.dr6
&= ~15;
5512 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5513 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5514 skip_emulated_instruction(vcpu
);
5516 kvm_queue_exception(vcpu
, DB_VECTOR
);
5519 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5520 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5524 * Update instruction length as we may reinject #BP from
5525 * user space while in guest debugging mode. Reading it for
5526 * #DB as well causes no harm, it is not used in that case.
5528 vmx
->vcpu
.arch
.event_exit_inst_len
=
5529 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5530 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5531 rip
= kvm_rip_read(vcpu
);
5532 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5533 kvm_run
->debug
.arch
.exception
= ex_no
;
5536 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5537 kvm_run
->ex
.exception
= ex_no
;
5538 kvm_run
->ex
.error_code
= error_code
;
5544 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5546 ++vcpu
->stat
.irq_exits
;
5550 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5552 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5556 static int handle_io(struct kvm_vcpu
*vcpu
)
5558 unsigned long exit_qualification
;
5559 int size
, in
, string
;
5562 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5563 string
= (exit_qualification
& 16) != 0;
5564 in
= (exit_qualification
& 8) != 0;
5566 ++vcpu
->stat
.io_exits
;
5569 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5571 port
= exit_qualification
>> 16;
5572 size
= (exit_qualification
& 7) + 1;
5573 skip_emulated_instruction(vcpu
);
5575 return kvm_fast_pio_out(vcpu
, size
, port
);
5579 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5582 * Patch in the VMCALL instruction:
5584 hypercall
[0] = 0x0f;
5585 hypercall
[1] = 0x01;
5586 hypercall
[2] = 0xc1;
5589 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5591 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5592 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5594 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5595 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5596 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5597 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5598 return (val
& always_on
) == always_on
;
5601 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5602 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5604 if (is_guest_mode(vcpu
)) {
5605 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5606 unsigned long orig_val
= val
;
5609 * We get here when L2 changed cr0 in a way that did not change
5610 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5611 * but did change L0 shadowed bits. So we first calculate the
5612 * effective cr0 value that L1 would like to write into the
5613 * hardware. It consists of the L2-owned bits from the new
5614 * value combined with the L1-owned bits from L1's guest_cr0.
5616 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5617 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5619 if (!nested_cr0_valid(vcpu
, val
))
5622 if (kvm_set_cr0(vcpu
, val
))
5624 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5627 if (to_vmx(vcpu
)->nested
.vmxon
&&
5628 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5630 return kvm_set_cr0(vcpu
, val
);
5634 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5636 if (is_guest_mode(vcpu
)) {
5637 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5638 unsigned long orig_val
= val
;
5640 /* analogously to handle_set_cr0 */
5641 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5642 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5643 if (kvm_set_cr4(vcpu
, val
))
5645 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5648 return kvm_set_cr4(vcpu
, val
);
5651 /* called to set cr0 as appropriate for clts instruction exit. */
5652 static void handle_clts(struct kvm_vcpu
*vcpu
)
5654 if (is_guest_mode(vcpu
)) {
5656 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5657 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5658 * just pretend it's off (also in arch.cr0 for fpu_activate).
5660 vmcs_writel(CR0_READ_SHADOW
,
5661 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5662 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5664 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5667 static int handle_cr(struct kvm_vcpu
*vcpu
)
5669 unsigned long exit_qualification
, val
;
5674 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5675 cr
= exit_qualification
& 15;
5676 reg
= (exit_qualification
>> 8) & 15;
5677 switch ((exit_qualification
>> 4) & 3) {
5678 case 0: /* mov to cr */
5679 val
= kvm_register_readl(vcpu
, reg
);
5680 trace_kvm_cr_write(cr
, val
);
5683 err
= handle_set_cr0(vcpu
, val
);
5684 kvm_complete_insn_gp(vcpu
, err
);
5687 err
= kvm_set_cr3(vcpu
, val
);
5688 kvm_complete_insn_gp(vcpu
, err
);
5691 err
= handle_set_cr4(vcpu
, val
);
5692 kvm_complete_insn_gp(vcpu
, err
);
5695 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5697 err
= kvm_set_cr8(vcpu
, cr8
);
5698 kvm_complete_insn_gp(vcpu
, err
);
5699 if (lapic_in_kernel(vcpu
))
5701 if (cr8_prev
<= cr8
)
5703 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5710 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5711 skip_emulated_instruction(vcpu
);
5712 vmx_fpu_activate(vcpu
);
5714 case 1: /*mov from cr*/
5717 val
= kvm_read_cr3(vcpu
);
5718 kvm_register_write(vcpu
, reg
, val
);
5719 trace_kvm_cr_read(cr
, val
);
5720 skip_emulated_instruction(vcpu
);
5723 val
= kvm_get_cr8(vcpu
);
5724 kvm_register_write(vcpu
, reg
, val
);
5725 trace_kvm_cr_read(cr
, val
);
5726 skip_emulated_instruction(vcpu
);
5731 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5732 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5733 kvm_lmsw(vcpu
, val
);
5735 skip_emulated_instruction(vcpu
);
5740 vcpu
->run
->exit_reason
= 0;
5741 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5742 (int)(exit_qualification
>> 4) & 3, cr
);
5746 static int handle_dr(struct kvm_vcpu
*vcpu
)
5748 unsigned long exit_qualification
;
5751 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5752 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5754 /* First, if DR does not exist, trigger UD */
5755 if (!kvm_require_dr(vcpu
, dr
))
5758 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5759 if (!kvm_require_cpl(vcpu
, 0))
5761 dr7
= vmcs_readl(GUEST_DR7
);
5764 * As the vm-exit takes precedence over the debug trap, we
5765 * need to emulate the latter, either for the host or the
5766 * guest debugging itself.
5768 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5769 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5770 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5771 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5772 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5773 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5776 vcpu
->arch
.dr6
&= ~15;
5777 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5778 kvm_queue_exception(vcpu
, DB_VECTOR
);
5783 if (vcpu
->guest_debug
== 0) {
5784 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5785 CPU_BASED_MOV_DR_EXITING
);
5788 * No more DR vmexits; force a reload of the debug registers
5789 * and reenter on this instruction. The next vmexit will
5790 * retrieve the full state of the debug registers.
5792 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5796 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5797 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5800 if (kvm_get_dr(vcpu
, dr
, &val
))
5802 kvm_register_write(vcpu
, reg
, val
);
5804 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5807 skip_emulated_instruction(vcpu
);
5811 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5813 return vcpu
->arch
.dr6
;
5816 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5820 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5822 get_debugreg(vcpu
->arch
.db
[0], 0);
5823 get_debugreg(vcpu
->arch
.db
[1], 1);
5824 get_debugreg(vcpu
->arch
.db
[2], 2);
5825 get_debugreg(vcpu
->arch
.db
[3], 3);
5826 get_debugreg(vcpu
->arch
.dr6
, 6);
5827 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5829 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5830 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5833 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5835 vmcs_writel(GUEST_DR7
, val
);
5838 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5840 kvm_emulate_cpuid(vcpu
);
5844 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5846 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5847 struct msr_data msr_info
;
5849 msr_info
.index
= ecx
;
5850 msr_info
.host_initiated
= false;
5851 if (vmx_get_msr(vcpu
, &msr_info
)) {
5852 trace_kvm_msr_read_ex(ecx
);
5853 kvm_inject_gp(vcpu
, 0);
5857 trace_kvm_msr_read(ecx
, msr_info
.data
);
5859 /* FIXME: handling of bits 32:63 of rax, rdx */
5860 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5861 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5862 skip_emulated_instruction(vcpu
);
5866 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5868 struct msr_data msr
;
5869 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5870 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5871 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5875 msr
.host_initiated
= false;
5876 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5877 trace_kvm_msr_write_ex(ecx
, data
);
5878 kvm_inject_gp(vcpu
, 0);
5882 trace_kvm_msr_write(ecx
, data
);
5883 skip_emulated_instruction(vcpu
);
5887 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5889 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5893 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5895 u32 cpu_based_vm_exec_control
;
5897 /* clear pending irq */
5898 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5899 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5900 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5902 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5904 ++vcpu
->stat
.irq_window_exits
;
5908 static int handle_halt(struct kvm_vcpu
*vcpu
)
5910 return kvm_emulate_halt(vcpu
);
5913 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5915 return kvm_emulate_hypercall(vcpu
);
5918 static int handle_invd(struct kvm_vcpu
*vcpu
)
5920 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5923 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5925 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5927 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5928 skip_emulated_instruction(vcpu
);
5932 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5936 err
= kvm_rdpmc(vcpu
);
5937 kvm_complete_insn_gp(vcpu
, err
);
5942 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5944 kvm_emulate_wbinvd(vcpu
);
5948 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5950 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5951 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5953 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5954 skip_emulated_instruction(vcpu
);
5958 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5960 skip_emulated_instruction(vcpu
);
5961 WARN(1, "this should never happen\n");
5965 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5967 skip_emulated_instruction(vcpu
);
5968 WARN(1, "this should never happen\n");
5972 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5974 if (likely(fasteoi
)) {
5975 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5976 int access_type
, offset
;
5978 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5979 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5981 * Sane guest uses MOV to write EOI, with written value
5982 * not cared. So make a short-circuit here by avoiding
5983 * heavy instruction emulation.
5985 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5986 (offset
== APIC_EOI
)) {
5987 kvm_lapic_set_eoi(vcpu
);
5988 skip_emulated_instruction(vcpu
);
5992 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5995 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5997 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5998 int vector
= exit_qualification
& 0xff;
6000 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6001 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6005 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6007 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6008 u32 offset
= exit_qualification
& 0xfff;
6010 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6011 kvm_apic_write_nodecode(vcpu
, offset
);
6015 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6017 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6018 unsigned long exit_qualification
;
6019 bool has_error_code
= false;
6022 int reason
, type
, idt_v
, idt_index
;
6024 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6025 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6026 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6028 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6030 reason
= (u32
)exit_qualification
>> 30;
6031 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6033 case INTR_TYPE_NMI_INTR
:
6034 vcpu
->arch
.nmi_injected
= false;
6035 vmx_set_nmi_mask(vcpu
, true);
6037 case INTR_TYPE_EXT_INTR
:
6038 case INTR_TYPE_SOFT_INTR
:
6039 kvm_clear_interrupt_queue(vcpu
);
6041 case INTR_TYPE_HARD_EXCEPTION
:
6042 if (vmx
->idt_vectoring_info
&
6043 VECTORING_INFO_DELIVER_CODE_MASK
) {
6044 has_error_code
= true;
6046 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6049 case INTR_TYPE_SOFT_EXCEPTION
:
6050 kvm_clear_exception_queue(vcpu
);
6056 tss_selector
= exit_qualification
;
6058 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6059 type
!= INTR_TYPE_EXT_INTR
&&
6060 type
!= INTR_TYPE_NMI_INTR
))
6061 skip_emulated_instruction(vcpu
);
6063 if (kvm_task_switch(vcpu
, tss_selector
,
6064 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6065 has_error_code
, error_code
) == EMULATE_FAIL
) {
6066 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6067 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6068 vcpu
->run
->internal
.ndata
= 0;
6073 * TODO: What about debug traps on tss switch?
6074 * Are we supposed to inject them and update dr6?
6080 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6082 unsigned long exit_qualification
;
6087 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6089 gla_validity
= (exit_qualification
>> 7) & 0x3;
6090 if (gla_validity
== 0x2) {
6091 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6092 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6093 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6094 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6095 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6096 (long unsigned int)exit_qualification
);
6097 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6098 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6103 * EPT violation happened while executing iret from NMI,
6104 * "blocked by NMI" bit has to be set before next VM entry.
6105 * There are errata that may cause this bit to not be set:
6108 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6109 cpu_has_virtual_nmis() &&
6110 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6111 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6113 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6114 trace_kvm_page_fault(gpa
, exit_qualification
);
6116 /* it is a read fault? */
6117 error_code
= (exit_qualification
<< 2) & PFERR_USER_MASK
;
6118 /* it is a write fault? */
6119 error_code
|= exit_qualification
& PFERR_WRITE_MASK
;
6120 /* It is a fetch fault? */
6121 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6122 /* ept page table is present? */
6123 error_code
|= (exit_qualification
& 0x38) != 0;
6125 vcpu
->arch
.exit_qualification
= exit_qualification
;
6127 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6130 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6135 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6136 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6137 skip_emulated_instruction(vcpu
);
6138 trace_kvm_fast_mmio(gpa
);
6142 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6143 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6144 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6147 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6148 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6150 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6153 /* It is the real ept misconfig */
6156 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6157 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6162 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6164 u32 cpu_based_vm_exec_control
;
6166 /* clear pending NMI */
6167 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6168 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6169 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6170 ++vcpu
->stat
.nmi_window_exits
;
6171 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6176 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6178 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6179 enum emulation_result err
= EMULATE_DONE
;
6182 bool intr_window_requested
;
6183 unsigned count
= 130;
6185 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6186 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6188 while (vmx
->emulation_required
&& count
-- != 0) {
6189 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6190 return handle_interrupt_window(&vmx
->vcpu
);
6192 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6195 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6197 if (err
== EMULATE_USER_EXIT
) {
6198 ++vcpu
->stat
.mmio_exits
;
6203 if (err
!= EMULATE_DONE
) {
6204 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6205 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6206 vcpu
->run
->internal
.ndata
= 0;
6210 if (vcpu
->arch
.halt_request
) {
6211 vcpu
->arch
.halt_request
= 0;
6212 ret
= kvm_vcpu_halt(vcpu
);
6216 if (signal_pending(current
))
6226 static int __grow_ple_window(int val
)
6228 if (ple_window_grow
< 1)
6231 val
= min(val
, ple_window_actual_max
);
6233 if (ple_window_grow
< ple_window
)
6234 val
*= ple_window_grow
;
6236 val
+= ple_window_grow
;
6241 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6246 if (modifier
< ple_window
)
6251 return max(val
, minimum
);
6254 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6257 int old
= vmx
->ple_window
;
6259 vmx
->ple_window
= __grow_ple_window(old
);
6261 if (vmx
->ple_window
!= old
)
6262 vmx
->ple_window_dirty
= true;
6264 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6267 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6269 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6270 int old
= vmx
->ple_window
;
6272 vmx
->ple_window
= __shrink_ple_window(old
,
6273 ple_window_shrink
, ple_window
);
6275 if (vmx
->ple_window
!= old
)
6276 vmx
->ple_window_dirty
= true;
6278 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6282 * ple_window_actual_max is computed to be one grow_ple_window() below
6283 * ple_window_max. (See __grow_ple_window for the reason.)
6284 * This prevents overflows, because ple_window_max is int.
6285 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6287 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6289 static void update_ple_window_actual_max(void)
6291 ple_window_actual_max
=
6292 __shrink_ple_window(max(ple_window_max
, ple_window
),
6293 ple_window_grow
, INT_MIN
);
6297 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6299 static void wakeup_handler(void)
6301 struct kvm_vcpu
*vcpu
;
6302 int cpu
= smp_processor_id();
6304 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6305 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6306 blocked_vcpu_list
) {
6307 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6309 if (pi_test_on(pi_desc
) == 1)
6310 kvm_vcpu_kick(vcpu
);
6312 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6315 static __init
int hardware_setup(void)
6317 int r
= -ENOMEM
, i
, msr
;
6319 rdmsrl_safe(MSR_EFER
, &host_efer
);
6321 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6322 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6324 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6325 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6330 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6331 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6332 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6335 * Allow direct access to the PC debug port (it is often used for I/O
6336 * delays, but the vmexits simply slow things down).
6338 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6339 clear_bit(0x80, vmx_io_bitmap_a
);
6341 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6343 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6344 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6346 if (setup_vmcs_config(&vmcs_config
) < 0) {
6351 if (boot_cpu_has(X86_FEATURE_NX
))
6352 kvm_enable_efer_bits(EFER_NX
);
6354 if (!cpu_has_vmx_vpid())
6356 if (!cpu_has_vmx_shadow_vmcs())
6357 enable_shadow_vmcs
= 0;
6358 if (enable_shadow_vmcs
)
6359 init_vmcs_shadow_fields();
6361 if (!cpu_has_vmx_ept() ||
6362 !cpu_has_vmx_ept_4levels()) {
6364 enable_unrestricted_guest
= 0;
6365 enable_ept_ad_bits
= 0;
6368 if (!cpu_has_vmx_ept_ad_bits())
6369 enable_ept_ad_bits
= 0;
6371 if (!cpu_has_vmx_unrestricted_guest())
6372 enable_unrestricted_guest
= 0;
6374 if (!cpu_has_vmx_flexpriority())
6375 flexpriority_enabled
= 0;
6378 * set_apic_access_page_addr() is used to reload apic access
6379 * page upon invalidation. No need to do anything if not
6380 * using the APIC_ACCESS_ADDR VMCS field.
6382 if (!flexpriority_enabled
)
6383 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6385 if (!cpu_has_vmx_tpr_shadow())
6386 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6388 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6389 kvm_disable_largepages();
6391 if (!cpu_has_vmx_ple())
6394 if (!cpu_has_vmx_apicv())
6397 if (cpu_has_vmx_tsc_scaling()) {
6398 kvm_has_tsc_control
= true;
6399 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6400 kvm_tsc_scaling_ratio_frac_bits
= 48;
6403 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6404 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6405 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6406 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6407 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6408 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6409 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6411 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6412 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6413 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6414 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6415 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6416 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6417 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6418 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6420 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6422 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6423 if (msr
== 0x839 /* TMCCT */)
6425 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6429 * TPR reads and writes can be virtualized even if virtual interrupt
6430 * delivery is not in use.
6432 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6433 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6436 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6438 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6441 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6442 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6443 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6444 0ull, VMX_EPT_EXECUTABLE_MASK
,
6445 cpu_has_vmx_ept_execute_only() ?
6446 0ull : VMX_EPT_READABLE_MASK
);
6447 ept_set_mmio_spte_mask();
6452 update_ple_window_actual_max();
6455 * Only enable PML when hardware supports PML feature, and both EPT
6456 * and EPT A/D bit features are enabled -- PML depends on them to work.
6458 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6462 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6463 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6464 kvm_x86_ops
->flush_log_dirty
= NULL
;
6465 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6468 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6471 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6472 cpu_preemption_timer_multi
=
6473 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6475 kvm_x86_ops
->set_hv_timer
= NULL
;
6476 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6479 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6481 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6483 return alloc_kvm_area();
6486 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6487 free_page((unsigned long)vmx_bitmap
[i
]);
6492 static __exit
void hardware_unsetup(void)
6496 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6497 free_page((unsigned long)vmx_bitmap
[i
]);
6503 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6504 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6506 static int handle_pause(struct kvm_vcpu
*vcpu
)
6509 grow_ple_window(vcpu
);
6511 skip_emulated_instruction(vcpu
);
6512 kvm_vcpu_on_spin(vcpu
);
6517 static int handle_nop(struct kvm_vcpu
*vcpu
)
6519 skip_emulated_instruction(vcpu
);
6523 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6525 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6526 return handle_nop(vcpu
);
6529 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6534 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6536 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6537 return handle_nop(vcpu
);
6541 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6542 * We could reuse a single VMCS for all the L2 guests, but we also want the
6543 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6544 * allows keeping them loaded on the processor, and in the future will allow
6545 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6546 * every entry if they never change.
6547 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6548 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6550 * The following functions allocate and free a vmcs02 in this pool.
6553 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6554 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6556 struct vmcs02_list
*item
;
6557 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6558 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6559 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6560 return &item
->vmcs02
;
6563 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6564 /* Recycle the least recently used VMCS. */
6565 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6566 struct vmcs02_list
, list
);
6567 item
->vmptr
= vmx
->nested
.current_vmptr
;
6568 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6569 return &item
->vmcs02
;
6572 /* Create a new VMCS */
6573 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6576 item
->vmcs02
.vmcs
= alloc_vmcs();
6577 item
->vmcs02
.shadow_vmcs
= NULL
;
6578 if (!item
->vmcs02
.vmcs
) {
6582 loaded_vmcs_init(&item
->vmcs02
);
6583 item
->vmptr
= vmx
->nested
.current_vmptr
;
6584 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6585 vmx
->nested
.vmcs02_num
++;
6586 return &item
->vmcs02
;
6589 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6590 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6592 struct vmcs02_list
*item
;
6593 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6594 if (item
->vmptr
== vmptr
) {
6595 free_loaded_vmcs(&item
->vmcs02
);
6596 list_del(&item
->list
);
6598 vmx
->nested
.vmcs02_num
--;
6604 * Free all VMCSs saved for this vcpu, except the one pointed by
6605 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6606 * must be &vmx->vmcs01.
6608 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6610 struct vmcs02_list
*item
, *n
;
6612 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6613 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6615 * Something will leak if the above WARN triggers. Better than
6618 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6621 free_loaded_vmcs(&item
->vmcs02
);
6622 list_del(&item
->list
);
6624 vmx
->nested
.vmcs02_num
--;
6629 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6630 * set the success or error code of an emulated VMX instruction, as specified
6631 * by Vol 2B, VMX Instruction Reference, "Conventions".
6633 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6635 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6636 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6637 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6640 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6642 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6643 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6644 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6648 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6649 u32 vm_instruction_error
)
6651 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6653 * failValid writes the error number to the current VMCS, which
6654 * can't be done there isn't a current VMCS.
6656 nested_vmx_failInvalid(vcpu
);
6659 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6660 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6661 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6663 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6665 * We don't need to force a shadow sync because
6666 * VM_INSTRUCTION_ERROR is not shadowed
6670 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6672 /* TODO: not to reset guest simply here. */
6673 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6674 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6677 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6679 struct vcpu_vmx
*vmx
=
6680 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6682 vmx
->nested
.preemption_timer_expired
= true;
6683 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6684 kvm_vcpu_kick(&vmx
->vcpu
);
6686 return HRTIMER_NORESTART
;
6690 * Decode the memory-address operand of a vmx instruction, as recorded on an
6691 * exit caused by such an instruction (run by a guest hypervisor).
6692 * On success, returns 0. When the operand is invalid, returns 1 and throws
6695 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6696 unsigned long exit_qualification
,
6697 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6701 struct kvm_segment s
;
6704 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6705 * Execution", on an exit, vmx_instruction_info holds most of the
6706 * addressing components of the operand. Only the displacement part
6707 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6708 * For how an actual address is calculated from all these components,
6709 * refer to Vol. 1, "Operand Addressing".
6711 int scaling
= vmx_instruction_info
& 3;
6712 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6713 bool is_reg
= vmx_instruction_info
& (1u << 10);
6714 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6715 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6716 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6717 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6718 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6721 kvm_queue_exception(vcpu
, UD_VECTOR
);
6725 /* Addr = segment_base + offset */
6726 /* offset = base + [index * scale] + displacement */
6727 off
= exit_qualification
; /* holds the displacement */
6729 off
+= kvm_register_read(vcpu
, base_reg
);
6731 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6732 vmx_get_segment(vcpu
, &s
, seg_reg
);
6733 *ret
= s
.base
+ off
;
6735 if (addr_size
== 1) /* 32 bit */
6738 /* Checks for #GP/#SS exceptions. */
6740 if (is_long_mode(vcpu
)) {
6741 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6742 * non-canonical form. This is the only check on the memory
6743 * destination for long mode!
6745 exn
= is_noncanonical_address(*ret
);
6746 } else if (is_protmode(vcpu
)) {
6747 /* Protected mode: apply checks for segment validity in the
6749 * - segment type check (#GP(0) may be thrown)
6750 * - usability check (#GP(0)/#SS(0))
6751 * - limit check (#GP(0)/#SS(0))
6754 /* #GP(0) if the destination operand is located in a
6755 * read-only data segment or any code segment.
6757 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6759 /* #GP(0) if the source operand is located in an
6760 * execute-only code segment
6762 exn
= ((s
.type
& 0xa) == 8);
6764 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6767 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6769 exn
= (s
.unusable
!= 0);
6770 /* Protected mode: #GP(0)/#SS(0) if the memory
6771 * operand is outside the segment limit.
6773 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6776 kvm_queue_exception_e(vcpu
,
6777 seg_reg
== VCPU_SREG_SS
?
6778 SS_VECTOR
: GP_VECTOR
,
6787 * This function performs the various checks including
6788 * - if it's 4KB aligned
6789 * - No bits beyond the physical address width are set
6790 * - Returns 0 on success or else 1
6791 * (Intel SDM Section 30.3)
6793 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6798 struct x86_exception e
;
6800 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6801 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6803 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6804 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6807 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6808 sizeof(vmptr
), &e
)) {
6809 kvm_inject_page_fault(vcpu
, &e
);
6813 switch (exit_reason
) {
6814 case EXIT_REASON_VMON
:
6817 * The first 4 bytes of VMXON region contain the supported
6818 * VMCS revision identifier
6820 * Note - IA32_VMX_BASIC[48] will never be 1
6821 * for the nested case;
6822 * which replaces physical address width with 32
6825 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6826 nested_vmx_failInvalid(vcpu
);
6827 skip_emulated_instruction(vcpu
);
6831 page
= nested_get_page(vcpu
, vmptr
);
6833 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6834 nested_vmx_failInvalid(vcpu
);
6836 skip_emulated_instruction(vcpu
);
6840 vmx
->nested
.vmxon_ptr
= vmptr
;
6842 case EXIT_REASON_VMCLEAR
:
6843 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6844 nested_vmx_failValid(vcpu
,
6845 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6846 skip_emulated_instruction(vcpu
);
6850 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6851 nested_vmx_failValid(vcpu
,
6852 VMXERR_VMCLEAR_VMXON_POINTER
);
6853 skip_emulated_instruction(vcpu
);
6857 case EXIT_REASON_VMPTRLD
:
6858 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6859 nested_vmx_failValid(vcpu
,
6860 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6861 skip_emulated_instruction(vcpu
);
6865 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6866 nested_vmx_failValid(vcpu
,
6867 VMXERR_VMCLEAR_VMXON_POINTER
);
6868 skip_emulated_instruction(vcpu
);
6873 return 1; /* shouldn't happen */
6882 * Emulate the VMXON instruction.
6883 * Currently, we just remember that VMX is active, and do not save or even
6884 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6885 * do not currently need to store anything in that guest-allocated memory
6886 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6887 * argument is different from the VMXON pointer (which the spec says they do).
6889 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6891 struct kvm_segment cs
;
6892 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6893 struct vmcs
*shadow_vmcs
;
6894 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6895 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6897 /* The Intel VMX Instruction Reference lists a bunch of bits that
6898 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6899 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6900 * Otherwise, we should fail with #UD. We test these now:
6902 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6903 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6904 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6905 kvm_queue_exception(vcpu
, UD_VECTOR
);
6909 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6910 if (is_long_mode(vcpu
) && !cs
.l
) {
6911 kvm_queue_exception(vcpu
, UD_VECTOR
);
6915 if (vmx_get_cpl(vcpu
)) {
6916 kvm_inject_gp(vcpu
, 0);
6920 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6923 if (vmx
->nested
.vmxon
) {
6924 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6925 skip_emulated_instruction(vcpu
);
6929 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6930 != VMXON_NEEDED_FEATURES
) {
6931 kvm_inject_gp(vcpu
, 0);
6935 if (cpu_has_vmx_msr_bitmap()) {
6936 vmx
->nested
.msr_bitmap
=
6937 (unsigned long *)__get_free_page(GFP_KERNEL
);
6938 if (!vmx
->nested
.msr_bitmap
)
6939 goto out_msr_bitmap
;
6942 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
6943 if (!vmx
->nested
.cached_vmcs12
)
6944 goto out_cached_vmcs12
;
6946 if (enable_shadow_vmcs
) {
6947 shadow_vmcs
= alloc_vmcs();
6949 goto out_shadow_vmcs
;
6950 /* mark vmcs as shadow */
6951 shadow_vmcs
->revision_id
|= (1u << 31);
6952 /* init shadow vmcs */
6953 vmcs_clear(shadow_vmcs
);
6954 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
6957 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6958 vmx
->nested
.vmcs02_num
= 0;
6960 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6961 HRTIMER_MODE_REL_PINNED
);
6962 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6964 vmx
->nested
.vmxon
= true;
6966 skip_emulated_instruction(vcpu
);
6967 nested_vmx_succeed(vcpu
);
6971 kfree(vmx
->nested
.cached_vmcs12
);
6974 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
6981 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6982 * for running VMX instructions (except VMXON, whose prerequisites are
6983 * slightly different). It also specifies what exception to inject otherwise.
6985 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6987 struct kvm_segment cs
;
6988 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6990 if (!vmx
->nested
.vmxon
) {
6991 kvm_queue_exception(vcpu
, UD_VECTOR
);
6995 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6996 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6997 (is_long_mode(vcpu
) && !cs
.l
)) {
6998 kvm_queue_exception(vcpu
, UD_VECTOR
);
7002 if (vmx_get_cpl(vcpu
)) {
7003 kvm_inject_gp(vcpu
, 0);
7010 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7012 if (vmx
->nested
.current_vmptr
== -1ull)
7015 /* current_vmptr and current_vmcs12 are always set/reset together */
7016 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7019 if (enable_shadow_vmcs
) {
7020 /* copy to memory all shadowed fields in case
7021 they were modified */
7022 copy_shadow_to_vmcs12(vmx
);
7023 vmx
->nested
.sync_shadow_vmcs
= false;
7024 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7025 SECONDARY_EXEC_SHADOW_VMCS
);
7026 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7028 vmx
->nested
.posted_intr_nv
= -1;
7030 /* Flush VMCS12 to guest memory */
7031 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7034 kunmap(vmx
->nested
.current_vmcs12_page
);
7035 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7036 vmx
->nested
.current_vmptr
= -1ull;
7037 vmx
->nested
.current_vmcs12
= NULL
;
7041 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7042 * just stops using VMX.
7044 static void free_nested(struct vcpu_vmx
*vmx
)
7046 if (!vmx
->nested
.vmxon
)
7049 vmx
->nested
.vmxon
= false;
7050 free_vpid(vmx
->nested
.vpid02
);
7051 nested_release_vmcs12(vmx
);
7052 if (vmx
->nested
.msr_bitmap
) {
7053 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7054 vmx
->nested
.msr_bitmap
= NULL
;
7056 if (enable_shadow_vmcs
) {
7057 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7058 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7059 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7061 kfree(vmx
->nested
.cached_vmcs12
);
7062 /* Unpin physical memory we referred to in current vmcs02 */
7063 if (vmx
->nested
.apic_access_page
) {
7064 nested_release_page(vmx
->nested
.apic_access_page
);
7065 vmx
->nested
.apic_access_page
= NULL
;
7067 if (vmx
->nested
.virtual_apic_page
) {
7068 nested_release_page(vmx
->nested
.virtual_apic_page
);
7069 vmx
->nested
.virtual_apic_page
= NULL
;
7071 if (vmx
->nested
.pi_desc_page
) {
7072 kunmap(vmx
->nested
.pi_desc_page
);
7073 nested_release_page(vmx
->nested
.pi_desc_page
);
7074 vmx
->nested
.pi_desc_page
= NULL
;
7075 vmx
->nested
.pi_desc
= NULL
;
7078 nested_free_all_saved_vmcss(vmx
);
7081 /* Emulate the VMXOFF instruction */
7082 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7084 if (!nested_vmx_check_permission(vcpu
))
7086 free_nested(to_vmx(vcpu
));
7087 skip_emulated_instruction(vcpu
);
7088 nested_vmx_succeed(vcpu
);
7092 /* Emulate the VMCLEAR instruction */
7093 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7095 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7097 struct vmcs12
*vmcs12
;
7100 if (!nested_vmx_check_permission(vcpu
))
7103 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7106 if (vmptr
== vmx
->nested
.current_vmptr
)
7107 nested_release_vmcs12(vmx
);
7109 page
= nested_get_page(vcpu
, vmptr
);
7112 * For accurate processor emulation, VMCLEAR beyond available
7113 * physical memory should do nothing at all. However, it is
7114 * possible that a nested vmx bug, not a guest hypervisor bug,
7115 * resulted in this case, so let's shut down before doing any
7118 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7121 vmcs12
= kmap(page
);
7122 vmcs12
->launch_state
= 0;
7124 nested_release_page(page
);
7126 nested_free_vmcs02(vmx
, vmptr
);
7128 skip_emulated_instruction(vcpu
);
7129 nested_vmx_succeed(vcpu
);
7133 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7135 /* Emulate the VMLAUNCH instruction */
7136 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7138 return nested_vmx_run(vcpu
, true);
7141 /* Emulate the VMRESUME instruction */
7142 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7145 return nested_vmx_run(vcpu
, false);
7148 enum vmcs_field_type
{
7149 VMCS_FIELD_TYPE_U16
= 0,
7150 VMCS_FIELD_TYPE_U64
= 1,
7151 VMCS_FIELD_TYPE_U32
= 2,
7152 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7155 static inline int vmcs_field_type(unsigned long field
)
7157 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7158 return VMCS_FIELD_TYPE_U32
;
7159 return (field
>> 13) & 0x3 ;
7162 static inline int vmcs_field_readonly(unsigned long field
)
7164 return (((field
>> 10) & 0x3) == 1);
7168 * Read a vmcs12 field. Since these can have varying lengths and we return
7169 * one type, we chose the biggest type (u64) and zero-extend the return value
7170 * to that size. Note that the caller, handle_vmread, might need to use only
7171 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7172 * 64-bit fields are to be returned).
7174 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7175 unsigned long field
, u64
*ret
)
7177 short offset
= vmcs_field_to_offset(field
);
7183 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7185 switch (vmcs_field_type(field
)) {
7186 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7187 *ret
= *((natural_width
*)p
);
7189 case VMCS_FIELD_TYPE_U16
:
7192 case VMCS_FIELD_TYPE_U32
:
7195 case VMCS_FIELD_TYPE_U64
:
7205 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7206 unsigned long field
, u64 field_value
){
7207 short offset
= vmcs_field_to_offset(field
);
7208 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7212 switch (vmcs_field_type(field
)) {
7213 case VMCS_FIELD_TYPE_U16
:
7214 *(u16
*)p
= field_value
;
7216 case VMCS_FIELD_TYPE_U32
:
7217 *(u32
*)p
= field_value
;
7219 case VMCS_FIELD_TYPE_U64
:
7220 *(u64
*)p
= field_value
;
7222 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7223 *(natural_width
*)p
= field_value
;
7232 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7235 unsigned long field
;
7237 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7238 const unsigned long *fields
= shadow_read_write_fields
;
7239 const int num_fields
= max_shadow_read_write_fields
;
7243 vmcs_load(shadow_vmcs
);
7245 for (i
= 0; i
< num_fields
; i
++) {
7247 switch (vmcs_field_type(field
)) {
7248 case VMCS_FIELD_TYPE_U16
:
7249 field_value
= vmcs_read16(field
);
7251 case VMCS_FIELD_TYPE_U32
:
7252 field_value
= vmcs_read32(field
);
7254 case VMCS_FIELD_TYPE_U64
:
7255 field_value
= vmcs_read64(field
);
7257 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7258 field_value
= vmcs_readl(field
);
7264 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7267 vmcs_clear(shadow_vmcs
);
7268 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7273 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7275 const unsigned long *fields
[] = {
7276 shadow_read_write_fields
,
7277 shadow_read_only_fields
7279 const int max_fields
[] = {
7280 max_shadow_read_write_fields
,
7281 max_shadow_read_only_fields
7284 unsigned long field
;
7285 u64 field_value
= 0;
7286 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7288 vmcs_load(shadow_vmcs
);
7290 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7291 for (i
= 0; i
< max_fields
[q
]; i
++) {
7292 field
= fields
[q
][i
];
7293 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7295 switch (vmcs_field_type(field
)) {
7296 case VMCS_FIELD_TYPE_U16
:
7297 vmcs_write16(field
, (u16
)field_value
);
7299 case VMCS_FIELD_TYPE_U32
:
7300 vmcs_write32(field
, (u32
)field_value
);
7302 case VMCS_FIELD_TYPE_U64
:
7303 vmcs_write64(field
, (u64
)field_value
);
7305 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7306 vmcs_writel(field
, (long)field_value
);
7315 vmcs_clear(shadow_vmcs
);
7316 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7320 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7321 * used before) all generate the same failure when it is missing.
7323 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7325 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7326 if (vmx
->nested
.current_vmptr
== -1ull) {
7327 nested_vmx_failInvalid(vcpu
);
7328 skip_emulated_instruction(vcpu
);
7334 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7336 unsigned long field
;
7338 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7339 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7342 if (!nested_vmx_check_permission(vcpu
) ||
7343 !nested_vmx_check_vmcs12(vcpu
))
7346 /* Decode instruction info and find the field to read */
7347 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7348 /* Read the field, zero-extended to a u64 field_value */
7349 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7350 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7351 skip_emulated_instruction(vcpu
);
7355 * Now copy part of this value to register or memory, as requested.
7356 * Note that the number of bits actually copied is 32 or 64 depending
7357 * on the guest's mode (32 or 64 bit), not on the given field's length.
7359 if (vmx_instruction_info
& (1u << 10)) {
7360 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7363 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7364 vmx_instruction_info
, true, &gva
))
7366 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7367 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7368 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7371 nested_vmx_succeed(vcpu
);
7372 skip_emulated_instruction(vcpu
);
7377 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7379 unsigned long field
;
7381 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7382 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7383 /* The value to write might be 32 or 64 bits, depending on L1's long
7384 * mode, and eventually we need to write that into a field of several
7385 * possible lengths. The code below first zero-extends the value to 64
7386 * bit (field_value), and then copies only the appropriate number of
7387 * bits into the vmcs12 field.
7389 u64 field_value
= 0;
7390 struct x86_exception e
;
7392 if (!nested_vmx_check_permission(vcpu
) ||
7393 !nested_vmx_check_vmcs12(vcpu
))
7396 if (vmx_instruction_info
& (1u << 10))
7397 field_value
= kvm_register_readl(vcpu
,
7398 (((vmx_instruction_info
) >> 3) & 0xf));
7400 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7401 vmx_instruction_info
, false, &gva
))
7403 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7404 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7405 kvm_inject_page_fault(vcpu
, &e
);
7411 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7412 if (vmcs_field_readonly(field
)) {
7413 nested_vmx_failValid(vcpu
,
7414 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7415 skip_emulated_instruction(vcpu
);
7419 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7420 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7421 skip_emulated_instruction(vcpu
);
7425 nested_vmx_succeed(vcpu
);
7426 skip_emulated_instruction(vcpu
);
7430 /* Emulate the VMPTRLD instruction */
7431 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7433 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7436 if (!nested_vmx_check_permission(vcpu
))
7439 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7442 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7443 struct vmcs12
*new_vmcs12
;
7445 page
= nested_get_page(vcpu
, vmptr
);
7447 nested_vmx_failInvalid(vcpu
);
7448 skip_emulated_instruction(vcpu
);
7451 new_vmcs12
= kmap(page
);
7452 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7454 nested_release_page_clean(page
);
7455 nested_vmx_failValid(vcpu
,
7456 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7457 skip_emulated_instruction(vcpu
);
7461 nested_release_vmcs12(vmx
);
7462 vmx
->nested
.current_vmptr
= vmptr
;
7463 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7464 vmx
->nested
.current_vmcs12_page
= page
;
7466 * Load VMCS12 from guest memory since it is not already
7469 memcpy(vmx
->nested
.cached_vmcs12
,
7470 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7472 if (enable_shadow_vmcs
) {
7473 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7474 SECONDARY_EXEC_SHADOW_VMCS
);
7475 vmcs_write64(VMCS_LINK_POINTER
,
7476 __pa(vmx
->vmcs01
.shadow_vmcs
));
7477 vmx
->nested
.sync_shadow_vmcs
= true;
7481 nested_vmx_succeed(vcpu
);
7482 skip_emulated_instruction(vcpu
);
7486 /* Emulate the VMPTRST instruction */
7487 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7489 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7490 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7492 struct x86_exception e
;
7494 if (!nested_vmx_check_permission(vcpu
))
7497 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7498 vmx_instruction_info
, true, &vmcs_gva
))
7500 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7501 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7502 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7504 kvm_inject_page_fault(vcpu
, &e
);
7507 nested_vmx_succeed(vcpu
);
7508 skip_emulated_instruction(vcpu
);
7512 /* Emulate the INVEPT instruction */
7513 static int handle_invept(struct kvm_vcpu
*vcpu
)
7515 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7516 u32 vmx_instruction_info
, types
;
7519 struct x86_exception e
;
7524 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7525 SECONDARY_EXEC_ENABLE_EPT
) ||
7526 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7527 kvm_queue_exception(vcpu
, UD_VECTOR
);
7531 if (!nested_vmx_check_permission(vcpu
))
7534 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7535 kvm_queue_exception(vcpu
, UD_VECTOR
);
7539 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7540 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7542 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7544 if (type
>= 32 || !(types
& (1 << type
))) {
7545 nested_vmx_failValid(vcpu
,
7546 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7547 skip_emulated_instruction(vcpu
);
7551 /* According to the Intel VMX instruction reference, the memory
7552 * operand is read even if it isn't needed (e.g., for type==global)
7554 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7555 vmx_instruction_info
, false, &gva
))
7557 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7558 sizeof(operand
), &e
)) {
7559 kvm_inject_page_fault(vcpu
, &e
);
7564 case VMX_EPT_EXTENT_GLOBAL
:
7566 * TODO: track mappings and invalidate
7567 * single context requests appropriately
7569 case VMX_EPT_EXTENT_CONTEXT
:
7570 kvm_mmu_sync_roots(vcpu
);
7571 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7572 nested_vmx_succeed(vcpu
);
7579 skip_emulated_instruction(vcpu
);
7583 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7585 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7586 u32 vmx_instruction_info
;
7587 unsigned long type
, types
;
7589 struct x86_exception e
;
7592 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7593 SECONDARY_EXEC_ENABLE_VPID
) ||
7594 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7595 kvm_queue_exception(vcpu
, UD_VECTOR
);
7599 if (!nested_vmx_check_permission(vcpu
))
7602 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7603 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7605 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7606 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7608 if (type
>= 32 || !(types
& (1 << type
))) {
7609 nested_vmx_failValid(vcpu
,
7610 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7611 skip_emulated_instruction(vcpu
);
7615 /* according to the intel vmx instruction reference, the memory
7616 * operand is read even if it isn't needed (e.g., for type==global)
7618 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7619 vmx_instruction_info
, false, &gva
))
7621 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7623 kvm_inject_page_fault(vcpu
, &e
);
7628 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7629 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7630 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7632 nested_vmx_failValid(vcpu
,
7633 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7634 skip_emulated_instruction(vcpu
);
7638 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7642 skip_emulated_instruction(vcpu
);
7646 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7647 nested_vmx_succeed(vcpu
);
7649 skip_emulated_instruction(vcpu
);
7653 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7655 unsigned long exit_qualification
;
7657 trace_kvm_pml_full(vcpu
->vcpu_id
);
7659 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7662 * PML buffer FULL happened while executing iret from NMI,
7663 * "blocked by NMI" bit has to be set before next VM entry.
7665 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7666 cpu_has_virtual_nmis() &&
7667 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7668 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7669 GUEST_INTR_STATE_NMI
);
7672 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7673 * here.., and there's no userspace involvement needed for PML.
7678 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7680 kvm_lapic_expired_hv_timer(vcpu
);
7685 * The exit handlers return 1 if the exit was handled fully and guest execution
7686 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7687 * to be done to userspace and return 0.
7689 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7690 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7691 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7692 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7693 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7694 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7695 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7696 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7697 [EXIT_REASON_CPUID
] = handle_cpuid
,
7698 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7699 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7700 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7701 [EXIT_REASON_HLT
] = handle_halt
,
7702 [EXIT_REASON_INVD
] = handle_invd
,
7703 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7704 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7705 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7706 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7707 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7708 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7709 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7710 [EXIT_REASON_VMREAD
] = handle_vmread
,
7711 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7712 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7713 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7714 [EXIT_REASON_VMON
] = handle_vmon
,
7715 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7716 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7717 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7718 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7719 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7720 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7721 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7722 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7723 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7724 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7725 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7726 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7727 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7728 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7729 [EXIT_REASON_INVEPT
] = handle_invept
,
7730 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7731 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7732 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7733 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7734 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7737 static const int kvm_vmx_max_exit_handlers
=
7738 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7740 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7741 struct vmcs12
*vmcs12
)
7743 unsigned long exit_qualification
;
7744 gpa_t bitmap
, last_bitmap
;
7749 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7750 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7752 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7754 port
= exit_qualification
>> 16;
7755 size
= (exit_qualification
& 7) + 1;
7757 last_bitmap
= (gpa_t
)-1;
7762 bitmap
= vmcs12
->io_bitmap_a
;
7763 else if (port
< 0x10000)
7764 bitmap
= vmcs12
->io_bitmap_b
;
7767 bitmap
+= (port
& 0x7fff) / 8;
7769 if (last_bitmap
!= bitmap
)
7770 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7772 if (b
& (1 << (port
& 7)))
7777 last_bitmap
= bitmap
;
7784 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7785 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7786 * disinterest in the current event (read or write a specific MSR) by using an
7787 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7789 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7790 struct vmcs12
*vmcs12
, u32 exit_reason
)
7792 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7795 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7799 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7800 * for the four combinations of read/write and low/high MSR numbers.
7801 * First we need to figure out which of the four to use:
7803 bitmap
= vmcs12
->msr_bitmap
;
7804 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7806 if (msr_index
>= 0xc0000000) {
7807 msr_index
-= 0xc0000000;
7811 /* Then read the msr_index'th bit from this bitmap: */
7812 if (msr_index
< 1024*8) {
7814 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7816 return 1 & (b
>> (msr_index
& 7));
7818 return true; /* let L1 handle the wrong parameter */
7822 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7823 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7824 * intercept (via guest_host_mask etc.) the current event.
7826 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7827 struct vmcs12
*vmcs12
)
7829 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7830 int cr
= exit_qualification
& 15;
7831 int reg
= (exit_qualification
>> 8) & 15;
7832 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7834 switch ((exit_qualification
>> 4) & 3) {
7835 case 0: /* mov to cr */
7838 if (vmcs12
->cr0_guest_host_mask
&
7839 (val
^ vmcs12
->cr0_read_shadow
))
7843 if ((vmcs12
->cr3_target_count
>= 1 &&
7844 vmcs12
->cr3_target_value0
== val
) ||
7845 (vmcs12
->cr3_target_count
>= 2 &&
7846 vmcs12
->cr3_target_value1
== val
) ||
7847 (vmcs12
->cr3_target_count
>= 3 &&
7848 vmcs12
->cr3_target_value2
== val
) ||
7849 (vmcs12
->cr3_target_count
>= 4 &&
7850 vmcs12
->cr3_target_value3
== val
))
7852 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7856 if (vmcs12
->cr4_guest_host_mask
&
7857 (vmcs12
->cr4_read_shadow
^ val
))
7861 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7867 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7868 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7871 case 1: /* mov from cr */
7874 if (vmcs12
->cpu_based_vm_exec_control
&
7875 CPU_BASED_CR3_STORE_EXITING
)
7879 if (vmcs12
->cpu_based_vm_exec_control
&
7880 CPU_BASED_CR8_STORE_EXITING
)
7887 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7888 * cr0. Other attempted changes are ignored, with no exit.
7890 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7891 (val
^ vmcs12
->cr0_read_shadow
))
7893 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7894 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7903 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7904 * should handle it ourselves in L0 (and then continue L2). Only call this
7905 * when in is_guest_mode (L2).
7907 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7909 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7910 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7911 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7912 u32 exit_reason
= vmx
->exit_reason
;
7914 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7915 vmcs_readl(EXIT_QUALIFICATION
),
7916 vmx
->idt_vectoring_info
,
7918 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7921 if (vmx
->nested
.nested_run_pending
)
7924 if (unlikely(vmx
->fail
)) {
7925 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7926 vmcs_read32(VM_INSTRUCTION_ERROR
));
7930 switch (exit_reason
) {
7931 case EXIT_REASON_EXCEPTION_NMI
:
7932 if (!is_exception(intr_info
))
7934 else if (is_page_fault(intr_info
))
7936 else if (is_no_device(intr_info
) &&
7937 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7939 else if (is_debug(intr_info
) &&
7941 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7943 else if (is_breakpoint(intr_info
) &&
7944 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7946 return vmcs12
->exception_bitmap
&
7947 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7948 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7950 case EXIT_REASON_TRIPLE_FAULT
:
7952 case EXIT_REASON_PENDING_INTERRUPT
:
7953 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7954 case EXIT_REASON_NMI_WINDOW
:
7955 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7956 case EXIT_REASON_TASK_SWITCH
:
7958 case EXIT_REASON_CPUID
:
7959 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7962 case EXIT_REASON_HLT
:
7963 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7964 case EXIT_REASON_INVD
:
7966 case EXIT_REASON_INVLPG
:
7967 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7968 case EXIT_REASON_RDPMC
:
7969 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7970 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7971 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7972 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7973 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7974 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7975 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7976 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7977 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7979 * VMX instructions trap unconditionally. This allows L1 to
7980 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7983 case EXIT_REASON_CR_ACCESS
:
7984 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7985 case EXIT_REASON_DR_ACCESS
:
7986 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7987 case EXIT_REASON_IO_INSTRUCTION
:
7988 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7989 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
7990 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
7991 case EXIT_REASON_MSR_READ
:
7992 case EXIT_REASON_MSR_WRITE
:
7993 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7994 case EXIT_REASON_INVALID_STATE
:
7996 case EXIT_REASON_MWAIT_INSTRUCTION
:
7997 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7998 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7999 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8000 case EXIT_REASON_MONITOR_INSTRUCTION
:
8001 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8002 case EXIT_REASON_PAUSE_INSTRUCTION
:
8003 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8004 nested_cpu_has2(vmcs12
,
8005 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8006 case EXIT_REASON_MCE_DURING_VMENTRY
:
8008 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8009 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8010 case EXIT_REASON_APIC_ACCESS
:
8011 return nested_cpu_has2(vmcs12
,
8012 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8013 case EXIT_REASON_APIC_WRITE
:
8014 case EXIT_REASON_EOI_INDUCED
:
8015 /* apic_write and eoi_induced should exit unconditionally. */
8017 case EXIT_REASON_EPT_VIOLATION
:
8019 * L0 always deals with the EPT violation. If nested EPT is
8020 * used, and the nested mmu code discovers that the address is
8021 * missing in the guest EPT table (EPT12), the EPT violation
8022 * will be injected with nested_ept_inject_page_fault()
8025 case EXIT_REASON_EPT_MISCONFIG
:
8027 * L2 never uses directly L1's EPT, but rather L0's own EPT
8028 * table (shadow on EPT) or a merged EPT table that L0 built
8029 * (EPT on EPT). So any problems with the structure of the
8030 * table is L0's fault.
8033 case EXIT_REASON_WBINVD
:
8034 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8035 case EXIT_REASON_XSETBV
:
8037 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8039 * This should never happen, since it is not possible to
8040 * set XSS to a non-zero value---neither in L1 nor in L2.
8041 * If if it were, XSS would have to be checked against
8042 * the XSS exit bitmap in vmcs12.
8044 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8045 case EXIT_REASON_PREEMPTION_TIMER
:
8052 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8054 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8055 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8058 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8061 __free_page(vmx
->pml_pg
);
8066 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8068 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8072 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8074 /* Do nothing if PML buffer is empty */
8075 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8078 /* PML index always points to next available PML buffer entity */
8079 if (pml_idx
>= PML_ENTITY_NUM
)
8084 pml_buf
= page_address(vmx
->pml_pg
);
8085 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8088 gpa
= pml_buf
[pml_idx
];
8089 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8090 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8093 /* reset PML index */
8094 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8098 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8099 * Called before reporting dirty_bitmap to userspace.
8101 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8104 struct kvm_vcpu
*vcpu
;
8106 * We only need to kick vcpu out of guest mode here, as PML buffer
8107 * is flushed at beginning of all VMEXITs, and it's obvious that only
8108 * vcpus running in guest are possible to have unflushed GPAs in PML
8111 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8112 kvm_vcpu_kick(vcpu
);
8115 static void vmx_dump_sel(char *name
, uint32_t sel
)
8117 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8118 name
, vmcs_read32(sel
),
8119 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8120 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8121 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8124 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8126 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8127 name
, vmcs_read32(limit
),
8128 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8131 static void dump_vmcs(void)
8133 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8134 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8135 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8136 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8137 u32 secondary_exec_control
= 0;
8138 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8139 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8142 if (cpu_has_secondary_exec_ctrls())
8143 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8145 pr_err("*** Guest State ***\n");
8146 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8147 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8148 vmcs_readl(CR0_GUEST_HOST_MASK
));
8149 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8150 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8151 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8152 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8153 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8155 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8156 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8157 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8158 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8160 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8161 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8162 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8163 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8164 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8165 vmcs_readl(GUEST_SYSENTER_ESP
),
8166 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8167 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8168 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8169 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8170 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8171 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8172 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8173 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8174 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8175 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8176 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8177 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8178 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8179 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8180 efer
, vmcs_read64(GUEST_IA32_PAT
));
8181 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8182 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8183 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8184 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8185 pr_err("PerfGlobCtl = 0x%016llx\n",
8186 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8187 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8188 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8189 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8190 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8191 vmcs_read32(GUEST_ACTIVITY_STATE
));
8192 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8193 pr_err("InterruptStatus = %04x\n",
8194 vmcs_read16(GUEST_INTR_STATUS
));
8196 pr_err("*** Host State ***\n");
8197 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8198 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8199 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8200 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8201 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8202 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8203 vmcs_read16(HOST_TR_SELECTOR
));
8204 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8205 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8206 vmcs_readl(HOST_TR_BASE
));
8207 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8208 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8209 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8210 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8211 vmcs_readl(HOST_CR4
));
8212 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8213 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8214 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8215 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8216 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8217 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8218 vmcs_read64(HOST_IA32_EFER
),
8219 vmcs_read64(HOST_IA32_PAT
));
8220 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8221 pr_err("PerfGlobCtl = 0x%016llx\n",
8222 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8224 pr_err("*** Control State ***\n");
8225 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8226 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8227 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8228 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8229 vmcs_read32(EXCEPTION_BITMAP
),
8230 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8231 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8232 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8233 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8234 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8235 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8236 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8237 vmcs_read32(VM_EXIT_INTR_INFO
),
8238 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8239 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8240 pr_err(" reason=%08x qualification=%016lx\n",
8241 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8242 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8243 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8244 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8245 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8246 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8247 pr_err("TSC Multiplier = 0x%016llx\n",
8248 vmcs_read64(TSC_MULTIPLIER
));
8249 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8250 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8251 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8252 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8253 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8254 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8255 n
= vmcs_read32(CR3_TARGET_COUNT
);
8256 for (i
= 0; i
+ 1 < n
; i
+= 4)
8257 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8258 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8259 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8261 pr_err("CR3 target%u=%016lx\n",
8262 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8263 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8264 pr_err("PLE Gap=%08x Window=%08x\n",
8265 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8266 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8267 pr_err("Virtual processor ID = 0x%04x\n",
8268 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8272 * The guest has exited. See if we can fix it or if we need userspace
8275 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8277 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8278 u32 exit_reason
= vmx
->exit_reason
;
8279 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8281 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8284 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8285 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8286 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8287 * mode as if vcpus is in root mode, the PML buffer must has been
8291 vmx_flush_pml_buffer(vcpu
);
8293 /* If guest state is invalid, start emulating */
8294 if (vmx
->emulation_required
)
8295 return handle_invalid_guest_state(vcpu
);
8297 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8298 nested_vmx_vmexit(vcpu
, exit_reason
,
8299 vmcs_read32(VM_EXIT_INTR_INFO
),
8300 vmcs_readl(EXIT_QUALIFICATION
));
8304 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8306 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8307 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8312 if (unlikely(vmx
->fail
)) {
8313 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8314 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8315 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8321 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8322 * delivery event since it indicates guest is accessing MMIO.
8323 * The vm-exit can be triggered again after return to guest that
8324 * will cause infinite loop.
8326 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8327 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8328 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8329 exit_reason
!= EXIT_REASON_PML_FULL
&&
8330 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8331 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8332 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8333 vcpu
->run
->internal
.ndata
= 2;
8334 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8335 vcpu
->run
->internal
.data
[1] = exit_reason
;
8339 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8340 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8341 get_vmcs12(vcpu
))))) {
8342 if (vmx_interrupt_allowed(vcpu
)) {
8343 vmx
->soft_vnmi_blocked
= 0;
8344 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8345 vcpu
->arch
.nmi_pending
) {
8347 * This CPU don't support us in finding the end of an
8348 * NMI-blocked window if the guest runs with IRQs
8349 * disabled. So we pull the trigger after 1 s of
8350 * futile waiting, but inform the user about this.
8352 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8353 "state on VCPU %d after 1 s timeout\n",
8354 __func__
, vcpu
->vcpu_id
);
8355 vmx
->soft_vnmi_blocked
= 0;
8359 if (exit_reason
< kvm_vmx_max_exit_handlers
8360 && kvm_vmx_exit_handlers
[exit_reason
])
8361 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8363 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8364 kvm_queue_exception(vcpu
, UD_VECTOR
);
8369 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8371 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8373 if (is_guest_mode(vcpu
) &&
8374 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8377 if (irr
== -1 || tpr
< irr
) {
8378 vmcs_write32(TPR_THRESHOLD
, 0);
8382 vmcs_write32(TPR_THRESHOLD
, irr
);
8385 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8387 u32 sec_exec_control
;
8389 /* Postpone execution until vmcs01 is the current VMCS. */
8390 if (is_guest_mode(vcpu
)) {
8391 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8395 if (!cpu_has_vmx_virtualize_x2apic_mode())
8398 if (!cpu_need_tpr_shadow(vcpu
))
8401 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8404 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8405 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8407 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8408 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8410 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8412 vmx_set_msr_bitmap(vcpu
);
8415 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8417 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8420 * Currently we do not handle the nested case where L2 has an
8421 * APIC access page of its own; that page is still pinned.
8422 * Hence, we skip the case where the VCPU is in guest mode _and_
8423 * L1 prepared an APIC access page for L2.
8425 * For the case where L1 and L2 share the same APIC access page
8426 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8427 * in the vmcs12), this function will only update either the vmcs01
8428 * or the vmcs02. If the former, the vmcs02 will be updated by
8429 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8430 * the next L2->L1 exit.
8432 if (!is_guest_mode(vcpu
) ||
8433 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8434 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8435 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8438 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8446 status
= vmcs_read16(GUEST_INTR_STATUS
);
8448 if (max_isr
!= old
) {
8450 status
|= max_isr
<< 8;
8451 vmcs_write16(GUEST_INTR_STATUS
, status
);
8455 static void vmx_set_rvi(int vector
)
8463 status
= vmcs_read16(GUEST_INTR_STATUS
);
8464 old
= (u8
)status
& 0xff;
8465 if ((u8
)vector
!= old
) {
8467 status
|= (u8
)vector
;
8468 vmcs_write16(GUEST_INTR_STATUS
, status
);
8472 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8474 if (!is_guest_mode(vcpu
)) {
8475 vmx_set_rvi(max_irr
);
8483 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8486 if (nested_exit_on_intr(vcpu
))
8490 * Else, fall back to pre-APICv interrupt injection since L2
8491 * is run without virtual interrupt delivery.
8493 if (!kvm_event_needs_reinjection(vcpu
) &&
8494 vmx_interrupt_allowed(vcpu
)) {
8495 kvm_queue_interrupt(vcpu
, max_irr
, false);
8496 vmx_inject_irq(vcpu
);
8500 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8502 if (!kvm_vcpu_apicv_active(vcpu
))
8505 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8506 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8507 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8508 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8511 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8515 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8516 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8519 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8520 exit_intr_info
= vmx
->exit_intr_info
;
8522 /* Handle machine checks before interrupts are enabled */
8523 if (is_machine_check(exit_intr_info
))
8524 kvm_machine_check();
8526 /* We need to handle NMIs before interrupts are enabled */
8527 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8528 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8529 kvm_before_handle_nmi(&vmx
->vcpu
);
8531 kvm_after_handle_nmi(&vmx
->vcpu
);
8535 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8537 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8538 register void *__sp
asm(_ASM_SP
);
8540 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8541 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8542 unsigned int vector
;
8543 unsigned long entry
;
8545 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8546 #ifdef CONFIG_X86_64
8550 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8551 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8552 entry
= gate_offset(*desc
);
8554 #ifdef CONFIG_X86_64
8555 "mov %%" _ASM_SP
", %[sp]\n\t"
8556 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8561 __ASM_SIZE(push
) " $%c[cs]\n\t"
8562 "call *%[entry]\n\t"
8564 #ifdef CONFIG_X86_64
8570 [ss
]"i"(__KERNEL_DS
),
8571 [cs
]"i"(__KERNEL_CS
)
8576 static bool vmx_has_high_real_mode_segbase(void)
8578 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8581 static bool vmx_mpx_supported(void)
8583 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8584 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8587 static bool vmx_xsaves_supported(void)
8589 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8590 SECONDARY_EXEC_XSAVES
;
8593 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8598 bool idtv_info_valid
;
8600 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8602 if (cpu_has_virtual_nmis()) {
8603 if (vmx
->nmi_known_unmasked
)
8606 * Can't use vmx->exit_intr_info since we're not sure what
8607 * the exit reason is.
8609 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8610 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8611 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8613 * SDM 3: 27.7.1.2 (September 2008)
8614 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8615 * a guest IRET fault.
8616 * SDM 3: 23.2.2 (September 2008)
8617 * Bit 12 is undefined in any of the following cases:
8618 * If the VM exit sets the valid bit in the IDT-vectoring
8619 * information field.
8620 * If the VM exit is due to a double fault.
8622 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8623 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8624 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8625 GUEST_INTR_STATE_NMI
);
8627 vmx
->nmi_known_unmasked
=
8628 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8629 & GUEST_INTR_STATE_NMI
);
8630 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8631 vmx
->vnmi_blocked_time
+=
8632 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8635 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8636 u32 idt_vectoring_info
,
8637 int instr_len_field
,
8638 int error_code_field
)
8642 bool idtv_info_valid
;
8644 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8646 vcpu
->arch
.nmi_injected
= false;
8647 kvm_clear_exception_queue(vcpu
);
8648 kvm_clear_interrupt_queue(vcpu
);
8650 if (!idtv_info_valid
)
8653 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8655 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8656 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8659 case INTR_TYPE_NMI_INTR
:
8660 vcpu
->arch
.nmi_injected
= true;
8662 * SDM 3: 27.7.1.2 (September 2008)
8663 * Clear bit "block by NMI" before VM entry if a NMI
8666 vmx_set_nmi_mask(vcpu
, false);
8668 case INTR_TYPE_SOFT_EXCEPTION
:
8669 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8671 case INTR_TYPE_HARD_EXCEPTION
:
8672 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8673 u32 err
= vmcs_read32(error_code_field
);
8674 kvm_requeue_exception_e(vcpu
, vector
, err
);
8676 kvm_requeue_exception(vcpu
, vector
);
8678 case INTR_TYPE_SOFT_INTR
:
8679 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8681 case INTR_TYPE_EXT_INTR
:
8682 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8689 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8691 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8692 VM_EXIT_INSTRUCTION_LEN
,
8693 IDT_VECTORING_ERROR_CODE
);
8696 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8698 __vmx_complete_interrupts(vcpu
,
8699 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8700 VM_ENTRY_INSTRUCTION_LEN
,
8701 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8703 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8706 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8709 struct perf_guest_switch_msr
*msrs
;
8711 msrs
= perf_guest_get_msrs(&nr_msrs
);
8716 for (i
= 0; i
< nr_msrs
; i
++)
8717 if (msrs
[i
].host
== msrs
[i
].guest
)
8718 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8720 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8724 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8726 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8730 if (vmx
->hv_deadline_tsc
== -1)
8734 if (vmx
->hv_deadline_tsc
> tscl
)
8735 /* sure to be 32 bit only because checked on set_hv_timer */
8736 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8737 cpu_preemption_timer_multi
);
8741 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8744 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8747 unsigned long debugctlmsr
, cr4
;
8749 /* Record the guest's net vcpu time for enforced NMI injections. */
8750 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8751 vmx
->entry_time
= ktime_get();
8753 /* Don't enter VMX if guest state is invalid, let the exit handler
8754 start emulation until we arrive back to a valid state */
8755 if (vmx
->emulation_required
)
8758 if (vmx
->ple_window_dirty
) {
8759 vmx
->ple_window_dirty
= false;
8760 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8763 if (vmx
->nested
.sync_shadow_vmcs
) {
8764 copy_vmcs12_to_shadow(vmx
);
8765 vmx
->nested
.sync_shadow_vmcs
= false;
8768 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8769 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8770 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8771 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8773 cr4
= cr4_read_shadow();
8774 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8775 vmcs_writel(HOST_CR4
, cr4
);
8776 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8779 /* When single-stepping over STI and MOV SS, we must clear the
8780 * corresponding interruptibility bits in the guest state. Otherwise
8781 * vmentry fails as it then expects bit 14 (BS) in pending debug
8782 * exceptions being set, but that's not correct for the guest debugging
8784 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8785 vmx_set_interrupt_shadow(vcpu
, 0);
8787 if (vmx
->guest_pkru_valid
)
8788 __write_pkru(vmx
->guest_pkru
);
8790 atomic_switch_perf_msrs(vmx
);
8791 debugctlmsr
= get_debugctlmsr();
8793 vmx_arm_hv_timer(vcpu
);
8795 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8797 /* Store host registers */
8798 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8799 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8800 "push %%" _ASM_CX
" \n\t"
8801 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8803 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8804 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8806 /* Reload cr2 if changed */
8807 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8808 "mov %%cr2, %%" _ASM_DX
" \n\t"
8809 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8811 "mov %%" _ASM_AX
", %%cr2 \n\t"
8813 /* Check if vmlaunch of vmresume is needed */
8814 "cmpl $0, %c[launched](%0) \n\t"
8815 /* Load guest registers. Don't clobber flags. */
8816 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8817 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8818 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8819 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8820 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8821 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8822 #ifdef CONFIG_X86_64
8823 "mov %c[r8](%0), %%r8 \n\t"
8824 "mov %c[r9](%0), %%r9 \n\t"
8825 "mov %c[r10](%0), %%r10 \n\t"
8826 "mov %c[r11](%0), %%r11 \n\t"
8827 "mov %c[r12](%0), %%r12 \n\t"
8828 "mov %c[r13](%0), %%r13 \n\t"
8829 "mov %c[r14](%0), %%r14 \n\t"
8830 "mov %c[r15](%0), %%r15 \n\t"
8832 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8834 /* Enter guest mode */
8836 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8838 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8840 /* Save guest registers, load host registers, keep flags */
8841 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8843 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8844 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8845 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8846 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8847 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8848 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8849 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8850 #ifdef CONFIG_X86_64
8851 "mov %%r8, %c[r8](%0) \n\t"
8852 "mov %%r9, %c[r9](%0) \n\t"
8853 "mov %%r10, %c[r10](%0) \n\t"
8854 "mov %%r11, %c[r11](%0) \n\t"
8855 "mov %%r12, %c[r12](%0) \n\t"
8856 "mov %%r13, %c[r13](%0) \n\t"
8857 "mov %%r14, %c[r14](%0) \n\t"
8858 "mov %%r15, %c[r15](%0) \n\t"
8860 "mov %%cr2, %%" _ASM_AX
" \n\t"
8861 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8863 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8864 "setbe %c[fail](%0) \n\t"
8865 ".pushsection .rodata \n\t"
8866 ".global vmx_return \n\t"
8867 "vmx_return: " _ASM_PTR
" 2b \n\t"
8869 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8870 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8871 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8872 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8873 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8874 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8875 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8876 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8877 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8878 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8879 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8880 #ifdef CONFIG_X86_64
8881 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8882 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8883 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8884 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8885 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8886 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8887 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8888 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8890 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8891 [wordsize
]"i"(sizeof(ulong
))
8893 #ifdef CONFIG_X86_64
8894 , "rax", "rbx", "rdi", "rsi"
8895 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8897 , "eax", "ebx", "edi", "esi"
8901 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8903 update_debugctlmsr(debugctlmsr
);
8905 #ifndef CONFIG_X86_64
8907 * The sysexit path does not restore ds/es, so we must set them to
8908 * a reasonable value ourselves.
8910 * We can't defer this to vmx_load_host_state() since that function
8911 * may be executed in interrupt context, which saves and restore segments
8912 * around it, nullifying its effect.
8914 loadsegment(ds
, __USER_DS
);
8915 loadsegment(es
, __USER_DS
);
8918 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8919 | (1 << VCPU_EXREG_RFLAGS
)
8920 | (1 << VCPU_EXREG_PDPTR
)
8921 | (1 << VCPU_EXREG_SEGMENTS
)
8922 | (1 << VCPU_EXREG_CR3
));
8923 vcpu
->arch
.regs_dirty
= 0;
8925 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8927 vmx
->loaded_vmcs
->launched
= 1;
8929 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8932 * eager fpu is enabled if PKEY is supported and CR4 is switched
8933 * back on host, so it is safe to read guest PKRU from current
8936 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8937 vmx
->guest_pkru
= __read_pkru();
8938 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
8939 vmx
->guest_pkru_valid
= true;
8940 __write_pkru(vmx
->host_pkru
);
8942 vmx
->guest_pkru_valid
= false;
8946 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8947 * we did not inject a still-pending event to L1 now because of
8948 * nested_run_pending, we need to re-enable this bit.
8950 if (vmx
->nested
.nested_run_pending
)
8951 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8953 vmx
->nested
.nested_run_pending
= 0;
8955 vmx_complete_atomic_exit(vmx
);
8956 vmx_recover_nmi_blocking(vmx
);
8957 vmx_complete_interrupts(vmx
);
8960 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8962 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8965 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8969 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8971 vmx_vcpu_load(vcpu
, cpu
);
8977 * Ensure that the current vmcs of the logical processor is the
8978 * vmcs01 of the vcpu before calling free_nested().
8980 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
8982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8985 r
= vcpu_load(vcpu
);
8987 vmx_load_vmcs01(vcpu
);
8992 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8994 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8997 vmx_destroy_pml_buffer(vmx
);
8998 free_vpid(vmx
->vpid
);
8999 leave_guest_mode(vcpu
);
9000 vmx_free_vcpu_nested(vcpu
);
9001 free_loaded_vmcs(vmx
->loaded_vmcs
);
9002 kfree(vmx
->guest_msrs
);
9003 kvm_vcpu_uninit(vcpu
);
9004 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9007 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9010 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9014 return ERR_PTR(-ENOMEM
);
9016 vmx
->vpid
= allocate_vpid();
9018 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9025 * If PML is turned on, failure on enabling PML just results in failure
9026 * of creating the vcpu, therefore we can simplify PML logic (by
9027 * avoiding dealing with cases, such as enabling PML partially on vcpus
9028 * for the guest, etc.
9031 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9036 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9037 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9040 if (!vmx
->guest_msrs
)
9043 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9044 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9045 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9046 if (!vmx
->loaded_vmcs
->vmcs
)
9049 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9050 loaded_vmcs_init(vmx
->loaded_vmcs
);
9055 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9056 vmx
->vcpu
.cpu
= cpu
;
9057 err
= vmx_vcpu_setup(vmx
);
9058 vmx_vcpu_put(&vmx
->vcpu
);
9062 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9063 err
= alloc_apic_access_page(kvm
);
9069 if (!kvm
->arch
.ept_identity_map_addr
)
9070 kvm
->arch
.ept_identity_map_addr
=
9071 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9072 err
= init_rmode_identity_map(kvm
);
9078 nested_vmx_setup_ctls_msrs(vmx
);
9079 vmx
->nested
.vpid02
= allocate_vpid();
9082 vmx
->nested
.posted_intr_nv
= -1;
9083 vmx
->nested
.current_vmptr
= -1ull;
9084 vmx
->nested
.current_vmcs12
= NULL
;
9086 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9091 free_vpid(vmx
->nested
.vpid02
);
9092 free_loaded_vmcs(vmx
->loaded_vmcs
);
9094 kfree(vmx
->guest_msrs
);
9096 vmx_destroy_pml_buffer(vmx
);
9098 kvm_vcpu_uninit(&vmx
->vcpu
);
9100 free_vpid(vmx
->vpid
);
9101 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9102 return ERR_PTR(err
);
9105 static void __init
vmx_check_processor_compat(void *rtn
)
9107 struct vmcs_config vmcs_conf
;
9110 if (setup_vmcs_config(&vmcs_conf
) < 0)
9112 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9113 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9114 smp_processor_id());
9119 static int get_ept_level(void)
9121 return VMX_EPT_DEFAULT_GAW
+ 1;
9124 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9129 /* For VT-d and EPT combination
9130 * 1. MMIO: always map as UC
9132 * a. VT-d without snooping control feature: can't guarantee the
9133 * result, try to trust guest.
9134 * b. VT-d with snooping control feature: snooping control feature of
9135 * VT-d engine can guarantee the cache correctness. Just set it
9136 * to WB to keep consistent with host. So the same as item 3.
9137 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9138 * consistent with host MTRR
9141 cache
= MTRR_TYPE_UNCACHABLE
;
9145 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9146 ipat
= VMX_EPT_IPAT_BIT
;
9147 cache
= MTRR_TYPE_WRBACK
;
9151 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9152 ipat
= VMX_EPT_IPAT_BIT
;
9153 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9154 cache
= MTRR_TYPE_WRBACK
;
9156 cache
= MTRR_TYPE_UNCACHABLE
;
9160 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9163 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9166 static int vmx_get_lpage_level(void)
9168 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9169 return PT_DIRECTORY_LEVEL
;
9171 /* For shadow and EPT supported 1GB page */
9172 return PT_PDPE_LEVEL
;
9175 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9178 * These bits in the secondary execution controls field
9179 * are dynamic, the others are mostly based on the hypervisor
9180 * architecture and the guest's CPUID. Do not touch the
9184 SECONDARY_EXEC_SHADOW_VMCS
|
9185 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9186 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9188 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9190 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9191 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9194 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9196 struct kvm_cpuid_entry2
*best
;
9197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9198 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9200 if (vmx_rdtscp_supported()) {
9201 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9202 if (!rdtscp_enabled
)
9203 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9207 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9208 SECONDARY_EXEC_RDTSCP
;
9210 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9211 ~SECONDARY_EXEC_RDTSCP
;
9215 /* Exposing INVPCID only when PCID is exposed */
9216 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9217 if (vmx_invpcid_supported() &&
9218 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9219 !guest_cpuid_has_pcid(vcpu
))) {
9220 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9223 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9226 if (cpu_has_secondary_exec_ctrls())
9227 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9229 if (nested_vmx_allowed(vcpu
))
9230 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9231 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9233 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9234 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9237 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9239 if (func
== 1 && nested
)
9240 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9243 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9244 struct x86_exception
*fault
)
9246 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9249 if (fault
->error_code
& PFERR_RSVD_MASK
)
9250 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9252 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9253 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9254 vmcs12
->guest_physical_address
= fault
->address
;
9257 /* Callbacks for nested_ept_init_mmu_context: */
9259 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9261 /* return the page table to be shadowed - in our case, EPT12 */
9262 return get_vmcs12(vcpu
)->ept_pointer
;
9265 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9267 WARN_ON(mmu_is_nested(vcpu
));
9268 kvm_init_shadow_ept_mmu(vcpu
,
9269 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9270 VMX_EPT_EXECUTE_ONLY_BIT
);
9271 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9272 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9273 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9275 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9278 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9280 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9283 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9286 bool inequality
, bit
;
9288 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9290 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9291 vmcs12
->page_fault_error_code_match
;
9292 return inequality
^ bit
;
9295 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9296 struct x86_exception
*fault
)
9298 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9300 WARN_ON(!is_guest_mode(vcpu
));
9302 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9303 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9304 vmcs_read32(VM_EXIT_INTR_INFO
),
9305 vmcs_readl(EXIT_QUALIFICATION
));
9307 kvm_inject_page_fault(vcpu
, fault
);
9310 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9311 struct vmcs12
*vmcs12
)
9313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9314 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9316 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9317 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9318 vmcs12
->apic_access_addr
>> maxphyaddr
)
9322 * Translate L1 physical address to host physical
9323 * address for vmcs02. Keep the page pinned, so this
9324 * physical address remains valid. We keep a reference
9325 * to it so we can release it later.
9327 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9328 nested_release_page(vmx
->nested
.apic_access_page
);
9329 vmx
->nested
.apic_access_page
=
9330 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9333 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9334 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9335 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9338 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9339 nested_release_page(vmx
->nested
.virtual_apic_page
);
9340 vmx
->nested
.virtual_apic_page
=
9341 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9344 * Failing the vm entry is _not_ what the processor does
9345 * but it's basically the only possibility we have.
9346 * We could still enter the guest if CR8 load exits are
9347 * enabled, CR8 store exits are enabled, and virtualize APIC
9348 * access is disabled; in this case the processor would never
9349 * use the TPR shadow and we could simply clear the bit from
9350 * the execution control. But such a configuration is useless,
9351 * so let's keep the code simple.
9353 if (!vmx
->nested
.virtual_apic_page
)
9357 if (nested_cpu_has_posted_intr(vmcs12
)) {
9358 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9359 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9362 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9363 kunmap(vmx
->nested
.pi_desc_page
);
9364 nested_release_page(vmx
->nested
.pi_desc_page
);
9366 vmx
->nested
.pi_desc_page
=
9367 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9368 if (!vmx
->nested
.pi_desc_page
)
9371 vmx
->nested
.pi_desc
=
9372 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9373 if (!vmx
->nested
.pi_desc
) {
9374 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9377 vmx
->nested
.pi_desc
=
9378 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9379 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9386 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9388 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9389 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9391 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9394 /* Make sure short timeouts reliably trigger an immediate vmexit.
9395 * hrtimer_start does not guarantee this. */
9396 if (preemption_timeout
<= 1) {
9397 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9401 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9402 preemption_timeout
*= 1000000;
9403 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9404 hrtimer_start(&vmx
->nested
.preemption_timer
,
9405 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9408 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9409 struct vmcs12
*vmcs12
)
9414 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9417 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9421 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9423 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9424 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9431 * Merge L0's and L1's MSR bitmap, return false to indicate that
9432 * we do not use the hardware.
9434 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9435 struct vmcs12
*vmcs12
)
9439 unsigned long *msr_bitmap_l1
;
9440 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9442 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9443 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9446 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9451 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9452 if (!msr_bitmap_l1
) {
9453 nested_release_page_clean(page
);
9458 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9460 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9461 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9462 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9463 nested_vmx_disable_intercept_for_msr(
9464 msr_bitmap_l1
, msr_bitmap_l0
,
9467 nested_vmx_disable_intercept_for_msr(
9468 msr_bitmap_l1
, msr_bitmap_l0
,
9469 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9470 MSR_TYPE_R
| MSR_TYPE_W
);
9472 if (nested_cpu_has_vid(vmcs12
)) {
9473 nested_vmx_disable_intercept_for_msr(
9474 msr_bitmap_l1
, msr_bitmap_l0
,
9475 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9477 nested_vmx_disable_intercept_for_msr(
9478 msr_bitmap_l1
, msr_bitmap_l0
,
9479 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9484 nested_release_page_clean(page
);
9489 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9490 struct vmcs12
*vmcs12
)
9492 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9493 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9494 !nested_cpu_has_vid(vmcs12
) &&
9495 !nested_cpu_has_posted_intr(vmcs12
))
9499 * If virtualize x2apic mode is enabled,
9500 * virtualize apic access must be disabled.
9502 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9503 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9507 * If virtual interrupt delivery is enabled,
9508 * we must exit on external interrupts.
9510 if (nested_cpu_has_vid(vmcs12
) &&
9511 !nested_exit_on_intr(vcpu
))
9515 * bits 15:8 should be zero in posted_intr_nv,
9516 * the descriptor address has been already checked
9517 * in nested_get_vmcs12_pages.
9519 if (nested_cpu_has_posted_intr(vmcs12
) &&
9520 (!nested_cpu_has_vid(vmcs12
) ||
9521 !nested_exit_intr_ack_set(vcpu
) ||
9522 vmcs12
->posted_intr_nv
& 0xff00))
9525 /* tpr shadow is needed by all apicv features. */
9526 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9532 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9533 unsigned long count_field
,
9534 unsigned long addr_field
)
9539 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9540 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9546 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9547 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9548 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9549 pr_debug_ratelimited(
9550 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9551 addr_field
, maxphyaddr
, count
, addr
);
9557 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9558 struct vmcs12
*vmcs12
)
9560 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9561 vmcs12
->vm_exit_msr_store_count
== 0 &&
9562 vmcs12
->vm_entry_msr_load_count
== 0)
9563 return 0; /* Fast path */
9564 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9565 VM_EXIT_MSR_LOAD_ADDR
) ||
9566 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9567 VM_EXIT_MSR_STORE_ADDR
) ||
9568 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9569 VM_ENTRY_MSR_LOAD_ADDR
))
9574 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9575 struct vmx_msr_entry
*e
)
9577 /* x2APIC MSR accesses are not allowed */
9578 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9580 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9581 e
->index
== MSR_IA32_UCODE_REV
)
9583 if (e
->reserved
!= 0)
9588 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9589 struct vmx_msr_entry
*e
)
9591 if (e
->index
== MSR_FS_BASE
||
9592 e
->index
== MSR_GS_BASE
||
9593 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9594 nested_vmx_msr_check_common(vcpu
, e
))
9599 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9600 struct vmx_msr_entry
*e
)
9602 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9603 nested_vmx_msr_check_common(vcpu
, e
))
9609 * Load guest's/host's msr at nested entry/exit.
9610 * return 0 for success, entry index for failure.
9612 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9615 struct vmx_msr_entry e
;
9616 struct msr_data msr
;
9618 msr
.host_initiated
= false;
9619 for (i
= 0; i
< count
; i
++) {
9620 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9622 pr_debug_ratelimited(
9623 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9624 __func__
, i
, gpa
+ i
* sizeof(e
));
9627 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9628 pr_debug_ratelimited(
9629 "%s check failed (%u, 0x%x, 0x%x)\n",
9630 __func__
, i
, e
.index
, e
.reserved
);
9633 msr
.index
= e
.index
;
9635 if (kvm_set_msr(vcpu
, &msr
)) {
9636 pr_debug_ratelimited(
9637 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9638 __func__
, i
, e
.index
, e
.value
);
9647 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9650 struct vmx_msr_entry e
;
9652 for (i
= 0; i
< count
; i
++) {
9653 struct msr_data msr_info
;
9654 if (kvm_vcpu_read_guest(vcpu
,
9655 gpa
+ i
* sizeof(e
),
9656 &e
, 2 * sizeof(u32
))) {
9657 pr_debug_ratelimited(
9658 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9659 __func__
, i
, gpa
+ i
* sizeof(e
));
9662 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9663 pr_debug_ratelimited(
9664 "%s check failed (%u, 0x%x, 0x%x)\n",
9665 __func__
, i
, e
.index
, e
.reserved
);
9668 msr_info
.host_initiated
= false;
9669 msr_info
.index
= e
.index
;
9670 if (kvm_get_msr(vcpu
, &msr_info
)) {
9671 pr_debug_ratelimited(
9672 "%s cannot read MSR (%u, 0x%x)\n",
9673 __func__
, i
, e
.index
);
9676 if (kvm_vcpu_write_guest(vcpu
,
9677 gpa
+ i
* sizeof(e
) +
9678 offsetof(struct vmx_msr_entry
, value
),
9679 &msr_info
.data
, sizeof(msr_info
.data
))) {
9680 pr_debug_ratelimited(
9681 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9682 __func__
, i
, e
.index
, msr_info
.data
);
9690 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9691 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9692 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9693 * guest in a way that will both be appropriate to L1's requests, and our
9694 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9695 * function also has additional necessary side-effects, like setting various
9696 * vcpu->arch fields.
9698 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9700 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9703 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9704 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9705 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9706 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9707 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9708 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9709 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9710 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9711 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9712 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9713 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9714 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9715 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9716 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9717 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9718 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9719 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9720 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9721 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9722 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9723 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9724 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9725 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9726 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9727 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9728 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9729 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9730 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9731 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9732 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9733 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9734 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9735 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9736 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9737 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9738 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9740 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9741 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9742 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9744 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9745 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9747 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9748 vmcs12
->vm_entry_intr_info_field
);
9749 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9750 vmcs12
->vm_entry_exception_error_code
);
9751 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9752 vmcs12
->vm_entry_instruction_len
);
9753 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9754 vmcs12
->guest_interruptibility_info
);
9755 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9756 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9757 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9758 vmcs12
->guest_pending_dbg_exceptions
);
9759 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9760 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9762 if (nested_cpu_has_xsaves(vmcs12
))
9763 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9764 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9766 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9768 /* Preemption timer setting is only taken from vmcs01. */
9769 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9770 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9771 if (vmx
->hv_deadline_tsc
== -1)
9772 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9774 /* Posted interrupts setting is only taken from vmcs12. */
9775 if (nested_cpu_has_posted_intr(vmcs12
)) {
9777 * Note that we use L0's vector here and in
9778 * vmx_deliver_nested_posted_interrupt.
9780 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9781 vmx
->nested
.pi_pending
= false;
9782 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9783 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9784 page_to_phys(vmx
->nested
.pi_desc_page
) +
9785 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9788 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9790 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9792 vmx
->nested
.preemption_timer_expired
= false;
9793 if (nested_cpu_has_preemption_timer(vmcs12
))
9794 vmx_start_preemption_timer(vcpu
);
9797 * Whether page-faults are trapped is determined by a combination of
9798 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9799 * If enable_ept, L0 doesn't care about page faults and we should
9800 * set all of these to L1's desires. However, if !enable_ept, L0 does
9801 * care about (at least some) page faults, and because it is not easy
9802 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9803 * to exit on each and every L2 page fault. This is done by setting
9804 * MASK=MATCH=0 and (see below) EB.PF=1.
9805 * Note that below we don't need special code to set EB.PF beyond the
9806 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9807 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9808 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9810 * A problem with this approach (when !enable_ept) is that L1 may be
9811 * injected with more page faults than it asked for. This could have
9812 * caused problems, but in practice existing hypervisors don't care.
9813 * To fix this, we will need to emulate the PFEC checking (on the L1
9814 * page tables), using walk_addr(), when injecting PFs to L1.
9816 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9817 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9818 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9819 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9821 if (cpu_has_secondary_exec_ctrls()) {
9822 exec_control
= vmx_secondary_exec_control(vmx
);
9824 /* Take the following fields only from vmcs12 */
9825 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9826 SECONDARY_EXEC_RDTSCP
|
9827 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9828 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
9829 if (nested_cpu_has(vmcs12
,
9830 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9831 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9833 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9835 * If translation failed, no matter: This feature asks
9836 * to exit when accessing the given address, and if it
9837 * can never be accessed, this feature won't do
9840 if (!vmx
->nested
.apic_access_page
)
9842 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9844 vmcs_write64(APIC_ACCESS_ADDR
,
9845 page_to_phys(vmx
->nested
.apic_access_page
));
9846 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9847 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9849 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9850 kvm_vcpu_reload_apic_access_page(vcpu
);
9853 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9854 vmcs_write64(EOI_EXIT_BITMAP0
,
9855 vmcs12
->eoi_exit_bitmap0
);
9856 vmcs_write64(EOI_EXIT_BITMAP1
,
9857 vmcs12
->eoi_exit_bitmap1
);
9858 vmcs_write64(EOI_EXIT_BITMAP2
,
9859 vmcs12
->eoi_exit_bitmap2
);
9860 vmcs_write64(EOI_EXIT_BITMAP3
,
9861 vmcs12
->eoi_exit_bitmap3
);
9862 vmcs_write16(GUEST_INTR_STATUS
,
9863 vmcs12
->guest_intr_status
);
9866 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9871 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9872 * Some constant fields are set here by vmx_set_constant_host_state().
9873 * Other fields are different per CPU, and will be set later when
9874 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9876 vmx_set_constant_host_state(vmx
);
9879 * Set the MSR load/store lists to match L0's settings.
9881 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
9882 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
9883 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
9884 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
9885 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
9888 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9889 * entry, but only if the current (host) sp changed from the value
9890 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9891 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9892 * here we just force the write to happen on entry.
9896 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9897 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9898 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9899 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9900 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9902 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9903 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9904 page_to_phys(vmx
->nested
.virtual_apic_page
));
9905 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9908 if (cpu_has_vmx_msr_bitmap() &&
9909 exec_control
& CPU_BASED_USE_MSR_BITMAPS
&&
9910 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9911 ; /* MSR_BITMAP will be set by following vmx_set_efer. */
9913 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9916 * Merging of IO bitmap not currently supported.
9917 * Rather, exit every time.
9919 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9920 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9922 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9924 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9925 * bitwise-or of what L1 wants to trap for L2, and what we want to
9926 * trap. Note that CR0.TS also needs updating - we do this later.
9928 update_exception_bitmap(vcpu
);
9929 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9930 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9932 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9933 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9934 * bits are further modified by vmx_set_efer() below.
9936 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9938 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9939 * emulated by vmx_set_efer(), below.
9941 vm_entry_controls_init(vmx
,
9942 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9943 ~VM_ENTRY_IA32E_MODE
) |
9944 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9946 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9947 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9948 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9949 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9950 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9953 set_cr4_guest_host_mask(vmx
);
9955 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9956 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9958 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9959 vmcs_write64(TSC_OFFSET
,
9960 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
9962 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
9963 if (kvm_has_tsc_control
)
9964 decache_tsc_multiplier(vmx
);
9968 * There is no direct mapping between vpid02 and vpid12, the
9969 * vpid02 is per-vCPU for L0 and reused while the value of
9970 * vpid12 is changed w/ one invvpid during nested vmentry.
9971 * The vpid12 is allocated by L1 for L2, so it will not
9972 * influence global bitmap(for vpid01 and vpid02 allocation)
9973 * even if spawn a lot of nested vCPUs.
9975 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9976 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9977 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9978 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9979 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9982 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9983 vmx_flush_tlb(vcpu
);
9988 if (nested_cpu_has_ept(vmcs12
)) {
9989 kvm_mmu_unload(vcpu
);
9990 nested_ept_init_mmu_context(vcpu
);
9993 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9994 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9995 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9996 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9998 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9999 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10000 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10003 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
10004 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
10005 * The CR0_READ_SHADOW is what L2 should have expected to read given
10006 * the specifications by L1; It's not enough to take
10007 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10008 * have more bits than L1 expected.
10010 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10011 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10013 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10014 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10016 /* shadow page tables on either EPT or shadow page tables */
10017 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
10018 kvm_mmu_reset_context(vcpu
);
10021 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10024 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10027 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10028 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10029 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10030 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10033 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10034 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10038 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10039 * for running an L2 nested guest.
10041 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10043 struct vmcs12
*vmcs12
;
10044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10046 struct loaded_vmcs
*vmcs02
;
10050 if (!nested_vmx_check_permission(vcpu
) ||
10051 !nested_vmx_check_vmcs12(vcpu
))
10054 skip_emulated_instruction(vcpu
);
10055 vmcs12
= get_vmcs12(vcpu
);
10057 if (enable_shadow_vmcs
)
10058 copy_shadow_to_vmcs12(vmx
);
10061 * The nested entry process starts with enforcing various prerequisites
10062 * on vmcs12 as required by the Intel SDM, and act appropriately when
10063 * they fail: As the SDM explains, some conditions should cause the
10064 * instruction to fail, while others will cause the instruction to seem
10065 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10066 * To speed up the normal (success) code path, we should avoid checking
10067 * for misconfigurations which will anyway be caught by the processor
10068 * when using the merged vmcs02.
10070 if (vmcs12
->launch_state
== launch
) {
10071 nested_vmx_failValid(vcpu
,
10072 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10073 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10077 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10078 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
10079 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10083 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
10084 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10088 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
10089 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10093 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
10094 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10098 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
10099 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10103 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10104 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
10105 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10106 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10107 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10108 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10109 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10110 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10111 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10112 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10113 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
10114 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10115 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10116 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
10117 vmx
->nested
.nested_vmx_entry_ctls_high
))
10119 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
10123 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
10124 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10125 nested_vmx_failValid(vcpu
,
10126 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
10130 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10131 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
10132 nested_vmx_entry_failure(vcpu
, vmcs12
,
10133 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10136 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
10137 nested_vmx_entry_failure(vcpu
, vmcs12
,
10138 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
10143 * If the load IA32_EFER VM-entry control is 1, the following checks
10144 * are performed on the field for the IA32_EFER MSR:
10145 * - Bits reserved in the IA32_EFER MSR must be 0.
10146 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10147 * the IA-32e mode guest VM-exit control. It must also be identical
10148 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10151 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10152 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10153 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10154 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10155 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10156 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10157 nested_vmx_entry_failure(vcpu
, vmcs12
,
10158 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10164 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10165 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10166 * the values of the LMA and LME bits in the field must each be that of
10167 * the host address-space size VM-exit control.
10169 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10170 ia32e
= (vmcs12
->vm_exit_controls
&
10171 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10172 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10173 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10174 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10175 nested_vmx_entry_failure(vcpu
, vmcs12
,
10176 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10182 * We're finally done with prerequisite checking, and can start with
10183 * the nested entry.
10186 vmcs02
= nested_get_current_vmcs02(vmx
);
10190 enter_guest_mode(vcpu
);
10192 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10193 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10196 vmx
->loaded_vmcs
= vmcs02
;
10197 vmx_vcpu_put(vcpu
);
10198 vmx_vcpu_load(vcpu
, cpu
);
10202 vmx_segment_cache_clear(vmx
);
10204 prepare_vmcs02(vcpu
, vmcs12
);
10206 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10207 vmcs12
->vm_entry_msr_load_addr
,
10208 vmcs12
->vm_entry_msr_load_count
);
10209 if (msr_entry_idx
) {
10210 leave_guest_mode(vcpu
);
10211 vmx_load_vmcs01(vcpu
);
10212 nested_vmx_entry_failure(vcpu
, vmcs12
,
10213 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10217 vmcs12
->launch_state
= 1;
10219 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10220 return kvm_vcpu_halt(vcpu
);
10222 vmx
->nested
.nested_run_pending
= 1;
10225 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10226 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10227 * returned as far as L1 is concerned. It will only return (and set
10228 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10234 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10235 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10236 * This function returns the new value we should put in vmcs12.guest_cr0.
10237 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10238 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10239 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10240 * didn't trap the bit, because if L1 did, so would L0).
10241 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10242 * been modified by L2, and L1 knows it. So just leave the old value of
10243 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10244 * isn't relevant, because if L0 traps this bit it can set it to anything.
10245 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10246 * changed these bits, and therefore they need to be updated, but L0
10247 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10248 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10250 static inline unsigned long
10251 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10254 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10255 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10256 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10257 vcpu
->arch
.cr0_guest_owned_bits
));
10260 static inline unsigned long
10261 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10264 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10265 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10266 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10267 vcpu
->arch
.cr4_guest_owned_bits
));
10270 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10271 struct vmcs12
*vmcs12
)
10276 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10277 nr
= vcpu
->arch
.exception
.nr
;
10278 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10280 if (kvm_exception_is_soft(nr
)) {
10281 vmcs12
->vm_exit_instruction_len
=
10282 vcpu
->arch
.event_exit_inst_len
;
10283 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10285 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10287 if (vcpu
->arch
.exception
.has_error_code
) {
10288 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10289 vmcs12
->idt_vectoring_error_code
=
10290 vcpu
->arch
.exception
.error_code
;
10293 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10294 } else if (vcpu
->arch
.nmi_injected
) {
10295 vmcs12
->idt_vectoring_info_field
=
10296 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10297 } else if (vcpu
->arch
.interrupt
.pending
) {
10298 nr
= vcpu
->arch
.interrupt
.nr
;
10299 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10301 if (vcpu
->arch
.interrupt
.soft
) {
10302 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10303 vmcs12
->vm_entry_instruction_len
=
10304 vcpu
->arch
.event_exit_inst_len
;
10306 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10308 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10312 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10314 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10316 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10317 vmx
->nested
.preemption_timer_expired
) {
10318 if (vmx
->nested
.nested_run_pending
)
10320 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10324 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10325 if (vmx
->nested
.nested_run_pending
||
10326 vcpu
->arch
.interrupt
.pending
)
10328 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10329 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10330 INTR_INFO_VALID_MASK
, 0);
10332 * The NMI-triggered VM exit counts as injection:
10333 * clear this one and block further NMIs.
10335 vcpu
->arch
.nmi_pending
= 0;
10336 vmx_set_nmi_mask(vcpu
, true);
10340 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10341 nested_exit_on_intr(vcpu
)) {
10342 if (vmx
->nested
.nested_run_pending
)
10344 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10348 return vmx_complete_nested_posted_interrupt(vcpu
);
10351 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10353 ktime_t remaining
=
10354 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10357 if (ktime_to_ns(remaining
) <= 0)
10360 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10361 do_div(value
, 1000000);
10362 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10366 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10367 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10368 * and this function updates it to reflect the changes to the guest state while
10369 * L2 was running (and perhaps made some exits which were handled directly by L0
10370 * without going back to L1), and to reflect the exit reason.
10371 * Note that we do not have to copy here all VMCS fields, just those that
10372 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10373 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10374 * which already writes to vmcs12 directly.
10376 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10377 u32 exit_reason
, u32 exit_intr_info
,
10378 unsigned long exit_qualification
)
10380 /* update guest state fields: */
10381 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10382 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10384 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10385 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10386 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10388 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10389 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10390 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10391 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10392 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10393 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10394 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10395 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10396 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10397 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10398 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10399 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10400 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10401 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10402 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10403 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10404 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10405 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10406 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10407 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10408 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10409 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10410 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10411 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10412 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10413 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10414 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10415 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10416 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10417 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10418 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10419 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10420 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10421 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10422 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10423 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10425 vmcs12
->guest_interruptibility_info
=
10426 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10427 vmcs12
->guest_pending_dbg_exceptions
=
10428 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10429 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10430 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10432 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10434 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10435 if (vmcs12
->vm_exit_controls
&
10436 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10437 vmcs12
->vmx_preemption_timer_value
=
10438 vmx_get_preemption_timer_value(vcpu
);
10439 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10443 * In some cases (usually, nested EPT), L2 is allowed to change its
10444 * own CR3 without exiting. If it has changed it, we must keep it.
10445 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10446 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10448 * Additionally, restore L2's PDPTR to vmcs12.
10451 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10452 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10453 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10454 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10455 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10458 if (nested_cpu_has_ept(vmcs12
))
10459 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10461 if (nested_cpu_has_vid(vmcs12
))
10462 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10464 vmcs12
->vm_entry_controls
=
10465 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10466 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10468 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10469 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10470 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10473 /* TODO: These cannot have changed unless we have MSR bitmaps and
10474 * the relevant bit asks not to trap the change */
10475 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10476 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10477 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10478 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10479 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10480 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10481 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10482 if (kvm_mpx_supported())
10483 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10484 if (nested_cpu_has_xsaves(vmcs12
))
10485 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10487 /* update exit information fields: */
10489 vmcs12
->vm_exit_reason
= exit_reason
;
10490 vmcs12
->exit_qualification
= exit_qualification
;
10492 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10493 if ((vmcs12
->vm_exit_intr_info
&
10494 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10495 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10496 vmcs12
->vm_exit_intr_error_code
=
10497 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10498 vmcs12
->idt_vectoring_info_field
= 0;
10499 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10500 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10502 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10503 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10504 * instead of reading the real value. */
10505 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10508 * Transfer the event that L0 or L1 may wanted to inject into
10509 * L2 to IDT_VECTORING_INFO_FIELD.
10511 vmcs12_save_pending_event(vcpu
, vmcs12
);
10515 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10516 * preserved above and would only end up incorrectly in L1.
10518 vcpu
->arch
.nmi_injected
= false;
10519 kvm_clear_exception_queue(vcpu
);
10520 kvm_clear_interrupt_queue(vcpu
);
10524 * A part of what we need to when the nested L2 guest exits and we want to
10525 * run its L1 parent, is to reset L1's guest state to the host state specified
10527 * This function is to be called not only on normal nested exit, but also on
10528 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10529 * Failures During or After Loading Guest State").
10530 * This function should be called when the active VMCS is L1's (vmcs01).
10532 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10533 struct vmcs12
*vmcs12
)
10535 struct kvm_segment seg
;
10537 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10538 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10539 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10540 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10542 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10543 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10545 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10546 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10547 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10549 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10550 * actually changed, because it depends on the current state of
10551 * fpu_active (which may have changed).
10552 * Note that vmx_set_cr0 refers to efer set above.
10554 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10556 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10557 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10558 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10560 update_exception_bitmap(vcpu
);
10561 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10562 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10565 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10566 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10568 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10569 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10571 nested_ept_uninit_mmu_context(vcpu
);
10573 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10574 kvm_mmu_reset_context(vcpu
);
10577 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10581 * Trivially support vpid by letting L2s share their parent
10582 * L1's vpid. TODO: move to a more elaborate solution, giving
10583 * each L2 its own vpid and exposing the vpid feature to L1.
10585 vmx_flush_tlb(vcpu
);
10589 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10590 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10591 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10592 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10593 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10595 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10596 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10597 vmcs_write64(GUEST_BNDCFGS
, 0);
10599 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10600 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10601 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10603 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10604 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10605 vmcs12
->host_ia32_perf_global_ctrl
);
10607 /* Set L1 segment info according to Intel SDM
10608 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10609 seg
= (struct kvm_segment
) {
10611 .limit
= 0xFFFFFFFF,
10612 .selector
= vmcs12
->host_cs_selector
,
10618 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10622 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10623 seg
= (struct kvm_segment
) {
10625 .limit
= 0xFFFFFFFF,
10632 seg
.selector
= vmcs12
->host_ds_selector
;
10633 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10634 seg
.selector
= vmcs12
->host_es_selector
;
10635 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10636 seg
.selector
= vmcs12
->host_ss_selector
;
10637 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10638 seg
.selector
= vmcs12
->host_fs_selector
;
10639 seg
.base
= vmcs12
->host_fs_base
;
10640 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10641 seg
.selector
= vmcs12
->host_gs_selector
;
10642 seg
.base
= vmcs12
->host_gs_base
;
10643 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10644 seg
= (struct kvm_segment
) {
10645 .base
= vmcs12
->host_tr_base
,
10647 .selector
= vmcs12
->host_tr_selector
,
10651 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10653 kvm_set_dr(vcpu
, 7, 0x400);
10654 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10656 if (cpu_has_vmx_msr_bitmap())
10657 vmx_set_msr_bitmap(vcpu
);
10659 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10660 vmcs12
->vm_exit_msr_load_count
))
10661 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10665 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10666 * and modify vmcs12 to make it see what it would expect to see there if
10667 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10669 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10670 u32 exit_intr_info
,
10671 unsigned long exit_qualification
)
10673 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10674 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10675 u32 vm_inst_error
= 0;
10677 /* trying to cancel vmlaunch/vmresume is a bug */
10678 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10680 leave_guest_mode(vcpu
);
10681 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10682 exit_qualification
);
10684 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10685 vmcs12
->vm_exit_msr_store_count
))
10686 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10688 if (unlikely(vmx
->fail
))
10689 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
10691 vmx_load_vmcs01(vcpu
);
10693 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10694 && nested_exit_intr_ack_set(vcpu
)) {
10695 int irq
= kvm_cpu_get_interrupt(vcpu
);
10697 vmcs12
->vm_exit_intr_info
= irq
|
10698 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10701 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10702 vmcs12
->exit_qualification
,
10703 vmcs12
->idt_vectoring_info_field
,
10704 vmcs12
->vm_exit_intr_info
,
10705 vmcs12
->vm_exit_intr_error_code
,
10708 vm_entry_controls_reset_shadow(vmx
);
10709 vm_exit_controls_reset_shadow(vmx
);
10710 vmx_segment_cache_clear(vmx
);
10712 /* if no vmcs02 cache requested, remove the one we used */
10713 if (VMCS02_POOL_SIZE
== 0)
10714 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10716 load_vmcs12_host_state(vcpu
, vmcs12
);
10718 /* Update any VMCS fields that might have changed while L2 ran */
10719 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10720 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10721 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10722 if (vmx
->hv_deadline_tsc
== -1)
10723 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10724 PIN_BASED_VMX_PREEMPTION_TIMER
);
10726 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10727 PIN_BASED_VMX_PREEMPTION_TIMER
);
10728 if (kvm_has_tsc_control
)
10729 decache_tsc_multiplier(vmx
);
10731 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
10732 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
10733 vmx_set_virtual_x2apic_mode(vcpu
,
10734 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
10737 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10740 /* Unpin physical memory we referred to in vmcs02 */
10741 if (vmx
->nested
.apic_access_page
) {
10742 nested_release_page(vmx
->nested
.apic_access_page
);
10743 vmx
->nested
.apic_access_page
= NULL
;
10745 if (vmx
->nested
.virtual_apic_page
) {
10746 nested_release_page(vmx
->nested
.virtual_apic_page
);
10747 vmx
->nested
.virtual_apic_page
= NULL
;
10749 if (vmx
->nested
.pi_desc_page
) {
10750 kunmap(vmx
->nested
.pi_desc_page
);
10751 nested_release_page(vmx
->nested
.pi_desc_page
);
10752 vmx
->nested
.pi_desc_page
= NULL
;
10753 vmx
->nested
.pi_desc
= NULL
;
10757 * We are now running in L2, mmu_notifier will force to reload the
10758 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10760 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
10763 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10764 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10765 * success or failure flag accordingly.
10767 if (unlikely(vmx
->fail
)) {
10769 nested_vmx_failValid(vcpu
, vm_inst_error
);
10771 nested_vmx_succeed(vcpu
);
10772 if (enable_shadow_vmcs
)
10773 vmx
->nested
.sync_shadow_vmcs
= true;
10775 /* in case we halted in L2 */
10776 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10780 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10782 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10784 if (is_guest_mode(vcpu
))
10785 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10786 free_nested(to_vmx(vcpu
));
10790 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10791 * 23.7 "VM-entry failures during or after loading guest state" (this also
10792 * lists the acceptable exit-reason and exit-qualification parameters).
10793 * It should only be called before L2 actually succeeded to run, and when
10794 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10796 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10797 struct vmcs12
*vmcs12
,
10798 u32 reason
, unsigned long qualification
)
10800 load_vmcs12_host_state(vcpu
, vmcs12
);
10801 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10802 vmcs12
->exit_qualification
= qualification
;
10803 nested_vmx_succeed(vcpu
);
10804 if (enable_shadow_vmcs
)
10805 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10808 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10809 struct x86_instruction_info
*info
,
10810 enum x86_intercept_stage stage
)
10812 return X86EMUL_CONTINUE
;
10815 #ifdef CONFIG_X86_64
10816 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
10817 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
10818 u64 divisor
, u64
*result
)
10820 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
10822 /* To avoid the overflow on divq */
10823 if (high
>= divisor
)
10826 /* Low hold the result, high hold rem which is discarded */
10827 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
10828 "rm" (divisor
), "0" (low
), "1" (high
));
10834 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
10836 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10837 u64 tscl
= rdtsc();
10838 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
10839 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
10841 /* Convert to host delta tsc if tsc scaling is enabled */
10842 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
10843 u64_shl_div_u64(delta_tsc
,
10844 kvm_tsc_scaling_ratio_frac_bits
,
10845 vcpu
->arch
.tsc_scaling_ratio
,
10850 * If the delta tsc can't fit in the 32 bit after the multi shift,
10851 * we can't use the preemption timer.
10852 * It's possible that it fits on later vmentries, but checking
10853 * on every vmentry is costly so we just use an hrtimer.
10855 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
10858 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
10859 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10860 PIN_BASED_VMX_PREEMPTION_TIMER
);
10864 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
10866 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10867 vmx
->hv_deadline_tsc
= -1;
10868 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10869 PIN_BASED_VMX_PREEMPTION_TIMER
);
10873 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10876 shrink_ple_window(vcpu
);
10879 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10880 struct kvm_memory_slot
*slot
)
10882 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10883 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10886 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10887 struct kvm_memory_slot
*slot
)
10889 kvm_mmu_slot_set_dirty(kvm
, slot
);
10892 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10894 kvm_flush_pml_buffers(kvm
);
10897 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10898 struct kvm_memory_slot
*memslot
,
10899 gfn_t offset
, unsigned long mask
)
10901 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10905 * This routine does the following things for vCPU which is going
10906 * to be blocked if VT-d PI is enabled.
10907 * - Store the vCPU to the wakeup list, so when interrupts happen
10908 * we can find the right vCPU to wake up.
10909 * - Change the Posted-interrupt descriptor as below:
10910 * 'NDST' <-- vcpu->pre_pcpu
10911 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10912 * - If 'ON' is set during this process, which means at least one
10913 * interrupt is posted for this vCPU, we cannot block it, in
10914 * this case, return 1, otherwise, return 0.
10917 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
10919 unsigned long flags
;
10921 struct pi_desc old
, new;
10922 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10924 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10925 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10926 !kvm_vcpu_apicv_active(vcpu
))
10929 vcpu
->pre_pcpu
= vcpu
->cpu
;
10930 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10931 vcpu
->pre_pcpu
), flags
);
10932 list_add_tail(&vcpu
->blocked_vcpu_list
,
10933 &per_cpu(blocked_vcpu_on_cpu
,
10935 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10936 vcpu
->pre_pcpu
), flags
);
10939 old
.control
= new.control
= pi_desc
->control
;
10942 * We should not block the vCPU if
10943 * an interrupt is posted for it.
10945 if (pi_test_on(pi_desc
) == 1) {
10946 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10947 vcpu
->pre_pcpu
), flags
);
10948 list_del(&vcpu
->blocked_vcpu_list
);
10949 spin_unlock_irqrestore(
10950 &per_cpu(blocked_vcpu_on_cpu_lock
,
10951 vcpu
->pre_pcpu
), flags
);
10952 vcpu
->pre_pcpu
= -1;
10957 WARN((pi_desc
->sn
== 1),
10958 "Warning: SN field of posted-interrupts "
10959 "is set before blocking\n");
10962 * Since vCPU can be preempted during this process,
10963 * vcpu->cpu could be different with pre_pcpu, we
10964 * need to set pre_pcpu as the destination of wakeup
10965 * notification event, then we can find the right vCPU
10966 * to wakeup in wakeup handler if interrupts happen
10967 * when the vCPU is in blocked state.
10969 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10971 if (x2apic_enabled())
10974 new.ndst
= (dest
<< 8) & 0xFF00;
10976 /* set 'NV' to 'wakeup vector' */
10977 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10978 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10979 new.control
) != old
.control
);
10984 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10986 if (pi_pre_block(vcpu
))
10989 if (kvm_lapic_hv_timer_in_use(vcpu
))
10990 kvm_lapic_switch_to_sw_timer(vcpu
);
10995 static void pi_post_block(struct kvm_vcpu
*vcpu
)
10997 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10998 struct pi_desc old
, new;
11000 unsigned long flags
;
11002 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11003 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11004 !kvm_vcpu_apicv_active(vcpu
))
11008 old
.control
= new.control
= pi_desc
->control
;
11010 dest
= cpu_physical_id(vcpu
->cpu
);
11012 if (x2apic_enabled())
11015 new.ndst
= (dest
<< 8) & 0xFF00;
11017 /* Allow posting non-urgent interrupts */
11020 /* set 'NV' to 'notification vector' */
11021 new.nv
= POSTED_INTR_VECTOR
;
11022 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11023 new.control
) != old
.control
);
11025 if(vcpu
->pre_pcpu
!= -1) {
11027 &per_cpu(blocked_vcpu_on_cpu_lock
,
11028 vcpu
->pre_pcpu
), flags
);
11029 list_del(&vcpu
->blocked_vcpu_list
);
11030 spin_unlock_irqrestore(
11031 &per_cpu(blocked_vcpu_on_cpu_lock
,
11032 vcpu
->pre_pcpu
), flags
);
11033 vcpu
->pre_pcpu
= -1;
11037 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11039 if (kvm_x86_ops
->set_hv_timer
)
11040 kvm_lapic_switch_to_hv_timer(vcpu
);
11042 pi_post_block(vcpu
);
11046 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11049 * @host_irq: host irq of the interrupt
11050 * @guest_irq: gsi of the interrupt
11051 * @set: set or unset PI
11052 * returns 0 on success, < 0 on failure
11054 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11055 uint32_t guest_irq
, bool set
)
11057 struct kvm_kernel_irq_routing_entry
*e
;
11058 struct kvm_irq_routing_table
*irq_rt
;
11059 struct kvm_lapic_irq irq
;
11060 struct kvm_vcpu
*vcpu
;
11061 struct vcpu_data vcpu_info
;
11062 int idx
, ret
= -EINVAL
;
11064 if (!kvm_arch_has_assigned_device(kvm
) ||
11065 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11066 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11069 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11070 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11071 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11073 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11074 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11077 * VT-d PI cannot support posting multicast/broadcast
11078 * interrupts to a vCPU, we still use interrupt remapping
11079 * for these kind of interrupts.
11081 * For lowest-priority interrupts, we only support
11082 * those with single CPU as the destination, e.g. user
11083 * configures the interrupts via /proc/irq or uses
11084 * irqbalance to make the interrupts single-CPU.
11086 * We will support full lowest-priority interrupt later.
11089 kvm_set_msi_irq(kvm
, e
, &irq
);
11090 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11092 * Make sure the IRTE is in remapped mode if
11093 * we don't handle it in posted mode.
11095 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11098 "failed to back to remapped mode, irq: %u\n",
11106 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11107 vcpu_info
.vector
= irq
.vector
;
11109 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11110 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11113 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11115 /* suppress notification event before unposting */
11116 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11117 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11118 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11122 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11130 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11134 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11136 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11137 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11138 FEATURE_CONTROL_LMCE
;
11140 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11141 ~FEATURE_CONTROL_LMCE
;
11144 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11145 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11146 .disabled_by_bios
= vmx_disabled_by_bios
,
11147 .hardware_setup
= hardware_setup
,
11148 .hardware_unsetup
= hardware_unsetup
,
11149 .check_processor_compatibility
= vmx_check_processor_compat
,
11150 .hardware_enable
= hardware_enable
,
11151 .hardware_disable
= hardware_disable
,
11152 .cpu_has_accelerated_tpr
= report_flexpriority
,
11153 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11155 .vcpu_create
= vmx_create_vcpu
,
11156 .vcpu_free
= vmx_free_vcpu
,
11157 .vcpu_reset
= vmx_vcpu_reset
,
11159 .prepare_guest_switch
= vmx_save_host_state
,
11160 .vcpu_load
= vmx_vcpu_load
,
11161 .vcpu_put
= vmx_vcpu_put
,
11163 .update_bp_intercept
= update_exception_bitmap
,
11164 .get_msr
= vmx_get_msr
,
11165 .set_msr
= vmx_set_msr
,
11166 .get_segment_base
= vmx_get_segment_base
,
11167 .get_segment
= vmx_get_segment
,
11168 .set_segment
= vmx_set_segment
,
11169 .get_cpl
= vmx_get_cpl
,
11170 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11171 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11172 .decache_cr3
= vmx_decache_cr3
,
11173 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11174 .set_cr0
= vmx_set_cr0
,
11175 .set_cr3
= vmx_set_cr3
,
11176 .set_cr4
= vmx_set_cr4
,
11177 .set_efer
= vmx_set_efer
,
11178 .get_idt
= vmx_get_idt
,
11179 .set_idt
= vmx_set_idt
,
11180 .get_gdt
= vmx_get_gdt
,
11181 .set_gdt
= vmx_set_gdt
,
11182 .get_dr6
= vmx_get_dr6
,
11183 .set_dr6
= vmx_set_dr6
,
11184 .set_dr7
= vmx_set_dr7
,
11185 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11186 .cache_reg
= vmx_cache_reg
,
11187 .get_rflags
= vmx_get_rflags
,
11188 .set_rflags
= vmx_set_rflags
,
11190 .get_pkru
= vmx_get_pkru
,
11192 .fpu_activate
= vmx_fpu_activate
,
11193 .fpu_deactivate
= vmx_fpu_deactivate
,
11195 .tlb_flush
= vmx_flush_tlb
,
11197 .run
= vmx_vcpu_run
,
11198 .handle_exit
= vmx_handle_exit
,
11199 .skip_emulated_instruction
= skip_emulated_instruction
,
11200 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11201 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11202 .patch_hypercall
= vmx_patch_hypercall
,
11203 .set_irq
= vmx_inject_irq
,
11204 .set_nmi
= vmx_inject_nmi
,
11205 .queue_exception
= vmx_queue_exception
,
11206 .cancel_injection
= vmx_cancel_injection
,
11207 .interrupt_allowed
= vmx_interrupt_allowed
,
11208 .nmi_allowed
= vmx_nmi_allowed
,
11209 .get_nmi_mask
= vmx_get_nmi_mask
,
11210 .set_nmi_mask
= vmx_set_nmi_mask
,
11211 .enable_nmi_window
= enable_nmi_window
,
11212 .enable_irq_window
= enable_irq_window
,
11213 .update_cr8_intercept
= update_cr8_intercept
,
11214 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11215 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11216 .get_enable_apicv
= vmx_get_enable_apicv
,
11217 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11218 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11219 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11220 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11221 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11222 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11224 .set_tss_addr
= vmx_set_tss_addr
,
11225 .get_tdp_level
= get_ept_level
,
11226 .get_mt_mask
= vmx_get_mt_mask
,
11228 .get_exit_info
= vmx_get_exit_info
,
11230 .get_lpage_level
= vmx_get_lpage_level
,
11232 .cpuid_update
= vmx_cpuid_update
,
11234 .rdtscp_supported
= vmx_rdtscp_supported
,
11235 .invpcid_supported
= vmx_invpcid_supported
,
11237 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11239 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11241 .write_tsc_offset
= vmx_write_tsc_offset
,
11243 .set_tdp_cr3
= vmx_set_cr3
,
11245 .check_intercept
= vmx_check_intercept
,
11246 .handle_external_intr
= vmx_handle_external_intr
,
11247 .mpx_supported
= vmx_mpx_supported
,
11248 .xsaves_supported
= vmx_xsaves_supported
,
11250 .check_nested_events
= vmx_check_nested_events
,
11252 .sched_in
= vmx_sched_in
,
11254 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11255 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11256 .flush_log_dirty
= vmx_flush_log_dirty
,
11257 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11259 .pre_block
= vmx_pre_block
,
11260 .post_block
= vmx_post_block
,
11262 .pmu_ops
= &intel_pmu_ops
,
11264 .update_pi_irte
= vmx_update_pi_irte
,
11266 #ifdef CONFIG_X86_64
11267 .set_hv_timer
= vmx_set_hv_timer
,
11268 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11271 .setup_mce
= vmx_setup_mce
,
11274 static int __init
vmx_init(void)
11276 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11277 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11281 #ifdef CONFIG_KEXEC_CORE
11282 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11283 crash_vmclear_local_loaded_vmcss
);
11289 static void __exit
vmx_exit(void)
11291 #ifdef CONFIG_KEXEC_CORE
11292 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11299 module_init(vmx_init
)
11300 module_exit(vmx_exit
)