2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include "kvm_cache_regs.h"
35 #include <asm/virtext.h>
40 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42 MODULE_AUTHOR("Qumranet");
43 MODULE_LICENSE("GPL");
45 static int __read_mostly bypass_guest_pf
= 1;
46 module_param(bypass_guest_pf
, bool, S_IRUGO
);
48 static int __read_mostly enable_vpid
= 1;
49 module_param_named(vpid
, enable_vpid
, bool, 0444);
51 static int __read_mostly flexpriority_enabled
= 1;
52 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
54 static int __read_mostly enable_ept
= 1;
55 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
57 static int __read_mostly enable_unrestricted_guest
= 1;
58 module_param_named(unrestricted_guest
,
59 enable_unrestricted_guest
, bool, S_IRUGO
);
61 static int __read_mostly emulate_invalid_guest_state
= 0;
62 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
64 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
65 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
66 #define KVM_GUEST_CR0_MASK \
67 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
68 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
69 (X86_CR0_WP | X86_CR0_NE)
70 #define KVM_VM_CR0_ALWAYS_ON \
71 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
72 #define KVM_CR4_GUEST_OWNED_BITS \
73 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
76 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
77 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
80 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
81 * ple_gap: upper bound on the amount of time between two successive
82 * executions of PAUSE in a loop. Also indicate if ple enabled.
83 * According to test, this time is usually small than 41 cycles.
84 * ple_window: upper bound on the amount of time a guest is allowed to execute
85 * in a PAUSE loop. Tests indicate that most spinlocks are held for
86 * less than 2^12 cycles
87 * Time is measured based on a counter that runs at the same rate as the TSC,
88 * refer SDM volume 3b section 21.6.13 & 22.1.3.
90 #define KVM_VMX_DEFAULT_PLE_GAP 41
91 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
92 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
93 module_param(ple_gap
, int, S_IRUGO
);
95 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
96 module_param(ple_window
, int, S_IRUGO
);
104 struct shared_msr_entry
{
111 struct kvm_vcpu vcpu
;
112 struct list_head local_vcpus_link
;
113 unsigned long host_rsp
;
116 u32 idt_vectoring_info
;
117 struct shared_msr_entry
*guest_msrs
;
121 u64 msr_host_kernel_gs_base
;
122 u64 msr_guest_kernel_gs_base
;
127 u16 fs_sel
, gs_sel
, ldt_sel
;
128 int gs_ldt_reload_needed
;
129 int fs_reload_needed
;
134 struct kvm_save_segment
{
139 } tr
, es
, ds
, fs
, gs
;
147 bool emulation_required
;
149 /* Support for vnmi-less CPUs */
150 int soft_vnmi_blocked
;
152 s64 vnmi_blocked_time
;
158 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
160 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
163 static int init_rmode(struct kvm
*kvm
);
164 static u64
construct_eptp(unsigned long root_hpa
);
166 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
167 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
168 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
170 static unsigned long *vmx_io_bitmap_a
;
171 static unsigned long *vmx_io_bitmap_b
;
172 static unsigned long *vmx_msr_bitmap_legacy
;
173 static unsigned long *vmx_msr_bitmap_longmode
;
175 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
176 static DEFINE_SPINLOCK(vmx_vpid_lock
);
178 static struct vmcs_config
{
182 u32 pin_based_exec_ctrl
;
183 u32 cpu_based_exec_ctrl
;
184 u32 cpu_based_2nd_exec_ctrl
;
189 static struct vmx_capability
{
194 #define VMX_SEGMENT_FIELD(seg) \
195 [VCPU_SREG_##seg] = { \
196 .selector = GUEST_##seg##_SELECTOR, \
197 .base = GUEST_##seg##_BASE, \
198 .limit = GUEST_##seg##_LIMIT, \
199 .ar_bytes = GUEST_##seg##_AR_BYTES, \
202 static struct kvm_vmx_segment_field
{
207 } kvm_vmx_segment_fields
[] = {
208 VMX_SEGMENT_FIELD(CS
),
209 VMX_SEGMENT_FIELD(DS
),
210 VMX_SEGMENT_FIELD(ES
),
211 VMX_SEGMENT_FIELD(FS
),
212 VMX_SEGMENT_FIELD(GS
),
213 VMX_SEGMENT_FIELD(SS
),
214 VMX_SEGMENT_FIELD(TR
),
215 VMX_SEGMENT_FIELD(LDTR
),
218 static u64 host_efer
;
220 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
223 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
224 * away by decrementing the array size.
226 static const u32 vmx_msr_index
[] = {
228 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
230 MSR_EFER
, MSR_TSC_AUX
, MSR_K6_STAR
,
232 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
234 static inline int is_page_fault(u32 intr_info
)
236 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
237 INTR_INFO_VALID_MASK
)) ==
238 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
241 static inline int is_no_device(u32 intr_info
)
243 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
244 INTR_INFO_VALID_MASK
)) ==
245 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
248 static inline int is_invalid_opcode(u32 intr_info
)
250 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
251 INTR_INFO_VALID_MASK
)) ==
252 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
255 static inline int is_external_interrupt(u32 intr_info
)
257 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
258 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
261 static inline int is_machine_check(u32 intr_info
)
263 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
264 INTR_INFO_VALID_MASK
)) ==
265 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
268 static inline int cpu_has_vmx_msr_bitmap(void)
270 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
273 static inline int cpu_has_vmx_tpr_shadow(void)
275 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
278 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
280 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
283 static inline int cpu_has_secondary_exec_ctrls(void)
285 return vmcs_config
.cpu_based_exec_ctrl
&
286 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
289 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
292 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
295 static inline bool cpu_has_vmx_flexpriority(void)
297 return cpu_has_vmx_tpr_shadow() &&
298 cpu_has_vmx_virtualize_apic_accesses();
301 static inline bool cpu_has_vmx_ept_execute_only(void)
303 return !!(vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
);
306 static inline bool cpu_has_vmx_eptp_uncacheable(void)
308 return !!(vmx_capability
.ept
& VMX_EPTP_UC_BIT
);
311 static inline bool cpu_has_vmx_eptp_writeback(void)
313 return !!(vmx_capability
.ept
& VMX_EPTP_WB_BIT
);
316 static inline bool cpu_has_vmx_ept_2m_page(void)
318 return !!(vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
);
321 static inline bool cpu_has_vmx_ept_1g_page(void)
323 return !!(vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
);
326 static inline int cpu_has_vmx_invept_individual_addr(void)
328 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
);
331 static inline int cpu_has_vmx_invept_context(void)
333 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
);
336 static inline int cpu_has_vmx_invept_global(void)
338 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
);
341 static inline int cpu_has_vmx_ept(void)
343 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
344 SECONDARY_EXEC_ENABLE_EPT
;
347 static inline int cpu_has_vmx_unrestricted_guest(void)
349 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
350 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
353 static inline int cpu_has_vmx_ple(void)
355 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
356 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
359 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
361 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
364 static inline int cpu_has_vmx_vpid(void)
366 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
367 SECONDARY_EXEC_ENABLE_VPID
;
370 static inline int cpu_has_vmx_rdtscp(void)
372 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
373 SECONDARY_EXEC_RDTSCP
;
376 static inline int cpu_has_virtual_nmis(void)
378 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
381 static inline bool report_flexpriority(void)
383 return flexpriority_enabled
;
386 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
390 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
391 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
396 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
402 } operand
= { vpid
, 0, gva
};
404 asm volatile (__ex(ASM_VMX_INVVPID
)
405 /* CF==1 or ZF==1 --> rc = -1 */
407 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
410 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
414 } operand
= {eptp
, gpa
};
416 asm volatile (__ex(ASM_VMX_INVEPT
)
417 /* CF==1 or ZF==1 --> rc = -1 */
418 "; ja 1f ; ud2 ; 1:\n"
419 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
422 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
426 i
= __find_msr_index(vmx
, msr
);
428 return &vmx
->guest_msrs
[i
];
432 static void vmcs_clear(struct vmcs
*vmcs
)
434 u64 phys_addr
= __pa(vmcs
);
437 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
438 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
441 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
445 static void __vcpu_clear(void *arg
)
447 struct vcpu_vmx
*vmx
= arg
;
448 int cpu
= raw_smp_processor_id();
450 if (vmx
->vcpu
.cpu
== cpu
)
451 vmcs_clear(vmx
->vmcs
);
452 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
453 per_cpu(current_vmcs
, cpu
) = NULL
;
454 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
455 list_del(&vmx
->local_vcpus_link
);
460 static void vcpu_clear(struct vcpu_vmx
*vmx
)
462 if (vmx
->vcpu
.cpu
== -1)
464 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
467 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
472 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
475 static inline void ept_sync_global(void)
477 if (cpu_has_vmx_invept_global())
478 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
481 static inline void ept_sync_context(u64 eptp
)
484 if (cpu_has_vmx_invept_context())
485 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
491 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
494 if (cpu_has_vmx_invept_individual_addr())
495 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
498 ept_sync_context(eptp
);
502 static unsigned long vmcs_readl(unsigned long field
)
506 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
507 : "=a"(value
) : "d"(field
) : "cc");
511 static u16
vmcs_read16(unsigned long field
)
513 return vmcs_readl(field
);
516 static u32
vmcs_read32(unsigned long field
)
518 return vmcs_readl(field
);
521 static u64
vmcs_read64(unsigned long field
)
524 return vmcs_readl(field
);
526 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
530 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
532 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
533 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
537 static void vmcs_writel(unsigned long field
, unsigned long value
)
541 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
542 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
544 vmwrite_error(field
, value
);
547 static void vmcs_write16(unsigned long field
, u16 value
)
549 vmcs_writel(field
, value
);
552 static void vmcs_write32(unsigned long field
, u32 value
)
554 vmcs_writel(field
, value
);
557 static void vmcs_write64(unsigned long field
, u64 value
)
559 vmcs_writel(field
, value
);
560 #ifndef CONFIG_X86_64
562 vmcs_writel(field
+1, value
>> 32);
566 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
568 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
571 static void vmcs_set_bits(unsigned long field
, u32 mask
)
573 vmcs_writel(field
, vmcs_readl(field
) | mask
);
576 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
580 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
581 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
582 if ((vcpu
->guest_debug
&
583 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
584 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
585 eb
|= 1u << BP_VECTOR
;
586 if (to_vmx(vcpu
)->rmode
.vm86_active
)
589 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
590 if (vcpu
->fpu_active
)
591 eb
&= ~(1u << NM_VECTOR
);
592 vmcs_write32(EXCEPTION_BITMAP
, eb
);
595 static void reload_tss(void)
598 * VT restores TR but not its size. Useless.
600 struct descriptor_table gdt
;
601 struct desc_struct
*descs
;
604 descs
= (void *)gdt
.base
;
605 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
609 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
614 guest_efer
= vmx
->vcpu
.arch
.efer
;
617 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
620 ignore_bits
= EFER_NX
| EFER_SCE
;
622 ignore_bits
|= EFER_LMA
| EFER_LME
;
623 /* SCE is meaningful only in long mode on Intel */
624 if (guest_efer
& EFER_LMA
)
625 ignore_bits
&= ~(u64
)EFER_SCE
;
627 guest_efer
&= ~ignore_bits
;
628 guest_efer
|= host_efer
& ignore_bits
;
629 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
630 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
634 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
639 if (vmx
->host_state
.loaded
)
642 vmx
->host_state
.loaded
= 1;
644 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
645 * allow segment selectors with cpl > 0 or ti == 1.
647 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
648 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
649 vmx
->host_state
.fs_sel
= kvm_read_fs();
650 if (!(vmx
->host_state
.fs_sel
& 7)) {
651 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
652 vmx
->host_state
.fs_reload_needed
= 0;
654 vmcs_write16(HOST_FS_SELECTOR
, 0);
655 vmx
->host_state
.fs_reload_needed
= 1;
657 vmx
->host_state
.gs_sel
= kvm_read_gs();
658 if (!(vmx
->host_state
.gs_sel
& 7))
659 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
661 vmcs_write16(HOST_GS_SELECTOR
, 0);
662 vmx
->host_state
.gs_ldt_reload_needed
= 1;
666 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
667 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
669 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
670 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
674 if (is_long_mode(&vmx
->vcpu
)) {
675 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
676 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
679 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
680 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
681 vmx
->guest_msrs
[i
].data
,
682 vmx
->guest_msrs
[i
].mask
);
685 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
689 if (!vmx
->host_state
.loaded
)
692 ++vmx
->vcpu
.stat
.host_state_reload
;
693 vmx
->host_state
.loaded
= 0;
694 if (vmx
->host_state
.fs_reload_needed
)
695 kvm_load_fs(vmx
->host_state
.fs_sel
);
696 if (vmx
->host_state
.gs_ldt_reload_needed
) {
697 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
699 * If we have to reload gs, we must take care to
700 * preserve our gs base.
702 local_irq_save(flags
);
703 kvm_load_gs(vmx
->host_state
.gs_sel
);
705 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
707 local_irq_restore(flags
);
711 if (is_long_mode(&vmx
->vcpu
)) {
712 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
713 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
718 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
721 __vmx_load_host_state(vmx
);
726 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
727 * vcpu mutex is already taken.
729 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
731 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
732 u64 phys_addr
= __pa(vmx
->vmcs
);
733 u64 tsc_this
, delta
, new_offset
;
735 if (vcpu
->cpu
!= cpu
) {
737 kvm_migrate_timers(vcpu
);
738 set_bit(KVM_REQ_TLB_FLUSH
, &vcpu
->requests
);
740 list_add(&vmx
->local_vcpus_link
,
741 &per_cpu(vcpus_on_cpu
, cpu
));
745 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
748 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
749 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
750 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
753 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
754 vmx
->vmcs
, phys_addr
);
757 if (vcpu
->cpu
!= cpu
) {
758 struct descriptor_table dt
;
759 unsigned long sysenter_esp
;
763 * Linux uses per-cpu TSS and GDT, so set these when switching
766 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
768 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
770 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
771 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
774 * Make sure the time stamp counter is monotonous.
777 if (tsc_this
< vcpu
->arch
.host_tsc
) {
778 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
779 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
780 vmcs_write64(TSC_OFFSET
, new_offset
);
785 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
787 __vmx_load_host_state(to_vmx(vcpu
));
790 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
794 if (vcpu
->fpu_active
)
796 vcpu
->fpu_active
= 1;
797 cr0
= vmcs_readl(GUEST_CR0
);
798 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
799 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
800 vmcs_writel(GUEST_CR0
, cr0
);
801 update_exception_bitmap(vcpu
);
802 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
803 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
806 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
808 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
810 vmx_decache_cr0_guest_bits(vcpu
);
811 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
812 update_exception_bitmap(vcpu
);
813 vcpu
->arch
.cr0_guest_owned_bits
= 0;
814 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
815 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
818 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
820 unsigned long rflags
;
822 rflags
= vmcs_readl(GUEST_RFLAGS
);
823 if (to_vmx(vcpu
)->rmode
.vm86_active
)
824 rflags
&= ~(unsigned long)(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
828 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
830 if (to_vmx(vcpu
)->rmode
.vm86_active
)
831 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
832 vmcs_writel(GUEST_RFLAGS
, rflags
);
835 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
837 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
840 if (interruptibility
& GUEST_INTR_STATE_STI
)
841 ret
|= X86_SHADOW_INT_STI
;
842 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
843 ret
|= X86_SHADOW_INT_MOV_SS
;
848 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
850 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
851 u32 interruptibility
= interruptibility_old
;
853 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
855 if (mask
& X86_SHADOW_INT_MOV_SS
)
856 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
857 if (mask
& X86_SHADOW_INT_STI
)
858 interruptibility
|= GUEST_INTR_STATE_STI
;
860 if ((interruptibility
!= interruptibility_old
))
861 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
864 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
868 rip
= kvm_rip_read(vcpu
);
869 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
870 kvm_rip_write(vcpu
, rip
);
872 /* skipping an emulated instruction also counts */
873 vmx_set_interrupt_shadow(vcpu
, 0);
876 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
877 bool has_error_code
, u32 error_code
)
879 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
880 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
882 if (has_error_code
) {
883 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
884 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
887 if (vmx
->rmode
.vm86_active
) {
888 vmx
->rmode
.irq
.pending
= true;
889 vmx
->rmode
.irq
.vector
= nr
;
890 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
891 if (kvm_exception_is_soft(nr
))
892 vmx
->rmode
.irq
.rip
+=
893 vmx
->vcpu
.arch
.event_exit_inst_len
;
894 intr_info
|= INTR_TYPE_SOFT_INTR
;
895 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
896 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
897 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
901 if (kvm_exception_is_soft(nr
)) {
902 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
903 vmx
->vcpu
.arch
.event_exit_inst_len
);
904 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
906 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
908 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
911 static bool vmx_rdtscp_supported(void)
913 return cpu_has_vmx_rdtscp();
917 * Swap MSR entry in host/guest MSR entry array.
919 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
921 struct shared_msr_entry tmp
;
923 tmp
= vmx
->guest_msrs
[to
];
924 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
925 vmx
->guest_msrs
[from
] = tmp
;
929 * Set up the vmcs to automatically save and restore system
930 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
931 * mode, as fiddling with msrs is very expensive.
933 static void setup_msrs(struct vcpu_vmx
*vmx
)
935 int save_nmsrs
, index
;
936 unsigned long *msr_bitmap
;
938 vmx_load_host_state(vmx
);
941 if (is_long_mode(&vmx
->vcpu
)) {
942 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
944 move_msr_up(vmx
, index
, save_nmsrs
++);
945 index
= __find_msr_index(vmx
, MSR_LSTAR
);
947 move_msr_up(vmx
, index
, save_nmsrs
++);
948 index
= __find_msr_index(vmx
, MSR_CSTAR
);
950 move_msr_up(vmx
, index
, save_nmsrs
++);
951 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
952 if (index
>= 0 && vmx
->rdtscp_enabled
)
953 move_msr_up(vmx
, index
, save_nmsrs
++);
955 * MSR_K6_STAR is only needed on long mode guests, and only
956 * if efer.sce is enabled.
958 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
959 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
960 move_msr_up(vmx
, index
, save_nmsrs
++);
963 index
= __find_msr_index(vmx
, MSR_EFER
);
964 if (index
>= 0 && update_transition_efer(vmx
, index
))
965 move_msr_up(vmx
, index
, save_nmsrs
++);
967 vmx
->save_nmsrs
= save_nmsrs
;
969 if (cpu_has_vmx_msr_bitmap()) {
970 if (is_long_mode(&vmx
->vcpu
))
971 msr_bitmap
= vmx_msr_bitmap_longmode
;
973 msr_bitmap
= vmx_msr_bitmap_legacy
;
975 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
980 * reads and returns guest's timestamp counter "register"
981 * guest_tsc = host_tsc + tsc_offset -- 21.3
983 static u64
guest_read_tsc(void)
985 u64 host_tsc
, tsc_offset
;
988 tsc_offset
= vmcs_read64(TSC_OFFSET
);
989 return host_tsc
+ tsc_offset
;
993 * writes 'guest_tsc' into guest's timestamp counter "register"
994 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
996 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
998 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
1002 * Reads an msr value (of 'msr_index') into 'pdata'.
1003 * Returns 0 on success, non-0 otherwise.
1004 * Assumes vcpu_load() was already called.
1006 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1009 struct shared_msr_entry
*msr
;
1012 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1016 switch (msr_index
) {
1017 #ifdef CONFIG_X86_64
1019 data
= vmcs_readl(GUEST_FS_BASE
);
1022 data
= vmcs_readl(GUEST_GS_BASE
);
1024 case MSR_KERNEL_GS_BASE
:
1025 vmx_load_host_state(to_vmx(vcpu
));
1026 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1030 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1032 data
= guest_read_tsc();
1034 case MSR_IA32_SYSENTER_CS
:
1035 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1037 case MSR_IA32_SYSENTER_EIP
:
1038 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1040 case MSR_IA32_SYSENTER_ESP
:
1041 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1044 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1046 /* Otherwise falls through */
1048 vmx_load_host_state(to_vmx(vcpu
));
1049 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1051 vmx_load_host_state(to_vmx(vcpu
));
1055 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1063 * Writes msr value into into the appropriate "register".
1064 * Returns 0 on success, non-0 otherwise.
1065 * Assumes vcpu_load() was already called.
1067 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1070 struct shared_msr_entry
*msr
;
1074 switch (msr_index
) {
1076 vmx_load_host_state(vmx
);
1077 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1079 #ifdef CONFIG_X86_64
1081 vmcs_writel(GUEST_FS_BASE
, data
);
1084 vmcs_writel(GUEST_GS_BASE
, data
);
1086 case MSR_KERNEL_GS_BASE
:
1087 vmx_load_host_state(vmx
);
1088 vmx
->msr_guest_kernel_gs_base
= data
;
1091 case MSR_IA32_SYSENTER_CS
:
1092 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1094 case MSR_IA32_SYSENTER_EIP
:
1095 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1097 case MSR_IA32_SYSENTER_ESP
:
1098 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1102 guest_write_tsc(data
, host_tsc
);
1104 case MSR_IA32_CR_PAT
:
1105 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1106 vmcs_write64(GUEST_IA32_PAT
, data
);
1107 vcpu
->arch
.pat
= data
;
1110 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1113 if (!vmx
->rdtscp_enabled
)
1115 /* Check reserved bit, higher 32 bits should be zero */
1116 if ((data
>> 32) != 0)
1118 /* Otherwise falls through */
1120 msr
= find_msr_entry(vmx
, msr_index
);
1122 vmx_load_host_state(vmx
);
1126 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1132 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1134 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1137 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1140 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1142 case VCPU_EXREG_PDPTR
:
1144 ept_save_pdptrs(vcpu
);
1151 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1153 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1154 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1156 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1158 update_exception_bitmap(vcpu
);
1161 static __init
int cpu_has_kvm_support(void)
1163 return cpu_has_vmx();
1166 static __init
int vmx_disabled_by_bios(void)
1170 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1171 return (msr
& (FEATURE_CONTROL_LOCKED
|
1172 FEATURE_CONTROL_VMXON_ENABLED
))
1173 == FEATURE_CONTROL_LOCKED
;
1174 /* locked but not enabled */
1177 static int hardware_enable(void *garbage
)
1179 int cpu
= raw_smp_processor_id();
1180 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1183 if (read_cr4() & X86_CR4_VMXE
)
1186 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1187 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1188 if ((old
& (FEATURE_CONTROL_LOCKED
|
1189 FEATURE_CONTROL_VMXON_ENABLED
))
1190 != (FEATURE_CONTROL_LOCKED
|
1191 FEATURE_CONTROL_VMXON_ENABLED
))
1192 /* enable and lock */
1193 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
1194 FEATURE_CONTROL_LOCKED
|
1195 FEATURE_CONTROL_VMXON_ENABLED
);
1196 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1197 asm volatile (ASM_VMX_VMXON_RAX
1198 : : "a"(&phys_addr
), "m"(phys_addr
)
1206 static void vmclear_local_vcpus(void)
1208 int cpu
= raw_smp_processor_id();
1209 struct vcpu_vmx
*vmx
, *n
;
1211 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1217 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1220 static void kvm_cpu_vmxoff(void)
1222 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1223 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1226 static void hardware_disable(void *garbage
)
1228 vmclear_local_vcpus();
1232 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1233 u32 msr
, u32
*result
)
1235 u32 vmx_msr_low
, vmx_msr_high
;
1236 u32 ctl
= ctl_min
| ctl_opt
;
1238 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1240 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1241 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1243 /* Ensure minimum (required) set of control bits are supported. */
1251 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1253 u32 vmx_msr_low
, vmx_msr_high
;
1254 u32 min
, opt
, min2
, opt2
;
1255 u32 _pin_based_exec_control
= 0;
1256 u32 _cpu_based_exec_control
= 0;
1257 u32 _cpu_based_2nd_exec_control
= 0;
1258 u32 _vmexit_control
= 0;
1259 u32 _vmentry_control
= 0;
1261 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1262 opt
= PIN_BASED_VIRTUAL_NMIS
;
1263 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1264 &_pin_based_exec_control
) < 0)
1267 min
= CPU_BASED_HLT_EXITING
|
1268 #ifdef CONFIG_X86_64
1269 CPU_BASED_CR8_LOAD_EXITING
|
1270 CPU_BASED_CR8_STORE_EXITING
|
1272 CPU_BASED_CR3_LOAD_EXITING
|
1273 CPU_BASED_CR3_STORE_EXITING
|
1274 CPU_BASED_USE_IO_BITMAPS
|
1275 CPU_BASED_MOV_DR_EXITING
|
1276 CPU_BASED_USE_TSC_OFFSETING
|
1277 CPU_BASED_MWAIT_EXITING
|
1278 CPU_BASED_MONITOR_EXITING
|
1279 CPU_BASED_INVLPG_EXITING
;
1280 opt
= CPU_BASED_TPR_SHADOW
|
1281 CPU_BASED_USE_MSR_BITMAPS
|
1282 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1283 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1284 &_cpu_based_exec_control
) < 0)
1286 #ifdef CONFIG_X86_64
1287 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1288 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1289 ~CPU_BASED_CR8_STORE_EXITING
;
1291 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1293 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1294 SECONDARY_EXEC_WBINVD_EXITING
|
1295 SECONDARY_EXEC_ENABLE_VPID
|
1296 SECONDARY_EXEC_ENABLE_EPT
|
1297 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1298 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1299 SECONDARY_EXEC_RDTSCP
;
1300 if (adjust_vmx_controls(min2
, opt2
,
1301 MSR_IA32_VMX_PROCBASED_CTLS2
,
1302 &_cpu_based_2nd_exec_control
) < 0)
1305 #ifndef CONFIG_X86_64
1306 if (!(_cpu_based_2nd_exec_control
&
1307 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1308 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1310 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1311 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1313 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1314 CPU_BASED_CR3_STORE_EXITING
|
1315 CPU_BASED_INVLPG_EXITING
);
1316 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1317 vmx_capability
.ept
, vmx_capability
.vpid
);
1321 #ifdef CONFIG_X86_64
1322 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1324 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1325 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1326 &_vmexit_control
) < 0)
1330 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1331 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1332 &_vmentry_control
) < 0)
1335 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1337 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1338 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1341 #ifdef CONFIG_X86_64
1342 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1343 if (vmx_msr_high
& (1u<<16))
1347 /* Require Write-Back (WB) memory type for VMCS accesses. */
1348 if (((vmx_msr_high
>> 18) & 15) != 6)
1351 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1352 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1353 vmcs_conf
->revision_id
= vmx_msr_low
;
1355 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1356 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1357 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1358 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1359 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1364 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1366 int node
= cpu_to_node(cpu
);
1370 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1373 vmcs
= page_address(pages
);
1374 memset(vmcs
, 0, vmcs_config
.size
);
1375 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1379 static struct vmcs
*alloc_vmcs(void)
1381 return alloc_vmcs_cpu(raw_smp_processor_id());
1384 static void free_vmcs(struct vmcs
*vmcs
)
1386 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1389 static void free_kvm_area(void)
1393 for_each_possible_cpu(cpu
) {
1394 free_vmcs(per_cpu(vmxarea
, cpu
));
1395 per_cpu(vmxarea
, cpu
) = NULL
;
1399 static __init
int alloc_kvm_area(void)
1403 for_each_possible_cpu(cpu
) {
1406 vmcs
= alloc_vmcs_cpu(cpu
);
1412 per_cpu(vmxarea
, cpu
) = vmcs
;
1417 static __init
int hardware_setup(void)
1419 if (setup_vmcs_config(&vmcs_config
) < 0)
1422 if (boot_cpu_has(X86_FEATURE_NX
))
1423 kvm_enable_efer_bits(EFER_NX
);
1425 if (!cpu_has_vmx_vpid())
1428 if (!cpu_has_vmx_ept()) {
1430 enable_unrestricted_guest
= 0;
1433 if (!cpu_has_vmx_unrestricted_guest())
1434 enable_unrestricted_guest
= 0;
1436 if (!cpu_has_vmx_flexpriority())
1437 flexpriority_enabled
= 0;
1439 if (!cpu_has_vmx_tpr_shadow())
1440 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1442 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1443 kvm_disable_largepages();
1445 if (!cpu_has_vmx_ple())
1448 return alloc_kvm_area();
1451 static __exit
void hardware_unsetup(void)
1456 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1458 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1460 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1461 vmcs_write16(sf
->selector
, save
->selector
);
1462 vmcs_writel(sf
->base
, save
->base
);
1463 vmcs_write32(sf
->limit
, save
->limit
);
1464 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1466 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1468 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1472 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1474 unsigned long flags
;
1475 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1477 vmx
->emulation_required
= 1;
1478 vmx
->rmode
.vm86_active
= 0;
1480 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1481 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1482 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1484 flags
= vmcs_readl(GUEST_RFLAGS
);
1485 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1486 flags
|= (vmx
->rmode
.save_iopl
<< IOPL_SHIFT
);
1487 vmcs_writel(GUEST_RFLAGS
, flags
);
1489 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1490 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1492 update_exception_bitmap(vcpu
);
1494 if (emulate_invalid_guest_state
)
1497 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1498 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1499 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1500 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1502 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1503 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1505 vmcs_write16(GUEST_CS_SELECTOR
,
1506 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1507 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1510 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1512 if (!kvm
->arch
.tss_addr
) {
1513 struct kvm_memslots
*slots
;
1516 slots
= rcu_dereference(kvm
->memslots
);
1517 base_gfn
= kvm
->memslots
->memslots
[0].base_gfn
+
1518 kvm
->memslots
->memslots
[0].npages
- 3;
1519 return base_gfn
<< PAGE_SHIFT
;
1521 return kvm
->arch
.tss_addr
;
1524 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1526 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1528 save
->selector
= vmcs_read16(sf
->selector
);
1529 save
->base
= vmcs_readl(sf
->base
);
1530 save
->limit
= vmcs_read32(sf
->limit
);
1531 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1532 vmcs_write16(sf
->selector
, save
->base
>> 4);
1533 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1534 vmcs_write32(sf
->limit
, 0xffff);
1535 vmcs_write32(sf
->ar_bytes
, 0xf3);
1538 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1540 unsigned long flags
;
1541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1543 if (enable_unrestricted_guest
)
1546 vmx
->emulation_required
= 1;
1547 vmx
->rmode
.vm86_active
= 1;
1549 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1550 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1552 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1553 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1555 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1556 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1558 flags
= vmcs_readl(GUEST_RFLAGS
);
1559 vmx
->rmode
.save_iopl
1560 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1562 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1564 vmcs_writel(GUEST_RFLAGS
, flags
);
1565 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1566 update_exception_bitmap(vcpu
);
1568 if (emulate_invalid_guest_state
)
1569 goto continue_rmode
;
1571 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1572 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1573 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1575 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1576 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1577 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1578 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1579 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1581 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1582 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1583 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1584 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1587 kvm_mmu_reset_context(vcpu
);
1588 init_rmode(vcpu
->kvm
);
1591 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1593 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1594 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1600 * Force kernel_gs_base reloading before EFER changes, as control
1601 * of this msr depends on is_long_mode().
1603 vmx_load_host_state(to_vmx(vcpu
));
1604 vcpu
->arch
.efer
= efer
;
1605 if (efer
& EFER_LMA
) {
1606 vmcs_write32(VM_ENTRY_CONTROLS
,
1607 vmcs_read32(VM_ENTRY_CONTROLS
) |
1608 VM_ENTRY_IA32E_MODE
);
1611 vmcs_write32(VM_ENTRY_CONTROLS
,
1612 vmcs_read32(VM_ENTRY_CONTROLS
) &
1613 ~VM_ENTRY_IA32E_MODE
);
1615 msr
->data
= efer
& ~EFER_LME
;
1620 #ifdef CONFIG_X86_64
1622 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1626 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1627 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1628 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1630 vmcs_write32(GUEST_TR_AR_BYTES
,
1631 (guest_tr_ar
& ~AR_TYPE_MASK
)
1632 | AR_TYPE_BUSY_64_TSS
);
1634 vcpu
->arch
.efer
|= EFER_LMA
;
1635 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
1638 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1640 vcpu
->arch
.efer
&= ~EFER_LMA
;
1642 vmcs_write32(VM_ENTRY_CONTROLS
,
1643 vmcs_read32(VM_ENTRY_CONTROLS
)
1644 & ~VM_ENTRY_IA32E_MODE
);
1649 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1651 vpid_sync_vcpu_all(to_vmx(vcpu
));
1653 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1656 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1658 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
1660 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
1661 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
1664 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1666 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1668 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1669 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1672 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1674 if (!test_bit(VCPU_EXREG_PDPTR
,
1675 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1678 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1679 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1680 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1681 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1682 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1686 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1688 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1689 vcpu
->arch
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1690 vcpu
->arch
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1691 vcpu
->arch
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1692 vcpu
->arch
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1695 __set_bit(VCPU_EXREG_PDPTR
,
1696 (unsigned long *)&vcpu
->arch
.regs_avail
);
1697 __set_bit(VCPU_EXREG_PDPTR
,
1698 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1701 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1703 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1705 struct kvm_vcpu
*vcpu
)
1707 if (!(cr0
& X86_CR0_PG
)) {
1708 /* From paging/starting to nonpaging */
1709 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1710 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1711 (CPU_BASED_CR3_LOAD_EXITING
|
1712 CPU_BASED_CR3_STORE_EXITING
));
1713 vcpu
->arch
.cr0
= cr0
;
1714 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1715 } else if (!is_paging(vcpu
)) {
1716 /* From nonpaging to paging */
1717 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1718 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1719 ~(CPU_BASED_CR3_LOAD_EXITING
|
1720 CPU_BASED_CR3_STORE_EXITING
));
1721 vcpu
->arch
.cr0
= cr0
;
1722 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1725 if (!(cr0
& X86_CR0_WP
))
1726 *hw_cr0
&= ~X86_CR0_WP
;
1729 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1731 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1732 unsigned long hw_cr0
;
1734 if (enable_unrestricted_guest
)
1735 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1736 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1738 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1740 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1743 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1746 #ifdef CONFIG_X86_64
1747 if (vcpu
->arch
.efer
& EFER_LME
) {
1748 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1750 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1756 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1758 if (!vcpu
->fpu_active
)
1759 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
1761 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1762 vmcs_writel(GUEST_CR0
, hw_cr0
);
1763 vcpu
->arch
.cr0
= cr0
;
1766 static u64
construct_eptp(unsigned long root_hpa
)
1770 /* TODO write the value reading from MSR */
1771 eptp
= VMX_EPT_DEFAULT_MT
|
1772 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1773 eptp
|= (root_hpa
& PAGE_MASK
);
1778 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1780 unsigned long guest_cr3
;
1785 eptp
= construct_eptp(cr3
);
1786 vmcs_write64(EPT_POINTER
, eptp
);
1787 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1788 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1789 ept_load_pdptrs(vcpu
);
1792 vmx_flush_tlb(vcpu
);
1793 vmcs_writel(GUEST_CR3
, guest_cr3
);
1796 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1798 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1799 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1801 vcpu
->arch
.cr4
= cr4
;
1803 if (!is_paging(vcpu
)) {
1804 hw_cr4
&= ~X86_CR4_PAE
;
1805 hw_cr4
|= X86_CR4_PSE
;
1806 } else if (!(cr4
& X86_CR4_PAE
)) {
1807 hw_cr4
&= ~X86_CR4_PAE
;
1811 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1812 vmcs_writel(GUEST_CR4
, hw_cr4
);
1815 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1817 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1819 return vmcs_readl(sf
->base
);
1822 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1823 struct kvm_segment
*var
, int seg
)
1825 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1828 var
->base
= vmcs_readl(sf
->base
);
1829 var
->limit
= vmcs_read32(sf
->limit
);
1830 var
->selector
= vmcs_read16(sf
->selector
);
1831 ar
= vmcs_read32(sf
->ar_bytes
);
1832 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1834 var
->type
= ar
& 15;
1835 var
->s
= (ar
>> 4) & 1;
1836 var
->dpl
= (ar
>> 5) & 3;
1837 var
->present
= (ar
>> 7) & 1;
1838 var
->avl
= (ar
>> 12) & 1;
1839 var
->l
= (ar
>> 13) & 1;
1840 var
->db
= (ar
>> 14) & 1;
1841 var
->g
= (ar
>> 15) & 1;
1842 var
->unusable
= (ar
>> 16) & 1;
1845 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1847 if (!is_protmode(vcpu
))
1850 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1853 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
1856 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1863 ar
= var
->type
& 15;
1864 ar
|= (var
->s
& 1) << 4;
1865 ar
|= (var
->dpl
& 3) << 5;
1866 ar
|= (var
->present
& 1) << 7;
1867 ar
|= (var
->avl
& 1) << 12;
1868 ar
|= (var
->l
& 1) << 13;
1869 ar
|= (var
->db
& 1) << 14;
1870 ar
|= (var
->g
& 1) << 15;
1872 if (ar
== 0) /* a 0 value means unusable */
1873 ar
= AR_UNUSABLE_MASK
;
1878 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1879 struct kvm_segment
*var
, int seg
)
1881 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1882 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1885 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
1886 vmx
->rmode
.tr
.selector
= var
->selector
;
1887 vmx
->rmode
.tr
.base
= var
->base
;
1888 vmx
->rmode
.tr
.limit
= var
->limit
;
1889 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1892 vmcs_writel(sf
->base
, var
->base
);
1893 vmcs_write32(sf
->limit
, var
->limit
);
1894 vmcs_write16(sf
->selector
, var
->selector
);
1895 if (vmx
->rmode
.vm86_active
&& var
->s
) {
1897 * Hack real-mode segments into vm86 compatibility.
1899 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1900 vmcs_writel(sf
->base
, 0xf0000);
1903 ar
= vmx_segment_access_rights(var
);
1906 * Fix the "Accessed" bit in AR field of segment registers for older
1908 * IA32 arch specifies that at the time of processor reset the
1909 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1910 * is setting it to 0 in the usedland code. This causes invalid guest
1911 * state vmexit when "unrestricted guest" mode is turned on.
1912 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1913 * tree. Newer qemu binaries with that qemu fix would not need this
1916 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
1917 ar
|= 0x1; /* Accessed */
1919 vmcs_write32(sf
->ar_bytes
, ar
);
1922 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1924 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1926 *db
= (ar
>> 14) & 1;
1927 *l
= (ar
>> 13) & 1;
1930 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1932 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1933 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1936 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1938 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1939 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1942 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1944 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1945 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1948 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1950 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1951 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1954 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1956 struct kvm_segment var
;
1959 vmx_get_segment(vcpu
, &var
, seg
);
1960 ar
= vmx_segment_access_rights(&var
);
1962 if (var
.base
!= (var
.selector
<< 4))
1964 if (var
.limit
!= 0xffff)
1972 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
1974 struct kvm_segment cs
;
1975 unsigned int cs_rpl
;
1977 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1978 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
1982 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
1986 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
1987 if (cs
.dpl
> cs_rpl
)
1990 if (cs
.dpl
!= cs_rpl
)
1996 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2000 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2002 struct kvm_segment ss
;
2003 unsigned int ss_rpl
;
2005 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2006 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2010 if (ss
.type
!= 3 && ss
.type
!= 7)
2014 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2022 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2024 struct kvm_segment var
;
2027 vmx_get_segment(vcpu
, &var
, seg
);
2028 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2036 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2037 if (var
.dpl
< rpl
) /* DPL < RPL */
2041 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2047 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2049 struct kvm_segment tr
;
2051 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2055 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2057 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2065 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2067 struct kvm_segment ldtr
;
2069 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2073 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2083 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2085 struct kvm_segment cs
, ss
;
2087 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2088 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2090 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2091 (ss
.selector
& SELECTOR_RPL_MASK
));
2095 * Check if guest state is valid. Returns true if valid, false if
2097 * We assume that registers are always usable
2099 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2101 /* real mode guest state checks */
2102 if (!is_protmode(vcpu
)) {
2103 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2105 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2107 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2109 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2111 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2113 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2116 /* protected mode guest state checks */
2117 if (!cs_ss_rpl_check(vcpu
))
2119 if (!code_segment_valid(vcpu
))
2121 if (!stack_segment_valid(vcpu
))
2123 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2125 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2127 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2129 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2131 if (!tr_valid(vcpu
))
2133 if (!ldtr_valid(vcpu
))
2137 * - Add checks on RIP
2138 * - Add checks on RFLAGS
2144 static int init_rmode_tss(struct kvm
*kvm
)
2146 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2151 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2154 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2155 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2156 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2159 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2162 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2166 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2167 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2177 static int init_rmode_identity_map(struct kvm
*kvm
)
2180 pfn_t identity_map_pfn
;
2185 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2186 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2187 "haven't been allocated!\n");
2190 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2193 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2194 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2197 /* Set up identity-mapping pagetable for EPT in real mode */
2198 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2199 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2200 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2201 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2202 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2206 kvm
->arch
.ept_identity_pagetable_done
= true;
2212 static void seg_setup(int seg
)
2214 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2217 vmcs_write16(sf
->selector
, 0);
2218 vmcs_writel(sf
->base
, 0);
2219 vmcs_write32(sf
->limit
, 0xffff);
2220 if (enable_unrestricted_guest
) {
2222 if (seg
== VCPU_SREG_CS
)
2223 ar
|= 0x08; /* code segment */
2227 vmcs_write32(sf
->ar_bytes
, ar
);
2230 static int alloc_apic_access_page(struct kvm
*kvm
)
2232 struct kvm_userspace_memory_region kvm_userspace_mem
;
2235 mutex_lock(&kvm
->slots_lock
);
2236 if (kvm
->arch
.apic_access_page
)
2238 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2239 kvm_userspace_mem
.flags
= 0;
2240 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2241 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2242 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2246 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2248 mutex_unlock(&kvm
->slots_lock
);
2252 static int alloc_identity_pagetable(struct kvm
*kvm
)
2254 struct kvm_userspace_memory_region kvm_userspace_mem
;
2257 mutex_lock(&kvm
->slots_lock
);
2258 if (kvm
->arch
.ept_identity_pagetable
)
2260 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2261 kvm_userspace_mem
.flags
= 0;
2262 kvm_userspace_mem
.guest_phys_addr
=
2263 kvm
->arch
.ept_identity_map_addr
;
2264 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2265 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2269 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2270 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2272 mutex_unlock(&kvm
->slots_lock
);
2276 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2283 spin_lock(&vmx_vpid_lock
);
2284 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2285 if (vpid
< VMX_NR_VPIDS
) {
2287 __set_bit(vpid
, vmx_vpid_bitmap
);
2289 spin_unlock(&vmx_vpid_lock
);
2292 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2294 int f
= sizeof(unsigned long);
2296 if (!cpu_has_vmx_msr_bitmap())
2300 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2301 * have the write-low and read-high bitmap offsets the wrong way round.
2302 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2304 if (msr
<= 0x1fff) {
2305 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2306 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2307 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2309 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2310 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2314 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2317 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2318 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2322 * Sets up the vmcs for emulated real mode.
2324 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2326 u32 host_sysenter_cs
, msr_low
, msr_high
;
2328 u64 host_pat
, tsc_this
, tsc_base
;
2330 struct descriptor_table dt
;
2332 unsigned long kvm_vmx_return
;
2336 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2337 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2339 if (cpu_has_vmx_msr_bitmap())
2340 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2342 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2345 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2346 vmcs_config
.pin_based_exec_ctrl
);
2348 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2349 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2350 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2351 #ifdef CONFIG_X86_64
2352 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2353 CPU_BASED_CR8_LOAD_EXITING
;
2357 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2358 CPU_BASED_CR3_LOAD_EXITING
|
2359 CPU_BASED_INVLPG_EXITING
;
2360 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2362 if (cpu_has_secondary_exec_ctrls()) {
2363 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2364 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2366 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2368 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2370 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2371 enable_unrestricted_guest
= 0;
2373 if (!enable_unrestricted_guest
)
2374 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2376 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2377 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2381 vmcs_write32(PLE_GAP
, ple_gap
);
2382 vmcs_write32(PLE_WINDOW
, ple_window
);
2385 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2386 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2387 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2389 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2390 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2391 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2393 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2394 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2395 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2396 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2397 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2398 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2399 #ifdef CONFIG_X86_64
2400 rdmsrl(MSR_FS_BASE
, a
);
2401 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2402 rdmsrl(MSR_GS_BASE
, a
);
2403 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2405 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2406 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2409 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2412 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
2414 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2415 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2416 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2417 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2418 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2420 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2421 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2422 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2423 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2424 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2425 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2427 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2428 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2429 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2430 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2432 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2433 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2434 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2435 /* Write the default value follow host pat */
2436 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2437 /* Keep arch.pat sync with GUEST_IA32_PAT */
2438 vmx
->vcpu
.arch
.pat
= host_pat
;
2441 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2442 u32 index
= vmx_msr_index
[i
];
2443 u32 data_low
, data_high
;
2446 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2448 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2450 vmx
->guest_msrs
[j
].index
= i
;
2451 vmx
->guest_msrs
[j
].data
= 0;
2452 vmx
->guest_msrs
[j
].mask
= -1ull;
2456 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2458 /* 22.2.1, 20.8.1 */
2459 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2461 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2462 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2464 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2465 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2467 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2469 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2470 tsc_base
= tsc_this
;
2472 guest_write_tsc(0, tsc_base
);
2477 static int init_rmode(struct kvm
*kvm
)
2479 if (!init_rmode_tss(kvm
))
2481 if (!init_rmode_identity_map(kvm
))
2486 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2488 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2492 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2493 idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2494 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2499 vmx
->rmode
.vm86_active
= 0;
2501 vmx
->soft_vnmi_blocked
= 0;
2503 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2504 kvm_set_cr8(&vmx
->vcpu
, 0);
2505 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2506 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2507 msr
|= MSR_IA32_APICBASE_BSP
;
2508 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2510 fx_init(&vmx
->vcpu
);
2512 seg_setup(VCPU_SREG_CS
);
2514 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2515 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2517 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2518 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2519 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2521 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2522 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2525 seg_setup(VCPU_SREG_DS
);
2526 seg_setup(VCPU_SREG_ES
);
2527 seg_setup(VCPU_SREG_FS
);
2528 seg_setup(VCPU_SREG_GS
);
2529 seg_setup(VCPU_SREG_SS
);
2531 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2532 vmcs_writel(GUEST_TR_BASE
, 0);
2533 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2534 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2536 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2537 vmcs_writel(GUEST_LDTR_BASE
, 0);
2538 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2539 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2541 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2542 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2543 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2545 vmcs_writel(GUEST_RFLAGS
, 0x02);
2546 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2547 kvm_rip_write(vcpu
, 0xfff0);
2549 kvm_rip_write(vcpu
, 0);
2550 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2552 vmcs_writel(GUEST_DR7
, 0x400);
2554 vmcs_writel(GUEST_GDTR_BASE
, 0);
2555 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2557 vmcs_writel(GUEST_IDTR_BASE
, 0);
2558 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2560 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2561 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2562 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2564 /* Special registers */
2565 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2569 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2571 if (cpu_has_vmx_tpr_shadow()) {
2572 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2573 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2574 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2575 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2576 vmcs_write32(TPR_THRESHOLD
, 0);
2579 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2580 vmcs_write64(APIC_ACCESS_ADDR
,
2581 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2584 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2586 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2587 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
2588 vmx_set_cr4(&vmx
->vcpu
, 0);
2589 vmx_set_efer(&vmx
->vcpu
, 0);
2590 vmx_fpu_activate(&vmx
->vcpu
);
2591 update_exception_bitmap(&vmx
->vcpu
);
2593 vpid_sync_vcpu_all(vmx
);
2597 /* HACK: Don't enable emulation on guest boot/reset */
2598 vmx
->emulation_required
= 0;
2601 srcu_read_unlock(&vcpu
->kvm
->srcu
, idx
);
2605 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2607 u32 cpu_based_vm_exec_control
;
2609 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2610 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2611 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2614 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2616 u32 cpu_based_vm_exec_control
;
2618 if (!cpu_has_virtual_nmis()) {
2619 enable_irq_window(vcpu
);
2623 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2624 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2625 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2628 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2632 int irq
= vcpu
->arch
.interrupt
.nr
;
2634 trace_kvm_inj_virq(irq
);
2636 ++vcpu
->stat
.irq_injections
;
2637 if (vmx
->rmode
.vm86_active
) {
2638 vmx
->rmode
.irq
.pending
= true;
2639 vmx
->rmode
.irq
.vector
= irq
;
2640 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2641 if (vcpu
->arch
.interrupt
.soft
)
2642 vmx
->rmode
.irq
.rip
+=
2643 vmx
->vcpu
.arch
.event_exit_inst_len
;
2644 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2645 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2646 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2647 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2650 intr
= irq
| INTR_INFO_VALID_MASK
;
2651 if (vcpu
->arch
.interrupt
.soft
) {
2652 intr
|= INTR_TYPE_SOFT_INTR
;
2653 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2654 vmx
->vcpu
.arch
.event_exit_inst_len
);
2656 intr
|= INTR_TYPE_EXT_INTR
;
2657 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2660 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2664 if (!cpu_has_virtual_nmis()) {
2666 * Tracking the NMI-blocked state in software is built upon
2667 * finding the next open IRQ window. This, in turn, depends on
2668 * well-behaving guests: They have to keep IRQs disabled at
2669 * least as long as the NMI handler runs. Otherwise we may
2670 * cause NMI nesting, maybe breaking the guest. But as this is
2671 * highly unlikely, we can live with the residual risk.
2673 vmx
->soft_vnmi_blocked
= 1;
2674 vmx
->vnmi_blocked_time
= 0;
2677 ++vcpu
->stat
.nmi_injections
;
2678 if (vmx
->rmode
.vm86_active
) {
2679 vmx
->rmode
.irq
.pending
= true;
2680 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2681 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2682 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2683 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2684 INTR_INFO_VALID_MASK
);
2685 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2686 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2689 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2690 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2693 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2695 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2698 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2699 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
|
2700 GUEST_INTR_STATE_NMI
));
2703 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2705 if (!cpu_has_virtual_nmis())
2706 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2708 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2709 GUEST_INTR_STATE_NMI
);
2712 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2714 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2716 if (!cpu_has_virtual_nmis()) {
2717 if (vmx
->soft_vnmi_blocked
!= masked
) {
2718 vmx
->soft_vnmi_blocked
= masked
;
2719 vmx
->vnmi_blocked_time
= 0;
2723 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2724 GUEST_INTR_STATE_NMI
);
2726 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2727 GUEST_INTR_STATE_NMI
);
2731 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2733 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2734 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2735 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2738 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2741 struct kvm_userspace_memory_region tss_mem
= {
2742 .slot
= TSS_PRIVATE_MEMSLOT
,
2743 .guest_phys_addr
= addr
,
2744 .memory_size
= PAGE_SIZE
* 3,
2748 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2751 kvm
->arch
.tss_addr
= addr
;
2755 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2756 int vec
, u32 err_code
)
2759 * Instruction with address size override prefix opcode 0x67
2760 * Cause the #SS fault with 0 error code in VM86 mode.
2762 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2763 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
)
2766 * Forward all other exceptions that are valid in real mode.
2767 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2768 * the required debugging infrastructure rework.
2772 if (vcpu
->guest_debug
&
2773 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2775 kvm_queue_exception(vcpu
, vec
);
2779 * Update instruction length as we may reinject the exception
2780 * from user space while in guest debugging mode.
2782 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
2783 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2784 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2795 kvm_queue_exception(vcpu
, vec
);
2802 * Trigger machine check on the host. We assume all the MSRs are already set up
2803 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2804 * We pass a fake environment to the machine check handler because we want
2805 * the guest to be always treated like user space, no matter what context
2806 * it used internally.
2808 static void kvm_machine_check(void)
2810 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2811 struct pt_regs regs
= {
2812 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
2813 .flags
= X86_EFLAGS_IF
,
2816 do_machine_check(®s
, 0);
2820 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
2822 /* already handled by vcpu_run */
2826 static int handle_exception(struct kvm_vcpu
*vcpu
)
2828 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2829 struct kvm_run
*kvm_run
= vcpu
->run
;
2830 u32 intr_info
, ex_no
, error_code
;
2831 unsigned long cr2
, rip
, dr6
;
2833 enum emulation_result er
;
2835 vect_info
= vmx
->idt_vectoring_info
;
2836 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2838 if (is_machine_check(intr_info
))
2839 return handle_machine_check(vcpu
);
2841 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2842 !is_page_fault(intr_info
)) {
2843 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
2844 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
2845 vcpu
->run
->internal
.ndata
= 2;
2846 vcpu
->run
->internal
.data
[0] = vect_info
;
2847 vcpu
->run
->internal
.data
[1] = intr_info
;
2851 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2852 return 1; /* already handled by vmx_vcpu_run() */
2854 if (is_no_device(intr_info
)) {
2855 vmx_fpu_activate(vcpu
);
2859 if (is_invalid_opcode(intr_info
)) {
2860 er
= emulate_instruction(vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
2861 if (er
!= EMULATE_DONE
)
2862 kvm_queue_exception(vcpu
, UD_VECTOR
);
2867 rip
= kvm_rip_read(vcpu
);
2868 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2869 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2870 if (is_page_fault(intr_info
)) {
2871 /* EPT won't cause page fault directly */
2874 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2875 trace_kvm_page_fault(cr2
, error_code
);
2877 if (kvm_event_needs_reinjection(vcpu
))
2878 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
2879 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2882 if (vmx
->rmode
.vm86_active
&&
2883 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2885 if (vcpu
->arch
.halt_request
) {
2886 vcpu
->arch
.halt_request
= 0;
2887 return kvm_emulate_halt(vcpu
);
2892 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
2895 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
2896 if (!(vcpu
->guest_debug
&
2897 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
2898 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
2899 kvm_queue_exception(vcpu
, DB_VECTOR
);
2902 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
2903 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
2907 * Update instruction length as we may reinject #BP from
2908 * user space while in guest debugging mode. Reading it for
2909 * #DB as well causes no harm, it is not used in that case.
2911 vmx
->vcpu
.arch
.event_exit_inst_len
=
2912 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2913 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2914 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
2915 kvm_run
->debug
.arch
.exception
= ex_no
;
2918 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2919 kvm_run
->ex
.exception
= ex_no
;
2920 kvm_run
->ex
.error_code
= error_code
;
2926 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
2928 ++vcpu
->stat
.irq_exits
;
2932 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
2934 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2938 static int handle_io(struct kvm_vcpu
*vcpu
)
2940 unsigned long exit_qualification
;
2941 int size
, in
, string
;
2944 ++vcpu
->stat
.io_exits
;
2945 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2946 string
= (exit_qualification
& 16) != 0;
2949 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DO_MMIO
)
2954 size
= (exit_qualification
& 7) + 1;
2955 in
= (exit_qualification
& 8) != 0;
2956 port
= exit_qualification
>> 16;
2958 skip_emulated_instruction(vcpu
);
2959 return kvm_emulate_pio(vcpu
, in
, size
, port
);
2963 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2966 * Patch in the VMCALL instruction:
2968 hypercall
[0] = 0x0f;
2969 hypercall
[1] = 0x01;
2970 hypercall
[2] = 0xc1;
2973 static int handle_cr(struct kvm_vcpu
*vcpu
)
2975 unsigned long exit_qualification
, val
;
2979 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2980 cr
= exit_qualification
& 15;
2981 reg
= (exit_qualification
>> 8) & 15;
2982 switch ((exit_qualification
>> 4) & 3) {
2983 case 0: /* mov to cr */
2984 val
= kvm_register_read(vcpu
, reg
);
2985 trace_kvm_cr_write(cr
, val
);
2988 kvm_set_cr0(vcpu
, val
);
2989 skip_emulated_instruction(vcpu
);
2992 kvm_set_cr3(vcpu
, val
);
2993 skip_emulated_instruction(vcpu
);
2996 kvm_set_cr4(vcpu
, val
);
2997 skip_emulated_instruction(vcpu
);
3000 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3001 u8 cr8
= kvm_register_read(vcpu
, reg
);
3002 kvm_set_cr8(vcpu
, cr8
);
3003 skip_emulated_instruction(vcpu
);
3004 if (irqchip_in_kernel(vcpu
->kvm
))
3006 if (cr8_prev
<= cr8
)
3008 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3014 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3015 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3016 skip_emulated_instruction(vcpu
);
3017 vmx_fpu_activate(vcpu
);
3019 case 1: /*mov from cr*/
3022 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3023 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3024 skip_emulated_instruction(vcpu
);
3027 val
= kvm_get_cr8(vcpu
);
3028 kvm_register_write(vcpu
, reg
, val
);
3029 trace_kvm_cr_read(cr
, val
);
3030 skip_emulated_instruction(vcpu
);
3035 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3036 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3037 kvm_lmsw(vcpu
, val
);
3039 skip_emulated_instruction(vcpu
);
3044 vcpu
->run
->exit_reason
= 0;
3045 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3046 (int)(exit_qualification
>> 4) & 3, cr
);
3050 static int check_dr_alias(struct kvm_vcpu
*vcpu
)
3052 if (kvm_read_cr4_bits(vcpu
, X86_CR4_DE
)) {
3053 kvm_queue_exception(vcpu
, UD_VECTOR
);
3059 static int handle_dr(struct kvm_vcpu
*vcpu
)
3061 unsigned long exit_qualification
;
3065 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3066 if (!kvm_require_cpl(vcpu
, 0))
3068 dr
= vmcs_readl(GUEST_DR7
);
3071 * As the vm-exit takes precedence over the debug trap, we
3072 * need to emulate the latter, either for the host or the
3073 * guest debugging itself.
3075 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3076 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3077 vcpu
->run
->debug
.arch
.dr7
= dr
;
3078 vcpu
->run
->debug
.arch
.pc
=
3079 vmcs_readl(GUEST_CS_BASE
) +
3080 vmcs_readl(GUEST_RIP
);
3081 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3082 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3085 vcpu
->arch
.dr7
&= ~DR7_GD
;
3086 vcpu
->arch
.dr6
|= DR6_BD
;
3087 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3088 kvm_queue_exception(vcpu
, DB_VECTOR
);
3093 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3094 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3095 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3096 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3099 val
= vcpu
->arch
.db
[dr
];
3102 if (check_dr_alias(vcpu
) < 0)
3106 val
= vcpu
->arch
.dr6
;
3109 if (check_dr_alias(vcpu
) < 0)
3113 val
= vcpu
->arch
.dr7
;
3116 kvm_register_write(vcpu
, reg
, val
);
3118 val
= vcpu
->arch
.regs
[reg
];
3121 vcpu
->arch
.db
[dr
] = val
;
3122 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
3123 vcpu
->arch
.eff_db
[dr
] = val
;
3126 if (check_dr_alias(vcpu
) < 0)
3130 if (val
& 0xffffffff00000000ULL
) {
3131 kvm_inject_gp(vcpu
, 0);
3134 vcpu
->arch
.dr6
= (val
& DR6_VOLATILE
) | DR6_FIXED_1
;
3137 if (check_dr_alias(vcpu
) < 0)
3141 if (val
& 0xffffffff00000000ULL
) {
3142 kvm_inject_gp(vcpu
, 0);
3145 vcpu
->arch
.dr7
= (val
& DR7_VOLATILE
) | DR7_FIXED_1
;
3146 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
3147 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3148 vcpu
->arch
.switch_db_regs
=
3149 (val
& DR7_BP_EN_MASK
);
3154 skip_emulated_instruction(vcpu
);
3158 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3160 kvm_emulate_cpuid(vcpu
);
3164 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3166 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3169 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3170 trace_kvm_msr_read_ex(ecx
);
3171 kvm_inject_gp(vcpu
, 0);
3175 trace_kvm_msr_read(ecx
, data
);
3177 /* FIXME: handling of bits 32:63 of rax, rdx */
3178 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3179 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3180 skip_emulated_instruction(vcpu
);
3184 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3186 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3187 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3188 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3190 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3191 trace_kvm_msr_write_ex(ecx
, data
);
3192 kvm_inject_gp(vcpu
, 0);
3196 trace_kvm_msr_write(ecx
, data
);
3197 skip_emulated_instruction(vcpu
);
3201 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3206 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3208 u32 cpu_based_vm_exec_control
;
3210 /* clear pending irq */
3211 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3212 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3213 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3215 ++vcpu
->stat
.irq_window_exits
;
3218 * If the user space waits to inject interrupts, exit as soon as
3221 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3222 vcpu
->run
->request_interrupt_window
&&
3223 !kvm_cpu_has_interrupt(vcpu
)) {
3224 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3230 static int handle_halt(struct kvm_vcpu
*vcpu
)
3232 skip_emulated_instruction(vcpu
);
3233 return kvm_emulate_halt(vcpu
);
3236 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3238 skip_emulated_instruction(vcpu
);
3239 kvm_emulate_hypercall(vcpu
);
3243 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3245 kvm_queue_exception(vcpu
, UD_VECTOR
);
3249 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3251 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3253 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3254 skip_emulated_instruction(vcpu
);
3258 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3260 skip_emulated_instruction(vcpu
);
3261 /* TODO: Add support for VT-d/pass-through device */
3265 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3267 unsigned long exit_qualification
;
3268 enum emulation_result er
;
3269 unsigned long offset
;
3271 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3272 offset
= exit_qualification
& 0xffful
;
3274 er
= emulate_instruction(vcpu
, 0, 0, 0);
3276 if (er
!= EMULATE_DONE
) {
3278 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3285 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3287 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3288 unsigned long exit_qualification
;
3290 int reason
, type
, idt_v
;
3292 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3293 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3295 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3297 reason
= (u32
)exit_qualification
>> 30;
3298 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3300 case INTR_TYPE_NMI_INTR
:
3301 vcpu
->arch
.nmi_injected
= false;
3302 if (cpu_has_virtual_nmis())
3303 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3304 GUEST_INTR_STATE_NMI
);
3306 case INTR_TYPE_EXT_INTR
:
3307 case INTR_TYPE_SOFT_INTR
:
3308 kvm_clear_interrupt_queue(vcpu
);
3310 case INTR_TYPE_HARD_EXCEPTION
:
3311 case INTR_TYPE_SOFT_EXCEPTION
:
3312 kvm_clear_exception_queue(vcpu
);
3318 tss_selector
= exit_qualification
;
3320 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3321 type
!= INTR_TYPE_EXT_INTR
&&
3322 type
!= INTR_TYPE_NMI_INTR
))
3323 skip_emulated_instruction(vcpu
);
3325 if (!kvm_task_switch(vcpu
, tss_selector
, reason
))
3328 /* clear all local breakpoint enable flags */
3329 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3332 * TODO: What about debug traps on tss switch?
3333 * Are we supposed to inject them and update dr6?
3339 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3341 unsigned long exit_qualification
;
3345 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3347 if (exit_qualification
& (1 << 6)) {
3348 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3352 gla_validity
= (exit_qualification
>> 7) & 0x3;
3353 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3354 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3355 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3356 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3357 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3358 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3359 (long unsigned int)exit_qualification
);
3360 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3361 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3365 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3366 trace_kvm_page_fault(gpa
, exit_qualification
);
3367 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3370 static u64
ept_rsvd_mask(u64 spte
, int level
)
3375 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3376 mask
|= (1ULL << i
);
3379 /* bits 7:3 reserved */
3381 else if (level
== 2) {
3382 if (spte
& (1ULL << 7))
3383 /* 2MB ref, bits 20:12 reserved */
3386 /* bits 6:3 reserved */
3393 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3396 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3398 /* 010b (write-only) */
3399 WARN_ON((spte
& 0x7) == 0x2);
3401 /* 110b (write/execute) */
3402 WARN_ON((spte
& 0x7) == 0x6);
3404 /* 100b (execute-only) and value not supported by logical processor */
3405 if (!cpu_has_vmx_ept_execute_only())
3406 WARN_ON((spte
& 0x7) == 0x4);
3410 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3412 if (rsvd_bits
!= 0) {
3413 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3414 __func__
, rsvd_bits
);
3418 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3419 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3421 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3422 ept_mem_type
== 7) {
3423 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3424 __func__
, ept_mem_type
);
3431 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3437 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3439 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3440 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3442 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3444 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3445 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3447 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3448 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3453 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3455 u32 cpu_based_vm_exec_control
;
3457 /* clear pending NMI */
3458 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3459 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3461 ++vcpu
->stat
.nmi_window_exits
;
3466 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3469 enum emulation_result err
= EMULATE_DONE
;
3472 while (!guest_state_valid(vcpu
)) {
3473 err
= emulate_instruction(vcpu
, 0, 0, 0);
3475 if (err
== EMULATE_DO_MMIO
) {
3480 if (err
!= EMULATE_DONE
) {
3481 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3482 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3483 vcpu
->run
->internal
.ndata
= 0;
3488 if (signal_pending(current
))
3494 vmx
->emulation_required
= 0;
3500 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3501 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3503 static int handle_pause(struct kvm_vcpu
*vcpu
)
3505 skip_emulated_instruction(vcpu
);
3506 kvm_vcpu_on_spin(vcpu
);
3511 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3513 kvm_queue_exception(vcpu
, UD_VECTOR
);
3518 * The exit handlers return 1 if the exit was handled fully and guest execution
3519 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3520 * to be done to userspace and return 0.
3522 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3523 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3524 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3525 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3526 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3527 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3528 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3529 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3530 [EXIT_REASON_CPUID
] = handle_cpuid
,
3531 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3532 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3533 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3534 [EXIT_REASON_HLT
] = handle_halt
,
3535 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3536 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3537 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3538 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3539 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3540 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3541 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3542 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3543 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3544 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3545 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3546 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3547 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3548 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3549 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3550 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3551 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3552 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3553 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3554 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3555 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3558 static const int kvm_vmx_max_exit_handlers
=
3559 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3562 * The guest has exited. See if we can fix it or if we need userspace
3565 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3567 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3568 u32 exit_reason
= vmx
->exit_reason
;
3569 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3571 trace_kvm_exit(exit_reason
, kvm_rip_read(vcpu
));
3573 /* If guest state is invalid, start emulating */
3574 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3575 return handle_invalid_guest_state(vcpu
);
3577 /* Access CR3 don't cause VMExit in paging mode, so we need
3578 * to sync with guest real CR3. */
3579 if (enable_ept
&& is_paging(vcpu
))
3580 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3582 if (unlikely(vmx
->fail
)) {
3583 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3584 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3585 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3589 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3590 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3591 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3592 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3593 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3594 "(0x%x) and exit reason is 0x%x\n",
3595 __func__
, vectoring_info
, exit_reason
);
3597 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3598 if (vmx_interrupt_allowed(vcpu
)) {
3599 vmx
->soft_vnmi_blocked
= 0;
3600 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3601 vcpu
->arch
.nmi_pending
) {
3603 * This CPU don't support us in finding the end of an
3604 * NMI-blocked window if the guest runs with IRQs
3605 * disabled. So we pull the trigger after 1 s of
3606 * futile waiting, but inform the user about this.
3608 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3609 "state on VCPU %d after 1 s timeout\n",
3610 __func__
, vcpu
->vcpu_id
);
3611 vmx
->soft_vnmi_blocked
= 0;
3615 if (exit_reason
< kvm_vmx_max_exit_handlers
3616 && kvm_vmx_exit_handlers
[exit_reason
])
3617 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3619 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3620 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3625 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3627 if (irr
== -1 || tpr
< irr
) {
3628 vmcs_write32(TPR_THRESHOLD
, 0);
3632 vmcs_write32(TPR_THRESHOLD
, irr
);
3635 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3638 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3642 bool idtv_info_valid
;
3644 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3646 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3648 /* Handle machine checks before interrupts are enabled */
3649 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3650 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3651 && is_machine_check(exit_intr_info
)))
3652 kvm_machine_check();
3654 /* We need to handle NMIs before interrupts are enabled */
3655 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3656 (exit_intr_info
& INTR_INFO_VALID_MASK
))
3659 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3661 if (cpu_has_virtual_nmis()) {
3662 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3663 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3665 * SDM 3: 27.7.1.2 (September 2008)
3666 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3667 * a guest IRET fault.
3668 * SDM 3: 23.2.2 (September 2008)
3669 * Bit 12 is undefined in any of the following cases:
3670 * If the VM exit sets the valid bit in the IDT-vectoring
3671 * information field.
3672 * If the VM exit is due to a double fault.
3674 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3675 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3676 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3677 GUEST_INTR_STATE_NMI
);
3678 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3679 vmx
->vnmi_blocked_time
+=
3680 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3682 vmx
->vcpu
.arch
.nmi_injected
= false;
3683 kvm_clear_exception_queue(&vmx
->vcpu
);
3684 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3686 if (!idtv_info_valid
)
3689 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3690 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3693 case INTR_TYPE_NMI_INTR
:
3694 vmx
->vcpu
.arch
.nmi_injected
= true;
3696 * SDM 3: 27.7.1.2 (September 2008)
3697 * Clear bit "block by NMI" before VM entry if a NMI
3700 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3701 GUEST_INTR_STATE_NMI
);
3703 case INTR_TYPE_SOFT_EXCEPTION
:
3704 vmx
->vcpu
.arch
.event_exit_inst_len
=
3705 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3707 case INTR_TYPE_HARD_EXCEPTION
:
3708 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3709 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3710 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3712 kvm_queue_exception(&vmx
->vcpu
, vector
);
3714 case INTR_TYPE_SOFT_INTR
:
3715 vmx
->vcpu
.arch
.event_exit_inst_len
=
3716 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3718 case INTR_TYPE_EXT_INTR
:
3719 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3720 type
== INTR_TYPE_SOFT_INTR
);
3728 * Failure to inject an interrupt should give us the information
3729 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3730 * when fetching the interrupt redirection bitmap in the real-mode
3731 * tss, this doesn't happen. So we do it ourselves.
3733 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3735 vmx
->rmode
.irq
.pending
= 0;
3736 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3738 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3739 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3740 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3741 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3744 vmx
->idt_vectoring_info
=
3745 VECTORING_INFO_VALID_MASK
3746 | INTR_TYPE_EXT_INTR
3747 | vmx
->rmode
.irq
.vector
;
3750 #ifdef CONFIG_X86_64
3758 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3760 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3762 /* Record the guest's net vcpu time for enforced NMI injections. */
3763 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3764 vmx
->entry_time
= ktime_get();
3766 /* Don't enter VMX if guest state is invalid, let the exit handler
3767 start emulation until we arrive back to a valid state */
3768 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3771 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3772 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3773 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3774 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3776 /* When single-stepping over STI and MOV SS, we must clear the
3777 * corresponding interruptibility bits in the guest state. Otherwise
3778 * vmentry fails as it then expects bit 14 (BS) in pending debug
3779 * exceptions being set, but that's not correct for the guest debugging
3781 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3782 vmx_set_interrupt_shadow(vcpu
, 0);
3785 * Loading guest fpu may have cleared host cr0.ts
3787 vmcs_writel(HOST_CR0
, read_cr0());
3790 /* Store host registers */
3791 "push %%"R
"dx; push %%"R
"bp;"
3793 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3795 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3796 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3798 /* Reload cr2 if changed */
3799 "mov %c[cr2](%0), %%"R
"ax \n\t"
3800 "mov %%cr2, %%"R
"dx \n\t"
3801 "cmp %%"R
"ax, %%"R
"dx \n\t"
3803 "mov %%"R
"ax, %%cr2 \n\t"
3805 /* Check if vmlaunch of vmresume is needed */
3806 "cmpl $0, %c[launched](%0) \n\t"
3807 /* Load guest registers. Don't clobber flags. */
3808 "mov %c[rax](%0), %%"R
"ax \n\t"
3809 "mov %c[rbx](%0), %%"R
"bx \n\t"
3810 "mov %c[rdx](%0), %%"R
"dx \n\t"
3811 "mov %c[rsi](%0), %%"R
"si \n\t"
3812 "mov %c[rdi](%0), %%"R
"di \n\t"
3813 "mov %c[rbp](%0), %%"R
"bp \n\t"
3814 #ifdef CONFIG_X86_64
3815 "mov %c[r8](%0), %%r8 \n\t"
3816 "mov %c[r9](%0), %%r9 \n\t"
3817 "mov %c[r10](%0), %%r10 \n\t"
3818 "mov %c[r11](%0), %%r11 \n\t"
3819 "mov %c[r12](%0), %%r12 \n\t"
3820 "mov %c[r13](%0), %%r13 \n\t"
3821 "mov %c[r14](%0), %%r14 \n\t"
3822 "mov %c[r15](%0), %%r15 \n\t"
3824 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3826 /* Enter guest mode */
3827 "jne .Llaunched \n\t"
3828 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3829 "jmp .Lkvm_vmx_return \n\t"
3830 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3831 ".Lkvm_vmx_return: "
3832 /* Save guest registers, load host registers, keep flags */
3833 "xchg %0, (%%"R
"sp) \n\t"
3834 "mov %%"R
"ax, %c[rax](%0) \n\t"
3835 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3836 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3837 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3838 "mov %%"R
"si, %c[rsi](%0) \n\t"
3839 "mov %%"R
"di, %c[rdi](%0) \n\t"
3840 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3841 #ifdef CONFIG_X86_64
3842 "mov %%r8, %c[r8](%0) \n\t"
3843 "mov %%r9, %c[r9](%0) \n\t"
3844 "mov %%r10, %c[r10](%0) \n\t"
3845 "mov %%r11, %c[r11](%0) \n\t"
3846 "mov %%r12, %c[r12](%0) \n\t"
3847 "mov %%r13, %c[r13](%0) \n\t"
3848 "mov %%r14, %c[r14](%0) \n\t"
3849 "mov %%r15, %c[r15](%0) \n\t"
3851 "mov %%cr2, %%"R
"ax \n\t"
3852 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3854 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3855 "setbe %c[fail](%0) \n\t"
3856 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3857 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3858 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3859 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3860 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3861 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3862 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3863 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3864 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3865 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3866 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3867 #ifdef CONFIG_X86_64
3868 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3869 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3870 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3871 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3872 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3873 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3874 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3875 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3877 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3879 , R
"bx", R
"di", R
"si"
3880 #ifdef CONFIG_X86_64
3881 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3885 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
3886 | (1 << VCPU_EXREG_PDPTR
));
3887 vcpu
->arch
.regs_dirty
= 0;
3889 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3890 if (vmx
->rmode
.irq
.pending
)
3891 fixup_rmode_irq(vmx
);
3893 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3896 vmx_complete_interrupts(vmx
);
3902 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3908 free_vmcs(vmx
->vmcs
);
3913 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3915 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3917 spin_lock(&vmx_vpid_lock
);
3919 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3920 spin_unlock(&vmx_vpid_lock
);
3921 vmx_free_vmcs(vcpu
);
3922 kfree(vmx
->guest_msrs
);
3923 kvm_vcpu_uninit(vcpu
);
3924 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3927 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
3930 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
3934 return ERR_PTR(-ENOMEM
);
3938 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
3942 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3943 if (!vmx
->guest_msrs
) {
3948 vmx
->vmcs
= alloc_vmcs();
3952 vmcs_clear(vmx
->vmcs
);
3955 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
3956 err
= vmx_vcpu_setup(vmx
);
3957 vmx_vcpu_put(&vmx
->vcpu
);
3961 if (vm_need_virtualize_apic_accesses(kvm
))
3962 if (alloc_apic_access_page(kvm
) != 0)
3966 if (!kvm
->arch
.ept_identity_map_addr
)
3967 kvm
->arch
.ept_identity_map_addr
=
3968 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
3969 if (alloc_identity_pagetable(kvm
) != 0)
3976 free_vmcs(vmx
->vmcs
);
3978 kfree(vmx
->guest_msrs
);
3980 kvm_vcpu_uninit(&vmx
->vcpu
);
3982 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3983 return ERR_PTR(err
);
3986 static void __init
vmx_check_processor_compat(void *rtn
)
3988 struct vmcs_config vmcs_conf
;
3991 if (setup_vmcs_config(&vmcs_conf
) < 0)
3993 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
3994 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
3995 smp_processor_id());
4000 static int get_ept_level(void)
4002 return VMX_EPT_DEFAULT_GAW
+ 1;
4005 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4009 /* For VT-d and EPT combination
4010 * 1. MMIO: always map as UC
4012 * a. VT-d without snooping control feature: can't guarantee the
4013 * result, try to trust guest.
4014 * b. VT-d with snooping control feature: snooping control feature of
4015 * VT-d engine can guarantee the cache correctness. Just set it
4016 * to WB to keep consistent with host. So the same as item 3.
4017 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4018 * consistent with host MTRR
4021 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4022 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4023 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4024 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4025 VMX_EPT_MT_EPTE_SHIFT
;
4027 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4033 #define _ER(x) { EXIT_REASON_##x, #x }
4035 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4037 _ER(EXTERNAL_INTERRUPT
),
4039 _ER(PENDING_INTERRUPT
),
4059 _ER(IO_INSTRUCTION
),
4062 _ER(MWAIT_INSTRUCTION
),
4063 _ER(MONITOR_INSTRUCTION
),
4064 _ER(PAUSE_INSTRUCTION
),
4065 _ER(MCE_DURING_VMENTRY
),
4066 _ER(TPR_BELOW_THRESHOLD
),
4076 static int vmx_get_lpage_level(void)
4078 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
4079 return PT_DIRECTORY_LEVEL
;
4081 /* For shadow and EPT supported 1GB page */
4082 return PT_PDPE_LEVEL
;
4085 static inline u32
bit(int bitno
)
4087 return 1 << (bitno
& 31);
4090 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4092 struct kvm_cpuid_entry2
*best
;
4093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4096 vmx
->rdtscp_enabled
= false;
4097 if (vmx_rdtscp_supported()) {
4098 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4099 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4100 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4101 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4102 vmx
->rdtscp_enabled
= true;
4104 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4105 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4112 static struct kvm_x86_ops vmx_x86_ops
= {
4113 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4114 .disabled_by_bios
= vmx_disabled_by_bios
,
4115 .hardware_setup
= hardware_setup
,
4116 .hardware_unsetup
= hardware_unsetup
,
4117 .check_processor_compatibility
= vmx_check_processor_compat
,
4118 .hardware_enable
= hardware_enable
,
4119 .hardware_disable
= hardware_disable
,
4120 .cpu_has_accelerated_tpr
= report_flexpriority
,
4122 .vcpu_create
= vmx_create_vcpu
,
4123 .vcpu_free
= vmx_free_vcpu
,
4124 .vcpu_reset
= vmx_vcpu_reset
,
4126 .prepare_guest_switch
= vmx_save_host_state
,
4127 .vcpu_load
= vmx_vcpu_load
,
4128 .vcpu_put
= vmx_vcpu_put
,
4130 .set_guest_debug
= set_guest_debug
,
4131 .get_msr
= vmx_get_msr
,
4132 .set_msr
= vmx_set_msr
,
4133 .get_segment_base
= vmx_get_segment_base
,
4134 .get_segment
= vmx_get_segment
,
4135 .set_segment
= vmx_set_segment
,
4136 .get_cpl
= vmx_get_cpl
,
4137 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4138 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
4139 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4140 .set_cr0
= vmx_set_cr0
,
4141 .set_cr3
= vmx_set_cr3
,
4142 .set_cr4
= vmx_set_cr4
,
4143 .set_efer
= vmx_set_efer
,
4144 .get_idt
= vmx_get_idt
,
4145 .set_idt
= vmx_set_idt
,
4146 .get_gdt
= vmx_get_gdt
,
4147 .set_gdt
= vmx_set_gdt
,
4148 .cache_reg
= vmx_cache_reg
,
4149 .get_rflags
= vmx_get_rflags
,
4150 .set_rflags
= vmx_set_rflags
,
4151 .fpu_activate
= vmx_fpu_activate
,
4152 .fpu_deactivate
= vmx_fpu_deactivate
,
4154 .tlb_flush
= vmx_flush_tlb
,
4156 .run
= vmx_vcpu_run
,
4157 .handle_exit
= vmx_handle_exit
,
4158 .skip_emulated_instruction
= skip_emulated_instruction
,
4159 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4160 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4161 .patch_hypercall
= vmx_patch_hypercall
,
4162 .set_irq
= vmx_inject_irq
,
4163 .set_nmi
= vmx_inject_nmi
,
4164 .queue_exception
= vmx_queue_exception
,
4165 .interrupt_allowed
= vmx_interrupt_allowed
,
4166 .nmi_allowed
= vmx_nmi_allowed
,
4167 .get_nmi_mask
= vmx_get_nmi_mask
,
4168 .set_nmi_mask
= vmx_set_nmi_mask
,
4169 .enable_nmi_window
= enable_nmi_window
,
4170 .enable_irq_window
= enable_irq_window
,
4171 .update_cr8_intercept
= update_cr8_intercept
,
4173 .set_tss_addr
= vmx_set_tss_addr
,
4174 .get_tdp_level
= get_ept_level
,
4175 .get_mt_mask
= vmx_get_mt_mask
,
4177 .exit_reasons_str
= vmx_exit_reasons_str
,
4178 .get_lpage_level
= vmx_get_lpage_level
,
4180 .cpuid_update
= vmx_cpuid_update
,
4182 .rdtscp_supported
= vmx_rdtscp_supported
,
4185 static int __init
vmx_init(void)
4189 rdmsrl_safe(MSR_EFER
, &host_efer
);
4191 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4192 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4194 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4195 if (!vmx_io_bitmap_a
)
4198 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4199 if (!vmx_io_bitmap_b
) {
4204 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4205 if (!vmx_msr_bitmap_legacy
) {
4210 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4211 if (!vmx_msr_bitmap_longmode
) {
4217 * Allow direct access to the PC debug port (it is often used for I/O
4218 * delays, but the vmexits simply slow things down).
4220 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4221 clear_bit(0x80, vmx_io_bitmap_a
);
4223 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4225 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4226 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4228 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4230 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
4234 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4235 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4236 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4237 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4238 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4239 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4242 bypass_guest_pf
= 0;
4243 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
4244 VMX_EPT_WRITABLE_MASK
);
4245 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4246 VMX_EPT_EXECUTABLE_MASK
);
4251 if (bypass_guest_pf
)
4252 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4257 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4259 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4261 free_page((unsigned long)vmx_io_bitmap_b
);
4263 free_page((unsigned long)vmx_io_bitmap_a
);
4267 static void __exit
vmx_exit(void)
4269 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4270 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4271 free_page((unsigned long)vmx_io_bitmap_b
);
4272 free_page((unsigned long)vmx_io_bitmap_a
);
4277 module_init(vmx_init
)
4278 module_exit(vmx_exit
)