2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id
[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
65 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
67 static bool __read_mostly enable_vpid
= 1;
68 module_param_named(vpid
, enable_vpid
, bool, 0444);
70 static bool __read_mostly flexpriority_enabled
= 1;
71 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
73 static bool __read_mostly enable_ept
= 1;
74 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
76 static bool __read_mostly enable_unrestricted_guest
= 1;
77 module_param_named(unrestricted_guest
,
78 enable_unrestricted_guest
, bool, S_IRUGO
);
80 static bool __read_mostly enable_ept_ad_bits
= 1;
81 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
83 static bool __read_mostly emulate_invalid_guest_state
= true;
84 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
86 static bool __read_mostly vmm_exclusive
= 1;
87 module_param(vmm_exclusive
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
111 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
112 #define KVM_VM_CR0_ALWAYS_ON \
113 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
114 #define KVM_CR4_GUEST_OWNED_BITS \
115 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
116 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
118 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
119 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
121 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
123 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
126 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
127 * ple_gap: upper bound on the amount of time between two successive
128 * executions of PAUSE in a loop. Also indicate if ple enabled.
129 * According to test, this time is usually smaller than 128 cycles.
130 * ple_window: upper bound on the amount of time a guest is allowed to execute
131 * in a PAUSE loop. Tests indicate that most spinlocks are held for
132 * less than 2^12 cycles
133 * Time is measured based on a counter that runs at the same rate as the TSC,
134 * refer SDM volume 3b section 21.6.13 & 22.1.3.
136 #define KVM_VMX_DEFAULT_PLE_GAP 128
137 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
139 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
141 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
143 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
144 module_param(ple_gap
, int, S_IRUGO
);
146 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
147 module_param(ple_window
, int, S_IRUGO
);
149 /* Default doubles per-vcpu window every exit. */
150 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
151 module_param(ple_window_grow
, int, S_IRUGO
);
153 /* Default resets per-vcpu window every exit to ple_window. */
154 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
155 module_param(ple_window_shrink
, int, S_IRUGO
);
157 /* Default is to compute the maximum so we can never overflow. */
158 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
159 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
160 module_param(ple_window_max
, int, S_IRUGO
);
162 extern const ulong vmx_return
;
164 #define NR_AUTOLOAD_MSRS 8
165 #define VMCS02_POOL_SIZE 1
174 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
175 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
176 * loaded on this CPU (so we can clear them if the CPU goes down).
182 struct list_head loaded_vmcss_on_cpu_link
;
185 struct shared_msr_entry
{
192 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
193 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
194 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
195 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
196 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
197 * More than one of these structures may exist, if L1 runs multiple L2 guests.
198 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
199 * underlying hardware which will be used to run L2.
200 * This structure is packed to ensure that its layout is identical across
201 * machines (necessary for live migration).
202 * If there are changes in this struct, VMCS12_REVISION must be changed.
204 typedef u64 natural_width
;
205 struct __packed vmcs12
{
206 /* According to the Intel spec, a VMCS region must start with the
207 * following two fields. Then follow implementation-specific data.
212 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
213 u32 padding
[7]; /* room for future expansion */
218 u64 vm_exit_msr_store_addr
;
219 u64 vm_exit_msr_load_addr
;
220 u64 vm_entry_msr_load_addr
;
222 u64 virtual_apic_page_addr
;
223 u64 apic_access_addr
;
224 u64 posted_intr_desc_addr
;
226 u64 eoi_exit_bitmap0
;
227 u64 eoi_exit_bitmap1
;
228 u64 eoi_exit_bitmap2
;
229 u64 eoi_exit_bitmap3
;
231 u64 guest_physical_address
;
232 u64 vmcs_link_pointer
;
233 u64 guest_ia32_debugctl
;
236 u64 guest_ia32_perf_global_ctrl
;
244 u64 host_ia32_perf_global_ctrl
;
245 u64 padding64
[8]; /* room for future expansion */
247 * To allow migration of L1 (complete with its L2 guests) between
248 * machines of different natural widths (32 or 64 bit), we cannot have
249 * unsigned long fields with no explict size. We use u64 (aliased
250 * natural_width) instead. Luckily, x86 is little-endian.
252 natural_width cr0_guest_host_mask
;
253 natural_width cr4_guest_host_mask
;
254 natural_width cr0_read_shadow
;
255 natural_width cr4_read_shadow
;
256 natural_width cr3_target_value0
;
257 natural_width cr3_target_value1
;
258 natural_width cr3_target_value2
;
259 natural_width cr3_target_value3
;
260 natural_width exit_qualification
;
261 natural_width guest_linear_address
;
262 natural_width guest_cr0
;
263 natural_width guest_cr3
;
264 natural_width guest_cr4
;
265 natural_width guest_es_base
;
266 natural_width guest_cs_base
;
267 natural_width guest_ss_base
;
268 natural_width guest_ds_base
;
269 natural_width guest_fs_base
;
270 natural_width guest_gs_base
;
271 natural_width guest_ldtr_base
;
272 natural_width guest_tr_base
;
273 natural_width guest_gdtr_base
;
274 natural_width guest_idtr_base
;
275 natural_width guest_dr7
;
276 natural_width guest_rsp
;
277 natural_width guest_rip
;
278 natural_width guest_rflags
;
279 natural_width guest_pending_dbg_exceptions
;
280 natural_width guest_sysenter_esp
;
281 natural_width guest_sysenter_eip
;
282 natural_width host_cr0
;
283 natural_width host_cr3
;
284 natural_width host_cr4
;
285 natural_width host_fs_base
;
286 natural_width host_gs_base
;
287 natural_width host_tr_base
;
288 natural_width host_gdtr_base
;
289 natural_width host_idtr_base
;
290 natural_width host_ia32_sysenter_esp
;
291 natural_width host_ia32_sysenter_eip
;
292 natural_width host_rsp
;
293 natural_width host_rip
;
294 natural_width paddingl
[8]; /* room for future expansion */
295 u32 pin_based_vm_exec_control
;
296 u32 cpu_based_vm_exec_control
;
297 u32 exception_bitmap
;
298 u32 page_fault_error_code_mask
;
299 u32 page_fault_error_code_match
;
300 u32 cr3_target_count
;
301 u32 vm_exit_controls
;
302 u32 vm_exit_msr_store_count
;
303 u32 vm_exit_msr_load_count
;
304 u32 vm_entry_controls
;
305 u32 vm_entry_msr_load_count
;
306 u32 vm_entry_intr_info_field
;
307 u32 vm_entry_exception_error_code
;
308 u32 vm_entry_instruction_len
;
310 u32 secondary_vm_exec_control
;
311 u32 vm_instruction_error
;
313 u32 vm_exit_intr_info
;
314 u32 vm_exit_intr_error_code
;
315 u32 idt_vectoring_info_field
;
316 u32 idt_vectoring_error_code
;
317 u32 vm_exit_instruction_len
;
318 u32 vmx_instruction_info
;
325 u32 guest_ldtr_limit
;
327 u32 guest_gdtr_limit
;
328 u32 guest_idtr_limit
;
329 u32 guest_es_ar_bytes
;
330 u32 guest_cs_ar_bytes
;
331 u32 guest_ss_ar_bytes
;
332 u32 guest_ds_ar_bytes
;
333 u32 guest_fs_ar_bytes
;
334 u32 guest_gs_ar_bytes
;
335 u32 guest_ldtr_ar_bytes
;
336 u32 guest_tr_ar_bytes
;
337 u32 guest_interruptibility_info
;
338 u32 guest_activity_state
;
339 u32 guest_sysenter_cs
;
340 u32 host_ia32_sysenter_cs
;
341 u32 vmx_preemption_timer_value
;
342 u32 padding32
[7]; /* room for future expansion */
343 u16 virtual_processor_id
;
345 u16 guest_es_selector
;
346 u16 guest_cs_selector
;
347 u16 guest_ss_selector
;
348 u16 guest_ds_selector
;
349 u16 guest_fs_selector
;
350 u16 guest_gs_selector
;
351 u16 guest_ldtr_selector
;
352 u16 guest_tr_selector
;
353 u16 guest_intr_status
;
354 u16 host_es_selector
;
355 u16 host_cs_selector
;
356 u16 host_ss_selector
;
357 u16 host_ds_selector
;
358 u16 host_fs_selector
;
359 u16 host_gs_selector
;
360 u16 host_tr_selector
;
364 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
365 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
366 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
368 #define VMCS12_REVISION 0x11e57ed0
371 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
372 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
373 * current implementation, 4K are reserved to avoid future complications.
375 #define VMCS12_SIZE 0x1000
377 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
379 struct list_head list
;
381 struct loaded_vmcs vmcs02
;
385 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
386 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
389 /* Has the level1 guest done vmxon? */
393 /* The guest-physical address of the current VMCS L1 keeps for L2 */
395 /* The host-usable pointer to the above */
396 struct page
*current_vmcs12_page
;
397 struct vmcs12
*current_vmcs12
;
398 struct vmcs
*current_shadow_vmcs
;
400 * Indicates if the shadow vmcs must be updated with the
401 * data hold by vmcs12
403 bool sync_shadow_vmcs
;
405 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
406 struct list_head vmcs02_pool
;
408 u64 vmcs01_tsc_offset
;
409 /* L2 must run next, and mustn't decide to exit to L1. */
410 bool nested_run_pending
;
412 * Guest pages referred to in vmcs02 with host-physical pointers, so
413 * we must keep them pinned while L2 runs.
415 struct page
*apic_access_page
;
416 struct page
*virtual_apic_page
;
417 struct page
*pi_desc_page
;
418 struct pi_desc
*pi_desc
;
421 u64 msr_ia32_feature_control
;
423 struct hrtimer preemption_timer
;
424 bool preemption_timer_expired
;
426 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
432 u32 nested_vmx_procbased_ctls_low
;
433 u32 nested_vmx_procbased_ctls_high
;
434 u32 nested_vmx_true_procbased_ctls_low
;
435 u32 nested_vmx_secondary_ctls_low
;
436 u32 nested_vmx_secondary_ctls_high
;
437 u32 nested_vmx_pinbased_ctls_low
;
438 u32 nested_vmx_pinbased_ctls_high
;
439 u32 nested_vmx_exit_ctls_low
;
440 u32 nested_vmx_exit_ctls_high
;
441 u32 nested_vmx_true_exit_ctls_low
;
442 u32 nested_vmx_entry_ctls_low
;
443 u32 nested_vmx_entry_ctls_high
;
444 u32 nested_vmx_true_entry_ctls_low
;
445 u32 nested_vmx_misc_low
;
446 u32 nested_vmx_misc_high
;
447 u32 nested_vmx_ept_caps
;
448 u32 nested_vmx_vpid_caps
;
451 #define POSTED_INTR_ON 0
452 #define POSTED_INTR_SN 1
454 /* Posted-Interrupt Descriptor */
456 u32 pir
[8]; /* Posted interrupt requested */
459 /* bit 256 - Outstanding Notification */
461 /* bit 257 - Suppress Notification */
463 /* bit 271:258 - Reserved */
465 /* bit 279:272 - Notification Vector */
467 /* bit 287:280 - Reserved */
469 /* bit 319:288 - Notification Destination */
477 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
479 return test_and_set_bit(POSTED_INTR_ON
,
480 (unsigned long *)&pi_desc
->control
);
483 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
485 return test_and_clear_bit(POSTED_INTR_ON
,
486 (unsigned long *)&pi_desc
->control
);
489 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
491 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
494 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
496 return clear_bit(POSTED_INTR_SN
,
497 (unsigned long *)&pi_desc
->control
);
500 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
502 return set_bit(POSTED_INTR_SN
,
503 (unsigned long *)&pi_desc
->control
);
506 static inline int pi_test_on(struct pi_desc
*pi_desc
)
508 return test_bit(POSTED_INTR_ON
,
509 (unsigned long *)&pi_desc
->control
);
512 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
514 return test_bit(POSTED_INTR_SN
,
515 (unsigned long *)&pi_desc
->control
);
519 struct kvm_vcpu vcpu
;
520 unsigned long host_rsp
;
522 bool nmi_known_unmasked
;
524 u32 idt_vectoring_info
;
526 struct shared_msr_entry
*guest_msrs
;
529 unsigned long host_idt_base
;
531 u64 msr_host_kernel_gs_base
;
532 u64 msr_guest_kernel_gs_base
;
534 u32 vm_entry_controls_shadow
;
535 u32 vm_exit_controls_shadow
;
537 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
538 * non-nested (L1) guest, it always points to vmcs01. For a nested
539 * guest (L2), it points to a different VMCS.
541 struct loaded_vmcs vmcs01
;
542 struct loaded_vmcs
*loaded_vmcs
;
543 bool __launched
; /* temporary, used in vmx_vcpu_run */
544 struct msr_autoload
{
546 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
547 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
551 u16 fs_sel
, gs_sel
, ldt_sel
;
555 int gs_ldt_reload_needed
;
556 int fs_reload_needed
;
557 u64 msr_host_bndcfgs
;
558 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
563 struct kvm_segment segs
[8];
566 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
567 struct kvm_save_segment
{
575 bool emulation_required
;
577 /* Support for vnmi-less CPUs */
578 int soft_vnmi_blocked
;
580 s64 vnmi_blocked_time
;
583 /* Posted interrupt descriptor */
584 struct pi_desc pi_desc
;
586 /* Support for a guest hypervisor (nested VMX) */
587 struct nested_vmx nested
;
589 /* Dynamic PLE window. */
591 bool ple_window_dirty
;
593 /* Support for PML */
594 #define PML_ENTITY_NUM 512
598 enum segment_cache_field
{
607 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
609 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
612 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
614 return &(to_vmx(vcpu
)->pi_desc
);
617 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
618 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
619 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
620 [number##_HIGH] = VMCS12_OFFSET(name)+4
623 static unsigned long shadow_read_only_fields
[] = {
625 * We do NOT shadow fields that are modified when L0
626 * traps and emulates any vmx instruction (e.g. VMPTRLD,
627 * VMXON...) executed by L1.
628 * For example, VM_INSTRUCTION_ERROR is read
629 * by L1 if a vmx instruction fails (part of the error path).
630 * Note the code assumes this logic. If for some reason
631 * we start shadowing these fields then we need to
632 * force a shadow sync when L0 emulates vmx instructions
633 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
634 * by nested_vmx_failValid)
638 VM_EXIT_INSTRUCTION_LEN
,
639 IDT_VECTORING_INFO_FIELD
,
640 IDT_VECTORING_ERROR_CODE
,
641 VM_EXIT_INTR_ERROR_CODE
,
643 GUEST_LINEAR_ADDRESS
,
644 GUEST_PHYSICAL_ADDRESS
646 static int max_shadow_read_only_fields
=
647 ARRAY_SIZE(shadow_read_only_fields
);
649 static unsigned long shadow_read_write_fields
[] = {
656 GUEST_INTERRUPTIBILITY_INFO
,
669 CPU_BASED_VM_EXEC_CONTROL
,
670 VM_ENTRY_EXCEPTION_ERROR_CODE
,
671 VM_ENTRY_INTR_INFO_FIELD
,
672 VM_ENTRY_INSTRUCTION_LEN
,
673 VM_ENTRY_EXCEPTION_ERROR_CODE
,
679 static int max_shadow_read_write_fields
=
680 ARRAY_SIZE(shadow_read_write_fields
);
682 static const unsigned short vmcs_field_to_offset_table
[] = {
683 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
684 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
685 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
686 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
687 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
688 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
689 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
690 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
691 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
692 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
693 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
694 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
695 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
696 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
697 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
698 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
699 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
700 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
701 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
702 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
703 FIELD64(MSR_BITMAP
, msr_bitmap
),
704 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
705 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
706 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
707 FIELD64(TSC_OFFSET
, tsc_offset
),
708 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
709 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
710 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
711 FIELD64(EPT_POINTER
, ept_pointer
),
712 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
713 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
714 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
715 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
716 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
717 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
718 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
719 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
720 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
721 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
722 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
723 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
724 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
725 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
726 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
727 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
728 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
729 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
730 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
731 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
732 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
733 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
734 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
735 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
736 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
737 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
738 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
739 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
740 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
741 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
742 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
743 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
744 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
745 FIELD(TPR_THRESHOLD
, tpr_threshold
),
746 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
747 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
748 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
749 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
750 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
751 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
752 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
753 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
754 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
755 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
756 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
757 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
758 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
759 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
760 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
761 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
762 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
763 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
764 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
765 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
766 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
767 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
768 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
769 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
770 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
771 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
772 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
773 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
774 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
775 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
776 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
777 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
778 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
779 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
780 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
781 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
782 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
783 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
784 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
785 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
786 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
787 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
788 FIELD(GUEST_CR0
, guest_cr0
),
789 FIELD(GUEST_CR3
, guest_cr3
),
790 FIELD(GUEST_CR4
, guest_cr4
),
791 FIELD(GUEST_ES_BASE
, guest_es_base
),
792 FIELD(GUEST_CS_BASE
, guest_cs_base
),
793 FIELD(GUEST_SS_BASE
, guest_ss_base
),
794 FIELD(GUEST_DS_BASE
, guest_ds_base
),
795 FIELD(GUEST_FS_BASE
, guest_fs_base
),
796 FIELD(GUEST_GS_BASE
, guest_gs_base
),
797 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
798 FIELD(GUEST_TR_BASE
, guest_tr_base
),
799 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
800 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
801 FIELD(GUEST_DR7
, guest_dr7
),
802 FIELD(GUEST_RSP
, guest_rsp
),
803 FIELD(GUEST_RIP
, guest_rip
),
804 FIELD(GUEST_RFLAGS
, guest_rflags
),
805 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
806 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
807 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
808 FIELD(HOST_CR0
, host_cr0
),
809 FIELD(HOST_CR3
, host_cr3
),
810 FIELD(HOST_CR4
, host_cr4
),
811 FIELD(HOST_FS_BASE
, host_fs_base
),
812 FIELD(HOST_GS_BASE
, host_gs_base
),
813 FIELD(HOST_TR_BASE
, host_tr_base
),
814 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
815 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
816 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
817 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
818 FIELD(HOST_RSP
, host_rsp
),
819 FIELD(HOST_RIP
, host_rip
),
822 static inline short vmcs_field_to_offset(unsigned long field
)
824 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
826 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
827 vmcs_field_to_offset_table
[field
] == 0)
830 return vmcs_field_to_offset_table
[field
];
833 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
835 return to_vmx(vcpu
)->nested
.current_vmcs12
;
838 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
840 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
841 if (is_error_page(page
))
847 static void nested_release_page(struct page
*page
)
849 kvm_release_page_dirty(page
);
852 static void nested_release_page_clean(struct page
*page
)
854 kvm_release_page_clean(page
);
857 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
858 static u64
construct_eptp(unsigned long root_hpa
);
859 static void kvm_cpu_vmxon(u64 addr
);
860 static void kvm_cpu_vmxoff(void);
861 static bool vmx_mpx_supported(void);
862 static bool vmx_xsaves_supported(void);
863 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
);
864 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
865 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
866 struct kvm_segment
*var
, int seg
);
867 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
868 struct kvm_segment
*var
, int seg
);
869 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
870 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
871 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
872 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
873 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
874 static int alloc_identity_pagetable(struct kvm
*kvm
);
876 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
877 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
879 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
880 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
882 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
883 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
886 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
887 * can find which vCPU should be waken up.
889 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
890 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
892 static unsigned long *vmx_io_bitmap_a
;
893 static unsigned long *vmx_io_bitmap_b
;
894 static unsigned long *vmx_msr_bitmap_legacy
;
895 static unsigned long *vmx_msr_bitmap_longmode
;
896 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
897 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
898 static unsigned long *vmx_msr_bitmap_nested
;
899 static unsigned long *vmx_vmread_bitmap
;
900 static unsigned long *vmx_vmwrite_bitmap
;
902 static bool cpu_has_load_ia32_efer
;
903 static bool cpu_has_load_perf_global_ctrl
;
905 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
906 static DEFINE_SPINLOCK(vmx_vpid_lock
);
908 static struct vmcs_config
{
912 u32 pin_based_exec_ctrl
;
913 u32 cpu_based_exec_ctrl
;
914 u32 cpu_based_2nd_exec_ctrl
;
919 static struct vmx_capability
{
924 #define VMX_SEGMENT_FIELD(seg) \
925 [VCPU_SREG_##seg] = { \
926 .selector = GUEST_##seg##_SELECTOR, \
927 .base = GUEST_##seg##_BASE, \
928 .limit = GUEST_##seg##_LIMIT, \
929 .ar_bytes = GUEST_##seg##_AR_BYTES, \
932 static const struct kvm_vmx_segment_field
{
937 } kvm_vmx_segment_fields
[] = {
938 VMX_SEGMENT_FIELD(CS
),
939 VMX_SEGMENT_FIELD(DS
),
940 VMX_SEGMENT_FIELD(ES
),
941 VMX_SEGMENT_FIELD(FS
),
942 VMX_SEGMENT_FIELD(GS
),
943 VMX_SEGMENT_FIELD(SS
),
944 VMX_SEGMENT_FIELD(TR
),
945 VMX_SEGMENT_FIELD(LDTR
),
948 static u64 host_efer
;
950 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
953 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
954 * away by decrementing the array size.
956 static const u32 vmx_msr_index
[] = {
958 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
960 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
963 static inline bool is_page_fault(u32 intr_info
)
965 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
966 INTR_INFO_VALID_MASK
)) ==
967 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
970 static inline bool is_no_device(u32 intr_info
)
972 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
973 INTR_INFO_VALID_MASK
)) ==
974 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
977 static inline bool is_invalid_opcode(u32 intr_info
)
979 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
980 INTR_INFO_VALID_MASK
)) ==
981 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
984 static inline bool is_external_interrupt(u32 intr_info
)
986 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
987 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
990 static inline bool is_machine_check(u32 intr_info
)
992 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
993 INTR_INFO_VALID_MASK
)) ==
994 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
997 static inline bool cpu_has_vmx_msr_bitmap(void)
999 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1002 static inline bool cpu_has_vmx_tpr_shadow(void)
1004 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1007 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1009 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1012 static inline bool cpu_has_secondary_exec_ctrls(void)
1014 return vmcs_config
.cpu_based_exec_ctrl
&
1015 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1018 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1020 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1021 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1024 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1026 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1027 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1030 static inline bool cpu_has_vmx_apic_register_virt(void)
1032 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1033 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1036 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1038 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1039 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1042 static inline bool cpu_has_vmx_posted_intr(void)
1044 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1045 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1048 static inline bool cpu_has_vmx_apicv(void)
1050 return cpu_has_vmx_apic_register_virt() &&
1051 cpu_has_vmx_virtual_intr_delivery() &&
1052 cpu_has_vmx_posted_intr();
1055 static inline bool cpu_has_vmx_flexpriority(void)
1057 return cpu_has_vmx_tpr_shadow() &&
1058 cpu_has_vmx_virtualize_apic_accesses();
1061 static inline bool cpu_has_vmx_ept_execute_only(void)
1063 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1066 static inline bool cpu_has_vmx_ept_2m_page(void)
1068 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1071 static inline bool cpu_has_vmx_ept_1g_page(void)
1073 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1076 static inline bool cpu_has_vmx_ept_4levels(void)
1078 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1081 static inline bool cpu_has_vmx_ept_ad_bits(void)
1083 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1086 static inline bool cpu_has_vmx_invept_context(void)
1088 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1091 static inline bool cpu_has_vmx_invept_global(void)
1093 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1096 static inline bool cpu_has_vmx_invvpid_single(void)
1098 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1101 static inline bool cpu_has_vmx_invvpid_global(void)
1103 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1106 static inline bool cpu_has_vmx_ept(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_ENABLE_EPT
;
1112 static inline bool cpu_has_vmx_unrestricted_guest(void)
1114 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1115 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1118 static inline bool cpu_has_vmx_ple(void)
1120 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1121 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1124 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1126 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1129 static inline bool cpu_has_vmx_vpid(void)
1131 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1132 SECONDARY_EXEC_ENABLE_VPID
;
1135 static inline bool cpu_has_vmx_rdtscp(void)
1137 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1138 SECONDARY_EXEC_RDTSCP
;
1141 static inline bool cpu_has_vmx_invpcid(void)
1143 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1144 SECONDARY_EXEC_ENABLE_INVPCID
;
1147 static inline bool cpu_has_virtual_nmis(void)
1149 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1152 static inline bool cpu_has_vmx_wbinvd_exit(void)
1154 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1155 SECONDARY_EXEC_WBINVD_EXITING
;
1158 static inline bool cpu_has_vmx_shadow_vmcs(void)
1161 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1162 /* check if the cpu supports writing r/o exit information fields */
1163 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1166 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1167 SECONDARY_EXEC_SHADOW_VMCS
;
1170 static inline bool cpu_has_vmx_pml(void)
1172 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1175 static inline bool report_flexpriority(void)
1177 return flexpriority_enabled
;
1180 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1182 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1185 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1187 return (vmcs12
->cpu_based_vm_exec_control
&
1188 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1189 (vmcs12
->secondary_vm_exec_control
& bit
);
1192 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1194 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1197 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1199 return vmcs12
->pin_based_vm_exec_control
&
1200 PIN_BASED_VMX_PREEMPTION_TIMER
;
1203 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1205 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1208 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1210 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1211 vmx_xsaves_supported();
1214 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1216 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1219 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1221 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1224 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1226 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1229 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1231 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1234 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1236 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1239 static inline bool is_exception(u32 intr_info
)
1241 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1242 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1245 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1247 unsigned long exit_qualification
);
1248 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1249 struct vmcs12
*vmcs12
,
1250 u32 reason
, unsigned long qualification
);
1252 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1256 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1257 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1262 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1268 } operand
= { vpid
, 0, gva
};
1270 asm volatile (__ex(ASM_VMX_INVVPID
)
1271 /* CF==1 or ZF==1 --> rc = -1 */
1272 "; ja 1f ; ud2 ; 1:"
1273 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1276 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1280 } operand
= {eptp
, gpa
};
1282 asm volatile (__ex(ASM_VMX_INVEPT
)
1283 /* CF==1 or ZF==1 --> rc = -1 */
1284 "; ja 1f ; ud2 ; 1:\n"
1285 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1288 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1292 i
= __find_msr_index(vmx
, msr
);
1294 return &vmx
->guest_msrs
[i
];
1298 static void vmcs_clear(struct vmcs
*vmcs
)
1300 u64 phys_addr
= __pa(vmcs
);
1303 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1304 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1307 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1311 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1313 vmcs_clear(loaded_vmcs
->vmcs
);
1314 loaded_vmcs
->cpu
= -1;
1315 loaded_vmcs
->launched
= 0;
1318 static void vmcs_load(struct vmcs
*vmcs
)
1320 u64 phys_addr
= __pa(vmcs
);
1323 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1324 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1327 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1331 #ifdef CONFIG_KEXEC_CORE
1333 * This bitmap is used to indicate whether the vmclear
1334 * operation is enabled on all cpus. All disabled by
1337 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1339 static inline void crash_enable_local_vmclear(int cpu
)
1341 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1344 static inline void crash_disable_local_vmclear(int cpu
)
1346 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1349 static inline int crash_local_vmclear_enabled(int cpu
)
1351 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1354 static void crash_vmclear_local_loaded_vmcss(void)
1356 int cpu
= raw_smp_processor_id();
1357 struct loaded_vmcs
*v
;
1359 if (!crash_local_vmclear_enabled(cpu
))
1362 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1363 loaded_vmcss_on_cpu_link
)
1364 vmcs_clear(v
->vmcs
);
1367 static inline void crash_enable_local_vmclear(int cpu
) { }
1368 static inline void crash_disable_local_vmclear(int cpu
) { }
1369 #endif /* CONFIG_KEXEC_CORE */
1371 static void __loaded_vmcs_clear(void *arg
)
1373 struct loaded_vmcs
*loaded_vmcs
= arg
;
1374 int cpu
= raw_smp_processor_id();
1376 if (loaded_vmcs
->cpu
!= cpu
)
1377 return; /* vcpu migration can race with cpu offline */
1378 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1379 per_cpu(current_vmcs
, cpu
) = NULL
;
1380 crash_disable_local_vmclear(cpu
);
1381 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1384 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1385 * is before setting loaded_vmcs->vcpu to -1 which is done in
1386 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1387 * then adds the vmcs into percpu list before it is deleted.
1391 loaded_vmcs_init(loaded_vmcs
);
1392 crash_enable_local_vmclear(cpu
);
1395 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1397 int cpu
= loaded_vmcs
->cpu
;
1400 smp_call_function_single(cpu
,
1401 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1404 static inline void vpid_sync_vcpu_single(int vpid
)
1409 if (cpu_has_vmx_invvpid_single())
1410 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1413 static inline void vpid_sync_vcpu_global(void)
1415 if (cpu_has_vmx_invvpid_global())
1416 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1419 static inline void vpid_sync_context(int vpid
)
1421 if (cpu_has_vmx_invvpid_single())
1422 vpid_sync_vcpu_single(vpid
);
1424 vpid_sync_vcpu_global();
1427 static inline void ept_sync_global(void)
1429 if (cpu_has_vmx_invept_global())
1430 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1433 static inline void ept_sync_context(u64 eptp
)
1436 if (cpu_has_vmx_invept_context())
1437 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1443 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1445 unsigned long value
;
1447 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1448 : "=a"(value
) : "d"(field
) : "cc");
1452 static __always_inline u16
vmcs_read16(unsigned long field
)
1454 return vmcs_readl(field
);
1457 static __always_inline u32
vmcs_read32(unsigned long field
)
1459 return vmcs_readl(field
);
1462 static __always_inline u64
vmcs_read64(unsigned long field
)
1464 #ifdef CONFIG_X86_64
1465 return vmcs_readl(field
);
1467 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1471 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1473 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1474 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1478 static void vmcs_writel(unsigned long field
, unsigned long value
)
1482 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1483 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1484 if (unlikely(error
))
1485 vmwrite_error(field
, value
);
1488 static void vmcs_write16(unsigned long field
, u16 value
)
1490 vmcs_writel(field
, value
);
1493 static void vmcs_write32(unsigned long field
, u32 value
)
1495 vmcs_writel(field
, value
);
1498 static void vmcs_write64(unsigned long field
, u64 value
)
1500 vmcs_writel(field
, value
);
1501 #ifndef CONFIG_X86_64
1503 vmcs_writel(field
+1, value
>> 32);
1507 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1509 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1512 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1514 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1517 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1519 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1520 vmx
->vm_entry_controls_shadow
= val
;
1523 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1525 if (vmx
->vm_entry_controls_shadow
!= val
)
1526 vm_entry_controls_init(vmx
, val
);
1529 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1531 return vmx
->vm_entry_controls_shadow
;
1535 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1537 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1540 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1542 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1545 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1547 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1548 vmx
->vm_exit_controls_shadow
= val
;
1551 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1553 if (vmx
->vm_exit_controls_shadow
!= val
)
1554 vm_exit_controls_init(vmx
, val
);
1557 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1559 return vmx
->vm_exit_controls_shadow
;
1563 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1565 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1568 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1570 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1573 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1575 vmx
->segment_cache
.bitmask
= 0;
1578 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1582 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1584 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1585 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1586 vmx
->segment_cache
.bitmask
= 0;
1588 ret
= vmx
->segment_cache
.bitmask
& mask
;
1589 vmx
->segment_cache
.bitmask
|= mask
;
1593 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1595 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1597 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1598 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1602 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1604 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1606 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1607 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1611 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1613 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1615 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1616 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1620 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1622 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1624 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1625 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1629 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1633 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1634 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1635 if ((vcpu
->guest_debug
&
1636 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1637 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1638 eb
|= 1u << BP_VECTOR
;
1639 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1642 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1643 if (vcpu
->fpu_active
)
1644 eb
&= ~(1u << NM_VECTOR
);
1646 /* When we are running a nested L2 guest and L1 specified for it a
1647 * certain exception bitmap, we must trap the same exceptions and pass
1648 * them to L1. When running L2, we will only handle the exceptions
1649 * specified above if L1 did not want them.
1651 if (is_guest_mode(vcpu
))
1652 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1654 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1657 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1658 unsigned long entry
, unsigned long exit
)
1660 vm_entry_controls_clearbit(vmx
, entry
);
1661 vm_exit_controls_clearbit(vmx
, exit
);
1664 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1667 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1671 if (cpu_has_load_ia32_efer
) {
1672 clear_atomic_switch_msr_special(vmx
,
1673 VM_ENTRY_LOAD_IA32_EFER
,
1674 VM_EXIT_LOAD_IA32_EFER
);
1678 case MSR_CORE_PERF_GLOBAL_CTRL
:
1679 if (cpu_has_load_perf_global_ctrl
) {
1680 clear_atomic_switch_msr_special(vmx
,
1681 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1682 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1688 for (i
= 0; i
< m
->nr
; ++i
)
1689 if (m
->guest
[i
].index
== msr
)
1695 m
->guest
[i
] = m
->guest
[m
->nr
];
1696 m
->host
[i
] = m
->host
[m
->nr
];
1697 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1698 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1701 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1702 unsigned long entry
, unsigned long exit
,
1703 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1704 u64 guest_val
, u64 host_val
)
1706 vmcs_write64(guest_val_vmcs
, guest_val
);
1707 vmcs_write64(host_val_vmcs
, host_val
);
1708 vm_entry_controls_setbit(vmx
, entry
);
1709 vm_exit_controls_setbit(vmx
, exit
);
1712 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1713 u64 guest_val
, u64 host_val
)
1716 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1720 if (cpu_has_load_ia32_efer
) {
1721 add_atomic_switch_msr_special(vmx
,
1722 VM_ENTRY_LOAD_IA32_EFER
,
1723 VM_EXIT_LOAD_IA32_EFER
,
1726 guest_val
, host_val
);
1730 case MSR_CORE_PERF_GLOBAL_CTRL
:
1731 if (cpu_has_load_perf_global_ctrl
) {
1732 add_atomic_switch_msr_special(vmx
,
1733 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1734 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1735 GUEST_IA32_PERF_GLOBAL_CTRL
,
1736 HOST_IA32_PERF_GLOBAL_CTRL
,
1737 guest_val
, host_val
);
1743 for (i
= 0; i
< m
->nr
; ++i
)
1744 if (m
->guest
[i
].index
== msr
)
1747 if (i
== NR_AUTOLOAD_MSRS
) {
1748 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1749 "Can't add msr %x\n", msr
);
1751 } else if (i
== m
->nr
) {
1753 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1754 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1757 m
->guest
[i
].index
= msr
;
1758 m
->guest
[i
].value
= guest_val
;
1759 m
->host
[i
].index
= msr
;
1760 m
->host
[i
].value
= host_val
;
1763 static void reload_tss(void)
1766 * VT restores TR but not its size. Useless.
1768 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1769 struct desc_struct
*descs
;
1771 descs
= (void *)gdt
->address
;
1772 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1776 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1781 guest_efer
= vmx
->vcpu
.arch
.efer
;
1784 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1787 ignore_bits
= EFER_NX
| EFER_SCE
;
1788 #ifdef CONFIG_X86_64
1789 ignore_bits
|= EFER_LMA
| EFER_LME
;
1790 /* SCE is meaningful only in long mode on Intel */
1791 if (guest_efer
& EFER_LMA
)
1792 ignore_bits
&= ~(u64
)EFER_SCE
;
1794 guest_efer
&= ~ignore_bits
;
1795 guest_efer
|= host_efer
& ignore_bits
;
1796 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1797 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1799 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1802 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1803 * On CPUs that support "load IA32_EFER", always switch EFER
1804 * atomically, since it's faster than switching it manually.
1806 if (cpu_has_load_ia32_efer
||
1807 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1808 guest_efer
= vmx
->vcpu
.arch
.efer
;
1809 if (!(guest_efer
& EFER_LMA
))
1810 guest_efer
&= ~EFER_LME
;
1811 if (guest_efer
!= host_efer
)
1812 add_atomic_switch_msr(vmx
, MSR_EFER
,
1813 guest_efer
, host_efer
);
1820 static unsigned long segment_base(u16 selector
)
1822 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1823 struct desc_struct
*d
;
1824 unsigned long table_base
;
1827 if (!(selector
& ~3))
1830 table_base
= gdt
->address
;
1832 if (selector
& 4) { /* from ldt */
1833 u16 ldt_selector
= kvm_read_ldt();
1835 if (!(ldt_selector
& ~3))
1838 table_base
= segment_base(ldt_selector
);
1840 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1841 v
= get_desc_base(d
);
1842 #ifdef CONFIG_X86_64
1843 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1844 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1849 static inline unsigned long kvm_read_tr_base(void)
1852 asm("str %0" : "=g"(tr
));
1853 return segment_base(tr
);
1856 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1858 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1861 if (vmx
->host_state
.loaded
)
1864 vmx
->host_state
.loaded
= 1;
1866 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1867 * allow segment selectors with cpl > 0 or ti == 1.
1869 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1870 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1871 savesegment(fs
, vmx
->host_state
.fs_sel
);
1872 if (!(vmx
->host_state
.fs_sel
& 7)) {
1873 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1874 vmx
->host_state
.fs_reload_needed
= 0;
1876 vmcs_write16(HOST_FS_SELECTOR
, 0);
1877 vmx
->host_state
.fs_reload_needed
= 1;
1879 savesegment(gs
, vmx
->host_state
.gs_sel
);
1880 if (!(vmx
->host_state
.gs_sel
& 7))
1881 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1883 vmcs_write16(HOST_GS_SELECTOR
, 0);
1884 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1887 #ifdef CONFIG_X86_64
1888 savesegment(ds
, vmx
->host_state
.ds_sel
);
1889 savesegment(es
, vmx
->host_state
.es_sel
);
1892 #ifdef CONFIG_X86_64
1893 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1894 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1896 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1897 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1900 #ifdef CONFIG_X86_64
1901 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1902 if (is_long_mode(&vmx
->vcpu
))
1903 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1905 if (boot_cpu_has(X86_FEATURE_MPX
))
1906 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1907 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1908 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1909 vmx
->guest_msrs
[i
].data
,
1910 vmx
->guest_msrs
[i
].mask
);
1913 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1915 if (!vmx
->host_state
.loaded
)
1918 ++vmx
->vcpu
.stat
.host_state_reload
;
1919 vmx
->host_state
.loaded
= 0;
1920 #ifdef CONFIG_X86_64
1921 if (is_long_mode(&vmx
->vcpu
))
1922 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1924 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1925 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1926 #ifdef CONFIG_X86_64
1927 load_gs_index(vmx
->host_state
.gs_sel
);
1929 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1932 if (vmx
->host_state
.fs_reload_needed
)
1933 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1934 #ifdef CONFIG_X86_64
1935 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1936 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1937 loadsegment(es
, vmx
->host_state
.es_sel
);
1941 #ifdef CONFIG_X86_64
1942 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1944 if (vmx
->host_state
.msr_host_bndcfgs
)
1945 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1947 * If the FPU is not active (through the host task or
1948 * the guest vcpu), then restore the cr0.TS bit.
1950 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
1952 load_gdt(this_cpu_ptr(&host_gdt
));
1955 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1958 __vmx_load_host_state(vmx
);
1962 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
1964 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
1965 struct pi_desc old
, new;
1968 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
1969 !irq_remapping_cap(IRQ_POSTING_CAP
))
1973 old
.control
= new.control
= pi_desc
->control
;
1976 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
1977 * are two possible cases:
1978 * 1. After running 'pre_block', context switch
1979 * happened. For this case, 'sn' was set in
1980 * vmx_vcpu_put(), so we need to clear it here.
1981 * 2. After running 'pre_block', we were blocked,
1982 * and woken up by some other guy. For this case,
1983 * we don't need to do anything, 'pi_post_block'
1984 * will do everything for us. However, we cannot
1985 * check whether it is case #1 or case #2 here
1986 * (maybe, not needed), so we also clear sn here,
1987 * I think it is not a big deal.
1989 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
1990 if (vcpu
->cpu
!= cpu
) {
1991 dest
= cpu_physical_id(cpu
);
1993 if (x2apic_enabled())
1996 new.ndst
= (dest
<< 8) & 0xFF00;
1999 /* set 'NV' to 'notification vector' */
2000 new.nv
= POSTED_INTR_VECTOR
;
2003 /* Allow posting non-urgent interrupts */
2005 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2006 new.control
) != old
.control
);
2009 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2010 * vcpu mutex is already taken.
2012 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2014 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2015 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2018 kvm_cpu_vmxon(phys_addr
);
2019 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2020 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2022 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2023 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2024 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2027 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2028 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2029 unsigned long sysenter_esp
;
2031 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2032 local_irq_disable();
2033 crash_disable_local_vmclear(cpu
);
2036 * Read loaded_vmcs->cpu should be before fetching
2037 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2038 * See the comments in __loaded_vmcs_clear().
2042 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2043 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2044 crash_enable_local_vmclear(cpu
);
2048 * Linux uses per-cpu TSS and GDT, so set these when switching
2051 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2052 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2054 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2055 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2056 vmx
->loaded_vmcs
->cpu
= cpu
;
2059 vmx_vcpu_pi_load(vcpu
, cpu
);
2062 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2064 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2066 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2067 !irq_remapping_cap(IRQ_POSTING_CAP
))
2070 /* Set SN when the vCPU is preempted */
2071 if (vcpu
->preempted
)
2075 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2077 vmx_vcpu_pi_put(vcpu
);
2079 __vmx_load_host_state(to_vmx(vcpu
));
2080 if (!vmm_exclusive
) {
2081 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2087 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2091 if (vcpu
->fpu_active
)
2093 vcpu
->fpu_active
= 1;
2094 cr0
= vmcs_readl(GUEST_CR0
);
2095 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2096 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2097 vmcs_writel(GUEST_CR0
, cr0
);
2098 update_exception_bitmap(vcpu
);
2099 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2100 if (is_guest_mode(vcpu
))
2101 vcpu
->arch
.cr0_guest_owned_bits
&=
2102 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2103 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2106 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2109 * Return the cr0 value that a nested guest would read. This is a combination
2110 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2111 * its hypervisor (cr0_read_shadow).
2113 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2115 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2116 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2118 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2120 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2121 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2124 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2126 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2127 * set this *before* calling this function.
2129 vmx_decache_cr0_guest_bits(vcpu
);
2130 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2131 update_exception_bitmap(vcpu
);
2132 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2133 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2134 if (is_guest_mode(vcpu
)) {
2136 * L1's specified read shadow might not contain the TS bit,
2137 * so now that we turned on shadowing of this bit, we need to
2138 * set this bit of the shadow. Like in nested_vmx_run we need
2139 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2140 * up-to-date here because we just decached cr0.TS (and we'll
2141 * only update vmcs12->guest_cr0 on nested exit).
2143 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2144 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2145 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2146 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2148 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2151 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2153 unsigned long rflags
, save_rflags
;
2155 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2156 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2157 rflags
= vmcs_readl(GUEST_RFLAGS
);
2158 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2159 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2160 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2161 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2163 to_vmx(vcpu
)->rflags
= rflags
;
2165 return to_vmx(vcpu
)->rflags
;
2168 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2170 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2171 to_vmx(vcpu
)->rflags
= rflags
;
2172 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2173 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2174 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2176 vmcs_writel(GUEST_RFLAGS
, rflags
);
2179 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2181 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2184 if (interruptibility
& GUEST_INTR_STATE_STI
)
2185 ret
|= KVM_X86_SHADOW_INT_STI
;
2186 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2187 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2192 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2194 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2195 u32 interruptibility
= interruptibility_old
;
2197 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2199 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2200 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2201 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2202 interruptibility
|= GUEST_INTR_STATE_STI
;
2204 if ((interruptibility
!= interruptibility_old
))
2205 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2208 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2212 rip
= kvm_rip_read(vcpu
);
2213 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2214 kvm_rip_write(vcpu
, rip
);
2216 /* skipping an emulated instruction also counts */
2217 vmx_set_interrupt_shadow(vcpu
, 0);
2221 * KVM wants to inject page-faults which it got to the guest. This function
2222 * checks whether in a nested guest, we need to inject them to L1 or L2.
2224 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2226 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2228 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2231 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2232 vmcs_read32(VM_EXIT_INTR_INFO
),
2233 vmcs_readl(EXIT_QUALIFICATION
));
2237 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2238 bool has_error_code
, u32 error_code
,
2241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2242 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2244 if (!reinject
&& is_guest_mode(vcpu
) &&
2245 nested_vmx_check_exception(vcpu
, nr
))
2248 if (has_error_code
) {
2249 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2250 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2253 if (vmx
->rmode
.vm86_active
) {
2255 if (kvm_exception_is_soft(nr
))
2256 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2257 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2258 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2262 if (kvm_exception_is_soft(nr
)) {
2263 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2264 vmx
->vcpu
.arch
.event_exit_inst_len
);
2265 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2267 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2269 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2272 static bool vmx_rdtscp_supported(void)
2274 return cpu_has_vmx_rdtscp();
2277 static bool vmx_invpcid_supported(void)
2279 return cpu_has_vmx_invpcid() && enable_ept
;
2283 * Swap MSR entry in host/guest MSR entry array.
2285 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2287 struct shared_msr_entry tmp
;
2289 tmp
= vmx
->guest_msrs
[to
];
2290 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2291 vmx
->guest_msrs
[from
] = tmp
;
2294 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2296 unsigned long *msr_bitmap
;
2298 if (is_guest_mode(vcpu
))
2299 msr_bitmap
= vmx_msr_bitmap_nested
;
2300 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2301 if (is_long_mode(vcpu
))
2302 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2304 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2306 if (is_long_mode(vcpu
))
2307 msr_bitmap
= vmx_msr_bitmap_longmode
;
2309 msr_bitmap
= vmx_msr_bitmap_legacy
;
2312 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2316 * Set up the vmcs to automatically save and restore system
2317 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2318 * mode, as fiddling with msrs is very expensive.
2320 static void setup_msrs(struct vcpu_vmx
*vmx
)
2322 int save_nmsrs
, index
;
2325 #ifdef CONFIG_X86_64
2326 if (is_long_mode(&vmx
->vcpu
)) {
2327 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2329 move_msr_up(vmx
, index
, save_nmsrs
++);
2330 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2332 move_msr_up(vmx
, index
, save_nmsrs
++);
2333 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2335 move_msr_up(vmx
, index
, save_nmsrs
++);
2336 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2337 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2338 move_msr_up(vmx
, index
, save_nmsrs
++);
2340 * MSR_STAR is only needed on long mode guests, and only
2341 * if efer.sce is enabled.
2343 index
= __find_msr_index(vmx
, MSR_STAR
);
2344 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2345 move_msr_up(vmx
, index
, save_nmsrs
++);
2348 index
= __find_msr_index(vmx
, MSR_EFER
);
2349 if (index
>= 0 && update_transition_efer(vmx
, index
))
2350 move_msr_up(vmx
, index
, save_nmsrs
++);
2352 vmx
->save_nmsrs
= save_nmsrs
;
2354 if (cpu_has_vmx_msr_bitmap())
2355 vmx_set_msr_bitmap(&vmx
->vcpu
);
2359 * reads and returns guest's timestamp counter "register"
2360 * guest_tsc = host_tsc + tsc_offset -- 21.3
2362 static u64
guest_read_tsc(void)
2364 u64 host_tsc
, tsc_offset
;
2367 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2368 return host_tsc
+ tsc_offset
;
2372 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2373 * counter, even if a nested guest (L2) is currently running.
2375 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2379 tsc_offset
= is_guest_mode(vcpu
) ?
2380 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2381 vmcs_read64(TSC_OFFSET
);
2382 return host_tsc
+ tsc_offset
;
2386 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2387 * software catchup for faster rates on slower CPUs.
2389 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2394 if (user_tsc_khz
> tsc_khz
) {
2395 vcpu
->arch
.tsc_catchup
= 1;
2396 vcpu
->arch
.tsc_always_catchup
= 1;
2398 WARN(1, "user requested TSC rate below hardware speed\n");
2401 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2403 return vmcs_read64(TSC_OFFSET
);
2407 * writes 'offset' into guest's timestamp counter offset register
2409 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2411 if (is_guest_mode(vcpu
)) {
2413 * We're here if L1 chose not to trap WRMSR to TSC. According
2414 * to the spec, this should set L1's TSC; The offset that L1
2415 * set for L2 remains unchanged, and still needs to be added
2416 * to the newly set TSC to get L2's TSC.
2418 struct vmcs12
*vmcs12
;
2419 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2420 /* recalculate vmcs02.TSC_OFFSET: */
2421 vmcs12
= get_vmcs12(vcpu
);
2422 vmcs_write64(TSC_OFFSET
, offset
+
2423 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2424 vmcs12
->tsc_offset
: 0));
2426 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2427 vmcs_read64(TSC_OFFSET
), offset
);
2428 vmcs_write64(TSC_OFFSET
, offset
);
2432 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2434 u64 offset
= vmcs_read64(TSC_OFFSET
);
2436 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2437 if (is_guest_mode(vcpu
)) {
2438 /* Even when running L2, the adjustment needs to apply to L1 */
2439 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2441 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2442 offset
+ adjustment
);
2445 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2447 return target_tsc
- rdtsc();
2450 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2452 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2453 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2457 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2458 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2459 * all guests if the "nested" module option is off, and can also be disabled
2460 * for a single guest by disabling its VMX cpuid bit.
2462 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2464 return nested
&& guest_cpuid_has_vmx(vcpu
);
2468 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2469 * returned for the various VMX controls MSRs when nested VMX is enabled.
2470 * The same values should also be used to verify that vmcs12 control fields are
2471 * valid during nested entry from L1 to L2.
2472 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2473 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2474 * bit in the high half is on if the corresponding bit in the control field
2475 * may be on. See also vmx_control_verify().
2477 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2480 * Note that as a general rule, the high half of the MSRs (bits in
2481 * the control fields which may be 1) should be initialized by the
2482 * intersection of the underlying hardware's MSR (i.e., features which
2483 * can be supported) and the list of features we want to expose -
2484 * because they are known to be properly supported in our code.
2485 * Also, usually, the low half of the MSRs (bits which must be 1) can
2486 * be set to 0, meaning that L1 may turn off any of these bits. The
2487 * reason is that if one of these bits is necessary, it will appear
2488 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2489 * fields of vmcs01 and vmcs02, will turn these bits off - and
2490 * nested_vmx_exit_handled() will not pass related exits to L1.
2491 * These rules have exceptions below.
2494 /* pin-based controls */
2495 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2496 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2497 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2498 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2499 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2500 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2501 PIN_BASED_EXT_INTR_MASK
|
2502 PIN_BASED_NMI_EXITING
|
2503 PIN_BASED_VIRTUAL_NMIS
;
2504 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2505 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2506 PIN_BASED_VMX_PREEMPTION_TIMER
;
2507 if (vmx_cpu_uses_apicv(&vmx
->vcpu
))
2508 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2509 PIN_BASED_POSTED_INTR
;
2512 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2513 vmx
->nested
.nested_vmx_exit_ctls_low
,
2514 vmx
->nested
.nested_vmx_exit_ctls_high
);
2515 vmx
->nested
.nested_vmx_exit_ctls_low
=
2516 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2518 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2519 #ifdef CONFIG_X86_64
2520 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2522 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2523 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2524 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2525 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2526 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2528 if (vmx_mpx_supported())
2529 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2531 /* We support free control of debug control saving. */
2532 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2533 vmx
->nested
.nested_vmx_exit_ctls_low
&
2534 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2536 /* entry controls */
2537 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2538 vmx
->nested
.nested_vmx_entry_ctls_low
,
2539 vmx
->nested
.nested_vmx_entry_ctls_high
);
2540 vmx
->nested
.nested_vmx_entry_ctls_low
=
2541 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2542 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2543 #ifdef CONFIG_X86_64
2544 VM_ENTRY_IA32E_MODE
|
2546 VM_ENTRY_LOAD_IA32_PAT
;
2547 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2548 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2549 if (vmx_mpx_supported())
2550 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2552 /* We support free control of debug control loading. */
2553 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2554 vmx
->nested
.nested_vmx_entry_ctls_low
&
2555 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2557 /* cpu-based controls */
2558 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2559 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2560 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2561 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2562 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2563 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2564 CPU_BASED_VIRTUAL_INTR_PENDING
|
2565 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2566 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2567 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2568 CPU_BASED_CR3_STORE_EXITING
|
2569 #ifdef CONFIG_X86_64
2570 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2572 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2573 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2574 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2575 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2576 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2578 * We can allow some features even when not supported by the
2579 * hardware. For example, L1 can specify an MSR bitmap - and we
2580 * can use it to avoid exits to L1 - even when L0 runs L2
2581 * without MSR bitmaps.
2583 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2584 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2585 CPU_BASED_USE_MSR_BITMAPS
;
2587 /* We support free control of CR3 access interception. */
2588 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2589 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2590 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2592 /* secondary cpu-based controls */
2593 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2594 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2595 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2596 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2597 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2598 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2599 SECONDARY_EXEC_RDTSCP
|
2600 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2601 SECONDARY_EXEC_ENABLE_VPID
|
2602 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2603 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2604 SECONDARY_EXEC_WBINVD_EXITING
|
2605 SECONDARY_EXEC_XSAVES
|
2606 SECONDARY_EXEC_PCOMMIT
;
2609 /* nested EPT: emulate EPT also to L1 */
2610 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2611 SECONDARY_EXEC_ENABLE_EPT
;
2612 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2613 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2615 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2617 * For nested guests, we don't do anything specific
2618 * for single context invalidation. Hence, only advertise
2619 * support for global context invalidation.
2621 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2623 vmx
->nested
.nested_vmx_ept_caps
= 0;
2626 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2627 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2629 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2631 if (enable_unrestricted_guest
)
2632 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2633 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2635 /* miscellaneous data */
2636 rdmsr(MSR_IA32_VMX_MISC
,
2637 vmx
->nested
.nested_vmx_misc_low
,
2638 vmx
->nested
.nested_vmx_misc_high
);
2639 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2640 vmx
->nested
.nested_vmx_misc_low
|=
2641 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2642 VMX_MISC_ACTIVITY_HLT
;
2643 vmx
->nested
.nested_vmx_misc_high
= 0;
2646 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2649 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2651 return ((control
& high
) | low
) == control
;
2654 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2656 return low
| ((u64
)high
<< 32);
2659 /* Returns 0 on success, non-0 otherwise. */
2660 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2664 switch (msr_index
) {
2665 case MSR_IA32_VMX_BASIC
:
2667 * This MSR reports some information about VMX support. We
2668 * should return information about the VMX we emulate for the
2669 * guest, and the VMCS structure we give it - not about the
2670 * VMX support of the underlying hardware.
2672 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2673 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2674 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2676 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2677 case MSR_IA32_VMX_PINBASED_CTLS
:
2678 *pdata
= vmx_control_msr(
2679 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2680 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2682 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2683 *pdata
= vmx_control_msr(
2684 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2685 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2687 case MSR_IA32_VMX_PROCBASED_CTLS
:
2688 *pdata
= vmx_control_msr(
2689 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2690 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2692 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2693 *pdata
= vmx_control_msr(
2694 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2695 vmx
->nested
.nested_vmx_exit_ctls_high
);
2697 case MSR_IA32_VMX_EXIT_CTLS
:
2698 *pdata
= vmx_control_msr(
2699 vmx
->nested
.nested_vmx_exit_ctls_low
,
2700 vmx
->nested
.nested_vmx_exit_ctls_high
);
2702 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2703 *pdata
= vmx_control_msr(
2704 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2705 vmx
->nested
.nested_vmx_entry_ctls_high
);
2707 case MSR_IA32_VMX_ENTRY_CTLS
:
2708 *pdata
= vmx_control_msr(
2709 vmx
->nested
.nested_vmx_entry_ctls_low
,
2710 vmx
->nested
.nested_vmx_entry_ctls_high
);
2712 case MSR_IA32_VMX_MISC
:
2713 *pdata
= vmx_control_msr(
2714 vmx
->nested
.nested_vmx_misc_low
,
2715 vmx
->nested
.nested_vmx_misc_high
);
2718 * These MSRs specify bits which the guest must keep fixed (on or off)
2719 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2720 * We picked the standard core2 setting.
2722 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2723 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2724 case MSR_IA32_VMX_CR0_FIXED0
:
2725 *pdata
= VMXON_CR0_ALWAYSON
;
2727 case MSR_IA32_VMX_CR0_FIXED1
:
2730 case MSR_IA32_VMX_CR4_FIXED0
:
2731 *pdata
= VMXON_CR4_ALWAYSON
;
2733 case MSR_IA32_VMX_CR4_FIXED1
:
2736 case MSR_IA32_VMX_VMCS_ENUM
:
2737 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2739 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2740 *pdata
= vmx_control_msr(
2741 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2742 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2744 case MSR_IA32_VMX_EPT_VPID_CAP
:
2745 /* Currently, no nested vpid support */
2746 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2747 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2757 * Reads an msr value (of 'msr_index') into 'pdata'.
2758 * Returns 0 on success, non-0 otherwise.
2759 * Assumes vcpu_load() was already called.
2761 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2763 struct shared_msr_entry
*msr
;
2765 switch (msr_info
->index
) {
2766 #ifdef CONFIG_X86_64
2768 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2771 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2773 case MSR_KERNEL_GS_BASE
:
2774 vmx_load_host_state(to_vmx(vcpu
));
2775 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2779 return kvm_get_msr_common(vcpu
, msr_info
);
2781 msr_info
->data
= guest_read_tsc();
2783 case MSR_IA32_SYSENTER_CS
:
2784 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2786 case MSR_IA32_SYSENTER_EIP
:
2787 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2789 case MSR_IA32_SYSENTER_ESP
:
2790 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2792 case MSR_IA32_BNDCFGS
:
2793 if (!vmx_mpx_supported())
2795 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2797 case MSR_IA32_FEATURE_CONTROL
:
2798 if (!nested_vmx_allowed(vcpu
))
2800 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2802 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2803 if (!nested_vmx_allowed(vcpu
))
2805 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2807 if (!vmx_xsaves_supported())
2809 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2812 if (!guest_cpuid_has_rdtscp(vcpu
))
2814 /* Otherwise falls through */
2816 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2818 msr_info
->data
= msr
->data
;
2821 return kvm_get_msr_common(vcpu
, msr_info
);
2827 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2830 * Writes msr value into into the appropriate "register".
2831 * Returns 0 on success, non-0 otherwise.
2832 * Assumes vcpu_load() was already called.
2834 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2836 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2837 struct shared_msr_entry
*msr
;
2839 u32 msr_index
= msr_info
->index
;
2840 u64 data
= msr_info
->data
;
2842 switch (msr_index
) {
2844 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2846 #ifdef CONFIG_X86_64
2848 vmx_segment_cache_clear(vmx
);
2849 vmcs_writel(GUEST_FS_BASE
, data
);
2852 vmx_segment_cache_clear(vmx
);
2853 vmcs_writel(GUEST_GS_BASE
, data
);
2855 case MSR_KERNEL_GS_BASE
:
2856 vmx_load_host_state(vmx
);
2857 vmx
->msr_guest_kernel_gs_base
= data
;
2860 case MSR_IA32_SYSENTER_CS
:
2861 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2863 case MSR_IA32_SYSENTER_EIP
:
2864 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2866 case MSR_IA32_SYSENTER_ESP
:
2867 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2869 case MSR_IA32_BNDCFGS
:
2870 if (!vmx_mpx_supported())
2872 vmcs_write64(GUEST_BNDCFGS
, data
);
2875 kvm_write_tsc(vcpu
, msr_info
);
2877 case MSR_IA32_CR_PAT
:
2878 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2879 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2881 vmcs_write64(GUEST_IA32_PAT
, data
);
2882 vcpu
->arch
.pat
= data
;
2885 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2887 case MSR_IA32_TSC_ADJUST
:
2888 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2890 case MSR_IA32_FEATURE_CONTROL
:
2891 if (!nested_vmx_allowed(vcpu
) ||
2892 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2893 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2895 vmx
->nested
.msr_ia32_feature_control
= data
;
2896 if (msr_info
->host_initiated
&& data
== 0)
2897 vmx_leave_nested(vcpu
);
2899 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2900 return 1; /* they are read-only */
2902 if (!vmx_xsaves_supported())
2905 * The only supported bit as of Skylake is bit 8, but
2906 * it is not supported on KVM.
2910 vcpu
->arch
.ia32_xss
= data
;
2911 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2912 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2913 vcpu
->arch
.ia32_xss
, host_xss
);
2915 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2918 if (!guest_cpuid_has_rdtscp(vcpu
))
2920 /* Check reserved bit, higher 32 bits should be zero */
2921 if ((data
>> 32) != 0)
2923 /* Otherwise falls through */
2925 msr
= find_msr_entry(vmx
, msr_index
);
2927 u64 old_msr_data
= msr
->data
;
2929 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2931 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2935 msr
->data
= old_msr_data
;
2939 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2945 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2947 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2950 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2953 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2955 case VCPU_EXREG_PDPTR
:
2957 ept_save_pdptrs(vcpu
);
2964 static __init
int cpu_has_kvm_support(void)
2966 return cpu_has_vmx();
2969 static __init
int vmx_disabled_by_bios(void)
2973 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2974 if (msr
& FEATURE_CONTROL_LOCKED
) {
2975 /* launched w/ TXT and VMX disabled */
2976 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2979 /* launched w/o TXT and VMX only enabled w/ TXT */
2980 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2981 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2982 && !tboot_enabled()) {
2983 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2984 "activate TXT before enabling KVM\n");
2987 /* launched w/o TXT and VMX disabled */
2988 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2989 && !tboot_enabled())
2996 static void kvm_cpu_vmxon(u64 addr
)
2998 asm volatile (ASM_VMX_VMXON_RAX
2999 : : "a"(&addr
), "m"(addr
)
3003 static int hardware_enable(void)
3005 int cpu
= raw_smp_processor_id();
3006 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3009 if (cr4_read_shadow() & X86_CR4_VMXE
)
3012 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3013 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3014 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3017 * Now we can enable the vmclear operation in kdump
3018 * since the loaded_vmcss_on_cpu list on this cpu
3019 * has been initialized.
3021 * Though the cpu is not in VMX operation now, there
3022 * is no problem to enable the vmclear operation
3023 * for the loaded_vmcss_on_cpu list is empty!
3025 crash_enable_local_vmclear(cpu
);
3027 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3029 test_bits
= FEATURE_CONTROL_LOCKED
;
3030 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3031 if (tboot_enabled())
3032 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3034 if ((old
& test_bits
) != test_bits
) {
3035 /* enable and lock */
3036 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3038 cr4_set_bits(X86_CR4_VMXE
);
3040 if (vmm_exclusive
) {
3041 kvm_cpu_vmxon(phys_addr
);
3045 native_store_gdt(this_cpu_ptr(&host_gdt
));
3050 static void vmclear_local_loaded_vmcss(void)
3052 int cpu
= raw_smp_processor_id();
3053 struct loaded_vmcs
*v
, *n
;
3055 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3056 loaded_vmcss_on_cpu_link
)
3057 __loaded_vmcs_clear(v
);
3061 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3064 static void kvm_cpu_vmxoff(void)
3066 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3069 static void hardware_disable(void)
3071 if (vmm_exclusive
) {
3072 vmclear_local_loaded_vmcss();
3075 cr4_clear_bits(X86_CR4_VMXE
);
3078 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3079 u32 msr
, u32
*result
)
3081 u32 vmx_msr_low
, vmx_msr_high
;
3082 u32 ctl
= ctl_min
| ctl_opt
;
3084 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3086 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3087 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3089 /* Ensure minimum (required) set of control bits are supported. */
3097 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3099 u32 vmx_msr_low
, vmx_msr_high
;
3101 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3102 return vmx_msr_high
& ctl
;
3105 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3107 u32 vmx_msr_low
, vmx_msr_high
;
3108 u32 min
, opt
, min2
, opt2
;
3109 u32 _pin_based_exec_control
= 0;
3110 u32 _cpu_based_exec_control
= 0;
3111 u32 _cpu_based_2nd_exec_control
= 0;
3112 u32 _vmexit_control
= 0;
3113 u32 _vmentry_control
= 0;
3115 min
= CPU_BASED_HLT_EXITING
|
3116 #ifdef CONFIG_X86_64
3117 CPU_BASED_CR8_LOAD_EXITING
|
3118 CPU_BASED_CR8_STORE_EXITING
|
3120 CPU_BASED_CR3_LOAD_EXITING
|
3121 CPU_BASED_CR3_STORE_EXITING
|
3122 CPU_BASED_USE_IO_BITMAPS
|
3123 CPU_BASED_MOV_DR_EXITING
|
3124 CPU_BASED_USE_TSC_OFFSETING
|
3125 CPU_BASED_MWAIT_EXITING
|
3126 CPU_BASED_MONITOR_EXITING
|
3127 CPU_BASED_INVLPG_EXITING
|
3128 CPU_BASED_RDPMC_EXITING
;
3130 opt
= CPU_BASED_TPR_SHADOW
|
3131 CPU_BASED_USE_MSR_BITMAPS
|
3132 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3133 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3134 &_cpu_based_exec_control
) < 0)
3136 #ifdef CONFIG_X86_64
3137 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3138 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3139 ~CPU_BASED_CR8_STORE_EXITING
;
3141 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3143 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3144 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3145 SECONDARY_EXEC_WBINVD_EXITING
|
3146 SECONDARY_EXEC_ENABLE_VPID
|
3147 SECONDARY_EXEC_ENABLE_EPT
|
3148 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3149 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3150 SECONDARY_EXEC_RDTSCP
|
3151 SECONDARY_EXEC_ENABLE_INVPCID
|
3152 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3153 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3154 SECONDARY_EXEC_SHADOW_VMCS
|
3155 SECONDARY_EXEC_XSAVES
|
3156 SECONDARY_EXEC_ENABLE_PML
|
3157 SECONDARY_EXEC_PCOMMIT
;
3158 if (adjust_vmx_controls(min2
, opt2
,
3159 MSR_IA32_VMX_PROCBASED_CTLS2
,
3160 &_cpu_based_2nd_exec_control
) < 0)
3163 #ifndef CONFIG_X86_64
3164 if (!(_cpu_based_2nd_exec_control
&
3165 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3166 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3169 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3170 _cpu_based_2nd_exec_control
&= ~(
3171 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3172 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3173 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3175 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3176 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3178 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3179 CPU_BASED_CR3_STORE_EXITING
|
3180 CPU_BASED_INVLPG_EXITING
);
3181 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3182 vmx_capability
.ept
, vmx_capability
.vpid
);
3185 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3186 #ifdef CONFIG_X86_64
3187 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3189 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3190 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3191 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3192 &_vmexit_control
) < 0)
3195 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3196 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3197 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3198 &_pin_based_exec_control
) < 0)
3201 if (!(_cpu_based_2nd_exec_control
&
3202 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3203 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3204 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3206 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3207 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3208 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3209 &_vmentry_control
) < 0)
3212 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3214 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3215 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3218 #ifdef CONFIG_X86_64
3219 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3220 if (vmx_msr_high
& (1u<<16))
3224 /* Require Write-Back (WB) memory type for VMCS accesses. */
3225 if (((vmx_msr_high
>> 18) & 15) != 6)
3228 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3229 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3230 vmcs_conf
->revision_id
= vmx_msr_low
;
3232 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3233 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3234 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3235 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3236 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3238 cpu_has_load_ia32_efer
=
3239 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3240 VM_ENTRY_LOAD_IA32_EFER
)
3241 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3242 VM_EXIT_LOAD_IA32_EFER
);
3244 cpu_has_load_perf_global_ctrl
=
3245 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3246 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3247 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3248 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3251 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3252 * but due to arrata below it can't be used. Workaround is to use
3253 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3255 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3260 * BC86,AAY89,BD102 (model 44)
3264 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3265 switch (boot_cpu_data
.x86_model
) {
3271 cpu_has_load_perf_global_ctrl
= false;
3272 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3273 "does not work properly. Using workaround\n");
3281 rdmsrl(MSR_IA32_XSS
, host_xss
);
3286 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3288 int node
= cpu_to_node(cpu
);
3292 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3295 vmcs
= page_address(pages
);
3296 memset(vmcs
, 0, vmcs_config
.size
);
3297 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3301 static struct vmcs
*alloc_vmcs(void)
3303 return alloc_vmcs_cpu(raw_smp_processor_id());
3306 static void free_vmcs(struct vmcs
*vmcs
)
3308 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3312 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3314 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3316 if (!loaded_vmcs
->vmcs
)
3318 loaded_vmcs_clear(loaded_vmcs
);
3319 free_vmcs(loaded_vmcs
->vmcs
);
3320 loaded_vmcs
->vmcs
= NULL
;
3323 static void free_kvm_area(void)
3327 for_each_possible_cpu(cpu
) {
3328 free_vmcs(per_cpu(vmxarea
, cpu
));
3329 per_cpu(vmxarea
, cpu
) = NULL
;
3333 static void init_vmcs_shadow_fields(void)
3337 /* No checks for read only fields yet */
3339 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3340 switch (shadow_read_write_fields
[i
]) {
3342 if (!vmx_mpx_supported())
3350 shadow_read_write_fields
[j
] =
3351 shadow_read_write_fields
[i
];
3354 max_shadow_read_write_fields
= j
;
3356 /* shadowed fields guest access without vmexit */
3357 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3358 clear_bit(shadow_read_write_fields
[i
],
3359 vmx_vmwrite_bitmap
);
3360 clear_bit(shadow_read_write_fields
[i
],
3363 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3364 clear_bit(shadow_read_only_fields
[i
],
3368 static __init
int alloc_kvm_area(void)
3372 for_each_possible_cpu(cpu
) {
3375 vmcs
= alloc_vmcs_cpu(cpu
);
3381 per_cpu(vmxarea
, cpu
) = vmcs
;
3386 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3388 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3391 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3392 struct kvm_segment
*save
)
3394 if (!emulate_invalid_guest_state
) {
3396 * CS and SS RPL should be equal during guest entry according
3397 * to VMX spec, but in reality it is not always so. Since vcpu
3398 * is in the middle of the transition from real mode to
3399 * protected mode it is safe to assume that RPL 0 is a good
3402 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3403 save
->selector
&= ~SEGMENT_RPL_MASK
;
3404 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3407 vmx_set_segment(vcpu
, save
, seg
);
3410 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3412 unsigned long flags
;
3413 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3416 * Update real mode segment cache. It may be not up-to-date if sement
3417 * register was written while vcpu was in a guest mode.
3419 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3420 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3421 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3422 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3423 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3424 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3426 vmx
->rmode
.vm86_active
= 0;
3428 vmx_segment_cache_clear(vmx
);
3430 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3432 flags
= vmcs_readl(GUEST_RFLAGS
);
3433 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3434 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3435 vmcs_writel(GUEST_RFLAGS
, flags
);
3437 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3438 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3440 update_exception_bitmap(vcpu
);
3442 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3443 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3444 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3445 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3446 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3447 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3450 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3452 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3453 struct kvm_segment var
= *save
;
3456 if (seg
== VCPU_SREG_CS
)
3459 if (!emulate_invalid_guest_state
) {
3460 var
.selector
= var
.base
>> 4;
3461 var
.base
= var
.base
& 0xffff0;
3471 if (save
->base
& 0xf)
3472 printk_once(KERN_WARNING
"kvm: segment base is not "
3473 "paragraph aligned when entering "
3474 "protected mode (seg=%d)", seg
);
3477 vmcs_write16(sf
->selector
, var
.selector
);
3478 vmcs_write32(sf
->base
, var
.base
);
3479 vmcs_write32(sf
->limit
, var
.limit
);
3480 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3483 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3485 unsigned long flags
;
3486 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3488 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3489 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3490 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3491 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3492 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3493 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3494 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3496 vmx
->rmode
.vm86_active
= 1;
3499 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3500 * vcpu. Warn the user that an update is overdue.
3502 if (!vcpu
->kvm
->arch
.tss_addr
)
3503 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3504 "called before entering vcpu\n");
3506 vmx_segment_cache_clear(vmx
);
3508 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3509 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3510 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3512 flags
= vmcs_readl(GUEST_RFLAGS
);
3513 vmx
->rmode
.save_rflags
= flags
;
3515 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3517 vmcs_writel(GUEST_RFLAGS
, flags
);
3518 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3519 update_exception_bitmap(vcpu
);
3521 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3522 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3523 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3524 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3525 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3526 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3528 kvm_mmu_reset_context(vcpu
);
3531 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3533 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3534 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3540 * Force kernel_gs_base reloading before EFER changes, as control
3541 * of this msr depends on is_long_mode().
3543 vmx_load_host_state(to_vmx(vcpu
));
3544 vcpu
->arch
.efer
= efer
;
3545 if (efer
& EFER_LMA
) {
3546 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3549 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3551 msr
->data
= efer
& ~EFER_LME
;
3556 #ifdef CONFIG_X86_64
3558 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3562 vmx_segment_cache_clear(to_vmx(vcpu
));
3564 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3565 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3566 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3568 vmcs_write32(GUEST_TR_AR_BYTES
,
3569 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3570 | VMX_AR_TYPE_BUSY_64_TSS
);
3572 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3575 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3577 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3578 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3583 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3585 vpid_sync_context(vpid
);
3587 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3589 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3593 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3595 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3598 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3600 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3602 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3603 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3606 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3608 if (enable_ept
&& is_paging(vcpu
))
3609 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3610 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3613 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3615 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3617 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3618 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3621 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3623 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3625 if (!test_bit(VCPU_EXREG_PDPTR
,
3626 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3629 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3630 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3631 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3632 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3633 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3637 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3639 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3641 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3642 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3643 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3644 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3645 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3648 __set_bit(VCPU_EXREG_PDPTR
,
3649 (unsigned long *)&vcpu
->arch
.regs_avail
);
3650 __set_bit(VCPU_EXREG_PDPTR
,
3651 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3654 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3656 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3658 struct kvm_vcpu
*vcpu
)
3660 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3661 vmx_decache_cr3(vcpu
);
3662 if (!(cr0
& X86_CR0_PG
)) {
3663 /* From paging/starting to nonpaging */
3664 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3665 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3666 (CPU_BASED_CR3_LOAD_EXITING
|
3667 CPU_BASED_CR3_STORE_EXITING
));
3668 vcpu
->arch
.cr0
= cr0
;
3669 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3670 } else if (!is_paging(vcpu
)) {
3671 /* From nonpaging to paging */
3672 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3673 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3674 ~(CPU_BASED_CR3_LOAD_EXITING
|
3675 CPU_BASED_CR3_STORE_EXITING
));
3676 vcpu
->arch
.cr0
= cr0
;
3677 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3680 if (!(cr0
& X86_CR0_WP
))
3681 *hw_cr0
&= ~X86_CR0_WP
;
3684 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3686 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3687 unsigned long hw_cr0
;
3689 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3690 if (enable_unrestricted_guest
)
3691 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3693 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3695 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3698 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3702 #ifdef CONFIG_X86_64
3703 if (vcpu
->arch
.efer
& EFER_LME
) {
3704 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3706 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3712 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3714 if (!vcpu
->fpu_active
)
3715 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3717 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3718 vmcs_writel(GUEST_CR0
, hw_cr0
);
3719 vcpu
->arch
.cr0
= cr0
;
3721 /* depends on vcpu->arch.cr0 to be set to a new value */
3722 vmx
->emulation_required
= emulation_required(vcpu
);
3725 static u64
construct_eptp(unsigned long root_hpa
)
3729 /* TODO write the value reading from MSR */
3730 eptp
= VMX_EPT_DEFAULT_MT
|
3731 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3732 if (enable_ept_ad_bits
)
3733 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3734 eptp
|= (root_hpa
& PAGE_MASK
);
3739 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3741 unsigned long guest_cr3
;
3746 eptp
= construct_eptp(cr3
);
3747 vmcs_write64(EPT_POINTER
, eptp
);
3748 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3749 guest_cr3
= kvm_read_cr3(vcpu
);
3751 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3752 ept_load_pdptrs(vcpu
);
3755 vmx_flush_tlb(vcpu
);
3756 vmcs_writel(GUEST_CR3
, guest_cr3
);
3759 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3762 * Pass through host's Machine Check Enable value to hw_cr4, which
3763 * is in force while we are in guest mode. Do not let guests control
3764 * this bit, even if host CR4.MCE == 0.
3766 unsigned long hw_cr4
=
3767 (cr4_read_shadow() & X86_CR4_MCE
) |
3768 (cr4
& ~X86_CR4_MCE
) |
3769 (to_vmx(vcpu
)->rmode
.vm86_active
?
3770 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3772 if (cr4
& X86_CR4_VMXE
) {
3774 * To use VMXON (and later other VMX instructions), a guest
3775 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3776 * So basically the check on whether to allow nested VMX
3779 if (!nested_vmx_allowed(vcpu
))
3782 if (to_vmx(vcpu
)->nested
.vmxon
&&
3783 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3786 vcpu
->arch
.cr4
= cr4
;
3788 if (!is_paging(vcpu
)) {
3789 hw_cr4
&= ~X86_CR4_PAE
;
3790 hw_cr4
|= X86_CR4_PSE
;
3792 * SMEP/SMAP is disabled if CPU is in non-paging mode
3793 * in hardware. However KVM always uses paging mode to
3794 * emulate guest non-paging mode with TDP.
3795 * To emulate this behavior, SMEP/SMAP needs to be
3796 * manually disabled when guest switches to non-paging
3799 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3800 } else if (!(cr4
& X86_CR4_PAE
)) {
3801 hw_cr4
&= ~X86_CR4_PAE
;
3805 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3806 vmcs_writel(GUEST_CR4
, hw_cr4
);
3810 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3811 struct kvm_segment
*var
, int seg
)
3813 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3816 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3817 *var
= vmx
->rmode
.segs
[seg
];
3818 if (seg
== VCPU_SREG_TR
3819 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3821 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3822 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3825 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3826 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3827 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3828 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3829 var
->unusable
= (ar
>> 16) & 1;
3830 var
->type
= ar
& 15;
3831 var
->s
= (ar
>> 4) & 1;
3832 var
->dpl
= (ar
>> 5) & 3;
3834 * Some userspaces do not preserve unusable property. Since usable
3835 * segment has to be present according to VMX spec we can use present
3836 * property to amend userspace bug by making unusable segment always
3837 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3838 * segment as unusable.
3840 var
->present
= !var
->unusable
;
3841 var
->avl
= (ar
>> 12) & 1;
3842 var
->l
= (ar
>> 13) & 1;
3843 var
->db
= (ar
>> 14) & 1;
3844 var
->g
= (ar
>> 15) & 1;
3847 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3849 struct kvm_segment s
;
3851 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3852 vmx_get_segment(vcpu
, &s
, seg
);
3855 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3858 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3862 if (unlikely(vmx
->rmode
.vm86_active
))
3865 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3866 return VMX_AR_DPL(ar
);
3870 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3874 if (var
->unusable
|| !var
->present
)
3877 ar
= var
->type
& 15;
3878 ar
|= (var
->s
& 1) << 4;
3879 ar
|= (var
->dpl
& 3) << 5;
3880 ar
|= (var
->present
& 1) << 7;
3881 ar
|= (var
->avl
& 1) << 12;
3882 ar
|= (var
->l
& 1) << 13;
3883 ar
|= (var
->db
& 1) << 14;
3884 ar
|= (var
->g
& 1) << 15;
3890 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3891 struct kvm_segment
*var
, int seg
)
3893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3894 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3896 vmx_segment_cache_clear(vmx
);
3898 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3899 vmx
->rmode
.segs
[seg
] = *var
;
3900 if (seg
== VCPU_SREG_TR
)
3901 vmcs_write16(sf
->selector
, var
->selector
);
3903 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3907 vmcs_writel(sf
->base
, var
->base
);
3908 vmcs_write32(sf
->limit
, var
->limit
);
3909 vmcs_write16(sf
->selector
, var
->selector
);
3912 * Fix the "Accessed" bit in AR field of segment registers for older
3914 * IA32 arch specifies that at the time of processor reset the
3915 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3916 * is setting it to 0 in the userland code. This causes invalid guest
3917 * state vmexit when "unrestricted guest" mode is turned on.
3918 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3919 * tree. Newer qemu binaries with that qemu fix would not need this
3922 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3923 var
->type
|= 0x1; /* Accessed */
3925 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3928 vmx
->emulation_required
= emulation_required(vcpu
);
3931 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3933 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3935 *db
= (ar
>> 14) & 1;
3936 *l
= (ar
>> 13) & 1;
3939 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3941 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3942 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3945 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3947 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3948 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3951 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3953 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3954 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3957 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3959 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3960 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3963 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3965 struct kvm_segment var
;
3968 vmx_get_segment(vcpu
, &var
, seg
);
3970 if (seg
== VCPU_SREG_CS
)
3972 ar
= vmx_segment_access_rights(&var
);
3974 if (var
.base
!= (var
.selector
<< 4))
3976 if (var
.limit
!= 0xffff)
3984 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3986 struct kvm_segment cs
;
3987 unsigned int cs_rpl
;
3989 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3990 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3994 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
3998 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
3999 if (cs
.dpl
> cs_rpl
)
4002 if (cs
.dpl
!= cs_rpl
)
4008 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4012 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4014 struct kvm_segment ss
;
4015 unsigned int ss_rpl
;
4017 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4018 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4022 if (ss
.type
!= 3 && ss
.type
!= 7)
4026 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4034 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4036 struct kvm_segment var
;
4039 vmx_get_segment(vcpu
, &var
, seg
);
4040 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4048 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4049 if (var
.dpl
< rpl
) /* DPL < RPL */
4053 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4059 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4061 struct kvm_segment tr
;
4063 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4067 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4069 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4077 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4079 struct kvm_segment ldtr
;
4081 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4085 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4095 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4097 struct kvm_segment cs
, ss
;
4099 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4100 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4102 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4103 (ss
.selector
& SEGMENT_RPL_MASK
));
4107 * Check if guest state is valid. Returns true if valid, false if
4109 * We assume that registers are always usable
4111 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4113 if (enable_unrestricted_guest
)
4116 /* real mode guest state checks */
4117 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4118 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4120 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4122 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4124 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4126 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4128 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4131 /* protected mode guest state checks */
4132 if (!cs_ss_rpl_check(vcpu
))
4134 if (!code_segment_valid(vcpu
))
4136 if (!stack_segment_valid(vcpu
))
4138 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4140 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4142 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4144 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4146 if (!tr_valid(vcpu
))
4148 if (!ldtr_valid(vcpu
))
4152 * - Add checks on RIP
4153 * - Add checks on RFLAGS
4159 static int init_rmode_tss(struct kvm
*kvm
)
4165 idx
= srcu_read_lock(&kvm
->srcu
);
4166 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4167 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4170 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4171 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4172 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4175 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4178 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4182 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4183 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4186 srcu_read_unlock(&kvm
->srcu
, idx
);
4190 static int init_rmode_identity_map(struct kvm
*kvm
)
4193 pfn_t identity_map_pfn
;
4199 /* Protect kvm->arch.ept_identity_pagetable_done. */
4200 mutex_lock(&kvm
->slots_lock
);
4202 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4205 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4207 r
= alloc_identity_pagetable(kvm
);
4211 idx
= srcu_read_lock(&kvm
->srcu
);
4212 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4215 /* Set up identity-mapping pagetable for EPT in real mode */
4216 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4217 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4218 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4219 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4220 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4224 kvm
->arch
.ept_identity_pagetable_done
= true;
4227 srcu_read_unlock(&kvm
->srcu
, idx
);
4230 mutex_unlock(&kvm
->slots_lock
);
4234 static void seg_setup(int seg
)
4236 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4239 vmcs_write16(sf
->selector
, 0);
4240 vmcs_writel(sf
->base
, 0);
4241 vmcs_write32(sf
->limit
, 0xffff);
4243 if (seg
== VCPU_SREG_CS
)
4244 ar
|= 0x08; /* code segment */
4246 vmcs_write32(sf
->ar_bytes
, ar
);
4249 static int alloc_apic_access_page(struct kvm
*kvm
)
4254 mutex_lock(&kvm
->slots_lock
);
4255 if (kvm
->arch
.apic_access_page_done
)
4257 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4258 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4262 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4263 if (is_error_page(page
)) {
4269 * Do not pin the page in memory, so that memory hot-unplug
4270 * is able to migrate it.
4273 kvm
->arch
.apic_access_page_done
= true;
4275 mutex_unlock(&kvm
->slots_lock
);
4279 static int alloc_identity_pagetable(struct kvm
*kvm
)
4281 /* Called with kvm->slots_lock held. */
4285 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4287 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4288 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4293 static int allocate_vpid(void)
4299 spin_lock(&vmx_vpid_lock
);
4300 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4301 if (vpid
< VMX_NR_VPIDS
)
4302 __set_bit(vpid
, vmx_vpid_bitmap
);
4305 spin_unlock(&vmx_vpid_lock
);
4309 static void free_vpid(int vpid
)
4311 if (!enable_vpid
|| vpid
== 0)
4313 spin_lock(&vmx_vpid_lock
);
4314 __clear_bit(vpid
, vmx_vpid_bitmap
);
4315 spin_unlock(&vmx_vpid_lock
);
4318 #define MSR_TYPE_R 1
4319 #define MSR_TYPE_W 2
4320 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4323 int f
= sizeof(unsigned long);
4325 if (!cpu_has_vmx_msr_bitmap())
4329 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4330 * have the write-low and read-high bitmap offsets the wrong way round.
4331 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4333 if (msr
<= 0x1fff) {
4334 if (type
& MSR_TYPE_R
)
4336 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4338 if (type
& MSR_TYPE_W
)
4340 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4342 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4344 if (type
& MSR_TYPE_R
)
4346 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4348 if (type
& MSR_TYPE_W
)
4350 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4355 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4358 int f
= sizeof(unsigned long);
4360 if (!cpu_has_vmx_msr_bitmap())
4364 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4365 * have the write-low and read-high bitmap offsets the wrong way round.
4366 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4368 if (msr
<= 0x1fff) {
4369 if (type
& MSR_TYPE_R
)
4371 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4373 if (type
& MSR_TYPE_W
)
4375 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4377 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4379 if (type
& MSR_TYPE_R
)
4381 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4383 if (type
& MSR_TYPE_W
)
4385 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4391 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4392 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4394 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4395 unsigned long *msr_bitmap_nested
,
4398 int f
= sizeof(unsigned long);
4400 if (!cpu_has_vmx_msr_bitmap()) {
4406 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4407 * have the write-low and read-high bitmap offsets the wrong way round.
4408 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4410 if (msr
<= 0x1fff) {
4411 if (type
& MSR_TYPE_R
&&
4412 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4414 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4416 if (type
& MSR_TYPE_W
&&
4417 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4419 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4421 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4423 if (type
& MSR_TYPE_R
&&
4424 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4426 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4428 if (type
& MSR_TYPE_W
&&
4429 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4431 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4436 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4439 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4440 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4441 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4442 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4445 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4447 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4449 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4453 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4455 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4457 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4461 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4463 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4465 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4469 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
4471 return enable_apicv
&& lapic_in_kernel(vcpu
);
4474 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4481 if (vmx
->nested
.pi_desc
&&
4482 vmx
->nested
.pi_pending
) {
4483 vmx
->nested
.pi_pending
= false;
4484 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4487 max_irr
= find_last_bit(
4488 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4493 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4498 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4499 kunmap(vmx
->nested
.virtual_apic_page
);
4501 status
= vmcs_read16(GUEST_INTR_STATUS
);
4502 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4504 status
|= (u8
)max_irr
;
4505 vmcs_write16(GUEST_INTR_STATUS
, status
);
4511 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4514 if (vcpu
->mode
== IN_GUEST_MODE
) {
4515 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4518 * Currently, we don't support urgent interrupt,
4519 * all interrupts are recognized as non-urgent
4520 * interrupt, so we cannot post interrupts when
4523 * If the vcpu is in guest mode, it means it is
4524 * running instead of being scheduled out and
4525 * waiting in the run queue, and that's the only
4526 * case when 'SN' is set currently, warning if
4529 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4531 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4532 POSTED_INTR_VECTOR
);
4539 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4544 if (is_guest_mode(vcpu
) &&
4545 vector
== vmx
->nested
.posted_intr_nv
) {
4546 /* the PIR and ON have been set by L1. */
4547 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4549 * If a posted intr is not recognized by hardware,
4550 * we will accomplish it in the next vmentry.
4552 vmx
->nested
.pi_pending
= true;
4553 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4559 * Send interrupt to vcpu via posted interrupt way.
4560 * 1. If target vcpu is running(non-root mode), send posted interrupt
4561 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4562 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4563 * interrupt from PIR in next vmentry.
4565 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4567 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4570 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4574 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4577 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4578 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4579 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4580 kvm_vcpu_kick(vcpu
);
4583 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4585 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4587 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4590 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4593 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4599 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4600 * will not change in the lifetime of the guest.
4601 * Note that host-state that does change is set elsewhere. E.g., host-state
4602 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4604 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4611 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4612 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4614 /* Save the most likely value for this task's CR4 in the VMCS. */
4615 cr4
= cr4_read_shadow();
4616 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4617 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4619 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4620 #ifdef CONFIG_X86_64
4622 * Load null selectors, so we can avoid reloading them in
4623 * __vmx_load_host_state(), in case userspace uses the null selectors
4624 * too (the expected case).
4626 vmcs_write16(HOST_DS_SELECTOR
, 0);
4627 vmcs_write16(HOST_ES_SELECTOR
, 0);
4629 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4630 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4632 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4633 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4635 native_store_idt(&dt
);
4636 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4637 vmx
->host_idt_base
= dt
.address
;
4639 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4641 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4642 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4643 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4644 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4646 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4647 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4648 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4652 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4654 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4656 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4657 if (is_guest_mode(&vmx
->vcpu
))
4658 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4659 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4660 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4663 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4665 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4667 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4668 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4669 return pin_based_exec_ctrl
;
4672 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4674 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4676 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4677 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4679 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4680 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4681 #ifdef CONFIG_X86_64
4682 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4683 CPU_BASED_CR8_LOAD_EXITING
;
4687 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4688 CPU_BASED_CR3_LOAD_EXITING
|
4689 CPU_BASED_INVLPG_EXITING
;
4690 return exec_control
;
4693 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4695 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4696 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4697 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4699 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4701 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4702 enable_unrestricted_guest
= 0;
4703 /* Enable INVPCID for non-ept guests may cause performance regression. */
4704 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4706 if (!enable_unrestricted_guest
)
4707 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4709 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4710 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4711 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4712 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4713 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4714 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4716 We can NOT enable shadow_vmcs here because we don't have yet
4719 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4720 /* PML is enabled/disabled in creating/destorying vcpu */
4721 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4723 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4724 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4726 return exec_control
;
4729 static void ept_set_mmio_spte_mask(void)
4732 * EPT Misconfigurations can be generated if the value of bits 2:0
4733 * of an EPT paging-structure entry is 110b (write/execute).
4734 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4737 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4740 #define VMX_XSS_EXIT_BITMAP 0
4742 * Sets up the vmcs for emulated real mode.
4744 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4746 #ifdef CONFIG_X86_64
4752 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4753 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4755 if (enable_shadow_vmcs
) {
4756 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4757 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4759 if (cpu_has_vmx_msr_bitmap())
4760 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4762 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4765 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4767 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4769 if (cpu_has_secondary_exec_ctrls())
4770 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4771 vmx_secondary_exec_control(vmx
));
4773 if (vmx_cpu_uses_apicv(&vmx
->vcpu
)) {
4774 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4775 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4776 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4777 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4779 vmcs_write16(GUEST_INTR_STATUS
, 0);
4781 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4782 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4786 vmcs_write32(PLE_GAP
, ple_gap
);
4787 vmx
->ple_window
= ple_window
;
4788 vmx
->ple_window_dirty
= true;
4791 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4792 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4793 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4795 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4796 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4797 vmx_set_constant_host_state(vmx
);
4798 #ifdef CONFIG_X86_64
4799 rdmsrl(MSR_FS_BASE
, a
);
4800 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4801 rdmsrl(MSR_GS_BASE
, a
);
4802 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4804 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4805 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4808 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4809 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4810 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4811 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4812 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4814 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4815 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4817 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4818 u32 index
= vmx_msr_index
[i
];
4819 u32 data_low
, data_high
;
4822 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4824 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4826 vmx
->guest_msrs
[j
].index
= i
;
4827 vmx
->guest_msrs
[j
].data
= 0;
4828 vmx
->guest_msrs
[j
].mask
= -1ull;
4833 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4835 /* 22.2.1, 20.8.1 */
4836 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4838 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4839 set_cr4_guest_host_mask(vmx
);
4841 if (vmx_xsaves_supported())
4842 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4847 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4849 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4850 struct msr_data apic_base_msr
;
4853 vmx
->rmode
.vm86_active
= 0;
4855 vmx
->soft_vnmi_blocked
= 0;
4857 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4858 kvm_set_cr8(vcpu
, 0);
4861 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4862 MSR_IA32_APICBASE_ENABLE
;
4863 if (kvm_vcpu_is_reset_bsp(vcpu
))
4864 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4865 apic_base_msr
.host_initiated
= true;
4866 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4869 vmx_segment_cache_clear(vmx
);
4871 seg_setup(VCPU_SREG_CS
);
4872 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4873 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4875 seg_setup(VCPU_SREG_DS
);
4876 seg_setup(VCPU_SREG_ES
);
4877 seg_setup(VCPU_SREG_FS
);
4878 seg_setup(VCPU_SREG_GS
);
4879 seg_setup(VCPU_SREG_SS
);
4881 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4882 vmcs_writel(GUEST_TR_BASE
, 0);
4883 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4884 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4886 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4887 vmcs_writel(GUEST_LDTR_BASE
, 0);
4888 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4889 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4892 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4893 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4894 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4895 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4898 vmcs_writel(GUEST_RFLAGS
, 0x02);
4899 kvm_rip_write(vcpu
, 0xfff0);
4901 vmcs_writel(GUEST_GDTR_BASE
, 0);
4902 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4904 vmcs_writel(GUEST_IDTR_BASE
, 0);
4905 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4907 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4908 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4909 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4913 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4915 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4916 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4917 if (cpu_need_tpr_shadow(vcpu
))
4918 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4919 __pa(vcpu
->arch
.apic
->regs
));
4920 vmcs_write32(TPR_THRESHOLD
, 0);
4923 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4925 if (vmx_cpu_uses_apicv(vcpu
))
4926 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4929 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4931 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4932 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4933 vmx
->vcpu
.arch
.cr0
= cr0
;
4934 vmx_set_cr4(vcpu
, 0);
4936 vmx_set_efer(vcpu
, 0);
4937 vmx_fpu_activate(vcpu
);
4938 update_exception_bitmap(vcpu
);
4940 vpid_sync_context(vmx
->vpid
);
4944 * In nested virtualization, check if L1 asked to exit on external interrupts.
4945 * For most existing hypervisors, this will always return true.
4947 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4949 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4950 PIN_BASED_EXT_INTR_MASK
;
4954 * In nested virtualization, check if L1 has set
4955 * VM_EXIT_ACK_INTR_ON_EXIT
4957 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4959 return get_vmcs12(vcpu
)->vm_exit_controls
&
4960 VM_EXIT_ACK_INTR_ON_EXIT
;
4963 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4965 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4966 PIN_BASED_NMI_EXITING
;
4969 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4971 u32 cpu_based_vm_exec_control
;
4973 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4974 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4975 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4978 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4980 u32 cpu_based_vm_exec_control
;
4982 if (!cpu_has_virtual_nmis() ||
4983 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4984 enable_irq_window(vcpu
);
4988 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4989 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4990 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4993 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4995 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4997 int irq
= vcpu
->arch
.interrupt
.nr
;
4999 trace_kvm_inj_virq(irq
);
5001 ++vcpu
->stat
.irq_injections
;
5002 if (vmx
->rmode
.vm86_active
) {
5004 if (vcpu
->arch
.interrupt
.soft
)
5005 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5006 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5007 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5010 intr
= irq
| INTR_INFO_VALID_MASK
;
5011 if (vcpu
->arch
.interrupt
.soft
) {
5012 intr
|= INTR_TYPE_SOFT_INTR
;
5013 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5014 vmx
->vcpu
.arch
.event_exit_inst_len
);
5016 intr
|= INTR_TYPE_EXT_INTR
;
5017 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5020 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5022 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5024 if (is_guest_mode(vcpu
))
5027 if (!cpu_has_virtual_nmis()) {
5029 * Tracking the NMI-blocked state in software is built upon
5030 * finding the next open IRQ window. This, in turn, depends on
5031 * well-behaving guests: They have to keep IRQs disabled at
5032 * least as long as the NMI handler runs. Otherwise we may
5033 * cause NMI nesting, maybe breaking the guest. But as this is
5034 * highly unlikely, we can live with the residual risk.
5036 vmx
->soft_vnmi_blocked
= 1;
5037 vmx
->vnmi_blocked_time
= 0;
5040 ++vcpu
->stat
.nmi_injections
;
5041 vmx
->nmi_known_unmasked
= false;
5042 if (vmx
->rmode
.vm86_active
) {
5043 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5044 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5047 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5048 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5051 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5053 if (!cpu_has_virtual_nmis())
5054 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5055 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5057 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5060 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5062 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5064 if (!cpu_has_virtual_nmis()) {
5065 if (vmx
->soft_vnmi_blocked
!= masked
) {
5066 vmx
->soft_vnmi_blocked
= masked
;
5067 vmx
->vnmi_blocked_time
= 0;
5070 vmx
->nmi_known_unmasked
= !masked
;
5072 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5073 GUEST_INTR_STATE_NMI
);
5075 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5076 GUEST_INTR_STATE_NMI
);
5080 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5082 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5085 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5088 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5089 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5090 | GUEST_INTR_STATE_NMI
));
5093 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5095 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5096 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5097 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5098 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5101 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5105 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5109 kvm
->arch
.tss_addr
= addr
;
5110 return init_rmode_tss(kvm
);
5113 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5118 * Update instruction length as we may reinject the exception
5119 * from user space while in guest debugging mode.
5121 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5122 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5123 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5127 if (vcpu
->guest_debug
&
5128 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5145 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5146 int vec
, u32 err_code
)
5149 * Instruction with address size override prefix opcode 0x67
5150 * Cause the #SS fault with 0 error code in VM86 mode.
5152 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5153 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5154 if (vcpu
->arch
.halt_request
) {
5155 vcpu
->arch
.halt_request
= 0;
5156 return kvm_vcpu_halt(vcpu
);
5164 * Forward all other exceptions that are valid in real mode.
5165 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5166 * the required debugging infrastructure rework.
5168 kvm_queue_exception(vcpu
, vec
);
5173 * Trigger machine check on the host. We assume all the MSRs are already set up
5174 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5175 * We pass a fake environment to the machine check handler because we want
5176 * the guest to be always treated like user space, no matter what context
5177 * it used internally.
5179 static void kvm_machine_check(void)
5181 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5182 struct pt_regs regs
= {
5183 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5184 .flags
= X86_EFLAGS_IF
,
5187 do_machine_check(®s
, 0);
5191 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5193 /* already handled by vcpu_run */
5197 static int handle_exception(struct kvm_vcpu
*vcpu
)
5199 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5200 struct kvm_run
*kvm_run
= vcpu
->run
;
5201 u32 intr_info
, ex_no
, error_code
;
5202 unsigned long cr2
, rip
, dr6
;
5204 enum emulation_result er
;
5206 vect_info
= vmx
->idt_vectoring_info
;
5207 intr_info
= vmx
->exit_intr_info
;
5209 if (is_machine_check(intr_info
))
5210 return handle_machine_check(vcpu
);
5212 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5213 return 1; /* already handled by vmx_vcpu_run() */
5215 if (is_no_device(intr_info
)) {
5216 vmx_fpu_activate(vcpu
);
5220 if (is_invalid_opcode(intr_info
)) {
5221 if (is_guest_mode(vcpu
)) {
5222 kvm_queue_exception(vcpu
, UD_VECTOR
);
5225 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5226 if (er
!= EMULATE_DONE
)
5227 kvm_queue_exception(vcpu
, UD_VECTOR
);
5232 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5233 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5236 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5237 * MMIO, it is better to report an internal error.
5238 * See the comments in vmx_handle_exit.
5240 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5241 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5242 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5243 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5244 vcpu
->run
->internal
.ndata
= 3;
5245 vcpu
->run
->internal
.data
[0] = vect_info
;
5246 vcpu
->run
->internal
.data
[1] = intr_info
;
5247 vcpu
->run
->internal
.data
[2] = error_code
;
5251 if (is_page_fault(intr_info
)) {
5252 /* EPT won't cause page fault directly */
5254 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5255 trace_kvm_page_fault(cr2
, error_code
);
5257 if (kvm_event_needs_reinjection(vcpu
))
5258 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5259 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5262 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5264 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5265 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5269 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5270 if (!(vcpu
->guest_debug
&
5271 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5272 vcpu
->arch
.dr6
&= ~15;
5273 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5274 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5275 skip_emulated_instruction(vcpu
);
5277 kvm_queue_exception(vcpu
, DB_VECTOR
);
5280 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5281 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5285 * Update instruction length as we may reinject #BP from
5286 * user space while in guest debugging mode. Reading it for
5287 * #DB as well causes no harm, it is not used in that case.
5289 vmx
->vcpu
.arch
.event_exit_inst_len
=
5290 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5291 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5292 rip
= kvm_rip_read(vcpu
);
5293 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5294 kvm_run
->debug
.arch
.exception
= ex_no
;
5297 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5298 kvm_run
->ex
.exception
= ex_no
;
5299 kvm_run
->ex
.error_code
= error_code
;
5305 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5307 ++vcpu
->stat
.irq_exits
;
5311 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5313 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5317 static int handle_io(struct kvm_vcpu
*vcpu
)
5319 unsigned long exit_qualification
;
5320 int size
, in
, string
;
5323 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5324 string
= (exit_qualification
& 16) != 0;
5325 in
= (exit_qualification
& 8) != 0;
5327 ++vcpu
->stat
.io_exits
;
5330 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5332 port
= exit_qualification
>> 16;
5333 size
= (exit_qualification
& 7) + 1;
5334 skip_emulated_instruction(vcpu
);
5336 return kvm_fast_pio_out(vcpu
, size
, port
);
5340 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5343 * Patch in the VMCALL instruction:
5345 hypercall
[0] = 0x0f;
5346 hypercall
[1] = 0x01;
5347 hypercall
[2] = 0xc1;
5350 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5352 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5353 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5355 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5356 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5357 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5358 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5359 return (val
& always_on
) == always_on
;
5362 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5363 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5365 if (is_guest_mode(vcpu
)) {
5366 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5367 unsigned long orig_val
= val
;
5370 * We get here when L2 changed cr0 in a way that did not change
5371 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5372 * but did change L0 shadowed bits. So we first calculate the
5373 * effective cr0 value that L1 would like to write into the
5374 * hardware. It consists of the L2-owned bits from the new
5375 * value combined with the L1-owned bits from L1's guest_cr0.
5377 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5378 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5380 if (!nested_cr0_valid(vcpu
, val
))
5383 if (kvm_set_cr0(vcpu
, val
))
5385 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5388 if (to_vmx(vcpu
)->nested
.vmxon
&&
5389 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5391 return kvm_set_cr0(vcpu
, val
);
5395 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5397 if (is_guest_mode(vcpu
)) {
5398 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5399 unsigned long orig_val
= val
;
5401 /* analogously to handle_set_cr0 */
5402 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5403 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5404 if (kvm_set_cr4(vcpu
, val
))
5406 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5409 return kvm_set_cr4(vcpu
, val
);
5412 /* called to set cr0 as approriate for clts instruction exit. */
5413 static void handle_clts(struct kvm_vcpu
*vcpu
)
5415 if (is_guest_mode(vcpu
)) {
5417 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5418 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5419 * just pretend it's off (also in arch.cr0 for fpu_activate).
5421 vmcs_writel(CR0_READ_SHADOW
,
5422 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5423 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5425 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5428 static int handle_cr(struct kvm_vcpu
*vcpu
)
5430 unsigned long exit_qualification
, val
;
5435 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5436 cr
= exit_qualification
& 15;
5437 reg
= (exit_qualification
>> 8) & 15;
5438 switch ((exit_qualification
>> 4) & 3) {
5439 case 0: /* mov to cr */
5440 val
= kvm_register_readl(vcpu
, reg
);
5441 trace_kvm_cr_write(cr
, val
);
5444 err
= handle_set_cr0(vcpu
, val
);
5445 kvm_complete_insn_gp(vcpu
, err
);
5448 err
= kvm_set_cr3(vcpu
, val
);
5449 kvm_complete_insn_gp(vcpu
, err
);
5452 err
= handle_set_cr4(vcpu
, val
);
5453 kvm_complete_insn_gp(vcpu
, err
);
5456 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5458 err
= kvm_set_cr8(vcpu
, cr8
);
5459 kvm_complete_insn_gp(vcpu
, err
);
5460 if (lapic_in_kernel(vcpu
))
5462 if (cr8_prev
<= cr8
)
5464 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5471 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5472 skip_emulated_instruction(vcpu
);
5473 vmx_fpu_activate(vcpu
);
5475 case 1: /*mov from cr*/
5478 val
= kvm_read_cr3(vcpu
);
5479 kvm_register_write(vcpu
, reg
, val
);
5480 trace_kvm_cr_read(cr
, val
);
5481 skip_emulated_instruction(vcpu
);
5484 val
= kvm_get_cr8(vcpu
);
5485 kvm_register_write(vcpu
, reg
, val
);
5486 trace_kvm_cr_read(cr
, val
);
5487 skip_emulated_instruction(vcpu
);
5492 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5493 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5494 kvm_lmsw(vcpu
, val
);
5496 skip_emulated_instruction(vcpu
);
5501 vcpu
->run
->exit_reason
= 0;
5502 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5503 (int)(exit_qualification
>> 4) & 3, cr
);
5507 static int handle_dr(struct kvm_vcpu
*vcpu
)
5509 unsigned long exit_qualification
;
5512 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5513 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5515 /* First, if DR does not exist, trigger UD */
5516 if (!kvm_require_dr(vcpu
, dr
))
5519 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5520 if (!kvm_require_cpl(vcpu
, 0))
5522 dr7
= vmcs_readl(GUEST_DR7
);
5525 * As the vm-exit takes precedence over the debug trap, we
5526 * need to emulate the latter, either for the host or the
5527 * guest debugging itself.
5529 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5530 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5531 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5532 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5533 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5534 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5537 vcpu
->arch
.dr6
&= ~15;
5538 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5539 kvm_queue_exception(vcpu
, DB_VECTOR
);
5544 if (vcpu
->guest_debug
== 0) {
5545 u32 cpu_based_vm_exec_control
;
5547 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5548 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5549 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5552 * No more DR vmexits; force a reload of the debug registers
5553 * and reenter on this instruction. The next vmexit will
5554 * retrieve the full state of the debug registers.
5556 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5560 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5561 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5564 if (kvm_get_dr(vcpu
, dr
, &val
))
5566 kvm_register_write(vcpu
, reg
, val
);
5568 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5571 skip_emulated_instruction(vcpu
);
5575 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5577 return vcpu
->arch
.dr6
;
5580 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5584 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5586 u32 cpu_based_vm_exec_control
;
5588 get_debugreg(vcpu
->arch
.db
[0], 0);
5589 get_debugreg(vcpu
->arch
.db
[1], 1);
5590 get_debugreg(vcpu
->arch
.db
[2], 2);
5591 get_debugreg(vcpu
->arch
.db
[3], 3);
5592 get_debugreg(vcpu
->arch
.dr6
, 6);
5593 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5595 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5597 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5598 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5599 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5602 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5604 vmcs_writel(GUEST_DR7
, val
);
5607 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5609 kvm_emulate_cpuid(vcpu
);
5613 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5615 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5616 struct msr_data msr_info
;
5618 msr_info
.index
= ecx
;
5619 msr_info
.host_initiated
= false;
5620 if (vmx_get_msr(vcpu
, &msr_info
)) {
5621 trace_kvm_msr_read_ex(ecx
);
5622 kvm_inject_gp(vcpu
, 0);
5626 trace_kvm_msr_read(ecx
, msr_info
.data
);
5628 /* FIXME: handling of bits 32:63 of rax, rdx */
5629 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5630 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5631 skip_emulated_instruction(vcpu
);
5635 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5637 struct msr_data msr
;
5638 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5639 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5640 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5644 msr
.host_initiated
= false;
5645 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5646 trace_kvm_msr_write_ex(ecx
, data
);
5647 kvm_inject_gp(vcpu
, 0);
5651 trace_kvm_msr_write(ecx
, data
);
5652 skip_emulated_instruction(vcpu
);
5656 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5658 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5662 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5664 u32 cpu_based_vm_exec_control
;
5666 /* clear pending irq */
5667 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5668 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5669 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5671 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5673 ++vcpu
->stat
.irq_window_exits
;
5677 static int handle_halt(struct kvm_vcpu
*vcpu
)
5679 return kvm_emulate_halt(vcpu
);
5682 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5684 kvm_emulate_hypercall(vcpu
);
5688 static int handle_invd(struct kvm_vcpu
*vcpu
)
5690 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5693 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5695 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5697 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5698 skip_emulated_instruction(vcpu
);
5702 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5706 err
= kvm_rdpmc(vcpu
);
5707 kvm_complete_insn_gp(vcpu
, err
);
5712 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5714 kvm_emulate_wbinvd(vcpu
);
5718 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5720 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5721 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5723 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5724 skip_emulated_instruction(vcpu
);
5728 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5730 skip_emulated_instruction(vcpu
);
5731 WARN(1, "this should never happen\n");
5735 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5737 skip_emulated_instruction(vcpu
);
5738 WARN(1, "this should never happen\n");
5742 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5744 if (likely(fasteoi
)) {
5745 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5746 int access_type
, offset
;
5748 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5749 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5751 * Sane guest uses MOV to write EOI, with written value
5752 * not cared. So make a short-circuit here by avoiding
5753 * heavy instruction emulation.
5755 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5756 (offset
== APIC_EOI
)) {
5757 kvm_lapic_set_eoi(vcpu
);
5758 skip_emulated_instruction(vcpu
);
5762 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5765 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5767 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5768 int vector
= exit_qualification
& 0xff;
5770 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5771 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5775 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5777 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5778 u32 offset
= exit_qualification
& 0xfff;
5780 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5781 kvm_apic_write_nodecode(vcpu
, offset
);
5785 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5787 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5788 unsigned long exit_qualification
;
5789 bool has_error_code
= false;
5792 int reason
, type
, idt_v
, idt_index
;
5794 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5795 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5796 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5798 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5800 reason
= (u32
)exit_qualification
>> 30;
5801 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5803 case INTR_TYPE_NMI_INTR
:
5804 vcpu
->arch
.nmi_injected
= false;
5805 vmx_set_nmi_mask(vcpu
, true);
5807 case INTR_TYPE_EXT_INTR
:
5808 case INTR_TYPE_SOFT_INTR
:
5809 kvm_clear_interrupt_queue(vcpu
);
5811 case INTR_TYPE_HARD_EXCEPTION
:
5812 if (vmx
->idt_vectoring_info
&
5813 VECTORING_INFO_DELIVER_CODE_MASK
) {
5814 has_error_code
= true;
5816 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5819 case INTR_TYPE_SOFT_EXCEPTION
:
5820 kvm_clear_exception_queue(vcpu
);
5826 tss_selector
= exit_qualification
;
5828 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5829 type
!= INTR_TYPE_EXT_INTR
&&
5830 type
!= INTR_TYPE_NMI_INTR
))
5831 skip_emulated_instruction(vcpu
);
5833 if (kvm_task_switch(vcpu
, tss_selector
,
5834 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5835 has_error_code
, error_code
) == EMULATE_FAIL
) {
5836 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5837 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5838 vcpu
->run
->internal
.ndata
= 0;
5843 * TODO: What about debug traps on tss switch?
5844 * Are we supposed to inject them and update dr6?
5850 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5852 unsigned long exit_qualification
;
5857 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5859 gla_validity
= (exit_qualification
>> 7) & 0x3;
5860 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5861 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5862 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5863 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5864 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5865 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5866 (long unsigned int)exit_qualification
);
5867 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5868 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5873 * EPT violation happened while executing iret from NMI,
5874 * "blocked by NMI" bit has to be set before next VM entry.
5875 * There are errata that may cause this bit to not be set:
5878 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5879 cpu_has_virtual_nmis() &&
5880 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5881 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5883 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5884 trace_kvm_page_fault(gpa
, exit_qualification
);
5886 /* It is a write fault? */
5887 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5888 /* It is a fetch fault? */
5889 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5890 /* ept page table is present? */
5891 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5893 vcpu
->arch
.exit_qualification
= exit_qualification
;
5895 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5898 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5903 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5904 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5905 skip_emulated_instruction(vcpu
);
5906 trace_kvm_fast_mmio(gpa
);
5910 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5911 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5912 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5915 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5916 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5918 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5921 /* It is the real ept misconfig */
5924 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5925 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5930 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5932 u32 cpu_based_vm_exec_control
;
5934 /* clear pending NMI */
5935 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5936 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5937 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5938 ++vcpu
->stat
.nmi_window_exits
;
5939 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5944 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5946 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5947 enum emulation_result err
= EMULATE_DONE
;
5950 bool intr_window_requested
;
5951 unsigned count
= 130;
5953 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5954 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5956 while (vmx
->emulation_required
&& count
-- != 0) {
5957 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5958 return handle_interrupt_window(&vmx
->vcpu
);
5960 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5963 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5965 if (err
== EMULATE_USER_EXIT
) {
5966 ++vcpu
->stat
.mmio_exits
;
5971 if (err
!= EMULATE_DONE
) {
5972 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5973 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5974 vcpu
->run
->internal
.ndata
= 0;
5978 if (vcpu
->arch
.halt_request
) {
5979 vcpu
->arch
.halt_request
= 0;
5980 ret
= kvm_vcpu_halt(vcpu
);
5984 if (signal_pending(current
))
5994 static int __grow_ple_window(int val
)
5996 if (ple_window_grow
< 1)
5999 val
= min(val
, ple_window_actual_max
);
6001 if (ple_window_grow
< ple_window
)
6002 val
*= ple_window_grow
;
6004 val
+= ple_window_grow
;
6009 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6014 if (modifier
< ple_window
)
6019 return max(val
, minimum
);
6022 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6024 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6025 int old
= vmx
->ple_window
;
6027 vmx
->ple_window
= __grow_ple_window(old
);
6029 if (vmx
->ple_window
!= old
)
6030 vmx
->ple_window_dirty
= true;
6032 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6035 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6037 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6038 int old
= vmx
->ple_window
;
6040 vmx
->ple_window
= __shrink_ple_window(old
,
6041 ple_window_shrink
, ple_window
);
6043 if (vmx
->ple_window
!= old
)
6044 vmx
->ple_window_dirty
= true;
6046 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6050 * ple_window_actual_max is computed to be one grow_ple_window() below
6051 * ple_window_max. (See __grow_ple_window for the reason.)
6052 * This prevents overflows, because ple_window_max is int.
6053 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6055 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6057 static void update_ple_window_actual_max(void)
6059 ple_window_actual_max
=
6060 __shrink_ple_window(max(ple_window_max
, ple_window
),
6061 ple_window_grow
, INT_MIN
);
6065 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6067 static void wakeup_handler(void)
6069 struct kvm_vcpu
*vcpu
;
6070 int cpu
= smp_processor_id();
6072 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6073 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6074 blocked_vcpu_list
) {
6075 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6077 if (pi_test_on(pi_desc
) == 1)
6078 kvm_vcpu_kick(vcpu
);
6080 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6083 static __init
int hardware_setup(void)
6085 int r
= -ENOMEM
, i
, msr
;
6087 rdmsrl_safe(MSR_EFER
, &host_efer
);
6089 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6090 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6092 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6093 if (!vmx_io_bitmap_a
)
6096 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6097 if (!vmx_io_bitmap_b
)
6100 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6101 if (!vmx_msr_bitmap_legacy
)
6104 vmx_msr_bitmap_legacy_x2apic
=
6105 (unsigned long *)__get_free_page(GFP_KERNEL
);
6106 if (!vmx_msr_bitmap_legacy_x2apic
)
6109 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6110 if (!vmx_msr_bitmap_longmode
)
6113 vmx_msr_bitmap_longmode_x2apic
=
6114 (unsigned long *)__get_free_page(GFP_KERNEL
);
6115 if (!vmx_msr_bitmap_longmode_x2apic
)
6119 vmx_msr_bitmap_nested
=
6120 (unsigned long *)__get_free_page(GFP_KERNEL
);
6121 if (!vmx_msr_bitmap_nested
)
6125 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6126 if (!vmx_vmread_bitmap
)
6129 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6130 if (!vmx_vmwrite_bitmap
)
6133 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6134 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6137 * Allow direct access to the PC debug port (it is often used for I/O
6138 * delays, but the vmexits simply slow things down).
6140 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6141 clear_bit(0x80, vmx_io_bitmap_a
);
6143 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6145 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6146 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6148 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6150 if (setup_vmcs_config(&vmcs_config
) < 0) {
6155 if (boot_cpu_has(X86_FEATURE_NX
))
6156 kvm_enable_efer_bits(EFER_NX
);
6158 if (!cpu_has_vmx_vpid())
6160 if (!cpu_has_vmx_shadow_vmcs())
6161 enable_shadow_vmcs
= 0;
6162 if (enable_shadow_vmcs
)
6163 init_vmcs_shadow_fields();
6165 if (!cpu_has_vmx_ept() ||
6166 !cpu_has_vmx_ept_4levels()) {
6168 enable_unrestricted_guest
= 0;
6169 enable_ept_ad_bits
= 0;
6172 if (!cpu_has_vmx_ept_ad_bits())
6173 enable_ept_ad_bits
= 0;
6175 if (!cpu_has_vmx_unrestricted_guest())
6176 enable_unrestricted_guest
= 0;
6178 if (!cpu_has_vmx_flexpriority())
6179 flexpriority_enabled
= 0;
6182 * set_apic_access_page_addr() is used to reload apic access
6183 * page upon invalidation. No need to do anything if not
6184 * using the APIC_ACCESS_ADDR VMCS field.
6186 if (!flexpriority_enabled
)
6187 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6189 if (!cpu_has_vmx_tpr_shadow())
6190 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6192 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6193 kvm_disable_largepages();
6195 if (!cpu_has_vmx_ple())
6198 if (!cpu_has_vmx_apicv())
6202 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6204 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6205 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6206 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6207 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6210 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6211 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6212 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6213 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6214 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6215 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6216 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6218 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6219 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6220 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6221 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6223 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6226 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6227 vmx_disable_intercept_msr_read_x2apic(msr
);
6229 /* According SDM, in x2apic mode, the whole id reg is used.
6230 * But in KVM, it only use the highest eight bits. Need to
6232 vmx_enable_intercept_msr_read_x2apic(0x802);
6234 vmx_enable_intercept_msr_read_x2apic(0x839);
6236 vmx_disable_intercept_msr_write_x2apic(0x808);
6238 vmx_disable_intercept_msr_write_x2apic(0x80b);
6240 vmx_disable_intercept_msr_write_x2apic(0x83f);
6244 kvm_mmu_set_mask_ptes(0ull,
6245 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6246 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6247 0ull, VMX_EPT_EXECUTABLE_MASK
);
6248 ept_set_mmio_spte_mask();
6253 update_ple_window_actual_max();
6256 * Only enable PML when hardware supports PML feature, and both EPT
6257 * and EPT A/D bit features are enabled -- PML depends on them to work.
6259 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6263 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6264 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6265 kvm_x86_ops
->flush_log_dirty
= NULL
;
6266 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6269 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6271 return alloc_kvm_area();
6274 free_page((unsigned long)vmx_vmwrite_bitmap
);
6276 free_page((unsigned long)vmx_vmread_bitmap
);
6279 free_page((unsigned long)vmx_msr_bitmap_nested
);
6281 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6283 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6285 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6287 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6289 free_page((unsigned long)vmx_io_bitmap_b
);
6291 free_page((unsigned long)vmx_io_bitmap_a
);
6296 static __exit
void hardware_unsetup(void)
6298 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6299 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6300 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6301 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6302 free_page((unsigned long)vmx_io_bitmap_b
);
6303 free_page((unsigned long)vmx_io_bitmap_a
);
6304 free_page((unsigned long)vmx_vmwrite_bitmap
);
6305 free_page((unsigned long)vmx_vmread_bitmap
);
6307 free_page((unsigned long)vmx_msr_bitmap_nested
);
6313 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6314 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6316 static int handle_pause(struct kvm_vcpu
*vcpu
)
6319 grow_ple_window(vcpu
);
6321 skip_emulated_instruction(vcpu
);
6322 kvm_vcpu_on_spin(vcpu
);
6327 static int handle_nop(struct kvm_vcpu
*vcpu
)
6329 skip_emulated_instruction(vcpu
);
6333 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6335 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6336 return handle_nop(vcpu
);
6339 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6344 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6346 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6347 return handle_nop(vcpu
);
6351 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6352 * We could reuse a single VMCS for all the L2 guests, but we also want the
6353 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6354 * allows keeping them loaded on the processor, and in the future will allow
6355 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6356 * every entry if they never change.
6357 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6358 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6360 * The following functions allocate and free a vmcs02 in this pool.
6363 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6364 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6366 struct vmcs02_list
*item
;
6367 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6368 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6369 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6370 return &item
->vmcs02
;
6373 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6374 /* Recycle the least recently used VMCS. */
6375 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6376 struct vmcs02_list
, list
);
6377 item
->vmptr
= vmx
->nested
.current_vmptr
;
6378 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6379 return &item
->vmcs02
;
6382 /* Create a new VMCS */
6383 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6386 item
->vmcs02
.vmcs
= alloc_vmcs();
6387 if (!item
->vmcs02
.vmcs
) {
6391 loaded_vmcs_init(&item
->vmcs02
);
6392 item
->vmptr
= vmx
->nested
.current_vmptr
;
6393 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6394 vmx
->nested
.vmcs02_num
++;
6395 return &item
->vmcs02
;
6398 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6399 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6401 struct vmcs02_list
*item
;
6402 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6403 if (item
->vmptr
== vmptr
) {
6404 free_loaded_vmcs(&item
->vmcs02
);
6405 list_del(&item
->list
);
6407 vmx
->nested
.vmcs02_num
--;
6413 * Free all VMCSs saved for this vcpu, except the one pointed by
6414 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6415 * must be &vmx->vmcs01.
6417 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6419 struct vmcs02_list
*item
, *n
;
6421 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6422 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6424 * Something will leak if the above WARN triggers. Better than
6427 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6430 free_loaded_vmcs(&item
->vmcs02
);
6431 list_del(&item
->list
);
6433 vmx
->nested
.vmcs02_num
--;
6438 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6439 * set the success or error code of an emulated VMX instruction, as specified
6440 * by Vol 2B, VMX Instruction Reference, "Conventions".
6442 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6444 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6445 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6446 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6449 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6451 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6452 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6453 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6457 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6458 u32 vm_instruction_error
)
6460 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6462 * failValid writes the error number to the current VMCS, which
6463 * can't be done there isn't a current VMCS.
6465 nested_vmx_failInvalid(vcpu
);
6468 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6469 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6470 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6472 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6474 * We don't need to force a shadow sync because
6475 * VM_INSTRUCTION_ERROR is not shadowed
6479 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6481 /* TODO: not to reset guest simply here. */
6482 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6483 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6486 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6488 struct vcpu_vmx
*vmx
=
6489 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6491 vmx
->nested
.preemption_timer_expired
= true;
6492 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6493 kvm_vcpu_kick(&vmx
->vcpu
);
6495 return HRTIMER_NORESTART
;
6499 * Decode the memory-address operand of a vmx instruction, as recorded on an
6500 * exit caused by such an instruction (run by a guest hypervisor).
6501 * On success, returns 0. When the operand is invalid, returns 1 and throws
6504 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6505 unsigned long exit_qualification
,
6506 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6510 struct kvm_segment s
;
6513 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6514 * Execution", on an exit, vmx_instruction_info holds most of the
6515 * addressing components of the operand. Only the displacement part
6516 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6517 * For how an actual address is calculated from all these components,
6518 * refer to Vol. 1, "Operand Addressing".
6520 int scaling
= vmx_instruction_info
& 3;
6521 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6522 bool is_reg
= vmx_instruction_info
& (1u << 10);
6523 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6524 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6525 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6526 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6527 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6530 kvm_queue_exception(vcpu
, UD_VECTOR
);
6534 /* Addr = segment_base + offset */
6535 /* offset = base + [index * scale] + displacement */
6536 off
= exit_qualification
; /* holds the displacement */
6538 off
+= kvm_register_read(vcpu
, base_reg
);
6540 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6541 vmx_get_segment(vcpu
, &s
, seg_reg
);
6542 *ret
= s
.base
+ off
;
6544 if (addr_size
== 1) /* 32 bit */
6547 /* Checks for #GP/#SS exceptions. */
6549 if (is_protmode(vcpu
)) {
6550 /* Protected mode: apply checks for segment validity in the
6552 * - segment type check (#GP(0) may be thrown)
6553 * - usability check (#GP(0)/#SS(0))
6554 * - limit check (#GP(0)/#SS(0))
6557 /* #GP(0) if the destination operand is located in a
6558 * read-only data segment or any code segment.
6560 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6562 /* #GP(0) if the source operand is located in an
6563 * execute-only code segment
6565 exn
= ((s
.type
& 0xa) == 8);
6568 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6571 if (is_long_mode(vcpu
)) {
6572 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6573 * non-canonical form. This is an only check for long mode.
6575 exn
= is_noncanonical_address(*ret
);
6576 } else if (is_protmode(vcpu
)) {
6577 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6579 exn
= (s
.unusable
!= 0);
6580 /* Protected mode: #GP(0)/#SS(0) if the memory
6581 * operand is outside the segment limit.
6583 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6586 kvm_queue_exception_e(vcpu
,
6587 seg_reg
== VCPU_SREG_SS
?
6588 SS_VECTOR
: GP_VECTOR
,
6597 * This function performs the various checks including
6598 * - if it's 4KB aligned
6599 * - No bits beyond the physical address width are set
6600 * - Returns 0 on success or else 1
6601 * (Intel SDM Section 30.3)
6603 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6608 struct x86_exception e
;
6610 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6611 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6613 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6614 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6617 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6618 sizeof(vmptr
), &e
)) {
6619 kvm_inject_page_fault(vcpu
, &e
);
6623 switch (exit_reason
) {
6624 case EXIT_REASON_VMON
:
6627 * The first 4 bytes of VMXON region contain the supported
6628 * VMCS revision identifier
6630 * Note - IA32_VMX_BASIC[48] will never be 1
6631 * for the nested case;
6632 * which replaces physical address width with 32
6635 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6636 nested_vmx_failInvalid(vcpu
);
6637 skip_emulated_instruction(vcpu
);
6641 page
= nested_get_page(vcpu
, vmptr
);
6643 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6644 nested_vmx_failInvalid(vcpu
);
6646 skip_emulated_instruction(vcpu
);
6650 vmx
->nested
.vmxon_ptr
= vmptr
;
6652 case EXIT_REASON_VMCLEAR
:
6653 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6654 nested_vmx_failValid(vcpu
,
6655 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6656 skip_emulated_instruction(vcpu
);
6660 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6661 nested_vmx_failValid(vcpu
,
6662 VMXERR_VMCLEAR_VMXON_POINTER
);
6663 skip_emulated_instruction(vcpu
);
6667 case EXIT_REASON_VMPTRLD
:
6668 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6669 nested_vmx_failValid(vcpu
,
6670 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6671 skip_emulated_instruction(vcpu
);
6675 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6676 nested_vmx_failValid(vcpu
,
6677 VMXERR_VMCLEAR_VMXON_POINTER
);
6678 skip_emulated_instruction(vcpu
);
6683 return 1; /* shouldn't happen */
6692 * Emulate the VMXON instruction.
6693 * Currently, we just remember that VMX is active, and do not save or even
6694 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6695 * do not currently need to store anything in that guest-allocated memory
6696 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6697 * argument is different from the VMXON pointer (which the spec says they do).
6699 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6701 struct kvm_segment cs
;
6702 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6703 struct vmcs
*shadow_vmcs
;
6704 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6705 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6707 /* The Intel VMX Instruction Reference lists a bunch of bits that
6708 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6709 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6710 * Otherwise, we should fail with #UD. We test these now:
6712 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6713 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6714 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6715 kvm_queue_exception(vcpu
, UD_VECTOR
);
6719 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6720 if (is_long_mode(vcpu
) && !cs
.l
) {
6721 kvm_queue_exception(vcpu
, UD_VECTOR
);
6725 if (vmx_get_cpl(vcpu
)) {
6726 kvm_inject_gp(vcpu
, 0);
6730 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6733 if (vmx
->nested
.vmxon
) {
6734 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6735 skip_emulated_instruction(vcpu
);
6739 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6740 != VMXON_NEEDED_FEATURES
) {
6741 kvm_inject_gp(vcpu
, 0);
6745 if (enable_shadow_vmcs
) {
6746 shadow_vmcs
= alloc_vmcs();
6749 /* mark vmcs as shadow */
6750 shadow_vmcs
->revision_id
|= (1u << 31);
6751 /* init shadow vmcs */
6752 vmcs_clear(shadow_vmcs
);
6753 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6756 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6757 vmx
->nested
.vmcs02_num
= 0;
6759 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6761 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6763 vmx
->nested
.vmxon
= true;
6765 skip_emulated_instruction(vcpu
);
6766 nested_vmx_succeed(vcpu
);
6771 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6772 * for running VMX instructions (except VMXON, whose prerequisites are
6773 * slightly different). It also specifies what exception to inject otherwise.
6775 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6777 struct kvm_segment cs
;
6778 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6780 if (!vmx
->nested
.vmxon
) {
6781 kvm_queue_exception(vcpu
, UD_VECTOR
);
6785 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6786 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6787 (is_long_mode(vcpu
) && !cs
.l
)) {
6788 kvm_queue_exception(vcpu
, UD_VECTOR
);
6792 if (vmx_get_cpl(vcpu
)) {
6793 kvm_inject_gp(vcpu
, 0);
6800 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6802 if (vmx
->nested
.current_vmptr
== -1ull)
6805 /* current_vmptr and current_vmcs12 are always set/reset together */
6806 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6809 if (enable_shadow_vmcs
) {
6810 /* copy to memory all shadowed fields in case
6811 they were modified */
6812 copy_shadow_to_vmcs12(vmx
);
6813 vmx
->nested
.sync_shadow_vmcs
= false;
6814 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6815 SECONDARY_EXEC_SHADOW_VMCS
);
6816 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6818 vmx
->nested
.posted_intr_nv
= -1;
6819 kunmap(vmx
->nested
.current_vmcs12_page
);
6820 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6821 vmx
->nested
.current_vmptr
= -1ull;
6822 vmx
->nested
.current_vmcs12
= NULL
;
6826 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6827 * just stops using VMX.
6829 static void free_nested(struct vcpu_vmx
*vmx
)
6831 if (!vmx
->nested
.vmxon
)
6834 vmx
->nested
.vmxon
= false;
6835 free_vpid(vmx
->nested
.vpid02
);
6836 nested_release_vmcs12(vmx
);
6837 if (enable_shadow_vmcs
)
6838 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6839 /* Unpin physical memory we referred to in current vmcs02 */
6840 if (vmx
->nested
.apic_access_page
) {
6841 nested_release_page(vmx
->nested
.apic_access_page
);
6842 vmx
->nested
.apic_access_page
= NULL
;
6844 if (vmx
->nested
.virtual_apic_page
) {
6845 nested_release_page(vmx
->nested
.virtual_apic_page
);
6846 vmx
->nested
.virtual_apic_page
= NULL
;
6848 if (vmx
->nested
.pi_desc_page
) {
6849 kunmap(vmx
->nested
.pi_desc_page
);
6850 nested_release_page(vmx
->nested
.pi_desc_page
);
6851 vmx
->nested
.pi_desc_page
= NULL
;
6852 vmx
->nested
.pi_desc
= NULL
;
6855 nested_free_all_saved_vmcss(vmx
);
6858 /* Emulate the VMXOFF instruction */
6859 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6861 if (!nested_vmx_check_permission(vcpu
))
6863 free_nested(to_vmx(vcpu
));
6864 skip_emulated_instruction(vcpu
);
6865 nested_vmx_succeed(vcpu
);
6869 /* Emulate the VMCLEAR instruction */
6870 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6872 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6874 struct vmcs12
*vmcs12
;
6877 if (!nested_vmx_check_permission(vcpu
))
6880 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6883 if (vmptr
== vmx
->nested
.current_vmptr
)
6884 nested_release_vmcs12(vmx
);
6886 page
= nested_get_page(vcpu
, vmptr
);
6889 * For accurate processor emulation, VMCLEAR beyond available
6890 * physical memory should do nothing at all. However, it is
6891 * possible that a nested vmx bug, not a guest hypervisor bug,
6892 * resulted in this case, so let's shut down before doing any
6895 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6898 vmcs12
= kmap(page
);
6899 vmcs12
->launch_state
= 0;
6901 nested_release_page(page
);
6903 nested_free_vmcs02(vmx
, vmptr
);
6905 skip_emulated_instruction(vcpu
);
6906 nested_vmx_succeed(vcpu
);
6910 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6912 /* Emulate the VMLAUNCH instruction */
6913 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6915 return nested_vmx_run(vcpu
, true);
6918 /* Emulate the VMRESUME instruction */
6919 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6922 return nested_vmx_run(vcpu
, false);
6925 enum vmcs_field_type
{
6926 VMCS_FIELD_TYPE_U16
= 0,
6927 VMCS_FIELD_TYPE_U64
= 1,
6928 VMCS_FIELD_TYPE_U32
= 2,
6929 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6932 static inline int vmcs_field_type(unsigned long field
)
6934 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6935 return VMCS_FIELD_TYPE_U32
;
6936 return (field
>> 13) & 0x3 ;
6939 static inline int vmcs_field_readonly(unsigned long field
)
6941 return (((field
>> 10) & 0x3) == 1);
6945 * Read a vmcs12 field. Since these can have varying lengths and we return
6946 * one type, we chose the biggest type (u64) and zero-extend the return value
6947 * to that size. Note that the caller, handle_vmread, might need to use only
6948 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6949 * 64-bit fields are to be returned).
6951 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6952 unsigned long field
, u64
*ret
)
6954 short offset
= vmcs_field_to_offset(field
);
6960 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6962 switch (vmcs_field_type(field
)) {
6963 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6964 *ret
= *((natural_width
*)p
);
6966 case VMCS_FIELD_TYPE_U16
:
6969 case VMCS_FIELD_TYPE_U32
:
6972 case VMCS_FIELD_TYPE_U64
:
6982 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6983 unsigned long field
, u64 field_value
){
6984 short offset
= vmcs_field_to_offset(field
);
6985 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6989 switch (vmcs_field_type(field
)) {
6990 case VMCS_FIELD_TYPE_U16
:
6991 *(u16
*)p
= field_value
;
6993 case VMCS_FIELD_TYPE_U32
:
6994 *(u32
*)p
= field_value
;
6996 case VMCS_FIELD_TYPE_U64
:
6997 *(u64
*)p
= field_value
;
6999 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7000 *(natural_width
*)p
= field_value
;
7009 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7012 unsigned long field
;
7014 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7015 const unsigned long *fields
= shadow_read_write_fields
;
7016 const int num_fields
= max_shadow_read_write_fields
;
7020 vmcs_load(shadow_vmcs
);
7022 for (i
= 0; i
< num_fields
; i
++) {
7024 switch (vmcs_field_type(field
)) {
7025 case VMCS_FIELD_TYPE_U16
:
7026 field_value
= vmcs_read16(field
);
7028 case VMCS_FIELD_TYPE_U32
:
7029 field_value
= vmcs_read32(field
);
7031 case VMCS_FIELD_TYPE_U64
:
7032 field_value
= vmcs_read64(field
);
7034 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7035 field_value
= vmcs_readl(field
);
7041 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7044 vmcs_clear(shadow_vmcs
);
7045 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7050 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7052 const unsigned long *fields
[] = {
7053 shadow_read_write_fields
,
7054 shadow_read_only_fields
7056 const int max_fields
[] = {
7057 max_shadow_read_write_fields
,
7058 max_shadow_read_only_fields
7061 unsigned long field
;
7062 u64 field_value
= 0;
7063 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7065 vmcs_load(shadow_vmcs
);
7067 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7068 for (i
= 0; i
< max_fields
[q
]; i
++) {
7069 field
= fields
[q
][i
];
7070 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7072 switch (vmcs_field_type(field
)) {
7073 case VMCS_FIELD_TYPE_U16
:
7074 vmcs_write16(field
, (u16
)field_value
);
7076 case VMCS_FIELD_TYPE_U32
:
7077 vmcs_write32(field
, (u32
)field_value
);
7079 case VMCS_FIELD_TYPE_U64
:
7080 vmcs_write64(field
, (u64
)field_value
);
7082 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7083 vmcs_writel(field
, (long)field_value
);
7092 vmcs_clear(shadow_vmcs
);
7093 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7097 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7098 * used before) all generate the same failure when it is missing.
7100 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7102 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7103 if (vmx
->nested
.current_vmptr
== -1ull) {
7104 nested_vmx_failInvalid(vcpu
);
7105 skip_emulated_instruction(vcpu
);
7111 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7113 unsigned long field
;
7115 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7116 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7119 if (!nested_vmx_check_permission(vcpu
) ||
7120 !nested_vmx_check_vmcs12(vcpu
))
7123 /* Decode instruction info and find the field to read */
7124 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7125 /* Read the field, zero-extended to a u64 field_value */
7126 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7127 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7128 skip_emulated_instruction(vcpu
);
7132 * Now copy part of this value to register or memory, as requested.
7133 * Note that the number of bits actually copied is 32 or 64 depending
7134 * on the guest's mode (32 or 64 bit), not on the given field's length.
7136 if (vmx_instruction_info
& (1u << 10)) {
7137 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7140 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7141 vmx_instruction_info
, true, &gva
))
7143 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7144 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7145 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7148 nested_vmx_succeed(vcpu
);
7149 skip_emulated_instruction(vcpu
);
7154 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7156 unsigned long field
;
7158 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7159 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7160 /* The value to write might be 32 or 64 bits, depending on L1's long
7161 * mode, and eventually we need to write that into a field of several
7162 * possible lengths. The code below first zero-extends the value to 64
7163 * bit (field_value), and then copies only the approriate number of
7164 * bits into the vmcs12 field.
7166 u64 field_value
= 0;
7167 struct x86_exception e
;
7169 if (!nested_vmx_check_permission(vcpu
) ||
7170 !nested_vmx_check_vmcs12(vcpu
))
7173 if (vmx_instruction_info
& (1u << 10))
7174 field_value
= kvm_register_readl(vcpu
,
7175 (((vmx_instruction_info
) >> 3) & 0xf));
7177 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7178 vmx_instruction_info
, false, &gva
))
7180 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7181 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7182 kvm_inject_page_fault(vcpu
, &e
);
7188 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7189 if (vmcs_field_readonly(field
)) {
7190 nested_vmx_failValid(vcpu
,
7191 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7192 skip_emulated_instruction(vcpu
);
7196 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7197 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7198 skip_emulated_instruction(vcpu
);
7202 nested_vmx_succeed(vcpu
);
7203 skip_emulated_instruction(vcpu
);
7207 /* Emulate the VMPTRLD instruction */
7208 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7210 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7213 if (!nested_vmx_check_permission(vcpu
))
7216 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7219 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7220 struct vmcs12
*new_vmcs12
;
7222 page
= nested_get_page(vcpu
, vmptr
);
7224 nested_vmx_failInvalid(vcpu
);
7225 skip_emulated_instruction(vcpu
);
7228 new_vmcs12
= kmap(page
);
7229 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7231 nested_release_page_clean(page
);
7232 nested_vmx_failValid(vcpu
,
7233 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7234 skip_emulated_instruction(vcpu
);
7238 nested_release_vmcs12(vmx
);
7239 vmx
->nested
.current_vmptr
= vmptr
;
7240 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7241 vmx
->nested
.current_vmcs12_page
= page
;
7242 if (enable_shadow_vmcs
) {
7243 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7244 SECONDARY_EXEC_SHADOW_VMCS
);
7245 vmcs_write64(VMCS_LINK_POINTER
,
7246 __pa(vmx
->nested
.current_shadow_vmcs
));
7247 vmx
->nested
.sync_shadow_vmcs
= true;
7251 nested_vmx_succeed(vcpu
);
7252 skip_emulated_instruction(vcpu
);
7256 /* Emulate the VMPTRST instruction */
7257 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7259 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7260 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7262 struct x86_exception e
;
7264 if (!nested_vmx_check_permission(vcpu
))
7267 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7268 vmx_instruction_info
, true, &vmcs_gva
))
7270 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7271 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7272 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7274 kvm_inject_page_fault(vcpu
, &e
);
7277 nested_vmx_succeed(vcpu
);
7278 skip_emulated_instruction(vcpu
);
7282 /* Emulate the INVEPT instruction */
7283 static int handle_invept(struct kvm_vcpu
*vcpu
)
7285 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7286 u32 vmx_instruction_info
, types
;
7289 struct x86_exception e
;
7294 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7295 SECONDARY_EXEC_ENABLE_EPT
) ||
7296 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7297 kvm_queue_exception(vcpu
, UD_VECTOR
);
7301 if (!nested_vmx_check_permission(vcpu
))
7304 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7305 kvm_queue_exception(vcpu
, UD_VECTOR
);
7309 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7310 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7312 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7314 if (!(types
& (1UL << type
))) {
7315 nested_vmx_failValid(vcpu
,
7316 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7320 /* According to the Intel VMX instruction reference, the memory
7321 * operand is read even if it isn't needed (e.g., for type==global)
7323 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7324 vmx_instruction_info
, false, &gva
))
7326 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7327 sizeof(operand
), &e
)) {
7328 kvm_inject_page_fault(vcpu
, &e
);
7333 case VMX_EPT_EXTENT_GLOBAL
:
7334 kvm_mmu_sync_roots(vcpu
);
7335 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7336 nested_vmx_succeed(vcpu
);
7339 /* Trap single context invalidation invept calls */
7344 skip_emulated_instruction(vcpu
);
7348 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7350 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7351 u32 vmx_instruction_info
;
7352 unsigned long type
, types
;
7354 struct x86_exception e
;
7357 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7358 SECONDARY_EXEC_ENABLE_VPID
) ||
7359 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7360 kvm_queue_exception(vcpu
, UD_VECTOR
);
7364 if (!nested_vmx_check_permission(vcpu
))
7367 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7368 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7370 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7372 if (!(types
& (1UL << type
))) {
7373 nested_vmx_failValid(vcpu
,
7374 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7378 /* according to the intel vmx instruction reference, the memory
7379 * operand is read even if it isn't needed (e.g., for type==global)
7381 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7382 vmx_instruction_info
, false, &gva
))
7384 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7386 kvm_inject_page_fault(vcpu
, &e
);
7391 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7392 if (get_vmcs12(vcpu
)->virtual_processor_id
== 0) {
7393 nested_vmx_failValid(vcpu
,
7394 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7397 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7398 nested_vmx_succeed(vcpu
);
7401 /* Trap single context invalidation invvpid calls */
7406 skip_emulated_instruction(vcpu
);
7410 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7412 unsigned long exit_qualification
;
7414 trace_kvm_pml_full(vcpu
->vcpu_id
);
7416 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7419 * PML buffer FULL happened while executing iret from NMI,
7420 * "blocked by NMI" bit has to be set before next VM entry.
7422 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7423 cpu_has_virtual_nmis() &&
7424 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7425 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7426 GUEST_INTR_STATE_NMI
);
7429 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7430 * here.., and there's no userspace involvement needed for PML.
7435 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7437 /* we never catch pcommit instruct for L1 guest. */
7443 * The exit handlers return 1 if the exit was handled fully and guest execution
7444 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7445 * to be done to userspace and return 0.
7447 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7448 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7449 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7450 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7451 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7452 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7453 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7454 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7455 [EXIT_REASON_CPUID
] = handle_cpuid
,
7456 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7457 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7458 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7459 [EXIT_REASON_HLT
] = handle_halt
,
7460 [EXIT_REASON_INVD
] = handle_invd
,
7461 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7462 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7463 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7464 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7465 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7466 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7467 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7468 [EXIT_REASON_VMREAD
] = handle_vmread
,
7469 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7470 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7471 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7472 [EXIT_REASON_VMON
] = handle_vmon
,
7473 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7474 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7475 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7476 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7477 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7478 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7479 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7480 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7481 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7482 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7483 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7484 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7485 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7486 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7487 [EXIT_REASON_INVEPT
] = handle_invept
,
7488 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7489 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7490 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7491 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7492 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7495 static const int kvm_vmx_max_exit_handlers
=
7496 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7498 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7499 struct vmcs12
*vmcs12
)
7501 unsigned long exit_qualification
;
7502 gpa_t bitmap
, last_bitmap
;
7507 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7508 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7510 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7512 port
= exit_qualification
>> 16;
7513 size
= (exit_qualification
& 7) + 1;
7515 last_bitmap
= (gpa_t
)-1;
7520 bitmap
= vmcs12
->io_bitmap_a
;
7521 else if (port
< 0x10000)
7522 bitmap
= vmcs12
->io_bitmap_b
;
7525 bitmap
+= (port
& 0x7fff) / 8;
7527 if (last_bitmap
!= bitmap
)
7528 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7530 if (b
& (1 << (port
& 7)))
7535 last_bitmap
= bitmap
;
7542 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7543 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7544 * disinterest in the current event (read or write a specific MSR) by using an
7545 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7547 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7548 struct vmcs12
*vmcs12
, u32 exit_reason
)
7550 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7553 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7557 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7558 * for the four combinations of read/write and low/high MSR numbers.
7559 * First we need to figure out which of the four to use:
7561 bitmap
= vmcs12
->msr_bitmap
;
7562 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7564 if (msr_index
>= 0xc0000000) {
7565 msr_index
-= 0xc0000000;
7569 /* Then read the msr_index'th bit from this bitmap: */
7570 if (msr_index
< 1024*8) {
7572 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7574 return 1 & (b
>> (msr_index
& 7));
7576 return true; /* let L1 handle the wrong parameter */
7580 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7581 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7582 * intercept (via guest_host_mask etc.) the current event.
7584 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7585 struct vmcs12
*vmcs12
)
7587 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7588 int cr
= exit_qualification
& 15;
7589 int reg
= (exit_qualification
>> 8) & 15;
7590 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7592 switch ((exit_qualification
>> 4) & 3) {
7593 case 0: /* mov to cr */
7596 if (vmcs12
->cr0_guest_host_mask
&
7597 (val
^ vmcs12
->cr0_read_shadow
))
7601 if ((vmcs12
->cr3_target_count
>= 1 &&
7602 vmcs12
->cr3_target_value0
== val
) ||
7603 (vmcs12
->cr3_target_count
>= 2 &&
7604 vmcs12
->cr3_target_value1
== val
) ||
7605 (vmcs12
->cr3_target_count
>= 3 &&
7606 vmcs12
->cr3_target_value2
== val
) ||
7607 (vmcs12
->cr3_target_count
>= 4 &&
7608 vmcs12
->cr3_target_value3
== val
))
7610 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7614 if (vmcs12
->cr4_guest_host_mask
&
7615 (vmcs12
->cr4_read_shadow
^ val
))
7619 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7625 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7626 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7629 case 1: /* mov from cr */
7632 if (vmcs12
->cpu_based_vm_exec_control
&
7633 CPU_BASED_CR3_STORE_EXITING
)
7637 if (vmcs12
->cpu_based_vm_exec_control
&
7638 CPU_BASED_CR8_STORE_EXITING
)
7645 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7646 * cr0. Other attempted changes are ignored, with no exit.
7648 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7649 (val
^ vmcs12
->cr0_read_shadow
))
7651 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7652 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7661 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7662 * should handle it ourselves in L0 (and then continue L2). Only call this
7663 * when in is_guest_mode (L2).
7665 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7667 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7668 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7669 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7670 u32 exit_reason
= vmx
->exit_reason
;
7672 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7673 vmcs_readl(EXIT_QUALIFICATION
),
7674 vmx
->idt_vectoring_info
,
7676 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7679 if (vmx
->nested
.nested_run_pending
)
7682 if (unlikely(vmx
->fail
)) {
7683 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7684 vmcs_read32(VM_INSTRUCTION_ERROR
));
7688 switch (exit_reason
) {
7689 case EXIT_REASON_EXCEPTION_NMI
:
7690 if (!is_exception(intr_info
))
7692 else if (is_page_fault(intr_info
))
7694 else if (is_no_device(intr_info
) &&
7695 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7697 return vmcs12
->exception_bitmap
&
7698 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7699 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7701 case EXIT_REASON_TRIPLE_FAULT
:
7703 case EXIT_REASON_PENDING_INTERRUPT
:
7704 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7705 case EXIT_REASON_NMI_WINDOW
:
7706 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7707 case EXIT_REASON_TASK_SWITCH
:
7709 case EXIT_REASON_CPUID
:
7710 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7713 case EXIT_REASON_HLT
:
7714 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7715 case EXIT_REASON_INVD
:
7717 case EXIT_REASON_INVLPG
:
7718 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7719 case EXIT_REASON_RDPMC
:
7720 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7721 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7722 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7723 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7724 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7725 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7726 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7727 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7728 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7730 * VMX instructions trap unconditionally. This allows L1 to
7731 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7734 case EXIT_REASON_CR_ACCESS
:
7735 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7736 case EXIT_REASON_DR_ACCESS
:
7737 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7738 case EXIT_REASON_IO_INSTRUCTION
:
7739 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7740 case EXIT_REASON_MSR_READ
:
7741 case EXIT_REASON_MSR_WRITE
:
7742 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7743 case EXIT_REASON_INVALID_STATE
:
7745 case EXIT_REASON_MWAIT_INSTRUCTION
:
7746 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7747 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7748 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7749 case EXIT_REASON_MONITOR_INSTRUCTION
:
7750 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7751 case EXIT_REASON_PAUSE_INSTRUCTION
:
7752 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7753 nested_cpu_has2(vmcs12
,
7754 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7755 case EXIT_REASON_MCE_DURING_VMENTRY
:
7757 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7758 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7759 case EXIT_REASON_APIC_ACCESS
:
7760 return nested_cpu_has2(vmcs12
,
7761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7762 case EXIT_REASON_APIC_WRITE
:
7763 case EXIT_REASON_EOI_INDUCED
:
7764 /* apic_write and eoi_induced should exit unconditionally. */
7766 case EXIT_REASON_EPT_VIOLATION
:
7768 * L0 always deals with the EPT violation. If nested EPT is
7769 * used, and the nested mmu code discovers that the address is
7770 * missing in the guest EPT table (EPT12), the EPT violation
7771 * will be injected with nested_ept_inject_page_fault()
7774 case EXIT_REASON_EPT_MISCONFIG
:
7776 * L2 never uses directly L1's EPT, but rather L0's own EPT
7777 * table (shadow on EPT) or a merged EPT table that L0 built
7778 * (EPT on EPT). So any problems with the structure of the
7779 * table is L0's fault.
7782 case EXIT_REASON_WBINVD
:
7783 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7784 case EXIT_REASON_XSETBV
:
7786 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7788 * This should never happen, since it is not possible to
7789 * set XSS to a non-zero value---neither in L1 nor in L2.
7790 * If if it were, XSS would have to be checked against
7791 * the XSS exit bitmap in vmcs12.
7793 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7794 case EXIT_REASON_PCOMMIT
:
7795 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7801 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7803 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7804 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7807 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7809 struct page
*pml_pg
;
7811 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7815 vmx
->pml_pg
= pml_pg
;
7817 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7818 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7820 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7825 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7827 ASSERT(vmx
->pml_pg
);
7828 __free_page(vmx
->pml_pg
);
7831 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_ENABLE_PML
);
7834 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7836 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7840 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7842 /* Do nothing if PML buffer is empty */
7843 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7846 /* PML index always points to next available PML buffer entity */
7847 if (pml_idx
>= PML_ENTITY_NUM
)
7852 pml_buf
= page_address(vmx
->pml_pg
);
7853 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7856 gpa
= pml_buf
[pml_idx
];
7857 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7858 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7861 /* reset PML index */
7862 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7866 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7867 * Called before reporting dirty_bitmap to userspace.
7869 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7872 struct kvm_vcpu
*vcpu
;
7874 * We only need to kick vcpu out of guest mode here, as PML buffer
7875 * is flushed at beginning of all VMEXITs, and it's obvious that only
7876 * vcpus running in guest are possible to have unflushed GPAs in PML
7879 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7880 kvm_vcpu_kick(vcpu
);
7883 static void vmx_dump_sel(char *name
, uint32_t sel
)
7885 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7886 name
, vmcs_read32(sel
),
7887 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7888 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7889 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7892 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7894 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7895 name
, vmcs_read32(limit
),
7896 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7899 static void dump_vmcs(void)
7901 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7902 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7903 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7904 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7905 u32 secondary_exec_control
= 0;
7906 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7907 u64 efer
= vmcs_readl(GUEST_IA32_EFER
);
7910 if (cpu_has_secondary_exec_ctrls())
7911 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7913 pr_err("*** Guest State ***\n");
7914 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7915 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7916 vmcs_readl(CR0_GUEST_HOST_MASK
));
7917 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7918 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7919 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7920 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7921 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7923 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7924 vmcs_readl(GUEST_PDPTR0
), vmcs_readl(GUEST_PDPTR1
));
7925 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7926 vmcs_readl(GUEST_PDPTR2
), vmcs_readl(GUEST_PDPTR3
));
7928 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7929 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
7930 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7931 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
7932 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7933 vmcs_readl(GUEST_SYSENTER_ESP
),
7934 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
7935 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
7936 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
7937 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
7938 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
7939 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
7940 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
7941 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
7942 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
7943 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
7944 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
7945 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
7946 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
7947 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7948 efer
, vmcs_readl(GUEST_IA32_PAT
));
7949 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7950 vmcs_readl(GUEST_IA32_DEBUGCTL
),
7951 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
7952 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
7953 pr_err("PerfGlobCtl = 0x%016lx\n",
7954 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL
));
7955 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
7956 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS
));
7957 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7958 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
7959 vmcs_read32(GUEST_ACTIVITY_STATE
));
7960 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
7961 pr_err("InterruptStatus = %04x\n",
7962 vmcs_read16(GUEST_INTR_STATUS
));
7964 pr_err("*** Host State ***\n");
7965 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7966 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
7967 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7968 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
7969 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
7970 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
7971 vmcs_read16(HOST_TR_SELECTOR
));
7972 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7973 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
7974 vmcs_readl(HOST_TR_BASE
));
7975 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7976 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
7977 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7978 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
7979 vmcs_readl(HOST_CR4
));
7980 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7981 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
7982 vmcs_read32(HOST_IA32_SYSENTER_CS
),
7983 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
7984 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
7985 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
7986 vmcs_readl(HOST_IA32_EFER
), vmcs_readl(HOST_IA32_PAT
));
7987 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7988 pr_err("PerfGlobCtl = 0x%016lx\n",
7989 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL
));
7991 pr_err("*** Control State ***\n");
7992 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
7993 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
7994 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
7995 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
7996 vmcs_read32(EXCEPTION_BITMAP
),
7997 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
7998 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
7999 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8000 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8001 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8002 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8003 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8004 vmcs_read32(VM_EXIT_INTR_INFO
),
8005 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8006 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8007 pr_err(" reason=%08x qualification=%016lx\n",
8008 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8009 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8010 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8011 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8012 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET
));
8013 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8014 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8015 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8016 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8017 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8018 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER
));
8019 n
= vmcs_read32(CR3_TARGET_COUNT
);
8020 for (i
= 0; i
+ 1 < n
; i
+= 4)
8021 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8022 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8023 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8025 pr_err("CR3 target%u=%016lx\n",
8026 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8027 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8028 pr_err("PLE Gap=%08x Window=%08x\n",
8029 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8030 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8031 pr_err("Virtual processor ID = 0x%04x\n",
8032 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8036 * The guest has exited. See if we can fix it or if we need userspace
8039 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8041 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8042 u32 exit_reason
= vmx
->exit_reason
;
8043 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8046 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8047 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8048 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8049 * mode as if vcpus is in root mode, the PML buffer must has been
8053 vmx_flush_pml_buffer(vcpu
);
8055 /* If guest state is invalid, start emulating */
8056 if (vmx
->emulation_required
)
8057 return handle_invalid_guest_state(vcpu
);
8059 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8060 nested_vmx_vmexit(vcpu
, exit_reason
,
8061 vmcs_read32(VM_EXIT_INTR_INFO
),
8062 vmcs_readl(EXIT_QUALIFICATION
));
8066 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8068 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8069 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8074 if (unlikely(vmx
->fail
)) {
8075 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8076 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8077 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8083 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8084 * delivery event since it indicates guest is accessing MMIO.
8085 * The vm-exit can be triggered again after return to guest that
8086 * will cause infinite loop.
8088 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8089 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8090 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8091 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8092 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8093 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8094 vcpu
->run
->internal
.ndata
= 2;
8095 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8096 vcpu
->run
->internal
.data
[1] = exit_reason
;
8100 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8101 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8102 get_vmcs12(vcpu
))))) {
8103 if (vmx_interrupt_allowed(vcpu
)) {
8104 vmx
->soft_vnmi_blocked
= 0;
8105 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8106 vcpu
->arch
.nmi_pending
) {
8108 * This CPU don't support us in finding the end of an
8109 * NMI-blocked window if the guest runs with IRQs
8110 * disabled. So we pull the trigger after 1 s of
8111 * futile waiting, but inform the user about this.
8113 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8114 "state on VCPU %d after 1 s timeout\n",
8115 __func__
, vcpu
->vcpu_id
);
8116 vmx
->soft_vnmi_blocked
= 0;
8120 if (exit_reason
< kvm_vmx_max_exit_handlers
8121 && kvm_vmx_exit_handlers
[exit_reason
])
8122 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8124 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8125 kvm_queue_exception(vcpu
, UD_VECTOR
);
8130 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8132 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8134 if (is_guest_mode(vcpu
) &&
8135 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8138 if (irr
== -1 || tpr
< irr
) {
8139 vmcs_write32(TPR_THRESHOLD
, 0);
8143 vmcs_write32(TPR_THRESHOLD
, irr
);
8146 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8148 u32 sec_exec_control
;
8151 * There is not point to enable virtualize x2apic without enable
8154 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8155 !vmx_cpu_uses_apicv(vcpu
))
8158 if (!cpu_need_tpr_shadow(vcpu
))
8161 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8164 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8165 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8167 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8168 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8170 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8172 vmx_set_msr_bitmap(vcpu
);
8175 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8177 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8180 * Currently we do not handle the nested case where L2 has an
8181 * APIC access page of its own; that page is still pinned.
8182 * Hence, we skip the case where the VCPU is in guest mode _and_
8183 * L1 prepared an APIC access page for L2.
8185 * For the case where L1 and L2 share the same APIC access page
8186 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8187 * in the vmcs12), this function will only update either the vmcs01
8188 * or the vmcs02. If the former, the vmcs02 will be updated by
8189 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8190 * the next L2->L1 exit.
8192 if (!is_guest_mode(vcpu
) ||
8193 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8194 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8195 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8198 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
8206 status
= vmcs_read16(GUEST_INTR_STATUS
);
8211 vmcs_write16(GUEST_INTR_STATUS
, status
);
8215 static void vmx_set_rvi(int vector
)
8223 status
= vmcs_read16(GUEST_INTR_STATUS
);
8224 old
= (u8
)status
& 0xff;
8225 if ((u8
)vector
!= old
) {
8227 status
|= (u8
)vector
;
8228 vmcs_write16(GUEST_INTR_STATUS
, status
);
8232 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8234 if (!is_guest_mode(vcpu
)) {
8235 vmx_set_rvi(max_irr
);
8243 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8246 if (nested_exit_on_intr(vcpu
))
8250 * Else, fall back to pre-APICv interrupt injection since L2
8251 * is run without virtual interrupt delivery.
8253 if (!kvm_event_needs_reinjection(vcpu
) &&
8254 vmx_interrupt_allowed(vcpu
)) {
8255 kvm_queue_interrupt(vcpu
, max_irr
, false);
8256 vmx_inject_irq(vcpu
);
8260 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
8262 u64
*eoi_exit_bitmap
= vcpu
->arch
.eoi_exit_bitmap
;
8263 if (!vmx_cpu_uses_apicv(vcpu
))
8266 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8267 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8268 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8269 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8272 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8276 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8277 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8280 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8281 exit_intr_info
= vmx
->exit_intr_info
;
8283 /* Handle machine checks before interrupts are enabled */
8284 if (is_machine_check(exit_intr_info
))
8285 kvm_machine_check();
8287 /* We need to handle NMIs before interrupts are enabled */
8288 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8289 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8290 kvm_before_handle_nmi(&vmx
->vcpu
);
8292 kvm_after_handle_nmi(&vmx
->vcpu
);
8296 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8298 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8301 * If external interrupt exists, IF bit is set in rflags/eflags on the
8302 * interrupt stack frame, and interrupt will be enabled on a return
8303 * from interrupt handler.
8305 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8306 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8307 unsigned int vector
;
8308 unsigned long entry
;
8310 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8311 #ifdef CONFIG_X86_64
8315 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8316 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8317 entry
= gate_offset(*desc
);
8319 #ifdef CONFIG_X86_64
8320 "mov %%" _ASM_SP
", %[sp]\n\t"
8321 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8326 "orl $0x200, (%%" _ASM_SP
")\n\t"
8327 __ASM_SIZE(push
) " $%c[cs]\n\t"
8328 "call *%[entry]\n\t"
8330 #ifdef CONFIG_X86_64
8335 [ss
]"i"(__KERNEL_DS
),
8336 [cs
]"i"(__KERNEL_CS
)
8342 static bool vmx_has_high_real_mode_segbase(void)
8344 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8347 static bool vmx_mpx_supported(void)
8349 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8350 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8353 static bool vmx_xsaves_supported(void)
8355 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8356 SECONDARY_EXEC_XSAVES
;
8359 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8364 bool idtv_info_valid
;
8366 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8368 if (cpu_has_virtual_nmis()) {
8369 if (vmx
->nmi_known_unmasked
)
8372 * Can't use vmx->exit_intr_info since we're not sure what
8373 * the exit reason is.
8375 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8376 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8377 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8379 * SDM 3: 27.7.1.2 (September 2008)
8380 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8381 * a guest IRET fault.
8382 * SDM 3: 23.2.2 (September 2008)
8383 * Bit 12 is undefined in any of the following cases:
8384 * If the VM exit sets the valid bit in the IDT-vectoring
8385 * information field.
8386 * If the VM exit is due to a double fault.
8388 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8389 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8390 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8391 GUEST_INTR_STATE_NMI
);
8393 vmx
->nmi_known_unmasked
=
8394 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8395 & GUEST_INTR_STATE_NMI
);
8396 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8397 vmx
->vnmi_blocked_time
+=
8398 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8401 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8402 u32 idt_vectoring_info
,
8403 int instr_len_field
,
8404 int error_code_field
)
8408 bool idtv_info_valid
;
8410 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8412 vcpu
->arch
.nmi_injected
= false;
8413 kvm_clear_exception_queue(vcpu
);
8414 kvm_clear_interrupt_queue(vcpu
);
8416 if (!idtv_info_valid
)
8419 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8421 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8422 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8425 case INTR_TYPE_NMI_INTR
:
8426 vcpu
->arch
.nmi_injected
= true;
8428 * SDM 3: 27.7.1.2 (September 2008)
8429 * Clear bit "block by NMI" before VM entry if a NMI
8432 vmx_set_nmi_mask(vcpu
, false);
8434 case INTR_TYPE_SOFT_EXCEPTION
:
8435 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8437 case INTR_TYPE_HARD_EXCEPTION
:
8438 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8439 u32 err
= vmcs_read32(error_code_field
);
8440 kvm_requeue_exception_e(vcpu
, vector
, err
);
8442 kvm_requeue_exception(vcpu
, vector
);
8444 case INTR_TYPE_SOFT_INTR
:
8445 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8447 case INTR_TYPE_EXT_INTR
:
8448 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8455 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8457 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8458 VM_EXIT_INSTRUCTION_LEN
,
8459 IDT_VECTORING_ERROR_CODE
);
8462 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8464 __vmx_complete_interrupts(vcpu
,
8465 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8466 VM_ENTRY_INSTRUCTION_LEN
,
8467 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8469 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8472 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8475 struct perf_guest_switch_msr
*msrs
;
8477 msrs
= perf_guest_get_msrs(&nr_msrs
);
8482 for (i
= 0; i
< nr_msrs
; i
++)
8483 if (msrs
[i
].host
== msrs
[i
].guest
)
8484 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8486 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8490 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8492 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8493 unsigned long debugctlmsr
, cr4
;
8495 /* Record the guest's net vcpu time for enforced NMI injections. */
8496 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8497 vmx
->entry_time
= ktime_get();
8499 /* Don't enter VMX if guest state is invalid, let the exit handler
8500 start emulation until we arrive back to a valid state */
8501 if (vmx
->emulation_required
)
8504 if (vmx
->ple_window_dirty
) {
8505 vmx
->ple_window_dirty
= false;
8506 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8509 if (vmx
->nested
.sync_shadow_vmcs
) {
8510 copy_vmcs12_to_shadow(vmx
);
8511 vmx
->nested
.sync_shadow_vmcs
= false;
8514 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8515 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8516 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8517 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8519 cr4
= cr4_read_shadow();
8520 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8521 vmcs_writel(HOST_CR4
, cr4
);
8522 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8525 /* When single-stepping over STI and MOV SS, we must clear the
8526 * corresponding interruptibility bits in the guest state. Otherwise
8527 * vmentry fails as it then expects bit 14 (BS) in pending debug
8528 * exceptions being set, but that's not correct for the guest debugging
8530 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8531 vmx_set_interrupt_shadow(vcpu
, 0);
8533 atomic_switch_perf_msrs(vmx
);
8534 debugctlmsr
= get_debugctlmsr();
8536 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8538 /* Store host registers */
8539 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8540 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8541 "push %%" _ASM_CX
" \n\t"
8542 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8544 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8545 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8547 /* Reload cr2 if changed */
8548 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8549 "mov %%cr2, %%" _ASM_DX
" \n\t"
8550 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8552 "mov %%" _ASM_AX
", %%cr2 \n\t"
8554 /* Check if vmlaunch of vmresume is needed */
8555 "cmpl $0, %c[launched](%0) \n\t"
8556 /* Load guest registers. Don't clobber flags. */
8557 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8558 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8559 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8560 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8561 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8562 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8563 #ifdef CONFIG_X86_64
8564 "mov %c[r8](%0), %%r8 \n\t"
8565 "mov %c[r9](%0), %%r9 \n\t"
8566 "mov %c[r10](%0), %%r10 \n\t"
8567 "mov %c[r11](%0), %%r11 \n\t"
8568 "mov %c[r12](%0), %%r12 \n\t"
8569 "mov %c[r13](%0), %%r13 \n\t"
8570 "mov %c[r14](%0), %%r14 \n\t"
8571 "mov %c[r15](%0), %%r15 \n\t"
8573 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8575 /* Enter guest mode */
8577 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8579 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8581 /* Save guest registers, load host registers, keep flags */
8582 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8584 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8585 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8586 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8587 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8588 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8589 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8590 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8591 #ifdef CONFIG_X86_64
8592 "mov %%r8, %c[r8](%0) \n\t"
8593 "mov %%r9, %c[r9](%0) \n\t"
8594 "mov %%r10, %c[r10](%0) \n\t"
8595 "mov %%r11, %c[r11](%0) \n\t"
8596 "mov %%r12, %c[r12](%0) \n\t"
8597 "mov %%r13, %c[r13](%0) \n\t"
8598 "mov %%r14, %c[r14](%0) \n\t"
8599 "mov %%r15, %c[r15](%0) \n\t"
8601 "mov %%cr2, %%" _ASM_AX
" \n\t"
8602 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8604 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8605 "setbe %c[fail](%0) \n\t"
8606 ".pushsection .rodata \n\t"
8607 ".global vmx_return \n\t"
8608 "vmx_return: " _ASM_PTR
" 2b \n\t"
8610 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8611 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8612 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8613 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8614 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8615 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8616 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8617 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8618 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8619 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8620 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8621 #ifdef CONFIG_X86_64
8622 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8623 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8624 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8625 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8626 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8627 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8628 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8629 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8631 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8632 [wordsize
]"i"(sizeof(ulong
))
8634 #ifdef CONFIG_X86_64
8635 , "rax", "rbx", "rdi", "rsi"
8636 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8638 , "eax", "ebx", "edi", "esi"
8642 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8644 update_debugctlmsr(debugctlmsr
);
8646 #ifndef CONFIG_X86_64
8648 * The sysexit path does not restore ds/es, so we must set them to
8649 * a reasonable value ourselves.
8651 * We can't defer this to vmx_load_host_state() since that function
8652 * may be executed in interrupt context, which saves and restore segments
8653 * around it, nullifying its effect.
8655 loadsegment(ds
, __USER_DS
);
8656 loadsegment(es
, __USER_DS
);
8659 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8660 | (1 << VCPU_EXREG_RFLAGS
)
8661 | (1 << VCPU_EXREG_PDPTR
)
8662 | (1 << VCPU_EXREG_SEGMENTS
)
8663 | (1 << VCPU_EXREG_CR3
));
8664 vcpu
->arch
.regs_dirty
= 0;
8666 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8668 vmx
->loaded_vmcs
->launched
= 1;
8670 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8671 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8674 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8675 * we did not inject a still-pending event to L1 now because of
8676 * nested_run_pending, we need to re-enable this bit.
8678 if (vmx
->nested
.nested_run_pending
)
8679 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8681 vmx
->nested
.nested_run_pending
= 0;
8683 vmx_complete_atomic_exit(vmx
);
8684 vmx_recover_nmi_blocking(vmx
);
8685 vmx_complete_interrupts(vmx
);
8688 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8690 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8693 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8697 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8699 vmx_vcpu_load(vcpu
, cpu
);
8704 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8709 vmx_disable_pml(vmx
);
8710 free_vpid(vmx
->vpid
);
8711 leave_guest_mode(vcpu
);
8712 vmx_load_vmcs01(vcpu
);
8714 free_loaded_vmcs(vmx
->loaded_vmcs
);
8715 kfree(vmx
->guest_msrs
);
8716 kvm_vcpu_uninit(vcpu
);
8717 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8720 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8723 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8727 return ERR_PTR(-ENOMEM
);
8729 vmx
->vpid
= allocate_vpid();
8731 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8735 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8736 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8740 if (!vmx
->guest_msrs
) {
8744 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8745 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8746 if (!vmx
->loaded_vmcs
->vmcs
)
8749 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8750 loaded_vmcs_init(vmx
->loaded_vmcs
);
8755 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8756 vmx
->vcpu
.cpu
= cpu
;
8757 err
= vmx_vcpu_setup(vmx
);
8758 vmx_vcpu_put(&vmx
->vcpu
);
8762 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8763 err
= alloc_apic_access_page(kvm
);
8769 if (!kvm
->arch
.ept_identity_map_addr
)
8770 kvm
->arch
.ept_identity_map_addr
=
8771 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8772 err
= init_rmode_identity_map(kvm
);
8778 nested_vmx_setup_ctls_msrs(vmx
);
8779 vmx
->nested
.vpid02
= allocate_vpid();
8782 vmx
->nested
.posted_intr_nv
= -1;
8783 vmx
->nested
.current_vmptr
= -1ull;
8784 vmx
->nested
.current_vmcs12
= NULL
;
8787 * If PML is turned on, failure on enabling PML just results in failure
8788 * of creating the vcpu, therefore we can simplify PML logic (by
8789 * avoiding dealing with cases, such as enabling PML partially on vcpus
8790 * for the guest, etc.
8793 err
= vmx_enable_pml(vmx
);
8801 free_vpid(vmx
->nested
.vpid02
);
8802 free_loaded_vmcs(vmx
->loaded_vmcs
);
8804 kfree(vmx
->guest_msrs
);
8806 kvm_vcpu_uninit(&vmx
->vcpu
);
8808 free_vpid(vmx
->vpid
);
8809 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8810 return ERR_PTR(err
);
8813 static void __init
vmx_check_processor_compat(void *rtn
)
8815 struct vmcs_config vmcs_conf
;
8818 if (setup_vmcs_config(&vmcs_conf
) < 0)
8820 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8821 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8822 smp_processor_id());
8827 static int get_ept_level(void)
8829 return VMX_EPT_DEFAULT_GAW
+ 1;
8832 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8837 /* For VT-d and EPT combination
8838 * 1. MMIO: always map as UC
8840 * a. VT-d without snooping control feature: can't guarantee the
8841 * result, try to trust guest.
8842 * b. VT-d with snooping control feature: snooping control feature of
8843 * VT-d engine can guarantee the cache correctness. Just set it
8844 * to WB to keep consistent with host. So the same as item 3.
8845 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8846 * consistent with host MTRR
8849 cache
= MTRR_TYPE_UNCACHABLE
;
8853 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8854 ipat
= VMX_EPT_IPAT_BIT
;
8855 cache
= MTRR_TYPE_WRBACK
;
8859 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8860 ipat
= VMX_EPT_IPAT_BIT
;
8861 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8862 cache
= MTRR_TYPE_WRBACK
;
8864 cache
= MTRR_TYPE_UNCACHABLE
;
8868 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8871 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8874 static int vmx_get_lpage_level(void)
8876 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8877 return PT_DIRECTORY_LEVEL
;
8879 /* For shadow and EPT supported 1GB page */
8880 return PT_PDPE_LEVEL
;
8883 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
8886 * These bits in the secondary execution controls field
8887 * are dynamic, the others are mostly based on the hypervisor
8888 * architecture and the guest's CPUID. Do not touch the
8892 SECONDARY_EXEC_SHADOW_VMCS
|
8893 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
8894 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8896 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8898 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8899 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
8902 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8904 struct kvm_cpuid_entry2
*best
;
8905 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8906 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
8908 if (vmx_rdtscp_supported()) {
8909 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
8910 if (!rdtscp_enabled
)
8911 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
8915 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8916 SECONDARY_EXEC_RDTSCP
;
8918 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8919 ~SECONDARY_EXEC_RDTSCP
;
8923 /* Exposing INVPCID only when PCID is exposed */
8924 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8925 if (vmx_invpcid_supported() &&
8926 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
8927 !guest_cpuid_has_pcid(vcpu
))) {
8928 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8931 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8934 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
8936 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
8937 if (guest_cpuid_has_pcommit(vcpu
))
8938 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8939 SECONDARY_EXEC_PCOMMIT
;
8941 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8942 ~SECONDARY_EXEC_PCOMMIT
;
8946 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8948 if (func
== 1 && nested
)
8949 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8952 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8953 struct x86_exception
*fault
)
8955 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8958 if (fault
->error_code
& PFERR_RSVD_MASK
)
8959 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8961 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8962 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8963 vmcs12
->guest_physical_address
= fault
->address
;
8966 /* Callbacks for nested_ept_init_mmu_context: */
8968 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8970 /* return the page table to be shadowed - in our case, EPT12 */
8971 return get_vmcs12(vcpu
)->ept_pointer
;
8974 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8976 WARN_ON(mmu_is_nested(vcpu
));
8977 kvm_init_shadow_ept_mmu(vcpu
,
8978 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8979 VMX_EPT_EXECUTE_ONLY_BIT
);
8980 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8981 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8982 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8984 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8987 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8989 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8992 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8995 bool inequality
, bit
;
8997 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8999 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9000 vmcs12
->page_fault_error_code_match
;
9001 return inequality
^ bit
;
9004 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9005 struct x86_exception
*fault
)
9007 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9009 WARN_ON(!is_guest_mode(vcpu
));
9011 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9012 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9013 vmcs_read32(VM_EXIT_INTR_INFO
),
9014 vmcs_readl(EXIT_QUALIFICATION
));
9016 kvm_inject_page_fault(vcpu
, fault
);
9019 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9020 struct vmcs12
*vmcs12
)
9022 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9023 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9025 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9026 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9027 vmcs12
->apic_access_addr
>> maxphyaddr
)
9031 * Translate L1 physical address to host physical
9032 * address for vmcs02. Keep the page pinned, so this
9033 * physical address remains valid. We keep a reference
9034 * to it so we can release it later.
9036 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9037 nested_release_page(vmx
->nested
.apic_access_page
);
9038 vmx
->nested
.apic_access_page
=
9039 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9042 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9043 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9044 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9047 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9048 nested_release_page(vmx
->nested
.virtual_apic_page
);
9049 vmx
->nested
.virtual_apic_page
=
9050 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9053 * Failing the vm entry is _not_ what the processor does
9054 * but it's basically the only possibility we have.
9055 * We could still enter the guest if CR8 load exits are
9056 * enabled, CR8 store exits are enabled, and virtualize APIC
9057 * access is disabled; in this case the processor would never
9058 * use the TPR shadow and we could simply clear the bit from
9059 * the execution control. But such a configuration is useless,
9060 * so let's keep the code simple.
9062 if (!vmx
->nested
.virtual_apic_page
)
9066 if (nested_cpu_has_posted_intr(vmcs12
)) {
9067 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9068 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9071 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9072 kunmap(vmx
->nested
.pi_desc_page
);
9073 nested_release_page(vmx
->nested
.pi_desc_page
);
9075 vmx
->nested
.pi_desc_page
=
9076 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9077 if (!vmx
->nested
.pi_desc_page
)
9080 vmx
->nested
.pi_desc
=
9081 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9082 if (!vmx
->nested
.pi_desc
) {
9083 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9086 vmx
->nested
.pi_desc
=
9087 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9088 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9095 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9097 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9100 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9103 /* Make sure short timeouts reliably trigger an immediate vmexit.
9104 * hrtimer_start does not guarantee this. */
9105 if (preemption_timeout
<= 1) {
9106 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9110 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9111 preemption_timeout
*= 1000000;
9112 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9113 hrtimer_start(&vmx
->nested
.preemption_timer
,
9114 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9117 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9118 struct vmcs12
*vmcs12
)
9123 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9126 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9130 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9132 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9133 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9140 * Merge L0's and L1's MSR bitmap, return false to indicate that
9141 * we do not use the hardware.
9143 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9144 struct vmcs12
*vmcs12
)
9148 unsigned long *msr_bitmap
;
9150 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9153 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9158 msr_bitmap
= (unsigned long *)kmap(page
);
9160 nested_release_page_clean(page
);
9165 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9166 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9167 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9168 nested_vmx_disable_intercept_for_msr(
9170 vmx_msr_bitmap_nested
,
9172 /* TPR is allowed */
9173 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9174 vmx_msr_bitmap_nested
,
9175 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9176 MSR_TYPE_R
| MSR_TYPE_W
);
9177 if (nested_cpu_has_vid(vmcs12
)) {
9178 /* EOI and self-IPI are allowed */
9179 nested_vmx_disable_intercept_for_msr(
9181 vmx_msr_bitmap_nested
,
9182 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9184 nested_vmx_disable_intercept_for_msr(
9186 vmx_msr_bitmap_nested
,
9187 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9192 * Enable reading intercept of all the x2apic
9193 * MSRs. We should not rely on vmcs12 to do any
9194 * optimizations here, it may have been modified
9197 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9198 __vmx_enable_intercept_for_msr(
9199 vmx_msr_bitmap_nested
,
9203 __vmx_enable_intercept_for_msr(
9204 vmx_msr_bitmap_nested
,
9205 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9207 __vmx_enable_intercept_for_msr(
9208 vmx_msr_bitmap_nested
,
9209 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9211 __vmx_enable_intercept_for_msr(
9212 vmx_msr_bitmap_nested
,
9213 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9217 nested_release_page_clean(page
);
9222 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9223 struct vmcs12
*vmcs12
)
9225 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9226 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9227 !nested_cpu_has_vid(vmcs12
) &&
9228 !nested_cpu_has_posted_intr(vmcs12
))
9232 * If virtualize x2apic mode is enabled,
9233 * virtualize apic access must be disabled.
9235 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9236 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9240 * If virtual interrupt delivery is enabled,
9241 * we must exit on external interrupts.
9243 if (nested_cpu_has_vid(vmcs12
) &&
9244 !nested_exit_on_intr(vcpu
))
9248 * bits 15:8 should be zero in posted_intr_nv,
9249 * the descriptor address has been already checked
9250 * in nested_get_vmcs12_pages.
9252 if (nested_cpu_has_posted_intr(vmcs12
) &&
9253 (!nested_cpu_has_vid(vmcs12
) ||
9254 !nested_exit_intr_ack_set(vcpu
) ||
9255 vmcs12
->posted_intr_nv
& 0xff00))
9258 /* tpr shadow is needed by all apicv features. */
9259 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9265 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9266 unsigned long count_field
,
9267 unsigned long addr_field
)
9272 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9273 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9279 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9280 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9281 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9282 pr_warn_ratelimited(
9283 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9284 addr_field
, maxphyaddr
, count
, addr
);
9290 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9291 struct vmcs12
*vmcs12
)
9293 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9294 vmcs12
->vm_exit_msr_store_count
== 0 &&
9295 vmcs12
->vm_entry_msr_load_count
== 0)
9296 return 0; /* Fast path */
9297 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9298 VM_EXIT_MSR_LOAD_ADDR
) ||
9299 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9300 VM_EXIT_MSR_STORE_ADDR
) ||
9301 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9302 VM_ENTRY_MSR_LOAD_ADDR
))
9307 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9308 struct vmx_msr_entry
*e
)
9310 /* x2APIC MSR accesses are not allowed */
9311 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9313 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9314 e
->index
== MSR_IA32_UCODE_REV
)
9316 if (e
->reserved
!= 0)
9321 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9322 struct vmx_msr_entry
*e
)
9324 if (e
->index
== MSR_FS_BASE
||
9325 e
->index
== MSR_GS_BASE
||
9326 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9327 nested_vmx_msr_check_common(vcpu
, e
))
9332 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9333 struct vmx_msr_entry
*e
)
9335 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9336 nested_vmx_msr_check_common(vcpu
, e
))
9342 * Load guest's/host's msr at nested entry/exit.
9343 * return 0 for success, entry index for failure.
9345 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9348 struct vmx_msr_entry e
;
9349 struct msr_data msr
;
9351 msr
.host_initiated
= false;
9352 for (i
= 0; i
< count
; i
++) {
9353 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9355 pr_warn_ratelimited(
9356 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9357 __func__
, i
, gpa
+ i
* sizeof(e
));
9360 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9361 pr_warn_ratelimited(
9362 "%s check failed (%u, 0x%x, 0x%x)\n",
9363 __func__
, i
, e
.index
, e
.reserved
);
9366 msr
.index
= e
.index
;
9368 if (kvm_set_msr(vcpu
, &msr
)) {
9369 pr_warn_ratelimited(
9370 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9371 __func__
, i
, e
.index
, e
.value
);
9380 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9383 struct vmx_msr_entry e
;
9385 for (i
= 0; i
< count
; i
++) {
9386 struct msr_data msr_info
;
9387 if (kvm_vcpu_read_guest(vcpu
,
9388 gpa
+ i
* sizeof(e
),
9389 &e
, 2 * sizeof(u32
))) {
9390 pr_warn_ratelimited(
9391 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9392 __func__
, i
, gpa
+ i
* sizeof(e
));
9395 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9396 pr_warn_ratelimited(
9397 "%s check failed (%u, 0x%x, 0x%x)\n",
9398 __func__
, i
, e
.index
, e
.reserved
);
9401 msr_info
.host_initiated
= false;
9402 msr_info
.index
= e
.index
;
9403 if (kvm_get_msr(vcpu
, &msr_info
)) {
9404 pr_warn_ratelimited(
9405 "%s cannot read MSR (%u, 0x%x)\n",
9406 __func__
, i
, e
.index
);
9409 if (kvm_vcpu_write_guest(vcpu
,
9410 gpa
+ i
* sizeof(e
) +
9411 offsetof(struct vmx_msr_entry
, value
),
9412 &msr_info
.data
, sizeof(msr_info
.data
))) {
9413 pr_warn_ratelimited(
9414 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9415 __func__
, i
, e
.index
, msr_info
.data
);
9423 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9424 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9425 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9426 * guest in a way that will both be appropriate to L1's requests, and our
9427 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9428 * function also has additional necessary side-effects, like setting various
9429 * vcpu->arch fields.
9431 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9433 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9436 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9437 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9438 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9439 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9440 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9441 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9442 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9443 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9444 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9445 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9446 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9447 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9448 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9449 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9450 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9451 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9452 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9453 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9454 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9455 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9456 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9457 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9458 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9459 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9460 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9461 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9462 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9463 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9464 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9465 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9466 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9467 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9468 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9469 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9470 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9471 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9473 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9474 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9475 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9477 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9478 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9480 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9481 vmcs12
->vm_entry_intr_info_field
);
9482 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9483 vmcs12
->vm_entry_exception_error_code
);
9484 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9485 vmcs12
->vm_entry_instruction_len
);
9486 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9487 vmcs12
->guest_interruptibility_info
);
9488 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9489 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9490 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9491 vmcs12
->guest_pending_dbg_exceptions
);
9492 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9493 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9495 if (nested_cpu_has_xsaves(vmcs12
))
9496 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9497 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9499 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9500 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9501 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9503 if (nested_cpu_has_posted_intr(vmcs12
)) {
9505 * Note that we use L0's vector here and in
9506 * vmx_deliver_nested_posted_interrupt.
9508 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9509 vmx
->nested
.pi_pending
= false;
9510 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9511 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9512 page_to_phys(vmx
->nested
.pi_desc_page
) +
9513 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9516 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9518 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9520 vmx
->nested
.preemption_timer_expired
= false;
9521 if (nested_cpu_has_preemption_timer(vmcs12
))
9522 vmx_start_preemption_timer(vcpu
);
9525 * Whether page-faults are trapped is determined by a combination of
9526 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9527 * If enable_ept, L0 doesn't care about page faults and we should
9528 * set all of these to L1's desires. However, if !enable_ept, L0 does
9529 * care about (at least some) page faults, and because it is not easy
9530 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9531 * to exit on each and every L2 page fault. This is done by setting
9532 * MASK=MATCH=0 and (see below) EB.PF=1.
9533 * Note that below we don't need special code to set EB.PF beyond the
9534 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9535 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9536 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9538 * A problem with this approach (when !enable_ept) is that L1 may be
9539 * injected with more page faults than it asked for. This could have
9540 * caused problems, but in practice existing hypervisors don't care.
9541 * To fix this, we will need to emulate the PFEC checking (on the L1
9542 * page tables), using walk_addr(), when injecting PFs to L1.
9544 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9545 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9546 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9547 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9549 if (cpu_has_secondary_exec_ctrls()) {
9550 exec_control
= vmx_secondary_exec_control(vmx
);
9552 /* Take the following fields only from vmcs12 */
9553 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9554 SECONDARY_EXEC_RDTSCP
|
9555 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9556 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9557 SECONDARY_EXEC_PCOMMIT
);
9558 if (nested_cpu_has(vmcs12
,
9559 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9560 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9562 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9564 * If translation failed, no matter: This feature asks
9565 * to exit when accessing the given address, and if it
9566 * can never be accessed, this feature won't do
9569 if (!vmx
->nested
.apic_access_page
)
9571 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9573 vmcs_write64(APIC_ACCESS_ADDR
,
9574 page_to_phys(vmx
->nested
.apic_access_page
));
9575 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9576 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9578 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9579 kvm_vcpu_reload_apic_access_page(vcpu
);
9582 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9583 vmcs_write64(EOI_EXIT_BITMAP0
,
9584 vmcs12
->eoi_exit_bitmap0
);
9585 vmcs_write64(EOI_EXIT_BITMAP1
,
9586 vmcs12
->eoi_exit_bitmap1
);
9587 vmcs_write64(EOI_EXIT_BITMAP2
,
9588 vmcs12
->eoi_exit_bitmap2
);
9589 vmcs_write64(EOI_EXIT_BITMAP3
,
9590 vmcs12
->eoi_exit_bitmap3
);
9591 vmcs_write16(GUEST_INTR_STATUS
,
9592 vmcs12
->guest_intr_status
);
9595 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9600 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9601 * Some constant fields are set here by vmx_set_constant_host_state().
9602 * Other fields are different per CPU, and will be set later when
9603 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9605 vmx_set_constant_host_state(vmx
);
9608 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9609 * entry, but only if the current (host) sp changed from the value
9610 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9611 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9612 * here we just force the write to happen on entry.
9616 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9617 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9618 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9619 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9620 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9622 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9623 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9624 page_to_phys(vmx
->nested
.virtual_apic_page
));
9625 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9628 if (cpu_has_vmx_msr_bitmap() &&
9629 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9630 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9631 /* MSR_BITMAP will be set by following vmx_set_efer. */
9633 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9636 * Merging of IO bitmap not currently supported.
9637 * Rather, exit every time.
9639 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9640 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9642 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9644 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9645 * bitwise-or of what L1 wants to trap for L2, and what we want to
9646 * trap. Note that CR0.TS also needs updating - we do this later.
9648 update_exception_bitmap(vcpu
);
9649 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9650 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9652 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9653 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9654 * bits are further modified by vmx_set_efer() below.
9656 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9658 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9659 * emulated by vmx_set_efer(), below.
9661 vm_entry_controls_init(vmx
,
9662 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9663 ~VM_ENTRY_IA32E_MODE
) |
9664 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9666 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9667 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9668 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9669 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9670 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9673 set_cr4_guest_host_mask(vmx
);
9675 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9676 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9678 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9679 vmcs_write64(TSC_OFFSET
,
9680 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9682 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9686 * There is no direct mapping between vpid02 and vpid12, the
9687 * vpid02 is per-vCPU for L0 and reused while the value of
9688 * vpid12 is changed w/ one invvpid during nested vmentry.
9689 * The vpid12 is allocated by L1 for L2, so it will not
9690 * influence global bitmap(for vpid01 and vpid02 allocation)
9691 * even if spawn a lot of nested vCPUs.
9693 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9694 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9695 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9696 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9697 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9700 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9701 vmx_flush_tlb(vcpu
);
9706 if (nested_cpu_has_ept(vmcs12
)) {
9707 kvm_mmu_unload(vcpu
);
9708 nested_ept_init_mmu_context(vcpu
);
9711 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9712 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9713 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9714 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9716 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9717 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9718 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9721 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9722 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9723 * The CR0_READ_SHADOW is what L2 should have expected to read given
9724 * the specifications by L1; It's not enough to take
9725 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9726 * have more bits than L1 expected.
9728 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9729 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9731 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9732 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9734 /* shadow page tables on either EPT or shadow page tables */
9735 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9736 kvm_mmu_reset_context(vcpu
);
9739 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9742 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9745 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9746 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9747 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9748 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9751 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9752 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9756 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9757 * for running an L2 nested guest.
9759 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9761 struct vmcs12
*vmcs12
;
9762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9764 struct loaded_vmcs
*vmcs02
;
9768 if (!nested_vmx_check_permission(vcpu
) ||
9769 !nested_vmx_check_vmcs12(vcpu
))
9772 skip_emulated_instruction(vcpu
);
9773 vmcs12
= get_vmcs12(vcpu
);
9775 if (enable_shadow_vmcs
)
9776 copy_shadow_to_vmcs12(vmx
);
9779 * The nested entry process starts with enforcing various prerequisites
9780 * on vmcs12 as required by the Intel SDM, and act appropriately when
9781 * they fail: As the SDM explains, some conditions should cause the
9782 * instruction to fail, while others will cause the instruction to seem
9783 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9784 * To speed up the normal (success) code path, we should avoid checking
9785 * for misconfigurations which will anyway be caught by the processor
9786 * when using the merged vmcs02.
9788 if (vmcs12
->launch_state
== launch
) {
9789 nested_vmx_failValid(vcpu
,
9790 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9791 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9795 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9796 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9797 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9801 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9802 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9806 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9807 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9811 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9812 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9816 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9817 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9821 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9822 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9823 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9824 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9825 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9826 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9827 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9828 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9829 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9830 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9831 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9832 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9833 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9834 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9835 vmx
->nested
.nested_vmx_entry_ctls_high
))
9837 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9841 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9842 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9843 nested_vmx_failValid(vcpu
,
9844 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9848 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9849 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9850 nested_vmx_entry_failure(vcpu
, vmcs12
,
9851 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9854 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9855 nested_vmx_entry_failure(vcpu
, vmcs12
,
9856 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9861 * If the load IA32_EFER VM-entry control is 1, the following checks
9862 * are performed on the field for the IA32_EFER MSR:
9863 * - Bits reserved in the IA32_EFER MSR must be 0.
9864 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9865 * the IA-32e mode guest VM-exit control. It must also be identical
9866 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9869 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9870 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9871 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9872 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9873 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9874 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9875 nested_vmx_entry_failure(vcpu
, vmcs12
,
9876 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9882 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9883 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9884 * the values of the LMA and LME bits in the field must each be that of
9885 * the host address-space size VM-exit control.
9887 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9888 ia32e
= (vmcs12
->vm_exit_controls
&
9889 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9890 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9891 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9892 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9893 nested_vmx_entry_failure(vcpu
, vmcs12
,
9894 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9900 * We're finally done with prerequisite checking, and can start with
9904 vmcs02
= nested_get_current_vmcs02(vmx
);
9908 enter_guest_mode(vcpu
);
9910 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9912 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9913 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9916 vmx
->loaded_vmcs
= vmcs02
;
9918 vmx_vcpu_load(vcpu
, cpu
);
9922 vmx_segment_cache_clear(vmx
);
9924 prepare_vmcs02(vcpu
, vmcs12
);
9926 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9927 vmcs12
->vm_entry_msr_load_addr
,
9928 vmcs12
->vm_entry_msr_load_count
);
9929 if (msr_entry_idx
) {
9930 leave_guest_mode(vcpu
);
9931 vmx_load_vmcs01(vcpu
);
9932 nested_vmx_entry_failure(vcpu
, vmcs12
,
9933 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9937 vmcs12
->launch_state
= 1;
9939 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9940 return kvm_vcpu_halt(vcpu
);
9942 vmx
->nested
.nested_run_pending
= 1;
9945 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9946 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9947 * returned as far as L1 is concerned. It will only return (and set
9948 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9954 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9955 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9956 * This function returns the new value we should put in vmcs12.guest_cr0.
9957 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9958 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9959 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9960 * didn't trap the bit, because if L1 did, so would L0).
9961 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9962 * been modified by L2, and L1 knows it. So just leave the old value of
9963 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9964 * isn't relevant, because if L0 traps this bit it can set it to anything.
9965 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9966 * changed these bits, and therefore they need to be updated, but L0
9967 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9968 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9970 static inline unsigned long
9971 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9974 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9975 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9976 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9977 vcpu
->arch
.cr0_guest_owned_bits
));
9980 static inline unsigned long
9981 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9984 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9985 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9986 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9987 vcpu
->arch
.cr4_guest_owned_bits
));
9990 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9991 struct vmcs12
*vmcs12
)
9996 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9997 nr
= vcpu
->arch
.exception
.nr
;
9998 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10000 if (kvm_exception_is_soft(nr
)) {
10001 vmcs12
->vm_exit_instruction_len
=
10002 vcpu
->arch
.event_exit_inst_len
;
10003 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10005 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10007 if (vcpu
->arch
.exception
.has_error_code
) {
10008 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10009 vmcs12
->idt_vectoring_error_code
=
10010 vcpu
->arch
.exception
.error_code
;
10013 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10014 } else if (vcpu
->arch
.nmi_injected
) {
10015 vmcs12
->idt_vectoring_info_field
=
10016 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10017 } else if (vcpu
->arch
.interrupt
.pending
) {
10018 nr
= vcpu
->arch
.interrupt
.nr
;
10019 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10021 if (vcpu
->arch
.interrupt
.soft
) {
10022 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10023 vmcs12
->vm_entry_instruction_len
=
10024 vcpu
->arch
.event_exit_inst_len
;
10026 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10028 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10032 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10034 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10036 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10037 vmx
->nested
.preemption_timer_expired
) {
10038 if (vmx
->nested
.nested_run_pending
)
10040 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10044 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10045 if (vmx
->nested
.nested_run_pending
||
10046 vcpu
->arch
.interrupt
.pending
)
10048 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10049 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10050 INTR_INFO_VALID_MASK
, 0);
10052 * The NMI-triggered VM exit counts as injection:
10053 * clear this one and block further NMIs.
10055 vcpu
->arch
.nmi_pending
= 0;
10056 vmx_set_nmi_mask(vcpu
, true);
10060 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10061 nested_exit_on_intr(vcpu
)) {
10062 if (vmx
->nested
.nested_run_pending
)
10064 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10068 return vmx_complete_nested_posted_interrupt(vcpu
);
10071 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10073 ktime_t remaining
=
10074 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10077 if (ktime_to_ns(remaining
) <= 0)
10080 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10081 do_div(value
, 1000000);
10082 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10086 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10087 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10088 * and this function updates it to reflect the changes to the guest state while
10089 * L2 was running (and perhaps made some exits which were handled directly by L0
10090 * without going back to L1), and to reflect the exit reason.
10091 * Note that we do not have to copy here all VMCS fields, just those that
10092 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10093 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10094 * which already writes to vmcs12 directly.
10096 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10097 u32 exit_reason
, u32 exit_intr_info
,
10098 unsigned long exit_qualification
)
10100 /* update guest state fields: */
10101 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10102 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10104 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10105 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10106 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10108 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10109 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10110 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10111 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10112 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10113 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10114 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10115 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10116 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10117 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10118 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10119 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10120 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10121 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10122 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10123 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10124 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10125 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10126 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10127 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10128 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10129 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10130 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10131 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10132 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10133 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10134 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10135 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10136 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10137 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10138 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10139 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10140 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10141 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10142 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10143 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10145 vmcs12
->guest_interruptibility_info
=
10146 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10147 vmcs12
->guest_pending_dbg_exceptions
=
10148 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10149 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10150 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10152 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10154 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10155 if (vmcs12
->vm_exit_controls
&
10156 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10157 vmcs12
->vmx_preemption_timer_value
=
10158 vmx_get_preemption_timer_value(vcpu
);
10159 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10163 * In some cases (usually, nested EPT), L2 is allowed to change its
10164 * own CR3 without exiting. If it has changed it, we must keep it.
10165 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10166 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10168 * Additionally, restore L2's PDPTR to vmcs12.
10171 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
10172 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10173 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10174 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10175 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10178 if (nested_cpu_has_vid(vmcs12
))
10179 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10181 vmcs12
->vm_entry_controls
=
10182 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10183 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10185 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10186 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10187 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10190 /* TODO: These cannot have changed unless we have MSR bitmaps and
10191 * the relevant bit asks not to trap the change */
10192 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10193 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10194 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10195 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10196 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10197 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10198 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10199 if (vmx_mpx_supported())
10200 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10201 if (nested_cpu_has_xsaves(vmcs12
))
10202 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10204 /* update exit information fields: */
10206 vmcs12
->vm_exit_reason
= exit_reason
;
10207 vmcs12
->exit_qualification
= exit_qualification
;
10209 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10210 if ((vmcs12
->vm_exit_intr_info
&
10211 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10212 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10213 vmcs12
->vm_exit_intr_error_code
=
10214 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10215 vmcs12
->idt_vectoring_info_field
= 0;
10216 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10217 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10219 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10220 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10221 * instead of reading the real value. */
10222 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10225 * Transfer the event that L0 or L1 may wanted to inject into
10226 * L2 to IDT_VECTORING_INFO_FIELD.
10228 vmcs12_save_pending_event(vcpu
, vmcs12
);
10232 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10233 * preserved above and would only end up incorrectly in L1.
10235 vcpu
->arch
.nmi_injected
= false;
10236 kvm_clear_exception_queue(vcpu
);
10237 kvm_clear_interrupt_queue(vcpu
);
10241 * A part of what we need to when the nested L2 guest exits and we want to
10242 * run its L1 parent, is to reset L1's guest state to the host state specified
10244 * This function is to be called not only on normal nested exit, but also on
10245 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10246 * Failures During or After Loading Guest State").
10247 * This function should be called when the active VMCS is L1's (vmcs01).
10249 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10250 struct vmcs12
*vmcs12
)
10252 struct kvm_segment seg
;
10254 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10255 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10256 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10257 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10259 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10260 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10262 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10263 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10264 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10266 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10267 * actually changed, because it depends on the current state of
10268 * fpu_active (which may have changed).
10269 * Note that vmx_set_cr0 refers to efer set above.
10271 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10273 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10274 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10275 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10277 update_exception_bitmap(vcpu
);
10278 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10279 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10282 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10283 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10285 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10286 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10288 nested_ept_uninit_mmu_context(vcpu
);
10290 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10291 kvm_mmu_reset_context(vcpu
);
10294 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10298 * Trivially support vpid by letting L2s share their parent
10299 * L1's vpid. TODO: move to a more elaborate solution, giving
10300 * each L2 its own vpid and exposing the vpid feature to L1.
10302 vmx_flush_tlb(vcpu
);
10306 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10307 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10308 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10309 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10310 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10312 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10313 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10314 vmcs_write64(GUEST_BNDCFGS
, 0);
10316 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10317 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10318 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10320 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10321 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10322 vmcs12
->host_ia32_perf_global_ctrl
);
10324 /* Set L1 segment info according to Intel SDM
10325 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10326 seg
= (struct kvm_segment
) {
10328 .limit
= 0xFFFFFFFF,
10329 .selector
= vmcs12
->host_cs_selector
,
10335 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10339 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10340 seg
= (struct kvm_segment
) {
10342 .limit
= 0xFFFFFFFF,
10349 seg
.selector
= vmcs12
->host_ds_selector
;
10350 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10351 seg
.selector
= vmcs12
->host_es_selector
;
10352 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10353 seg
.selector
= vmcs12
->host_ss_selector
;
10354 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10355 seg
.selector
= vmcs12
->host_fs_selector
;
10356 seg
.base
= vmcs12
->host_fs_base
;
10357 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10358 seg
.selector
= vmcs12
->host_gs_selector
;
10359 seg
.base
= vmcs12
->host_gs_base
;
10360 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10361 seg
= (struct kvm_segment
) {
10362 .base
= vmcs12
->host_tr_base
,
10364 .selector
= vmcs12
->host_tr_selector
,
10368 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10370 kvm_set_dr(vcpu
, 7, 0x400);
10371 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10373 if (cpu_has_vmx_msr_bitmap())
10374 vmx_set_msr_bitmap(vcpu
);
10376 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10377 vmcs12
->vm_exit_msr_load_count
))
10378 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10382 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10383 * and modify vmcs12 to make it see what it would expect to see there if
10384 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10386 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10387 u32 exit_intr_info
,
10388 unsigned long exit_qualification
)
10390 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10391 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10393 /* trying to cancel vmlaunch/vmresume is a bug */
10394 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10396 leave_guest_mode(vcpu
);
10397 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10398 exit_qualification
);
10400 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10401 vmcs12
->vm_exit_msr_store_count
))
10402 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10404 vmx_load_vmcs01(vcpu
);
10406 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10407 && nested_exit_intr_ack_set(vcpu
)) {
10408 int irq
= kvm_cpu_get_interrupt(vcpu
);
10410 vmcs12
->vm_exit_intr_info
= irq
|
10411 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10414 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10415 vmcs12
->exit_qualification
,
10416 vmcs12
->idt_vectoring_info_field
,
10417 vmcs12
->vm_exit_intr_info
,
10418 vmcs12
->vm_exit_intr_error_code
,
10421 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10422 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10423 vmx_segment_cache_clear(vmx
);
10425 /* if no vmcs02 cache requested, remove the one we used */
10426 if (VMCS02_POOL_SIZE
== 0)
10427 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10429 load_vmcs12_host_state(vcpu
, vmcs12
);
10431 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10432 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10434 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10437 /* Unpin physical memory we referred to in vmcs02 */
10438 if (vmx
->nested
.apic_access_page
) {
10439 nested_release_page(vmx
->nested
.apic_access_page
);
10440 vmx
->nested
.apic_access_page
= NULL
;
10442 if (vmx
->nested
.virtual_apic_page
) {
10443 nested_release_page(vmx
->nested
.virtual_apic_page
);
10444 vmx
->nested
.virtual_apic_page
= NULL
;
10446 if (vmx
->nested
.pi_desc_page
) {
10447 kunmap(vmx
->nested
.pi_desc_page
);
10448 nested_release_page(vmx
->nested
.pi_desc_page
);
10449 vmx
->nested
.pi_desc_page
= NULL
;
10450 vmx
->nested
.pi_desc
= NULL
;
10454 * We are now running in L2, mmu_notifier will force to reload the
10455 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10457 kvm_vcpu_reload_apic_access_page(vcpu
);
10460 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10461 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10462 * success or failure flag accordingly.
10464 if (unlikely(vmx
->fail
)) {
10466 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10468 nested_vmx_succeed(vcpu
);
10469 if (enable_shadow_vmcs
)
10470 vmx
->nested
.sync_shadow_vmcs
= true;
10472 /* in case we halted in L2 */
10473 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10477 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10479 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10481 if (is_guest_mode(vcpu
))
10482 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10483 free_nested(to_vmx(vcpu
));
10487 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10488 * 23.7 "VM-entry failures during or after loading guest state" (this also
10489 * lists the acceptable exit-reason and exit-qualification parameters).
10490 * It should only be called before L2 actually succeeded to run, and when
10491 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10493 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10494 struct vmcs12
*vmcs12
,
10495 u32 reason
, unsigned long qualification
)
10497 load_vmcs12_host_state(vcpu
, vmcs12
);
10498 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10499 vmcs12
->exit_qualification
= qualification
;
10500 nested_vmx_succeed(vcpu
);
10501 if (enable_shadow_vmcs
)
10502 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10505 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10506 struct x86_instruction_info
*info
,
10507 enum x86_intercept_stage stage
)
10509 return X86EMUL_CONTINUE
;
10512 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10515 shrink_ple_window(vcpu
);
10518 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10519 struct kvm_memory_slot
*slot
)
10521 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10522 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10525 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10526 struct kvm_memory_slot
*slot
)
10528 kvm_mmu_slot_set_dirty(kvm
, slot
);
10531 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10533 kvm_flush_pml_buffers(kvm
);
10536 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10537 struct kvm_memory_slot
*memslot
,
10538 gfn_t offset
, unsigned long mask
)
10540 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10544 * This routine does the following things for vCPU which is going
10545 * to be blocked if VT-d PI is enabled.
10546 * - Store the vCPU to the wakeup list, so when interrupts happen
10547 * we can find the right vCPU to wake up.
10548 * - Change the Posted-interrupt descriptor as below:
10549 * 'NDST' <-- vcpu->pre_pcpu
10550 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10551 * - If 'ON' is set during this process, which means at least one
10552 * interrupt is posted for this vCPU, we cannot block it, in
10553 * this case, return 1, otherwise, return 0.
10556 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10558 unsigned long flags
;
10560 struct pi_desc old
, new;
10561 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10563 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10564 !irq_remapping_cap(IRQ_POSTING_CAP
))
10567 vcpu
->pre_pcpu
= vcpu
->cpu
;
10568 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10569 vcpu
->pre_pcpu
), flags
);
10570 list_add_tail(&vcpu
->blocked_vcpu_list
,
10571 &per_cpu(blocked_vcpu_on_cpu
,
10573 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10574 vcpu
->pre_pcpu
), flags
);
10577 old
.control
= new.control
= pi_desc
->control
;
10580 * We should not block the vCPU if
10581 * an interrupt is posted for it.
10583 if (pi_test_on(pi_desc
) == 1) {
10584 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10585 vcpu
->pre_pcpu
), flags
);
10586 list_del(&vcpu
->blocked_vcpu_list
);
10587 spin_unlock_irqrestore(
10588 &per_cpu(blocked_vcpu_on_cpu_lock
,
10589 vcpu
->pre_pcpu
), flags
);
10590 vcpu
->pre_pcpu
= -1;
10595 WARN((pi_desc
->sn
== 1),
10596 "Warning: SN field of posted-interrupts "
10597 "is set before blocking\n");
10600 * Since vCPU can be preempted during this process,
10601 * vcpu->cpu could be different with pre_pcpu, we
10602 * need to set pre_pcpu as the destination of wakeup
10603 * notification event, then we can find the right vCPU
10604 * to wakeup in wakeup handler if interrupts happen
10605 * when the vCPU is in blocked state.
10607 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10609 if (x2apic_enabled())
10612 new.ndst
= (dest
<< 8) & 0xFF00;
10614 /* set 'NV' to 'wakeup vector' */
10615 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10616 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10617 new.control
) != old
.control
);
10622 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10624 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10625 struct pi_desc old
, new;
10627 unsigned long flags
;
10629 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10630 !irq_remapping_cap(IRQ_POSTING_CAP
))
10634 old
.control
= new.control
= pi_desc
->control
;
10636 dest
= cpu_physical_id(vcpu
->cpu
);
10638 if (x2apic_enabled())
10641 new.ndst
= (dest
<< 8) & 0xFF00;
10643 /* Allow posting non-urgent interrupts */
10646 /* set 'NV' to 'notification vector' */
10647 new.nv
= POSTED_INTR_VECTOR
;
10648 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10649 new.control
) != old
.control
);
10651 if(vcpu
->pre_pcpu
!= -1) {
10653 &per_cpu(blocked_vcpu_on_cpu_lock
,
10654 vcpu
->pre_pcpu
), flags
);
10655 list_del(&vcpu
->blocked_vcpu_list
);
10656 spin_unlock_irqrestore(
10657 &per_cpu(blocked_vcpu_on_cpu_lock
,
10658 vcpu
->pre_pcpu
), flags
);
10659 vcpu
->pre_pcpu
= -1;
10664 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10667 * @host_irq: host irq of the interrupt
10668 * @guest_irq: gsi of the interrupt
10669 * @set: set or unset PI
10670 * returns 0 on success, < 0 on failure
10672 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10673 uint32_t guest_irq
, bool set
)
10675 struct kvm_kernel_irq_routing_entry
*e
;
10676 struct kvm_irq_routing_table
*irq_rt
;
10677 struct kvm_lapic_irq irq
;
10678 struct kvm_vcpu
*vcpu
;
10679 struct vcpu_data vcpu_info
;
10680 int idx
, ret
= -EINVAL
;
10682 if (!kvm_arch_has_assigned_device(kvm
) ||
10683 !irq_remapping_cap(IRQ_POSTING_CAP
))
10686 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10687 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10688 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10690 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10691 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10694 * VT-d PI cannot support posting multicast/broadcast
10695 * interrupts to a vCPU, we still use interrupt remapping
10696 * for these kind of interrupts.
10698 * For lowest-priority interrupts, we only support
10699 * those with single CPU as the destination, e.g. user
10700 * configures the interrupts via /proc/irq or uses
10701 * irqbalance to make the interrupts single-CPU.
10703 * We will support full lowest-priority interrupt later.
10706 kvm_set_msi_irq(e
, &irq
);
10707 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
))
10710 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10711 vcpu_info
.vector
= irq
.vector
;
10713 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, e
->gsi
,
10714 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10717 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10719 /* suppress notification event before unposting */
10720 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10721 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10722 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10726 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10734 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10738 static struct kvm_x86_ops vmx_x86_ops
= {
10739 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10740 .disabled_by_bios
= vmx_disabled_by_bios
,
10741 .hardware_setup
= hardware_setup
,
10742 .hardware_unsetup
= hardware_unsetup
,
10743 .check_processor_compatibility
= vmx_check_processor_compat
,
10744 .hardware_enable
= hardware_enable
,
10745 .hardware_disable
= hardware_disable
,
10746 .cpu_has_accelerated_tpr
= report_flexpriority
,
10747 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10749 .vcpu_create
= vmx_create_vcpu
,
10750 .vcpu_free
= vmx_free_vcpu
,
10751 .vcpu_reset
= vmx_vcpu_reset
,
10753 .prepare_guest_switch
= vmx_save_host_state
,
10754 .vcpu_load
= vmx_vcpu_load
,
10755 .vcpu_put
= vmx_vcpu_put
,
10757 .update_db_bp_intercept
= update_exception_bitmap
,
10758 .get_msr
= vmx_get_msr
,
10759 .set_msr
= vmx_set_msr
,
10760 .get_segment_base
= vmx_get_segment_base
,
10761 .get_segment
= vmx_get_segment
,
10762 .set_segment
= vmx_set_segment
,
10763 .get_cpl
= vmx_get_cpl
,
10764 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10765 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10766 .decache_cr3
= vmx_decache_cr3
,
10767 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10768 .set_cr0
= vmx_set_cr0
,
10769 .set_cr3
= vmx_set_cr3
,
10770 .set_cr4
= vmx_set_cr4
,
10771 .set_efer
= vmx_set_efer
,
10772 .get_idt
= vmx_get_idt
,
10773 .set_idt
= vmx_set_idt
,
10774 .get_gdt
= vmx_get_gdt
,
10775 .set_gdt
= vmx_set_gdt
,
10776 .get_dr6
= vmx_get_dr6
,
10777 .set_dr6
= vmx_set_dr6
,
10778 .set_dr7
= vmx_set_dr7
,
10779 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10780 .cache_reg
= vmx_cache_reg
,
10781 .get_rflags
= vmx_get_rflags
,
10782 .set_rflags
= vmx_set_rflags
,
10783 .fpu_activate
= vmx_fpu_activate
,
10784 .fpu_deactivate
= vmx_fpu_deactivate
,
10786 .tlb_flush
= vmx_flush_tlb
,
10788 .run
= vmx_vcpu_run
,
10789 .handle_exit
= vmx_handle_exit
,
10790 .skip_emulated_instruction
= skip_emulated_instruction
,
10791 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10792 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10793 .patch_hypercall
= vmx_patch_hypercall
,
10794 .set_irq
= vmx_inject_irq
,
10795 .set_nmi
= vmx_inject_nmi
,
10796 .queue_exception
= vmx_queue_exception
,
10797 .cancel_injection
= vmx_cancel_injection
,
10798 .interrupt_allowed
= vmx_interrupt_allowed
,
10799 .nmi_allowed
= vmx_nmi_allowed
,
10800 .get_nmi_mask
= vmx_get_nmi_mask
,
10801 .set_nmi_mask
= vmx_set_nmi_mask
,
10802 .enable_nmi_window
= enable_nmi_window
,
10803 .enable_irq_window
= enable_irq_window
,
10804 .update_cr8_intercept
= update_cr8_intercept
,
10805 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10806 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10807 .cpu_uses_apicv
= vmx_cpu_uses_apicv
,
10808 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10809 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10810 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10811 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10812 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10814 .set_tss_addr
= vmx_set_tss_addr
,
10815 .get_tdp_level
= get_ept_level
,
10816 .get_mt_mask
= vmx_get_mt_mask
,
10818 .get_exit_info
= vmx_get_exit_info
,
10820 .get_lpage_level
= vmx_get_lpage_level
,
10822 .cpuid_update
= vmx_cpuid_update
,
10824 .rdtscp_supported
= vmx_rdtscp_supported
,
10825 .invpcid_supported
= vmx_invpcid_supported
,
10827 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10829 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10831 .set_tsc_khz
= vmx_set_tsc_khz
,
10832 .read_tsc_offset
= vmx_read_tsc_offset
,
10833 .write_tsc_offset
= vmx_write_tsc_offset
,
10834 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10835 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10836 .read_l1_tsc
= vmx_read_l1_tsc
,
10838 .set_tdp_cr3
= vmx_set_cr3
,
10840 .check_intercept
= vmx_check_intercept
,
10841 .handle_external_intr
= vmx_handle_external_intr
,
10842 .mpx_supported
= vmx_mpx_supported
,
10843 .xsaves_supported
= vmx_xsaves_supported
,
10845 .check_nested_events
= vmx_check_nested_events
,
10847 .sched_in
= vmx_sched_in
,
10849 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10850 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10851 .flush_log_dirty
= vmx_flush_log_dirty
,
10852 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10854 .pre_block
= vmx_pre_block
,
10855 .post_block
= vmx_post_block
,
10857 .pmu_ops
= &intel_pmu_ops
,
10859 .update_pi_irte
= vmx_update_pi_irte
,
10862 static int __init
vmx_init(void)
10864 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10865 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10869 #ifdef CONFIG_KEXEC_CORE
10870 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10871 crash_vmclear_local_loaded_vmcss
);
10877 static void __exit
vmx_exit(void)
10879 #ifdef CONFIG_KEXEC_CORE
10880 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10887 module_init(vmx_init
)
10888 module_exit(vmx_exit
)