2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include <linux/nospec.h>
38 #include "kvm_cache_regs.h"
46 #include <asm/virtext.h>
48 #include <asm/fpu/internal.h>
49 #include <asm/perf_event.h>
50 #include <asm/debugreg.h>
51 #include <asm/kexec.h>
53 #include <asm/irq_remapping.h>
54 #include <asm/mmu_context.h>
55 #include <asm/spec-ctrl.h>
56 #include <asm/mshyperv.h>
60 #include "vmx_evmcs.h"
62 #define __ex(x) __kvm_handle_fault_on_reboot(x)
63 #define __ex_clear(x, reg) \
64 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
66 MODULE_AUTHOR("Qumranet");
67 MODULE_LICENSE("GPL");
69 static const struct x86_cpu_id vmx_cpu_id
[] = {
70 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
73 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
75 static bool __read_mostly enable_vpid
= 1;
76 module_param_named(vpid
, enable_vpid
, bool, 0444);
78 static bool __read_mostly enable_vnmi
= 1;
79 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
81 static bool __read_mostly flexpriority_enabled
= 1;
82 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
84 static bool __read_mostly enable_ept
= 1;
85 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
87 static bool __read_mostly enable_unrestricted_guest
= 1;
88 module_param_named(unrestricted_guest
,
89 enable_unrestricted_guest
, bool, S_IRUGO
);
91 static bool __read_mostly enable_ept_ad_bits
= 1;
92 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
94 static bool __read_mostly emulate_invalid_guest_state
= true;
95 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
97 static bool __read_mostly fasteoi
= 1;
98 module_param(fasteoi
, bool, S_IRUGO
);
100 static bool __read_mostly enable_apicv
= 1;
101 module_param(enable_apicv
, bool, S_IRUGO
);
103 static bool __read_mostly enable_shadow_vmcs
= 1;
104 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
106 * If nested=1, nested virtualization is supported, i.e., guests may use
107 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
108 * use VMX instructions.
110 static bool __read_mostly nested
= 0;
111 module_param(nested
, bool, S_IRUGO
);
113 static u64 __read_mostly host_xss
;
115 static bool __read_mostly enable_pml
= 1;
116 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
120 #define MSR_TYPE_RW 3
122 #define MSR_BITMAP_MODE_X2APIC 1
123 #define MSR_BITMAP_MODE_X2APIC_APICV 2
124 #define MSR_BITMAP_MODE_LM 4
126 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
128 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
129 static int __read_mostly cpu_preemption_timer_multi
;
130 static bool __read_mostly enable_preemption_timer
= 1;
132 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
135 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
136 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
137 #define KVM_VM_CR0_ALWAYS_ON \
138 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
139 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
140 #define KVM_CR4_GUEST_OWNED_BITS \
141 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
142 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
144 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
145 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
146 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
148 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
150 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
153 * Hyper-V requires all of these, so mark them as supported even though
154 * they are just treated the same as all-context.
156 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
157 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
158 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
159 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
160 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
163 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
164 * ple_gap: upper bound on the amount of time between two successive
165 * executions of PAUSE in a loop. Also indicate if ple enabled.
166 * According to test, this time is usually smaller than 128 cycles.
167 * ple_window: upper bound on the amount of time a guest is allowed to execute
168 * in a PAUSE loop. Tests indicate that most spinlocks are held for
169 * less than 2^12 cycles
170 * Time is measured based on a counter that runs at the same rate as the TSC,
171 * refer SDM volume 3b section 21.6.13 & 22.1.3.
173 static unsigned int ple_gap
= KVM_DEFAULT_PLE_GAP
;
175 static unsigned int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
176 module_param(ple_window
, uint
, 0444);
178 /* Default doubles per-vcpu window every exit. */
179 static unsigned int ple_window_grow
= KVM_DEFAULT_PLE_WINDOW_GROW
;
180 module_param(ple_window_grow
, uint
, 0444);
182 /* Default resets per-vcpu window every exit to ple_window. */
183 static unsigned int ple_window_shrink
= KVM_DEFAULT_PLE_WINDOW_SHRINK
;
184 module_param(ple_window_shrink
, uint
, 0444);
186 /* Default is to compute the maximum so we can never overflow. */
187 static unsigned int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
188 module_param(ple_window_max
, uint
, 0444);
190 extern const ulong vmx_return
;
192 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush
);
193 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond
);
194 static DEFINE_MUTEX(vmx_l1d_flush_mutex
);
196 /* Storage for pre module init parameter parsing */
197 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param
= VMENTER_L1D_FLUSH_AUTO
;
199 static const struct {
202 } vmentry_l1d_param
[] = {
203 [VMENTER_L1D_FLUSH_AUTO
] = {"auto", true},
204 [VMENTER_L1D_FLUSH_NEVER
] = {"never", true},
205 [VMENTER_L1D_FLUSH_COND
] = {"cond", true},
206 [VMENTER_L1D_FLUSH_ALWAYS
] = {"always", true},
207 [VMENTER_L1D_FLUSH_EPT_DISABLED
] = {"EPT disabled", false},
208 [VMENTER_L1D_FLUSH_NOT_REQUIRED
] = {"not required", false},
211 #define L1D_CACHE_ORDER 4
212 static void *vmx_l1d_flush_pages
;
214 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf
)
220 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_EPT_DISABLED
;
224 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES
)) {
227 rdmsrl(MSR_IA32_ARCH_CAPABILITIES
, msr
);
228 if (msr
& ARCH_CAP_SKIP_VMENTRY_L1DFLUSH
) {
229 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_NOT_REQUIRED
;
234 /* If set to auto use the default l1tf mitigation method */
235 if (l1tf
== VMENTER_L1D_FLUSH_AUTO
) {
236 switch (l1tf_mitigation
) {
237 case L1TF_MITIGATION_OFF
:
238 l1tf
= VMENTER_L1D_FLUSH_NEVER
;
240 case L1TF_MITIGATION_FLUSH_NOWARN
:
241 case L1TF_MITIGATION_FLUSH
:
242 case L1TF_MITIGATION_FLUSH_NOSMT
:
243 l1tf
= VMENTER_L1D_FLUSH_COND
;
245 case L1TF_MITIGATION_FULL
:
246 case L1TF_MITIGATION_FULL_FORCE
:
247 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
250 } else if (l1tf_mitigation
== L1TF_MITIGATION_FULL_FORCE
) {
251 l1tf
= VMENTER_L1D_FLUSH_ALWAYS
;
254 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
&& !vmx_l1d_flush_pages
&&
255 !boot_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
256 page
= alloc_pages(GFP_KERNEL
, L1D_CACHE_ORDER
);
259 vmx_l1d_flush_pages
= page_address(page
);
262 * Initialize each page with a different pattern in
263 * order to protect against KSM in the nested
264 * virtualization case.
266 for (i
= 0; i
< 1u << L1D_CACHE_ORDER
; ++i
) {
267 memset(vmx_l1d_flush_pages
+ i
* PAGE_SIZE
, i
+ 1,
272 l1tf_vmx_mitigation
= l1tf
;
274 if (l1tf
!= VMENTER_L1D_FLUSH_NEVER
)
275 static_branch_enable(&vmx_l1d_should_flush
);
277 static_branch_disable(&vmx_l1d_should_flush
);
279 if (l1tf
== VMENTER_L1D_FLUSH_COND
)
280 static_branch_enable(&vmx_l1d_flush_cond
);
282 static_branch_disable(&vmx_l1d_flush_cond
);
286 static int vmentry_l1d_flush_parse(const char *s
)
291 for (i
= 0; i
< ARRAY_SIZE(vmentry_l1d_param
); i
++) {
292 if (vmentry_l1d_param
[i
].for_parse
&&
293 sysfs_streq(s
, vmentry_l1d_param
[i
].option
))
300 static int vmentry_l1d_flush_set(const char *s
, const struct kernel_param
*kp
)
304 l1tf
= vmentry_l1d_flush_parse(s
);
308 if (!boot_cpu_has(X86_BUG_L1TF
))
312 * Has vmx_init() run already? If not then this is the pre init
313 * parameter parsing. In that case just store the value and let
314 * vmx_init() do the proper setup after enable_ept has been
317 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_AUTO
) {
318 vmentry_l1d_flush_param
= l1tf
;
322 mutex_lock(&vmx_l1d_flush_mutex
);
323 ret
= vmx_setup_l1d_flush(l1tf
);
324 mutex_unlock(&vmx_l1d_flush_mutex
);
328 static int vmentry_l1d_flush_get(char *s
, const struct kernel_param
*kp
)
330 if (WARN_ON_ONCE(l1tf_vmx_mitigation
>= ARRAY_SIZE(vmentry_l1d_param
)))
331 return sprintf(s
, "???\n");
333 return sprintf(s
, "%s\n", vmentry_l1d_param
[l1tf_vmx_mitigation
].option
);
336 static const struct kernel_param_ops vmentry_l1d_flush_ops
= {
337 .set
= vmentry_l1d_flush_set
,
338 .get
= vmentry_l1d_flush_get
,
340 module_param_cb(vmentry_l1d_flush
, &vmentry_l1d_flush_ops
, NULL
, 0644);
342 enum ept_pointers_status
{
343 EPT_POINTERS_CHECK
= 0,
344 EPT_POINTERS_MATCH
= 1,
345 EPT_POINTERS_MISMATCH
= 2
351 unsigned int tss_addr
;
352 bool ept_identity_pagetable_done
;
353 gpa_t ept_identity_map_addr
;
355 enum ept_pointers_status ept_pointers_match
;
356 spinlock_t ept_pointer_lock
;
359 #define NR_AUTOLOAD_MSRS 8
373 * vmcs_host_state tracks registers that are loaded from the VMCS on VMEXIT
374 * and whose values change infrequently, but are not constant. I.e. this is
375 * used as a write-through cache of the corresponding VMCS fields.
377 struct vmcs_host_state
{
378 unsigned long cr3
; /* May not match real cr3 */
379 unsigned long cr4
; /* May not match real cr4 */
380 unsigned long gs_base
;
381 unsigned long fs_base
;
383 u16 fs_sel
, gs_sel
, ldt_sel
;
390 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
391 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
392 * loaded on this CPU (so we can clear them if the CPU goes down).
396 struct vmcs
*shadow_vmcs
;
399 bool nmi_known_unmasked
;
401 /* Support for vnmi-less CPUs */
402 int soft_vnmi_blocked
;
404 s64 vnmi_blocked_time
;
405 unsigned long *msr_bitmap
;
406 struct list_head loaded_vmcss_on_cpu_link
;
407 struct vmcs_host_state host_state
;
410 struct shared_msr_entry
{
417 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
418 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
419 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
420 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
421 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
422 * More than one of these structures may exist, if L1 runs multiple L2 guests.
423 * nested_vmx_run() will use the data here to build the vmcs02: a VMCS for the
424 * underlying hardware which will be used to run L2.
425 * This structure is packed to ensure that its layout is identical across
426 * machines (necessary for live migration).
428 * IMPORTANT: Changing the layout of existing fields in this structure
429 * will break save/restore compatibility with older kvm releases. When
430 * adding new fields, either use space in the reserved padding* arrays
431 * or add the new fields to the end of the structure.
433 typedef u64 natural_width
;
434 struct __packed vmcs12
{
435 /* According to the Intel spec, a VMCS region must start with the
436 * following two fields. Then follow implementation-specific data.
441 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
442 u32 padding
[7]; /* room for future expansion */
447 u64 vm_exit_msr_store_addr
;
448 u64 vm_exit_msr_load_addr
;
449 u64 vm_entry_msr_load_addr
;
451 u64 virtual_apic_page_addr
;
452 u64 apic_access_addr
;
453 u64 posted_intr_desc_addr
;
455 u64 eoi_exit_bitmap0
;
456 u64 eoi_exit_bitmap1
;
457 u64 eoi_exit_bitmap2
;
458 u64 eoi_exit_bitmap3
;
460 u64 guest_physical_address
;
461 u64 vmcs_link_pointer
;
462 u64 guest_ia32_debugctl
;
465 u64 guest_ia32_perf_global_ctrl
;
473 u64 host_ia32_perf_global_ctrl
;
476 u64 vm_function_control
;
477 u64 eptp_list_address
;
479 u64 padding64
[3]; /* room for future expansion */
481 * To allow migration of L1 (complete with its L2 guests) between
482 * machines of different natural widths (32 or 64 bit), we cannot have
483 * unsigned long fields with no explict size. We use u64 (aliased
484 * natural_width) instead. Luckily, x86 is little-endian.
486 natural_width cr0_guest_host_mask
;
487 natural_width cr4_guest_host_mask
;
488 natural_width cr0_read_shadow
;
489 natural_width cr4_read_shadow
;
490 natural_width cr3_target_value0
;
491 natural_width cr3_target_value1
;
492 natural_width cr3_target_value2
;
493 natural_width cr3_target_value3
;
494 natural_width exit_qualification
;
495 natural_width guest_linear_address
;
496 natural_width guest_cr0
;
497 natural_width guest_cr3
;
498 natural_width guest_cr4
;
499 natural_width guest_es_base
;
500 natural_width guest_cs_base
;
501 natural_width guest_ss_base
;
502 natural_width guest_ds_base
;
503 natural_width guest_fs_base
;
504 natural_width guest_gs_base
;
505 natural_width guest_ldtr_base
;
506 natural_width guest_tr_base
;
507 natural_width guest_gdtr_base
;
508 natural_width guest_idtr_base
;
509 natural_width guest_dr7
;
510 natural_width guest_rsp
;
511 natural_width guest_rip
;
512 natural_width guest_rflags
;
513 natural_width guest_pending_dbg_exceptions
;
514 natural_width guest_sysenter_esp
;
515 natural_width guest_sysenter_eip
;
516 natural_width host_cr0
;
517 natural_width host_cr3
;
518 natural_width host_cr4
;
519 natural_width host_fs_base
;
520 natural_width host_gs_base
;
521 natural_width host_tr_base
;
522 natural_width host_gdtr_base
;
523 natural_width host_idtr_base
;
524 natural_width host_ia32_sysenter_esp
;
525 natural_width host_ia32_sysenter_eip
;
526 natural_width host_rsp
;
527 natural_width host_rip
;
528 natural_width paddingl
[8]; /* room for future expansion */
529 u32 pin_based_vm_exec_control
;
530 u32 cpu_based_vm_exec_control
;
531 u32 exception_bitmap
;
532 u32 page_fault_error_code_mask
;
533 u32 page_fault_error_code_match
;
534 u32 cr3_target_count
;
535 u32 vm_exit_controls
;
536 u32 vm_exit_msr_store_count
;
537 u32 vm_exit_msr_load_count
;
538 u32 vm_entry_controls
;
539 u32 vm_entry_msr_load_count
;
540 u32 vm_entry_intr_info_field
;
541 u32 vm_entry_exception_error_code
;
542 u32 vm_entry_instruction_len
;
544 u32 secondary_vm_exec_control
;
545 u32 vm_instruction_error
;
547 u32 vm_exit_intr_info
;
548 u32 vm_exit_intr_error_code
;
549 u32 idt_vectoring_info_field
;
550 u32 idt_vectoring_error_code
;
551 u32 vm_exit_instruction_len
;
552 u32 vmx_instruction_info
;
559 u32 guest_ldtr_limit
;
561 u32 guest_gdtr_limit
;
562 u32 guest_idtr_limit
;
563 u32 guest_es_ar_bytes
;
564 u32 guest_cs_ar_bytes
;
565 u32 guest_ss_ar_bytes
;
566 u32 guest_ds_ar_bytes
;
567 u32 guest_fs_ar_bytes
;
568 u32 guest_gs_ar_bytes
;
569 u32 guest_ldtr_ar_bytes
;
570 u32 guest_tr_ar_bytes
;
571 u32 guest_interruptibility_info
;
572 u32 guest_activity_state
;
573 u32 guest_sysenter_cs
;
574 u32 host_ia32_sysenter_cs
;
575 u32 vmx_preemption_timer_value
;
576 u32 padding32
[7]; /* room for future expansion */
577 u16 virtual_processor_id
;
579 u16 guest_es_selector
;
580 u16 guest_cs_selector
;
581 u16 guest_ss_selector
;
582 u16 guest_ds_selector
;
583 u16 guest_fs_selector
;
584 u16 guest_gs_selector
;
585 u16 guest_ldtr_selector
;
586 u16 guest_tr_selector
;
587 u16 guest_intr_status
;
588 u16 host_es_selector
;
589 u16 host_cs_selector
;
590 u16 host_ss_selector
;
591 u16 host_ds_selector
;
592 u16 host_fs_selector
;
593 u16 host_gs_selector
;
594 u16 host_tr_selector
;
599 * For save/restore compatibility, the vmcs12 field offsets must not change.
601 #define CHECK_OFFSET(field, loc) \
602 BUILD_BUG_ON_MSG(offsetof(struct vmcs12, field) != (loc), \
603 "Offset of " #field " in struct vmcs12 has changed.")
605 static inline void vmx_check_vmcs12_offsets(void) {
606 CHECK_OFFSET(hdr
, 0);
607 CHECK_OFFSET(abort
, 4);
608 CHECK_OFFSET(launch_state
, 8);
609 CHECK_OFFSET(io_bitmap_a
, 40);
610 CHECK_OFFSET(io_bitmap_b
, 48);
611 CHECK_OFFSET(msr_bitmap
, 56);
612 CHECK_OFFSET(vm_exit_msr_store_addr
, 64);
613 CHECK_OFFSET(vm_exit_msr_load_addr
, 72);
614 CHECK_OFFSET(vm_entry_msr_load_addr
, 80);
615 CHECK_OFFSET(tsc_offset
, 88);
616 CHECK_OFFSET(virtual_apic_page_addr
, 96);
617 CHECK_OFFSET(apic_access_addr
, 104);
618 CHECK_OFFSET(posted_intr_desc_addr
, 112);
619 CHECK_OFFSET(ept_pointer
, 120);
620 CHECK_OFFSET(eoi_exit_bitmap0
, 128);
621 CHECK_OFFSET(eoi_exit_bitmap1
, 136);
622 CHECK_OFFSET(eoi_exit_bitmap2
, 144);
623 CHECK_OFFSET(eoi_exit_bitmap3
, 152);
624 CHECK_OFFSET(xss_exit_bitmap
, 160);
625 CHECK_OFFSET(guest_physical_address
, 168);
626 CHECK_OFFSET(vmcs_link_pointer
, 176);
627 CHECK_OFFSET(guest_ia32_debugctl
, 184);
628 CHECK_OFFSET(guest_ia32_pat
, 192);
629 CHECK_OFFSET(guest_ia32_efer
, 200);
630 CHECK_OFFSET(guest_ia32_perf_global_ctrl
, 208);
631 CHECK_OFFSET(guest_pdptr0
, 216);
632 CHECK_OFFSET(guest_pdptr1
, 224);
633 CHECK_OFFSET(guest_pdptr2
, 232);
634 CHECK_OFFSET(guest_pdptr3
, 240);
635 CHECK_OFFSET(guest_bndcfgs
, 248);
636 CHECK_OFFSET(host_ia32_pat
, 256);
637 CHECK_OFFSET(host_ia32_efer
, 264);
638 CHECK_OFFSET(host_ia32_perf_global_ctrl
, 272);
639 CHECK_OFFSET(vmread_bitmap
, 280);
640 CHECK_OFFSET(vmwrite_bitmap
, 288);
641 CHECK_OFFSET(vm_function_control
, 296);
642 CHECK_OFFSET(eptp_list_address
, 304);
643 CHECK_OFFSET(pml_address
, 312);
644 CHECK_OFFSET(cr0_guest_host_mask
, 344);
645 CHECK_OFFSET(cr4_guest_host_mask
, 352);
646 CHECK_OFFSET(cr0_read_shadow
, 360);
647 CHECK_OFFSET(cr4_read_shadow
, 368);
648 CHECK_OFFSET(cr3_target_value0
, 376);
649 CHECK_OFFSET(cr3_target_value1
, 384);
650 CHECK_OFFSET(cr3_target_value2
, 392);
651 CHECK_OFFSET(cr3_target_value3
, 400);
652 CHECK_OFFSET(exit_qualification
, 408);
653 CHECK_OFFSET(guest_linear_address
, 416);
654 CHECK_OFFSET(guest_cr0
, 424);
655 CHECK_OFFSET(guest_cr3
, 432);
656 CHECK_OFFSET(guest_cr4
, 440);
657 CHECK_OFFSET(guest_es_base
, 448);
658 CHECK_OFFSET(guest_cs_base
, 456);
659 CHECK_OFFSET(guest_ss_base
, 464);
660 CHECK_OFFSET(guest_ds_base
, 472);
661 CHECK_OFFSET(guest_fs_base
, 480);
662 CHECK_OFFSET(guest_gs_base
, 488);
663 CHECK_OFFSET(guest_ldtr_base
, 496);
664 CHECK_OFFSET(guest_tr_base
, 504);
665 CHECK_OFFSET(guest_gdtr_base
, 512);
666 CHECK_OFFSET(guest_idtr_base
, 520);
667 CHECK_OFFSET(guest_dr7
, 528);
668 CHECK_OFFSET(guest_rsp
, 536);
669 CHECK_OFFSET(guest_rip
, 544);
670 CHECK_OFFSET(guest_rflags
, 552);
671 CHECK_OFFSET(guest_pending_dbg_exceptions
, 560);
672 CHECK_OFFSET(guest_sysenter_esp
, 568);
673 CHECK_OFFSET(guest_sysenter_eip
, 576);
674 CHECK_OFFSET(host_cr0
, 584);
675 CHECK_OFFSET(host_cr3
, 592);
676 CHECK_OFFSET(host_cr4
, 600);
677 CHECK_OFFSET(host_fs_base
, 608);
678 CHECK_OFFSET(host_gs_base
, 616);
679 CHECK_OFFSET(host_tr_base
, 624);
680 CHECK_OFFSET(host_gdtr_base
, 632);
681 CHECK_OFFSET(host_idtr_base
, 640);
682 CHECK_OFFSET(host_ia32_sysenter_esp
, 648);
683 CHECK_OFFSET(host_ia32_sysenter_eip
, 656);
684 CHECK_OFFSET(host_rsp
, 664);
685 CHECK_OFFSET(host_rip
, 672);
686 CHECK_OFFSET(pin_based_vm_exec_control
, 744);
687 CHECK_OFFSET(cpu_based_vm_exec_control
, 748);
688 CHECK_OFFSET(exception_bitmap
, 752);
689 CHECK_OFFSET(page_fault_error_code_mask
, 756);
690 CHECK_OFFSET(page_fault_error_code_match
, 760);
691 CHECK_OFFSET(cr3_target_count
, 764);
692 CHECK_OFFSET(vm_exit_controls
, 768);
693 CHECK_OFFSET(vm_exit_msr_store_count
, 772);
694 CHECK_OFFSET(vm_exit_msr_load_count
, 776);
695 CHECK_OFFSET(vm_entry_controls
, 780);
696 CHECK_OFFSET(vm_entry_msr_load_count
, 784);
697 CHECK_OFFSET(vm_entry_intr_info_field
, 788);
698 CHECK_OFFSET(vm_entry_exception_error_code
, 792);
699 CHECK_OFFSET(vm_entry_instruction_len
, 796);
700 CHECK_OFFSET(tpr_threshold
, 800);
701 CHECK_OFFSET(secondary_vm_exec_control
, 804);
702 CHECK_OFFSET(vm_instruction_error
, 808);
703 CHECK_OFFSET(vm_exit_reason
, 812);
704 CHECK_OFFSET(vm_exit_intr_info
, 816);
705 CHECK_OFFSET(vm_exit_intr_error_code
, 820);
706 CHECK_OFFSET(idt_vectoring_info_field
, 824);
707 CHECK_OFFSET(idt_vectoring_error_code
, 828);
708 CHECK_OFFSET(vm_exit_instruction_len
, 832);
709 CHECK_OFFSET(vmx_instruction_info
, 836);
710 CHECK_OFFSET(guest_es_limit
, 840);
711 CHECK_OFFSET(guest_cs_limit
, 844);
712 CHECK_OFFSET(guest_ss_limit
, 848);
713 CHECK_OFFSET(guest_ds_limit
, 852);
714 CHECK_OFFSET(guest_fs_limit
, 856);
715 CHECK_OFFSET(guest_gs_limit
, 860);
716 CHECK_OFFSET(guest_ldtr_limit
, 864);
717 CHECK_OFFSET(guest_tr_limit
, 868);
718 CHECK_OFFSET(guest_gdtr_limit
, 872);
719 CHECK_OFFSET(guest_idtr_limit
, 876);
720 CHECK_OFFSET(guest_es_ar_bytes
, 880);
721 CHECK_OFFSET(guest_cs_ar_bytes
, 884);
722 CHECK_OFFSET(guest_ss_ar_bytes
, 888);
723 CHECK_OFFSET(guest_ds_ar_bytes
, 892);
724 CHECK_OFFSET(guest_fs_ar_bytes
, 896);
725 CHECK_OFFSET(guest_gs_ar_bytes
, 900);
726 CHECK_OFFSET(guest_ldtr_ar_bytes
, 904);
727 CHECK_OFFSET(guest_tr_ar_bytes
, 908);
728 CHECK_OFFSET(guest_interruptibility_info
, 912);
729 CHECK_OFFSET(guest_activity_state
, 916);
730 CHECK_OFFSET(guest_sysenter_cs
, 920);
731 CHECK_OFFSET(host_ia32_sysenter_cs
, 924);
732 CHECK_OFFSET(vmx_preemption_timer_value
, 928);
733 CHECK_OFFSET(virtual_processor_id
, 960);
734 CHECK_OFFSET(posted_intr_nv
, 962);
735 CHECK_OFFSET(guest_es_selector
, 964);
736 CHECK_OFFSET(guest_cs_selector
, 966);
737 CHECK_OFFSET(guest_ss_selector
, 968);
738 CHECK_OFFSET(guest_ds_selector
, 970);
739 CHECK_OFFSET(guest_fs_selector
, 972);
740 CHECK_OFFSET(guest_gs_selector
, 974);
741 CHECK_OFFSET(guest_ldtr_selector
, 976);
742 CHECK_OFFSET(guest_tr_selector
, 978);
743 CHECK_OFFSET(guest_intr_status
, 980);
744 CHECK_OFFSET(host_es_selector
, 982);
745 CHECK_OFFSET(host_cs_selector
, 984);
746 CHECK_OFFSET(host_ss_selector
, 986);
747 CHECK_OFFSET(host_ds_selector
, 988);
748 CHECK_OFFSET(host_fs_selector
, 990);
749 CHECK_OFFSET(host_gs_selector
, 992);
750 CHECK_OFFSET(host_tr_selector
, 994);
751 CHECK_OFFSET(guest_pml_index
, 996);
755 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
756 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
757 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
759 * IMPORTANT: Changing this value will break save/restore compatibility with
760 * older kvm releases.
762 #define VMCS12_REVISION 0x11e57ed0
765 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
766 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
767 * current implementation, 4K are reserved to avoid future complications.
769 #define VMCS12_SIZE 0x1000
772 * VMCS12_MAX_FIELD_INDEX is the highest index value used in any
773 * supported VMCS12 field encoding.
775 #define VMCS12_MAX_FIELD_INDEX 0x17
777 struct nested_vmx_msrs
{
779 * We only store the "true" versions of the VMX capability MSRs. We
780 * generate the "non-true" versions by setting the must-be-1 bits
781 * according to the SDM.
783 u32 procbased_ctls_low
;
784 u32 procbased_ctls_high
;
785 u32 secondary_ctls_low
;
786 u32 secondary_ctls_high
;
787 u32 pinbased_ctls_low
;
788 u32 pinbased_ctls_high
;
807 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
808 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
811 /* Has the level1 guest done vmxon? */
816 /* The guest-physical address of the current VMCS L1 keeps for L2 */
819 * Cache of the guest's VMCS, existing outside of guest memory.
820 * Loaded from guest memory during VMPTRLD. Flushed to guest
821 * memory during VMCLEAR and VMPTRLD.
823 struct vmcs12
*cached_vmcs12
;
825 * Cache of the guest's shadow VMCS, existing outside of guest
826 * memory. Loaded from guest memory during VM entry. Flushed
827 * to guest memory during VM exit.
829 struct vmcs12
*cached_shadow_vmcs12
;
831 * Indicates if the shadow vmcs must be updated with the
832 * data hold by vmcs12
834 bool sync_shadow_vmcs
;
837 bool change_vmcs01_virtual_apic_mode
;
839 /* L2 must run next, and mustn't decide to exit to L1. */
840 bool nested_run_pending
;
842 struct loaded_vmcs vmcs02
;
845 * Guest pages referred to in the vmcs02 with host-physical
846 * pointers, so we must keep them pinned while L2 runs.
848 struct page
*apic_access_page
;
849 struct page
*virtual_apic_page
;
850 struct page
*pi_desc_page
;
851 struct pi_desc
*pi_desc
;
855 struct hrtimer preemption_timer
;
856 bool preemption_timer_expired
;
858 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
864 struct nested_vmx_msrs msrs
;
866 /* SMM related state */
868 /* in VMX operation on SMM entry? */
870 /* in guest mode on SMM entry? */
875 #define POSTED_INTR_ON 0
876 #define POSTED_INTR_SN 1
878 /* Posted-Interrupt Descriptor */
880 u32 pir
[8]; /* Posted interrupt requested */
883 /* bit 256 - Outstanding Notification */
885 /* bit 257 - Suppress Notification */
887 /* bit 271:258 - Reserved */
889 /* bit 279:272 - Notification Vector */
891 /* bit 287:280 - Reserved */
893 /* bit 319:288 - Notification Destination */
901 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
903 return test_and_set_bit(POSTED_INTR_ON
,
904 (unsigned long *)&pi_desc
->control
);
907 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
909 return test_and_clear_bit(POSTED_INTR_ON
,
910 (unsigned long *)&pi_desc
->control
);
913 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
915 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
918 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
920 return clear_bit(POSTED_INTR_SN
,
921 (unsigned long *)&pi_desc
->control
);
924 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
926 return set_bit(POSTED_INTR_SN
,
927 (unsigned long *)&pi_desc
->control
);
930 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
932 clear_bit(POSTED_INTR_ON
,
933 (unsigned long *)&pi_desc
->control
);
936 static inline int pi_test_on(struct pi_desc
*pi_desc
)
938 return test_bit(POSTED_INTR_ON
,
939 (unsigned long *)&pi_desc
->control
);
942 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
944 return test_bit(POSTED_INTR_SN
,
945 (unsigned long *)&pi_desc
->control
);
950 struct vmx_msr_entry val
[NR_AUTOLOAD_MSRS
];
954 struct kvm_vcpu vcpu
;
955 unsigned long host_rsp
;
959 u32 idt_vectoring_info
;
961 struct shared_msr_entry
*guest_msrs
;
964 unsigned long host_idt_base
;
966 u64 msr_host_kernel_gs_base
;
967 u64 msr_guest_kernel_gs_base
;
970 u64 arch_capabilities
;
973 u32 vm_entry_controls_shadow
;
974 u32 vm_exit_controls_shadow
;
975 u32 secondary_exec_control
;
978 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
979 * non-nested (L1) guest, it always points to vmcs01. For a nested
980 * guest (L2), it points to a different VMCS. loaded_cpu_state points
981 * to the VMCS whose state is loaded into the CPU registers that only
982 * need to be switched when transitioning to/from the kernel; a NULL
983 * value indicates that host state is loaded.
985 struct loaded_vmcs vmcs01
;
986 struct loaded_vmcs
*loaded_vmcs
;
987 struct loaded_vmcs
*loaded_cpu_state
;
988 bool __launched
; /* temporary, used in vmx_vcpu_run */
989 struct msr_autoload
{
990 struct vmx_msrs guest
;
991 struct vmx_msrs host
;
997 struct kvm_segment segs
[8];
1000 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
1001 struct kvm_save_segment
{
1009 bool emulation_required
;
1013 /* Posted interrupt descriptor */
1014 struct pi_desc pi_desc
;
1016 /* Support for a guest hypervisor (nested VMX) */
1017 struct nested_vmx nested
;
1019 /* Dynamic PLE window. */
1021 bool ple_window_dirty
;
1023 bool req_immediate_exit
;
1025 /* Support for PML */
1026 #define PML_ENTITY_NUM 512
1027 struct page
*pml_pg
;
1029 /* apic deadline value in host tsc */
1030 u64 hv_deadline_tsc
;
1032 u64 current_tsc_ratio
;
1036 unsigned long host_debugctlmsr
;
1039 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
1040 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
1041 * in msr_ia32_feature_control_valid_bits.
1043 u64 msr_ia32_feature_control
;
1044 u64 msr_ia32_feature_control_valid_bits
;
1048 enum segment_cache_field
{
1051 SEG_FIELD_LIMIT
= 2,
1057 static inline struct kvm_vmx
*to_kvm_vmx(struct kvm
*kvm
)
1059 return container_of(kvm
, struct kvm_vmx
, kvm
);
1062 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
1064 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
1067 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
1069 return &(to_vmx(vcpu
)->pi_desc
);
1072 #define ROL16(val, n) ((u16)(((u16)(val) << (n)) | ((u16)(val) >> (16 - (n)))))
1073 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
1074 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name)
1075 #define FIELD64(number, name) \
1076 FIELD(number, name), \
1077 [ROL16(number##_HIGH, 6)] = VMCS12_OFFSET(name) + sizeof(u32)
1080 static u16 shadow_read_only_fields
[] = {
1081 #define SHADOW_FIELD_RO(x) x,
1082 #include "vmx_shadow_fields.h"
1084 static int max_shadow_read_only_fields
=
1085 ARRAY_SIZE(shadow_read_only_fields
);
1087 static u16 shadow_read_write_fields
[] = {
1088 #define SHADOW_FIELD_RW(x) x,
1089 #include "vmx_shadow_fields.h"
1091 static int max_shadow_read_write_fields
=
1092 ARRAY_SIZE(shadow_read_write_fields
);
1094 static const unsigned short vmcs_field_to_offset_table
[] = {
1095 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
1096 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
1097 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
1098 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
1099 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
1100 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
1101 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
1102 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
1103 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
1104 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
1105 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
1106 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
1107 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
1108 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
1109 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
1110 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
1111 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
1112 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
1113 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
1114 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
1115 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
1116 FIELD64(MSR_BITMAP
, msr_bitmap
),
1117 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
1118 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
1119 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
1120 FIELD64(PML_ADDRESS
, pml_address
),
1121 FIELD64(TSC_OFFSET
, tsc_offset
),
1122 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
1123 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
1124 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
1125 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
1126 FIELD64(EPT_POINTER
, ept_pointer
),
1127 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
1128 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
1129 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
1130 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
1131 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
1132 FIELD64(VMREAD_BITMAP
, vmread_bitmap
),
1133 FIELD64(VMWRITE_BITMAP
, vmwrite_bitmap
),
1134 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
1135 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
1136 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
1137 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
1138 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
1139 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
1140 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
1141 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
1142 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
1143 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
1144 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
1145 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
1146 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
1147 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
1148 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
1149 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
1150 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
1151 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
1152 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
1153 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
1154 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
1155 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
1156 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
1157 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
1158 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
1159 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
1160 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
1161 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
1162 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
1163 FIELD(TPR_THRESHOLD
, tpr_threshold
),
1164 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
1165 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
1166 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
1167 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
1168 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
1169 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
1170 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
1171 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
1172 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
1173 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
1174 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
1175 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
1176 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
1177 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
1178 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
1179 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
1180 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
1181 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
1182 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
1183 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
1184 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
1185 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
1186 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
1187 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
1188 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
1189 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
1190 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
1191 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
1192 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
1193 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
1194 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
1195 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
1196 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
1197 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
1198 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
1199 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
1200 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
1201 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
1202 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
1203 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
1204 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
1205 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
1206 FIELD(GUEST_CR0
, guest_cr0
),
1207 FIELD(GUEST_CR3
, guest_cr3
),
1208 FIELD(GUEST_CR4
, guest_cr4
),
1209 FIELD(GUEST_ES_BASE
, guest_es_base
),
1210 FIELD(GUEST_CS_BASE
, guest_cs_base
),
1211 FIELD(GUEST_SS_BASE
, guest_ss_base
),
1212 FIELD(GUEST_DS_BASE
, guest_ds_base
),
1213 FIELD(GUEST_FS_BASE
, guest_fs_base
),
1214 FIELD(GUEST_GS_BASE
, guest_gs_base
),
1215 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
1216 FIELD(GUEST_TR_BASE
, guest_tr_base
),
1217 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
1218 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
1219 FIELD(GUEST_DR7
, guest_dr7
),
1220 FIELD(GUEST_RSP
, guest_rsp
),
1221 FIELD(GUEST_RIP
, guest_rip
),
1222 FIELD(GUEST_RFLAGS
, guest_rflags
),
1223 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
1224 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
1225 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
1226 FIELD(HOST_CR0
, host_cr0
),
1227 FIELD(HOST_CR3
, host_cr3
),
1228 FIELD(HOST_CR4
, host_cr4
),
1229 FIELD(HOST_FS_BASE
, host_fs_base
),
1230 FIELD(HOST_GS_BASE
, host_gs_base
),
1231 FIELD(HOST_TR_BASE
, host_tr_base
),
1232 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
1233 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
1234 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
1235 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
1236 FIELD(HOST_RSP
, host_rsp
),
1237 FIELD(HOST_RIP
, host_rip
),
1240 static inline short vmcs_field_to_offset(unsigned long field
)
1242 const size_t size
= ARRAY_SIZE(vmcs_field_to_offset_table
);
1243 unsigned short offset
;
1249 index
= ROL16(field
, 6);
1253 index
= array_index_nospec(index
, size
);
1254 offset
= vmcs_field_to_offset_table
[index
];
1260 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
1262 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
1265 static inline struct vmcs12
*get_shadow_vmcs12(struct kvm_vcpu
*vcpu
)
1267 return to_vmx(vcpu
)->nested
.cached_shadow_vmcs12
;
1270 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
1271 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
1272 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
1273 static bool vmx_xsaves_supported(void);
1274 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1275 struct kvm_segment
*var
, int seg
);
1276 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1277 struct kvm_segment
*var
, int seg
);
1278 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
1279 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
1280 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
1281 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
1282 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
1283 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
1285 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
);
1286 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
1289 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
1290 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
1292 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
1293 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
1295 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
1298 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
1299 * can find which vCPU should be waken up.
1301 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
1302 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
1310 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
1312 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
1313 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
1315 static bool cpu_has_load_ia32_efer
;
1316 static bool cpu_has_load_perf_global_ctrl
;
1318 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
1319 static DEFINE_SPINLOCK(vmx_vpid_lock
);
1321 static struct vmcs_config
{
1326 u32 pin_based_exec_ctrl
;
1327 u32 cpu_based_exec_ctrl
;
1328 u32 cpu_based_2nd_exec_ctrl
;
1331 struct nested_vmx_msrs nested
;
1334 static struct vmx_capability
{
1339 #define VMX_SEGMENT_FIELD(seg) \
1340 [VCPU_SREG_##seg] = { \
1341 .selector = GUEST_##seg##_SELECTOR, \
1342 .base = GUEST_##seg##_BASE, \
1343 .limit = GUEST_##seg##_LIMIT, \
1344 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1347 static const struct kvm_vmx_segment_field
{
1352 } kvm_vmx_segment_fields
[] = {
1353 VMX_SEGMENT_FIELD(CS
),
1354 VMX_SEGMENT_FIELD(DS
),
1355 VMX_SEGMENT_FIELD(ES
),
1356 VMX_SEGMENT_FIELD(FS
),
1357 VMX_SEGMENT_FIELD(GS
),
1358 VMX_SEGMENT_FIELD(SS
),
1359 VMX_SEGMENT_FIELD(TR
),
1360 VMX_SEGMENT_FIELD(LDTR
),
1363 static u64 host_efer
;
1365 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1368 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1369 * away by decrementing the array size.
1371 static const u32 vmx_msr_index
[] = {
1372 #ifdef CONFIG_X86_64
1373 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1375 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1378 DEFINE_STATIC_KEY_FALSE(enable_evmcs
);
1380 #define current_evmcs ((struct hv_enlightened_vmcs *)this_cpu_read(current_vmcs))
1382 #define KVM_EVMCS_VERSION 1
1384 #if IS_ENABLED(CONFIG_HYPERV)
1385 static bool __read_mostly enlightened_vmcs
= true;
1386 module_param(enlightened_vmcs
, bool, 0444);
1388 static inline void evmcs_write64(unsigned long field
, u64 value
)
1391 int offset
= get_evmcs_offset(field
, &clean_field
);
1396 *(u64
*)((char *)current_evmcs
+ offset
) = value
;
1398 current_evmcs
->hv_clean_fields
&= ~clean_field
;
1401 static inline void evmcs_write32(unsigned long field
, u32 value
)
1404 int offset
= get_evmcs_offset(field
, &clean_field
);
1409 *(u32
*)((char *)current_evmcs
+ offset
) = value
;
1410 current_evmcs
->hv_clean_fields
&= ~clean_field
;
1413 static inline void evmcs_write16(unsigned long field
, u16 value
)
1416 int offset
= get_evmcs_offset(field
, &clean_field
);
1421 *(u16
*)((char *)current_evmcs
+ offset
) = value
;
1422 current_evmcs
->hv_clean_fields
&= ~clean_field
;
1425 static inline u64
evmcs_read64(unsigned long field
)
1427 int offset
= get_evmcs_offset(field
, NULL
);
1432 return *(u64
*)((char *)current_evmcs
+ offset
);
1435 static inline u32
evmcs_read32(unsigned long field
)
1437 int offset
= get_evmcs_offset(field
, NULL
);
1442 return *(u32
*)((char *)current_evmcs
+ offset
);
1445 static inline u16
evmcs_read16(unsigned long field
)
1447 int offset
= get_evmcs_offset(field
, NULL
);
1452 return *(u16
*)((char *)current_evmcs
+ offset
);
1455 static inline void evmcs_touch_msr_bitmap(void)
1457 if (unlikely(!current_evmcs
))
1460 if (current_evmcs
->hv_enlightenments_control
.msr_bitmap
)
1461 current_evmcs
->hv_clean_fields
&=
1462 ~HV_VMX_ENLIGHTENED_CLEAN_FIELD_MSR_BITMAP
;
1465 static void evmcs_load(u64 phys_addr
)
1467 struct hv_vp_assist_page
*vp_ap
=
1468 hv_get_vp_assist_page(smp_processor_id());
1470 vp_ap
->current_nested_vmcs
= phys_addr
;
1471 vp_ap
->enlighten_vmentry
= 1;
1474 static void evmcs_sanitize_exec_ctrls(struct vmcs_config
*vmcs_conf
)
1477 * Enlightened VMCSv1 doesn't support these:
1479 * POSTED_INTR_NV = 0x00000002,
1480 * GUEST_INTR_STATUS = 0x00000810,
1481 * APIC_ACCESS_ADDR = 0x00002014,
1482 * POSTED_INTR_DESC_ADDR = 0x00002016,
1483 * EOI_EXIT_BITMAP0 = 0x0000201c,
1484 * EOI_EXIT_BITMAP1 = 0x0000201e,
1485 * EOI_EXIT_BITMAP2 = 0x00002020,
1486 * EOI_EXIT_BITMAP3 = 0x00002022,
1488 vmcs_conf
->pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
1489 vmcs_conf
->cpu_based_2nd_exec_ctrl
&=
1490 ~SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1491 vmcs_conf
->cpu_based_2nd_exec_ctrl
&=
1492 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1493 vmcs_conf
->cpu_based_2nd_exec_ctrl
&=
1494 ~SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1497 * GUEST_PML_INDEX = 0x00000812,
1498 * PML_ADDRESS = 0x0000200e,
1500 vmcs_conf
->cpu_based_2nd_exec_ctrl
&= ~SECONDARY_EXEC_ENABLE_PML
;
1502 /* VM_FUNCTION_CONTROL = 0x00002018, */
1503 vmcs_conf
->cpu_based_2nd_exec_ctrl
&= ~SECONDARY_EXEC_ENABLE_VMFUNC
;
1506 * EPTP_LIST_ADDRESS = 0x00002024,
1507 * VMREAD_BITMAP = 0x00002026,
1508 * VMWRITE_BITMAP = 0x00002028,
1510 vmcs_conf
->cpu_based_2nd_exec_ctrl
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
1513 * TSC_MULTIPLIER = 0x00002032,
1515 vmcs_conf
->cpu_based_2nd_exec_ctrl
&= ~SECONDARY_EXEC_TSC_SCALING
;
1518 * PLE_GAP = 0x00004020,
1519 * PLE_WINDOW = 0x00004022,
1521 vmcs_conf
->cpu_based_2nd_exec_ctrl
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1524 * VMX_PREEMPTION_TIMER_VALUE = 0x0000482E,
1526 vmcs_conf
->pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
1529 * GUEST_IA32_PERF_GLOBAL_CTRL = 0x00002808,
1530 * HOST_IA32_PERF_GLOBAL_CTRL = 0x00002c04,
1532 vmcs_conf
->vmexit_ctrl
&= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
;
1533 vmcs_conf
->vmentry_ctrl
&= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
;
1536 * Currently unsupported in KVM:
1537 * GUEST_IA32_RTIT_CTL = 0x00002814,
1541 /* check_ept_pointer() should be under protection of ept_pointer_lock. */
1542 static void check_ept_pointer_match(struct kvm
*kvm
)
1544 struct kvm_vcpu
*vcpu
;
1545 u64 tmp_eptp
= INVALID_PAGE
;
1548 kvm_for_each_vcpu(i
, vcpu
, kvm
) {
1549 if (!VALID_PAGE(tmp_eptp
)) {
1550 tmp_eptp
= to_vmx(vcpu
)->ept_pointer
;
1551 } else if (tmp_eptp
!= to_vmx(vcpu
)->ept_pointer
) {
1552 to_kvm_vmx(kvm
)->ept_pointers_match
1553 = EPT_POINTERS_MISMATCH
;
1558 to_kvm_vmx(kvm
)->ept_pointers_match
= EPT_POINTERS_MATCH
;
1561 static int vmx_hv_remote_flush_tlb(struct kvm
*kvm
)
1565 spin_lock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
1567 if (to_kvm_vmx(kvm
)->ept_pointers_match
== EPT_POINTERS_CHECK
)
1568 check_ept_pointer_match(kvm
);
1570 if (to_kvm_vmx(kvm
)->ept_pointers_match
!= EPT_POINTERS_MATCH
) {
1575 ret
= hyperv_flush_guest_mapping(
1576 to_vmx(kvm_get_vcpu(kvm
, 0))->ept_pointer
);
1579 spin_unlock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
1582 #else /* !IS_ENABLED(CONFIG_HYPERV) */
1583 static inline void evmcs_write64(unsigned long field
, u64 value
) {}
1584 static inline void evmcs_write32(unsigned long field
, u32 value
) {}
1585 static inline void evmcs_write16(unsigned long field
, u16 value
) {}
1586 static inline u64
evmcs_read64(unsigned long field
) { return 0; }
1587 static inline u32
evmcs_read32(unsigned long field
) { return 0; }
1588 static inline u16
evmcs_read16(unsigned long field
) { return 0; }
1589 static inline void evmcs_load(u64 phys_addr
) {}
1590 static inline void evmcs_sanitize_exec_ctrls(struct vmcs_config
*vmcs_conf
) {}
1591 static inline void evmcs_touch_msr_bitmap(void) {}
1592 #endif /* IS_ENABLED(CONFIG_HYPERV) */
1594 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1596 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1597 INTR_INFO_VALID_MASK
)) ==
1598 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1601 static inline bool is_debug(u32 intr_info
)
1603 return is_exception_n(intr_info
, DB_VECTOR
);
1606 static inline bool is_breakpoint(u32 intr_info
)
1608 return is_exception_n(intr_info
, BP_VECTOR
);
1611 static inline bool is_page_fault(u32 intr_info
)
1613 return is_exception_n(intr_info
, PF_VECTOR
);
1616 static inline bool is_no_device(u32 intr_info
)
1618 return is_exception_n(intr_info
, NM_VECTOR
);
1621 static inline bool is_invalid_opcode(u32 intr_info
)
1623 return is_exception_n(intr_info
, UD_VECTOR
);
1626 static inline bool is_gp_fault(u32 intr_info
)
1628 return is_exception_n(intr_info
, GP_VECTOR
);
1631 static inline bool is_external_interrupt(u32 intr_info
)
1633 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1634 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1637 static inline bool is_machine_check(u32 intr_info
)
1639 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1640 INTR_INFO_VALID_MASK
)) ==
1641 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1644 /* Undocumented: icebp/int1 */
1645 static inline bool is_icebp(u32 intr_info
)
1647 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1648 == (INTR_TYPE_PRIV_SW_EXCEPTION
| INTR_INFO_VALID_MASK
);
1651 static inline bool cpu_has_vmx_msr_bitmap(void)
1653 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1656 static inline bool cpu_has_vmx_tpr_shadow(void)
1658 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1661 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1663 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1666 static inline bool cpu_has_secondary_exec_ctrls(void)
1668 return vmcs_config
.cpu_based_exec_ctrl
&
1669 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1672 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1674 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1675 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1678 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1680 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1681 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1684 static inline bool cpu_has_vmx_apic_register_virt(void)
1686 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1687 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1690 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1692 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1693 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1696 static inline bool cpu_has_vmx_encls_vmexit(void)
1698 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1699 SECONDARY_EXEC_ENCLS_EXITING
;
1703 * Comment's format: document - errata name - stepping - processor name.
1705 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1707 static u32 vmx_preemption_cpu_tfms
[] = {
1708 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1710 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1711 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1712 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1714 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1716 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1717 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1719 * 320767.pdf - AAP86 - B1 -
1720 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1723 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1725 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1727 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1729 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1730 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1731 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1735 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1737 u32 eax
= cpuid_eax(0x00000001), i
;
1739 /* Clear the reserved bits */
1740 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1741 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1742 if (eax
== vmx_preemption_cpu_tfms
[i
])
1748 static inline bool cpu_has_vmx_preemption_timer(void)
1750 return vmcs_config
.pin_based_exec_ctrl
&
1751 PIN_BASED_VMX_PREEMPTION_TIMER
;
1754 static inline bool cpu_has_vmx_posted_intr(void)
1756 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1757 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1760 static inline bool cpu_has_vmx_apicv(void)
1762 return cpu_has_vmx_apic_register_virt() &&
1763 cpu_has_vmx_virtual_intr_delivery() &&
1764 cpu_has_vmx_posted_intr();
1767 static inline bool cpu_has_vmx_flexpriority(void)
1769 return cpu_has_vmx_tpr_shadow() &&
1770 cpu_has_vmx_virtualize_apic_accesses();
1773 static inline bool cpu_has_vmx_ept_execute_only(void)
1775 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1778 static inline bool cpu_has_vmx_ept_2m_page(void)
1780 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1783 static inline bool cpu_has_vmx_ept_1g_page(void)
1785 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1788 static inline bool cpu_has_vmx_ept_4levels(void)
1790 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1793 static inline bool cpu_has_vmx_ept_mt_wb(void)
1795 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1798 static inline bool cpu_has_vmx_ept_5levels(void)
1800 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1803 static inline bool cpu_has_vmx_ept_ad_bits(void)
1805 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1808 static inline bool cpu_has_vmx_invept_context(void)
1810 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1813 static inline bool cpu_has_vmx_invept_global(void)
1815 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1818 static inline bool cpu_has_vmx_invvpid_individual_addr(void)
1820 return vmx_capability
.vpid
& VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT
;
1823 static inline bool cpu_has_vmx_invvpid_single(void)
1825 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1828 static inline bool cpu_has_vmx_invvpid_global(void)
1830 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1833 static inline bool cpu_has_vmx_invvpid(void)
1835 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1838 static inline bool cpu_has_vmx_ept(void)
1840 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1841 SECONDARY_EXEC_ENABLE_EPT
;
1844 static inline bool cpu_has_vmx_unrestricted_guest(void)
1846 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1847 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1850 static inline bool cpu_has_vmx_ple(void)
1852 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1853 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1856 static inline bool cpu_has_vmx_basic_inout(void)
1858 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1861 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1863 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1866 static inline bool cpu_has_vmx_vpid(void)
1868 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1869 SECONDARY_EXEC_ENABLE_VPID
;
1872 static inline bool cpu_has_vmx_rdtscp(void)
1874 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1875 SECONDARY_EXEC_RDTSCP
;
1878 static inline bool cpu_has_vmx_invpcid(void)
1880 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1881 SECONDARY_EXEC_ENABLE_INVPCID
;
1884 static inline bool cpu_has_virtual_nmis(void)
1886 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1889 static inline bool cpu_has_vmx_wbinvd_exit(void)
1891 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1892 SECONDARY_EXEC_WBINVD_EXITING
;
1895 static inline bool cpu_has_vmx_shadow_vmcs(void)
1898 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1899 /* check if the cpu supports writing r/o exit information fields */
1900 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1903 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1904 SECONDARY_EXEC_SHADOW_VMCS
;
1907 static inline bool cpu_has_vmx_pml(void)
1909 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1912 static inline bool cpu_has_vmx_tsc_scaling(void)
1914 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1915 SECONDARY_EXEC_TSC_SCALING
;
1918 static inline bool cpu_has_vmx_vmfunc(void)
1920 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1921 SECONDARY_EXEC_ENABLE_VMFUNC
;
1924 static bool vmx_umip_emulated(void)
1926 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1927 SECONDARY_EXEC_DESC
;
1930 static inline bool report_flexpriority(void)
1932 return flexpriority_enabled
;
1935 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1937 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.msrs
.misc_low
);
1941 * Do the virtual VMX capability MSRs specify that L1 can use VMWRITE
1942 * to modify any valid field of the VMCS, or are the VM-exit
1943 * information fields read-only?
1945 static inline bool nested_cpu_has_vmwrite_any_field(struct kvm_vcpu
*vcpu
)
1947 return to_vmx(vcpu
)->nested
.msrs
.misc_low
&
1948 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
;
1951 static inline bool nested_cpu_has_zero_length_injection(struct kvm_vcpu
*vcpu
)
1953 return to_vmx(vcpu
)->nested
.msrs
.misc_low
& VMX_MISC_ZERO_LEN_INS
;
1956 static inline bool nested_cpu_supports_monitor_trap_flag(struct kvm_vcpu
*vcpu
)
1958 return to_vmx(vcpu
)->nested
.msrs
.procbased_ctls_high
&
1959 CPU_BASED_MONITOR_TRAP_FLAG
;
1962 static inline bool nested_cpu_has_vmx_shadow_vmcs(struct kvm_vcpu
*vcpu
)
1964 return to_vmx(vcpu
)->nested
.msrs
.secondary_ctls_high
&
1965 SECONDARY_EXEC_SHADOW_VMCS
;
1968 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1970 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1973 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1975 return (vmcs12
->cpu_based_vm_exec_control
&
1976 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1977 (vmcs12
->secondary_vm_exec_control
& bit
);
1980 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1982 return vmcs12
->pin_based_vm_exec_control
&
1983 PIN_BASED_VMX_PREEMPTION_TIMER
;
1986 static inline bool nested_cpu_has_nmi_exiting(struct vmcs12
*vmcs12
)
1988 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_NMI_EXITING
;
1991 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1993 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1996 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1998 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
2001 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
2003 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
2006 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
2008 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
2011 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
2013 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
2016 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
2018 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
2021 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
2023 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
2026 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
2028 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2031 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
2033 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
2036 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
2038 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
2041 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
2043 return nested_cpu_has_vmfunc(vmcs12
) &&
2044 (vmcs12
->vm_function_control
&
2045 VMX_VMFUNC_EPTP_SWITCHING
);
2048 static inline bool nested_cpu_has_shadow_vmcs(struct vmcs12
*vmcs12
)
2050 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
);
2053 static inline bool is_nmi(u32 intr_info
)
2055 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
2056 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
2059 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
2061 unsigned long exit_qualification
);
2062 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
2063 struct vmcs12
*vmcs12
,
2064 u32 reason
, unsigned long qualification
);
2066 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
2070 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
2071 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
2076 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
2082 } operand
= { vpid
, 0, gva
};
2085 asm volatile (__ex(ASM_VMX_INVVPID
) CC_SET(na
)
2086 : CC_OUT(na
) (error
) : "a"(&operand
), "c"(ext
)
2091 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
2095 } operand
= {eptp
, gpa
};
2098 asm volatile (__ex(ASM_VMX_INVEPT
) CC_SET(na
)
2099 : CC_OUT(na
) (error
) : "a" (&operand
), "c" (ext
)
2104 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
2108 i
= __find_msr_index(vmx
, msr
);
2110 return &vmx
->guest_msrs
[i
];
2114 static void vmcs_clear(struct vmcs
*vmcs
)
2116 u64 phys_addr
= __pa(vmcs
);
2119 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) CC_SET(na
)
2120 : CC_OUT(na
) (error
) : "a"(&phys_addr
), "m"(phys_addr
)
2122 if (unlikely(error
))
2123 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
2127 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
2129 vmcs_clear(loaded_vmcs
->vmcs
);
2130 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
2131 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
2132 loaded_vmcs
->cpu
= -1;
2133 loaded_vmcs
->launched
= 0;
2136 static void vmcs_load(struct vmcs
*vmcs
)
2138 u64 phys_addr
= __pa(vmcs
);
2141 if (static_branch_unlikely(&enable_evmcs
))
2142 return evmcs_load(phys_addr
);
2144 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) CC_SET(na
)
2145 : CC_OUT(na
) (error
) : "a"(&phys_addr
), "m"(phys_addr
)
2147 if (unlikely(error
))
2148 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
2152 #ifdef CONFIG_KEXEC_CORE
2154 * This bitmap is used to indicate whether the vmclear
2155 * operation is enabled on all cpus. All disabled by
2158 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
2160 static inline void crash_enable_local_vmclear(int cpu
)
2162 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
2165 static inline void crash_disable_local_vmclear(int cpu
)
2167 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
2170 static inline int crash_local_vmclear_enabled(int cpu
)
2172 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
2175 static void crash_vmclear_local_loaded_vmcss(void)
2177 int cpu
= raw_smp_processor_id();
2178 struct loaded_vmcs
*v
;
2180 if (!crash_local_vmclear_enabled(cpu
))
2183 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2184 loaded_vmcss_on_cpu_link
)
2185 vmcs_clear(v
->vmcs
);
2188 static inline void crash_enable_local_vmclear(int cpu
) { }
2189 static inline void crash_disable_local_vmclear(int cpu
) { }
2190 #endif /* CONFIG_KEXEC_CORE */
2192 static void __loaded_vmcs_clear(void *arg
)
2194 struct loaded_vmcs
*loaded_vmcs
= arg
;
2195 int cpu
= raw_smp_processor_id();
2197 if (loaded_vmcs
->cpu
!= cpu
)
2198 return; /* vcpu migration can race with cpu offline */
2199 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
2200 per_cpu(current_vmcs
, cpu
) = NULL
;
2201 crash_disable_local_vmclear(cpu
);
2202 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
2205 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
2206 * is before setting loaded_vmcs->vcpu to -1 which is done in
2207 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
2208 * then adds the vmcs into percpu list before it is deleted.
2212 loaded_vmcs_init(loaded_vmcs
);
2213 crash_enable_local_vmclear(cpu
);
2216 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
2218 int cpu
= loaded_vmcs
->cpu
;
2221 smp_call_function_single(cpu
,
2222 __loaded_vmcs_clear
, loaded_vmcs
, 1);
2225 static inline bool vpid_sync_vcpu_addr(int vpid
, gva_t addr
)
2230 if (cpu_has_vmx_invvpid_individual_addr()) {
2231 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR
, vpid
, addr
);
2238 static inline void vpid_sync_vcpu_single(int vpid
)
2243 if (cpu_has_vmx_invvpid_single())
2244 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
2247 static inline void vpid_sync_vcpu_global(void)
2249 if (cpu_has_vmx_invvpid_global())
2250 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
2253 static inline void vpid_sync_context(int vpid
)
2255 if (cpu_has_vmx_invvpid_single())
2256 vpid_sync_vcpu_single(vpid
);
2258 vpid_sync_vcpu_global();
2261 static inline void ept_sync_global(void)
2263 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
2266 static inline void ept_sync_context(u64 eptp
)
2268 if (cpu_has_vmx_invept_context())
2269 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
2274 static __always_inline
void vmcs_check16(unsigned long field
)
2276 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
2277 "16-bit accessor invalid for 64-bit field");
2278 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
2279 "16-bit accessor invalid for 64-bit high field");
2280 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
2281 "16-bit accessor invalid for 32-bit high field");
2282 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
2283 "16-bit accessor invalid for natural width field");
2286 static __always_inline
void vmcs_check32(unsigned long field
)
2288 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
2289 "32-bit accessor invalid for 16-bit field");
2290 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
2291 "32-bit accessor invalid for natural width field");
2294 static __always_inline
void vmcs_check64(unsigned long field
)
2296 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
2297 "64-bit accessor invalid for 16-bit field");
2298 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
2299 "64-bit accessor invalid for 64-bit high field");
2300 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
2301 "64-bit accessor invalid for 32-bit field");
2302 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
2303 "64-bit accessor invalid for natural width field");
2306 static __always_inline
void vmcs_checkl(unsigned long field
)
2308 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
2309 "Natural width accessor invalid for 16-bit field");
2310 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
2311 "Natural width accessor invalid for 64-bit field");
2312 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
2313 "Natural width accessor invalid for 64-bit high field");
2314 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
2315 "Natural width accessor invalid for 32-bit field");
2318 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
2320 unsigned long value
;
2322 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
2323 : "=a"(value
) : "d"(field
) : "cc");
2327 static __always_inline u16
vmcs_read16(unsigned long field
)
2329 vmcs_check16(field
);
2330 if (static_branch_unlikely(&enable_evmcs
))
2331 return evmcs_read16(field
);
2332 return __vmcs_readl(field
);
2335 static __always_inline u32
vmcs_read32(unsigned long field
)
2337 vmcs_check32(field
);
2338 if (static_branch_unlikely(&enable_evmcs
))
2339 return evmcs_read32(field
);
2340 return __vmcs_readl(field
);
2343 static __always_inline u64
vmcs_read64(unsigned long field
)
2345 vmcs_check64(field
);
2346 if (static_branch_unlikely(&enable_evmcs
))
2347 return evmcs_read64(field
);
2348 #ifdef CONFIG_X86_64
2349 return __vmcs_readl(field
);
2351 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
2355 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
2358 if (static_branch_unlikely(&enable_evmcs
))
2359 return evmcs_read64(field
);
2360 return __vmcs_readl(field
);
2363 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
2365 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
2366 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
2370 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
2374 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) CC_SET(na
)
2375 : CC_OUT(na
) (error
) : "a"(value
), "d"(field
));
2376 if (unlikely(error
))
2377 vmwrite_error(field
, value
);
2380 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
2382 vmcs_check16(field
);
2383 if (static_branch_unlikely(&enable_evmcs
))
2384 return evmcs_write16(field
, value
);
2386 __vmcs_writel(field
, value
);
2389 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
2391 vmcs_check32(field
);
2392 if (static_branch_unlikely(&enable_evmcs
))
2393 return evmcs_write32(field
, value
);
2395 __vmcs_writel(field
, value
);
2398 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
2400 vmcs_check64(field
);
2401 if (static_branch_unlikely(&enable_evmcs
))
2402 return evmcs_write64(field
, value
);
2404 __vmcs_writel(field
, value
);
2405 #ifndef CONFIG_X86_64
2407 __vmcs_writel(field
+1, value
>> 32);
2411 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
2414 if (static_branch_unlikely(&enable_evmcs
))
2415 return evmcs_write64(field
, value
);
2417 __vmcs_writel(field
, value
);
2420 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
2422 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
2423 "vmcs_clear_bits does not support 64-bit fields");
2424 if (static_branch_unlikely(&enable_evmcs
))
2425 return evmcs_write32(field
, evmcs_read32(field
) & ~mask
);
2427 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
2430 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
2432 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
2433 "vmcs_set_bits does not support 64-bit fields");
2434 if (static_branch_unlikely(&enable_evmcs
))
2435 return evmcs_write32(field
, evmcs_read32(field
) | mask
);
2437 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
2440 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
2442 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
2445 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
2447 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
2448 vmx
->vm_entry_controls_shadow
= val
;
2451 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
2453 if (vmx
->vm_entry_controls_shadow
!= val
)
2454 vm_entry_controls_init(vmx
, val
);
2457 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
2459 return vmx
->vm_entry_controls_shadow
;
2463 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
2465 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
2468 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
2470 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
2473 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
2475 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
2478 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
2480 vmcs_write32(VM_EXIT_CONTROLS
, val
);
2481 vmx
->vm_exit_controls_shadow
= val
;
2484 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
2486 if (vmx
->vm_exit_controls_shadow
!= val
)
2487 vm_exit_controls_init(vmx
, val
);
2490 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
2492 return vmx
->vm_exit_controls_shadow
;
2496 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
2498 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
2501 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
2503 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
2506 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
2508 vmx
->segment_cache
.bitmask
= 0;
2511 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
2515 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
2517 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
2518 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
2519 vmx
->segment_cache
.bitmask
= 0;
2521 ret
= vmx
->segment_cache
.bitmask
& mask
;
2522 vmx
->segment_cache
.bitmask
|= mask
;
2526 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
2528 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
2530 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
2531 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
2535 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
2537 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
2539 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
2540 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
2544 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
2546 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
2548 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
2549 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
2553 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
2555 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
2557 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
2558 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
2562 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
2566 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
2567 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
2569 * Guest access to VMware backdoor ports could legitimately
2570 * trigger #GP because of TSS I/O permission bitmap.
2571 * We intercept those #GP and allow access to them anyway
2574 if (enable_vmware_backdoor
)
2575 eb
|= (1u << GP_VECTOR
);
2576 if ((vcpu
->guest_debug
&
2577 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
2578 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
2579 eb
|= 1u << BP_VECTOR
;
2580 if (to_vmx(vcpu
)->rmode
.vm86_active
)
2583 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
2585 /* When we are running a nested L2 guest and L1 specified for it a
2586 * certain exception bitmap, we must trap the same exceptions and pass
2587 * them to L1. When running L2, we will only handle the exceptions
2588 * specified above if L1 did not want them.
2590 if (is_guest_mode(vcpu
))
2591 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
2593 vmcs_write32(EXCEPTION_BITMAP
, eb
);
2597 * Check if MSR is intercepted for currently loaded MSR bitmap.
2599 static bool msr_write_intercepted(struct kvm_vcpu
*vcpu
, u32 msr
)
2601 unsigned long *msr_bitmap
;
2602 int f
= sizeof(unsigned long);
2604 if (!cpu_has_vmx_msr_bitmap())
2607 msr_bitmap
= to_vmx(vcpu
)->loaded_vmcs
->msr_bitmap
;
2609 if (msr
<= 0x1fff) {
2610 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
2611 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2613 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
2620 * Check if MSR is intercepted for L01 MSR bitmap.
2622 static bool msr_write_intercepted_l01(struct kvm_vcpu
*vcpu
, u32 msr
)
2624 unsigned long *msr_bitmap
;
2625 int f
= sizeof(unsigned long);
2627 if (!cpu_has_vmx_msr_bitmap())
2630 msr_bitmap
= to_vmx(vcpu
)->vmcs01
.msr_bitmap
;
2632 if (msr
<= 0x1fff) {
2633 return !!test_bit(msr
, msr_bitmap
+ 0x800 / f
);
2634 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2636 return !!test_bit(msr
, msr_bitmap
+ 0xc00 / f
);
2642 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
2643 unsigned long entry
, unsigned long exit
)
2645 vm_entry_controls_clearbit(vmx
, entry
);
2646 vm_exit_controls_clearbit(vmx
, exit
);
2649 static int find_msr(struct vmx_msrs
*m
, unsigned int msr
)
2653 for (i
= 0; i
< m
->nr
; ++i
) {
2654 if (m
->val
[i
].index
== msr
)
2660 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
2663 struct msr_autoload
*m
= &vmx
->msr_autoload
;
2667 if (cpu_has_load_ia32_efer
) {
2668 clear_atomic_switch_msr_special(vmx
,
2669 VM_ENTRY_LOAD_IA32_EFER
,
2670 VM_EXIT_LOAD_IA32_EFER
);
2674 case MSR_CORE_PERF_GLOBAL_CTRL
:
2675 if (cpu_has_load_perf_global_ctrl
) {
2676 clear_atomic_switch_msr_special(vmx
,
2677 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2678 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2683 i
= find_msr(&m
->guest
, msr
);
2687 m
->guest
.val
[i
] = m
->guest
.val
[m
->guest
.nr
];
2688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
2691 i
= find_msr(&m
->host
, msr
);
2696 m
->host
.val
[i
] = m
->host
.val
[m
->host
.nr
];
2697 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
2700 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
2701 unsigned long entry
, unsigned long exit
,
2702 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
2703 u64 guest_val
, u64 host_val
)
2705 vmcs_write64(guest_val_vmcs
, guest_val
);
2706 vmcs_write64(host_val_vmcs
, host_val
);
2707 vm_entry_controls_setbit(vmx
, entry
);
2708 vm_exit_controls_setbit(vmx
, exit
);
2711 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
2712 u64 guest_val
, u64 host_val
, bool entry_only
)
2715 struct msr_autoload
*m
= &vmx
->msr_autoload
;
2719 if (cpu_has_load_ia32_efer
) {
2720 add_atomic_switch_msr_special(vmx
,
2721 VM_ENTRY_LOAD_IA32_EFER
,
2722 VM_EXIT_LOAD_IA32_EFER
,
2725 guest_val
, host_val
);
2729 case MSR_CORE_PERF_GLOBAL_CTRL
:
2730 if (cpu_has_load_perf_global_ctrl
) {
2731 add_atomic_switch_msr_special(vmx
,
2732 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
2733 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
2734 GUEST_IA32_PERF_GLOBAL_CTRL
,
2735 HOST_IA32_PERF_GLOBAL_CTRL
,
2736 guest_val
, host_val
);
2740 case MSR_IA32_PEBS_ENABLE
:
2741 /* PEBS needs a quiescent period after being disabled (to write
2742 * a record). Disabling PEBS through VMX MSR swapping doesn't
2743 * provide that period, so a CPU could write host's record into
2746 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2749 i
= find_msr(&m
->guest
, msr
);
2751 j
= find_msr(&m
->host
, msr
);
2753 if (i
== NR_AUTOLOAD_MSRS
|| j
== NR_AUTOLOAD_MSRS
) {
2754 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2755 "Can't add msr %x\n", msr
);
2760 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->guest
.nr
);
2762 m
->guest
.val
[i
].index
= msr
;
2763 m
->guest
.val
[i
].value
= guest_val
;
2770 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->host
.nr
);
2772 m
->host
.val
[j
].index
= msr
;
2773 m
->host
.val
[j
].value
= host_val
;
2776 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2778 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2779 u64 ignore_bits
= 0;
2783 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2784 * host CPUID is more efficient than testing guest CPUID
2785 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2787 if (boot_cpu_has(X86_FEATURE_SMEP
))
2788 guest_efer
|= EFER_NX
;
2789 else if (!(guest_efer
& EFER_NX
))
2790 ignore_bits
|= EFER_NX
;
2794 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2796 ignore_bits
|= EFER_SCE
;
2797 #ifdef CONFIG_X86_64
2798 ignore_bits
|= EFER_LMA
| EFER_LME
;
2799 /* SCE is meaningful only in long mode on Intel */
2800 if (guest_efer
& EFER_LMA
)
2801 ignore_bits
&= ~(u64
)EFER_SCE
;
2804 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2807 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2808 * On CPUs that support "load IA32_EFER", always switch EFER
2809 * atomically, since it's faster than switching it manually.
2811 if (cpu_has_load_ia32_efer
||
2812 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2813 if (!(guest_efer
& EFER_LMA
))
2814 guest_efer
&= ~EFER_LME
;
2815 if (guest_efer
!= host_efer
)
2816 add_atomic_switch_msr(vmx
, MSR_EFER
,
2817 guest_efer
, host_efer
, false);
2820 guest_efer
&= ~ignore_bits
;
2821 guest_efer
|= host_efer
& ignore_bits
;
2823 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2824 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2830 #ifdef CONFIG_X86_32
2832 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2833 * VMCS rather than the segment table. KVM uses this helper to figure
2834 * out the current bases to poke them into the VMCS before entry.
2836 static unsigned long segment_base(u16 selector
)
2838 struct desc_struct
*table
;
2841 if (!(selector
& ~SEGMENT_RPL_MASK
))
2844 table
= get_current_gdt_ro();
2846 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2847 u16 ldt_selector
= kvm_read_ldt();
2849 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2852 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2854 v
= get_desc_base(&table
[selector
>> 3]);
2859 static void vmx_prepare_switch_to_guest(struct kvm_vcpu
*vcpu
)
2861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2862 struct vmcs_host_state
*host_state
;
2863 #ifdef CONFIG_X86_64
2864 int cpu
= raw_smp_processor_id();
2866 unsigned long fs_base
, gs_base
;
2870 vmx
->req_immediate_exit
= false;
2872 if (vmx
->loaded_cpu_state
)
2875 vmx
->loaded_cpu_state
= vmx
->loaded_vmcs
;
2876 host_state
= &vmx
->loaded_cpu_state
->host_state
;
2879 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2880 * allow segment selectors with cpl > 0 or ti == 1.
2882 host_state
->ldt_sel
= kvm_read_ldt();
2884 #ifdef CONFIG_X86_64
2885 savesegment(ds
, host_state
->ds_sel
);
2886 savesegment(es
, host_state
->es_sel
);
2888 gs_base
= cpu_kernelmode_gs_base(cpu
);
2889 if (likely(is_64bit_mm(current
->mm
))) {
2890 save_fsgs_for_kvm();
2891 fs_sel
= current
->thread
.fsindex
;
2892 gs_sel
= current
->thread
.gsindex
;
2893 fs_base
= current
->thread
.fsbase
;
2894 vmx
->msr_host_kernel_gs_base
= current
->thread
.gsbase
;
2896 savesegment(fs
, fs_sel
);
2897 savesegment(gs
, gs_sel
);
2898 fs_base
= read_msr(MSR_FS_BASE
);
2899 vmx
->msr_host_kernel_gs_base
= read_msr(MSR_KERNEL_GS_BASE
);
2902 if (is_long_mode(&vmx
->vcpu
))
2903 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2905 savesegment(fs
, fs_sel
);
2906 savesegment(gs
, gs_sel
);
2907 fs_base
= segment_base(fs_sel
);
2908 gs_base
= segment_base(gs_sel
);
2911 if (unlikely(fs_sel
!= host_state
->fs_sel
)) {
2913 vmcs_write16(HOST_FS_SELECTOR
, fs_sel
);
2915 vmcs_write16(HOST_FS_SELECTOR
, 0);
2916 host_state
->fs_sel
= fs_sel
;
2918 if (unlikely(gs_sel
!= host_state
->gs_sel
)) {
2920 vmcs_write16(HOST_GS_SELECTOR
, gs_sel
);
2922 vmcs_write16(HOST_GS_SELECTOR
, 0);
2923 host_state
->gs_sel
= gs_sel
;
2925 if (unlikely(fs_base
!= host_state
->fs_base
)) {
2926 vmcs_writel(HOST_FS_BASE
, fs_base
);
2927 host_state
->fs_base
= fs_base
;
2929 if (unlikely(gs_base
!= host_state
->gs_base
)) {
2930 vmcs_writel(HOST_GS_BASE
, gs_base
);
2931 host_state
->gs_base
= gs_base
;
2934 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2935 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2936 vmx
->guest_msrs
[i
].data
,
2937 vmx
->guest_msrs
[i
].mask
);
2940 static void vmx_prepare_switch_to_host(struct vcpu_vmx
*vmx
)
2942 struct vmcs_host_state
*host_state
;
2944 if (!vmx
->loaded_cpu_state
)
2947 WARN_ON_ONCE(vmx
->loaded_cpu_state
!= vmx
->loaded_vmcs
);
2948 host_state
= &vmx
->loaded_cpu_state
->host_state
;
2950 ++vmx
->vcpu
.stat
.host_state_reload
;
2951 vmx
->loaded_cpu_state
= NULL
;
2953 #ifdef CONFIG_X86_64
2954 if (is_long_mode(&vmx
->vcpu
))
2955 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2957 if (host_state
->ldt_sel
|| (host_state
->gs_sel
& 7)) {
2958 kvm_load_ldt(host_state
->ldt_sel
);
2959 #ifdef CONFIG_X86_64
2960 load_gs_index(host_state
->gs_sel
);
2962 loadsegment(gs
, host_state
->gs_sel
);
2965 if (host_state
->fs_sel
& 7)
2966 loadsegment(fs
, host_state
->fs_sel
);
2967 #ifdef CONFIG_X86_64
2968 if (unlikely(host_state
->ds_sel
| host_state
->es_sel
)) {
2969 loadsegment(ds
, host_state
->ds_sel
);
2970 loadsegment(es
, host_state
->es_sel
);
2973 invalidate_tss_limit();
2974 #ifdef CONFIG_X86_64
2975 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2977 load_fixmap_gdt(raw_smp_processor_id());
2980 #ifdef CONFIG_X86_64
2981 static u64
vmx_read_guest_kernel_gs_base(struct vcpu_vmx
*vmx
)
2983 if (is_long_mode(&vmx
->vcpu
)) {
2985 if (vmx
->loaded_cpu_state
)
2986 rdmsrl(MSR_KERNEL_GS_BASE
,
2987 vmx
->msr_guest_kernel_gs_base
);
2990 return vmx
->msr_guest_kernel_gs_base
;
2993 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx
*vmx
, u64 data
)
2995 if (is_long_mode(&vmx
->vcpu
)) {
2997 if (vmx
->loaded_cpu_state
)
2998 wrmsrl(MSR_KERNEL_GS_BASE
, data
);
3001 vmx
->msr_guest_kernel_gs_base
= data
;
3005 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
3007 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
3008 struct pi_desc old
, new;
3012 * In case of hot-plug or hot-unplug, we may have to undo
3013 * vmx_vcpu_pi_put even if there is no assigned device. And we
3014 * always keep PI.NDST up to date for simplicity: it makes the
3015 * code easier, and CPU migration is not a fast path.
3017 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
3021 * First handle the simple case where no cmpxchg is necessary; just
3022 * allow posting non-urgent interrupts.
3024 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
3025 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
3026 * expects the VCPU to be on the blocked_vcpu_list that matches
3029 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
3031 pi_clear_sn(pi_desc
);
3035 /* The full case. */
3037 old
.control
= new.control
= pi_desc
->control
;
3039 dest
= cpu_physical_id(cpu
);
3041 if (x2apic_enabled())
3044 new.ndst
= (dest
<< 8) & 0xFF00;
3047 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
3048 new.control
) != old
.control
);
3051 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
3053 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
3054 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
3058 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
3059 * vcpu mutex is already taken.
3061 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
3063 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3064 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
3066 if (!already_loaded
) {
3067 loaded_vmcs_clear(vmx
->loaded_vmcs
);
3068 local_irq_disable();
3069 crash_disable_local_vmclear(cpu
);
3072 * Read loaded_vmcs->cpu should be before fetching
3073 * loaded_vmcs->loaded_vmcss_on_cpu_link.
3074 * See the comments in __loaded_vmcs_clear().
3078 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
3079 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
3080 crash_enable_local_vmclear(cpu
);
3084 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
3085 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
3086 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
3087 indirect_branch_prediction_barrier();
3090 if (!already_loaded
) {
3091 void *gdt
= get_current_gdt_ro();
3092 unsigned long sysenter_esp
;
3094 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
3097 * Linux uses per-cpu TSS and GDT, so set these when switching
3098 * processors. See 22.2.4.
3100 vmcs_writel(HOST_TR_BASE
,
3101 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
3102 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
3105 * VM exits change the host TR limit to 0x67 after a VM
3106 * exit. This is okay, since 0x67 covers everything except
3107 * the IO bitmap and have have code to handle the IO bitmap
3108 * being lost after a VM exit.
3110 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
3112 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
3113 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
3115 vmx
->loaded_vmcs
->cpu
= cpu
;
3118 /* Setup TSC multiplier */
3119 if (kvm_has_tsc_control
&&
3120 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
3121 decache_tsc_multiplier(vmx
);
3123 vmx_vcpu_pi_load(vcpu
, cpu
);
3124 vmx
->host_pkru
= read_pkru();
3125 vmx
->host_debugctlmsr
= get_debugctlmsr();
3128 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
3130 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
3132 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
3133 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
3134 !kvm_vcpu_apicv_active(vcpu
))
3137 /* Set SN when the vCPU is preempted */
3138 if (vcpu
->preempted
)
3142 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
3144 vmx_vcpu_pi_put(vcpu
);
3146 vmx_prepare_switch_to_host(to_vmx(vcpu
));
3149 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3151 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3154 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
3157 * Return the cr0 value that a nested guest would read. This is a combination
3158 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
3159 * its hypervisor (cr0_read_shadow).
3161 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
3163 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
3164 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
3166 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
3168 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
3169 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
3172 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
3174 unsigned long rflags
, save_rflags
;
3176 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3177 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
3178 rflags
= vmcs_readl(GUEST_RFLAGS
);
3179 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3180 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3181 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
3182 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3184 to_vmx(vcpu
)->rflags
= rflags
;
3186 return to_vmx(vcpu
)->rflags
;
3189 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
3191 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
3193 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
3194 to_vmx(vcpu
)->rflags
= rflags
;
3195 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3196 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
3197 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3199 vmcs_writel(GUEST_RFLAGS
, rflags
);
3201 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
3202 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
3205 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
3207 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
3210 if (interruptibility
& GUEST_INTR_STATE_STI
)
3211 ret
|= KVM_X86_SHADOW_INT_STI
;
3212 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
3213 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
3218 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
3220 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
3221 u32 interruptibility
= interruptibility_old
;
3223 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
3225 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
3226 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
3227 else if (mask
& KVM_X86_SHADOW_INT_STI
)
3228 interruptibility
|= GUEST_INTR_STATE_STI
;
3230 if ((interruptibility
!= interruptibility_old
))
3231 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
3234 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
3238 rip
= kvm_rip_read(vcpu
);
3239 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3240 kvm_rip_write(vcpu
, rip
);
3242 /* skipping an emulated instruction also counts */
3243 vmx_set_interrupt_shadow(vcpu
, 0);
3246 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
3247 unsigned long exit_qual
)
3249 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
3250 unsigned int nr
= vcpu
->arch
.exception
.nr
;
3251 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
3253 if (vcpu
->arch
.exception
.has_error_code
) {
3254 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
3255 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
3258 if (kvm_exception_is_soft(nr
))
3259 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
3261 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
3263 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
3264 vmx_get_nmi_mask(vcpu
))
3265 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
3267 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
3271 * KVM wants to inject page-faults which it got to the guest. This function
3272 * checks whether in a nested guest, we need to inject them to L1 or L2.
3274 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
3276 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
3277 unsigned int nr
= vcpu
->arch
.exception
.nr
;
3279 if (nr
== PF_VECTOR
) {
3280 if (vcpu
->arch
.exception
.nested_apf
) {
3281 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
3285 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
3286 * The fix is to add the ancillary datum (CR2 or DR6) to structs
3287 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
3288 * can be written only when inject_pending_event runs. This should be
3289 * conditional on a new capability---if the capability is disabled,
3290 * kvm_multiple_exception would write the ancillary information to
3291 * CR2 or DR6, for backwards ABI-compatibility.
3293 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
3294 vcpu
->arch
.exception
.error_code
)) {
3295 *exit_qual
= vcpu
->arch
.cr2
;
3299 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
3300 if (nr
== DB_VECTOR
)
3301 *exit_qual
= vcpu
->arch
.dr6
;
3311 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
3314 * Ensure that we clear the HLT state in the VMCS. We don't need to
3315 * explicitly skip the instruction because if the HLT state is set,
3316 * then the instruction is already executing and RIP has already been
3319 if (kvm_hlt_in_guest(vcpu
->kvm
) &&
3320 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
3321 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3324 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
3326 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3327 unsigned nr
= vcpu
->arch
.exception
.nr
;
3328 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
3329 u32 error_code
= vcpu
->arch
.exception
.error_code
;
3330 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
3332 if (has_error_code
) {
3333 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
3334 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
3337 if (vmx
->rmode
.vm86_active
) {
3339 if (kvm_exception_is_soft(nr
))
3340 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
3341 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
3342 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3346 WARN_ON_ONCE(vmx
->emulation_required
);
3348 if (kvm_exception_is_soft(nr
)) {
3349 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
3350 vmx
->vcpu
.arch
.event_exit_inst_len
);
3351 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
3353 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
3355 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
3357 vmx_clear_hlt(vcpu
);
3360 static bool vmx_rdtscp_supported(void)
3362 return cpu_has_vmx_rdtscp();
3365 static bool vmx_invpcid_supported(void)
3367 return cpu_has_vmx_invpcid();
3371 * Swap MSR entry in host/guest MSR entry array.
3373 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
3375 struct shared_msr_entry tmp
;
3377 tmp
= vmx
->guest_msrs
[to
];
3378 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
3379 vmx
->guest_msrs
[from
] = tmp
;
3383 * Set up the vmcs to automatically save and restore system
3384 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
3385 * mode, as fiddling with msrs is very expensive.
3387 static void setup_msrs(struct vcpu_vmx
*vmx
)
3389 int save_nmsrs
, index
;
3392 #ifdef CONFIG_X86_64
3393 if (is_long_mode(&vmx
->vcpu
)) {
3394 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
3396 move_msr_up(vmx
, index
, save_nmsrs
++);
3397 index
= __find_msr_index(vmx
, MSR_LSTAR
);
3399 move_msr_up(vmx
, index
, save_nmsrs
++);
3400 index
= __find_msr_index(vmx
, MSR_CSTAR
);
3402 move_msr_up(vmx
, index
, save_nmsrs
++);
3403 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
3404 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
3405 move_msr_up(vmx
, index
, save_nmsrs
++);
3407 * MSR_STAR is only needed on long mode guests, and only
3408 * if efer.sce is enabled.
3410 index
= __find_msr_index(vmx
, MSR_STAR
);
3411 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
3412 move_msr_up(vmx
, index
, save_nmsrs
++);
3415 index
= __find_msr_index(vmx
, MSR_EFER
);
3416 if (index
>= 0 && update_transition_efer(vmx
, index
))
3417 move_msr_up(vmx
, index
, save_nmsrs
++);
3419 vmx
->save_nmsrs
= save_nmsrs
;
3421 if (cpu_has_vmx_msr_bitmap())
3422 vmx_update_msr_bitmap(&vmx
->vcpu
);
3425 static u64
vmx_read_l1_tsc_offset(struct kvm_vcpu
*vcpu
)
3427 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
3429 if (is_guest_mode(vcpu
) &&
3430 (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
))
3431 return vcpu
->arch
.tsc_offset
- vmcs12
->tsc_offset
;
3433 return vcpu
->arch
.tsc_offset
;
3437 * writes 'offset' into guest's timestamp counter offset register
3439 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
3441 if (is_guest_mode(vcpu
)) {
3443 * We're here if L1 chose not to trap WRMSR to TSC. According
3444 * to the spec, this should set L1's TSC; The offset that L1
3445 * set for L2 remains unchanged, and still needs to be added
3446 * to the newly set TSC to get L2's TSC.
3448 struct vmcs12
*vmcs12
;
3449 /* recalculate vmcs02.TSC_OFFSET: */
3450 vmcs12
= get_vmcs12(vcpu
);
3451 vmcs_write64(TSC_OFFSET
, offset
+
3452 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
3453 vmcs12
->tsc_offset
: 0));
3455 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
3456 vmcs_read64(TSC_OFFSET
), offset
);
3457 vmcs_write64(TSC_OFFSET
, offset
);
3462 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
3463 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
3464 * all guests if the "nested" module option is off, and can also be disabled
3465 * for a single guest by disabling its VMX cpuid bit.
3467 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
3469 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
3473 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
3474 * returned for the various VMX controls MSRs when nested VMX is enabled.
3475 * The same values should also be used to verify that vmcs12 control fields are
3476 * valid during nested entry from L1 to L2.
3477 * Each of these control msrs has a low and high 32-bit half: A low bit is on
3478 * if the corresponding bit in the (32-bit) control field *must* be on, and a
3479 * bit in the high half is on if the corresponding bit in the control field
3480 * may be on. See also vmx_control_verify().
3482 static void nested_vmx_setup_ctls_msrs(struct nested_vmx_msrs
*msrs
, bool apicv
)
3485 memset(msrs
, 0, sizeof(*msrs
));
3490 * Note that as a general rule, the high half of the MSRs (bits in
3491 * the control fields which may be 1) should be initialized by the
3492 * intersection of the underlying hardware's MSR (i.e., features which
3493 * can be supported) and the list of features we want to expose -
3494 * because they are known to be properly supported in our code.
3495 * Also, usually, the low half of the MSRs (bits which must be 1) can
3496 * be set to 0, meaning that L1 may turn off any of these bits. The
3497 * reason is that if one of these bits is necessary, it will appear
3498 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
3499 * fields of vmcs01 and vmcs02, will turn these bits off - and
3500 * nested_vmx_exit_reflected() will not pass related exits to L1.
3501 * These rules have exceptions below.
3504 /* pin-based controls */
3505 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
3506 msrs
->pinbased_ctls_low
,
3507 msrs
->pinbased_ctls_high
);
3508 msrs
->pinbased_ctls_low
|=
3509 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3510 msrs
->pinbased_ctls_high
&=
3511 PIN_BASED_EXT_INTR_MASK
|
3512 PIN_BASED_NMI_EXITING
|
3513 PIN_BASED_VIRTUAL_NMIS
|
3514 (apicv
? PIN_BASED_POSTED_INTR
: 0);
3515 msrs
->pinbased_ctls_high
|=
3516 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
3517 PIN_BASED_VMX_PREEMPTION_TIMER
;
3520 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
3521 msrs
->exit_ctls_low
,
3522 msrs
->exit_ctls_high
);
3523 msrs
->exit_ctls_low
=
3524 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3526 msrs
->exit_ctls_high
&=
3527 #ifdef CONFIG_X86_64
3528 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
3530 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
3531 msrs
->exit_ctls_high
|=
3532 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
3533 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
3534 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
3536 if (kvm_mpx_supported())
3537 msrs
->exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
3539 /* We support free control of debug control saving. */
3540 msrs
->exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
3542 /* entry controls */
3543 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
3544 msrs
->entry_ctls_low
,
3545 msrs
->entry_ctls_high
);
3546 msrs
->entry_ctls_low
=
3547 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3548 msrs
->entry_ctls_high
&=
3549 #ifdef CONFIG_X86_64
3550 VM_ENTRY_IA32E_MODE
|
3552 VM_ENTRY_LOAD_IA32_PAT
;
3553 msrs
->entry_ctls_high
|=
3554 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
3555 if (kvm_mpx_supported())
3556 msrs
->entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
3558 /* We support free control of debug control loading. */
3559 msrs
->entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3561 /* cpu-based controls */
3562 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
3563 msrs
->procbased_ctls_low
,
3564 msrs
->procbased_ctls_high
);
3565 msrs
->procbased_ctls_low
=
3566 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3567 msrs
->procbased_ctls_high
&=
3568 CPU_BASED_VIRTUAL_INTR_PENDING
|
3569 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
3570 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
3571 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
3572 CPU_BASED_CR3_STORE_EXITING
|
3573 #ifdef CONFIG_X86_64
3574 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
3576 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
3577 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
3578 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
3579 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
3580 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3582 * We can allow some features even when not supported by the
3583 * hardware. For example, L1 can specify an MSR bitmap - and we
3584 * can use it to avoid exits to L1 - even when L0 runs L2
3585 * without MSR bitmaps.
3587 msrs
->procbased_ctls_high
|=
3588 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
3589 CPU_BASED_USE_MSR_BITMAPS
;
3591 /* We support free control of CR3 access interception. */
3592 msrs
->procbased_ctls_low
&=
3593 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
3596 * secondary cpu-based controls. Do not include those that
3597 * depend on CPUID bits, they are added later by vmx_cpuid_update.
3599 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
3600 msrs
->secondary_ctls_low
,
3601 msrs
->secondary_ctls_high
);
3602 msrs
->secondary_ctls_low
= 0;
3603 msrs
->secondary_ctls_high
&=
3604 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3605 SECONDARY_EXEC_DESC
|
3606 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3607 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3608 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3609 SECONDARY_EXEC_WBINVD_EXITING
;
3611 * We can emulate "VMCS shadowing," even if the hardware
3612 * doesn't support it.
3614 msrs
->secondary_ctls_high
|=
3615 SECONDARY_EXEC_SHADOW_VMCS
;
3618 /* nested EPT: emulate EPT also to L1 */
3619 msrs
->secondary_ctls_high
|=
3620 SECONDARY_EXEC_ENABLE_EPT
;
3621 msrs
->ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
3622 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
3623 if (cpu_has_vmx_ept_execute_only())
3625 VMX_EPT_EXECUTE_ONLY_BIT
;
3626 msrs
->ept_caps
&= vmx_capability
.ept
;
3627 msrs
->ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
3628 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
3629 VMX_EPT_1GB_PAGE_BIT
;
3630 if (enable_ept_ad_bits
) {
3631 msrs
->secondary_ctls_high
|=
3632 SECONDARY_EXEC_ENABLE_PML
;
3633 msrs
->ept_caps
|= VMX_EPT_AD_BIT
;
3637 if (cpu_has_vmx_vmfunc()) {
3638 msrs
->secondary_ctls_high
|=
3639 SECONDARY_EXEC_ENABLE_VMFUNC
;
3641 * Advertise EPTP switching unconditionally
3642 * since we emulate it
3645 msrs
->vmfunc_controls
=
3646 VMX_VMFUNC_EPTP_SWITCHING
;
3650 * Old versions of KVM use the single-context version without
3651 * checking for support, so declare that it is supported even
3652 * though it is treated as global context. The alternative is
3653 * not failing the single-context invvpid, and it is worse.
3656 msrs
->secondary_ctls_high
|=
3657 SECONDARY_EXEC_ENABLE_VPID
;
3658 msrs
->vpid_caps
= VMX_VPID_INVVPID_BIT
|
3659 VMX_VPID_EXTENT_SUPPORTED_MASK
;
3662 if (enable_unrestricted_guest
)
3663 msrs
->secondary_ctls_high
|=
3664 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3666 /* miscellaneous data */
3667 rdmsr(MSR_IA32_VMX_MISC
,
3670 msrs
->misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
3672 MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
|
3673 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
3674 VMX_MISC_ACTIVITY_HLT
;
3675 msrs
->misc_high
= 0;
3678 * This MSR reports some information about VMX support. We
3679 * should return information about the VMX we emulate for the
3680 * guest, and the VMCS structure we give it - not about the
3681 * VMX support of the underlying hardware.
3685 VMX_BASIC_TRUE_CTLS
|
3686 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
3687 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
3689 if (cpu_has_vmx_basic_inout())
3690 msrs
->basic
|= VMX_BASIC_INOUT
;
3693 * These MSRs specify bits which the guest must keep fixed on
3694 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
3695 * We picked the standard core2 setting.
3697 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
3698 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
3699 msrs
->cr0_fixed0
= VMXON_CR0_ALWAYSON
;
3700 msrs
->cr4_fixed0
= VMXON_CR4_ALWAYSON
;
3702 /* These MSRs specify bits which the guest must keep fixed off. */
3703 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, msrs
->cr0_fixed1
);
3704 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, msrs
->cr4_fixed1
);
3706 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
3707 msrs
->vmcs_enum
= VMCS12_MAX_FIELD_INDEX
<< 1;
3711 * if fixed0[i] == 1: val[i] must be 1
3712 * if fixed1[i] == 0: val[i] must be 0
3714 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
3716 return ((val
& fixed1
) | fixed0
) == val
;
3719 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
3721 return fixed_bits_valid(control
, low
, high
);
3724 static inline u64
vmx_control_msr(u32 low
, u32 high
)
3726 return low
| ((u64
)high
<< 32);
3729 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
3734 return (superset
| subset
) == superset
;
3737 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
3739 const u64 feature_and_reserved
=
3740 /* feature (except bit 48; see below) */
3741 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
3743 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
3744 u64 vmx_basic
= vmx
->nested
.msrs
.basic
;
3746 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
3750 * KVM does not emulate a version of VMX that constrains physical
3751 * addresses of VMX structures (e.g. VMCS) to 32-bits.
3753 if (data
& BIT_ULL(48))
3756 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
3757 vmx_basic_vmcs_revision_id(data
))
3760 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
3763 vmx
->nested
.msrs
.basic
= data
;
3768 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3773 switch (msr_index
) {
3774 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3775 lowp
= &vmx
->nested
.msrs
.pinbased_ctls_low
;
3776 highp
= &vmx
->nested
.msrs
.pinbased_ctls_high
;
3778 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3779 lowp
= &vmx
->nested
.msrs
.procbased_ctls_low
;
3780 highp
= &vmx
->nested
.msrs
.procbased_ctls_high
;
3782 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3783 lowp
= &vmx
->nested
.msrs
.exit_ctls_low
;
3784 highp
= &vmx
->nested
.msrs
.exit_ctls_high
;
3786 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3787 lowp
= &vmx
->nested
.msrs
.entry_ctls_low
;
3788 highp
= &vmx
->nested
.msrs
.entry_ctls_high
;
3790 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3791 lowp
= &vmx
->nested
.msrs
.secondary_ctls_low
;
3792 highp
= &vmx
->nested
.msrs
.secondary_ctls_high
;
3798 supported
= vmx_control_msr(*lowp
, *highp
);
3800 /* Check must-be-1 bits are still 1. */
3801 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3804 /* Check must-be-0 bits are still 0. */
3805 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3809 *highp
= data
>> 32;
3813 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3815 const u64 feature_and_reserved_bits
=
3817 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3818 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3820 GENMASK_ULL(13, 9) | BIT_ULL(31);
3823 vmx_misc
= vmx_control_msr(vmx
->nested
.msrs
.misc_low
,
3824 vmx
->nested
.msrs
.misc_high
);
3826 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3829 if ((vmx
->nested
.msrs
.pinbased_ctls_high
&
3830 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3831 vmx_misc_preemption_timer_rate(data
) !=
3832 vmx_misc_preemption_timer_rate(vmx_misc
))
3835 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3838 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3841 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3844 vmx
->nested
.msrs
.misc_low
= data
;
3845 vmx
->nested
.msrs
.misc_high
= data
>> 32;
3848 * If L1 has read-only VM-exit information fields, use the
3849 * less permissive vmx_vmwrite_bitmap to specify write
3850 * permissions for the shadow VMCS.
3852 if (enable_shadow_vmcs
&& !nested_cpu_has_vmwrite_any_field(&vmx
->vcpu
))
3853 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
3858 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3860 u64 vmx_ept_vpid_cap
;
3862 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.msrs
.ept_caps
,
3863 vmx
->nested
.msrs
.vpid_caps
);
3865 /* Every bit is either reserved or a feature bit. */
3866 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3869 vmx
->nested
.msrs
.ept_caps
= data
;
3870 vmx
->nested
.msrs
.vpid_caps
= data
>> 32;
3874 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3878 switch (msr_index
) {
3879 case MSR_IA32_VMX_CR0_FIXED0
:
3880 msr
= &vmx
->nested
.msrs
.cr0_fixed0
;
3882 case MSR_IA32_VMX_CR4_FIXED0
:
3883 msr
= &vmx
->nested
.msrs
.cr4_fixed0
;
3890 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3891 * must be 1 in the restored value.
3893 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3901 * Called when userspace is restoring VMX MSRs.
3903 * Returns 0 on success, non-0 otherwise.
3905 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3907 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3910 * Don't allow changes to the VMX capability MSRs while the vCPU
3911 * is in VMX operation.
3913 if (vmx
->nested
.vmxon
)
3916 switch (msr_index
) {
3917 case MSR_IA32_VMX_BASIC
:
3918 return vmx_restore_vmx_basic(vmx
, data
);
3919 case MSR_IA32_VMX_PINBASED_CTLS
:
3920 case MSR_IA32_VMX_PROCBASED_CTLS
:
3921 case MSR_IA32_VMX_EXIT_CTLS
:
3922 case MSR_IA32_VMX_ENTRY_CTLS
:
3924 * The "non-true" VMX capability MSRs are generated from the
3925 * "true" MSRs, so we do not support restoring them directly.
3927 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3928 * should restore the "true" MSRs with the must-be-1 bits
3929 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3930 * DEFAULT SETTINGS".
3933 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3934 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3935 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3936 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3937 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3938 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3939 case MSR_IA32_VMX_MISC
:
3940 return vmx_restore_vmx_misc(vmx
, data
);
3941 case MSR_IA32_VMX_CR0_FIXED0
:
3942 case MSR_IA32_VMX_CR4_FIXED0
:
3943 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3944 case MSR_IA32_VMX_CR0_FIXED1
:
3945 case MSR_IA32_VMX_CR4_FIXED1
:
3947 * These MSRs are generated based on the vCPU's CPUID, so we
3948 * do not support restoring them directly.
3951 case MSR_IA32_VMX_EPT_VPID_CAP
:
3952 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3953 case MSR_IA32_VMX_VMCS_ENUM
:
3954 vmx
->nested
.msrs
.vmcs_enum
= data
;
3958 * The rest of the VMX capability MSRs do not support restore.
3964 /* Returns 0 on success, non-0 otherwise. */
3965 static int vmx_get_vmx_msr(struct nested_vmx_msrs
*msrs
, u32 msr_index
, u64
*pdata
)
3967 switch (msr_index
) {
3968 case MSR_IA32_VMX_BASIC
:
3969 *pdata
= msrs
->basic
;
3971 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3972 case MSR_IA32_VMX_PINBASED_CTLS
:
3973 *pdata
= vmx_control_msr(
3974 msrs
->pinbased_ctls_low
,
3975 msrs
->pinbased_ctls_high
);
3976 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3977 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3979 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3980 case MSR_IA32_VMX_PROCBASED_CTLS
:
3981 *pdata
= vmx_control_msr(
3982 msrs
->procbased_ctls_low
,
3983 msrs
->procbased_ctls_high
);
3984 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3985 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3987 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3988 case MSR_IA32_VMX_EXIT_CTLS
:
3989 *pdata
= vmx_control_msr(
3990 msrs
->exit_ctls_low
,
3991 msrs
->exit_ctls_high
);
3992 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3993 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3995 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3996 case MSR_IA32_VMX_ENTRY_CTLS
:
3997 *pdata
= vmx_control_msr(
3998 msrs
->entry_ctls_low
,
3999 msrs
->entry_ctls_high
);
4000 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
4001 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
4003 case MSR_IA32_VMX_MISC
:
4004 *pdata
= vmx_control_msr(
4008 case MSR_IA32_VMX_CR0_FIXED0
:
4009 *pdata
= msrs
->cr0_fixed0
;
4011 case MSR_IA32_VMX_CR0_FIXED1
:
4012 *pdata
= msrs
->cr0_fixed1
;
4014 case MSR_IA32_VMX_CR4_FIXED0
:
4015 *pdata
= msrs
->cr4_fixed0
;
4017 case MSR_IA32_VMX_CR4_FIXED1
:
4018 *pdata
= msrs
->cr4_fixed1
;
4020 case MSR_IA32_VMX_VMCS_ENUM
:
4021 *pdata
= msrs
->vmcs_enum
;
4023 case MSR_IA32_VMX_PROCBASED_CTLS2
:
4024 *pdata
= vmx_control_msr(
4025 msrs
->secondary_ctls_low
,
4026 msrs
->secondary_ctls_high
);
4028 case MSR_IA32_VMX_EPT_VPID_CAP
:
4029 *pdata
= msrs
->ept_caps
|
4030 ((u64
)msrs
->vpid_caps
<< 32);
4032 case MSR_IA32_VMX_VMFUNC
:
4033 *pdata
= msrs
->vmfunc_controls
;
4042 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
4045 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
4047 return !(val
& ~valid_bits
);
4050 static int vmx_get_msr_feature(struct kvm_msr_entry
*msr
)
4052 switch (msr
->index
) {
4053 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
4056 return vmx_get_vmx_msr(&vmcs_config
.nested
, msr
->index
, &msr
->data
);
4065 * Reads an msr value (of 'msr_index') into 'pdata'.
4066 * Returns 0 on success, non-0 otherwise.
4067 * Assumes vcpu_load() was already called.
4069 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4071 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4072 struct shared_msr_entry
*msr
;
4074 switch (msr_info
->index
) {
4075 #ifdef CONFIG_X86_64
4077 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
4080 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
4082 case MSR_KERNEL_GS_BASE
:
4083 msr_info
->data
= vmx_read_guest_kernel_gs_base(vmx
);
4087 return kvm_get_msr_common(vcpu
, msr_info
);
4088 case MSR_IA32_SPEC_CTRL
:
4089 if (!msr_info
->host_initiated
&&
4090 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
4093 msr_info
->data
= to_vmx(vcpu
)->spec_ctrl
;
4095 case MSR_IA32_ARCH_CAPABILITIES
:
4096 if (!msr_info
->host_initiated
&&
4097 !guest_cpuid_has(vcpu
, X86_FEATURE_ARCH_CAPABILITIES
))
4099 msr_info
->data
= to_vmx(vcpu
)->arch_capabilities
;
4101 case MSR_IA32_SYSENTER_CS
:
4102 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
4104 case MSR_IA32_SYSENTER_EIP
:
4105 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
4107 case MSR_IA32_SYSENTER_ESP
:
4108 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
4110 case MSR_IA32_BNDCFGS
:
4111 if (!kvm_mpx_supported() ||
4112 (!msr_info
->host_initiated
&&
4113 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
4115 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
4117 case MSR_IA32_MCG_EXT_CTL
:
4118 if (!msr_info
->host_initiated
&&
4119 !(vmx
->msr_ia32_feature_control
&
4120 FEATURE_CONTROL_LMCE
))
4122 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
4124 case MSR_IA32_FEATURE_CONTROL
:
4125 msr_info
->data
= vmx
->msr_ia32_feature_control
;
4127 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
4128 if (!nested_vmx_allowed(vcpu
))
4130 return vmx_get_vmx_msr(&vmx
->nested
.msrs
, msr_info
->index
,
4133 if (!vmx_xsaves_supported())
4135 msr_info
->data
= vcpu
->arch
.ia32_xss
;
4138 if (!msr_info
->host_initiated
&&
4139 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
4141 /* Otherwise falls through */
4143 msr
= find_msr_entry(vmx
, msr_info
->index
);
4145 msr_info
->data
= msr
->data
;
4148 return kvm_get_msr_common(vcpu
, msr_info
);
4154 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
4157 * Writes msr value into into the appropriate "register".
4158 * Returns 0 on success, non-0 otherwise.
4159 * Assumes vcpu_load() was already called.
4161 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
4163 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4164 struct shared_msr_entry
*msr
;
4166 u32 msr_index
= msr_info
->index
;
4167 u64 data
= msr_info
->data
;
4169 switch (msr_index
) {
4171 ret
= kvm_set_msr_common(vcpu
, msr_info
);
4173 #ifdef CONFIG_X86_64
4175 vmx_segment_cache_clear(vmx
);
4176 vmcs_writel(GUEST_FS_BASE
, data
);
4179 vmx_segment_cache_clear(vmx
);
4180 vmcs_writel(GUEST_GS_BASE
, data
);
4182 case MSR_KERNEL_GS_BASE
:
4183 vmx_write_guest_kernel_gs_base(vmx
, data
);
4186 case MSR_IA32_SYSENTER_CS
:
4187 vmcs_write32(GUEST_SYSENTER_CS
, data
);
4189 case MSR_IA32_SYSENTER_EIP
:
4190 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
4192 case MSR_IA32_SYSENTER_ESP
:
4193 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
4195 case MSR_IA32_BNDCFGS
:
4196 if (!kvm_mpx_supported() ||
4197 (!msr_info
->host_initiated
&&
4198 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
4200 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
4201 (data
& MSR_IA32_BNDCFGS_RSVD
))
4203 vmcs_write64(GUEST_BNDCFGS
, data
);
4205 case MSR_IA32_SPEC_CTRL
:
4206 if (!msr_info
->host_initiated
&&
4207 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
4210 /* The STIBP bit doesn't fault even if it's not advertised */
4211 if (data
& ~(SPEC_CTRL_IBRS
| SPEC_CTRL_STIBP
| SPEC_CTRL_SSBD
))
4214 vmx
->spec_ctrl
= data
;
4221 * When it's written (to non-zero) for the first time, pass
4225 * The handling of the MSR bitmap for L2 guests is done in
4226 * nested_vmx_merge_msr_bitmap. We should not touch the
4227 * vmcs02.msr_bitmap here since it gets completely overwritten
4228 * in the merging. We update the vmcs01 here for L1 as well
4229 * since it will end up touching the MSR anyway now.
4231 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
,
4235 case MSR_IA32_PRED_CMD
:
4236 if (!msr_info
->host_initiated
&&
4237 !guest_cpuid_has(vcpu
, X86_FEATURE_SPEC_CTRL
))
4240 if (data
& ~PRED_CMD_IBPB
)
4246 wrmsrl(MSR_IA32_PRED_CMD
, PRED_CMD_IBPB
);
4250 * When it's written (to non-zero) for the first time, pass
4254 * The handling of the MSR bitmap for L2 guests is done in
4255 * nested_vmx_merge_msr_bitmap. We should not touch the
4256 * vmcs02.msr_bitmap here since it gets completely overwritten
4259 vmx_disable_intercept_for_msr(vmx
->vmcs01
.msr_bitmap
, MSR_IA32_PRED_CMD
,
4262 case MSR_IA32_ARCH_CAPABILITIES
:
4263 if (!msr_info
->host_initiated
)
4265 vmx
->arch_capabilities
= data
;
4267 case MSR_IA32_CR_PAT
:
4268 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4269 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
4271 vmcs_write64(GUEST_IA32_PAT
, data
);
4272 vcpu
->arch
.pat
= data
;
4275 ret
= kvm_set_msr_common(vcpu
, msr_info
);
4277 case MSR_IA32_TSC_ADJUST
:
4278 ret
= kvm_set_msr_common(vcpu
, msr_info
);
4280 case MSR_IA32_MCG_EXT_CTL
:
4281 if ((!msr_info
->host_initiated
&&
4282 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
4283 FEATURE_CONTROL_LMCE
)) ||
4284 (data
& ~MCG_EXT_CTL_LMCE_EN
))
4286 vcpu
->arch
.mcg_ext_ctl
= data
;
4288 case MSR_IA32_FEATURE_CONTROL
:
4289 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
4290 (to_vmx(vcpu
)->msr_ia32_feature_control
&
4291 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
4293 vmx
->msr_ia32_feature_control
= data
;
4294 if (msr_info
->host_initiated
&& data
== 0)
4295 vmx_leave_nested(vcpu
);
4297 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
4298 if (!msr_info
->host_initiated
)
4299 return 1; /* they are read-only */
4300 if (!nested_vmx_allowed(vcpu
))
4302 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
4304 if (!vmx_xsaves_supported())
4307 * The only supported bit as of Skylake is bit 8, but
4308 * it is not supported on KVM.
4312 vcpu
->arch
.ia32_xss
= data
;
4313 if (vcpu
->arch
.ia32_xss
!= host_xss
)
4314 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
4315 vcpu
->arch
.ia32_xss
, host_xss
, false);
4317 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
4320 if (!msr_info
->host_initiated
&&
4321 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
4323 /* Check reserved bit, higher 32 bits should be zero */
4324 if ((data
>> 32) != 0)
4326 /* Otherwise falls through */
4328 msr
= find_msr_entry(vmx
, msr_index
);
4330 u64 old_msr_data
= msr
->data
;
4332 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
4334 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
4338 msr
->data
= old_msr_data
;
4342 ret
= kvm_set_msr_common(vcpu
, msr_info
);
4348 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
4350 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
4353 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
4356 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
4358 case VCPU_EXREG_PDPTR
:
4360 ept_save_pdptrs(vcpu
);
4367 static __init
int cpu_has_kvm_support(void)
4369 return cpu_has_vmx();
4372 static __init
int vmx_disabled_by_bios(void)
4376 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
4377 if (msr
& FEATURE_CONTROL_LOCKED
) {
4378 /* launched w/ TXT and VMX disabled */
4379 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
4382 /* launched w/o TXT and VMX only enabled w/ TXT */
4383 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
4384 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
4385 && !tboot_enabled()) {
4386 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
4387 "activate TXT before enabling KVM\n");
4390 /* launched w/o TXT and VMX disabled */
4391 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
4392 && !tboot_enabled())
4399 static void kvm_cpu_vmxon(u64 addr
)
4401 cr4_set_bits(X86_CR4_VMXE
);
4402 intel_pt_handle_vmx(1);
4404 asm volatile (ASM_VMX_VMXON_RAX
4405 : : "a"(&addr
), "m"(addr
)
4409 static int hardware_enable(void)
4411 int cpu
= raw_smp_processor_id();
4412 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
4415 if (cr4_read_shadow() & X86_CR4_VMXE
)
4419 * This can happen if we hot-added a CPU but failed to allocate
4420 * VP assist page for it.
4422 if (static_branch_unlikely(&enable_evmcs
) &&
4423 !hv_get_vp_assist_page(cpu
))
4426 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
4427 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
4428 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
4431 * Now we can enable the vmclear operation in kdump
4432 * since the loaded_vmcss_on_cpu list on this cpu
4433 * has been initialized.
4435 * Though the cpu is not in VMX operation now, there
4436 * is no problem to enable the vmclear operation
4437 * for the loaded_vmcss_on_cpu list is empty!
4439 crash_enable_local_vmclear(cpu
);
4441 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
4443 test_bits
= FEATURE_CONTROL_LOCKED
;
4444 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
4445 if (tboot_enabled())
4446 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
4448 if ((old
& test_bits
) != test_bits
) {
4449 /* enable and lock */
4450 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
4452 kvm_cpu_vmxon(phys_addr
);
4459 static void vmclear_local_loaded_vmcss(void)
4461 int cpu
= raw_smp_processor_id();
4462 struct loaded_vmcs
*v
, *n
;
4464 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
4465 loaded_vmcss_on_cpu_link
)
4466 __loaded_vmcs_clear(v
);
4470 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
4473 static void kvm_cpu_vmxoff(void)
4475 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
4477 intel_pt_handle_vmx(0);
4478 cr4_clear_bits(X86_CR4_VMXE
);
4481 static void hardware_disable(void)
4483 vmclear_local_loaded_vmcss();
4487 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
4488 u32 msr
, u32
*result
)
4490 u32 vmx_msr_low
, vmx_msr_high
;
4491 u32 ctl
= ctl_min
| ctl_opt
;
4493 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
4495 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
4496 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
4498 /* Ensure minimum (required) set of control bits are supported. */
4506 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
4508 u32 vmx_msr_low
, vmx_msr_high
;
4510 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
4511 return vmx_msr_high
& ctl
;
4514 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
4516 u32 vmx_msr_low
, vmx_msr_high
;
4517 u32 min
, opt
, min2
, opt2
;
4518 u32 _pin_based_exec_control
= 0;
4519 u32 _cpu_based_exec_control
= 0;
4520 u32 _cpu_based_2nd_exec_control
= 0;
4521 u32 _vmexit_control
= 0;
4522 u32 _vmentry_control
= 0;
4524 memset(vmcs_conf
, 0, sizeof(*vmcs_conf
));
4525 min
= CPU_BASED_HLT_EXITING
|
4526 #ifdef CONFIG_X86_64
4527 CPU_BASED_CR8_LOAD_EXITING
|
4528 CPU_BASED_CR8_STORE_EXITING
|
4530 CPU_BASED_CR3_LOAD_EXITING
|
4531 CPU_BASED_CR3_STORE_EXITING
|
4532 CPU_BASED_UNCOND_IO_EXITING
|
4533 CPU_BASED_MOV_DR_EXITING
|
4534 CPU_BASED_USE_TSC_OFFSETING
|
4535 CPU_BASED_MWAIT_EXITING
|
4536 CPU_BASED_MONITOR_EXITING
|
4537 CPU_BASED_INVLPG_EXITING
|
4538 CPU_BASED_RDPMC_EXITING
;
4540 opt
= CPU_BASED_TPR_SHADOW
|
4541 CPU_BASED_USE_MSR_BITMAPS
|
4542 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
4543 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
4544 &_cpu_based_exec_control
) < 0)
4546 #ifdef CONFIG_X86_64
4547 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
4548 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
4549 ~CPU_BASED_CR8_STORE_EXITING
;
4551 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
4553 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
4554 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
4555 SECONDARY_EXEC_WBINVD_EXITING
|
4556 SECONDARY_EXEC_ENABLE_VPID
|
4557 SECONDARY_EXEC_ENABLE_EPT
|
4558 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
4559 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
4560 SECONDARY_EXEC_DESC
|
4561 SECONDARY_EXEC_RDTSCP
|
4562 SECONDARY_EXEC_ENABLE_INVPCID
|
4563 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4564 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
4565 SECONDARY_EXEC_SHADOW_VMCS
|
4566 SECONDARY_EXEC_XSAVES
|
4567 SECONDARY_EXEC_RDSEED_EXITING
|
4568 SECONDARY_EXEC_RDRAND_EXITING
|
4569 SECONDARY_EXEC_ENABLE_PML
|
4570 SECONDARY_EXEC_TSC_SCALING
|
4571 SECONDARY_EXEC_ENABLE_VMFUNC
|
4572 SECONDARY_EXEC_ENCLS_EXITING
;
4573 if (adjust_vmx_controls(min2
, opt2
,
4574 MSR_IA32_VMX_PROCBASED_CTLS2
,
4575 &_cpu_based_2nd_exec_control
) < 0)
4578 #ifndef CONFIG_X86_64
4579 if (!(_cpu_based_2nd_exec_control
&
4580 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
4581 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4584 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
4585 _cpu_based_2nd_exec_control
&= ~(
4586 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4587 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
4588 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4590 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
4591 &vmx_capability
.ept
, &vmx_capability
.vpid
);
4593 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
4594 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
4596 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
4597 CPU_BASED_CR3_STORE_EXITING
|
4598 CPU_BASED_INVLPG_EXITING
);
4599 } else if (vmx_capability
.ept
) {
4600 vmx_capability
.ept
= 0;
4601 pr_warn_once("EPT CAP should not exist if not support "
4602 "1-setting enable EPT VM-execution control\n");
4604 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
4605 vmx_capability
.vpid
) {
4606 vmx_capability
.vpid
= 0;
4607 pr_warn_once("VPID CAP should not exist if not support "
4608 "1-setting enable VPID VM-execution control\n");
4611 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
4612 #ifdef CONFIG_X86_64
4613 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
4615 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
4616 VM_EXIT_CLEAR_BNDCFGS
;
4617 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
4618 &_vmexit_control
) < 0)
4621 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
4622 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
4623 PIN_BASED_VMX_PREEMPTION_TIMER
;
4624 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
4625 &_pin_based_exec_control
) < 0)
4628 if (cpu_has_broken_vmx_preemption_timer())
4629 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
4630 if (!(_cpu_based_2nd_exec_control
&
4631 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
4632 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
4634 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
4635 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
4636 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
4637 &_vmentry_control
) < 0)
4640 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
4642 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
4643 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
4646 #ifdef CONFIG_X86_64
4647 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
4648 if (vmx_msr_high
& (1u<<16))
4652 /* Require Write-Back (WB) memory type for VMCS accesses. */
4653 if (((vmx_msr_high
>> 18) & 15) != 6)
4656 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
4657 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
4658 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
4660 vmcs_conf
->revision_id
= vmx_msr_low
;
4662 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
4663 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
4664 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
4665 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
4666 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
4668 if (static_branch_unlikely(&enable_evmcs
))
4669 evmcs_sanitize_exec_ctrls(vmcs_conf
);
4671 cpu_has_load_ia32_efer
=
4672 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
4673 VM_ENTRY_LOAD_IA32_EFER
)
4674 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
4675 VM_EXIT_LOAD_IA32_EFER
);
4677 cpu_has_load_perf_global_ctrl
=
4678 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
4679 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
4680 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
4681 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
4684 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
4685 * but due to errata below it can't be used. Workaround is to use
4686 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
4688 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
4693 * BC86,AAY89,BD102 (model 44)
4697 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
4698 switch (boot_cpu_data
.x86_model
) {
4704 cpu_has_load_perf_global_ctrl
= false;
4705 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
4706 "does not work properly. Using workaround\n");
4713 if (boot_cpu_has(X86_FEATURE_XSAVES
))
4714 rdmsrl(MSR_IA32_XSS
, host_xss
);
4719 static struct vmcs
*alloc_vmcs_cpu(bool shadow
, int cpu
)
4721 int node
= cpu_to_node(cpu
);
4725 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
4728 vmcs
= page_address(pages
);
4729 memset(vmcs
, 0, vmcs_config
.size
);
4731 /* KVM supports Enlightened VMCS v1 only */
4732 if (static_branch_unlikely(&enable_evmcs
))
4733 vmcs
->hdr
.revision_id
= KVM_EVMCS_VERSION
;
4735 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
4738 vmcs
->hdr
.shadow_vmcs
= 1;
4742 static void free_vmcs(struct vmcs
*vmcs
)
4744 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
4748 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
4750 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
4752 if (!loaded_vmcs
->vmcs
)
4754 loaded_vmcs_clear(loaded_vmcs
);
4755 free_vmcs(loaded_vmcs
->vmcs
);
4756 loaded_vmcs
->vmcs
= NULL
;
4757 if (loaded_vmcs
->msr_bitmap
)
4758 free_page((unsigned long)loaded_vmcs
->msr_bitmap
);
4759 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
4762 static struct vmcs
*alloc_vmcs(bool shadow
)
4764 return alloc_vmcs_cpu(shadow
, raw_smp_processor_id());
4767 static int alloc_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
4769 loaded_vmcs
->vmcs
= alloc_vmcs(false);
4770 if (!loaded_vmcs
->vmcs
)
4773 loaded_vmcs
->shadow_vmcs
= NULL
;
4774 loaded_vmcs_init(loaded_vmcs
);
4776 if (cpu_has_vmx_msr_bitmap()) {
4777 loaded_vmcs
->msr_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4778 if (!loaded_vmcs
->msr_bitmap
)
4780 memset(loaded_vmcs
->msr_bitmap
, 0xff, PAGE_SIZE
);
4782 if (IS_ENABLED(CONFIG_HYPERV
) &&
4783 static_branch_unlikely(&enable_evmcs
) &&
4784 (ms_hyperv
.nested_features
& HV_X64_NESTED_MSR_BITMAP
)) {
4785 struct hv_enlightened_vmcs
*evmcs
=
4786 (struct hv_enlightened_vmcs
*)loaded_vmcs
->vmcs
;
4788 evmcs
->hv_enlightenments_control
.msr_bitmap
= 1;
4792 memset(&loaded_vmcs
->host_state
, 0, sizeof(struct vmcs_host_state
));
4797 free_loaded_vmcs(loaded_vmcs
);
4801 static void free_kvm_area(void)
4805 for_each_possible_cpu(cpu
) {
4806 free_vmcs(per_cpu(vmxarea
, cpu
));
4807 per_cpu(vmxarea
, cpu
) = NULL
;
4811 enum vmcs_field_width
{
4812 VMCS_FIELD_WIDTH_U16
= 0,
4813 VMCS_FIELD_WIDTH_U64
= 1,
4814 VMCS_FIELD_WIDTH_U32
= 2,
4815 VMCS_FIELD_WIDTH_NATURAL_WIDTH
= 3
4818 static inline int vmcs_field_width(unsigned long field
)
4820 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
4821 return VMCS_FIELD_WIDTH_U32
;
4822 return (field
>> 13) & 0x3 ;
4825 static inline int vmcs_field_readonly(unsigned long field
)
4827 return (((field
>> 10) & 0x3) == 1);
4830 static void init_vmcs_shadow_fields(void)
4834 for (i
= j
= 0; i
< max_shadow_read_only_fields
; i
++) {
4835 u16 field
= shadow_read_only_fields
[i
];
4836 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
4837 (i
+ 1 == max_shadow_read_only_fields
||
4838 shadow_read_only_fields
[i
+ 1] != field
+ 1))
4839 pr_err("Missing field from shadow_read_only_field %x\n",
4842 clear_bit(field
, vmx_vmread_bitmap
);
4843 #ifdef CONFIG_X86_64
4848 shadow_read_only_fields
[j
] = field
;
4851 max_shadow_read_only_fields
= j
;
4853 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
4854 u16 field
= shadow_read_write_fields
[i
];
4855 if (vmcs_field_width(field
) == VMCS_FIELD_WIDTH_U64
&&
4856 (i
+ 1 == max_shadow_read_write_fields
||
4857 shadow_read_write_fields
[i
+ 1] != field
+ 1))
4858 pr_err("Missing field from shadow_read_write_field %x\n",
4862 * PML and the preemption timer can be emulated, but the
4863 * processor cannot vmwrite to fields that don't exist
4867 case GUEST_PML_INDEX
:
4868 if (!cpu_has_vmx_pml())
4871 case VMX_PREEMPTION_TIMER_VALUE
:
4872 if (!cpu_has_vmx_preemption_timer())
4875 case GUEST_INTR_STATUS
:
4876 if (!cpu_has_vmx_apicv())
4883 clear_bit(field
, vmx_vmwrite_bitmap
);
4884 clear_bit(field
, vmx_vmread_bitmap
);
4885 #ifdef CONFIG_X86_64
4890 shadow_read_write_fields
[j
] = field
;
4893 max_shadow_read_write_fields
= j
;
4896 static __init
int alloc_kvm_area(void)
4900 for_each_possible_cpu(cpu
) {
4903 vmcs
= alloc_vmcs_cpu(false, cpu
);
4910 * When eVMCS is enabled, alloc_vmcs_cpu() sets
4911 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
4912 * revision_id reported by MSR_IA32_VMX_BASIC.
4914 * However, even though not explictly documented by
4915 * TLFS, VMXArea passed as VMXON argument should
4916 * still be marked with revision_id reported by
4919 if (static_branch_unlikely(&enable_evmcs
))
4920 vmcs
->hdr
.revision_id
= vmcs_config
.revision_id
;
4922 per_cpu(vmxarea
, cpu
) = vmcs
;
4927 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
4928 struct kvm_segment
*save
)
4930 if (!emulate_invalid_guest_state
) {
4932 * CS and SS RPL should be equal during guest entry according
4933 * to VMX spec, but in reality it is not always so. Since vcpu
4934 * is in the middle of the transition from real mode to
4935 * protected mode it is safe to assume that RPL 0 is a good
4938 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
4939 save
->selector
&= ~SEGMENT_RPL_MASK
;
4940 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
4943 vmx_set_segment(vcpu
, save
, seg
);
4946 static void enter_pmode(struct kvm_vcpu
*vcpu
)
4948 unsigned long flags
;
4949 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4952 * Update real mode segment cache. It may be not up-to-date if sement
4953 * register was written while vcpu was in a guest mode.
4955 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4956 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4957 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4958 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4959 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4960 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4962 vmx
->rmode
.vm86_active
= 0;
4964 vmx_segment_cache_clear(vmx
);
4966 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4968 flags
= vmcs_readl(GUEST_RFLAGS
);
4969 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
4970 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
4971 vmcs_writel(GUEST_RFLAGS
, flags
);
4973 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
4974 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
4976 update_exception_bitmap(vcpu
);
4978 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4979 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4980 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4981 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4982 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4983 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4986 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4988 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4989 struct kvm_segment var
= *save
;
4992 if (seg
== VCPU_SREG_CS
)
4995 if (!emulate_invalid_guest_state
) {
4996 var
.selector
= var
.base
>> 4;
4997 var
.base
= var
.base
& 0xffff0;
5007 if (save
->base
& 0xf)
5008 printk_once(KERN_WARNING
"kvm: segment base is not "
5009 "paragraph aligned when entering "
5010 "protected mode (seg=%d)", seg
);
5013 vmcs_write16(sf
->selector
, var
.selector
);
5014 vmcs_writel(sf
->base
, var
.base
);
5015 vmcs_write32(sf
->limit
, var
.limit
);
5016 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
5019 static void enter_rmode(struct kvm_vcpu
*vcpu
)
5021 unsigned long flags
;
5022 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5023 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(vcpu
->kvm
);
5025 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
5026 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
5027 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
5028 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
5029 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
5030 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
5031 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
5033 vmx
->rmode
.vm86_active
= 1;
5036 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
5037 * vcpu. Warn the user that an update is overdue.
5039 if (!kvm_vmx
->tss_addr
)
5040 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
5041 "called before entering vcpu\n");
5043 vmx_segment_cache_clear(vmx
);
5045 vmcs_writel(GUEST_TR_BASE
, kvm_vmx
->tss_addr
);
5046 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
5047 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5049 flags
= vmcs_readl(GUEST_RFLAGS
);
5050 vmx
->rmode
.save_rflags
= flags
;
5052 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
5054 vmcs_writel(GUEST_RFLAGS
, flags
);
5055 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
5056 update_exception_bitmap(vcpu
);
5058 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
5059 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
5060 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
5061 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
5062 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
5063 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
5065 kvm_mmu_reset_context(vcpu
);
5068 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
5070 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5071 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
5077 * MSR_KERNEL_GS_BASE is not intercepted when the guest is in
5078 * 64-bit mode as a 64-bit kernel may frequently access the
5079 * MSR. This means we need to manually save/restore the MSR
5080 * when switching between guest and host state, but only if
5081 * the guest is in 64-bit mode. Sync our cached value if the
5082 * guest is transitioning to 32-bit mode and the CPU contains
5083 * guest state, i.e. the cache is stale.
5085 #ifdef CONFIG_X86_64
5086 if (!(efer
& EFER_LMA
))
5087 (void)vmx_read_guest_kernel_gs_base(vmx
);
5089 vcpu
->arch
.efer
= efer
;
5090 if (efer
& EFER_LMA
) {
5091 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
5094 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
5096 msr
->data
= efer
& ~EFER_LME
;
5101 #ifdef CONFIG_X86_64
5103 static void enter_lmode(struct kvm_vcpu
*vcpu
)
5107 vmx_segment_cache_clear(to_vmx(vcpu
));
5109 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
5110 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
5111 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
5113 vmcs_write32(GUEST_TR_AR_BYTES
,
5114 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
5115 | VMX_AR_TYPE_BUSY_64_TSS
);
5117 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
5120 static void exit_lmode(struct kvm_vcpu
*vcpu
)
5122 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
5123 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
5128 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
,
5129 bool invalidate_gpa
)
5131 if (enable_ept
&& (invalidate_gpa
|| !enable_vpid
)) {
5132 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
5134 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
5136 vpid_sync_context(vpid
);
5140 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
, bool invalidate_gpa
)
5142 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
, invalidate_gpa
);
5145 static void vmx_flush_tlb_gva(struct kvm_vcpu
*vcpu
, gva_t addr
)
5147 int vpid
= to_vmx(vcpu
)->vpid
;
5149 if (!vpid_sync_vcpu_addr(vpid
, addr
))
5150 vpid_sync_context(vpid
);
5153 * If VPIDs are not supported or enabled, then the above is a no-op.
5154 * But we don't really need a TLB flush in that case anyway, because
5155 * each VM entry/exit includes an implicit flush when VPID is 0.
5159 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
5161 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
5163 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
5164 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
5167 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
5169 if (enable_unrestricted_guest
|| (enable_ept
&& is_paging(vcpu
)))
5170 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
5171 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
5174 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
5176 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
5178 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
5179 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
5182 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
5184 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
5186 if (!test_bit(VCPU_EXREG_PDPTR
,
5187 (unsigned long *)&vcpu
->arch
.regs_dirty
))
5190 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
5191 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
5192 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
5193 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
5194 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
5198 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
5200 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
5202 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
5203 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
5204 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
5205 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
5206 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
5209 __set_bit(VCPU_EXREG_PDPTR
,
5210 (unsigned long *)&vcpu
->arch
.regs_avail
);
5211 __set_bit(VCPU_EXREG_PDPTR
,
5212 (unsigned long *)&vcpu
->arch
.regs_dirty
);
5215 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5217 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed0
;
5218 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed1
;
5219 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5221 if (to_vmx(vcpu
)->nested
.msrs
.secondary_ctls_high
&
5222 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5223 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5224 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5226 return fixed_bits_valid(val
, fixed0
, fixed1
);
5229 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5231 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed0
;
5232 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr0_fixed1
;
5234 return fixed_bits_valid(val
, fixed0
, fixed1
);
5237 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5239 u64 fixed0
= to_vmx(vcpu
)->nested
.msrs
.cr4_fixed0
;
5240 u64 fixed1
= to_vmx(vcpu
)->nested
.msrs
.cr4_fixed1
;
5242 return fixed_bits_valid(val
, fixed0
, fixed1
);
5245 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
5246 #define nested_guest_cr4_valid nested_cr4_valid
5247 #define nested_host_cr4_valid nested_cr4_valid
5249 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
5251 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
5253 struct kvm_vcpu
*vcpu
)
5255 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
5256 vmx_decache_cr3(vcpu
);
5257 if (!(cr0
& X86_CR0_PG
)) {
5258 /* From paging/starting to nonpaging */
5259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
5260 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
5261 (CPU_BASED_CR3_LOAD_EXITING
|
5262 CPU_BASED_CR3_STORE_EXITING
));
5263 vcpu
->arch
.cr0
= cr0
;
5264 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
5265 } else if (!is_paging(vcpu
)) {
5266 /* From nonpaging to paging */
5267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
5268 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
5269 ~(CPU_BASED_CR3_LOAD_EXITING
|
5270 CPU_BASED_CR3_STORE_EXITING
));
5271 vcpu
->arch
.cr0
= cr0
;
5272 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
5275 if (!(cr0
& X86_CR0_WP
))
5276 *hw_cr0
&= ~X86_CR0_WP
;
5279 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
5281 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5282 unsigned long hw_cr0
;
5284 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
5285 if (enable_unrestricted_guest
)
5286 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
5288 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
5290 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
5293 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
5297 #ifdef CONFIG_X86_64
5298 if (vcpu
->arch
.efer
& EFER_LME
) {
5299 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
5301 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
5306 if (enable_ept
&& !enable_unrestricted_guest
)
5307 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
5309 vmcs_writel(CR0_READ_SHADOW
, cr0
);
5310 vmcs_writel(GUEST_CR0
, hw_cr0
);
5311 vcpu
->arch
.cr0
= cr0
;
5313 /* depends on vcpu->arch.cr0 to be set to a new value */
5314 vmx
->emulation_required
= emulation_required(vcpu
);
5317 static int get_ept_level(struct kvm_vcpu
*vcpu
)
5319 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
5324 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
5326 u64 eptp
= VMX_EPTP_MT_WB
;
5328 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
5330 if (enable_ept_ad_bits
&&
5331 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
5332 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
5333 eptp
|= (root_hpa
& PAGE_MASK
);
5338 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
5340 struct kvm
*kvm
= vcpu
->kvm
;
5341 unsigned long guest_cr3
;
5346 eptp
= construct_eptp(vcpu
, cr3
);
5347 vmcs_write64(EPT_POINTER
, eptp
);
5349 if (kvm_x86_ops
->tlb_remote_flush
) {
5350 spin_lock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
5351 to_vmx(vcpu
)->ept_pointer
= eptp
;
5352 to_kvm_vmx(kvm
)->ept_pointers_match
5353 = EPT_POINTERS_CHECK
;
5354 spin_unlock(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
5357 if (enable_unrestricted_guest
|| is_paging(vcpu
) ||
5358 is_guest_mode(vcpu
))
5359 guest_cr3
= kvm_read_cr3(vcpu
);
5361 guest_cr3
= to_kvm_vmx(kvm
)->ept_identity_map_addr
;
5362 ept_load_pdptrs(vcpu
);
5365 vmcs_writel(GUEST_CR3
, guest_cr3
);
5368 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
5371 * Pass through host's Machine Check Enable value to hw_cr4, which
5372 * is in force while we are in guest mode. Do not let guests control
5373 * this bit, even if host CR4.MCE == 0.
5375 unsigned long hw_cr4
;
5377 hw_cr4
= (cr4_read_shadow() & X86_CR4_MCE
) | (cr4
& ~X86_CR4_MCE
);
5378 if (enable_unrestricted_guest
)
5379 hw_cr4
|= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST
;
5380 else if (to_vmx(vcpu
)->rmode
.vm86_active
)
5381 hw_cr4
|= KVM_RMODE_VM_CR4_ALWAYS_ON
;
5383 hw_cr4
|= KVM_PMODE_VM_CR4_ALWAYS_ON
;
5385 if (!boot_cpu_has(X86_FEATURE_UMIP
) && vmx_umip_emulated()) {
5386 if (cr4
& X86_CR4_UMIP
) {
5387 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5388 SECONDARY_EXEC_DESC
);
5389 hw_cr4
&= ~X86_CR4_UMIP
;
5390 } else if (!is_guest_mode(vcpu
) ||
5391 !nested_cpu_has2(get_vmcs12(vcpu
), SECONDARY_EXEC_DESC
))
5392 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5393 SECONDARY_EXEC_DESC
);
5396 if (cr4
& X86_CR4_VMXE
) {
5398 * To use VMXON (and later other VMX instructions), a guest
5399 * must first be able to turn on cr4.VMXE (see handle_vmon()).
5400 * So basically the check on whether to allow nested VMX
5401 * is here. We operate under the default treatment of SMM,
5402 * so VMX cannot be enabled under SMM.
5404 if (!nested_vmx_allowed(vcpu
) || is_smm(vcpu
))
5408 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
5411 vcpu
->arch
.cr4
= cr4
;
5413 if (!enable_unrestricted_guest
) {
5415 if (!is_paging(vcpu
)) {
5416 hw_cr4
&= ~X86_CR4_PAE
;
5417 hw_cr4
|= X86_CR4_PSE
;
5418 } else if (!(cr4
& X86_CR4_PAE
)) {
5419 hw_cr4
&= ~X86_CR4_PAE
;
5424 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
5425 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
5426 * to be manually disabled when guest switches to non-paging
5429 * If !enable_unrestricted_guest, the CPU is always running
5430 * with CR0.PG=1 and CR4 needs to be modified.
5431 * If enable_unrestricted_guest, the CPU automatically
5432 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
5434 if (!is_paging(vcpu
))
5435 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
5438 vmcs_writel(CR4_READ_SHADOW
, cr4
);
5439 vmcs_writel(GUEST_CR4
, hw_cr4
);
5443 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
5444 struct kvm_segment
*var
, int seg
)
5446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5449 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
5450 *var
= vmx
->rmode
.segs
[seg
];
5451 if (seg
== VCPU_SREG_TR
5452 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
5454 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
5455 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
5458 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
5459 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
5460 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
5461 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
5462 var
->unusable
= (ar
>> 16) & 1;
5463 var
->type
= ar
& 15;
5464 var
->s
= (ar
>> 4) & 1;
5465 var
->dpl
= (ar
>> 5) & 3;
5467 * Some userspaces do not preserve unusable property. Since usable
5468 * segment has to be present according to VMX spec we can use present
5469 * property to amend userspace bug by making unusable segment always
5470 * nonpresent. vmx_segment_access_rights() already marks nonpresent
5471 * segment as unusable.
5473 var
->present
= !var
->unusable
;
5474 var
->avl
= (ar
>> 12) & 1;
5475 var
->l
= (ar
>> 13) & 1;
5476 var
->db
= (ar
>> 14) & 1;
5477 var
->g
= (ar
>> 15) & 1;
5480 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
5482 struct kvm_segment s
;
5484 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
5485 vmx_get_segment(vcpu
, &s
, seg
);
5488 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
5491 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
5493 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5495 if (unlikely(vmx
->rmode
.vm86_active
))
5498 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
5499 return VMX_AR_DPL(ar
);
5503 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
5507 if (var
->unusable
|| !var
->present
)
5510 ar
= var
->type
& 15;
5511 ar
|= (var
->s
& 1) << 4;
5512 ar
|= (var
->dpl
& 3) << 5;
5513 ar
|= (var
->present
& 1) << 7;
5514 ar
|= (var
->avl
& 1) << 12;
5515 ar
|= (var
->l
& 1) << 13;
5516 ar
|= (var
->db
& 1) << 14;
5517 ar
|= (var
->g
& 1) << 15;
5523 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
5524 struct kvm_segment
*var
, int seg
)
5526 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5527 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
5529 vmx_segment_cache_clear(vmx
);
5531 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
5532 vmx
->rmode
.segs
[seg
] = *var
;
5533 if (seg
== VCPU_SREG_TR
)
5534 vmcs_write16(sf
->selector
, var
->selector
);
5536 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
5540 vmcs_writel(sf
->base
, var
->base
);
5541 vmcs_write32(sf
->limit
, var
->limit
);
5542 vmcs_write16(sf
->selector
, var
->selector
);
5545 * Fix the "Accessed" bit in AR field of segment registers for older
5547 * IA32 arch specifies that at the time of processor reset the
5548 * "Accessed" bit in the AR field of segment registers is 1. And qemu
5549 * is setting it to 0 in the userland code. This causes invalid guest
5550 * state vmexit when "unrestricted guest" mode is turned on.
5551 * Fix for this setup issue in cpu_reset is being pushed in the qemu
5552 * tree. Newer qemu binaries with that qemu fix would not need this
5555 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
5556 var
->type
|= 0x1; /* Accessed */
5558 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
5561 vmx
->emulation_required
= emulation_required(vcpu
);
5564 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
5566 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
5568 *db
= (ar
>> 14) & 1;
5569 *l
= (ar
>> 13) & 1;
5572 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
5574 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
5575 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
5578 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
5580 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
5581 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
5584 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
5586 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
5587 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
5590 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
5592 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
5593 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
5596 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
5598 struct kvm_segment var
;
5601 vmx_get_segment(vcpu
, &var
, seg
);
5603 if (seg
== VCPU_SREG_CS
)
5605 ar
= vmx_segment_access_rights(&var
);
5607 if (var
.base
!= (var
.selector
<< 4))
5609 if (var
.limit
!= 0xffff)
5617 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
5619 struct kvm_segment cs
;
5620 unsigned int cs_rpl
;
5622 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5623 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
5627 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
5631 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
5632 if (cs
.dpl
> cs_rpl
)
5635 if (cs
.dpl
!= cs_rpl
)
5641 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
5645 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
5647 struct kvm_segment ss
;
5648 unsigned int ss_rpl
;
5650 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
5651 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
5655 if (ss
.type
!= 3 && ss
.type
!= 7)
5659 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
5667 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
5669 struct kvm_segment var
;
5672 vmx_get_segment(vcpu
, &var
, seg
);
5673 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
5681 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
5682 if (var
.dpl
< rpl
) /* DPL < RPL */
5686 /* TODO: Add other members to kvm_segment_field to allow checking for other access
5692 static bool tr_valid(struct kvm_vcpu
*vcpu
)
5694 struct kvm_segment tr
;
5696 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
5700 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
5702 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
5710 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
5712 struct kvm_segment ldtr
;
5714 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
5718 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
5728 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
5730 struct kvm_segment cs
, ss
;
5732 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5733 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
5735 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
5736 (ss
.selector
& SEGMENT_RPL_MASK
));
5740 * Check if guest state is valid. Returns true if valid, false if
5742 * We assume that registers are always usable
5744 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
5746 if (enable_unrestricted_guest
)
5749 /* real mode guest state checks */
5750 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5751 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
5753 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
5755 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
5757 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
5759 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
5761 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
5764 /* protected mode guest state checks */
5765 if (!cs_ss_rpl_check(vcpu
))
5767 if (!code_segment_valid(vcpu
))
5769 if (!stack_segment_valid(vcpu
))
5771 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
5773 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
5775 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
5777 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
5779 if (!tr_valid(vcpu
))
5781 if (!ldtr_valid(vcpu
))
5785 * - Add checks on RIP
5786 * - Add checks on RFLAGS
5792 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
5794 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
5797 static int init_rmode_tss(struct kvm
*kvm
)
5803 idx
= srcu_read_lock(&kvm
->srcu
);
5804 fn
= to_kvm_vmx(kvm
)->tss_addr
>> PAGE_SHIFT
;
5805 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
5808 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
5809 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
5810 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
5813 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
5816 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
5820 r
= kvm_write_guest_page(kvm
, fn
, &data
,
5821 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
5824 srcu_read_unlock(&kvm
->srcu
, idx
);
5828 static int init_rmode_identity_map(struct kvm
*kvm
)
5830 struct kvm_vmx
*kvm_vmx
= to_kvm_vmx(kvm
);
5832 kvm_pfn_t identity_map_pfn
;
5835 /* Protect kvm_vmx->ept_identity_pagetable_done. */
5836 mutex_lock(&kvm
->slots_lock
);
5838 if (likely(kvm_vmx
->ept_identity_pagetable_done
))
5841 if (!kvm_vmx
->ept_identity_map_addr
)
5842 kvm_vmx
->ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
5843 identity_map_pfn
= kvm_vmx
->ept_identity_map_addr
>> PAGE_SHIFT
;
5845 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
5846 kvm_vmx
->ept_identity_map_addr
, PAGE_SIZE
);
5850 idx
= srcu_read_lock(&kvm
->srcu
);
5851 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
5854 /* Set up identity-mapping pagetable for EPT in real mode */
5855 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
5856 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
5857 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
5858 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
5859 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
5863 kvm_vmx
->ept_identity_pagetable_done
= true;
5866 srcu_read_unlock(&kvm
->srcu
, idx
);
5869 mutex_unlock(&kvm
->slots_lock
);
5873 static void seg_setup(int seg
)
5875 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
5878 vmcs_write16(sf
->selector
, 0);
5879 vmcs_writel(sf
->base
, 0);
5880 vmcs_write32(sf
->limit
, 0xffff);
5882 if (seg
== VCPU_SREG_CS
)
5883 ar
|= 0x08; /* code segment */
5885 vmcs_write32(sf
->ar_bytes
, ar
);
5888 static int alloc_apic_access_page(struct kvm
*kvm
)
5893 mutex_lock(&kvm
->slots_lock
);
5894 if (kvm
->arch
.apic_access_page_done
)
5896 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
5897 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
5901 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
5902 if (is_error_page(page
)) {
5908 * Do not pin the page in memory, so that memory hot-unplug
5909 * is able to migrate it.
5912 kvm
->arch
.apic_access_page_done
= true;
5914 mutex_unlock(&kvm
->slots_lock
);
5918 static int allocate_vpid(void)
5924 spin_lock(&vmx_vpid_lock
);
5925 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
5926 if (vpid
< VMX_NR_VPIDS
)
5927 __set_bit(vpid
, vmx_vpid_bitmap
);
5930 spin_unlock(&vmx_vpid_lock
);
5934 static void free_vpid(int vpid
)
5936 if (!enable_vpid
|| vpid
== 0)
5938 spin_lock(&vmx_vpid_lock
);
5939 __clear_bit(vpid
, vmx_vpid_bitmap
);
5940 spin_unlock(&vmx_vpid_lock
);
5943 static void __always_inline
vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
5946 int f
= sizeof(unsigned long);
5948 if (!cpu_has_vmx_msr_bitmap())
5951 if (static_branch_unlikely(&enable_evmcs
))
5952 evmcs_touch_msr_bitmap();
5955 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5956 * have the write-low and read-high bitmap offsets the wrong way round.
5957 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5959 if (msr
<= 0x1fff) {
5960 if (type
& MSR_TYPE_R
)
5962 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
5964 if (type
& MSR_TYPE_W
)
5966 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
5968 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
5970 if (type
& MSR_TYPE_R
)
5972 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
5974 if (type
& MSR_TYPE_W
)
5976 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
5981 static void __always_inline
vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
5984 int f
= sizeof(unsigned long);
5986 if (!cpu_has_vmx_msr_bitmap())
5989 if (static_branch_unlikely(&enable_evmcs
))
5990 evmcs_touch_msr_bitmap();
5993 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
5994 * have the write-low and read-high bitmap offsets the wrong way round.
5995 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
5997 if (msr
<= 0x1fff) {
5998 if (type
& MSR_TYPE_R
)
6000 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
6002 if (type
& MSR_TYPE_W
)
6004 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
6006 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
6008 if (type
& MSR_TYPE_R
)
6010 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
6012 if (type
& MSR_TYPE_W
)
6014 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
6019 static void __always_inline
vmx_set_intercept_for_msr(unsigned long *msr_bitmap
,
6020 u32 msr
, int type
, bool value
)
6023 vmx_enable_intercept_for_msr(msr_bitmap
, msr
, type
);
6025 vmx_disable_intercept_for_msr(msr_bitmap
, msr
, type
);
6029 * If a msr is allowed by L0, we should check whether it is allowed by L1.
6030 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
6032 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
6033 unsigned long *msr_bitmap_nested
,
6036 int f
= sizeof(unsigned long);
6039 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
6040 * have the write-low and read-high bitmap offsets the wrong way round.
6041 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
6043 if (msr
<= 0x1fff) {
6044 if (type
& MSR_TYPE_R
&&
6045 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
6047 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
6049 if (type
& MSR_TYPE_W
&&
6050 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
6052 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
6054 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
6056 if (type
& MSR_TYPE_R
&&
6057 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
6059 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
6061 if (type
& MSR_TYPE_W
&&
6062 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
6064 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
6069 static u8
vmx_msr_bitmap_mode(struct kvm_vcpu
*vcpu
)
6073 if (cpu_has_secondary_exec_ctrls() &&
6074 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
6075 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
6076 mode
|= MSR_BITMAP_MODE_X2APIC
;
6077 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
))
6078 mode
|= MSR_BITMAP_MODE_X2APIC_APICV
;
6081 if (is_long_mode(vcpu
))
6082 mode
|= MSR_BITMAP_MODE_LM
;
6087 #define X2APIC_MSR(r) (APIC_BASE_MSR + ((r) >> 4))
6089 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap
,
6094 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
6095 unsigned word
= msr
/ BITS_PER_LONG
;
6096 msr_bitmap
[word
] = (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) ? 0 : ~0;
6097 msr_bitmap
[word
+ (0x800 / sizeof(long))] = ~0;
6100 if (mode
& MSR_BITMAP_MODE_X2APIC
) {
6102 * TPR reads and writes can be virtualized even if virtual interrupt
6103 * delivery is not in use.
6105 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TASKPRI
), MSR_TYPE_RW
);
6106 if (mode
& MSR_BITMAP_MODE_X2APIC_APICV
) {
6107 vmx_enable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_TMCCT
), MSR_TYPE_R
);
6108 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_EOI
), MSR_TYPE_W
);
6109 vmx_disable_intercept_for_msr(msr_bitmap
, X2APIC_MSR(APIC_SELF_IPI
), MSR_TYPE_W
);
6114 static void vmx_update_msr_bitmap(struct kvm_vcpu
*vcpu
)
6116 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6117 unsigned long *msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
6118 u8 mode
= vmx_msr_bitmap_mode(vcpu
);
6119 u8 changed
= mode
^ vmx
->msr_bitmap_mode
;
6124 vmx_set_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
,
6125 !(mode
& MSR_BITMAP_MODE_LM
));
6127 if (changed
& (MSR_BITMAP_MODE_X2APIC
| MSR_BITMAP_MODE_X2APIC_APICV
))
6128 vmx_update_msr_bitmap_x2apic(msr_bitmap
, mode
);
6130 vmx
->msr_bitmap_mode
= mode
;
6133 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
6135 return enable_apicv
;
6138 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
6140 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6144 * Don't need to mark the APIC access page dirty; it is never
6145 * written to by the CPU during APIC virtualization.
6148 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
6149 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
6150 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
6153 if (nested_cpu_has_posted_intr(vmcs12
)) {
6154 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
6155 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
6160 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
6162 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6167 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
6170 vmx
->nested
.pi_pending
= false;
6171 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
6174 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
6175 if (max_irr
!= 256) {
6176 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
6177 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
,
6178 vapic_page
, &max_irr
);
6179 kunmap(vmx
->nested
.virtual_apic_page
);
6181 status
= vmcs_read16(GUEST_INTR_STATUS
);
6182 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
6184 status
|= (u8
)max_irr
;
6185 vmcs_write16(GUEST_INTR_STATUS
, status
);
6189 nested_mark_vmcs12_pages_dirty(vcpu
);
6192 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
6196 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
6198 if (vcpu
->mode
== IN_GUEST_MODE
) {
6200 * The vector of interrupt to be delivered to vcpu had
6201 * been set in PIR before this function.
6203 * Following cases will be reached in this block, and
6204 * we always send a notification event in all cases as
6207 * Case 1: vcpu keeps in non-root mode. Sending a
6208 * notification event posts the interrupt to vcpu.
6210 * Case 2: vcpu exits to root mode and is still
6211 * runnable. PIR will be synced to vIRR before the
6212 * next vcpu entry. Sending a notification event in
6213 * this case has no effect, as vcpu is not in root
6216 * Case 3: vcpu exits to root mode and is blocked.
6217 * vcpu_block() has already synced PIR to vIRR and
6218 * never blocks vcpu if vIRR is not cleared. Therefore,
6219 * a blocked vcpu here does not wait for any requested
6220 * interrupts in PIR, and sending a notification event
6221 * which has no effect is safe here.
6224 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
6231 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
6234 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6236 if (is_guest_mode(vcpu
) &&
6237 vector
== vmx
->nested
.posted_intr_nv
) {
6239 * If a posted intr is not recognized by hardware,
6240 * we will accomplish it in the next vmentry.
6242 vmx
->nested
.pi_pending
= true;
6243 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6244 /* the PIR and ON have been set by L1. */
6245 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, true))
6246 kvm_vcpu_kick(vcpu
);
6252 * Send interrupt to vcpu via posted interrupt way.
6253 * 1. If target vcpu is running(non-root mode), send posted interrupt
6254 * notification to vcpu and hardware will sync PIR to vIRR atomically.
6255 * 2. If target vcpu isn't running(root mode), kick it to pick up the
6256 * interrupt from PIR in next vmentry.
6258 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
6260 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6263 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
6267 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
6270 /* If a previous notification has sent the IPI, nothing to do. */
6271 if (pi_test_and_set_on(&vmx
->pi_desc
))
6274 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
6275 kvm_vcpu_kick(vcpu
);
6279 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
6280 * will not change in the lifetime of the guest.
6281 * Note that host-state that does change is set elsewhere. E.g., host-state
6282 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
6284 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
6289 unsigned long cr0
, cr3
, cr4
;
6292 WARN_ON(cr0
& X86_CR0_TS
);
6293 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
6296 * Save the most likely value for this task's CR3 in the VMCS.
6297 * We can't use __get_current_cr3_fast() because we're not atomic.
6300 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
6301 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
6303 /* Save the most likely value for this task's CR4 in the VMCS. */
6304 cr4
= cr4_read_shadow();
6305 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
6306 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
6308 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
6309 #ifdef CONFIG_X86_64
6311 * Load null selectors, so we can avoid reloading them in
6312 * vmx_prepare_switch_to_host(), in case userspace uses
6313 * the null selectors too (the expected case).
6315 vmcs_write16(HOST_DS_SELECTOR
, 0);
6316 vmcs_write16(HOST_ES_SELECTOR
, 0);
6318 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
6319 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
6321 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
6322 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
6325 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
6326 vmx
->host_idt_base
= dt
.address
;
6328 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
6330 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
6331 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
6332 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
6333 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
6335 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
6336 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
6337 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
6341 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
6343 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
6345 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
6346 if (is_guest_mode(&vmx
->vcpu
))
6347 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
6348 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
6349 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
6352 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
6354 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
6356 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
6357 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
6360 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
6362 /* Enable the preemption timer dynamically */
6363 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
6364 return pin_based_exec_ctrl
;
6367 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
6369 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6371 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
6372 if (cpu_has_secondary_exec_ctrls()) {
6373 if (kvm_vcpu_apicv_active(vcpu
))
6374 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
6375 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
6376 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
6378 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6379 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
6380 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
6383 if (cpu_has_vmx_msr_bitmap())
6384 vmx_update_msr_bitmap(vcpu
);
6387 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
6389 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
6391 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
6392 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
6394 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
6395 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6396 #ifdef CONFIG_X86_64
6397 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
6398 CPU_BASED_CR8_LOAD_EXITING
;
6402 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
6403 CPU_BASED_CR3_LOAD_EXITING
|
6404 CPU_BASED_INVLPG_EXITING
;
6405 if (kvm_mwait_in_guest(vmx
->vcpu
.kvm
))
6406 exec_control
&= ~(CPU_BASED_MWAIT_EXITING
|
6407 CPU_BASED_MONITOR_EXITING
);
6408 if (kvm_hlt_in_guest(vmx
->vcpu
.kvm
))
6409 exec_control
&= ~CPU_BASED_HLT_EXITING
;
6410 return exec_control
;
6413 static bool vmx_rdrand_supported(void)
6415 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
6416 SECONDARY_EXEC_RDRAND_EXITING
;
6419 static bool vmx_rdseed_supported(void)
6421 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
6422 SECONDARY_EXEC_RDSEED_EXITING
;
6425 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
6427 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
6429 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
6431 if (!cpu_need_virtualize_apic_accesses(vcpu
))
6432 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6434 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
6436 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
6437 enable_unrestricted_guest
= 0;
6439 if (!enable_unrestricted_guest
)
6440 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
6441 if (kvm_pause_in_guest(vmx
->vcpu
.kvm
))
6442 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
6443 if (!kvm_vcpu_apicv_active(vcpu
))
6444 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
6445 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
6446 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6448 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
6449 * in vmx_set_cr4. */
6450 exec_control
&= ~SECONDARY_EXEC_DESC
;
6452 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
6454 We can NOT enable shadow_vmcs here because we don't have yet
6457 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6460 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
6462 if (vmx_xsaves_supported()) {
6463 /* Exposing XSAVES only when XSAVE is exposed */
6464 bool xsaves_enabled
=
6465 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
6466 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
6468 if (!xsaves_enabled
)
6469 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
6473 vmx
->nested
.msrs
.secondary_ctls_high
|=
6474 SECONDARY_EXEC_XSAVES
;
6476 vmx
->nested
.msrs
.secondary_ctls_high
&=
6477 ~SECONDARY_EXEC_XSAVES
;
6481 if (vmx_rdtscp_supported()) {
6482 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
6483 if (!rdtscp_enabled
)
6484 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6488 vmx
->nested
.msrs
.secondary_ctls_high
|=
6489 SECONDARY_EXEC_RDTSCP
;
6491 vmx
->nested
.msrs
.secondary_ctls_high
&=
6492 ~SECONDARY_EXEC_RDTSCP
;
6496 if (vmx_invpcid_supported()) {
6497 /* Exposing INVPCID only when PCID is exposed */
6498 bool invpcid_enabled
=
6499 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
6500 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
6502 if (!invpcid_enabled
) {
6503 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
6504 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
6508 if (invpcid_enabled
)
6509 vmx
->nested
.msrs
.secondary_ctls_high
|=
6510 SECONDARY_EXEC_ENABLE_INVPCID
;
6512 vmx
->nested
.msrs
.secondary_ctls_high
&=
6513 ~SECONDARY_EXEC_ENABLE_INVPCID
;
6517 if (vmx_rdrand_supported()) {
6518 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
6520 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
6524 vmx
->nested
.msrs
.secondary_ctls_high
|=
6525 SECONDARY_EXEC_RDRAND_EXITING
;
6527 vmx
->nested
.msrs
.secondary_ctls_high
&=
6528 ~SECONDARY_EXEC_RDRAND_EXITING
;
6532 if (vmx_rdseed_supported()) {
6533 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
6535 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
6539 vmx
->nested
.msrs
.secondary_ctls_high
|=
6540 SECONDARY_EXEC_RDSEED_EXITING
;
6542 vmx
->nested
.msrs
.secondary_ctls_high
&=
6543 ~SECONDARY_EXEC_RDSEED_EXITING
;
6547 vmx
->secondary_exec_control
= exec_control
;
6550 static void ept_set_mmio_spte_mask(void)
6553 * EPT Misconfigurations can be generated if the value of bits 2:0
6554 * of an EPT paging-structure entry is 110b (write/execute).
6556 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
6557 VMX_EPT_MISCONFIG_WX_VALUE
);
6560 #define VMX_XSS_EXIT_BITMAP 0
6562 * Sets up the vmcs for emulated real mode.
6564 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
6568 if (enable_shadow_vmcs
) {
6570 * At vCPU creation, "VMWRITE to any supported field
6571 * in the VMCS" is supported, so use the more
6572 * permissive vmx_vmread_bitmap to specify both read
6573 * and write permissions for the shadow VMCS.
6575 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
6576 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmread_bitmap
));
6578 if (cpu_has_vmx_msr_bitmap())
6579 vmcs_write64(MSR_BITMAP
, __pa(vmx
->vmcs01
.msr_bitmap
));
6581 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
6584 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
6585 vmx
->hv_deadline_tsc
= -1;
6587 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
6589 if (cpu_has_secondary_exec_ctrls()) {
6590 vmx_compute_secondary_exec_control(vmx
);
6591 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6592 vmx
->secondary_exec_control
);
6595 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
6596 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
6597 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
6598 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
6599 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
6601 vmcs_write16(GUEST_INTR_STATUS
, 0);
6603 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
6604 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
6607 if (!kvm_pause_in_guest(vmx
->vcpu
.kvm
)) {
6608 vmcs_write32(PLE_GAP
, ple_gap
);
6609 vmx
->ple_window
= ple_window
;
6610 vmx
->ple_window_dirty
= true;
6613 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
6614 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
6615 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
6617 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
6618 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
6619 vmx_set_constant_host_state(vmx
);
6620 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
6621 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
6623 if (cpu_has_vmx_vmfunc())
6624 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
6626 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
6627 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
6628 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
.val
));
6629 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
6630 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
.val
));
6632 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6633 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6635 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
6636 u32 index
= vmx_msr_index
[i
];
6637 u32 data_low
, data_high
;
6640 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
6642 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
6644 vmx
->guest_msrs
[j
].index
= i
;
6645 vmx
->guest_msrs
[j
].data
= 0;
6646 vmx
->guest_msrs
[j
].mask
= -1ull;
6650 vmx
->arch_capabilities
= kvm_get_arch_capabilities();
6652 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
6654 /* 22.2.1, 20.8.1 */
6655 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
6657 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
6658 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
6660 set_cr4_guest_host_mask(vmx
);
6662 if (vmx_xsaves_supported())
6663 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
6666 ASSERT(vmx
->pml_pg
);
6667 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
6668 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
6671 if (cpu_has_vmx_encls_vmexit())
6672 vmcs_write64(ENCLS_EXITING_BITMAP
, -1ull);
6675 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
6677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6678 struct msr_data apic_base_msr
;
6681 vmx
->rmode
.vm86_active
= 0;
6684 vcpu
->arch
.microcode_version
= 0x100000000ULL
;
6685 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
6686 kvm_set_cr8(vcpu
, 0);
6689 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
6690 MSR_IA32_APICBASE_ENABLE
;
6691 if (kvm_vcpu_is_reset_bsp(vcpu
))
6692 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
6693 apic_base_msr
.host_initiated
= true;
6694 kvm_set_apic_base(vcpu
, &apic_base_msr
);
6697 vmx_segment_cache_clear(vmx
);
6699 seg_setup(VCPU_SREG_CS
);
6700 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
6701 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
6703 seg_setup(VCPU_SREG_DS
);
6704 seg_setup(VCPU_SREG_ES
);
6705 seg_setup(VCPU_SREG_FS
);
6706 seg_setup(VCPU_SREG_GS
);
6707 seg_setup(VCPU_SREG_SS
);
6709 vmcs_write16(GUEST_TR_SELECTOR
, 0);
6710 vmcs_writel(GUEST_TR_BASE
, 0);
6711 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
6712 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
6714 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
6715 vmcs_writel(GUEST_LDTR_BASE
, 0);
6716 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
6717 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
6720 vmcs_write32(GUEST_SYSENTER_CS
, 0);
6721 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
6722 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
6723 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
6726 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
6727 kvm_rip_write(vcpu
, 0xfff0);
6729 vmcs_writel(GUEST_GDTR_BASE
, 0);
6730 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
6732 vmcs_writel(GUEST_IDTR_BASE
, 0);
6733 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
6735 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
6736 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
6737 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
6738 if (kvm_mpx_supported())
6739 vmcs_write64(GUEST_BNDCFGS
, 0);
6743 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
6745 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
6746 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
6747 if (cpu_need_tpr_shadow(vcpu
))
6748 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
6749 __pa(vcpu
->arch
.apic
->regs
));
6750 vmcs_write32(TPR_THRESHOLD
, 0);
6753 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
6756 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6758 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
6759 vmx
->vcpu
.arch
.cr0
= cr0
;
6760 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
6761 vmx_set_cr4(vcpu
, 0);
6762 vmx_set_efer(vcpu
, 0);
6764 update_exception_bitmap(vcpu
);
6766 vpid_sync_context(vmx
->vpid
);
6768 vmx_clear_hlt(vcpu
);
6772 * In nested virtualization, check if L1 asked to exit on external interrupts.
6773 * For most existing hypervisors, this will always return true.
6775 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
6777 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
6778 PIN_BASED_EXT_INTR_MASK
;
6782 * In nested virtualization, check if L1 has set
6783 * VM_EXIT_ACK_INTR_ON_EXIT
6785 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
6787 return get_vmcs12(vcpu
)->vm_exit_controls
&
6788 VM_EXIT_ACK_INTR_ON_EXIT
;
6791 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
6793 return nested_cpu_has_nmi_exiting(get_vmcs12(vcpu
));
6796 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
6798 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
6799 CPU_BASED_VIRTUAL_INTR_PENDING
);
6802 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
6805 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
6806 enable_irq_window(vcpu
);
6810 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
6811 CPU_BASED_VIRTUAL_NMI_PENDING
);
6814 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
6816 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6818 int irq
= vcpu
->arch
.interrupt
.nr
;
6820 trace_kvm_inj_virq(irq
);
6822 ++vcpu
->stat
.irq_injections
;
6823 if (vmx
->rmode
.vm86_active
) {
6825 if (vcpu
->arch
.interrupt
.soft
)
6826 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
6827 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
6828 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6831 intr
= irq
| INTR_INFO_VALID_MASK
;
6832 if (vcpu
->arch
.interrupt
.soft
) {
6833 intr
|= INTR_TYPE_SOFT_INTR
;
6834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6835 vmx
->vcpu
.arch
.event_exit_inst_len
);
6837 intr
|= INTR_TYPE_EXT_INTR
;
6838 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
6840 vmx_clear_hlt(vcpu
);
6843 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
6845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6849 * Tracking the NMI-blocked state in software is built upon
6850 * finding the next open IRQ window. This, in turn, depends on
6851 * well-behaving guests: They have to keep IRQs disabled at
6852 * least as long as the NMI handler runs. Otherwise we may
6853 * cause NMI nesting, maybe breaking the guest. But as this is
6854 * highly unlikely, we can live with the residual risk.
6856 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
6857 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
6860 ++vcpu
->stat
.nmi_injections
;
6861 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
6863 if (vmx
->rmode
.vm86_active
) {
6864 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
6865 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6870 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
6872 vmx_clear_hlt(vcpu
);
6875 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
6877 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6881 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
6882 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
6884 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
6885 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
6889 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
6891 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6894 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
6895 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
6896 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
6899 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
6901 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6902 GUEST_INTR_STATE_NMI
);
6904 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
6905 GUEST_INTR_STATE_NMI
);
6909 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
6911 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
6915 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
6918 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6919 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
6920 | GUEST_INTR_STATE_NMI
));
6923 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
6925 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
6926 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
6927 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
6928 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
6931 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
6935 if (enable_unrestricted_guest
)
6938 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
6942 to_kvm_vmx(kvm
)->tss_addr
= addr
;
6943 return init_rmode_tss(kvm
);
6946 static int vmx_set_identity_map_addr(struct kvm
*kvm
, u64 ident_addr
)
6948 to_kvm_vmx(kvm
)->ept_identity_map_addr
= ident_addr
;
6952 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
6957 * Update instruction length as we may reinject the exception
6958 * from user space while in guest debugging mode.
6960 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
6961 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6962 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
6966 if (vcpu
->guest_debug
&
6967 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
6984 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
6985 int vec
, u32 err_code
)
6988 * Instruction with address size override prefix opcode 0x67
6989 * Cause the #SS fault with 0 error code in VM86 mode.
6991 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
6992 if (kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
6993 if (vcpu
->arch
.halt_request
) {
6994 vcpu
->arch
.halt_request
= 0;
6995 return kvm_vcpu_halt(vcpu
);
7003 * Forward all other exceptions that are valid in real mode.
7004 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
7005 * the required debugging infrastructure rework.
7007 kvm_queue_exception(vcpu
, vec
);
7012 * Trigger machine check on the host. We assume all the MSRs are already set up
7013 * by the CPU and that we still run on the same CPU as the MCE occurred on.
7014 * We pass a fake environment to the machine check handler because we want
7015 * the guest to be always treated like user space, no matter what context
7016 * it used internally.
7018 static void kvm_machine_check(void)
7020 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
7021 struct pt_regs regs
= {
7022 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
7023 .flags
= X86_EFLAGS_IF
,
7026 do_machine_check(®s
, 0);
7030 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
7032 /* already handled by vcpu_run */
7036 static int handle_exception(struct kvm_vcpu
*vcpu
)
7038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7039 struct kvm_run
*kvm_run
= vcpu
->run
;
7040 u32 intr_info
, ex_no
, error_code
;
7041 unsigned long cr2
, rip
, dr6
;
7043 enum emulation_result er
;
7045 vect_info
= vmx
->idt_vectoring_info
;
7046 intr_info
= vmx
->exit_intr_info
;
7048 if (is_machine_check(intr_info
))
7049 return handle_machine_check(vcpu
);
7051 if (is_nmi(intr_info
))
7052 return 1; /* already handled by vmx_vcpu_run() */
7054 if (is_invalid_opcode(intr_info
))
7055 return handle_ud(vcpu
);
7058 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
7059 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7061 if (!vmx
->rmode
.vm86_active
&& is_gp_fault(intr_info
)) {
7062 WARN_ON_ONCE(!enable_vmware_backdoor
);
7063 er
= kvm_emulate_instruction(vcpu
,
7064 EMULTYPE_VMWARE
| EMULTYPE_NO_UD_ON_FAIL
);
7065 if (er
== EMULATE_USER_EXIT
)
7067 else if (er
!= EMULATE_DONE
)
7068 kvm_queue_exception_e(vcpu
, GP_VECTOR
, error_code
);
7073 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
7074 * MMIO, it is better to report an internal error.
7075 * See the comments in vmx_handle_exit.
7077 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
7078 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
7079 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7080 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
7081 vcpu
->run
->internal
.ndata
= 3;
7082 vcpu
->run
->internal
.data
[0] = vect_info
;
7083 vcpu
->run
->internal
.data
[1] = intr_info
;
7084 vcpu
->run
->internal
.data
[2] = error_code
;
7088 if (is_page_fault(intr_info
)) {
7089 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
7090 /* EPT won't cause page fault directly */
7091 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
7092 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
7095 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
7097 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
7098 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
7102 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
7105 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
7106 if (!(vcpu
->guest_debug
&
7107 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
7108 vcpu
->arch
.dr6
&= ~15;
7109 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
7110 if (is_icebp(intr_info
))
7111 skip_emulated_instruction(vcpu
);
7113 kvm_queue_exception(vcpu
, DB_VECTOR
);
7116 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
7117 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
7121 * Update instruction length as we may reinject #BP from
7122 * user space while in guest debugging mode. Reading it for
7123 * #DB as well causes no harm, it is not used in that case.
7125 vmx
->vcpu
.arch
.event_exit_inst_len
=
7126 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7127 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
7128 rip
= kvm_rip_read(vcpu
);
7129 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
7130 kvm_run
->debug
.arch
.exception
= ex_no
;
7133 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
7134 kvm_run
->ex
.exception
= ex_no
;
7135 kvm_run
->ex
.error_code
= error_code
;
7141 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
7143 ++vcpu
->stat
.irq_exits
;
7147 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
7149 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
7150 vcpu
->mmio_needed
= 0;
7154 static int handle_io(struct kvm_vcpu
*vcpu
)
7156 unsigned long exit_qualification
;
7157 int size
, in
, string
;
7160 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7161 string
= (exit_qualification
& 16) != 0;
7163 ++vcpu
->stat
.io_exits
;
7166 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
7168 port
= exit_qualification
>> 16;
7169 size
= (exit_qualification
& 7) + 1;
7170 in
= (exit_qualification
& 8) != 0;
7172 return kvm_fast_pio(vcpu
, size
, port
, in
);
7176 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
7179 * Patch in the VMCALL instruction:
7181 hypercall
[0] = 0x0f;
7182 hypercall
[1] = 0x01;
7183 hypercall
[2] = 0xc1;
7186 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
7187 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
7189 if (is_guest_mode(vcpu
)) {
7190 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7191 unsigned long orig_val
= val
;
7194 * We get here when L2 changed cr0 in a way that did not change
7195 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
7196 * but did change L0 shadowed bits. So we first calculate the
7197 * effective cr0 value that L1 would like to write into the
7198 * hardware. It consists of the L2-owned bits from the new
7199 * value combined with the L1-owned bits from L1's guest_cr0.
7201 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
7202 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
7204 if (!nested_guest_cr0_valid(vcpu
, val
))
7207 if (kvm_set_cr0(vcpu
, val
))
7209 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
7212 if (to_vmx(vcpu
)->nested
.vmxon
&&
7213 !nested_host_cr0_valid(vcpu
, val
))
7216 return kvm_set_cr0(vcpu
, val
);
7220 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
7222 if (is_guest_mode(vcpu
)) {
7223 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7224 unsigned long orig_val
= val
;
7226 /* analogously to handle_set_cr0 */
7227 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
7228 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
7229 if (kvm_set_cr4(vcpu
, val
))
7231 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
7234 return kvm_set_cr4(vcpu
, val
);
7237 static int handle_desc(struct kvm_vcpu
*vcpu
)
7239 WARN_ON(!(vcpu
->arch
.cr4
& X86_CR4_UMIP
));
7240 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
7243 static int handle_cr(struct kvm_vcpu
*vcpu
)
7245 unsigned long exit_qualification
, val
;
7251 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7252 cr
= exit_qualification
& 15;
7253 reg
= (exit_qualification
>> 8) & 15;
7254 switch ((exit_qualification
>> 4) & 3) {
7255 case 0: /* mov to cr */
7256 val
= kvm_register_readl(vcpu
, reg
);
7257 trace_kvm_cr_write(cr
, val
);
7260 err
= handle_set_cr0(vcpu
, val
);
7261 return kvm_complete_insn_gp(vcpu
, err
);
7263 WARN_ON_ONCE(enable_unrestricted_guest
);
7264 err
= kvm_set_cr3(vcpu
, val
);
7265 return kvm_complete_insn_gp(vcpu
, err
);
7267 err
= handle_set_cr4(vcpu
, val
);
7268 return kvm_complete_insn_gp(vcpu
, err
);
7270 u8 cr8_prev
= kvm_get_cr8(vcpu
);
7272 err
= kvm_set_cr8(vcpu
, cr8
);
7273 ret
= kvm_complete_insn_gp(vcpu
, err
);
7274 if (lapic_in_kernel(vcpu
))
7276 if (cr8_prev
<= cr8
)
7279 * TODO: we might be squashing a
7280 * KVM_GUESTDBG_SINGLESTEP-triggered
7281 * KVM_EXIT_DEBUG here.
7283 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
7289 WARN_ONCE(1, "Guest should always own CR0.TS");
7290 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
7291 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
7292 return kvm_skip_emulated_instruction(vcpu
);
7293 case 1: /*mov from cr*/
7296 WARN_ON_ONCE(enable_unrestricted_guest
);
7297 val
= kvm_read_cr3(vcpu
);
7298 kvm_register_write(vcpu
, reg
, val
);
7299 trace_kvm_cr_read(cr
, val
);
7300 return kvm_skip_emulated_instruction(vcpu
);
7302 val
= kvm_get_cr8(vcpu
);
7303 kvm_register_write(vcpu
, reg
, val
);
7304 trace_kvm_cr_read(cr
, val
);
7305 return kvm_skip_emulated_instruction(vcpu
);
7309 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
7310 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
7311 kvm_lmsw(vcpu
, val
);
7313 return kvm_skip_emulated_instruction(vcpu
);
7317 vcpu
->run
->exit_reason
= 0;
7318 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
7319 (int)(exit_qualification
>> 4) & 3, cr
);
7323 static int handle_dr(struct kvm_vcpu
*vcpu
)
7325 unsigned long exit_qualification
;
7328 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7329 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
7331 /* First, if DR does not exist, trigger UD */
7332 if (!kvm_require_dr(vcpu
, dr
))
7335 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
7336 if (!kvm_require_cpl(vcpu
, 0))
7338 dr7
= vmcs_readl(GUEST_DR7
);
7341 * As the vm-exit takes precedence over the debug trap, we
7342 * need to emulate the latter, either for the host or the
7343 * guest debugging itself.
7345 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
7346 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
7347 vcpu
->run
->debug
.arch
.dr7
= dr7
;
7348 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
7349 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
7350 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
7353 vcpu
->arch
.dr6
&= ~15;
7354 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
7355 kvm_queue_exception(vcpu
, DB_VECTOR
);
7360 if (vcpu
->guest_debug
== 0) {
7361 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
7362 CPU_BASED_MOV_DR_EXITING
);
7365 * No more DR vmexits; force a reload of the debug registers
7366 * and reenter on this instruction. The next vmexit will
7367 * retrieve the full state of the debug registers.
7369 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
7373 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
7374 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
7377 if (kvm_get_dr(vcpu
, dr
, &val
))
7379 kvm_register_write(vcpu
, reg
, val
);
7381 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
7384 return kvm_skip_emulated_instruction(vcpu
);
7387 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
7389 return vcpu
->arch
.dr6
;
7392 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
7396 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
7398 get_debugreg(vcpu
->arch
.db
[0], 0);
7399 get_debugreg(vcpu
->arch
.db
[1], 1);
7400 get_debugreg(vcpu
->arch
.db
[2], 2);
7401 get_debugreg(vcpu
->arch
.db
[3], 3);
7402 get_debugreg(vcpu
->arch
.dr6
, 6);
7403 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
7405 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
7406 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
7409 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
7411 vmcs_writel(GUEST_DR7
, val
);
7414 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
7416 return kvm_emulate_cpuid(vcpu
);
7419 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
7421 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7422 struct msr_data msr_info
;
7424 msr_info
.index
= ecx
;
7425 msr_info
.host_initiated
= false;
7426 if (vmx_get_msr(vcpu
, &msr_info
)) {
7427 trace_kvm_msr_read_ex(ecx
);
7428 kvm_inject_gp(vcpu
, 0);
7432 trace_kvm_msr_read(ecx
, msr_info
.data
);
7434 /* FIXME: handling of bits 32:63 of rax, rdx */
7435 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
7436 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
7437 return kvm_skip_emulated_instruction(vcpu
);
7440 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
7442 struct msr_data msr
;
7443 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7444 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
7445 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
7449 msr
.host_initiated
= false;
7450 if (kvm_set_msr(vcpu
, &msr
) != 0) {
7451 trace_kvm_msr_write_ex(ecx
, data
);
7452 kvm_inject_gp(vcpu
, 0);
7456 trace_kvm_msr_write(ecx
, data
);
7457 return kvm_skip_emulated_instruction(vcpu
);
7460 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
7462 kvm_apic_update_ppr(vcpu
);
7466 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
7468 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
7469 CPU_BASED_VIRTUAL_INTR_PENDING
);
7471 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7473 ++vcpu
->stat
.irq_window_exits
;
7477 static int handle_halt(struct kvm_vcpu
*vcpu
)
7479 return kvm_emulate_halt(vcpu
);
7482 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
7484 return kvm_emulate_hypercall(vcpu
);
7487 static int handle_invd(struct kvm_vcpu
*vcpu
)
7489 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
7492 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
7494 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7496 kvm_mmu_invlpg(vcpu
, exit_qualification
);
7497 return kvm_skip_emulated_instruction(vcpu
);
7500 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
7504 err
= kvm_rdpmc(vcpu
);
7505 return kvm_complete_insn_gp(vcpu
, err
);
7508 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
7510 return kvm_emulate_wbinvd(vcpu
);
7513 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
7515 u64 new_bv
= kvm_read_edx_eax(vcpu
);
7516 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
7518 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
7519 return kvm_skip_emulated_instruction(vcpu
);
7523 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
7525 kvm_skip_emulated_instruction(vcpu
);
7526 WARN(1, "this should never happen\n");
7530 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
7532 kvm_skip_emulated_instruction(vcpu
);
7533 WARN(1, "this should never happen\n");
7537 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
7539 if (likely(fasteoi
)) {
7540 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7541 int access_type
, offset
;
7543 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
7544 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
7546 * Sane guest uses MOV to write EOI, with written value
7547 * not cared. So make a short-circuit here by avoiding
7548 * heavy instruction emulation.
7550 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
7551 (offset
== APIC_EOI
)) {
7552 kvm_lapic_set_eoi(vcpu
);
7553 return kvm_skip_emulated_instruction(vcpu
);
7556 return kvm_emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
7559 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
7561 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7562 int vector
= exit_qualification
& 0xff;
7564 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
7565 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
7569 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
7571 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7572 u32 offset
= exit_qualification
& 0xfff;
7574 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
7575 kvm_apic_write_nodecode(vcpu
, offset
);
7579 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
7581 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7582 unsigned long exit_qualification
;
7583 bool has_error_code
= false;
7586 int reason
, type
, idt_v
, idt_index
;
7588 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
7589 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
7590 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
7592 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7594 reason
= (u32
)exit_qualification
>> 30;
7595 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
7597 case INTR_TYPE_NMI_INTR
:
7598 vcpu
->arch
.nmi_injected
= false;
7599 vmx_set_nmi_mask(vcpu
, true);
7601 case INTR_TYPE_EXT_INTR
:
7602 case INTR_TYPE_SOFT_INTR
:
7603 kvm_clear_interrupt_queue(vcpu
);
7605 case INTR_TYPE_HARD_EXCEPTION
:
7606 if (vmx
->idt_vectoring_info
&
7607 VECTORING_INFO_DELIVER_CODE_MASK
) {
7608 has_error_code
= true;
7610 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
7613 case INTR_TYPE_SOFT_EXCEPTION
:
7614 kvm_clear_exception_queue(vcpu
);
7620 tss_selector
= exit_qualification
;
7622 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
7623 type
!= INTR_TYPE_EXT_INTR
&&
7624 type
!= INTR_TYPE_NMI_INTR
))
7625 skip_emulated_instruction(vcpu
);
7627 if (kvm_task_switch(vcpu
, tss_selector
,
7628 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
7629 has_error_code
, error_code
) == EMULATE_FAIL
) {
7630 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7631 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
7632 vcpu
->run
->internal
.ndata
= 0;
7637 * TODO: What about debug traps on tss switch?
7638 * Are we supposed to inject them and update dr6?
7644 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
7646 unsigned long exit_qualification
;
7650 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7653 * EPT violation happened while executing iret from NMI,
7654 * "blocked by NMI" bit has to be set before next VM entry.
7655 * There are errata that may cause this bit to not be set:
7658 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7660 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7661 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
7663 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
7664 trace_kvm_page_fault(gpa
, exit_qualification
);
7666 /* Is it a read fault? */
7667 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
7668 ? PFERR_USER_MASK
: 0;
7669 /* Is it a write fault? */
7670 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
7671 ? PFERR_WRITE_MASK
: 0;
7672 /* Is it a fetch fault? */
7673 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
7674 ? PFERR_FETCH_MASK
: 0;
7675 /* ept page table entry is present? */
7676 error_code
|= (exit_qualification
&
7677 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
7678 EPT_VIOLATION_EXECUTABLE
))
7679 ? PFERR_PRESENT_MASK
: 0;
7681 error_code
|= (exit_qualification
& 0x100) != 0 ?
7682 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
7684 vcpu
->arch
.exit_qualification
= exit_qualification
;
7685 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
7688 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
7693 * A nested guest cannot optimize MMIO vmexits, because we have an
7694 * nGPA here instead of the required GPA.
7696 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
7697 if (!is_guest_mode(vcpu
) &&
7698 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
7699 trace_kvm_fast_mmio(gpa
);
7701 * Doing kvm_skip_emulated_instruction() depends on undefined
7702 * behavior: Intel's manual doesn't mandate
7703 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
7704 * occurs and while on real hardware it was observed to be set,
7705 * other hypervisors (namely Hyper-V) don't set it, we end up
7706 * advancing IP with some random value. Disable fast mmio when
7707 * running nested and keep it for real hardware in hope that
7708 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
7710 if (!static_cpu_has(X86_FEATURE_HYPERVISOR
))
7711 return kvm_skip_emulated_instruction(vcpu
);
7713 return kvm_emulate_instruction(vcpu
, EMULTYPE_SKIP
) ==
7717 return kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
7720 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
7722 WARN_ON_ONCE(!enable_vnmi
);
7723 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
7724 CPU_BASED_VIRTUAL_NMI_PENDING
);
7725 ++vcpu
->stat
.nmi_window_exits
;
7726 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7731 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
7733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7734 enum emulation_result err
= EMULATE_DONE
;
7737 bool intr_window_requested
;
7738 unsigned count
= 130;
7741 * We should never reach the point where we are emulating L2
7742 * due to invalid guest state as that means we incorrectly
7743 * allowed a nested VMEntry with an invalid vmcs12.
7745 WARN_ON_ONCE(vmx
->emulation_required
&& vmx
->nested
.nested_run_pending
);
7747 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7748 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
7750 while (vmx
->emulation_required
&& count
-- != 0) {
7751 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
7752 return handle_interrupt_window(&vmx
->vcpu
);
7754 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
7757 err
= kvm_emulate_instruction(vcpu
, 0);
7759 if (err
== EMULATE_USER_EXIT
) {
7760 ++vcpu
->stat
.mmio_exits
;
7765 if (err
!= EMULATE_DONE
)
7766 goto emulation_error
;
7768 if (vmx
->emulation_required
&& !vmx
->rmode
.vm86_active
&&
7769 vcpu
->arch
.exception
.pending
)
7770 goto emulation_error
;
7772 if (vcpu
->arch
.halt_request
) {
7773 vcpu
->arch
.halt_request
= 0;
7774 ret
= kvm_vcpu_halt(vcpu
);
7778 if (signal_pending(current
))
7788 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7789 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
7790 vcpu
->run
->internal
.ndata
= 0;
7794 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
7796 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7797 int old
= vmx
->ple_window
;
7799 vmx
->ple_window
= __grow_ple_window(old
, ple_window
,
7803 if (vmx
->ple_window
!= old
)
7804 vmx
->ple_window_dirty
= true;
7806 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
7809 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
7811 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7812 int old
= vmx
->ple_window
;
7814 vmx
->ple_window
= __shrink_ple_window(old
, ple_window
,
7818 if (vmx
->ple_window
!= old
)
7819 vmx
->ple_window_dirty
= true;
7821 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
7825 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
7827 static void wakeup_handler(void)
7829 struct kvm_vcpu
*vcpu
;
7830 int cpu
= smp_processor_id();
7832 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
7833 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
7834 blocked_vcpu_list
) {
7835 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
7837 if (pi_test_on(pi_desc
) == 1)
7838 kvm_vcpu_kick(vcpu
);
7840 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
7843 static void vmx_enable_tdp(void)
7845 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
7846 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
7847 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
7848 0ull, VMX_EPT_EXECUTABLE_MASK
,
7849 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
7850 VMX_EPT_RWX_MASK
, 0ull);
7852 ept_set_mmio_spte_mask();
7856 static __init
int hardware_setup(void)
7858 unsigned long host_bndcfgs
;
7861 rdmsrl_safe(MSR_EFER
, &host_efer
);
7863 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
7864 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7866 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
7867 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
7872 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
7873 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
7875 if (setup_vmcs_config(&vmcs_config
) < 0) {
7880 if (boot_cpu_has(X86_FEATURE_NX
))
7881 kvm_enable_efer_bits(EFER_NX
);
7883 if (boot_cpu_has(X86_FEATURE_MPX
)) {
7884 rdmsrl(MSR_IA32_BNDCFGS
, host_bndcfgs
);
7885 WARN_ONCE(host_bndcfgs
, "KVM: BNDCFGS in host will be lost");
7888 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7889 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7892 if (!cpu_has_vmx_ept() ||
7893 !cpu_has_vmx_ept_4levels() ||
7894 !cpu_has_vmx_ept_mt_wb() ||
7895 !cpu_has_vmx_invept_global())
7898 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
7899 enable_ept_ad_bits
= 0;
7901 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
7902 enable_unrestricted_guest
= 0;
7904 if (!cpu_has_vmx_flexpriority())
7905 flexpriority_enabled
= 0;
7907 if (!cpu_has_virtual_nmis())
7911 * set_apic_access_page_addr() is used to reload apic access
7912 * page upon invalidation. No need to do anything if not
7913 * using the APIC_ACCESS_ADDR VMCS field.
7915 if (!flexpriority_enabled
)
7916 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
7918 if (!cpu_has_vmx_tpr_shadow())
7919 kvm_x86_ops
->update_cr8_intercept
= NULL
;
7921 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
7922 kvm_disable_largepages();
7924 #if IS_ENABLED(CONFIG_HYPERV)
7925 if (ms_hyperv
.nested_features
& HV_X64_NESTED_GUEST_MAPPING_FLUSH
7927 kvm_x86_ops
->tlb_remote_flush
= vmx_hv_remote_flush_tlb
;
7930 if (!cpu_has_vmx_ple()) {
7933 ple_window_grow
= 0;
7935 ple_window_shrink
= 0;
7938 if (!cpu_has_vmx_apicv()) {
7940 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
7943 if (cpu_has_vmx_tsc_scaling()) {
7944 kvm_has_tsc_control
= true;
7945 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
7946 kvm_tsc_scaling_ratio_frac_bits
= 48;
7949 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7957 kvm_x86_ops
->get_nested_state
= NULL
;
7958 kvm_x86_ops
->set_nested_state
= NULL
;
7962 * Only enable PML when hardware supports PML feature, and both EPT
7963 * and EPT A/D bit features are enabled -- PML depends on them to work.
7965 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
7969 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
7970 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
7971 kvm_x86_ops
->flush_log_dirty
= NULL
;
7972 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
7975 if (!cpu_has_vmx_preemption_timer())
7976 kvm_x86_ops
->request_immediate_exit
= __kvm_request_immediate_exit
;
7978 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
7981 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
7982 cpu_preemption_timer_multi
=
7983 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
7985 kvm_x86_ops
->set_hv_timer
= NULL
;
7986 kvm_x86_ops
->cancel_hv_timer
= NULL
;
7989 if (!cpu_has_vmx_shadow_vmcs())
7990 enable_shadow_vmcs
= 0;
7991 if (enable_shadow_vmcs
)
7992 init_vmcs_shadow_fields();
7994 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
7995 nested_vmx_setup_ctls_msrs(&vmcs_config
.nested
, enable_apicv
);
7997 kvm_mce_cap_supported
|= MCG_LMCE_P
;
7999 return alloc_kvm_area();
8002 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
8003 free_page((unsigned long)vmx_bitmap
[i
]);
8008 static __exit
void hardware_unsetup(void)
8012 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
8013 free_page((unsigned long)vmx_bitmap
[i
]);
8019 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
8020 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
8022 static int handle_pause(struct kvm_vcpu
*vcpu
)
8024 if (!kvm_pause_in_guest(vcpu
->kvm
))
8025 grow_ple_window(vcpu
);
8028 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
8029 * VM-execution control is ignored if CPL > 0. OTOH, KVM
8030 * never set PAUSE_EXITING and just set PLE if supported,
8031 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
8033 kvm_vcpu_on_spin(vcpu
, true);
8034 return kvm_skip_emulated_instruction(vcpu
);
8037 static int handle_nop(struct kvm_vcpu
*vcpu
)
8039 return kvm_skip_emulated_instruction(vcpu
);
8042 static int handle_mwait(struct kvm_vcpu
*vcpu
)
8044 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
8045 return handle_nop(vcpu
);
8048 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
8050 kvm_queue_exception(vcpu
, UD_VECTOR
);
8054 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
8059 static int handle_monitor(struct kvm_vcpu
*vcpu
)
8061 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
8062 return handle_nop(vcpu
);
8066 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
8067 * set the success or error code of an emulated VMX instruction, as specified
8068 * by Vol 2B, VMX Instruction Reference, "Conventions".
8070 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
8072 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
8073 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
8074 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
8077 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
8079 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
8080 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
8081 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
8085 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
8086 u32 vm_instruction_error
)
8088 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
8090 * failValid writes the error number to the current VMCS, which
8091 * can't be done there isn't a current VMCS.
8093 nested_vmx_failInvalid(vcpu
);
8096 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
8097 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
8098 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
8100 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
8102 * We don't need to force a shadow sync because
8103 * VM_INSTRUCTION_ERROR is not shadowed
8107 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
8109 /* TODO: not to reset guest simply here. */
8110 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
8111 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
8114 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
8116 struct vcpu_vmx
*vmx
=
8117 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
8119 vmx
->nested
.preemption_timer_expired
= true;
8120 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
8121 kvm_vcpu_kick(&vmx
->vcpu
);
8123 return HRTIMER_NORESTART
;
8127 * Decode the memory-address operand of a vmx instruction, as recorded on an
8128 * exit caused by such an instruction (run by a guest hypervisor).
8129 * On success, returns 0. When the operand is invalid, returns 1 and throws
8132 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
8133 unsigned long exit_qualification
,
8134 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
8138 struct kvm_segment s
;
8141 * According to Vol. 3B, "Information for VM Exits Due to Instruction
8142 * Execution", on an exit, vmx_instruction_info holds most of the
8143 * addressing components of the operand. Only the displacement part
8144 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
8145 * For how an actual address is calculated from all these components,
8146 * refer to Vol. 1, "Operand Addressing".
8148 int scaling
= vmx_instruction_info
& 3;
8149 int addr_size
= (vmx_instruction_info
>> 7) & 7;
8150 bool is_reg
= vmx_instruction_info
& (1u << 10);
8151 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
8152 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
8153 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
8154 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
8155 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
8158 kvm_queue_exception(vcpu
, UD_VECTOR
);
8162 /* Addr = segment_base + offset */
8163 /* offset = base + [index * scale] + displacement */
8164 off
= exit_qualification
; /* holds the displacement */
8166 off
+= kvm_register_read(vcpu
, base_reg
);
8168 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
8169 vmx_get_segment(vcpu
, &s
, seg_reg
);
8170 *ret
= s
.base
+ off
;
8172 if (addr_size
== 1) /* 32 bit */
8175 /* Checks for #GP/#SS exceptions. */
8177 if (is_long_mode(vcpu
)) {
8178 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
8179 * non-canonical form. This is the only check on the memory
8180 * destination for long mode!
8182 exn
= is_noncanonical_address(*ret
, vcpu
);
8183 } else if (is_protmode(vcpu
)) {
8184 /* Protected mode: apply checks for segment validity in the
8186 * - segment type check (#GP(0) may be thrown)
8187 * - usability check (#GP(0)/#SS(0))
8188 * - limit check (#GP(0)/#SS(0))
8191 /* #GP(0) if the destination operand is located in a
8192 * read-only data segment or any code segment.
8194 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
8196 /* #GP(0) if the source operand is located in an
8197 * execute-only code segment
8199 exn
= ((s
.type
& 0xa) == 8);
8201 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
8204 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
8206 exn
= (s
.unusable
!= 0);
8207 /* Protected mode: #GP(0)/#SS(0) if the memory
8208 * operand is outside the segment limit.
8210 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
8213 kvm_queue_exception_e(vcpu
,
8214 seg_reg
== VCPU_SREG_SS
?
8215 SS_VECTOR
: GP_VECTOR
,
8223 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
8226 struct x86_exception e
;
8228 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
8229 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
8232 if (kvm_read_guest_virt(vcpu
, gva
, vmpointer
, sizeof(*vmpointer
), &e
)) {
8233 kvm_inject_page_fault(vcpu
, &e
);
8241 * Allocate a shadow VMCS and associate it with the currently loaded
8242 * VMCS, unless such a shadow VMCS already exists. The newly allocated
8243 * VMCS is also VMCLEARed, so that it is ready for use.
8245 static struct vmcs
*alloc_shadow_vmcs(struct kvm_vcpu
*vcpu
)
8247 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8248 struct loaded_vmcs
*loaded_vmcs
= vmx
->loaded_vmcs
;
8251 * We should allocate a shadow vmcs for vmcs01 only when L1
8252 * executes VMXON and free it when L1 executes VMXOFF.
8253 * As it is invalid to execute VMXON twice, we shouldn't reach
8254 * here when vmcs01 already have an allocated shadow vmcs.
8256 WARN_ON(loaded_vmcs
== &vmx
->vmcs01
&& loaded_vmcs
->shadow_vmcs
);
8258 if (!loaded_vmcs
->shadow_vmcs
) {
8259 loaded_vmcs
->shadow_vmcs
= alloc_vmcs(true);
8260 if (loaded_vmcs
->shadow_vmcs
)
8261 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
8263 return loaded_vmcs
->shadow_vmcs
;
8266 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
8268 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8271 r
= alloc_loaded_vmcs(&vmx
->nested
.vmcs02
);
8275 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
8276 if (!vmx
->nested
.cached_vmcs12
)
8277 goto out_cached_vmcs12
;
8279 vmx
->nested
.cached_shadow_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
8280 if (!vmx
->nested
.cached_shadow_vmcs12
)
8281 goto out_cached_shadow_vmcs12
;
8283 if (enable_shadow_vmcs
&& !alloc_shadow_vmcs(vcpu
))
8284 goto out_shadow_vmcs
;
8286 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
8287 HRTIMER_MODE_REL_PINNED
);
8288 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
8290 vmx
->nested
.vpid02
= allocate_vpid();
8292 vmx
->nested
.vmxon
= true;
8296 kfree(vmx
->nested
.cached_shadow_vmcs12
);
8298 out_cached_shadow_vmcs12
:
8299 kfree(vmx
->nested
.cached_vmcs12
);
8302 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
8309 * Emulate the VMXON instruction.
8310 * Currently, we just remember that VMX is active, and do not save or even
8311 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
8312 * do not currently need to store anything in that guest-allocated memory
8313 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
8314 * argument is different from the VMXON pointer (which the spec says they do).
8316 static int handle_vmon(struct kvm_vcpu
*vcpu
)
8321 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8322 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
8323 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
8326 * The Intel VMX Instruction Reference lists a bunch of bits that are
8327 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
8328 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
8329 * Otherwise, we should fail with #UD. But most faulting conditions
8330 * have already been checked by hardware, prior to the VM-exit for
8331 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
8332 * that bit set to 1 in non-root mode.
8334 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
8335 kvm_queue_exception(vcpu
, UD_VECTOR
);
8339 /* CPL=0 must be checked manually. */
8340 if (vmx_get_cpl(vcpu
)) {
8341 kvm_inject_gp(vcpu
, 0);
8345 if (vmx
->nested
.vmxon
) {
8346 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
8347 return kvm_skip_emulated_instruction(vcpu
);
8350 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
8351 != VMXON_NEEDED_FEATURES
) {
8352 kvm_inject_gp(vcpu
, 0);
8356 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
8361 * The first 4 bytes of VMXON region contain the supported
8362 * VMCS revision identifier
8364 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
8365 * which replaces physical address width with 32
8367 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
8368 nested_vmx_failInvalid(vcpu
);
8369 return kvm_skip_emulated_instruction(vcpu
);
8372 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
8373 if (is_error_page(page
)) {
8374 nested_vmx_failInvalid(vcpu
);
8375 return kvm_skip_emulated_instruction(vcpu
);
8377 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
8379 kvm_release_page_clean(page
);
8380 nested_vmx_failInvalid(vcpu
);
8381 return kvm_skip_emulated_instruction(vcpu
);
8384 kvm_release_page_clean(page
);
8386 vmx
->nested
.vmxon_ptr
= vmptr
;
8387 ret
= enter_vmx_operation(vcpu
);
8391 nested_vmx_succeed(vcpu
);
8392 return kvm_skip_emulated_instruction(vcpu
);
8396 * Intel's VMX Instruction Reference specifies a common set of prerequisites
8397 * for running VMX instructions (except VMXON, whose prerequisites are
8398 * slightly different). It also specifies what exception to inject otherwise.
8399 * Note that many of these exceptions have priority over VM exits, so they
8400 * don't have to be checked again here.
8402 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
8404 if (!to_vmx(vcpu
)->nested
.vmxon
) {
8405 kvm_queue_exception(vcpu
, UD_VECTOR
);
8409 if (vmx_get_cpl(vcpu
)) {
8410 kvm_inject_gp(vcpu
, 0);
8417 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
8419 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
8420 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
8423 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
8425 if (vmx
->nested
.current_vmptr
== -1ull)
8428 if (enable_shadow_vmcs
) {
8429 /* copy to memory all shadowed fields in case
8430 they were modified */
8431 copy_shadow_to_vmcs12(vmx
);
8432 vmx
->nested
.sync_shadow_vmcs
= false;
8433 vmx_disable_shadow_vmcs(vmx
);
8435 vmx
->nested
.posted_intr_nv
= -1;
8437 /* Flush VMCS12 to guest memory */
8438 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
8439 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
8440 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
8442 vmx
->nested
.current_vmptr
= -1ull;
8446 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
8447 * just stops using VMX.
8449 static void free_nested(struct vcpu_vmx
*vmx
)
8451 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
8454 vmx
->nested
.vmxon
= false;
8455 vmx
->nested
.smm
.vmxon
= false;
8456 free_vpid(vmx
->nested
.vpid02
);
8457 vmx
->nested
.posted_intr_nv
= -1;
8458 vmx
->nested
.current_vmptr
= -1ull;
8459 if (enable_shadow_vmcs
) {
8460 vmx_disable_shadow_vmcs(vmx
);
8461 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
8462 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
8463 vmx
->vmcs01
.shadow_vmcs
= NULL
;
8465 kfree(vmx
->nested
.cached_vmcs12
);
8466 kfree(vmx
->nested
.cached_shadow_vmcs12
);
8467 /* Unpin physical memory we referred to in the vmcs02 */
8468 if (vmx
->nested
.apic_access_page
) {
8469 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
8470 vmx
->nested
.apic_access_page
= NULL
;
8472 if (vmx
->nested
.virtual_apic_page
) {
8473 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
8474 vmx
->nested
.virtual_apic_page
= NULL
;
8476 if (vmx
->nested
.pi_desc_page
) {
8477 kunmap(vmx
->nested
.pi_desc_page
);
8478 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
8479 vmx
->nested
.pi_desc_page
= NULL
;
8480 vmx
->nested
.pi_desc
= NULL
;
8483 free_loaded_vmcs(&vmx
->nested
.vmcs02
);
8486 /* Emulate the VMXOFF instruction */
8487 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
8489 if (!nested_vmx_check_permission(vcpu
))
8491 free_nested(to_vmx(vcpu
));
8492 nested_vmx_succeed(vcpu
);
8493 return kvm_skip_emulated_instruction(vcpu
);
8496 /* Emulate the VMCLEAR instruction */
8497 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
8499 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8503 if (!nested_vmx_check_permission(vcpu
))
8506 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
8509 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
8510 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
8511 return kvm_skip_emulated_instruction(vcpu
);
8514 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
8515 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
8516 return kvm_skip_emulated_instruction(vcpu
);
8519 if (vmptr
== vmx
->nested
.current_vmptr
)
8520 nested_release_vmcs12(vmx
);
8522 kvm_vcpu_write_guest(vcpu
,
8523 vmptr
+ offsetof(struct vmcs12
, launch_state
),
8524 &zero
, sizeof(zero
));
8526 nested_vmx_succeed(vcpu
);
8527 return kvm_skip_emulated_instruction(vcpu
);
8530 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
8532 /* Emulate the VMLAUNCH instruction */
8533 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
8535 return nested_vmx_run(vcpu
, true);
8538 /* Emulate the VMRESUME instruction */
8539 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
8542 return nested_vmx_run(vcpu
, false);
8546 * Read a vmcs12 field. Since these can have varying lengths and we return
8547 * one type, we chose the biggest type (u64) and zero-extend the return value
8548 * to that size. Note that the caller, handle_vmread, might need to use only
8549 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
8550 * 64-bit fields are to be returned).
8552 static inline int vmcs12_read_any(struct vmcs12
*vmcs12
,
8553 unsigned long field
, u64
*ret
)
8555 short offset
= vmcs_field_to_offset(field
);
8561 p
= (char *)vmcs12
+ offset
;
8563 switch (vmcs_field_width(field
)) {
8564 case VMCS_FIELD_WIDTH_NATURAL_WIDTH
:
8565 *ret
= *((natural_width
*)p
);
8567 case VMCS_FIELD_WIDTH_U16
:
8570 case VMCS_FIELD_WIDTH_U32
:
8573 case VMCS_FIELD_WIDTH_U64
:
8583 static inline int vmcs12_write_any(struct vmcs12
*vmcs12
,
8584 unsigned long field
, u64 field_value
){
8585 short offset
= vmcs_field_to_offset(field
);
8586 char *p
= (char *)vmcs12
+ offset
;
8590 switch (vmcs_field_width(field
)) {
8591 case VMCS_FIELD_WIDTH_U16
:
8592 *(u16
*)p
= field_value
;
8594 case VMCS_FIELD_WIDTH_U32
:
8595 *(u32
*)p
= field_value
;
8597 case VMCS_FIELD_WIDTH_U64
:
8598 *(u64
*)p
= field_value
;
8600 case VMCS_FIELD_WIDTH_NATURAL_WIDTH
:
8601 *(natural_width
*)p
= field_value
;
8611 * Copy the writable VMCS shadow fields back to the VMCS12, in case
8612 * they have been modified by the L1 guest. Note that the "read-only"
8613 * VM-exit information fields are actually writable if the vCPU is
8614 * configured to support "VMWRITE to any supported field in the VMCS."
8616 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
8618 const u16
*fields
[] = {
8619 shadow_read_write_fields
,
8620 shadow_read_only_fields
8622 const int max_fields
[] = {
8623 max_shadow_read_write_fields
,
8624 max_shadow_read_only_fields
8627 unsigned long field
;
8629 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
8633 vmcs_load(shadow_vmcs
);
8635 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
8636 for (i
= 0; i
< max_fields
[q
]; i
++) {
8637 field
= fields
[q
][i
];
8638 field_value
= __vmcs_readl(field
);
8639 vmcs12_write_any(get_vmcs12(&vmx
->vcpu
), field
, field_value
);
8642 * Skip the VM-exit information fields if they are read-only.
8644 if (!nested_cpu_has_vmwrite_any_field(&vmx
->vcpu
))
8648 vmcs_clear(shadow_vmcs
);
8649 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
8654 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
8656 const u16
*fields
[] = {
8657 shadow_read_write_fields
,
8658 shadow_read_only_fields
8660 const int max_fields
[] = {
8661 max_shadow_read_write_fields
,
8662 max_shadow_read_only_fields
8665 unsigned long field
;
8666 u64 field_value
= 0;
8667 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
8669 vmcs_load(shadow_vmcs
);
8671 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
8672 for (i
= 0; i
< max_fields
[q
]; i
++) {
8673 field
= fields
[q
][i
];
8674 vmcs12_read_any(get_vmcs12(&vmx
->vcpu
), field
, &field_value
);
8675 __vmcs_writel(field
, field_value
);
8679 vmcs_clear(shadow_vmcs
);
8680 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
8684 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
8685 * used before) all generate the same failure when it is missing.
8687 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
8689 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8690 if (vmx
->nested
.current_vmptr
== -1ull) {
8691 nested_vmx_failInvalid(vcpu
);
8697 static int handle_vmread(struct kvm_vcpu
*vcpu
)
8699 unsigned long field
;
8701 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8702 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8704 struct vmcs12
*vmcs12
;
8706 if (!nested_vmx_check_permission(vcpu
))
8709 if (!nested_vmx_check_vmcs12(vcpu
))
8710 return kvm_skip_emulated_instruction(vcpu
);
8712 if (!is_guest_mode(vcpu
))
8713 vmcs12
= get_vmcs12(vcpu
);
8716 * When vmcs->vmcs_link_pointer is -1ull, any VMREAD
8717 * to shadowed-field sets the ALU flags for VMfailInvalid.
8719 if (get_vmcs12(vcpu
)->vmcs_link_pointer
== -1ull) {
8720 nested_vmx_failInvalid(vcpu
);
8721 return kvm_skip_emulated_instruction(vcpu
);
8723 vmcs12
= get_shadow_vmcs12(vcpu
);
8726 /* Decode instruction info and find the field to read */
8727 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
8728 /* Read the field, zero-extended to a u64 field_value */
8729 if (vmcs12_read_any(vmcs12
, field
, &field_value
) < 0) {
8730 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
8731 return kvm_skip_emulated_instruction(vcpu
);
8734 * Now copy part of this value to register or memory, as requested.
8735 * Note that the number of bits actually copied is 32 or 64 depending
8736 * on the guest's mode (32 or 64 bit), not on the given field's length.
8738 if (vmx_instruction_info
& (1u << 10)) {
8739 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
8742 if (get_vmx_mem_address(vcpu
, exit_qualification
,
8743 vmx_instruction_info
, true, &gva
))
8745 /* _system ok, nested_vmx_check_permission has verified cpl=0 */
8746 kvm_write_guest_virt_system(vcpu
, gva
, &field_value
,
8747 (is_long_mode(vcpu
) ? 8 : 4), NULL
);
8750 nested_vmx_succeed(vcpu
);
8751 return kvm_skip_emulated_instruction(vcpu
);
8755 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
8757 unsigned long field
;
8759 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8760 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8761 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8763 /* The value to write might be 32 or 64 bits, depending on L1's long
8764 * mode, and eventually we need to write that into a field of several
8765 * possible lengths. The code below first zero-extends the value to 64
8766 * bit (field_value), and then copies only the appropriate number of
8767 * bits into the vmcs12 field.
8769 u64 field_value
= 0;
8770 struct x86_exception e
;
8771 struct vmcs12
*vmcs12
;
8773 if (!nested_vmx_check_permission(vcpu
))
8776 if (!nested_vmx_check_vmcs12(vcpu
))
8777 return kvm_skip_emulated_instruction(vcpu
);
8779 if (vmx_instruction_info
& (1u << 10))
8780 field_value
= kvm_register_readl(vcpu
,
8781 (((vmx_instruction_info
) >> 3) & 0xf));
8783 if (get_vmx_mem_address(vcpu
, exit_qualification
,
8784 vmx_instruction_info
, false, &gva
))
8786 if (kvm_read_guest_virt(vcpu
, gva
, &field_value
,
8787 (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
8788 kvm_inject_page_fault(vcpu
, &e
);
8794 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
8796 * If the vCPU supports "VMWRITE to any supported field in the
8797 * VMCS," then the "read-only" fields are actually read/write.
8799 if (vmcs_field_readonly(field
) &&
8800 !nested_cpu_has_vmwrite_any_field(vcpu
)) {
8801 nested_vmx_failValid(vcpu
,
8802 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
8803 return kvm_skip_emulated_instruction(vcpu
);
8806 if (!is_guest_mode(vcpu
))
8807 vmcs12
= get_vmcs12(vcpu
);
8810 * When vmcs->vmcs_link_pointer is -1ull, any VMWRITE
8811 * to shadowed-field sets the ALU flags for VMfailInvalid.
8813 if (get_vmcs12(vcpu
)->vmcs_link_pointer
== -1ull) {
8814 nested_vmx_failInvalid(vcpu
);
8815 return kvm_skip_emulated_instruction(vcpu
);
8817 vmcs12
= get_shadow_vmcs12(vcpu
);
8821 if (vmcs12_write_any(vmcs12
, field
, field_value
) < 0) {
8822 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
8823 return kvm_skip_emulated_instruction(vcpu
);
8827 * Do not track vmcs12 dirty-state if in guest-mode
8828 * as we actually dirty shadow vmcs12 instead of vmcs12.
8830 if (!is_guest_mode(vcpu
)) {
8832 #define SHADOW_FIELD_RW(x) case x:
8833 #include "vmx_shadow_fields.h"
8835 * The fields that can be updated by L1 without a vmexit are
8836 * always updated in the vmcs02, the others go down the slow
8837 * path of prepare_vmcs02.
8841 vmx
->nested
.dirty_vmcs12
= true;
8846 nested_vmx_succeed(vcpu
);
8847 return kvm_skip_emulated_instruction(vcpu
);
8850 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
8852 vmx
->nested
.current_vmptr
= vmptr
;
8853 if (enable_shadow_vmcs
) {
8854 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
8855 SECONDARY_EXEC_SHADOW_VMCS
);
8856 vmcs_write64(VMCS_LINK_POINTER
,
8857 __pa(vmx
->vmcs01
.shadow_vmcs
));
8858 vmx
->nested
.sync_shadow_vmcs
= true;
8860 vmx
->nested
.dirty_vmcs12
= true;
8863 /* Emulate the VMPTRLD instruction */
8864 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
8866 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8869 if (!nested_vmx_check_permission(vcpu
))
8872 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
8875 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
8876 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
8877 return kvm_skip_emulated_instruction(vcpu
);
8880 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
8881 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
8882 return kvm_skip_emulated_instruction(vcpu
);
8885 if (vmx
->nested
.current_vmptr
!= vmptr
) {
8886 struct vmcs12
*new_vmcs12
;
8888 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
8889 if (is_error_page(page
)) {
8890 nested_vmx_failInvalid(vcpu
);
8891 return kvm_skip_emulated_instruction(vcpu
);
8893 new_vmcs12
= kmap(page
);
8894 if (new_vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
||
8895 (new_vmcs12
->hdr
.shadow_vmcs
&&
8896 !nested_cpu_has_vmx_shadow_vmcs(vcpu
))) {
8898 kvm_release_page_clean(page
);
8899 nested_vmx_failValid(vcpu
,
8900 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
8901 return kvm_skip_emulated_instruction(vcpu
);
8904 nested_release_vmcs12(vmx
);
8906 * Load VMCS12 from guest memory since it is not already
8909 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
8911 kvm_release_page_clean(page
);
8913 set_current_vmptr(vmx
, vmptr
);
8916 nested_vmx_succeed(vcpu
);
8917 return kvm_skip_emulated_instruction(vcpu
);
8920 /* Emulate the VMPTRST instruction */
8921 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
8923 unsigned long exit_qual
= vmcs_readl(EXIT_QUALIFICATION
);
8924 u32 instr_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8925 gpa_t current_vmptr
= to_vmx(vcpu
)->nested
.current_vmptr
;
8926 struct x86_exception e
;
8929 if (!nested_vmx_check_permission(vcpu
))
8932 if (get_vmx_mem_address(vcpu
, exit_qual
, instr_info
, true, &gva
))
8934 /* *_system ok, nested_vmx_check_permission has verified cpl=0 */
8935 if (kvm_write_guest_virt_system(vcpu
, gva
, (void *)¤t_vmptr
,
8936 sizeof(gpa_t
), &e
)) {
8937 kvm_inject_page_fault(vcpu
, &e
);
8940 nested_vmx_succeed(vcpu
);
8941 return kvm_skip_emulated_instruction(vcpu
);
8944 /* Emulate the INVEPT instruction */
8945 static int handle_invept(struct kvm_vcpu
*vcpu
)
8947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8948 u32 vmx_instruction_info
, types
;
8951 struct x86_exception e
;
8956 if (!(vmx
->nested
.msrs
.secondary_ctls_high
&
8957 SECONDARY_EXEC_ENABLE_EPT
) ||
8958 !(vmx
->nested
.msrs
.ept_caps
& VMX_EPT_INVEPT_BIT
)) {
8959 kvm_queue_exception(vcpu
, UD_VECTOR
);
8963 if (!nested_vmx_check_permission(vcpu
))
8966 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8967 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
8969 types
= (vmx
->nested
.msrs
.ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
8971 if (type
>= 32 || !(types
& (1 << type
))) {
8972 nested_vmx_failValid(vcpu
,
8973 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
8974 return kvm_skip_emulated_instruction(vcpu
);
8977 /* According to the Intel VMX instruction reference, the memory
8978 * operand is read even if it isn't needed (e.g., for type==global)
8980 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
8981 vmx_instruction_info
, false, &gva
))
8983 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
8984 kvm_inject_page_fault(vcpu
, &e
);
8989 case VMX_EPT_EXTENT_GLOBAL
:
8991 * TODO: track mappings and invalidate
8992 * single context requests appropriately
8994 case VMX_EPT_EXTENT_CONTEXT
:
8995 kvm_mmu_sync_roots(vcpu
);
8996 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
8997 nested_vmx_succeed(vcpu
);
9004 return kvm_skip_emulated_instruction(vcpu
);
9007 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
9009 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9010 u32 vmx_instruction_info
;
9011 unsigned long type
, types
;
9013 struct x86_exception e
;
9019 if (!(vmx
->nested
.msrs
.secondary_ctls_high
&
9020 SECONDARY_EXEC_ENABLE_VPID
) ||
9021 !(vmx
->nested
.msrs
.vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
9022 kvm_queue_exception(vcpu
, UD_VECTOR
);
9026 if (!nested_vmx_check_permission(vcpu
))
9029 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9030 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
9032 types
= (vmx
->nested
.msrs
.vpid_caps
&
9033 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
9035 if (type
>= 32 || !(types
& (1 << type
))) {
9036 nested_vmx_failValid(vcpu
,
9037 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
9038 return kvm_skip_emulated_instruction(vcpu
);
9041 /* according to the intel vmx instruction reference, the memory
9042 * operand is read even if it isn't needed (e.g., for type==global)
9044 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
9045 vmx_instruction_info
, false, &gva
))
9047 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
9048 kvm_inject_page_fault(vcpu
, &e
);
9051 if (operand
.vpid
>> 16) {
9052 nested_vmx_failValid(vcpu
,
9053 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
9054 return kvm_skip_emulated_instruction(vcpu
);
9058 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
9059 if (!operand
.vpid
||
9060 is_noncanonical_address(operand
.gla
, vcpu
)) {
9061 nested_vmx_failValid(vcpu
,
9062 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
9063 return kvm_skip_emulated_instruction(vcpu
);
9065 if (cpu_has_vmx_invvpid_individual_addr() &&
9066 vmx
->nested
.vpid02
) {
9067 __invvpid(VMX_VPID_EXTENT_INDIVIDUAL_ADDR
,
9068 vmx
->nested
.vpid02
, operand
.gla
);
9070 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
, true);
9072 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
9073 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
9074 if (!operand
.vpid
) {
9075 nested_vmx_failValid(vcpu
,
9076 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
9077 return kvm_skip_emulated_instruction(vcpu
);
9079 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
, true);
9081 case VMX_VPID_EXTENT_ALL_CONTEXT
:
9082 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
, true);
9086 return kvm_skip_emulated_instruction(vcpu
);
9089 nested_vmx_succeed(vcpu
);
9091 return kvm_skip_emulated_instruction(vcpu
);
9094 static int handle_invpcid(struct kvm_vcpu
*vcpu
)
9096 u32 vmx_instruction_info
;
9100 struct x86_exception e
;
9102 unsigned long roots_to_free
= 0;
9108 if (!guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
)) {
9109 kvm_queue_exception(vcpu
, UD_VECTOR
);
9113 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9114 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
9117 kvm_inject_gp(vcpu
, 0);
9121 /* According to the Intel instruction reference, the memory operand
9122 * is read even if it isn't needed (e.g., for type==all)
9124 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
9125 vmx_instruction_info
, false, &gva
))
9128 if (kvm_read_guest_virt(vcpu
, gva
, &operand
, sizeof(operand
), &e
)) {
9129 kvm_inject_page_fault(vcpu
, &e
);
9133 if (operand
.pcid
>> 12 != 0) {
9134 kvm_inject_gp(vcpu
, 0);
9138 pcid_enabled
= kvm_read_cr4_bits(vcpu
, X86_CR4_PCIDE
);
9141 case INVPCID_TYPE_INDIV_ADDR
:
9142 if ((!pcid_enabled
&& (operand
.pcid
!= 0)) ||
9143 is_noncanonical_address(operand
.gla
, vcpu
)) {
9144 kvm_inject_gp(vcpu
, 0);
9147 kvm_mmu_invpcid_gva(vcpu
, operand
.gla
, operand
.pcid
);
9148 return kvm_skip_emulated_instruction(vcpu
);
9150 case INVPCID_TYPE_SINGLE_CTXT
:
9151 if (!pcid_enabled
&& (operand
.pcid
!= 0)) {
9152 kvm_inject_gp(vcpu
, 0);
9156 if (kvm_get_active_pcid(vcpu
) == operand
.pcid
) {
9157 kvm_mmu_sync_roots(vcpu
);
9158 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
9161 for (i
= 0; i
< KVM_MMU_NUM_PREV_ROOTS
; i
++)
9162 if (kvm_get_pcid(vcpu
, vcpu
->arch
.mmu
.prev_roots
[i
].cr3
)
9164 roots_to_free
|= KVM_MMU_ROOT_PREVIOUS(i
);
9166 kvm_mmu_free_roots(vcpu
, roots_to_free
);
9168 * If neither the current cr3 nor any of the prev_roots use the
9169 * given PCID, then nothing needs to be done here because a
9170 * resync will happen anyway before switching to any other CR3.
9173 return kvm_skip_emulated_instruction(vcpu
);
9175 case INVPCID_TYPE_ALL_NON_GLOBAL
:
9177 * Currently, KVM doesn't mark global entries in the shadow
9178 * page tables, so a non-global flush just degenerates to a
9179 * global flush. If needed, we could optimize this later by
9180 * keeping track of global entries in shadow page tables.
9184 case INVPCID_TYPE_ALL_INCL_GLOBAL
:
9185 kvm_mmu_unload(vcpu
);
9186 return kvm_skip_emulated_instruction(vcpu
);
9189 BUG(); /* We have already checked above that type <= 3 */
9193 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
9195 unsigned long exit_qualification
;
9197 trace_kvm_pml_full(vcpu
->vcpu_id
);
9199 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
9202 * PML buffer FULL happened while executing iret from NMI,
9203 * "blocked by NMI" bit has to be set before next VM entry.
9205 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
9207 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
9208 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9209 GUEST_INTR_STATE_NMI
);
9212 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
9213 * here.., and there's no userspace involvement needed for PML.
9218 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
9220 if (!to_vmx(vcpu
)->req_immediate_exit
)
9221 kvm_lapic_expired_hv_timer(vcpu
);
9225 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
9227 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9228 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9230 /* Check for memory type validity */
9231 switch (address
& VMX_EPTP_MT_MASK
) {
9232 case VMX_EPTP_MT_UC
:
9233 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPTP_UC_BIT
))
9236 case VMX_EPTP_MT_WB
:
9237 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPTP_WB_BIT
))
9244 /* only 4 levels page-walk length are valid */
9245 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
9248 /* Reserved bits should not be set */
9249 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
9252 /* AD, if set, should be supported */
9253 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
9254 if (!(vmx
->nested
.msrs
.ept_caps
& VMX_EPT_AD_BIT
))
9261 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
9262 struct vmcs12
*vmcs12
)
9264 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
9266 bool accessed_dirty
;
9267 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
9269 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
9270 !nested_cpu_has_ept(vmcs12
))
9273 if (index
>= VMFUNC_EPTP_ENTRIES
)
9277 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
9278 &address
, index
* 8, 8))
9281 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
9284 * If the (L2) guest does a vmfunc to the currently
9285 * active ept pointer, we don't have to do anything else
9287 if (vmcs12
->ept_pointer
!= address
) {
9288 if (!valid_ept_address(vcpu
, address
))
9291 kvm_mmu_unload(vcpu
);
9292 mmu
->ept_ad
= accessed_dirty
;
9293 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
9294 vmcs12
->ept_pointer
= address
;
9296 * TODO: Check what's the correct approach in case
9297 * mmu reload fails. Currently, we just let the next
9298 * reload potentially fail
9300 kvm_mmu_reload(vcpu
);
9306 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
9308 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9309 struct vmcs12
*vmcs12
;
9310 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
9313 * VMFUNC is only supported for nested guests, but we always enable the
9314 * secondary control for simplicity; for non-nested mode, fake that we
9315 * didn't by injecting #UD.
9317 if (!is_guest_mode(vcpu
)) {
9318 kvm_queue_exception(vcpu
, UD_VECTOR
);
9322 vmcs12
= get_vmcs12(vcpu
);
9323 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
9328 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
9334 return kvm_skip_emulated_instruction(vcpu
);
9337 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
9338 vmcs_read32(VM_EXIT_INTR_INFO
),
9339 vmcs_readl(EXIT_QUALIFICATION
));
9343 static int handle_encls(struct kvm_vcpu
*vcpu
)
9346 * SGX virtualization is not yet supported. There is no software
9347 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
9348 * to prevent the guest from executing ENCLS.
9350 kvm_queue_exception(vcpu
, UD_VECTOR
);
9355 * The exit handlers return 1 if the exit was handled fully and guest execution
9356 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
9357 * to be done to userspace and return 0.
9359 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
9360 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
9361 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
9362 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
9363 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
9364 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
9365 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
9366 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
9367 [EXIT_REASON_CPUID
] = handle_cpuid
,
9368 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
9369 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
9370 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
9371 [EXIT_REASON_HLT
] = handle_halt
,
9372 [EXIT_REASON_INVD
] = handle_invd
,
9373 [EXIT_REASON_INVLPG
] = handle_invlpg
,
9374 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
9375 [EXIT_REASON_VMCALL
] = handle_vmcall
,
9376 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
9377 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
9378 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
9379 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
9380 [EXIT_REASON_VMREAD
] = handle_vmread
,
9381 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
9382 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
9383 [EXIT_REASON_VMOFF
] = handle_vmoff
,
9384 [EXIT_REASON_VMON
] = handle_vmon
,
9385 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
9386 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
9387 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
9388 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
9389 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
9390 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
9391 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
9392 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
9393 [EXIT_REASON_GDTR_IDTR
] = handle_desc
,
9394 [EXIT_REASON_LDTR_TR
] = handle_desc
,
9395 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
9396 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
9397 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
9398 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
9399 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
9400 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
9401 [EXIT_REASON_INVEPT
] = handle_invept
,
9402 [EXIT_REASON_INVVPID
] = handle_invvpid
,
9403 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
9404 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
9405 [EXIT_REASON_XSAVES
] = handle_xsaves
,
9406 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
9407 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
9408 [EXIT_REASON_INVPCID
] = handle_invpcid
,
9409 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
9410 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
9411 [EXIT_REASON_ENCLS
] = handle_encls
,
9414 static const int kvm_vmx_max_exit_handlers
=
9415 ARRAY_SIZE(kvm_vmx_exit_handlers
);
9417 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
9418 struct vmcs12
*vmcs12
)
9420 unsigned long exit_qualification
;
9421 gpa_t bitmap
, last_bitmap
;
9426 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9427 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
9429 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
9431 port
= exit_qualification
>> 16;
9432 size
= (exit_qualification
& 7) + 1;
9434 last_bitmap
= (gpa_t
)-1;
9439 bitmap
= vmcs12
->io_bitmap_a
;
9440 else if (port
< 0x10000)
9441 bitmap
= vmcs12
->io_bitmap_b
;
9444 bitmap
+= (port
& 0x7fff) / 8;
9446 if (last_bitmap
!= bitmap
)
9447 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
9449 if (b
& (1 << (port
& 7)))
9454 last_bitmap
= bitmap
;
9461 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
9462 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
9463 * disinterest in the current event (read or write a specific MSR) by using an
9464 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
9466 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
9467 struct vmcs12
*vmcs12
, u32 exit_reason
)
9469 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
9472 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9476 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
9477 * for the four combinations of read/write and low/high MSR numbers.
9478 * First we need to figure out which of the four to use:
9480 bitmap
= vmcs12
->msr_bitmap
;
9481 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
9483 if (msr_index
>= 0xc0000000) {
9484 msr_index
-= 0xc0000000;
9488 /* Then read the msr_index'th bit from this bitmap: */
9489 if (msr_index
< 1024*8) {
9491 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
9493 return 1 & (b
>> (msr_index
& 7));
9495 return true; /* let L1 handle the wrong parameter */
9499 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
9500 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
9501 * intercept (via guest_host_mask etc.) the current event.
9503 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
9504 struct vmcs12
*vmcs12
)
9506 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
9507 int cr
= exit_qualification
& 15;
9511 switch ((exit_qualification
>> 4) & 3) {
9512 case 0: /* mov to cr */
9513 reg
= (exit_qualification
>> 8) & 15;
9514 val
= kvm_register_readl(vcpu
, reg
);
9517 if (vmcs12
->cr0_guest_host_mask
&
9518 (val
^ vmcs12
->cr0_read_shadow
))
9522 if ((vmcs12
->cr3_target_count
>= 1 &&
9523 vmcs12
->cr3_target_value0
== val
) ||
9524 (vmcs12
->cr3_target_count
>= 2 &&
9525 vmcs12
->cr3_target_value1
== val
) ||
9526 (vmcs12
->cr3_target_count
>= 3 &&
9527 vmcs12
->cr3_target_value2
== val
) ||
9528 (vmcs12
->cr3_target_count
>= 4 &&
9529 vmcs12
->cr3_target_value3
== val
))
9531 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
9535 if (vmcs12
->cr4_guest_host_mask
&
9536 (vmcs12
->cr4_read_shadow
^ val
))
9540 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
9546 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
9547 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
9550 case 1: /* mov from cr */
9553 if (vmcs12
->cpu_based_vm_exec_control
&
9554 CPU_BASED_CR3_STORE_EXITING
)
9558 if (vmcs12
->cpu_based_vm_exec_control
&
9559 CPU_BASED_CR8_STORE_EXITING
)
9566 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
9567 * cr0. Other attempted changes are ignored, with no exit.
9569 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
9570 if (vmcs12
->cr0_guest_host_mask
& 0xe &
9571 (val
^ vmcs12
->cr0_read_shadow
))
9573 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
9574 !(vmcs12
->cr0_read_shadow
& 0x1) &&
9582 static bool nested_vmx_exit_handled_vmcs_access(struct kvm_vcpu
*vcpu
,
9583 struct vmcs12
*vmcs12
, gpa_t bitmap
)
9585 u32 vmx_instruction_info
;
9586 unsigned long field
;
9589 if (!nested_cpu_has_shadow_vmcs(vmcs12
))
9592 /* Decode instruction info and find the field to access */
9593 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9594 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
9596 /* Out-of-range fields always cause a VM exit from L2 to L1 */
9600 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ field
/8, &b
, 1))
9603 return 1 & (b
>> (field
& 7));
9607 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
9608 * should handle it ourselves in L0 (and then continue L2). Only call this
9609 * when in is_guest_mode (L2).
9611 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
9613 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9614 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9615 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9617 if (vmx
->nested
.nested_run_pending
)
9620 if (unlikely(vmx
->fail
)) {
9621 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
9622 vmcs_read32(VM_INSTRUCTION_ERROR
));
9627 * The host physical addresses of some pages of guest memory
9628 * are loaded into the vmcs02 (e.g. vmcs12's Virtual APIC
9629 * Page). The CPU may write to these pages via their host
9630 * physical address while L2 is running, bypassing any
9631 * address-translation-based dirty tracking (e.g. EPT write
9634 * Mark them dirty on every exit from L2 to prevent them from
9635 * getting out of sync with dirty tracking.
9637 nested_mark_vmcs12_pages_dirty(vcpu
);
9639 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
9640 vmcs_readl(EXIT_QUALIFICATION
),
9641 vmx
->idt_vectoring_info
,
9643 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
9646 switch (exit_reason
) {
9647 case EXIT_REASON_EXCEPTION_NMI
:
9648 if (is_nmi(intr_info
))
9650 else if (is_page_fault(intr_info
))
9651 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
9652 else if (is_no_device(intr_info
) &&
9653 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
9655 else if (is_debug(intr_info
) &&
9657 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
9659 else if (is_breakpoint(intr_info
) &&
9660 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
9662 return vmcs12
->exception_bitmap
&
9663 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
9664 case EXIT_REASON_EXTERNAL_INTERRUPT
:
9666 case EXIT_REASON_TRIPLE_FAULT
:
9668 case EXIT_REASON_PENDING_INTERRUPT
:
9669 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
9670 case EXIT_REASON_NMI_WINDOW
:
9671 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
9672 case EXIT_REASON_TASK_SWITCH
:
9674 case EXIT_REASON_CPUID
:
9676 case EXIT_REASON_HLT
:
9677 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
9678 case EXIT_REASON_INVD
:
9680 case EXIT_REASON_INVLPG
:
9681 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
9682 case EXIT_REASON_RDPMC
:
9683 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
9684 case EXIT_REASON_RDRAND
:
9685 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
9686 case EXIT_REASON_RDSEED
:
9687 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
9688 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
9689 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
9690 case EXIT_REASON_VMREAD
:
9691 return nested_vmx_exit_handled_vmcs_access(vcpu
, vmcs12
,
9692 vmcs12
->vmread_bitmap
);
9693 case EXIT_REASON_VMWRITE
:
9694 return nested_vmx_exit_handled_vmcs_access(vcpu
, vmcs12
,
9695 vmcs12
->vmwrite_bitmap
);
9696 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
9697 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
9698 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMRESUME
:
9699 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
9700 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
9702 * VMX instructions trap unconditionally. This allows L1 to
9703 * emulate them for its L2 guest, i.e., allows 3-level nesting!
9706 case EXIT_REASON_CR_ACCESS
:
9707 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
9708 case EXIT_REASON_DR_ACCESS
:
9709 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
9710 case EXIT_REASON_IO_INSTRUCTION
:
9711 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
9712 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
9713 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
9714 case EXIT_REASON_MSR_READ
:
9715 case EXIT_REASON_MSR_WRITE
:
9716 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
9717 case EXIT_REASON_INVALID_STATE
:
9719 case EXIT_REASON_MWAIT_INSTRUCTION
:
9720 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
9721 case EXIT_REASON_MONITOR_TRAP_FLAG
:
9722 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
9723 case EXIT_REASON_MONITOR_INSTRUCTION
:
9724 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
9725 case EXIT_REASON_PAUSE_INSTRUCTION
:
9726 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
9727 nested_cpu_has2(vmcs12
,
9728 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
9729 case EXIT_REASON_MCE_DURING_VMENTRY
:
9731 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
9732 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
9733 case EXIT_REASON_APIC_ACCESS
:
9734 case EXIT_REASON_APIC_WRITE
:
9735 case EXIT_REASON_EOI_INDUCED
:
9737 * The controls for "virtualize APIC accesses," "APIC-
9738 * register virtualization," and "virtual-interrupt
9739 * delivery" only come from vmcs12.
9742 case EXIT_REASON_EPT_VIOLATION
:
9744 * L0 always deals with the EPT violation. If nested EPT is
9745 * used, and the nested mmu code discovers that the address is
9746 * missing in the guest EPT table (EPT12), the EPT violation
9747 * will be injected with nested_ept_inject_page_fault()
9750 case EXIT_REASON_EPT_MISCONFIG
:
9752 * L2 never uses directly L1's EPT, but rather L0's own EPT
9753 * table (shadow on EPT) or a merged EPT table that L0 built
9754 * (EPT on EPT). So any problems with the structure of the
9755 * table is L0's fault.
9758 case EXIT_REASON_INVPCID
:
9760 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
9761 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
9762 case EXIT_REASON_WBINVD
:
9763 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
9764 case EXIT_REASON_XSETBV
:
9766 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
9768 * This should never happen, since it is not possible to
9769 * set XSS to a non-zero value---neither in L1 nor in L2.
9770 * If if it were, XSS would have to be checked against
9771 * the XSS exit bitmap in vmcs12.
9773 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
9774 case EXIT_REASON_PREEMPTION_TIMER
:
9776 case EXIT_REASON_PML_FULL
:
9777 /* We emulate PML support to L1. */
9779 case EXIT_REASON_VMFUNC
:
9780 /* VM functions are emulated through L2->L0 vmexits. */
9782 case EXIT_REASON_ENCLS
:
9783 /* SGX is never exposed to L1 */
9790 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
9792 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9795 * At this point, the exit interruption info in exit_intr_info
9796 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
9797 * we need to query the in-kernel LAPIC.
9799 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
9800 if ((exit_intr_info
&
9801 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
9802 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
9803 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9804 vmcs12
->vm_exit_intr_error_code
=
9805 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
9808 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
9809 vmcs_readl(EXIT_QUALIFICATION
));
9813 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
9815 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
9816 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
9819 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
9822 __free_page(vmx
->pml_pg
);
9827 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
9829 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9833 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
9835 /* Do nothing if PML buffer is empty */
9836 if (pml_idx
== (PML_ENTITY_NUM
- 1))
9839 /* PML index always points to next available PML buffer entity */
9840 if (pml_idx
>= PML_ENTITY_NUM
)
9845 pml_buf
= page_address(vmx
->pml_pg
);
9846 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
9849 gpa
= pml_buf
[pml_idx
];
9850 WARN_ON(gpa
& (PAGE_SIZE
- 1));
9851 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
9854 /* reset PML index */
9855 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
9859 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
9860 * Called before reporting dirty_bitmap to userspace.
9862 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
9865 struct kvm_vcpu
*vcpu
;
9867 * We only need to kick vcpu out of guest mode here, as PML buffer
9868 * is flushed at beginning of all VMEXITs, and it's obvious that only
9869 * vcpus running in guest are possible to have unflushed GPAs in PML
9872 kvm_for_each_vcpu(i
, vcpu
, kvm
)
9873 kvm_vcpu_kick(vcpu
);
9876 static void vmx_dump_sel(char *name
, uint32_t sel
)
9878 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
9879 name
, vmcs_read16(sel
),
9880 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
9881 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
9882 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
9885 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
9887 pr_err("%s limit=0x%08x, base=0x%016lx\n",
9888 name
, vmcs_read32(limit
),
9889 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
9892 static void dump_vmcs(void)
9894 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
9895 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
9896 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
9897 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
9898 u32 secondary_exec_control
= 0;
9899 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
9900 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
9903 if (cpu_has_secondary_exec_ctrls())
9904 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9906 pr_err("*** Guest State ***\n");
9907 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9908 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
9909 vmcs_readl(CR0_GUEST_HOST_MASK
));
9910 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
9911 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
9912 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
9913 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
9914 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
9916 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
9917 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
9918 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
9919 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
9921 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
9922 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
9923 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
9924 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
9925 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9926 vmcs_readl(GUEST_SYSENTER_ESP
),
9927 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
9928 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
9929 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
9930 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
9931 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
9932 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
9933 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
9934 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
9935 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
9936 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
9937 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
9938 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
9939 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
9940 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9941 efer
, vmcs_read64(GUEST_IA32_PAT
));
9942 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
9943 vmcs_read64(GUEST_IA32_DEBUGCTL
),
9944 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
9945 if (cpu_has_load_perf_global_ctrl
&&
9946 vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
9947 pr_err("PerfGlobCtl = 0x%016llx\n",
9948 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
9949 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
9950 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
9951 pr_err("Interruptibility = %08x ActivityState = %08x\n",
9952 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
9953 vmcs_read32(GUEST_ACTIVITY_STATE
));
9954 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
9955 pr_err("InterruptStatus = %04x\n",
9956 vmcs_read16(GUEST_INTR_STATUS
));
9958 pr_err("*** Host State ***\n");
9959 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
9960 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
9961 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
9962 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
9963 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
9964 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
9965 vmcs_read16(HOST_TR_SELECTOR
));
9966 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
9967 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
9968 vmcs_readl(HOST_TR_BASE
));
9969 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
9970 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
9971 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
9972 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
9973 vmcs_readl(HOST_CR4
));
9974 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
9975 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
9976 vmcs_read32(HOST_IA32_SYSENTER_CS
),
9977 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
9978 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
9979 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
9980 vmcs_read64(HOST_IA32_EFER
),
9981 vmcs_read64(HOST_IA32_PAT
));
9982 if (cpu_has_load_perf_global_ctrl
&&
9983 vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
9984 pr_err("PerfGlobCtl = 0x%016llx\n",
9985 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
9987 pr_err("*** Control State ***\n");
9988 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
9989 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
9990 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
9991 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
9992 vmcs_read32(EXCEPTION_BITMAP
),
9993 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
9994 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
9995 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
9996 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9997 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
9998 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
9999 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
10000 vmcs_read32(VM_EXIT_INTR_INFO
),
10001 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
10002 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
10003 pr_err(" reason=%08x qualification=%016lx\n",
10004 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
10005 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
10006 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
10007 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
10008 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
10009 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
10010 pr_err("TSC Multiplier = 0x%016llx\n",
10011 vmcs_read64(TSC_MULTIPLIER
));
10012 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
10013 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
10014 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
10015 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
10016 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
10017 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
10018 n
= vmcs_read32(CR3_TARGET_COUNT
);
10019 for (i
= 0; i
+ 1 < n
; i
+= 4)
10020 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
10021 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
10022 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
10024 pr_err("CR3 target%u=%016lx\n",
10025 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
10026 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
10027 pr_err("PLE Gap=%08x Window=%08x\n",
10028 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
10029 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
10030 pr_err("Virtual processor ID = 0x%04x\n",
10031 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
10035 * The guest has exited. See if we can fix it or if we need userspace
10038 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
10040 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10041 u32 exit_reason
= vmx
->exit_reason
;
10042 u32 vectoring_info
= vmx
->idt_vectoring_info
;
10044 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
10047 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
10048 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
10049 * querying dirty_bitmap, we only need to kick all vcpus out of guest
10050 * mode as if vcpus is in root mode, the PML buffer must has been
10054 vmx_flush_pml_buffer(vcpu
);
10056 /* If guest state is invalid, start emulating */
10057 if (vmx
->emulation_required
)
10058 return handle_invalid_guest_state(vcpu
);
10060 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
10061 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
10063 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
10065 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
10066 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
10071 if (unlikely(vmx
->fail
)) {
10072 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
10073 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
10074 = vmcs_read32(VM_INSTRUCTION_ERROR
);
10080 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
10081 * delivery event since it indicates guest is accessing MMIO.
10082 * The vm-exit can be triggered again after return to guest that
10083 * will cause infinite loop.
10085 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
10086 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
10087 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
10088 exit_reason
!= EXIT_REASON_PML_FULL
&&
10089 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
10090 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
10091 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
10092 vcpu
->run
->internal
.ndata
= 3;
10093 vcpu
->run
->internal
.data
[0] = vectoring_info
;
10094 vcpu
->run
->internal
.data
[1] = exit_reason
;
10095 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
10096 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
10097 vcpu
->run
->internal
.ndata
++;
10098 vcpu
->run
->internal
.data
[3] =
10099 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
10104 if (unlikely(!enable_vnmi
&&
10105 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
10106 if (vmx_interrupt_allowed(vcpu
)) {
10107 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
10108 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
10109 vcpu
->arch
.nmi_pending
) {
10111 * This CPU don't support us in finding the end of an
10112 * NMI-blocked window if the guest runs with IRQs
10113 * disabled. So we pull the trigger after 1 s of
10114 * futile waiting, but inform the user about this.
10116 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
10117 "state on VCPU %d after 1 s timeout\n",
10118 __func__
, vcpu
->vcpu_id
);
10119 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
10123 if (exit_reason
< kvm_vmx_max_exit_handlers
10124 && kvm_vmx_exit_handlers
[exit_reason
])
10125 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
10127 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
10129 kvm_queue_exception(vcpu
, UD_VECTOR
);
10135 * Software based L1D cache flush which is used when microcode providing
10136 * the cache control MSR is not loaded.
10138 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
10139 * flush it is required to read in 64 KiB because the replacement algorithm
10140 * is not exactly LRU. This could be sized at runtime via topology
10141 * information but as all relevant affected CPUs have 32KiB L1D cache size
10142 * there is no point in doing so.
10144 static void vmx_l1d_flush(struct kvm_vcpu
*vcpu
)
10146 int size
= PAGE_SIZE
<< L1D_CACHE_ORDER
;
10149 * This code is only executed when the the flush mode is 'cond' or
10152 if (static_branch_likely(&vmx_l1d_flush_cond
)) {
10156 * Clear the per-vcpu flush bit, it gets set again
10157 * either from vcpu_run() or from one of the unsafe
10160 flush_l1d
= vcpu
->arch
.l1tf_flush_l1d
;
10161 vcpu
->arch
.l1tf_flush_l1d
= false;
10164 * Clear the per-cpu flush bit, it gets set again from
10165 * the interrupt handlers.
10167 flush_l1d
|= kvm_get_cpu_l1tf_flush_l1d();
10168 kvm_clear_cpu_l1tf_flush_l1d();
10174 vcpu
->stat
.l1d_flush
++;
10176 if (static_cpu_has(X86_FEATURE_FLUSH_L1D
)) {
10177 wrmsrl(MSR_IA32_FLUSH_CMD
, L1D_FLUSH
);
10182 /* First ensure the pages are in the TLB */
10183 "xorl %%eax, %%eax\n"
10184 ".Lpopulate_tlb:\n\t"
10185 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
10186 "addl $4096, %%eax\n\t"
10187 "cmpl %%eax, %[size]\n\t"
10188 "jne .Lpopulate_tlb\n\t"
10189 "xorl %%eax, %%eax\n\t"
10191 /* Now fill the cache */
10192 "xorl %%eax, %%eax\n"
10194 "movzbl (%[flush_pages], %%" _ASM_AX
"), %%ecx\n\t"
10195 "addl $64, %%eax\n\t"
10196 "cmpl %%eax, %[size]\n\t"
10197 "jne .Lfill_cache\n\t"
10199 :: [flush_pages
] "r" (vmx_l1d_flush_pages
),
10201 : "eax", "ebx", "ecx", "edx");
10204 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
10206 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10208 if (is_guest_mode(vcpu
) &&
10209 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10212 if (irr
== -1 || tpr
< irr
) {
10213 vmcs_write32(TPR_THRESHOLD
, 0);
10217 vmcs_write32(TPR_THRESHOLD
, irr
);
10220 static void vmx_set_virtual_apic_mode(struct kvm_vcpu
*vcpu
)
10222 u32 sec_exec_control
;
10224 if (!lapic_in_kernel(vcpu
))
10227 /* Postpone execution until vmcs01 is the current VMCS. */
10228 if (is_guest_mode(vcpu
)) {
10229 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_apic_mode
= true;
10233 if (!cpu_need_tpr_shadow(vcpu
))
10236 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
10237 sec_exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10238 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
10240 switch (kvm_get_apic_mode(vcpu
)) {
10241 case LAPIC_MODE_INVALID
:
10242 WARN_ONCE(true, "Invalid local APIC state");
10243 case LAPIC_MODE_DISABLED
:
10245 case LAPIC_MODE_XAPIC
:
10246 if (flexpriority_enabled
) {
10247 sec_exec_control
|=
10248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
10249 vmx_flush_tlb(vcpu
, true);
10252 case LAPIC_MODE_X2APIC
:
10253 if (cpu_has_vmx_virtualize_x2apic_mode())
10254 sec_exec_control
|=
10255 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
10258 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
10260 vmx_update_msr_bitmap(vcpu
);
10263 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
10265 if (!is_guest_mode(vcpu
)) {
10266 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
10267 vmx_flush_tlb(vcpu
, true);
10271 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
10279 status
= vmcs_read16(GUEST_INTR_STATUS
);
10281 if (max_isr
!= old
) {
10283 status
|= max_isr
<< 8;
10284 vmcs_write16(GUEST_INTR_STATUS
, status
);
10288 static void vmx_set_rvi(int vector
)
10296 status
= vmcs_read16(GUEST_INTR_STATUS
);
10297 old
= (u8
)status
& 0xff;
10298 if ((u8
)vector
!= old
) {
10300 status
|= (u8
)vector
;
10301 vmcs_write16(GUEST_INTR_STATUS
, status
);
10305 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
10308 * When running L2, updating RVI is only relevant when
10309 * vmcs12 virtual-interrupt-delivery enabled.
10310 * However, it can be enabled only when L1 also
10311 * intercepts external-interrupts and in that case
10312 * we should not update vmcs02 RVI but instead intercept
10313 * interrupt. Therefore, do nothing when running L2.
10315 if (!is_guest_mode(vcpu
))
10316 vmx_set_rvi(max_irr
);
10319 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
10321 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10323 bool max_irr_updated
;
10325 WARN_ON(!vcpu
->arch
.apicv_active
);
10326 if (pi_test_on(&vmx
->pi_desc
)) {
10327 pi_clear_on(&vmx
->pi_desc
);
10329 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
10330 * But on x86 this is just a compiler barrier anyway.
10332 smp_mb__after_atomic();
10334 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
, &max_irr
);
10337 * If we are running L2 and L1 has a new pending interrupt
10338 * which can be injected, we should re-evaluate
10339 * what should be done with this new L1 interrupt.
10340 * If L1 intercepts external-interrupts, we should
10341 * exit from L2 to L1. Otherwise, interrupt should be
10342 * delivered directly to L2.
10344 if (is_guest_mode(vcpu
) && max_irr_updated
) {
10345 if (nested_exit_on_intr(vcpu
))
10346 kvm_vcpu_exiting_guest_mode(vcpu
);
10348 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
10351 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
10353 vmx_hwapic_irr_update(vcpu
, max_irr
);
10357 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
10359 if (!kvm_vcpu_apicv_active(vcpu
))
10362 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
10363 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
10364 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
10365 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
10368 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
10370 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10372 pi_clear_on(&vmx
->pi_desc
);
10373 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
10376 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
10378 u32 exit_intr_info
= 0;
10379 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
10381 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
10382 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
10385 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
10386 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
10387 vmx
->exit_intr_info
= exit_intr_info
;
10389 /* if exit due to PF check for async PF */
10390 if (is_page_fault(exit_intr_info
))
10391 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
10393 /* Handle machine checks before interrupts are enabled */
10394 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
10395 is_machine_check(exit_intr_info
))
10396 kvm_machine_check();
10398 /* We need to handle NMIs before interrupts are enabled */
10399 if (is_nmi(exit_intr_info
)) {
10400 kvm_before_interrupt(&vmx
->vcpu
);
10402 kvm_after_interrupt(&vmx
->vcpu
);
10406 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
10408 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
10410 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
10411 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
10412 unsigned int vector
;
10413 unsigned long entry
;
10415 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10416 #ifdef CONFIG_X86_64
10420 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
10421 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
10422 entry
= gate_offset(desc
);
10424 #ifdef CONFIG_X86_64
10425 "mov %%" _ASM_SP
", %[sp]\n\t"
10426 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
10431 __ASM_SIZE(push
) " $%c[cs]\n\t"
10434 #ifdef CONFIG_X86_64
10437 ASM_CALL_CONSTRAINT
10439 THUNK_TARGET(entry
),
10440 [ss
]"i"(__KERNEL_DS
),
10441 [cs
]"i"(__KERNEL_CS
)
10445 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
10447 static bool vmx_has_emulated_msr(int index
)
10450 case MSR_IA32_SMBASE
:
10452 * We cannot do SMM unless we can run the guest in big
10455 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
10456 case MSR_AMD64_VIRT_SPEC_CTRL
:
10457 /* This is AMD only. */
10464 static bool vmx_mpx_supported(void)
10466 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
10467 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
10470 static bool vmx_xsaves_supported(void)
10472 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
10473 SECONDARY_EXEC_XSAVES
;
10476 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
10478 u32 exit_intr_info
;
10481 bool idtv_info_valid
;
10483 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
10486 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
10489 * Can't use vmx->exit_intr_info since we're not sure what
10490 * the exit reason is.
10492 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
10493 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
10494 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
10496 * SDM 3: 27.7.1.2 (September 2008)
10497 * Re-set bit "block by NMI" before VM entry if vmexit caused by
10498 * a guest IRET fault.
10499 * SDM 3: 23.2.2 (September 2008)
10500 * Bit 12 is undefined in any of the following cases:
10501 * If the VM exit sets the valid bit in the IDT-vectoring
10502 * information field.
10503 * If the VM exit is due to a double fault.
10505 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
10506 vector
!= DF_VECTOR
&& !idtv_info_valid
)
10507 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
10508 GUEST_INTR_STATE_NMI
);
10510 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10511 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
10512 & GUEST_INTR_STATE_NMI
);
10513 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
10514 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
10515 ktime_to_ns(ktime_sub(ktime_get(),
10516 vmx
->loaded_vmcs
->entry_time
));
10519 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
10520 u32 idt_vectoring_info
,
10521 int instr_len_field
,
10522 int error_code_field
)
10526 bool idtv_info_valid
;
10528 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
10530 vcpu
->arch
.nmi_injected
= false;
10531 kvm_clear_exception_queue(vcpu
);
10532 kvm_clear_interrupt_queue(vcpu
);
10534 if (!idtv_info_valid
)
10537 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
10539 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
10540 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
10543 case INTR_TYPE_NMI_INTR
:
10544 vcpu
->arch
.nmi_injected
= true;
10546 * SDM 3: 27.7.1.2 (September 2008)
10547 * Clear bit "block by NMI" before VM entry if a NMI
10548 * delivery faulted.
10550 vmx_set_nmi_mask(vcpu
, false);
10552 case INTR_TYPE_SOFT_EXCEPTION
:
10553 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
10555 case INTR_TYPE_HARD_EXCEPTION
:
10556 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
10557 u32 err
= vmcs_read32(error_code_field
);
10558 kvm_requeue_exception_e(vcpu
, vector
, err
);
10560 kvm_requeue_exception(vcpu
, vector
);
10562 case INTR_TYPE_SOFT_INTR
:
10563 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
10565 case INTR_TYPE_EXT_INTR
:
10566 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
10573 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
10575 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
10576 VM_EXIT_INSTRUCTION_LEN
,
10577 IDT_VECTORING_ERROR_CODE
);
10580 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
10582 __vmx_complete_interrupts(vcpu
,
10583 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
10584 VM_ENTRY_INSTRUCTION_LEN
,
10585 VM_ENTRY_EXCEPTION_ERROR_CODE
);
10587 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10590 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
10593 struct perf_guest_switch_msr
*msrs
;
10595 msrs
= perf_guest_get_msrs(&nr_msrs
);
10600 for (i
= 0; i
< nr_msrs
; i
++)
10601 if (msrs
[i
].host
== msrs
[i
].guest
)
10602 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
10604 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
10605 msrs
[i
].host
, false);
10608 static void vmx_arm_hv_timer(struct vcpu_vmx
*vmx
, u32 val
)
10610 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, val
);
10611 if (!vmx
->loaded_vmcs
->hv_timer_armed
)
10612 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10613 PIN_BASED_VMX_PREEMPTION_TIMER
);
10614 vmx
->loaded_vmcs
->hv_timer_armed
= true;
10617 static void vmx_update_hv_timer(struct kvm_vcpu
*vcpu
)
10619 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10623 if (vmx
->req_immediate_exit
) {
10624 vmx_arm_hv_timer(vmx
, 0);
10628 if (vmx
->hv_deadline_tsc
!= -1) {
10630 if (vmx
->hv_deadline_tsc
> tscl
)
10631 /* set_hv_timer ensures the delta fits in 32-bits */
10632 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
10633 cpu_preemption_timer_multi
);
10637 vmx_arm_hv_timer(vmx
, delta_tsc
);
10641 if (vmx
->loaded_vmcs
->hv_timer_armed
)
10642 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10643 PIN_BASED_VMX_PREEMPTION_TIMER
);
10644 vmx
->loaded_vmcs
->hv_timer_armed
= false;
10647 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
10649 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10650 unsigned long cr3
, cr4
, evmcs_rsp
;
10652 /* Record the guest's net vcpu time for enforced NMI injections. */
10653 if (unlikely(!enable_vnmi
&&
10654 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
10655 vmx
->loaded_vmcs
->entry_time
= ktime_get();
10657 /* Don't enter VMX if guest state is invalid, let the exit handler
10658 start emulation until we arrive back to a valid state */
10659 if (vmx
->emulation_required
)
10662 if (vmx
->ple_window_dirty
) {
10663 vmx
->ple_window_dirty
= false;
10664 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
10667 if (vmx
->nested
.sync_shadow_vmcs
) {
10668 copy_vmcs12_to_shadow(vmx
);
10669 vmx
->nested
.sync_shadow_vmcs
= false;
10672 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
10673 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
10674 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
10675 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
10677 cr3
= __get_current_cr3_fast();
10678 if (unlikely(cr3
!= vmx
->loaded_vmcs
->host_state
.cr3
)) {
10679 vmcs_writel(HOST_CR3
, cr3
);
10680 vmx
->loaded_vmcs
->host_state
.cr3
= cr3
;
10683 cr4
= cr4_read_shadow();
10684 if (unlikely(cr4
!= vmx
->loaded_vmcs
->host_state
.cr4
)) {
10685 vmcs_writel(HOST_CR4
, cr4
);
10686 vmx
->loaded_vmcs
->host_state
.cr4
= cr4
;
10689 /* When single-stepping over STI and MOV SS, we must clear the
10690 * corresponding interruptibility bits in the guest state. Otherwise
10691 * vmentry fails as it then expects bit 14 (BS) in pending debug
10692 * exceptions being set, but that's not correct for the guest debugging
10694 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
10695 vmx_set_interrupt_shadow(vcpu
, 0);
10697 if (static_cpu_has(X86_FEATURE_PKU
) &&
10698 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
10699 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
10700 __write_pkru(vcpu
->arch
.pkru
);
10702 atomic_switch_perf_msrs(vmx
);
10704 vmx_update_hv_timer(vcpu
);
10707 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
10708 * it's non-zero. Since vmentry is serialising on affected CPUs, there
10709 * is no need to worry about the conditional branch over the wrmsr
10710 * being speculatively taken.
10712 x86_spec_ctrl_set_guest(vmx
->spec_ctrl
, 0);
10714 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
10716 evmcs_rsp
= static_branch_unlikely(&enable_evmcs
) ?
10717 (unsigned long)¤t_evmcs
->host_rsp
: 0;
10719 if (static_branch_unlikely(&vmx_l1d_should_flush
))
10720 vmx_l1d_flush(vcpu
);
10723 /* Store host registers */
10724 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
10725 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
10726 "push %%" _ASM_CX
" \n\t"
10727 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
10729 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
10730 /* Avoid VMWRITE when Enlightened VMCS is in use */
10731 "test %%" _ASM_SI
", %%" _ASM_SI
" \n\t"
10733 "mov %%" _ASM_SP
", (%%" _ASM_SI
") \n\t"
10736 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
10738 /* Reload cr2 if changed */
10739 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
10740 "mov %%cr2, %%" _ASM_DX
" \n\t"
10741 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
10743 "mov %%" _ASM_AX
", %%cr2 \n\t"
10745 /* Check if vmlaunch of vmresume is needed */
10746 "cmpl $0, %c[launched](%0) \n\t"
10747 /* Load guest registers. Don't clobber flags. */
10748 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
10749 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
10750 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
10751 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
10752 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
10753 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
10754 #ifdef CONFIG_X86_64
10755 "mov %c[r8](%0), %%r8 \n\t"
10756 "mov %c[r9](%0), %%r9 \n\t"
10757 "mov %c[r10](%0), %%r10 \n\t"
10758 "mov %c[r11](%0), %%r11 \n\t"
10759 "mov %c[r12](%0), %%r12 \n\t"
10760 "mov %c[r13](%0), %%r13 \n\t"
10761 "mov %c[r14](%0), %%r14 \n\t"
10762 "mov %c[r15](%0), %%r15 \n\t"
10764 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
10766 /* Enter guest mode */
10768 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
10770 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
10772 /* Save guest registers, load host registers, keep flags */
10773 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
10775 "setbe %c[fail](%0)\n\t"
10776 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
10777 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
10778 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
10779 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
10780 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
10781 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
10782 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
10783 #ifdef CONFIG_X86_64
10784 "mov %%r8, %c[r8](%0) \n\t"
10785 "mov %%r9, %c[r9](%0) \n\t"
10786 "mov %%r10, %c[r10](%0) \n\t"
10787 "mov %%r11, %c[r11](%0) \n\t"
10788 "mov %%r12, %c[r12](%0) \n\t"
10789 "mov %%r13, %c[r13](%0) \n\t"
10790 "mov %%r14, %c[r14](%0) \n\t"
10791 "mov %%r15, %c[r15](%0) \n\t"
10792 "xor %%r8d, %%r8d \n\t"
10793 "xor %%r9d, %%r9d \n\t"
10794 "xor %%r10d, %%r10d \n\t"
10795 "xor %%r11d, %%r11d \n\t"
10796 "xor %%r12d, %%r12d \n\t"
10797 "xor %%r13d, %%r13d \n\t"
10798 "xor %%r14d, %%r14d \n\t"
10799 "xor %%r15d, %%r15d \n\t"
10801 "mov %%cr2, %%" _ASM_AX
" \n\t"
10802 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
10804 "xor %%eax, %%eax \n\t"
10805 "xor %%ebx, %%ebx \n\t"
10806 "xor %%esi, %%esi \n\t"
10807 "xor %%edi, %%edi \n\t"
10808 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
10809 ".pushsection .rodata \n\t"
10810 ".global vmx_return \n\t"
10811 "vmx_return: " _ASM_PTR
" 2b \n\t"
10813 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
), "S"(evmcs_rsp
),
10814 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
10815 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
10816 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
10817 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
10818 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
10819 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
10820 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
10821 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
10822 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
10823 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
10824 #ifdef CONFIG_X86_64
10825 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
10826 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
10827 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
10828 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
10829 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
10830 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
10831 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
10832 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
10834 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
10835 [wordsize
]"i"(sizeof(ulong
))
10837 #ifdef CONFIG_X86_64
10838 , "rax", "rbx", "rdi"
10839 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
10841 , "eax", "ebx", "edi"
10846 * We do not use IBRS in the kernel. If this vCPU has used the
10847 * SPEC_CTRL MSR it may have left it on; save the value and
10848 * turn it off. This is much more efficient than blindly adding
10849 * it to the atomic save/restore list. Especially as the former
10850 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
10852 * For non-nested case:
10853 * If the L01 MSR bitmap does not intercept the MSR, then we need to
10857 * If the L02 MSR bitmap does not intercept the MSR, then we need to
10860 if (unlikely(!msr_write_intercepted(vcpu
, MSR_IA32_SPEC_CTRL
)))
10861 vmx
->spec_ctrl
= native_read_msr(MSR_IA32_SPEC_CTRL
);
10863 x86_spec_ctrl_restore_host(vmx
->spec_ctrl
, 0);
10865 /* Eliminate branch target predictions from guest mode */
10868 /* All fields are clean at this point */
10869 if (static_branch_unlikely(&enable_evmcs
))
10870 current_evmcs
->hv_clean_fields
|=
10871 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL
;
10873 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
10874 if (vmx
->host_debugctlmsr
)
10875 update_debugctlmsr(vmx
->host_debugctlmsr
);
10877 #ifndef CONFIG_X86_64
10879 * The sysexit path does not restore ds/es, so we must set them to
10880 * a reasonable value ourselves.
10882 * We can't defer this to vmx_prepare_switch_to_host() since that
10883 * function may be executed in interrupt context, which saves and
10884 * restore segments around it, nullifying its effect.
10886 loadsegment(ds
, __USER_DS
);
10887 loadsegment(es
, __USER_DS
);
10890 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
10891 | (1 << VCPU_EXREG_RFLAGS
)
10892 | (1 << VCPU_EXREG_PDPTR
)
10893 | (1 << VCPU_EXREG_SEGMENTS
)
10894 | (1 << VCPU_EXREG_CR3
));
10895 vcpu
->arch
.regs_dirty
= 0;
10898 * eager fpu is enabled if PKEY is supported and CR4 is switched
10899 * back on host, so it is safe to read guest PKRU from current
10902 if (static_cpu_has(X86_FEATURE_PKU
) &&
10903 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
10904 vcpu
->arch
.pkru
= __read_pkru();
10905 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
10906 __write_pkru(vmx
->host_pkru
);
10909 vmx
->nested
.nested_run_pending
= 0;
10910 vmx
->idt_vectoring_info
= 0;
10912 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
10913 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
10916 vmx
->loaded_vmcs
->launched
= 1;
10917 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
10919 vmx_complete_atomic_exit(vmx
);
10920 vmx_recover_nmi_blocking(vmx
);
10921 vmx_complete_interrupts(vmx
);
10923 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
10925 static struct kvm
*vmx_vm_alloc(void)
10927 struct kvm_vmx
*kvm_vmx
= vzalloc(sizeof(struct kvm_vmx
));
10928 return &kvm_vmx
->kvm
;
10931 static void vmx_vm_free(struct kvm
*kvm
)
10933 vfree(to_kvm_vmx(kvm
));
10936 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
10938 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10941 if (vmx
->loaded_vmcs
== vmcs
)
10945 vmx_vcpu_put(vcpu
);
10946 vmx
->loaded_vmcs
= vmcs
;
10947 vmx_vcpu_load(vcpu
, cpu
);
10952 * Ensure that the current vmcs of the logical processor is the
10953 * vmcs01 of the vcpu before calling free_nested().
10955 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
10957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10960 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10965 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
10967 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10970 vmx_destroy_pml_buffer(vmx
);
10971 free_vpid(vmx
->vpid
);
10972 leave_guest_mode(vcpu
);
10973 vmx_free_vcpu_nested(vcpu
);
10974 free_loaded_vmcs(vmx
->loaded_vmcs
);
10975 kfree(vmx
->guest_msrs
);
10976 kvm_vcpu_uninit(vcpu
);
10977 kmem_cache_free(kvm_vcpu_cache
, vmx
);
10980 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
10983 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
10984 unsigned long *msr_bitmap
;
10988 return ERR_PTR(-ENOMEM
);
10990 vmx
->vpid
= allocate_vpid();
10992 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
10999 * If PML is turned on, failure on enabling PML just results in failure
11000 * of creating the vcpu, therefore we can simplify PML logic (by
11001 * avoiding dealing with cases, such as enabling PML partially on vcpus
11002 * for the guest, etc.
11005 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
11010 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
11011 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
11014 if (!vmx
->guest_msrs
)
11017 err
= alloc_loaded_vmcs(&vmx
->vmcs01
);
11021 msr_bitmap
= vmx
->vmcs01
.msr_bitmap
;
11022 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_FS_BASE
, MSR_TYPE_RW
);
11023 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_GS_BASE
, MSR_TYPE_RW
);
11024 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_KERNEL_GS_BASE
, MSR_TYPE_RW
);
11025 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_CS
, MSR_TYPE_RW
);
11026 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_ESP
, MSR_TYPE_RW
);
11027 vmx_disable_intercept_for_msr(msr_bitmap
, MSR_IA32_SYSENTER_EIP
, MSR_TYPE_RW
);
11028 vmx
->msr_bitmap_mode
= 0;
11030 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
11032 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
11033 vmx
->vcpu
.cpu
= cpu
;
11034 vmx_vcpu_setup(vmx
);
11035 vmx_vcpu_put(&vmx
->vcpu
);
11037 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
11038 err
= alloc_apic_access_page(kvm
);
11043 if (enable_ept
&& !enable_unrestricted_guest
) {
11044 err
= init_rmode_identity_map(kvm
);
11050 nested_vmx_setup_ctls_msrs(&vmx
->nested
.msrs
,
11051 kvm_vcpu_apicv_active(&vmx
->vcpu
));
11053 vmx
->nested
.posted_intr_nv
= -1;
11054 vmx
->nested
.current_vmptr
= -1ull;
11056 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
11059 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
11060 * or POSTED_INTR_WAKEUP_VECTOR.
11062 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
11063 vmx
->pi_desc
.sn
= 1;
11068 free_loaded_vmcs(vmx
->loaded_vmcs
);
11070 kfree(vmx
->guest_msrs
);
11072 vmx_destroy_pml_buffer(vmx
);
11074 kvm_vcpu_uninit(&vmx
->vcpu
);
11076 free_vpid(vmx
->vpid
);
11077 kmem_cache_free(kvm_vcpu_cache
, vmx
);
11078 return ERR_PTR(err
);
11081 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11082 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
11084 static int vmx_vm_init(struct kvm
*kvm
)
11086 spin_lock_init(&to_kvm_vmx(kvm
)->ept_pointer_lock
);
11089 kvm
->arch
.pause_in_guest
= true;
11091 if (boot_cpu_has(X86_BUG_L1TF
) && enable_ept
) {
11092 switch (l1tf_mitigation
) {
11093 case L1TF_MITIGATION_OFF
:
11094 case L1TF_MITIGATION_FLUSH_NOWARN
:
11095 /* 'I explicitly don't care' is set */
11097 case L1TF_MITIGATION_FLUSH
:
11098 case L1TF_MITIGATION_FLUSH_NOSMT
:
11099 case L1TF_MITIGATION_FULL
:
11101 * Warn upon starting the first VM in a potentially
11102 * insecure environment.
11104 if (cpu_smt_control
== CPU_SMT_ENABLED
)
11105 pr_warn_once(L1TF_MSG_SMT
);
11106 if (l1tf_vmx_mitigation
== VMENTER_L1D_FLUSH_NEVER
)
11107 pr_warn_once(L1TF_MSG_L1D
);
11109 case L1TF_MITIGATION_FULL_FORCE
:
11110 /* Flush is enforced */
11117 static void __init
vmx_check_processor_compat(void *rtn
)
11119 struct vmcs_config vmcs_conf
;
11122 if (setup_vmcs_config(&vmcs_conf
) < 0)
11123 *(int *)rtn
= -EIO
;
11124 nested_vmx_setup_ctls_msrs(&vmcs_conf
.nested
, enable_apicv
);
11125 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
11126 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
11127 smp_processor_id());
11128 *(int *)rtn
= -EIO
;
11132 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
11137 /* For VT-d and EPT combination
11138 * 1. MMIO: always map as UC
11139 * 2. EPT with VT-d:
11140 * a. VT-d without snooping control feature: can't guarantee the
11141 * result, try to trust guest.
11142 * b. VT-d with snooping control feature: snooping control feature of
11143 * VT-d engine can guarantee the cache correctness. Just set it
11144 * to WB to keep consistent with host. So the same as item 3.
11145 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
11146 * consistent with host MTRR
11149 cache
= MTRR_TYPE_UNCACHABLE
;
11153 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
11154 ipat
= VMX_EPT_IPAT_BIT
;
11155 cache
= MTRR_TYPE_WRBACK
;
11159 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
11160 ipat
= VMX_EPT_IPAT_BIT
;
11161 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
11162 cache
= MTRR_TYPE_WRBACK
;
11164 cache
= MTRR_TYPE_UNCACHABLE
;
11168 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
11171 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
11174 static int vmx_get_lpage_level(void)
11176 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
11177 return PT_DIRECTORY_LEVEL
;
11179 /* For shadow and EPT supported 1GB page */
11180 return PT_PDPE_LEVEL
;
11183 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
11186 * These bits in the secondary execution controls field
11187 * are dynamic, the others are mostly based on the hypervisor
11188 * architecture and the guest's CPUID. Do not touch the
11192 SECONDARY_EXEC_SHADOW_VMCS
|
11193 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
11194 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
11195 SECONDARY_EXEC_DESC
;
11197 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
11199 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
11200 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
11204 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
11205 * (indicating "allowed-1") if they are supported in the guest's CPUID.
11207 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
11209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11210 struct kvm_cpuid_entry2
*entry
;
11212 vmx
->nested
.msrs
.cr0_fixed1
= 0xffffffff;
11213 vmx
->nested
.msrs
.cr4_fixed1
= X86_CR4_PCE
;
11215 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
11216 if (entry && (entry->_reg & (_cpuid_mask))) \
11217 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
11220 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
11221 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
11222 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
11223 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
11224 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
11225 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
11226 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
11227 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
11228 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
11229 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
11230 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
11231 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
11232 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
11233 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
11234 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
11236 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
11237 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
11238 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
11239 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
11240 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
11241 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
11243 #undef cr4_fixed1_update
11246 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
11248 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11250 if (cpu_has_secondary_exec_ctrls()) {
11251 vmx_compute_secondary_exec_control(vmx
);
11252 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
11255 if (nested_vmx_allowed(vcpu
))
11256 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11257 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
11259 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11260 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
11262 if (nested_vmx_allowed(vcpu
))
11263 nested_vmx_cr_fixed1_bits_update(vcpu
);
11266 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
11268 if (func
== 1 && nested
)
11269 entry
->ecx
|= bit(X86_FEATURE_VMX
);
11272 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
11273 struct x86_exception
*fault
)
11275 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11276 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11278 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
11280 if (vmx
->nested
.pml_full
) {
11281 exit_reason
= EXIT_REASON_PML_FULL
;
11282 vmx
->nested
.pml_full
= false;
11283 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
11284 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
11285 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
11287 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
11289 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
11290 vmcs12
->guest_physical_address
= fault
->address
;
11293 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
11295 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
11298 /* Callbacks for nested_ept_init_mmu_context: */
11300 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
11302 /* return the page table to be shadowed - in our case, EPT12 */
11303 return get_vmcs12(vcpu
)->ept_pointer
;
11306 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
11308 WARN_ON(mmu_is_nested(vcpu
));
11309 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
11312 kvm_init_shadow_ept_mmu(vcpu
,
11313 to_vmx(vcpu
)->nested
.msrs
.ept_caps
&
11314 VMX_EPT_EXECUTE_ONLY_BIT
,
11315 nested_ept_ad_enabled(vcpu
),
11316 nested_ept_get_cr3(vcpu
));
11317 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
11318 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
11319 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
11321 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
11325 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
11327 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
11330 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
11333 bool inequality
, bit
;
11335 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
11337 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
11338 vmcs12
->page_fault_error_code_match
;
11339 return inequality
^ bit
;
11342 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
11343 struct x86_exception
*fault
)
11345 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11347 WARN_ON(!is_guest_mode(vcpu
));
11349 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
11350 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
11351 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
11352 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11353 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
11354 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
11357 kvm_inject_page_fault(vcpu
, fault
);
11361 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
11362 struct vmcs12
*vmcs12
);
11364 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
)
11366 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11367 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11371 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11373 * Translate L1 physical address to host physical
11374 * address for vmcs02. Keep the page pinned, so this
11375 * physical address remains valid. We keep a reference
11376 * to it so we can release it later.
11378 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
11379 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11380 vmx
->nested
.apic_access_page
= NULL
;
11382 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
11384 * If translation failed, no matter: This feature asks
11385 * to exit when accessing the given address, and if it
11386 * can never be accessed, this feature won't do
11389 if (!is_error_page(page
)) {
11390 vmx
->nested
.apic_access_page
= page
;
11391 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
11392 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
11394 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
11395 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
11399 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
11400 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
11401 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11402 vmx
->nested
.virtual_apic_page
= NULL
;
11404 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
11407 * If translation failed, VM entry will fail because
11408 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
11409 * Failing the vm entry is _not_ what the processor
11410 * does but it's basically the only possibility we
11411 * have. We could still enter the guest if CR8 load
11412 * exits are enabled, CR8 store exits are enabled, and
11413 * virtualize APIC access is disabled; in this case
11414 * the processor would never use the TPR shadow and we
11415 * could simply clear the bit from the execution
11416 * control. But such a configuration is useless, so
11417 * let's keep the code simple.
11419 if (!is_error_page(page
)) {
11420 vmx
->nested
.virtual_apic_page
= page
;
11421 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
11422 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
11426 if (nested_cpu_has_posted_intr(vmcs12
)) {
11427 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
11428 kunmap(vmx
->nested
.pi_desc_page
);
11429 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11430 vmx
->nested
.pi_desc_page
= NULL
;
11432 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
11433 if (is_error_page(page
))
11435 vmx
->nested
.pi_desc_page
= page
;
11436 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
11437 vmx
->nested
.pi_desc
=
11438 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
11439 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
11441 vmcs_write64(POSTED_INTR_DESC_ADDR
,
11442 page_to_phys(vmx
->nested
.pi_desc_page
) +
11443 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
11446 if (nested_vmx_prepare_msr_bitmap(vcpu
, vmcs12
))
11447 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
11448 CPU_BASED_USE_MSR_BITMAPS
);
11450 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
11451 CPU_BASED_USE_MSR_BITMAPS
);
11454 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
11456 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
11457 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11460 * A timer value of zero is architecturally guaranteed to cause
11461 * a VMExit prior to executing any instructions in the guest.
11463 if (preemption_timeout
== 0) {
11464 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
11468 if (vcpu
->arch
.virtual_tsc_khz
== 0)
11471 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11472 preemption_timeout
*= 1000000;
11473 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
11474 hrtimer_start(&vmx
->nested
.preemption_timer
,
11475 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
11478 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
11479 struct vmcs12
*vmcs12
)
11481 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
11484 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
11485 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
11491 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
11492 struct vmcs12
*vmcs12
)
11494 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
11497 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
11503 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
11504 struct vmcs12
*vmcs12
)
11506 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
11509 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
11516 * Merge L0's and L1's MSR bitmap, return false to indicate that
11517 * we do not use the hardware.
11519 static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu
*vcpu
,
11520 struct vmcs12
*vmcs12
)
11524 unsigned long *msr_bitmap_l1
;
11525 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.vmcs02
.msr_bitmap
;
11527 * pred_cmd & spec_ctrl are trying to verify two things:
11529 * 1. L0 gave a permission to L1 to actually passthrough the MSR. This
11530 * ensures that we do not accidentally generate an L02 MSR bitmap
11531 * from the L12 MSR bitmap that is too permissive.
11532 * 2. That L1 or L2s have actually used the MSR. This avoids
11533 * unnecessarily merging of the bitmap if the MSR is unused. This
11534 * works properly because we only update the L01 MSR bitmap lazily.
11535 * So even if L0 should pass L1 these MSRs, the L01 bitmap is only
11536 * updated to reflect this when L1 (or its L2s) actually write to
11539 bool pred_cmd
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_PRED_CMD
);
11540 bool spec_ctrl
= !msr_write_intercepted_l01(vcpu
, MSR_IA32_SPEC_CTRL
);
11542 /* Nothing to do if the MSR bitmap is not in use. */
11543 if (!cpu_has_vmx_msr_bitmap() ||
11544 !nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
11547 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
11548 !pred_cmd
&& !spec_ctrl
)
11551 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
11552 if (is_error_page(page
))
11555 msr_bitmap_l1
= (unsigned long *)kmap(page
);
11556 if (nested_cpu_has_apic_reg_virt(vmcs12
)) {
11558 * L0 need not intercept reads for MSRs between 0x800 and 0x8ff, it
11559 * just lets the processor take the value from the virtual-APIC page;
11560 * take those 256 bits directly from the L1 bitmap.
11562 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
11563 unsigned word
= msr
/ BITS_PER_LONG
;
11564 msr_bitmap_l0
[word
] = msr_bitmap_l1
[word
];
11565 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
11568 for (msr
= 0x800; msr
<= 0x8ff; msr
+= BITS_PER_LONG
) {
11569 unsigned word
= msr
/ BITS_PER_LONG
;
11570 msr_bitmap_l0
[word
] = ~0;
11571 msr_bitmap_l0
[word
+ (0x800 / sizeof(long))] = ~0;
11575 nested_vmx_disable_intercept_for_msr(
11576 msr_bitmap_l1
, msr_bitmap_l0
,
11577 X2APIC_MSR(APIC_TASKPRI
),
11580 if (nested_cpu_has_vid(vmcs12
)) {
11581 nested_vmx_disable_intercept_for_msr(
11582 msr_bitmap_l1
, msr_bitmap_l0
,
11583 X2APIC_MSR(APIC_EOI
),
11585 nested_vmx_disable_intercept_for_msr(
11586 msr_bitmap_l1
, msr_bitmap_l0
,
11587 X2APIC_MSR(APIC_SELF_IPI
),
11592 nested_vmx_disable_intercept_for_msr(
11593 msr_bitmap_l1
, msr_bitmap_l0
,
11594 MSR_IA32_SPEC_CTRL
,
11595 MSR_TYPE_R
| MSR_TYPE_W
);
11598 nested_vmx_disable_intercept_for_msr(
11599 msr_bitmap_l1
, msr_bitmap_l0
,
11604 kvm_release_page_clean(page
);
11609 static void nested_cache_shadow_vmcs12(struct kvm_vcpu
*vcpu
,
11610 struct vmcs12
*vmcs12
)
11612 struct vmcs12
*shadow
;
11615 if (!nested_cpu_has_shadow_vmcs(vmcs12
) ||
11616 vmcs12
->vmcs_link_pointer
== -1ull)
11619 shadow
= get_shadow_vmcs12(vcpu
);
11620 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->vmcs_link_pointer
);
11622 memcpy(shadow
, kmap(page
), VMCS12_SIZE
);
11625 kvm_release_page_clean(page
);
11628 static void nested_flush_cached_shadow_vmcs12(struct kvm_vcpu
*vcpu
,
11629 struct vmcs12
*vmcs12
)
11631 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11633 if (!nested_cpu_has_shadow_vmcs(vmcs12
) ||
11634 vmcs12
->vmcs_link_pointer
== -1ull)
11637 kvm_write_guest(vmx
->vcpu
.kvm
, vmcs12
->vmcs_link_pointer
,
11638 get_shadow_vmcs12(vcpu
), VMCS12_SIZE
);
11641 static int nested_vmx_check_apic_access_controls(struct kvm_vcpu
*vcpu
,
11642 struct vmcs12
*vmcs12
)
11644 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
11645 !page_address_valid(vcpu
, vmcs12
->apic_access_addr
))
11651 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
11652 struct vmcs12
*vmcs12
)
11654 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
11655 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
11656 !nested_cpu_has_vid(vmcs12
) &&
11657 !nested_cpu_has_posted_intr(vmcs12
))
11661 * If virtualize x2apic mode is enabled,
11662 * virtualize apic access must be disabled.
11664 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
11665 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
11669 * If virtual interrupt delivery is enabled,
11670 * we must exit on external interrupts.
11672 if (nested_cpu_has_vid(vmcs12
) &&
11673 !nested_exit_on_intr(vcpu
))
11677 * bits 15:8 should be zero in posted_intr_nv,
11678 * the descriptor address has been already checked
11679 * in nested_get_vmcs12_pages.
11681 if (nested_cpu_has_posted_intr(vmcs12
) &&
11682 (!nested_cpu_has_vid(vmcs12
) ||
11683 !nested_exit_intr_ack_set(vcpu
) ||
11684 vmcs12
->posted_intr_nv
& 0xff00))
11687 /* tpr shadow is needed by all apicv features. */
11688 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
11694 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
11695 unsigned long count_field
,
11696 unsigned long addr_field
)
11698 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11702 if (vmcs12_read_any(vmcs12
, count_field
, &count
) ||
11703 vmcs12_read_any(vmcs12
, addr_field
, &addr
)) {
11709 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
11710 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
11711 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
11712 pr_debug_ratelimited(
11713 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
11714 addr_field
, maxphyaddr
, count
, addr
);
11720 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
11721 struct vmcs12
*vmcs12
)
11723 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
11724 vmcs12
->vm_exit_msr_store_count
== 0 &&
11725 vmcs12
->vm_entry_msr_load_count
== 0)
11726 return 0; /* Fast path */
11727 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
11728 VM_EXIT_MSR_LOAD_ADDR
) ||
11729 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
11730 VM_EXIT_MSR_STORE_ADDR
) ||
11731 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
11732 VM_ENTRY_MSR_LOAD_ADDR
))
11737 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
11738 struct vmcs12
*vmcs12
)
11740 u64 address
= vmcs12
->pml_address
;
11741 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
11743 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
11744 if (!nested_cpu_has_ept(vmcs12
) ||
11745 !IS_ALIGNED(address
, 4096) ||
11746 address
>> maxphyaddr
)
11753 static int nested_vmx_check_shadow_vmcs_controls(struct kvm_vcpu
*vcpu
,
11754 struct vmcs12
*vmcs12
)
11756 if (!nested_cpu_has_shadow_vmcs(vmcs12
))
11759 if (!page_address_valid(vcpu
, vmcs12
->vmread_bitmap
) ||
11760 !page_address_valid(vcpu
, vmcs12
->vmwrite_bitmap
))
11766 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
11767 struct vmx_msr_entry
*e
)
11769 /* x2APIC MSR accesses are not allowed */
11770 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
11772 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
11773 e
->index
== MSR_IA32_UCODE_REV
)
11775 if (e
->reserved
!= 0)
11780 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
11781 struct vmx_msr_entry
*e
)
11783 if (e
->index
== MSR_FS_BASE
||
11784 e
->index
== MSR_GS_BASE
||
11785 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
11786 nested_vmx_msr_check_common(vcpu
, e
))
11791 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
11792 struct vmx_msr_entry
*e
)
11794 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
11795 nested_vmx_msr_check_common(vcpu
, e
))
11801 * Load guest's/host's msr at nested entry/exit.
11802 * return 0 for success, entry index for failure.
11804 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
11807 struct vmx_msr_entry e
;
11808 struct msr_data msr
;
11810 msr
.host_initiated
= false;
11811 for (i
= 0; i
< count
; i
++) {
11812 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
11814 pr_debug_ratelimited(
11815 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11816 __func__
, i
, gpa
+ i
* sizeof(e
));
11819 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
11820 pr_debug_ratelimited(
11821 "%s check failed (%u, 0x%x, 0x%x)\n",
11822 __func__
, i
, e
.index
, e
.reserved
);
11825 msr
.index
= e
.index
;
11826 msr
.data
= e
.value
;
11827 if (kvm_set_msr(vcpu
, &msr
)) {
11828 pr_debug_ratelimited(
11829 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11830 __func__
, i
, e
.index
, e
.value
);
11839 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
11842 struct vmx_msr_entry e
;
11844 for (i
= 0; i
< count
; i
++) {
11845 struct msr_data msr_info
;
11846 if (kvm_vcpu_read_guest(vcpu
,
11847 gpa
+ i
* sizeof(e
),
11848 &e
, 2 * sizeof(u32
))) {
11849 pr_debug_ratelimited(
11850 "%s cannot read MSR entry (%u, 0x%08llx)\n",
11851 __func__
, i
, gpa
+ i
* sizeof(e
));
11854 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
11855 pr_debug_ratelimited(
11856 "%s check failed (%u, 0x%x, 0x%x)\n",
11857 __func__
, i
, e
.index
, e
.reserved
);
11860 msr_info
.host_initiated
= false;
11861 msr_info
.index
= e
.index
;
11862 if (kvm_get_msr(vcpu
, &msr_info
)) {
11863 pr_debug_ratelimited(
11864 "%s cannot read MSR (%u, 0x%x)\n",
11865 __func__
, i
, e
.index
);
11868 if (kvm_vcpu_write_guest(vcpu
,
11869 gpa
+ i
* sizeof(e
) +
11870 offsetof(struct vmx_msr_entry
, value
),
11871 &msr_info
.data
, sizeof(msr_info
.data
))) {
11872 pr_debug_ratelimited(
11873 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
11874 __func__
, i
, e
.index
, msr_info
.data
);
11881 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
11883 unsigned long invalid_mask
;
11885 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
11886 return (val
& invalid_mask
) == 0;
11890 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
11891 * emulating VM entry into a guest with EPT enabled.
11892 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
11893 * is assigned to entry_failure_code on failure.
11895 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
11896 u32
*entry_failure_code
)
11898 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
11899 if (!nested_cr3_valid(vcpu
, cr3
)) {
11900 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
11905 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
11906 * must not be dereferenced.
11908 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
11910 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
11911 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
11918 kvm_mmu_new_cr3(vcpu
, cr3
, false);
11920 vcpu
->arch
.cr3
= cr3
;
11921 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
11923 kvm_init_mmu(vcpu
, false);
11928 static void prepare_vmcs02_full(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11930 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11932 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
11933 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
11934 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
11935 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
11936 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
11937 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
11938 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
11939 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
11940 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
11941 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
11942 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
11943 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
11944 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
11945 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
11946 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
11947 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
11948 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
11949 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
11950 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
11951 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
11952 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
11953 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
11954 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
11955 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
11956 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
11957 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
11958 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
11959 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
11960 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
11961 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
11962 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
11964 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
11965 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
11966 vmcs12
->guest_pending_dbg_exceptions
);
11967 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
11968 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
11970 if (nested_cpu_has_xsaves(vmcs12
))
11971 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
11972 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
11974 if (cpu_has_vmx_posted_intr())
11975 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
11978 * Whether page-faults are trapped is determined by a combination of
11979 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
11980 * If enable_ept, L0 doesn't care about page faults and we should
11981 * set all of these to L1's desires. However, if !enable_ept, L0 does
11982 * care about (at least some) page faults, and because it is not easy
11983 * (if at all possible?) to merge L0 and L1's desires, we simply ask
11984 * to exit on each and every L2 page fault. This is done by setting
11985 * MASK=MATCH=0 and (see below) EB.PF=1.
11986 * Note that below we don't need special code to set EB.PF beyond the
11987 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
11988 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
11989 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
11991 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
11992 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
11993 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
11994 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
11996 /* All VMFUNCs are currently emulated through L0 vmexits. */
11997 if (cpu_has_vmx_vmfunc())
11998 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
12000 if (cpu_has_vmx_apicv()) {
12001 vmcs_write64(EOI_EXIT_BITMAP0
, vmcs12
->eoi_exit_bitmap0
);
12002 vmcs_write64(EOI_EXIT_BITMAP1
, vmcs12
->eoi_exit_bitmap1
);
12003 vmcs_write64(EOI_EXIT_BITMAP2
, vmcs12
->eoi_exit_bitmap2
);
12004 vmcs_write64(EOI_EXIT_BITMAP3
, vmcs12
->eoi_exit_bitmap3
);
12008 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
12009 * Some constant fields are set here by vmx_set_constant_host_state().
12010 * Other fields are different per CPU, and will be set later when
12011 * vmx_vcpu_load() is called, and when vmx_prepare_switch_to_guest()
12014 vmx_set_constant_host_state(vmx
);
12017 * Set the MSR load/store lists to match L0's settings.
12019 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
12020 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.host
.nr
);
12021 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
.val
));
12022 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.guest
.nr
);
12023 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
.val
));
12025 set_cr4_guest_host_mask(vmx
);
12027 if (vmx_mpx_supported())
12028 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
12031 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
)
12032 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
12034 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
12038 * L1 may access the L2's PDPTR, so save them to construct vmcs12
12041 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
12042 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
12043 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
12044 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
12047 if (cpu_has_vmx_msr_bitmap())
12048 vmcs_write64(MSR_BITMAP
, __pa(vmx
->nested
.vmcs02
.msr_bitmap
));
12052 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
12053 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
12054 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
12055 * guest in a way that will both be appropriate to L1's requests, and our
12056 * needs. In addition to modifying the active vmcs (which is vmcs02), this
12057 * function also has additional necessary side-effects, like setting various
12058 * vcpu->arch fields.
12059 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
12060 * is assigned to entry_failure_code on failure.
12062 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
12063 u32
*entry_failure_code
)
12065 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12066 u32 exec_control
, vmcs12_exec_ctrl
;
12068 if (vmx
->nested
.dirty_vmcs12
) {
12069 prepare_vmcs02_full(vcpu
, vmcs12
);
12070 vmx
->nested
.dirty_vmcs12
= false;
12074 * First, the fields that are shadowed. This must be kept in sync
12075 * with vmx_shadow_fields.h.
12078 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
12079 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
12080 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
12081 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
12082 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
12084 if (vmx
->nested
.nested_run_pending
&&
12085 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
12086 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
12087 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
12089 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
12090 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
12092 if (vmx
->nested
.nested_run_pending
) {
12093 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
12094 vmcs12
->vm_entry_intr_info_field
);
12095 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
12096 vmcs12
->vm_entry_exception_error_code
);
12097 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
12098 vmcs12
->vm_entry_instruction_len
);
12099 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
12100 vmcs12
->guest_interruptibility_info
);
12101 vmx
->loaded_vmcs
->nmi_known_unmasked
=
12102 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
12104 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
12106 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
12108 exec_control
= vmcs12
->pin_based_vm_exec_control
;
12110 /* Preemption timer setting is computed directly in vmx_vcpu_run. */
12111 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
12112 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
12113 vmx
->loaded_vmcs
->hv_timer_armed
= false;
12115 /* Posted interrupts setting is only taken from vmcs12. */
12116 if (nested_cpu_has_posted_intr(vmcs12
)) {
12117 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
12118 vmx
->nested
.pi_pending
= false;
12120 exec_control
&= ~PIN_BASED_POSTED_INTR
;
12123 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
12125 vmx
->nested
.preemption_timer_expired
= false;
12126 if (nested_cpu_has_preemption_timer(vmcs12
))
12127 vmx_start_preemption_timer(vcpu
);
12129 if (cpu_has_secondary_exec_ctrls()) {
12130 exec_control
= vmx
->secondary_exec_control
;
12132 /* Take the following fields only from vmcs12 */
12133 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
12134 SECONDARY_EXEC_ENABLE_INVPCID
|
12135 SECONDARY_EXEC_RDTSCP
|
12136 SECONDARY_EXEC_XSAVES
|
12137 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
12138 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
12139 SECONDARY_EXEC_ENABLE_VMFUNC
);
12140 if (nested_cpu_has(vmcs12
,
12141 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
12142 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
12143 ~SECONDARY_EXEC_ENABLE_PML
;
12144 exec_control
|= vmcs12_exec_ctrl
;
12147 /* VMCS shadowing for L2 is emulated for now */
12148 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
12150 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
12151 vmcs_write16(GUEST_INTR_STATUS
,
12152 vmcs12
->guest_intr_status
);
12155 * Write an illegal value to APIC_ACCESS_ADDR. Later,
12156 * nested_get_vmcs12_pages will either fix it up or
12157 * remove the VM execution control.
12159 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
12160 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
12162 if (exec_control
& SECONDARY_EXEC_ENCLS_EXITING
)
12163 vmcs_write64(ENCLS_EXITING_BITMAP
, -1ull);
12165 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
12169 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
12170 * entry, but only if the current (host) sp changed from the value
12171 * we wrote last (vmx->host_rsp). This cache is no longer relevant
12172 * if we switch vmcs, and rather than hold a separate cache per vmcs,
12173 * here we just force the write to happen on entry.
12177 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
12178 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
12179 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
12180 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
12181 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
12184 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
12185 * nested_get_vmcs12_pages can't fix it up, the illegal value
12186 * will result in a VM entry failure.
12188 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
12189 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
12190 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
12192 #ifdef CONFIG_X86_64
12193 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
12194 CPU_BASED_CR8_STORE_EXITING
;
12199 * A vmexit (to either L1 hypervisor or L0 userspace) is always needed
12200 * for I/O port accesses.
12202 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
12203 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
12205 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
12207 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
12208 * bitwise-or of what L1 wants to trap for L2, and what we want to
12209 * trap. Note that CR0.TS also needs updating - we do this later.
12211 update_exception_bitmap(vcpu
);
12212 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
12213 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
12215 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
12216 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
12217 * bits are further modified by vmx_set_efer() below.
12219 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
12221 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
12222 * emulated by vmx_set_efer(), below.
12224 vm_entry_controls_init(vmx
,
12225 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
12226 ~VM_ENTRY_IA32E_MODE
) |
12227 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
12229 if (vmx
->nested
.nested_run_pending
&&
12230 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
12231 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
12232 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
12233 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
12234 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
12237 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
12239 if (kvm_has_tsc_control
)
12240 decache_tsc_multiplier(vmx
);
12244 * There is no direct mapping between vpid02 and vpid12, the
12245 * vpid02 is per-vCPU for L0 and reused while the value of
12246 * vpid12 is changed w/ one invvpid during nested vmentry.
12247 * The vpid12 is allocated by L1 for L2, so it will not
12248 * influence global bitmap(for vpid01 and vpid02 allocation)
12249 * even if spawn a lot of nested vCPUs.
12251 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
12252 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
12253 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
12254 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
, true);
12257 vmx_flush_tlb(vcpu
, true);
12263 * Conceptually we want to copy the PML address and index from
12264 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
12265 * since we always flush the log on each vmexit, this happens
12266 * to be equivalent to simply resetting the fields in vmcs02.
12268 ASSERT(vmx
->pml_pg
);
12269 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
12270 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
12273 if (nested_cpu_has_ept(vmcs12
)) {
12274 if (nested_ept_init_mmu_context(vcpu
)) {
12275 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
12278 } else if (nested_cpu_has2(vmcs12
,
12279 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
12280 vmx_flush_tlb(vcpu
, true);
12284 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
12285 * bits which we consider mandatory enabled.
12286 * The CR0_READ_SHADOW is what L2 should have expected to read given
12287 * the specifications by L1; It's not enough to take
12288 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
12289 * have more bits than L1 expected.
12291 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
12292 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
12294 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
12295 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
12297 if (vmx
->nested
.nested_run_pending
&&
12298 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
12299 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
12300 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
12301 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
12303 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
12304 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
12305 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
12308 * Guest state is invalid and unrestricted guest is disabled,
12309 * which means L1 attempted VMEntry to L2 with invalid state.
12310 * Fail the VMEntry.
12312 if (vmx
->emulation_required
) {
12313 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
12317 /* Shadow page tables on either EPT or shadow page tables. */
12318 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
12319 entry_failure_code
))
12323 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
12325 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
12326 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
12330 static int nested_vmx_check_nmi_controls(struct vmcs12
*vmcs12
)
12332 if (!nested_cpu_has_nmi_exiting(vmcs12
) &&
12333 nested_cpu_has_virtual_nmis(vmcs12
))
12336 if (!nested_cpu_has_virtual_nmis(vmcs12
) &&
12337 nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
))
12343 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
12345 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12347 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
12348 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
12349 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12351 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
12352 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12354 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
12355 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12357 if (nested_vmx_check_apic_access_controls(vcpu
, vmcs12
))
12358 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12360 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
12361 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12363 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
12364 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12366 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
12367 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12369 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
12370 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12372 if (nested_vmx_check_shadow_vmcs_controls(vcpu
, vmcs12
))
12373 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12375 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
12376 vmx
->nested
.msrs
.procbased_ctls_low
,
12377 vmx
->nested
.msrs
.procbased_ctls_high
) ||
12378 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
12379 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
12380 vmx
->nested
.msrs
.secondary_ctls_low
,
12381 vmx
->nested
.msrs
.secondary_ctls_high
)) ||
12382 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
12383 vmx
->nested
.msrs
.pinbased_ctls_low
,
12384 vmx
->nested
.msrs
.pinbased_ctls_high
) ||
12385 !vmx_control_verify(vmcs12
->vm_exit_controls
,
12386 vmx
->nested
.msrs
.exit_ctls_low
,
12387 vmx
->nested
.msrs
.exit_ctls_high
) ||
12388 !vmx_control_verify(vmcs12
->vm_entry_controls
,
12389 vmx
->nested
.msrs
.entry_ctls_low
,
12390 vmx
->nested
.msrs
.entry_ctls_high
))
12391 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12393 if (nested_vmx_check_nmi_controls(vmcs12
))
12394 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12396 if (nested_cpu_has_vmfunc(vmcs12
)) {
12397 if (vmcs12
->vm_function_control
&
12398 ~vmx
->nested
.msrs
.vmfunc_controls
)
12399 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12401 if (nested_cpu_has_eptp_switching(vmcs12
)) {
12402 if (!nested_cpu_has_ept(vmcs12
) ||
12403 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
12404 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12408 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
12409 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12411 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
12412 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
12413 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
12414 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
12417 * From the Intel SDM, volume 3:
12418 * Fields relevant to VM-entry event injection must be set properly.
12419 * These fields are the VM-entry interruption-information field, the
12420 * VM-entry exception error code, and the VM-entry instruction length.
12422 if (vmcs12
->vm_entry_intr_info_field
& INTR_INFO_VALID_MASK
) {
12423 u32 intr_info
= vmcs12
->vm_entry_intr_info_field
;
12424 u8 vector
= intr_info
& INTR_INFO_VECTOR_MASK
;
12425 u32 intr_type
= intr_info
& INTR_INFO_INTR_TYPE_MASK
;
12426 bool has_error_code
= intr_info
& INTR_INFO_DELIVER_CODE_MASK
;
12427 bool should_have_error_code
;
12428 bool urg
= nested_cpu_has2(vmcs12
,
12429 SECONDARY_EXEC_UNRESTRICTED_GUEST
);
12430 bool prot_mode
= !urg
|| vmcs12
->guest_cr0
& X86_CR0_PE
;
12432 /* VM-entry interruption-info field: interruption type */
12433 if (intr_type
== INTR_TYPE_RESERVED
||
12434 (intr_type
== INTR_TYPE_OTHER_EVENT
&&
12435 !nested_cpu_supports_monitor_trap_flag(vcpu
)))
12436 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12438 /* VM-entry interruption-info field: vector */
12439 if ((intr_type
== INTR_TYPE_NMI_INTR
&& vector
!= NMI_VECTOR
) ||
12440 (intr_type
== INTR_TYPE_HARD_EXCEPTION
&& vector
> 31) ||
12441 (intr_type
== INTR_TYPE_OTHER_EVENT
&& vector
!= 0))
12442 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12444 /* VM-entry interruption-info field: deliver error code */
12445 should_have_error_code
=
12446 intr_type
== INTR_TYPE_HARD_EXCEPTION
&& prot_mode
&&
12447 x86_exception_has_error_code(vector
);
12448 if (has_error_code
!= should_have_error_code
)
12449 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12451 /* VM-entry exception error code */
12452 if (has_error_code
&&
12453 vmcs12
->vm_entry_exception_error_code
& GENMASK(31, 15))
12454 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12456 /* VM-entry interruption-info field: reserved bits */
12457 if (intr_info
& INTR_INFO_RESVD_BITS_MASK
)
12458 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12460 /* VM-entry instruction length */
12461 switch (intr_type
) {
12462 case INTR_TYPE_SOFT_EXCEPTION
:
12463 case INTR_TYPE_SOFT_INTR
:
12464 case INTR_TYPE_PRIV_SW_EXCEPTION
:
12465 if ((vmcs12
->vm_entry_instruction_len
> 15) ||
12466 (vmcs12
->vm_entry_instruction_len
== 0 &&
12467 !nested_cpu_has_zero_length_injection(vcpu
)))
12468 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
12475 static int nested_vmx_check_vmcs_link_ptr(struct kvm_vcpu
*vcpu
,
12476 struct vmcs12
*vmcs12
)
12480 struct vmcs12
*shadow
;
12482 if (vmcs12
->vmcs_link_pointer
== -1ull)
12485 if (!page_address_valid(vcpu
, vmcs12
->vmcs_link_pointer
))
12488 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->vmcs_link_pointer
);
12489 if (is_error_page(page
))
12493 shadow
= kmap(page
);
12494 if (shadow
->hdr
.revision_id
!= VMCS12_REVISION
||
12495 shadow
->hdr
.shadow_vmcs
!= nested_cpu_has_shadow_vmcs(vmcs12
))
12498 kvm_release_page_clean(page
);
12502 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
12507 *exit_qual
= ENTRY_FAIL_DEFAULT
;
12509 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
12510 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
12513 if (nested_vmx_check_vmcs_link_ptr(vcpu
, vmcs12
)) {
12514 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
12519 * If the load IA32_EFER VM-entry control is 1, the following checks
12520 * are performed on the field for the IA32_EFER MSR:
12521 * - Bits reserved in the IA32_EFER MSR must be 0.
12522 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
12523 * the IA-32e mode guest VM-exit control. It must also be identical
12524 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
12527 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
12528 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
12529 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
12530 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
12531 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
12532 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
12533 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
12538 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
12539 * IA32_EFER MSR must be 0 in the field for that register. In addition,
12540 * the values of the LMA and LME bits in the field must each be that of
12541 * the host address-space size VM-exit control.
12543 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
12544 ia32e
= (vmcs12
->vm_exit_controls
&
12545 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
12546 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
12547 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
12548 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
12552 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
12553 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
12554 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
12561 * If exit_qual is NULL, this is being called from state restore (either RSM
12562 * or KVM_SET_NESTED_STATE). Otherwise it's called from vmlaunch/vmresume.
12564 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, u32
*exit_qual
)
12566 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12567 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
12568 bool from_vmentry
= !!exit_qual
;
12569 u32 dummy_exit_qual
;
12570 u32 vmcs01_cpu_exec_ctrl
;
12573 vmcs01_cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
12575 enter_guest_mode(vcpu
);
12577 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
12578 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
12580 vmx_switch_vmcs(vcpu
, &vmx
->nested
.vmcs02
);
12581 vmx_segment_cache_clear(vmx
);
12583 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
12584 vcpu
->arch
.tsc_offset
+= vmcs12
->tsc_offset
;
12586 r
= EXIT_REASON_INVALID_STATE
;
12587 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
? exit_qual
: &dummy_exit_qual
))
12590 if (from_vmentry
) {
12591 nested_get_vmcs12_pages(vcpu
);
12593 r
= EXIT_REASON_MSR_LOAD_FAIL
;
12594 *exit_qual
= nested_vmx_load_msr(vcpu
,
12595 vmcs12
->vm_entry_msr_load_addr
,
12596 vmcs12
->vm_entry_msr_load_count
);
12601 * The MMU is not initialized to point at the right entities yet and
12602 * "get pages" would need to read data from the guest (i.e. we will
12603 * need to perform gpa to hpa translation). Request a call
12604 * to nested_get_vmcs12_pages before the next VM-entry. The MSRs
12605 * have already been set at vmentry time and should not be reset.
12607 kvm_make_request(KVM_REQ_GET_VMCS12_PAGES
, vcpu
);
12611 * If L1 had a pending IRQ/NMI until it executed
12612 * VMLAUNCH/VMRESUME which wasn't delivered because it was
12613 * disallowed (e.g. interrupts disabled), L0 needs to
12614 * evaluate if this pending event should cause an exit from L2
12615 * to L1 or delivered directly to L2 (e.g. In case L1 don't
12616 * intercept EXTERNAL_INTERRUPT).
12618 * Usually this would be handled by L0 requesting a
12619 * IRQ/NMI window by setting VMCS accordingly. However,
12620 * this setting was done on VMCS01 and now VMCS02 is active
12621 * instead. Thus, we force L0 to perform pending event
12622 * evaluation by requesting a KVM_REQ_EVENT.
12624 if (vmcs01_cpu_exec_ctrl
&
12625 (CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_VIRTUAL_NMI_PENDING
)) {
12626 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
12630 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
12631 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
12632 * returned as far as L1 is concerned. It will only return (and set
12633 * the success flag) when L2 exits (see nested_vmx_vmexit()).
12638 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
12639 vcpu
->arch
.tsc_offset
-= vmcs12
->tsc_offset
;
12640 leave_guest_mode(vcpu
);
12641 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
12646 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
12647 * for running an L2 nested guest.
12649 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
12651 struct vmcs12
*vmcs12
;
12652 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12653 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
12657 if (!nested_vmx_check_permission(vcpu
))
12660 if (!nested_vmx_check_vmcs12(vcpu
))
12663 vmcs12
= get_vmcs12(vcpu
);
12666 * Can't VMLAUNCH or VMRESUME a shadow VMCS. Despite the fact
12667 * that there *is* a valid VMCS pointer, RFLAGS.CF is set
12668 * rather than RFLAGS.ZF, and no error number is stored to the
12669 * VM-instruction error field.
12671 if (vmcs12
->hdr
.shadow_vmcs
) {
12672 nested_vmx_failInvalid(vcpu
);
12676 if (enable_shadow_vmcs
)
12677 copy_shadow_to_vmcs12(vmx
);
12680 * The nested entry process starts with enforcing various prerequisites
12681 * on vmcs12 as required by the Intel SDM, and act appropriately when
12682 * they fail: As the SDM explains, some conditions should cause the
12683 * instruction to fail, while others will cause the instruction to seem
12684 * to succeed, but return an EXIT_REASON_INVALID_STATE.
12685 * To speed up the normal (success) code path, we should avoid checking
12686 * for misconfigurations which will anyway be caught by the processor
12687 * when using the merged vmcs02.
12689 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
12690 nested_vmx_failValid(vcpu
,
12691 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
12695 if (vmcs12
->launch_state
== launch
) {
12696 nested_vmx_failValid(vcpu
,
12697 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
12698 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
12702 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
12704 nested_vmx_failValid(vcpu
, ret
);
12709 * After this point, the trap flag no longer triggers a singlestep trap
12710 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
12711 * This is not 100% correct; for performance reasons, we delegate most
12712 * of the checks on host state to the processor. If those fail,
12713 * the singlestep trap is missed.
12715 skip_emulated_instruction(vcpu
);
12717 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
12719 nested_vmx_entry_failure(vcpu
, vmcs12
,
12720 EXIT_REASON_INVALID_STATE
, exit_qual
);
12725 * We're finally done with prerequisite checking, and can start with
12726 * the nested entry.
12729 vmx
->nested
.nested_run_pending
= 1;
12730 ret
= enter_vmx_non_root_mode(vcpu
, &exit_qual
);
12732 nested_vmx_entry_failure(vcpu
, vmcs12
, ret
, exit_qual
);
12733 vmx
->nested
.nested_run_pending
= 0;
12737 /* Hide L1D cache contents from the nested guest. */
12738 vmx
->vcpu
.arch
.l1tf_flush_l1d
= true;
12741 * Must happen outside of enter_vmx_non_root_mode() as it will
12742 * also be used as part of restoring nVMX state for
12743 * snapshot restore (migration).
12745 * In this flow, it is assumed that vmcs12 cache was
12746 * trasferred as part of captured nVMX state and should
12747 * therefore not be read from guest memory (which may not
12748 * exist on destination host yet).
12750 nested_cache_shadow_vmcs12(vcpu
, vmcs12
);
12753 * If we're entering a halted L2 vcpu and the L2 vcpu won't be woken
12754 * by event injection, halt vcpu.
12756 if ((vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
) &&
12757 !(vmcs12
->vm_entry_intr_info_field
& INTR_INFO_VALID_MASK
)) {
12758 vmx
->nested
.nested_run_pending
= 0;
12759 return kvm_vcpu_halt(vcpu
);
12764 return kvm_skip_emulated_instruction(vcpu
);
12768 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
12769 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
12770 * This function returns the new value we should put in vmcs12.guest_cr0.
12771 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
12772 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
12773 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
12774 * didn't trap the bit, because if L1 did, so would L0).
12775 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
12776 * been modified by L2, and L1 knows it. So just leave the old value of
12777 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
12778 * isn't relevant, because if L0 traps this bit it can set it to anything.
12779 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
12780 * changed these bits, and therefore they need to be updated, but L0
12781 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
12782 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
12784 static inline unsigned long
12785 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
12788 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
12789 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
12790 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
12791 vcpu
->arch
.cr0_guest_owned_bits
));
12794 static inline unsigned long
12795 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
12798 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
12799 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
12800 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
12801 vcpu
->arch
.cr4_guest_owned_bits
));
12804 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
12805 struct vmcs12
*vmcs12
)
12810 if (vcpu
->arch
.exception
.injected
) {
12811 nr
= vcpu
->arch
.exception
.nr
;
12812 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
12814 if (kvm_exception_is_soft(nr
)) {
12815 vmcs12
->vm_exit_instruction_len
=
12816 vcpu
->arch
.event_exit_inst_len
;
12817 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
12819 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
12821 if (vcpu
->arch
.exception
.has_error_code
) {
12822 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
12823 vmcs12
->idt_vectoring_error_code
=
12824 vcpu
->arch
.exception
.error_code
;
12827 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
12828 } else if (vcpu
->arch
.nmi_injected
) {
12829 vmcs12
->idt_vectoring_info_field
=
12830 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
12831 } else if (vcpu
->arch
.interrupt
.injected
) {
12832 nr
= vcpu
->arch
.interrupt
.nr
;
12833 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
12835 if (vcpu
->arch
.interrupt
.soft
) {
12836 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
12837 vmcs12
->vm_entry_instruction_len
=
12838 vcpu
->arch
.event_exit_inst_len
;
12840 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
12842 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
12846 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
12848 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12849 unsigned long exit_qual
;
12850 bool block_nested_events
=
12851 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
12853 if (vcpu
->arch
.exception
.pending
&&
12854 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
12855 if (block_nested_events
)
12857 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
12861 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
12862 vmx
->nested
.preemption_timer_expired
) {
12863 if (block_nested_events
)
12865 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
12869 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
12870 if (block_nested_events
)
12872 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
12873 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
12874 INTR_INFO_VALID_MASK
, 0);
12876 * The NMI-triggered VM exit counts as injection:
12877 * clear this one and block further NMIs.
12879 vcpu
->arch
.nmi_pending
= 0;
12880 vmx_set_nmi_mask(vcpu
, true);
12884 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
12885 nested_exit_on_intr(vcpu
)) {
12886 if (block_nested_events
)
12888 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
12892 vmx_complete_nested_posted_interrupt(vcpu
);
12896 static void vmx_request_immediate_exit(struct kvm_vcpu
*vcpu
)
12898 to_vmx(vcpu
)->req_immediate_exit
= true;
12901 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
12903 ktime_t remaining
=
12904 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
12907 if (ktime_to_ns(remaining
) <= 0)
12910 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
12911 do_div(value
, 1000000);
12912 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
12916 * Update the guest state fields of vmcs12 to reflect changes that
12917 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
12918 * VM-entry controls is also updated, since this is really a guest
12921 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
12923 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
12924 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
12926 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
12927 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
12928 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
12930 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
12931 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
12932 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
12933 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
12934 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
12935 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
12936 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
12937 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
12938 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
12939 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
12940 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
12941 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
12942 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
12943 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
12944 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
12945 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
12946 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
12947 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
12948 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
12949 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
12950 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
12951 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
12952 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
12953 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
12954 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
12955 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
12956 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
12957 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
12958 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
12959 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
12960 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
12961 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
12962 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
12963 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
12964 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
12965 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
12967 vmcs12
->guest_interruptibility_info
=
12968 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
12969 vmcs12
->guest_pending_dbg_exceptions
=
12970 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
12971 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
12972 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
12974 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
12976 if (nested_cpu_has_preemption_timer(vmcs12
)) {
12977 if (vmcs12
->vm_exit_controls
&
12978 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
12979 vmcs12
->vmx_preemption_timer_value
=
12980 vmx_get_preemption_timer_value(vcpu
);
12981 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
12985 * In some cases (usually, nested EPT), L2 is allowed to change its
12986 * own CR3 without exiting. If it has changed it, we must keep it.
12987 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
12988 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
12990 * Additionally, restore L2's PDPTR to vmcs12.
12993 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
12994 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
12995 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
12996 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
12997 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
13000 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
13002 if (nested_cpu_has_vid(vmcs12
))
13003 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
13005 vmcs12
->vm_entry_controls
=
13006 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
13007 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
13009 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
13010 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
13011 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
13014 /* TODO: These cannot have changed unless we have MSR bitmaps and
13015 * the relevant bit asks not to trap the change */
13016 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
13017 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
13018 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
13019 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
13020 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
13021 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
13022 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
13023 if (kvm_mpx_supported())
13024 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
13028 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
13029 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
13030 * and this function updates it to reflect the changes to the guest state while
13031 * L2 was running (and perhaps made some exits which were handled directly by L0
13032 * without going back to L1), and to reflect the exit reason.
13033 * Note that we do not have to copy here all VMCS fields, just those that
13034 * could have changed by the L2 guest or the exit - i.e., the guest-state and
13035 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
13036 * which already writes to vmcs12 directly.
13038 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
13039 u32 exit_reason
, u32 exit_intr_info
,
13040 unsigned long exit_qualification
)
13042 /* update guest state fields: */
13043 sync_vmcs12(vcpu
, vmcs12
);
13045 /* update exit information fields: */
13047 vmcs12
->vm_exit_reason
= exit_reason
;
13048 vmcs12
->exit_qualification
= exit_qualification
;
13049 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
13051 vmcs12
->idt_vectoring_info_field
= 0;
13052 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
13053 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
13055 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
13056 vmcs12
->launch_state
= 1;
13058 /* vm_entry_intr_info_field is cleared on exit. Emulate this
13059 * instead of reading the real value. */
13060 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
13063 * Transfer the event that L0 or L1 may wanted to inject into
13064 * L2 to IDT_VECTORING_INFO_FIELD.
13066 vmcs12_save_pending_event(vcpu
, vmcs12
);
13070 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
13071 * preserved above and would only end up incorrectly in L1.
13073 vcpu
->arch
.nmi_injected
= false;
13074 kvm_clear_exception_queue(vcpu
);
13075 kvm_clear_interrupt_queue(vcpu
);
13078 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
13079 struct vmcs12
*vmcs12
)
13081 u32 entry_failure_code
;
13083 nested_ept_uninit_mmu_context(vcpu
);
13086 * Only PDPTE load can fail as the value of cr3 was checked on entry and
13087 * couldn't have changed.
13089 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
13090 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
13093 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
13097 * A part of what we need to when the nested L2 guest exits and we want to
13098 * run its L1 parent, is to reset L1's guest state to the host state specified
13100 * This function is to be called not only on normal nested exit, but also on
13101 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
13102 * Failures During or After Loading Guest State").
13103 * This function should be called when the active VMCS is L1's (vmcs01).
13105 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
13106 struct vmcs12
*vmcs12
)
13108 struct kvm_segment seg
;
13110 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
13111 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
13112 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
13113 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
13115 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
13116 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
13118 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
13119 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
13120 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
13122 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
13123 * actually changed, because vmx_set_cr0 refers to efer set above.
13125 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
13126 * (KVM doesn't change it);
13128 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
13129 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
13131 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
13132 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
13133 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
13135 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
13138 * If vmcs01 don't use VPID, CPU flushes TLB on every
13139 * VMEntry/VMExit. Thus, no need to flush TLB.
13141 * If vmcs12 uses VPID, TLB entries populated by L2 are
13142 * tagged with vmx->nested.vpid02 while L1 entries are tagged
13143 * with vmx->vpid. Thus, no need to flush TLB.
13145 * Therefore, flush TLB only in case vmcs01 uses VPID and
13146 * vmcs12 don't use VPID as in this case L1 & L2 TLB entries
13147 * are both tagged with vmx->vpid.
13150 !(nested_cpu_has_vpid(vmcs12
) && to_vmx(vcpu
)->nested
.vpid02
)) {
13151 vmx_flush_tlb(vcpu
, true);
13154 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
13155 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
13156 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
13157 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
13158 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
13159 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
13160 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
13162 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
13163 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
13164 vmcs_write64(GUEST_BNDCFGS
, 0);
13166 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
13167 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
13168 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
13170 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
13171 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
13172 vmcs12
->host_ia32_perf_global_ctrl
);
13174 /* Set L1 segment info according to Intel SDM
13175 27.5.2 Loading Host Segment and Descriptor-Table Registers */
13176 seg
= (struct kvm_segment
) {
13178 .limit
= 0xFFFFFFFF,
13179 .selector
= vmcs12
->host_cs_selector
,
13185 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
13189 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
13190 seg
= (struct kvm_segment
) {
13192 .limit
= 0xFFFFFFFF,
13199 seg
.selector
= vmcs12
->host_ds_selector
;
13200 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
13201 seg
.selector
= vmcs12
->host_es_selector
;
13202 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
13203 seg
.selector
= vmcs12
->host_ss_selector
;
13204 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
13205 seg
.selector
= vmcs12
->host_fs_selector
;
13206 seg
.base
= vmcs12
->host_fs_base
;
13207 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
13208 seg
.selector
= vmcs12
->host_gs_selector
;
13209 seg
.base
= vmcs12
->host_gs_base
;
13210 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
13211 seg
= (struct kvm_segment
) {
13212 .base
= vmcs12
->host_tr_base
,
13214 .selector
= vmcs12
->host_tr_selector
,
13218 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
13220 kvm_set_dr(vcpu
, 7, 0x400);
13221 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
13223 if (cpu_has_vmx_msr_bitmap())
13224 vmx_update_msr_bitmap(vcpu
);
13226 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
13227 vmcs12
->vm_exit_msr_load_count
))
13228 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
13232 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
13233 * and modify vmcs12 to make it see what it would expect to see there if
13234 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
13236 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
13237 u32 exit_intr_info
,
13238 unsigned long exit_qualification
)
13240 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
13241 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
13243 /* trying to cancel vmlaunch/vmresume is a bug */
13244 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
13247 * The only expected VM-instruction error is "VM entry with
13248 * invalid control field(s)." Anything else indicates a
13251 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
13252 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
13254 leave_guest_mode(vcpu
);
13256 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
13257 vcpu
->arch
.tsc_offset
-= vmcs12
->tsc_offset
;
13259 if (likely(!vmx
->fail
)) {
13260 if (exit_reason
== -1)
13261 sync_vmcs12(vcpu
, vmcs12
);
13263 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
13264 exit_qualification
);
13267 * Must happen outside of sync_vmcs12() as it will
13268 * also be used to capture vmcs12 cache as part of
13269 * capturing nVMX state for snapshot (migration).
13271 * Otherwise, this flush will dirty guest memory at a
13272 * point it is already assumed by user-space to be
13275 nested_flush_cached_shadow_vmcs12(vcpu
, vmcs12
);
13277 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
13278 vmcs12
->vm_exit_msr_store_count
))
13279 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
13282 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
13283 vm_entry_controls_reset_shadow(vmx
);
13284 vm_exit_controls_reset_shadow(vmx
);
13285 vmx_segment_cache_clear(vmx
);
13287 /* Update any VMCS fields that might have changed while L2 ran */
13288 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.host
.nr
);
13289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.guest
.nr
);
13290 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
13292 if (kvm_has_tsc_control
)
13293 decache_tsc_multiplier(vmx
);
13295 if (vmx
->nested
.change_vmcs01_virtual_apic_mode
) {
13296 vmx
->nested
.change_vmcs01_virtual_apic_mode
= false;
13297 vmx_set_virtual_apic_mode(vcpu
);
13298 } else if (!nested_cpu_has_ept(vmcs12
) &&
13299 nested_cpu_has2(vmcs12
,
13300 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
13301 vmx_flush_tlb(vcpu
, true);
13304 /* This is needed for same reason as it was needed in prepare_vmcs02 */
13307 /* Unpin physical memory we referred to in vmcs02 */
13308 if (vmx
->nested
.apic_access_page
) {
13309 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
13310 vmx
->nested
.apic_access_page
= NULL
;
13312 if (vmx
->nested
.virtual_apic_page
) {
13313 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
13314 vmx
->nested
.virtual_apic_page
= NULL
;
13316 if (vmx
->nested
.pi_desc_page
) {
13317 kunmap(vmx
->nested
.pi_desc_page
);
13318 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
13319 vmx
->nested
.pi_desc_page
= NULL
;
13320 vmx
->nested
.pi_desc
= NULL
;
13324 * We are now running in L2, mmu_notifier will force to reload the
13325 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
13327 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
13329 if (enable_shadow_vmcs
&& exit_reason
!= -1)
13330 vmx
->nested
.sync_shadow_vmcs
= true;
13332 /* in case we halted in L2 */
13333 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
13335 if (likely(!vmx
->fail
)) {
13337 * TODO: SDM says that with acknowledge interrupt on
13338 * exit, bit 31 of the VM-exit interrupt information
13339 * (valid interrupt) is always set to 1 on
13340 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
13341 * need kvm_cpu_has_interrupt(). See the commit
13342 * message for details.
13344 if (nested_exit_intr_ack_set(vcpu
) &&
13345 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
13346 kvm_cpu_has_interrupt(vcpu
)) {
13347 int irq
= kvm_cpu_get_interrupt(vcpu
);
13349 vmcs12
->vm_exit_intr_info
= irq
|
13350 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
13353 if (exit_reason
!= -1)
13354 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
13355 vmcs12
->exit_qualification
,
13356 vmcs12
->idt_vectoring_info_field
,
13357 vmcs12
->vm_exit_intr_info
,
13358 vmcs12
->vm_exit_intr_error_code
,
13361 load_vmcs12_host_state(vcpu
, vmcs12
);
13367 * After an early L2 VM-entry failure, we're now back
13368 * in L1 which thinks it just finished a VMLAUNCH or
13369 * VMRESUME instruction, so we need to set the failure
13370 * flag and the VM-instruction error field of the VMCS
13373 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
13375 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
13378 * The emulated instruction was already skipped in
13379 * nested_vmx_run, but the updated RIP was never
13380 * written back to the vmcs01.
13382 skip_emulated_instruction(vcpu
);
13387 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
13389 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
13391 if (is_guest_mode(vcpu
)) {
13392 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
13393 nested_vmx_vmexit(vcpu
, -1, 0, 0);
13395 free_nested(to_vmx(vcpu
));
13399 * L1's failure to enter L2 is a subset of a normal exit, as explained in
13400 * 23.7 "VM-entry failures during or after loading guest state" (this also
13401 * lists the acceptable exit-reason and exit-qualification parameters).
13402 * It should only be called before L2 actually succeeded to run, and when
13403 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
13405 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
13406 struct vmcs12
*vmcs12
,
13407 u32 reason
, unsigned long qualification
)
13409 load_vmcs12_host_state(vcpu
, vmcs12
);
13410 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
13411 vmcs12
->exit_qualification
= qualification
;
13412 nested_vmx_succeed(vcpu
);
13413 if (enable_shadow_vmcs
)
13414 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
13417 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
13418 struct x86_instruction_info
*info
,
13419 enum x86_intercept_stage stage
)
13421 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
13422 struct x86_emulate_ctxt
*ctxt
= &vcpu
->arch
.emulate_ctxt
;
13425 * RDPID causes #UD if disabled through secondary execution controls.
13426 * Because it is marked as EmulateOnUD, we need to intercept it here.
13428 if (info
->intercept
== x86_intercept_rdtscp
&&
13429 !nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDTSCP
)) {
13430 ctxt
->exception
.vector
= UD_VECTOR
;
13431 ctxt
->exception
.error_code_valid
= false;
13432 return X86EMUL_PROPAGATE_FAULT
;
13435 /* TODO: check more intercepts... */
13436 return X86EMUL_CONTINUE
;
13439 #ifdef CONFIG_X86_64
13440 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
13441 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
13442 u64 divisor
, u64
*result
)
13444 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
13446 /* To avoid the overflow on divq */
13447 if (high
>= divisor
)
13450 /* Low hold the result, high hold rem which is discarded */
13451 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
13452 "rm" (divisor
), "0" (low
), "1" (high
));
13458 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
13460 struct vcpu_vmx
*vmx
;
13461 u64 tscl
, guest_tscl
, delta_tsc
, lapic_timer_advance_cycles
;
13463 if (kvm_mwait_in_guest(vcpu
->kvm
))
13464 return -EOPNOTSUPP
;
13466 vmx
= to_vmx(vcpu
);
13468 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
13469 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
13470 lapic_timer_advance_cycles
= nsec_to_cycles(vcpu
, lapic_timer_advance_ns
);
13472 if (delta_tsc
> lapic_timer_advance_cycles
)
13473 delta_tsc
-= lapic_timer_advance_cycles
;
13477 /* Convert to host delta tsc if tsc scaling is enabled */
13478 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
13479 u64_shl_div_u64(delta_tsc
,
13480 kvm_tsc_scaling_ratio_frac_bits
,
13481 vcpu
->arch
.tsc_scaling_ratio
,
13486 * If the delta tsc can't fit in the 32 bit after the multi shift,
13487 * we can't use the preemption timer.
13488 * It's possible that it fits on later vmentries, but checking
13489 * on every vmentry is costly so we just use an hrtimer.
13491 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
13494 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
13495 return delta_tsc
== 0;
13498 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
13500 to_vmx(vcpu
)->hv_deadline_tsc
= -1;
13504 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
13506 if (!kvm_pause_in_guest(vcpu
->kvm
))
13507 shrink_ple_window(vcpu
);
13510 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
13511 struct kvm_memory_slot
*slot
)
13513 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
13514 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
13517 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
13518 struct kvm_memory_slot
*slot
)
13520 kvm_mmu_slot_set_dirty(kvm
, slot
);
13523 static void vmx_flush_log_dirty(struct kvm
*kvm
)
13525 kvm_flush_pml_buffers(kvm
);
13528 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
13530 struct vmcs12
*vmcs12
;
13531 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
13533 struct page
*page
= NULL
;
13536 if (is_guest_mode(vcpu
)) {
13537 WARN_ON_ONCE(vmx
->nested
.pml_full
);
13540 * Check if PML is enabled for the nested guest.
13541 * Whether eptp bit 6 is set is already checked
13542 * as part of A/D emulation.
13544 vmcs12
= get_vmcs12(vcpu
);
13545 if (!nested_cpu_has_pml(vmcs12
))
13548 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
13549 vmx
->nested
.pml_full
= true;
13553 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
13555 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
13556 if (is_error_page(page
))
13559 pml_address
= kmap(page
);
13560 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
13562 kvm_release_page_clean(page
);
13568 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
13569 struct kvm_memory_slot
*memslot
,
13570 gfn_t offset
, unsigned long mask
)
13572 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
13575 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
13577 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
13578 struct pi_desc old
, new;
13582 old
.control
= new.control
= pi_desc
->control
;
13583 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
13584 "Wakeup handler not enabled while the VCPU is blocked\n");
13586 dest
= cpu_physical_id(vcpu
->cpu
);
13588 if (x2apic_enabled())
13591 new.ndst
= (dest
<< 8) & 0xFF00;
13593 /* set 'NV' to 'notification vector' */
13594 new.nv
= POSTED_INTR_VECTOR
;
13595 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
13596 new.control
) != old
.control
);
13598 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
13599 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
13600 list_del(&vcpu
->blocked_vcpu_list
);
13601 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
13602 vcpu
->pre_pcpu
= -1;
13607 * This routine does the following things for vCPU which is going
13608 * to be blocked if VT-d PI is enabled.
13609 * - Store the vCPU to the wakeup list, so when interrupts happen
13610 * we can find the right vCPU to wake up.
13611 * - Change the Posted-interrupt descriptor as below:
13612 * 'NDST' <-- vcpu->pre_pcpu
13613 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
13614 * - If 'ON' is set during this process, which means at least one
13615 * interrupt is posted for this vCPU, we cannot block it, in
13616 * this case, return 1, otherwise, return 0.
13619 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
13622 struct pi_desc old
, new;
13623 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
13625 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
13626 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
13627 !kvm_vcpu_apicv_active(vcpu
))
13630 WARN_ON(irqs_disabled());
13631 local_irq_disable();
13632 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
13633 vcpu
->pre_pcpu
= vcpu
->cpu
;
13634 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
13635 list_add_tail(&vcpu
->blocked_vcpu_list
,
13636 &per_cpu(blocked_vcpu_on_cpu
,
13638 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
13642 old
.control
= new.control
= pi_desc
->control
;
13644 WARN((pi_desc
->sn
== 1),
13645 "Warning: SN field of posted-interrupts "
13646 "is set before blocking\n");
13649 * Since vCPU can be preempted during this process,
13650 * vcpu->cpu could be different with pre_pcpu, we
13651 * need to set pre_pcpu as the destination of wakeup
13652 * notification event, then we can find the right vCPU
13653 * to wakeup in wakeup handler if interrupts happen
13654 * when the vCPU is in blocked state.
13656 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
13658 if (x2apic_enabled())
13661 new.ndst
= (dest
<< 8) & 0xFF00;
13663 /* set 'NV' to 'wakeup vector' */
13664 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
13665 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
13666 new.control
) != old
.control
);
13668 /* We should not block the vCPU if an interrupt is posted for it. */
13669 if (pi_test_on(pi_desc
) == 1)
13670 __pi_post_block(vcpu
);
13672 local_irq_enable();
13673 return (vcpu
->pre_pcpu
== -1);
13676 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
13678 if (pi_pre_block(vcpu
))
13681 if (kvm_lapic_hv_timer_in_use(vcpu
))
13682 kvm_lapic_switch_to_sw_timer(vcpu
);
13687 static void pi_post_block(struct kvm_vcpu
*vcpu
)
13689 if (vcpu
->pre_pcpu
== -1)
13692 WARN_ON(irqs_disabled());
13693 local_irq_disable();
13694 __pi_post_block(vcpu
);
13695 local_irq_enable();
13698 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
13700 if (kvm_x86_ops
->set_hv_timer
)
13701 kvm_lapic_switch_to_hv_timer(vcpu
);
13703 pi_post_block(vcpu
);
13707 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
13710 * @host_irq: host irq of the interrupt
13711 * @guest_irq: gsi of the interrupt
13712 * @set: set or unset PI
13713 * returns 0 on success, < 0 on failure
13715 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
13716 uint32_t guest_irq
, bool set
)
13718 struct kvm_kernel_irq_routing_entry
*e
;
13719 struct kvm_irq_routing_table
*irq_rt
;
13720 struct kvm_lapic_irq irq
;
13721 struct kvm_vcpu
*vcpu
;
13722 struct vcpu_data vcpu_info
;
13725 if (!kvm_arch_has_assigned_device(kvm
) ||
13726 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
13727 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
13730 idx
= srcu_read_lock(&kvm
->irq_srcu
);
13731 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
13732 if (guest_irq
>= irq_rt
->nr_rt_entries
||
13733 hlist_empty(&irq_rt
->map
[guest_irq
])) {
13734 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
13735 guest_irq
, irq_rt
->nr_rt_entries
);
13739 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
13740 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
13743 * VT-d PI cannot support posting multicast/broadcast
13744 * interrupts to a vCPU, we still use interrupt remapping
13745 * for these kind of interrupts.
13747 * For lowest-priority interrupts, we only support
13748 * those with single CPU as the destination, e.g. user
13749 * configures the interrupts via /proc/irq or uses
13750 * irqbalance to make the interrupts single-CPU.
13752 * We will support full lowest-priority interrupt later.
13755 kvm_set_msi_irq(kvm
, e
, &irq
);
13756 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
13758 * Make sure the IRTE is in remapped mode if
13759 * we don't handle it in posted mode.
13761 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
13764 "failed to back to remapped mode, irq: %u\n",
13772 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
13773 vcpu_info
.vector
= irq
.vector
;
13775 trace_kvm_pi_irte_update(host_irq
, vcpu
->vcpu_id
, e
->gsi
,
13776 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
13779 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
13781 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
13784 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
13792 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
13796 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
13798 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
13799 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
13800 FEATURE_CONTROL_LMCE
;
13802 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
13803 ~FEATURE_CONTROL_LMCE
;
13806 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
13808 /* we need a nested vmexit to enter SMM, postpone if run is pending */
13809 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
13814 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
13816 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
13818 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
13819 if (vmx
->nested
.smm
.guest_mode
)
13820 nested_vmx_vmexit(vcpu
, -1, 0, 0);
13822 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
13823 vmx
->nested
.vmxon
= false;
13824 vmx_clear_hlt(vcpu
);
13828 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
13830 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
13833 if (vmx
->nested
.smm
.vmxon
) {
13834 vmx
->nested
.vmxon
= true;
13835 vmx
->nested
.smm
.vmxon
= false;
13838 if (vmx
->nested
.smm
.guest_mode
) {
13839 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
13840 ret
= enter_vmx_non_root_mode(vcpu
, NULL
);
13841 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
13845 vmx
->nested
.smm
.guest_mode
= false;
13850 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
13855 static int vmx_get_nested_state(struct kvm_vcpu
*vcpu
,
13856 struct kvm_nested_state __user
*user_kvm_nested_state
,
13857 u32 user_data_size
)
13859 struct vcpu_vmx
*vmx
;
13860 struct vmcs12
*vmcs12
;
13861 struct kvm_nested_state kvm_state
= {
13864 .size
= sizeof(kvm_state
),
13865 .vmx
.vmxon_pa
= -1ull,
13866 .vmx
.vmcs_pa
= -1ull,
13870 return kvm_state
.size
+ 2 * VMCS12_SIZE
;
13872 vmx
= to_vmx(vcpu
);
13873 vmcs12
= get_vmcs12(vcpu
);
13874 if (nested_vmx_allowed(vcpu
) &&
13875 (vmx
->nested
.vmxon
|| vmx
->nested
.smm
.vmxon
)) {
13876 kvm_state
.vmx
.vmxon_pa
= vmx
->nested
.vmxon_ptr
;
13877 kvm_state
.vmx
.vmcs_pa
= vmx
->nested
.current_vmptr
;
13879 if (vmx
->nested
.current_vmptr
!= -1ull) {
13880 kvm_state
.size
+= VMCS12_SIZE
;
13882 if (is_guest_mode(vcpu
) &&
13883 nested_cpu_has_shadow_vmcs(vmcs12
) &&
13884 vmcs12
->vmcs_link_pointer
!= -1ull)
13885 kvm_state
.size
+= VMCS12_SIZE
;
13888 if (vmx
->nested
.smm
.vmxon
)
13889 kvm_state
.vmx
.smm
.flags
|= KVM_STATE_NESTED_SMM_VMXON
;
13891 if (vmx
->nested
.smm
.guest_mode
)
13892 kvm_state
.vmx
.smm
.flags
|= KVM_STATE_NESTED_SMM_GUEST_MODE
;
13894 if (is_guest_mode(vcpu
)) {
13895 kvm_state
.flags
|= KVM_STATE_NESTED_GUEST_MODE
;
13897 if (vmx
->nested
.nested_run_pending
)
13898 kvm_state
.flags
|= KVM_STATE_NESTED_RUN_PENDING
;
13902 if (user_data_size
< kvm_state
.size
)
13905 if (copy_to_user(user_kvm_nested_state
, &kvm_state
, sizeof(kvm_state
)))
13908 if (vmx
->nested
.current_vmptr
== -1ull)
13912 * When running L2, the authoritative vmcs12 state is in the
13913 * vmcs02. When running L1, the authoritative vmcs12 state is
13914 * in the shadow vmcs linked to vmcs01, unless
13915 * sync_shadow_vmcs is set, in which case, the authoritative
13916 * vmcs12 state is in the vmcs12 already.
13918 if (is_guest_mode(vcpu
))
13919 sync_vmcs12(vcpu
, vmcs12
);
13920 else if (enable_shadow_vmcs
&& !vmx
->nested
.sync_shadow_vmcs
)
13921 copy_shadow_to_vmcs12(vmx
);
13923 if (copy_to_user(user_kvm_nested_state
->data
, vmcs12
, sizeof(*vmcs12
)))
13926 if (nested_cpu_has_shadow_vmcs(vmcs12
) &&
13927 vmcs12
->vmcs_link_pointer
!= -1ull) {
13928 if (copy_to_user(user_kvm_nested_state
->data
+ VMCS12_SIZE
,
13929 get_shadow_vmcs12(vcpu
), sizeof(*vmcs12
)))
13934 return kvm_state
.size
;
13937 static int vmx_set_nested_state(struct kvm_vcpu
*vcpu
,
13938 struct kvm_nested_state __user
*user_kvm_nested_state
,
13939 struct kvm_nested_state
*kvm_state
)
13941 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
13942 struct vmcs12
*vmcs12
;
13946 if (kvm_state
->format
!= 0)
13949 if (!nested_vmx_allowed(vcpu
))
13950 return kvm_state
->vmx
.vmxon_pa
== -1ull ? 0 : -EINVAL
;
13952 if (kvm_state
->vmx
.vmxon_pa
== -1ull) {
13953 if (kvm_state
->vmx
.smm
.flags
)
13956 if (kvm_state
->vmx
.vmcs_pa
!= -1ull)
13959 vmx_leave_nested(vcpu
);
13963 if (!page_address_valid(vcpu
, kvm_state
->vmx
.vmxon_pa
))
13966 if (kvm_state
->size
< sizeof(kvm_state
) + sizeof(*vmcs12
))
13969 if (kvm_state
->vmx
.vmcs_pa
== kvm_state
->vmx
.vmxon_pa
||
13970 !page_address_valid(vcpu
, kvm_state
->vmx
.vmcs_pa
))
13973 if ((kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
) &&
13974 (kvm_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
))
13977 if (kvm_state
->vmx
.smm
.flags
&
13978 ~(KVM_STATE_NESTED_SMM_GUEST_MODE
| KVM_STATE_NESTED_SMM_VMXON
))
13982 * SMM temporarily disables VMX, so we cannot be in guest mode,
13983 * nor can VMLAUNCH/VMRESUME be pending. Outside SMM, SMM flags
13986 if (is_smm(vcpu
) ? kvm_state
->flags
: kvm_state
->vmx
.smm
.flags
)
13989 if ((kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
) &&
13990 !(kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_VMXON
))
13993 vmx_leave_nested(vcpu
);
13994 if (kvm_state
->vmx
.vmxon_pa
== -1ull)
13997 vmx
->nested
.vmxon_ptr
= kvm_state
->vmx
.vmxon_pa
;
13998 ret
= enter_vmx_operation(vcpu
);
14002 set_current_vmptr(vmx
, kvm_state
->vmx
.vmcs_pa
);
14004 if (kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_VMXON
) {
14005 vmx
->nested
.smm
.vmxon
= true;
14006 vmx
->nested
.vmxon
= false;
14008 if (kvm_state
->vmx
.smm
.flags
& KVM_STATE_NESTED_SMM_GUEST_MODE
)
14009 vmx
->nested
.smm
.guest_mode
= true;
14012 vmcs12
= get_vmcs12(vcpu
);
14013 if (copy_from_user(vmcs12
, user_kvm_nested_state
->data
, sizeof(*vmcs12
)))
14016 if (vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
)
14019 if (!(kvm_state
->flags
& KVM_STATE_NESTED_GUEST_MODE
))
14022 vmx
->nested
.nested_run_pending
=
14023 !!(kvm_state
->flags
& KVM_STATE_NESTED_RUN_PENDING
);
14025 if (nested_cpu_has_shadow_vmcs(vmcs12
) &&
14026 vmcs12
->vmcs_link_pointer
!= -1ull) {
14027 struct vmcs12
*shadow_vmcs12
= get_shadow_vmcs12(vcpu
);
14028 if (kvm_state
->size
< sizeof(kvm_state
) + 2 * sizeof(*vmcs12
))
14031 if (copy_from_user(shadow_vmcs12
,
14032 user_kvm_nested_state
->data
+ VMCS12_SIZE
,
14036 if (shadow_vmcs12
->hdr
.revision_id
!= VMCS12_REVISION
||
14037 !shadow_vmcs12
->hdr
.shadow_vmcs
)
14041 if (check_vmentry_prereqs(vcpu
, vmcs12
) ||
14042 check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
))
14045 vmx
->nested
.dirty_vmcs12
= true;
14046 ret
= enter_vmx_non_root_mode(vcpu
, NULL
);
14053 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
14054 .cpu_has_kvm_support
= cpu_has_kvm_support
,
14055 .disabled_by_bios
= vmx_disabled_by_bios
,
14056 .hardware_setup
= hardware_setup
,
14057 .hardware_unsetup
= hardware_unsetup
,
14058 .check_processor_compatibility
= vmx_check_processor_compat
,
14059 .hardware_enable
= hardware_enable
,
14060 .hardware_disable
= hardware_disable
,
14061 .cpu_has_accelerated_tpr
= report_flexpriority
,
14062 .has_emulated_msr
= vmx_has_emulated_msr
,
14064 .vm_init
= vmx_vm_init
,
14065 .vm_alloc
= vmx_vm_alloc
,
14066 .vm_free
= vmx_vm_free
,
14068 .vcpu_create
= vmx_create_vcpu
,
14069 .vcpu_free
= vmx_free_vcpu
,
14070 .vcpu_reset
= vmx_vcpu_reset
,
14072 .prepare_guest_switch
= vmx_prepare_switch_to_guest
,
14073 .vcpu_load
= vmx_vcpu_load
,
14074 .vcpu_put
= vmx_vcpu_put
,
14076 .update_bp_intercept
= update_exception_bitmap
,
14077 .get_msr_feature
= vmx_get_msr_feature
,
14078 .get_msr
= vmx_get_msr
,
14079 .set_msr
= vmx_set_msr
,
14080 .get_segment_base
= vmx_get_segment_base
,
14081 .get_segment
= vmx_get_segment
,
14082 .set_segment
= vmx_set_segment
,
14083 .get_cpl
= vmx_get_cpl
,
14084 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
14085 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
14086 .decache_cr3
= vmx_decache_cr3
,
14087 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
14088 .set_cr0
= vmx_set_cr0
,
14089 .set_cr3
= vmx_set_cr3
,
14090 .set_cr4
= vmx_set_cr4
,
14091 .set_efer
= vmx_set_efer
,
14092 .get_idt
= vmx_get_idt
,
14093 .set_idt
= vmx_set_idt
,
14094 .get_gdt
= vmx_get_gdt
,
14095 .set_gdt
= vmx_set_gdt
,
14096 .get_dr6
= vmx_get_dr6
,
14097 .set_dr6
= vmx_set_dr6
,
14098 .set_dr7
= vmx_set_dr7
,
14099 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
14100 .cache_reg
= vmx_cache_reg
,
14101 .get_rflags
= vmx_get_rflags
,
14102 .set_rflags
= vmx_set_rflags
,
14104 .tlb_flush
= vmx_flush_tlb
,
14105 .tlb_flush_gva
= vmx_flush_tlb_gva
,
14107 .run
= vmx_vcpu_run
,
14108 .handle_exit
= vmx_handle_exit
,
14109 .skip_emulated_instruction
= skip_emulated_instruction
,
14110 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
14111 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
14112 .patch_hypercall
= vmx_patch_hypercall
,
14113 .set_irq
= vmx_inject_irq
,
14114 .set_nmi
= vmx_inject_nmi
,
14115 .queue_exception
= vmx_queue_exception
,
14116 .cancel_injection
= vmx_cancel_injection
,
14117 .interrupt_allowed
= vmx_interrupt_allowed
,
14118 .nmi_allowed
= vmx_nmi_allowed
,
14119 .get_nmi_mask
= vmx_get_nmi_mask
,
14120 .set_nmi_mask
= vmx_set_nmi_mask
,
14121 .enable_nmi_window
= enable_nmi_window
,
14122 .enable_irq_window
= enable_irq_window
,
14123 .update_cr8_intercept
= update_cr8_intercept
,
14124 .set_virtual_apic_mode
= vmx_set_virtual_apic_mode
,
14125 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
14126 .get_enable_apicv
= vmx_get_enable_apicv
,
14127 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
14128 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
14129 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
14130 .hwapic_irr_update
= vmx_hwapic_irr_update
,
14131 .hwapic_isr_update
= vmx_hwapic_isr_update
,
14132 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
14133 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
14135 .set_tss_addr
= vmx_set_tss_addr
,
14136 .set_identity_map_addr
= vmx_set_identity_map_addr
,
14137 .get_tdp_level
= get_ept_level
,
14138 .get_mt_mask
= vmx_get_mt_mask
,
14140 .get_exit_info
= vmx_get_exit_info
,
14142 .get_lpage_level
= vmx_get_lpage_level
,
14144 .cpuid_update
= vmx_cpuid_update
,
14146 .rdtscp_supported
= vmx_rdtscp_supported
,
14147 .invpcid_supported
= vmx_invpcid_supported
,
14149 .set_supported_cpuid
= vmx_set_supported_cpuid
,
14151 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
14153 .read_l1_tsc_offset
= vmx_read_l1_tsc_offset
,
14154 .write_tsc_offset
= vmx_write_tsc_offset
,
14156 .set_tdp_cr3
= vmx_set_cr3
,
14158 .check_intercept
= vmx_check_intercept
,
14159 .handle_external_intr
= vmx_handle_external_intr
,
14160 .mpx_supported
= vmx_mpx_supported
,
14161 .xsaves_supported
= vmx_xsaves_supported
,
14162 .umip_emulated
= vmx_umip_emulated
,
14164 .check_nested_events
= vmx_check_nested_events
,
14165 .request_immediate_exit
= vmx_request_immediate_exit
,
14167 .sched_in
= vmx_sched_in
,
14169 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
14170 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
14171 .flush_log_dirty
= vmx_flush_log_dirty
,
14172 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
14173 .write_log_dirty
= vmx_write_pml_buffer
,
14175 .pre_block
= vmx_pre_block
,
14176 .post_block
= vmx_post_block
,
14178 .pmu_ops
= &intel_pmu_ops
,
14180 .update_pi_irte
= vmx_update_pi_irte
,
14182 #ifdef CONFIG_X86_64
14183 .set_hv_timer
= vmx_set_hv_timer
,
14184 .cancel_hv_timer
= vmx_cancel_hv_timer
,
14187 .setup_mce
= vmx_setup_mce
,
14189 .get_nested_state
= vmx_get_nested_state
,
14190 .set_nested_state
= vmx_set_nested_state
,
14191 .get_vmcs12_pages
= nested_get_vmcs12_pages
,
14193 .smi_allowed
= vmx_smi_allowed
,
14194 .pre_enter_smm
= vmx_pre_enter_smm
,
14195 .pre_leave_smm
= vmx_pre_leave_smm
,
14196 .enable_smi_window
= enable_smi_window
,
14199 static void vmx_cleanup_l1d_flush(void)
14201 if (vmx_l1d_flush_pages
) {
14202 free_pages((unsigned long)vmx_l1d_flush_pages
, L1D_CACHE_ORDER
);
14203 vmx_l1d_flush_pages
= NULL
;
14205 /* Restore state so sysfs ignores VMX */
14206 l1tf_vmx_mitigation
= VMENTER_L1D_FLUSH_AUTO
;
14209 static void vmx_exit(void)
14211 #ifdef CONFIG_KEXEC_CORE
14212 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
14218 #if IS_ENABLED(CONFIG_HYPERV)
14219 if (static_branch_unlikely(&enable_evmcs
)) {
14221 struct hv_vp_assist_page
*vp_ap
;
14223 * Reset everything to support using non-enlightened VMCS
14224 * access later (e.g. when we reload the module with
14225 * enlightened_vmcs=0)
14227 for_each_online_cpu(cpu
) {
14228 vp_ap
= hv_get_vp_assist_page(cpu
);
14233 vp_ap
->current_nested_vmcs
= 0;
14234 vp_ap
->enlighten_vmentry
= 0;
14237 static_branch_disable(&enable_evmcs
);
14240 vmx_cleanup_l1d_flush();
14242 module_exit(vmx_exit
);
14244 static int __init
vmx_init(void)
14248 #if IS_ENABLED(CONFIG_HYPERV)
14250 * Enlightened VMCS usage should be recommended and the host needs
14251 * to support eVMCS v1 or above. We can also disable eVMCS support
14252 * with module parameter.
14254 if (enlightened_vmcs
&&
14255 ms_hyperv
.hints
& HV_X64_ENLIGHTENED_VMCS_RECOMMENDED
&&
14256 (ms_hyperv
.nested_features
& HV_X64_ENLIGHTENED_VMCS_VERSION
) >=
14257 KVM_EVMCS_VERSION
) {
14260 /* Check that we have assist pages on all online CPUs */
14261 for_each_online_cpu(cpu
) {
14262 if (!hv_get_vp_assist_page(cpu
)) {
14263 enlightened_vmcs
= false;
14268 if (enlightened_vmcs
) {
14269 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
14270 static_branch_enable(&enable_evmcs
);
14273 enlightened_vmcs
= false;
14277 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
14278 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
14283 * Must be called after kvm_init() so enable_ept is properly set
14284 * up. Hand the parameter mitigation value in which was stored in
14285 * the pre module init parser. If no parameter was given, it will
14286 * contain 'auto' which will be turned into the default 'cond'
14289 if (boot_cpu_has(X86_BUG_L1TF
)) {
14290 r
= vmx_setup_l1d_flush(vmentry_l1d_flush_param
);
14297 #ifdef CONFIG_KEXEC_CORE
14298 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
14299 crash_vmclear_local_loaded_vmcss
);
14301 vmx_check_vmcs12_offsets();
14305 module_init(vmx_init
);