2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv_reg_vid
;
90 * If nested=1, nested virtualization is supported, i.e., guests may use
91 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
92 * use VMX instructions.
94 static bool __read_mostly nested
= 0;
95 module_param(nested
, bool, S_IRUGO
);
97 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
99 #define KVM_VM_CR0_ALWAYS_ON \
100 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
101 #define KVM_CR4_GUEST_OWNED_BITS \
102 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
103 | X86_CR4_OSXMMEXCPT)
105 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
106 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
111 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
112 * ple_gap: upper bound on the amount of time between two successive
113 * executions of PAUSE in a loop. Also indicate if ple enabled.
114 * According to test, this time is usually smaller than 128 cycles.
115 * ple_window: upper bound on the amount of time a guest is allowed to execute
116 * in a PAUSE loop. Tests indicate that most spinlocks are held for
117 * less than 2^12 cycles
118 * Time is measured based on a counter that runs at the same rate as the TSC,
119 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 #define KVM_VMX_DEFAULT_PLE_GAP 128
122 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
123 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
124 module_param(ple_gap
, int, S_IRUGO
);
126 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
127 module_param(ple_window
, int, S_IRUGO
);
129 extern const ulong vmx_return
;
131 #define NR_AUTOLOAD_MSRS 8
132 #define VMCS02_POOL_SIZE 1
141 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
142 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
143 * loaded on this CPU (so we can clear them if the CPU goes down).
149 struct list_head loaded_vmcss_on_cpu_link
;
152 struct shared_msr_entry
{
159 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
160 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
161 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
162 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
163 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
164 * More than one of these structures may exist, if L1 runs multiple L2 guests.
165 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
166 * underlying hardware which will be used to run L2.
167 * This structure is packed to ensure that its layout is identical across
168 * machines (necessary for live migration).
169 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 typedef u64 natural_width
;
172 struct __packed vmcs12
{
173 /* According to the Intel spec, a VMCS region must start with the
174 * following two fields. Then follow implementation-specific data.
179 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
180 u32 padding
[7]; /* room for future expansion */
185 u64 vm_exit_msr_store_addr
;
186 u64 vm_exit_msr_load_addr
;
187 u64 vm_entry_msr_load_addr
;
189 u64 virtual_apic_page_addr
;
190 u64 apic_access_addr
;
192 u64 guest_physical_address
;
193 u64 vmcs_link_pointer
;
194 u64 guest_ia32_debugctl
;
197 u64 guest_ia32_perf_global_ctrl
;
204 u64 host_ia32_perf_global_ctrl
;
205 u64 padding64
[8]; /* room for future expansion */
207 * To allow migration of L1 (complete with its L2 guests) between
208 * machines of different natural widths (32 or 64 bit), we cannot have
209 * unsigned long fields with no explict size. We use u64 (aliased
210 * natural_width) instead. Luckily, x86 is little-endian.
212 natural_width cr0_guest_host_mask
;
213 natural_width cr4_guest_host_mask
;
214 natural_width cr0_read_shadow
;
215 natural_width cr4_read_shadow
;
216 natural_width cr3_target_value0
;
217 natural_width cr3_target_value1
;
218 natural_width cr3_target_value2
;
219 natural_width cr3_target_value3
;
220 natural_width exit_qualification
;
221 natural_width guest_linear_address
;
222 natural_width guest_cr0
;
223 natural_width guest_cr3
;
224 natural_width guest_cr4
;
225 natural_width guest_es_base
;
226 natural_width guest_cs_base
;
227 natural_width guest_ss_base
;
228 natural_width guest_ds_base
;
229 natural_width guest_fs_base
;
230 natural_width guest_gs_base
;
231 natural_width guest_ldtr_base
;
232 natural_width guest_tr_base
;
233 natural_width guest_gdtr_base
;
234 natural_width guest_idtr_base
;
235 natural_width guest_dr7
;
236 natural_width guest_rsp
;
237 natural_width guest_rip
;
238 natural_width guest_rflags
;
239 natural_width guest_pending_dbg_exceptions
;
240 natural_width guest_sysenter_esp
;
241 natural_width guest_sysenter_eip
;
242 natural_width host_cr0
;
243 natural_width host_cr3
;
244 natural_width host_cr4
;
245 natural_width host_fs_base
;
246 natural_width host_gs_base
;
247 natural_width host_tr_base
;
248 natural_width host_gdtr_base
;
249 natural_width host_idtr_base
;
250 natural_width host_ia32_sysenter_esp
;
251 natural_width host_ia32_sysenter_eip
;
252 natural_width host_rsp
;
253 natural_width host_rip
;
254 natural_width paddingl
[8]; /* room for future expansion */
255 u32 pin_based_vm_exec_control
;
256 u32 cpu_based_vm_exec_control
;
257 u32 exception_bitmap
;
258 u32 page_fault_error_code_mask
;
259 u32 page_fault_error_code_match
;
260 u32 cr3_target_count
;
261 u32 vm_exit_controls
;
262 u32 vm_exit_msr_store_count
;
263 u32 vm_exit_msr_load_count
;
264 u32 vm_entry_controls
;
265 u32 vm_entry_msr_load_count
;
266 u32 vm_entry_intr_info_field
;
267 u32 vm_entry_exception_error_code
;
268 u32 vm_entry_instruction_len
;
270 u32 secondary_vm_exec_control
;
271 u32 vm_instruction_error
;
273 u32 vm_exit_intr_info
;
274 u32 vm_exit_intr_error_code
;
275 u32 idt_vectoring_info_field
;
276 u32 idt_vectoring_error_code
;
277 u32 vm_exit_instruction_len
;
278 u32 vmx_instruction_info
;
285 u32 guest_ldtr_limit
;
287 u32 guest_gdtr_limit
;
288 u32 guest_idtr_limit
;
289 u32 guest_es_ar_bytes
;
290 u32 guest_cs_ar_bytes
;
291 u32 guest_ss_ar_bytes
;
292 u32 guest_ds_ar_bytes
;
293 u32 guest_fs_ar_bytes
;
294 u32 guest_gs_ar_bytes
;
295 u32 guest_ldtr_ar_bytes
;
296 u32 guest_tr_ar_bytes
;
297 u32 guest_interruptibility_info
;
298 u32 guest_activity_state
;
299 u32 guest_sysenter_cs
;
300 u32 host_ia32_sysenter_cs
;
301 u32 vmx_preemption_timer_value
;
302 u32 padding32
[7]; /* room for future expansion */
303 u16 virtual_processor_id
;
304 u16 guest_es_selector
;
305 u16 guest_cs_selector
;
306 u16 guest_ss_selector
;
307 u16 guest_ds_selector
;
308 u16 guest_fs_selector
;
309 u16 guest_gs_selector
;
310 u16 guest_ldtr_selector
;
311 u16 guest_tr_selector
;
312 u16 host_es_selector
;
313 u16 host_cs_selector
;
314 u16 host_ss_selector
;
315 u16 host_ds_selector
;
316 u16 host_fs_selector
;
317 u16 host_gs_selector
;
318 u16 host_tr_selector
;
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 #define VMCS12_REVISION 0x11e57ed0
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
333 #define VMCS12_SIZE 0x1000
335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
337 struct list_head list
;
339 struct loaded_vmcs vmcs02
;
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
347 /* Has the level1 guest done vmxon? */
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 /* The host-usable pointer to the above */
353 struct page
*current_vmcs12_page
;
354 struct vmcs12
*current_vmcs12
;
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool
;
359 u64 vmcs01_tsc_offset
;
360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending
;
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
366 struct page
*apic_access_page
;
370 struct kvm_vcpu vcpu
;
371 unsigned long host_rsp
;
374 bool nmi_known_unmasked
;
376 u32 idt_vectoring_info
;
378 struct shared_msr_entry
*guest_msrs
;
382 u64 msr_host_kernel_gs_base
;
383 u64 msr_guest_kernel_gs_base
;
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
390 struct loaded_vmcs vmcs01
;
391 struct loaded_vmcs
*loaded_vmcs
;
392 bool __launched
; /* temporary, used in vmx_vcpu_run */
393 struct msr_autoload
{
395 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
396 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
400 u16 fs_sel
, gs_sel
, ldt_sel
;
404 int gs_ldt_reload_needed
;
405 int fs_reload_needed
;
410 struct kvm_segment segs
[8];
413 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
414 struct kvm_save_segment
{
422 bool emulation_required
;
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked
;
427 s64 vnmi_blocked_time
;
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested
;
436 enum segment_cache_field
{
445 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
447 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
455 static const unsigned short vmcs_field_to_offset_table
[] = {
456 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
457 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
458 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
459 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
460 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
461 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
462 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
463 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
464 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
465 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
466 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
467 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
468 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
469 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
470 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
471 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
472 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
473 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
474 FIELD64(MSR_BITMAP
, msr_bitmap
),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
478 FIELD64(TSC_OFFSET
, tsc_offset
),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
480 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
481 FIELD64(EPT_POINTER
, ept_pointer
),
482 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
483 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
484 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
485 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
486 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
488 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
489 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
490 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
491 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
492 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
493 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
497 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
500 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
501 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
502 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
504 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
509 FIELD(TPR_THRESHOLD
, tpr_threshold
),
510 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
511 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
512 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
513 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
514 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
515 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
516 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
517 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
518 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
519 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
520 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
521 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
522 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
523 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
524 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
525 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
526 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
527 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
528 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
529 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
530 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
531 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
532 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
533 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
534 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
535 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
536 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
538 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
539 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
540 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
541 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
542 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
543 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
544 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
545 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
546 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
547 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
548 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
549 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
550 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
551 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
552 FIELD(GUEST_CR0
, guest_cr0
),
553 FIELD(GUEST_CR3
, guest_cr3
),
554 FIELD(GUEST_CR4
, guest_cr4
),
555 FIELD(GUEST_ES_BASE
, guest_es_base
),
556 FIELD(GUEST_CS_BASE
, guest_cs_base
),
557 FIELD(GUEST_SS_BASE
, guest_ss_base
),
558 FIELD(GUEST_DS_BASE
, guest_ds_base
),
559 FIELD(GUEST_FS_BASE
, guest_fs_base
),
560 FIELD(GUEST_GS_BASE
, guest_gs_base
),
561 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
562 FIELD(GUEST_TR_BASE
, guest_tr_base
),
563 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
564 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
565 FIELD(GUEST_DR7
, guest_dr7
),
566 FIELD(GUEST_RSP
, guest_rsp
),
567 FIELD(GUEST_RIP
, guest_rip
),
568 FIELD(GUEST_RFLAGS
, guest_rflags
),
569 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
570 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
571 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
572 FIELD(HOST_CR0
, host_cr0
),
573 FIELD(HOST_CR3
, host_cr3
),
574 FIELD(HOST_CR4
, host_cr4
),
575 FIELD(HOST_FS_BASE
, host_fs_base
),
576 FIELD(HOST_GS_BASE
, host_gs_base
),
577 FIELD(HOST_TR_BASE
, host_tr_base
),
578 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
579 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
580 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
581 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
582 FIELD(HOST_RSP
, host_rsp
),
583 FIELD(HOST_RIP
, host_rip
),
585 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
587 static inline short vmcs_field_to_offset(unsigned long field
)
589 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
591 return vmcs_field_to_offset_table
[field
];
594 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
596 return to_vmx(vcpu
)->nested
.current_vmcs12
;
599 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
601 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
602 if (is_error_page(page
))
608 static void nested_release_page(struct page
*page
)
610 kvm_release_page_dirty(page
);
613 static void nested_release_page_clean(struct page
*page
)
615 kvm_release_page_clean(page
);
618 static u64
construct_eptp(unsigned long root_hpa
);
619 static void kvm_cpu_vmxon(u64 addr
);
620 static void kvm_cpu_vmxoff(void);
621 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
622 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
623 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
624 struct kvm_segment
*var
, int seg
);
625 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
626 struct kvm_segment
*var
, int seg
);
627 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
628 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
630 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
631 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
633 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
634 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
636 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
637 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
639 static unsigned long *vmx_io_bitmap_a
;
640 static unsigned long *vmx_io_bitmap_b
;
641 static unsigned long *vmx_msr_bitmap_legacy
;
642 static unsigned long *vmx_msr_bitmap_longmode
;
643 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
644 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
646 static bool cpu_has_load_ia32_efer
;
647 static bool cpu_has_load_perf_global_ctrl
;
649 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
650 static DEFINE_SPINLOCK(vmx_vpid_lock
);
652 static struct vmcs_config
{
656 u32 pin_based_exec_ctrl
;
657 u32 cpu_based_exec_ctrl
;
658 u32 cpu_based_2nd_exec_ctrl
;
663 static struct vmx_capability
{
668 #define VMX_SEGMENT_FIELD(seg) \
669 [VCPU_SREG_##seg] = { \
670 .selector = GUEST_##seg##_SELECTOR, \
671 .base = GUEST_##seg##_BASE, \
672 .limit = GUEST_##seg##_LIMIT, \
673 .ar_bytes = GUEST_##seg##_AR_BYTES, \
676 static const struct kvm_vmx_segment_field
{
681 } kvm_vmx_segment_fields
[] = {
682 VMX_SEGMENT_FIELD(CS
),
683 VMX_SEGMENT_FIELD(DS
),
684 VMX_SEGMENT_FIELD(ES
),
685 VMX_SEGMENT_FIELD(FS
),
686 VMX_SEGMENT_FIELD(GS
),
687 VMX_SEGMENT_FIELD(SS
),
688 VMX_SEGMENT_FIELD(TR
),
689 VMX_SEGMENT_FIELD(LDTR
),
692 static u64 host_efer
;
694 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
697 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
698 * away by decrementing the array size.
700 static const u32 vmx_msr_index
[] = {
702 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
704 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
706 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
708 static inline bool is_page_fault(u32 intr_info
)
710 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
711 INTR_INFO_VALID_MASK
)) ==
712 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
715 static inline bool is_no_device(u32 intr_info
)
717 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
718 INTR_INFO_VALID_MASK
)) ==
719 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
722 static inline bool is_invalid_opcode(u32 intr_info
)
724 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
725 INTR_INFO_VALID_MASK
)) ==
726 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
729 static inline bool is_external_interrupt(u32 intr_info
)
731 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
732 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
735 static inline bool is_machine_check(u32 intr_info
)
737 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
738 INTR_INFO_VALID_MASK
)) ==
739 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
742 static inline bool cpu_has_vmx_msr_bitmap(void)
744 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
747 static inline bool cpu_has_vmx_tpr_shadow(void)
749 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
752 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
754 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
757 static inline bool cpu_has_secondary_exec_ctrls(void)
759 return vmcs_config
.cpu_based_exec_ctrl
&
760 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
763 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
765 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
766 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
769 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
771 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
772 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
775 static inline bool cpu_has_vmx_apic_register_virt(void)
777 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
778 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
781 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
783 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
784 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
787 static inline bool cpu_has_vmx_flexpriority(void)
789 return cpu_has_vmx_tpr_shadow() &&
790 cpu_has_vmx_virtualize_apic_accesses();
793 static inline bool cpu_has_vmx_ept_execute_only(void)
795 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
798 static inline bool cpu_has_vmx_eptp_uncacheable(void)
800 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
803 static inline bool cpu_has_vmx_eptp_writeback(void)
805 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
808 static inline bool cpu_has_vmx_ept_2m_page(void)
810 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
813 static inline bool cpu_has_vmx_ept_1g_page(void)
815 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
818 static inline bool cpu_has_vmx_ept_4levels(void)
820 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
823 static inline bool cpu_has_vmx_ept_ad_bits(void)
825 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
828 static inline bool cpu_has_vmx_invept_context(void)
830 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
833 static inline bool cpu_has_vmx_invept_global(void)
835 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
838 static inline bool cpu_has_vmx_invvpid_single(void)
840 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
843 static inline bool cpu_has_vmx_invvpid_global(void)
845 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
848 static inline bool cpu_has_vmx_ept(void)
850 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
851 SECONDARY_EXEC_ENABLE_EPT
;
854 static inline bool cpu_has_vmx_unrestricted_guest(void)
856 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
857 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
860 static inline bool cpu_has_vmx_ple(void)
862 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
863 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
866 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
868 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
871 static inline bool cpu_has_vmx_vpid(void)
873 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
874 SECONDARY_EXEC_ENABLE_VPID
;
877 static inline bool cpu_has_vmx_rdtscp(void)
879 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
880 SECONDARY_EXEC_RDTSCP
;
883 static inline bool cpu_has_vmx_invpcid(void)
885 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
886 SECONDARY_EXEC_ENABLE_INVPCID
;
889 static inline bool cpu_has_virtual_nmis(void)
891 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
894 static inline bool cpu_has_vmx_wbinvd_exit(void)
896 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
897 SECONDARY_EXEC_WBINVD_EXITING
;
900 static inline bool report_flexpriority(void)
902 return flexpriority_enabled
;
905 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
907 return vmcs12
->cpu_based_vm_exec_control
& bit
;
910 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
912 return (vmcs12
->cpu_based_vm_exec_control
&
913 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
914 (vmcs12
->secondary_vm_exec_control
& bit
);
917 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
918 struct kvm_vcpu
*vcpu
)
920 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
923 static inline bool is_exception(u32 intr_info
)
925 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
926 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
929 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
930 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
931 struct vmcs12
*vmcs12
,
932 u32 reason
, unsigned long qualification
);
934 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
938 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
939 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
944 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
950 } operand
= { vpid
, 0, gva
};
952 asm volatile (__ex(ASM_VMX_INVVPID
)
953 /* CF==1 or ZF==1 --> rc = -1 */
955 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
958 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
962 } operand
= {eptp
, gpa
};
964 asm volatile (__ex(ASM_VMX_INVEPT
)
965 /* CF==1 or ZF==1 --> rc = -1 */
966 "; ja 1f ; ud2 ; 1:\n"
967 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
970 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
974 i
= __find_msr_index(vmx
, msr
);
976 return &vmx
->guest_msrs
[i
];
980 static void vmcs_clear(struct vmcs
*vmcs
)
982 u64 phys_addr
= __pa(vmcs
);
985 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
986 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
989 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
993 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
995 vmcs_clear(loaded_vmcs
->vmcs
);
996 loaded_vmcs
->cpu
= -1;
997 loaded_vmcs
->launched
= 0;
1000 static void vmcs_load(struct vmcs
*vmcs
)
1002 u64 phys_addr
= __pa(vmcs
);
1005 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1006 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1009 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1015 * This bitmap is used to indicate whether the vmclear
1016 * operation is enabled on all cpus. All disabled by
1019 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1021 static inline void crash_enable_local_vmclear(int cpu
)
1023 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1026 static inline void crash_disable_local_vmclear(int cpu
)
1028 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1031 static inline int crash_local_vmclear_enabled(int cpu
)
1033 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1036 static void crash_vmclear_local_loaded_vmcss(void)
1038 int cpu
= raw_smp_processor_id();
1039 struct loaded_vmcs
*v
;
1041 if (!crash_local_vmclear_enabled(cpu
))
1044 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1045 loaded_vmcss_on_cpu_link
)
1046 vmcs_clear(v
->vmcs
);
1049 static inline void crash_enable_local_vmclear(int cpu
) { }
1050 static inline void crash_disable_local_vmclear(int cpu
) { }
1051 #endif /* CONFIG_KEXEC */
1053 static void __loaded_vmcs_clear(void *arg
)
1055 struct loaded_vmcs
*loaded_vmcs
= arg
;
1056 int cpu
= raw_smp_processor_id();
1058 if (loaded_vmcs
->cpu
!= cpu
)
1059 return; /* vcpu migration can race with cpu offline */
1060 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1061 per_cpu(current_vmcs
, cpu
) = NULL
;
1062 crash_disable_local_vmclear(cpu
);
1063 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1066 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1067 * is before setting loaded_vmcs->vcpu to -1 which is done in
1068 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1069 * then adds the vmcs into percpu list before it is deleted.
1073 loaded_vmcs_init(loaded_vmcs
);
1074 crash_enable_local_vmclear(cpu
);
1077 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1079 int cpu
= loaded_vmcs
->cpu
;
1082 smp_call_function_single(cpu
,
1083 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1086 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1091 if (cpu_has_vmx_invvpid_single())
1092 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1095 static inline void vpid_sync_vcpu_global(void)
1097 if (cpu_has_vmx_invvpid_global())
1098 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1101 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1103 if (cpu_has_vmx_invvpid_single())
1104 vpid_sync_vcpu_single(vmx
);
1106 vpid_sync_vcpu_global();
1109 static inline void ept_sync_global(void)
1111 if (cpu_has_vmx_invept_global())
1112 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1115 static inline void ept_sync_context(u64 eptp
)
1118 if (cpu_has_vmx_invept_context())
1119 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1125 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1127 unsigned long value
;
1129 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1130 : "=a"(value
) : "d"(field
) : "cc");
1134 static __always_inline u16
vmcs_read16(unsigned long field
)
1136 return vmcs_readl(field
);
1139 static __always_inline u32
vmcs_read32(unsigned long field
)
1141 return vmcs_readl(field
);
1144 static __always_inline u64
vmcs_read64(unsigned long field
)
1146 #ifdef CONFIG_X86_64
1147 return vmcs_readl(field
);
1149 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1153 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1155 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1156 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1160 static void vmcs_writel(unsigned long field
, unsigned long value
)
1164 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1165 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1166 if (unlikely(error
))
1167 vmwrite_error(field
, value
);
1170 static void vmcs_write16(unsigned long field
, u16 value
)
1172 vmcs_writel(field
, value
);
1175 static void vmcs_write32(unsigned long field
, u32 value
)
1177 vmcs_writel(field
, value
);
1180 static void vmcs_write64(unsigned long field
, u64 value
)
1182 vmcs_writel(field
, value
);
1183 #ifndef CONFIG_X86_64
1185 vmcs_writel(field
+1, value
>> 32);
1189 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1191 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1194 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1196 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1199 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1201 vmx
->segment_cache
.bitmask
= 0;
1204 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1208 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1210 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1211 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1212 vmx
->segment_cache
.bitmask
= 0;
1214 ret
= vmx
->segment_cache
.bitmask
& mask
;
1215 vmx
->segment_cache
.bitmask
|= mask
;
1219 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1221 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1223 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1224 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1228 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1230 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1232 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1233 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1237 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1239 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1241 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1242 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1246 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1248 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1250 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1251 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1255 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1259 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1260 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1261 if ((vcpu
->guest_debug
&
1262 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1263 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1264 eb
|= 1u << BP_VECTOR
;
1265 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1268 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1269 if (vcpu
->fpu_active
)
1270 eb
&= ~(1u << NM_VECTOR
);
1272 /* When we are running a nested L2 guest and L1 specified for it a
1273 * certain exception bitmap, we must trap the same exceptions and pass
1274 * them to L1. When running L2, we will only handle the exceptions
1275 * specified above if L1 did not want them.
1277 if (is_guest_mode(vcpu
))
1278 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1280 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1283 static void clear_atomic_switch_msr_special(unsigned long entry
,
1286 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1287 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1290 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1293 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1297 if (cpu_has_load_ia32_efer
) {
1298 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1299 VM_EXIT_LOAD_IA32_EFER
);
1303 case MSR_CORE_PERF_GLOBAL_CTRL
:
1304 if (cpu_has_load_perf_global_ctrl
) {
1305 clear_atomic_switch_msr_special(
1306 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1307 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1313 for (i
= 0; i
< m
->nr
; ++i
)
1314 if (m
->guest
[i
].index
== msr
)
1320 m
->guest
[i
] = m
->guest
[m
->nr
];
1321 m
->host
[i
] = m
->host
[m
->nr
];
1322 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1323 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1326 static void add_atomic_switch_msr_special(unsigned long entry
,
1327 unsigned long exit
, unsigned long guest_val_vmcs
,
1328 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1330 vmcs_write64(guest_val_vmcs
, guest_val
);
1331 vmcs_write64(host_val_vmcs
, host_val
);
1332 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1333 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1336 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1337 u64 guest_val
, u64 host_val
)
1340 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1344 if (cpu_has_load_ia32_efer
) {
1345 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1346 VM_EXIT_LOAD_IA32_EFER
,
1349 guest_val
, host_val
);
1353 case MSR_CORE_PERF_GLOBAL_CTRL
:
1354 if (cpu_has_load_perf_global_ctrl
) {
1355 add_atomic_switch_msr_special(
1356 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1357 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1358 GUEST_IA32_PERF_GLOBAL_CTRL
,
1359 HOST_IA32_PERF_GLOBAL_CTRL
,
1360 guest_val
, host_val
);
1366 for (i
= 0; i
< m
->nr
; ++i
)
1367 if (m
->guest
[i
].index
== msr
)
1370 if (i
== NR_AUTOLOAD_MSRS
) {
1371 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1372 "Can't add msr %x\n", msr
);
1374 } else if (i
== m
->nr
) {
1376 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1377 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1380 m
->guest
[i
].index
= msr
;
1381 m
->guest
[i
].value
= guest_val
;
1382 m
->host
[i
].index
= msr
;
1383 m
->host
[i
].value
= host_val
;
1386 static void reload_tss(void)
1389 * VT restores TR but not its size. Useless.
1391 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1392 struct desc_struct
*descs
;
1394 descs
= (void *)gdt
->address
;
1395 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1399 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1404 guest_efer
= vmx
->vcpu
.arch
.efer
;
1407 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1410 ignore_bits
= EFER_NX
| EFER_SCE
;
1411 #ifdef CONFIG_X86_64
1412 ignore_bits
|= EFER_LMA
| EFER_LME
;
1413 /* SCE is meaningful only in long mode on Intel */
1414 if (guest_efer
& EFER_LMA
)
1415 ignore_bits
&= ~(u64
)EFER_SCE
;
1417 guest_efer
&= ~ignore_bits
;
1418 guest_efer
|= host_efer
& ignore_bits
;
1419 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1420 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1422 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1423 /* On ept, can't emulate nx, and must switch nx atomically */
1424 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1425 guest_efer
= vmx
->vcpu
.arch
.efer
;
1426 if (!(guest_efer
& EFER_LMA
))
1427 guest_efer
&= ~EFER_LME
;
1428 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1435 static unsigned long segment_base(u16 selector
)
1437 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1438 struct desc_struct
*d
;
1439 unsigned long table_base
;
1442 if (!(selector
& ~3))
1445 table_base
= gdt
->address
;
1447 if (selector
& 4) { /* from ldt */
1448 u16 ldt_selector
= kvm_read_ldt();
1450 if (!(ldt_selector
& ~3))
1453 table_base
= segment_base(ldt_selector
);
1455 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1456 v
= get_desc_base(d
);
1457 #ifdef CONFIG_X86_64
1458 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1459 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1464 static inline unsigned long kvm_read_tr_base(void)
1467 asm("str %0" : "=g"(tr
));
1468 return segment_base(tr
);
1471 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1473 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1476 if (vmx
->host_state
.loaded
)
1479 vmx
->host_state
.loaded
= 1;
1481 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1482 * allow segment selectors with cpl > 0 or ti == 1.
1484 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1485 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1486 savesegment(fs
, vmx
->host_state
.fs_sel
);
1487 if (!(vmx
->host_state
.fs_sel
& 7)) {
1488 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1489 vmx
->host_state
.fs_reload_needed
= 0;
1491 vmcs_write16(HOST_FS_SELECTOR
, 0);
1492 vmx
->host_state
.fs_reload_needed
= 1;
1494 savesegment(gs
, vmx
->host_state
.gs_sel
);
1495 if (!(vmx
->host_state
.gs_sel
& 7))
1496 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1498 vmcs_write16(HOST_GS_SELECTOR
, 0);
1499 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1502 #ifdef CONFIG_X86_64
1503 savesegment(ds
, vmx
->host_state
.ds_sel
);
1504 savesegment(es
, vmx
->host_state
.es_sel
);
1507 #ifdef CONFIG_X86_64
1508 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1509 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1511 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1512 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1515 #ifdef CONFIG_X86_64
1516 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1517 if (is_long_mode(&vmx
->vcpu
))
1518 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1520 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1521 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1522 vmx
->guest_msrs
[i
].data
,
1523 vmx
->guest_msrs
[i
].mask
);
1526 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1528 if (!vmx
->host_state
.loaded
)
1531 ++vmx
->vcpu
.stat
.host_state_reload
;
1532 vmx
->host_state
.loaded
= 0;
1533 #ifdef CONFIG_X86_64
1534 if (is_long_mode(&vmx
->vcpu
))
1535 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1537 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1538 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1539 #ifdef CONFIG_X86_64
1540 load_gs_index(vmx
->host_state
.gs_sel
);
1542 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1545 if (vmx
->host_state
.fs_reload_needed
)
1546 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1547 #ifdef CONFIG_X86_64
1548 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1549 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1550 loadsegment(es
, vmx
->host_state
.es_sel
);
1554 #ifdef CONFIG_X86_64
1555 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1558 * If the FPU is not active (through the host task or
1559 * the guest vcpu), then restore the cr0.TS bit.
1561 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1563 load_gdt(&__get_cpu_var(host_gdt
));
1566 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1569 __vmx_load_host_state(vmx
);
1574 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1575 * vcpu mutex is already taken.
1577 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1579 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1580 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1583 kvm_cpu_vmxon(phys_addr
);
1584 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1585 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1587 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1588 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1589 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1592 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1593 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1594 unsigned long sysenter_esp
;
1596 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1597 local_irq_disable();
1598 crash_disable_local_vmclear(cpu
);
1601 * Read loaded_vmcs->cpu should be before fetching
1602 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1603 * See the comments in __loaded_vmcs_clear().
1607 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1608 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1609 crash_enable_local_vmclear(cpu
);
1613 * Linux uses per-cpu TSS and GDT, so set these when switching
1616 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1617 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1619 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1620 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1621 vmx
->loaded_vmcs
->cpu
= cpu
;
1625 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1627 __vmx_load_host_state(to_vmx(vcpu
));
1628 if (!vmm_exclusive
) {
1629 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1635 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1639 if (vcpu
->fpu_active
)
1641 vcpu
->fpu_active
= 1;
1642 cr0
= vmcs_readl(GUEST_CR0
);
1643 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1644 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1645 vmcs_writel(GUEST_CR0
, cr0
);
1646 update_exception_bitmap(vcpu
);
1647 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1648 if (is_guest_mode(vcpu
))
1649 vcpu
->arch
.cr0_guest_owned_bits
&=
1650 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1651 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1654 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1657 * Return the cr0 value that a nested guest would read. This is a combination
1658 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1659 * its hypervisor (cr0_read_shadow).
1661 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1663 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1664 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1666 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1668 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1669 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1672 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1674 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1675 * set this *before* calling this function.
1677 vmx_decache_cr0_guest_bits(vcpu
);
1678 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1679 update_exception_bitmap(vcpu
);
1680 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1681 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1682 if (is_guest_mode(vcpu
)) {
1684 * L1's specified read shadow might not contain the TS bit,
1685 * so now that we turned on shadowing of this bit, we need to
1686 * set this bit of the shadow. Like in nested_vmx_run we need
1687 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1688 * up-to-date here because we just decached cr0.TS (and we'll
1689 * only update vmcs12->guest_cr0 on nested exit).
1691 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1692 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1693 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1694 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1696 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1699 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1701 unsigned long rflags
, save_rflags
;
1703 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1704 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1705 rflags
= vmcs_readl(GUEST_RFLAGS
);
1706 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1707 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1708 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1709 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1711 to_vmx(vcpu
)->rflags
= rflags
;
1713 return to_vmx(vcpu
)->rflags
;
1716 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1718 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1719 to_vmx(vcpu
)->rflags
= rflags
;
1720 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1721 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1722 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1724 vmcs_writel(GUEST_RFLAGS
, rflags
);
1727 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1729 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1732 if (interruptibility
& GUEST_INTR_STATE_STI
)
1733 ret
|= KVM_X86_SHADOW_INT_STI
;
1734 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1735 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1740 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1742 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1743 u32 interruptibility
= interruptibility_old
;
1745 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1747 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1748 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1749 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1750 interruptibility
|= GUEST_INTR_STATE_STI
;
1752 if ((interruptibility
!= interruptibility_old
))
1753 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1756 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1760 rip
= kvm_rip_read(vcpu
);
1761 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1762 kvm_rip_write(vcpu
, rip
);
1764 /* skipping an emulated instruction also counts */
1765 vmx_set_interrupt_shadow(vcpu
, 0);
1769 * KVM wants to inject page-faults which it got to the guest. This function
1770 * checks whether in a nested guest, we need to inject them to L1 or L2.
1771 * This function assumes it is called with the exit reason in vmcs02 being
1772 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1775 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1777 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1779 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1780 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1783 nested_vmx_vmexit(vcpu
);
1787 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1788 bool has_error_code
, u32 error_code
,
1791 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1792 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1794 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1795 nested_pf_handled(vcpu
))
1798 if (has_error_code
) {
1799 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1800 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1803 if (vmx
->rmode
.vm86_active
) {
1805 if (kvm_exception_is_soft(nr
))
1806 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1807 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1808 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1812 if (kvm_exception_is_soft(nr
)) {
1813 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1814 vmx
->vcpu
.arch
.event_exit_inst_len
);
1815 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1817 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1819 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1822 static bool vmx_rdtscp_supported(void)
1824 return cpu_has_vmx_rdtscp();
1827 static bool vmx_invpcid_supported(void)
1829 return cpu_has_vmx_invpcid() && enable_ept
;
1833 * Swap MSR entry in host/guest MSR entry array.
1835 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1837 struct shared_msr_entry tmp
;
1839 tmp
= vmx
->guest_msrs
[to
];
1840 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1841 vmx
->guest_msrs
[from
] = tmp
;
1844 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
1846 unsigned long *msr_bitmap
;
1848 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
1849 if (is_long_mode(vcpu
))
1850 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
1852 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
1854 if (is_long_mode(vcpu
))
1855 msr_bitmap
= vmx_msr_bitmap_longmode
;
1857 msr_bitmap
= vmx_msr_bitmap_legacy
;
1860 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1864 * Set up the vmcs to automatically save and restore system
1865 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1866 * mode, as fiddling with msrs is very expensive.
1868 static void setup_msrs(struct vcpu_vmx
*vmx
)
1870 int save_nmsrs
, index
;
1873 #ifdef CONFIG_X86_64
1874 if (is_long_mode(&vmx
->vcpu
)) {
1875 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1877 move_msr_up(vmx
, index
, save_nmsrs
++);
1878 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1880 move_msr_up(vmx
, index
, save_nmsrs
++);
1881 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1883 move_msr_up(vmx
, index
, save_nmsrs
++);
1884 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1885 if (index
>= 0 && vmx
->rdtscp_enabled
)
1886 move_msr_up(vmx
, index
, save_nmsrs
++);
1888 * MSR_STAR is only needed on long mode guests, and only
1889 * if efer.sce is enabled.
1891 index
= __find_msr_index(vmx
, MSR_STAR
);
1892 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1893 move_msr_up(vmx
, index
, save_nmsrs
++);
1896 index
= __find_msr_index(vmx
, MSR_EFER
);
1897 if (index
>= 0 && update_transition_efer(vmx
, index
))
1898 move_msr_up(vmx
, index
, save_nmsrs
++);
1900 vmx
->save_nmsrs
= save_nmsrs
;
1902 if (cpu_has_vmx_msr_bitmap())
1903 vmx_set_msr_bitmap(&vmx
->vcpu
);
1907 * reads and returns guest's timestamp counter "register"
1908 * guest_tsc = host_tsc + tsc_offset -- 21.3
1910 static u64
guest_read_tsc(void)
1912 u64 host_tsc
, tsc_offset
;
1915 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1916 return host_tsc
+ tsc_offset
;
1920 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1921 * counter, even if a nested guest (L2) is currently running.
1923 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
1927 tsc_offset
= is_guest_mode(vcpu
) ?
1928 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1929 vmcs_read64(TSC_OFFSET
);
1930 return host_tsc
+ tsc_offset
;
1934 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1935 * software catchup for faster rates on slower CPUs.
1937 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1942 if (user_tsc_khz
> tsc_khz
) {
1943 vcpu
->arch
.tsc_catchup
= 1;
1944 vcpu
->arch
.tsc_always_catchup
= 1;
1946 WARN(1, "user requested TSC rate below hardware speed\n");
1949 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
1951 return vmcs_read64(TSC_OFFSET
);
1955 * writes 'offset' into guest's timestamp counter offset register
1957 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1959 if (is_guest_mode(vcpu
)) {
1961 * We're here if L1 chose not to trap WRMSR to TSC. According
1962 * to the spec, this should set L1's TSC; The offset that L1
1963 * set for L2 remains unchanged, and still needs to be added
1964 * to the newly set TSC to get L2's TSC.
1966 struct vmcs12
*vmcs12
;
1967 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1968 /* recalculate vmcs02.TSC_OFFSET: */
1969 vmcs12
= get_vmcs12(vcpu
);
1970 vmcs_write64(TSC_OFFSET
, offset
+
1971 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1972 vmcs12
->tsc_offset
: 0));
1974 vmcs_write64(TSC_OFFSET
, offset
);
1978 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1980 u64 offset
= vmcs_read64(TSC_OFFSET
);
1981 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1982 if (is_guest_mode(vcpu
)) {
1983 /* Even when running L2, the adjustment needs to apply to L1 */
1984 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1988 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1990 return target_tsc
- native_read_tsc();
1993 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1995 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1996 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2000 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2001 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2002 * all guests if the "nested" module option is off, and can also be disabled
2003 * for a single guest by disabling its VMX cpuid bit.
2005 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2007 return nested
&& guest_cpuid_has_vmx(vcpu
);
2011 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2012 * returned for the various VMX controls MSRs when nested VMX is enabled.
2013 * The same values should also be used to verify that vmcs12 control fields are
2014 * valid during nested entry from L1 to L2.
2015 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2016 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2017 * bit in the high half is on if the corresponding bit in the control field
2018 * may be on. See also vmx_control_verify().
2019 * TODO: allow these variables to be modified (downgraded) by module options
2022 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2023 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2024 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2025 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2026 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2027 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2028 static __init
void nested_vmx_setup_ctls_msrs(void)
2031 * Note that as a general rule, the high half of the MSRs (bits in
2032 * the control fields which may be 1) should be initialized by the
2033 * intersection of the underlying hardware's MSR (i.e., features which
2034 * can be supported) and the list of features we want to expose -
2035 * because they are known to be properly supported in our code.
2036 * Also, usually, the low half of the MSRs (bits which must be 1) can
2037 * be set to 0, meaning that L1 may turn off any of these bits. The
2038 * reason is that if one of these bits is necessary, it will appear
2039 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2040 * fields of vmcs01 and vmcs02, will turn these bits off - and
2041 * nested_vmx_exit_handled() will not pass related exits to L1.
2042 * These rules have exceptions below.
2045 /* pin-based controls */
2046 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2047 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2049 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2050 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2052 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2053 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2054 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2055 PIN_BASED_VMX_PREEMPTION_TIMER
;
2056 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2060 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2063 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2064 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2065 #ifdef CONFIG_X86_64
2066 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2068 nested_vmx_exit_ctls_high
= 0;
2070 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2072 /* entry controls */
2073 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2074 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2075 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2076 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2077 nested_vmx_entry_ctls_high
&=
2078 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
2079 nested_vmx_entry_ctls_high
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2081 /* cpu-based controls */
2082 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2083 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2084 nested_vmx_procbased_ctls_low
= 0;
2085 nested_vmx_procbased_ctls_high
&=
2086 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2087 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2088 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2089 CPU_BASED_CR3_STORE_EXITING
|
2090 #ifdef CONFIG_X86_64
2091 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2093 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2094 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2095 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2096 CPU_BASED_PAUSE_EXITING
|
2097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2099 * We can allow some features even when not supported by the
2100 * hardware. For example, L1 can specify an MSR bitmap - and we
2101 * can use it to avoid exits to L1 - even when L0 runs L2
2102 * without MSR bitmaps.
2104 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2106 /* secondary cpu-based controls */
2107 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2108 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2109 nested_vmx_secondary_ctls_low
= 0;
2110 nested_vmx_secondary_ctls_high
&=
2111 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2112 SECONDARY_EXEC_WBINVD_EXITING
;
2114 /* miscellaneous data */
2115 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2116 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2117 VMX_MISC_SAVE_EFER_LMA
;
2118 nested_vmx_misc_high
= 0;
2121 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2124 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2126 return ((control
& high
) | low
) == control
;
2129 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2131 return low
| ((u64
)high
<< 32);
2135 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2136 * also let it use VMX-specific MSRs.
2137 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2138 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2139 * like all other MSRs).
2141 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2143 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2144 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2146 * According to the spec, processors which do not support VMX
2147 * should throw a #GP(0) when VMX capability MSRs are read.
2149 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2153 switch (msr_index
) {
2154 case MSR_IA32_FEATURE_CONTROL
:
2157 case MSR_IA32_VMX_BASIC
:
2159 * This MSR reports some information about VMX support. We
2160 * should return information about the VMX we emulate for the
2161 * guest, and the VMCS structure we give it - not about the
2162 * VMX support of the underlying hardware.
2164 *pdata
= VMCS12_REVISION
|
2165 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2166 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2168 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2169 case MSR_IA32_VMX_PINBASED_CTLS
:
2170 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2171 nested_vmx_pinbased_ctls_high
);
2173 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2174 case MSR_IA32_VMX_PROCBASED_CTLS
:
2175 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2176 nested_vmx_procbased_ctls_high
);
2178 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2179 case MSR_IA32_VMX_EXIT_CTLS
:
2180 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2181 nested_vmx_exit_ctls_high
);
2183 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2184 case MSR_IA32_VMX_ENTRY_CTLS
:
2185 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2186 nested_vmx_entry_ctls_high
);
2188 case MSR_IA32_VMX_MISC
:
2189 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2190 nested_vmx_misc_high
);
2193 * These MSRs specify bits which the guest must keep fixed (on or off)
2194 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2195 * We picked the standard core2 setting.
2197 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2198 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2199 case MSR_IA32_VMX_CR0_FIXED0
:
2200 *pdata
= VMXON_CR0_ALWAYSON
;
2202 case MSR_IA32_VMX_CR0_FIXED1
:
2205 case MSR_IA32_VMX_CR4_FIXED0
:
2206 *pdata
= VMXON_CR4_ALWAYSON
;
2208 case MSR_IA32_VMX_CR4_FIXED1
:
2211 case MSR_IA32_VMX_VMCS_ENUM
:
2214 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2215 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2216 nested_vmx_secondary_ctls_high
);
2218 case MSR_IA32_VMX_EPT_VPID_CAP
:
2219 /* Currently, no nested ept or nested vpid */
2229 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2231 if (!nested_vmx_allowed(vcpu
))
2234 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2235 /* TODO: the right thing. */
2238 * No need to treat VMX capability MSRs specially: If we don't handle
2239 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2245 * Reads an msr value (of 'msr_index') into 'pdata'.
2246 * Returns 0 on success, non-0 otherwise.
2247 * Assumes vcpu_load() was already called.
2249 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2252 struct shared_msr_entry
*msr
;
2255 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2259 switch (msr_index
) {
2260 #ifdef CONFIG_X86_64
2262 data
= vmcs_readl(GUEST_FS_BASE
);
2265 data
= vmcs_readl(GUEST_GS_BASE
);
2267 case MSR_KERNEL_GS_BASE
:
2268 vmx_load_host_state(to_vmx(vcpu
));
2269 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2273 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2275 data
= guest_read_tsc();
2277 case MSR_IA32_SYSENTER_CS
:
2278 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2280 case MSR_IA32_SYSENTER_EIP
:
2281 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2283 case MSR_IA32_SYSENTER_ESP
:
2284 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2287 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2289 /* Otherwise falls through */
2291 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2293 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2298 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2306 * Writes msr value into into the appropriate "register".
2307 * Returns 0 on success, non-0 otherwise.
2308 * Assumes vcpu_load() was already called.
2310 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2312 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2313 struct shared_msr_entry
*msr
;
2315 u32 msr_index
= msr_info
->index
;
2316 u64 data
= msr_info
->data
;
2318 switch (msr_index
) {
2320 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2322 #ifdef CONFIG_X86_64
2324 vmx_segment_cache_clear(vmx
);
2325 vmcs_writel(GUEST_FS_BASE
, data
);
2328 vmx_segment_cache_clear(vmx
);
2329 vmcs_writel(GUEST_GS_BASE
, data
);
2331 case MSR_KERNEL_GS_BASE
:
2332 vmx_load_host_state(vmx
);
2333 vmx
->msr_guest_kernel_gs_base
= data
;
2336 case MSR_IA32_SYSENTER_CS
:
2337 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2339 case MSR_IA32_SYSENTER_EIP
:
2340 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2342 case MSR_IA32_SYSENTER_ESP
:
2343 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2346 kvm_write_tsc(vcpu
, msr_info
);
2348 case MSR_IA32_CR_PAT
:
2349 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2350 vmcs_write64(GUEST_IA32_PAT
, data
);
2351 vcpu
->arch
.pat
= data
;
2354 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2356 case MSR_IA32_TSC_ADJUST
:
2357 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2360 if (!vmx
->rdtscp_enabled
)
2362 /* Check reserved bit, higher 32 bits should be zero */
2363 if ((data
>> 32) != 0)
2365 /* Otherwise falls through */
2367 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2369 msr
= find_msr_entry(vmx
, msr_index
);
2372 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2374 kvm_set_shared_msr(msr
->index
, msr
->data
,
2380 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2386 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2388 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2391 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2394 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2396 case VCPU_EXREG_PDPTR
:
2398 ept_save_pdptrs(vcpu
);
2405 static __init
int cpu_has_kvm_support(void)
2407 return cpu_has_vmx();
2410 static __init
int vmx_disabled_by_bios(void)
2414 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2415 if (msr
& FEATURE_CONTROL_LOCKED
) {
2416 /* launched w/ TXT and VMX disabled */
2417 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2420 /* launched w/o TXT and VMX only enabled w/ TXT */
2421 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2422 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2423 && !tboot_enabled()) {
2424 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2425 "activate TXT before enabling KVM\n");
2428 /* launched w/o TXT and VMX disabled */
2429 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2430 && !tboot_enabled())
2437 static void kvm_cpu_vmxon(u64 addr
)
2439 asm volatile (ASM_VMX_VMXON_RAX
2440 : : "a"(&addr
), "m"(addr
)
2444 static int hardware_enable(void *garbage
)
2446 int cpu
= raw_smp_processor_id();
2447 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2450 if (read_cr4() & X86_CR4_VMXE
)
2453 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2456 * Now we can enable the vmclear operation in kdump
2457 * since the loaded_vmcss_on_cpu list on this cpu
2458 * has been initialized.
2460 * Though the cpu is not in VMX operation now, there
2461 * is no problem to enable the vmclear operation
2462 * for the loaded_vmcss_on_cpu list is empty!
2464 crash_enable_local_vmclear(cpu
);
2466 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2468 test_bits
= FEATURE_CONTROL_LOCKED
;
2469 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2470 if (tboot_enabled())
2471 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2473 if ((old
& test_bits
) != test_bits
) {
2474 /* enable and lock */
2475 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2477 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2479 if (vmm_exclusive
) {
2480 kvm_cpu_vmxon(phys_addr
);
2484 store_gdt(&__get_cpu_var(host_gdt
));
2489 static void vmclear_local_loaded_vmcss(void)
2491 int cpu
= raw_smp_processor_id();
2492 struct loaded_vmcs
*v
, *n
;
2494 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2495 loaded_vmcss_on_cpu_link
)
2496 __loaded_vmcs_clear(v
);
2500 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2503 static void kvm_cpu_vmxoff(void)
2505 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2508 static void hardware_disable(void *garbage
)
2510 if (vmm_exclusive
) {
2511 vmclear_local_loaded_vmcss();
2514 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2517 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2518 u32 msr
, u32
*result
)
2520 u32 vmx_msr_low
, vmx_msr_high
;
2521 u32 ctl
= ctl_min
| ctl_opt
;
2523 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2525 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2526 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2528 /* Ensure minimum (required) set of control bits are supported. */
2536 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2538 u32 vmx_msr_low
, vmx_msr_high
;
2540 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2541 return vmx_msr_high
& ctl
;
2544 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2546 u32 vmx_msr_low
, vmx_msr_high
;
2547 u32 min
, opt
, min2
, opt2
;
2548 u32 _pin_based_exec_control
= 0;
2549 u32 _cpu_based_exec_control
= 0;
2550 u32 _cpu_based_2nd_exec_control
= 0;
2551 u32 _vmexit_control
= 0;
2552 u32 _vmentry_control
= 0;
2554 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2555 opt
= PIN_BASED_VIRTUAL_NMIS
;
2556 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2557 &_pin_based_exec_control
) < 0)
2560 min
= CPU_BASED_HLT_EXITING
|
2561 #ifdef CONFIG_X86_64
2562 CPU_BASED_CR8_LOAD_EXITING
|
2563 CPU_BASED_CR8_STORE_EXITING
|
2565 CPU_BASED_CR3_LOAD_EXITING
|
2566 CPU_BASED_CR3_STORE_EXITING
|
2567 CPU_BASED_USE_IO_BITMAPS
|
2568 CPU_BASED_MOV_DR_EXITING
|
2569 CPU_BASED_USE_TSC_OFFSETING
|
2570 CPU_BASED_MWAIT_EXITING
|
2571 CPU_BASED_MONITOR_EXITING
|
2572 CPU_BASED_INVLPG_EXITING
|
2573 CPU_BASED_RDPMC_EXITING
;
2575 opt
= CPU_BASED_TPR_SHADOW
|
2576 CPU_BASED_USE_MSR_BITMAPS
|
2577 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2578 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2579 &_cpu_based_exec_control
) < 0)
2581 #ifdef CONFIG_X86_64
2582 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2583 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2584 ~CPU_BASED_CR8_STORE_EXITING
;
2586 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2588 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2589 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2590 SECONDARY_EXEC_WBINVD_EXITING
|
2591 SECONDARY_EXEC_ENABLE_VPID
|
2592 SECONDARY_EXEC_ENABLE_EPT
|
2593 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2594 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2595 SECONDARY_EXEC_RDTSCP
|
2596 SECONDARY_EXEC_ENABLE_INVPCID
|
2597 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2598 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
2599 if (adjust_vmx_controls(min2
, opt2
,
2600 MSR_IA32_VMX_PROCBASED_CTLS2
,
2601 &_cpu_based_2nd_exec_control
) < 0)
2604 #ifndef CONFIG_X86_64
2605 if (!(_cpu_based_2nd_exec_control
&
2606 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2607 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2610 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2611 _cpu_based_2nd_exec_control
&= ~(
2612 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2613 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2614 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2616 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2617 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2619 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2620 CPU_BASED_CR3_STORE_EXITING
|
2621 CPU_BASED_INVLPG_EXITING
);
2622 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2623 vmx_capability
.ept
, vmx_capability
.vpid
);
2627 #ifdef CONFIG_X86_64
2628 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2630 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2631 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2632 &_vmexit_control
) < 0)
2636 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2637 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2638 &_vmentry_control
) < 0)
2641 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2643 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2644 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2647 #ifdef CONFIG_X86_64
2648 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2649 if (vmx_msr_high
& (1u<<16))
2653 /* Require Write-Back (WB) memory type for VMCS accesses. */
2654 if (((vmx_msr_high
>> 18) & 15) != 6)
2657 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2658 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2659 vmcs_conf
->revision_id
= vmx_msr_low
;
2661 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2662 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2663 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2664 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2665 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2667 cpu_has_load_ia32_efer
=
2668 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2669 VM_ENTRY_LOAD_IA32_EFER
)
2670 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2671 VM_EXIT_LOAD_IA32_EFER
);
2673 cpu_has_load_perf_global_ctrl
=
2674 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2675 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2676 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2677 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2680 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2681 * but due to arrata below it can't be used. Workaround is to use
2682 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2684 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2689 * BC86,AAY89,BD102 (model 44)
2693 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2694 switch (boot_cpu_data
.x86_model
) {
2700 cpu_has_load_perf_global_ctrl
= false;
2701 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2702 "does not work properly. Using workaround\n");
2712 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2714 int node
= cpu_to_node(cpu
);
2718 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2721 vmcs
= page_address(pages
);
2722 memset(vmcs
, 0, vmcs_config
.size
);
2723 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2727 static struct vmcs
*alloc_vmcs(void)
2729 return alloc_vmcs_cpu(raw_smp_processor_id());
2732 static void free_vmcs(struct vmcs
*vmcs
)
2734 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2738 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2740 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2742 if (!loaded_vmcs
->vmcs
)
2744 loaded_vmcs_clear(loaded_vmcs
);
2745 free_vmcs(loaded_vmcs
->vmcs
);
2746 loaded_vmcs
->vmcs
= NULL
;
2749 static void free_kvm_area(void)
2753 for_each_possible_cpu(cpu
) {
2754 free_vmcs(per_cpu(vmxarea
, cpu
));
2755 per_cpu(vmxarea
, cpu
) = NULL
;
2759 static __init
int alloc_kvm_area(void)
2763 for_each_possible_cpu(cpu
) {
2766 vmcs
= alloc_vmcs_cpu(cpu
);
2772 per_cpu(vmxarea
, cpu
) = vmcs
;
2777 static __init
int hardware_setup(void)
2779 if (setup_vmcs_config(&vmcs_config
) < 0)
2782 if (boot_cpu_has(X86_FEATURE_NX
))
2783 kvm_enable_efer_bits(EFER_NX
);
2785 if (!cpu_has_vmx_vpid())
2788 if (!cpu_has_vmx_ept() ||
2789 !cpu_has_vmx_ept_4levels()) {
2791 enable_unrestricted_guest
= 0;
2792 enable_ept_ad_bits
= 0;
2795 if (!cpu_has_vmx_ept_ad_bits())
2796 enable_ept_ad_bits
= 0;
2798 if (!cpu_has_vmx_unrestricted_guest())
2799 enable_unrestricted_guest
= 0;
2801 if (!cpu_has_vmx_flexpriority())
2802 flexpriority_enabled
= 0;
2804 if (!cpu_has_vmx_tpr_shadow())
2805 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2807 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2808 kvm_disable_largepages();
2810 if (!cpu_has_vmx_ple())
2813 if (!cpu_has_vmx_apic_register_virt() ||
2814 !cpu_has_vmx_virtual_intr_delivery())
2815 enable_apicv_reg_vid
= 0;
2817 if (enable_apicv_reg_vid
)
2818 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2820 kvm_x86_ops
->hwapic_irr_update
= NULL
;
2823 nested_vmx_setup_ctls_msrs();
2825 return alloc_kvm_area();
2828 static __exit
void hardware_unsetup(void)
2833 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2835 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2838 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
2839 struct kvm_segment
*save
)
2841 if (!emulate_invalid_guest_state
) {
2843 * CS and SS RPL should be equal during guest entry according
2844 * to VMX spec, but in reality it is not always so. Since vcpu
2845 * is in the middle of the transition from real mode to
2846 * protected mode it is safe to assume that RPL 0 is a good
2849 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
2850 save
->selector
&= ~SELECTOR_RPL_MASK
;
2851 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
2854 vmx_set_segment(vcpu
, save
, seg
);
2857 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2859 unsigned long flags
;
2860 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2863 * Update real mode segment cache. It may be not up-to-date if sement
2864 * register was written while vcpu was in a guest mode.
2866 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2867 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2868 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2869 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2870 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2871 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2873 vmx
->rmode
.vm86_active
= 0;
2875 vmx_segment_cache_clear(vmx
);
2877 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2879 flags
= vmcs_readl(GUEST_RFLAGS
);
2880 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2881 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2882 vmcs_writel(GUEST_RFLAGS
, flags
);
2884 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2885 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2887 update_exception_bitmap(vcpu
);
2889 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2890 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2891 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2892 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2893 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2894 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2896 /* CPL is always 0 when CPU enters protected mode */
2897 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2901 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2903 if (!kvm
->arch
.tss_addr
) {
2904 struct kvm_memslots
*slots
;
2905 struct kvm_memory_slot
*slot
;
2908 slots
= kvm_memslots(kvm
);
2909 slot
= id_to_memslot(slots
, 0);
2910 base_gfn
= slot
->base_gfn
+ slot
->npages
- 3;
2912 return base_gfn
<< PAGE_SHIFT
;
2914 return kvm
->arch
.tss_addr
;
2917 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
2919 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2920 struct kvm_segment var
= *save
;
2923 if (seg
== VCPU_SREG_CS
)
2926 if (!emulate_invalid_guest_state
) {
2927 var
.selector
= var
.base
>> 4;
2928 var
.base
= var
.base
& 0xffff0;
2938 if (save
->base
& 0xf)
2939 printk_once(KERN_WARNING
"kvm: segment base is not "
2940 "paragraph aligned when entering "
2941 "protected mode (seg=%d)", seg
);
2944 vmcs_write16(sf
->selector
, var
.selector
);
2945 vmcs_write32(sf
->base
, var
.base
);
2946 vmcs_write32(sf
->limit
, var
.limit
);
2947 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
2950 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2952 unsigned long flags
;
2953 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2955 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2956 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2957 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2958 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2959 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2960 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
2961 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
2963 vmx
->rmode
.vm86_active
= 1;
2966 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2967 * vcpu. Call it here with phys address pointing 16M below 4G.
2969 if (!vcpu
->kvm
->arch
.tss_addr
) {
2970 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2971 "called before entering vcpu\n");
2972 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2973 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2974 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2977 vmx_segment_cache_clear(vmx
);
2979 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2980 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2981 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2983 flags
= vmcs_readl(GUEST_RFLAGS
);
2984 vmx
->rmode
.save_rflags
= flags
;
2986 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2988 vmcs_writel(GUEST_RFLAGS
, flags
);
2989 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2990 update_exception_bitmap(vcpu
);
2992 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
2993 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
2994 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2995 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2996 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2997 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2999 kvm_mmu_reset_context(vcpu
);
3002 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3004 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3005 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3011 * Force kernel_gs_base reloading before EFER changes, as control
3012 * of this msr depends on is_long_mode().
3014 vmx_load_host_state(to_vmx(vcpu
));
3015 vcpu
->arch
.efer
= efer
;
3016 if (efer
& EFER_LMA
) {
3017 vmcs_write32(VM_ENTRY_CONTROLS
,
3018 vmcs_read32(VM_ENTRY_CONTROLS
) |
3019 VM_ENTRY_IA32E_MODE
);
3022 vmcs_write32(VM_ENTRY_CONTROLS
,
3023 vmcs_read32(VM_ENTRY_CONTROLS
) &
3024 ~VM_ENTRY_IA32E_MODE
);
3026 msr
->data
= efer
& ~EFER_LME
;
3031 #ifdef CONFIG_X86_64
3033 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3037 vmx_segment_cache_clear(to_vmx(vcpu
));
3039 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3040 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3041 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3043 vmcs_write32(GUEST_TR_AR_BYTES
,
3044 (guest_tr_ar
& ~AR_TYPE_MASK
)
3045 | AR_TYPE_BUSY_64_TSS
);
3047 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3050 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3052 vmcs_write32(VM_ENTRY_CONTROLS
,
3053 vmcs_read32(VM_ENTRY_CONTROLS
)
3054 & ~VM_ENTRY_IA32E_MODE
);
3055 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3060 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3062 vpid_sync_context(to_vmx(vcpu
));
3064 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3066 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3070 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3072 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3074 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3075 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3078 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3080 if (enable_ept
&& is_paging(vcpu
))
3081 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3082 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3085 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3087 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3089 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3090 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3093 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3095 if (!test_bit(VCPU_EXREG_PDPTR
,
3096 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3099 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3100 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
3101 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
3102 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
3103 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
3107 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3109 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3110 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3111 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3112 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3113 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3116 __set_bit(VCPU_EXREG_PDPTR
,
3117 (unsigned long *)&vcpu
->arch
.regs_avail
);
3118 __set_bit(VCPU_EXREG_PDPTR
,
3119 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3122 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3124 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3126 struct kvm_vcpu
*vcpu
)
3128 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3129 vmx_decache_cr3(vcpu
);
3130 if (!(cr0
& X86_CR0_PG
)) {
3131 /* From paging/starting to nonpaging */
3132 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3133 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3134 (CPU_BASED_CR3_LOAD_EXITING
|
3135 CPU_BASED_CR3_STORE_EXITING
));
3136 vcpu
->arch
.cr0
= cr0
;
3137 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3138 } else if (!is_paging(vcpu
)) {
3139 /* From nonpaging to paging */
3140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3141 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3142 ~(CPU_BASED_CR3_LOAD_EXITING
|
3143 CPU_BASED_CR3_STORE_EXITING
));
3144 vcpu
->arch
.cr0
= cr0
;
3145 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3148 if (!(cr0
& X86_CR0_WP
))
3149 *hw_cr0
&= ~X86_CR0_WP
;
3152 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3154 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3155 unsigned long hw_cr0
;
3157 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3158 if (enable_unrestricted_guest
)
3159 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3161 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3163 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3166 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3170 #ifdef CONFIG_X86_64
3171 if (vcpu
->arch
.efer
& EFER_LME
) {
3172 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3174 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3180 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3182 if (!vcpu
->fpu_active
)
3183 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3185 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3186 vmcs_writel(GUEST_CR0
, hw_cr0
);
3187 vcpu
->arch
.cr0
= cr0
;
3189 /* depends on vcpu->arch.cr0 to be set to a new value */
3190 vmx
->emulation_required
= emulation_required(vcpu
);
3193 static u64
construct_eptp(unsigned long root_hpa
)
3197 /* TODO write the value reading from MSR */
3198 eptp
= VMX_EPT_DEFAULT_MT
|
3199 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3200 if (enable_ept_ad_bits
)
3201 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3202 eptp
|= (root_hpa
& PAGE_MASK
);
3207 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3209 unsigned long guest_cr3
;
3214 eptp
= construct_eptp(cr3
);
3215 vmcs_write64(EPT_POINTER
, eptp
);
3216 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3217 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3218 ept_load_pdptrs(vcpu
);
3221 vmx_flush_tlb(vcpu
);
3222 vmcs_writel(GUEST_CR3
, guest_cr3
);
3225 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3227 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3228 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3230 if (cr4
& X86_CR4_VMXE
) {
3232 * To use VMXON (and later other VMX instructions), a guest
3233 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3234 * So basically the check on whether to allow nested VMX
3237 if (!nested_vmx_allowed(vcpu
))
3240 if (to_vmx(vcpu
)->nested
.vmxon
&&
3241 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3244 vcpu
->arch
.cr4
= cr4
;
3246 if (!is_paging(vcpu
)) {
3247 hw_cr4
&= ~X86_CR4_PAE
;
3248 hw_cr4
|= X86_CR4_PSE
;
3250 * SMEP is disabled if CPU is in non-paging mode in
3251 * hardware. However KVM always uses paging mode to
3252 * emulate guest non-paging mode with TDP.
3253 * To emulate this behavior, SMEP needs to be manually
3254 * disabled when guest switches to non-paging mode.
3256 hw_cr4
&= ~X86_CR4_SMEP
;
3257 } else if (!(cr4
& X86_CR4_PAE
)) {
3258 hw_cr4
&= ~X86_CR4_PAE
;
3262 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3263 vmcs_writel(GUEST_CR4
, hw_cr4
);
3267 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3268 struct kvm_segment
*var
, int seg
)
3270 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3273 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3274 *var
= vmx
->rmode
.segs
[seg
];
3275 if (seg
== VCPU_SREG_TR
3276 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3278 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3279 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3282 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3283 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3284 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3285 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3286 var
->type
= ar
& 15;
3287 var
->s
= (ar
>> 4) & 1;
3288 var
->dpl
= (ar
>> 5) & 3;
3289 var
->present
= (ar
>> 7) & 1;
3290 var
->avl
= (ar
>> 12) & 1;
3291 var
->l
= (ar
>> 13) & 1;
3292 var
->db
= (ar
>> 14) & 1;
3293 var
->g
= (ar
>> 15) & 1;
3294 var
->unusable
= (ar
>> 16) & 1;
3297 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3299 struct kvm_segment s
;
3301 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3302 vmx_get_segment(vcpu
, &s
, seg
);
3305 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3308 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3310 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3312 if (!is_protmode(vcpu
))
3315 if (!is_long_mode(vcpu
)
3316 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3319 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3320 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3321 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3328 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3332 if (var
->unusable
|| !var
->present
)
3335 ar
= var
->type
& 15;
3336 ar
|= (var
->s
& 1) << 4;
3337 ar
|= (var
->dpl
& 3) << 5;
3338 ar
|= (var
->present
& 1) << 7;
3339 ar
|= (var
->avl
& 1) << 12;
3340 ar
|= (var
->l
& 1) << 13;
3341 ar
|= (var
->db
& 1) << 14;
3342 ar
|= (var
->g
& 1) << 15;
3348 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3349 struct kvm_segment
*var
, int seg
)
3351 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3352 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3354 vmx_segment_cache_clear(vmx
);
3355 if (seg
== VCPU_SREG_CS
)
3356 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3358 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3359 vmx
->rmode
.segs
[seg
] = *var
;
3360 if (seg
== VCPU_SREG_TR
)
3361 vmcs_write16(sf
->selector
, var
->selector
);
3363 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3367 vmcs_writel(sf
->base
, var
->base
);
3368 vmcs_write32(sf
->limit
, var
->limit
);
3369 vmcs_write16(sf
->selector
, var
->selector
);
3372 * Fix the "Accessed" bit in AR field of segment registers for older
3374 * IA32 arch specifies that at the time of processor reset the
3375 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3376 * is setting it to 0 in the userland code. This causes invalid guest
3377 * state vmexit when "unrestricted guest" mode is turned on.
3378 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3379 * tree. Newer qemu binaries with that qemu fix would not need this
3382 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3383 var
->type
|= 0x1; /* Accessed */
3385 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3388 vmx
->emulation_required
|= emulation_required(vcpu
);
3391 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3393 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3395 *db
= (ar
>> 14) & 1;
3396 *l
= (ar
>> 13) & 1;
3399 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3401 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3402 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3405 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3407 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3408 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3411 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3413 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3414 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3417 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3419 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3420 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3423 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3425 struct kvm_segment var
;
3428 vmx_get_segment(vcpu
, &var
, seg
);
3430 if (seg
== VCPU_SREG_CS
)
3432 ar
= vmx_segment_access_rights(&var
);
3434 if (var
.base
!= (var
.selector
<< 4))
3436 if (var
.limit
!= 0xffff)
3444 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3446 struct kvm_segment cs
;
3447 unsigned int cs_rpl
;
3449 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3450 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3454 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3458 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3459 if (cs
.dpl
> cs_rpl
)
3462 if (cs
.dpl
!= cs_rpl
)
3468 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3472 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3474 struct kvm_segment ss
;
3475 unsigned int ss_rpl
;
3477 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3478 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3482 if (ss
.type
!= 3 && ss
.type
!= 7)
3486 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3494 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3496 struct kvm_segment var
;
3499 vmx_get_segment(vcpu
, &var
, seg
);
3500 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3508 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3509 if (var
.dpl
< rpl
) /* DPL < RPL */
3513 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3519 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3521 struct kvm_segment tr
;
3523 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3527 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3529 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3537 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3539 struct kvm_segment ldtr
;
3541 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3545 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3555 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3557 struct kvm_segment cs
, ss
;
3559 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3560 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3562 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3563 (ss
.selector
& SELECTOR_RPL_MASK
));
3567 * Check if guest state is valid. Returns true if valid, false if
3569 * We assume that registers are always usable
3571 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3573 if (enable_unrestricted_guest
)
3576 /* real mode guest state checks */
3577 if (!is_protmode(vcpu
)) {
3578 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3580 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3582 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3584 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3586 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3588 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3591 /* protected mode guest state checks */
3592 if (!cs_ss_rpl_check(vcpu
))
3594 if (!code_segment_valid(vcpu
))
3596 if (!stack_segment_valid(vcpu
))
3598 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3600 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3602 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3604 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3606 if (!tr_valid(vcpu
))
3608 if (!ldtr_valid(vcpu
))
3612 * - Add checks on RIP
3613 * - Add checks on RFLAGS
3619 static int init_rmode_tss(struct kvm
*kvm
)
3623 int r
, idx
, ret
= 0;
3625 idx
= srcu_read_lock(&kvm
->srcu
);
3626 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3627 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3630 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3631 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3632 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3635 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3638 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3642 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3643 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3650 srcu_read_unlock(&kvm
->srcu
, idx
);
3654 static int init_rmode_identity_map(struct kvm
*kvm
)
3657 pfn_t identity_map_pfn
;
3662 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3663 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3664 "haven't been allocated!\n");
3667 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3670 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3671 idx
= srcu_read_lock(&kvm
->srcu
);
3672 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3675 /* Set up identity-mapping pagetable for EPT in real mode */
3676 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3677 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3678 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3679 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3680 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3684 kvm
->arch
.ept_identity_pagetable_done
= true;
3687 srcu_read_unlock(&kvm
->srcu
, idx
);
3691 static void seg_setup(int seg
)
3693 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3696 vmcs_write16(sf
->selector
, 0);
3697 vmcs_writel(sf
->base
, 0);
3698 vmcs_write32(sf
->limit
, 0xffff);
3700 if (seg
== VCPU_SREG_CS
)
3701 ar
|= 0x08; /* code segment */
3703 vmcs_write32(sf
->ar_bytes
, ar
);
3706 static int alloc_apic_access_page(struct kvm
*kvm
)
3709 struct kvm_userspace_memory_region kvm_userspace_mem
;
3712 mutex_lock(&kvm
->slots_lock
);
3713 if (kvm
->arch
.apic_access_page
)
3715 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3716 kvm_userspace_mem
.flags
= 0;
3717 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3718 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3719 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3723 page
= gfn_to_page(kvm
, 0xfee00);
3724 if (is_error_page(page
)) {
3729 kvm
->arch
.apic_access_page
= page
;
3731 mutex_unlock(&kvm
->slots_lock
);
3735 static int alloc_identity_pagetable(struct kvm
*kvm
)
3738 struct kvm_userspace_memory_region kvm_userspace_mem
;
3741 mutex_lock(&kvm
->slots_lock
);
3742 if (kvm
->arch
.ept_identity_pagetable
)
3744 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3745 kvm_userspace_mem
.flags
= 0;
3746 kvm_userspace_mem
.guest_phys_addr
=
3747 kvm
->arch
.ept_identity_map_addr
;
3748 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3749 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3753 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3754 if (is_error_page(page
)) {
3759 kvm
->arch
.ept_identity_pagetable
= page
;
3761 mutex_unlock(&kvm
->slots_lock
);
3765 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3772 spin_lock(&vmx_vpid_lock
);
3773 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3774 if (vpid
< VMX_NR_VPIDS
) {
3776 __set_bit(vpid
, vmx_vpid_bitmap
);
3778 spin_unlock(&vmx_vpid_lock
);
3781 static void free_vpid(struct vcpu_vmx
*vmx
)
3785 spin_lock(&vmx_vpid_lock
);
3787 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3788 spin_unlock(&vmx_vpid_lock
);
3791 #define MSR_TYPE_R 1
3792 #define MSR_TYPE_W 2
3793 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
3796 int f
= sizeof(unsigned long);
3798 if (!cpu_has_vmx_msr_bitmap())
3802 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3803 * have the write-low and read-high bitmap offsets the wrong way round.
3804 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3806 if (msr
<= 0x1fff) {
3807 if (type
& MSR_TYPE_R
)
3809 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
3811 if (type
& MSR_TYPE_W
)
3813 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
3815 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3817 if (type
& MSR_TYPE_R
)
3819 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
3821 if (type
& MSR_TYPE_W
)
3823 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3828 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
3831 int f
= sizeof(unsigned long);
3833 if (!cpu_has_vmx_msr_bitmap())
3837 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3838 * have the write-low and read-high bitmap offsets the wrong way round.
3839 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3841 if (msr
<= 0x1fff) {
3842 if (type
& MSR_TYPE_R
)
3844 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
3846 if (type
& MSR_TYPE_W
)
3848 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
3850 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3852 if (type
& MSR_TYPE_R
)
3854 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
3856 if (type
& MSR_TYPE_W
)
3858 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3863 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3866 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
3867 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
3868 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
3869 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
3872 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
3874 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3876 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3880 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
3882 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3884 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3888 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
3890 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
3892 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
3897 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3898 * will not change in the lifetime of the guest.
3899 * Note that host-state that does change is set elsewhere. E.g., host-state
3900 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3902 static void vmx_set_constant_host_state(void)
3908 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
3909 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3910 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3912 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3913 #ifdef CONFIG_X86_64
3915 * Load null selectors, so we can avoid reloading them in
3916 * __vmx_load_host_state(), in case userspace uses the null selectors
3917 * too (the expected case).
3919 vmcs_write16(HOST_DS_SELECTOR
, 0);
3920 vmcs_write16(HOST_ES_SELECTOR
, 0);
3922 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3923 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3925 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3926 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3928 native_store_idt(&dt
);
3929 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3931 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
3933 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3934 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3935 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3936 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3938 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3939 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3940 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3944 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3946 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3948 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3949 if (is_guest_mode(&vmx
->vcpu
))
3950 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3951 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3952 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3955 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3957 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3958 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3959 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3960 #ifdef CONFIG_X86_64
3961 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3962 CPU_BASED_CR8_LOAD_EXITING
;
3966 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3967 CPU_BASED_CR3_LOAD_EXITING
|
3968 CPU_BASED_INVLPG_EXITING
;
3969 return exec_control
;
3972 static int vmx_vm_has_apicv(struct kvm
*kvm
)
3974 return enable_apicv_reg_vid
&& irqchip_in_kernel(kvm
);
3977 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3979 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3980 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3981 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3983 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3985 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3986 enable_unrestricted_guest
= 0;
3987 /* Enable INVPCID for non-ept guests may cause performance regression. */
3988 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
3990 if (!enable_unrestricted_guest
)
3991 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3993 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3994 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
3995 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3996 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3997 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
3998 return exec_control
;
4001 static void ept_set_mmio_spte_mask(void)
4004 * EPT Misconfigurations can be generated if the value of bits 2:0
4005 * of an EPT paging-structure entry is 110b (write/execute).
4006 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
4009 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
4013 * Sets up the vmcs for emulated real mode.
4015 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4017 #ifdef CONFIG_X86_64
4023 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4024 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4026 if (cpu_has_vmx_msr_bitmap())
4027 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4029 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4032 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
4033 vmcs_config
.pin_based_exec_ctrl
);
4035 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4037 if (cpu_has_secondary_exec_ctrls()) {
4038 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4039 vmx_secondary_exec_control(vmx
));
4042 if (enable_apicv_reg_vid
) {
4043 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4044 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4045 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4046 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4048 vmcs_write16(GUEST_INTR_STATUS
, 0);
4052 vmcs_write32(PLE_GAP
, ple_gap
);
4053 vmcs_write32(PLE_WINDOW
, ple_window
);
4056 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4057 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4058 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4060 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4061 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4062 vmx_set_constant_host_state();
4063 #ifdef CONFIG_X86_64
4064 rdmsrl(MSR_FS_BASE
, a
);
4065 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4066 rdmsrl(MSR_GS_BASE
, a
);
4067 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4069 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4070 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4073 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4074 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4075 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4076 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4077 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4079 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4080 u32 msr_low
, msr_high
;
4082 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4083 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4084 /* Write the default value follow host pat */
4085 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4086 /* Keep arch.pat sync with GUEST_IA32_PAT */
4087 vmx
->vcpu
.arch
.pat
= host_pat
;
4090 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4091 u32 index
= vmx_msr_index
[i
];
4092 u32 data_low
, data_high
;
4095 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4097 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4099 vmx
->guest_msrs
[j
].index
= i
;
4100 vmx
->guest_msrs
[j
].data
= 0;
4101 vmx
->guest_msrs
[j
].mask
= -1ull;
4105 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
4107 /* 22.2.1, 20.8.1 */
4108 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
4110 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4111 set_cr4_guest_host_mask(vmx
);
4116 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4118 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4121 vmx
->rmode
.vm86_active
= 0;
4123 vmx
->soft_vnmi_blocked
= 0;
4125 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4126 kvm_set_cr8(&vmx
->vcpu
, 0);
4127 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4128 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4129 msr
|= MSR_IA32_APICBASE_BSP
;
4130 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4132 vmx_segment_cache_clear(vmx
);
4134 seg_setup(VCPU_SREG_CS
);
4135 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4137 seg_setup(VCPU_SREG_DS
);
4138 seg_setup(VCPU_SREG_ES
);
4139 seg_setup(VCPU_SREG_FS
);
4140 seg_setup(VCPU_SREG_GS
);
4141 seg_setup(VCPU_SREG_SS
);
4143 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4144 vmcs_writel(GUEST_TR_BASE
, 0);
4145 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4146 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4148 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4149 vmcs_writel(GUEST_LDTR_BASE
, 0);
4150 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4151 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4153 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4154 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4155 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4157 vmcs_writel(GUEST_RFLAGS
, 0x02);
4158 kvm_rip_write(vcpu
, 0xfff0);
4160 vmcs_writel(GUEST_GDTR_BASE
, 0);
4161 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4163 vmcs_writel(GUEST_IDTR_BASE
, 0);
4164 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4166 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4167 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4168 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4170 /* Special registers */
4171 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4175 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4177 if (cpu_has_vmx_tpr_shadow()) {
4178 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4179 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4180 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4181 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4182 vmcs_write32(TPR_THRESHOLD
, 0);
4185 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4186 vmcs_write64(APIC_ACCESS_ADDR
,
4187 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4190 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4192 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4193 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
4194 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4195 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
4196 vmx_set_cr4(&vmx
->vcpu
, 0);
4197 vmx_set_efer(&vmx
->vcpu
, 0);
4198 vmx_fpu_activate(&vmx
->vcpu
);
4199 update_exception_bitmap(&vmx
->vcpu
);
4201 vpid_sync_context(vmx
);
4205 * In nested virtualization, check if L1 asked to exit on external interrupts.
4206 * For most existing hypervisors, this will always return true.
4208 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4210 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4211 PIN_BASED_EXT_INTR_MASK
;
4214 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4216 u32 cpu_based_vm_exec_control
;
4217 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4219 * We get here if vmx_interrupt_allowed() said we can't
4220 * inject to L1 now because L2 must run. Ask L2 to exit
4221 * right after entry, so we can inject to L1 more promptly.
4223 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT
, vcpu
);
4227 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4228 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4232 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4234 u32 cpu_based_vm_exec_control
;
4236 if (!cpu_has_virtual_nmis()) {
4237 enable_irq_window(vcpu
);
4241 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4242 enable_irq_window(vcpu
);
4245 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4246 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4247 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4250 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4252 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4254 int irq
= vcpu
->arch
.interrupt
.nr
;
4256 trace_kvm_inj_virq(irq
);
4258 ++vcpu
->stat
.irq_injections
;
4259 if (vmx
->rmode
.vm86_active
) {
4261 if (vcpu
->arch
.interrupt
.soft
)
4262 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4263 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4264 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4267 intr
= irq
| INTR_INFO_VALID_MASK
;
4268 if (vcpu
->arch
.interrupt
.soft
) {
4269 intr
|= INTR_TYPE_SOFT_INTR
;
4270 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4271 vmx
->vcpu
.arch
.event_exit_inst_len
);
4273 intr
|= INTR_TYPE_EXT_INTR
;
4274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4277 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4279 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4281 if (is_guest_mode(vcpu
))
4284 if (!cpu_has_virtual_nmis()) {
4286 * Tracking the NMI-blocked state in software is built upon
4287 * finding the next open IRQ window. This, in turn, depends on
4288 * well-behaving guests: They have to keep IRQs disabled at
4289 * least as long as the NMI handler runs. Otherwise we may
4290 * cause NMI nesting, maybe breaking the guest. But as this is
4291 * highly unlikely, we can live with the residual risk.
4293 vmx
->soft_vnmi_blocked
= 1;
4294 vmx
->vnmi_blocked_time
= 0;
4297 ++vcpu
->stat
.nmi_injections
;
4298 vmx
->nmi_known_unmasked
= false;
4299 if (vmx
->rmode
.vm86_active
) {
4300 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4301 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4304 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4305 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4308 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4310 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4313 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4314 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4315 | GUEST_INTR_STATE_NMI
));
4318 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4320 if (!cpu_has_virtual_nmis())
4321 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4322 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4324 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4327 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4329 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4331 if (!cpu_has_virtual_nmis()) {
4332 if (vmx
->soft_vnmi_blocked
!= masked
) {
4333 vmx
->soft_vnmi_blocked
= masked
;
4334 vmx
->vnmi_blocked_time
= 0;
4337 vmx
->nmi_known_unmasked
= !masked
;
4339 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4340 GUEST_INTR_STATE_NMI
);
4342 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4343 GUEST_INTR_STATE_NMI
);
4347 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4349 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4350 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4351 if (to_vmx(vcpu
)->nested
.nested_run_pending
||
4352 (vmcs12
->idt_vectoring_info_field
&
4353 VECTORING_INFO_VALID_MASK
))
4355 nested_vmx_vmexit(vcpu
);
4356 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
4357 vmcs12
->vm_exit_intr_info
= 0;
4358 /* fall through to normal code, but now in L1, not L2 */
4361 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4362 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4363 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4366 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4369 struct kvm_userspace_memory_region tss_mem
= {
4370 .slot
= TSS_PRIVATE_MEMSLOT
,
4371 .guest_phys_addr
= addr
,
4372 .memory_size
= PAGE_SIZE
* 3,
4376 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4379 kvm
->arch
.tss_addr
= addr
;
4380 if (!init_rmode_tss(kvm
))
4386 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4391 * Update instruction length as we may reinject the exception
4392 * from user space while in guest debugging mode.
4394 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4395 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4396 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4400 if (vcpu
->guest_debug
&
4401 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4418 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4419 int vec
, u32 err_code
)
4422 * Instruction with address size override prefix opcode 0x67
4423 * Cause the #SS fault with 0 error code in VM86 mode.
4425 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4426 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4427 if (vcpu
->arch
.halt_request
) {
4428 vcpu
->arch
.halt_request
= 0;
4429 return kvm_emulate_halt(vcpu
);
4437 * Forward all other exceptions that are valid in real mode.
4438 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4439 * the required debugging infrastructure rework.
4441 kvm_queue_exception(vcpu
, vec
);
4446 * Trigger machine check on the host. We assume all the MSRs are already set up
4447 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4448 * We pass a fake environment to the machine check handler because we want
4449 * the guest to be always treated like user space, no matter what context
4450 * it used internally.
4452 static void kvm_machine_check(void)
4454 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4455 struct pt_regs regs
= {
4456 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4457 .flags
= X86_EFLAGS_IF
,
4460 do_machine_check(®s
, 0);
4464 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4466 /* already handled by vcpu_run */
4470 static int handle_exception(struct kvm_vcpu
*vcpu
)
4472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4473 struct kvm_run
*kvm_run
= vcpu
->run
;
4474 u32 intr_info
, ex_no
, error_code
;
4475 unsigned long cr2
, rip
, dr6
;
4477 enum emulation_result er
;
4479 vect_info
= vmx
->idt_vectoring_info
;
4480 intr_info
= vmx
->exit_intr_info
;
4482 if (is_machine_check(intr_info
))
4483 return handle_machine_check(vcpu
);
4485 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4486 return 1; /* already handled by vmx_vcpu_run() */
4488 if (is_no_device(intr_info
)) {
4489 vmx_fpu_activate(vcpu
);
4493 if (is_invalid_opcode(intr_info
)) {
4494 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4495 if (er
!= EMULATE_DONE
)
4496 kvm_queue_exception(vcpu
, UD_VECTOR
);
4501 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4502 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4505 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4506 * MMIO, it is better to report an internal error.
4507 * See the comments in vmx_handle_exit.
4509 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4510 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4511 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4512 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4513 vcpu
->run
->internal
.ndata
= 2;
4514 vcpu
->run
->internal
.data
[0] = vect_info
;
4515 vcpu
->run
->internal
.data
[1] = intr_info
;
4519 if (is_page_fault(intr_info
)) {
4520 /* EPT won't cause page fault directly */
4522 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4523 trace_kvm_page_fault(cr2
, error_code
);
4525 if (kvm_event_needs_reinjection(vcpu
))
4526 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4527 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4530 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4532 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4533 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4537 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4538 if (!(vcpu
->guest_debug
&
4539 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4540 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4541 kvm_queue_exception(vcpu
, DB_VECTOR
);
4544 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4545 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4549 * Update instruction length as we may reinject #BP from
4550 * user space while in guest debugging mode. Reading it for
4551 * #DB as well causes no harm, it is not used in that case.
4553 vmx
->vcpu
.arch
.event_exit_inst_len
=
4554 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4555 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4556 rip
= kvm_rip_read(vcpu
);
4557 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4558 kvm_run
->debug
.arch
.exception
= ex_no
;
4561 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4562 kvm_run
->ex
.exception
= ex_no
;
4563 kvm_run
->ex
.error_code
= error_code
;
4569 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4571 ++vcpu
->stat
.irq_exits
;
4575 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4577 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4581 static int handle_io(struct kvm_vcpu
*vcpu
)
4583 unsigned long exit_qualification
;
4584 int size
, in
, string
;
4587 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4588 string
= (exit_qualification
& 16) != 0;
4589 in
= (exit_qualification
& 8) != 0;
4591 ++vcpu
->stat
.io_exits
;
4594 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4596 port
= exit_qualification
>> 16;
4597 size
= (exit_qualification
& 7) + 1;
4598 skip_emulated_instruction(vcpu
);
4600 return kvm_fast_pio_out(vcpu
, size
, port
);
4604 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4607 * Patch in the VMCALL instruction:
4609 hypercall
[0] = 0x0f;
4610 hypercall
[1] = 0x01;
4611 hypercall
[2] = 0xc1;
4614 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4615 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4617 if (is_guest_mode(vcpu
)) {
4618 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4619 unsigned long orig_val
= val
;
4622 * We get here when L2 changed cr0 in a way that did not change
4623 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4624 * but did change L0 shadowed bits. So we first calculate the
4625 * effective cr0 value that L1 would like to write into the
4626 * hardware. It consists of the L2-owned bits from the new
4627 * value combined with the L1-owned bits from L1's guest_cr0.
4629 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4630 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4632 /* TODO: will have to take unrestricted guest mode into
4634 if ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
)
4637 if (kvm_set_cr0(vcpu
, val
))
4639 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4642 if (to_vmx(vcpu
)->nested
.vmxon
&&
4643 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4645 return kvm_set_cr0(vcpu
, val
);
4649 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4651 if (is_guest_mode(vcpu
)) {
4652 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4653 unsigned long orig_val
= val
;
4655 /* analogously to handle_set_cr0 */
4656 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4657 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4658 if (kvm_set_cr4(vcpu
, val
))
4660 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4663 return kvm_set_cr4(vcpu
, val
);
4666 /* called to set cr0 as approriate for clts instruction exit. */
4667 static void handle_clts(struct kvm_vcpu
*vcpu
)
4669 if (is_guest_mode(vcpu
)) {
4671 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4672 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4673 * just pretend it's off (also in arch.cr0 for fpu_activate).
4675 vmcs_writel(CR0_READ_SHADOW
,
4676 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4677 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4679 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4682 static int handle_cr(struct kvm_vcpu
*vcpu
)
4684 unsigned long exit_qualification
, val
;
4689 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4690 cr
= exit_qualification
& 15;
4691 reg
= (exit_qualification
>> 8) & 15;
4692 switch ((exit_qualification
>> 4) & 3) {
4693 case 0: /* mov to cr */
4694 val
= kvm_register_read(vcpu
, reg
);
4695 trace_kvm_cr_write(cr
, val
);
4698 err
= handle_set_cr0(vcpu
, val
);
4699 kvm_complete_insn_gp(vcpu
, err
);
4702 err
= kvm_set_cr3(vcpu
, val
);
4703 kvm_complete_insn_gp(vcpu
, err
);
4706 err
= handle_set_cr4(vcpu
, val
);
4707 kvm_complete_insn_gp(vcpu
, err
);
4710 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4711 u8 cr8
= kvm_register_read(vcpu
, reg
);
4712 err
= kvm_set_cr8(vcpu
, cr8
);
4713 kvm_complete_insn_gp(vcpu
, err
);
4714 if (irqchip_in_kernel(vcpu
->kvm
))
4716 if (cr8_prev
<= cr8
)
4718 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4725 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4726 skip_emulated_instruction(vcpu
);
4727 vmx_fpu_activate(vcpu
);
4729 case 1: /*mov from cr*/
4732 val
= kvm_read_cr3(vcpu
);
4733 kvm_register_write(vcpu
, reg
, val
);
4734 trace_kvm_cr_read(cr
, val
);
4735 skip_emulated_instruction(vcpu
);
4738 val
= kvm_get_cr8(vcpu
);
4739 kvm_register_write(vcpu
, reg
, val
);
4740 trace_kvm_cr_read(cr
, val
);
4741 skip_emulated_instruction(vcpu
);
4746 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4747 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4748 kvm_lmsw(vcpu
, val
);
4750 skip_emulated_instruction(vcpu
);
4755 vcpu
->run
->exit_reason
= 0;
4756 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4757 (int)(exit_qualification
>> 4) & 3, cr
);
4761 static int handle_dr(struct kvm_vcpu
*vcpu
)
4763 unsigned long exit_qualification
;
4766 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4767 if (!kvm_require_cpl(vcpu
, 0))
4769 dr
= vmcs_readl(GUEST_DR7
);
4772 * As the vm-exit takes precedence over the debug trap, we
4773 * need to emulate the latter, either for the host or the
4774 * guest debugging itself.
4776 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4777 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4778 vcpu
->run
->debug
.arch
.dr7
= dr
;
4779 vcpu
->run
->debug
.arch
.pc
=
4780 vmcs_readl(GUEST_CS_BASE
) +
4781 vmcs_readl(GUEST_RIP
);
4782 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4783 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4786 vcpu
->arch
.dr7
&= ~DR7_GD
;
4787 vcpu
->arch
.dr6
|= DR6_BD
;
4788 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4789 kvm_queue_exception(vcpu
, DB_VECTOR
);
4794 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4795 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4796 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4797 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4799 if (!kvm_get_dr(vcpu
, dr
, &val
))
4800 kvm_register_write(vcpu
, reg
, val
);
4802 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4803 skip_emulated_instruction(vcpu
);
4807 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4809 vmcs_writel(GUEST_DR7
, val
);
4812 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4814 kvm_emulate_cpuid(vcpu
);
4818 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4820 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4823 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4824 trace_kvm_msr_read_ex(ecx
);
4825 kvm_inject_gp(vcpu
, 0);
4829 trace_kvm_msr_read(ecx
, data
);
4831 /* FIXME: handling of bits 32:63 of rax, rdx */
4832 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4833 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4834 skip_emulated_instruction(vcpu
);
4838 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4840 struct msr_data msr
;
4841 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4842 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4843 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4847 msr
.host_initiated
= false;
4848 if (vmx_set_msr(vcpu
, &msr
) != 0) {
4849 trace_kvm_msr_write_ex(ecx
, data
);
4850 kvm_inject_gp(vcpu
, 0);
4854 trace_kvm_msr_write(ecx
, data
);
4855 skip_emulated_instruction(vcpu
);
4859 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4861 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4865 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4867 u32 cpu_based_vm_exec_control
;
4869 /* clear pending irq */
4870 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4871 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4872 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4874 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4876 ++vcpu
->stat
.irq_window_exits
;
4879 * If the user space waits to inject interrupts, exit as soon as
4882 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4883 vcpu
->run
->request_interrupt_window
&&
4884 !kvm_cpu_has_interrupt(vcpu
)) {
4885 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4891 static int handle_halt(struct kvm_vcpu
*vcpu
)
4893 skip_emulated_instruction(vcpu
);
4894 return kvm_emulate_halt(vcpu
);
4897 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4899 skip_emulated_instruction(vcpu
);
4900 kvm_emulate_hypercall(vcpu
);
4904 static int handle_invd(struct kvm_vcpu
*vcpu
)
4906 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4909 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4911 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4913 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4914 skip_emulated_instruction(vcpu
);
4918 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
4922 err
= kvm_rdpmc(vcpu
);
4923 kvm_complete_insn_gp(vcpu
, err
);
4928 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4930 skip_emulated_instruction(vcpu
);
4931 kvm_emulate_wbinvd(vcpu
);
4935 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4937 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4938 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4940 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4941 skip_emulated_instruction(vcpu
);
4945 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4947 if (likely(fasteoi
)) {
4948 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4949 int access_type
, offset
;
4951 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4952 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4954 * Sane guest uses MOV to write EOI, with written value
4955 * not cared. So make a short-circuit here by avoiding
4956 * heavy instruction emulation.
4958 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4959 (offset
== APIC_EOI
)) {
4960 kvm_lapic_set_eoi(vcpu
);
4961 skip_emulated_instruction(vcpu
);
4965 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4968 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
4970 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4971 int vector
= exit_qualification
& 0xff;
4973 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4974 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
4978 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
4980 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4981 u32 offset
= exit_qualification
& 0xfff;
4983 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4984 kvm_apic_write_nodecode(vcpu
, offset
);
4988 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4990 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4991 unsigned long exit_qualification
;
4992 bool has_error_code
= false;
4995 int reason
, type
, idt_v
, idt_index
;
4997 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4998 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
4999 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5001 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5003 reason
= (u32
)exit_qualification
>> 30;
5004 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5006 case INTR_TYPE_NMI_INTR
:
5007 vcpu
->arch
.nmi_injected
= false;
5008 vmx_set_nmi_mask(vcpu
, true);
5010 case INTR_TYPE_EXT_INTR
:
5011 case INTR_TYPE_SOFT_INTR
:
5012 kvm_clear_interrupt_queue(vcpu
);
5014 case INTR_TYPE_HARD_EXCEPTION
:
5015 if (vmx
->idt_vectoring_info
&
5016 VECTORING_INFO_DELIVER_CODE_MASK
) {
5017 has_error_code
= true;
5019 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5022 case INTR_TYPE_SOFT_EXCEPTION
:
5023 kvm_clear_exception_queue(vcpu
);
5029 tss_selector
= exit_qualification
;
5031 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5032 type
!= INTR_TYPE_EXT_INTR
&&
5033 type
!= INTR_TYPE_NMI_INTR
))
5034 skip_emulated_instruction(vcpu
);
5036 if (kvm_task_switch(vcpu
, tss_selector
,
5037 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5038 has_error_code
, error_code
) == EMULATE_FAIL
) {
5039 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5040 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5041 vcpu
->run
->internal
.ndata
= 0;
5045 /* clear all local breakpoint enable flags */
5046 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5049 * TODO: What about debug traps on tss switch?
5050 * Are we supposed to inject them and update dr6?
5056 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5058 unsigned long exit_qualification
;
5063 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5065 gla_validity
= (exit_qualification
>> 7) & 0x3;
5066 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5067 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5068 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5069 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5070 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5071 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5072 (long unsigned int)exit_qualification
);
5073 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5074 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5078 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5079 trace_kvm_page_fault(gpa
, exit_qualification
);
5081 /* It is a write fault? */
5082 error_code
= exit_qualification
& (1U << 1);
5083 /* ept page table is present? */
5084 error_code
|= (exit_qualification
>> 3) & 0x1;
5086 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5089 static u64
ept_rsvd_mask(u64 spte
, int level
)
5094 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5095 mask
|= (1ULL << i
);
5098 /* bits 7:3 reserved */
5100 else if (level
== 2) {
5101 if (spte
& (1ULL << 7))
5102 /* 2MB ref, bits 20:12 reserved */
5105 /* bits 6:3 reserved */
5112 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5115 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5117 /* 010b (write-only) */
5118 WARN_ON((spte
& 0x7) == 0x2);
5120 /* 110b (write/execute) */
5121 WARN_ON((spte
& 0x7) == 0x6);
5123 /* 100b (execute-only) and value not supported by logical processor */
5124 if (!cpu_has_vmx_ept_execute_only())
5125 WARN_ON((spte
& 0x7) == 0x4);
5129 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5131 if (rsvd_bits
!= 0) {
5132 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5133 __func__
, rsvd_bits
);
5137 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5138 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5140 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5141 ept_mem_type
== 7) {
5142 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5143 __func__
, ept_mem_type
);
5150 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5153 int nr_sptes
, i
, ret
;
5156 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5158 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5159 if (likely(ret
== 1))
5160 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5165 /* It is the real ept misconfig */
5166 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5167 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5169 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5171 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5172 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5174 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5175 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5180 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5182 u32 cpu_based_vm_exec_control
;
5184 /* clear pending NMI */
5185 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5186 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5187 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5188 ++vcpu
->stat
.nmi_window_exits
;
5189 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5194 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5196 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5197 enum emulation_result err
= EMULATE_DONE
;
5200 bool intr_window_requested
;
5201 unsigned count
= 130;
5203 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5204 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5206 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5207 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5208 return handle_interrupt_window(&vmx
->vcpu
);
5210 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5213 err
= emulate_instruction(vcpu
, 0);
5215 if (err
== EMULATE_DO_MMIO
) {
5220 if (err
!= EMULATE_DONE
) {
5221 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5222 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5223 vcpu
->run
->internal
.ndata
= 0;
5227 if (signal_pending(current
))
5233 vmx
->emulation_required
= emulation_required(vcpu
);
5239 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5240 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5242 static int handle_pause(struct kvm_vcpu
*vcpu
)
5244 skip_emulated_instruction(vcpu
);
5245 kvm_vcpu_on_spin(vcpu
);
5250 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5252 kvm_queue_exception(vcpu
, UD_VECTOR
);
5257 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5258 * We could reuse a single VMCS for all the L2 guests, but we also want the
5259 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5260 * allows keeping them loaded on the processor, and in the future will allow
5261 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5262 * every entry if they never change.
5263 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5264 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5266 * The following functions allocate and free a vmcs02 in this pool.
5269 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5270 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5272 struct vmcs02_list
*item
;
5273 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5274 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5275 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5276 return &item
->vmcs02
;
5279 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5280 /* Recycle the least recently used VMCS. */
5281 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5282 struct vmcs02_list
, list
);
5283 item
->vmptr
= vmx
->nested
.current_vmptr
;
5284 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5285 return &item
->vmcs02
;
5288 /* Create a new VMCS */
5289 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5292 item
->vmcs02
.vmcs
= alloc_vmcs();
5293 if (!item
->vmcs02
.vmcs
) {
5297 loaded_vmcs_init(&item
->vmcs02
);
5298 item
->vmptr
= vmx
->nested
.current_vmptr
;
5299 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5300 vmx
->nested
.vmcs02_num
++;
5301 return &item
->vmcs02
;
5304 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5305 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5307 struct vmcs02_list
*item
;
5308 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5309 if (item
->vmptr
== vmptr
) {
5310 free_loaded_vmcs(&item
->vmcs02
);
5311 list_del(&item
->list
);
5313 vmx
->nested
.vmcs02_num
--;
5319 * Free all VMCSs saved for this vcpu, except the one pointed by
5320 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5321 * currently used, if running L2), and vmcs01 when running L2.
5323 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5325 struct vmcs02_list
*item
, *n
;
5326 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5327 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5328 free_loaded_vmcs(&item
->vmcs02
);
5329 list_del(&item
->list
);
5332 vmx
->nested
.vmcs02_num
= 0;
5334 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5335 free_loaded_vmcs(&vmx
->vmcs01
);
5339 * Emulate the VMXON instruction.
5340 * Currently, we just remember that VMX is active, and do not save or even
5341 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5342 * do not currently need to store anything in that guest-allocated memory
5343 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5344 * argument is different from the VMXON pointer (which the spec says they do).
5346 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5348 struct kvm_segment cs
;
5349 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5351 /* The Intel VMX Instruction Reference lists a bunch of bits that
5352 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5353 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5354 * Otherwise, we should fail with #UD. We test these now:
5356 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5357 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5358 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5359 kvm_queue_exception(vcpu
, UD_VECTOR
);
5363 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5364 if (is_long_mode(vcpu
) && !cs
.l
) {
5365 kvm_queue_exception(vcpu
, UD_VECTOR
);
5369 if (vmx_get_cpl(vcpu
)) {
5370 kvm_inject_gp(vcpu
, 0);
5374 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5375 vmx
->nested
.vmcs02_num
= 0;
5377 vmx
->nested
.vmxon
= true;
5379 skip_emulated_instruction(vcpu
);
5384 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5385 * for running VMX instructions (except VMXON, whose prerequisites are
5386 * slightly different). It also specifies what exception to inject otherwise.
5388 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5390 struct kvm_segment cs
;
5391 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5393 if (!vmx
->nested
.vmxon
) {
5394 kvm_queue_exception(vcpu
, UD_VECTOR
);
5398 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5399 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5400 (is_long_mode(vcpu
) && !cs
.l
)) {
5401 kvm_queue_exception(vcpu
, UD_VECTOR
);
5405 if (vmx_get_cpl(vcpu
)) {
5406 kvm_inject_gp(vcpu
, 0);
5414 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5415 * just stops using VMX.
5417 static void free_nested(struct vcpu_vmx
*vmx
)
5419 if (!vmx
->nested
.vmxon
)
5421 vmx
->nested
.vmxon
= false;
5422 if (vmx
->nested
.current_vmptr
!= -1ull) {
5423 kunmap(vmx
->nested
.current_vmcs12_page
);
5424 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5425 vmx
->nested
.current_vmptr
= -1ull;
5426 vmx
->nested
.current_vmcs12
= NULL
;
5428 /* Unpin physical memory we referred to in current vmcs02 */
5429 if (vmx
->nested
.apic_access_page
) {
5430 nested_release_page(vmx
->nested
.apic_access_page
);
5431 vmx
->nested
.apic_access_page
= 0;
5434 nested_free_all_saved_vmcss(vmx
);
5437 /* Emulate the VMXOFF instruction */
5438 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5440 if (!nested_vmx_check_permission(vcpu
))
5442 free_nested(to_vmx(vcpu
));
5443 skip_emulated_instruction(vcpu
);
5448 * Decode the memory-address operand of a vmx instruction, as recorded on an
5449 * exit caused by such an instruction (run by a guest hypervisor).
5450 * On success, returns 0. When the operand is invalid, returns 1 and throws
5453 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5454 unsigned long exit_qualification
,
5455 u32 vmx_instruction_info
, gva_t
*ret
)
5458 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5459 * Execution", on an exit, vmx_instruction_info holds most of the
5460 * addressing components of the operand. Only the displacement part
5461 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5462 * For how an actual address is calculated from all these components,
5463 * refer to Vol. 1, "Operand Addressing".
5465 int scaling
= vmx_instruction_info
& 3;
5466 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5467 bool is_reg
= vmx_instruction_info
& (1u << 10);
5468 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5469 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5470 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5471 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5472 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5475 kvm_queue_exception(vcpu
, UD_VECTOR
);
5479 /* Addr = segment_base + offset */
5480 /* offset = base + [index * scale] + displacement */
5481 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5483 *ret
+= kvm_register_read(vcpu
, base_reg
);
5485 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5486 *ret
+= exit_qualification
; /* holds the displacement */
5488 if (addr_size
== 1) /* 32 bit */
5492 * TODO: throw #GP (and return 1) in various cases that the VM*
5493 * instructions require it - e.g., offset beyond segment limit,
5494 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5495 * address, and so on. Currently these are not checked.
5501 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5502 * set the success or error code of an emulated VMX instruction, as specified
5503 * by Vol 2B, VMX Instruction Reference, "Conventions".
5505 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5507 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5508 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5509 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5512 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5514 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5515 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5516 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5520 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5521 u32 vm_instruction_error
)
5523 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5525 * failValid writes the error number to the current VMCS, which
5526 * can't be done there isn't a current VMCS.
5528 nested_vmx_failInvalid(vcpu
);
5531 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5532 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5533 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5535 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5538 /* Emulate the VMCLEAR instruction */
5539 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5544 struct vmcs12
*vmcs12
;
5546 struct x86_exception e
;
5548 if (!nested_vmx_check_permission(vcpu
))
5551 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5552 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5555 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5556 sizeof(vmptr
), &e
)) {
5557 kvm_inject_page_fault(vcpu
, &e
);
5561 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5562 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5563 skip_emulated_instruction(vcpu
);
5567 if (vmptr
== vmx
->nested
.current_vmptr
) {
5568 kunmap(vmx
->nested
.current_vmcs12_page
);
5569 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5570 vmx
->nested
.current_vmptr
= -1ull;
5571 vmx
->nested
.current_vmcs12
= NULL
;
5574 page
= nested_get_page(vcpu
, vmptr
);
5577 * For accurate processor emulation, VMCLEAR beyond available
5578 * physical memory should do nothing at all. However, it is
5579 * possible that a nested vmx bug, not a guest hypervisor bug,
5580 * resulted in this case, so let's shut down before doing any
5583 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5586 vmcs12
= kmap(page
);
5587 vmcs12
->launch_state
= 0;
5589 nested_release_page(page
);
5591 nested_free_vmcs02(vmx
, vmptr
);
5593 skip_emulated_instruction(vcpu
);
5594 nested_vmx_succeed(vcpu
);
5598 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5600 /* Emulate the VMLAUNCH instruction */
5601 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5603 return nested_vmx_run(vcpu
, true);
5606 /* Emulate the VMRESUME instruction */
5607 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5610 return nested_vmx_run(vcpu
, false);
5613 enum vmcs_field_type
{
5614 VMCS_FIELD_TYPE_U16
= 0,
5615 VMCS_FIELD_TYPE_U64
= 1,
5616 VMCS_FIELD_TYPE_U32
= 2,
5617 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5620 static inline int vmcs_field_type(unsigned long field
)
5622 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5623 return VMCS_FIELD_TYPE_U32
;
5624 return (field
>> 13) & 0x3 ;
5627 static inline int vmcs_field_readonly(unsigned long field
)
5629 return (((field
>> 10) & 0x3) == 1);
5633 * Read a vmcs12 field. Since these can have varying lengths and we return
5634 * one type, we chose the biggest type (u64) and zero-extend the return value
5635 * to that size. Note that the caller, handle_vmread, might need to use only
5636 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5637 * 64-bit fields are to be returned).
5639 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5640 unsigned long field
, u64
*ret
)
5642 short offset
= vmcs_field_to_offset(field
);
5648 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5650 switch (vmcs_field_type(field
)) {
5651 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5652 *ret
= *((natural_width
*)p
);
5654 case VMCS_FIELD_TYPE_U16
:
5657 case VMCS_FIELD_TYPE_U32
:
5660 case VMCS_FIELD_TYPE_U64
:
5664 return 0; /* can never happen. */
5669 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5670 * used before) all generate the same failure when it is missing.
5672 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5674 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5675 if (vmx
->nested
.current_vmptr
== -1ull) {
5676 nested_vmx_failInvalid(vcpu
);
5677 skip_emulated_instruction(vcpu
);
5683 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5685 unsigned long field
;
5687 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5688 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5691 if (!nested_vmx_check_permission(vcpu
) ||
5692 !nested_vmx_check_vmcs12(vcpu
))
5695 /* Decode instruction info and find the field to read */
5696 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5697 /* Read the field, zero-extended to a u64 field_value */
5698 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5699 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5700 skip_emulated_instruction(vcpu
);
5704 * Now copy part of this value to register or memory, as requested.
5705 * Note that the number of bits actually copied is 32 or 64 depending
5706 * on the guest's mode (32 or 64 bit), not on the given field's length.
5708 if (vmx_instruction_info
& (1u << 10)) {
5709 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5712 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5713 vmx_instruction_info
, &gva
))
5715 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5716 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5717 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5720 nested_vmx_succeed(vcpu
);
5721 skip_emulated_instruction(vcpu
);
5726 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5728 unsigned long field
;
5730 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5731 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5734 /* The value to write might be 32 or 64 bits, depending on L1's long
5735 * mode, and eventually we need to write that into a field of several
5736 * possible lengths. The code below first zero-extends the value to 64
5737 * bit (field_value), and then copies only the approriate number of
5738 * bits into the vmcs12 field.
5740 u64 field_value
= 0;
5741 struct x86_exception e
;
5743 if (!nested_vmx_check_permission(vcpu
) ||
5744 !nested_vmx_check_vmcs12(vcpu
))
5747 if (vmx_instruction_info
& (1u << 10))
5748 field_value
= kvm_register_read(vcpu
,
5749 (((vmx_instruction_info
) >> 3) & 0xf));
5751 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5752 vmx_instruction_info
, &gva
))
5754 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5755 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5756 kvm_inject_page_fault(vcpu
, &e
);
5762 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5763 if (vmcs_field_readonly(field
)) {
5764 nested_vmx_failValid(vcpu
,
5765 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5766 skip_emulated_instruction(vcpu
);
5770 offset
= vmcs_field_to_offset(field
);
5772 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5773 skip_emulated_instruction(vcpu
);
5776 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5778 switch (vmcs_field_type(field
)) {
5779 case VMCS_FIELD_TYPE_U16
:
5780 *(u16
*)p
= field_value
;
5782 case VMCS_FIELD_TYPE_U32
:
5783 *(u32
*)p
= field_value
;
5785 case VMCS_FIELD_TYPE_U64
:
5786 *(u64
*)p
= field_value
;
5788 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5789 *(natural_width
*)p
= field_value
;
5792 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5793 skip_emulated_instruction(vcpu
);
5797 nested_vmx_succeed(vcpu
);
5798 skip_emulated_instruction(vcpu
);
5802 /* Emulate the VMPTRLD instruction */
5803 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5805 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5808 struct x86_exception e
;
5810 if (!nested_vmx_check_permission(vcpu
))
5813 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5814 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5817 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5818 sizeof(vmptr
), &e
)) {
5819 kvm_inject_page_fault(vcpu
, &e
);
5823 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5824 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5825 skip_emulated_instruction(vcpu
);
5829 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5830 struct vmcs12
*new_vmcs12
;
5832 page
= nested_get_page(vcpu
, vmptr
);
5834 nested_vmx_failInvalid(vcpu
);
5835 skip_emulated_instruction(vcpu
);
5838 new_vmcs12
= kmap(page
);
5839 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5841 nested_release_page_clean(page
);
5842 nested_vmx_failValid(vcpu
,
5843 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5844 skip_emulated_instruction(vcpu
);
5847 if (vmx
->nested
.current_vmptr
!= -1ull) {
5848 kunmap(vmx
->nested
.current_vmcs12_page
);
5849 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5852 vmx
->nested
.current_vmptr
= vmptr
;
5853 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5854 vmx
->nested
.current_vmcs12_page
= page
;
5857 nested_vmx_succeed(vcpu
);
5858 skip_emulated_instruction(vcpu
);
5862 /* Emulate the VMPTRST instruction */
5863 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5865 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5866 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5868 struct x86_exception e
;
5870 if (!nested_vmx_check_permission(vcpu
))
5873 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5874 vmx_instruction_info
, &vmcs_gva
))
5876 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5877 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5878 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5880 kvm_inject_page_fault(vcpu
, &e
);
5883 nested_vmx_succeed(vcpu
);
5884 skip_emulated_instruction(vcpu
);
5889 * The exit handlers return 1 if the exit was handled fully and guest execution
5890 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5891 * to be done to userspace and return 0.
5893 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5894 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5895 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5896 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5897 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5898 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5899 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5900 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5901 [EXIT_REASON_CPUID
] = handle_cpuid
,
5902 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5903 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5904 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5905 [EXIT_REASON_HLT
] = handle_halt
,
5906 [EXIT_REASON_INVD
] = handle_invd
,
5907 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5908 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
5909 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5910 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5911 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5912 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5913 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5914 [EXIT_REASON_VMREAD
] = handle_vmread
,
5915 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5916 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5917 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5918 [EXIT_REASON_VMON
] = handle_vmon
,
5919 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5920 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5921 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
5922 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
5923 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5924 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5925 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5926 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5927 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5928 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5929 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5930 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5931 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5934 static const int kvm_vmx_max_exit_handlers
=
5935 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5937 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
5938 struct vmcs12
*vmcs12
)
5940 unsigned long exit_qualification
;
5941 gpa_t bitmap
, last_bitmap
;
5946 if (nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
))
5949 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
5952 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5954 port
= exit_qualification
>> 16;
5955 size
= (exit_qualification
& 7) + 1;
5957 last_bitmap
= (gpa_t
)-1;
5962 bitmap
= vmcs12
->io_bitmap_a
;
5963 else if (port
< 0x10000)
5964 bitmap
= vmcs12
->io_bitmap_b
;
5967 bitmap
+= (port
& 0x7fff) / 8;
5969 if (last_bitmap
!= bitmap
)
5970 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
5972 if (b
& (1 << (port
& 7)))
5977 last_bitmap
= bitmap
;
5984 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5985 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5986 * disinterest in the current event (read or write a specific MSR) by using an
5987 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5989 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5990 struct vmcs12
*vmcs12
, u32 exit_reason
)
5992 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5995 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
5999 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6000 * for the four combinations of read/write and low/high MSR numbers.
6001 * First we need to figure out which of the four to use:
6003 bitmap
= vmcs12
->msr_bitmap
;
6004 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6006 if (msr_index
>= 0xc0000000) {
6007 msr_index
-= 0xc0000000;
6011 /* Then read the msr_index'th bit from this bitmap: */
6012 if (msr_index
< 1024*8) {
6014 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6016 return 1 & (b
>> (msr_index
& 7));
6018 return 1; /* let L1 handle the wrong parameter */
6022 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6023 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6024 * intercept (via guest_host_mask etc.) the current event.
6026 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6027 struct vmcs12
*vmcs12
)
6029 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6030 int cr
= exit_qualification
& 15;
6031 int reg
= (exit_qualification
>> 8) & 15;
6032 unsigned long val
= kvm_register_read(vcpu
, reg
);
6034 switch ((exit_qualification
>> 4) & 3) {
6035 case 0: /* mov to cr */
6038 if (vmcs12
->cr0_guest_host_mask
&
6039 (val
^ vmcs12
->cr0_read_shadow
))
6043 if ((vmcs12
->cr3_target_count
>= 1 &&
6044 vmcs12
->cr3_target_value0
== val
) ||
6045 (vmcs12
->cr3_target_count
>= 2 &&
6046 vmcs12
->cr3_target_value1
== val
) ||
6047 (vmcs12
->cr3_target_count
>= 3 &&
6048 vmcs12
->cr3_target_value2
== val
) ||
6049 (vmcs12
->cr3_target_count
>= 4 &&
6050 vmcs12
->cr3_target_value3
== val
))
6052 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6056 if (vmcs12
->cr4_guest_host_mask
&
6057 (vmcs12
->cr4_read_shadow
^ val
))
6061 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6067 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6068 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6071 case 1: /* mov from cr */
6074 if (vmcs12
->cpu_based_vm_exec_control
&
6075 CPU_BASED_CR3_STORE_EXITING
)
6079 if (vmcs12
->cpu_based_vm_exec_control
&
6080 CPU_BASED_CR8_STORE_EXITING
)
6087 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6088 * cr0. Other attempted changes are ignored, with no exit.
6090 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6091 (val
^ vmcs12
->cr0_read_shadow
))
6093 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6094 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6103 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6104 * should handle it ourselves in L0 (and then continue L2). Only call this
6105 * when in is_guest_mode (L2).
6107 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6109 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6110 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6111 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6112 u32 exit_reason
= vmx
->exit_reason
;
6114 if (vmx
->nested
.nested_run_pending
)
6117 if (unlikely(vmx
->fail
)) {
6118 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6119 vmcs_read32(VM_INSTRUCTION_ERROR
));
6123 switch (exit_reason
) {
6124 case EXIT_REASON_EXCEPTION_NMI
:
6125 if (!is_exception(intr_info
))
6127 else if (is_page_fault(intr_info
))
6129 return vmcs12
->exception_bitmap
&
6130 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6131 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6133 case EXIT_REASON_TRIPLE_FAULT
:
6135 case EXIT_REASON_PENDING_INTERRUPT
:
6136 case EXIT_REASON_NMI_WINDOW
:
6138 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
6139 * (aka Interrupt Window Exiting) only when L1 turned it on,
6140 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
6141 * Same for NMI Window Exiting.
6144 case EXIT_REASON_TASK_SWITCH
:
6146 case EXIT_REASON_CPUID
:
6148 case EXIT_REASON_HLT
:
6149 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6150 case EXIT_REASON_INVD
:
6152 case EXIT_REASON_INVLPG
:
6153 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6154 case EXIT_REASON_RDPMC
:
6155 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6156 case EXIT_REASON_RDTSC
:
6157 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6158 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6159 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6160 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6161 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6162 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6164 * VMX instructions trap unconditionally. This allows L1 to
6165 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6168 case EXIT_REASON_CR_ACCESS
:
6169 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6170 case EXIT_REASON_DR_ACCESS
:
6171 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6172 case EXIT_REASON_IO_INSTRUCTION
:
6173 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6174 case EXIT_REASON_MSR_READ
:
6175 case EXIT_REASON_MSR_WRITE
:
6176 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6177 case EXIT_REASON_INVALID_STATE
:
6179 case EXIT_REASON_MWAIT_INSTRUCTION
:
6180 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6181 case EXIT_REASON_MONITOR_INSTRUCTION
:
6182 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6183 case EXIT_REASON_PAUSE_INSTRUCTION
:
6184 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6185 nested_cpu_has2(vmcs12
,
6186 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6187 case EXIT_REASON_MCE_DURING_VMENTRY
:
6189 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6191 case EXIT_REASON_APIC_ACCESS
:
6192 return nested_cpu_has2(vmcs12
,
6193 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6194 case EXIT_REASON_EPT_VIOLATION
:
6195 case EXIT_REASON_EPT_MISCONFIG
:
6197 case EXIT_REASON_PREEMPTION_TIMER
:
6198 return vmcs12
->pin_based_vm_exec_control
&
6199 PIN_BASED_VMX_PREEMPTION_TIMER
;
6200 case EXIT_REASON_WBINVD
:
6201 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6202 case EXIT_REASON_XSETBV
:
6209 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6211 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6212 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6216 * The guest has exited. See if we can fix it or if we need userspace
6219 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6221 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6222 u32 exit_reason
= vmx
->exit_reason
;
6223 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6225 /* If guest state is invalid, start emulating */
6226 if (vmx
->emulation_required
)
6227 return handle_invalid_guest_state(vcpu
);
6230 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
6231 * we did not inject a still-pending event to L1 now because of
6232 * nested_run_pending, we need to re-enable this bit.
6234 if (vmx
->nested
.nested_run_pending
)
6235 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6237 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
6238 exit_reason
== EXIT_REASON_VMRESUME
))
6239 vmx
->nested
.nested_run_pending
= 1;
6241 vmx
->nested
.nested_run_pending
= 0;
6243 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6244 nested_vmx_vmexit(vcpu
);
6248 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6249 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6250 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6255 if (unlikely(vmx
->fail
)) {
6256 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6257 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6258 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6264 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6265 * delivery event since it indicates guest is accessing MMIO.
6266 * The vm-exit can be triggered again after return to guest that
6267 * will cause infinite loop.
6269 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6270 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6271 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6272 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6273 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6274 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6275 vcpu
->run
->internal
.ndata
= 2;
6276 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6277 vcpu
->run
->internal
.data
[1] = exit_reason
;
6281 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6282 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6283 get_vmcs12(vcpu
), vcpu
)))) {
6284 if (vmx_interrupt_allowed(vcpu
)) {
6285 vmx
->soft_vnmi_blocked
= 0;
6286 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6287 vcpu
->arch
.nmi_pending
) {
6289 * This CPU don't support us in finding the end of an
6290 * NMI-blocked window if the guest runs with IRQs
6291 * disabled. So we pull the trigger after 1 s of
6292 * futile waiting, but inform the user about this.
6294 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6295 "state on VCPU %d after 1 s timeout\n",
6296 __func__
, vcpu
->vcpu_id
);
6297 vmx
->soft_vnmi_blocked
= 0;
6301 if (exit_reason
< kvm_vmx_max_exit_handlers
6302 && kvm_vmx_exit_handlers
[exit_reason
])
6303 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6305 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6306 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6311 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6313 if (irr
== -1 || tpr
< irr
) {
6314 vmcs_write32(TPR_THRESHOLD
, 0);
6318 vmcs_write32(TPR_THRESHOLD
, irr
);
6321 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6323 u32 sec_exec_control
;
6326 * There is not point to enable virtualize x2apic without enable
6329 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6330 !vmx_vm_has_apicv(vcpu
->kvm
))
6333 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6336 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6339 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6340 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6342 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6343 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6345 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6347 vmx_set_msr_bitmap(vcpu
);
6350 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6355 if (!vmx_vm_has_apicv(kvm
))
6361 status
= vmcs_read16(GUEST_INTR_STATUS
);
6366 vmcs_write16(GUEST_INTR_STATUS
, status
);
6370 static void vmx_set_rvi(int vector
)
6375 status
= vmcs_read16(GUEST_INTR_STATUS
);
6376 old
= (u8
)status
& 0xff;
6377 if ((u8
)vector
!= old
) {
6379 status
|= (u8
)vector
;
6380 vmcs_write16(GUEST_INTR_STATUS
, status
);
6384 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6389 vmx_set_rvi(max_irr
);
6392 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6394 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6395 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6396 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6397 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6400 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6404 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6405 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6408 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6409 exit_intr_info
= vmx
->exit_intr_info
;
6411 /* Handle machine checks before interrupts are enabled */
6412 if (is_machine_check(exit_intr_info
))
6413 kvm_machine_check();
6415 /* We need to handle NMIs before interrupts are enabled */
6416 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6417 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6418 kvm_before_handle_nmi(&vmx
->vcpu
);
6420 kvm_after_handle_nmi(&vmx
->vcpu
);
6424 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6429 bool idtv_info_valid
;
6431 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6433 if (cpu_has_virtual_nmis()) {
6434 if (vmx
->nmi_known_unmasked
)
6437 * Can't use vmx->exit_intr_info since we're not sure what
6438 * the exit reason is.
6440 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6441 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6442 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6444 * SDM 3: 27.7.1.2 (September 2008)
6445 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6446 * a guest IRET fault.
6447 * SDM 3: 23.2.2 (September 2008)
6448 * Bit 12 is undefined in any of the following cases:
6449 * If the VM exit sets the valid bit in the IDT-vectoring
6450 * information field.
6451 * If the VM exit is due to a double fault.
6453 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6454 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6455 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6456 GUEST_INTR_STATE_NMI
);
6458 vmx
->nmi_known_unmasked
=
6459 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6460 & GUEST_INTR_STATE_NMI
);
6461 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6462 vmx
->vnmi_blocked_time
+=
6463 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6466 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
6467 u32 idt_vectoring_info
,
6468 int instr_len_field
,
6469 int error_code_field
)
6473 bool idtv_info_valid
;
6475 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6477 vcpu
->arch
.nmi_injected
= false;
6478 kvm_clear_exception_queue(vcpu
);
6479 kvm_clear_interrupt_queue(vcpu
);
6481 if (!idtv_info_valid
)
6484 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6486 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6487 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6490 case INTR_TYPE_NMI_INTR
:
6491 vcpu
->arch
.nmi_injected
= true;
6493 * SDM 3: 27.7.1.2 (September 2008)
6494 * Clear bit "block by NMI" before VM entry if a NMI
6497 vmx_set_nmi_mask(vcpu
, false);
6499 case INTR_TYPE_SOFT_EXCEPTION
:
6500 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6502 case INTR_TYPE_HARD_EXCEPTION
:
6503 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6504 u32 err
= vmcs_read32(error_code_field
);
6505 kvm_queue_exception_e(vcpu
, vector
, err
);
6507 kvm_queue_exception(vcpu
, vector
);
6509 case INTR_TYPE_SOFT_INTR
:
6510 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
6512 case INTR_TYPE_EXT_INTR
:
6513 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
6520 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6522 if (is_guest_mode(&vmx
->vcpu
))
6524 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
6525 VM_EXIT_INSTRUCTION_LEN
,
6526 IDT_VECTORING_ERROR_CODE
);
6529 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6531 if (is_guest_mode(vcpu
))
6533 __vmx_complete_interrupts(vcpu
,
6534 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6535 VM_ENTRY_INSTRUCTION_LEN
,
6536 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6538 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6541 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6544 struct perf_guest_switch_msr
*msrs
;
6546 msrs
= perf_guest_get_msrs(&nr_msrs
);
6551 for (i
= 0; i
< nr_msrs
; i
++)
6552 if (msrs
[i
].host
== msrs
[i
].guest
)
6553 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6555 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6559 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6561 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6562 unsigned long debugctlmsr
;
6564 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
6565 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6566 if (vmcs12
->idt_vectoring_info_field
&
6567 VECTORING_INFO_VALID_MASK
) {
6568 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6569 vmcs12
->idt_vectoring_info_field
);
6570 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6571 vmcs12
->vm_exit_instruction_len
);
6572 if (vmcs12
->idt_vectoring_info_field
&
6573 VECTORING_INFO_DELIVER_CODE_MASK
)
6574 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6575 vmcs12
->idt_vectoring_error_code
);
6579 /* Record the guest's net vcpu time for enforced NMI injections. */
6580 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6581 vmx
->entry_time
= ktime_get();
6583 /* Don't enter VMX if guest state is invalid, let the exit handler
6584 start emulation until we arrive back to a valid state */
6585 if (vmx
->emulation_required
)
6588 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6589 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6590 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6591 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6593 /* When single-stepping over STI and MOV SS, we must clear the
6594 * corresponding interruptibility bits in the guest state. Otherwise
6595 * vmentry fails as it then expects bit 14 (BS) in pending debug
6596 * exceptions being set, but that's not correct for the guest debugging
6598 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6599 vmx_set_interrupt_shadow(vcpu
, 0);
6601 atomic_switch_perf_msrs(vmx
);
6602 debugctlmsr
= get_debugctlmsr();
6604 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6606 /* Store host registers */
6607 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
6608 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
6609 "push %%" _ASM_CX
" \n\t"
6610 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6612 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6613 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6615 /* Reload cr2 if changed */
6616 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
6617 "mov %%cr2, %%" _ASM_DX
" \n\t"
6618 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
6620 "mov %%" _ASM_AX
", %%cr2 \n\t"
6622 /* Check if vmlaunch of vmresume is needed */
6623 "cmpl $0, %c[launched](%0) \n\t"
6624 /* Load guest registers. Don't clobber flags. */
6625 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
6626 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
6627 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
6628 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
6629 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
6630 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
6631 #ifdef CONFIG_X86_64
6632 "mov %c[r8](%0), %%r8 \n\t"
6633 "mov %c[r9](%0), %%r9 \n\t"
6634 "mov %c[r10](%0), %%r10 \n\t"
6635 "mov %c[r11](%0), %%r11 \n\t"
6636 "mov %c[r12](%0), %%r12 \n\t"
6637 "mov %c[r13](%0), %%r13 \n\t"
6638 "mov %c[r14](%0), %%r14 \n\t"
6639 "mov %c[r15](%0), %%r15 \n\t"
6641 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
6643 /* Enter guest mode */
6645 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6647 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6649 /* Save guest registers, load host registers, keep flags */
6650 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
6652 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
6653 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
6654 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
6655 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
6656 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
6657 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
6658 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
6659 #ifdef CONFIG_X86_64
6660 "mov %%r8, %c[r8](%0) \n\t"
6661 "mov %%r9, %c[r9](%0) \n\t"
6662 "mov %%r10, %c[r10](%0) \n\t"
6663 "mov %%r11, %c[r11](%0) \n\t"
6664 "mov %%r12, %c[r12](%0) \n\t"
6665 "mov %%r13, %c[r13](%0) \n\t"
6666 "mov %%r14, %c[r14](%0) \n\t"
6667 "mov %%r15, %c[r15](%0) \n\t"
6669 "mov %%cr2, %%" _ASM_AX
" \n\t"
6670 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
6672 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
6673 "setbe %c[fail](%0) \n\t"
6674 ".pushsection .rodata \n\t"
6675 ".global vmx_return \n\t"
6676 "vmx_return: " _ASM_PTR
" 2b \n\t"
6678 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6679 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6680 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6681 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6682 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6683 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6684 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6685 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6686 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6687 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6688 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6689 #ifdef CONFIG_X86_64
6690 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6691 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6692 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6693 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6694 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6695 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6696 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6697 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6699 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6700 [wordsize
]"i"(sizeof(ulong
))
6702 #ifdef CONFIG_X86_64
6703 , "rax", "rbx", "rdi", "rsi"
6704 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6706 , "eax", "ebx", "edi", "esi"
6710 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6712 update_debugctlmsr(debugctlmsr
);
6714 #ifndef CONFIG_X86_64
6716 * The sysexit path does not restore ds/es, so we must set them to
6717 * a reasonable value ourselves.
6719 * We can't defer this to vmx_load_host_state() since that function
6720 * may be executed in interrupt context, which saves and restore segments
6721 * around it, nullifying its effect.
6723 loadsegment(ds
, __USER_DS
);
6724 loadsegment(es
, __USER_DS
);
6727 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6728 | (1 << VCPU_EXREG_RFLAGS
)
6729 | (1 << VCPU_EXREG_CPL
)
6730 | (1 << VCPU_EXREG_PDPTR
)
6731 | (1 << VCPU_EXREG_SEGMENTS
)
6732 | (1 << VCPU_EXREG_CR3
));
6733 vcpu
->arch
.regs_dirty
= 0;
6735 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6737 if (is_guest_mode(vcpu
)) {
6738 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6739 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6740 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6741 vmcs12
->idt_vectoring_error_code
=
6742 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6743 vmcs12
->vm_exit_instruction_len
=
6744 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6748 vmx
->loaded_vmcs
->launched
= 1;
6750 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6751 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6753 vmx_complete_atomic_exit(vmx
);
6754 vmx_recover_nmi_blocking(vmx
);
6755 vmx_complete_interrupts(vmx
);
6758 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6760 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6764 free_loaded_vmcs(vmx
->loaded_vmcs
);
6765 kfree(vmx
->guest_msrs
);
6766 kvm_vcpu_uninit(vcpu
);
6767 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6770 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6773 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6777 return ERR_PTR(-ENOMEM
);
6781 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6785 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6787 if (!vmx
->guest_msrs
) {
6791 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6792 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6793 if (!vmx
->loaded_vmcs
->vmcs
)
6796 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6797 loaded_vmcs_init(vmx
->loaded_vmcs
);
6802 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6803 vmx
->vcpu
.cpu
= cpu
;
6804 err
= vmx_vcpu_setup(vmx
);
6805 vmx_vcpu_put(&vmx
->vcpu
);
6809 if (vm_need_virtualize_apic_accesses(kvm
))
6810 err
= alloc_apic_access_page(kvm
);
6815 if (!kvm
->arch
.ept_identity_map_addr
)
6816 kvm
->arch
.ept_identity_map_addr
=
6817 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6819 if (alloc_identity_pagetable(kvm
) != 0)
6821 if (!init_rmode_identity_map(kvm
))
6825 vmx
->nested
.current_vmptr
= -1ull;
6826 vmx
->nested
.current_vmcs12
= NULL
;
6831 free_loaded_vmcs(vmx
->loaded_vmcs
);
6833 kfree(vmx
->guest_msrs
);
6835 kvm_vcpu_uninit(&vmx
->vcpu
);
6838 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6839 return ERR_PTR(err
);
6842 static void __init
vmx_check_processor_compat(void *rtn
)
6844 struct vmcs_config vmcs_conf
;
6847 if (setup_vmcs_config(&vmcs_conf
) < 0)
6849 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6850 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6851 smp_processor_id());
6856 static int get_ept_level(void)
6858 return VMX_EPT_DEFAULT_GAW
+ 1;
6861 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6865 /* For VT-d and EPT combination
6866 * 1. MMIO: always map as UC
6868 * a. VT-d without snooping control feature: can't guarantee the
6869 * result, try to trust guest.
6870 * b. VT-d with snooping control feature: snooping control feature of
6871 * VT-d engine can guarantee the cache correctness. Just set it
6872 * to WB to keep consistent with host. So the same as item 3.
6873 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6874 * consistent with host MTRR
6877 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6878 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6879 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6880 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6881 VMX_EPT_MT_EPTE_SHIFT
;
6883 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6889 static int vmx_get_lpage_level(void)
6891 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6892 return PT_DIRECTORY_LEVEL
;
6894 /* For shadow and EPT supported 1GB page */
6895 return PT_PDPE_LEVEL
;
6898 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6900 struct kvm_cpuid_entry2
*best
;
6901 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6904 vmx
->rdtscp_enabled
= false;
6905 if (vmx_rdtscp_supported()) {
6906 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6907 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6908 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6909 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6910 vmx
->rdtscp_enabled
= true;
6912 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6913 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6919 /* Exposing INVPCID only when PCID is exposed */
6920 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
6921 if (vmx_invpcid_supported() &&
6922 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
6923 guest_cpuid_has_pcid(vcpu
)) {
6924 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6925 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
6926 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6929 if (cpu_has_secondary_exec_ctrls()) {
6930 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6931 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
6932 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6936 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
6940 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6942 if (func
== 1 && nested
)
6943 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6947 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6948 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6949 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6950 * guest in a way that will both be appropriate to L1's requests, and our
6951 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6952 * function also has additional necessary side-effects, like setting various
6953 * vcpu->arch fields.
6955 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6957 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6960 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6961 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6962 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6963 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6964 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6965 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6966 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6967 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6968 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6969 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6970 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6971 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6972 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6973 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6974 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6975 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6976 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6977 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6978 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6979 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6980 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6981 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6982 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6983 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6984 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6985 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6986 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6987 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6988 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6989 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6990 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6991 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6992 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6993 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6994 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6995 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6997 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6998 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6999 vmcs12
->vm_entry_intr_info_field
);
7000 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7001 vmcs12
->vm_entry_exception_error_code
);
7002 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7003 vmcs12
->vm_entry_instruction_len
);
7004 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7005 vmcs12
->guest_interruptibility_info
);
7006 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
7007 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7008 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7009 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
7010 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7011 vmcs12
->guest_pending_dbg_exceptions
);
7012 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7013 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7015 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7017 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7018 (vmcs_config
.pin_based_exec_ctrl
|
7019 vmcs12
->pin_based_vm_exec_control
));
7021 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7022 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7023 vmcs12
->vmx_preemption_timer_value
);
7026 * Whether page-faults are trapped is determined by a combination of
7027 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7028 * If enable_ept, L0 doesn't care about page faults and we should
7029 * set all of these to L1's desires. However, if !enable_ept, L0 does
7030 * care about (at least some) page faults, and because it is not easy
7031 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7032 * to exit on each and every L2 page fault. This is done by setting
7033 * MASK=MATCH=0 and (see below) EB.PF=1.
7034 * Note that below we don't need special code to set EB.PF beyond the
7035 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7036 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7037 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7039 * A problem with this approach (when !enable_ept) is that L1 may be
7040 * injected with more page faults than it asked for. This could have
7041 * caused problems, but in practice existing hypervisors don't care.
7042 * To fix this, we will need to emulate the PFEC checking (on the L1
7043 * page tables), using walk_addr(), when injecting PFs to L1.
7045 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7046 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7047 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7048 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7050 if (cpu_has_secondary_exec_ctrls()) {
7051 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7052 if (!vmx
->rdtscp_enabled
)
7053 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7054 /* Take the following fields only from vmcs12 */
7055 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7056 if (nested_cpu_has(vmcs12
,
7057 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7058 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7060 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7062 * Translate L1 physical address to host physical
7063 * address for vmcs02. Keep the page pinned, so this
7064 * physical address remains valid. We keep a reference
7065 * to it so we can release it later.
7067 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7068 nested_release_page(vmx
->nested
.apic_access_page
);
7069 vmx
->nested
.apic_access_page
=
7070 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7072 * If translation failed, no matter: This feature asks
7073 * to exit when accessing the given address, and if it
7074 * can never be accessed, this feature won't do
7077 if (!vmx
->nested
.apic_access_page
)
7079 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7081 vmcs_write64(APIC_ACCESS_ADDR
,
7082 page_to_phys(vmx
->nested
.apic_access_page
));
7085 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7090 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7091 * Some constant fields are set here by vmx_set_constant_host_state().
7092 * Other fields are different per CPU, and will be set later when
7093 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7095 vmx_set_constant_host_state();
7098 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7099 * entry, but only if the current (host) sp changed from the value
7100 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7101 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7102 * here we just force the write to happen on entry.
7106 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7107 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7108 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7109 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7110 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7112 * Merging of IO and MSR bitmaps not currently supported.
7113 * Rather, exit every time.
7115 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7116 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7117 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7119 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7121 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7122 * bitwise-or of what L1 wants to trap for L2, and what we want to
7123 * trap. Note that CR0.TS also needs updating - we do this later.
7125 update_exception_bitmap(vcpu
);
7126 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7127 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7129 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
7130 vmcs_write32(VM_EXIT_CONTROLS
,
7131 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
7132 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
7133 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7135 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
7136 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7137 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7138 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7141 set_cr4_guest_host_mask(vmx
);
7143 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7144 vmcs_write64(TSC_OFFSET
,
7145 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7147 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7151 * Trivially support vpid by letting L2s share their parent
7152 * L1's vpid. TODO: move to a more elaborate solution, giving
7153 * each L2 its own vpid and exposing the vpid feature to L1.
7155 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7156 vmx_flush_tlb(vcpu
);
7159 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7160 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7161 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7162 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7164 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7165 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7166 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7169 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7170 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7171 * The CR0_READ_SHADOW is what L2 should have expected to read given
7172 * the specifications by L1; It's not enough to take
7173 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7174 * have more bits than L1 expected.
7176 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7177 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7179 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7180 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7182 /* shadow page tables on either EPT or shadow page tables */
7183 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7184 kvm_mmu_reset_context(vcpu
);
7186 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7187 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7191 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7192 * for running an L2 nested guest.
7194 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7196 struct vmcs12
*vmcs12
;
7197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7199 struct loaded_vmcs
*vmcs02
;
7201 if (!nested_vmx_check_permission(vcpu
) ||
7202 !nested_vmx_check_vmcs12(vcpu
))
7205 skip_emulated_instruction(vcpu
);
7206 vmcs12
= get_vmcs12(vcpu
);
7209 * The nested entry process starts with enforcing various prerequisites
7210 * on vmcs12 as required by the Intel SDM, and act appropriately when
7211 * they fail: As the SDM explains, some conditions should cause the
7212 * instruction to fail, while others will cause the instruction to seem
7213 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7214 * To speed up the normal (success) code path, we should avoid checking
7215 * for misconfigurations which will anyway be caught by the processor
7216 * when using the merged vmcs02.
7218 if (vmcs12
->launch_state
== launch
) {
7219 nested_vmx_failValid(vcpu
,
7220 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7221 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7225 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7226 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7227 /*TODO: Also verify bits beyond physical address width are 0*/
7228 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7232 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7233 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7234 /*TODO: Also verify bits beyond physical address width are 0*/
7235 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7239 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7240 vmcs12
->vm_exit_msr_load_count
> 0 ||
7241 vmcs12
->vm_exit_msr_store_count
> 0) {
7242 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7244 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7248 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7249 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7250 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7251 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7252 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7253 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7254 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7255 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7256 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7257 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7259 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7263 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7264 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7265 nested_vmx_failValid(vcpu
,
7266 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7270 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7271 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7272 nested_vmx_entry_failure(vcpu
, vmcs12
,
7273 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7276 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7277 nested_vmx_entry_failure(vcpu
, vmcs12
,
7278 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
7283 * We're finally done with prerequisite checking, and can start with
7287 vmcs02
= nested_get_current_vmcs02(vmx
);
7291 enter_guest_mode(vcpu
);
7293 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
7296 vmx
->loaded_vmcs
= vmcs02
;
7298 vmx_vcpu_load(vcpu
, cpu
);
7302 vmx_segment_cache_clear(vmx
);
7304 vmcs12
->launch_state
= 1;
7306 prepare_vmcs02(vcpu
, vmcs12
);
7309 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7310 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7311 * returned as far as L1 is concerned. It will only return (and set
7312 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7318 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7319 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7320 * This function returns the new value we should put in vmcs12.guest_cr0.
7321 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7322 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7323 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7324 * didn't trap the bit, because if L1 did, so would L0).
7325 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7326 * been modified by L2, and L1 knows it. So just leave the old value of
7327 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7328 * isn't relevant, because if L0 traps this bit it can set it to anything.
7329 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7330 * changed these bits, and therefore they need to be updated, but L0
7331 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7332 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
7334 static inline unsigned long
7335 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7338 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
7339 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
7340 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
7341 vcpu
->arch
.cr0_guest_owned_bits
));
7344 static inline unsigned long
7345 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7348 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
7349 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
7350 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
7351 vcpu
->arch
.cr4_guest_owned_bits
));
7355 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7356 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7357 * and this function updates it to reflect the changes to the guest state while
7358 * L2 was running (and perhaps made some exits which were handled directly by L0
7359 * without going back to L1), and to reflect the exit reason.
7360 * Note that we do not have to copy here all VMCS fields, just those that
7361 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7362 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7363 * which already writes to vmcs12 directly.
7365 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7367 /* update guest state fields: */
7368 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
7369 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
7371 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
7372 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
7373 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
7374 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
7376 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
7377 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
7378 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
7379 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
7380 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
7381 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
7382 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
7383 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
7384 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
7385 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
7386 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
7387 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
7388 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
7389 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
7390 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
7391 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
7392 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
7393 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
7394 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
7395 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
7396 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
7397 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
7398 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
7399 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
7400 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
7401 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
7402 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
7403 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
7404 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
7405 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
7406 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
7407 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
7408 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
7409 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
7410 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
7411 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
7413 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
7414 vmcs12
->guest_interruptibility_info
=
7415 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
7416 vmcs12
->guest_pending_dbg_exceptions
=
7417 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
7419 vmcs12
->vm_entry_controls
=
7420 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
7421 (vmcs_read32(VM_ENTRY_CONTROLS
) & VM_ENTRY_IA32E_MODE
);
7423 /* TODO: These cannot have changed unless we have MSR bitmaps and
7424 * the relevant bit asks not to trap the change */
7425 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
7426 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
7427 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
7428 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
7429 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
7430 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
7432 /* update exit information fields: */
7434 vmcs12
->vm_exit_reason
= to_vmx(vcpu
)->exit_reason
;
7435 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7437 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7438 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7439 vmcs12
->idt_vectoring_info_field
= to_vmx(vcpu
)->idt_vectoring_info
;
7440 vmcs12
->idt_vectoring_error_code
=
7441 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
7442 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7443 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7445 /* clear vm-entry fields which are to be cleared on exit */
7446 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
7447 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
7451 * A part of what we need to when the nested L2 guest exits and we want to
7452 * run its L1 parent, is to reset L1's guest state to the host state specified
7454 * This function is to be called not only on normal nested exit, but also on
7455 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7456 * Failures During or After Loading Guest State").
7457 * This function should be called when the active VMCS is L1's (vmcs01).
7459 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
7460 struct vmcs12
*vmcs12
)
7462 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
7463 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7464 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7465 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7467 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7468 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7470 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7471 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7472 vmx_set_rflags(vcpu
, X86_EFLAGS_BIT1
);
7474 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7475 * actually changed, because it depends on the current state of
7476 * fpu_active (which may have changed).
7477 * Note that vmx_set_cr0 refers to efer set above.
7479 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
7481 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7482 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7483 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7485 update_exception_bitmap(vcpu
);
7486 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
7487 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7490 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7491 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7493 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
7494 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
7496 /* shadow page tables on either EPT or shadow page tables */
7497 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
7498 kvm_mmu_reset_context(vcpu
);
7502 * Trivially support vpid by letting L2s share their parent
7503 * L1's vpid. TODO: move to a more elaborate solution, giving
7504 * each L2 its own vpid and exposing the vpid feature to L1.
7506 vmx_flush_tlb(vcpu
);
7510 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
7511 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
7512 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
7513 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
7514 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
7515 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
7516 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
7517 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
7518 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
7519 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
7520 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
7521 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
7522 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
7523 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
7524 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
7526 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
7527 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
7528 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7529 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
7530 vmcs12
->host_ia32_perf_global_ctrl
);
7532 kvm_set_dr(vcpu
, 7, 0x400);
7533 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
7537 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7538 * and modify vmcs12 to make it see what it would expect to see there if
7539 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7541 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
7543 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7545 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7547 leave_guest_mode(vcpu
);
7548 prepare_vmcs12(vcpu
, vmcs12
);
7551 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7553 vmx_vcpu_load(vcpu
, cpu
);
7557 vmx_segment_cache_clear(vmx
);
7559 /* if no vmcs02 cache requested, remove the one we used */
7560 if (VMCS02_POOL_SIZE
== 0)
7561 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
7563 load_vmcs12_host_state(vcpu
, vmcs12
);
7565 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7566 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7568 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7571 /* Unpin physical memory we referred to in vmcs02 */
7572 if (vmx
->nested
.apic_access_page
) {
7573 nested_release_page(vmx
->nested
.apic_access_page
);
7574 vmx
->nested
.apic_access_page
= 0;
7578 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7579 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7580 * success or failure flag accordingly.
7582 if (unlikely(vmx
->fail
)) {
7584 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
7586 nested_vmx_succeed(vcpu
);
7590 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7591 * 23.7 "VM-entry failures during or after loading guest state" (this also
7592 * lists the acceptable exit-reason and exit-qualification parameters).
7593 * It should only be called before L2 actually succeeded to run, and when
7594 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7596 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
7597 struct vmcs12
*vmcs12
,
7598 u32 reason
, unsigned long qualification
)
7600 load_vmcs12_host_state(vcpu
, vmcs12
);
7601 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
7602 vmcs12
->exit_qualification
= qualification
;
7603 nested_vmx_succeed(vcpu
);
7606 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7607 struct x86_instruction_info
*info
,
7608 enum x86_intercept_stage stage
)
7610 return X86EMUL_CONTINUE
;
7613 static struct kvm_x86_ops vmx_x86_ops
= {
7614 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7615 .disabled_by_bios
= vmx_disabled_by_bios
,
7616 .hardware_setup
= hardware_setup
,
7617 .hardware_unsetup
= hardware_unsetup
,
7618 .check_processor_compatibility
= vmx_check_processor_compat
,
7619 .hardware_enable
= hardware_enable
,
7620 .hardware_disable
= hardware_disable
,
7621 .cpu_has_accelerated_tpr
= report_flexpriority
,
7623 .vcpu_create
= vmx_create_vcpu
,
7624 .vcpu_free
= vmx_free_vcpu
,
7625 .vcpu_reset
= vmx_vcpu_reset
,
7627 .prepare_guest_switch
= vmx_save_host_state
,
7628 .vcpu_load
= vmx_vcpu_load
,
7629 .vcpu_put
= vmx_vcpu_put
,
7631 .update_db_bp_intercept
= update_exception_bitmap
,
7632 .get_msr
= vmx_get_msr
,
7633 .set_msr
= vmx_set_msr
,
7634 .get_segment_base
= vmx_get_segment_base
,
7635 .get_segment
= vmx_get_segment
,
7636 .set_segment
= vmx_set_segment
,
7637 .get_cpl
= vmx_get_cpl
,
7638 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7639 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7640 .decache_cr3
= vmx_decache_cr3
,
7641 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7642 .set_cr0
= vmx_set_cr0
,
7643 .set_cr3
= vmx_set_cr3
,
7644 .set_cr4
= vmx_set_cr4
,
7645 .set_efer
= vmx_set_efer
,
7646 .get_idt
= vmx_get_idt
,
7647 .set_idt
= vmx_set_idt
,
7648 .get_gdt
= vmx_get_gdt
,
7649 .set_gdt
= vmx_set_gdt
,
7650 .set_dr7
= vmx_set_dr7
,
7651 .cache_reg
= vmx_cache_reg
,
7652 .get_rflags
= vmx_get_rflags
,
7653 .set_rflags
= vmx_set_rflags
,
7654 .fpu_activate
= vmx_fpu_activate
,
7655 .fpu_deactivate
= vmx_fpu_deactivate
,
7657 .tlb_flush
= vmx_flush_tlb
,
7659 .run
= vmx_vcpu_run
,
7660 .handle_exit
= vmx_handle_exit
,
7661 .skip_emulated_instruction
= skip_emulated_instruction
,
7662 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7663 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7664 .patch_hypercall
= vmx_patch_hypercall
,
7665 .set_irq
= vmx_inject_irq
,
7666 .set_nmi
= vmx_inject_nmi
,
7667 .queue_exception
= vmx_queue_exception
,
7668 .cancel_injection
= vmx_cancel_injection
,
7669 .interrupt_allowed
= vmx_interrupt_allowed
,
7670 .nmi_allowed
= vmx_nmi_allowed
,
7671 .get_nmi_mask
= vmx_get_nmi_mask
,
7672 .set_nmi_mask
= vmx_set_nmi_mask
,
7673 .enable_nmi_window
= enable_nmi_window
,
7674 .enable_irq_window
= enable_irq_window
,
7675 .update_cr8_intercept
= update_cr8_intercept
,
7676 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
7677 .vm_has_apicv
= vmx_vm_has_apicv
,
7678 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
7679 .hwapic_irr_update
= vmx_hwapic_irr_update
,
7680 .hwapic_isr_update
= vmx_hwapic_isr_update
,
7682 .set_tss_addr
= vmx_set_tss_addr
,
7683 .get_tdp_level
= get_ept_level
,
7684 .get_mt_mask
= vmx_get_mt_mask
,
7686 .get_exit_info
= vmx_get_exit_info
,
7688 .get_lpage_level
= vmx_get_lpage_level
,
7690 .cpuid_update
= vmx_cpuid_update
,
7692 .rdtscp_supported
= vmx_rdtscp_supported
,
7693 .invpcid_supported
= vmx_invpcid_supported
,
7695 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7697 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7699 .set_tsc_khz
= vmx_set_tsc_khz
,
7700 .read_tsc_offset
= vmx_read_tsc_offset
,
7701 .write_tsc_offset
= vmx_write_tsc_offset
,
7702 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7703 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7704 .read_l1_tsc
= vmx_read_l1_tsc
,
7706 .set_tdp_cr3
= vmx_set_cr3
,
7708 .check_intercept
= vmx_check_intercept
,
7711 static int __init
vmx_init(void)
7715 rdmsrl_safe(MSR_EFER
, &host_efer
);
7717 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7718 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7720 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7721 if (!vmx_io_bitmap_a
)
7726 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7727 if (!vmx_io_bitmap_b
)
7730 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7731 if (!vmx_msr_bitmap_legacy
)
7734 vmx_msr_bitmap_legacy_x2apic
=
7735 (unsigned long *)__get_free_page(GFP_KERNEL
);
7736 if (!vmx_msr_bitmap_legacy_x2apic
)
7739 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7740 if (!vmx_msr_bitmap_longmode
)
7743 vmx_msr_bitmap_longmode_x2apic
=
7744 (unsigned long *)__get_free_page(GFP_KERNEL
);
7745 if (!vmx_msr_bitmap_longmode_x2apic
)
7749 * Allow direct access to the PC debug port (it is often used for I/O
7750 * delays, but the vmexits simply slow things down).
7752 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7753 clear_bit(0x80, vmx_io_bitmap_a
);
7755 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7757 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7758 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7760 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7762 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7763 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7768 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
7769 crash_vmclear_local_loaded_vmcss
);
7772 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7773 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7774 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7775 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7776 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7777 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7778 memcpy(vmx_msr_bitmap_legacy_x2apic
,
7779 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
7780 memcpy(vmx_msr_bitmap_longmode_x2apic
,
7781 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
7783 if (enable_apicv_reg_vid
) {
7784 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
7785 vmx_disable_intercept_msr_read_x2apic(msr
);
7787 /* According SDM, in x2apic mode, the whole id reg is used.
7788 * But in KVM, it only use the highest eight bits. Need to
7790 vmx_enable_intercept_msr_read_x2apic(0x802);
7792 vmx_enable_intercept_msr_read_x2apic(0x839);
7794 vmx_disable_intercept_msr_write_x2apic(0x808);
7796 vmx_disable_intercept_msr_write_x2apic(0x80b);
7798 vmx_disable_intercept_msr_write_x2apic(0x83f);
7802 kvm_mmu_set_mask_ptes(0ull,
7803 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
7804 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
7805 0ull, VMX_EPT_EXECUTABLE_MASK
);
7806 ept_set_mmio_spte_mask();
7814 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7816 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
7818 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7820 free_page((unsigned long)vmx_io_bitmap_b
);
7822 free_page((unsigned long)vmx_io_bitmap_a
);
7826 static void __exit
vmx_exit(void)
7828 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
7829 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
7830 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7831 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7832 free_page((unsigned long)vmx_io_bitmap_b
);
7833 free_page((unsigned long)vmx_io_bitmap_a
);
7836 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
7843 module_init(vmx_init
)
7844 module_exit(vmx_exit
)