2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending
;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page
*apic_access_page
;
376 u64 msr_ia32_feature_control
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
422 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
423 * non-nested (L1) guest, it always points to vmcs01. For a nested
424 * guest (L2), it points to a different VMCS.
426 struct loaded_vmcs vmcs01
;
427 struct loaded_vmcs
*loaded_vmcs
;
428 bool __launched
; /* temporary, used in vmx_vcpu_run */
429 struct msr_autoload
{
431 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
432 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
436 u16 fs_sel
, gs_sel
, ldt_sel
;
440 int gs_ldt_reload_needed
;
441 int fs_reload_needed
;
446 struct kvm_segment segs
[8];
449 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
450 struct kvm_save_segment
{
458 bool emulation_required
;
460 /* Support for vnmi-less CPUs */
461 int soft_vnmi_blocked
;
463 s64 vnmi_blocked_time
;
468 /* Posted interrupt descriptor */
469 struct pi_desc pi_desc
;
471 /* Support for a guest hypervisor (nested VMX) */
472 struct nested_vmx nested
;
475 enum segment_cache_field
{
484 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
486 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
489 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
490 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
491 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
492 [number##_HIGH] = VMCS12_OFFSET(name)+4
495 static const unsigned long shadow_read_only_fields
[] = {
497 * We do NOT shadow fields that are modified when L0
498 * traps and emulates any vmx instruction (e.g. VMPTRLD,
499 * VMXON...) executed by L1.
500 * For example, VM_INSTRUCTION_ERROR is read
501 * by L1 if a vmx instruction fails (part of the error path).
502 * Note the code assumes this logic. If for some reason
503 * we start shadowing these fields then we need to
504 * force a shadow sync when L0 emulates vmx instructions
505 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
506 * by nested_vmx_failValid)
510 VM_EXIT_INSTRUCTION_LEN
,
511 IDT_VECTORING_INFO_FIELD
,
512 IDT_VECTORING_ERROR_CODE
,
513 VM_EXIT_INTR_ERROR_CODE
,
515 GUEST_LINEAR_ADDRESS
,
516 GUEST_PHYSICAL_ADDRESS
518 static const int max_shadow_read_only_fields
=
519 ARRAY_SIZE(shadow_read_only_fields
);
521 static const unsigned long shadow_read_write_fields
[] = {
527 GUEST_INTERRUPTIBILITY_INFO
,
539 CPU_BASED_VM_EXEC_CONTROL
,
540 VM_ENTRY_EXCEPTION_ERROR_CODE
,
541 VM_ENTRY_INTR_INFO_FIELD
,
542 VM_ENTRY_INSTRUCTION_LEN
,
543 VM_ENTRY_EXCEPTION_ERROR_CODE
,
549 static const int max_shadow_read_write_fields
=
550 ARRAY_SIZE(shadow_read_write_fields
);
552 static const unsigned short vmcs_field_to_offset_table
[] = {
553 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
554 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
555 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
556 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
557 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
558 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
559 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
560 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
561 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
562 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
563 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
564 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
565 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
566 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
567 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
568 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
569 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
570 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
571 FIELD64(MSR_BITMAP
, msr_bitmap
),
572 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
573 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
574 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
575 FIELD64(TSC_OFFSET
, tsc_offset
),
576 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
577 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
578 FIELD64(EPT_POINTER
, ept_pointer
),
579 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
580 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
581 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
582 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
583 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
584 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
585 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
586 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
587 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
588 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
589 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
590 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
591 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
592 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
593 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
594 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
595 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
596 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
597 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
598 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
599 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
600 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
601 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
602 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
603 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
604 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
605 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
606 FIELD(TPR_THRESHOLD
, tpr_threshold
),
607 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
608 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
609 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
610 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
611 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
612 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
613 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
614 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
615 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
616 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
617 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
618 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
619 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
620 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
621 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
622 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
623 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
624 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
625 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
626 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
627 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
628 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
629 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
630 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
631 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
632 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
633 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
634 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
635 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
636 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
637 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
638 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
639 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
640 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
641 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
642 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
643 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
644 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
645 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
646 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
647 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
648 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
649 FIELD(GUEST_CR0
, guest_cr0
),
650 FIELD(GUEST_CR3
, guest_cr3
),
651 FIELD(GUEST_CR4
, guest_cr4
),
652 FIELD(GUEST_ES_BASE
, guest_es_base
),
653 FIELD(GUEST_CS_BASE
, guest_cs_base
),
654 FIELD(GUEST_SS_BASE
, guest_ss_base
),
655 FIELD(GUEST_DS_BASE
, guest_ds_base
),
656 FIELD(GUEST_FS_BASE
, guest_fs_base
),
657 FIELD(GUEST_GS_BASE
, guest_gs_base
),
658 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
659 FIELD(GUEST_TR_BASE
, guest_tr_base
),
660 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
661 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
662 FIELD(GUEST_DR7
, guest_dr7
),
663 FIELD(GUEST_RSP
, guest_rsp
),
664 FIELD(GUEST_RIP
, guest_rip
),
665 FIELD(GUEST_RFLAGS
, guest_rflags
),
666 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
667 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
668 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
669 FIELD(HOST_CR0
, host_cr0
),
670 FIELD(HOST_CR3
, host_cr3
),
671 FIELD(HOST_CR4
, host_cr4
),
672 FIELD(HOST_FS_BASE
, host_fs_base
),
673 FIELD(HOST_GS_BASE
, host_gs_base
),
674 FIELD(HOST_TR_BASE
, host_tr_base
),
675 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
676 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
677 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
678 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
679 FIELD(HOST_RSP
, host_rsp
),
680 FIELD(HOST_RIP
, host_rip
),
682 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
684 static inline short vmcs_field_to_offset(unsigned long field
)
686 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
688 return vmcs_field_to_offset_table
[field
];
691 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
693 return to_vmx(vcpu
)->nested
.current_vmcs12
;
696 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
698 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
699 if (is_error_page(page
))
705 static void nested_release_page(struct page
*page
)
707 kvm_release_page_dirty(page
);
710 static void nested_release_page_clean(struct page
*page
)
712 kvm_release_page_clean(page
);
715 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
716 static u64
construct_eptp(unsigned long root_hpa
);
717 static void kvm_cpu_vmxon(u64 addr
);
718 static void kvm_cpu_vmxoff(void);
719 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
720 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
721 struct kvm_segment
*var
, int seg
);
722 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
723 struct kvm_segment
*var
, int seg
);
724 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
725 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
726 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
727 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
728 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
730 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
731 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
733 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
734 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
736 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
737 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
739 static unsigned long *vmx_io_bitmap_a
;
740 static unsigned long *vmx_io_bitmap_b
;
741 static unsigned long *vmx_msr_bitmap_legacy
;
742 static unsigned long *vmx_msr_bitmap_longmode
;
743 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
744 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
745 static unsigned long *vmx_vmread_bitmap
;
746 static unsigned long *vmx_vmwrite_bitmap
;
748 static bool cpu_has_load_ia32_efer
;
749 static bool cpu_has_load_perf_global_ctrl
;
751 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
752 static DEFINE_SPINLOCK(vmx_vpid_lock
);
754 static struct vmcs_config
{
758 u32 pin_based_exec_ctrl
;
759 u32 cpu_based_exec_ctrl
;
760 u32 cpu_based_2nd_exec_ctrl
;
765 static struct vmx_capability
{
770 #define VMX_SEGMENT_FIELD(seg) \
771 [VCPU_SREG_##seg] = { \
772 .selector = GUEST_##seg##_SELECTOR, \
773 .base = GUEST_##seg##_BASE, \
774 .limit = GUEST_##seg##_LIMIT, \
775 .ar_bytes = GUEST_##seg##_AR_BYTES, \
778 static const struct kvm_vmx_segment_field
{
783 } kvm_vmx_segment_fields
[] = {
784 VMX_SEGMENT_FIELD(CS
),
785 VMX_SEGMENT_FIELD(DS
),
786 VMX_SEGMENT_FIELD(ES
),
787 VMX_SEGMENT_FIELD(FS
),
788 VMX_SEGMENT_FIELD(GS
),
789 VMX_SEGMENT_FIELD(SS
),
790 VMX_SEGMENT_FIELD(TR
),
791 VMX_SEGMENT_FIELD(LDTR
),
794 static u64 host_efer
;
796 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
799 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
800 * away by decrementing the array size.
802 static const u32 vmx_msr_index
[] = {
804 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
806 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
808 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
810 static inline bool is_page_fault(u32 intr_info
)
812 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
813 INTR_INFO_VALID_MASK
)) ==
814 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
817 static inline bool is_no_device(u32 intr_info
)
819 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
820 INTR_INFO_VALID_MASK
)) ==
821 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
824 static inline bool is_invalid_opcode(u32 intr_info
)
826 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
827 INTR_INFO_VALID_MASK
)) ==
828 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
831 static inline bool is_external_interrupt(u32 intr_info
)
833 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
834 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
837 static inline bool is_machine_check(u32 intr_info
)
839 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
840 INTR_INFO_VALID_MASK
)) ==
841 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
844 static inline bool cpu_has_vmx_msr_bitmap(void)
846 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
849 static inline bool cpu_has_vmx_tpr_shadow(void)
851 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
854 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
856 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
859 static inline bool cpu_has_secondary_exec_ctrls(void)
861 return vmcs_config
.cpu_based_exec_ctrl
&
862 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
865 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
867 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
868 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
871 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
873 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
874 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
877 static inline bool cpu_has_vmx_apic_register_virt(void)
879 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
880 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
883 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
885 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
886 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
889 static inline bool cpu_has_vmx_posted_intr(void)
891 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
894 static inline bool cpu_has_vmx_apicv(void)
896 return cpu_has_vmx_apic_register_virt() &&
897 cpu_has_vmx_virtual_intr_delivery() &&
898 cpu_has_vmx_posted_intr();
901 static inline bool cpu_has_vmx_flexpriority(void)
903 return cpu_has_vmx_tpr_shadow() &&
904 cpu_has_vmx_virtualize_apic_accesses();
907 static inline bool cpu_has_vmx_ept_execute_only(void)
909 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
912 static inline bool cpu_has_vmx_eptp_uncacheable(void)
914 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
917 static inline bool cpu_has_vmx_eptp_writeback(void)
919 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
922 static inline bool cpu_has_vmx_ept_2m_page(void)
924 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
927 static inline bool cpu_has_vmx_ept_1g_page(void)
929 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
932 static inline bool cpu_has_vmx_ept_4levels(void)
934 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
937 static inline bool cpu_has_vmx_ept_ad_bits(void)
939 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
942 static inline bool cpu_has_vmx_invept_context(void)
944 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
947 static inline bool cpu_has_vmx_invept_global(void)
949 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
952 static inline bool cpu_has_vmx_invvpid_single(void)
954 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
957 static inline bool cpu_has_vmx_invvpid_global(void)
959 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
962 static inline bool cpu_has_vmx_ept(void)
964 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
965 SECONDARY_EXEC_ENABLE_EPT
;
968 static inline bool cpu_has_vmx_unrestricted_guest(void)
970 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
971 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
974 static inline bool cpu_has_vmx_ple(void)
976 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
977 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
980 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
982 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
985 static inline bool cpu_has_vmx_vpid(void)
987 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
988 SECONDARY_EXEC_ENABLE_VPID
;
991 static inline bool cpu_has_vmx_rdtscp(void)
993 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
994 SECONDARY_EXEC_RDTSCP
;
997 static inline bool cpu_has_vmx_invpcid(void)
999 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1000 SECONDARY_EXEC_ENABLE_INVPCID
;
1003 static inline bool cpu_has_virtual_nmis(void)
1005 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1008 static inline bool cpu_has_vmx_wbinvd_exit(void)
1010 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1011 SECONDARY_EXEC_WBINVD_EXITING
;
1014 static inline bool cpu_has_vmx_shadow_vmcs(void)
1017 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1018 /* check if the cpu supports writing r/o exit information fields */
1019 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1022 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1023 SECONDARY_EXEC_SHADOW_VMCS
;
1026 static inline bool report_flexpriority(void)
1028 return flexpriority_enabled
;
1031 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1033 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1036 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1038 return (vmcs12
->cpu_based_vm_exec_control
&
1039 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1040 (vmcs12
->secondary_vm_exec_control
& bit
);
1043 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1045 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1048 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1050 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1053 static inline bool is_exception(u32 intr_info
)
1055 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1056 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1059 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
1060 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1061 struct vmcs12
*vmcs12
,
1062 u32 reason
, unsigned long qualification
);
1064 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1068 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1069 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1074 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1080 } operand
= { vpid
, 0, gva
};
1082 asm volatile (__ex(ASM_VMX_INVVPID
)
1083 /* CF==1 or ZF==1 --> rc = -1 */
1084 "; ja 1f ; ud2 ; 1:"
1085 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1088 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1092 } operand
= {eptp
, gpa
};
1094 asm volatile (__ex(ASM_VMX_INVEPT
)
1095 /* CF==1 or ZF==1 --> rc = -1 */
1096 "; ja 1f ; ud2 ; 1:\n"
1097 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1100 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1104 i
= __find_msr_index(vmx
, msr
);
1106 return &vmx
->guest_msrs
[i
];
1110 static void vmcs_clear(struct vmcs
*vmcs
)
1112 u64 phys_addr
= __pa(vmcs
);
1115 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1116 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1119 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1123 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1125 vmcs_clear(loaded_vmcs
->vmcs
);
1126 loaded_vmcs
->cpu
= -1;
1127 loaded_vmcs
->launched
= 0;
1130 static void vmcs_load(struct vmcs
*vmcs
)
1132 u64 phys_addr
= __pa(vmcs
);
1135 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1136 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1139 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1145 * This bitmap is used to indicate whether the vmclear
1146 * operation is enabled on all cpus. All disabled by
1149 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1151 static inline void crash_enable_local_vmclear(int cpu
)
1153 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1156 static inline void crash_disable_local_vmclear(int cpu
)
1158 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1161 static inline int crash_local_vmclear_enabled(int cpu
)
1163 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1166 static void crash_vmclear_local_loaded_vmcss(void)
1168 int cpu
= raw_smp_processor_id();
1169 struct loaded_vmcs
*v
;
1171 if (!crash_local_vmclear_enabled(cpu
))
1174 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1175 loaded_vmcss_on_cpu_link
)
1176 vmcs_clear(v
->vmcs
);
1179 static inline void crash_enable_local_vmclear(int cpu
) { }
1180 static inline void crash_disable_local_vmclear(int cpu
) { }
1181 #endif /* CONFIG_KEXEC */
1183 static void __loaded_vmcs_clear(void *arg
)
1185 struct loaded_vmcs
*loaded_vmcs
= arg
;
1186 int cpu
= raw_smp_processor_id();
1188 if (loaded_vmcs
->cpu
!= cpu
)
1189 return; /* vcpu migration can race with cpu offline */
1190 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1191 per_cpu(current_vmcs
, cpu
) = NULL
;
1192 crash_disable_local_vmclear(cpu
);
1193 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1196 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1197 * is before setting loaded_vmcs->vcpu to -1 which is done in
1198 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1199 * then adds the vmcs into percpu list before it is deleted.
1203 loaded_vmcs_init(loaded_vmcs
);
1204 crash_enable_local_vmclear(cpu
);
1207 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1209 int cpu
= loaded_vmcs
->cpu
;
1212 smp_call_function_single(cpu
,
1213 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1216 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1221 if (cpu_has_vmx_invvpid_single())
1222 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1225 static inline void vpid_sync_vcpu_global(void)
1227 if (cpu_has_vmx_invvpid_global())
1228 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1231 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1233 if (cpu_has_vmx_invvpid_single())
1234 vpid_sync_vcpu_single(vmx
);
1236 vpid_sync_vcpu_global();
1239 static inline void ept_sync_global(void)
1241 if (cpu_has_vmx_invept_global())
1242 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1245 static inline void ept_sync_context(u64 eptp
)
1248 if (cpu_has_vmx_invept_context())
1249 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1255 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1257 unsigned long value
;
1259 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1260 : "=a"(value
) : "d"(field
) : "cc");
1264 static __always_inline u16
vmcs_read16(unsigned long field
)
1266 return vmcs_readl(field
);
1269 static __always_inline u32
vmcs_read32(unsigned long field
)
1271 return vmcs_readl(field
);
1274 static __always_inline u64
vmcs_read64(unsigned long field
)
1276 #ifdef CONFIG_X86_64
1277 return vmcs_readl(field
);
1279 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1283 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1285 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1286 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1290 static void vmcs_writel(unsigned long field
, unsigned long value
)
1294 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1295 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1296 if (unlikely(error
))
1297 vmwrite_error(field
, value
);
1300 static void vmcs_write16(unsigned long field
, u16 value
)
1302 vmcs_writel(field
, value
);
1305 static void vmcs_write32(unsigned long field
, u32 value
)
1307 vmcs_writel(field
, value
);
1310 static void vmcs_write64(unsigned long field
, u64 value
)
1312 vmcs_writel(field
, value
);
1313 #ifndef CONFIG_X86_64
1315 vmcs_writel(field
+1, value
>> 32);
1319 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1321 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1324 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1326 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1329 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1331 vmx
->segment_cache
.bitmask
= 0;
1334 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1338 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1340 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1341 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1342 vmx
->segment_cache
.bitmask
= 0;
1344 ret
= vmx
->segment_cache
.bitmask
& mask
;
1345 vmx
->segment_cache
.bitmask
|= mask
;
1349 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1351 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1353 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1354 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1358 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1360 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1362 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1363 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1367 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1369 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1371 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1372 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1376 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1378 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1380 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1381 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1385 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1389 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1390 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1391 if ((vcpu
->guest_debug
&
1392 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1393 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1394 eb
|= 1u << BP_VECTOR
;
1395 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1398 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1399 if (vcpu
->fpu_active
)
1400 eb
&= ~(1u << NM_VECTOR
);
1402 /* When we are running a nested L2 guest and L1 specified for it a
1403 * certain exception bitmap, we must trap the same exceptions and pass
1404 * them to L1. When running L2, we will only handle the exceptions
1405 * specified above if L1 did not want them.
1407 if (is_guest_mode(vcpu
))
1408 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1410 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1413 static void clear_atomic_switch_msr_special(unsigned long entry
,
1416 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1417 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1420 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1423 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1427 if (cpu_has_load_ia32_efer
) {
1428 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1429 VM_EXIT_LOAD_IA32_EFER
);
1433 case MSR_CORE_PERF_GLOBAL_CTRL
:
1434 if (cpu_has_load_perf_global_ctrl
) {
1435 clear_atomic_switch_msr_special(
1436 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1437 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1443 for (i
= 0; i
< m
->nr
; ++i
)
1444 if (m
->guest
[i
].index
== msr
)
1450 m
->guest
[i
] = m
->guest
[m
->nr
];
1451 m
->host
[i
] = m
->host
[m
->nr
];
1452 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1453 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1456 static void add_atomic_switch_msr_special(unsigned long entry
,
1457 unsigned long exit
, unsigned long guest_val_vmcs
,
1458 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1460 vmcs_write64(guest_val_vmcs
, guest_val
);
1461 vmcs_write64(host_val_vmcs
, host_val
);
1462 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1463 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1466 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1467 u64 guest_val
, u64 host_val
)
1470 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1474 if (cpu_has_load_ia32_efer
) {
1475 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1476 VM_EXIT_LOAD_IA32_EFER
,
1479 guest_val
, host_val
);
1483 case MSR_CORE_PERF_GLOBAL_CTRL
:
1484 if (cpu_has_load_perf_global_ctrl
) {
1485 add_atomic_switch_msr_special(
1486 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1487 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1488 GUEST_IA32_PERF_GLOBAL_CTRL
,
1489 HOST_IA32_PERF_GLOBAL_CTRL
,
1490 guest_val
, host_val
);
1496 for (i
= 0; i
< m
->nr
; ++i
)
1497 if (m
->guest
[i
].index
== msr
)
1500 if (i
== NR_AUTOLOAD_MSRS
) {
1501 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1502 "Can't add msr %x\n", msr
);
1504 } else if (i
== m
->nr
) {
1506 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1510 m
->guest
[i
].index
= msr
;
1511 m
->guest
[i
].value
= guest_val
;
1512 m
->host
[i
].index
= msr
;
1513 m
->host
[i
].value
= host_val
;
1516 static void reload_tss(void)
1519 * VT restores TR but not its size. Useless.
1521 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1522 struct desc_struct
*descs
;
1524 descs
= (void *)gdt
->address
;
1525 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1529 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1534 guest_efer
= vmx
->vcpu
.arch
.efer
;
1537 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1540 ignore_bits
= EFER_NX
| EFER_SCE
;
1541 #ifdef CONFIG_X86_64
1542 ignore_bits
|= EFER_LMA
| EFER_LME
;
1543 /* SCE is meaningful only in long mode on Intel */
1544 if (guest_efer
& EFER_LMA
)
1545 ignore_bits
&= ~(u64
)EFER_SCE
;
1547 guest_efer
&= ~ignore_bits
;
1548 guest_efer
|= host_efer
& ignore_bits
;
1549 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1550 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1552 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1553 /* On ept, can't emulate nx, and must switch nx atomically */
1554 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1555 guest_efer
= vmx
->vcpu
.arch
.efer
;
1556 if (!(guest_efer
& EFER_LMA
))
1557 guest_efer
&= ~EFER_LME
;
1558 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1565 static unsigned long segment_base(u16 selector
)
1567 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1568 struct desc_struct
*d
;
1569 unsigned long table_base
;
1572 if (!(selector
& ~3))
1575 table_base
= gdt
->address
;
1577 if (selector
& 4) { /* from ldt */
1578 u16 ldt_selector
= kvm_read_ldt();
1580 if (!(ldt_selector
& ~3))
1583 table_base
= segment_base(ldt_selector
);
1585 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1586 v
= get_desc_base(d
);
1587 #ifdef CONFIG_X86_64
1588 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1589 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1594 static inline unsigned long kvm_read_tr_base(void)
1597 asm("str %0" : "=g"(tr
));
1598 return segment_base(tr
);
1601 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1603 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1606 if (vmx
->host_state
.loaded
)
1609 vmx
->host_state
.loaded
= 1;
1611 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1612 * allow segment selectors with cpl > 0 or ti == 1.
1614 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1615 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1616 savesegment(fs
, vmx
->host_state
.fs_sel
);
1617 if (!(vmx
->host_state
.fs_sel
& 7)) {
1618 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1619 vmx
->host_state
.fs_reload_needed
= 0;
1621 vmcs_write16(HOST_FS_SELECTOR
, 0);
1622 vmx
->host_state
.fs_reload_needed
= 1;
1624 savesegment(gs
, vmx
->host_state
.gs_sel
);
1625 if (!(vmx
->host_state
.gs_sel
& 7))
1626 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1628 vmcs_write16(HOST_GS_SELECTOR
, 0);
1629 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1632 #ifdef CONFIG_X86_64
1633 savesegment(ds
, vmx
->host_state
.ds_sel
);
1634 savesegment(es
, vmx
->host_state
.es_sel
);
1637 #ifdef CONFIG_X86_64
1638 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1639 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1641 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1642 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1645 #ifdef CONFIG_X86_64
1646 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1647 if (is_long_mode(&vmx
->vcpu
))
1648 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1650 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1651 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1652 vmx
->guest_msrs
[i
].data
,
1653 vmx
->guest_msrs
[i
].mask
);
1656 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1658 if (!vmx
->host_state
.loaded
)
1661 ++vmx
->vcpu
.stat
.host_state_reload
;
1662 vmx
->host_state
.loaded
= 0;
1663 #ifdef CONFIG_X86_64
1664 if (is_long_mode(&vmx
->vcpu
))
1665 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1667 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1668 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1669 #ifdef CONFIG_X86_64
1670 load_gs_index(vmx
->host_state
.gs_sel
);
1672 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1675 if (vmx
->host_state
.fs_reload_needed
)
1676 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1677 #ifdef CONFIG_X86_64
1678 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1679 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1680 loadsegment(es
, vmx
->host_state
.es_sel
);
1684 #ifdef CONFIG_X86_64
1685 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1688 * If the FPU is not active (through the host task or
1689 * the guest vcpu), then restore the cr0.TS bit.
1691 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1693 load_gdt(&__get_cpu_var(host_gdt
));
1696 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1699 __vmx_load_host_state(vmx
);
1704 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1705 * vcpu mutex is already taken.
1707 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1709 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1710 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1713 kvm_cpu_vmxon(phys_addr
);
1714 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1715 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1717 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1718 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1719 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1722 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1723 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1724 unsigned long sysenter_esp
;
1726 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1727 local_irq_disable();
1728 crash_disable_local_vmclear(cpu
);
1731 * Read loaded_vmcs->cpu should be before fetching
1732 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1733 * See the comments in __loaded_vmcs_clear().
1737 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1738 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1739 crash_enable_local_vmclear(cpu
);
1743 * Linux uses per-cpu TSS and GDT, so set these when switching
1746 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1747 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1749 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1750 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1751 vmx
->loaded_vmcs
->cpu
= cpu
;
1755 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1757 __vmx_load_host_state(to_vmx(vcpu
));
1758 if (!vmm_exclusive
) {
1759 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1765 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1769 if (vcpu
->fpu_active
)
1771 vcpu
->fpu_active
= 1;
1772 cr0
= vmcs_readl(GUEST_CR0
);
1773 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1774 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1775 vmcs_writel(GUEST_CR0
, cr0
);
1776 update_exception_bitmap(vcpu
);
1777 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1778 if (is_guest_mode(vcpu
))
1779 vcpu
->arch
.cr0_guest_owned_bits
&=
1780 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1781 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1784 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1787 * Return the cr0 value that a nested guest would read. This is a combination
1788 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1789 * its hypervisor (cr0_read_shadow).
1791 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1793 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1794 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1796 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1798 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1799 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1802 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1804 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1805 * set this *before* calling this function.
1807 vmx_decache_cr0_guest_bits(vcpu
);
1808 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1809 update_exception_bitmap(vcpu
);
1810 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1811 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1812 if (is_guest_mode(vcpu
)) {
1814 * L1's specified read shadow might not contain the TS bit,
1815 * so now that we turned on shadowing of this bit, we need to
1816 * set this bit of the shadow. Like in nested_vmx_run we need
1817 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1818 * up-to-date here because we just decached cr0.TS (and we'll
1819 * only update vmcs12->guest_cr0 on nested exit).
1821 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1822 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1823 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1824 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1826 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1829 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1831 unsigned long rflags
, save_rflags
;
1833 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1834 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1835 rflags
= vmcs_readl(GUEST_RFLAGS
);
1836 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1837 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1838 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1839 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1841 to_vmx(vcpu
)->rflags
= rflags
;
1843 return to_vmx(vcpu
)->rflags
;
1846 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1848 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1849 to_vmx(vcpu
)->rflags
= rflags
;
1850 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1851 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1852 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1854 vmcs_writel(GUEST_RFLAGS
, rflags
);
1857 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1859 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1862 if (interruptibility
& GUEST_INTR_STATE_STI
)
1863 ret
|= KVM_X86_SHADOW_INT_STI
;
1864 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1865 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1870 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1872 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1873 u32 interruptibility
= interruptibility_old
;
1875 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1877 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1878 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1879 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1880 interruptibility
|= GUEST_INTR_STATE_STI
;
1882 if ((interruptibility
!= interruptibility_old
))
1883 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1886 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1890 rip
= kvm_rip_read(vcpu
);
1891 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1892 kvm_rip_write(vcpu
, rip
);
1894 /* skipping an emulated instruction also counts */
1895 vmx_set_interrupt_shadow(vcpu
, 0);
1899 * KVM wants to inject page-faults which it got to the guest. This function
1900 * checks whether in a nested guest, we need to inject them to L1 or L2.
1902 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1904 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1906 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1909 nested_vmx_vmexit(vcpu
);
1913 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1914 bool has_error_code
, u32 error_code
,
1917 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1918 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1920 if (!reinject
&& is_guest_mode(vcpu
) &&
1921 nested_vmx_check_exception(vcpu
, nr
))
1924 if (has_error_code
) {
1925 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1926 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1929 if (vmx
->rmode
.vm86_active
) {
1931 if (kvm_exception_is_soft(nr
))
1932 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1933 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1934 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1938 if (kvm_exception_is_soft(nr
)) {
1939 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1940 vmx
->vcpu
.arch
.event_exit_inst_len
);
1941 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1943 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1948 static bool vmx_rdtscp_supported(void)
1950 return cpu_has_vmx_rdtscp();
1953 static bool vmx_invpcid_supported(void)
1955 return cpu_has_vmx_invpcid() && enable_ept
;
1959 * Swap MSR entry in host/guest MSR entry array.
1961 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1963 struct shared_msr_entry tmp
;
1965 tmp
= vmx
->guest_msrs
[to
];
1966 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1967 vmx
->guest_msrs
[from
] = tmp
;
1970 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
1972 unsigned long *msr_bitmap
;
1974 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
1975 if (is_long_mode(vcpu
))
1976 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
1978 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
1980 if (is_long_mode(vcpu
))
1981 msr_bitmap
= vmx_msr_bitmap_longmode
;
1983 msr_bitmap
= vmx_msr_bitmap_legacy
;
1986 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1990 * Set up the vmcs to automatically save and restore system
1991 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1992 * mode, as fiddling with msrs is very expensive.
1994 static void setup_msrs(struct vcpu_vmx
*vmx
)
1996 int save_nmsrs
, index
;
1999 #ifdef CONFIG_X86_64
2000 if (is_long_mode(&vmx
->vcpu
)) {
2001 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2003 move_msr_up(vmx
, index
, save_nmsrs
++);
2004 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2006 move_msr_up(vmx
, index
, save_nmsrs
++);
2007 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2009 move_msr_up(vmx
, index
, save_nmsrs
++);
2010 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2011 if (index
>= 0 && vmx
->rdtscp_enabled
)
2012 move_msr_up(vmx
, index
, save_nmsrs
++);
2014 * MSR_STAR is only needed on long mode guests, and only
2015 * if efer.sce is enabled.
2017 index
= __find_msr_index(vmx
, MSR_STAR
);
2018 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2019 move_msr_up(vmx
, index
, save_nmsrs
++);
2022 index
= __find_msr_index(vmx
, MSR_EFER
);
2023 if (index
>= 0 && update_transition_efer(vmx
, index
))
2024 move_msr_up(vmx
, index
, save_nmsrs
++);
2026 vmx
->save_nmsrs
= save_nmsrs
;
2028 if (cpu_has_vmx_msr_bitmap())
2029 vmx_set_msr_bitmap(&vmx
->vcpu
);
2033 * reads and returns guest's timestamp counter "register"
2034 * guest_tsc = host_tsc + tsc_offset -- 21.3
2036 static u64
guest_read_tsc(void)
2038 u64 host_tsc
, tsc_offset
;
2041 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2042 return host_tsc
+ tsc_offset
;
2046 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2047 * counter, even if a nested guest (L2) is currently running.
2049 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2053 tsc_offset
= is_guest_mode(vcpu
) ?
2054 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2055 vmcs_read64(TSC_OFFSET
);
2056 return host_tsc
+ tsc_offset
;
2060 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2061 * software catchup for faster rates on slower CPUs.
2063 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2068 if (user_tsc_khz
> tsc_khz
) {
2069 vcpu
->arch
.tsc_catchup
= 1;
2070 vcpu
->arch
.tsc_always_catchup
= 1;
2072 WARN(1, "user requested TSC rate below hardware speed\n");
2075 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2077 return vmcs_read64(TSC_OFFSET
);
2081 * writes 'offset' into guest's timestamp counter offset register
2083 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2085 if (is_guest_mode(vcpu
)) {
2087 * We're here if L1 chose not to trap WRMSR to TSC. According
2088 * to the spec, this should set L1's TSC; The offset that L1
2089 * set for L2 remains unchanged, and still needs to be added
2090 * to the newly set TSC to get L2's TSC.
2092 struct vmcs12
*vmcs12
;
2093 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2094 /* recalculate vmcs02.TSC_OFFSET: */
2095 vmcs12
= get_vmcs12(vcpu
);
2096 vmcs_write64(TSC_OFFSET
, offset
+
2097 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2098 vmcs12
->tsc_offset
: 0));
2100 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2101 vmcs_read64(TSC_OFFSET
), offset
);
2102 vmcs_write64(TSC_OFFSET
, offset
);
2106 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2108 u64 offset
= vmcs_read64(TSC_OFFSET
);
2110 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2111 if (is_guest_mode(vcpu
)) {
2112 /* Even when running L2, the adjustment needs to apply to L1 */
2113 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2115 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2116 offset
+ adjustment
);
2119 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2121 return target_tsc
- native_read_tsc();
2124 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2126 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2127 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2131 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2132 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2133 * all guests if the "nested" module option is off, and can also be disabled
2134 * for a single guest by disabling its VMX cpuid bit.
2136 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2138 return nested
&& guest_cpuid_has_vmx(vcpu
);
2142 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2143 * returned for the various VMX controls MSRs when nested VMX is enabled.
2144 * The same values should also be used to verify that vmcs12 control fields are
2145 * valid during nested entry from L1 to L2.
2146 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2147 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2148 * bit in the high half is on if the corresponding bit in the control field
2149 * may be on. See also vmx_control_verify().
2150 * TODO: allow these variables to be modified (downgraded) by module options
2153 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2154 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2155 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2156 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2157 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2158 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2159 static u32 nested_vmx_ept_caps
;
2160 static __init
void nested_vmx_setup_ctls_msrs(void)
2163 * Note that as a general rule, the high half of the MSRs (bits in
2164 * the control fields which may be 1) should be initialized by the
2165 * intersection of the underlying hardware's MSR (i.e., features which
2166 * can be supported) and the list of features we want to expose -
2167 * because they are known to be properly supported in our code.
2168 * Also, usually, the low half of the MSRs (bits which must be 1) can
2169 * be set to 0, meaning that L1 may turn off any of these bits. The
2170 * reason is that if one of these bits is necessary, it will appear
2171 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2172 * fields of vmcs01 and vmcs02, will turn these bits off - and
2173 * nested_vmx_exit_handled() will not pass related exits to L1.
2174 * These rules have exceptions below.
2177 /* pin-based controls */
2178 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2179 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2181 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2182 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2184 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2185 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2186 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2187 PIN_BASED_VMX_PREEMPTION_TIMER
;
2188 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2192 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2195 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2196 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2197 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2198 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2199 nested_vmx_exit_ctls_high
&=
2200 #ifdef CONFIG_X86_64
2201 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2203 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2204 nested_vmx_exit_ctls_high
|= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2205 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
);
2207 /* entry controls */
2208 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2209 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2210 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2211 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2212 nested_vmx_entry_ctls_high
&=
2213 #ifdef CONFIG_X86_64
2214 VM_ENTRY_IA32E_MODE
|
2216 VM_ENTRY_LOAD_IA32_PAT
;
2217 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2218 VM_ENTRY_LOAD_IA32_EFER
);
2220 /* cpu-based controls */
2221 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2222 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2223 nested_vmx_procbased_ctls_low
= 0;
2224 nested_vmx_procbased_ctls_high
&=
2225 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2226 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2227 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2228 CPU_BASED_CR3_STORE_EXITING
|
2229 #ifdef CONFIG_X86_64
2230 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2232 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2233 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2234 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2235 CPU_BASED_PAUSE_EXITING
|
2236 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2238 * We can allow some features even when not supported by the
2239 * hardware. For example, L1 can specify an MSR bitmap - and we
2240 * can use it to avoid exits to L1 - even when L0 runs L2
2241 * without MSR bitmaps.
2243 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2245 /* secondary cpu-based controls */
2246 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2247 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2248 nested_vmx_secondary_ctls_low
= 0;
2249 nested_vmx_secondary_ctls_high
&=
2250 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2251 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2252 SECONDARY_EXEC_WBINVD_EXITING
;
2255 /* nested EPT: emulate EPT also to L1 */
2256 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2257 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2258 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2259 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2261 * Since invept is completely emulated we support both global
2262 * and context invalidation independent of what host cpu
2265 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2266 VMX_EPT_EXTENT_CONTEXT_BIT
;
2268 nested_vmx_ept_caps
= 0;
2270 /* miscellaneous data */
2271 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2272 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2273 VMX_MISC_SAVE_EFER_LMA
;
2274 nested_vmx_misc_high
= 0;
2277 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2280 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2282 return ((control
& high
) | low
) == control
;
2285 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2287 return low
| ((u64
)high
<< 32);
2291 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2292 * also let it use VMX-specific MSRs.
2293 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2294 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2295 * like all other MSRs).
2297 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2299 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2300 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2302 * According to the spec, processors which do not support VMX
2303 * should throw a #GP(0) when VMX capability MSRs are read.
2305 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2309 switch (msr_index
) {
2310 case MSR_IA32_FEATURE_CONTROL
:
2311 if (nested_vmx_allowed(vcpu
)) {
2312 *pdata
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2316 case MSR_IA32_VMX_BASIC
:
2318 * This MSR reports some information about VMX support. We
2319 * should return information about the VMX we emulate for the
2320 * guest, and the VMCS structure we give it - not about the
2321 * VMX support of the underlying hardware.
2323 *pdata
= VMCS12_REVISION
|
2324 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2325 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2327 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2328 case MSR_IA32_VMX_PINBASED_CTLS
:
2329 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2330 nested_vmx_pinbased_ctls_high
);
2332 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2333 case MSR_IA32_VMX_PROCBASED_CTLS
:
2334 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2335 nested_vmx_procbased_ctls_high
);
2337 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2338 case MSR_IA32_VMX_EXIT_CTLS
:
2339 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2340 nested_vmx_exit_ctls_high
);
2342 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2343 case MSR_IA32_VMX_ENTRY_CTLS
:
2344 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2345 nested_vmx_entry_ctls_high
);
2347 case MSR_IA32_VMX_MISC
:
2348 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2349 nested_vmx_misc_high
);
2352 * These MSRs specify bits which the guest must keep fixed (on or off)
2353 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2354 * We picked the standard core2 setting.
2356 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2357 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2358 case MSR_IA32_VMX_CR0_FIXED0
:
2359 *pdata
= VMXON_CR0_ALWAYSON
;
2361 case MSR_IA32_VMX_CR0_FIXED1
:
2364 case MSR_IA32_VMX_CR4_FIXED0
:
2365 *pdata
= VMXON_CR4_ALWAYSON
;
2367 case MSR_IA32_VMX_CR4_FIXED1
:
2370 case MSR_IA32_VMX_VMCS_ENUM
:
2373 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2374 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2375 nested_vmx_secondary_ctls_high
);
2377 case MSR_IA32_VMX_EPT_VPID_CAP
:
2378 /* Currently, no nested vpid support */
2379 *pdata
= nested_vmx_ept_caps
;
2388 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2390 u32 msr_index
= msr_info
->index
;
2391 u64 data
= msr_info
->data
;
2392 bool host_initialized
= msr_info
->host_initiated
;
2394 if (!nested_vmx_allowed(vcpu
))
2397 if (msr_index
== MSR_IA32_FEATURE_CONTROL
) {
2398 if (!host_initialized
&&
2399 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
2400 & FEATURE_CONTROL_LOCKED
)
2402 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
= data
;
2407 * No need to treat VMX capability MSRs specially: If we don't handle
2408 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2414 * Reads an msr value (of 'msr_index') into 'pdata'.
2415 * Returns 0 on success, non-0 otherwise.
2416 * Assumes vcpu_load() was already called.
2418 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2421 struct shared_msr_entry
*msr
;
2424 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2428 switch (msr_index
) {
2429 #ifdef CONFIG_X86_64
2431 data
= vmcs_readl(GUEST_FS_BASE
);
2434 data
= vmcs_readl(GUEST_GS_BASE
);
2436 case MSR_KERNEL_GS_BASE
:
2437 vmx_load_host_state(to_vmx(vcpu
));
2438 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2442 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2444 data
= guest_read_tsc();
2446 case MSR_IA32_SYSENTER_CS
:
2447 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2449 case MSR_IA32_SYSENTER_EIP
:
2450 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2452 case MSR_IA32_SYSENTER_ESP
:
2453 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2456 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2458 /* Otherwise falls through */
2460 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2462 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2467 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2475 * Writes msr value into into the appropriate "register".
2476 * Returns 0 on success, non-0 otherwise.
2477 * Assumes vcpu_load() was already called.
2479 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2481 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2482 struct shared_msr_entry
*msr
;
2484 u32 msr_index
= msr_info
->index
;
2485 u64 data
= msr_info
->data
;
2487 switch (msr_index
) {
2489 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2491 #ifdef CONFIG_X86_64
2493 vmx_segment_cache_clear(vmx
);
2494 vmcs_writel(GUEST_FS_BASE
, data
);
2497 vmx_segment_cache_clear(vmx
);
2498 vmcs_writel(GUEST_GS_BASE
, data
);
2500 case MSR_KERNEL_GS_BASE
:
2501 vmx_load_host_state(vmx
);
2502 vmx
->msr_guest_kernel_gs_base
= data
;
2505 case MSR_IA32_SYSENTER_CS
:
2506 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2508 case MSR_IA32_SYSENTER_EIP
:
2509 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2511 case MSR_IA32_SYSENTER_ESP
:
2512 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2515 kvm_write_tsc(vcpu
, msr_info
);
2517 case MSR_IA32_CR_PAT
:
2518 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2519 vmcs_write64(GUEST_IA32_PAT
, data
);
2520 vcpu
->arch
.pat
= data
;
2523 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2525 case MSR_IA32_TSC_ADJUST
:
2526 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2529 if (!vmx
->rdtscp_enabled
)
2531 /* Check reserved bit, higher 32 bits should be zero */
2532 if ((data
>> 32) != 0)
2534 /* Otherwise falls through */
2536 if (vmx_set_vmx_msr(vcpu
, msr_info
))
2538 msr
= find_msr_entry(vmx
, msr_index
);
2541 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2543 kvm_set_shared_msr(msr
->index
, msr
->data
,
2549 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2555 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2557 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2560 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2563 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2565 case VCPU_EXREG_PDPTR
:
2567 ept_save_pdptrs(vcpu
);
2574 static __init
int cpu_has_kvm_support(void)
2576 return cpu_has_vmx();
2579 static __init
int vmx_disabled_by_bios(void)
2583 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2584 if (msr
& FEATURE_CONTROL_LOCKED
) {
2585 /* launched w/ TXT and VMX disabled */
2586 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2589 /* launched w/o TXT and VMX only enabled w/ TXT */
2590 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2591 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2592 && !tboot_enabled()) {
2593 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2594 "activate TXT before enabling KVM\n");
2597 /* launched w/o TXT and VMX disabled */
2598 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2599 && !tboot_enabled())
2606 static void kvm_cpu_vmxon(u64 addr
)
2608 asm volatile (ASM_VMX_VMXON_RAX
2609 : : "a"(&addr
), "m"(addr
)
2613 static int hardware_enable(void *garbage
)
2615 int cpu
= raw_smp_processor_id();
2616 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2619 if (read_cr4() & X86_CR4_VMXE
)
2622 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2625 * Now we can enable the vmclear operation in kdump
2626 * since the loaded_vmcss_on_cpu list on this cpu
2627 * has been initialized.
2629 * Though the cpu is not in VMX operation now, there
2630 * is no problem to enable the vmclear operation
2631 * for the loaded_vmcss_on_cpu list is empty!
2633 crash_enable_local_vmclear(cpu
);
2635 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2637 test_bits
= FEATURE_CONTROL_LOCKED
;
2638 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2639 if (tboot_enabled())
2640 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2642 if ((old
& test_bits
) != test_bits
) {
2643 /* enable and lock */
2644 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2646 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2648 if (vmm_exclusive
) {
2649 kvm_cpu_vmxon(phys_addr
);
2653 native_store_gdt(&__get_cpu_var(host_gdt
));
2658 static void vmclear_local_loaded_vmcss(void)
2660 int cpu
= raw_smp_processor_id();
2661 struct loaded_vmcs
*v
, *n
;
2663 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2664 loaded_vmcss_on_cpu_link
)
2665 __loaded_vmcs_clear(v
);
2669 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2672 static void kvm_cpu_vmxoff(void)
2674 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2677 static void hardware_disable(void *garbage
)
2679 if (vmm_exclusive
) {
2680 vmclear_local_loaded_vmcss();
2683 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2686 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2687 u32 msr
, u32
*result
)
2689 u32 vmx_msr_low
, vmx_msr_high
;
2690 u32 ctl
= ctl_min
| ctl_opt
;
2692 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2694 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2695 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2697 /* Ensure minimum (required) set of control bits are supported. */
2705 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2707 u32 vmx_msr_low
, vmx_msr_high
;
2709 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2710 return vmx_msr_high
& ctl
;
2713 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2715 u32 vmx_msr_low
, vmx_msr_high
;
2716 u32 min
, opt
, min2
, opt2
;
2717 u32 _pin_based_exec_control
= 0;
2718 u32 _cpu_based_exec_control
= 0;
2719 u32 _cpu_based_2nd_exec_control
= 0;
2720 u32 _vmexit_control
= 0;
2721 u32 _vmentry_control
= 0;
2723 min
= CPU_BASED_HLT_EXITING
|
2724 #ifdef CONFIG_X86_64
2725 CPU_BASED_CR8_LOAD_EXITING
|
2726 CPU_BASED_CR8_STORE_EXITING
|
2728 CPU_BASED_CR3_LOAD_EXITING
|
2729 CPU_BASED_CR3_STORE_EXITING
|
2730 CPU_BASED_USE_IO_BITMAPS
|
2731 CPU_BASED_MOV_DR_EXITING
|
2732 CPU_BASED_USE_TSC_OFFSETING
|
2733 CPU_BASED_MWAIT_EXITING
|
2734 CPU_BASED_MONITOR_EXITING
|
2735 CPU_BASED_INVLPG_EXITING
|
2736 CPU_BASED_RDPMC_EXITING
;
2738 opt
= CPU_BASED_TPR_SHADOW
|
2739 CPU_BASED_USE_MSR_BITMAPS
|
2740 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2741 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2742 &_cpu_based_exec_control
) < 0)
2744 #ifdef CONFIG_X86_64
2745 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2746 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2747 ~CPU_BASED_CR8_STORE_EXITING
;
2749 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2751 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2752 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2753 SECONDARY_EXEC_WBINVD_EXITING
|
2754 SECONDARY_EXEC_ENABLE_VPID
|
2755 SECONDARY_EXEC_ENABLE_EPT
|
2756 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2757 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2758 SECONDARY_EXEC_RDTSCP
|
2759 SECONDARY_EXEC_ENABLE_INVPCID
|
2760 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2761 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2762 SECONDARY_EXEC_SHADOW_VMCS
;
2763 if (adjust_vmx_controls(min2
, opt2
,
2764 MSR_IA32_VMX_PROCBASED_CTLS2
,
2765 &_cpu_based_2nd_exec_control
) < 0)
2768 #ifndef CONFIG_X86_64
2769 if (!(_cpu_based_2nd_exec_control
&
2770 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2771 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2774 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2775 _cpu_based_2nd_exec_control
&= ~(
2776 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2777 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2778 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2780 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2781 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2783 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2784 CPU_BASED_CR3_STORE_EXITING
|
2785 CPU_BASED_INVLPG_EXITING
);
2786 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2787 vmx_capability
.ept
, vmx_capability
.vpid
);
2791 #ifdef CONFIG_X86_64
2792 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2794 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2795 VM_EXIT_ACK_INTR_ON_EXIT
;
2796 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2797 &_vmexit_control
) < 0)
2800 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2801 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2802 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2803 &_pin_based_exec_control
) < 0)
2806 if (!(_cpu_based_2nd_exec_control
&
2807 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2808 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2809 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2812 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2813 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2814 &_vmentry_control
) < 0)
2817 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2819 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2820 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2823 #ifdef CONFIG_X86_64
2824 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2825 if (vmx_msr_high
& (1u<<16))
2829 /* Require Write-Back (WB) memory type for VMCS accesses. */
2830 if (((vmx_msr_high
>> 18) & 15) != 6)
2833 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2834 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2835 vmcs_conf
->revision_id
= vmx_msr_low
;
2837 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2838 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2839 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2840 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2841 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2843 cpu_has_load_ia32_efer
=
2844 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2845 VM_ENTRY_LOAD_IA32_EFER
)
2846 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2847 VM_EXIT_LOAD_IA32_EFER
);
2849 cpu_has_load_perf_global_ctrl
=
2850 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2851 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2852 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2853 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2856 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2857 * but due to arrata below it can't be used. Workaround is to use
2858 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2860 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2865 * BC86,AAY89,BD102 (model 44)
2869 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2870 switch (boot_cpu_data
.x86_model
) {
2876 cpu_has_load_perf_global_ctrl
= false;
2877 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2878 "does not work properly. Using workaround\n");
2888 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2890 int node
= cpu_to_node(cpu
);
2894 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2897 vmcs
= page_address(pages
);
2898 memset(vmcs
, 0, vmcs_config
.size
);
2899 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2903 static struct vmcs
*alloc_vmcs(void)
2905 return alloc_vmcs_cpu(raw_smp_processor_id());
2908 static void free_vmcs(struct vmcs
*vmcs
)
2910 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2914 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2916 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2918 if (!loaded_vmcs
->vmcs
)
2920 loaded_vmcs_clear(loaded_vmcs
);
2921 free_vmcs(loaded_vmcs
->vmcs
);
2922 loaded_vmcs
->vmcs
= NULL
;
2925 static void free_kvm_area(void)
2929 for_each_possible_cpu(cpu
) {
2930 free_vmcs(per_cpu(vmxarea
, cpu
));
2931 per_cpu(vmxarea
, cpu
) = NULL
;
2935 static __init
int alloc_kvm_area(void)
2939 for_each_possible_cpu(cpu
) {
2942 vmcs
= alloc_vmcs_cpu(cpu
);
2948 per_cpu(vmxarea
, cpu
) = vmcs
;
2953 static __init
int hardware_setup(void)
2955 if (setup_vmcs_config(&vmcs_config
) < 0)
2958 if (boot_cpu_has(X86_FEATURE_NX
))
2959 kvm_enable_efer_bits(EFER_NX
);
2961 if (!cpu_has_vmx_vpid())
2963 if (!cpu_has_vmx_shadow_vmcs())
2964 enable_shadow_vmcs
= 0;
2966 if (!cpu_has_vmx_ept() ||
2967 !cpu_has_vmx_ept_4levels()) {
2969 enable_unrestricted_guest
= 0;
2970 enable_ept_ad_bits
= 0;
2973 if (!cpu_has_vmx_ept_ad_bits())
2974 enable_ept_ad_bits
= 0;
2976 if (!cpu_has_vmx_unrestricted_guest())
2977 enable_unrestricted_guest
= 0;
2979 if (!cpu_has_vmx_flexpriority())
2980 flexpriority_enabled
= 0;
2982 if (!cpu_has_vmx_tpr_shadow())
2983 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2985 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2986 kvm_disable_largepages();
2988 if (!cpu_has_vmx_ple())
2991 if (!cpu_has_vmx_apicv())
2995 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2997 kvm_x86_ops
->hwapic_irr_update
= NULL
;
2998 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
2999 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3003 nested_vmx_setup_ctls_msrs();
3005 return alloc_kvm_area();
3008 static __exit
void hardware_unsetup(void)
3013 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3015 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3018 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3019 struct kvm_segment
*save
)
3021 if (!emulate_invalid_guest_state
) {
3023 * CS and SS RPL should be equal during guest entry according
3024 * to VMX spec, but in reality it is not always so. Since vcpu
3025 * is in the middle of the transition from real mode to
3026 * protected mode it is safe to assume that RPL 0 is a good
3029 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3030 save
->selector
&= ~SELECTOR_RPL_MASK
;
3031 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3034 vmx_set_segment(vcpu
, save
, seg
);
3037 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3039 unsigned long flags
;
3040 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3043 * Update real mode segment cache. It may be not up-to-date if sement
3044 * register was written while vcpu was in a guest mode.
3046 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3047 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3048 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3049 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3050 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3051 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3053 vmx
->rmode
.vm86_active
= 0;
3055 vmx_segment_cache_clear(vmx
);
3057 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3059 flags
= vmcs_readl(GUEST_RFLAGS
);
3060 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3061 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3062 vmcs_writel(GUEST_RFLAGS
, flags
);
3064 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3065 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3067 update_exception_bitmap(vcpu
);
3069 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3070 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3071 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3072 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3073 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3074 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3076 /* CPL is always 0 when CPU enters protected mode */
3077 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3081 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3083 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3084 struct kvm_segment var
= *save
;
3087 if (seg
== VCPU_SREG_CS
)
3090 if (!emulate_invalid_guest_state
) {
3091 var
.selector
= var
.base
>> 4;
3092 var
.base
= var
.base
& 0xffff0;
3102 if (save
->base
& 0xf)
3103 printk_once(KERN_WARNING
"kvm: segment base is not "
3104 "paragraph aligned when entering "
3105 "protected mode (seg=%d)", seg
);
3108 vmcs_write16(sf
->selector
, var
.selector
);
3109 vmcs_write32(sf
->base
, var
.base
);
3110 vmcs_write32(sf
->limit
, var
.limit
);
3111 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3114 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3116 unsigned long flags
;
3117 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3119 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3120 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3121 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3122 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3123 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3124 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3125 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3127 vmx
->rmode
.vm86_active
= 1;
3130 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3131 * vcpu. Warn the user that an update is overdue.
3133 if (!vcpu
->kvm
->arch
.tss_addr
)
3134 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3135 "called before entering vcpu\n");
3137 vmx_segment_cache_clear(vmx
);
3139 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3140 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3141 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3143 flags
= vmcs_readl(GUEST_RFLAGS
);
3144 vmx
->rmode
.save_rflags
= flags
;
3146 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3148 vmcs_writel(GUEST_RFLAGS
, flags
);
3149 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3150 update_exception_bitmap(vcpu
);
3152 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3153 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3154 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3155 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3156 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3157 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3159 kvm_mmu_reset_context(vcpu
);
3162 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3165 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3171 * Force kernel_gs_base reloading before EFER changes, as control
3172 * of this msr depends on is_long_mode().
3174 vmx_load_host_state(to_vmx(vcpu
));
3175 vcpu
->arch
.efer
= efer
;
3176 if (efer
& EFER_LMA
) {
3177 vmcs_write32(VM_ENTRY_CONTROLS
,
3178 vmcs_read32(VM_ENTRY_CONTROLS
) |
3179 VM_ENTRY_IA32E_MODE
);
3182 vmcs_write32(VM_ENTRY_CONTROLS
,
3183 vmcs_read32(VM_ENTRY_CONTROLS
) &
3184 ~VM_ENTRY_IA32E_MODE
);
3186 msr
->data
= efer
& ~EFER_LME
;
3191 #ifdef CONFIG_X86_64
3193 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3197 vmx_segment_cache_clear(to_vmx(vcpu
));
3199 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3200 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3201 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3203 vmcs_write32(GUEST_TR_AR_BYTES
,
3204 (guest_tr_ar
& ~AR_TYPE_MASK
)
3205 | AR_TYPE_BUSY_64_TSS
);
3207 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3210 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3212 vmcs_write32(VM_ENTRY_CONTROLS
,
3213 vmcs_read32(VM_ENTRY_CONTROLS
)
3214 & ~VM_ENTRY_IA32E_MODE
);
3215 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3220 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3222 vpid_sync_context(to_vmx(vcpu
));
3224 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3226 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3230 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3232 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3234 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3235 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3238 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3240 if (enable_ept
&& is_paging(vcpu
))
3241 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3242 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3245 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3247 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3249 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3250 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3253 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3255 if (!test_bit(VCPU_EXREG_PDPTR
,
3256 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3259 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3260 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
3261 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
3262 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
3263 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
3267 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3269 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3270 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3271 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3272 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3273 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3276 __set_bit(VCPU_EXREG_PDPTR
,
3277 (unsigned long *)&vcpu
->arch
.regs_avail
);
3278 __set_bit(VCPU_EXREG_PDPTR
,
3279 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3282 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3284 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3286 struct kvm_vcpu
*vcpu
)
3288 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3289 vmx_decache_cr3(vcpu
);
3290 if (!(cr0
& X86_CR0_PG
)) {
3291 /* From paging/starting to nonpaging */
3292 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3293 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3294 (CPU_BASED_CR3_LOAD_EXITING
|
3295 CPU_BASED_CR3_STORE_EXITING
));
3296 vcpu
->arch
.cr0
= cr0
;
3297 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3298 } else if (!is_paging(vcpu
)) {
3299 /* From nonpaging to paging */
3300 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3301 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3302 ~(CPU_BASED_CR3_LOAD_EXITING
|
3303 CPU_BASED_CR3_STORE_EXITING
));
3304 vcpu
->arch
.cr0
= cr0
;
3305 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3308 if (!(cr0
& X86_CR0_WP
))
3309 *hw_cr0
&= ~X86_CR0_WP
;
3312 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3314 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3315 unsigned long hw_cr0
;
3317 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3318 if (enable_unrestricted_guest
)
3319 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3321 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3323 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3326 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3330 #ifdef CONFIG_X86_64
3331 if (vcpu
->arch
.efer
& EFER_LME
) {
3332 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3334 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3340 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3342 if (!vcpu
->fpu_active
)
3343 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3345 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3346 vmcs_writel(GUEST_CR0
, hw_cr0
);
3347 vcpu
->arch
.cr0
= cr0
;
3349 /* depends on vcpu->arch.cr0 to be set to a new value */
3350 vmx
->emulation_required
= emulation_required(vcpu
);
3353 static u64
construct_eptp(unsigned long root_hpa
)
3357 /* TODO write the value reading from MSR */
3358 eptp
= VMX_EPT_DEFAULT_MT
|
3359 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3360 if (enable_ept_ad_bits
)
3361 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3362 eptp
|= (root_hpa
& PAGE_MASK
);
3367 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3369 unsigned long guest_cr3
;
3374 eptp
= construct_eptp(cr3
);
3375 vmcs_write64(EPT_POINTER
, eptp
);
3376 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3377 guest_cr3
= kvm_read_cr3(vcpu
);
3379 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3380 ept_load_pdptrs(vcpu
);
3383 vmx_flush_tlb(vcpu
);
3384 vmcs_writel(GUEST_CR3
, guest_cr3
);
3387 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3389 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3390 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3392 if (cr4
& X86_CR4_VMXE
) {
3394 * To use VMXON (and later other VMX instructions), a guest
3395 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3396 * So basically the check on whether to allow nested VMX
3399 if (!nested_vmx_allowed(vcpu
))
3402 if (to_vmx(vcpu
)->nested
.vmxon
&&
3403 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3406 vcpu
->arch
.cr4
= cr4
;
3408 if (!is_paging(vcpu
)) {
3409 hw_cr4
&= ~X86_CR4_PAE
;
3410 hw_cr4
|= X86_CR4_PSE
;
3412 * SMEP is disabled if CPU is in non-paging mode in
3413 * hardware. However KVM always uses paging mode to
3414 * emulate guest non-paging mode with TDP.
3415 * To emulate this behavior, SMEP needs to be manually
3416 * disabled when guest switches to non-paging mode.
3418 hw_cr4
&= ~X86_CR4_SMEP
;
3419 } else if (!(cr4
& X86_CR4_PAE
)) {
3420 hw_cr4
&= ~X86_CR4_PAE
;
3424 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3425 vmcs_writel(GUEST_CR4
, hw_cr4
);
3429 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3430 struct kvm_segment
*var
, int seg
)
3432 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3435 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3436 *var
= vmx
->rmode
.segs
[seg
];
3437 if (seg
== VCPU_SREG_TR
3438 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3440 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3441 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3444 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3445 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3446 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3447 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3448 var
->unusable
= (ar
>> 16) & 1;
3449 var
->type
= ar
& 15;
3450 var
->s
= (ar
>> 4) & 1;
3451 var
->dpl
= (ar
>> 5) & 3;
3453 * Some userspaces do not preserve unusable property. Since usable
3454 * segment has to be present according to VMX spec we can use present
3455 * property to amend userspace bug by making unusable segment always
3456 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3457 * segment as unusable.
3459 var
->present
= !var
->unusable
;
3460 var
->avl
= (ar
>> 12) & 1;
3461 var
->l
= (ar
>> 13) & 1;
3462 var
->db
= (ar
>> 14) & 1;
3463 var
->g
= (ar
>> 15) & 1;
3466 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3468 struct kvm_segment s
;
3470 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3471 vmx_get_segment(vcpu
, &s
, seg
);
3474 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3477 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3479 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3481 if (!is_protmode(vcpu
))
3484 if (!is_long_mode(vcpu
)
3485 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3488 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3489 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3490 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3497 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3501 if (var
->unusable
|| !var
->present
)
3504 ar
= var
->type
& 15;
3505 ar
|= (var
->s
& 1) << 4;
3506 ar
|= (var
->dpl
& 3) << 5;
3507 ar
|= (var
->present
& 1) << 7;
3508 ar
|= (var
->avl
& 1) << 12;
3509 ar
|= (var
->l
& 1) << 13;
3510 ar
|= (var
->db
& 1) << 14;
3511 ar
|= (var
->g
& 1) << 15;
3517 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3518 struct kvm_segment
*var
, int seg
)
3520 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3521 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3523 vmx_segment_cache_clear(vmx
);
3524 if (seg
== VCPU_SREG_CS
)
3525 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3527 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3528 vmx
->rmode
.segs
[seg
] = *var
;
3529 if (seg
== VCPU_SREG_TR
)
3530 vmcs_write16(sf
->selector
, var
->selector
);
3532 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3536 vmcs_writel(sf
->base
, var
->base
);
3537 vmcs_write32(sf
->limit
, var
->limit
);
3538 vmcs_write16(sf
->selector
, var
->selector
);
3541 * Fix the "Accessed" bit in AR field of segment registers for older
3543 * IA32 arch specifies that at the time of processor reset the
3544 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3545 * is setting it to 0 in the userland code. This causes invalid guest
3546 * state vmexit when "unrestricted guest" mode is turned on.
3547 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3548 * tree. Newer qemu binaries with that qemu fix would not need this
3551 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3552 var
->type
|= 0x1; /* Accessed */
3554 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3557 vmx
->emulation_required
|= emulation_required(vcpu
);
3560 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3562 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3564 *db
= (ar
>> 14) & 1;
3565 *l
= (ar
>> 13) & 1;
3568 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3570 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3571 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3574 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3576 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3577 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3580 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3582 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3583 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3586 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3588 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3589 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3592 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3594 struct kvm_segment var
;
3597 vmx_get_segment(vcpu
, &var
, seg
);
3599 if (seg
== VCPU_SREG_CS
)
3601 ar
= vmx_segment_access_rights(&var
);
3603 if (var
.base
!= (var
.selector
<< 4))
3605 if (var
.limit
!= 0xffff)
3613 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3615 struct kvm_segment cs
;
3616 unsigned int cs_rpl
;
3618 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3619 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3623 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3627 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3628 if (cs
.dpl
> cs_rpl
)
3631 if (cs
.dpl
!= cs_rpl
)
3637 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3641 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3643 struct kvm_segment ss
;
3644 unsigned int ss_rpl
;
3646 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3647 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3651 if (ss
.type
!= 3 && ss
.type
!= 7)
3655 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3663 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3665 struct kvm_segment var
;
3668 vmx_get_segment(vcpu
, &var
, seg
);
3669 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3677 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3678 if (var
.dpl
< rpl
) /* DPL < RPL */
3682 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3688 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3690 struct kvm_segment tr
;
3692 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3696 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3698 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3706 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3708 struct kvm_segment ldtr
;
3710 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3714 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3724 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3726 struct kvm_segment cs
, ss
;
3728 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3729 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3731 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3732 (ss
.selector
& SELECTOR_RPL_MASK
));
3736 * Check if guest state is valid. Returns true if valid, false if
3738 * We assume that registers are always usable
3740 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3742 if (enable_unrestricted_guest
)
3745 /* real mode guest state checks */
3746 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3747 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3749 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3751 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3753 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3755 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3757 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3760 /* protected mode guest state checks */
3761 if (!cs_ss_rpl_check(vcpu
))
3763 if (!code_segment_valid(vcpu
))
3765 if (!stack_segment_valid(vcpu
))
3767 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3769 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3771 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3773 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3775 if (!tr_valid(vcpu
))
3777 if (!ldtr_valid(vcpu
))
3781 * - Add checks on RIP
3782 * - Add checks on RFLAGS
3788 static int init_rmode_tss(struct kvm
*kvm
)
3792 int r
, idx
, ret
= 0;
3794 idx
= srcu_read_lock(&kvm
->srcu
);
3795 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3796 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3799 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3800 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3801 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3804 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3807 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3811 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3812 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3819 srcu_read_unlock(&kvm
->srcu
, idx
);
3823 static int init_rmode_identity_map(struct kvm
*kvm
)
3826 pfn_t identity_map_pfn
;
3831 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3832 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3833 "haven't been allocated!\n");
3836 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3839 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3840 idx
= srcu_read_lock(&kvm
->srcu
);
3841 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3844 /* Set up identity-mapping pagetable for EPT in real mode */
3845 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3846 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3847 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3848 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3849 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3853 kvm
->arch
.ept_identity_pagetable_done
= true;
3856 srcu_read_unlock(&kvm
->srcu
, idx
);
3860 static void seg_setup(int seg
)
3862 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3865 vmcs_write16(sf
->selector
, 0);
3866 vmcs_writel(sf
->base
, 0);
3867 vmcs_write32(sf
->limit
, 0xffff);
3869 if (seg
== VCPU_SREG_CS
)
3870 ar
|= 0x08; /* code segment */
3872 vmcs_write32(sf
->ar_bytes
, ar
);
3875 static int alloc_apic_access_page(struct kvm
*kvm
)
3878 struct kvm_userspace_memory_region kvm_userspace_mem
;
3881 mutex_lock(&kvm
->slots_lock
);
3882 if (kvm
->arch
.apic_access_page
)
3884 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3885 kvm_userspace_mem
.flags
= 0;
3886 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3887 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3888 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3892 page
= gfn_to_page(kvm
, 0xfee00);
3893 if (is_error_page(page
)) {
3898 kvm
->arch
.apic_access_page
= page
;
3900 mutex_unlock(&kvm
->slots_lock
);
3904 static int alloc_identity_pagetable(struct kvm
*kvm
)
3907 struct kvm_userspace_memory_region kvm_userspace_mem
;
3910 mutex_lock(&kvm
->slots_lock
);
3911 if (kvm
->arch
.ept_identity_pagetable
)
3913 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3914 kvm_userspace_mem
.flags
= 0;
3915 kvm_userspace_mem
.guest_phys_addr
=
3916 kvm
->arch
.ept_identity_map_addr
;
3917 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3918 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3922 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3923 if (is_error_page(page
)) {
3928 kvm
->arch
.ept_identity_pagetable
= page
;
3930 mutex_unlock(&kvm
->slots_lock
);
3934 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3941 spin_lock(&vmx_vpid_lock
);
3942 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3943 if (vpid
< VMX_NR_VPIDS
) {
3945 __set_bit(vpid
, vmx_vpid_bitmap
);
3947 spin_unlock(&vmx_vpid_lock
);
3950 static void free_vpid(struct vcpu_vmx
*vmx
)
3954 spin_lock(&vmx_vpid_lock
);
3956 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3957 spin_unlock(&vmx_vpid_lock
);
3960 #define MSR_TYPE_R 1
3961 #define MSR_TYPE_W 2
3962 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
3965 int f
= sizeof(unsigned long);
3967 if (!cpu_has_vmx_msr_bitmap())
3971 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3972 * have the write-low and read-high bitmap offsets the wrong way round.
3973 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3975 if (msr
<= 0x1fff) {
3976 if (type
& MSR_TYPE_R
)
3978 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
3980 if (type
& MSR_TYPE_W
)
3982 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
3984 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3986 if (type
& MSR_TYPE_R
)
3988 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
3990 if (type
& MSR_TYPE_W
)
3992 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
3997 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4000 int f
= sizeof(unsigned long);
4002 if (!cpu_has_vmx_msr_bitmap())
4006 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4007 * have the write-low and read-high bitmap offsets the wrong way round.
4008 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4010 if (msr
<= 0x1fff) {
4011 if (type
& MSR_TYPE_R
)
4013 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4015 if (type
& MSR_TYPE_W
)
4017 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4019 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4021 if (type
& MSR_TYPE_R
)
4023 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4025 if (type
& MSR_TYPE_W
)
4027 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4032 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4035 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4036 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4037 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4038 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4041 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4043 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4045 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4049 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4051 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4053 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4057 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4059 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4061 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4065 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4067 return enable_apicv
&& irqchip_in_kernel(kvm
);
4071 * Send interrupt to vcpu via posted interrupt way.
4072 * 1. If target vcpu is running(non-root mode), send posted interrupt
4073 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4074 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4075 * interrupt from PIR in next vmentry.
4077 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4079 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4082 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4085 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4086 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4088 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4089 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4090 POSTED_INTR_VECTOR
);
4093 kvm_vcpu_kick(vcpu
);
4096 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4100 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4103 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4106 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4112 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4113 * will not change in the lifetime of the guest.
4114 * Note that host-state that does change is set elsewhere. E.g., host-state
4115 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4117 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4123 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4124 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4125 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4127 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4128 #ifdef CONFIG_X86_64
4130 * Load null selectors, so we can avoid reloading them in
4131 * __vmx_load_host_state(), in case userspace uses the null selectors
4132 * too (the expected case).
4134 vmcs_write16(HOST_DS_SELECTOR
, 0);
4135 vmcs_write16(HOST_ES_SELECTOR
, 0);
4137 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4138 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4140 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4141 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4143 native_store_idt(&dt
);
4144 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4145 vmx
->host_idt_base
= dt
.address
;
4147 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4149 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4150 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4151 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4152 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4154 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4155 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4156 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4160 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4162 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4164 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4165 if (is_guest_mode(&vmx
->vcpu
))
4166 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4167 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4168 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4171 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4173 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4175 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4176 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4177 return pin_based_exec_ctrl
;
4180 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4182 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4183 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4184 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4185 #ifdef CONFIG_X86_64
4186 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4187 CPU_BASED_CR8_LOAD_EXITING
;
4191 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4192 CPU_BASED_CR3_LOAD_EXITING
|
4193 CPU_BASED_INVLPG_EXITING
;
4194 return exec_control
;
4197 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4199 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4200 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4201 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4203 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4205 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4206 enable_unrestricted_guest
= 0;
4207 /* Enable INVPCID for non-ept guests may cause performance regression. */
4208 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4210 if (!enable_unrestricted_guest
)
4211 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4213 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4214 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4215 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4216 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4217 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4218 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4220 We can NOT enable shadow_vmcs here because we don't have yet
4223 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4224 return exec_control
;
4227 static void ept_set_mmio_spte_mask(void)
4230 * EPT Misconfigurations can be generated if the value of bits 2:0
4231 * of an EPT paging-structure entry is 110b (write/execute).
4232 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4235 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4239 * Sets up the vmcs for emulated real mode.
4241 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4243 #ifdef CONFIG_X86_64
4249 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4250 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4252 if (enable_shadow_vmcs
) {
4253 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4254 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4256 if (cpu_has_vmx_msr_bitmap())
4257 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4259 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4262 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4264 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4266 if (cpu_has_secondary_exec_ctrls()) {
4267 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4268 vmx_secondary_exec_control(vmx
));
4271 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4272 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4273 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4274 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4275 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4277 vmcs_write16(GUEST_INTR_STATUS
, 0);
4279 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4280 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4284 vmcs_write32(PLE_GAP
, ple_gap
);
4285 vmcs_write32(PLE_WINDOW
, ple_window
);
4288 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4289 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4290 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4292 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4293 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4294 vmx_set_constant_host_state(vmx
);
4295 #ifdef CONFIG_X86_64
4296 rdmsrl(MSR_FS_BASE
, a
);
4297 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4298 rdmsrl(MSR_GS_BASE
, a
);
4299 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4301 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4302 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4305 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4306 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4307 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4308 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4309 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4311 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4312 u32 msr_low
, msr_high
;
4314 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4315 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4316 /* Write the default value follow host pat */
4317 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4318 /* Keep arch.pat sync with GUEST_IA32_PAT */
4319 vmx
->vcpu
.arch
.pat
= host_pat
;
4322 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4323 u32 index
= vmx_msr_index
[i
];
4324 u32 data_low
, data_high
;
4327 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4329 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4331 vmx
->guest_msrs
[j
].index
= i
;
4332 vmx
->guest_msrs
[j
].data
= 0;
4333 vmx
->guest_msrs
[j
].mask
= -1ull;
4337 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
4339 /* 22.2.1, 20.8.1 */
4340 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
4342 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4343 set_cr4_guest_host_mask(vmx
);
4348 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4350 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4353 vmx
->rmode
.vm86_active
= 0;
4355 vmx
->soft_vnmi_blocked
= 0;
4357 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4358 kvm_set_cr8(&vmx
->vcpu
, 0);
4359 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4360 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4361 msr
|= MSR_IA32_APICBASE_BSP
;
4362 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4364 vmx_segment_cache_clear(vmx
);
4366 seg_setup(VCPU_SREG_CS
);
4367 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4368 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4370 seg_setup(VCPU_SREG_DS
);
4371 seg_setup(VCPU_SREG_ES
);
4372 seg_setup(VCPU_SREG_FS
);
4373 seg_setup(VCPU_SREG_GS
);
4374 seg_setup(VCPU_SREG_SS
);
4376 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4377 vmcs_writel(GUEST_TR_BASE
, 0);
4378 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4379 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4381 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4382 vmcs_writel(GUEST_LDTR_BASE
, 0);
4383 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4384 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4386 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4387 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4388 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4390 vmcs_writel(GUEST_RFLAGS
, 0x02);
4391 kvm_rip_write(vcpu
, 0xfff0);
4393 vmcs_writel(GUEST_GDTR_BASE
, 0);
4394 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4396 vmcs_writel(GUEST_IDTR_BASE
, 0);
4397 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4399 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4400 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4401 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4403 /* Special registers */
4404 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4408 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4410 if (cpu_has_vmx_tpr_shadow()) {
4411 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4412 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4413 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4414 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4415 vmcs_write32(TPR_THRESHOLD
, 0);
4418 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4419 vmcs_write64(APIC_ACCESS_ADDR
,
4420 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4422 if (vmx_vm_has_apicv(vcpu
->kvm
))
4423 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4426 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4428 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4429 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4430 vmx_set_cr4(&vmx
->vcpu
, 0);
4431 vmx_set_efer(&vmx
->vcpu
, 0);
4432 vmx_fpu_activate(&vmx
->vcpu
);
4433 update_exception_bitmap(&vmx
->vcpu
);
4435 vpid_sync_context(vmx
);
4439 * In nested virtualization, check if L1 asked to exit on external interrupts.
4440 * For most existing hypervisors, this will always return true.
4442 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4444 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4445 PIN_BASED_EXT_INTR_MASK
;
4448 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4450 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4451 PIN_BASED_NMI_EXITING
;
4454 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4456 u32 cpu_based_vm_exec_control
;
4458 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4460 * We get here if vmx_interrupt_allowed() said we can't
4461 * inject to L1 now because L2 must run. The caller will have
4462 * to make L2 exit right after entry, so we can inject to L1
4467 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4468 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4469 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4473 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4475 u32 cpu_based_vm_exec_control
;
4477 if (!cpu_has_virtual_nmis())
4478 return enable_irq_window(vcpu
);
4480 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4481 return enable_irq_window(vcpu
);
4483 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4484 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4485 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4489 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4491 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4493 int irq
= vcpu
->arch
.interrupt
.nr
;
4495 trace_kvm_inj_virq(irq
);
4497 ++vcpu
->stat
.irq_injections
;
4498 if (vmx
->rmode
.vm86_active
) {
4500 if (vcpu
->arch
.interrupt
.soft
)
4501 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4502 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4503 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4506 intr
= irq
| INTR_INFO_VALID_MASK
;
4507 if (vcpu
->arch
.interrupt
.soft
) {
4508 intr
|= INTR_TYPE_SOFT_INTR
;
4509 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4510 vmx
->vcpu
.arch
.event_exit_inst_len
);
4512 intr
|= INTR_TYPE_EXT_INTR
;
4513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4516 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4518 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4520 if (is_guest_mode(vcpu
))
4523 if (!cpu_has_virtual_nmis()) {
4525 * Tracking the NMI-blocked state in software is built upon
4526 * finding the next open IRQ window. This, in turn, depends on
4527 * well-behaving guests: They have to keep IRQs disabled at
4528 * least as long as the NMI handler runs. Otherwise we may
4529 * cause NMI nesting, maybe breaking the guest. But as this is
4530 * highly unlikely, we can live with the residual risk.
4532 vmx
->soft_vnmi_blocked
= 1;
4533 vmx
->vnmi_blocked_time
= 0;
4536 ++vcpu
->stat
.nmi_injections
;
4537 vmx
->nmi_known_unmasked
= false;
4538 if (vmx
->rmode
.vm86_active
) {
4539 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4540 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4543 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4544 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4547 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4549 if (!cpu_has_virtual_nmis())
4550 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4551 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4553 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4556 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4558 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4560 if (!cpu_has_virtual_nmis()) {
4561 if (vmx
->soft_vnmi_blocked
!= masked
) {
4562 vmx
->soft_vnmi_blocked
= masked
;
4563 vmx
->vnmi_blocked_time
= 0;
4566 vmx
->nmi_known_unmasked
= !masked
;
4568 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4569 GUEST_INTR_STATE_NMI
);
4571 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4572 GUEST_INTR_STATE_NMI
);
4576 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4578 if (is_guest_mode(vcpu
)) {
4579 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4581 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4583 if (nested_exit_on_nmi(vcpu
)) {
4584 nested_vmx_vmexit(vcpu
);
4585 vmcs12
->vm_exit_reason
= EXIT_REASON_EXCEPTION_NMI
;
4586 vmcs12
->vm_exit_intr_info
= NMI_VECTOR
|
4587 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
;
4589 * The NMI-triggered VM exit counts as injection:
4590 * clear this one and block further NMIs.
4592 vcpu
->arch
.nmi_pending
= 0;
4593 vmx_set_nmi_mask(vcpu
, true);
4598 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4601 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4602 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4603 | GUEST_INTR_STATE_NMI
));
4606 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4608 if (is_guest_mode(vcpu
)) {
4609 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4611 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4613 if (nested_exit_on_intr(vcpu
)) {
4614 nested_vmx_vmexit(vcpu
);
4615 vmcs12
->vm_exit_reason
=
4616 EXIT_REASON_EXTERNAL_INTERRUPT
;
4617 vmcs12
->vm_exit_intr_info
= 0;
4619 * fall through to normal code, but now in L1, not L2
4624 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4625 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4626 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4629 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4632 struct kvm_userspace_memory_region tss_mem
= {
4633 .slot
= TSS_PRIVATE_MEMSLOT
,
4634 .guest_phys_addr
= addr
,
4635 .memory_size
= PAGE_SIZE
* 3,
4639 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4642 kvm
->arch
.tss_addr
= addr
;
4643 if (!init_rmode_tss(kvm
))
4649 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4654 * Update instruction length as we may reinject the exception
4655 * from user space while in guest debugging mode.
4657 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4658 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4659 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4663 if (vcpu
->guest_debug
&
4664 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4681 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4682 int vec
, u32 err_code
)
4685 * Instruction with address size override prefix opcode 0x67
4686 * Cause the #SS fault with 0 error code in VM86 mode.
4688 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4689 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4690 if (vcpu
->arch
.halt_request
) {
4691 vcpu
->arch
.halt_request
= 0;
4692 return kvm_emulate_halt(vcpu
);
4700 * Forward all other exceptions that are valid in real mode.
4701 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4702 * the required debugging infrastructure rework.
4704 kvm_queue_exception(vcpu
, vec
);
4709 * Trigger machine check on the host. We assume all the MSRs are already set up
4710 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4711 * We pass a fake environment to the machine check handler because we want
4712 * the guest to be always treated like user space, no matter what context
4713 * it used internally.
4715 static void kvm_machine_check(void)
4717 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4718 struct pt_regs regs
= {
4719 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4720 .flags
= X86_EFLAGS_IF
,
4723 do_machine_check(®s
, 0);
4727 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4729 /* already handled by vcpu_run */
4733 static int handle_exception(struct kvm_vcpu
*vcpu
)
4735 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4736 struct kvm_run
*kvm_run
= vcpu
->run
;
4737 u32 intr_info
, ex_no
, error_code
;
4738 unsigned long cr2
, rip
, dr6
;
4740 enum emulation_result er
;
4742 vect_info
= vmx
->idt_vectoring_info
;
4743 intr_info
= vmx
->exit_intr_info
;
4745 if (is_machine_check(intr_info
))
4746 return handle_machine_check(vcpu
);
4748 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4749 return 1; /* already handled by vmx_vcpu_run() */
4751 if (is_no_device(intr_info
)) {
4752 vmx_fpu_activate(vcpu
);
4756 if (is_invalid_opcode(intr_info
)) {
4757 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4758 if (er
!= EMULATE_DONE
)
4759 kvm_queue_exception(vcpu
, UD_VECTOR
);
4764 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4765 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4768 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4769 * MMIO, it is better to report an internal error.
4770 * See the comments in vmx_handle_exit.
4772 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4773 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4774 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4775 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4776 vcpu
->run
->internal
.ndata
= 2;
4777 vcpu
->run
->internal
.data
[0] = vect_info
;
4778 vcpu
->run
->internal
.data
[1] = intr_info
;
4782 if (is_page_fault(intr_info
)) {
4783 /* EPT won't cause page fault directly */
4785 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4786 trace_kvm_page_fault(cr2
, error_code
);
4788 if (kvm_event_needs_reinjection(vcpu
))
4789 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4790 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4793 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4795 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4796 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4800 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4801 if (!(vcpu
->guest_debug
&
4802 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4803 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4804 kvm_queue_exception(vcpu
, DB_VECTOR
);
4807 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4808 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4812 * Update instruction length as we may reinject #BP from
4813 * user space while in guest debugging mode. Reading it for
4814 * #DB as well causes no harm, it is not used in that case.
4816 vmx
->vcpu
.arch
.event_exit_inst_len
=
4817 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4818 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4819 rip
= kvm_rip_read(vcpu
);
4820 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4821 kvm_run
->debug
.arch
.exception
= ex_no
;
4824 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4825 kvm_run
->ex
.exception
= ex_no
;
4826 kvm_run
->ex
.error_code
= error_code
;
4832 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4834 ++vcpu
->stat
.irq_exits
;
4838 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4840 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4844 static int handle_io(struct kvm_vcpu
*vcpu
)
4846 unsigned long exit_qualification
;
4847 int size
, in
, string
;
4850 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4851 string
= (exit_qualification
& 16) != 0;
4852 in
= (exit_qualification
& 8) != 0;
4854 ++vcpu
->stat
.io_exits
;
4857 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4859 port
= exit_qualification
>> 16;
4860 size
= (exit_qualification
& 7) + 1;
4861 skip_emulated_instruction(vcpu
);
4863 return kvm_fast_pio_out(vcpu
, size
, port
);
4867 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4870 * Patch in the VMCALL instruction:
4872 hypercall
[0] = 0x0f;
4873 hypercall
[1] = 0x01;
4874 hypercall
[2] = 0xc1;
4877 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4879 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4881 if (nested_vmx_secondary_ctls_high
&
4882 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4883 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4884 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4885 return (val
& always_on
) == always_on
;
4888 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4889 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4891 if (is_guest_mode(vcpu
)) {
4892 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4893 unsigned long orig_val
= val
;
4896 * We get here when L2 changed cr0 in a way that did not change
4897 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4898 * but did change L0 shadowed bits. So we first calculate the
4899 * effective cr0 value that L1 would like to write into the
4900 * hardware. It consists of the L2-owned bits from the new
4901 * value combined with the L1-owned bits from L1's guest_cr0.
4903 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4904 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4906 if (!nested_cr0_valid(vmcs12
, val
))
4909 if (kvm_set_cr0(vcpu
, val
))
4911 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4914 if (to_vmx(vcpu
)->nested
.vmxon
&&
4915 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4917 return kvm_set_cr0(vcpu
, val
);
4921 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4923 if (is_guest_mode(vcpu
)) {
4924 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4925 unsigned long orig_val
= val
;
4927 /* analogously to handle_set_cr0 */
4928 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4929 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4930 if (kvm_set_cr4(vcpu
, val
))
4932 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
4935 return kvm_set_cr4(vcpu
, val
);
4938 /* called to set cr0 as approriate for clts instruction exit. */
4939 static void handle_clts(struct kvm_vcpu
*vcpu
)
4941 if (is_guest_mode(vcpu
)) {
4943 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4944 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4945 * just pretend it's off (also in arch.cr0 for fpu_activate).
4947 vmcs_writel(CR0_READ_SHADOW
,
4948 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4949 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4951 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4954 static int handle_cr(struct kvm_vcpu
*vcpu
)
4956 unsigned long exit_qualification
, val
;
4961 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4962 cr
= exit_qualification
& 15;
4963 reg
= (exit_qualification
>> 8) & 15;
4964 switch ((exit_qualification
>> 4) & 3) {
4965 case 0: /* mov to cr */
4966 val
= kvm_register_read(vcpu
, reg
);
4967 trace_kvm_cr_write(cr
, val
);
4970 err
= handle_set_cr0(vcpu
, val
);
4971 kvm_complete_insn_gp(vcpu
, err
);
4974 err
= kvm_set_cr3(vcpu
, val
);
4975 kvm_complete_insn_gp(vcpu
, err
);
4978 err
= handle_set_cr4(vcpu
, val
);
4979 kvm_complete_insn_gp(vcpu
, err
);
4982 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4983 u8 cr8
= kvm_register_read(vcpu
, reg
);
4984 err
= kvm_set_cr8(vcpu
, cr8
);
4985 kvm_complete_insn_gp(vcpu
, err
);
4986 if (irqchip_in_kernel(vcpu
->kvm
))
4988 if (cr8_prev
<= cr8
)
4990 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4997 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4998 skip_emulated_instruction(vcpu
);
4999 vmx_fpu_activate(vcpu
);
5001 case 1: /*mov from cr*/
5004 val
= kvm_read_cr3(vcpu
);
5005 kvm_register_write(vcpu
, reg
, val
);
5006 trace_kvm_cr_read(cr
, val
);
5007 skip_emulated_instruction(vcpu
);
5010 val
= kvm_get_cr8(vcpu
);
5011 kvm_register_write(vcpu
, reg
, val
);
5012 trace_kvm_cr_read(cr
, val
);
5013 skip_emulated_instruction(vcpu
);
5018 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5019 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5020 kvm_lmsw(vcpu
, val
);
5022 skip_emulated_instruction(vcpu
);
5027 vcpu
->run
->exit_reason
= 0;
5028 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5029 (int)(exit_qualification
>> 4) & 3, cr
);
5033 static int handle_dr(struct kvm_vcpu
*vcpu
)
5035 unsigned long exit_qualification
;
5038 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5039 if (!kvm_require_cpl(vcpu
, 0))
5041 dr
= vmcs_readl(GUEST_DR7
);
5044 * As the vm-exit takes precedence over the debug trap, we
5045 * need to emulate the latter, either for the host or the
5046 * guest debugging itself.
5048 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5049 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5050 vcpu
->run
->debug
.arch
.dr7
= dr
;
5051 vcpu
->run
->debug
.arch
.pc
=
5052 vmcs_readl(GUEST_CS_BASE
) +
5053 vmcs_readl(GUEST_RIP
);
5054 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5055 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5058 vcpu
->arch
.dr7
&= ~DR7_GD
;
5059 vcpu
->arch
.dr6
|= DR6_BD
;
5060 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5061 kvm_queue_exception(vcpu
, DB_VECTOR
);
5066 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5067 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5068 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5069 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5071 if (!kvm_get_dr(vcpu
, dr
, &val
))
5072 kvm_register_write(vcpu
, reg
, val
);
5074 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
5075 skip_emulated_instruction(vcpu
);
5079 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5081 vmcs_writel(GUEST_DR7
, val
);
5084 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5086 kvm_emulate_cpuid(vcpu
);
5090 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5092 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5095 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5096 trace_kvm_msr_read_ex(ecx
);
5097 kvm_inject_gp(vcpu
, 0);
5101 trace_kvm_msr_read(ecx
, data
);
5103 /* FIXME: handling of bits 32:63 of rax, rdx */
5104 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5105 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5106 skip_emulated_instruction(vcpu
);
5110 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5112 struct msr_data msr
;
5113 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5114 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5115 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5119 msr
.host_initiated
= false;
5120 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5121 trace_kvm_msr_write_ex(ecx
, data
);
5122 kvm_inject_gp(vcpu
, 0);
5126 trace_kvm_msr_write(ecx
, data
);
5127 skip_emulated_instruction(vcpu
);
5131 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5133 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5137 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5139 u32 cpu_based_vm_exec_control
;
5141 /* clear pending irq */
5142 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5143 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5144 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5146 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5148 ++vcpu
->stat
.irq_window_exits
;
5151 * If the user space waits to inject interrupts, exit as soon as
5154 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5155 vcpu
->run
->request_interrupt_window
&&
5156 !kvm_cpu_has_interrupt(vcpu
)) {
5157 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5163 static int handle_halt(struct kvm_vcpu
*vcpu
)
5165 skip_emulated_instruction(vcpu
);
5166 return kvm_emulate_halt(vcpu
);
5169 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5171 skip_emulated_instruction(vcpu
);
5172 kvm_emulate_hypercall(vcpu
);
5176 static int handle_invd(struct kvm_vcpu
*vcpu
)
5178 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5181 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5183 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5185 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5186 skip_emulated_instruction(vcpu
);
5190 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5194 err
= kvm_rdpmc(vcpu
);
5195 kvm_complete_insn_gp(vcpu
, err
);
5200 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5202 skip_emulated_instruction(vcpu
);
5203 kvm_emulate_wbinvd(vcpu
);
5207 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5209 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5210 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5212 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5213 skip_emulated_instruction(vcpu
);
5217 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5219 if (likely(fasteoi
)) {
5220 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5221 int access_type
, offset
;
5223 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5224 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5226 * Sane guest uses MOV to write EOI, with written value
5227 * not cared. So make a short-circuit here by avoiding
5228 * heavy instruction emulation.
5230 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5231 (offset
== APIC_EOI
)) {
5232 kvm_lapic_set_eoi(vcpu
);
5233 skip_emulated_instruction(vcpu
);
5237 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5240 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5242 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5243 int vector
= exit_qualification
& 0xff;
5245 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5246 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5250 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5252 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5253 u32 offset
= exit_qualification
& 0xfff;
5255 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5256 kvm_apic_write_nodecode(vcpu
, offset
);
5260 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5263 unsigned long exit_qualification
;
5264 bool has_error_code
= false;
5267 int reason
, type
, idt_v
, idt_index
;
5269 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5270 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5271 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5273 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5275 reason
= (u32
)exit_qualification
>> 30;
5276 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5278 case INTR_TYPE_NMI_INTR
:
5279 vcpu
->arch
.nmi_injected
= false;
5280 vmx_set_nmi_mask(vcpu
, true);
5282 case INTR_TYPE_EXT_INTR
:
5283 case INTR_TYPE_SOFT_INTR
:
5284 kvm_clear_interrupt_queue(vcpu
);
5286 case INTR_TYPE_HARD_EXCEPTION
:
5287 if (vmx
->idt_vectoring_info
&
5288 VECTORING_INFO_DELIVER_CODE_MASK
) {
5289 has_error_code
= true;
5291 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5294 case INTR_TYPE_SOFT_EXCEPTION
:
5295 kvm_clear_exception_queue(vcpu
);
5301 tss_selector
= exit_qualification
;
5303 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5304 type
!= INTR_TYPE_EXT_INTR
&&
5305 type
!= INTR_TYPE_NMI_INTR
))
5306 skip_emulated_instruction(vcpu
);
5308 if (kvm_task_switch(vcpu
, tss_selector
,
5309 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5310 has_error_code
, error_code
) == EMULATE_FAIL
) {
5311 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5312 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5313 vcpu
->run
->internal
.ndata
= 0;
5317 /* clear all local breakpoint enable flags */
5318 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5321 * TODO: What about debug traps on tss switch?
5322 * Are we supposed to inject them and update dr6?
5328 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5330 unsigned long exit_qualification
;
5335 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5337 gla_validity
= (exit_qualification
>> 7) & 0x3;
5338 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5339 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5340 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5341 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5342 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5343 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5344 (long unsigned int)exit_qualification
);
5345 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5346 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5351 * EPT violation happened while executing iret from NMI,
5352 * "blocked by NMI" bit has to be set before next VM entry.
5353 * There are errata that may cause this bit to not be set:
5356 if (exit_qualification
& INTR_INFO_UNBLOCK_NMI
)
5357 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5359 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5360 trace_kvm_page_fault(gpa
, exit_qualification
);
5362 /* It is a write fault? */
5363 error_code
= exit_qualification
& (1U << 1);
5364 /* It is a fetch fault? */
5365 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5366 /* ept page table is present? */
5367 error_code
|= (exit_qualification
>> 3) & 0x1;
5369 vcpu
->arch
.exit_qualification
= exit_qualification
;
5371 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5374 static u64
ept_rsvd_mask(u64 spte
, int level
)
5379 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5380 mask
|= (1ULL << i
);
5383 /* bits 7:3 reserved */
5385 else if (level
== 2) {
5386 if (spte
& (1ULL << 7))
5387 /* 2MB ref, bits 20:12 reserved */
5390 /* bits 6:3 reserved */
5397 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5400 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5402 /* 010b (write-only) */
5403 WARN_ON((spte
& 0x7) == 0x2);
5405 /* 110b (write/execute) */
5406 WARN_ON((spte
& 0x7) == 0x6);
5408 /* 100b (execute-only) and value not supported by logical processor */
5409 if (!cpu_has_vmx_ept_execute_only())
5410 WARN_ON((spte
& 0x7) == 0x4);
5414 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5416 if (rsvd_bits
!= 0) {
5417 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5418 __func__
, rsvd_bits
);
5422 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5423 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5425 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5426 ept_mem_type
== 7) {
5427 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5428 __func__
, ept_mem_type
);
5435 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5438 int nr_sptes
, i
, ret
;
5441 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5443 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5444 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5445 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5448 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5449 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5451 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5454 /* It is the real ept misconfig */
5455 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5456 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5458 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5460 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5461 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5463 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5464 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5469 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5471 u32 cpu_based_vm_exec_control
;
5473 /* clear pending NMI */
5474 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5475 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5476 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5477 ++vcpu
->stat
.nmi_window_exits
;
5478 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5483 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5485 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5486 enum emulation_result err
= EMULATE_DONE
;
5489 bool intr_window_requested
;
5490 unsigned count
= 130;
5492 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5493 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5495 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5496 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5497 return handle_interrupt_window(&vmx
->vcpu
);
5499 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5502 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5504 if (err
== EMULATE_USER_EXIT
) {
5505 ++vcpu
->stat
.mmio_exits
;
5510 if (err
!= EMULATE_DONE
) {
5511 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5512 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5513 vcpu
->run
->internal
.ndata
= 0;
5517 if (vcpu
->arch
.halt_request
) {
5518 vcpu
->arch
.halt_request
= 0;
5519 ret
= kvm_emulate_halt(vcpu
);
5523 if (signal_pending(current
))
5529 vmx
->emulation_required
= emulation_required(vcpu
);
5535 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5536 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5538 static int handle_pause(struct kvm_vcpu
*vcpu
)
5540 skip_emulated_instruction(vcpu
);
5541 kvm_vcpu_on_spin(vcpu
);
5546 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5548 kvm_queue_exception(vcpu
, UD_VECTOR
);
5553 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5554 * We could reuse a single VMCS for all the L2 guests, but we also want the
5555 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5556 * allows keeping them loaded on the processor, and in the future will allow
5557 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5558 * every entry if they never change.
5559 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5560 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5562 * The following functions allocate and free a vmcs02 in this pool.
5565 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5566 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5568 struct vmcs02_list
*item
;
5569 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5570 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5571 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5572 return &item
->vmcs02
;
5575 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5576 /* Recycle the least recently used VMCS. */
5577 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5578 struct vmcs02_list
, list
);
5579 item
->vmptr
= vmx
->nested
.current_vmptr
;
5580 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5581 return &item
->vmcs02
;
5584 /* Create a new VMCS */
5585 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5588 item
->vmcs02
.vmcs
= alloc_vmcs();
5589 if (!item
->vmcs02
.vmcs
) {
5593 loaded_vmcs_init(&item
->vmcs02
);
5594 item
->vmptr
= vmx
->nested
.current_vmptr
;
5595 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5596 vmx
->nested
.vmcs02_num
++;
5597 return &item
->vmcs02
;
5600 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5601 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5603 struct vmcs02_list
*item
;
5604 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5605 if (item
->vmptr
== vmptr
) {
5606 free_loaded_vmcs(&item
->vmcs02
);
5607 list_del(&item
->list
);
5609 vmx
->nested
.vmcs02_num
--;
5615 * Free all VMCSs saved for this vcpu, except the one pointed by
5616 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5617 * currently used, if running L2), and vmcs01 when running L2.
5619 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5621 struct vmcs02_list
*item
, *n
;
5622 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5623 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5624 free_loaded_vmcs(&item
->vmcs02
);
5625 list_del(&item
->list
);
5628 vmx
->nested
.vmcs02_num
= 0;
5630 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5631 free_loaded_vmcs(&vmx
->vmcs01
);
5635 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5636 * set the success or error code of an emulated VMX instruction, as specified
5637 * by Vol 2B, VMX Instruction Reference, "Conventions".
5639 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5641 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5642 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5643 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5646 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5648 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5649 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5650 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5654 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5655 u32 vm_instruction_error
)
5657 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5659 * failValid writes the error number to the current VMCS, which
5660 * can't be done there isn't a current VMCS.
5662 nested_vmx_failInvalid(vcpu
);
5665 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5666 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5667 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5669 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5671 * We don't need to force a shadow sync because
5672 * VM_INSTRUCTION_ERROR is not shadowed
5677 * Emulate the VMXON instruction.
5678 * Currently, we just remember that VMX is active, and do not save or even
5679 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5680 * do not currently need to store anything in that guest-allocated memory
5681 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5682 * argument is different from the VMXON pointer (which the spec says they do).
5684 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5686 struct kvm_segment cs
;
5687 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5688 struct vmcs
*shadow_vmcs
;
5689 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5690 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5692 /* The Intel VMX Instruction Reference lists a bunch of bits that
5693 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5694 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5695 * Otherwise, we should fail with #UD. We test these now:
5697 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5698 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5699 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5700 kvm_queue_exception(vcpu
, UD_VECTOR
);
5704 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5705 if (is_long_mode(vcpu
) && !cs
.l
) {
5706 kvm_queue_exception(vcpu
, UD_VECTOR
);
5710 if (vmx_get_cpl(vcpu
)) {
5711 kvm_inject_gp(vcpu
, 0);
5714 if (vmx
->nested
.vmxon
) {
5715 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5716 skip_emulated_instruction(vcpu
);
5720 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5721 != VMXON_NEEDED_FEATURES
) {
5722 kvm_inject_gp(vcpu
, 0);
5726 if (enable_shadow_vmcs
) {
5727 shadow_vmcs
= alloc_vmcs();
5730 /* mark vmcs as shadow */
5731 shadow_vmcs
->revision_id
|= (1u << 31);
5732 /* init shadow vmcs */
5733 vmcs_clear(shadow_vmcs
);
5734 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5737 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5738 vmx
->nested
.vmcs02_num
= 0;
5740 vmx
->nested
.vmxon
= true;
5742 skip_emulated_instruction(vcpu
);
5743 nested_vmx_succeed(vcpu
);
5748 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5749 * for running VMX instructions (except VMXON, whose prerequisites are
5750 * slightly different). It also specifies what exception to inject otherwise.
5752 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5754 struct kvm_segment cs
;
5755 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5757 if (!vmx
->nested
.vmxon
) {
5758 kvm_queue_exception(vcpu
, UD_VECTOR
);
5762 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5763 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5764 (is_long_mode(vcpu
) && !cs
.l
)) {
5765 kvm_queue_exception(vcpu
, UD_VECTOR
);
5769 if (vmx_get_cpl(vcpu
)) {
5770 kvm_inject_gp(vcpu
, 0);
5777 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5780 if (enable_shadow_vmcs
) {
5781 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5782 /* copy to memory all shadowed fields in case
5783 they were modified */
5784 copy_shadow_to_vmcs12(vmx
);
5785 vmx
->nested
.sync_shadow_vmcs
= false;
5786 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5787 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5789 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5792 kunmap(vmx
->nested
.current_vmcs12_page
);
5793 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5797 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5798 * just stops using VMX.
5800 static void free_nested(struct vcpu_vmx
*vmx
)
5802 if (!vmx
->nested
.vmxon
)
5804 vmx
->nested
.vmxon
= false;
5805 if (vmx
->nested
.current_vmptr
!= -1ull) {
5806 nested_release_vmcs12(vmx
);
5807 vmx
->nested
.current_vmptr
= -1ull;
5808 vmx
->nested
.current_vmcs12
= NULL
;
5810 if (enable_shadow_vmcs
)
5811 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5812 /* Unpin physical memory we referred to in current vmcs02 */
5813 if (vmx
->nested
.apic_access_page
) {
5814 nested_release_page(vmx
->nested
.apic_access_page
);
5815 vmx
->nested
.apic_access_page
= 0;
5818 nested_free_all_saved_vmcss(vmx
);
5821 /* Emulate the VMXOFF instruction */
5822 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5824 if (!nested_vmx_check_permission(vcpu
))
5826 free_nested(to_vmx(vcpu
));
5827 skip_emulated_instruction(vcpu
);
5828 nested_vmx_succeed(vcpu
);
5833 * Decode the memory-address operand of a vmx instruction, as recorded on an
5834 * exit caused by such an instruction (run by a guest hypervisor).
5835 * On success, returns 0. When the operand is invalid, returns 1 and throws
5838 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5839 unsigned long exit_qualification
,
5840 u32 vmx_instruction_info
, gva_t
*ret
)
5843 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5844 * Execution", on an exit, vmx_instruction_info holds most of the
5845 * addressing components of the operand. Only the displacement part
5846 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5847 * For how an actual address is calculated from all these components,
5848 * refer to Vol. 1, "Operand Addressing".
5850 int scaling
= vmx_instruction_info
& 3;
5851 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5852 bool is_reg
= vmx_instruction_info
& (1u << 10);
5853 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5854 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5855 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5856 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5857 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5860 kvm_queue_exception(vcpu
, UD_VECTOR
);
5864 /* Addr = segment_base + offset */
5865 /* offset = base + [index * scale] + displacement */
5866 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5868 *ret
+= kvm_register_read(vcpu
, base_reg
);
5870 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5871 *ret
+= exit_qualification
; /* holds the displacement */
5873 if (addr_size
== 1) /* 32 bit */
5877 * TODO: throw #GP (and return 1) in various cases that the VM*
5878 * instructions require it - e.g., offset beyond segment limit,
5879 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5880 * address, and so on. Currently these are not checked.
5885 /* Emulate the VMCLEAR instruction */
5886 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5888 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5891 struct vmcs12
*vmcs12
;
5893 struct x86_exception e
;
5895 if (!nested_vmx_check_permission(vcpu
))
5898 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5899 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5902 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5903 sizeof(vmptr
), &e
)) {
5904 kvm_inject_page_fault(vcpu
, &e
);
5908 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5909 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5910 skip_emulated_instruction(vcpu
);
5914 if (vmptr
== vmx
->nested
.current_vmptr
) {
5915 nested_release_vmcs12(vmx
);
5916 vmx
->nested
.current_vmptr
= -1ull;
5917 vmx
->nested
.current_vmcs12
= NULL
;
5920 page
= nested_get_page(vcpu
, vmptr
);
5923 * For accurate processor emulation, VMCLEAR beyond available
5924 * physical memory should do nothing at all. However, it is
5925 * possible that a nested vmx bug, not a guest hypervisor bug,
5926 * resulted in this case, so let's shut down before doing any
5929 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5932 vmcs12
= kmap(page
);
5933 vmcs12
->launch_state
= 0;
5935 nested_release_page(page
);
5937 nested_free_vmcs02(vmx
, vmptr
);
5939 skip_emulated_instruction(vcpu
);
5940 nested_vmx_succeed(vcpu
);
5944 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5946 /* Emulate the VMLAUNCH instruction */
5947 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5949 return nested_vmx_run(vcpu
, true);
5952 /* Emulate the VMRESUME instruction */
5953 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5956 return nested_vmx_run(vcpu
, false);
5959 enum vmcs_field_type
{
5960 VMCS_FIELD_TYPE_U16
= 0,
5961 VMCS_FIELD_TYPE_U64
= 1,
5962 VMCS_FIELD_TYPE_U32
= 2,
5963 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5966 static inline int vmcs_field_type(unsigned long field
)
5968 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5969 return VMCS_FIELD_TYPE_U32
;
5970 return (field
>> 13) & 0x3 ;
5973 static inline int vmcs_field_readonly(unsigned long field
)
5975 return (((field
>> 10) & 0x3) == 1);
5979 * Read a vmcs12 field. Since these can have varying lengths and we return
5980 * one type, we chose the biggest type (u64) and zero-extend the return value
5981 * to that size. Note that the caller, handle_vmread, might need to use only
5982 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5983 * 64-bit fields are to be returned).
5985 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5986 unsigned long field
, u64
*ret
)
5988 short offset
= vmcs_field_to_offset(field
);
5994 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5996 switch (vmcs_field_type(field
)) {
5997 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5998 *ret
= *((natural_width
*)p
);
6000 case VMCS_FIELD_TYPE_U16
:
6003 case VMCS_FIELD_TYPE_U32
:
6006 case VMCS_FIELD_TYPE_U64
:
6010 return 0; /* can never happen. */
6015 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6016 unsigned long field
, u64 field_value
){
6017 short offset
= vmcs_field_to_offset(field
);
6018 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6022 switch (vmcs_field_type(field
)) {
6023 case VMCS_FIELD_TYPE_U16
:
6024 *(u16
*)p
= field_value
;
6026 case VMCS_FIELD_TYPE_U32
:
6027 *(u32
*)p
= field_value
;
6029 case VMCS_FIELD_TYPE_U64
:
6030 *(u64
*)p
= field_value
;
6032 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6033 *(natural_width
*)p
= field_value
;
6036 return false; /* can never happen. */
6041 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6044 unsigned long field
;
6046 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6047 const unsigned long *fields
= shadow_read_write_fields
;
6048 const int num_fields
= max_shadow_read_write_fields
;
6050 vmcs_load(shadow_vmcs
);
6052 for (i
= 0; i
< num_fields
; i
++) {
6054 switch (vmcs_field_type(field
)) {
6055 case VMCS_FIELD_TYPE_U16
:
6056 field_value
= vmcs_read16(field
);
6058 case VMCS_FIELD_TYPE_U32
:
6059 field_value
= vmcs_read32(field
);
6061 case VMCS_FIELD_TYPE_U64
:
6062 field_value
= vmcs_read64(field
);
6064 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6065 field_value
= vmcs_readl(field
);
6068 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6071 vmcs_clear(shadow_vmcs
);
6072 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6075 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6077 const unsigned long *fields
[] = {
6078 shadow_read_write_fields
,
6079 shadow_read_only_fields
6081 const int max_fields
[] = {
6082 max_shadow_read_write_fields
,
6083 max_shadow_read_only_fields
6086 unsigned long field
;
6087 u64 field_value
= 0;
6088 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6090 vmcs_load(shadow_vmcs
);
6092 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6093 for (i
= 0; i
< max_fields
[q
]; i
++) {
6094 field
= fields
[q
][i
];
6095 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6097 switch (vmcs_field_type(field
)) {
6098 case VMCS_FIELD_TYPE_U16
:
6099 vmcs_write16(field
, (u16
)field_value
);
6101 case VMCS_FIELD_TYPE_U32
:
6102 vmcs_write32(field
, (u32
)field_value
);
6104 case VMCS_FIELD_TYPE_U64
:
6105 vmcs_write64(field
, (u64
)field_value
);
6107 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6108 vmcs_writel(field
, (long)field_value
);
6114 vmcs_clear(shadow_vmcs
);
6115 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6119 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6120 * used before) all generate the same failure when it is missing.
6122 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6124 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6125 if (vmx
->nested
.current_vmptr
== -1ull) {
6126 nested_vmx_failInvalid(vcpu
);
6127 skip_emulated_instruction(vcpu
);
6133 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6135 unsigned long field
;
6137 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6138 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6141 if (!nested_vmx_check_permission(vcpu
) ||
6142 !nested_vmx_check_vmcs12(vcpu
))
6145 /* Decode instruction info and find the field to read */
6146 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6147 /* Read the field, zero-extended to a u64 field_value */
6148 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6149 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6150 skip_emulated_instruction(vcpu
);
6154 * Now copy part of this value to register or memory, as requested.
6155 * Note that the number of bits actually copied is 32 or 64 depending
6156 * on the guest's mode (32 or 64 bit), not on the given field's length.
6158 if (vmx_instruction_info
& (1u << 10)) {
6159 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6162 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6163 vmx_instruction_info
, &gva
))
6165 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6166 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6167 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6170 nested_vmx_succeed(vcpu
);
6171 skip_emulated_instruction(vcpu
);
6176 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6178 unsigned long field
;
6180 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6181 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6182 /* The value to write might be 32 or 64 bits, depending on L1's long
6183 * mode, and eventually we need to write that into a field of several
6184 * possible lengths. The code below first zero-extends the value to 64
6185 * bit (field_value), and then copies only the approriate number of
6186 * bits into the vmcs12 field.
6188 u64 field_value
= 0;
6189 struct x86_exception e
;
6191 if (!nested_vmx_check_permission(vcpu
) ||
6192 !nested_vmx_check_vmcs12(vcpu
))
6195 if (vmx_instruction_info
& (1u << 10))
6196 field_value
= kvm_register_read(vcpu
,
6197 (((vmx_instruction_info
) >> 3) & 0xf));
6199 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6200 vmx_instruction_info
, &gva
))
6202 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6203 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6204 kvm_inject_page_fault(vcpu
, &e
);
6210 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6211 if (vmcs_field_readonly(field
)) {
6212 nested_vmx_failValid(vcpu
,
6213 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6214 skip_emulated_instruction(vcpu
);
6218 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6219 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6220 skip_emulated_instruction(vcpu
);
6224 nested_vmx_succeed(vcpu
);
6225 skip_emulated_instruction(vcpu
);
6229 /* Emulate the VMPTRLD instruction */
6230 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6232 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6235 struct x86_exception e
;
6238 if (!nested_vmx_check_permission(vcpu
))
6241 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6242 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6245 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6246 sizeof(vmptr
), &e
)) {
6247 kvm_inject_page_fault(vcpu
, &e
);
6251 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6252 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6253 skip_emulated_instruction(vcpu
);
6257 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6258 struct vmcs12
*new_vmcs12
;
6260 page
= nested_get_page(vcpu
, vmptr
);
6262 nested_vmx_failInvalid(vcpu
);
6263 skip_emulated_instruction(vcpu
);
6266 new_vmcs12
= kmap(page
);
6267 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6269 nested_release_page_clean(page
);
6270 nested_vmx_failValid(vcpu
,
6271 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6272 skip_emulated_instruction(vcpu
);
6275 if (vmx
->nested
.current_vmptr
!= -1ull)
6276 nested_release_vmcs12(vmx
);
6278 vmx
->nested
.current_vmptr
= vmptr
;
6279 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6280 vmx
->nested
.current_vmcs12_page
= page
;
6281 if (enable_shadow_vmcs
) {
6282 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6283 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6284 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6285 vmcs_write64(VMCS_LINK_POINTER
,
6286 __pa(vmx
->nested
.current_shadow_vmcs
));
6287 vmx
->nested
.sync_shadow_vmcs
= true;
6291 nested_vmx_succeed(vcpu
);
6292 skip_emulated_instruction(vcpu
);
6296 /* Emulate the VMPTRST instruction */
6297 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6299 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6300 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6302 struct x86_exception e
;
6304 if (!nested_vmx_check_permission(vcpu
))
6307 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6308 vmx_instruction_info
, &vmcs_gva
))
6310 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6311 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6312 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6314 kvm_inject_page_fault(vcpu
, &e
);
6317 nested_vmx_succeed(vcpu
);
6318 skip_emulated_instruction(vcpu
);
6322 /* Emulate the INVEPT instruction */
6323 static int handle_invept(struct kvm_vcpu
*vcpu
)
6325 u32 vmx_instruction_info
, types
;
6328 struct x86_exception e
;
6332 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6334 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6335 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6336 kvm_queue_exception(vcpu
, UD_VECTOR
);
6340 if (!nested_vmx_check_permission(vcpu
))
6343 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6344 kvm_queue_exception(vcpu
, UD_VECTOR
);
6348 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6349 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6351 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6353 if (!(types
& (1UL << type
))) {
6354 nested_vmx_failValid(vcpu
,
6355 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6359 /* According to the Intel VMX instruction reference, the memory
6360 * operand is read even if it isn't needed (e.g., for type==global)
6362 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6363 vmx_instruction_info
, &gva
))
6365 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6366 sizeof(operand
), &e
)) {
6367 kvm_inject_page_fault(vcpu
, &e
);
6372 case VMX_EPT_EXTENT_CONTEXT
:
6373 if ((operand
.eptp
& eptp_mask
) !=
6374 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6376 case VMX_EPT_EXTENT_GLOBAL
:
6377 kvm_mmu_sync_roots(vcpu
);
6378 kvm_mmu_flush_tlb(vcpu
);
6379 nested_vmx_succeed(vcpu
);
6386 skip_emulated_instruction(vcpu
);
6391 * The exit handlers return 1 if the exit was handled fully and guest execution
6392 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6393 * to be done to userspace and return 0.
6395 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6396 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6397 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6398 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6399 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6400 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6401 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6402 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6403 [EXIT_REASON_CPUID
] = handle_cpuid
,
6404 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6405 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6406 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6407 [EXIT_REASON_HLT
] = handle_halt
,
6408 [EXIT_REASON_INVD
] = handle_invd
,
6409 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6410 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6411 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6412 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6413 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6414 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6415 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6416 [EXIT_REASON_VMREAD
] = handle_vmread
,
6417 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6418 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6419 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6420 [EXIT_REASON_VMON
] = handle_vmon
,
6421 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6422 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6423 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6424 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6425 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6426 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6427 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6428 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6429 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6430 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6431 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6432 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6433 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6434 [EXIT_REASON_INVEPT
] = handle_invept
,
6437 static const int kvm_vmx_max_exit_handlers
=
6438 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6440 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6441 struct vmcs12
*vmcs12
)
6443 unsigned long exit_qualification
;
6444 gpa_t bitmap
, last_bitmap
;
6449 if (nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
))
6452 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6455 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6457 port
= exit_qualification
>> 16;
6458 size
= (exit_qualification
& 7) + 1;
6460 last_bitmap
= (gpa_t
)-1;
6465 bitmap
= vmcs12
->io_bitmap_a
;
6466 else if (port
< 0x10000)
6467 bitmap
= vmcs12
->io_bitmap_b
;
6470 bitmap
+= (port
& 0x7fff) / 8;
6472 if (last_bitmap
!= bitmap
)
6473 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6475 if (b
& (1 << (port
& 7)))
6480 last_bitmap
= bitmap
;
6487 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6488 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6489 * disinterest in the current event (read or write a specific MSR) by using an
6490 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6492 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6493 struct vmcs12
*vmcs12
, u32 exit_reason
)
6495 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6498 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6502 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6503 * for the four combinations of read/write and low/high MSR numbers.
6504 * First we need to figure out which of the four to use:
6506 bitmap
= vmcs12
->msr_bitmap
;
6507 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6509 if (msr_index
>= 0xc0000000) {
6510 msr_index
-= 0xc0000000;
6514 /* Then read the msr_index'th bit from this bitmap: */
6515 if (msr_index
< 1024*8) {
6517 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6519 return 1 & (b
>> (msr_index
& 7));
6521 return 1; /* let L1 handle the wrong parameter */
6525 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6526 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6527 * intercept (via guest_host_mask etc.) the current event.
6529 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6530 struct vmcs12
*vmcs12
)
6532 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6533 int cr
= exit_qualification
& 15;
6534 int reg
= (exit_qualification
>> 8) & 15;
6535 unsigned long val
= kvm_register_read(vcpu
, reg
);
6537 switch ((exit_qualification
>> 4) & 3) {
6538 case 0: /* mov to cr */
6541 if (vmcs12
->cr0_guest_host_mask
&
6542 (val
^ vmcs12
->cr0_read_shadow
))
6546 if ((vmcs12
->cr3_target_count
>= 1 &&
6547 vmcs12
->cr3_target_value0
== val
) ||
6548 (vmcs12
->cr3_target_count
>= 2 &&
6549 vmcs12
->cr3_target_value1
== val
) ||
6550 (vmcs12
->cr3_target_count
>= 3 &&
6551 vmcs12
->cr3_target_value2
== val
) ||
6552 (vmcs12
->cr3_target_count
>= 4 &&
6553 vmcs12
->cr3_target_value3
== val
))
6555 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6559 if (vmcs12
->cr4_guest_host_mask
&
6560 (vmcs12
->cr4_read_shadow
^ val
))
6564 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6570 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6571 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6574 case 1: /* mov from cr */
6577 if (vmcs12
->cpu_based_vm_exec_control
&
6578 CPU_BASED_CR3_STORE_EXITING
)
6582 if (vmcs12
->cpu_based_vm_exec_control
&
6583 CPU_BASED_CR8_STORE_EXITING
)
6590 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6591 * cr0. Other attempted changes are ignored, with no exit.
6593 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6594 (val
^ vmcs12
->cr0_read_shadow
))
6596 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6597 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6606 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6607 * should handle it ourselves in L0 (and then continue L2). Only call this
6608 * when in is_guest_mode (L2).
6610 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6612 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6613 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6614 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6615 u32 exit_reason
= vmx
->exit_reason
;
6617 if (vmx
->nested
.nested_run_pending
)
6620 if (unlikely(vmx
->fail
)) {
6621 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6622 vmcs_read32(VM_INSTRUCTION_ERROR
));
6626 switch (exit_reason
) {
6627 case EXIT_REASON_EXCEPTION_NMI
:
6628 if (!is_exception(intr_info
))
6630 else if (is_page_fault(intr_info
))
6632 return vmcs12
->exception_bitmap
&
6633 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6634 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6636 case EXIT_REASON_TRIPLE_FAULT
:
6638 case EXIT_REASON_PENDING_INTERRUPT
:
6639 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6640 case EXIT_REASON_NMI_WINDOW
:
6641 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6642 case EXIT_REASON_TASK_SWITCH
:
6644 case EXIT_REASON_CPUID
:
6646 case EXIT_REASON_HLT
:
6647 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6648 case EXIT_REASON_INVD
:
6650 case EXIT_REASON_INVLPG
:
6651 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6652 case EXIT_REASON_RDPMC
:
6653 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6654 case EXIT_REASON_RDTSC
:
6655 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6656 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6657 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6658 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6659 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6660 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6661 case EXIT_REASON_INVEPT
:
6663 * VMX instructions trap unconditionally. This allows L1 to
6664 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6667 case EXIT_REASON_CR_ACCESS
:
6668 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6669 case EXIT_REASON_DR_ACCESS
:
6670 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6671 case EXIT_REASON_IO_INSTRUCTION
:
6672 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6673 case EXIT_REASON_MSR_READ
:
6674 case EXIT_REASON_MSR_WRITE
:
6675 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6676 case EXIT_REASON_INVALID_STATE
:
6678 case EXIT_REASON_MWAIT_INSTRUCTION
:
6679 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6680 case EXIT_REASON_MONITOR_INSTRUCTION
:
6681 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6682 case EXIT_REASON_PAUSE_INSTRUCTION
:
6683 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6684 nested_cpu_has2(vmcs12
,
6685 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6686 case EXIT_REASON_MCE_DURING_VMENTRY
:
6688 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6690 case EXIT_REASON_APIC_ACCESS
:
6691 return nested_cpu_has2(vmcs12
,
6692 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6693 case EXIT_REASON_EPT_VIOLATION
:
6695 * L0 always deals with the EPT violation. If nested EPT is
6696 * used, and the nested mmu code discovers that the address is
6697 * missing in the guest EPT table (EPT12), the EPT violation
6698 * will be injected with nested_ept_inject_page_fault()
6701 case EXIT_REASON_EPT_MISCONFIG
:
6703 * L2 never uses directly L1's EPT, but rather L0's own EPT
6704 * table (shadow on EPT) or a merged EPT table that L0 built
6705 * (EPT on EPT). So any problems with the structure of the
6706 * table is L0's fault.
6709 case EXIT_REASON_PREEMPTION_TIMER
:
6710 return vmcs12
->pin_based_vm_exec_control
&
6711 PIN_BASED_VMX_PREEMPTION_TIMER
;
6712 case EXIT_REASON_WBINVD
:
6713 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6714 case EXIT_REASON_XSETBV
:
6721 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6723 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6724 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6728 * The guest has exited. See if we can fix it or if we need userspace
6731 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6733 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6734 u32 exit_reason
= vmx
->exit_reason
;
6735 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6737 /* If guest state is invalid, start emulating */
6738 if (vmx
->emulation_required
)
6739 return handle_invalid_guest_state(vcpu
);
6741 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6742 nested_vmx_vmexit(vcpu
);
6746 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6747 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6748 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6753 if (unlikely(vmx
->fail
)) {
6754 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6755 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6756 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6762 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6763 * delivery event since it indicates guest is accessing MMIO.
6764 * The vm-exit can be triggered again after return to guest that
6765 * will cause infinite loop.
6767 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6768 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6769 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6770 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6771 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6772 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6773 vcpu
->run
->internal
.ndata
= 2;
6774 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6775 vcpu
->run
->internal
.data
[1] = exit_reason
;
6779 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6780 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6781 get_vmcs12(vcpu
))))) {
6782 if (vmx_interrupt_allowed(vcpu
)) {
6783 vmx
->soft_vnmi_blocked
= 0;
6784 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6785 vcpu
->arch
.nmi_pending
) {
6787 * This CPU don't support us in finding the end of an
6788 * NMI-blocked window if the guest runs with IRQs
6789 * disabled. So we pull the trigger after 1 s of
6790 * futile waiting, but inform the user about this.
6792 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6793 "state on VCPU %d after 1 s timeout\n",
6794 __func__
, vcpu
->vcpu_id
);
6795 vmx
->soft_vnmi_blocked
= 0;
6799 if (exit_reason
< kvm_vmx_max_exit_handlers
6800 && kvm_vmx_exit_handlers
[exit_reason
])
6801 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6803 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6804 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6809 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6811 if (irr
== -1 || tpr
< irr
) {
6812 vmcs_write32(TPR_THRESHOLD
, 0);
6816 vmcs_write32(TPR_THRESHOLD
, irr
);
6819 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6821 u32 sec_exec_control
;
6824 * There is not point to enable virtualize x2apic without enable
6827 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6828 !vmx_vm_has_apicv(vcpu
->kvm
))
6831 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6834 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6837 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6838 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6840 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6841 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6843 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6845 vmx_set_msr_bitmap(vcpu
);
6848 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6853 if (!vmx_vm_has_apicv(kvm
))
6859 status
= vmcs_read16(GUEST_INTR_STATUS
);
6864 vmcs_write16(GUEST_INTR_STATUS
, status
);
6868 static void vmx_set_rvi(int vector
)
6873 status
= vmcs_read16(GUEST_INTR_STATUS
);
6874 old
= (u8
)status
& 0xff;
6875 if ((u8
)vector
!= old
) {
6877 status
|= (u8
)vector
;
6878 vmcs_write16(GUEST_INTR_STATUS
, status
);
6882 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6887 vmx_set_rvi(max_irr
);
6890 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6892 if (!vmx_vm_has_apicv(vcpu
->kvm
))
6895 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
6896 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
6897 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
6898 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
6901 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6905 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6906 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6909 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6910 exit_intr_info
= vmx
->exit_intr_info
;
6912 /* Handle machine checks before interrupts are enabled */
6913 if (is_machine_check(exit_intr_info
))
6914 kvm_machine_check();
6916 /* We need to handle NMIs before interrupts are enabled */
6917 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6918 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6919 kvm_before_handle_nmi(&vmx
->vcpu
);
6921 kvm_after_handle_nmi(&vmx
->vcpu
);
6925 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
6927 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6930 * If external interrupt exists, IF bit is set in rflags/eflags on the
6931 * interrupt stack frame, and interrupt will be enabled on a return
6932 * from interrupt handler.
6934 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
6935 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
6936 unsigned int vector
;
6937 unsigned long entry
;
6939 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6940 #ifdef CONFIG_X86_64
6944 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6945 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
6946 entry
= gate_offset(*desc
);
6948 #ifdef CONFIG_X86_64
6949 "mov %%" _ASM_SP
", %[sp]\n\t"
6950 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
6955 "orl $0x200, (%%" _ASM_SP
")\n\t"
6956 __ASM_SIZE(push
) " $%c[cs]\n\t"
6957 "call *%[entry]\n\t"
6959 #ifdef CONFIG_X86_64
6964 [ss
]"i"(__KERNEL_DS
),
6965 [cs
]"i"(__KERNEL_CS
)
6971 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6976 bool idtv_info_valid
;
6978 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6980 if (cpu_has_virtual_nmis()) {
6981 if (vmx
->nmi_known_unmasked
)
6984 * Can't use vmx->exit_intr_info since we're not sure what
6985 * the exit reason is.
6987 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6988 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6989 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6991 * SDM 3: 27.7.1.2 (September 2008)
6992 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6993 * a guest IRET fault.
6994 * SDM 3: 23.2.2 (September 2008)
6995 * Bit 12 is undefined in any of the following cases:
6996 * If the VM exit sets the valid bit in the IDT-vectoring
6997 * information field.
6998 * If the VM exit is due to a double fault.
7000 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7001 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7002 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7003 GUEST_INTR_STATE_NMI
);
7005 vmx
->nmi_known_unmasked
=
7006 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7007 & GUEST_INTR_STATE_NMI
);
7008 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7009 vmx
->vnmi_blocked_time
+=
7010 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7013 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7014 u32 idt_vectoring_info
,
7015 int instr_len_field
,
7016 int error_code_field
)
7020 bool idtv_info_valid
;
7022 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7024 vcpu
->arch
.nmi_injected
= false;
7025 kvm_clear_exception_queue(vcpu
);
7026 kvm_clear_interrupt_queue(vcpu
);
7028 if (!idtv_info_valid
)
7031 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7033 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7034 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7037 case INTR_TYPE_NMI_INTR
:
7038 vcpu
->arch
.nmi_injected
= true;
7040 * SDM 3: 27.7.1.2 (September 2008)
7041 * Clear bit "block by NMI" before VM entry if a NMI
7044 vmx_set_nmi_mask(vcpu
, false);
7046 case INTR_TYPE_SOFT_EXCEPTION
:
7047 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7049 case INTR_TYPE_HARD_EXCEPTION
:
7050 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7051 u32 err
= vmcs_read32(error_code_field
);
7052 kvm_requeue_exception_e(vcpu
, vector
, err
);
7054 kvm_requeue_exception(vcpu
, vector
);
7056 case INTR_TYPE_SOFT_INTR
:
7057 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7059 case INTR_TYPE_EXT_INTR
:
7060 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7067 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7069 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7070 VM_EXIT_INSTRUCTION_LEN
,
7071 IDT_VECTORING_ERROR_CODE
);
7074 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7076 __vmx_complete_interrupts(vcpu
,
7077 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7078 VM_ENTRY_INSTRUCTION_LEN
,
7079 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7081 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7084 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7087 struct perf_guest_switch_msr
*msrs
;
7089 msrs
= perf_guest_get_msrs(&nr_msrs
);
7094 for (i
= 0; i
< nr_msrs
; i
++)
7095 if (msrs
[i
].host
== msrs
[i
].guest
)
7096 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7098 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7102 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7104 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7105 unsigned long debugctlmsr
;
7107 /* Record the guest's net vcpu time for enforced NMI injections. */
7108 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7109 vmx
->entry_time
= ktime_get();
7111 /* Don't enter VMX if guest state is invalid, let the exit handler
7112 start emulation until we arrive back to a valid state */
7113 if (vmx
->emulation_required
)
7116 if (vmx
->nested
.sync_shadow_vmcs
) {
7117 copy_vmcs12_to_shadow(vmx
);
7118 vmx
->nested
.sync_shadow_vmcs
= false;
7121 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7122 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7123 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7124 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7126 /* When single-stepping over STI and MOV SS, we must clear the
7127 * corresponding interruptibility bits in the guest state. Otherwise
7128 * vmentry fails as it then expects bit 14 (BS) in pending debug
7129 * exceptions being set, but that's not correct for the guest debugging
7131 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7132 vmx_set_interrupt_shadow(vcpu
, 0);
7134 atomic_switch_perf_msrs(vmx
);
7135 debugctlmsr
= get_debugctlmsr();
7137 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7139 /* Store host registers */
7140 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7141 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7142 "push %%" _ASM_CX
" \n\t"
7143 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7145 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7146 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7148 /* Reload cr2 if changed */
7149 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7150 "mov %%cr2, %%" _ASM_DX
" \n\t"
7151 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7153 "mov %%" _ASM_AX
", %%cr2 \n\t"
7155 /* Check if vmlaunch of vmresume is needed */
7156 "cmpl $0, %c[launched](%0) \n\t"
7157 /* Load guest registers. Don't clobber flags. */
7158 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7159 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7160 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7161 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7162 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7163 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7164 #ifdef CONFIG_X86_64
7165 "mov %c[r8](%0), %%r8 \n\t"
7166 "mov %c[r9](%0), %%r9 \n\t"
7167 "mov %c[r10](%0), %%r10 \n\t"
7168 "mov %c[r11](%0), %%r11 \n\t"
7169 "mov %c[r12](%0), %%r12 \n\t"
7170 "mov %c[r13](%0), %%r13 \n\t"
7171 "mov %c[r14](%0), %%r14 \n\t"
7172 "mov %c[r15](%0), %%r15 \n\t"
7174 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7176 /* Enter guest mode */
7178 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7180 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7182 /* Save guest registers, load host registers, keep flags */
7183 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7185 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7186 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7187 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7188 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7189 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7190 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7191 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7192 #ifdef CONFIG_X86_64
7193 "mov %%r8, %c[r8](%0) \n\t"
7194 "mov %%r9, %c[r9](%0) \n\t"
7195 "mov %%r10, %c[r10](%0) \n\t"
7196 "mov %%r11, %c[r11](%0) \n\t"
7197 "mov %%r12, %c[r12](%0) \n\t"
7198 "mov %%r13, %c[r13](%0) \n\t"
7199 "mov %%r14, %c[r14](%0) \n\t"
7200 "mov %%r15, %c[r15](%0) \n\t"
7202 "mov %%cr2, %%" _ASM_AX
" \n\t"
7203 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7205 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7206 "setbe %c[fail](%0) \n\t"
7207 ".pushsection .rodata \n\t"
7208 ".global vmx_return \n\t"
7209 "vmx_return: " _ASM_PTR
" 2b \n\t"
7211 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7212 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7213 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7214 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7215 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7216 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7217 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7218 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7219 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7220 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7221 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7222 #ifdef CONFIG_X86_64
7223 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7224 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7225 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7226 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7227 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7228 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7229 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7230 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7232 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7233 [wordsize
]"i"(sizeof(ulong
))
7235 #ifdef CONFIG_X86_64
7236 , "rax", "rbx", "rdi", "rsi"
7237 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7239 , "eax", "ebx", "edi", "esi"
7243 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7245 update_debugctlmsr(debugctlmsr
);
7247 #ifndef CONFIG_X86_64
7249 * The sysexit path does not restore ds/es, so we must set them to
7250 * a reasonable value ourselves.
7252 * We can't defer this to vmx_load_host_state() since that function
7253 * may be executed in interrupt context, which saves and restore segments
7254 * around it, nullifying its effect.
7256 loadsegment(ds
, __USER_DS
);
7257 loadsegment(es
, __USER_DS
);
7260 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7261 | (1 << VCPU_EXREG_RFLAGS
)
7262 | (1 << VCPU_EXREG_CPL
)
7263 | (1 << VCPU_EXREG_PDPTR
)
7264 | (1 << VCPU_EXREG_SEGMENTS
)
7265 | (1 << VCPU_EXREG_CR3
));
7266 vcpu
->arch
.regs_dirty
= 0;
7268 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7270 vmx
->loaded_vmcs
->launched
= 1;
7272 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7273 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7276 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7277 * we did not inject a still-pending event to L1 now because of
7278 * nested_run_pending, we need to re-enable this bit.
7280 if (vmx
->nested
.nested_run_pending
)
7281 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7283 vmx
->nested
.nested_run_pending
= 0;
7285 vmx_complete_atomic_exit(vmx
);
7286 vmx_recover_nmi_blocking(vmx
);
7287 vmx_complete_interrupts(vmx
);
7290 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7292 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7296 free_loaded_vmcs(vmx
->loaded_vmcs
);
7297 kfree(vmx
->guest_msrs
);
7298 kvm_vcpu_uninit(vcpu
);
7299 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7302 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7305 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7309 return ERR_PTR(-ENOMEM
);
7313 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7317 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7319 if (!vmx
->guest_msrs
) {
7323 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7324 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7325 if (!vmx
->loaded_vmcs
->vmcs
)
7328 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7329 loaded_vmcs_init(vmx
->loaded_vmcs
);
7334 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7335 vmx
->vcpu
.cpu
= cpu
;
7336 err
= vmx_vcpu_setup(vmx
);
7337 vmx_vcpu_put(&vmx
->vcpu
);
7341 if (vm_need_virtualize_apic_accesses(kvm
)) {
7342 err
= alloc_apic_access_page(kvm
);
7348 if (!kvm
->arch
.ept_identity_map_addr
)
7349 kvm
->arch
.ept_identity_map_addr
=
7350 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7352 if (alloc_identity_pagetable(kvm
) != 0)
7354 if (!init_rmode_identity_map(kvm
))
7358 vmx
->nested
.current_vmptr
= -1ull;
7359 vmx
->nested
.current_vmcs12
= NULL
;
7364 free_loaded_vmcs(vmx
->loaded_vmcs
);
7366 kfree(vmx
->guest_msrs
);
7368 kvm_vcpu_uninit(&vmx
->vcpu
);
7371 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7372 return ERR_PTR(err
);
7375 static void __init
vmx_check_processor_compat(void *rtn
)
7377 struct vmcs_config vmcs_conf
;
7380 if (setup_vmcs_config(&vmcs_conf
) < 0)
7382 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7383 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7384 smp_processor_id());
7389 static int get_ept_level(void)
7391 return VMX_EPT_DEFAULT_GAW
+ 1;
7394 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7398 /* For VT-d and EPT combination
7399 * 1. MMIO: always map as UC
7401 * a. VT-d without snooping control feature: can't guarantee the
7402 * result, try to trust guest.
7403 * b. VT-d with snooping control feature: snooping control feature of
7404 * VT-d engine can guarantee the cache correctness. Just set it
7405 * to WB to keep consistent with host. So the same as item 3.
7406 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7407 * consistent with host MTRR
7410 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7411 else if (vcpu
->kvm
->arch
.iommu_domain
&&
7412 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
7413 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7414 VMX_EPT_MT_EPTE_SHIFT
;
7416 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7422 static int vmx_get_lpage_level(void)
7424 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7425 return PT_DIRECTORY_LEVEL
;
7427 /* For shadow and EPT supported 1GB page */
7428 return PT_PDPE_LEVEL
;
7431 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7433 struct kvm_cpuid_entry2
*best
;
7434 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7437 vmx
->rdtscp_enabled
= false;
7438 if (vmx_rdtscp_supported()) {
7439 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7440 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7441 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7442 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7443 vmx
->rdtscp_enabled
= true;
7445 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7446 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7452 /* Exposing INVPCID only when PCID is exposed */
7453 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7454 if (vmx_invpcid_supported() &&
7455 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7456 guest_cpuid_has_pcid(vcpu
)) {
7457 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7458 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7459 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7462 if (cpu_has_secondary_exec_ctrls()) {
7463 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7464 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7465 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7469 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7473 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7475 if (func
== 1 && nested
)
7476 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7479 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7480 struct x86_exception
*fault
)
7482 struct vmcs12
*vmcs12
;
7483 nested_vmx_vmexit(vcpu
);
7484 vmcs12
= get_vmcs12(vcpu
);
7486 if (fault
->error_code
& PFERR_RSVD_MASK
)
7487 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7489 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7490 vmcs12
->exit_qualification
= vcpu
->arch
.exit_qualification
;
7491 vmcs12
->guest_physical_address
= fault
->address
;
7494 /* Callbacks for nested_ept_init_mmu_context: */
7496 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7498 /* return the page table to be shadowed - in our case, EPT12 */
7499 return get_vmcs12(vcpu
)->ept_pointer
;
7502 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7504 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7505 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7507 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7508 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7509 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7511 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7514 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7516 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7519 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7520 struct x86_exception
*fault
)
7522 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7524 WARN_ON(!is_guest_mode(vcpu
));
7526 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7527 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7528 nested_vmx_vmexit(vcpu
);
7530 kvm_inject_page_fault(vcpu
, fault
);
7534 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7535 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7536 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7537 * guest in a way that will both be appropriate to L1's requests, and our
7538 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7539 * function also has additional necessary side-effects, like setting various
7540 * vcpu->arch fields.
7542 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7544 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7547 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7548 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7549 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7550 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7551 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7552 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7553 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7554 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7555 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7556 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7557 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7558 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7559 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7560 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7561 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7562 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7563 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7564 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7565 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7566 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7567 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7568 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7569 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7570 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7571 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7572 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7573 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7574 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7575 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7576 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7577 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7578 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7579 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7580 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7581 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7582 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7584 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7586 vmcs12
->vm_entry_intr_info_field
);
7587 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7588 vmcs12
->vm_entry_exception_error_code
);
7589 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7590 vmcs12
->vm_entry_instruction_len
);
7591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7592 vmcs12
->guest_interruptibility_info
);
7593 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7594 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7595 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7596 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7597 vmcs12
->guest_pending_dbg_exceptions
);
7598 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7599 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7601 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7603 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7604 (vmcs_config
.pin_based_exec_ctrl
|
7605 vmcs12
->pin_based_vm_exec_control
));
7607 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7608 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7609 vmcs12
->vmx_preemption_timer_value
);
7612 * Whether page-faults are trapped is determined by a combination of
7613 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7614 * If enable_ept, L0 doesn't care about page faults and we should
7615 * set all of these to L1's desires. However, if !enable_ept, L0 does
7616 * care about (at least some) page faults, and because it is not easy
7617 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7618 * to exit on each and every L2 page fault. This is done by setting
7619 * MASK=MATCH=0 and (see below) EB.PF=1.
7620 * Note that below we don't need special code to set EB.PF beyond the
7621 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7622 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7623 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7625 * A problem with this approach (when !enable_ept) is that L1 may be
7626 * injected with more page faults than it asked for. This could have
7627 * caused problems, but in practice existing hypervisors don't care.
7628 * To fix this, we will need to emulate the PFEC checking (on the L1
7629 * page tables), using walk_addr(), when injecting PFs to L1.
7631 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7632 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7633 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7634 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7636 if (cpu_has_secondary_exec_ctrls()) {
7637 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7638 if (!vmx
->rdtscp_enabled
)
7639 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7640 /* Take the following fields only from vmcs12 */
7641 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7642 if (nested_cpu_has(vmcs12
,
7643 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7644 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7646 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7648 * Translate L1 physical address to host physical
7649 * address for vmcs02. Keep the page pinned, so this
7650 * physical address remains valid. We keep a reference
7651 * to it so we can release it later.
7653 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7654 nested_release_page(vmx
->nested
.apic_access_page
);
7655 vmx
->nested
.apic_access_page
=
7656 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7658 * If translation failed, no matter: This feature asks
7659 * to exit when accessing the given address, and if it
7660 * can never be accessed, this feature won't do
7663 if (!vmx
->nested
.apic_access_page
)
7665 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7667 vmcs_write64(APIC_ACCESS_ADDR
,
7668 page_to_phys(vmx
->nested
.apic_access_page
));
7671 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7676 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7677 * Some constant fields are set here by vmx_set_constant_host_state().
7678 * Other fields are different per CPU, and will be set later when
7679 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7681 vmx_set_constant_host_state(vmx
);
7684 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7685 * entry, but only if the current (host) sp changed from the value
7686 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7687 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7688 * here we just force the write to happen on entry.
7692 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7693 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7694 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7695 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7696 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7698 * Merging of IO and MSR bitmaps not currently supported.
7699 * Rather, exit every time.
7701 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7702 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7703 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7705 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7707 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7708 * bitwise-or of what L1 wants to trap for L2, and what we want to
7709 * trap. Note that CR0.TS also needs updating - we do this later.
7711 update_exception_bitmap(vcpu
);
7712 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7713 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7715 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7716 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7717 * bits are further modified by vmx_set_efer() below.
7719 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
7721 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7722 * emulated by vmx_set_efer(), below.
7724 vmcs_write32(VM_ENTRY_CONTROLS
,
7725 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7726 ~VM_ENTRY_IA32E_MODE
) |
7727 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7729 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7730 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7731 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7732 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7733 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7736 set_cr4_guest_host_mask(vmx
);
7738 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7739 vmcs_write64(TSC_OFFSET
,
7740 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7742 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7746 * Trivially support vpid by letting L2s share their parent
7747 * L1's vpid. TODO: move to a more elaborate solution, giving
7748 * each L2 its own vpid and exposing the vpid feature to L1.
7750 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7751 vmx_flush_tlb(vcpu
);
7754 if (nested_cpu_has_ept(vmcs12
)) {
7755 kvm_mmu_unload(vcpu
);
7756 nested_ept_init_mmu_context(vcpu
);
7759 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7760 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7761 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7762 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7764 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7765 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7766 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7769 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7770 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7771 * The CR0_READ_SHADOW is what L2 should have expected to read given
7772 * the specifications by L1; It's not enough to take
7773 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7774 * have more bits than L1 expected.
7776 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7777 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7779 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7780 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7782 /* shadow page tables on either EPT or shadow page tables */
7783 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7784 kvm_mmu_reset_context(vcpu
);
7787 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7790 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7793 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7794 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7795 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7796 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7797 __clear_bit(VCPU_EXREG_PDPTR
,
7798 (unsigned long *)&vcpu
->arch
.regs_avail
);
7799 __clear_bit(VCPU_EXREG_PDPTR
,
7800 (unsigned long *)&vcpu
->arch
.regs_dirty
);
7803 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7804 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7808 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7809 * for running an L2 nested guest.
7811 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7813 struct vmcs12
*vmcs12
;
7814 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7816 struct loaded_vmcs
*vmcs02
;
7819 if (!nested_vmx_check_permission(vcpu
) ||
7820 !nested_vmx_check_vmcs12(vcpu
))
7823 skip_emulated_instruction(vcpu
);
7824 vmcs12
= get_vmcs12(vcpu
);
7826 if (enable_shadow_vmcs
)
7827 copy_shadow_to_vmcs12(vmx
);
7830 * The nested entry process starts with enforcing various prerequisites
7831 * on vmcs12 as required by the Intel SDM, and act appropriately when
7832 * they fail: As the SDM explains, some conditions should cause the
7833 * instruction to fail, while others will cause the instruction to seem
7834 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7835 * To speed up the normal (success) code path, we should avoid checking
7836 * for misconfigurations which will anyway be caught by the processor
7837 * when using the merged vmcs02.
7839 if (vmcs12
->launch_state
== launch
) {
7840 nested_vmx_failValid(vcpu
,
7841 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7842 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7846 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
) {
7847 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7851 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7852 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7853 /*TODO: Also verify bits beyond physical address width are 0*/
7854 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7858 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7859 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7860 /*TODO: Also verify bits beyond physical address width are 0*/
7861 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7865 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7866 vmcs12
->vm_exit_msr_load_count
> 0 ||
7867 vmcs12
->vm_exit_msr_store_count
> 0) {
7868 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7870 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7874 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7875 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7876 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7877 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7878 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7879 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7880 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7881 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7882 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7883 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7885 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7889 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
7890 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7891 nested_vmx_failValid(vcpu
,
7892 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
7896 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
7897 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
7898 nested_vmx_entry_failure(vcpu
, vmcs12
,
7899 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7902 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
7903 nested_vmx_entry_failure(vcpu
, vmcs12
,
7904 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
7909 * If the load IA32_EFER VM-entry control is 1, the following checks
7910 * are performed on the field for the IA32_EFER MSR:
7911 * - Bits reserved in the IA32_EFER MSR must be 0.
7912 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
7913 * the IA-32e mode guest VM-exit control. It must also be identical
7914 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
7917 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
7918 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
7919 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
7920 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
7921 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
7922 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
7923 nested_vmx_entry_failure(vcpu
, vmcs12
,
7924 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7930 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
7931 * IA32_EFER MSR must be 0 in the field for that register. In addition,
7932 * the values of the LMA and LME bits in the field must each be that of
7933 * the host address-space size VM-exit control.
7935 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
7936 ia32e
= (vmcs12
->vm_exit_controls
&
7937 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
7938 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
7939 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
7940 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
7941 nested_vmx_entry_failure(vcpu
, vmcs12
,
7942 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
7948 * We're finally done with prerequisite checking, and can start with
7952 vmcs02
= nested_get_current_vmcs02(vmx
);
7956 enter_guest_mode(vcpu
);
7958 vmx
->nested
.nested_run_pending
= 1;
7960 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
7963 vmx
->loaded_vmcs
= vmcs02
;
7965 vmx_vcpu_load(vcpu
, cpu
);
7969 vmx_segment_cache_clear(vmx
);
7971 vmcs12
->launch_state
= 1;
7973 prepare_vmcs02(vcpu
, vmcs12
);
7976 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
7977 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
7978 * returned as far as L1 is concerned. It will only return (and set
7979 * the success flag) when L2 exits (see nested_vmx_vmexit()).
7985 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
7986 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
7987 * This function returns the new value we should put in vmcs12.guest_cr0.
7988 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
7989 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
7990 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
7991 * didn't trap the bit, because if L1 did, so would L0).
7992 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
7993 * been modified by L2, and L1 knows it. So just leave the old value of
7994 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
7995 * isn't relevant, because if L0 traps this bit it can set it to anything.
7996 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
7997 * changed these bits, and therefore they need to be updated, but L0
7998 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
7999 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8001 static inline unsigned long
8002 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8005 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8006 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8007 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8008 vcpu
->arch
.cr0_guest_owned_bits
));
8011 static inline unsigned long
8012 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8015 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8016 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8017 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8018 vcpu
->arch
.cr4_guest_owned_bits
));
8021 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8022 struct vmcs12
*vmcs12
)
8027 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8028 nr
= vcpu
->arch
.exception
.nr
;
8029 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8031 if (kvm_exception_is_soft(nr
)) {
8032 vmcs12
->vm_exit_instruction_len
=
8033 vcpu
->arch
.event_exit_inst_len
;
8034 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8036 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8038 if (vcpu
->arch
.exception
.has_error_code
) {
8039 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8040 vmcs12
->idt_vectoring_error_code
=
8041 vcpu
->arch
.exception
.error_code
;
8044 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8045 } else if (vcpu
->arch
.nmi_pending
) {
8046 vmcs12
->idt_vectoring_info_field
=
8047 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8048 } else if (vcpu
->arch
.interrupt
.pending
) {
8049 nr
= vcpu
->arch
.interrupt
.nr
;
8050 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8052 if (vcpu
->arch
.interrupt
.soft
) {
8053 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8054 vmcs12
->vm_entry_instruction_len
=
8055 vcpu
->arch
.event_exit_inst_len
;
8057 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8059 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8064 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8065 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8066 * and this function updates it to reflect the changes to the guest state while
8067 * L2 was running (and perhaps made some exits which were handled directly by L0
8068 * without going back to L1), and to reflect the exit reason.
8069 * Note that we do not have to copy here all VMCS fields, just those that
8070 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8071 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8072 * which already writes to vmcs12 directly.
8074 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8076 /* update guest state fields: */
8077 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8078 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8080 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8081 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8082 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8083 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8085 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8086 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8087 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8088 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8089 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8090 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8091 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8092 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8093 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8094 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8095 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8096 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8097 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8098 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8099 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8100 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8101 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8102 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8103 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8104 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8105 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8106 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8107 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8108 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8109 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8110 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8111 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8112 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8113 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8114 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8115 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8116 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8117 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8118 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8119 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8120 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8122 vmcs12
->guest_interruptibility_info
=
8123 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8124 vmcs12
->guest_pending_dbg_exceptions
=
8125 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8128 * In some cases (usually, nested EPT), L2 is allowed to change its
8129 * own CR3 without exiting. If it has changed it, we must keep it.
8130 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8131 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8133 * Additionally, restore L2's PDPTR to vmcs12.
8136 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8137 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8138 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8139 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8140 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8143 vmcs12
->vm_entry_controls
=
8144 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8145 (vmcs_read32(VM_ENTRY_CONTROLS
) & VM_ENTRY_IA32E_MODE
);
8147 /* TODO: These cannot have changed unless we have MSR bitmaps and
8148 * the relevant bit asks not to trap the change */
8149 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8150 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8151 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8152 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8153 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8154 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8155 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8156 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8158 /* update exit information fields: */
8160 vmcs12
->vm_exit_reason
= to_vmx(vcpu
)->exit_reason
;
8161 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8163 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8164 if ((vmcs12
->vm_exit_intr_info
&
8165 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8166 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8167 vmcs12
->vm_exit_intr_error_code
=
8168 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8169 vmcs12
->idt_vectoring_info_field
= 0;
8170 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8171 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8173 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8174 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8175 * instead of reading the real value. */
8176 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8179 * Transfer the event that L0 or L1 may wanted to inject into
8180 * L2 to IDT_VECTORING_INFO_FIELD.
8182 vmcs12_save_pending_event(vcpu
, vmcs12
);
8186 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8187 * preserved above and would only end up incorrectly in L1.
8189 vcpu
->arch
.nmi_injected
= false;
8190 kvm_clear_exception_queue(vcpu
);
8191 kvm_clear_interrupt_queue(vcpu
);
8195 * A part of what we need to when the nested L2 guest exits and we want to
8196 * run its L1 parent, is to reset L1's guest state to the host state specified
8198 * This function is to be called not only on normal nested exit, but also on
8199 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8200 * Failures During or After Loading Guest State").
8201 * This function should be called when the active VMCS is L1's (vmcs01).
8203 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8204 struct vmcs12
*vmcs12
)
8206 struct kvm_segment seg
;
8208 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8209 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8210 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8211 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8213 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8214 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8216 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8217 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8218 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8220 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8221 * actually changed, because it depends on the current state of
8222 * fpu_active (which may have changed).
8223 * Note that vmx_set_cr0 refers to efer set above.
8225 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8227 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8228 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8229 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8231 update_exception_bitmap(vcpu
);
8232 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8233 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8236 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8237 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8239 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8240 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8242 if (nested_cpu_has_ept(vmcs12
))
8243 nested_ept_uninit_mmu_context(vcpu
);
8245 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8246 kvm_mmu_reset_context(vcpu
);
8249 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8253 * Trivially support vpid by letting L2s share their parent
8254 * L1's vpid. TODO: move to a more elaborate solution, giving
8255 * each L2 its own vpid and exposing the vpid feature to L1.
8257 vmx_flush_tlb(vcpu
);
8261 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8262 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8263 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8264 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8265 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8267 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8268 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8269 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8271 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8272 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8273 vmcs12
->host_ia32_perf_global_ctrl
);
8275 /* Set L1 segment info according to Intel SDM
8276 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8277 seg
= (struct kvm_segment
) {
8279 .limit
= 0xFFFFFFFF,
8280 .selector
= vmcs12
->host_cs_selector
,
8286 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8290 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8291 seg
= (struct kvm_segment
) {
8293 .limit
= 0xFFFFFFFF,
8300 seg
.selector
= vmcs12
->host_ds_selector
;
8301 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8302 seg
.selector
= vmcs12
->host_es_selector
;
8303 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8304 seg
.selector
= vmcs12
->host_ss_selector
;
8305 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8306 seg
.selector
= vmcs12
->host_fs_selector
;
8307 seg
.base
= vmcs12
->host_fs_base
;
8308 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8309 seg
.selector
= vmcs12
->host_gs_selector
;
8310 seg
.base
= vmcs12
->host_gs_base
;
8311 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8312 seg
= (struct kvm_segment
) {
8313 .base
= vmcs12
->host_tr_base
,
8315 .selector
= vmcs12
->host_tr_selector
,
8319 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8321 kvm_set_dr(vcpu
, 7, 0x400);
8322 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8326 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8327 * and modify vmcs12 to make it see what it would expect to see there if
8328 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8330 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
8332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8334 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8336 /* trying to cancel vmlaunch/vmresume is a bug */
8337 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8339 leave_guest_mode(vcpu
);
8340 prepare_vmcs12(vcpu
, vmcs12
);
8343 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8345 vmx_vcpu_load(vcpu
, cpu
);
8349 vmx_segment_cache_clear(vmx
);
8351 /* if no vmcs02 cache requested, remove the one we used */
8352 if (VMCS02_POOL_SIZE
== 0)
8353 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8355 load_vmcs12_host_state(vcpu
, vmcs12
);
8357 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8358 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8360 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8363 /* Unpin physical memory we referred to in vmcs02 */
8364 if (vmx
->nested
.apic_access_page
) {
8365 nested_release_page(vmx
->nested
.apic_access_page
);
8366 vmx
->nested
.apic_access_page
= 0;
8370 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8371 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8372 * success or failure flag accordingly.
8374 if (unlikely(vmx
->fail
)) {
8376 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8378 nested_vmx_succeed(vcpu
);
8379 if (enable_shadow_vmcs
)
8380 vmx
->nested
.sync_shadow_vmcs
= true;
8384 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8385 * 23.7 "VM-entry failures during or after loading guest state" (this also
8386 * lists the acceptable exit-reason and exit-qualification parameters).
8387 * It should only be called before L2 actually succeeded to run, and when
8388 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8390 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8391 struct vmcs12
*vmcs12
,
8392 u32 reason
, unsigned long qualification
)
8394 load_vmcs12_host_state(vcpu
, vmcs12
);
8395 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8396 vmcs12
->exit_qualification
= qualification
;
8397 nested_vmx_succeed(vcpu
);
8398 if (enable_shadow_vmcs
)
8399 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8402 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8403 struct x86_instruction_info
*info
,
8404 enum x86_intercept_stage stage
)
8406 return X86EMUL_CONTINUE
;
8409 static struct kvm_x86_ops vmx_x86_ops
= {
8410 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8411 .disabled_by_bios
= vmx_disabled_by_bios
,
8412 .hardware_setup
= hardware_setup
,
8413 .hardware_unsetup
= hardware_unsetup
,
8414 .check_processor_compatibility
= vmx_check_processor_compat
,
8415 .hardware_enable
= hardware_enable
,
8416 .hardware_disable
= hardware_disable
,
8417 .cpu_has_accelerated_tpr
= report_flexpriority
,
8419 .vcpu_create
= vmx_create_vcpu
,
8420 .vcpu_free
= vmx_free_vcpu
,
8421 .vcpu_reset
= vmx_vcpu_reset
,
8423 .prepare_guest_switch
= vmx_save_host_state
,
8424 .vcpu_load
= vmx_vcpu_load
,
8425 .vcpu_put
= vmx_vcpu_put
,
8427 .update_db_bp_intercept
= update_exception_bitmap
,
8428 .get_msr
= vmx_get_msr
,
8429 .set_msr
= vmx_set_msr
,
8430 .get_segment_base
= vmx_get_segment_base
,
8431 .get_segment
= vmx_get_segment
,
8432 .set_segment
= vmx_set_segment
,
8433 .get_cpl
= vmx_get_cpl
,
8434 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8435 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8436 .decache_cr3
= vmx_decache_cr3
,
8437 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8438 .set_cr0
= vmx_set_cr0
,
8439 .set_cr3
= vmx_set_cr3
,
8440 .set_cr4
= vmx_set_cr4
,
8441 .set_efer
= vmx_set_efer
,
8442 .get_idt
= vmx_get_idt
,
8443 .set_idt
= vmx_set_idt
,
8444 .get_gdt
= vmx_get_gdt
,
8445 .set_gdt
= vmx_set_gdt
,
8446 .set_dr7
= vmx_set_dr7
,
8447 .cache_reg
= vmx_cache_reg
,
8448 .get_rflags
= vmx_get_rflags
,
8449 .set_rflags
= vmx_set_rflags
,
8450 .fpu_activate
= vmx_fpu_activate
,
8451 .fpu_deactivate
= vmx_fpu_deactivate
,
8453 .tlb_flush
= vmx_flush_tlb
,
8455 .run
= vmx_vcpu_run
,
8456 .handle_exit
= vmx_handle_exit
,
8457 .skip_emulated_instruction
= skip_emulated_instruction
,
8458 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8459 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8460 .patch_hypercall
= vmx_patch_hypercall
,
8461 .set_irq
= vmx_inject_irq
,
8462 .set_nmi
= vmx_inject_nmi
,
8463 .queue_exception
= vmx_queue_exception
,
8464 .cancel_injection
= vmx_cancel_injection
,
8465 .interrupt_allowed
= vmx_interrupt_allowed
,
8466 .nmi_allowed
= vmx_nmi_allowed
,
8467 .get_nmi_mask
= vmx_get_nmi_mask
,
8468 .set_nmi_mask
= vmx_set_nmi_mask
,
8469 .enable_nmi_window
= enable_nmi_window
,
8470 .enable_irq_window
= enable_irq_window
,
8471 .update_cr8_intercept
= update_cr8_intercept
,
8472 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8473 .vm_has_apicv
= vmx_vm_has_apicv
,
8474 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8475 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8476 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8477 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8478 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8480 .set_tss_addr
= vmx_set_tss_addr
,
8481 .get_tdp_level
= get_ept_level
,
8482 .get_mt_mask
= vmx_get_mt_mask
,
8484 .get_exit_info
= vmx_get_exit_info
,
8486 .get_lpage_level
= vmx_get_lpage_level
,
8488 .cpuid_update
= vmx_cpuid_update
,
8490 .rdtscp_supported
= vmx_rdtscp_supported
,
8491 .invpcid_supported
= vmx_invpcid_supported
,
8493 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8495 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8497 .set_tsc_khz
= vmx_set_tsc_khz
,
8498 .read_tsc_offset
= vmx_read_tsc_offset
,
8499 .write_tsc_offset
= vmx_write_tsc_offset
,
8500 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8501 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8502 .read_l1_tsc
= vmx_read_l1_tsc
,
8504 .set_tdp_cr3
= vmx_set_cr3
,
8506 .check_intercept
= vmx_check_intercept
,
8507 .handle_external_intr
= vmx_handle_external_intr
,
8510 static int __init
vmx_init(void)
8514 rdmsrl_safe(MSR_EFER
, &host_efer
);
8516 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8517 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8519 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8520 if (!vmx_io_bitmap_a
)
8525 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8526 if (!vmx_io_bitmap_b
)
8529 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8530 if (!vmx_msr_bitmap_legacy
)
8533 vmx_msr_bitmap_legacy_x2apic
=
8534 (unsigned long *)__get_free_page(GFP_KERNEL
);
8535 if (!vmx_msr_bitmap_legacy_x2apic
)
8538 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8539 if (!vmx_msr_bitmap_longmode
)
8542 vmx_msr_bitmap_longmode_x2apic
=
8543 (unsigned long *)__get_free_page(GFP_KERNEL
);
8544 if (!vmx_msr_bitmap_longmode_x2apic
)
8546 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8547 if (!vmx_vmread_bitmap
)
8550 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8551 if (!vmx_vmwrite_bitmap
)
8554 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8555 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8556 /* shadowed read/write fields */
8557 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8558 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8559 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8561 /* shadowed read only fields */
8562 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8563 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8566 * Allow direct access to the PC debug port (it is often used for I/O
8567 * delays, but the vmexits simply slow things down).
8569 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8570 clear_bit(0x80, vmx_io_bitmap_a
);
8572 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8574 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8575 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8577 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8579 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8580 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8585 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8586 crash_vmclear_local_loaded_vmcss
);
8589 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8590 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8591 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8592 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8593 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8594 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8595 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8596 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8597 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8598 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8601 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8602 vmx_disable_intercept_msr_read_x2apic(msr
);
8604 /* According SDM, in x2apic mode, the whole id reg is used.
8605 * But in KVM, it only use the highest eight bits. Need to
8607 vmx_enable_intercept_msr_read_x2apic(0x802);
8609 vmx_enable_intercept_msr_read_x2apic(0x839);
8611 vmx_disable_intercept_msr_write_x2apic(0x808);
8613 vmx_disable_intercept_msr_write_x2apic(0x80b);
8615 vmx_disable_intercept_msr_write_x2apic(0x83f);
8619 kvm_mmu_set_mask_ptes(0ull,
8620 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8621 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8622 0ull, VMX_EPT_EXECUTABLE_MASK
);
8623 ept_set_mmio_spte_mask();
8631 free_page((unsigned long)vmx_vmwrite_bitmap
);
8633 free_page((unsigned long)vmx_vmread_bitmap
);
8635 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8637 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8639 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8641 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8643 free_page((unsigned long)vmx_io_bitmap_b
);
8645 free_page((unsigned long)vmx_io_bitmap_a
);
8649 static void __exit
vmx_exit(void)
8651 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8652 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8653 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8654 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8655 free_page((unsigned long)vmx_io_bitmap_b
);
8656 free_page((unsigned long)vmx_io_bitmap_a
);
8657 free_page((unsigned long)vmx_vmwrite_bitmap
);
8658 free_page((unsigned long)vmx_vmread_bitmap
);
8661 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8668 module_init(vmx_init
)
8669 module_exit(vmx_exit
)