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[mirror_ubuntu-hirsute-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include <linux/ftrace_event.h>
29 #include <linux/slab.h>
30 #include "kvm_cache_regs.h"
31 #include "x86.h"
32
33 #include <asm/io.h>
34 #include <asm/desc.h>
35 #include <asm/vmx.h>
36 #include <asm/virtext.h>
37 #include <asm/mce.h>
38
39 #include "trace.h"
40
41 #define __ex(x) __kvm_handle_fault_on_reboot(x)
42
43 MODULE_AUTHOR("Qumranet");
44 MODULE_LICENSE("GPL");
45
46 static int __read_mostly bypass_guest_pf = 1;
47 module_param(bypass_guest_pf, bool, S_IRUGO);
48
49 static int __read_mostly enable_vpid = 1;
50 module_param_named(vpid, enable_vpid, bool, 0444);
51
52 static int __read_mostly flexpriority_enabled = 1;
53 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
54
55 static int __read_mostly enable_ept = 1;
56 module_param_named(ept, enable_ept, bool, S_IRUGO);
57
58 static int __read_mostly enable_unrestricted_guest = 1;
59 module_param_named(unrestricted_guest,
60 enable_unrestricted_guest, bool, S_IRUGO);
61
62 static int __read_mostly emulate_invalid_guest_state = 0;
63 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
64
65 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
66 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
67 #define KVM_GUEST_CR0_MASK \
68 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
69 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
70 (X86_CR0_WP | X86_CR0_NE)
71 #define KVM_VM_CR0_ALWAYS_ON \
72 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
73 #define KVM_CR4_GUEST_OWNED_BITS \
74 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
75 | X86_CR4_OSXMMEXCPT)
76
77 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
78 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
79
80 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
81
82 /*
83 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
84 * ple_gap: upper bound on the amount of time between two successive
85 * executions of PAUSE in a loop. Also indicate if ple enabled.
86 * According to test, this time is usually small than 41 cycles.
87 * ple_window: upper bound on the amount of time a guest is allowed to execute
88 * in a PAUSE loop. Tests indicate that most spinlocks are held for
89 * less than 2^12 cycles
90 * Time is measured based on a counter that runs at the same rate as the TSC,
91 * refer SDM volume 3b section 21.6.13 & 22.1.3.
92 */
93 #define KVM_VMX_DEFAULT_PLE_GAP 41
94 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
95 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
96 module_param(ple_gap, int, S_IRUGO);
97
98 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
99 module_param(ple_window, int, S_IRUGO);
100
101 struct vmcs {
102 u32 revision_id;
103 u32 abort;
104 char data[0];
105 };
106
107 struct shared_msr_entry {
108 unsigned index;
109 u64 data;
110 u64 mask;
111 };
112
113 struct vcpu_vmx {
114 struct kvm_vcpu vcpu;
115 struct list_head local_vcpus_link;
116 unsigned long host_rsp;
117 int launched;
118 u8 fail;
119 u32 idt_vectoring_info;
120 struct shared_msr_entry *guest_msrs;
121 int nmsrs;
122 int save_nmsrs;
123 #ifdef CONFIG_X86_64
124 u64 msr_host_kernel_gs_base;
125 u64 msr_guest_kernel_gs_base;
126 #endif
127 struct vmcs *vmcs;
128 struct {
129 int loaded;
130 u16 fs_sel, gs_sel, ldt_sel;
131 int gs_ldt_reload_needed;
132 int fs_reload_needed;
133 } host_state;
134 struct {
135 int vm86_active;
136 ulong save_rflags;
137 struct kvm_save_segment {
138 u16 selector;
139 unsigned long base;
140 u32 limit;
141 u32 ar;
142 } tr, es, ds, fs, gs;
143 struct {
144 bool pending;
145 u8 vector;
146 unsigned rip;
147 } irq;
148 } rmode;
149 int vpid;
150 bool emulation_required;
151
152 /* Support for vnmi-less CPUs */
153 int soft_vnmi_blocked;
154 ktime_t entry_time;
155 s64 vnmi_blocked_time;
156 u32 exit_reason;
157
158 bool rdtscp_enabled;
159 };
160
161 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
162 {
163 return container_of(vcpu, struct vcpu_vmx, vcpu);
164 }
165
166 static int init_rmode(struct kvm *kvm);
167 static u64 construct_eptp(unsigned long root_hpa);
168
169 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
170 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
171 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
172
173 static unsigned long *vmx_io_bitmap_a;
174 static unsigned long *vmx_io_bitmap_b;
175 static unsigned long *vmx_msr_bitmap_legacy;
176 static unsigned long *vmx_msr_bitmap_longmode;
177
178 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
179 static DEFINE_SPINLOCK(vmx_vpid_lock);
180
181 static struct vmcs_config {
182 int size;
183 int order;
184 u32 revision_id;
185 u32 pin_based_exec_ctrl;
186 u32 cpu_based_exec_ctrl;
187 u32 cpu_based_2nd_exec_ctrl;
188 u32 vmexit_ctrl;
189 u32 vmentry_ctrl;
190 } vmcs_config;
191
192 static struct vmx_capability {
193 u32 ept;
194 u32 vpid;
195 } vmx_capability;
196
197 #define VMX_SEGMENT_FIELD(seg) \
198 [VCPU_SREG_##seg] = { \
199 .selector = GUEST_##seg##_SELECTOR, \
200 .base = GUEST_##seg##_BASE, \
201 .limit = GUEST_##seg##_LIMIT, \
202 .ar_bytes = GUEST_##seg##_AR_BYTES, \
203 }
204
205 static struct kvm_vmx_segment_field {
206 unsigned selector;
207 unsigned base;
208 unsigned limit;
209 unsigned ar_bytes;
210 } kvm_vmx_segment_fields[] = {
211 VMX_SEGMENT_FIELD(CS),
212 VMX_SEGMENT_FIELD(DS),
213 VMX_SEGMENT_FIELD(ES),
214 VMX_SEGMENT_FIELD(FS),
215 VMX_SEGMENT_FIELD(GS),
216 VMX_SEGMENT_FIELD(SS),
217 VMX_SEGMENT_FIELD(TR),
218 VMX_SEGMENT_FIELD(LDTR),
219 };
220
221 static u64 host_efer;
222
223 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
224
225 /*
226 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
227 * away by decrementing the array size.
228 */
229 static const u32 vmx_msr_index[] = {
230 #ifdef CONFIG_X86_64
231 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
232 #endif
233 MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
234 };
235 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
236
237 static inline bool is_page_fault(u32 intr_info)
238 {
239 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
240 INTR_INFO_VALID_MASK)) ==
241 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
242 }
243
244 static inline bool is_no_device(u32 intr_info)
245 {
246 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
247 INTR_INFO_VALID_MASK)) ==
248 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
249 }
250
251 static inline bool is_invalid_opcode(u32 intr_info)
252 {
253 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
254 INTR_INFO_VALID_MASK)) ==
255 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
256 }
257
258 static inline bool is_external_interrupt(u32 intr_info)
259 {
260 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
261 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
262 }
263
264 static inline bool is_machine_check(u32 intr_info)
265 {
266 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
267 INTR_INFO_VALID_MASK)) ==
268 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
269 }
270
271 static inline bool cpu_has_vmx_msr_bitmap(void)
272 {
273 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
274 }
275
276 static inline bool cpu_has_vmx_tpr_shadow(void)
277 {
278 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
279 }
280
281 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
282 {
283 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
284 }
285
286 static inline bool cpu_has_secondary_exec_ctrls(void)
287 {
288 return vmcs_config.cpu_based_exec_ctrl &
289 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
290 }
291
292 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
293 {
294 return vmcs_config.cpu_based_2nd_exec_ctrl &
295 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
296 }
297
298 static inline bool cpu_has_vmx_flexpriority(void)
299 {
300 return cpu_has_vmx_tpr_shadow() &&
301 cpu_has_vmx_virtualize_apic_accesses();
302 }
303
304 static inline bool cpu_has_vmx_ept_execute_only(void)
305 {
306 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
307 }
308
309 static inline bool cpu_has_vmx_eptp_uncacheable(void)
310 {
311 return vmx_capability.ept & VMX_EPTP_UC_BIT;
312 }
313
314 static inline bool cpu_has_vmx_eptp_writeback(void)
315 {
316 return vmx_capability.ept & VMX_EPTP_WB_BIT;
317 }
318
319 static inline bool cpu_has_vmx_ept_2m_page(void)
320 {
321 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
322 }
323
324 static inline bool cpu_has_vmx_ept_1g_page(void)
325 {
326 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
327 }
328
329 static inline bool cpu_has_vmx_invept_individual_addr(void)
330 {
331 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
332 }
333
334 static inline bool cpu_has_vmx_invept_context(void)
335 {
336 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
337 }
338
339 static inline bool cpu_has_vmx_invept_global(void)
340 {
341 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
342 }
343
344 static inline bool cpu_has_vmx_ept(void)
345 {
346 return vmcs_config.cpu_based_2nd_exec_ctrl &
347 SECONDARY_EXEC_ENABLE_EPT;
348 }
349
350 static inline bool cpu_has_vmx_unrestricted_guest(void)
351 {
352 return vmcs_config.cpu_based_2nd_exec_ctrl &
353 SECONDARY_EXEC_UNRESTRICTED_GUEST;
354 }
355
356 static inline bool cpu_has_vmx_ple(void)
357 {
358 return vmcs_config.cpu_based_2nd_exec_ctrl &
359 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
360 }
361
362 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
363 {
364 return flexpriority_enabled && irqchip_in_kernel(kvm);
365 }
366
367 static inline bool cpu_has_vmx_vpid(void)
368 {
369 return vmcs_config.cpu_based_2nd_exec_ctrl &
370 SECONDARY_EXEC_ENABLE_VPID;
371 }
372
373 static inline bool cpu_has_vmx_rdtscp(void)
374 {
375 return vmcs_config.cpu_based_2nd_exec_ctrl &
376 SECONDARY_EXEC_RDTSCP;
377 }
378
379 static inline bool cpu_has_virtual_nmis(void)
380 {
381 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
382 }
383
384 static inline bool report_flexpriority(void)
385 {
386 return flexpriority_enabled;
387 }
388
389 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
390 {
391 int i;
392
393 for (i = 0; i < vmx->nmsrs; ++i)
394 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
395 return i;
396 return -1;
397 }
398
399 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
400 {
401 struct {
402 u64 vpid : 16;
403 u64 rsvd : 48;
404 u64 gva;
405 } operand = { vpid, 0, gva };
406
407 asm volatile (__ex(ASM_VMX_INVVPID)
408 /* CF==1 or ZF==1 --> rc = -1 */
409 "; ja 1f ; ud2 ; 1:"
410 : : "a"(&operand), "c"(ext) : "cc", "memory");
411 }
412
413 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
414 {
415 struct {
416 u64 eptp, gpa;
417 } operand = {eptp, gpa};
418
419 asm volatile (__ex(ASM_VMX_INVEPT)
420 /* CF==1 or ZF==1 --> rc = -1 */
421 "; ja 1f ; ud2 ; 1:\n"
422 : : "a" (&operand), "c" (ext) : "cc", "memory");
423 }
424
425 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
426 {
427 int i;
428
429 i = __find_msr_index(vmx, msr);
430 if (i >= 0)
431 return &vmx->guest_msrs[i];
432 return NULL;
433 }
434
435 static void vmcs_clear(struct vmcs *vmcs)
436 {
437 u64 phys_addr = __pa(vmcs);
438 u8 error;
439
440 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
441 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
442 : "cc", "memory");
443 if (error)
444 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
445 vmcs, phys_addr);
446 }
447
448 static void __vcpu_clear(void *arg)
449 {
450 struct vcpu_vmx *vmx = arg;
451 int cpu = raw_smp_processor_id();
452
453 if (vmx->vcpu.cpu == cpu)
454 vmcs_clear(vmx->vmcs);
455 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
456 per_cpu(current_vmcs, cpu) = NULL;
457 rdtscll(vmx->vcpu.arch.host_tsc);
458 list_del(&vmx->local_vcpus_link);
459 vmx->vcpu.cpu = -1;
460 vmx->launched = 0;
461 }
462
463 static void vcpu_clear(struct vcpu_vmx *vmx)
464 {
465 if (vmx->vcpu.cpu == -1)
466 return;
467 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
468 }
469
470 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
471 {
472 if (vmx->vpid == 0)
473 return;
474
475 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
476 }
477
478 static inline void ept_sync_global(void)
479 {
480 if (cpu_has_vmx_invept_global())
481 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
482 }
483
484 static inline void ept_sync_context(u64 eptp)
485 {
486 if (enable_ept) {
487 if (cpu_has_vmx_invept_context())
488 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
489 else
490 ept_sync_global();
491 }
492 }
493
494 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
495 {
496 if (enable_ept) {
497 if (cpu_has_vmx_invept_individual_addr())
498 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
499 eptp, gpa);
500 else
501 ept_sync_context(eptp);
502 }
503 }
504
505 static unsigned long vmcs_readl(unsigned long field)
506 {
507 unsigned long value;
508
509 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
510 : "=a"(value) : "d"(field) : "cc");
511 return value;
512 }
513
514 static u16 vmcs_read16(unsigned long field)
515 {
516 return vmcs_readl(field);
517 }
518
519 static u32 vmcs_read32(unsigned long field)
520 {
521 return vmcs_readl(field);
522 }
523
524 static u64 vmcs_read64(unsigned long field)
525 {
526 #ifdef CONFIG_X86_64
527 return vmcs_readl(field);
528 #else
529 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
530 #endif
531 }
532
533 static noinline void vmwrite_error(unsigned long field, unsigned long value)
534 {
535 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
536 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
537 dump_stack();
538 }
539
540 static void vmcs_writel(unsigned long field, unsigned long value)
541 {
542 u8 error;
543
544 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
545 : "=q"(error) : "a"(value), "d"(field) : "cc");
546 if (unlikely(error))
547 vmwrite_error(field, value);
548 }
549
550 static void vmcs_write16(unsigned long field, u16 value)
551 {
552 vmcs_writel(field, value);
553 }
554
555 static void vmcs_write32(unsigned long field, u32 value)
556 {
557 vmcs_writel(field, value);
558 }
559
560 static void vmcs_write64(unsigned long field, u64 value)
561 {
562 vmcs_writel(field, value);
563 #ifndef CONFIG_X86_64
564 asm volatile ("");
565 vmcs_writel(field+1, value >> 32);
566 #endif
567 }
568
569 static void vmcs_clear_bits(unsigned long field, u32 mask)
570 {
571 vmcs_writel(field, vmcs_readl(field) & ~mask);
572 }
573
574 static void vmcs_set_bits(unsigned long field, u32 mask)
575 {
576 vmcs_writel(field, vmcs_readl(field) | mask);
577 }
578
579 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
580 {
581 u32 eb;
582
583 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
584 (1u << NM_VECTOR) | (1u << DB_VECTOR);
585 if ((vcpu->guest_debug &
586 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
587 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
588 eb |= 1u << BP_VECTOR;
589 if (to_vmx(vcpu)->rmode.vm86_active)
590 eb = ~0;
591 if (enable_ept)
592 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
593 if (vcpu->fpu_active)
594 eb &= ~(1u << NM_VECTOR);
595 vmcs_write32(EXCEPTION_BITMAP, eb);
596 }
597
598 static void reload_tss(void)
599 {
600 /*
601 * VT restores TR but not its size. Useless.
602 */
603 struct desc_ptr gdt;
604 struct desc_struct *descs;
605
606 native_store_gdt(&gdt);
607 descs = (void *)gdt.address;
608 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
609 load_TR_desc();
610 }
611
612 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
613 {
614 u64 guest_efer;
615 u64 ignore_bits;
616
617 guest_efer = vmx->vcpu.arch.efer;
618
619 /*
620 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
621 * outside long mode
622 */
623 ignore_bits = EFER_NX | EFER_SCE;
624 #ifdef CONFIG_X86_64
625 ignore_bits |= EFER_LMA | EFER_LME;
626 /* SCE is meaningful only in long mode on Intel */
627 if (guest_efer & EFER_LMA)
628 ignore_bits &= ~(u64)EFER_SCE;
629 #endif
630 guest_efer &= ~ignore_bits;
631 guest_efer |= host_efer & ignore_bits;
632 vmx->guest_msrs[efer_offset].data = guest_efer;
633 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
634 return true;
635 }
636
637 static unsigned long segment_base(u16 selector)
638 {
639 struct desc_ptr gdt;
640 struct desc_struct *d;
641 unsigned long table_base;
642 unsigned long v;
643
644 if (!(selector & ~3))
645 return 0;
646
647 native_store_gdt(&gdt);
648 table_base = gdt.address;
649
650 if (selector & 4) { /* from ldt */
651 u16 ldt_selector = kvm_read_ldt();
652
653 if (!(ldt_selector & ~3))
654 return 0;
655
656 table_base = segment_base(ldt_selector);
657 }
658 d = (struct desc_struct *)(table_base + (selector & ~7));
659 v = get_desc_base(d);
660 #ifdef CONFIG_X86_64
661 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
662 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
663 #endif
664 return v;
665 }
666
667 static inline unsigned long kvm_read_tr_base(void)
668 {
669 u16 tr;
670 asm("str %0" : "=g"(tr));
671 return segment_base(tr);
672 }
673
674 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
675 {
676 struct vcpu_vmx *vmx = to_vmx(vcpu);
677 int i;
678
679 if (vmx->host_state.loaded)
680 return;
681
682 vmx->host_state.loaded = 1;
683 /*
684 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
685 * allow segment selectors with cpl > 0 or ti == 1.
686 */
687 vmx->host_state.ldt_sel = kvm_read_ldt();
688 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
689 vmx->host_state.fs_sel = kvm_read_fs();
690 if (!(vmx->host_state.fs_sel & 7)) {
691 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
692 vmx->host_state.fs_reload_needed = 0;
693 } else {
694 vmcs_write16(HOST_FS_SELECTOR, 0);
695 vmx->host_state.fs_reload_needed = 1;
696 }
697 vmx->host_state.gs_sel = kvm_read_gs();
698 if (!(vmx->host_state.gs_sel & 7))
699 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
700 else {
701 vmcs_write16(HOST_GS_SELECTOR, 0);
702 vmx->host_state.gs_ldt_reload_needed = 1;
703 }
704
705 #ifdef CONFIG_X86_64
706 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
707 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
708 #else
709 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
710 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
711 #endif
712
713 #ifdef CONFIG_X86_64
714 if (is_long_mode(&vmx->vcpu)) {
715 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
716 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
717 }
718 #endif
719 for (i = 0; i < vmx->save_nmsrs; ++i)
720 kvm_set_shared_msr(vmx->guest_msrs[i].index,
721 vmx->guest_msrs[i].data,
722 vmx->guest_msrs[i].mask);
723 }
724
725 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
726 {
727 unsigned long flags;
728
729 if (!vmx->host_state.loaded)
730 return;
731
732 ++vmx->vcpu.stat.host_state_reload;
733 vmx->host_state.loaded = 0;
734 if (vmx->host_state.fs_reload_needed)
735 kvm_load_fs(vmx->host_state.fs_sel);
736 if (vmx->host_state.gs_ldt_reload_needed) {
737 kvm_load_ldt(vmx->host_state.ldt_sel);
738 /*
739 * If we have to reload gs, we must take care to
740 * preserve our gs base.
741 */
742 local_irq_save(flags);
743 kvm_load_gs(vmx->host_state.gs_sel);
744 #ifdef CONFIG_X86_64
745 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
746 #endif
747 local_irq_restore(flags);
748 }
749 reload_tss();
750 #ifdef CONFIG_X86_64
751 if (is_long_mode(&vmx->vcpu)) {
752 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
753 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
754 }
755 #endif
756 }
757
758 static void vmx_load_host_state(struct vcpu_vmx *vmx)
759 {
760 preempt_disable();
761 __vmx_load_host_state(vmx);
762 preempt_enable();
763 }
764
765 /*
766 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
767 * vcpu mutex is already taken.
768 */
769 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
770 {
771 struct vcpu_vmx *vmx = to_vmx(vcpu);
772 u64 phys_addr = __pa(vmx->vmcs);
773 u64 tsc_this, delta, new_offset;
774
775 if (vcpu->cpu != cpu) {
776 vcpu_clear(vmx);
777 kvm_migrate_timers(vcpu);
778 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
779 local_irq_disable();
780 list_add(&vmx->local_vcpus_link,
781 &per_cpu(vcpus_on_cpu, cpu));
782 local_irq_enable();
783 }
784
785 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
786 u8 error;
787
788 per_cpu(current_vmcs, cpu) = vmx->vmcs;
789 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
790 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
791 : "cc");
792 if (error)
793 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
794 vmx->vmcs, phys_addr);
795 }
796
797 if (vcpu->cpu != cpu) {
798 struct desc_ptr dt;
799 unsigned long sysenter_esp;
800
801 vcpu->cpu = cpu;
802 /*
803 * Linux uses per-cpu TSS and GDT, so set these when switching
804 * processors.
805 */
806 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
807 native_store_gdt(&dt);
808 vmcs_writel(HOST_GDTR_BASE, dt.address); /* 22.2.4 */
809
810 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
811 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
812
813 /*
814 * Make sure the time stamp counter is monotonous.
815 */
816 rdtscll(tsc_this);
817 if (tsc_this < vcpu->arch.host_tsc) {
818 delta = vcpu->arch.host_tsc - tsc_this;
819 new_offset = vmcs_read64(TSC_OFFSET) + delta;
820 vmcs_write64(TSC_OFFSET, new_offset);
821 }
822 }
823 }
824
825 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
826 {
827 __vmx_load_host_state(to_vmx(vcpu));
828 }
829
830 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
831 {
832 ulong cr0;
833
834 if (vcpu->fpu_active)
835 return;
836 vcpu->fpu_active = 1;
837 cr0 = vmcs_readl(GUEST_CR0);
838 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
839 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
840 vmcs_writel(GUEST_CR0, cr0);
841 update_exception_bitmap(vcpu);
842 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
843 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
844 }
845
846 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
847
848 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
849 {
850 vmx_decache_cr0_guest_bits(vcpu);
851 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
852 update_exception_bitmap(vcpu);
853 vcpu->arch.cr0_guest_owned_bits = 0;
854 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
855 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
856 }
857
858 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
859 {
860 unsigned long rflags, save_rflags;
861
862 rflags = vmcs_readl(GUEST_RFLAGS);
863 if (to_vmx(vcpu)->rmode.vm86_active) {
864 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
865 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
866 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
867 }
868 return rflags;
869 }
870
871 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
872 {
873 if (to_vmx(vcpu)->rmode.vm86_active) {
874 to_vmx(vcpu)->rmode.save_rflags = rflags;
875 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
876 }
877 vmcs_writel(GUEST_RFLAGS, rflags);
878 }
879
880 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
881 {
882 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
883 int ret = 0;
884
885 if (interruptibility & GUEST_INTR_STATE_STI)
886 ret |= KVM_X86_SHADOW_INT_STI;
887 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
888 ret |= KVM_X86_SHADOW_INT_MOV_SS;
889
890 return ret & mask;
891 }
892
893 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
894 {
895 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
896 u32 interruptibility = interruptibility_old;
897
898 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
899
900 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
901 interruptibility |= GUEST_INTR_STATE_MOV_SS;
902 else if (mask & KVM_X86_SHADOW_INT_STI)
903 interruptibility |= GUEST_INTR_STATE_STI;
904
905 if ((interruptibility != interruptibility_old))
906 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
907 }
908
909 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
910 {
911 unsigned long rip;
912
913 rip = kvm_rip_read(vcpu);
914 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
915 kvm_rip_write(vcpu, rip);
916
917 /* skipping an emulated instruction also counts */
918 vmx_set_interrupt_shadow(vcpu, 0);
919 }
920
921 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
922 bool has_error_code, u32 error_code,
923 bool reinject)
924 {
925 struct vcpu_vmx *vmx = to_vmx(vcpu);
926 u32 intr_info = nr | INTR_INFO_VALID_MASK;
927
928 if (has_error_code) {
929 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
930 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
931 }
932
933 if (vmx->rmode.vm86_active) {
934 vmx->rmode.irq.pending = true;
935 vmx->rmode.irq.vector = nr;
936 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
937 if (kvm_exception_is_soft(nr))
938 vmx->rmode.irq.rip +=
939 vmx->vcpu.arch.event_exit_inst_len;
940 intr_info |= INTR_TYPE_SOFT_INTR;
941 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
942 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
943 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
944 return;
945 }
946
947 if (kvm_exception_is_soft(nr)) {
948 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
949 vmx->vcpu.arch.event_exit_inst_len);
950 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
951 } else
952 intr_info |= INTR_TYPE_HARD_EXCEPTION;
953
954 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
955 }
956
957 static bool vmx_rdtscp_supported(void)
958 {
959 return cpu_has_vmx_rdtscp();
960 }
961
962 /*
963 * Swap MSR entry in host/guest MSR entry array.
964 */
965 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
966 {
967 struct shared_msr_entry tmp;
968
969 tmp = vmx->guest_msrs[to];
970 vmx->guest_msrs[to] = vmx->guest_msrs[from];
971 vmx->guest_msrs[from] = tmp;
972 }
973
974 /*
975 * Set up the vmcs to automatically save and restore system
976 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
977 * mode, as fiddling with msrs is very expensive.
978 */
979 static void setup_msrs(struct vcpu_vmx *vmx)
980 {
981 int save_nmsrs, index;
982 unsigned long *msr_bitmap;
983
984 vmx_load_host_state(vmx);
985 save_nmsrs = 0;
986 #ifdef CONFIG_X86_64
987 if (is_long_mode(&vmx->vcpu)) {
988 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
989 if (index >= 0)
990 move_msr_up(vmx, index, save_nmsrs++);
991 index = __find_msr_index(vmx, MSR_LSTAR);
992 if (index >= 0)
993 move_msr_up(vmx, index, save_nmsrs++);
994 index = __find_msr_index(vmx, MSR_CSTAR);
995 if (index >= 0)
996 move_msr_up(vmx, index, save_nmsrs++);
997 index = __find_msr_index(vmx, MSR_TSC_AUX);
998 if (index >= 0 && vmx->rdtscp_enabled)
999 move_msr_up(vmx, index, save_nmsrs++);
1000 /*
1001 * MSR_K6_STAR is only needed on long mode guests, and only
1002 * if efer.sce is enabled.
1003 */
1004 index = __find_msr_index(vmx, MSR_K6_STAR);
1005 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1006 move_msr_up(vmx, index, save_nmsrs++);
1007 }
1008 #endif
1009 index = __find_msr_index(vmx, MSR_EFER);
1010 if (index >= 0 && update_transition_efer(vmx, index))
1011 move_msr_up(vmx, index, save_nmsrs++);
1012
1013 vmx->save_nmsrs = save_nmsrs;
1014
1015 if (cpu_has_vmx_msr_bitmap()) {
1016 if (is_long_mode(&vmx->vcpu))
1017 msr_bitmap = vmx_msr_bitmap_longmode;
1018 else
1019 msr_bitmap = vmx_msr_bitmap_legacy;
1020
1021 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1022 }
1023 }
1024
1025 /*
1026 * reads and returns guest's timestamp counter "register"
1027 * guest_tsc = host_tsc + tsc_offset -- 21.3
1028 */
1029 static u64 guest_read_tsc(void)
1030 {
1031 u64 host_tsc, tsc_offset;
1032
1033 rdtscll(host_tsc);
1034 tsc_offset = vmcs_read64(TSC_OFFSET);
1035 return host_tsc + tsc_offset;
1036 }
1037
1038 /*
1039 * writes 'guest_tsc' into guest's timestamp counter "register"
1040 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1041 */
1042 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1043 {
1044 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1045 }
1046
1047 /*
1048 * Reads an msr value (of 'msr_index') into 'pdata'.
1049 * Returns 0 on success, non-0 otherwise.
1050 * Assumes vcpu_load() was already called.
1051 */
1052 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1053 {
1054 u64 data;
1055 struct shared_msr_entry *msr;
1056
1057 if (!pdata) {
1058 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1059 return -EINVAL;
1060 }
1061
1062 switch (msr_index) {
1063 #ifdef CONFIG_X86_64
1064 case MSR_FS_BASE:
1065 data = vmcs_readl(GUEST_FS_BASE);
1066 break;
1067 case MSR_GS_BASE:
1068 data = vmcs_readl(GUEST_GS_BASE);
1069 break;
1070 case MSR_KERNEL_GS_BASE:
1071 vmx_load_host_state(to_vmx(vcpu));
1072 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1073 break;
1074 #endif
1075 case MSR_EFER:
1076 return kvm_get_msr_common(vcpu, msr_index, pdata);
1077 case MSR_IA32_TSC:
1078 data = guest_read_tsc();
1079 break;
1080 case MSR_IA32_SYSENTER_CS:
1081 data = vmcs_read32(GUEST_SYSENTER_CS);
1082 break;
1083 case MSR_IA32_SYSENTER_EIP:
1084 data = vmcs_readl(GUEST_SYSENTER_EIP);
1085 break;
1086 case MSR_IA32_SYSENTER_ESP:
1087 data = vmcs_readl(GUEST_SYSENTER_ESP);
1088 break;
1089 case MSR_TSC_AUX:
1090 if (!to_vmx(vcpu)->rdtscp_enabled)
1091 return 1;
1092 /* Otherwise falls through */
1093 default:
1094 vmx_load_host_state(to_vmx(vcpu));
1095 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1096 if (msr) {
1097 vmx_load_host_state(to_vmx(vcpu));
1098 data = msr->data;
1099 break;
1100 }
1101 return kvm_get_msr_common(vcpu, msr_index, pdata);
1102 }
1103
1104 *pdata = data;
1105 return 0;
1106 }
1107
1108 /*
1109 * Writes msr value into into the appropriate "register".
1110 * Returns 0 on success, non-0 otherwise.
1111 * Assumes vcpu_load() was already called.
1112 */
1113 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1114 {
1115 struct vcpu_vmx *vmx = to_vmx(vcpu);
1116 struct shared_msr_entry *msr;
1117 u64 host_tsc;
1118 int ret = 0;
1119
1120 switch (msr_index) {
1121 case MSR_EFER:
1122 vmx_load_host_state(vmx);
1123 ret = kvm_set_msr_common(vcpu, msr_index, data);
1124 break;
1125 #ifdef CONFIG_X86_64
1126 case MSR_FS_BASE:
1127 vmcs_writel(GUEST_FS_BASE, data);
1128 break;
1129 case MSR_GS_BASE:
1130 vmcs_writel(GUEST_GS_BASE, data);
1131 break;
1132 case MSR_KERNEL_GS_BASE:
1133 vmx_load_host_state(vmx);
1134 vmx->msr_guest_kernel_gs_base = data;
1135 break;
1136 #endif
1137 case MSR_IA32_SYSENTER_CS:
1138 vmcs_write32(GUEST_SYSENTER_CS, data);
1139 break;
1140 case MSR_IA32_SYSENTER_EIP:
1141 vmcs_writel(GUEST_SYSENTER_EIP, data);
1142 break;
1143 case MSR_IA32_SYSENTER_ESP:
1144 vmcs_writel(GUEST_SYSENTER_ESP, data);
1145 break;
1146 case MSR_IA32_TSC:
1147 rdtscll(host_tsc);
1148 guest_write_tsc(data, host_tsc);
1149 break;
1150 case MSR_IA32_CR_PAT:
1151 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1152 vmcs_write64(GUEST_IA32_PAT, data);
1153 vcpu->arch.pat = data;
1154 break;
1155 }
1156 ret = kvm_set_msr_common(vcpu, msr_index, data);
1157 break;
1158 case MSR_TSC_AUX:
1159 if (!vmx->rdtscp_enabled)
1160 return 1;
1161 /* Check reserved bit, higher 32 bits should be zero */
1162 if ((data >> 32) != 0)
1163 return 1;
1164 /* Otherwise falls through */
1165 default:
1166 msr = find_msr_entry(vmx, msr_index);
1167 if (msr) {
1168 vmx_load_host_state(vmx);
1169 msr->data = data;
1170 break;
1171 }
1172 ret = kvm_set_msr_common(vcpu, msr_index, data);
1173 }
1174
1175 return ret;
1176 }
1177
1178 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1179 {
1180 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1181 switch (reg) {
1182 case VCPU_REGS_RSP:
1183 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1184 break;
1185 case VCPU_REGS_RIP:
1186 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1187 break;
1188 case VCPU_EXREG_PDPTR:
1189 if (enable_ept)
1190 ept_save_pdptrs(vcpu);
1191 break;
1192 default:
1193 break;
1194 }
1195 }
1196
1197 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1198 {
1199 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1200 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1201 else
1202 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1203
1204 update_exception_bitmap(vcpu);
1205 }
1206
1207 static __init int cpu_has_kvm_support(void)
1208 {
1209 return cpu_has_vmx();
1210 }
1211
1212 static __init int vmx_disabled_by_bios(void)
1213 {
1214 u64 msr;
1215
1216 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1217 return (msr & (FEATURE_CONTROL_LOCKED |
1218 FEATURE_CONTROL_VMXON_ENABLED))
1219 == FEATURE_CONTROL_LOCKED;
1220 /* locked but not enabled */
1221 }
1222
1223 static int hardware_enable(void *garbage)
1224 {
1225 int cpu = raw_smp_processor_id();
1226 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1227 u64 old;
1228
1229 if (read_cr4() & X86_CR4_VMXE)
1230 return -EBUSY;
1231
1232 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1233 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1234 if ((old & (FEATURE_CONTROL_LOCKED |
1235 FEATURE_CONTROL_VMXON_ENABLED))
1236 != (FEATURE_CONTROL_LOCKED |
1237 FEATURE_CONTROL_VMXON_ENABLED))
1238 /* enable and lock */
1239 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1240 FEATURE_CONTROL_LOCKED |
1241 FEATURE_CONTROL_VMXON_ENABLED);
1242 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1243 asm volatile (ASM_VMX_VMXON_RAX
1244 : : "a"(&phys_addr), "m"(phys_addr)
1245 : "memory", "cc");
1246
1247 ept_sync_global();
1248
1249 return 0;
1250 }
1251
1252 static void vmclear_local_vcpus(void)
1253 {
1254 int cpu = raw_smp_processor_id();
1255 struct vcpu_vmx *vmx, *n;
1256
1257 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1258 local_vcpus_link)
1259 __vcpu_clear(vmx);
1260 }
1261
1262
1263 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1264 * tricks.
1265 */
1266 static void kvm_cpu_vmxoff(void)
1267 {
1268 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1269 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1270 }
1271
1272 static void hardware_disable(void *garbage)
1273 {
1274 vmclear_local_vcpus();
1275 kvm_cpu_vmxoff();
1276 }
1277
1278 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1279 u32 msr, u32 *result)
1280 {
1281 u32 vmx_msr_low, vmx_msr_high;
1282 u32 ctl = ctl_min | ctl_opt;
1283
1284 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1285
1286 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1287 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1288
1289 /* Ensure minimum (required) set of control bits are supported. */
1290 if (ctl_min & ~ctl)
1291 return -EIO;
1292
1293 *result = ctl;
1294 return 0;
1295 }
1296
1297 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1298 {
1299 u32 vmx_msr_low, vmx_msr_high;
1300 u32 min, opt, min2, opt2;
1301 u32 _pin_based_exec_control = 0;
1302 u32 _cpu_based_exec_control = 0;
1303 u32 _cpu_based_2nd_exec_control = 0;
1304 u32 _vmexit_control = 0;
1305 u32 _vmentry_control = 0;
1306
1307 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1308 opt = PIN_BASED_VIRTUAL_NMIS;
1309 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1310 &_pin_based_exec_control) < 0)
1311 return -EIO;
1312
1313 min = CPU_BASED_HLT_EXITING |
1314 #ifdef CONFIG_X86_64
1315 CPU_BASED_CR8_LOAD_EXITING |
1316 CPU_BASED_CR8_STORE_EXITING |
1317 #endif
1318 CPU_BASED_CR3_LOAD_EXITING |
1319 CPU_BASED_CR3_STORE_EXITING |
1320 CPU_BASED_USE_IO_BITMAPS |
1321 CPU_BASED_MOV_DR_EXITING |
1322 CPU_BASED_USE_TSC_OFFSETING |
1323 CPU_BASED_MWAIT_EXITING |
1324 CPU_BASED_MONITOR_EXITING |
1325 CPU_BASED_INVLPG_EXITING;
1326 opt = CPU_BASED_TPR_SHADOW |
1327 CPU_BASED_USE_MSR_BITMAPS |
1328 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1329 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1330 &_cpu_based_exec_control) < 0)
1331 return -EIO;
1332 #ifdef CONFIG_X86_64
1333 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1334 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1335 ~CPU_BASED_CR8_STORE_EXITING;
1336 #endif
1337 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1338 min2 = 0;
1339 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1340 SECONDARY_EXEC_WBINVD_EXITING |
1341 SECONDARY_EXEC_ENABLE_VPID |
1342 SECONDARY_EXEC_ENABLE_EPT |
1343 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1344 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1345 SECONDARY_EXEC_RDTSCP;
1346 if (adjust_vmx_controls(min2, opt2,
1347 MSR_IA32_VMX_PROCBASED_CTLS2,
1348 &_cpu_based_2nd_exec_control) < 0)
1349 return -EIO;
1350 }
1351 #ifndef CONFIG_X86_64
1352 if (!(_cpu_based_2nd_exec_control &
1353 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1354 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1355 #endif
1356 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1357 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1358 enabled */
1359 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1360 CPU_BASED_CR3_STORE_EXITING |
1361 CPU_BASED_INVLPG_EXITING);
1362 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1363 vmx_capability.ept, vmx_capability.vpid);
1364 }
1365
1366 min = 0;
1367 #ifdef CONFIG_X86_64
1368 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1369 #endif
1370 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1371 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1372 &_vmexit_control) < 0)
1373 return -EIO;
1374
1375 min = 0;
1376 opt = VM_ENTRY_LOAD_IA32_PAT;
1377 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1378 &_vmentry_control) < 0)
1379 return -EIO;
1380
1381 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1382
1383 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1384 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1385 return -EIO;
1386
1387 #ifdef CONFIG_X86_64
1388 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1389 if (vmx_msr_high & (1u<<16))
1390 return -EIO;
1391 #endif
1392
1393 /* Require Write-Back (WB) memory type for VMCS accesses. */
1394 if (((vmx_msr_high >> 18) & 15) != 6)
1395 return -EIO;
1396
1397 vmcs_conf->size = vmx_msr_high & 0x1fff;
1398 vmcs_conf->order = get_order(vmcs_config.size);
1399 vmcs_conf->revision_id = vmx_msr_low;
1400
1401 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1402 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1403 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1404 vmcs_conf->vmexit_ctrl = _vmexit_control;
1405 vmcs_conf->vmentry_ctrl = _vmentry_control;
1406
1407 return 0;
1408 }
1409
1410 static struct vmcs *alloc_vmcs_cpu(int cpu)
1411 {
1412 int node = cpu_to_node(cpu);
1413 struct page *pages;
1414 struct vmcs *vmcs;
1415
1416 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1417 if (!pages)
1418 return NULL;
1419 vmcs = page_address(pages);
1420 memset(vmcs, 0, vmcs_config.size);
1421 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1422 return vmcs;
1423 }
1424
1425 static struct vmcs *alloc_vmcs(void)
1426 {
1427 return alloc_vmcs_cpu(raw_smp_processor_id());
1428 }
1429
1430 static void free_vmcs(struct vmcs *vmcs)
1431 {
1432 free_pages((unsigned long)vmcs, vmcs_config.order);
1433 }
1434
1435 static void free_kvm_area(void)
1436 {
1437 int cpu;
1438
1439 for_each_possible_cpu(cpu) {
1440 free_vmcs(per_cpu(vmxarea, cpu));
1441 per_cpu(vmxarea, cpu) = NULL;
1442 }
1443 }
1444
1445 static __init int alloc_kvm_area(void)
1446 {
1447 int cpu;
1448
1449 for_each_possible_cpu(cpu) {
1450 struct vmcs *vmcs;
1451
1452 vmcs = alloc_vmcs_cpu(cpu);
1453 if (!vmcs) {
1454 free_kvm_area();
1455 return -ENOMEM;
1456 }
1457
1458 per_cpu(vmxarea, cpu) = vmcs;
1459 }
1460 return 0;
1461 }
1462
1463 static __init int hardware_setup(void)
1464 {
1465 if (setup_vmcs_config(&vmcs_config) < 0)
1466 return -EIO;
1467
1468 if (boot_cpu_has(X86_FEATURE_NX))
1469 kvm_enable_efer_bits(EFER_NX);
1470
1471 if (!cpu_has_vmx_vpid())
1472 enable_vpid = 0;
1473
1474 if (!cpu_has_vmx_ept()) {
1475 enable_ept = 0;
1476 enable_unrestricted_guest = 0;
1477 }
1478
1479 if (!cpu_has_vmx_unrestricted_guest())
1480 enable_unrestricted_guest = 0;
1481
1482 if (!cpu_has_vmx_flexpriority())
1483 flexpriority_enabled = 0;
1484
1485 if (!cpu_has_vmx_tpr_shadow())
1486 kvm_x86_ops->update_cr8_intercept = NULL;
1487
1488 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1489 kvm_disable_largepages();
1490
1491 if (!cpu_has_vmx_ple())
1492 ple_gap = 0;
1493
1494 return alloc_kvm_area();
1495 }
1496
1497 static __exit void hardware_unsetup(void)
1498 {
1499 free_kvm_area();
1500 }
1501
1502 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1503 {
1504 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1505
1506 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1507 vmcs_write16(sf->selector, save->selector);
1508 vmcs_writel(sf->base, save->base);
1509 vmcs_write32(sf->limit, save->limit);
1510 vmcs_write32(sf->ar_bytes, save->ar);
1511 } else {
1512 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1513 << AR_DPL_SHIFT;
1514 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1515 }
1516 }
1517
1518 static void enter_pmode(struct kvm_vcpu *vcpu)
1519 {
1520 unsigned long flags;
1521 struct vcpu_vmx *vmx = to_vmx(vcpu);
1522
1523 vmx->emulation_required = 1;
1524 vmx->rmode.vm86_active = 0;
1525
1526 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1527 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1528 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1529
1530 flags = vmcs_readl(GUEST_RFLAGS);
1531 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1532 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1533 vmcs_writel(GUEST_RFLAGS, flags);
1534
1535 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1536 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1537
1538 update_exception_bitmap(vcpu);
1539
1540 if (emulate_invalid_guest_state)
1541 return;
1542
1543 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1544 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1545 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1546 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1547
1548 vmcs_write16(GUEST_SS_SELECTOR, 0);
1549 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1550
1551 vmcs_write16(GUEST_CS_SELECTOR,
1552 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1553 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1554 }
1555
1556 static gva_t rmode_tss_base(struct kvm *kvm)
1557 {
1558 if (!kvm->arch.tss_addr) {
1559 struct kvm_memslots *slots;
1560 gfn_t base_gfn;
1561
1562 slots = kvm_memslots(kvm);
1563 base_gfn = kvm->memslots->memslots[0].base_gfn +
1564 kvm->memslots->memslots[0].npages - 3;
1565 return base_gfn << PAGE_SHIFT;
1566 }
1567 return kvm->arch.tss_addr;
1568 }
1569
1570 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1571 {
1572 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1573
1574 save->selector = vmcs_read16(sf->selector);
1575 save->base = vmcs_readl(sf->base);
1576 save->limit = vmcs_read32(sf->limit);
1577 save->ar = vmcs_read32(sf->ar_bytes);
1578 vmcs_write16(sf->selector, save->base >> 4);
1579 vmcs_write32(sf->base, save->base & 0xfffff);
1580 vmcs_write32(sf->limit, 0xffff);
1581 vmcs_write32(sf->ar_bytes, 0xf3);
1582 }
1583
1584 static void enter_rmode(struct kvm_vcpu *vcpu)
1585 {
1586 unsigned long flags;
1587 struct vcpu_vmx *vmx = to_vmx(vcpu);
1588
1589 if (enable_unrestricted_guest)
1590 return;
1591
1592 vmx->emulation_required = 1;
1593 vmx->rmode.vm86_active = 1;
1594
1595 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1596 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1597
1598 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1599 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1600
1601 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1602 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1603
1604 flags = vmcs_readl(GUEST_RFLAGS);
1605 vmx->rmode.save_rflags = flags;
1606
1607 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1608
1609 vmcs_writel(GUEST_RFLAGS, flags);
1610 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1611 update_exception_bitmap(vcpu);
1612
1613 if (emulate_invalid_guest_state)
1614 goto continue_rmode;
1615
1616 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1617 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1618 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1619
1620 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1621 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1622 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1623 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1624 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1625
1626 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1627 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1628 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1629 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1630
1631 continue_rmode:
1632 kvm_mmu_reset_context(vcpu);
1633 init_rmode(vcpu->kvm);
1634 }
1635
1636 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1637 {
1638 struct vcpu_vmx *vmx = to_vmx(vcpu);
1639 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1640
1641 if (!msr)
1642 return;
1643
1644 /*
1645 * Force kernel_gs_base reloading before EFER changes, as control
1646 * of this msr depends on is_long_mode().
1647 */
1648 vmx_load_host_state(to_vmx(vcpu));
1649 vcpu->arch.efer = efer;
1650 if (efer & EFER_LMA) {
1651 vmcs_write32(VM_ENTRY_CONTROLS,
1652 vmcs_read32(VM_ENTRY_CONTROLS) |
1653 VM_ENTRY_IA32E_MODE);
1654 msr->data = efer;
1655 } else {
1656 vmcs_write32(VM_ENTRY_CONTROLS,
1657 vmcs_read32(VM_ENTRY_CONTROLS) &
1658 ~VM_ENTRY_IA32E_MODE);
1659
1660 msr->data = efer & ~EFER_LME;
1661 }
1662 setup_msrs(vmx);
1663 }
1664
1665 #ifdef CONFIG_X86_64
1666
1667 static void enter_lmode(struct kvm_vcpu *vcpu)
1668 {
1669 u32 guest_tr_ar;
1670
1671 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1672 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1673 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1674 __func__);
1675 vmcs_write32(GUEST_TR_AR_BYTES,
1676 (guest_tr_ar & ~AR_TYPE_MASK)
1677 | AR_TYPE_BUSY_64_TSS);
1678 }
1679 vcpu->arch.efer |= EFER_LMA;
1680 vmx_set_efer(vcpu, vcpu->arch.efer);
1681 }
1682
1683 static void exit_lmode(struct kvm_vcpu *vcpu)
1684 {
1685 vcpu->arch.efer &= ~EFER_LMA;
1686
1687 vmcs_write32(VM_ENTRY_CONTROLS,
1688 vmcs_read32(VM_ENTRY_CONTROLS)
1689 & ~VM_ENTRY_IA32E_MODE);
1690 }
1691
1692 #endif
1693
1694 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1695 {
1696 vpid_sync_vcpu_all(to_vmx(vcpu));
1697 if (enable_ept)
1698 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1699 }
1700
1701 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1702 {
1703 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1704
1705 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1706 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1707 }
1708
1709 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1710 {
1711 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1712
1713 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1714 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1715 }
1716
1717 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1718 {
1719 if (!test_bit(VCPU_EXREG_PDPTR,
1720 (unsigned long *)&vcpu->arch.regs_dirty))
1721 return;
1722
1723 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1724 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1725 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1726 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1727 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1728 }
1729 }
1730
1731 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1732 {
1733 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1734 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1735 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1736 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1737 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1738 }
1739
1740 __set_bit(VCPU_EXREG_PDPTR,
1741 (unsigned long *)&vcpu->arch.regs_avail);
1742 __set_bit(VCPU_EXREG_PDPTR,
1743 (unsigned long *)&vcpu->arch.regs_dirty);
1744 }
1745
1746 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1747
1748 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1749 unsigned long cr0,
1750 struct kvm_vcpu *vcpu)
1751 {
1752 if (!(cr0 & X86_CR0_PG)) {
1753 /* From paging/starting to nonpaging */
1754 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1755 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1756 (CPU_BASED_CR3_LOAD_EXITING |
1757 CPU_BASED_CR3_STORE_EXITING));
1758 vcpu->arch.cr0 = cr0;
1759 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1760 } else if (!is_paging(vcpu)) {
1761 /* From nonpaging to paging */
1762 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1763 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1764 ~(CPU_BASED_CR3_LOAD_EXITING |
1765 CPU_BASED_CR3_STORE_EXITING));
1766 vcpu->arch.cr0 = cr0;
1767 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1768 }
1769
1770 if (!(cr0 & X86_CR0_WP))
1771 *hw_cr0 &= ~X86_CR0_WP;
1772 }
1773
1774 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1775 {
1776 struct vcpu_vmx *vmx = to_vmx(vcpu);
1777 unsigned long hw_cr0;
1778
1779 if (enable_unrestricted_guest)
1780 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1781 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1782 else
1783 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1784
1785 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1786 enter_pmode(vcpu);
1787
1788 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1789 enter_rmode(vcpu);
1790
1791 #ifdef CONFIG_X86_64
1792 if (vcpu->arch.efer & EFER_LME) {
1793 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1794 enter_lmode(vcpu);
1795 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1796 exit_lmode(vcpu);
1797 }
1798 #endif
1799
1800 if (enable_ept)
1801 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1802
1803 if (!vcpu->fpu_active)
1804 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1805
1806 vmcs_writel(CR0_READ_SHADOW, cr0);
1807 vmcs_writel(GUEST_CR0, hw_cr0);
1808 vcpu->arch.cr0 = cr0;
1809 }
1810
1811 static u64 construct_eptp(unsigned long root_hpa)
1812 {
1813 u64 eptp;
1814
1815 /* TODO write the value reading from MSR */
1816 eptp = VMX_EPT_DEFAULT_MT |
1817 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1818 eptp |= (root_hpa & PAGE_MASK);
1819
1820 return eptp;
1821 }
1822
1823 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1824 {
1825 unsigned long guest_cr3;
1826 u64 eptp;
1827
1828 guest_cr3 = cr3;
1829 if (enable_ept) {
1830 eptp = construct_eptp(cr3);
1831 vmcs_write64(EPT_POINTER, eptp);
1832 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1833 vcpu->kvm->arch.ept_identity_map_addr;
1834 ept_load_pdptrs(vcpu);
1835 }
1836
1837 vmx_flush_tlb(vcpu);
1838 vmcs_writel(GUEST_CR3, guest_cr3);
1839 }
1840
1841 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1842 {
1843 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1844 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1845
1846 vcpu->arch.cr4 = cr4;
1847 if (enable_ept) {
1848 if (!is_paging(vcpu)) {
1849 hw_cr4 &= ~X86_CR4_PAE;
1850 hw_cr4 |= X86_CR4_PSE;
1851 } else if (!(cr4 & X86_CR4_PAE)) {
1852 hw_cr4 &= ~X86_CR4_PAE;
1853 }
1854 }
1855
1856 vmcs_writel(CR4_READ_SHADOW, cr4);
1857 vmcs_writel(GUEST_CR4, hw_cr4);
1858 }
1859
1860 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1861 {
1862 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1863
1864 return vmcs_readl(sf->base);
1865 }
1866
1867 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1868 struct kvm_segment *var, int seg)
1869 {
1870 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1871 u32 ar;
1872
1873 var->base = vmcs_readl(sf->base);
1874 var->limit = vmcs_read32(sf->limit);
1875 var->selector = vmcs_read16(sf->selector);
1876 ar = vmcs_read32(sf->ar_bytes);
1877 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1878 ar = 0;
1879 var->type = ar & 15;
1880 var->s = (ar >> 4) & 1;
1881 var->dpl = (ar >> 5) & 3;
1882 var->present = (ar >> 7) & 1;
1883 var->avl = (ar >> 12) & 1;
1884 var->l = (ar >> 13) & 1;
1885 var->db = (ar >> 14) & 1;
1886 var->g = (ar >> 15) & 1;
1887 var->unusable = (ar >> 16) & 1;
1888 }
1889
1890 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1891 {
1892 if (!is_protmode(vcpu))
1893 return 0;
1894
1895 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1896 return 3;
1897
1898 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1899 }
1900
1901 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1902 {
1903 u32 ar;
1904
1905 if (var->unusable)
1906 ar = 1 << 16;
1907 else {
1908 ar = var->type & 15;
1909 ar |= (var->s & 1) << 4;
1910 ar |= (var->dpl & 3) << 5;
1911 ar |= (var->present & 1) << 7;
1912 ar |= (var->avl & 1) << 12;
1913 ar |= (var->l & 1) << 13;
1914 ar |= (var->db & 1) << 14;
1915 ar |= (var->g & 1) << 15;
1916 }
1917 if (ar == 0) /* a 0 value means unusable */
1918 ar = AR_UNUSABLE_MASK;
1919
1920 return ar;
1921 }
1922
1923 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1924 struct kvm_segment *var, int seg)
1925 {
1926 struct vcpu_vmx *vmx = to_vmx(vcpu);
1927 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1928 u32 ar;
1929
1930 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1931 vmx->rmode.tr.selector = var->selector;
1932 vmx->rmode.tr.base = var->base;
1933 vmx->rmode.tr.limit = var->limit;
1934 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1935 return;
1936 }
1937 vmcs_writel(sf->base, var->base);
1938 vmcs_write32(sf->limit, var->limit);
1939 vmcs_write16(sf->selector, var->selector);
1940 if (vmx->rmode.vm86_active && var->s) {
1941 /*
1942 * Hack real-mode segments into vm86 compatibility.
1943 */
1944 if (var->base == 0xffff0000 && var->selector == 0xf000)
1945 vmcs_writel(sf->base, 0xf0000);
1946 ar = 0xf3;
1947 } else
1948 ar = vmx_segment_access_rights(var);
1949
1950 /*
1951 * Fix the "Accessed" bit in AR field of segment registers for older
1952 * qemu binaries.
1953 * IA32 arch specifies that at the time of processor reset the
1954 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1955 * is setting it to 0 in the usedland code. This causes invalid guest
1956 * state vmexit when "unrestricted guest" mode is turned on.
1957 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1958 * tree. Newer qemu binaries with that qemu fix would not need this
1959 * kvm hack.
1960 */
1961 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1962 ar |= 0x1; /* Accessed */
1963
1964 vmcs_write32(sf->ar_bytes, ar);
1965 }
1966
1967 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1968 {
1969 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1970
1971 *db = (ar >> 14) & 1;
1972 *l = (ar >> 13) & 1;
1973 }
1974
1975 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1976 {
1977 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
1978 dt->address = vmcs_readl(GUEST_IDTR_BASE);
1979 }
1980
1981 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1982 {
1983 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
1984 vmcs_writel(GUEST_IDTR_BASE, dt->address);
1985 }
1986
1987 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1988 {
1989 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
1990 dt->address = vmcs_readl(GUEST_GDTR_BASE);
1991 }
1992
1993 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1994 {
1995 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
1996 vmcs_writel(GUEST_GDTR_BASE, dt->address);
1997 }
1998
1999 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2000 {
2001 struct kvm_segment var;
2002 u32 ar;
2003
2004 vmx_get_segment(vcpu, &var, seg);
2005 ar = vmx_segment_access_rights(&var);
2006
2007 if (var.base != (var.selector << 4))
2008 return false;
2009 if (var.limit != 0xffff)
2010 return false;
2011 if (ar != 0xf3)
2012 return false;
2013
2014 return true;
2015 }
2016
2017 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2018 {
2019 struct kvm_segment cs;
2020 unsigned int cs_rpl;
2021
2022 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2023 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2024
2025 if (cs.unusable)
2026 return false;
2027 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2028 return false;
2029 if (!cs.s)
2030 return false;
2031 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2032 if (cs.dpl > cs_rpl)
2033 return false;
2034 } else {
2035 if (cs.dpl != cs_rpl)
2036 return false;
2037 }
2038 if (!cs.present)
2039 return false;
2040
2041 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2042 return true;
2043 }
2044
2045 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2046 {
2047 struct kvm_segment ss;
2048 unsigned int ss_rpl;
2049
2050 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2051 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2052
2053 if (ss.unusable)
2054 return true;
2055 if (ss.type != 3 && ss.type != 7)
2056 return false;
2057 if (!ss.s)
2058 return false;
2059 if (ss.dpl != ss_rpl) /* DPL != RPL */
2060 return false;
2061 if (!ss.present)
2062 return false;
2063
2064 return true;
2065 }
2066
2067 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2068 {
2069 struct kvm_segment var;
2070 unsigned int rpl;
2071
2072 vmx_get_segment(vcpu, &var, seg);
2073 rpl = var.selector & SELECTOR_RPL_MASK;
2074
2075 if (var.unusable)
2076 return true;
2077 if (!var.s)
2078 return false;
2079 if (!var.present)
2080 return false;
2081 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2082 if (var.dpl < rpl) /* DPL < RPL */
2083 return false;
2084 }
2085
2086 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2087 * rights flags
2088 */
2089 return true;
2090 }
2091
2092 static bool tr_valid(struct kvm_vcpu *vcpu)
2093 {
2094 struct kvm_segment tr;
2095
2096 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2097
2098 if (tr.unusable)
2099 return false;
2100 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2101 return false;
2102 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2103 return false;
2104 if (!tr.present)
2105 return false;
2106
2107 return true;
2108 }
2109
2110 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2111 {
2112 struct kvm_segment ldtr;
2113
2114 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2115
2116 if (ldtr.unusable)
2117 return true;
2118 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2119 return false;
2120 if (ldtr.type != 2)
2121 return false;
2122 if (!ldtr.present)
2123 return false;
2124
2125 return true;
2126 }
2127
2128 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2129 {
2130 struct kvm_segment cs, ss;
2131
2132 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2133 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2134
2135 return ((cs.selector & SELECTOR_RPL_MASK) ==
2136 (ss.selector & SELECTOR_RPL_MASK));
2137 }
2138
2139 /*
2140 * Check if guest state is valid. Returns true if valid, false if
2141 * not.
2142 * We assume that registers are always usable
2143 */
2144 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2145 {
2146 /* real mode guest state checks */
2147 if (!is_protmode(vcpu)) {
2148 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2149 return false;
2150 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2151 return false;
2152 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2153 return false;
2154 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2155 return false;
2156 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2157 return false;
2158 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2159 return false;
2160 } else {
2161 /* protected mode guest state checks */
2162 if (!cs_ss_rpl_check(vcpu))
2163 return false;
2164 if (!code_segment_valid(vcpu))
2165 return false;
2166 if (!stack_segment_valid(vcpu))
2167 return false;
2168 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2169 return false;
2170 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2171 return false;
2172 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2173 return false;
2174 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2175 return false;
2176 if (!tr_valid(vcpu))
2177 return false;
2178 if (!ldtr_valid(vcpu))
2179 return false;
2180 }
2181 /* TODO:
2182 * - Add checks on RIP
2183 * - Add checks on RFLAGS
2184 */
2185
2186 return true;
2187 }
2188
2189 static int init_rmode_tss(struct kvm *kvm)
2190 {
2191 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2192 u16 data = 0;
2193 int ret = 0;
2194 int r;
2195
2196 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2197 if (r < 0)
2198 goto out;
2199 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2200 r = kvm_write_guest_page(kvm, fn++, &data,
2201 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2202 if (r < 0)
2203 goto out;
2204 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2205 if (r < 0)
2206 goto out;
2207 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2208 if (r < 0)
2209 goto out;
2210 data = ~0;
2211 r = kvm_write_guest_page(kvm, fn, &data,
2212 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2213 sizeof(u8));
2214 if (r < 0)
2215 goto out;
2216
2217 ret = 1;
2218 out:
2219 return ret;
2220 }
2221
2222 static int init_rmode_identity_map(struct kvm *kvm)
2223 {
2224 int i, r, ret;
2225 pfn_t identity_map_pfn;
2226 u32 tmp;
2227
2228 if (!enable_ept)
2229 return 1;
2230 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2231 printk(KERN_ERR "EPT: identity-mapping pagetable "
2232 "haven't been allocated!\n");
2233 return 0;
2234 }
2235 if (likely(kvm->arch.ept_identity_pagetable_done))
2236 return 1;
2237 ret = 0;
2238 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2239 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2240 if (r < 0)
2241 goto out;
2242 /* Set up identity-mapping pagetable for EPT in real mode */
2243 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2244 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2245 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2246 r = kvm_write_guest_page(kvm, identity_map_pfn,
2247 &tmp, i * sizeof(tmp), sizeof(tmp));
2248 if (r < 0)
2249 goto out;
2250 }
2251 kvm->arch.ept_identity_pagetable_done = true;
2252 ret = 1;
2253 out:
2254 return ret;
2255 }
2256
2257 static void seg_setup(int seg)
2258 {
2259 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2260 unsigned int ar;
2261
2262 vmcs_write16(sf->selector, 0);
2263 vmcs_writel(sf->base, 0);
2264 vmcs_write32(sf->limit, 0xffff);
2265 if (enable_unrestricted_guest) {
2266 ar = 0x93;
2267 if (seg == VCPU_SREG_CS)
2268 ar |= 0x08; /* code segment */
2269 } else
2270 ar = 0xf3;
2271
2272 vmcs_write32(sf->ar_bytes, ar);
2273 }
2274
2275 static int alloc_apic_access_page(struct kvm *kvm)
2276 {
2277 struct kvm_userspace_memory_region kvm_userspace_mem;
2278 int r = 0;
2279
2280 mutex_lock(&kvm->slots_lock);
2281 if (kvm->arch.apic_access_page)
2282 goto out;
2283 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2284 kvm_userspace_mem.flags = 0;
2285 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2286 kvm_userspace_mem.memory_size = PAGE_SIZE;
2287 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2288 if (r)
2289 goto out;
2290
2291 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2292 out:
2293 mutex_unlock(&kvm->slots_lock);
2294 return r;
2295 }
2296
2297 static int alloc_identity_pagetable(struct kvm *kvm)
2298 {
2299 struct kvm_userspace_memory_region kvm_userspace_mem;
2300 int r = 0;
2301
2302 mutex_lock(&kvm->slots_lock);
2303 if (kvm->arch.ept_identity_pagetable)
2304 goto out;
2305 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2306 kvm_userspace_mem.flags = 0;
2307 kvm_userspace_mem.guest_phys_addr =
2308 kvm->arch.ept_identity_map_addr;
2309 kvm_userspace_mem.memory_size = PAGE_SIZE;
2310 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2311 if (r)
2312 goto out;
2313
2314 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2315 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2316 out:
2317 mutex_unlock(&kvm->slots_lock);
2318 return r;
2319 }
2320
2321 static void allocate_vpid(struct vcpu_vmx *vmx)
2322 {
2323 int vpid;
2324
2325 vmx->vpid = 0;
2326 if (!enable_vpid)
2327 return;
2328 spin_lock(&vmx_vpid_lock);
2329 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2330 if (vpid < VMX_NR_VPIDS) {
2331 vmx->vpid = vpid;
2332 __set_bit(vpid, vmx_vpid_bitmap);
2333 }
2334 spin_unlock(&vmx_vpid_lock);
2335 }
2336
2337 static void free_vpid(struct vcpu_vmx *vmx)
2338 {
2339 if (!enable_vpid)
2340 return;
2341 spin_lock(&vmx_vpid_lock);
2342 if (vmx->vpid != 0)
2343 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2344 spin_unlock(&vmx_vpid_lock);
2345 }
2346
2347 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2348 {
2349 int f = sizeof(unsigned long);
2350
2351 if (!cpu_has_vmx_msr_bitmap())
2352 return;
2353
2354 /*
2355 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2356 * have the write-low and read-high bitmap offsets the wrong way round.
2357 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2358 */
2359 if (msr <= 0x1fff) {
2360 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2361 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2362 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2363 msr &= 0x1fff;
2364 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2365 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2366 }
2367 }
2368
2369 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2370 {
2371 if (!longmode_only)
2372 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2373 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2374 }
2375
2376 /*
2377 * Sets up the vmcs for emulated real mode.
2378 */
2379 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2380 {
2381 u32 host_sysenter_cs, msr_low, msr_high;
2382 u32 junk;
2383 u64 host_pat, tsc_this, tsc_base;
2384 unsigned long a;
2385 struct desc_ptr dt;
2386 int i;
2387 unsigned long kvm_vmx_return;
2388 u32 exec_control;
2389
2390 /* I/O */
2391 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2392 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2393
2394 if (cpu_has_vmx_msr_bitmap())
2395 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2396
2397 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2398
2399 /* Control */
2400 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2401 vmcs_config.pin_based_exec_ctrl);
2402
2403 exec_control = vmcs_config.cpu_based_exec_ctrl;
2404 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2405 exec_control &= ~CPU_BASED_TPR_SHADOW;
2406 #ifdef CONFIG_X86_64
2407 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2408 CPU_BASED_CR8_LOAD_EXITING;
2409 #endif
2410 }
2411 if (!enable_ept)
2412 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2413 CPU_BASED_CR3_LOAD_EXITING |
2414 CPU_BASED_INVLPG_EXITING;
2415 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2416
2417 if (cpu_has_secondary_exec_ctrls()) {
2418 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2419 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2420 exec_control &=
2421 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2422 if (vmx->vpid == 0)
2423 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2424 if (!enable_ept) {
2425 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2426 enable_unrestricted_guest = 0;
2427 }
2428 if (!enable_unrestricted_guest)
2429 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2430 if (!ple_gap)
2431 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2432 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2433 }
2434
2435 if (ple_gap) {
2436 vmcs_write32(PLE_GAP, ple_gap);
2437 vmcs_write32(PLE_WINDOW, ple_window);
2438 }
2439
2440 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2441 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2442 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2443
2444 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2445 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2446 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2447
2448 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2449 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2450 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2451 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2452 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2453 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2454 #ifdef CONFIG_X86_64
2455 rdmsrl(MSR_FS_BASE, a);
2456 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2457 rdmsrl(MSR_GS_BASE, a);
2458 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2459 #else
2460 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2461 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2462 #endif
2463
2464 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2465
2466 native_store_idt(&dt);
2467 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2468
2469 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2470 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2471 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2472 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2473 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2474
2475 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2476 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2477 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2478 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2479 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2480 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2481
2482 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2483 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2484 host_pat = msr_low | ((u64) msr_high << 32);
2485 vmcs_write64(HOST_IA32_PAT, host_pat);
2486 }
2487 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2488 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2489 host_pat = msr_low | ((u64) msr_high << 32);
2490 /* Write the default value follow host pat */
2491 vmcs_write64(GUEST_IA32_PAT, host_pat);
2492 /* Keep arch.pat sync with GUEST_IA32_PAT */
2493 vmx->vcpu.arch.pat = host_pat;
2494 }
2495
2496 for (i = 0; i < NR_VMX_MSR; ++i) {
2497 u32 index = vmx_msr_index[i];
2498 u32 data_low, data_high;
2499 int j = vmx->nmsrs;
2500
2501 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2502 continue;
2503 if (wrmsr_safe(index, data_low, data_high) < 0)
2504 continue;
2505 vmx->guest_msrs[j].index = i;
2506 vmx->guest_msrs[j].data = 0;
2507 vmx->guest_msrs[j].mask = -1ull;
2508 ++vmx->nmsrs;
2509 }
2510
2511 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2512
2513 /* 22.2.1, 20.8.1 */
2514 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2515
2516 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2517 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2518 if (enable_ept)
2519 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2520 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2521
2522 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2523 rdtscll(tsc_this);
2524 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2525 tsc_base = tsc_this;
2526
2527 guest_write_tsc(0, tsc_base);
2528
2529 return 0;
2530 }
2531
2532 static int init_rmode(struct kvm *kvm)
2533 {
2534 if (!init_rmode_tss(kvm))
2535 return 0;
2536 if (!init_rmode_identity_map(kvm))
2537 return 0;
2538 return 1;
2539 }
2540
2541 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2542 {
2543 struct vcpu_vmx *vmx = to_vmx(vcpu);
2544 u64 msr;
2545 int ret, idx;
2546
2547 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2548 idx = srcu_read_lock(&vcpu->kvm->srcu);
2549 if (!init_rmode(vmx->vcpu.kvm)) {
2550 ret = -ENOMEM;
2551 goto out;
2552 }
2553
2554 vmx->rmode.vm86_active = 0;
2555
2556 vmx->soft_vnmi_blocked = 0;
2557
2558 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2559 kvm_set_cr8(&vmx->vcpu, 0);
2560 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2561 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2562 msr |= MSR_IA32_APICBASE_BSP;
2563 kvm_set_apic_base(&vmx->vcpu, msr);
2564
2565 fx_init(&vmx->vcpu);
2566
2567 seg_setup(VCPU_SREG_CS);
2568 /*
2569 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2570 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2571 */
2572 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2573 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2574 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2575 } else {
2576 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2577 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2578 }
2579
2580 seg_setup(VCPU_SREG_DS);
2581 seg_setup(VCPU_SREG_ES);
2582 seg_setup(VCPU_SREG_FS);
2583 seg_setup(VCPU_SREG_GS);
2584 seg_setup(VCPU_SREG_SS);
2585
2586 vmcs_write16(GUEST_TR_SELECTOR, 0);
2587 vmcs_writel(GUEST_TR_BASE, 0);
2588 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2589 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2590
2591 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2592 vmcs_writel(GUEST_LDTR_BASE, 0);
2593 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2594 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2595
2596 vmcs_write32(GUEST_SYSENTER_CS, 0);
2597 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2598 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2599
2600 vmcs_writel(GUEST_RFLAGS, 0x02);
2601 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2602 kvm_rip_write(vcpu, 0xfff0);
2603 else
2604 kvm_rip_write(vcpu, 0);
2605 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2606
2607 vmcs_writel(GUEST_DR7, 0x400);
2608
2609 vmcs_writel(GUEST_GDTR_BASE, 0);
2610 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2611
2612 vmcs_writel(GUEST_IDTR_BASE, 0);
2613 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2614
2615 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2616 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2617 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2618
2619 /* Special registers */
2620 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2621
2622 setup_msrs(vmx);
2623
2624 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2625
2626 if (cpu_has_vmx_tpr_shadow()) {
2627 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2628 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2629 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2630 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2631 vmcs_write32(TPR_THRESHOLD, 0);
2632 }
2633
2634 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2635 vmcs_write64(APIC_ACCESS_ADDR,
2636 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2637
2638 if (vmx->vpid != 0)
2639 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2640
2641 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2642 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2643 vmx_set_cr4(&vmx->vcpu, 0);
2644 vmx_set_efer(&vmx->vcpu, 0);
2645 vmx_fpu_activate(&vmx->vcpu);
2646 update_exception_bitmap(&vmx->vcpu);
2647
2648 vpid_sync_vcpu_all(vmx);
2649
2650 ret = 0;
2651
2652 /* HACK: Don't enable emulation on guest boot/reset */
2653 vmx->emulation_required = 0;
2654
2655 out:
2656 srcu_read_unlock(&vcpu->kvm->srcu, idx);
2657 return ret;
2658 }
2659
2660 static void enable_irq_window(struct kvm_vcpu *vcpu)
2661 {
2662 u32 cpu_based_vm_exec_control;
2663
2664 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2665 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2666 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2667 }
2668
2669 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2670 {
2671 u32 cpu_based_vm_exec_control;
2672
2673 if (!cpu_has_virtual_nmis()) {
2674 enable_irq_window(vcpu);
2675 return;
2676 }
2677
2678 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2679 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2680 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2681 }
2682
2683 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2684 {
2685 struct vcpu_vmx *vmx = to_vmx(vcpu);
2686 uint32_t intr;
2687 int irq = vcpu->arch.interrupt.nr;
2688
2689 trace_kvm_inj_virq(irq);
2690
2691 ++vcpu->stat.irq_injections;
2692 if (vmx->rmode.vm86_active) {
2693 vmx->rmode.irq.pending = true;
2694 vmx->rmode.irq.vector = irq;
2695 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2696 if (vcpu->arch.interrupt.soft)
2697 vmx->rmode.irq.rip +=
2698 vmx->vcpu.arch.event_exit_inst_len;
2699 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2700 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2701 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2702 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2703 return;
2704 }
2705 intr = irq | INTR_INFO_VALID_MASK;
2706 if (vcpu->arch.interrupt.soft) {
2707 intr |= INTR_TYPE_SOFT_INTR;
2708 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2709 vmx->vcpu.arch.event_exit_inst_len);
2710 } else
2711 intr |= INTR_TYPE_EXT_INTR;
2712 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2713 }
2714
2715 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2716 {
2717 struct vcpu_vmx *vmx = to_vmx(vcpu);
2718
2719 if (!cpu_has_virtual_nmis()) {
2720 /*
2721 * Tracking the NMI-blocked state in software is built upon
2722 * finding the next open IRQ window. This, in turn, depends on
2723 * well-behaving guests: They have to keep IRQs disabled at
2724 * least as long as the NMI handler runs. Otherwise we may
2725 * cause NMI nesting, maybe breaking the guest. But as this is
2726 * highly unlikely, we can live with the residual risk.
2727 */
2728 vmx->soft_vnmi_blocked = 1;
2729 vmx->vnmi_blocked_time = 0;
2730 }
2731
2732 ++vcpu->stat.nmi_injections;
2733 if (vmx->rmode.vm86_active) {
2734 vmx->rmode.irq.pending = true;
2735 vmx->rmode.irq.vector = NMI_VECTOR;
2736 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2737 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2738 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2739 INTR_INFO_VALID_MASK);
2740 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2741 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2742 return;
2743 }
2744 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2745 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2746 }
2747
2748 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2749 {
2750 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2751 return 0;
2752
2753 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2754 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2755 GUEST_INTR_STATE_NMI));
2756 }
2757
2758 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2759 {
2760 if (!cpu_has_virtual_nmis())
2761 return to_vmx(vcpu)->soft_vnmi_blocked;
2762 else
2763 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2764 GUEST_INTR_STATE_NMI);
2765 }
2766
2767 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2768 {
2769 struct vcpu_vmx *vmx = to_vmx(vcpu);
2770
2771 if (!cpu_has_virtual_nmis()) {
2772 if (vmx->soft_vnmi_blocked != masked) {
2773 vmx->soft_vnmi_blocked = masked;
2774 vmx->vnmi_blocked_time = 0;
2775 }
2776 } else {
2777 if (masked)
2778 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2779 GUEST_INTR_STATE_NMI);
2780 else
2781 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2782 GUEST_INTR_STATE_NMI);
2783 }
2784 }
2785
2786 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2787 {
2788 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2789 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2790 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2791 }
2792
2793 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2794 {
2795 int ret;
2796 struct kvm_userspace_memory_region tss_mem = {
2797 .slot = TSS_PRIVATE_MEMSLOT,
2798 .guest_phys_addr = addr,
2799 .memory_size = PAGE_SIZE * 3,
2800 .flags = 0,
2801 };
2802
2803 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2804 if (ret)
2805 return ret;
2806 kvm->arch.tss_addr = addr;
2807 return 0;
2808 }
2809
2810 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2811 int vec, u32 err_code)
2812 {
2813 /*
2814 * Instruction with address size override prefix opcode 0x67
2815 * Cause the #SS fault with 0 error code in VM86 mode.
2816 */
2817 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2818 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2819 return 1;
2820 /*
2821 * Forward all other exceptions that are valid in real mode.
2822 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2823 * the required debugging infrastructure rework.
2824 */
2825 switch (vec) {
2826 case DB_VECTOR:
2827 if (vcpu->guest_debug &
2828 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2829 return 0;
2830 kvm_queue_exception(vcpu, vec);
2831 return 1;
2832 case BP_VECTOR:
2833 /*
2834 * Update instruction length as we may reinject the exception
2835 * from user space while in guest debugging mode.
2836 */
2837 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2838 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2839 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2840 return 0;
2841 /* fall through */
2842 case DE_VECTOR:
2843 case OF_VECTOR:
2844 case BR_VECTOR:
2845 case UD_VECTOR:
2846 case DF_VECTOR:
2847 case SS_VECTOR:
2848 case GP_VECTOR:
2849 case MF_VECTOR:
2850 kvm_queue_exception(vcpu, vec);
2851 return 1;
2852 }
2853 return 0;
2854 }
2855
2856 /*
2857 * Trigger machine check on the host. We assume all the MSRs are already set up
2858 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2859 * We pass a fake environment to the machine check handler because we want
2860 * the guest to be always treated like user space, no matter what context
2861 * it used internally.
2862 */
2863 static void kvm_machine_check(void)
2864 {
2865 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2866 struct pt_regs regs = {
2867 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2868 .flags = X86_EFLAGS_IF,
2869 };
2870
2871 do_machine_check(&regs, 0);
2872 #endif
2873 }
2874
2875 static int handle_machine_check(struct kvm_vcpu *vcpu)
2876 {
2877 /* already handled by vcpu_run */
2878 return 1;
2879 }
2880
2881 static int handle_exception(struct kvm_vcpu *vcpu)
2882 {
2883 struct vcpu_vmx *vmx = to_vmx(vcpu);
2884 struct kvm_run *kvm_run = vcpu->run;
2885 u32 intr_info, ex_no, error_code;
2886 unsigned long cr2, rip, dr6;
2887 u32 vect_info;
2888 enum emulation_result er;
2889
2890 vect_info = vmx->idt_vectoring_info;
2891 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2892
2893 if (is_machine_check(intr_info))
2894 return handle_machine_check(vcpu);
2895
2896 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2897 !is_page_fault(intr_info)) {
2898 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2899 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2900 vcpu->run->internal.ndata = 2;
2901 vcpu->run->internal.data[0] = vect_info;
2902 vcpu->run->internal.data[1] = intr_info;
2903 return 0;
2904 }
2905
2906 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2907 return 1; /* already handled by vmx_vcpu_run() */
2908
2909 if (is_no_device(intr_info)) {
2910 vmx_fpu_activate(vcpu);
2911 return 1;
2912 }
2913
2914 if (is_invalid_opcode(intr_info)) {
2915 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2916 if (er != EMULATE_DONE)
2917 kvm_queue_exception(vcpu, UD_VECTOR);
2918 return 1;
2919 }
2920
2921 error_code = 0;
2922 rip = kvm_rip_read(vcpu);
2923 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2924 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2925 if (is_page_fault(intr_info)) {
2926 /* EPT won't cause page fault directly */
2927 if (enable_ept)
2928 BUG();
2929 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2930 trace_kvm_page_fault(cr2, error_code);
2931
2932 if (kvm_event_needs_reinjection(vcpu))
2933 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2934 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2935 }
2936
2937 if (vmx->rmode.vm86_active &&
2938 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2939 error_code)) {
2940 if (vcpu->arch.halt_request) {
2941 vcpu->arch.halt_request = 0;
2942 return kvm_emulate_halt(vcpu);
2943 }
2944 return 1;
2945 }
2946
2947 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2948 switch (ex_no) {
2949 case DB_VECTOR:
2950 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2951 if (!(vcpu->guest_debug &
2952 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2953 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2954 kvm_queue_exception(vcpu, DB_VECTOR);
2955 return 1;
2956 }
2957 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2958 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2959 /* fall through */
2960 case BP_VECTOR:
2961 /*
2962 * Update instruction length as we may reinject #BP from
2963 * user space while in guest debugging mode. Reading it for
2964 * #DB as well causes no harm, it is not used in that case.
2965 */
2966 vmx->vcpu.arch.event_exit_inst_len =
2967 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2968 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2969 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2970 kvm_run->debug.arch.exception = ex_no;
2971 break;
2972 default:
2973 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2974 kvm_run->ex.exception = ex_no;
2975 kvm_run->ex.error_code = error_code;
2976 break;
2977 }
2978 return 0;
2979 }
2980
2981 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
2982 {
2983 ++vcpu->stat.irq_exits;
2984 return 1;
2985 }
2986
2987 static int handle_triple_fault(struct kvm_vcpu *vcpu)
2988 {
2989 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
2990 return 0;
2991 }
2992
2993 static int handle_io(struct kvm_vcpu *vcpu)
2994 {
2995 unsigned long exit_qualification;
2996 int size, in, string;
2997 unsigned port;
2998
2999 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3000 string = (exit_qualification & 16) != 0;
3001 in = (exit_qualification & 8) != 0;
3002
3003 ++vcpu->stat.io_exits;
3004
3005 if (string || in)
3006 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
3007
3008 port = exit_qualification >> 16;
3009 size = (exit_qualification & 7) + 1;
3010 skip_emulated_instruction(vcpu);
3011
3012 return kvm_fast_pio_out(vcpu, size, port);
3013 }
3014
3015 static void
3016 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3017 {
3018 /*
3019 * Patch in the VMCALL instruction:
3020 */
3021 hypercall[0] = 0x0f;
3022 hypercall[1] = 0x01;
3023 hypercall[2] = 0xc1;
3024 }
3025
3026 static int handle_cr(struct kvm_vcpu *vcpu)
3027 {
3028 unsigned long exit_qualification, val;
3029 int cr;
3030 int reg;
3031
3032 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3033 cr = exit_qualification & 15;
3034 reg = (exit_qualification >> 8) & 15;
3035 switch ((exit_qualification >> 4) & 3) {
3036 case 0: /* mov to cr */
3037 val = kvm_register_read(vcpu, reg);
3038 trace_kvm_cr_write(cr, val);
3039 switch (cr) {
3040 case 0:
3041 kvm_set_cr0(vcpu, val);
3042 skip_emulated_instruction(vcpu);
3043 return 1;
3044 case 3:
3045 kvm_set_cr3(vcpu, val);
3046 skip_emulated_instruction(vcpu);
3047 return 1;
3048 case 4:
3049 kvm_set_cr4(vcpu, val);
3050 skip_emulated_instruction(vcpu);
3051 return 1;
3052 case 8: {
3053 u8 cr8_prev = kvm_get_cr8(vcpu);
3054 u8 cr8 = kvm_register_read(vcpu, reg);
3055 kvm_set_cr8(vcpu, cr8);
3056 skip_emulated_instruction(vcpu);
3057 if (irqchip_in_kernel(vcpu->kvm))
3058 return 1;
3059 if (cr8_prev <= cr8)
3060 return 1;
3061 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3062 return 0;
3063 }
3064 };
3065 break;
3066 case 2: /* clts */
3067 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3068 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3069 skip_emulated_instruction(vcpu);
3070 vmx_fpu_activate(vcpu);
3071 return 1;
3072 case 1: /*mov from cr*/
3073 switch (cr) {
3074 case 3:
3075 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3076 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3077 skip_emulated_instruction(vcpu);
3078 return 1;
3079 case 8:
3080 val = kvm_get_cr8(vcpu);
3081 kvm_register_write(vcpu, reg, val);
3082 trace_kvm_cr_read(cr, val);
3083 skip_emulated_instruction(vcpu);
3084 return 1;
3085 }
3086 break;
3087 case 3: /* lmsw */
3088 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3089 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3090 kvm_lmsw(vcpu, val);
3091
3092 skip_emulated_instruction(vcpu);
3093 return 1;
3094 default:
3095 break;
3096 }
3097 vcpu->run->exit_reason = 0;
3098 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3099 (int)(exit_qualification >> 4) & 3, cr);
3100 return 0;
3101 }
3102
3103 static int handle_dr(struct kvm_vcpu *vcpu)
3104 {
3105 unsigned long exit_qualification;
3106 int dr, reg;
3107
3108 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3109 if (!kvm_require_cpl(vcpu, 0))
3110 return 1;
3111 dr = vmcs_readl(GUEST_DR7);
3112 if (dr & DR7_GD) {
3113 /*
3114 * As the vm-exit takes precedence over the debug trap, we
3115 * need to emulate the latter, either for the host or the
3116 * guest debugging itself.
3117 */
3118 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3119 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3120 vcpu->run->debug.arch.dr7 = dr;
3121 vcpu->run->debug.arch.pc =
3122 vmcs_readl(GUEST_CS_BASE) +
3123 vmcs_readl(GUEST_RIP);
3124 vcpu->run->debug.arch.exception = DB_VECTOR;
3125 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3126 return 0;
3127 } else {
3128 vcpu->arch.dr7 &= ~DR7_GD;
3129 vcpu->arch.dr6 |= DR6_BD;
3130 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3131 kvm_queue_exception(vcpu, DB_VECTOR);
3132 return 1;
3133 }
3134 }
3135
3136 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3137 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3138 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3139 if (exit_qualification & TYPE_MOV_FROM_DR) {
3140 unsigned long val;
3141 if (!kvm_get_dr(vcpu, dr, &val))
3142 kvm_register_write(vcpu, reg, val);
3143 } else
3144 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3145 skip_emulated_instruction(vcpu);
3146 return 1;
3147 }
3148
3149 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3150 {
3151 vmcs_writel(GUEST_DR7, val);
3152 }
3153
3154 static int handle_cpuid(struct kvm_vcpu *vcpu)
3155 {
3156 kvm_emulate_cpuid(vcpu);
3157 return 1;
3158 }
3159
3160 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3161 {
3162 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3163 u64 data;
3164
3165 if (vmx_get_msr(vcpu, ecx, &data)) {
3166 trace_kvm_msr_read_ex(ecx);
3167 kvm_inject_gp(vcpu, 0);
3168 return 1;
3169 }
3170
3171 trace_kvm_msr_read(ecx, data);
3172
3173 /* FIXME: handling of bits 32:63 of rax, rdx */
3174 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3175 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3176 skip_emulated_instruction(vcpu);
3177 return 1;
3178 }
3179
3180 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3181 {
3182 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3183 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3184 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3185
3186 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3187 trace_kvm_msr_write_ex(ecx, data);
3188 kvm_inject_gp(vcpu, 0);
3189 return 1;
3190 }
3191
3192 trace_kvm_msr_write(ecx, data);
3193 skip_emulated_instruction(vcpu);
3194 return 1;
3195 }
3196
3197 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3198 {
3199 return 1;
3200 }
3201
3202 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3203 {
3204 u32 cpu_based_vm_exec_control;
3205
3206 /* clear pending irq */
3207 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3208 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3209 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3210
3211 ++vcpu->stat.irq_window_exits;
3212
3213 /*
3214 * If the user space waits to inject interrupts, exit as soon as
3215 * possible
3216 */
3217 if (!irqchip_in_kernel(vcpu->kvm) &&
3218 vcpu->run->request_interrupt_window &&
3219 !kvm_cpu_has_interrupt(vcpu)) {
3220 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3221 return 0;
3222 }
3223 return 1;
3224 }
3225
3226 static int handle_halt(struct kvm_vcpu *vcpu)
3227 {
3228 skip_emulated_instruction(vcpu);
3229 return kvm_emulate_halt(vcpu);
3230 }
3231
3232 static int handle_vmcall(struct kvm_vcpu *vcpu)
3233 {
3234 skip_emulated_instruction(vcpu);
3235 kvm_emulate_hypercall(vcpu);
3236 return 1;
3237 }
3238
3239 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3240 {
3241 kvm_queue_exception(vcpu, UD_VECTOR);
3242 return 1;
3243 }
3244
3245 static int handle_invlpg(struct kvm_vcpu *vcpu)
3246 {
3247 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3248
3249 kvm_mmu_invlpg(vcpu, exit_qualification);
3250 skip_emulated_instruction(vcpu);
3251 return 1;
3252 }
3253
3254 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3255 {
3256 skip_emulated_instruction(vcpu);
3257 /* TODO: Add support for VT-d/pass-through device */
3258 return 1;
3259 }
3260
3261 static int handle_apic_access(struct kvm_vcpu *vcpu)
3262 {
3263 unsigned long exit_qualification;
3264 enum emulation_result er;
3265 unsigned long offset;
3266
3267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3268 offset = exit_qualification & 0xffful;
3269
3270 er = emulate_instruction(vcpu, 0, 0, 0);
3271
3272 if (er != EMULATE_DONE) {
3273 printk(KERN_ERR
3274 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3275 offset);
3276 return -ENOEXEC;
3277 }
3278 return 1;
3279 }
3280
3281 static int handle_task_switch(struct kvm_vcpu *vcpu)
3282 {
3283 struct vcpu_vmx *vmx = to_vmx(vcpu);
3284 unsigned long exit_qualification;
3285 bool has_error_code = false;
3286 u32 error_code = 0;
3287 u16 tss_selector;
3288 int reason, type, idt_v;
3289
3290 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3291 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3292
3293 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3294
3295 reason = (u32)exit_qualification >> 30;
3296 if (reason == TASK_SWITCH_GATE && idt_v) {
3297 switch (type) {
3298 case INTR_TYPE_NMI_INTR:
3299 vcpu->arch.nmi_injected = false;
3300 if (cpu_has_virtual_nmis())
3301 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3302 GUEST_INTR_STATE_NMI);
3303 break;
3304 case INTR_TYPE_EXT_INTR:
3305 case INTR_TYPE_SOFT_INTR:
3306 kvm_clear_interrupt_queue(vcpu);
3307 break;
3308 case INTR_TYPE_HARD_EXCEPTION:
3309 if (vmx->idt_vectoring_info &
3310 VECTORING_INFO_DELIVER_CODE_MASK) {
3311 has_error_code = true;
3312 error_code =
3313 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3314 }
3315 /* fall through */
3316 case INTR_TYPE_SOFT_EXCEPTION:
3317 kvm_clear_exception_queue(vcpu);
3318 break;
3319 default:
3320 break;
3321 }
3322 }
3323 tss_selector = exit_qualification;
3324
3325 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3326 type != INTR_TYPE_EXT_INTR &&
3327 type != INTR_TYPE_NMI_INTR))
3328 skip_emulated_instruction(vcpu);
3329
3330 if (kvm_task_switch(vcpu, tss_selector, reason,
3331 has_error_code, error_code) == EMULATE_FAIL) {
3332 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3333 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3334 vcpu->run->internal.ndata = 0;
3335 return 0;
3336 }
3337
3338 /* clear all local breakpoint enable flags */
3339 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3340
3341 /*
3342 * TODO: What about debug traps on tss switch?
3343 * Are we supposed to inject them and update dr6?
3344 */
3345
3346 return 1;
3347 }
3348
3349 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3350 {
3351 unsigned long exit_qualification;
3352 gpa_t gpa;
3353 int gla_validity;
3354
3355 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3356
3357 if (exit_qualification & (1 << 6)) {
3358 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3359 return -EINVAL;
3360 }
3361
3362 gla_validity = (exit_qualification >> 7) & 0x3;
3363 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3364 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3365 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3366 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3367 vmcs_readl(GUEST_LINEAR_ADDRESS));
3368 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3369 (long unsigned int)exit_qualification);
3370 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3371 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3372 return 0;
3373 }
3374
3375 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3376 trace_kvm_page_fault(gpa, exit_qualification);
3377 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3378 }
3379
3380 static u64 ept_rsvd_mask(u64 spte, int level)
3381 {
3382 int i;
3383 u64 mask = 0;
3384
3385 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3386 mask |= (1ULL << i);
3387
3388 if (level > 2)
3389 /* bits 7:3 reserved */
3390 mask |= 0xf8;
3391 else if (level == 2) {
3392 if (spte & (1ULL << 7))
3393 /* 2MB ref, bits 20:12 reserved */
3394 mask |= 0x1ff000;
3395 else
3396 /* bits 6:3 reserved */
3397 mask |= 0x78;
3398 }
3399
3400 return mask;
3401 }
3402
3403 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3404 int level)
3405 {
3406 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3407
3408 /* 010b (write-only) */
3409 WARN_ON((spte & 0x7) == 0x2);
3410
3411 /* 110b (write/execute) */
3412 WARN_ON((spte & 0x7) == 0x6);
3413
3414 /* 100b (execute-only) and value not supported by logical processor */
3415 if (!cpu_has_vmx_ept_execute_only())
3416 WARN_ON((spte & 0x7) == 0x4);
3417
3418 /* not 000b */
3419 if ((spte & 0x7)) {
3420 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3421
3422 if (rsvd_bits != 0) {
3423 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3424 __func__, rsvd_bits);
3425 WARN_ON(1);
3426 }
3427
3428 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3429 u64 ept_mem_type = (spte & 0x38) >> 3;
3430
3431 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3432 ept_mem_type == 7) {
3433 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3434 __func__, ept_mem_type);
3435 WARN_ON(1);
3436 }
3437 }
3438 }
3439 }
3440
3441 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3442 {
3443 u64 sptes[4];
3444 int nr_sptes, i;
3445 gpa_t gpa;
3446
3447 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3448
3449 printk(KERN_ERR "EPT: Misconfiguration.\n");
3450 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3451
3452 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3453
3454 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3455 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3456
3457 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3458 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3459
3460 return 0;
3461 }
3462
3463 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3464 {
3465 u32 cpu_based_vm_exec_control;
3466
3467 /* clear pending NMI */
3468 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3469 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3470 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3471 ++vcpu->stat.nmi_window_exits;
3472
3473 return 1;
3474 }
3475
3476 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3477 {
3478 struct vcpu_vmx *vmx = to_vmx(vcpu);
3479 enum emulation_result err = EMULATE_DONE;
3480 int ret = 1;
3481
3482 while (!guest_state_valid(vcpu)) {
3483 err = emulate_instruction(vcpu, 0, 0, 0);
3484
3485 if (err == EMULATE_DO_MMIO) {
3486 ret = 0;
3487 goto out;
3488 }
3489
3490 if (err != EMULATE_DONE) {
3491 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3492 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3493 vcpu->run->internal.ndata = 0;
3494 ret = 0;
3495 goto out;
3496 }
3497
3498 if (signal_pending(current))
3499 goto out;
3500 if (need_resched())
3501 schedule();
3502 }
3503
3504 vmx->emulation_required = 0;
3505 out:
3506 return ret;
3507 }
3508
3509 /*
3510 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3511 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3512 */
3513 static int handle_pause(struct kvm_vcpu *vcpu)
3514 {
3515 skip_emulated_instruction(vcpu);
3516 kvm_vcpu_on_spin(vcpu);
3517
3518 return 1;
3519 }
3520
3521 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3522 {
3523 kvm_queue_exception(vcpu, UD_VECTOR);
3524 return 1;
3525 }
3526
3527 /*
3528 * The exit handlers return 1 if the exit was handled fully and guest execution
3529 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3530 * to be done to userspace and return 0.
3531 */
3532 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3533 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3534 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3535 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3536 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3537 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3538 [EXIT_REASON_CR_ACCESS] = handle_cr,
3539 [EXIT_REASON_DR_ACCESS] = handle_dr,
3540 [EXIT_REASON_CPUID] = handle_cpuid,
3541 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3542 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3543 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3544 [EXIT_REASON_HLT] = handle_halt,
3545 [EXIT_REASON_INVLPG] = handle_invlpg,
3546 [EXIT_REASON_VMCALL] = handle_vmcall,
3547 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3548 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3549 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3550 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3551 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3552 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3553 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3554 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3555 [EXIT_REASON_VMON] = handle_vmx_insn,
3556 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3557 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3558 [EXIT_REASON_WBINVD] = handle_wbinvd,
3559 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3560 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3561 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3562 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3563 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3564 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3565 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3566 };
3567
3568 static const int kvm_vmx_max_exit_handlers =
3569 ARRAY_SIZE(kvm_vmx_exit_handlers);
3570
3571 /*
3572 * The guest has exited. See if we can fix it or if we need userspace
3573 * assistance.
3574 */
3575 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3576 {
3577 struct vcpu_vmx *vmx = to_vmx(vcpu);
3578 u32 exit_reason = vmx->exit_reason;
3579 u32 vectoring_info = vmx->idt_vectoring_info;
3580
3581 trace_kvm_exit(exit_reason, vcpu);
3582
3583 /* If guest state is invalid, start emulating */
3584 if (vmx->emulation_required && emulate_invalid_guest_state)
3585 return handle_invalid_guest_state(vcpu);
3586
3587 /* Access CR3 don't cause VMExit in paging mode, so we need
3588 * to sync with guest real CR3. */
3589 if (enable_ept && is_paging(vcpu))
3590 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3591
3592 if (unlikely(vmx->fail)) {
3593 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3594 vcpu->run->fail_entry.hardware_entry_failure_reason
3595 = vmcs_read32(VM_INSTRUCTION_ERROR);
3596 return 0;
3597 }
3598
3599 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3600 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3601 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3602 exit_reason != EXIT_REASON_TASK_SWITCH))
3603 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3604 "(0x%x) and exit reason is 0x%x\n",
3605 __func__, vectoring_info, exit_reason);
3606
3607 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3608 if (vmx_interrupt_allowed(vcpu)) {
3609 vmx->soft_vnmi_blocked = 0;
3610 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3611 vcpu->arch.nmi_pending) {
3612 /*
3613 * This CPU don't support us in finding the end of an
3614 * NMI-blocked window if the guest runs with IRQs
3615 * disabled. So we pull the trigger after 1 s of
3616 * futile waiting, but inform the user about this.
3617 */
3618 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3619 "state on VCPU %d after 1 s timeout\n",
3620 __func__, vcpu->vcpu_id);
3621 vmx->soft_vnmi_blocked = 0;
3622 }
3623 }
3624
3625 if (exit_reason < kvm_vmx_max_exit_handlers
3626 && kvm_vmx_exit_handlers[exit_reason])
3627 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3628 else {
3629 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3630 vcpu->run->hw.hardware_exit_reason = exit_reason;
3631 }
3632 return 0;
3633 }
3634
3635 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3636 {
3637 if (irr == -1 || tpr < irr) {
3638 vmcs_write32(TPR_THRESHOLD, 0);
3639 return;
3640 }
3641
3642 vmcs_write32(TPR_THRESHOLD, irr);
3643 }
3644
3645 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3646 {
3647 u32 exit_intr_info;
3648 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3649 bool unblock_nmi;
3650 u8 vector;
3651 int type;
3652 bool idtv_info_valid;
3653
3654 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3655
3656 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3657
3658 /* Handle machine checks before interrupts are enabled */
3659 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3660 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3661 && is_machine_check(exit_intr_info)))
3662 kvm_machine_check();
3663
3664 /* We need to handle NMIs before interrupts are enabled */
3665 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3666 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3667 kvm_before_handle_nmi(&vmx->vcpu);
3668 asm("int $2");
3669 kvm_after_handle_nmi(&vmx->vcpu);
3670 }
3671
3672 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3673
3674 if (cpu_has_virtual_nmis()) {
3675 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3676 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3677 /*
3678 * SDM 3: 27.7.1.2 (September 2008)
3679 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3680 * a guest IRET fault.
3681 * SDM 3: 23.2.2 (September 2008)
3682 * Bit 12 is undefined in any of the following cases:
3683 * If the VM exit sets the valid bit in the IDT-vectoring
3684 * information field.
3685 * If the VM exit is due to a double fault.
3686 */
3687 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3688 vector != DF_VECTOR && !idtv_info_valid)
3689 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3690 GUEST_INTR_STATE_NMI);
3691 } else if (unlikely(vmx->soft_vnmi_blocked))
3692 vmx->vnmi_blocked_time +=
3693 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3694
3695 vmx->vcpu.arch.nmi_injected = false;
3696 kvm_clear_exception_queue(&vmx->vcpu);
3697 kvm_clear_interrupt_queue(&vmx->vcpu);
3698
3699 if (!idtv_info_valid)
3700 return;
3701
3702 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3703 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3704
3705 switch (type) {
3706 case INTR_TYPE_NMI_INTR:
3707 vmx->vcpu.arch.nmi_injected = true;
3708 /*
3709 * SDM 3: 27.7.1.2 (September 2008)
3710 * Clear bit "block by NMI" before VM entry if a NMI
3711 * delivery faulted.
3712 */
3713 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3714 GUEST_INTR_STATE_NMI);
3715 break;
3716 case INTR_TYPE_SOFT_EXCEPTION:
3717 vmx->vcpu.arch.event_exit_inst_len =
3718 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3719 /* fall through */
3720 case INTR_TYPE_HARD_EXCEPTION:
3721 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3722 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3723 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3724 } else
3725 kvm_queue_exception(&vmx->vcpu, vector);
3726 break;
3727 case INTR_TYPE_SOFT_INTR:
3728 vmx->vcpu.arch.event_exit_inst_len =
3729 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3730 /* fall through */
3731 case INTR_TYPE_EXT_INTR:
3732 kvm_queue_interrupt(&vmx->vcpu, vector,
3733 type == INTR_TYPE_SOFT_INTR);
3734 break;
3735 default:
3736 break;
3737 }
3738 }
3739
3740 /*
3741 * Failure to inject an interrupt should give us the information
3742 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3743 * when fetching the interrupt redirection bitmap in the real-mode
3744 * tss, this doesn't happen. So we do it ourselves.
3745 */
3746 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3747 {
3748 vmx->rmode.irq.pending = 0;
3749 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3750 return;
3751 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3752 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3753 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3754 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3755 return;
3756 }
3757 vmx->idt_vectoring_info =
3758 VECTORING_INFO_VALID_MASK
3759 | INTR_TYPE_EXT_INTR
3760 | vmx->rmode.irq.vector;
3761 }
3762
3763 #ifdef CONFIG_X86_64
3764 #define R "r"
3765 #define Q "q"
3766 #else
3767 #define R "e"
3768 #define Q "l"
3769 #endif
3770
3771 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3772 {
3773 struct vcpu_vmx *vmx = to_vmx(vcpu);
3774
3775 /* Record the guest's net vcpu time for enforced NMI injections. */
3776 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3777 vmx->entry_time = ktime_get();
3778
3779 /* Don't enter VMX if guest state is invalid, let the exit handler
3780 start emulation until we arrive back to a valid state */
3781 if (vmx->emulation_required && emulate_invalid_guest_state)
3782 return;
3783
3784 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3785 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3786 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3787 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3788
3789 /* When single-stepping over STI and MOV SS, we must clear the
3790 * corresponding interruptibility bits in the guest state. Otherwise
3791 * vmentry fails as it then expects bit 14 (BS) in pending debug
3792 * exceptions being set, but that's not correct for the guest debugging
3793 * case. */
3794 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3795 vmx_set_interrupt_shadow(vcpu, 0);
3796
3797 /*
3798 * Loading guest fpu may have cleared host cr0.ts
3799 */
3800 vmcs_writel(HOST_CR0, read_cr0());
3801
3802 asm(
3803 /* Store host registers */
3804 "push %%"R"dx; push %%"R"bp;"
3805 "push %%"R"cx \n\t"
3806 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3807 "je 1f \n\t"
3808 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3809 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3810 "1: \n\t"
3811 /* Reload cr2 if changed */
3812 "mov %c[cr2](%0), %%"R"ax \n\t"
3813 "mov %%cr2, %%"R"dx \n\t"
3814 "cmp %%"R"ax, %%"R"dx \n\t"
3815 "je 2f \n\t"
3816 "mov %%"R"ax, %%cr2 \n\t"
3817 "2: \n\t"
3818 /* Check if vmlaunch of vmresume is needed */
3819 "cmpl $0, %c[launched](%0) \n\t"
3820 /* Load guest registers. Don't clobber flags. */
3821 "mov %c[rax](%0), %%"R"ax \n\t"
3822 "mov %c[rbx](%0), %%"R"bx \n\t"
3823 "mov %c[rdx](%0), %%"R"dx \n\t"
3824 "mov %c[rsi](%0), %%"R"si \n\t"
3825 "mov %c[rdi](%0), %%"R"di \n\t"
3826 "mov %c[rbp](%0), %%"R"bp \n\t"
3827 #ifdef CONFIG_X86_64
3828 "mov %c[r8](%0), %%r8 \n\t"
3829 "mov %c[r9](%0), %%r9 \n\t"
3830 "mov %c[r10](%0), %%r10 \n\t"
3831 "mov %c[r11](%0), %%r11 \n\t"
3832 "mov %c[r12](%0), %%r12 \n\t"
3833 "mov %c[r13](%0), %%r13 \n\t"
3834 "mov %c[r14](%0), %%r14 \n\t"
3835 "mov %c[r15](%0), %%r15 \n\t"
3836 #endif
3837 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3838
3839 /* Enter guest mode */
3840 "jne .Llaunched \n\t"
3841 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3842 "jmp .Lkvm_vmx_return \n\t"
3843 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3844 ".Lkvm_vmx_return: "
3845 /* Save guest registers, load host registers, keep flags */
3846 "xchg %0, (%%"R"sp) \n\t"
3847 "mov %%"R"ax, %c[rax](%0) \n\t"
3848 "mov %%"R"bx, %c[rbx](%0) \n\t"
3849 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3850 "mov %%"R"dx, %c[rdx](%0) \n\t"
3851 "mov %%"R"si, %c[rsi](%0) \n\t"
3852 "mov %%"R"di, %c[rdi](%0) \n\t"
3853 "mov %%"R"bp, %c[rbp](%0) \n\t"
3854 #ifdef CONFIG_X86_64
3855 "mov %%r8, %c[r8](%0) \n\t"
3856 "mov %%r9, %c[r9](%0) \n\t"
3857 "mov %%r10, %c[r10](%0) \n\t"
3858 "mov %%r11, %c[r11](%0) \n\t"
3859 "mov %%r12, %c[r12](%0) \n\t"
3860 "mov %%r13, %c[r13](%0) \n\t"
3861 "mov %%r14, %c[r14](%0) \n\t"
3862 "mov %%r15, %c[r15](%0) \n\t"
3863 #endif
3864 "mov %%cr2, %%"R"ax \n\t"
3865 "mov %%"R"ax, %c[cr2](%0) \n\t"
3866
3867 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3868 "setbe %c[fail](%0) \n\t"
3869 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3870 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3871 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3872 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3873 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3874 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3875 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3876 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3877 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3878 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3879 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3880 #ifdef CONFIG_X86_64
3881 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3882 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3883 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3884 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3885 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3886 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3887 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3888 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3889 #endif
3890 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3891 : "cc", "memory"
3892 , R"bx", R"di", R"si"
3893 #ifdef CONFIG_X86_64
3894 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3895 #endif
3896 );
3897
3898 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3899 | (1 << VCPU_EXREG_PDPTR));
3900 vcpu->arch.regs_dirty = 0;
3901
3902 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3903 if (vmx->rmode.irq.pending)
3904 fixup_rmode_irq(vmx);
3905
3906 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3907 vmx->launched = 1;
3908
3909 vmx_complete_interrupts(vmx);
3910 }
3911
3912 #undef R
3913 #undef Q
3914
3915 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3916 {
3917 struct vcpu_vmx *vmx = to_vmx(vcpu);
3918
3919 if (vmx->vmcs) {
3920 vcpu_clear(vmx);
3921 free_vmcs(vmx->vmcs);
3922 vmx->vmcs = NULL;
3923 }
3924 }
3925
3926 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3927 {
3928 struct vcpu_vmx *vmx = to_vmx(vcpu);
3929
3930 free_vpid(vmx);
3931 vmx_free_vmcs(vcpu);
3932 kfree(vmx->guest_msrs);
3933 kvm_vcpu_uninit(vcpu);
3934 kmem_cache_free(kvm_vcpu_cache, vmx);
3935 }
3936
3937 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3938 {
3939 int err;
3940 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3941 int cpu;
3942
3943 if (!vmx)
3944 return ERR_PTR(-ENOMEM);
3945
3946 allocate_vpid(vmx);
3947
3948 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3949 if (err)
3950 goto free_vcpu;
3951
3952 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3953 if (!vmx->guest_msrs) {
3954 err = -ENOMEM;
3955 goto uninit_vcpu;
3956 }
3957
3958 vmx->vmcs = alloc_vmcs();
3959 if (!vmx->vmcs)
3960 goto free_msrs;
3961
3962 vmcs_clear(vmx->vmcs);
3963
3964 cpu = get_cpu();
3965 vmx_vcpu_load(&vmx->vcpu, cpu);
3966 err = vmx_vcpu_setup(vmx);
3967 vmx_vcpu_put(&vmx->vcpu);
3968 put_cpu();
3969 if (err)
3970 goto free_vmcs;
3971 if (vm_need_virtualize_apic_accesses(kvm))
3972 if (alloc_apic_access_page(kvm) != 0)
3973 goto free_vmcs;
3974
3975 if (enable_ept) {
3976 if (!kvm->arch.ept_identity_map_addr)
3977 kvm->arch.ept_identity_map_addr =
3978 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3979 if (alloc_identity_pagetable(kvm) != 0)
3980 goto free_vmcs;
3981 }
3982
3983 return &vmx->vcpu;
3984
3985 free_vmcs:
3986 free_vmcs(vmx->vmcs);
3987 free_msrs:
3988 kfree(vmx->guest_msrs);
3989 uninit_vcpu:
3990 kvm_vcpu_uninit(&vmx->vcpu);
3991 free_vcpu:
3992 free_vpid(vmx);
3993 kmem_cache_free(kvm_vcpu_cache, vmx);
3994 return ERR_PTR(err);
3995 }
3996
3997 static void __init vmx_check_processor_compat(void *rtn)
3998 {
3999 struct vmcs_config vmcs_conf;
4000
4001 *(int *)rtn = 0;
4002 if (setup_vmcs_config(&vmcs_conf) < 0)
4003 *(int *)rtn = -EIO;
4004 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4005 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4006 smp_processor_id());
4007 *(int *)rtn = -EIO;
4008 }
4009 }
4010
4011 static int get_ept_level(void)
4012 {
4013 return VMX_EPT_DEFAULT_GAW + 1;
4014 }
4015
4016 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4017 {
4018 u64 ret;
4019
4020 /* For VT-d and EPT combination
4021 * 1. MMIO: always map as UC
4022 * 2. EPT with VT-d:
4023 * a. VT-d without snooping control feature: can't guarantee the
4024 * result, try to trust guest.
4025 * b. VT-d with snooping control feature: snooping control feature of
4026 * VT-d engine can guarantee the cache correctness. Just set it
4027 * to WB to keep consistent with host. So the same as item 3.
4028 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4029 * consistent with host MTRR
4030 */
4031 if (is_mmio)
4032 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4033 else if (vcpu->kvm->arch.iommu_domain &&
4034 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4035 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4036 VMX_EPT_MT_EPTE_SHIFT;
4037 else
4038 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4039 | VMX_EPT_IPAT_BIT;
4040
4041 return ret;
4042 }
4043
4044 #define _ER(x) { EXIT_REASON_##x, #x }
4045
4046 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4047 _ER(EXCEPTION_NMI),
4048 _ER(EXTERNAL_INTERRUPT),
4049 _ER(TRIPLE_FAULT),
4050 _ER(PENDING_INTERRUPT),
4051 _ER(NMI_WINDOW),
4052 _ER(TASK_SWITCH),
4053 _ER(CPUID),
4054 _ER(HLT),
4055 _ER(INVLPG),
4056 _ER(RDPMC),
4057 _ER(RDTSC),
4058 _ER(VMCALL),
4059 _ER(VMCLEAR),
4060 _ER(VMLAUNCH),
4061 _ER(VMPTRLD),
4062 _ER(VMPTRST),
4063 _ER(VMREAD),
4064 _ER(VMRESUME),
4065 _ER(VMWRITE),
4066 _ER(VMOFF),
4067 _ER(VMON),
4068 _ER(CR_ACCESS),
4069 _ER(DR_ACCESS),
4070 _ER(IO_INSTRUCTION),
4071 _ER(MSR_READ),
4072 _ER(MSR_WRITE),
4073 _ER(MWAIT_INSTRUCTION),
4074 _ER(MONITOR_INSTRUCTION),
4075 _ER(PAUSE_INSTRUCTION),
4076 _ER(MCE_DURING_VMENTRY),
4077 _ER(TPR_BELOW_THRESHOLD),
4078 _ER(APIC_ACCESS),
4079 _ER(EPT_VIOLATION),
4080 _ER(EPT_MISCONFIG),
4081 _ER(WBINVD),
4082 { -1, NULL }
4083 };
4084
4085 #undef _ER
4086
4087 static int vmx_get_lpage_level(void)
4088 {
4089 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4090 return PT_DIRECTORY_LEVEL;
4091 else
4092 /* For shadow and EPT supported 1GB page */
4093 return PT_PDPE_LEVEL;
4094 }
4095
4096 static inline u32 bit(int bitno)
4097 {
4098 return 1 << (bitno & 31);
4099 }
4100
4101 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4102 {
4103 struct kvm_cpuid_entry2 *best;
4104 struct vcpu_vmx *vmx = to_vmx(vcpu);
4105 u32 exec_control;
4106
4107 vmx->rdtscp_enabled = false;
4108 if (vmx_rdtscp_supported()) {
4109 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4110 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4111 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4112 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4113 vmx->rdtscp_enabled = true;
4114 else {
4115 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4116 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4117 exec_control);
4118 }
4119 }
4120 }
4121 }
4122
4123 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4124 {
4125 }
4126
4127 static struct kvm_x86_ops vmx_x86_ops = {
4128 .cpu_has_kvm_support = cpu_has_kvm_support,
4129 .disabled_by_bios = vmx_disabled_by_bios,
4130 .hardware_setup = hardware_setup,
4131 .hardware_unsetup = hardware_unsetup,
4132 .check_processor_compatibility = vmx_check_processor_compat,
4133 .hardware_enable = hardware_enable,
4134 .hardware_disable = hardware_disable,
4135 .cpu_has_accelerated_tpr = report_flexpriority,
4136
4137 .vcpu_create = vmx_create_vcpu,
4138 .vcpu_free = vmx_free_vcpu,
4139 .vcpu_reset = vmx_vcpu_reset,
4140
4141 .prepare_guest_switch = vmx_save_host_state,
4142 .vcpu_load = vmx_vcpu_load,
4143 .vcpu_put = vmx_vcpu_put,
4144
4145 .set_guest_debug = set_guest_debug,
4146 .get_msr = vmx_get_msr,
4147 .set_msr = vmx_set_msr,
4148 .get_segment_base = vmx_get_segment_base,
4149 .get_segment = vmx_get_segment,
4150 .set_segment = vmx_set_segment,
4151 .get_cpl = vmx_get_cpl,
4152 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4153 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4154 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4155 .set_cr0 = vmx_set_cr0,
4156 .set_cr3 = vmx_set_cr3,
4157 .set_cr4 = vmx_set_cr4,
4158 .set_efer = vmx_set_efer,
4159 .get_idt = vmx_get_idt,
4160 .set_idt = vmx_set_idt,
4161 .get_gdt = vmx_get_gdt,
4162 .set_gdt = vmx_set_gdt,
4163 .set_dr7 = vmx_set_dr7,
4164 .cache_reg = vmx_cache_reg,
4165 .get_rflags = vmx_get_rflags,
4166 .set_rflags = vmx_set_rflags,
4167 .fpu_activate = vmx_fpu_activate,
4168 .fpu_deactivate = vmx_fpu_deactivate,
4169
4170 .tlb_flush = vmx_flush_tlb,
4171
4172 .run = vmx_vcpu_run,
4173 .handle_exit = vmx_handle_exit,
4174 .skip_emulated_instruction = skip_emulated_instruction,
4175 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4176 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4177 .patch_hypercall = vmx_patch_hypercall,
4178 .set_irq = vmx_inject_irq,
4179 .set_nmi = vmx_inject_nmi,
4180 .queue_exception = vmx_queue_exception,
4181 .interrupt_allowed = vmx_interrupt_allowed,
4182 .nmi_allowed = vmx_nmi_allowed,
4183 .get_nmi_mask = vmx_get_nmi_mask,
4184 .set_nmi_mask = vmx_set_nmi_mask,
4185 .enable_nmi_window = enable_nmi_window,
4186 .enable_irq_window = enable_irq_window,
4187 .update_cr8_intercept = update_cr8_intercept,
4188
4189 .set_tss_addr = vmx_set_tss_addr,
4190 .get_tdp_level = get_ept_level,
4191 .get_mt_mask = vmx_get_mt_mask,
4192
4193 .exit_reasons_str = vmx_exit_reasons_str,
4194 .get_lpage_level = vmx_get_lpage_level,
4195
4196 .cpuid_update = vmx_cpuid_update,
4197
4198 .rdtscp_supported = vmx_rdtscp_supported,
4199
4200 .set_supported_cpuid = vmx_set_supported_cpuid,
4201 };
4202
4203 static int __init vmx_init(void)
4204 {
4205 int r, i;
4206
4207 rdmsrl_safe(MSR_EFER, &host_efer);
4208
4209 for (i = 0; i < NR_VMX_MSR; ++i)
4210 kvm_define_shared_msr(i, vmx_msr_index[i]);
4211
4212 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4213 if (!vmx_io_bitmap_a)
4214 return -ENOMEM;
4215
4216 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4217 if (!vmx_io_bitmap_b) {
4218 r = -ENOMEM;
4219 goto out;
4220 }
4221
4222 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4223 if (!vmx_msr_bitmap_legacy) {
4224 r = -ENOMEM;
4225 goto out1;
4226 }
4227
4228 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4229 if (!vmx_msr_bitmap_longmode) {
4230 r = -ENOMEM;
4231 goto out2;
4232 }
4233
4234 /*
4235 * Allow direct access to the PC debug port (it is often used for I/O
4236 * delays, but the vmexits simply slow things down).
4237 */
4238 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4239 clear_bit(0x80, vmx_io_bitmap_a);
4240
4241 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4242
4243 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4244 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4245
4246 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4247
4248 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4249 __alignof__(struct vcpu_vmx), THIS_MODULE);
4250 if (r)
4251 goto out3;
4252
4253 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4254 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4255 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4256 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4257 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4258 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4259
4260 if (enable_ept) {
4261 bypass_guest_pf = 0;
4262 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4263 VMX_EPT_WRITABLE_MASK);
4264 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4265 VMX_EPT_EXECUTABLE_MASK);
4266 kvm_enable_tdp();
4267 } else
4268 kvm_disable_tdp();
4269
4270 if (bypass_guest_pf)
4271 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4272
4273 return 0;
4274
4275 out3:
4276 free_page((unsigned long)vmx_msr_bitmap_longmode);
4277 out2:
4278 free_page((unsigned long)vmx_msr_bitmap_legacy);
4279 out1:
4280 free_page((unsigned long)vmx_io_bitmap_b);
4281 out:
4282 free_page((unsigned long)vmx_io_bitmap_a);
4283 return r;
4284 }
4285
4286 static void __exit vmx_exit(void)
4287 {
4288 free_page((unsigned long)vmx_msr_bitmap_legacy);
4289 free_page((unsigned long)vmx_msr_bitmap_longmode);
4290 free_page((unsigned long)vmx_io_bitmap_b);
4291 free_page((unsigned long)vmx_io_bitmap_a);
4292
4293 kvm_exit();
4294 }
4295
4296 module_init(vmx_init)
4297 module_exit(vmx_exit)
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