2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
139 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
149 * According to test, this time is usually smaller than 128 cycles.
150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
156 #define KVM_VMX_DEFAULT_PLE_GAP 128
157 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
163 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
164 module_param(ple_gap
, int, S_IRUGO
);
166 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
167 module_param(ple_window
, int, S_IRUGO
);
169 /* Default doubles per-vcpu window every exit. */
170 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
171 module_param(ple_window_grow
, int, S_IRUGO
);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
175 module_param(ple_window_shrink
, int, S_IRUGO
);
177 /* Default is to compute the maximum so we can never overflow. */
178 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
180 module_param(ple_window_max
, int, S_IRUGO
);
182 extern const ulong vmx_return
;
184 #define NR_AUTOLOAD_MSRS 8
185 #define VMCS02_POOL_SIZE 1
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
200 struct vmcs
*shadow_vmcs
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
247 u64 eoi_exit_bitmap0
;
248 u64 eoi_exit_bitmap1
;
249 u64 eoi_exit_bitmap2
;
250 u64 eoi_exit_bitmap3
;
252 u64 guest_physical_address
;
253 u64 vmcs_link_pointer
;
254 u64 guest_ia32_debugctl
;
257 u64 guest_ia32_perf_global_ctrl
;
265 u64 host_ia32_perf_global_ctrl
;
266 u64 padding64
[8]; /* room for future expansion */
268 * To allow migration of L1 (complete with its L2 guests) between
269 * machines of different natural widths (32 or 64 bit), we cannot have
270 * unsigned long fields with no explict size. We use u64 (aliased
271 * natural_width) instead. Luckily, x86 is little-endian.
273 natural_width cr0_guest_host_mask
;
274 natural_width cr4_guest_host_mask
;
275 natural_width cr0_read_shadow
;
276 natural_width cr4_read_shadow
;
277 natural_width cr3_target_value0
;
278 natural_width cr3_target_value1
;
279 natural_width cr3_target_value2
;
280 natural_width cr3_target_value3
;
281 natural_width exit_qualification
;
282 natural_width guest_linear_address
;
283 natural_width guest_cr0
;
284 natural_width guest_cr3
;
285 natural_width guest_cr4
;
286 natural_width guest_es_base
;
287 natural_width guest_cs_base
;
288 natural_width guest_ss_base
;
289 natural_width guest_ds_base
;
290 natural_width guest_fs_base
;
291 natural_width guest_gs_base
;
292 natural_width guest_ldtr_base
;
293 natural_width guest_tr_base
;
294 natural_width guest_gdtr_base
;
295 natural_width guest_idtr_base
;
296 natural_width guest_dr7
;
297 natural_width guest_rsp
;
298 natural_width guest_rip
;
299 natural_width guest_rflags
;
300 natural_width guest_pending_dbg_exceptions
;
301 natural_width guest_sysenter_esp
;
302 natural_width guest_sysenter_eip
;
303 natural_width host_cr0
;
304 natural_width host_cr3
;
305 natural_width host_cr4
;
306 natural_width host_fs_base
;
307 natural_width host_gs_base
;
308 natural_width host_tr_base
;
309 natural_width host_gdtr_base
;
310 natural_width host_idtr_base
;
311 natural_width host_ia32_sysenter_esp
;
312 natural_width host_ia32_sysenter_eip
;
313 natural_width host_rsp
;
314 natural_width host_rip
;
315 natural_width paddingl
[8]; /* room for future expansion */
316 u32 pin_based_vm_exec_control
;
317 u32 cpu_based_vm_exec_control
;
318 u32 exception_bitmap
;
319 u32 page_fault_error_code_mask
;
320 u32 page_fault_error_code_match
;
321 u32 cr3_target_count
;
322 u32 vm_exit_controls
;
323 u32 vm_exit_msr_store_count
;
324 u32 vm_exit_msr_load_count
;
325 u32 vm_entry_controls
;
326 u32 vm_entry_msr_load_count
;
327 u32 vm_entry_intr_info_field
;
328 u32 vm_entry_exception_error_code
;
329 u32 vm_entry_instruction_len
;
331 u32 secondary_vm_exec_control
;
332 u32 vm_instruction_error
;
334 u32 vm_exit_intr_info
;
335 u32 vm_exit_intr_error_code
;
336 u32 idt_vectoring_info_field
;
337 u32 idt_vectoring_error_code
;
338 u32 vm_exit_instruction_len
;
339 u32 vmx_instruction_info
;
346 u32 guest_ldtr_limit
;
348 u32 guest_gdtr_limit
;
349 u32 guest_idtr_limit
;
350 u32 guest_es_ar_bytes
;
351 u32 guest_cs_ar_bytes
;
352 u32 guest_ss_ar_bytes
;
353 u32 guest_ds_ar_bytes
;
354 u32 guest_fs_ar_bytes
;
355 u32 guest_gs_ar_bytes
;
356 u32 guest_ldtr_ar_bytes
;
357 u32 guest_tr_ar_bytes
;
358 u32 guest_interruptibility_info
;
359 u32 guest_activity_state
;
360 u32 guest_sysenter_cs
;
361 u32 host_ia32_sysenter_cs
;
362 u32 vmx_preemption_timer_value
;
363 u32 padding32
[7]; /* room for future expansion */
364 u16 virtual_processor_id
;
366 u16 guest_es_selector
;
367 u16 guest_cs_selector
;
368 u16 guest_ss_selector
;
369 u16 guest_ds_selector
;
370 u16 guest_fs_selector
;
371 u16 guest_gs_selector
;
372 u16 guest_ldtr_selector
;
373 u16 guest_tr_selector
;
374 u16 guest_intr_status
;
375 u16 host_es_selector
;
376 u16 host_cs_selector
;
377 u16 host_ss_selector
;
378 u16 host_ds_selector
;
379 u16 host_fs_selector
;
380 u16 host_gs_selector
;
381 u16 host_tr_selector
;
385 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
386 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
387 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
389 #define VMCS12_REVISION 0x11e57ed0
392 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
393 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
394 * current implementation, 4K are reserved to avoid future complications.
396 #define VMCS12_SIZE 0x1000
398 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
400 struct list_head list
;
402 struct loaded_vmcs vmcs02
;
406 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
407 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
410 /* Has the level1 guest done vmxon? */
414 /* The guest-physical address of the current VMCS L1 keeps for L2 */
416 /* The host-usable pointer to the above */
417 struct page
*current_vmcs12_page
;
418 struct vmcs12
*current_vmcs12
;
420 * Cache of the guest's VMCS, existing outside of guest memory.
421 * Loaded from guest memory during VMPTRLD. Flushed to guest
422 * memory during VMXOFF, VMCLEAR, VMPTRLD.
424 struct vmcs12
*cached_vmcs12
;
426 * Indicates if the shadow vmcs must be updated with the
427 * data hold by vmcs12
429 bool sync_shadow_vmcs
;
431 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
432 struct list_head vmcs02_pool
;
434 bool change_vmcs01_virtual_x2apic_mode
;
435 /* L2 must run next, and mustn't decide to exit to L1. */
436 bool nested_run_pending
;
438 * Guest pages referred to in vmcs02 with host-physical pointers, so
439 * we must keep them pinned while L2 runs.
441 struct page
*apic_access_page
;
442 struct page
*virtual_apic_page
;
443 struct page
*pi_desc_page
;
444 struct pi_desc
*pi_desc
;
448 unsigned long *msr_bitmap
;
450 struct hrtimer preemption_timer
;
451 bool preemption_timer_expired
;
453 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
460 * We only store the "true" versions of the VMX capability MSRs. We
461 * generate the "non-true" versions by setting the must-be-1 bits
462 * according to the SDM.
464 u32 nested_vmx_procbased_ctls_low
;
465 u32 nested_vmx_procbased_ctls_high
;
466 u32 nested_vmx_secondary_ctls_low
;
467 u32 nested_vmx_secondary_ctls_high
;
468 u32 nested_vmx_pinbased_ctls_low
;
469 u32 nested_vmx_pinbased_ctls_high
;
470 u32 nested_vmx_exit_ctls_low
;
471 u32 nested_vmx_exit_ctls_high
;
472 u32 nested_vmx_entry_ctls_low
;
473 u32 nested_vmx_entry_ctls_high
;
474 u32 nested_vmx_misc_low
;
475 u32 nested_vmx_misc_high
;
476 u32 nested_vmx_ept_caps
;
477 u32 nested_vmx_vpid_caps
;
478 u64 nested_vmx_basic
;
479 u64 nested_vmx_cr0_fixed0
;
480 u64 nested_vmx_cr0_fixed1
;
481 u64 nested_vmx_cr4_fixed0
;
482 u64 nested_vmx_cr4_fixed1
;
483 u64 nested_vmx_vmcs_enum
;
486 #define POSTED_INTR_ON 0
487 #define POSTED_INTR_SN 1
489 /* Posted-Interrupt Descriptor */
491 u32 pir
[8]; /* Posted interrupt requested */
494 /* bit 256 - Outstanding Notification */
496 /* bit 257 - Suppress Notification */
498 /* bit 271:258 - Reserved */
500 /* bit 279:272 - Notification Vector */
502 /* bit 287:280 - Reserved */
504 /* bit 319:288 - Notification Destination */
512 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
514 return test_and_set_bit(POSTED_INTR_ON
,
515 (unsigned long *)&pi_desc
->control
);
518 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
520 return test_and_clear_bit(POSTED_INTR_ON
,
521 (unsigned long *)&pi_desc
->control
);
524 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
526 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
529 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
531 return clear_bit(POSTED_INTR_SN
,
532 (unsigned long *)&pi_desc
->control
);
535 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
537 return set_bit(POSTED_INTR_SN
,
538 (unsigned long *)&pi_desc
->control
);
541 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
543 clear_bit(POSTED_INTR_ON
,
544 (unsigned long *)&pi_desc
->control
);
547 static inline int pi_test_on(struct pi_desc
*pi_desc
)
549 return test_bit(POSTED_INTR_ON
,
550 (unsigned long *)&pi_desc
->control
);
553 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
555 return test_bit(POSTED_INTR_SN
,
556 (unsigned long *)&pi_desc
->control
);
560 struct kvm_vcpu vcpu
;
561 unsigned long host_rsp
;
563 bool nmi_known_unmasked
;
565 u32 idt_vectoring_info
;
567 struct shared_msr_entry
*guest_msrs
;
570 unsigned long host_idt_base
;
572 u64 msr_host_kernel_gs_base
;
573 u64 msr_guest_kernel_gs_base
;
575 u32 vm_entry_controls_shadow
;
576 u32 vm_exit_controls_shadow
;
578 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
579 * non-nested (L1) guest, it always points to vmcs01. For a nested
580 * guest (L2), it points to a different VMCS.
582 struct loaded_vmcs vmcs01
;
583 struct loaded_vmcs
*loaded_vmcs
;
584 bool __launched
; /* temporary, used in vmx_vcpu_run */
585 struct msr_autoload
{
587 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
588 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
592 u16 fs_sel
, gs_sel
, ldt_sel
;
596 int gs_ldt_reload_needed
;
597 int fs_reload_needed
;
598 u64 msr_host_bndcfgs
;
599 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
604 struct kvm_segment segs
[8];
607 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
608 struct kvm_save_segment
{
616 bool emulation_required
;
618 /* Support for vnmi-less CPUs */
619 int soft_vnmi_blocked
;
621 s64 vnmi_blocked_time
;
624 /* Posted interrupt descriptor */
625 struct pi_desc pi_desc
;
627 /* Support for a guest hypervisor (nested VMX) */
628 struct nested_vmx nested
;
630 /* Dynamic PLE window. */
632 bool ple_window_dirty
;
634 /* Support for PML */
635 #define PML_ENTITY_NUM 512
638 /* apic deadline value in host tsc */
641 u64 current_tsc_ratio
;
643 bool guest_pkru_valid
;
648 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
649 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
650 * in msr_ia32_feature_control_valid_bits.
652 u64 msr_ia32_feature_control
;
653 u64 msr_ia32_feature_control_valid_bits
;
656 enum segment_cache_field
{
665 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
667 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
670 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
672 return &(to_vmx(vcpu
)->pi_desc
);
675 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
676 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
677 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
678 [number##_HIGH] = VMCS12_OFFSET(name)+4
681 static unsigned long shadow_read_only_fields
[] = {
683 * We do NOT shadow fields that are modified when L0
684 * traps and emulates any vmx instruction (e.g. VMPTRLD,
685 * VMXON...) executed by L1.
686 * For example, VM_INSTRUCTION_ERROR is read
687 * by L1 if a vmx instruction fails (part of the error path).
688 * Note the code assumes this logic. If for some reason
689 * we start shadowing these fields then we need to
690 * force a shadow sync when L0 emulates vmx instructions
691 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
692 * by nested_vmx_failValid)
696 VM_EXIT_INSTRUCTION_LEN
,
697 IDT_VECTORING_INFO_FIELD
,
698 IDT_VECTORING_ERROR_CODE
,
699 VM_EXIT_INTR_ERROR_CODE
,
701 GUEST_LINEAR_ADDRESS
,
702 GUEST_PHYSICAL_ADDRESS
704 static int max_shadow_read_only_fields
=
705 ARRAY_SIZE(shadow_read_only_fields
);
707 static unsigned long shadow_read_write_fields
[] = {
714 GUEST_INTERRUPTIBILITY_INFO
,
727 CPU_BASED_VM_EXEC_CONTROL
,
728 VM_ENTRY_EXCEPTION_ERROR_CODE
,
729 VM_ENTRY_INTR_INFO_FIELD
,
730 VM_ENTRY_INSTRUCTION_LEN
,
731 VM_ENTRY_EXCEPTION_ERROR_CODE
,
737 static int max_shadow_read_write_fields
=
738 ARRAY_SIZE(shadow_read_write_fields
);
740 static const unsigned short vmcs_field_to_offset_table
[] = {
741 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
742 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
743 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
744 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
745 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
746 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
747 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
748 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
749 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
750 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
751 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
752 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
753 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
754 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
755 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
756 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
757 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
758 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
759 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
760 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
761 FIELD64(MSR_BITMAP
, msr_bitmap
),
762 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
763 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
764 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
765 FIELD64(TSC_OFFSET
, tsc_offset
),
766 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
767 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
768 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
769 FIELD64(EPT_POINTER
, ept_pointer
),
770 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
771 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
772 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
773 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
774 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
775 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
776 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
777 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
778 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
779 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
780 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
781 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
782 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
783 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
784 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
785 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
786 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
787 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
788 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
789 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
790 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
791 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
792 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
793 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
794 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
795 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
796 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
797 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
798 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
799 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
800 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
801 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
802 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
803 FIELD(TPR_THRESHOLD
, tpr_threshold
),
804 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
805 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
806 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
807 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
808 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
809 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
810 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
811 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
812 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
813 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
814 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
815 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
816 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
817 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
818 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
819 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
820 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
821 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
822 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
823 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
824 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
825 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
826 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
827 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
828 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
829 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
830 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
831 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
832 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
833 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
834 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
835 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
836 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
837 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
838 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
839 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
840 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
841 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
842 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
843 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
844 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
845 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
846 FIELD(GUEST_CR0
, guest_cr0
),
847 FIELD(GUEST_CR3
, guest_cr3
),
848 FIELD(GUEST_CR4
, guest_cr4
),
849 FIELD(GUEST_ES_BASE
, guest_es_base
),
850 FIELD(GUEST_CS_BASE
, guest_cs_base
),
851 FIELD(GUEST_SS_BASE
, guest_ss_base
),
852 FIELD(GUEST_DS_BASE
, guest_ds_base
),
853 FIELD(GUEST_FS_BASE
, guest_fs_base
),
854 FIELD(GUEST_GS_BASE
, guest_gs_base
),
855 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
856 FIELD(GUEST_TR_BASE
, guest_tr_base
),
857 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
858 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
859 FIELD(GUEST_DR7
, guest_dr7
),
860 FIELD(GUEST_RSP
, guest_rsp
),
861 FIELD(GUEST_RIP
, guest_rip
),
862 FIELD(GUEST_RFLAGS
, guest_rflags
),
863 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
864 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
865 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
866 FIELD(HOST_CR0
, host_cr0
),
867 FIELD(HOST_CR3
, host_cr3
),
868 FIELD(HOST_CR4
, host_cr4
),
869 FIELD(HOST_FS_BASE
, host_fs_base
),
870 FIELD(HOST_GS_BASE
, host_gs_base
),
871 FIELD(HOST_TR_BASE
, host_tr_base
),
872 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
873 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
874 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
875 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
876 FIELD(HOST_RSP
, host_rsp
),
877 FIELD(HOST_RIP
, host_rip
),
880 static inline short vmcs_field_to_offset(unsigned long field
)
882 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
884 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
885 vmcs_field_to_offset_table
[field
] == 0)
888 return vmcs_field_to_offset_table
[field
];
891 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
893 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
896 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
898 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
899 if (is_error_page(page
))
905 static void nested_release_page(struct page
*page
)
907 kvm_release_page_dirty(page
);
910 static void nested_release_page_clean(struct page
*page
)
912 kvm_release_page_clean(page
);
915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
916 static u64
construct_eptp(unsigned long root_hpa
);
917 static void kvm_cpu_vmxon(u64 addr
);
918 static void kvm_cpu_vmxoff(void);
919 static bool vmx_xsaves_supported(void);
920 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
921 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
922 struct kvm_segment
*var
, int seg
);
923 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
924 struct kvm_segment
*var
, int seg
);
925 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
926 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
927 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
928 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
929 static int alloc_identity_pagetable(struct kvm
*kvm
);
931 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
932 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
938 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
941 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
942 * can find which vCPU should be waken up.
944 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
945 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
950 VMX_MSR_BITMAP_LEGACY
,
951 VMX_MSR_BITMAP_LONGMODE
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
954 VMX_MSR_BITMAP_LEGACY_X2APIC
,
955 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
961 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
963 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
964 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
965 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
966 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
967 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
968 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
969 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
970 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
971 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
972 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
974 static bool cpu_has_load_ia32_efer
;
975 static bool cpu_has_load_perf_global_ctrl
;
977 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
978 static DEFINE_SPINLOCK(vmx_vpid_lock
);
980 static struct vmcs_config
{
985 u32 pin_based_exec_ctrl
;
986 u32 cpu_based_exec_ctrl
;
987 u32 cpu_based_2nd_exec_ctrl
;
992 static struct vmx_capability
{
997 #define VMX_SEGMENT_FIELD(seg) \
998 [VCPU_SREG_##seg] = { \
999 .selector = GUEST_##seg##_SELECTOR, \
1000 .base = GUEST_##seg##_BASE, \
1001 .limit = GUEST_##seg##_LIMIT, \
1002 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1005 static const struct kvm_vmx_segment_field
{
1010 } kvm_vmx_segment_fields
[] = {
1011 VMX_SEGMENT_FIELD(CS
),
1012 VMX_SEGMENT_FIELD(DS
),
1013 VMX_SEGMENT_FIELD(ES
),
1014 VMX_SEGMENT_FIELD(FS
),
1015 VMX_SEGMENT_FIELD(GS
),
1016 VMX_SEGMENT_FIELD(SS
),
1017 VMX_SEGMENT_FIELD(TR
),
1018 VMX_SEGMENT_FIELD(LDTR
),
1021 static u64 host_efer
;
1023 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1026 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1027 * away by decrementing the array size.
1029 static const u32 vmx_msr_index
[] = {
1030 #ifdef CONFIG_X86_64
1031 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1033 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1036 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1038 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1039 INTR_INFO_VALID_MASK
)) ==
1040 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1043 static inline bool is_debug(u32 intr_info
)
1045 return is_exception_n(intr_info
, DB_VECTOR
);
1048 static inline bool is_breakpoint(u32 intr_info
)
1050 return is_exception_n(intr_info
, BP_VECTOR
);
1053 static inline bool is_page_fault(u32 intr_info
)
1055 return is_exception_n(intr_info
, PF_VECTOR
);
1058 static inline bool is_no_device(u32 intr_info
)
1060 return is_exception_n(intr_info
, NM_VECTOR
);
1063 static inline bool is_invalid_opcode(u32 intr_info
)
1065 return is_exception_n(intr_info
, UD_VECTOR
);
1068 static inline bool is_external_interrupt(u32 intr_info
)
1070 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1071 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1074 static inline bool is_machine_check(u32 intr_info
)
1076 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1077 INTR_INFO_VALID_MASK
)) ==
1078 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1081 static inline bool cpu_has_vmx_msr_bitmap(void)
1083 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1086 static inline bool cpu_has_vmx_tpr_shadow(void)
1088 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1091 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1093 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1096 static inline bool cpu_has_secondary_exec_ctrls(void)
1098 return vmcs_config
.cpu_based_exec_ctrl
&
1099 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1102 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1108 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1114 static inline bool cpu_has_vmx_apic_register_virt(void)
1116 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1117 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1120 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1122 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1123 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1127 * Comment's format: document - errata name - stepping - processor name.
1129 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1131 static u32 vmx_preemption_cpu_tfms
[] = {
1132 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1134 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1135 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1136 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1140 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1141 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1143 * 320767.pdf - AAP86 - B1 -
1144 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1147 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1149 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1151 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1153 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1154 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1155 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1159 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1161 u32 eax
= cpuid_eax(0x00000001), i
;
1163 /* Clear the reserved bits */
1164 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1165 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1166 if (eax
== vmx_preemption_cpu_tfms
[i
])
1172 static inline bool cpu_has_vmx_preemption_timer(void)
1174 return vmcs_config
.pin_based_exec_ctrl
&
1175 PIN_BASED_VMX_PREEMPTION_TIMER
;
1178 static inline bool cpu_has_vmx_posted_intr(void)
1180 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1181 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1184 static inline bool cpu_has_vmx_apicv(void)
1186 return cpu_has_vmx_apic_register_virt() &&
1187 cpu_has_vmx_virtual_intr_delivery() &&
1188 cpu_has_vmx_posted_intr();
1191 static inline bool cpu_has_vmx_flexpriority(void)
1193 return cpu_has_vmx_tpr_shadow() &&
1194 cpu_has_vmx_virtualize_apic_accesses();
1197 static inline bool cpu_has_vmx_ept_execute_only(void)
1199 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1202 static inline bool cpu_has_vmx_ept_2m_page(void)
1204 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1207 static inline bool cpu_has_vmx_ept_1g_page(void)
1209 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1212 static inline bool cpu_has_vmx_ept_4levels(void)
1214 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1217 static inline bool cpu_has_vmx_ept_ad_bits(void)
1219 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1222 static inline bool cpu_has_vmx_invept_context(void)
1224 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1227 static inline bool cpu_has_vmx_invept_global(void)
1229 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1232 static inline bool cpu_has_vmx_invvpid_single(void)
1234 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1237 static inline bool cpu_has_vmx_invvpid_global(void)
1239 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1242 static inline bool cpu_has_vmx_invvpid(void)
1244 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1247 static inline bool cpu_has_vmx_ept(void)
1249 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1250 SECONDARY_EXEC_ENABLE_EPT
;
1253 static inline bool cpu_has_vmx_unrestricted_guest(void)
1255 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1256 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1259 static inline bool cpu_has_vmx_ple(void)
1261 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1262 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1265 static inline bool cpu_has_vmx_basic_inout(void)
1267 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1270 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1272 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1275 static inline bool cpu_has_vmx_vpid(void)
1277 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1278 SECONDARY_EXEC_ENABLE_VPID
;
1281 static inline bool cpu_has_vmx_rdtscp(void)
1283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1284 SECONDARY_EXEC_RDTSCP
;
1287 static inline bool cpu_has_vmx_invpcid(void)
1289 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1290 SECONDARY_EXEC_ENABLE_INVPCID
;
1293 static inline bool cpu_has_virtual_nmis(void)
1295 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1298 static inline bool cpu_has_vmx_wbinvd_exit(void)
1300 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1301 SECONDARY_EXEC_WBINVD_EXITING
;
1304 static inline bool cpu_has_vmx_shadow_vmcs(void)
1307 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1308 /* check if the cpu supports writing r/o exit information fields */
1309 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1312 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1313 SECONDARY_EXEC_SHADOW_VMCS
;
1316 static inline bool cpu_has_vmx_pml(void)
1318 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1321 static inline bool cpu_has_vmx_tsc_scaling(void)
1323 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1324 SECONDARY_EXEC_TSC_SCALING
;
1327 static inline bool report_flexpriority(void)
1329 return flexpriority_enabled
;
1332 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1334 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1337 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1339 return (vmcs12
->cpu_based_vm_exec_control
&
1340 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1341 (vmcs12
->secondary_vm_exec_control
& bit
);
1344 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1346 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1349 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1351 return vmcs12
->pin_based_vm_exec_control
&
1352 PIN_BASED_VMX_PREEMPTION_TIMER
;
1355 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1357 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1360 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1362 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1363 vmx_xsaves_supported();
1366 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1371 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1376 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1378 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1381 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1383 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1386 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1388 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1391 static inline bool is_nmi(u32 intr_info
)
1393 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1394 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1397 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1399 unsigned long exit_qualification
);
1400 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1401 struct vmcs12
*vmcs12
,
1402 u32 reason
, unsigned long qualification
);
1404 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1408 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1409 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1414 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1420 } operand
= { vpid
, 0, gva
};
1422 asm volatile (__ex(ASM_VMX_INVVPID
)
1423 /* CF==1 or ZF==1 --> rc = -1 */
1424 "; ja 1f ; ud2 ; 1:"
1425 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1428 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1432 } operand
= {eptp
, gpa
};
1434 asm volatile (__ex(ASM_VMX_INVEPT
)
1435 /* CF==1 or ZF==1 --> rc = -1 */
1436 "; ja 1f ; ud2 ; 1:\n"
1437 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1440 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1444 i
= __find_msr_index(vmx
, msr
);
1446 return &vmx
->guest_msrs
[i
];
1450 static void vmcs_clear(struct vmcs
*vmcs
)
1452 u64 phys_addr
= __pa(vmcs
);
1455 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1456 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1459 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1463 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1465 vmcs_clear(loaded_vmcs
->vmcs
);
1466 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1467 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1468 loaded_vmcs
->cpu
= -1;
1469 loaded_vmcs
->launched
= 0;
1472 static void vmcs_load(struct vmcs
*vmcs
)
1474 u64 phys_addr
= __pa(vmcs
);
1477 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1478 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1481 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1485 #ifdef CONFIG_KEXEC_CORE
1487 * This bitmap is used to indicate whether the vmclear
1488 * operation is enabled on all cpus. All disabled by
1491 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1493 static inline void crash_enable_local_vmclear(int cpu
)
1495 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1498 static inline void crash_disable_local_vmclear(int cpu
)
1500 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static inline int crash_local_vmclear_enabled(int cpu
)
1505 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1508 static void crash_vmclear_local_loaded_vmcss(void)
1510 int cpu
= raw_smp_processor_id();
1511 struct loaded_vmcs
*v
;
1513 if (!crash_local_vmclear_enabled(cpu
))
1516 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1517 loaded_vmcss_on_cpu_link
)
1518 vmcs_clear(v
->vmcs
);
1521 static inline void crash_enable_local_vmclear(int cpu
) { }
1522 static inline void crash_disable_local_vmclear(int cpu
) { }
1523 #endif /* CONFIG_KEXEC_CORE */
1525 static void __loaded_vmcs_clear(void *arg
)
1527 struct loaded_vmcs
*loaded_vmcs
= arg
;
1528 int cpu
= raw_smp_processor_id();
1530 if (loaded_vmcs
->cpu
!= cpu
)
1531 return; /* vcpu migration can race with cpu offline */
1532 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1533 per_cpu(current_vmcs
, cpu
) = NULL
;
1534 crash_disable_local_vmclear(cpu
);
1535 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1538 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1539 * is before setting loaded_vmcs->vcpu to -1 which is done in
1540 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1541 * then adds the vmcs into percpu list before it is deleted.
1545 loaded_vmcs_init(loaded_vmcs
);
1546 crash_enable_local_vmclear(cpu
);
1549 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1551 int cpu
= loaded_vmcs
->cpu
;
1554 smp_call_function_single(cpu
,
1555 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1558 static inline void vpid_sync_vcpu_single(int vpid
)
1563 if (cpu_has_vmx_invvpid_single())
1564 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1567 static inline void vpid_sync_vcpu_global(void)
1569 if (cpu_has_vmx_invvpid_global())
1570 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1573 static inline void vpid_sync_context(int vpid
)
1575 if (cpu_has_vmx_invvpid_single())
1576 vpid_sync_vcpu_single(vpid
);
1578 vpid_sync_vcpu_global();
1581 static inline void ept_sync_global(void)
1583 if (cpu_has_vmx_invept_global())
1584 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1587 static inline void ept_sync_context(u64 eptp
)
1590 if (cpu_has_vmx_invept_context())
1591 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1597 static __always_inline
void vmcs_check16(unsigned long field
)
1599 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1600 "16-bit accessor invalid for 64-bit field");
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1602 "16-bit accessor invalid for 64-bit high field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1604 "16-bit accessor invalid for 32-bit high field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1606 "16-bit accessor invalid for natural width field");
1609 static __always_inline
void vmcs_check32(unsigned long field
)
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1612 "32-bit accessor invalid for 16-bit field");
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1614 "32-bit accessor invalid for natural width field");
1617 static __always_inline
void vmcs_check64(unsigned long field
)
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1620 "64-bit accessor invalid for 16-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1622 "64-bit accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1624 "64-bit accessor invalid for 32-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1626 "64-bit accessor invalid for natural width field");
1629 static __always_inline
void vmcs_checkl(unsigned long field
)
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1632 "Natural width accessor invalid for 16-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1634 "Natural width accessor invalid for 64-bit field");
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1636 "Natural width accessor invalid for 64-bit high field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1638 "Natural width accessor invalid for 32-bit field");
1641 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1643 unsigned long value
;
1645 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1646 : "=a"(value
) : "d"(field
) : "cc");
1650 static __always_inline u16
vmcs_read16(unsigned long field
)
1652 vmcs_check16(field
);
1653 return __vmcs_readl(field
);
1656 static __always_inline u32
vmcs_read32(unsigned long field
)
1658 vmcs_check32(field
);
1659 return __vmcs_readl(field
);
1662 static __always_inline u64
vmcs_read64(unsigned long field
)
1664 vmcs_check64(field
);
1665 #ifdef CONFIG_X86_64
1666 return __vmcs_readl(field
);
1668 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1672 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1675 return __vmcs_readl(field
);
1678 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1680 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1681 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1685 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1689 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1690 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1691 if (unlikely(error
))
1692 vmwrite_error(field
, value
);
1695 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1697 vmcs_check16(field
);
1698 __vmcs_writel(field
, value
);
1701 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1703 vmcs_check32(field
);
1704 __vmcs_writel(field
, value
);
1707 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1709 vmcs_check64(field
);
1710 __vmcs_writel(field
, value
);
1711 #ifndef CONFIG_X86_64
1713 __vmcs_writel(field
+1, value
>> 32);
1717 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1720 __vmcs_writel(field
, value
);
1723 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1725 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1726 "vmcs_clear_bits does not support 64-bit fields");
1727 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1730 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1732 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1733 "vmcs_set_bits does not support 64-bit fields");
1734 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1737 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1739 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1742 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1744 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1745 vmx
->vm_entry_controls_shadow
= val
;
1748 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1750 if (vmx
->vm_entry_controls_shadow
!= val
)
1751 vm_entry_controls_init(vmx
, val
);
1754 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1756 return vmx
->vm_entry_controls_shadow
;
1760 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1762 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1765 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1767 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1770 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1772 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1775 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1777 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1778 vmx
->vm_exit_controls_shadow
= val
;
1781 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1783 if (vmx
->vm_exit_controls_shadow
!= val
)
1784 vm_exit_controls_init(vmx
, val
);
1787 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1789 return vmx
->vm_exit_controls_shadow
;
1793 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1795 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1798 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1800 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1803 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1805 vmx
->segment_cache
.bitmask
= 0;
1808 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1812 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1814 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1815 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1816 vmx
->segment_cache
.bitmask
= 0;
1818 ret
= vmx
->segment_cache
.bitmask
& mask
;
1819 vmx
->segment_cache
.bitmask
|= mask
;
1823 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1825 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1827 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1828 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1832 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1834 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1836 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1837 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1841 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1843 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1845 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1846 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1850 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1855 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1859 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1863 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1864 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1865 if ((vcpu
->guest_debug
&
1866 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1867 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1868 eb
|= 1u << BP_VECTOR
;
1869 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1872 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1874 /* When we are running a nested L2 guest and L1 specified for it a
1875 * certain exception bitmap, we must trap the same exceptions and pass
1876 * them to L1. When running L2, we will only handle the exceptions
1877 * specified above if L1 did not want them.
1879 if (is_guest_mode(vcpu
))
1880 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1882 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1885 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1886 unsigned long entry
, unsigned long exit
)
1888 vm_entry_controls_clearbit(vmx
, entry
);
1889 vm_exit_controls_clearbit(vmx
, exit
);
1892 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1895 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1899 if (cpu_has_load_ia32_efer
) {
1900 clear_atomic_switch_msr_special(vmx
,
1901 VM_ENTRY_LOAD_IA32_EFER
,
1902 VM_EXIT_LOAD_IA32_EFER
);
1906 case MSR_CORE_PERF_GLOBAL_CTRL
:
1907 if (cpu_has_load_perf_global_ctrl
) {
1908 clear_atomic_switch_msr_special(vmx
,
1909 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1910 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1916 for (i
= 0; i
< m
->nr
; ++i
)
1917 if (m
->guest
[i
].index
== msr
)
1923 m
->guest
[i
] = m
->guest
[m
->nr
];
1924 m
->host
[i
] = m
->host
[m
->nr
];
1925 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1926 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1929 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1930 unsigned long entry
, unsigned long exit
,
1931 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1932 u64 guest_val
, u64 host_val
)
1934 vmcs_write64(guest_val_vmcs
, guest_val
);
1935 vmcs_write64(host_val_vmcs
, host_val
);
1936 vm_entry_controls_setbit(vmx
, entry
);
1937 vm_exit_controls_setbit(vmx
, exit
);
1940 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1941 u64 guest_val
, u64 host_val
)
1944 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1948 if (cpu_has_load_ia32_efer
) {
1949 add_atomic_switch_msr_special(vmx
,
1950 VM_ENTRY_LOAD_IA32_EFER
,
1951 VM_EXIT_LOAD_IA32_EFER
,
1954 guest_val
, host_val
);
1958 case MSR_CORE_PERF_GLOBAL_CTRL
:
1959 if (cpu_has_load_perf_global_ctrl
) {
1960 add_atomic_switch_msr_special(vmx
,
1961 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1962 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1963 GUEST_IA32_PERF_GLOBAL_CTRL
,
1964 HOST_IA32_PERF_GLOBAL_CTRL
,
1965 guest_val
, host_val
);
1969 case MSR_IA32_PEBS_ENABLE
:
1970 /* PEBS needs a quiescent period after being disabled (to write
1971 * a record). Disabling PEBS through VMX MSR swapping doesn't
1972 * provide that period, so a CPU could write host's record into
1975 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1978 for (i
= 0; i
< m
->nr
; ++i
)
1979 if (m
->guest
[i
].index
== msr
)
1982 if (i
== NR_AUTOLOAD_MSRS
) {
1983 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1984 "Can't add msr %x\n", msr
);
1986 } else if (i
== m
->nr
) {
1988 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1989 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1992 m
->guest
[i
].index
= msr
;
1993 m
->guest
[i
].value
= guest_val
;
1994 m
->host
[i
].index
= msr
;
1995 m
->host
[i
].value
= host_val
;
1998 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2000 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2001 u64 ignore_bits
= 0;
2005 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2006 * host CPUID is more efficient than testing guest CPUID
2007 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2009 if (boot_cpu_has(X86_FEATURE_SMEP
))
2010 guest_efer
|= EFER_NX
;
2011 else if (!(guest_efer
& EFER_NX
))
2012 ignore_bits
|= EFER_NX
;
2016 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2018 ignore_bits
|= EFER_SCE
;
2019 #ifdef CONFIG_X86_64
2020 ignore_bits
|= EFER_LMA
| EFER_LME
;
2021 /* SCE is meaningful only in long mode on Intel */
2022 if (guest_efer
& EFER_LMA
)
2023 ignore_bits
&= ~(u64
)EFER_SCE
;
2026 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2029 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2030 * On CPUs that support "load IA32_EFER", always switch EFER
2031 * atomically, since it's faster than switching it manually.
2033 if (cpu_has_load_ia32_efer
||
2034 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2035 if (!(guest_efer
& EFER_LMA
))
2036 guest_efer
&= ~EFER_LME
;
2037 if (guest_efer
!= host_efer
)
2038 add_atomic_switch_msr(vmx
, MSR_EFER
,
2039 guest_efer
, host_efer
);
2042 guest_efer
&= ~ignore_bits
;
2043 guest_efer
|= host_efer
& ignore_bits
;
2045 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2046 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2052 #ifdef CONFIG_X86_32
2054 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2055 * VMCS rather than the segment table. KVM uses this helper to figure
2056 * out the current bases to poke them into the VMCS before entry.
2058 static unsigned long segment_base(u16 selector
)
2060 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2061 struct desc_struct
*table
;
2064 if (!(selector
& ~SEGMENT_RPL_MASK
))
2067 table
= (struct desc_struct
*)gdt
->address
;
2069 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2070 u16 ldt_selector
= kvm_read_ldt();
2072 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2075 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2077 v
= get_desc_base(&table
[selector
>> 3]);
2082 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2087 if (vmx
->host_state
.loaded
)
2090 vmx
->host_state
.loaded
= 1;
2092 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2093 * allow segment selectors with cpl > 0 or ti == 1.
2095 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2096 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2097 savesegment(fs
, vmx
->host_state
.fs_sel
);
2098 if (!(vmx
->host_state
.fs_sel
& 7)) {
2099 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2100 vmx
->host_state
.fs_reload_needed
= 0;
2102 vmcs_write16(HOST_FS_SELECTOR
, 0);
2103 vmx
->host_state
.fs_reload_needed
= 1;
2105 savesegment(gs
, vmx
->host_state
.gs_sel
);
2106 if (!(vmx
->host_state
.gs_sel
& 7))
2107 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2109 vmcs_write16(HOST_GS_SELECTOR
, 0);
2110 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2113 #ifdef CONFIG_X86_64
2114 savesegment(ds
, vmx
->host_state
.ds_sel
);
2115 savesegment(es
, vmx
->host_state
.es_sel
);
2118 #ifdef CONFIG_X86_64
2119 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2120 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2122 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2123 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2126 #ifdef CONFIG_X86_64
2127 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2128 if (is_long_mode(&vmx
->vcpu
))
2129 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2131 if (boot_cpu_has(X86_FEATURE_MPX
))
2132 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2133 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2134 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2135 vmx
->guest_msrs
[i
].data
,
2136 vmx
->guest_msrs
[i
].mask
);
2139 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2141 if (!vmx
->host_state
.loaded
)
2144 ++vmx
->vcpu
.stat
.host_state_reload
;
2145 vmx
->host_state
.loaded
= 0;
2146 #ifdef CONFIG_X86_64
2147 if (is_long_mode(&vmx
->vcpu
))
2148 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2150 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2151 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2152 #ifdef CONFIG_X86_64
2153 load_gs_index(vmx
->host_state
.gs_sel
);
2155 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2158 if (vmx
->host_state
.fs_reload_needed
)
2159 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2160 #ifdef CONFIG_X86_64
2161 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2162 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2163 loadsegment(es
, vmx
->host_state
.es_sel
);
2166 invalidate_tss_limit();
2167 #ifdef CONFIG_X86_64
2168 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2170 if (vmx
->host_state
.msr_host_bndcfgs
)
2171 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2172 load_gdt(this_cpu_ptr(&host_gdt
));
2175 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2178 __vmx_load_host_state(vmx
);
2182 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2184 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2185 struct pi_desc old
, new;
2188 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2189 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2190 !kvm_vcpu_apicv_active(vcpu
))
2194 old
.control
= new.control
= pi_desc
->control
;
2197 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2198 * are two possible cases:
2199 * 1. After running 'pre_block', context switch
2200 * happened. For this case, 'sn' was set in
2201 * vmx_vcpu_put(), so we need to clear it here.
2202 * 2. After running 'pre_block', we were blocked,
2203 * and woken up by some other guy. For this case,
2204 * we don't need to do anything, 'pi_post_block'
2205 * will do everything for us. However, we cannot
2206 * check whether it is case #1 or case #2 here
2207 * (maybe, not needed), so we also clear sn here,
2208 * I think it is not a big deal.
2210 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2211 if (vcpu
->cpu
!= cpu
) {
2212 dest
= cpu_physical_id(cpu
);
2214 if (x2apic_enabled())
2217 new.ndst
= (dest
<< 8) & 0xFF00;
2220 /* set 'NV' to 'notification vector' */
2221 new.nv
= POSTED_INTR_VECTOR
;
2224 /* Allow posting non-urgent interrupts */
2226 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2227 new.control
) != old
.control
);
2230 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2232 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2233 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2237 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2238 * vcpu mutex is already taken.
2240 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2242 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2243 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2244 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2247 kvm_cpu_vmxon(phys_addr
);
2248 else if (!already_loaded
)
2249 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2251 if (!already_loaded
) {
2252 local_irq_disable();
2253 crash_disable_local_vmclear(cpu
);
2256 * Read loaded_vmcs->cpu should be before fetching
2257 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2258 * See the comments in __loaded_vmcs_clear().
2262 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2263 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2264 crash_enable_local_vmclear(cpu
);
2268 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2269 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2270 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2273 if (!already_loaded
) {
2274 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2275 unsigned long sysenter_esp
;
2277 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2280 * Linux uses per-cpu TSS and GDT, so set these when switching
2281 * processors. See 22.2.4.
2283 vmcs_writel(HOST_TR_BASE
,
2284 (unsigned long)this_cpu_ptr(&cpu_tss
));
2285 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
);
2288 * VM exits change the host TR limit to 0x67 after a VM
2289 * exit. This is okay, since 0x67 covers everything except
2290 * the IO bitmap and have have code to handle the IO bitmap
2291 * being lost after a VM exit.
2293 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2295 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2296 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2298 vmx
->loaded_vmcs
->cpu
= cpu
;
2301 /* Setup TSC multiplier */
2302 if (kvm_has_tsc_control
&&
2303 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2304 decache_tsc_multiplier(vmx
);
2306 vmx_vcpu_pi_load(vcpu
, cpu
);
2307 vmx
->host_pkru
= read_pkru();
2310 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2312 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2314 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2315 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2316 !kvm_vcpu_apicv_active(vcpu
))
2319 /* Set SN when the vCPU is preempted */
2320 if (vcpu
->preempted
)
2324 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2326 vmx_vcpu_pi_put(vcpu
);
2328 __vmx_load_host_state(to_vmx(vcpu
));
2329 if (!vmm_exclusive
) {
2330 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2336 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2339 * Return the cr0 value that a nested guest would read. This is a combination
2340 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2341 * its hypervisor (cr0_read_shadow).
2343 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2345 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2346 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2348 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2350 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2351 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2354 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2356 unsigned long rflags
, save_rflags
;
2358 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2359 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2360 rflags
= vmcs_readl(GUEST_RFLAGS
);
2361 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2362 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2363 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2364 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2366 to_vmx(vcpu
)->rflags
= rflags
;
2368 return to_vmx(vcpu
)->rflags
;
2371 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2373 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2374 to_vmx(vcpu
)->rflags
= rflags
;
2375 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2376 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2377 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2379 vmcs_writel(GUEST_RFLAGS
, rflags
);
2382 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2384 return to_vmx(vcpu
)->guest_pkru
;
2387 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2389 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2392 if (interruptibility
& GUEST_INTR_STATE_STI
)
2393 ret
|= KVM_X86_SHADOW_INT_STI
;
2394 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2395 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2400 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2402 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2403 u32 interruptibility
= interruptibility_old
;
2405 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2407 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2408 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2409 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2410 interruptibility
|= GUEST_INTR_STATE_STI
;
2412 if ((interruptibility
!= interruptibility_old
))
2413 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2416 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2420 rip
= kvm_rip_read(vcpu
);
2421 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2422 kvm_rip_write(vcpu
, rip
);
2424 /* skipping an emulated instruction also counts */
2425 vmx_set_interrupt_shadow(vcpu
, 0);
2429 * KVM wants to inject page-faults which it got to the guest. This function
2430 * checks whether in a nested guest, we need to inject them to L1 or L2.
2432 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2434 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2436 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2439 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2440 vmcs_read32(VM_EXIT_INTR_INFO
),
2441 vmcs_readl(EXIT_QUALIFICATION
));
2445 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2446 bool has_error_code
, u32 error_code
,
2449 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2450 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2452 if (!reinject
&& is_guest_mode(vcpu
) &&
2453 nested_vmx_check_exception(vcpu
, nr
))
2456 if (has_error_code
) {
2457 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2458 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2461 if (vmx
->rmode
.vm86_active
) {
2463 if (kvm_exception_is_soft(nr
))
2464 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2465 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2466 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2470 if (kvm_exception_is_soft(nr
)) {
2471 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2472 vmx
->vcpu
.arch
.event_exit_inst_len
);
2473 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2475 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2477 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2480 static bool vmx_rdtscp_supported(void)
2482 return cpu_has_vmx_rdtscp();
2485 static bool vmx_invpcid_supported(void)
2487 return cpu_has_vmx_invpcid() && enable_ept
;
2491 * Swap MSR entry in host/guest MSR entry array.
2493 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2495 struct shared_msr_entry tmp
;
2497 tmp
= vmx
->guest_msrs
[to
];
2498 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2499 vmx
->guest_msrs
[from
] = tmp
;
2502 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2504 unsigned long *msr_bitmap
;
2506 if (is_guest_mode(vcpu
))
2507 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2508 else if (cpu_has_secondary_exec_ctrls() &&
2509 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2510 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2511 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2512 if (is_long_mode(vcpu
))
2513 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2515 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2517 if (is_long_mode(vcpu
))
2518 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2520 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2523 if (is_long_mode(vcpu
))
2524 msr_bitmap
= vmx_msr_bitmap_longmode
;
2526 msr_bitmap
= vmx_msr_bitmap_legacy
;
2529 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2533 * Set up the vmcs to automatically save and restore system
2534 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2535 * mode, as fiddling with msrs is very expensive.
2537 static void setup_msrs(struct vcpu_vmx
*vmx
)
2539 int save_nmsrs
, index
;
2542 #ifdef CONFIG_X86_64
2543 if (is_long_mode(&vmx
->vcpu
)) {
2544 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2546 move_msr_up(vmx
, index
, save_nmsrs
++);
2547 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2549 move_msr_up(vmx
, index
, save_nmsrs
++);
2550 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2552 move_msr_up(vmx
, index
, save_nmsrs
++);
2553 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2554 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2555 move_msr_up(vmx
, index
, save_nmsrs
++);
2557 * MSR_STAR is only needed on long mode guests, and only
2558 * if efer.sce is enabled.
2560 index
= __find_msr_index(vmx
, MSR_STAR
);
2561 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2562 move_msr_up(vmx
, index
, save_nmsrs
++);
2565 index
= __find_msr_index(vmx
, MSR_EFER
);
2566 if (index
>= 0 && update_transition_efer(vmx
, index
))
2567 move_msr_up(vmx
, index
, save_nmsrs
++);
2569 vmx
->save_nmsrs
= save_nmsrs
;
2571 if (cpu_has_vmx_msr_bitmap())
2572 vmx_set_msr_bitmap(&vmx
->vcpu
);
2576 * reads and returns guest's timestamp counter "register"
2577 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2578 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2580 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2582 u64 host_tsc
, tsc_offset
;
2585 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2586 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2590 * writes 'offset' into guest's timestamp counter offset register
2592 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2594 if (is_guest_mode(vcpu
)) {
2596 * We're here if L1 chose not to trap WRMSR to TSC. According
2597 * to the spec, this should set L1's TSC; The offset that L1
2598 * set for L2 remains unchanged, and still needs to be added
2599 * to the newly set TSC to get L2's TSC.
2601 struct vmcs12
*vmcs12
;
2602 /* recalculate vmcs02.TSC_OFFSET: */
2603 vmcs12
= get_vmcs12(vcpu
);
2604 vmcs_write64(TSC_OFFSET
, offset
+
2605 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2606 vmcs12
->tsc_offset
: 0));
2608 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2609 vmcs_read64(TSC_OFFSET
), offset
);
2610 vmcs_write64(TSC_OFFSET
, offset
);
2614 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2616 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2617 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2621 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2622 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2623 * all guests if the "nested" module option is off, and can also be disabled
2624 * for a single guest by disabling its VMX cpuid bit.
2626 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2628 return nested
&& guest_cpuid_has_vmx(vcpu
);
2632 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2633 * returned for the various VMX controls MSRs when nested VMX is enabled.
2634 * The same values should also be used to verify that vmcs12 control fields are
2635 * valid during nested entry from L1 to L2.
2636 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2637 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2638 * bit in the high half is on if the corresponding bit in the control field
2639 * may be on. See also vmx_control_verify().
2641 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2644 * Note that as a general rule, the high half of the MSRs (bits in
2645 * the control fields which may be 1) should be initialized by the
2646 * intersection of the underlying hardware's MSR (i.e., features which
2647 * can be supported) and the list of features we want to expose -
2648 * because they are known to be properly supported in our code.
2649 * Also, usually, the low half of the MSRs (bits which must be 1) can
2650 * be set to 0, meaning that L1 may turn off any of these bits. The
2651 * reason is that if one of these bits is necessary, it will appear
2652 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2653 * fields of vmcs01 and vmcs02, will turn these bits off - and
2654 * nested_vmx_exit_handled() will not pass related exits to L1.
2655 * These rules have exceptions below.
2658 /* pin-based controls */
2659 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2660 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2661 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2662 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2663 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2664 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2665 PIN_BASED_EXT_INTR_MASK
|
2666 PIN_BASED_NMI_EXITING
|
2667 PIN_BASED_VIRTUAL_NMIS
;
2668 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2669 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2670 PIN_BASED_VMX_PREEMPTION_TIMER
;
2671 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2672 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2673 PIN_BASED_POSTED_INTR
;
2676 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2677 vmx
->nested
.nested_vmx_exit_ctls_low
,
2678 vmx
->nested
.nested_vmx_exit_ctls_high
);
2679 vmx
->nested
.nested_vmx_exit_ctls_low
=
2680 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2682 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2683 #ifdef CONFIG_X86_64
2684 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2686 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2687 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2688 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2689 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2690 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2692 if (kvm_mpx_supported())
2693 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2695 /* We support free control of debug control saving. */
2696 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2698 /* entry controls */
2699 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2700 vmx
->nested
.nested_vmx_entry_ctls_low
,
2701 vmx
->nested
.nested_vmx_entry_ctls_high
);
2702 vmx
->nested
.nested_vmx_entry_ctls_low
=
2703 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2704 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2705 #ifdef CONFIG_X86_64
2706 VM_ENTRY_IA32E_MODE
|
2708 VM_ENTRY_LOAD_IA32_PAT
;
2709 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2710 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2711 if (kvm_mpx_supported())
2712 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2714 /* We support free control of debug control loading. */
2715 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2717 /* cpu-based controls */
2718 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2719 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2720 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2721 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2722 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2723 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2724 CPU_BASED_VIRTUAL_INTR_PENDING
|
2725 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2726 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2727 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2728 CPU_BASED_CR3_STORE_EXITING
|
2729 #ifdef CONFIG_X86_64
2730 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2732 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2733 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2734 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2735 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2736 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2738 * We can allow some features even when not supported by the
2739 * hardware. For example, L1 can specify an MSR bitmap - and we
2740 * can use it to avoid exits to L1 - even when L0 runs L2
2741 * without MSR bitmaps.
2743 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2744 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2745 CPU_BASED_USE_MSR_BITMAPS
;
2747 /* We support free control of CR3 access interception. */
2748 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2749 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2751 /* secondary cpu-based controls */
2752 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2753 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2754 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2755 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2756 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2757 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2758 SECONDARY_EXEC_RDTSCP
|
2759 SECONDARY_EXEC_DESC
|
2760 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2761 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2762 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2763 SECONDARY_EXEC_WBINVD_EXITING
|
2764 SECONDARY_EXEC_XSAVES
;
2767 /* nested EPT: emulate EPT also to L1 */
2768 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2769 SECONDARY_EXEC_ENABLE_EPT
;
2770 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2771 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2773 if (cpu_has_vmx_ept_execute_only())
2774 vmx
->nested
.nested_vmx_ept_caps
|=
2775 VMX_EPT_EXECUTE_ONLY_BIT
;
2776 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2777 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2778 VMX_EPT_EXTENT_CONTEXT_BIT
;
2780 vmx
->nested
.nested_vmx_ept_caps
= 0;
2783 * Old versions of KVM use the single-context version without
2784 * checking for support, so declare that it is supported even
2785 * though it is treated as global context. The alternative is
2786 * not failing the single-context invvpid, and it is worse.
2789 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2790 SECONDARY_EXEC_ENABLE_VPID
;
2791 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2792 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2794 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2796 if (enable_unrestricted_guest
)
2797 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2798 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2800 /* miscellaneous data */
2801 rdmsr(MSR_IA32_VMX_MISC
,
2802 vmx
->nested
.nested_vmx_misc_low
,
2803 vmx
->nested
.nested_vmx_misc_high
);
2804 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2805 vmx
->nested
.nested_vmx_misc_low
|=
2806 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2807 VMX_MISC_ACTIVITY_HLT
;
2808 vmx
->nested
.nested_vmx_misc_high
= 0;
2811 * This MSR reports some information about VMX support. We
2812 * should return information about the VMX we emulate for the
2813 * guest, and the VMCS structure we give it - not about the
2814 * VMX support of the underlying hardware.
2816 vmx
->nested
.nested_vmx_basic
=
2818 VMX_BASIC_TRUE_CTLS
|
2819 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2820 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2822 if (cpu_has_vmx_basic_inout())
2823 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2826 * These MSRs specify bits which the guest must keep fixed on
2827 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2828 * We picked the standard core2 setting.
2830 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2831 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2832 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2833 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2835 /* These MSRs specify bits which the guest must keep fixed off. */
2836 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2837 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2839 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2840 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2844 * if fixed0[i] == 1: val[i] must be 1
2845 * if fixed1[i] == 0: val[i] must be 0
2847 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2849 return ((val
& fixed1
) | fixed0
) == val
;
2852 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2854 return fixed_bits_valid(control
, low
, high
);
2857 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2859 return low
| ((u64
)high
<< 32);
2862 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2867 return (superset
| subset
) == superset
;
2870 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2872 const u64 feature_and_reserved
=
2873 /* feature (except bit 48; see below) */
2874 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2876 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2877 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2879 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2883 * KVM does not emulate a version of VMX that constrains physical
2884 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2886 if (data
& BIT_ULL(48))
2889 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2890 vmx_basic_vmcs_revision_id(data
))
2893 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2896 vmx
->nested
.nested_vmx_basic
= data
;
2901 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2906 switch (msr_index
) {
2907 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2908 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2909 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2911 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2912 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2913 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2915 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2916 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2917 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2919 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2920 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2921 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2923 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2924 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2925 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2931 supported
= vmx_control_msr(*lowp
, *highp
);
2933 /* Check must-be-1 bits are still 1. */
2934 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2937 /* Check must-be-0 bits are still 0. */
2938 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2942 *highp
= data
>> 32;
2946 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2948 const u64 feature_and_reserved_bits
=
2950 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2951 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2953 GENMASK_ULL(13, 9) | BIT_ULL(31);
2956 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
2957 vmx
->nested
.nested_vmx_misc_high
);
2959 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2962 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
2963 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2964 vmx_misc_preemption_timer_rate(data
) !=
2965 vmx_misc_preemption_timer_rate(vmx_misc
))
2968 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2971 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2974 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2977 vmx
->nested
.nested_vmx_misc_low
= data
;
2978 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
2982 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2984 u64 vmx_ept_vpid_cap
;
2986 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
2987 vmx
->nested
.nested_vmx_vpid_caps
);
2989 /* Every bit is either reserved or a feature bit. */
2990 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2993 vmx
->nested
.nested_vmx_ept_caps
= data
;
2994 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
2998 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3002 switch (msr_index
) {
3003 case MSR_IA32_VMX_CR0_FIXED0
:
3004 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3006 case MSR_IA32_VMX_CR4_FIXED0
:
3007 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3014 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3015 * must be 1 in the restored value.
3017 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3025 * Called when userspace is restoring VMX MSRs.
3027 * Returns 0 on success, non-0 otherwise.
3029 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3031 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3033 switch (msr_index
) {
3034 case MSR_IA32_VMX_BASIC
:
3035 return vmx_restore_vmx_basic(vmx
, data
);
3036 case MSR_IA32_VMX_PINBASED_CTLS
:
3037 case MSR_IA32_VMX_PROCBASED_CTLS
:
3038 case MSR_IA32_VMX_EXIT_CTLS
:
3039 case MSR_IA32_VMX_ENTRY_CTLS
:
3041 * The "non-true" VMX capability MSRs are generated from the
3042 * "true" MSRs, so we do not support restoring them directly.
3044 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3045 * should restore the "true" MSRs with the must-be-1 bits
3046 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3047 * DEFAULT SETTINGS".
3050 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3051 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3052 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3053 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3054 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3055 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3056 case MSR_IA32_VMX_MISC
:
3057 return vmx_restore_vmx_misc(vmx
, data
);
3058 case MSR_IA32_VMX_CR0_FIXED0
:
3059 case MSR_IA32_VMX_CR4_FIXED0
:
3060 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3061 case MSR_IA32_VMX_CR0_FIXED1
:
3062 case MSR_IA32_VMX_CR4_FIXED1
:
3064 * These MSRs are generated based on the vCPU's CPUID, so we
3065 * do not support restoring them directly.
3068 case MSR_IA32_VMX_EPT_VPID_CAP
:
3069 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3070 case MSR_IA32_VMX_VMCS_ENUM
:
3071 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3075 * The rest of the VMX capability MSRs do not support restore.
3081 /* Returns 0 on success, non-0 otherwise. */
3082 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3086 switch (msr_index
) {
3087 case MSR_IA32_VMX_BASIC
:
3088 *pdata
= vmx
->nested
.nested_vmx_basic
;
3090 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3091 case MSR_IA32_VMX_PINBASED_CTLS
:
3092 *pdata
= vmx_control_msr(
3093 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3094 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3095 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3096 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3098 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3099 case MSR_IA32_VMX_PROCBASED_CTLS
:
3100 *pdata
= vmx_control_msr(
3101 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3102 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3103 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3104 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3106 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3107 case MSR_IA32_VMX_EXIT_CTLS
:
3108 *pdata
= vmx_control_msr(
3109 vmx
->nested
.nested_vmx_exit_ctls_low
,
3110 vmx
->nested
.nested_vmx_exit_ctls_high
);
3111 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3112 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3114 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3115 case MSR_IA32_VMX_ENTRY_CTLS
:
3116 *pdata
= vmx_control_msr(
3117 vmx
->nested
.nested_vmx_entry_ctls_low
,
3118 vmx
->nested
.nested_vmx_entry_ctls_high
);
3119 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3120 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3122 case MSR_IA32_VMX_MISC
:
3123 *pdata
= vmx_control_msr(
3124 vmx
->nested
.nested_vmx_misc_low
,
3125 vmx
->nested
.nested_vmx_misc_high
);
3127 case MSR_IA32_VMX_CR0_FIXED0
:
3128 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3130 case MSR_IA32_VMX_CR0_FIXED1
:
3131 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3133 case MSR_IA32_VMX_CR4_FIXED0
:
3134 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3136 case MSR_IA32_VMX_CR4_FIXED1
:
3137 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3139 case MSR_IA32_VMX_VMCS_ENUM
:
3140 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3142 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3143 *pdata
= vmx_control_msr(
3144 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3145 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3147 case MSR_IA32_VMX_EPT_VPID_CAP
:
3148 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3149 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3158 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3161 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3163 return !(val
& ~valid_bits
);
3167 * Reads an msr value (of 'msr_index') into 'pdata'.
3168 * Returns 0 on success, non-0 otherwise.
3169 * Assumes vcpu_load() was already called.
3171 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3173 struct shared_msr_entry
*msr
;
3175 switch (msr_info
->index
) {
3176 #ifdef CONFIG_X86_64
3178 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3181 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3183 case MSR_KERNEL_GS_BASE
:
3184 vmx_load_host_state(to_vmx(vcpu
));
3185 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3189 return kvm_get_msr_common(vcpu
, msr_info
);
3191 msr_info
->data
= guest_read_tsc(vcpu
);
3193 case MSR_IA32_SYSENTER_CS
:
3194 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3196 case MSR_IA32_SYSENTER_EIP
:
3197 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3199 case MSR_IA32_SYSENTER_ESP
:
3200 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3202 case MSR_IA32_BNDCFGS
:
3203 if (!kvm_mpx_supported())
3205 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3207 case MSR_IA32_MCG_EXT_CTL
:
3208 if (!msr_info
->host_initiated
&&
3209 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3210 FEATURE_CONTROL_LMCE
))
3212 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3214 case MSR_IA32_FEATURE_CONTROL
:
3215 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3217 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3218 if (!nested_vmx_allowed(vcpu
))
3220 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3222 if (!vmx_xsaves_supported())
3224 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3227 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3229 /* Otherwise falls through */
3231 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3233 msr_info
->data
= msr
->data
;
3236 return kvm_get_msr_common(vcpu
, msr_info
);
3242 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3245 * Writes msr value into into the appropriate "register".
3246 * Returns 0 on success, non-0 otherwise.
3247 * Assumes vcpu_load() was already called.
3249 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3251 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3252 struct shared_msr_entry
*msr
;
3254 u32 msr_index
= msr_info
->index
;
3255 u64 data
= msr_info
->data
;
3257 switch (msr_index
) {
3259 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3261 #ifdef CONFIG_X86_64
3263 vmx_segment_cache_clear(vmx
);
3264 vmcs_writel(GUEST_FS_BASE
, data
);
3267 vmx_segment_cache_clear(vmx
);
3268 vmcs_writel(GUEST_GS_BASE
, data
);
3270 case MSR_KERNEL_GS_BASE
:
3271 vmx_load_host_state(vmx
);
3272 vmx
->msr_guest_kernel_gs_base
= data
;
3275 case MSR_IA32_SYSENTER_CS
:
3276 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3278 case MSR_IA32_SYSENTER_EIP
:
3279 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3281 case MSR_IA32_SYSENTER_ESP
:
3282 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3284 case MSR_IA32_BNDCFGS
:
3285 if (!kvm_mpx_supported())
3287 vmcs_write64(GUEST_BNDCFGS
, data
);
3290 kvm_write_tsc(vcpu
, msr_info
);
3292 case MSR_IA32_CR_PAT
:
3293 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3294 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3296 vmcs_write64(GUEST_IA32_PAT
, data
);
3297 vcpu
->arch
.pat
= data
;
3300 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3302 case MSR_IA32_TSC_ADJUST
:
3303 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3305 case MSR_IA32_MCG_EXT_CTL
:
3306 if ((!msr_info
->host_initiated
&&
3307 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3308 FEATURE_CONTROL_LMCE
)) ||
3309 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3311 vcpu
->arch
.mcg_ext_ctl
= data
;
3313 case MSR_IA32_FEATURE_CONTROL
:
3314 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3315 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3316 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3318 vmx
->msr_ia32_feature_control
= data
;
3319 if (msr_info
->host_initiated
&& data
== 0)
3320 vmx_leave_nested(vcpu
);
3322 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3323 if (!msr_info
->host_initiated
)
3324 return 1; /* they are read-only */
3325 if (!nested_vmx_allowed(vcpu
))
3327 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3329 if (!vmx_xsaves_supported())
3332 * The only supported bit as of Skylake is bit 8, but
3333 * it is not supported on KVM.
3337 vcpu
->arch
.ia32_xss
= data
;
3338 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3339 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3340 vcpu
->arch
.ia32_xss
, host_xss
);
3342 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3345 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3347 /* Check reserved bit, higher 32 bits should be zero */
3348 if ((data
>> 32) != 0)
3350 /* Otherwise falls through */
3352 msr
= find_msr_entry(vmx
, msr_index
);
3354 u64 old_msr_data
= msr
->data
;
3356 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3358 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3362 msr
->data
= old_msr_data
;
3366 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3372 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3374 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3377 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3380 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3382 case VCPU_EXREG_PDPTR
:
3384 ept_save_pdptrs(vcpu
);
3391 static __init
int cpu_has_kvm_support(void)
3393 return cpu_has_vmx();
3396 static __init
int vmx_disabled_by_bios(void)
3400 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3401 if (msr
& FEATURE_CONTROL_LOCKED
) {
3402 /* launched w/ TXT and VMX disabled */
3403 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3406 /* launched w/o TXT and VMX only enabled w/ TXT */
3407 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3408 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3409 && !tboot_enabled()) {
3410 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3411 "activate TXT before enabling KVM\n");
3414 /* launched w/o TXT and VMX disabled */
3415 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3416 && !tboot_enabled())
3423 static void kvm_cpu_vmxon(u64 addr
)
3425 intel_pt_handle_vmx(1);
3427 asm volatile (ASM_VMX_VMXON_RAX
3428 : : "a"(&addr
), "m"(addr
)
3432 static int hardware_enable(void)
3434 int cpu
= raw_smp_processor_id();
3435 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3438 if (cr4_read_shadow() & X86_CR4_VMXE
)
3441 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3442 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3443 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3446 * Now we can enable the vmclear operation in kdump
3447 * since the loaded_vmcss_on_cpu list on this cpu
3448 * has been initialized.
3450 * Though the cpu is not in VMX operation now, there
3451 * is no problem to enable the vmclear operation
3452 * for the loaded_vmcss_on_cpu list is empty!
3454 crash_enable_local_vmclear(cpu
);
3456 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3458 test_bits
= FEATURE_CONTROL_LOCKED
;
3459 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3460 if (tboot_enabled())
3461 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3463 if ((old
& test_bits
) != test_bits
) {
3464 /* enable and lock */
3465 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3467 cr4_set_bits(X86_CR4_VMXE
);
3469 if (vmm_exclusive
) {
3470 kvm_cpu_vmxon(phys_addr
);
3474 native_store_gdt(this_cpu_ptr(&host_gdt
));
3479 static void vmclear_local_loaded_vmcss(void)
3481 int cpu
= raw_smp_processor_id();
3482 struct loaded_vmcs
*v
, *n
;
3484 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3485 loaded_vmcss_on_cpu_link
)
3486 __loaded_vmcs_clear(v
);
3490 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3493 static void kvm_cpu_vmxoff(void)
3495 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3497 intel_pt_handle_vmx(0);
3500 static void hardware_disable(void)
3502 if (vmm_exclusive
) {
3503 vmclear_local_loaded_vmcss();
3506 cr4_clear_bits(X86_CR4_VMXE
);
3509 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3510 u32 msr
, u32
*result
)
3512 u32 vmx_msr_low
, vmx_msr_high
;
3513 u32 ctl
= ctl_min
| ctl_opt
;
3515 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3517 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3518 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3520 /* Ensure minimum (required) set of control bits are supported. */
3528 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3530 u32 vmx_msr_low
, vmx_msr_high
;
3532 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3533 return vmx_msr_high
& ctl
;
3536 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3538 u32 vmx_msr_low
, vmx_msr_high
;
3539 u32 min
, opt
, min2
, opt2
;
3540 u32 _pin_based_exec_control
= 0;
3541 u32 _cpu_based_exec_control
= 0;
3542 u32 _cpu_based_2nd_exec_control
= 0;
3543 u32 _vmexit_control
= 0;
3544 u32 _vmentry_control
= 0;
3546 min
= CPU_BASED_HLT_EXITING
|
3547 #ifdef CONFIG_X86_64
3548 CPU_BASED_CR8_LOAD_EXITING
|
3549 CPU_BASED_CR8_STORE_EXITING
|
3551 CPU_BASED_CR3_LOAD_EXITING
|
3552 CPU_BASED_CR3_STORE_EXITING
|
3553 CPU_BASED_USE_IO_BITMAPS
|
3554 CPU_BASED_MOV_DR_EXITING
|
3555 CPU_BASED_USE_TSC_OFFSETING
|
3556 CPU_BASED_MWAIT_EXITING
|
3557 CPU_BASED_MONITOR_EXITING
|
3558 CPU_BASED_INVLPG_EXITING
|
3559 CPU_BASED_RDPMC_EXITING
;
3561 opt
= CPU_BASED_TPR_SHADOW
|
3562 CPU_BASED_USE_MSR_BITMAPS
|
3563 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3564 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3565 &_cpu_based_exec_control
) < 0)
3567 #ifdef CONFIG_X86_64
3568 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3569 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3570 ~CPU_BASED_CR8_STORE_EXITING
;
3572 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3574 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3575 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3576 SECONDARY_EXEC_WBINVD_EXITING
|
3577 SECONDARY_EXEC_ENABLE_VPID
|
3578 SECONDARY_EXEC_ENABLE_EPT
|
3579 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3580 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3581 SECONDARY_EXEC_RDTSCP
|
3582 SECONDARY_EXEC_ENABLE_INVPCID
|
3583 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3584 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3585 SECONDARY_EXEC_SHADOW_VMCS
|
3586 SECONDARY_EXEC_XSAVES
|
3587 SECONDARY_EXEC_ENABLE_PML
|
3588 SECONDARY_EXEC_TSC_SCALING
;
3589 if (adjust_vmx_controls(min2
, opt2
,
3590 MSR_IA32_VMX_PROCBASED_CTLS2
,
3591 &_cpu_based_2nd_exec_control
) < 0)
3594 #ifndef CONFIG_X86_64
3595 if (!(_cpu_based_2nd_exec_control
&
3596 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3597 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3600 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3601 _cpu_based_2nd_exec_control
&= ~(
3602 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3603 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3604 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3606 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3607 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3609 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3610 CPU_BASED_CR3_STORE_EXITING
|
3611 CPU_BASED_INVLPG_EXITING
);
3612 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3613 vmx_capability
.ept
, vmx_capability
.vpid
);
3616 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3617 #ifdef CONFIG_X86_64
3618 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3620 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3621 VM_EXIT_CLEAR_BNDCFGS
;
3622 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3623 &_vmexit_control
) < 0)
3626 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3627 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3628 PIN_BASED_VMX_PREEMPTION_TIMER
;
3629 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3630 &_pin_based_exec_control
) < 0)
3633 if (cpu_has_broken_vmx_preemption_timer())
3634 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3635 if (!(_cpu_based_2nd_exec_control
&
3636 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3637 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3639 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3640 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3641 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3642 &_vmentry_control
) < 0)
3645 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3647 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3648 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3651 #ifdef CONFIG_X86_64
3652 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3653 if (vmx_msr_high
& (1u<<16))
3657 /* Require Write-Back (WB) memory type for VMCS accesses. */
3658 if (((vmx_msr_high
>> 18) & 15) != 6)
3661 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3662 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3663 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3664 vmcs_conf
->revision_id
= vmx_msr_low
;
3666 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3667 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3668 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3669 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3670 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3672 cpu_has_load_ia32_efer
=
3673 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3674 VM_ENTRY_LOAD_IA32_EFER
)
3675 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3676 VM_EXIT_LOAD_IA32_EFER
);
3678 cpu_has_load_perf_global_ctrl
=
3679 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3680 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3681 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3682 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3685 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3686 * but due to errata below it can't be used. Workaround is to use
3687 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3689 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3694 * BC86,AAY89,BD102 (model 44)
3698 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3699 switch (boot_cpu_data
.x86_model
) {
3705 cpu_has_load_perf_global_ctrl
= false;
3706 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3707 "does not work properly. Using workaround\n");
3714 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3715 rdmsrl(MSR_IA32_XSS
, host_xss
);
3720 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3722 int node
= cpu_to_node(cpu
);
3726 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3729 vmcs
= page_address(pages
);
3730 memset(vmcs
, 0, vmcs_config
.size
);
3731 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3735 static struct vmcs
*alloc_vmcs(void)
3737 return alloc_vmcs_cpu(raw_smp_processor_id());
3740 static void free_vmcs(struct vmcs
*vmcs
)
3742 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3746 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3748 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3750 if (!loaded_vmcs
->vmcs
)
3752 loaded_vmcs_clear(loaded_vmcs
);
3753 free_vmcs(loaded_vmcs
->vmcs
);
3754 loaded_vmcs
->vmcs
= NULL
;
3755 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3758 static void free_kvm_area(void)
3762 for_each_possible_cpu(cpu
) {
3763 free_vmcs(per_cpu(vmxarea
, cpu
));
3764 per_cpu(vmxarea
, cpu
) = NULL
;
3768 static void init_vmcs_shadow_fields(void)
3772 /* No checks for read only fields yet */
3774 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3775 switch (shadow_read_write_fields
[i
]) {
3777 if (!kvm_mpx_supported())
3785 shadow_read_write_fields
[j
] =
3786 shadow_read_write_fields
[i
];
3789 max_shadow_read_write_fields
= j
;
3791 /* shadowed fields guest access without vmexit */
3792 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3793 clear_bit(shadow_read_write_fields
[i
],
3794 vmx_vmwrite_bitmap
);
3795 clear_bit(shadow_read_write_fields
[i
],
3798 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3799 clear_bit(shadow_read_only_fields
[i
],
3803 static __init
int alloc_kvm_area(void)
3807 for_each_possible_cpu(cpu
) {
3810 vmcs
= alloc_vmcs_cpu(cpu
);
3816 per_cpu(vmxarea
, cpu
) = vmcs
;
3821 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3823 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3826 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3827 struct kvm_segment
*save
)
3829 if (!emulate_invalid_guest_state
) {
3831 * CS and SS RPL should be equal during guest entry according
3832 * to VMX spec, but in reality it is not always so. Since vcpu
3833 * is in the middle of the transition from real mode to
3834 * protected mode it is safe to assume that RPL 0 is a good
3837 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3838 save
->selector
&= ~SEGMENT_RPL_MASK
;
3839 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3842 vmx_set_segment(vcpu
, save
, seg
);
3845 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3847 unsigned long flags
;
3848 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3851 * Update real mode segment cache. It may be not up-to-date if sement
3852 * register was written while vcpu was in a guest mode.
3854 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3855 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3856 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3857 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3858 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3859 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3861 vmx
->rmode
.vm86_active
= 0;
3863 vmx_segment_cache_clear(vmx
);
3865 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3867 flags
= vmcs_readl(GUEST_RFLAGS
);
3868 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3869 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3870 vmcs_writel(GUEST_RFLAGS
, flags
);
3872 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3873 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3875 update_exception_bitmap(vcpu
);
3877 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3878 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3879 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3880 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3881 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3882 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3885 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3887 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3888 struct kvm_segment var
= *save
;
3891 if (seg
== VCPU_SREG_CS
)
3894 if (!emulate_invalid_guest_state
) {
3895 var
.selector
= var
.base
>> 4;
3896 var
.base
= var
.base
& 0xffff0;
3906 if (save
->base
& 0xf)
3907 printk_once(KERN_WARNING
"kvm: segment base is not "
3908 "paragraph aligned when entering "
3909 "protected mode (seg=%d)", seg
);
3912 vmcs_write16(sf
->selector
, var
.selector
);
3913 vmcs_writel(sf
->base
, var
.base
);
3914 vmcs_write32(sf
->limit
, var
.limit
);
3915 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3918 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3920 unsigned long flags
;
3921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3923 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3924 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3925 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3926 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3927 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3928 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3929 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3931 vmx
->rmode
.vm86_active
= 1;
3934 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3935 * vcpu. Warn the user that an update is overdue.
3937 if (!vcpu
->kvm
->arch
.tss_addr
)
3938 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3939 "called before entering vcpu\n");
3941 vmx_segment_cache_clear(vmx
);
3943 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3944 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3945 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3947 flags
= vmcs_readl(GUEST_RFLAGS
);
3948 vmx
->rmode
.save_rflags
= flags
;
3950 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3952 vmcs_writel(GUEST_RFLAGS
, flags
);
3953 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3954 update_exception_bitmap(vcpu
);
3956 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3957 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3958 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3959 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3960 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3961 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3963 kvm_mmu_reset_context(vcpu
);
3966 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3968 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3969 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3975 * Force kernel_gs_base reloading before EFER changes, as control
3976 * of this msr depends on is_long_mode().
3978 vmx_load_host_state(to_vmx(vcpu
));
3979 vcpu
->arch
.efer
= efer
;
3980 if (efer
& EFER_LMA
) {
3981 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3984 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3986 msr
->data
= efer
& ~EFER_LME
;
3991 #ifdef CONFIG_X86_64
3993 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3997 vmx_segment_cache_clear(to_vmx(vcpu
));
3999 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4000 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4001 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4003 vmcs_write32(GUEST_TR_AR_BYTES
,
4004 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4005 | VMX_AR_TYPE_BUSY_64_TSS
);
4007 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4010 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4012 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4013 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4018 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4020 vpid_sync_context(vpid
);
4022 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4024 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
4028 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4030 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4033 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4036 vmx_flush_tlb(vcpu
);
4039 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4041 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4043 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4044 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4047 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4049 if (enable_ept
&& is_paging(vcpu
))
4050 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4051 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4054 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4056 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4058 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4059 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4062 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4064 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4066 if (!test_bit(VCPU_EXREG_PDPTR
,
4067 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4070 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4071 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4072 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4073 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4074 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4078 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4080 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4082 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4083 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4084 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4085 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4086 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4089 __set_bit(VCPU_EXREG_PDPTR
,
4090 (unsigned long *)&vcpu
->arch
.regs_avail
);
4091 __set_bit(VCPU_EXREG_PDPTR
,
4092 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4095 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4097 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4098 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4099 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4101 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4102 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4103 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4104 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4106 return fixed_bits_valid(val
, fixed0
, fixed1
);
4109 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4111 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4112 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4114 return fixed_bits_valid(val
, fixed0
, fixed1
);
4117 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4119 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4120 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4122 return fixed_bits_valid(val
, fixed0
, fixed1
);
4125 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4126 #define nested_guest_cr4_valid nested_cr4_valid
4127 #define nested_host_cr4_valid nested_cr4_valid
4129 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4131 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4133 struct kvm_vcpu
*vcpu
)
4135 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4136 vmx_decache_cr3(vcpu
);
4137 if (!(cr0
& X86_CR0_PG
)) {
4138 /* From paging/starting to nonpaging */
4139 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4140 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4141 (CPU_BASED_CR3_LOAD_EXITING
|
4142 CPU_BASED_CR3_STORE_EXITING
));
4143 vcpu
->arch
.cr0
= cr0
;
4144 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4145 } else if (!is_paging(vcpu
)) {
4146 /* From nonpaging to paging */
4147 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4148 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4149 ~(CPU_BASED_CR3_LOAD_EXITING
|
4150 CPU_BASED_CR3_STORE_EXITING
));
4151 vcpu
->arch
.cr0
= cr0
;
4152 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4155 if (!(cr0
& X86_CR0_WP
))
4156 *hw_cr0
&= ~X86_CR0_WP
;
4159 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4161 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4162 unsigned long hw_cr0
;
4164 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4165 if (enable_unrestricted_guest
)
4166 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4168 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4170 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4173 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4177 #ifdef CONFIG_X86_64
4178 if (vcpu
->arch
.efer
& EFER_LME
) {
4179 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4181 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4187 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4189 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4190 vmcs_writel(GUEST_CR0
, hw_cr0
);
4191 vcpu
->arch
.cr0
= cr0
;
4193 /* depends on vcpu->arch.cr0 to be set to a new value */
4194 vmx
->emulation_required
= emulation_required(vcpu
);
4197 static u64
construct_eptp(unsigned long root_hpa
)
4201 /* TODO write the value reading from MSR */
4202 eptp
= VMX_EPT_DEFAULT_MT
|
4203 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4204 if (enable_ept_ad_bits
)
4205 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4206 eptp
|= (root_hpa
& PAGE_MASK
);
4211 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4213 unsigned long guest_cr3
;
4218 eptp
= construct_eptp(cr3
);
4219 vmcs_write64(EPT_POINTER
, eptp
);
4220 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4221 guest_cr3
= kvm_read_cr3(vcpu
);
4223 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4224 ept_load_pdptrs(vcpu
);
4227 vmx_flush_tlb(vcpu
);
4228 vmcs_writel(GUEST_CR3
, guest_cr3
);
4231 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4234 * Pass through host's Machine Check Enable value to hw_cr4, which
4235 * is in force while we are in guest mode. Do not let guests control
4236 * this bit, even if host CR4.MCE == 0.
4238 unsigned long hw_cr4
=
4239 (cr4_read_shadow() & X86_CR4_MCE
) |
4240 (cr4
& ~X86_CR4_MCE
) |
4241 (to_vmx(vcpu
)->rmode
.vm86_active
?
4242 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4244 if (cr4
& X86_CR4_VMXE
) {
4246 * To use VMXON (and later other VMX instructions), a guest
4247 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4248 * So basically the check on whether to allow nested VMX
4251 if (!nested_vmx_allowed(vcpu
))
4255 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4258 vcpu
->arch
.cr4
= cr4
;
4260 if (!is_paging(vcpu
)) {
4261 hw_cr4
&= ~X86_CR4_PAE
;
4262 hw_cr4
|= X86_CR4_PSE
;
4263 } else if (!(cr4
& X86_CR4_PAE
)) {
4264 hw_cr4
&= ~X86_CR4_PAE
;
4268 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4270 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4271 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4272 * to be manually disabled when guest switches to non-paging
4275 * If !enable_unrestricted_guest, the CPU is always running
4276 * with CR0.PG=1 and CR4 needs to be modified.
4277 * If enable_unrestricted_guest, the CPU automatically
4278 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4280 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4282 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4283 vmcs_writel(GUEST_CR4
, hw_cr4
);
4287 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4288 struct kvm_segment
*var
, int seg
)
4290 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4293 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4294 *var
= vmx
->rmode
.segs
[seg
];
4295 if (seg
== VCPU_SREG_TR
4296 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4298 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4299 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4302 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4303 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4304 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4305 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4306 var
->unusable
= (ar
>> 16) & 1;
4307 var
->type
= ar
& 15;
4308 var
->s
= (ar
>> 4) & 1;
4309 var
->dpl
= (ar
>> 5) & 3;
4311 * Some userspaces do not preserve unusable property. Since usable
4312 * segment has to be present according to VMX spec we can use present
4313 * property to amend userspace bug by making unusable segment always
4314 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4315 * segment as unusable.
4317 var
->present
= !var
->unusable
;
4318 var
->avl
= (ar
>> 12) & 1;
4319 var
->l
= (ar
>> 13) & 1;
4320 var
->db
= (ar
>> 14) & 1;
4321 var
->g
= (ar
>> 15) & 1;
4324 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4326 struct kvm_segment s
;
4328 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4329 vmx_get_segment(vcpu
, &s
, seg
);
4332 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4335 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4337 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4339 if (unlikely(vmx
->rmode
.vm86_active
))
4342 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4343 return VMX_AR_DPL(ar
);
4347 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4351 if (var
->unusable
|| !var
->present
)
4354 ar
= var
->type
& 15;
4355 ar
|= (var
->s
& 1) << 4;
4356 ar
|= (var
->dpl
& 3) << 5;
4357 ar
|= (var
->present
& 1) << 7;
4358 ar
|= (var
->avl
& 1) << 12;
4359 ar
|= (var
->l
& 1) << 13;
4360 ar
|= (var
->db
& 1) << 14;
4361 ar
|= (var
->g
& 1) << 15;
4367 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4368 struct kvm_segment
*var
, int seg
)
4370 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4371 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4373 vmx_segment_cache_clear(vmx
);
4375 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4376 vmx
->rmode
.segs
[seg
] = *var
;
4377 if (seg
== VCPU_SREG_TR
)
4378 vmcs_write16(sf
->selector
, var
->selector
);
4380 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4384 vmcs_writel(sf
->base
, var
->base
);
4385 vmcs_write32(sf
->limit
, var
->limit
);
4386 vmcs_write16(sf
->selector
, var
->selector
);
4389 * Fix the "Accessed" bit in AR field of segment registers for older
4391 * IA32 arch specifies that at the time of processor reset the
4392 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4393 * is setting it to 0 in the userland code. This causes invalid guest
4394 * state vmexit when "unrestricted guest" mode is turned on.
4395 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4396 * tree. Newer qemu binaries with that qemu fix would not need this
4399 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4400 var
->type
|= 0x1; /* Accessed */
4402 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4405 vmx
->emulation_required
= emulation_required(vcpu
);
4408 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4410 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4412 *db
= (ar
>> 14) & 1;
4413 *l
= (ar
>> 13) & 1;
4416 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4418 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4419 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4422 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4424 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4425 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4428 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4430 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4431 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4434 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4436 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4437 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4440 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4442 struct kvm_segment var
;
4445 vmx_get_segment(vcpu
, &var
, seg
);
4447 if (seg
== VCPU_SREG_CS
)
4449 ar
= vmx_segment_access_rights(&var
);
4451 if (var
.base
!= (var
.selector
<< 4))
4453 if (var
.limit
!= 0xffff)
4461 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4463 struct kvm_segment cs
;
4464 unsigned int cs_rpl
;
4466 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4467 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4471 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4475 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4476 if (cs
.dpl
> cs_rpl
)
4479 if (cs
.dpl
!= cs_rpl
)
4485 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4489 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4491 struct kvm_segment ss
;
4492 unsigned int ss_rpl
;
4494 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4495 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4499 if (ss
.type
!= 3 && ss
.type
!= 7)
4503 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4511 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4513 struct kvm_segment var
;
4516 vmx_get_segment(vcpu
, &var
, seg
);
4517 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4525 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4526 if (var
.dpl
< rpl
) /* DPL < RPL */
4530 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4536 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4538 struct kvm_segment tr
;
4540 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4544 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4546 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4554 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4556 struct kvm_segment ldtr
;
4558 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4562 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4572 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4574 struct kvm_segment cs
, ss
;
4576 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4577 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4579 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4580 (ss
.selector
& SEGMENT_RPL_MASK
));
4584 * Check if guest state is valid. Returns true if valid, false if
4586 * We assume that registers are always usable
4588 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4590 if (enable_unrestricted_guest
)
4593 /* real mode guest state checks */
4594 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4595 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4597 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4599 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4601 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4603 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4605 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4608 /* protected mode guest state checks */
4609 if (!cs_ss_rpl_check(vcpu
))
4611 if (!code_segment_valid(vcpu
))
4613 if (!stack_segment_valid(vcpu
))
4615 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4617 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4619 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4621 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4623 if (!tr_valid(vcpu
))
4625 if (!ldtr_valid(vcpu
))
4629 * - Add checks on RIP
4630 * - Add checks on RFLAGS
4636 static int init_rmode_tss(struct kvm
*kvm
)
4642 idx
= srcu_read_lock(&kvm
->srcu
);
4643 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4644 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4647 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4648 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4649 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4652 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4655 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4659 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4660 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4663 srcu_read_unlock(&kvm
->srcu
, idx
);
4667 static int init_rmode_identity_map(struct kvm
*kvm
)
4670 kvm_pfn_t identity_map_pfn
;
4676 /* Protect kvm->arch.ept_identity_pagetable_done. */
4677 mutex_lock(&kvm
->slots_lock
);
4679 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4682 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4684 r
= alloc_identity_pagetable(kvm
);
4688 idx
= srcu_read_lock(&kvm
->srcu
);
4689 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4692 /* Set up identity-mapping pagetable for EPT in real mode */
4693 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4694 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4695 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4696 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4697 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4701 kvm
->arch
.ept_identity_pagetable_done
= true;
4704 srcu_read_unlock(&kvm
->srcu
, idx
);
4707 mutex_unlock(&kvm
->slots_lock
);
4711 static void seg_setup(int seg
)
4713 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4716 vmcs_write16(sf
->selector
, 0);
4717 vmcs_writel(sf
->base
, 0);
4718 vmcs_write32(sf
->limit
, 0xffff);
4720 if (seg
== VCPU_SREG_CS
)
4721 ar
|= 0x08; /* code segment */
4723 vmcs_write32(sf
->ar_bytes
, ar
);
4726 static int alloc_apic_access_page(struct kvm
*kvm
)
4731 mutex_lock(&kvm
->slots_lock
);
4732 if (kvm
->arch
.apic_access_page_done
)
4734 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4735 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4739 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4740 if (is_error_page(page
)) {
4746 * Do not pin the page in memory, so that memory hot-unplug
4747 * is able to migrate it.
4750 kvm
->arch
.apic_access_page_done
= true;
4752 mutex_unlock(&kvm
->slots_lock
);
4756 static int alloc_identity_pagetable(struct kvm
*kvm
)
4758 /* Called with kvm->slots_lock held. */
4762 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4764 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4765 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4770 static int allocate_vpid(void)
4776 spin_lock(&vmx_vpid_lock
);
4777 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4778 if (vpid
< VMX_NR_VPIDS
)
4779 __set_bit(vpid
, vmx_vpid_bitmap
);
4782 spin_unlock(&vmx_vpid_lock
);
4786 static void free_vpid(int vpid
)
4788 if (!enable_vpid
|| vpid
== 0)
4790 spin_lock(&vmx_vpid_lock
);
4791 __clear_bit(vpid
, vmx_vpid_bitmap
);
4792 spin_unlock(&vmx_vpid_lock
);
4795 #define MSR_TYPE_R 1
4796 #define MSR_TYPE_W 2
4797 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4800 int f
= sizeof(unsigned long);
4802 if (!cpu_has_vmx_msr_bitmap())
4806 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4807 * have the write-low and read-high bitmap offsets the wrong way round.
4808 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4810 if (msr
<= 0x1fff) {
4811 if (type
& MSR_TYPE_R
)
4813 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4815 if (type
& MSR_TYPE_W
)
4817 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4819 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4821 if (type
& MSR_TYPE_R
)
4823 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4825 if (type
& MSR_TYPE_W
)
4827 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4833 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4834 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4836 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4837 unsigned long *msr_bitmap_nested
,
4840 int f
= sizeof(unsigned long);
4842 if (!cpu_has_vmx_msr_bitmap()) {
4848 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4849 * have the write-low and read-high bitmap offsets the wrong way round.
4850 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4852 if (msr
<= 0x1fff) {
4853 if (type
& MSR_TYPE_R
&&
4854 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4856 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4858 if (type
& MSR_TYPE_W
&&
4859 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4861 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4863 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4865 if (type
& MSR_TYPE_R
&&
4866 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4868 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4870 if (type
& MSR_TYPE_W
&&
4871 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4873 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4878 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4881 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4882 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4883 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4884 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4887 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4890 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4892 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4895 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4897 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4902 static bool vmx_get_enable_apicv(void)
4904 return enable_apicv
;
4907 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4909 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4914 if (vmx
->nested
.pi_desc
&&
4915 vmx
->nested
.pi_pending
) {
4916 vmx
->nested
.pi_pending
= false;
4917 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4920 max_irr
= find_last_bit(
4921 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4926 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4927 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4928 kunmap(vmx
->nested
.virtual_apic_page
);
4930 status
= vmcs_read16(GUEST_INTR_STATUS
);
4931 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4933 status
|= (u8
)max_irr
;
4934 vmcs_write16(GUEST_INTR_STATUS
, status
);
4939 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4942 if (vcpu
->mode
== IN_GUEST_MODE
) {
4943 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4946 * Currently, we don't support urgent interrupt,
4947 * all interrupts are recognized as non-urgent
4948 * interrupt, so we cannot post interrupts when
4951 * If the vcpu is in guest mode, it means it is
4952 * running instead of being scheduled out and
4953 * waiting in the run queue, and that's the only
4954 * case when 'SN' is set currently, warning if
4957 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4959 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4960 POSTED_INTR_VECTOR
);
4967 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4970 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4972 if (is_guest_mode(vcpu
) &&
4973 vector
== vmx
->nested
.posted_intr_nv
) {
4974 /* the PIR and ON have been set by L1. */
4975 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4977 * If a posted intr is not recognized by hardware,
4978 * we will accomplish it in the next vmentry.
4980 vmx
->nested
.pi_pending
= true;
4981 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4987 * Send interrupt to vcpu via posted interrupt way.
4988 * 1. If target vcpu is running(non-root mode), send posted interrupt
4989 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4990 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4991 * interrupt from PIR in next vmentry.
4993 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4995 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4998 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5002 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5005 /* If a previous notification has sent the IPI, nothing to do. */
5006 if (pi_test_and_set_on(&vmx
->pi_desc
))
5009 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
))
5010 kvm_vcpu_kick(vcpu
);
5014 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5015 * will not change in the lifetime of the guest.
5016 * Note that host-state that does change is set elsewhere. E.g., host-state
5017 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5019 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5024 unsigned long cr0
, cr4
;
5027 WARN_ON(cr0
& X86_CR0_TS
);
5028 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5029 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5031 /* Save the most likely value for this task's CR4 in the VMCS. */
5032 cr4
= cr4_read_shadow();
5033 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5034 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5036 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5037 #ifdef CONFIG_X86_64
5039 * Load null selectors, so we can avoid reloading them in
5040 * __vmx_load_host_state(), in case userspace uses the null selectors
5041 * too (the expected case).
5043 vmcs_write16(HOST_DS_SELECTOR
, 0);
5044 vmcs_write16(HOST_ES_SELECTOR
, 0);
5046 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5047 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5049 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5050 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5052 native_store_idt(&dt
);
5053 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5054 vmx
->host_idt_base
= dt
.address
;
5056 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5058 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5059 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5060 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5061 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5063 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5064 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5065 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5069 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5071 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5073 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5074 if (is_guest_mode(&vmx
->vcpu
))
5075 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5076 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5077 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5080 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5082 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5084 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5085 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5086 /* Enable the preemption timer dynamically */
5087 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5088 return pin_based_exec_ctrl
;
5091 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5095 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5096 if (cpu_has_secondary_exec_ctrls()) {
5097 if (kvm_vcpu_apicv_active(vcpu
))
5098 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5099 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5100 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5102 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5103 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5104 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5107 if (cpu_has_vmx_msr_bitmap())
5108 vmx_set_msr_bitmap(vcpu
);
5111 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5113 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5115 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5116 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5118 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5119 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5120 #ifdef CONFIG_X86_64
5121 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5122 CPU_BASED_CR8_LOAD_EXITING
;
5126 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5127 CPU_BASED_CR3_LOAD_EXITING
|
5128 CPU_BASED_INVLPG_EXITING
;
5129 return exec_control
;
5132 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5134 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5135 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5136 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5138 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5140 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5141 enable_unrestricted_guest
= 0;
5142 /* Enable INVPCID for non-ept guests may cause performance regression. */
5143 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5145 if (!enable_unrestricted_guest
)
5146 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5148 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5149 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5150 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5151 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5152 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5153 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5155 We can NOT enable shadow_vmcs here because we don't have yet
5158 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5161 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5163 return exec_control
;
5166 static void ept_set_mmio_spte_mask(void)
5169 * EPT Misconfigurations can be generated if the value of bits 2:0
5170 * of an EPT paging-structure entry is 110b (write/execute).
5172 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE
);
5175 #define VMX_XSS_EXIT_BITMAP 0
5177 * Sets up the vmcs for emulated real mode.
5179 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5181 #ifdef CONFIG_X86_64
5187 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5188 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5190 if (enable_shadow_vmcs
) {
5191 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5192 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5194 if (cpu_has_vmx_msr_bitmap())
5195 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5197 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5200 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5201 vmx
->hv_deadline_tsc
= -1;
5203 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5205 if (cpu_has_secondary_exec_ctrls()) {
5206 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5207 vmx_secondary_exec_control(vmx
));
5210 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5211 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5212 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5213 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5214 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5216 vmcs_write16(GUEST_INTR_STATUS
, 0);
5218 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5219 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5223 vmcs_write32(PLE_GAP
, ple_gap
);
5224 vmx
->ple_window
= ple_window
;
5225 vmx
->ple_window_dirty
= true;
5228 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5229 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5230 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5232 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5233 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5234 vmx_set_constant_host_state(vmx
);
5235 #ifdef CONFIG_X86_64
5236 rdmsrl(MSR_FS_BASE
, a
);
5237 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5238 rdmsrl(MSR_GS_BASE
, a
);
5239 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5241 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5242 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5245 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5246 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5247 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5248 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5249 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5251 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5252 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5254 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5255 u32 index
= vmx_msr_index
[i
];
5256 u32 data_low
, data_high
;
5259 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5261 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5263 vmx
->guest_msrs
[j
].index
= i
;
5264 vmx
->guest_msrs
[j
].data
= 0;
5265 vmx
->guest_msrs
[j
].mask
= -1ull;
5270 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5272 /* 22.2.1, 20.8.1 */
5273 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5275 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5276 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5278 set_cr4_guest_host_mask(vmx
);
5280 if (vmx_xsaves_supported())
5281 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5284 ASSERT(vmx
->pml_pg
);
5285 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5286 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5292 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5294 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5295 struct msr_data apic_base_msr
;
5298 vmx
->rmode
.vm86_active
= 0;
5300 vmx
->soft_vnmi_blocked
= 0;
5302 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5303 kvm_set_cr8(vcpu
, 0);
5306 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5307 MSR_IA32_APICBASE_ENABLE
;
5308 if (kvm_vcpu_is_reset_bsp(vcpu
))
5309 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5310 apic_base_msr
.host_initiated
= true;
5311 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5314 vmx_segment_cache_clear(vmx
);
5316 seg_setup(VCPU_SREG_CS
);
5317 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5318 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5320 seg_setup(VCPU_SREG_DS
);
5321 seg_setup(VCPU_SREG_ES
);
5322 seg_setup(VCPU_SREG_FS
);
5323 seg_setup(VCPU_SREG_GS
);
5324 seg_setup(VCPU_SREG_SS
);
5326 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5327 vmcs_writel(GUEST_TR_BASE
, 0);
5328 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5329 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5331 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5332 vmcs_writel(GUEST_LDTR_BASE
, 0);
5333 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5334 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5337 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5338 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5339 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5340 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5343 vmcs_writel(GUEST_RFLAGS
, 0x02);
5344 kvm_rip_write(vcpu
, 0xfff0);
5346 vmcs_writel(GUEST_GDTR_BASE
, 0);
5347 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5349 vmcs_writel(GUEST_IDTR_BASE
, 0);
5350 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5352 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5353 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5354 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5358 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5360 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5361 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5362 if (cpu_need_tpr_shadow(vcpu
))
5363 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5364 __pa(vcpu
->arch
.apic
->regs
));
5365 vmcs_write32(TPR_THRESHOLD
, 0);
5368 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5370 if (kvm_vcpu_apicv_active(vcpu
))
5371 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5374 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5376 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5377 vmx
->vcpu
.arch
.cr0
= cr0
;
5378 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5379 vmx_set_cr4(vcpu
, 0);
5380 vmx_set_efer(vcpu
, 0);
5382 update_exception_bitmap(vcpu
);
5384 vpid_sync_context(vmx
->vpid
);
5388 * In nested virtualization, check if L1 asked to exit on external interrupts.
5389 * For most existing hypervisors, this will always return true.
5391 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5393 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5394 PIN_BASED_EXT_INTR_MASK
;
5398 * In nested virtualization, check if L1 has set
5399 * VM_EXIT_ACK_INTR_ON_EXIT
5401 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5403 return get_vmcs12(vcpu
)->vm_exit_controls
&
5404 VM_EXIT_ACK_INTR_ON_EXIT
;
5407 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5409 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5410 PIN_BASED_NMI_EXITING
;
5413 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5415 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5416 CPU_BASED_VIRTUAL_INTR_PENDING
);
5419 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5421 if (!cpu_has_virtual_nmis() ||
5422 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5423 enable_irq_window(vcpu
);
5427 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5428 CPU_BASED_VIRTUAL_NMI_PENDING
);
5431 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5433 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5435 int irq
= vcpu
->arch
.interrupt
.nr
;
5437 trace_kvm_inj_virq(irq
);
5439 ++vcpu
->stat
.irq_injections
;
5440 if (vmx
->rmode
.vm86_active
) {
5442 if (vcpu
->arch
.interrupt
.soft
)
5443 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5444 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5445 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5448 intr
= irq
| INTR_INFO_VALID_MASK
;
5449 if (vcpu
->arch
.interrupt
.soft
) {
5450 intr
|= INTR_TYPE_SOFT_INTR
;
5451 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5452 vmx
->vcpu
.arch
.event_exit_inst_len
);
5454 intr
|= INTR_TYPE_EXT_INTR
;
5455 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5458 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5460 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5462 if (!is_guest_mode(vcpu
)) {
5463 if (!cpu_has_virtual_nmis()) {
5465 * Tracking the NMI-blocked state in software is built upon
5466 * finding the next open IRQ window. This, in turn, depends on
5467 * well-behaving guests: They have to keep IRQs disabled at
5468 * least as long as the NMI handler runs. Otherwise we may
5469 * cause NMI nesting, maybe breaking the guest. But as this is
5470 * highly unlikely, we can live with the residual risk.
5472 vmx
->soft_vnmi_blocked
= 1;
5473 vmx
->vnmi_blocked_time
= 0;
5476 ++vcpu
->stat
.nmi_injections
;
5477 vmx
->nmi_known_unmasked
= false;
5480 if (vmx
->rmode
.vm86_active
) {
5481 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5482 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5486 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5487 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5490 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5492 if (!cpu_has_virtual_nmis())
5493 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5494 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5496 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5499 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5501 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5503 if (!cpu_has_virtual_nmis()) {
5504 if (vmx
->soft_vnmi_blocked
!= masked
) {
5505 vmx
->soft_vnmi_blocked
= masked
;
5506 vmx
->vnmi_blocked_time
= 0;
5509 vmx
->nmi_known_unmasked
= !masked
;
5511 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5512 GUEST_INTR_STATE_NMI
);
5514 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5515 GUEST_INTR_STATE_NMI
);
5519 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5521 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5524 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5527 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5528 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5529 | GUEST_INTR_STATE_NMI
));
5532 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5534 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5535 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5536 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5537 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5540 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5544 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5548 kvm
->arch
.tss_addr
= addr
;
5549 return init_rmode_tss(kvm
);
5552 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5557 * Update instruction length as we may reinject the exception
5558 * from user space while in guest debugging mode.
5560 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5561 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5562 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5566 if (vcpu
->guest_debug
&
5567 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5584 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5585 int vec
, u32 err_code
)
5588 * Instruction with address size override prefix opcode 0x67
5589 * Cause the #SS fault with 0 error code in VM86 mode.
5591 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5592 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5593 if (vcpu
->arch
.halt_request
) {
5594 vcpu
->arch
.halt_request
= 0;
5595 return kvm_vcpu_halt(vcpu
);
5603 * Forward all other exceptions that are valid in real mode.
5604 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5605 * the required debugging infrastructure rework.
5607 kvm_queue_exception(vcpu
, vec
);
5612 * Trigger machine check on the host. We assume all the MSRs are already set up
5613 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5614 * We pass a fake environment to the machine check handler because we want
5615 * the guest to be always treated like user space, no matter what context
5616 * it used internally.
5618 static void kvm_machine_check(void)
5620 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5621 struct pt_regs regs
= {
5622 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5623 .flags
= X86_EFLAGS_IF
,
5626 do_machine_check(®s
, 0);
5630 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5632 /* already handled by vcpu_run */
5636 static int handle_exception(struct kvm_vcpu
*vcpu
)
5638 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5639 struct kvm_run
*kvm_run
= vcpu
->run
;
5640 u32 intr_info
, ex_no
, error_code
;
5641 unsigned long cr2
, rip
, dr6
;
5643 enum emulation_result er
;
5645 vect_info
= vmx
->idt_vectoring_info
;
5646 intr_info
= vmx
->exit_intr_info
;
5648 if (is_machine_check(intr_info
))
5649 return handle_machine_check(vcpu
);
5651 if (is_nmi(intr_info
))
5652 return 1; /* already handled by vmx_vcpu_run() */
5654 if (is_invalid_opcode(intr_info
)) {
5655 if (is_guest_mode(vcpu
)) {
5656 kvm_queue_exception(vcpu
, UD_VECTOR
);
5659 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5660 if (er
!= EMULATE_DONE
)
5661 kvm_queue_exception(vcpu
, UD_VECTOR
);
5666 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5667 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5670 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5671 * MMIO, it is better to report an internal error.
5672 * See the comments in vmx_handle_exit.
5674 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5675 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5676 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5677 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5678 vcpu
->run
->internal
.ndata
= 3;
5679 vcpu
->run
->internal
.data
[0] = vect_info
;
5680 vcpu
->run
->internal
.data
[1] = intr_info
;
5681 vcpu
->run
->internal
.data
[2] = error_code
;
5685 if (is_page_fault(intr_info
)) {
5686 /* EPT won't cause page fault directly */
5688 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5689 trace_kvm_page_fault(cr2
, error_code
);
5691 if (kvm_event_needs_reinjection(vcpu
))
5692 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5693 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5696 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5698 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5699 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5703 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5706 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5707 if (!(vcpu
->guest_debug
&
5708 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5709 vcpu
->arch
.dr6
&= ~15;
5710 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5711 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5712 skip_emulated_instruction(vcpu
);
5714 kvm_queue_exception(vcpu
, DB_VECTOR
);
5717 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5718 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5722 * Update instruction length as we may reinject #BP from
5723 * user space while in guest debugging mode. Reading it for
5724 * #DB as well causes no harm, it is not used in that case.
5726 vmx
->vcpu
.arch
.event_exit_inst_len
=
5727 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5728 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5729 rip
= kvm_rip_read(vcpu
);
5730 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5731 kvm_run
->debug
.arch
.exception
= ex_no
;
5734 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5735 kvm_run
->ex
.exception
= ex_no
;
5736 kvm_run
->ex
.error_code
= error_code
;
5742 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5744 ++vcpu
->stat
.irq_exits
;
5748 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5750 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5754 static int handle_io(struct kvm_vcpu
*vcpu
)
5756 unsigned long exit_qualification
;
5757 int size
, in
, string
, ret
;
5760 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5761 string
= (exit_qualification
& 16) != 0;
5762 in
= (exit_qualification
& 8) != 0;
5764 ++vcpu
->stat
.io_exits
;
5767 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5769 port
= exit_qualification
>> 16;
5770 size
= (exit_qualification
& 7) + 1;
5772 ret
= kvm_skip_emulated_instruction(vcpu
);
5775 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5776 * KVM_EXIT_DEBUG here.
5778 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5782 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5785 * Patch in the VMCALL instruction:
5787 hypercall
[0] = 0x0f;
5788 hypercall
[1] = 0x01;
5789 hypercall
[2] = 0xc1;
5792 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5793 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5795 if (is_guest_mode(vcpu
)) {
5796 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5797 unsigned long orig_val
= val
;
5800 * We get here when L2 changed cr0 in a way that did not change
5801 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5802 * but did change L0 shadowed bits. So we first calculate the
5803 * effective cr0 value that L1 would like to write into the
5804 * hardware. It consists of the L2-owned bits from the new
5805 * value combined with the L1-owned bits from L1's guest_cr0.
5807 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5808 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5810 if (!nested_guest_cr0_valid(vcpu
, val
))
5813 if (kvm_set_cr0(vcpu
, val
))
5815 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5818 if (to_vmx(vcpu
)->nested
.vmxon
&&
5819 !nested_host_cr0_valid(vcpu
, val
))
5822 return kvm_set_cr0(vcpu
, val
);
5826 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5828 if (is_guest_mode(vcpu
)) {
5829 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5830 unsigned long orig_val
= val
;
5832 /* analogously to handle_set_cr0 */
5833 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5834 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5835 if (kvm_set_cr4(vcpu
, val
))
5837 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5840 return kvm_set_cr4(vcpu
, val
);
5843 static int handle_cr(struct kvm_vcpu
*vcpu
)
5845 unsigned long exit_qualification
, val
;
5851 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5852 cr
= exit_qualification
& 15;
5853 reg
= (exit_qualification
>> 8) & 15;
5854 switch ((exit_qualification
>> 4) & 3) {
5855 case 0: /* mov to cr */
5856 val
= kvm_register_readl(vcpu
, reg
);
5857 trace_kvm_cr_write(cr
, val
);
5860 err
= handle_set_cr0(vcpu
, val
);
5861 return kvm_complete_insn_gp(vcpu
, err
);
5863 err
= kvm_set_cr3(vcpu
, val
);
5864 return kvm_complete_insn_gp(vcpu
, err
);
5866 err
= handle_set_cr4(vcpu
, val
);
5867 return kvm_complete_insn_gp(vcpu
, err
);
5869 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5871 err
= kvm_set_cr8(vcpu
, cr8
);
5872 ret
= kvm_complete_insn_gp(vcpu
, err
);
5873 if (lapic_in_kernel(vcpu
))
5875 if (cr8_prev
<= cr8
)
5878 * TODO: we might be squashing a
5879 * KVM_GUESTDBG_SINGLESTEP-triggered
5880 * KVM_EXIT_DEBUG here.
5882 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5888 WARN_ONCE(1, "Guest should always own CR0.TS");
5889 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5890 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5891 return kvm_skip_emulated_instruction(vcpu
);
5892 case 1: /*mov from cr*/
5895 val
= kvm_read_cr3(vcpu
);
5896 kvm_register_write(vcpu
, reg
, val
);
5897 trace_kvm_cr_read(cr
, val
);
5898 return kvm_skip_emulated_instruction(vcpu
);
5900 val
= kvm_get_cr8(vcpu
);
5901 kvm_register_write(vcpu
, reg
, val
);
5902 trace_kvm_cr_read(cr
, val
);
5903 return kvm_skip_emulated_instruction(vcpu
);
5907 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5908 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5909 kvm_lmsw(vcpu
, val
);
5911 return kvm_skip_emulated_instruction(vcpu
);
5915 vcpu
->run
->exit_reason
= 0;
5916 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5917 (int)(exit_qualification
>> 4) & 3, cr
);
5921 static int handle_dr(struct kvm_vcpu
*vcpu
)
5923 unsigned long exit_qualification
;
5926 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5927 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5929 /* First, if DR does not exist, trigger UD */
5930 if (!kvm_require_dr(vcpu
, dr
))
5933 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5934 if (!kvm_require_cpl(vcpu
, 0))
5936 dr7
= vmcs_readl(GUEST_DR7
);
5939 * As the vm-exit takes precedence over the debug trap, we
5940 * need to emulate the latter, either for the host or the
5941 * guest debugging itself.
5943 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5944 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5945 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5946 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5947 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5948 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5951 vcpu
->arch
.dr6
&= ~15;
5952 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5953 kvm_queue_exception(vcpu
, DB_VECTOR
);
5958 if (vcpu
->guest_debug
== 0) {
5959 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5960 CPU_BASED_MOV_DR_EXITING
);
5963 * No more DR vmexits; force a reload of the debug registers
5964 * and reenter on this instruction. The next vmexit will
5965 * retrieve the full state of the debug registers.
5967 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5971 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5972 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5975 if (kvm_get_dr(vcpu
, dr
, &val
))
5977 kvm_register_write(vcpu
, reg
, val
);
5979 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5982 return kvm_skip_emulated_instruction(vcpu
);
5985 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5987 return vcpu
->arch
.dr6
;
5990 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5994 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5996 get_debugreg(vcpu
->arch
.db
[0], 0);
5997 get_debugreg(vcpu
->arch
.db
[1], 1);
5998 get_debugreg(vcpu
->arch
.db
[2], 2);
5999 get_debugreg(vcpu
->arch
.db
[3], 3);
6000 get_debugreg(vcpu
->arch
.dr6
, 6);
6001 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6003 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6004 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6007 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6009 vmcs_writel(GUEST_DR7
, val
);
6012 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6014 return kvm_emulate_cpuid(vcpu
);
6017 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6019 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6020 struct msr_data msr_info
;
6022 msr_info
.index
= ecx
;
6023 msr_info
.host_initiated
= false;
6024 if (vmx_get_msr(vcpu
, &msr_info
)) {
6025 trace_kvm_msr_read_ex(ecx
);
6026 kvm_inject_gp(vcpu
, 0);
6030 trace_kvm_msr_read(ecx
, msr_info
.data
);
6032 /* FIXME: handling of bits 32:63 of rax, rdx */
6033 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6034 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6035 return kvm_skip_emulated_instruction(vcpu
);
6038 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6040 struct msr_data msr
;
6041 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6042 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6043 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6047 msr
.host_initiated
= false;
6048 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6049 trace_kvm_msr_write_ex(ecx
, data
);
6050 kvm_inject_gp(vcpu
, 0);
6054 trace_kvm_msr_write(ecx
, data
);
6055 return kvm_skip_emulated_instruction(vcpu
);
6058 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6060 kvm_apic_update_ppr(vcpu
);
6064 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6066 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6067 CPU_BASED_VIRTUAL_INTR_PENDING
);
6069 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6071 ++vcpu
->stat
.irq_window_exits
;
6075 static int handle_halt(struct kvm_vcpu
*vcpu
)
6077 return kvm_emulate_halt(vcpu
);
6080 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6082 return kvm_emulate_hypercall(vcpu
);
6085 static int handle_invd(struct kvm_vcpu
*vcpu
)
6087 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6090 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6092 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6094 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6095 return kvm_skip_emulated_instruction(vcpu
);
6098 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6102 err
= kvm_rdpmc(vcpu
);
6103 return kvm_complete_insn_gp(vcpu
, err
);
6106 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6108 return kvm_emulate_wbinvd(vcpu
);
6111 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6113 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6114 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6116 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6117 return kvm_skip_emulated_instruction(vcpu
);
6121 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6123 kvm_skip_emulated_instruction(vcpu
);
6124 WARN(1, "this should never happen\n");
6128 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6130 kvm_skip_emulated_instruction(vcpu
);
6131 WARN(1, "this should never happen\n");
6135 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6137 if (likely(fasteoi
)) {
6138 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6139 int access_type
, offset
;
6141 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6142 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6144 * Sane guest uses MOV to write EOI, with written value
6145 * not cared. So make a short-circuit here by avoiding
6146 * heavy instruction emulation.
6148 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6149 (offset
== APIC_EOI
)) {
6150 kvm_lapic_set_eoi(vcpu
);
6151 return kvm_skip_emulated_instruction(vcpu
);
6154 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6157 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6159 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6160 int vector
= exit_qualification
& 0xff;
6162 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6163 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6167 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6169 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6170 u32 offset
= exit_qualification
& 0xfff;
6172 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6173 kvm_apic_write_nodecode(vcpu
, offset
);
6177 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6179 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6180 unsigned long exit_qualification
;
6181 bool has_error_code
= false;
6184 int reason
, type
, idt_v
, idt_index
;
6186 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6187 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6188 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6190 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6192 reason
= (u32
)exit_qualification
>> 30;
6193 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6195 case INTR_TYPE_NMI_INTR
:
6196 vcpu
->arch
.nmi_injected
= false;
6197 vmx_set_nmi_mask(vcpu
, true);
6199 case INTR_TYPE_EXT_INTR
:
6200 case INTR_TYPE_SOFT_INTR
:
6201 kvm_clear_interrupt_queue(vcpu
);
6203 case INTR_TYPE_HARD_EXCEPTION
:
6204 if (vmx
->idt_vectoring_info
&
6205 VECTORING_INFO_DELIVER_CODE_MASK
) {
6206 has_error_code
= true;
6208 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6211 case INTR_TYPE_SOFT_EXCEPTION
:
6212 kvm_clear_exception_queue(vcpu
);
6218 tss_selector
= exit_qualification
;
6220 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6221 type
!= INTR_TYPE_EXT_INTR
&&
6222 type
!= INTR_TYPE_NMI_INTR
))
6223 skip_emulated_instruction(vcpu
);
6225 if (kvm_task_switch(vcpu
, tss_selector
,
6226 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6227 has_error_code
, error_code
) == EMULATE_FAIL
) {
6228 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6229 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6230 vcpu
->run
->internal
.ndata
= 0;
6235 * TODO: What about debug traps on tss switch?
6236 * Are we supposed to inject them and update dr6?
6242 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6244 unsigned long exit_qualification
;
6249 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6251 gla_validity
= (exit_qualification
>> 7) & 0x3;
6252 if (gla_validity
== 0x2) {
6253 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
6254 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
6255 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
6256 vmcs_readl(GUEST_LINEAR_ADDRESS
));
6257 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
6258 (long unsigned int)exit_qualification
);
6259 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6260 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6265 * EPT violation happened while executing iret from NMI,
6266 * "blocked by NMI" bit has to be set before next VM entry.
6267 * There are errata that may cause this bit to not be set:
6270 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6271 cpu_has_virtual_nmis() &&
6272 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6273 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6275 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6276 trace_kvm_page_fault(gpa
, exit_qualification
);
6278 /* Is it a read fault? */
6279 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6280 ? PFERR_USER_MASK
: 0;
6281 /* Is it a write fault? */
6282 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6283 ? PFERR_WRITE_MASK
: 0;
6284 /* Is it a fetch fault? */
6285 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6286 ? PFERR_FETCH_MASK
: 0;
6287 /* ept page table entry is present? */
6288 error_code
|= (exit_qualification
&
6289 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6290 EPT_VIOLATION_EXECUTABLE
))
6291 ? PFERR_PRESENT_MASK
: 0;
6293 vcpu
->arch
.gpa_available
= true;
6294 vcpu
->arch
.exit_qualification
= exit_qualification
;
6296 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6299 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6304 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6305 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6306 trace_kvm_fast_mmio(gpa
);
6307 return kvm_skip_emulated_instruction(vcpu
);
6310 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6311 vcpu
->arch
.gpa_available
= true;
6312 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6313 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6316 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6317 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6319 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6322 /* It is the real ept misconfig */
6325 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6326 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6331 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6333 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6334 CPU_BASED_VIRTUAL_NMI_PENDING
);
6335 ++vcpu
->stat
.nmi_window_exits
;
6336 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6341 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6343 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6344 enum emulation_result err
= EMULATE_DONE
;
6347 bool intr_window_requested
;
6348 unsigned count
= 130;
6350 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6351 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6353 while (vmx
->emulation_required
&& count
-- != 0) {
6354 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6355 return handle_interrupt_window(&vmx
->vcpu
);
6357 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6360 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6362 if (err
== EMULATE_USER_EXIT
) {
6363 ++vcpu
->stat
.mmio_exits
;
6368 if (err
!= EMULATE_DONE
) {
6369 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6370 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6371 vcpu
->run
->internal
.ndata
= 0;
6375 if (vcpu
->arch
.halt_request
) {
6376 vcpu
->arch
.halt_request
= 0;
6377 ret
= kvm_vcpu_halt(vcpu
);
6381 if (signal_pending(current
))
6391 static int __grow_ple_window(int val
)
6393 if (ple_window_grow
< 1)
6396 val
= min(val
, ple_window_actual_max
);
6398 if (ple_window_grow
< ple_window
)
6399 val
*= ple_window_grow
;
6401 val
+= ple_window_grow
;
6406 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6411 if (modifier
< ple_window
)
6416 return max(val
, minimum
);
6419 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6421 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6422 int old
= vmx
->ple_window
;
6424 vmx
->ple_window
= __grow_ple_window(old
);
6426 if (vmx
->ple_window
!= old
)
6427 vmx
->ple_window_dirty
= true;
6429 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6432 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6434 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6435 int old
= vmx
->ple_window
;
6437 vmx
->ple_window
= __shrink_ple_window(old
,
6438 ple_window_shrink
, ple_window
);
6440 if (vmx
->ple_window
!= old
)
6441 vmx
->ple_window_dirty
= true;
6443 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6447 * ple_window_actual_max is computed to be one grow_ple_window() below
6448 * ple_window_max. (See __grow_ple_window for the reason.)
6449 * This prevents overflows, because ple_window_max is int.
6450 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6452 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6454 static void update_ple_window_actual_max(void)
6456 ple_window_actual_max
=
6457 __shrink_ple_window(max(ple_window_max
, ple_window
),
6458 ple_window_grow
, INT_MIN
);
6462 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6464 static void wakeup_handler(void)
6466 struct kvm_vcpu
*vcpu
;
6467 int cpu
= smp_processor_id();
6469 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6470 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6471 blocked_vcpu_list
) {
6472 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6474 if (pi_test_on(pi_desc
) == 1)
6475 kvm_vcpu_kick(vcpu
);
6477 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6480 void vmx_enable_tdp(void)
6482 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6483 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6484 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6485 0ull, VMX_EPT_EXECUTABLE_MASK
,
6486 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6487 enable_ept_ad_bits
? 0ull : VMX_EPT_RWX_MASK
);
6489 ept_set_mmio_spte_mask();
6493 static __init
int hardware_setup(void)
6495 int r
= -ENOMEM
, i
, msr
;
6497 rdmsrl_safe(MSR_EFER
, &host_efer
);
6499 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6500 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6502 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6503 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6508 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6509 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6510 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6513 * Allow direct access to the PC debug port (it is often used for I/O
6514 * delays, but the vmexits simply slow things down).
6516 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6517 clear_bit(0x80, vmx_io_bitmap_a
);
6519 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6521 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6522 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6524 if (setup_vmcs_config(&vmcs_config
) < 0) {
6529 if (boot_cpu_has(X86_FEATURE_NX
))
6530 kvm_enable_efer_bits(EFER_NX
);
6532 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6533 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6536 if (!cpu_has_vmx_shadow_vmcs())
6537 enable_shadow_vmcs
= 0;
6538 if (enable_shadow_vmcs
)
6539 init_vmcs_shadow_fields();
6541 if (!cpu_has_vmx_ept() ||
6542 !cpu_has_vmx_ept_4levels()) {
6544 enable_unrestricted_guest
= 0;
6545 enable_ept_ad_bits
= 0;
6548 if (!cpu_has_vmx_ept_ad_bits())
6549 enable_ept_ad_bits
= 0;
6551 if (!cpu_has_vmx_unrestricted_guest())
6552 enable_unrestricted_guest
= 0;
6554 if (!cpu_has_vmx_flexpriority())
6555 flexpriority_enabled
= 0;
6558 * set_apic_access_page_addr() is used to reload apic access
6559 * page upon invalidation. No need to do anything if not
6560 * using the APIC_ACCESS_ADDR VMCS field.
6562 if (!flexpriority_enabled
)
6563 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6565 if (!cpu_has_vmx_tpr_shadow())
6566 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6568 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6569 kvm_disable_largepages();
6571 if (!cpu_has_vmx_ple())
6574 if (!cpu_has_vmx_apicv()) {
6576 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6579 if (cpu_has_vmx_tsc_scaling()) {
6580 kvm_has_tsc_control
= true;
6581 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6582 kvm_tsc_scaling_ratio_frac_bits
= 48;
6585 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6586 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6587 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6588 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6589 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6590 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6591 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6593 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6594 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6595 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6596 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6597 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6598 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6599 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6600 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6602 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6604 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6605 if (msr
== 0x839 /* TMCCT */)
6607 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6611 * TPR reads and writes can be virtualized even if virtual interrupt
6612 * delivery is not in use.
6614 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6615 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6618 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6620 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6627 update_ple_window_actual_max();
6630 * Only enable PML when hardware supports PML feature, and both EPT
6631 * and EPT A/D bit features are enabled -- PML depends on them to work.
6633 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6637 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6638 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6639 kvm_x86_ops
->flush_log_dirty
= NULL
;
6640 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6643 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6646 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6647 cpu_preemption_timer_multi
=
6648 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6650 kvm_x86_ops
->set_hv_timer
= NULL
;
6651 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6654 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6656 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6658 return alloc_kvm_area();
6661 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6662 free_page((unsigned long)vmx_bitmap
[i
]);
6667 static __exit
void hardware_unsetup(void)
6671 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6672 free_page((unsigned long)vmx_bitmap
[i
]);
6678 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6679 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6681 static int handle_pause(struct kvm_vcpu
*vcpu
)
6684 grow_ple_window(vcpu
);
6686 kvm_vcpu_on_spin(vcpu
);
6687 return kvm_skip_emulated_instruction(vcpu
);
6690 static int handle_nop(struct kvm_vcpu
*vcpu
)
6692 return kvm_skip_emulated_instruction(vcpu
);
6695 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6697 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6698 return handle_nop(vcpu
);
6701 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6706 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6708 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6709 return handle_nop(vcpu
);
6713 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6714 * We could reuse a single VMCS for all the L2 guests, but we also want the
6715 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6716 * allows keeping them loaded on the processor, and in the future will allow
6717 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6718 * every entry if they never change.
6719 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6720 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6722 * The following functions allocate and free a vmcs02 in this pool.
6725 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6726 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6728 struct vmcs02_list
*item
;
6729 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6730 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6731 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6732 return &item
->vmcs02
;
6735 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6736 /* Recycle the least recently used VMCS. */
6737 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6738 struct vmcs02_list
, list
);
6739 item
->vmptr
= vmx
->nested
.current_vmptr
;
6740 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6741 return &item
->vmcs02
;
6744 /* Create a new VMCS */
6745 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6748 item
->vmcs02
.vmcs
= alloc_vmcs();
6749 item
->vmcs02
.shadow_vmcs
= NULL
;
6750 if (!item
->vmcs02
.vmcs
) {
6754 loaded_vmcs_init(&item
->vmcs02
);
6755 item
->vmptr
= vmx
->nested
.current_vmptr
;
6756 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6757 vmx
->nested
.vmcs02_num
++;
6758 return &item
->vmcs02
;
6761 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6762 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6764 struct vmcs02_list
*item
;
6765 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6766 if (item
->vmptr
== vmptr
) {
6767 free_loaded_vmcs(&item
->vmcs02
);
6768 list_del(&item
->list
);
6770 vmx
->nested
.vmcs02_num
--;
6776 * Free all VMCSs saved for this vcpu, except the one pointed by
6777 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6778 * must be &vmx->vmcs01.
6780 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6782 struct vmcs02_list
*item
, *n
;
6784 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6785 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6787 * Something will leak if the above WARN triggers. Better than
6790 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6793 free_loaded_vmcs(&item
->vmcs02
);
6794 list_del(&item
->list
);
6796 vmx
->nested
.vmcs02_num
--;
6801 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6802 * set the success or error code of an emulated VMX instruction, as specified
6803 * by Vol 2B, VMX Instruction Reference, "Conventions".
6805 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6807 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6808 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6809 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6812 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6814 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6815 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6816 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6820 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6821 u32 vm_instruction_error
)
6823 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6825 * failValid writes the error number to the current VMCS, which
6826 * can't be done there isn't a current VMCS.
6828 nested_vmx_failInvalid(vcpu
);
6831 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6832 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6833 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6835 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6837 * We don't need to force a shadow sync because
6838 * VM_INSTRUCTION_ERROR is not shadowed
6842 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6844 /* TODO: not to reset guest simply here. */
6845 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6846 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6849 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6851 struct vcpu_vmx
*vmx
=
6852 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6854 vmx
->nested
.preemption_timer_expired
= true;
6855 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6856 kvm_vcpu_kick(&vmx
->vcpu
);
6858 return HRTIMER_NORESTART
;
6862 * Decode the memory-address operand of a vmx instruction, as recorded on an
6863 * exit caused by such an instruction (run by a guest hypervisor).
6864 * On success, returns 0. When the operand is invalid, returns 1 and throws
6867 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6868 unsigned long exit_qualification
,
6869 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6873 struct kvm_segment s
;
6876 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6877 * Execution", on an exit, vmx_instruction_info holds most of the
6878 * addressing components of the operand. Only the displacement part
6879 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6880 * For how an actual address is calculated from all these components,
6881 * refer to Vol. 1, "Operand Addressing".
6883 int scaling
= vmx_instruction_info
& 3;
6884 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6885 bool is_reg
= vmx_instruction_info
& (1u << 10);
6886 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6887 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6888 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6889 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6890 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6893 kvm_queue_exception(vcpu
, UD_VECTOR
);
6897 /* Addr = segment_base + offset */
6898 /* offset = base + [index * scale] + displacement */
6899 off
= exit_qualification
; /* holds the displacement */
6901 off
+= kvm_register_read(vcpu
, base_reg
);
6903 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6904 vmx_get_segment(vcpu
, &s
, seg_reg
);
6905 *ret
= s
.base
+ off
;
6907 if (addr_size
== 1) /* 32 bit */
6910 /* Checks for #GP/#SS exceptions. */
6912 if (is_long_mode(vcpu
)) {
6913 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6914 * non-canonical form. This is the only check on the memory
6915 * destination for long mode!
6917 exn
= is_noncanonical_address(*ret
);
6918 } else if (is_protmode(vcpu
)) {
6919 /* Protected mode: apply checks for segment validity in the
6921 * - segment type check (#GP(0) may be thrown)
6922 * - usability check (#GP(0)/#SS(0))
6923 * - limit check (#GP(0)/#SS(0))
6926 /* #GP(0) if the destination operand is located in a
6927 * read-only data segment or any code segment.
6929 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6931 /* #GP(0) if the source operand is located in an
6932 * execute-only code segment
6934 exn
= ((s
.type
& 0xa) == 8);
6936 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6939 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6941 exn
= (s
.unusable
!= 0);
6942 /* Protected mode: #GP(0)/#SS(0) if the memory
6943 * operand is outside the segment limit.
6945 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6948 kvm_queue_exception_e(vcpu
,
6949 seg_reg
== VCPU_SREG_SS
?
6950 SS_VECTOR
: GP_VECTOR
,
6959 * This function performs the various checks including
6960 * - if it's 4KB aligned
6961 * - No bits beyond the physical address width are set
6962 * - Returns 0 on success or else 1
6963 * (Intel SDM Section 30.3)
6965 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6970 struct x86_exception e
;
6972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6973 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6975 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6976 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6979 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6980 sizeof(vmptr
), &e
)) {
6981 kvm_inject_page_fault(vcpu
, &e
);
6985 switch (exit_reason
) {
6986 case EXIT_REASON_VMON
:
6989 * The first 4 bytes of VMXON region contain the supported
6990 * VMCS revision identifier
6992 * Note - IA32_VMX_BASIC[48] will never be 1
6993 * for the nested case;
6994 * which replaces physical address width with 32
6997 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6998 nested_vmx_failInvalid(vcpu
);
6999 return kvm_skip_emulated_instruction(vcpu
);
7002 page
= nested_get_page(vcpu
, vmptr
);
7004 nested_vmx_failInvalid(vcpu
);
7005 return kvm_skip_emulated_instruction(vcpu
);
7007 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7009 nested_release_page_clean(page
);
7010 nested_vmx_failInvalid(vcpu
);
7011 return kvm_skip_emulated_instruction(vcpu
);
7014 nested_release_page_clean(page
);
7015 vmx
->nested
.vmxon_ptr
= vmptr
;
7017 case EXIT_REASON_VMCLEAR
:
7018 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
7019 nested_vmx_failValid(vcpu
,
7020 VMXERR_VMCLEAR_INVALID_ADDRESS
);
7021 return kvm_skip_emulated_instruction(vcpu
);
7024 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7025 nested_vmx_failValid(vcpu
,
7026 VMXERR_VMCLEAR_VMXON_POINTER
);
7027 return kvm_skip_emulated_instruction(vcpu
);
7030 case EXIT_REASON_VMPTRLD
:
7031 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
7032 nested_vmx_failValid(vcpu
,
7033 VMXERR_VMPTRLD_INVALID_ADDRESS
);
7034 return kvm_skip_emulated_instruction(vcpu
);
7037 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7038 nested_vmx_failValid(vcpu
,
7039 VMXERR_VMPTRLD_VMXON_POINTER
);
7040 return kvm_skip_emulated_instruction(vcpu
);
7044 return 1; /* shouldn't happen */
7052 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7054 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7055 struct vmcs
*shadow_vmcs
;
7057 if (cpu_has_vmx_msr_bitmap()) {
7058 vmx
->nested
.msr_bitmap
=
7059 (unsigned long *)__get_free_page(GFP_KERNEL
);
7060 if (!vmx
->nested
.msr_bitmap
)
7061 goto out_msr_bitmap
;
7064 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7065 if (!vmx
->nested
.cached_vmcs12
)
7066 goto out_cached_vmcs12
;
7068 if (enable_shadow_vmcs
) {
7069 shadow_vmcs
= alloc_vmcs();
7071 goto out_shadow_vmcs
;
7072 /* mark vmcs as shadow */
7073 shadow_vmcs
->revision_id
|= (1u << 31);
7074 /* init shadow vmcs */
7075 vmcs_clear(shadow_vmcs
);
7076 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7079 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7080 vmx
->nested
.vmcs02_num
= 0;
7082 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7083 HRTIMER_MODE_REL_PINNED
);
7084 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7086 vmx
->nested
.vmxon
= true;
7090 kfree(vmx
->nested
.cached_vmcs12
);
7093 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7100 * Emulate the VMXON instruction.
7101 * Currently, we just remember that VMX is active, and do not save or even
7102 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7103 * do not currently need to store anything in that guest-allocated memory
7104 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7105 * argument is different from the VMXON pointer (which the spec says they do).
7107 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7110 struct kvm_segment cs
;
7111 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7112 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7113 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7115 /* The Intel VMX Instruction Reference lists a bunch of bits that
7116 * are prerequisite to running VMXON, most notably cr4.VMXE must be
7117 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
7118 * Otherwise, we should fail with #UD. We test these now:
7120 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
7121 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
7122 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
7123 kvm_queue_exception(vcpu
, UD_VECTOR
);
7127 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7128 if (is_long_mode(vcpu
) && !cs
.l
) {
7129 kvm_queue_exception(vcpu
, UD_VECTOR
);
7133 if (vmx_get_cpl(vcpu
)) {
7134 kvm_inject_gp(vcpu
, 0);
7138 if (vmx
->nested
.vmxon
) {
7139 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7140 return kvm_skip_emulated_instruction(vcpu
);
7143 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7144 != VMXON_NEEDED_FEATURES
) {
7145 kvm_inject_gp(vcpu
, 0);
7149 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
7152 ret
= enter_vmx_operation(vcpu
);
7156 nested_vmx_succeed(vcpu
);
7157 return kvm_skip_emulated_instruction(vcpu
);
7161 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7162 * for running VMX instructions (except VMXON, whose prerequisites are
7163 * slightly different). It also specifies what exception to inject otherwise.
7165 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7167 struct kvm_segment cs
;
7168 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7170 if (!vmx
->nested
.vmxon
) {
7171 kvm_queue_exception(vcpu
, UD_VECTOR
);
7175 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
7176 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
7177 (is_long_mode(vcpu
) && !cs
.l
)) {
7178 kvm_queue_exception(vcpu
, UD_VECTOR
);
7182 if (vmx_get_cpl(vcpu
)) {
7183 kvm_inject_gp(vcpu
, 0);
7190 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7192 if (vmx
->nested
.current_vmptr
== -1ull)
7195 /* current_vmptr and current_vmcs12 are always set/reset together */
7196 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7199 if (enable_shadow_vmcs
) {
7200 /* copy to memory all shadowed fields in case
7201 they were modified */
7202 copy_shadow_to_vmcs12(vmx
);
7203 vmx
->nested
.sync_shadow_vmcs
= false;
7204 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7205 SECONDARY_EXEC_SHADOW_VMCS
);
7206 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7208 vmx
->nested
.posted_intr_nv
= -1;
7210 /* Flush VMCS12 to guest memory */
7211 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7214 kunmap(vmx
->nested
.current_vmcs12_page
);
7215 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7216 vmx
->nested
.current_vmptr
= -1ull;
7217 vmx
->nested
.current_vmcs12
= NULL
;
7221 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7222 * just stops using VMX.
7224 static void free_nested(struct vcpu_vmx
*vmx
)
7226 if (!vmx
->nested
.vmxon
)
7229 vmx
->nested
.vmxon
= false;
7230 free_vpid(vmx
->nested
.vpid02
);
7231 nested_release_vmcs12(vmx
);
7232 if (vmx
->nested
.msr_bitmap
) {
7233 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7234 vmx
->nested
.msr_bitmap
= NULL
;
7236 if (enable_shadow_vmcs
) {
7237 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7238 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7239 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7241 kfree(vmx
->nested
.cached_vmcs12
);
7242 /* Unpin physical memory we referred to in current vmcs02 */
7243 if (vmx
->nested
.apic_access_page
) {
7244 nested_release_page(vmx
->nested
.apic_access_page
);
7245 vmx
->nested
.apic_access_page
= NULL
;
7247 if (vmx
->nested
.virtual_apic_page
) {
7248 nested_release_page(vmx
->nested
.virtual_apic_page
);
7249 vmx
->nested
.virtual_apic_page
= NULL
;
7251 if (vmx
->nested
.pi_desc_page
) {
7252 kunmap(vmx
->nested
.pi_desc_page
);
7253 nested_release_page(vmx
->nested
.pi_desc_page
);
7254 vmx
->nested
.pi_desc_page
= NULL
;
7255 vmx
->nested
.pi_desc
= NULL
;
7258 nested_free_all_saved_vmcss(vmx
);
7261 /* Emulate the VMXOFF instruction */
7262 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7264 if (!nested_vmx_check_permission(vcpu
))
7266 free_nested(to_vmx(vcpu
));
7267 nested_vmx_succeed(vcpu
);
7268 return kvm_skip_emulated_instruction(vcpu
);
7271 /* Emulate the VMCLEAR instruction */
7272 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7274 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7278 if (!nested_vmx_check_permission(vcpu
))
7281 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7284 if (vmptr
== vmx
->nested
.current_vmptr
)
7285 nested_release_vmcs12(vmx
);
7287 kvm_vcpu_write_guest(vcpu
,
7288 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7289 &zero
, sizeof(zero
));
7291 nested_free_vmcs02(vmx
, vmptr
);
7293 nested_vmx_succeed(vcpu
);
7294 return kvm_skip_emulated_instruction(vcpu
);
7297 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7299 /* Emulate the VMLAUNCH instruction */
7300 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7302 return nested_vmx_run(vcpu
, true);
7305 /* Emulate the VMRESUME instruction */
7306 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7309 return nested_vmx_run(vcpu
, false);
7312 enum vmcs_field_type
{
7313 VMCS_FIELD_TYPE_U16
= 0,
7314 VMCS_FIELD_TYPE_U64
= 1,
7315 VMCS_FIELD_TYPE_U32
= 2,
7316 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7319 static inline int vmcs_field_type(unsigned long field
)
7321 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7322 return VMCS_FIELD_TYPE_U32
;
7323 return (field
>> 13) & 0x3 ;
7326 static inline int vmcs_field_readonly(unsigned long field
)
7328 return (((field
>> 10) & 0x3) == 1);
7332 * Read a vmcs12 field. Since these can have varying lengths and we return
7333 * one type, we chose the biggest type (u64) and zero-extend the return value
7334 * to that size. Note that the caller, handle_vmread, might need to use only
7335 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7336 * 64-bit fields are to be returned).
7338 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7339 unsigned long field
, u64
*ret
)
7341 short offset
= vmcs_field_to_offset(field
);
7347 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7349 switch (vmcs_field_type(field
)) {
7350 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7351 *ret
= *((natural_width
*)p
);
7353 case VMCS_FIELD_TYPE_U16
:
7356 case VMCS_FIELD_TYPE_U32
:
7359 case VMCS_FIELD_TYPE_U64
:
7369 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7370 unsigned long field
, u64 field_value
){
7371 short offset
= vmcs_field_to_offset(field
);
7372 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7376 switch (vmcs_field_type(field
)) {
7377 case VMCS_FIELD_TYPE_U16
:
7378 *(u16
*)p
= field_value
;
7380 case VMCS_FIELD_TYPE_U32
:
7381 *(u32
*)p
= field_value
;
7383 case VMCS_FIELD_TYPE_U64
:
7384 *(u64
*)p
= field_value
;
7386 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7387 *(natural_width
*)p
= field_value
;
7396 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7399 unsigned long field
;
7401 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7402 const unsigned long *fields
= shadow_read_write_fields
;
7403 const int num_fields
= max_shadow_read_write_fields
;
7407 vmcs_load(shadow_vmcs
);
7409 for (i
= 0; i
< num_fields
; i
++) {
7411 switch (vmcs_field_type(field
)) {
7412 case VMCS_FIELD_TYPE_U16
:
7413 field_value
= vmcs_read16(field
);
7415 case VMCS_FIELD_TYPE_U32
:
7416 field_value
= vmcs_read32(field
);
7418 case VMCS_FIELD_TYPE_U64
:
7419 field_value
= vmcs_read64(field
);
7421 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7422 field_value
= vmcs_readl(field
);
7428 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7431 vmcs_clear(shadow_vmcs
);
7432 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7437 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7439 const unsigned long *fields
[] = {
7440 shadow_read_write_fields
,
7441 shadow_read_only_fields
7443 const int max_fields
[] = {
7444 max_shadow_read_write_fields
,
7445 max_shadow_read_only_fields
7448 unsigned long field
;
7449 u64 field_value
= 0;
7450 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7452 vmcs_load(shadow_vmcs
);
7454 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7455 for (i
= 0; i
< max_fields
[q
]; i
++) {
7456 field
= fields
[q
][i
];
7457 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7459 switch (vmcs_field_type(field
)) {
7460 case VMCS_FIELD_TYPE_U16
:
7461 vmcs_write16(field
, (u16
)field_value
);
7463 case VMCS_FIELD_TYPE_U32
:
7464 vmcs_write32(field
, (u32
)field_value
);
7466 case VMCS_FIELD_TYPE_U64
:
7467 vmcs_write64(field
, (u64
)field_value
);
7469 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7470 vmcs_writel(field
, (long)field_value
);
7479 vmcs_clear(shadow_vmcs
);
7480 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7484 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7485 * used before) all generate the same failure when it is missing.
7487 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7490 if (vmx
->nested
.current_vmptr
== -1ull) {
7491 nested_vmx_failInvalid(vcpu
);
7497 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7499 unsigned long field
;
7501 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7502 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7505 if (!nested_vmx_check_permission(vcpu
))
7508 if (!nested_vmx_check_vmcs12(vcpu
))
7509 return kvm_skip_emulated_instruction(vcpu
);
7511 /* Decode instruction info and find the field to read */
7512 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7513 /* Read the field, zero-extended to a u64 field_value */
7514 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7515 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7516 return kvm_skip_emulated_instruction(vcpu
);
7519 * Now copy part of this value to register or memory, as requested.
7520 * Note that the number of bits actually copied is 32 or 64 depending
7521 * on the guest's mode (32 or 64 bit), not on the given field's length.
7523 if (vmx_instruction_info
& (1u << 10)) {
7524 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7527 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7528 vmx_instruction_info
, true, &gva
))
7530 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7531 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7532 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7535 nested_vmx_succeed(vcpu
);
7536 return kvm_skip_emulated_instruction(vcpu
);
7540 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7542 unsigned long field
;
7544 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7545 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7546 /* The value to write might be 32 or 64 bits, depending on L1's long
7547 * mode, and eventually we need to write that into a field of several
7548 * possible lengths. The code below first zero-extends the value to 64
7549 * bit (field_value), and then copies only the appropriate number of
7550 * bits into the vmcs12 field.
7552 u64 field_value
= 0;
7553 struct x86_exception e
;
7555 if (!nested_vmx_check_permission(vcpu
))
7558 if (!nested_vmx_check_vmcs12(vcpu
))
7559 return kvm_skip_emulated_instruction(vcpu
);
7561 if (vmx_instruction_info
& (1u << 10))
7562 field_value
= kvm_register_readl(vcpu
,
7563 (((vmx_instruction_info
) >> 3) & 0xf));
7565 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7566 vmx_instruction_info
, false, &gva
))
7568 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7569 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7570 kvm_inject_page_fault(vcpu
, &e
);
7576 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7577 if (vmcs_field_readonly(field
)) {
7578 nested_vmx_failValid(vcpu
,
7579 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7580 return kvm_skip_emulated_instruction(vcpu
);
7583 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7584 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7585 return kvm_skip_emulated_instruction(vcpu
);
7588 nested_vmx_succeed(vcpu
);
7589 return kvm_skip_emulated_instruction(vcpu
);
7592 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7594 vmx
->nested
.current_vmptr
= vmptr
;
7595 if (enable_shadow_vmcs
) {
7596 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7597 SECONDARY_EXEC_SHADOW_VMCS
);
7598 vmcs_write64(VMCS_LINK_POINTER
,
7599 __pa(vmx
->vmcs01
.shadow_vmcs
));
7600 vmx
->nested
.sync_shadow_vmcs
= true;
7604 /* Emulate the VMPTRLD instruction */
7605 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7610 if (!nested_vmx_check_permission(vcpu
))
7613 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7616 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7617 struct vmcs12
*new_vmcs12
;
7619 page
= nested_get_page(vcpu
, vmptr
);
7621 nested_vmx_failInvalid(vcpu
);
7622 return kvm_skip_emulated_instruction(vcpu
);
7624 new_vmcs12
= kmap(page
);
7625 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7627 nested_release_page_clean(page
);
7628 nested_vmx_failValid(vcpu
,
7629 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7630 return kvm_skip_emulated_instruction(vcpu
);
7633 nested_release_vmcs12(vmx
);
7634 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7635 vmx
->nested
.current_vmcs12_page
= page
;
7637 * Load VMCS12 from guest memory since it is not already
7640 memcpy(vmx
->nested
.cached_vmcs12
,
7641 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7642 set_current_vmptr(vmx
, vmptr
);
7645 nested_vmx_succeed(vcpu
);
7646 return kvm_skip_emulated_instruction(vcpu
);
7649 /* Emulate the VMPTRST instruction */
7650 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7652 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7653 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7655 struct x86_exception e
;
7657 if (!nested_vmx_check_permission(vcpu
))
7660 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7661 vmx_instruction_info
, true, &vmcs_gva
))
7663 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7664 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7665 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7667 kvm_inject_page_fault(vcpu
, &e
);
7670 nested_vmx_succeed(vcpu
);
7671 return kvm_skip_emulated_instruction(vcpu
);
7674 /* Emulate the INVEPT instruction */
7675 static int handle_invept(struct kvm_vcpu
*vcpu
)
7677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7678 u32 vmx_instruction_info
, types
;
7681 struct x86_exception e
;
7686 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7687 SECONDARY_EXEC_ENABLE_EPT
) ||
7688 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7689 kvm_queue_exception(vcpu
, UD_VECTOR
);
7693 if (!nested_vmx_check_permission(vcpu
))
7696 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7697 kvm_queue_exception(vcpu
, UD_VECTOR
);
7701 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7702 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7704 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7706 if (type
>= 32 || !(types
& (1 << type
))) {
7707 nested_vmx_failValid(vcpu
,
7708 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7709 return kvm_skip_emulated_instruction(vcpu
);
7712 /* According to the Intel VMX instruction reference, the memory
7713 * operand is read even if it isn't needed (e.g., for type==global)
7715 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7716 vmx_instruction_info
, false, &gva
))
7718 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7719 sizeof(operand
), &e
)) {
7720 kvm_inject_page_fault(vcpu
, &e
);
7725 case VMX_EPT_EXTENT_GLOBAL
:
7727 * TODO: track mappings and invalidate
7728 * single context requests appropriately
7730 case VMX_EPT_EXTENT_CONTEXT
:
7731 kvm_mmu_sync_roots(vcpu
);
7732 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7733 nested_vmx_succeed(vcpu
);
7740 return kvm_skip_emulated_instruction(vcpu
);
7743 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7745 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7746 u32 vmx_instruction_info
;
7747 unsigned long type
, types
;
7749 struct x86_exception e
;
7752 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7753 SECONDARY_EXEC_ENABLE_VPID
) ||
7754 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7755 kvm_queue_exception(vcpu
, UD_VECTOR
);
7759 if (!nested_vmx_check_permission(vcpu
))
7762 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7763 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7765 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7766 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7768 if (type
>= 32 || !(types
& (1 << type
))) {
7769 nested_vmx_failValid(vcpu
,
7770 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7771 return kvm_skip_emulated_instruction(vcpu
);
7774 /* according to the intel vmx instruction reference, the memory
7775 * operand is read even if it isn't needed (e.g., for type==global)
7777 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7778 vmx_instruction_info
, false, &gva
))
7780 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7782 kvm_inject_page_fault(vcpu
, &e
);
7787 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7788 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7789 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7791 nested_vmx_failValid(vcpu
,
7792 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7793 return kvm_skip_emulated_instruction(vcpu
);
7796 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7800 return kvm_skip_emulated_instruction(vcpu
);
7803 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7804 nested_vmx_succeed(vcpu
);
7806 return kvm_skip_emulated_instruction(vcpu
);
7809 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7811 unsigned long exit_qualification
;
7813 trace_kvm_pml_full(vcpu
->vcpu_id
);
7815 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7818 * PML buffer FULL happened while executing iret from NMI,
7819 * "blocked by NMI" bit has to be set before next VM entry.
7821 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7822 cpu_has_virtual_nmis() &&
7823 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7824 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7825 GUEST_INTR_STATE_NMI
);
7828 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7829 * here.., and there's no userspace involvement needed for PML.
7834 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7836 kvm_lapic_expired_hv_timer(vcpu
);
7841 * The exit handlers return 1 if the exit was handled fully and guest execution
7842 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7843 * to be done to userspace and return 0.
7845 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7846 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7847 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7848 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7849 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7850 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7851 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7852 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7853 [EXIT_REASON_CPUID
] = handle_cpuid
,
7854 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7855 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7856 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7857 [EXIT_REASON_HLT
] = handle_halt
,
7858 [EXIT_REASON_INVD
] = handle_invd
,
7859 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7860 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7861 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7862 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7863 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7864 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7865 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7866 [EXIT_REASON_VMREAD
] = handle_vmread
,
7867 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7868 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7869 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7870 [EXIT_REASON_VMON
] = handle_vmon
,
7871 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7872 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7873 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7874 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7875 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7876 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7877 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7878 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7879 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7880 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7881 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7882 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7883 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7884 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7885 [EXIT_REASON_INVEPT
] = handle_invept
,
7886 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7887 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7888 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7889 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7890 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7893 static const int kvm_vmx_max_exit_handlers
=
7894 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7896 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7897 struct vmcs12
*vmcs12
)
7899 unsigned long exit_qualification
;
7900 gpa_t bitmap
, last_bitmap
;
7905 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7906 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7908 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7910 port
= exit_qualification
>> 16;
7911 size
= (exit_qualification
& 7) + 1;
7913 last_bitmap
= (gpa_t
)-1;
7918 bitmap
= vmcs12
->io_bitmap_a
;
7919 else if (port
< 0x10000)
7920 bitmap
= vmcs12
->io_bitmap_b
;
7923 bitmap
+= (port
& 0x7fff) / 8;
7925 if (last_bitmap
!= bitmap
)
7926 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7928 if (b
& (1 << (port
& 7)))
7933 last_bitmap
= bitmap
;
7940 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7941 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7942 * disinterest in the current event (read or write a specific MSR) by using an
7943 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7945 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7946 struct vmcs12
*vmcs12
, u32 exit_reason
)
7948 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7951 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7955 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7956 * for the four combinations of read/write and low/high MSR numbers.
7957 * First we need to figure out which of the four to use:
7959 bitmap
= vmcs12
->msr_bitmap
;
7960 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7962 if (msr_index
>= 0xc0000000) {
7963 msr_index
-= 0xc0000000;
7967 /* Then read the msr_index'th bit from this bitmap: */
7968 if (msr_index
< 1024*8) {
7970 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7972 return 1 & (b
>> (msr_index
& 7));
7974 return true; /* let L1 handle the wrong parameter */
7978 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7979 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7980 * intercept (via guest_host_mask etc.) the current event.
7982 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7983 struct vmcs12
*vmcs12
)
7985 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7986 int cr
= exit_qualification
& 15;
7987 int reg
= (exit_qualification
>> 8) & 15;
7988 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7990 switch ((exit_qualification
>> 4) & 3) {
7991 case 0: /* mov to cr */
7994 if (vmcs12
->cr0_guest_host_mask
&
7995 (val
^ vmcs12
->cr0_read_shadow
))
7999 if ((vmcs12
->cr3_target_count
>= 1 &&
8000 vmcs12
->cr3_target_value0
== val
) ||
8001 (vmcs12
->cr3_target_count
>= 2 &&
8002 vmcs12
->cr3_target_value1
== val
) ||
8003 (vmcs12
->cr3_target_count
>= 3 &&
8004 vmcs12
->cr3_target_value2
== val
) ||
8005 (vmcs12
->cr3_target_count
>= 4 &&
8006 vmcs12
->cr3_target_value3
== val
))
8008 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8012 if (vmcs12
->cr4_guest_host_mask
&
8013 (vmcs12
->cr4_read_shadow
^ val
))
8017 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8023 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8024 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8027 case 1: /* mov from cr */
8030 if (vmcs12
->cpu_based_vm_exec_control
&
8031 CPU_BASED_CR3_STORE_EXITING
)
8035 if (vmcs12
->cpu_based_vm_exec_control
&
8036 CPU_BASED_CR8_STORE_EXITING
)
8043 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8044 * cr0. Other attempted changes are ignored, with no exit.
8046 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8047 (val
^ vmcs12
->cr0_read_shadow
))
8049 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8050 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8059 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8060 * should handle it ourselves in L0 (and then continue L2). Only call this
8061 * when in is_guest_mode (L2).
8063 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
8065 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8067 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8068 u32 exit_reason
= vmx
->exit_reason
;
8070 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8071 vmcs_readl(EXIT_QUALIFICATION
),
8072 vmx
->idt_vectoring_info
,
8074 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8077 if (vmx
->nested
.nested_run_pending
)
8080 if (unlikely(vmx
->fail
)) {
8081 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8082 vmcs_read32(VM_INSTRUCTION_ERROR
));
8086 switch (exit_reason
) {
8087 case EXIT_REASON_EXCEPTION_NMI
:
8088 if (is_nmi(intr_info
))
8090 else if (is_page_fault(intr_info
))
8092 else if (is_no_device(intr_info
) &&
8093 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8095 else if (is_debug(intr_info
) &&
8097 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8099 else if (is_breakpoint(intr_info
) &&
8100 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8102 return vmcs12
->exception_bitmap
&
8103 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8104 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8106 case EXIT_REASON_TRIPLE_FAULT
:
8108 case EXIT_REASON_PENDING_INTERRUPT
:
8109 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8110 case EXIT_REASON_NMI_WINDOW
:
8111 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8112 case EXIT_REASON_TASK_SWITCH
:
8114 case EXIT_REASON_CPUID
:
8116 case EXIT_REASON_HLT
:
8117 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8118 case EXIT_REASON_INVD
:
8120 case EXIT_REASON_INVLPG
:
8121 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8122 case EXIT_REASON_RDPMC
:
8123 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8124 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8125 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8126 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8127 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8128 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8129 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8130 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8131 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8133 * VMX instructions trap unconditionally. This allows L1 to
8134 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8137 case EXIT_REASON_CR_ACCESS
:
8138 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8139 case EXIT_REASON_DR_ACCESS
:
8140 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8141 case EXIT_REASON_IO_INSTRUCTION
:
8142 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8143 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8144 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8145 case EXIT_REASON_MSR_READ
:
8146 case EXIT_REASON_MSR_WRITE
:
8147 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8148 case EXIT_REASON_INVALID_STATE
:
8150 case EXIT_REASON_MWAIT_INSTRUCTION
:
8151 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8152 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8153 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8154 case EXIT_REASON_MONITOR_INSTRUCTION
:
8155 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8156 case EXIT_REASON_PAUSE_INSTRUCTION
:
8157 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8158 nested_cpu_has2(vmcs12
,
8159 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8160 case EXIT_REASON_MCE_DURING_VMENTRY
:
8162 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8163 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8164 case EXIT_REASON_APIC_ACCESS
:
8165 return nested_cpu_has2(vmcs12
,
8166 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8167 case EXIT_REASON_APIC_WRITE
:
8168 case EXIT_REASON_EOI_INDUCED
:
8169 /* apic_write and eoi_induced should exit unconditionally. */
8171 case EXIT_REASON_EPT_VIOLATION
:
8173 * L0 always deals with the EPT violation. If nested EPT is
8174 * used, and the nested mmu code discovers that the address is
8175 * missing in the guest EPT table (EPT12), the EPT violation
8176 * will be injected with nested_ept_inject_page_fault()
8179 case EXIT_REASON_EPT_MISCONFIG
:
8181 * L2 never uses directly L1's EPT, but rather L0's own EPT
8182 * table (shadow on EPT) or a merged EPT table that L0 built
8183 * (EPT on EPT). So any problems with the structure of the
8184 * table is L0's fault.
8187 case EXIT_REASON_WBINVD
:
8188 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8189 case EXIT_REASON_XSETBV
:
8191 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8193 * This should never happen, since it is not possible to
8194 * set XSS to a non-zero value---neither in L1 nor in L2.
8195 * If if it were, XSS would have to be checked against
8196 * the XSS exit bitmap in vmcs12.
8198 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8199 case EXIT_REASON_PREEMPTION_TIMER
:
8206 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8208 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8209 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8212 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8215 __free_page(vmx
->pml_pg
);
8220 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8222 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8226 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8228 /* Do nothing if PML buffer is empty */
8229 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8232 /* PML index always points to next available PML buffer entity */
8233 if (pml_idx
>= PML_ENTITY_NUM
)
8238 pml_buf
= page_address(vmx
->pml_pg
);
8239 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8242 gpa
= pml_buf
[pml_idx
];
8243 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8244 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8247 /* reset PML index */
8248 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8252 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8253 * Called before reporting dirty_bitmap to userspace.
8255 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8258 struct kvm_vcpu
*vcpu
;
8260 * We only need to kick vcpu out of guest mode here, as PML buffer
8261 * is flushed at beginning of all VMEXITs, and it's obvious that only
8262 * vcpus running in guest are possible to have unflushed GPAs in PML
8265 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8266 kvm_vcpu_kick(vcpu
);
8269 static void vmx_dump_sel(char *name
, uint32_t sel
)
8271 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8272 name
, vmcs_read16(sel
),
8273 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8274 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8275 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8278 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8280 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8281 name
, vmcs_read32(limit
),
8282 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8285 static void dump_vmcs(void)
8287 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8288 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8289 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8290 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8291 u32 secondary_exec_control
= 0;
8292 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8293 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8296 if (cpu_has_secondary_exec_ctrls())
8297 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8299 pr_err("*** Guest State ***\n");
8300 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8301 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8302 vmcs_readl(CR0_GUEST_HOST_MASK
));
8303 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8304 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8305 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8306 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8307 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8309 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8310 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8311 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8312 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8314 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8315 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8316 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8317 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8318 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8319 vmcs_readl(GUEST_SYSENTER_ESP
),
8320 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8321 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8322 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8323 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8324 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8325 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8326 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8327 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8328 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8329 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8330 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8331 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8332 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8333 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8334 efer
, vmcs_read64(GUEST_IA32_PAT
));
8335 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8336 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8337 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8338 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8339 pr_err("PerfGlobCtl = 0x%016llx\n",
8340 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8341 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8342 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8343 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8344 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8345 vmcs_read32(GUEST_ACTIVITY_STATE
));
8346 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8347 pr_err("InterruptStatus = %04x\n",
8348 vmcs_read16(GUEST_INTR_STATUS
));
8350 pr_err("*** Host State ***\n");
8351 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8352 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8353 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8354 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8355 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8356 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8357 vmcs_read16(HOST_TR_SELECTOR
));
8358 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8359 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8360 vmcs_readl(HOST_TR_BASE
));
8361 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8362 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8363 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8364 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8365 vmcs_readl(HOST_CR4
));
8366 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8367 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8368 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8369 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8370 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8371 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8372 vmcs_read64(HOST_IA32_EFER
),
8373 vmcs_read64(HOST_IA32_PAT
));
8374 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8375 pr_err("PerfGlobCtl = 0x%016llx\n",
8376 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8378 pr_err("*** Control State ***\n");
8379 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8380 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8381 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8382 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8383 vmcs_read32(EXCEPTION_BITMAP
),
8384 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8385 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8386 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8387 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8388 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8389 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8390 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8391 vmcs_read32(VM_EXIT_INTR_INFO
),
8392 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8393 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8394 pr_err(" reason=%08x qualification=%016lx\n",
8395 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8396 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8397 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8398 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8399 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8400 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8401 pr_err("TSC Multiplier = 0x%016llx\n",
8402 vmcs_read64(TSC_MULTIPLIER
));
8403 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8404 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8405 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8406 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8407 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8408 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8409 n
= vmcs_read32(CR3_TARGET_COUNT
);
8410 for (i
= 0; i
+ 1 < n
; i
+= 4)
8411 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8412 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8413 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8415 pr_err("CR3 target%u=%016lx\n",
8416 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8417 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8418 pr_err("PLE Gap=%08x Window=%08x\n",
8419 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8420 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8421 pr_err("Virtual processor ID = 0x%04x\n",
8422 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8426 * The guest has exited. See if we can fix it or if we need userspace
8429 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8431 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8432 u32 exit_reason
= vmx
->exit_reason
;
8433 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8435 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8436 vcpu
->arch
.gpa_available
= false;
8439 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8440 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8441 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8442 * mode as if vcpus is in root mode, the PML buffer must has been
8446 vmx_flush_pml_buffer(vcpu
);
8448 /* If guest state is invalid, start emulating */
8449 if (vmx
->emulation_required
)
8450 return handle_invalid_guest_state(vcpu
);
8452 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8453 nested_vmx_vmexit(vcpu
, exit_reason
,
8454 vmcs_read32(VM_EXIT_INTR_INFO
),
8455 vmcs_readl(EXIT_QUALIFICATION
));
8459 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8461 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8462 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8467 if (unlikely(vmx
->fail
)) {
8468 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8469 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8470 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8476 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8477 * delivery event since it indicates guest is accessing MMIO.
8478 * The vm-exit can be triggered again after return to guest that
8479 * will cause infinite loop.
8481 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8482 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8483 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8484 exit_reason
!= EXIT_REASON_PML_FULL
&&
8485 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8486 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8487 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8488 vcpu
->run
->internal
.ndata
= 2;
8489 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8490 vcpu
->run
->internal
.data
[1] = exit_reason
;
8494 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8495 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8496 get_vmcs12(vcpu
))))) {
8497 if (vmx_interrupt_allowed(vcpu
)) {
8498 vmx
->soft_vnmi_blocked
= 0;
8499 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8500 vcpu
->arch
.nmi_pending
) {
8502 * This CPU don't support us in finding the end of an
8503 * NMI-blocked window if the guest runs with IRQs
8504 * disabled. So we pull the trigger after 1 s of
8505 * futile waiting, but inform the user about this.
8507 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8508 "state on VCPU %d after 1 s timeout\n",
8509 __func__
, vcpu
->vcpu_id
);
8510 vmx
->soft_vnmi_blocked
= 0;
8514 if (exit_reason
< kvm_vmx_max_exit_handlers
8515 && kvm_vmx_exit_handlers
[exit_reason
])
8516 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8518 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8520 kvm_queue_exception(vcpu
, UD_VECTOR
);
8525 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8527 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8529 if (is_guest_mode(vcpu
) &&
8530 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8533 if (irr
== -1 || tpr
< irr
) {
8534 vmcs_write32(TPR_THRESHOLD
, 0);
8538 vmcs_write32(TPR_THRESHOLD
, irr
);
8541 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8543 u32 sec_exec_control
;
8545 /* Postpone execution until vmcs01 is the current VMCS. */
8546 if (is_guest_mode(vcpu
)) {
8547 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8551 if (!cpu_has_vmx_virtualize_x2apic_mode())
8554 if (!cpu_need_tpr_shadow(vcpu
))
8557 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8560 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8561 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8563 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8564 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8565 vmx_flush_tlb_ept_only(vcpu
);
8567 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8569 vmx_set_msr_bitmap(vcpu
);
8572 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8574 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8577 * Currently we do not handle the nested case where L2 has an
8578 * APIC access page of its own; that page is still pinned.
8579 * Hence, we skip the case where the VCPU is in guest mode _and_
8580 * L1 prepared an APIC access page for L2.
8582 * For the case where L1 and L2 share the same APIC access page
8583 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8584 * in the vmcs12), this function will only update either the vmcs01
8585 * or the vmcs02. If the former, the vmcs02 will be updated by
8586 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8587 * the next L2->L1 exit.
8589 if (!is_guest_mode(vcpu
) ||
8590 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8591 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8592 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8593 vmx_flush_tlb_ept_only(vcpu
);
8597 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8605 status
= vmcs_read16(GUEST_INTR_STATUS
);
8607 if (max_isr
!= old
) {
8609 status
|= max_isr
<< 8;
8610 vmcs_write16(GUEST_INTR_STATUS
, status
);
8614 static void vmx_set_rvi(int vector
)
8622 status
= vmcs_read16(GUEST_INTR_STATUS
);
8623 old
= (u8
)status
& 0xff;
8624 if ((u8
)vector
!= old
) {
8626 status
|= (u8
)vector
;
8627 vmcs_write16(GUEST_INTR_STATUS
, status
);
8631 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8633 if (!is_guest_mode(vcpu
)) {
8634 vmx_set_rvi(max_irr
);
8642 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8645 if (nested_exit_on_intr(vcpu
))
8649 * Else, fall back to pre-APICv interrupt injection since L2
8650 * is run without virtual interrupt delivery.
8652 if (!kvm_event_needs_reinjection(vcpu
) &&
8653 vmx_interrupt_allowed(vcpu
)) {
8654 kvm_queue_interrupt(vcpu
, max_irr
, false);
8655 vmx_inject_irq(vcpu
);
8659 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8661 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8664 WARN_ON(!vcpu
->arch
.apicv_active
);
8665 if (pi_test_on(&vmx
->pi_desc
)) {
8666 pi_clear_on(&vmx
->pi_desc
);
8668 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8669 * But on x86 this is just a compiler barrier anyway.
8671 smp_mb__after_atomic();
8672 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8674 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8676 vmx_hwapic_irr_update(vcpu
, max_irr
);
8680 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8682 if (!kvm_vcpu_apicv_active(vcpu
))
8685 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8686 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8687 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8688 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8691 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8693 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8695 pi_clear_on(&vmx
->pi_desc
);
8696 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8699 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8703 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8704 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8707 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8708 exit_intr_info
= vmx
->exit_intr_info
;
8710 /* Handle machine checks before interrupts are enabled */
8711 if (is_machine_check(exit_intr_info
))
8712 kvm_machine_check();
8714 /* We need to handle NMIs before interrupts are enabled */
8715 if (is_nmi(exit_intr_info
)) {
8716 kvm_before_handle_nmi(&vmx
->vcpu
);
8718 kvm_after_handle_nmi(&vmx
->vcpu
);
8722 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8724 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8725 register void *__sp
asm(_ASM_SP
);
8727 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8728 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8729 unsigned int vector
;
8730 unsigned long entry
;
8732 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8733 #ifdef CONFIG_X86_64
8737 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8738 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8739 entry
= gate_offset(*desc
);
8741 #ifdef CONFIG_X86_64
8742 "mov %%" _ASM_SP
", %[sp]\n\t"
8743 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8748 __ASM_SIZE(push
) " $%c[cs]\n\t"
8749 "call *%[entry]\n\t"
8751 #ifdef CONFIG_X86_64
8757 [ss
]"i"(__KERNEL_DS
),
8758 [cs
]"i"(__KERNEL_CS
)
8763 static bool vmx_has_high_real_mode_segbase(void)
8765 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8768 static bool vmx_mpx_supported(void)
8770 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8771 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8774 static bool vmx_xsaves_supported(void)
8776 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8777 SECONDARY_EXEC_XSAVES
;
8780 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8785 bool idtv_info_valid
;
8787 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8789 if (cpu_has_virtual_nmis()) {
8790 if (vmx
->nmi_known_unmasked
)
8793 * Can't use vmx->exit_intr_info since we're not sure what
8794 * the exit reason is.
8796 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8797 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8798 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8800 * SDM 3: 27.7.1.2 (September 2008)
8801 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8802 * a guest IRET fault.
8803 * SDM 3: 23.2.2 (September 2008)
8804 * Bit 12 is undefined in any of the following cases:
8805 * If the VM exit sets the valid bit in the IDT-vectoring
8806 * information field.
8807 * If the VM exit is due to a double fault.
8809 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8810 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8811 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8812 GUEST_INTR_STATE_NMI
);
8814 vmx
->nmi_known_unmasked
=
8815 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8816 & GUEST_INTR_STATE_NMI
);
8817 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8818 vmx
->vnmi_blocked_time
+=
8819 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8822 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8823 u32 idt_vectoring_info
,
8824 int instr_len_field
,
8825 int error_code_field
)
8829 bool idtv_info_valid
;
8831 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8833 vcpu
->arch
.nmi_injected
= false;
8834 kvm_clear_exception_queue(vcpu
);
8835 kvm_clear_interrupt_queue(vcpu
);
8837 if (!idtv_info_valid
)
8840 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8842 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8843 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8846 case INTR_TYPE_NMI_INTR
:
8847 vcpu
->arch
.nmi_injected
= true;
8849 * SDM 3: 27.7.1.2 (September 2008)
8850 * Clear bit "block by NMI" before VM entry if a NMI
8853 vmx_set_nmi_mask(vcpu
, false);
8855 case INTR_TYPE_SOFT_EXCEPTION
:
8856 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8858 case INTR_TYPE_HARD_EXCEPTION
:
8859 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8860 u32 err
= vmcs_read32(error_code_field
);
8861 kvm_requeue_exception_e(vcpu
, vector
, err
);
8863 kvm_requeue_exception(vcpu
, vector
);
8865 case INTR_TYPE_SOFT_INTR
:
8866 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8868 case INTR_TYPE_EXT_INTR
:
8869 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8876 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8878 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8879 VM_EXIT_INSTRUCTION_LEN
,
8880 IDT_VECTORING_ERROR_CODE
);
8883 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8885 __vmx_complete_interrupts(vcpu
,
8886 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8887 VM_ENTRY_INSTRUCTION_LEN
,
8888 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8890 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8893 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8896 struct perf_guest_switch_msr
*msrs
;
8898 msrs
= perf_guest_get_msrs(&nr_msrs
);
8903 for (i
= 0; i
< nr_msrs
; i
++)
8904 if (msrs
[i
].host
== msrs
[i
].guest
)
8905 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8907 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8911 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8913 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8917 if (vmx
->hv_deadline_tsc
== -1)
8921 if (vmx
->hv_deadline_tsc
> tscl
)
8922 /* sure to be 32 bit only because checked on set_hv_timer */
8923 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8924 cpu_preemption_timer_multi
);
8928 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8931 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8933 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8934 unsigned long debugctlmsr
, cr4
;
8936 /* Record the guest's net vcpu time for enforced NMI injections. */
8937 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8938 vmx
->entry_time
= ktime_get();
8940 /* Don't enter VMX if guest state is invalid, let the exit handler
8941 start emulation until we arrive back to a valid state */
8942 if (vmx
->emulation_required
)
8945 if (vmx
->ple_window_dirty
) {
8946 vmx
->ple_window_dirty
= false;
8947 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8950 if (vmx
->nested
.sync_shadow_vmcs
) {
8951 copy_vmcs12_to_shadow(vmx
);
8952 vmx
->nested
.sync_shadow_vmcs
= false;
8955 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8956 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8957 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8958 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8960 cr4
= cr4_read_shadow();
8961 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8962 vmcs_writel(HOST_CR4
, cr4
);
8963 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8966 /* When single-stepping over STI and MOV SS, we must clear the
8967 * corresponding interruptibility bits in the guest state. Otherwise
8968 * vmentry fails as it then expects bit 14 (BS) in pending debug
8969 * exceptions being set, but that's not correct for the guest debugging
8971 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8972 vmx_set_interrupt_shadow(vcpu
, 0);
8974 if (vmx
->guest_pkru_valid
)
8975 __write_pkru(vmx
->guest_pkru
);
8977 atomic_switch_perf_msrs(vmx
);
8978 debugctlmsr
= get_debugctlmsr();
8980 vmx_arm_hv_timer(vcpu
);
8982 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8984 /* Store host registers */
8985 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8986 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8987 "push %%" _ASM_CX
" \n\t"
8988 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8990 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8991 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8993 /* Reload cr2 if changed */
8994 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8995 "mov %%cr2, %%" _ASM_DX
" \n\t"
8996 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8998 "mov %%" _ASM_AX
", %%cr2 \n\t"
9000 /* Check if vmlaunch of vmresume is needed */
9001 "cmpl $0, %c[launched](%0) \n\t"
9002 /* Load guest registers. Don't clobber flags. */
9003 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9004 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9005 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9006 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9007 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9008 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9009 #ifdef CONFIG_X86_64
9010 "mov %c[r8](%0), %%r8 \n\t"
9011 "mov %c[r9](%0), %%r9 \n\t"
9012 "mov %c[r10](%0), %%r10 \n\t"
9013 "mov %c[r11](%0), %%r11 \n\t"
9014 "mov %c[r12](%0), %%r12 \n\t"
9015 "mov %c[r13](%0), %%r13 \n\t"
9016 "mov %c[r14](%0), %%r14 \n\t"
9017 "mov %c[r15](%0), %%r15 \n\t"
9019 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9021 /* Enter guest mode */
9023 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9025 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9027 /* Save guest registers, load host registers, keep flags */
9028 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9030 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9031 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9032 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9033 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9034 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9035 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9036 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9037 #ifdef CONFIG_X86_64
9038 "mov %%r8, %c[r8](%0) \n\t"
9039 "mov %%r9, %c[r9](%0) \n\t"
9040 "mov %%r10, %c[r10](%0) \n\t"
9041 "mov %%r11, %c[r11](%0) \n\t"
9042 "mov %%r12, %c[r12](%0) \n\t"
9043 "mov %%r13, %c[r13](%0) \n\t"
9044 "mov %%r14, %c[r14](%0) \n\t"
9045 "mov %%r15, %c[r15](%0) \n\t"
9047 "mov %%cr2, %%" _ASM_AX
" \n\t"
9048 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9050 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9051 "setbe %c[fail](%0) \n\t"
9052 ".pushsection .rodata \n\t"
9053 ".global vmx_return \n\t"
9054 "vmx_return: " _ASM_PTR
" 2b \n\t"
9056 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9057 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9058 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9059 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9060 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9061 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9062 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9063 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9064 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9065 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9066 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9067 #ifdef CONFIG_X86_64
9068 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9069 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9070 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9071 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9072 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9073 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9074 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9075 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9077 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9078 [wordsize
]"i"(sizeof(ulong
))
9080 #ifdef CONFIG_X86_64
9081 , "rax", "rbx", "rdi", "rsi"
9082 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9084 , "eax", "ebx", "edi", "esi"
9088 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9090 update_debugctlmsr(debugctlmsr
);
9092 #ifndef CONFIG_X86_64
9094 * The sysexit path does not restore ds/es, so we must set them to
9095 * a reasonable value ourselves.
9097 * We can't defer this to vmx_load_host_state() since that function
9098 * may be executed in interrupt context, which saves and restore segments
9099 * around it, nullifying its effect.
9101 loadsegment(ds
, __USER_DS
);
9102 loadsegment(es
, __USER_DS
);
9105 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9106 | (1 << VCPU_EXREG_RFLAGS
)
9107 | (1 << VCPU_EXREG_PDPTR
)
9108 | (1 << VCPU_EXREG_SEGMENTS
)
9109 | (1 << VCPU_EXREG_CR3
));
9110 vcpu
->arch
.regs_dirty
= 0;
9112 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9114 vmx
->loaded_vmcs
->launched
= 1;
9116 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9119 * eager fpu is enabled if PKEY is supported and CR4 is switched
9120 * back on host, so it is safe to read guest PKRU from current
9123 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9124 vmx
->guest_pkru
= __read_pkru();
9125 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9126 vmx
->guest_pkru_valid
= true;
9127 __write_pkru(vmx
->host_pkru
);
9129 vmx
->guest_pkru_valid
= false;
9133 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9134 * we did not inject a still-pending event to L1 now because of
9135 * nested_run_pending, we need to re-enable this bit.
9137 if (vmx
->nested
.nested_run_pending
)
9138 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9140 vmx
->nested
.nested_run_pending
= 0;
9142 vmx_complete_atomic_exit(vmx
);
9143 vmx_recover_nmi_blocking(vmx
);
9144 vmx_complete_interrupts(vmx
);
9147 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
9149 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9152 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
9156 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9158 vmx_vcpu_load(vcpu
, cpu
);
9164 * Ensure that the current vmcs of the logical processor is the
9165 * vmcs01 of the vcpu before calling free_nested().
9167 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9169 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9172 r
= vcpu_load(vcpu
);
9174 vmx_load_vmcs01(vcpu
);
9179 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9181 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9184 vmx_destroy_pml_buffer(vmx
);
9185 free_vpid(vmx
->vpid
);
9186 leave_guest_mode(vcpu
);
9187 vmx_free_vcpu_nested(vcpu
);
9188 free_loaded_vmcs(vmx
->loaded_vmcs
);
9189 kfree(vmx
->guest_msrs
);
9190 kvm_vcpu_uninit(vcpu
);
9191 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9194 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9197 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9201 return ERR_PTR(-ENOMEM
);
9203 vmx
->vpid
= allocate_vpid();
9205 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9212 * If PML is turned on, failure on enabling PML just results in failure
9213 * of creating the vcpu, therefore we can simplify PML logic (by
9214 * avoiding dealing with cases, such as enabling PML partially on vcpus
9215 * for the guest, etc.
9218 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9223 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9224 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9227 if (!vmx
->guest_msrs
)
9230 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9231 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9232 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9233 if (!vmx
->loaded_vmcs
->vmcs
)
9236 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
9237 loaded_vmcs_init(vmx
->loaded_vmcs
);
9242 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9243 vmx
->vcpu
.cpu
= cpu
;
9244 err
= vmx_vcpu_setup(vmx
);
9245 vmx_vcpu_put(&vmx
->vcpu
);
9249 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9250 err
= alloc_apic_access_page(kvm
);
9256 if (!kvm
->arch
.ept_identity_map_addr
)
9257 kvm
->arch
.ept_identity_map_addr
=
9258 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9259 err
= init_rmode_identity_map(kvm
);
9265 nested_vmx_setup_ctls_msrs(vmx
);
9266 vmx
->nested
.vpid02
= allocate_vpid();
9269 vmx
->nested
.posted_intr_nv
= -1;
9270 vmx
->nested
.current_vmptr
= -1ull;
9271 vmx
->nested
.current_vmcs12
= NULL
;
9273 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9278 free_vpid(vmx
->nested
.vpid02
);
9279 free_loaded_vmcs(vmx
->loaded_vmcs
);
9281 kfree(vmx
->guest_msrs
);
9283 vmx_destroy_pml_buffer(vmx
);
9285 kvm_vcpu_uninit(&vmx
->vcpu
);
9287 free_vpid(vmx
->vpid
);
9288 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9289 return ERR_PTR(err
);
9292 static void __init
vmx_check_processor_compat(void *rtn
)
9294 struct vmcs_config vmcs_conf
;
9297 if (setup_vmcs_config(&vmcs_conf
) < 0)
9299 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9300 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9301 smp_processor_id());
9306 static int get_ept_level(void)
9308 return VMX_EPT_DEFAULT_GAW
+ 1;
9311 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9316 /* For VT-d and EPT combination
9317 * 1. MMIO: always map as UC
9319 * a. VT-d without snooping control feature: can't guarantee the
9320 * result, try to trust guest.
9321 * b. VT-d with snooping control feature: snooping control feature of
9322 * VT-d engine can guarantee the cache correctness. Just set it
9323 * to WB to keep consistent with host. So the same as item 3.
9324 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9325 * consistent with host MTRR
9328 cache
= MTRR_TYPE_UNCACHABLE
;
9332 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9333 ipat
= VMX_EPT_IPAT_BIT
;
9334 cache
= MTRR_TYPE_WRBACK
;
9338 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9339 ipat
= VMX_EPT_IPAT_BIT
;
9340 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9341 cache
= MTRR_TYPE_WRBACK
;
9343 cache
= MTRR_TYPE_UNCACHABLE
;
9347 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9350 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9353 static int vmx_get_lpage_level(void)
9355 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9356 return PT_DIRECTORY_LEVEL
;
9358 /* For shadow and EPT supported 1GB page */
9359 return PT_PDPE_LEVEL
;
9362 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9365 * These bits in the secondary execution controls field
9366 * are dynamic, the others are mostly based on the hypervisor
9367 * architecture and the guest's CPUID. Do not touch the
9371 SECONDARY_EXEC_SHADOW_VMCS
|
9372 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9373 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9375 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9377 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9378 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9382 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9383 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9385 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9387 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9388 struct kvm_cpuid_entry2
*entry
;
9390 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9391 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9393 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9394 if (entry && (entry->_reg & (_cpuid_mask))) \
9395 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9398 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9399 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9400 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9401 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9402 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9403 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9404 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9405 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9406 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9407 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9408 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9409 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9410 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9411 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9412 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9414 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9415 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9416 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9417 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9418 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9419 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9420 cr4_fixed1_update(bit(11), ecx
, bit(2));
9422 #undef cr4_fixed1_update
9425 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9427 struct kvm_cpuid_entry2
*best
;
9428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9429 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9431 if (vmx_rdtscp_supported()) {
9432 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9433 if (!rdtscp_enabled
)
9434 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9438 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9439 SECONDARY_EXEC_RDTSCP
;
9441 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9442 ~SECONDARY_EXEC_RDTSCP
;
9446 /* Exposing INVPCID only when PCID is exposed */
9447 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9448 if (vmx_invpcid_supported() &&
9449 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9450 !guest_cpuid_has_pcid(vcpu
))) {
9451 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9454 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9457 if (cpu_has_secondary_exec_ctrls())
9458 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9460 if (nested_vmx_allowed(vcpu
))
9461 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9462 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9464 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9465 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9467 if (nested_vmx_allowed(vcpu
))
9468 nested_vmx_cr_fixed1_bits_update(vcpu
);
9471 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9473 if (func
== 1 && nested
)
9474 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9477 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9478 struct x86_exception
*fault
)
9480 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9483 if (fault
->error_code
& PFERR_RSVD_MASK
)
9484 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9486 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9487 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9488 vmcs12
->guest_physical_address
= fault
->address
;
9491 /* Callbacks for nested_ept_init_mmu_context: */
9493 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9495 /* return the page table to be shadowed - in our case, EPT12 */
9496 return get_vmcs12(vcpu
)->ept_pointer
;
9499 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9501 WARN_ON(mmu_is_nested(vcpu
));
9502 kvm_init_shadow_ept_mmu(vcpu
,
9503 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9504 VMX_EPT_EXECUTE_ONLY_BIT
);
9505 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9506 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9507 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9509 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9512 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9514 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9517 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9520 bool inequality
, bit
;
9522 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9524 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9525 vmcs12
->page_fault_error_code_match
;
9526 return inequality
^ bit
;
9529 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9530 struct x86_exception
*fault
)
9532 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9534 WARN_ON(!is_guest_mode(vcpu
));
9536 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9537 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9538 vmcs_read32(VM_EXIT_INTR_INFO
),
9539 vmcs_readl(EXIT_QUALIFICATION
));
9541 kvm_inject_page_fault(vcpu
, fault
);
9544 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9545 struct vmcs12
*vmcs12
);
9547 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9548 struct vmcs12
*vmcs12
)
9550 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9553 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9555 * Translate L1 physical address to host physical
9556 * address for vmcs02. Keep the page pinned, so this
9557 * physical address remains valid. We keep a reference
9558 * to it so we can release it later.
9560 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9561 nested_release_page(vmx
->nested
.apic_access_page
);
9562 vmx
->nested
.apic_access_page
=
9563 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9565 * If translation failed, no matter: This feature asks
9566 * to exit when accessing the given address, and if it
9567 * can never be accessed, this feature won't do
9570 if (vmx
->nested
.apic_access_page
) {
9571 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9572 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9574 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9575 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9577 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9578 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9579 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9580 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9581 kvm_vcpu_reload_apic_access_page(vcpu
);
9584 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9585 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9586 nested_release_page(vmx
->nested
.virtual_apic_page
);
9587 vmx
->nested
.virtual_apic_page
=
9588 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9591 * If translation failed, VM entry will fail because
9592 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9593 * Failing the vm entry is _not_ what the processor
9594 * does but it's basically the only possibility we
9595 * have. We could still enter the guest if CR8 load
9596 * exits are enabled, CR8 store exits are enabled, and
9597 * virtualize APIC access is disabled; in this case
9598 * the processor would never use the TPR shadow and we
9599 * could simply clear the bit from the execution
9600 * control. But such a configuration is useless, so
9601 * let's keep the code simple.
9603 if (vmx
->nested
.virtual_apic_page
) {
9604 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9605 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9609 if (nested_cpu_has_posted_intr(vmcs12
)) {
9610 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9611 kunmap(vmx
->nested
.pi_desc_page
);
9612 nested_release_page(vmx
->nested
.pi_desc_page
);
9614 vmx
->nested
.pi_desc_page
=
9615 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9616 vmx
->nested
.pi_desc
=
9617 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9618 if (!vmx
->nested
.pi_desc
) {
9619 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9622 vmx
->nested
.pi_desc
=
9623 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9624 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9626 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9627 page_to_phys(vmx
->nested
.pi_desc_page
) +
9628 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9631 if (cpu_has_vmx_msr_bitmap() &&
9632 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9633 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9636 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9637 CPU_BASED_USE_MSR_BITMAPS
);
9640 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9642 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9643 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9645 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9648 /* Make sure short timeouts reliably trigger an immediate vmexit.
9649 * hrtimer_start does not guarantee this. */
9650 if (preemption_timeout
<= 1) {
9651 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9655 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9656 preemption_timeout
*= 1000000;
9657 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9658 hrtimer_start(&vmx
->nested
.preemption_timer
,
9659 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9662 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9663 struct vmcs12
*vmcs12
)
9668 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9671 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9675 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9677 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9678 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9685 * Merge L0's and L1's MSR bitmap, return false to indicate that
9686 * we do not use the hardware.
9688 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9689 struct vmcs12
*vmcs12
)
9693 unsigned long *msr_bitmap_l1
;
9694 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9696 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9697 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9700 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9703 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9705 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9707 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9708 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9709 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9710 nested_vmx_disable_intercept_for_msr(
9711 msr_bitmap_l1
, msr_bitmap_l0
,
9714 nested_vmx_disable_intercept_for_msr(
9715 msr_bitmap_l1
, msr_bitmap_l0
,
9716 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9717 MSR_TYPE_R
| MSR_TYPE_W
);
9719 if (nested_cpu_has_vid(vmcs12
)) {
9720 nested_vmx_disable_intercept_for_msr(
9721 msr_bitmap_l1
, msr_bitmap_l0
,
9722 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9724 nested_vmx_disable_intercept_for_msr(
9725 msr_bitmap_l1
, msr_bitmap_l0
,
9726 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9731 nested_release_page_clean(page
);
9736 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9737 struct vmcs12
*vmcs12
)
9739 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9740 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9741 !nested_cpu_has_vid(vmcs12
) &&
9742 !nested_cpu_has_posted_intr(vmcs12
))
9746 * If virtualize x2apic mode is enabled,
9747 * virtualize apic access must be disabled.
9749 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9750 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9754 * If virtual interrupt delivery is enabled,
9755 * we must exit on external interrupts.
9757 if (nested_cpu_has_vid(vmcs12
) &&
9758 !nested_exit_on_intr(vcpu
))
9762 * bits 15:8 should be zero in posted_intr_nv,
9763 * the descriptor address has been already checked
9764 * in nested_get_vmcs12_pages.
9766 if (nested_cpu_has_posted_intr(vmcs12
) &&
9767 (!nested_cpu_has_vid(vmcs12
) ||
9768 !nested_exit_intr_ack_set(vcpu
) ||
9769 vmcs12
->posted_intr_nv
& 0xff00))
9772 /* tpr shadow is needed by all apicv features. */
9773 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9779 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9780 unsigned long count_field
,
9781 unsigned long addr_field
)
9786 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9787 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9793 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9794 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9795 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9796 pr_debug_ratelimited(
9797 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9798 addr_field
, maxphyaddr
, count
, addr
);
9804 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9805 struct vmcs12
*vmcs12
)
9807 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9808 vmcs12
->vm_exit_msr_store_count
== 0 &&
9809 vmcs12
->vm_entry_msr_load_count
== 0)
9810 return 0; /* Fast path */
9811 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9812 VM_EXIT_MSR_LOAD_ADDR
) ||
9813 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9814 VM_EXIT_MSR_STORE_ADDR
) ||
9815 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9816 VM_ENTRY_MSR_LOAD_ADDR
))
9821 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9822 struct vmx_msr_entry
*e
)
9824 /* x2APIC MSR accesses are not allowed */
9825 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9827 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9828 e
->index
== MSR_IA32_UCODE_REV
)
9830 if (e
->reserved
!= 0)
9835 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9836 struct vmx_msr_entry
*e
)
9838 if (e
->index
== MSR_FS_BASE
||
9839 e
->index
== MSR_GS_BASE
||
9840 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9841 nested_vmx_msr_check_common(vcpu
, e
))
9846 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9847 struct vmx_msr_entry
*e
)
9849 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9850 nested_vmx_msr_check_common(vcpu
, e
))
9856 * Load guest's/host's msr at nested entry/exit.
9857 * return 0 for success, entry index for failure.
9859 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9862 struct vmx_msr_entry e
;
9863 struct msr_data msr
;
9865 msr
.host_initiated
= false;
9866 for (i
= 0; i
< count
; i
++) {
9867 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9869 pr_debug_ratelimited(
9870 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9871 __func__
, i
, gpa
+ i
* sizeof(e
));
9874 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9875 pr_debug_ratelimited(
9876 "%s check failed (%u, 0x%x, 0x%x)\n",
9877 __func__
, i
, e
.index
, e
.reserved
);
9880 msr
.index
= e
.index
;
9882 if (kvm_set_msr(vcpu
, &msr
)) {
9883 pr_debug_ratelimited(
9884 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9885 __func__
, i
, e
.index
, e
.value
);
9894 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9897 struct vmx_msr_entry e
;
9899 for (i
= 0; i
< count
; i
++) {
9900 struct msr_data msr_info
;
9901 if (kvm_vcpu_read_guest(vcpu
,
9902 gpa
+ i
* sizeof(e
),
9903 &e
, 2 * sizeof(u32
))) {
9904 pr_debug_ratelimited(
9905 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9906 __func__
, i
, gpa
+ i
* sizeof(e
));
9909 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9910 pr_debug_ratelimited(
9911 "%s check failed (%u, 0x%x, 0x%x)\n",
9912 __func__
, i
, e
.index
, e
.reserved
);
9915 msr_info
.host_initiated
= false;
9916 msr_info
.index
= e
.index
;
9917 if (kvm_get_msr(vcpu
, &msr_info
)) {
9918 pr_debug_ratelimited(
9919 "%s cannot read MSR (%u, 0x%x)\n",
9920 __func__
, i
, e
.index
);
9923 if (kvm_vcpu_write_guest(vcpu
,
9924 gpa
+ i
* sizeof(e
) +
9925 offsetof(struct vmx_msr_entry
, value
),
9926 &msr_info
.data
, sizeof(msr_info
.data
))) {
9927 pr_debug_ratelimited(
9928 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9929 __func__
, i
, e
.index
, msr_info
.data
);
9936 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9938 unsigned long invalid_mask
;
9940 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9941 return (val
& invalid_mask
) == 0;
9945 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9946 * emulating VM entry into a guest with EPT enabled.
9947 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9948 * is assigned to entry_failure_code on failure.
9950 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
9951 u32
*entry_failure_code
)
9953 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
9954 if (!nested_cr3_valid(vcpu
, cr3
)) {
9955 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
9960 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9961 * must not be dereferenced.
9963 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
9965 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
9966 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
9971 vcpu
->arch
.cr3
= cr3
;
9972 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
9975 kvm_mmu_reset_context(vcpu
);
9980 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9981 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9982 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9983 * guest in a way that will both be appropriate to L1's requests, and our
9984 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9985 * function also has additional necessary side-effects, like setting various
9986 * vcpu->arch fields.
9987 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9988 * is assigned to entry_failure_code on failure.
9990 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9991 bool from_vmentry
, u32
*entry_failure_code
)
9993 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9996 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9997 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9998 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9999 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10000 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10001 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10002 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10003 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10004 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10005 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10006 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10007 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10008 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10009 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10010 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10011 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10012 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10013 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10014 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10015 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10016 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10017 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10018 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10019 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10020 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10021 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10022 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10023 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10024 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10025 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10026 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10027 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10028 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10029 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10030 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10031 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10033 if (from_vmentry
&&
10034 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10035 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10036 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10038 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10039 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10041 if (from_vmentry
) {
10042 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10043 vmcs12
->vm_entry_intr_info_field
);
10044 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10045 vmcs12
->vm_entry_exception_error_code
);
10046 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10047 vmcs12
->vm_entry_instruction_len
);
10048 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10049 vmcs12
->guest_interruptibility_info
);
10051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10053 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10054 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10055 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10056 vmcs12
->guest_pending_dbg_exceptions
);
10057 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10058 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10060 if (nested_cpu_has_xsaves(vmcs12
))
10061 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10062 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10064 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10066 /* Preemption timer setting is only taken from vmcs01. */
10067 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10068 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10069 if (vmx
->hv_deadline_tsc
== -1)
10070 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10072 /* Posted interrupts setting is only taken from vmcs12. */
10073 if (nested_cpu_has_posted_intr(vmcs12
)) {
10075 * Note that we use L0's vector here and in
10076 * vmx_deliver_nested_posted_interrupt.
10078 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10079 vmx
->nested
.pi_pending
= false;
10080 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
10082 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10085 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10087 vmx
->nested
.preemption_timer_expired
= false;
10088 if (nested_cpu_has_preemption_timer(vmcs12
))
10089 vmx_start_preemption_timer(vcpu
);
10092 * Whether page-faults are trapped is determined by a combination of
10093 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10094 * If enable_ept, L0 doesn't care about page faults and we should
10095 * set all of these to L1's desires. However, if !enable_ept, L0 does
10096 * care about (at least some) page faults, and because it is not easy
10097 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10098 * to exit on each and every L2 page fault. This is done by setting
10099 * MASK=MATCH=0 and (see below) EB.PF=1.
10100 * Note that below we don't need special code to set EB.PF beyond the
10101 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10102 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10103 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10105 * A problem with this approach (when !enable_ept) is that L1 may be
10106 * injected with more page faults than it asked for. This could have
10107 * caused problems, but in practice existing hypervisors don't care.
10108 * To fix this, we will need to emulate the PFEC checking (on the L1
10109 * page tables), using walk_addr(), when injecting PFs to L1.
10111 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10112 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10113 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10114 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10116 if (cpu_has_secondary_exec_ctrls()) {
10117 exec_control
= vmx_secondary_exec_control(vmx
);
10119 /* Take the following fields only from vmcs12 */
10120 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10121 SECONDARY_EXEC_RDTSCP
|
10122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10123 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10124 if (nested_cpu_has(vmcs12
,
10125 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
10126 exec_control
|= vmcs12
->secondary_vm_exec_control
;
10128 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10129 vmcs_write64(EOI_EXIT_BITMAP0
,
10130 vmcs12
->eoi_exit_bitmap0
);
10131 vmcs_write64(EOI_EXIT_BITMAP1
,
10132 vmcs12
->eoi_exit_bitmap1
);
10133 vmcs_write64(EOI_EXIT_BITMAP2
,
10134 vmcs12
->eoi_exit_bitmap2
);
10135 vmcs_write64(EOI_EXIT_BITMAP3
,
10136 vmcs12
->eoi_exit_bitmap3
);
10137 vmcs_write16(GUEST_INTR_STATUS
,
10138 vmcs12
->guest_intr_status
);
10142 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10143 * nested_get_vmcs12_pages will either fix it up or
10144 * remove the VM execution control.
10146 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10147 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10149 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10154 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10155 * Some constant fields are set here by vmx_set_constant_host_state().
10156 * Other fields are different per CPU, and will be set later when
10157 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10159 vmx_set_constant_host_state(vmx
);
10162 * Set the MSR load/store lists to match L0's settings.
10164 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10165 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10166 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10167 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10168 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10171 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10172 * entry, but only if the current (host) sp changed from the value
10173 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10174 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10175 * here we just force the write to happen on entry.
10179 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10180 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10181 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10182 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10183 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10186 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10187 * nested_get_vmcs12_pages can't fix it up, the illegal value
10188 * will result in a VM entry failure.
10190 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10191 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10192 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10196 * Merging of IO bitmap not currently supported.
10197 * Rather, exit every time.
10199 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10200 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10202 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10204 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10205 * bitwise-or of what L1 wants to trap for L2, and what we want to
10206 * trap. Note that CR0.TS also needs updating - we do this later.
10208 update_exception_bitmap(vcpu
);
10209 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10210 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10212 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10213 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10214 * bits are further modified by vmx_set_efer() below.
10216 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10218 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10219 * emulated by vmx_set_efer(), below.
10221 vm_entry_controls_init(vmx
,
10222 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10223 ~VM_ENTRY_IA32E_MODE
) |
10224 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10226 if (from_vmentry
&&
10227 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10228 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10229 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10230 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10231 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10234 set_cr4_guest_host_mask(vmx
);
10236 if (from_vmentry
&&
10237 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10238 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10240 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10241 vmcs_write64(TSC_OFFSET
,
10242 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10244 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10245 if (kvm_has_tsc_control
)
10246 decache_tsc_multiplier(vmx
);
10250 * There is no direct mapping between vpid02 and vpid12, the
10251 * vpid02 is per-vCPU for L0 and reused while the value of
10252 * vpid12 is changed w/ one invvpid during nested vmentry.
10253 * The vpid12 is allocated by L1 for L2, so it will not
10254 * influence global bitmap(for vpid01 and vpid02 allocation)
10255 * even if spawn a lot of nested vCPUs.
10257 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10258 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10259 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10260 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10261 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10264 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10265 vmx_flush_tlb(vcpu
);
10270 if (nested_cpu_has_ept(vmcs12
)) {
10271 kvm_mmu_unload(vcpu
);
10272 nested_ept_init_mmu_context(vcpu
);
10273 } else if (nested_cpu_has2(vmcs12
,
10274 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10275 vmx_flush_tlb_ept_only(vcpu
);
10279 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10280 * bits which we consider mandatory enabled.
10281 * The CR0_READ_SHADOW is what L2 should have expected to read given
10282 * the specifications by L1; It's not enough to take
10283 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10284 * have more bits than L1 expected.
10286 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10287 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10289 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10290 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10292 if (from_vmentry
&&
10293 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10294 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10295 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10296 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10298 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10299 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10300 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10302 /* Shadow page tables on either EPT or shadow page tables. */
10303 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10304 entry_failure_code
))
10308 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10311 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10314 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10315 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10316 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10317 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10320 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10321 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10325 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10327 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10329 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10330 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10331 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10333 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10334 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10336 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10337 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10339 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10340 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10342 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10343 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10344 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10345 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10346 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10347 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
10348 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10349 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10350 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10351 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10352 vmx
->nested
.nested_vmx_exit_ctls_low
,
10353 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10354 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10355 vmx
->nested
.nested_vmx_entry_ctls_low
,
10356 vmx
->nested
.nested_vmx_entry_ctls_high
))
10357 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10359 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10360 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10361 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10362 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10367 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10372 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10374 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10375 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10378 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10379 vmcs12
->vmcs_link_pointer
!= -1ull) {
10380 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10385 * If the load IA32_EFER VM-entry control is 1, the following checks
10386 * are performed on the field for the IA32_EFER MSR:
10387 * - Bits reserved in the IA32_EFER MSR must be 0.
10388 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10389 * the IA-32e mode guest VM-exit control. It must also be identical
10390 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10393 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10394 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10395 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10396 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10397 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10398 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10399 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10404 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10405 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10406 * the values of the LMA and LME bits in the field must each be that of
10407 * the host address-space size VM-exit control.
10409 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10410 ia32e
= (vmcs12
->vm_exit_controls
&
10411 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10412 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10413 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10414 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10421 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10424 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10425 struct loaded_vmcs
*vmcs02
;
10430 vmcs02
= nested_get_current_vmcs02(vmx
);
10434 enter_guest_mode(vcpu
);
10436 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10437 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10440 vmx
->loaded_vmcs
= vmcs02
;
10441 vmx_vcpu_put(vcpu
);
10442 vmx_vcpu_load(vcpu
, cpu
);
10446 vmx_segment_cache_clear(vmx
);
10448 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10449 leave_guest_mode(vcpu
);
10450 vmx_load_vmcs01(vcpu
);
10451 nested_vmx_entry_failure(vcpu
, vmcs12
,
10452 EXIT_REASON_INVALID_STATE
, exit_qual
);
10456 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10458 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10459 vmcs12
->vm_entry_msr_load_addr
,
10460 vmcs12
->vm_entry_msr_load_count
);
10461 if (msr_entry_idx
) {
10462 leave_guest_mode(vcpu
);
10463 vmx_load_vmcs01(vcpu
);
10464 nested_vmx_entry_failure(vcpu
, vmcs12
,
10465 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10469 vmcs12
->launch_state
= 1;
10472 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10473 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10474 * returned as far as L1 is concerned. It will only return (and set
10475 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10481 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10482 * for running an L2 nested guest.
10484 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10486 struct vmcs12
*vmcs12
;
10487 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10491 if (!nested_vmx_check_permission(vcpu
))
10494 if (!nested_vmx_check_vmcs12(vcpu
))
10497 vmcs12
= get_vmcs12(vcpu
);
10499 if (enable_shadow_vmcs
)
10500 copy_shadow_to_vmcs12(vmx
);
10503 * The nested entry process starts with enforcing various prerequisites
10504 * on vmcs12 as required by the Intel SDM, and act appropriately when
10505 * they fail: As the SDM explains, some conditions should cause the
10506 * instruction to fail, while others will cause the instruction to seem
10507 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10508 * To speed up the normal (success) code path, we should avoid checking
10509 * for misconfigurations which will anyway be caught by the processor
10510 * when using the merged vmcs02.
10512 if (vmcs12
->launch_state
== launch
) {
10513 nested_vmx_failValid(vcpu
,
10514 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10515 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10519 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10521 nested_vmx_failValid(vcpu
, ret
);
10526 * After this point, the trap flag no longer triggers a singlestep trap
10527 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10528 * This is not 100% correct; for performance reasons, we delegate most
10529 * of the checks on host state to the processor. If those fail,
10530 * the singlestep trap is missed.
10532 skip_emulated_instruction(vcpu
);
10534 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10536 nested_vmx_entry_failure(vcpu
, vmcs12
,
10537 EXIT_REASON_INVALID_STATE
, exit_qual
);
10542 * We're finally done with prerequisite checking, and can start with
10543 * the nested entry.
10546 ret
= enter_vmx_non_root_mode(vcpu
, true);
10550 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10551 return kvm_vcpu_halt(vcpu
);
10553 vmx
->nested
.nested_run_pending
= 1;
10558 return kvm_skip_emulated_instruction(vcpu
);
10562 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10563 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10564 * This function returns the new value we should put in vmcs12.guest_cr0.
10565 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10566 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10567 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10568 * didn't trap the bit, because if L1 did, so would L0).
10569 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10570 * been modified by L2, and L1 knows it. So just leave the old value of
10571 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10572 * isn't relevant, because if L0 traps this bit it can set it to anything.
10573 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10574 * changed these bits, and therefore they need to be updated, but L0
10575 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10576 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10578 static inline unsigned long
10579 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10582 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10583 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10584 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10585 vcpu
->arch
.cr0_guest_owned_bits
));
10588 static inline unsigned long
10589 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10592 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10593 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10594 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10595 vcpu
->arch
.cr4_guest_owned_bits
));
10598 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10599 struct vmcs12
*vmcs12
)
10604 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10605 nr
= vcpu
->arch
.exception
.nr
;
10606 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10608 if (kvm_exception_is_soft(nr
)) {
10609 vmcs12
->vm_exit_instruction_len
=
10610 vcpu
->arch
.event_exit_inst_len
;
10611 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10613 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10615 if (vcpu
->arch
.exception
.has_error_code
) {
10616 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10617 vmcs12
->idt_vectoring_error_code
=
10618 vcpu
->arch
.exception
.error_code
;
10621 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10622 } else if (vcpu
->arch
.nmi_injected
) {
10623 vmcs12
->idt_vectoring_info_field
=
10624 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10625 } else if (vcpu
->arch
.interrupt
.pending
) {
10626 nr
= vcpu
->arch
.interrupt
.nr
;
10627 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10629 if (vcpu
->arch
.interrupt
.soft
) {
10630 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10631 vmcs12
->vm_entry_instruction_len
=
10632 vcpu
->arch
.event_exit_inst_len
;
10634 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10636 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10640 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10642 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10644 if (vcpu
->arch
.exception
.pending
||
10645 vcpu
->arch
.nmi_injected
||
10646 vcpu
->arch
.interrupt
.pending
)
10649 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10650 vmx
->nested
.preemption_timer_expired
) {
10651 if (vmx
->nested
.nested_run_pending
)
10653 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10657 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10658 if (vmx
->nested
.nested_run_pending
)
10660 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10661 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10662 INTR_INFO_VALID_MASK
, 0);
10664 * The NMI-triggered VM exit counts as injection:
10665 * clear this one and block further NMIs.
10667 vcpu
->arch
.nmi_pending
= 0;
10668 vmx_set_nmi_mask(vcpu
, true);
10672 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10673 nested_exit_on_intr(vcpu
)) {
10674 if (vmx
->nested
.nested_run_pending
)
10676 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10680 vmx_complete_nested_posted_interrupt(vcpu
);
10684 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10686 ktime_t remaining
=
10687 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10690 if (ktime_to_ns(remaining
) <= 0)
10693 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10694 do_div(value
, 1000000);
10695 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10699 * Update the guest state fields of vmcs12 to reflect changes that
10700 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10701 * VM-entry controls is also updated, since this is really a guest
10704 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10706 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10707 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10709 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10710 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10711 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10713 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10714 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10715 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10716 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10717 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10718 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10719 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10720 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10721 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10722 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10723 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10724 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10725 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10726 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10727 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10728 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10729 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10730 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10731 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10732 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10733 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10734 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10735 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10736 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10737 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10738 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10739 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10740 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10741 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10742 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10743 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10744 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10745 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10746 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10747 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10748 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10750 vmcs12
->guest_interruptibility_info
=
10751 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10752 vmcs12
->guest_pending_dbg_exceptions
=
10753 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10754 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10755 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10757 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10759 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10760 if (vmcs12
->vm_exit_controls
&
10761 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10762 vmcs12
->vmx_preemption_timer_value
=
10763 vmx_get_preemption_timer_value(vcpu
);
10764 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10768 * In some cases (usually, nested EPT), L2 is allowed to change its
10769 * own CR3 without exiting. If it has changed it, we must keep it.
10770 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10771 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10773 * Additionally, restore L2's PDPTR to vmcs12.
10776 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10777 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10778 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10779 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10780 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10783 if (nested_cpu_has_ept(vmcs12
))
10784 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10786 if (nested_cpu_has_vid(vmcs12
))
10787 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10789 vmcs12
->vm_entry_controls
=
10790 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10791 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10793 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10794 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10795 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10798 /* TODO: These cannot have changed unless we have MSR bitmaps and
10799 * the relevant bit asks not to trap the change */
10800 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10801 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10802 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10803 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10804 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10805 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10806 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10807 if (kvm_mpx_supported())
10808 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10809 if (nested_cpu_has_xsaves(vmcs12
))
10810 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10814 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10815 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10816 * and this function updates it to reflect the changes to the guest state while
10817 * L2 was running (and perhaps made some exits which were handled directly by L0
10818 * without going back to L1), and to reflect the exit reason.
10819 * Note that we do not have to copy here all VMCS fields, just those that
10820 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10821 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10822 * which already writes to vmcs12 directly.
10824 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10825 u32 exit_reason
, u32 exit_intr_info
,
10826 unsigned long exit_qualification
)
10828 /* update guest state fields: */
10829 sync_vmcs12(vcpu
, vmcs12
);
10831 /* update exit information fields: */
10833 vmcs12
->vm_exit_reason
= exit_reason
;
10834 vmcs12
->exit_qualification
= exit_qualification
;
10836 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10837 if ((vmcs12
->vm_exit_intr_info
&
10838 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10839 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10840 vmcs12
->vm_exit_intr_error_code
=
10841 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10842 vmcs12
->idt_vectoring_info_field
= 0;
10843 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10844 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10846 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10847 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10848 * instead of reading the real value. */
10849 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10852 * Transfer the event that L0 or L1 may wanted to inject into
10853 * L2 to IDT_VECTORING_INFO_FIELD.
10855 vmcs12_save_pending_event(vcpu
, vmcs12
);
10859 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10860 * preserved above and would only end up incorrectly in L1.
10862 vcpu
->arch
.nmi_injected
= false;
10863 kvm_clear_exception_queue(vcpu
);
10864 kvm_clear_interrupt_queue(vcpu
);
10868 * A part of what we need to when the nested L2 guest exits and we want to
10869 * run its L1 parent, is to reset L1's guest state to the host state specified
10871 * This function is to be called not only on normal nested exit, but also on
10872 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10873 * Failures During or After Loading Guest State").
10874 * This function should be called when the active VMCS is L1's (vmcs01).
10876 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10877 struct vmcs12
*vmcs12
)
10879 struct kvm_segment seg
;
10880 u32 entry_failure_code
;
10882 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10883 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10884 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10885 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10887 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10888 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10890 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10891 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10892 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10894 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10895 * actually changed, because vmx_set_cr0 refers to efer set above.
10897 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10898 * (KVM doesn't change it);
10900 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10901 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10903 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10904 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10905 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10907 nested_ept_uninit_mmu_context(vcpu
);
10910 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10911 * couldn't have changed.
10913 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10914 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10917 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10921 * Trivially support vpid by letting L2s share their parent
10922 * L1's vpid. TODO: move to a more elaborate solution, giving
10923 * each L2 its own vpid and exposing the vpid feature to L1.
10925 vmx_flush_tlb(vcpu
);
10929 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10930 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10931 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10932 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10933 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10935 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10936 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10937 vmcs_write64(GUEST_BNDCFGS
, 0);
10939 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10940 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10941 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10943 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10944 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10945 vmcs12
->host_ia32_perf_global_ctrl
);
10947 /* Set L1 segment info according to Intel SDM
10948 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10949 seg
= (struct kvm_segment
) {
10951 .limit
= 0xFFFFFFFF,
10952 .selector
= vmcs12
->host_cs_selector
,
10958 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10962 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10963 seg
= (struct kvm_segment
) {
10965 .limit
= 0xFFFFFFFF,
10972 seg
.selector
= vmcs12
->host_ds_selector
;
10973 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10974 seg
.selector
= vmcs12
->host_es_selector
;
10975 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10976 seg
.selector
= vmcs12
->host_ss_selector
;
10977 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10978 seg
.selector
= vmcs12
->host_fs_selector
;
10979 seg
.base
= vmcs12
->host_fs_base
;
10980 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10981 seg
.selector
= vmcs12
->host_gs_selector
;
10982 seg
.base
= vmcs12
->host_gs_base
;
10983 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10984 seg
= (struct kvm_segment
) {
10985 .base
= vmcs12
->host_tr_base
,
10987 .selector
= vmcs12
->host_tr_selector
,
10991 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10993 kvm_set_dr(vcpu
, 7, 0x400);
10994 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10996 if (cpu_has_vmx_msr_bitmap())
10997 vmx_set_msr_bitmap(vcpu
);
10999 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11000 vmcs12
->vm_exit_msr_load_count
))
11001 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11005 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11006 * and modify vmcs12 to make it see what it would expect to see there if
11007 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11009 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11010 u32 exit_intr_info
,
11011 unsigned long exit_qualification
)
11013 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11014 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11015 u32 vm_inst_error
= 0;
11017 /* trying to cancel vmlaunch/vmresume is a bug */
11018 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11020 leave_guest_mode(vcpu
);
11021 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11022 exit_qualification
);
11024 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11025 vmcs12
->vm_exit_msr_store_count
))
11026 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11028 if (unlikely(vmx
->fail
))
11029 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11031 vmx_load_vmcs01(vcpu
);
11033 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
11034 && nested_exit_intr_ack_set(vcpu
)) {
11035 int irq
= kvm_cpu_get_interrupt(vcpu
);
11037 vmcs12
->vm_exit_intr_info
= irq
|
11038 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11041 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11042 vmcs12
->exit_qualification
,
11043 vmcs12
->idt_vectoring_info_field
,
11044 vmcs12
->vm_exit_intr_info
,
11045 vmcs12
->vm_exit_intr_error_code
,
11048 vm_entry_controls_reset_shadow(vmx
);
11049 vm_exit_controls_reset_shadow(vmx
);
11050 vmx_segment_cache_clear(vmx
);
11052 /* if no vmcs02 cache requested, remove the one we used */
11053 if (VMCS02_POOL_SIZE
== 0)
11054 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11056 load_vmcs12_host_state(vcpu
, vmcs12
);
11058 /* Update any VMCS fields that might have changed while L2 ran */
11059 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11060 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11061 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11062 if (vmx
->hv_deadline_tsc
== -1)
11063 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11064 PIN_BASED_VMX_PREEMPTION_TIMER
);
11066 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11067 PIN_BASED_VMX_PREEMPTION_TIMER
);
11068 if (kvm_has_tsc_control
)
11069 decache_tsc_multiplier(vmx
);
11071 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11072 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11073 vmx_set_virtual_x2apic_mode(vcpu
,
11074 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11075 } else if (!nested_cpu_has_ept(vmcs12
) &&
11076 nested_cpu_has2(vmcs12
,
11077 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11078 vmx_flush_tlb_ept_only(vcpu
);
11081 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11084 /* Unpin physical memory we referred to in vmcs02 */
11085 if (vmx
->nested
.apic_access_page
) {
11086 nested_release_page(vmx
->nested
.apic_access_page
);
11087 vmx
->nested
.apic_access_page
= NULL
;
11089 if (vmx
->nested
.virtual_apic_page
) {
11090 nested_release_page(vmx
->nested
.virtual_apic_page
);
11091 vmx
->nested
.virtual_apic_page
= NULL
;
11093 if (vmx
->nested
.pi_desc_page
) {
11094 kunmap(vmx
->nested
.pi_desc_page
);
11095 nested_release_page(vmx
->nested
.pi_desc_page
);
11096 vmx
->nested
.pi_desc_page
= NULL
;
11097 vmx
->nested
.pi_desc
= NULL
;
11101 * We are now running in L2, mmu_notifier will force to reload the
11102 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11104 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11107 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11108 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11109 * success or failure flag accordingly.
11111 if (unlikely(vmx
->fail
)) {
11113 nested_vmx_failValid(vcpu
, vm_inst_error
);
11115 nested_vmx_succeed(vcpu
);
11116 if (enable_shadow_vmcs
)
11117 vmx
->nested
.sync_shadow_vmcs
= true;
11119 /* in case we halted in L2 */
11120 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11124 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11126 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11128 if (is_guest_mode(vcpu
)) {
11129 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11130 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11132 free_nested(to_vmx(vcpu
));
11136 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11137 * 23.7 "VM-entry failures during or after loading guest state" (this also
11138 * lists the acceptable exit-reason and exit-qualification parameters).
11139 * It should only be called before L2 actually succeeded to run, and when
11140 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11142 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11143 struct vmcs12
*vmcs12
,
11144 u32 reason
, unsigned long qualification
)
11146 load_vmcs12_host_state(vcpu
, vmcs12
);
11147 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11148 vmcs12
->exit_qualification
= qualification
;
11149 nested_vmx_succeed(vcpu
);
11150 if (enable_shadow_vmcs
)
11151 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11154 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11155 struct x86_instruction_info
*info
,
11156 enum x86_intercept_stage stage
)
11158 return X86EMUL_CONTINUE
;
11161 #ifdef CONFIG_X86_64
11162 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11163 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11164 u64 divisor
, u64
*result
)
11166 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11168 /* To avoid the overflow on divq */
11169 if (high
>= divisor
)
11172 /* Low hold the result, high hold rem which is discarded */
11173 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11174 "rm" (divisor
), "0" (low
), "1" (high
));
11180 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11182 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11183 u64 tscl
= rdtsc();
11184 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11185 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11187 /* Convert to host delta tsc if tsc scaling is enabled */
11188 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11189 u64_shl_div_u64(delta_tsc
,
11190 kvm_tsc_scaling_ratio_frac_bits
,
11191 vcpu
->arch
.tsc_scaling_ratio
,
11196 * If the delta tsc can't fit in the 32 bit after the multi shift,
11197 * we can't use the preemption timer.
11198 * It's possible that it fits on later vmentries, but checking
11199 * on every vmentry is costly so we just use an hrtimer.
11201 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11204 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11205 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11206 PIN_BASED_VMX_PREEMPTION_TIMER
);
11210 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11212 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11213 vmx
->hv_deadline_tsc
= -1;
11214 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11215 PIN_BASED_VMX_PREEMPTION_TIMER
);
11219 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11222 shrink_ple_window(vcpu
);
11225 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11226 struct kvm_memory_slot
*slot
)
11228 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11229 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11232 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11233 struct kvm_memory_slot
*slot
)
11235 kvm_mmu_slot_set_dirty(kvm
, slot
);
11238 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11240 kvm_flush_pml_buffers(kvm
);
11243 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11244 struct kvm_memory_slot
*memslot
,
11245 gfn_t offset
, unsigned long mask
)
11247 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11251 * This routine does the following things for vCPU which is going
11252 * to be blocked if VT-d PI is enabled.
11253 * - Store the vCPU to the wakeup list, so when interrupts happen
11254 * we can find the right vCPU to wake up.
11255 * - Change the Posted-interrupt descriptor as below:
11256 * 'NDST' <-- vcpu->pre_pcpu
11257 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11258 * - If 'ON' is set during this process, which means at least one
11259 * interrupt is posted for this vCPU, we cannot block it, in
11260 * this case, return 1, otherwise, return 0.
11263 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11265 unsigned long flags
;
11267 struct pi_desc old
, new;
11268 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11270 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11271 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11272 !kvm_vcpu_apicv_active(vcpu
))
11275 vcpu
->pre_pcpu
= vcpu
->cpu
;
11276 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11277 vcpu
->pre_pcpu
), flags
);
11278 list_add_tail(&vcpu
->blocked_vcpu_list
,
11279 &per_cpu(blocked_vcpu_on_cpu
,
11281 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11282 vcpu
->pre_pcpu
), flags
);
11285 old
.control
= new.control
= pi_desc
->control
;
11288 * We should not block the vCPU if
11289 * an interrupt is posted for it.
11291 if (pi_test_on(pi_desc
) == 1) {
11292 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11293 vcpu
->pre_pcpu
), flags
);
11294 list_del(&vcpu
->blocked_vcpu_list
);
11295 spin_unlock_irqrestore(
11296 &per_cpu(blocked_vcpu_on_cpu_lock
,
11297 vcpu
->pre_pcpu
), flags
);
11298 vcpu
->pre_pcpu
= -1;
11303 WARN((pi_desc
->sn
== 1),
11304 "Warning: SN field of posted-interrupts "
11305 "is set before blocking\n");
11308 * Since vCPU can be preempted during this process,
11309 * vcpu->cpu could be different with pre_pcpu, we
11310 * need to set pre_pcpu as the destination of wakeup
11311 * notification event, then we can find the right vCPU
11312 * to wakeup in wakeup handler if interrupts happen
11313 * when the vCPU is in blocked state.
11315 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11317 if (x2apic_enabled())
11320 new.ndst
= (dest
<< 8) & 0xFF00;
11322 /* set 'NV' to 'wakeup vector' */
11323 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11324 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11325 new.control
) != old
.control
);
11330 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11332 if (pi_pre_block(vcpu
))
11335 if (kvm_lapic_hv_timer_in_use(vcpu
))
11336 kvm_lapic_switch_to_sw_timer(vcpu
);
11341 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11343 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11344 struct pi_desc old
, new;
11346 unsigned long flags
;
11348 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11349 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11350 !kvm_vcpu_apicv_active(vcpu
))
11354 old
.control
= new.control
= pi_desc
->control
;
11356 dest
= cpu_physical_id(vcpu
->cpu
);
11358 if (x2apic_enabled())
11361 new.ndst
= (dest
<< 8) & 0xFF00;
11363 /* Allow posting non-urgent interrupts */
11366 /* set 'NV' to 'notification vector' */
11367 new.nv
= POSTED_INTR_VECTOR
;
11368 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11369 new.control
) != old
.control
);
11371 if(vcpu
->pre_pcpu
!= -1) {
11373 &per_cpu(blocked_vcpu_on_cpu_lock
,
11374 vcpu
->pre_pcpu
), flags
);
11375 list_del(&vcpu
->blocked_vcpu_list
);
11376 spin_unlock_irqrestore(
11377 &per_cpu(blocked_vcpu_on_cpu_lock
,
11378 vcpu
->pre_pcpu
), flags
);
11379 vcpu
->pre_pcpu
= -1;
11383 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11385 if (kvm_x86_ops
->set_hv_timer
)
11386 kvm_lapic_switch_to_hv_timer(vcpu
);
11388 pi_post_block(vcpu
);
11392 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11395 * @host_irq: host irq of the interrupt
11396 * @guest_irq: gsi of the interrupt
11397 * @set: set or unset PI
11398 * returns 0 on success, < 0 on failure
11400 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11401 uint32_t guest_irq
, bool set
)
11403 struct kvm_kernel_irq_routing_entry
*e
;
11404 struct kvm_irq_routing_table
*irq_rt
;
11405 struct kvm_lapic_irq irq
;
11406 struct kvm_vcpu
*vcpu
;
11407 struct vcpu_data vcpu_info
;
11408 int idx
, ret
= -EINVAL
;
11410 if (!kvm_arch_has_assigned_device(kvm
) ||
11411 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11412 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11415 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11416 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11417 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11419 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11420 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11423 * VT-d PI cannot support posting multicast/broadcast
11424 * interrupts to a vCPU, we still use interrupt remapping
11425 * for these kind of interrupts.
11427 * For lowest-priority interrupts, we only support
11428 * those with single CPU as the destination, e.g. user
11429 * configures the interrupts via /proc/irq or uses
11430 * irqbalance to make the interrupts single-CPU.
11432 * We will support full lowest-priority interrupt later.
11435 kvm_set_msi_irq(kvm
, e
, &irq
);
11436 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11438 * Make sure the IRTE is in remapped mode if
11439 * we don't handle it in posted mode.
11441 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11444 "failed to back to remapped mode, irq: %u\n",
11452 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11453 vcpu_info
.vector
= irq
.vector
;
11455 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11456 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11459 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11461 /* suppress notification event before unposting */
11462 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11463 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11464 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11468 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11476 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11480 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11482 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11483 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11484 FEATURE_CONTROL_LMCE
;
11486 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11487 ~FEATURE_CONTROL_LMCE
;
11490 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11491 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11492 .disabled_by_bios
= vmx_disabled_by_bios
,
11493 .hardware_setup
= hardware_setup
,
11494 .hardware_unsetup
= hardware_unsetup
,
11495 .check_processor_compatibility
= vmx_check_processor_compat
,
11496 .hardware_enable
= hardware_enable
,
11497 .hardware_disable
= hardware_disable
,
11498 .cpu_has_accelerated_tpr
= report_flexpriority
,
11499 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11501 .vcpu_create
= vmx_create_vcpu
,
11502 .vcpu_free
= vmx_free_vcpu
,
11503 .vcpu_reset
= vmx_vcpu_reset
,
11505 .prepare_guest_switch
= vmx_save_host_state
,
11506 .vcpu_load
= vmx_vcpu_load
,
11507 .vcpu_put
= vmx_vcpu_put
,
11509 .update_bp_intercept
= update_exception_bitmap
,
11510 .get_msr
= vmx_get_msr
,
11511 .set_msr
= vmx_set_msr
,
11512 .get_segment_base
= vmx_get_segment_base
,
11513 .get_segment
= vmx_get_segment
,
11514 .set_segment
= vmx_set_segment
,
11515 .get_cpl
= vmx_get_cpl
,
11516 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11517 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11518 .decache_cr3
= vmx_decache_cr3
,
11519 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11520 .set_cr0
= vmx_set_cr0
,
11521 .set_cr3
= vmx_set_cr3
,
11522 .set_cr4
= vmx_set_cr4
,
11523 .set_efer
= vmx_set_efer
,
11524 .get_idt
= vmx_get_idt
,
11525 .set_idt
= vmx_set_idt
,
11526 .get_gdt
= vmx_get_gdt
,
11527 .set_gdt
= vmx_set_gdt
,
11528 .get_dr6
= vmx_get_dr6
,
11529 .set_dr6
= vmx_set_dr6
,
11530 .set_dr7
= vmx_set_dr7
,
11531 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11532 .cache_reg
= vmx_cache_reg
,
11533 .get_rflags
= vmx_get_rflags
,
11534 .set_rflags
= vmx_set_rflags
,
11536 .get_pkru
= vmx_get_pkru
,
11538 .tlb_flush
= vmx_flush_tlb
,
11540 .run
= vmx_vcpu_run
,
11541 .handle_exit
= vmx_handle_exit
,
11542 .skip_emulated_instruction
= skip_emulated_instruction
,
11543 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11544 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11545 .patch_hypercall
= vmx_patch_hypercall
,
11546 .set_irq
= vmx_inject_irq
,
11547 .set_nmi
= vmx_inject_nmi
,
11548 .queue_exception
= vmx_queue_exception
,
11549 .cancel_injection
= vmx_cancel_injection
,
11550 .interrupt_allowed
= vmx_interrupt_allowed
,
11551 .nmi_allowed
= vmx_nmi_allowed
,
11552 .get_nmi_mask
= vmx_get_nmi_mask
,
11553 .set_nmi_mask
= vmx_set_nmi_mask
,
11554 .enable_nmi_window
= enable_nmi_window
,
11555 .enable_irq_window
= enable_irq_window
,
11556 .update_cr8_intercept
= update_cr8_intercept
,
11557 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11558 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11559 .get_enable_apicv
= vmx_get_enable_apicv
,
11560 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11561 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11562 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11563 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11564 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11565 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11566 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11568 .set_tss_addr
= vmx_set_tss_addr
,
11569 .get_tdp_level
= get_ept_level
,
11570 .get_mt_mask
= vmx_get_mt_mask
,
11572 .get_exit_info
= vmx_get_exit_info
,
11574 .get_lpage_level
= vmx_get_lpage_level
,
11576 .cpuid_update
= vmx_cpuid_update
,
11578 .rdtscp_supported
= vmx_rdtscp_supported
,
11579 .invpcid_supported
= vmx_invpcid_supported
,
11581 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11583 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11585 .write_tsc_offset
= vmx_write_tsc_offset
,
11587 .set_tdp_cr3
= vmx_set_cr3
,
11589 .check_intercept
= vmx_check_intercept
,
11590 .handle_external_intr
= vmx_handle_external_intr
,
11591 .mpx_supported
= vmx_mpx_supported
,
11592 .xsaves_supported
= vmx_xsaves_supported
,
11594 .check_nested_events
= vmx_check_nested_events
,
11596 .sched_in
= vmx_sched_in
,
11598 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11599 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11600 .flush_log_dirty
= vmx_flush_log_dirty
,
11601 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11603 .pre_block
= vmx_pre_block
,
11604 .post_block
= vmx_post_block
,
11606 .pmu_ops
= &intel_pmu_ops
,
11608 .update_pi_irte
= vmx_update_pi_irte
,
11610 #ifdef CONFIG_X86_64
11611 .set_hv_timer
= vmx_set_hv_timer
,
11612 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11615 .setup_mce
= vmx_setup_mce
,
11618 static int __init
vmx_init(void)
11620 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11621 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11625 #ifdef CONFIG_KEXEC_CORE
11626 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11627 crash_vmclear_local_loaded_vmcss
);
11633 static void __exit
vmx_exit(void)
11635 #ifdef CONFIG_KEXEC_CORE
11636 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11643 module_init(vmx_init
)
11644 module_exit(vmx_exit
)