2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 struct list_head loaded_vmcss_on_cpu_link
;
206 struct shared_msr_entry
{
213 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
214 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
215 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
216 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
217 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
218 * More than one of these structures may exist, if L1 runs multiple L2 guests.
219 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
220 * underlying hardware which will be used to run L2.
221 * This structure is packed to ensure that its layout is identical across
222 * machines (necessary for live migration).
223 * If there are changes in this struct, VMCS12_REVISION must be changed.
225 typedef u64 natural_width
;
226 struct __packed vmcs12
{
227 /* According to the Intel spec, a VMCS region must start with the
228 * following two fields. Then follow implementation-specific data.
233 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
234 u32 padding
[7]; /* room for future expansion */
239 u64 vm_exit_msr_store_addr
;
240 u64 vm_exit_msr_load_addr
;
241 u64 vm_entry_msr_load_addr
;
243 u64 virtual_apic_page_addr
;
244 u64 apic_access_addr
;
245 u64 posted_intr_desc_addr
;
246 u64 vm_function_control
;
248 u64 eoi_exit_bitmap0
;
249 u64 eoi_exit_bitmap1
;
250 u64 eoi_exit_bitmap2
;
251 u64 eoi_exit_bitmap3
;
252 u64 eptp_list_address
;
254 u64 guest_physical_address
;
255 u64 vmcs_link_pointer
;
257 u64 guest_ia32_debugctl
;
260 u64 guest_ia32_perf_global_ctrl
;
268 u64 host_ia32_perf_global_ctrl
;
269 u64 padding64
[8]; /* room for future expansion */
271 * To allow migration of L1 (complete with its L2 guests) between
272 * machines of different natural widths (32 or 64 bit), we cannot have
273 * unsigned long fields with no explict size. We use u64 (aliased
274 * natural_width) instead. Luckily, x86 is little-endian.
276 natural_width cr0_guest_host_mask
;
277 natural_width cr4_guest_host_mask
;
278 natural_width cr0_read_shadow
;
279 natural_width cr4_read_shadow
;
280 natural_width cr3_target_value0
;
281 natural_width cr3_target_value1
;
282 natural_width cr3_target_value2
;
283 natural_width cr3_target_value3
;
284 natural_width exit_qualification
;
285 natural_width guest_linear_address
;
286 natural_width guest_cr0
;
287 natural_width guest_cr3
;
288 natural_width guest_cr4
;
289 natural_width guest_es_base
;
290 natural_width guest_cs_base
;
291 natural_width guest_ss_base
;
292 natural_width guest_ds_base
;
293 natural_width guest_fs_base
;
294 natural_width guest_gs_base
;
295 natural_width guest_ldtr_base
;
296 natural_width guest_tr_base
;
297 natural_width guest_gdtr_base
;
298 natural_width guest_idtr_base
;
299 natural_width guest_dr7
;
300 natural_width guest_rsp
;
301 natural_width guest_rip
;
302 natural_width guest_rflags
;
303 natural_width guest_pending_dbg_exceptions
;
304 natural_width guest_sysenter_esp
;
305 natural_width guest_sysenter_eip
;
306 natural_width host_cr0
;
307 natural_width host_cr3
;
308 natural_width host_cr4
;
309 natural_width host_fs_base
;
310 natural_width host_gs_base
;
311 natural_width host_tr_base
;
312 natural_width host_gdtr_base
;
313 natural_width host_idtr_base
;
314 natural_width host_ia32_sysenter_esp
;
315 natural_width host_ia32_sysenter_eip
;
316 natural_width host_rsp
;
317 natural_width host_rip
;
318 natural_width paddingl
[8]; /* room for future expansion */
319 u32 pin_based_vm_exec_control
;
320 u32 cpu_based_vm_exec_control
;
321 u32 exception_bitmap
;
322 u32 page_fault_error_code_mask
;
323 u32 page_fault_error_code_match
;
324 u32 cr3_target_count
;
325 u32 vm_exit_controls
;
326 u32 vm_exit_msr_store_count
;
327 u32 vm_exit_msr_load_count
;
328 u32 vm_entry_controls
;
329 u32 vm_entry_msr_load_count
;
330 u32 vm_entry_intr_info_field
;
331 u32 vm_entry_exception_error_code
;
332 u32 vm_entry_instruction_len
;
334 u32 secondary_vm_exec_control
;
335 u32 vm_instruction_error
;
337 u32 vm_exit_intr_info
;
338 u32 vm_exit_intr_error_code
;
339 u32 idt_vectoring_info_field
;
340 u32 idt_vectoring_error_code
;
341 u32 vm_exit_instruction_len
;
342 u32 vmx_instruction_info
;
349 u32 guest_ldtr_limit
;
351 u32 guest_gdtr_limit
;
352 u32 guest_idtr_limit
;
353 u32 guest_es_ar_bytes
;
354 u32 guest_cs_ar_bytes
;
355 u32 guest_ss_ar_bytes
;
356 u32 guest_ds_ar_bytes
;
357 u32 guest_fs_ar_bytes
;
358 u32 guest_gs_ar_bytes
;
359 u32 guest_ldtr_ar_bytes
;
360 u32 guest_tr_ar_bytes
;
361 u32 guest_interruptibility_info
;
362 u32 guest_activity_state
;
363 u32 guest_sysenter_cs
;
364 u32 host_ia32_sysenter_cs
;
365 u32 vmx_preemption_timer_value
;
366 u32 padding32
[7]; /* room for future expansion */
367 u16 virtual_processor_id
;
369 u16 guest_es_selector
;
370 u16 guest_cs_selector
;
371 u16 guest_ss_selector
;
372 u16 guest_ds_selector
;
373 u16 guest_fs_selector
;
374 u16 guest_gs_selector
;
375 u16 guest_ldtr_selector
;
376 u16 guest_tr_selector
;
377 u16 guest_intr_status
;
379 u16 host_es_selector
;
380 u16 host_cs_selector
;
381 u16 host_ss_selector
;
382 u16 host_ds_selector
;
383 u16 host_fs_selector
;
384 u16 host_gs_selector
;
385 u16 host_tr_selector
;
389 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
390 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
391 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
393 #define VMCS12_REVISION 0x11e57ed0
396 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
397 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
398 * current implementation, 4K are reserved to avoid future complications.
400 #define VMCS12_SIZE 0x1000
402 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
404 struct list_head list
;
406 struct loaded_vmcs vmcs02
;
410 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
411 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
414 /* Has the level1 guest done vmxon? */
419 /* The guest-physical address of the current VMCS L1 keeps for L2 */
422 * Cache of the guest's VMCS, existing outside of guest memory.
423 * Loaded from guest memory during VMPTRLD. Flushed to guest
424 * memory during VMCLEAR and VMPTRLD.
426 struct vmcs12
*cached_vmcs12
;
428 * Indicates if the shadow vmcs must be updated with the
429 * data hold by vmcs12
431 bool sync_shadow_vmcs
;
433 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
434 struct list_head vmcs02_pool
;
436 bool change_vmcs01_virtual_x2apic_mode
;
437 /* L2 must run next, and mustn't decide to exit to L1. */
438 bool nested_run_pending
;
440 * Guest pages referred to in vmcs02 with host-physical pointers, so
441 * we must keep them pinned while L2 runs.
443 struct page
*apic_access_page
;
444 struct page
*virtual_apic_page
;
445 struct page
*pi_desc_page
;
446 struct pi_desc
*pi_desc
;
450 unsigned long *msr_bitmap
;
452 struct hrtimer preemption_timer
;
453 bool preemption_timer_expired
;
455 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
462 * We only store the "true" versions of the VMX capability MSRs. We
463 * generate the "non-true" versions by setting the must-be-1 bits
464 * according to the SDM.
466 u32 nested_vmx_procbased_ctls_low
;
467 u32 nested_vmx_procbased_ctls_high
;
468 u32 nested_vmx_secondary_ctls_low
;
469 u32 nested_vmx_secondary_ctls_high
;
470 u32 nested_vmx_pinbased_ctls_low
;
471 u32 nested_vmx_pinbased_ctls_high
;
472 u32 nested_vmx_exit_ctls_low
;
473 u32 nested_vmx_exit_ctls_high
;
474 u32 nested_vmx_entry_ctls_low
;
475 u32 nested_vmx_entry_ctls_high
;
476 u32 nested_vmx_misc_low
;
477 u32 nested_vmx_misc_high
;
478 u32 nested_vmx_ept_caps
;
479 u32 nested_vmx_vpid_caps
;
480 u64 nested_vmx_basic
;
481 u64 nested_vmx_cr0_fixed0
;
482 u64 nested_vmx_cr0_fixed1
;
483 u64 nested_vmx_cr4_fixed0
;
484 u64 nested_vmx_cr4_fixed1
;
485 u64 nested_vmx_vmcs_enum
;
486 u64 nested_vmx_vmfunc_controls
;
489 #define POSTED_INTR_ON 0
490 #define POSTED_INTR_SN 1
492 /* Posted-Interrupt Descriptor */
494 u32 pir
[8]; /* Posted interrupt requested */
497 /* bit 256 - Outstanding Notification */
499 /* bit 257 - Suppress Notification */
501 /* bit 271:258 - Reserved */
503 /* bit 279:272 - Notification Vector */
505 /* bit 287:280 - Reserved */
507 /* bit 319:288 - Notification Destination */
515 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
517 return test_and_set_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
523 return test_and_clear_bit(POSTED_INTR_ON
,
524 (unsigned long *)&pi_desc
->control
);
527 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
529 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
532 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
534 return clear_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
540 return set_bit(POSTED_INTR_SN
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
546 clear_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_on(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_ON
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
558 return test_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
563 struct kvm_vcpu vcpu
;
564 unsigned long host_rsp
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
579 u32 secondary_exec_control
;
582 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
583 * non-nested (L1) guest, it always points to vmcs01. For a nested
584 * guest (L2), it points to a different VMCS.
586 struct loaded_vmcs vmcs01
;
587 struct loaded_vmcs
*loaded_vmcs
;
588 bool __launched
; /* temporary, used in vmx_vcpu_run */
589 struct msr_autoload
{
591 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
592 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
596 u16 fs_sel
, gs_sel
, ldt_sel
;
600 int gs_ldt_reload_needed
;
601 int fs_reload_needed
;
602 u64 msr_host_bndcfgs
;
603 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
604 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
609 struct kvm_segment segs
[8];
612 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
613 struct kvm_save_segment
{
621 bool emulation_required
;
625 /* Posted interrupt descriptor */
626 struct pi_desc pi_desc
;
628 /* Support for a guest hypervisor (nested VMX) */
629 struct nested_vmx nested
;
631 /* Dynamic PLE window. */
633 bool ple_window_dirty
;
635 /* Support for PML */
636 #define PML_ENTITY_NUM 512
639 /* apic deadline value in host tsc */
642 u64 current_tsc_ratio
;
644 bool guest_pkru_valid
;
649 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
650 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
651 * in msr_ia32_feature_control_valid_bits.
653 u64 msr_ia32_feature_control
;
654 u64 msr_ia32_feature_control_valid_bits
;
657 enum segment_cache_field
{
666 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
668 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
671 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
673 return &(to_vmx(vcpu
)->pi_desc
);
676 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
677 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
678 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
679 [number##_HIGH] = VMCS12_OFFSET(name)+4
682 static unsigned long shadow_read_only_fields
[] = {
684 * We do NOT shadow fields that are modified when L0
685 * traps and emulates any vmx instruction (e.g. VMPTRLD,
686 * VMXON...) executed by L1.
687 * For example, VM_INSTRUCTION_ERROR is read
688 * by L1 if a vmx instruction fails (part of the error path).
689 * Note the code assumes this logic. If for some reason
690 * we start shadowing these fields then we need to
691 * force a shadow sync when L0 emulates vmx instructions
692 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
693 * by nested_vmx_failValid)
697 VM_EXIT_INSTRUCTION_LEN
,
698 IDT_VECTORING_INFO_FIELD
,
699 IDT_VECTORING_ERROR_CODE
,
700 VM_EXIT_INTR_ERROR_CODE
,
702 GUEST_LINEAR_ADDRESS
,
703 GUEST_PHYSICAL_ADDRESS
705 static int max_shadow_read_only_fields
=
706 ARRAY_SIZE(shadow_read_only_fields
);
708 static unsigned long shadow_read_write_fields
[] = {
715 GUEST_INTERRUPTIBILITY_INFO
,
728 CPU_BASED_VM_EXEC_CONTROL
,
729 VM_ENTRY_EXCEPTION_ERROR_CODE
,
730 VM_ENTRY_INTR_INFO_FIELD
,
731 VM_ENTRY_INSTRUCTION_LEN
,
732 VM_ENTRY_EXCEPTION_ERROR_CODE
,
738 static int max_shadow_read_write_fields
=
739 ARRAY_SIZE(shadow_read_write_fields
);
741 static const unsigned short vmcs_field_to_offset_table
[] = {
742 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
743 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
744 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
745 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
746 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
747 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
748 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
749 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
750 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
751 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
752 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
753 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
754 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
755 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
756 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
757 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
758 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
759 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
760 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
761 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
762 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
763 FIELD64(MSR_BITMAP
, msr_bitmap
),
764 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
765 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
766 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
767 FIELD64(TSC_OFFSET
, tsc_offset
),
768 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
769 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
770 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
771 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
772 FIELD64(EPT_POINTER
, ept_pointer
),
773 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
774 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
775 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
776 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
777 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
778 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
779 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
780 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
781 FIELD64(PML_ADDRESS
, pml_address
),
782 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
783 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
784 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
785 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
786 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
787 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
788 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
789 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
790 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
791 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
792 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
793 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
794 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
795 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
796 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
797 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
798 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
799 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
800 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
801 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
802 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
803 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
804 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
805 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
806 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
807 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
808 FIELD(TPR_THRESHOLD
, tpr_threshold
),
809 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
810 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
811 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
812 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
813 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
814 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
815 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
816 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
817 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
818 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
819 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
820 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
821 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
822 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
823 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
824 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
825 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
826 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
827 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
828 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
829 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
830 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
831 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
832 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
833 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
834 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
835 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
836 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
837 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
838 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
839 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
840 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
841 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
842 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
843 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
844 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
845 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
846 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
847 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
848 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
849 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
850 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
851 FIELD(GUEST_CR0
, guest_cr0
),
852 FIELD(GUEST_CR3
, guest_cr3
),
853 FIELD(GUEST_CR4
, guest_cr4
),
854 FIELD(GUEST_ES_BASE
, guest_es_base
),
855 FIELD(GUEST_CS_BASE
, guest_cs_base
),
856 FIELD(GUEST_SS_BASE
, guest_ss_base
),
857 FIELD(GUEST_DS_BASE
, guest_ds_base
),
858 FIELD(GUEST_FS_BASE
, guest_fs_base
),
859 FIELD(GUEST_GS_BASE
, guest_gs_base
),
860 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
861 FIELD(GUEST_TR_BASE
, guest_tr_base
),
862 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
863 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
864 FIELD(GUEST_DR7
, guest_dr7
),
865 FIELD(GUEST_RSP
, guest_rsp
),
866 FIELD(GUEST_RIP
, guest_rip
),
867 FIELD(GUEST_RFLAGS
, guest_rflags
),
868 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
869 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
870 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
871 FIELD(HOST_CR0
, host_cr0
),
872 FIELD(HOST_CR3
, host_cr3
),
873 FIELD(HOST_CR4
, host_cr4
),
874 FIELD(HOST_FS_BASE
, host_fs_base
),
875 FIELD(HOST_GS_BASE
, host_gs_base
),
876 FIELD(HOST_TR_BASE
, host_tr_base
),
877 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
878 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
879 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
880 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
881 FIELD(HOST_RSP
, host_rsp
),
882 FIELD(HOST_RIP
, host_rip
),
885 static inline short vmcs_field_to_offset(unsigned long field
)
887 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
889 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
890 vmcs_field_to_offset_table
[field
] == 0)
893 return vmcs_field_to_offset_table
[field
];
896 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
898 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
901 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
902 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
903 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
904 static bool vmx_xsaves_supported(void);
905 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
906 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
907 struct kvm_segment
*var
, int seg
);
908 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
909 struct kvm_segment
*var
, int seg
);
910 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
911 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
912 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
913 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
914 static int alloc_identity_pagetable(struct kvm
*kvm
);
915 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
916 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
917 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
920 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
921 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
923 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
924 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
926 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
929 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
930 * can find which vCPU should be waken up.
932 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
933 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
938 VMX_MSR_BITMAP_LEGACY
,
939 VMX_MSR_BITMAP_LONGMODE
,
940 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
941 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
942 VMX_MSR_BITMAP_LEGACY_X2APIC
,
943 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
949 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
951 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
952 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
953 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
954 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
955 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
956 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
957 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
958 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
959 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
960 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
962 static bool cpu_has_load_ia32_efer
;
963 static bool cpu_has_load_perf_global_ctrl
;
965 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
966 static DEFINE_SPINLOCK(vmx_vpid_lock
);
968 static struct vmcs_config
{
973 u32 pin_based_exec_ctrl
;
974 u32 cpu_based_exec_ctrl
;
975 u32 cpu_based_2nd_exec_ctrl
;
980 static struct vmx_capability
{
985 #define VMX_SEGMENT_FIELD(seg) \
986 [VCPU_SREG_##seg] = { \
987 .selector = GUEST_##seg##_SELECTOR, \
988 .base = GUEST_##seg##_BASE, \
989 .limit = GUEST_##seg##_LIMIT, \
990 .ar_bytes = GUEST_##seg##_AR_BYTES, \
993 static const struct kvm_vmx_segment_field
{
998 } kvm_vmx_segment_fields
[] = {
999 VMX_SEGMENT_FIELD(CS
),
1000 VMX_SEGMENT_FIELD(DS
),
1001 VMX_SEGMENT_FIELD(ES
),
1002 VMX_SEGMENT_FIELD(FS
),
1003 VMX_SEGMENT_FIELD(GS
),
1004 VMX_SEGMENT_FIELD(SS
),
1005 VMX_SEGMENT_FIELD(TR
),
1006 VMX_SEGMENT_FIELD(LDTR
),
1009 static u64 host_efer
;
1011 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1014 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1015 * away by decrementing the array size.
1017 static const u32 vmx_msr_index
[] = {
1018 #ifdef CONFIG_X86_64
1019 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1021 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1024 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1026 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1027 INTR_INFO_VALID_MASK
)) ==
1028 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1031 static inline bool is_debug(u32 intr_info
)
1033 return is_exception_n(intr_info
, DB_VECTOR
);
1036 static inline bool is_breakpoint(u32 intr_info
)
1038 return is_exception_n(intr_info
, BP_VECTOR
);
1041 static inline bool is_page_fault(u32 intr_info
)
1043 return is_exception_n(intr_info
, PF_VECTOR
);
1046 static inline bool is_no_device(u32 intr_info
)
1048 return is_exception_n(intr_info
, NM_VECTOR
);
1051 static inline bool is_invalid_opcode(u32 intr_info
)
1053 return is_exception_n(intr_info
, UD_VECTOR
);
1056 static inline bool is_external_interrupt(u32 intr_info
)
1058 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1059 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1062 static inline bool is_machine_check(u32 intr_info
)
1064 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1065 INTR_INFO_VALID_MASK
)) ==
1066 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1069 static inline bool cpu_has_vmx_msr_bitmap(void)
1071 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1074 static inline bool cpu_has_vmx_tpr_shadow(void)
1076 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1079 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1081 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1084 static inline bool cpu_has_secondary_exec_ctrls(void)
1086 return vmcs_config
.cpu_based_exec_ctrl
&
1087 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1090 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1092 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1093 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1096 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1098 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1099 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1102 static inline bool cpu_has_vmx_apic_register_virt(void)
1104 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1105 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1108 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1110 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1111 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1115 * Comment's format: document - errata name - stepping - processor name.
1117 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1119 static u32 vmx_preemption_cpu_tfms
[] = {
1120 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1122 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1123 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1124 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1126 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1128 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1129 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1131 * 320767.pdf - AAP86 - B1 -
1132 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1135 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1137 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1139 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1141 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1142 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1143 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1147 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1149 u32 eax
= cpuid_eax(0x00000001), i
;
1151 /* Clear the reserved bits */
1152 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1153 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1154 if (eax
== vmx_preemption_cpu_tfms
[i
])
1160 static inline bool cpu_has_vmx_preemption_timer(void)
1162 return vmcs_config
.pin_based_exec_ctrl
&
1163 PIN_BASED_VMX_PREEMPTION_TIMER
;
1166 static inline bool cpu_has_vmx_posted_intr(void)
1168 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1169 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1172 static inline bool cpu_has_vmx_apicv(void)
1174 return cpu_has_vmx_apic_register_virt() &&
1175 cpu_has_vmx_virtual_intr_delivery() &&
1176 cpu_has_vmx_posted_intr();
1179 static inline bool cpu_has_vmx_flexpriority(void)
1181 return cpu_has_vmx_tpr_shadow() &&
1182 cpu_has_vmx_virtualize_apic_accesses();
1185 static inline bool cpu_has_vmx_ept_execute_only(void)
1187 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1190 static inline bool cpu_has_vmx_ept_2m_page(void)
1192 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1195 static inline bool cpu_has_vmx_ept_1g_page(void)
1197 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1200 static inline bool cpu_has_vmx_ept_4levels(void)
1202 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1205 static inline bool cpu_has_vmx_ept_mt_wb(void)
1207 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1210 static inline bool cpu_has_vmx_ept_5levels(void)
1212 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1215 static inline bool cpu_has_vmx_ept_ad_bits(void)
1217 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1220 static inline bool cpu_has_vmx_invept_context(void)
1222 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1225 static inline bool cpu_has_vmx_invept_global(void)
1227 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1230 static inline bool cpu_has_vmx_invvpid_single(void)
1232 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1235 static inline bool cpu_has_vmx_invvpid_global(void)
1237 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1240 static inline bool cpu_has_vmx_invvpid(void)
1242 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1245 static inline bool cpu_has_vmx_ept(void)
1247 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1248 SECONDARY_EXEC_ENABLE_EPT
;
1251 static inline bool cpu_has_vmx_unrestricted_guest(void)
1253 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1254 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1257 static inline bool cpu_has_vmx_ple(void)
1259 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1260 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1263 static inline bool cpu_has_vmx_basic_inout(void)
1265 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1268 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1270 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1273 static inline bool cpu_has_vmx_vpid(void)
1275 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1276 SECONDARY_EXEC_ENABLE_VPID
;
1279 static inline bool cpu_has_vmx_rdtscp(void)
1281 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1282 SECONDARY_EXEC_RDTSCP
;
1285 static inline bool cpu_has_vmx_invpcid(void)
1287 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1288 SECONDARY_EXEC_ENABLE_INVPCID
;
1291 static inline bool cpu_has_vmx_wbinvd_exit(void)
1293 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1294 SECONDARY_EXEC_WBINVD_EXITING
;
1297 static inline bool cpu_has_vmx_shadow_vmcs(void)
1300 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1301 /* check if the cpu supports writing r/o exit information fields */
1302 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1305 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1306 SECONDARY_EXEC_SHADOW_VMCS
;
1309 static inline bool cpu_has_vmx_pml(void)
1311 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1314 static inline bool cpu_has_vmx_tsc_scaling(void)
1316 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1317 SECONDARY_EXEC_TSC_SCALING
;
1320 static inline bool cpu_has_vmx_vmfunc(void)
1322 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1323 SECONDARY_EXEC_ENABLE_VMFUNC
;
1326 static inline bool report_flexpriority(void)
1328 return flexpriority_enabled
;
1331 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1333 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1336 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1338 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1341 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1343 return (vmcs12
->cpu_based_vm_exec_control
&
1344 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1345 (vmcs12
->secondary_vm_exec_control
& bit
);
1348 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1350 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1353 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1355 return vmcs12
->pin_based_vm_exec_control
&
1356 PIN_BASED_VMX_PREEMPTION_TIMER
;
1359 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1361 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1364 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1366 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1369 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1371 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1374 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1376 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1379 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1381 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1384 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1386 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1389 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1391 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1394 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1396 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1399 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1401 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1404 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1406 return nested_cpu_has_vmfunc(vmcs12
) &&
1407 (vmcs12
->vm_function_control
&
1408 VMX_VMFUNC_EPTP_SWITCHING
);
1411 static inline bool is_nmi(u32 intr_info
)
1413 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1414 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1417 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1419 unsigned long exit_qualification
);
1420 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1421 struct vmcs12
*vmcs12
,
1422 u32 reason
, unsigned long qualification
);
1424 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1428 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1429 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1434 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1440 } operand
= { vpid
, 0, gva
};
1442 asm volatile (__ex(ASM_VMX_INVVPID
)
1443 /* CF==1 or ZF==1 --> rc = -1 */
1444 "; ja 1f ; ud2 ; 1:"
1445 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1448 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1452 } operand
= {eptp
, gpa
};
1454 asm volatile (__ex(ASM_VMX_INVEPT
)
1455 /* CF==1 or ZF==1 --> rc = -1 */
1456 "; ja 1f ; ud2 ; 1:\n"
1457 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1460 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1464 i
= __find_msr_index(vmx
, msr
);
1466 return &vmx
->guest_msrs
[i
];
1470 static void vmcs_clear(struct vmcs
*vmcs
)
1472 u64 phys_addr
= __pa(vmcs
);
1475 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1476 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1479 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1483 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1485 vmcs_clear(loaded_vmcs
->vmcs
);
1486 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1487 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1488 loaded_vmcs
->cpu
= -1;
1489 loaded_vmcs
->launched
= 0;
1492 static void vmcs_load(struct vmcs
*vmcs
)
1494 u64 phys_addr
= __pa(vmcs
);
1497 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1498 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1501 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1505 #ifdef CONFIG_KEXEC_CORE
1507 * This bitmap is used to indicate whether the vmclear
1508 * operation is enabled on all cpus. All disabled by
1511 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1513 static inline void crash_enable_local_vmclear(int cpu
)
1515 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1518 static inline void crash_disable_local_vmclear(int cpu
)
1520 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1523 static inline int crash_local_vmclear_enabled(int cpu
)
1525 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1528 static void crash_vmclear_local_loaded_vmcss(void)
1530 int cpu
= raw_smp_processor_id();
1531 struct loaded_vmcs
*v
;
1533 if (!crash_local_vmclear_enabled(cpu
))
1536 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1537 loaded_vmcss_on_cpu_link
)
1538 vmcs_clear(v
->vmcs
);
1541 static inline void crash_enable_local_vmclear(int cpu
) { }
1542 static inline void crash_disable_local_vmclear(int cpu
) { }
1543 #endif /* CONFIG_KEXEC_CORE */
1545 static void __loaded_vmcs_clear(void *arg
)
1547 struct loaded_vmcs
*loaded_vmcs
= arg
;
1548 int cpu
= raw_smp_processor_id();
1550 if (loaded_vmcs
->cpu
!= cpu
)
1551 return; /* vcpu migration can race with cpu offline */
1552 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1553 per_cpu(current_vmcs
, cpu
) = NULL
;
1554 crash_disable_local_vmclear(cpu
);
1555 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1558 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1559 * is before setting loaded_vmcs->vcpu to -1 which is done in
1560 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1561 * then adds the vmcs into percpu list before it is deleted.
1565 loaded_vmcs_init(loaded_vmcs
);
1566 crash_enable_local_vmclear(cpu
);
1569 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1571 int cpu
= loaded_vmcs
->cpu
;
1574 smp_call_function_single(cpu
,
1575 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1578 static inline void vpid_sync_vcpu_single(int vpid
)
1583 if (cpu_has_vmx_invvpid_single())
1584 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1587 static inline void vpid_sync_vcpu_global(void)
1589 if (cpu_has_vmx_invvpid_global())
1590 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1593 static inline void vpid_sync_context(int vpid
)
1595 if (cpu_has_vmx_invvpid_single())
1596 vpid_sync_vcpu_single(vpid
);
1598 vpid_sync_vcpu_global();
1601 static inline void ept_sync_global(void)
1603 if (cpu_has_vmx_invept_global())
1604 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1607 static inline void ept_sync_context(u64 eptp
)
1610 if (cpu_has_vmx_invept_context())
1611 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1617 static __always_inline
void vmcs_check16(unsigned long field
)
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1620 "16-bit accessor invalid for 64-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1622 "16-bit accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1624 "16-bit accessor invalid for 32-bit high field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1626 "16-bit accessor invalid for natural width field");
1629 static __always_inline
void vmcs_check32(unsigned long field
)
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1632 "32-bit accessor invalid for 16-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1634 "32-bit accessor invalid for natural width field");
1637 static __always_inline
void vmcs_check64(unsigned long field
)
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1640 "64-bit accessor invalid for 16-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1642 "64-bit accessor invalid for 64-bit high field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1644 "64-bit accessor invalid for 32-bit field");
1645 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1646 "64-bit accessor invalid for natural width field");
1649 static __always_inline
void vmcs_checkl(unsigned long field
)
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1652 "Natural width accessor invalid for 16-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1654 "Natural width accessor invalid for 64-bit field");
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1656 "Natural width accessor invalid for 64-bit high field");
1657 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1658 "Natural width accessor invalid for 32-bit field");
1661 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1663 unsigned long value
;
1665 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1666 : "=a"(value
) : "d"(field
) : "cc");
1670 static __always_inline u16
vmcs_read16(unsigned long field
)
1672 vmcs_check16(field
);
1673 return __vmcs_readl(field
);
1676 static __always_inline u32
vmcs_read32(unsigned long field
)
1678 vmcs_check32(field
);
1679 return __vmcs_readl(field
);
1682 static __always_inline u64
vmcs_read64(unsigned long field
)
1684 vmcs_check64(field
);
1685 #ifdef CONFIG_X86_64
1686 return __vmcs_readl(field
);
1688 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1692 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1695 return __vmcs_readl(field
);
1698 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1700 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1701 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1705 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1709 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1710 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1711 if (unlikely(error
))
1712 vmwrite_error(field
, value
);
1715 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1717 vmcs_check16(field
);
1718 __vmcs_writel(field
, value
);
1721 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1723 vmcs_check32(field
);
1724 __vmcs_writel(field
, value
);
1727 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1729 vmcs_check64(field
);
1730 __vmcs_writel(field
, value
);
1731 #ifndef CONFIG_X86_64
1733 __vmcs_writel(field
+1, value
>> 32);
1737 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1740 __vmcs_writel(field
, value
);
1743 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1745 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1746 "vmcs_clear_bits does not support 64-bit fields");
1747 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1750 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1752 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1753 "vmcs_set_bits does not support 64-bit fields");
1754 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1757 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1759 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1762 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1764 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1765 vmx
->vm_entry_controls_shadow
= val
;
1768 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1770 if (vmx
->vm_entry_controls_shadow
!= val
)
1771 vm_entry_controls_init(vmx
, val
);
1774 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1776 return vmx
->vm_entry_controls_shadow
;
1780 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1782 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1785 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1787 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1790 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1792 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1795 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1797 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1798 vmx
->vm_exit_controls_shadow
= val
;
1801 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1803 if (vmx
->vm_exit_controls_shadow
!= val
)
1804 vm_exit_controls_init(vmx
, val
);
1807 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1809 return vmx
->vm_exit_controls_shadow
;
1813 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1815 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1818 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1820 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1823 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1825 vmx
->segment_cache
.bitmask
= 0;
1828 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1832 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1834 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1835 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1836 vmx
->segment_cache
.bitmask
= 0;
1838 ret
= vmx
->segment_cache
.bitmask
& mask
;
1839 vmx
->segment_cache
.bitmask
|= mask
;
1843 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1845 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1847 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1848 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1852 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1854 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1856 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1857 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1861 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1863 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1865 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1866 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1870 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1872 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1874 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1875 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1879 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1883 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1884 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1885 if ((vcpu
->guest_debug
&
1886 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1887 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1888 eb
|= 1u << BP_VECTOR
;
1889 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1892 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1894 /* When we are running a nested L2 guest and L1 specified for it a
1895 * certain exception bitmap, we must trap the same exceptions and pass
1896 * them to L1. When running L2, we will only handle the exceptions
1897 * specified above if L1 did not want them.
1899 if (is_guest_mode(vcpu
))
1900 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1902 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1905 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1906 unsigned long entry
, unsigned long exit
)
1908 vm_entry_controls_clearbit(vmx
, entry
);
1909 vm_exit_controls_clearbit(vmx
, exit
);
1912 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1915 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1919 if (cpu_has_load_ia32_efer
) {
1920 clear_atomic_switch_msr_special(vmx
,
1921 VM_ENTRY_LOAD_IA32_EFER
,
1922 VM_EXIT_LOAD_IA32_EFER
);
1926 case MSR_CORE_PERF_GLOBAL_CTRL
:
1927 if (cpu_has_load_perf_global_ctrl
) {
1928 clear_atomic_switch_msr_special(vmx
,
1929 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1936 for (i
= 0; i
< m
->nr
; ++i
)
1937 if (m
->guest
[i
].index
== msr
)
1943 m
->guest
[i
] = m
->guest
[m
->nr
];
1944 m
->host
[i
] = m
->host
[m
->nr
];
1945 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1946 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1949 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1950 unsigned long entry
, unsigned long exit
,
1951 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1952 u64 guest_val
, u64 host_val
)
1954 vmcs_write64(guest_val_vmcs
, guest_val
);
1955 vmcs_write64(host_val_vmcs
, host_val
);
1956 vm_entry_controls_setbit(vmx
, entry
);
1957 vm_exit_controls_setbit(vmx
, exit
);
1960 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1961 u64 guest_val
, u64 host_val
)
1964 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1968 if (cpu_has_load_ia32_efer
) {
1969 add_atomic_switch_msr_special(vmx
,
1970 VM_ENTRY_LOAD_IA32_EFER
,
1971 VM_EXIT_LOAD_IA32_EFER
,
1974 guest_val
, host_val
);
1978 case MSR_CORE_PERF_GLOBAL_CTRL
:
1979 if (cpu_has_load_perf_global_ctrl
) {
1980 add_atomic_switch_msr_special(vmx
,
1981 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1982 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1983 GUEST_IA32_PERF_GLOBAL_CTRL
,
1984 HOST_IA32_PERF_GLOBAL_CTRL
,
1985 guest_val
, host_val
);
1989 case MSR_IA32_PEBS_ENABLE
:
1990 /* PEBS needs a quiescent period after being disabled (to write
1991 * a record). Disabling PEBS through VMX MSR swapping doesn't
1992 * provide that period, so a CPU could write host's record into
1995 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1998 for (i
= 0; i
< m
->nr
; ++i
)
1999 if (m
->guest
[i
].index
== msr
)
2002 if (i
== NR_AUTOLOAD_MSRS
) {
2003 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2004 "Can't add msr %x\n", msr
);
2006 } else if (i
== m
->nr
) {
2008 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2009 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2012 m
->guest
[i
].index
= msr
;
2013 m
->guest
[i
].value
= guest_val
;
2014 m
->host
[i
].index
= msr
;
2015 m
->host
[i
].value
= host_val
;
2018 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2020 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2021 u64 ignore_bits
= 0;
2025 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2026 * host CPUID is more efficient than testing guest CPUID
2027 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2029 if (boot_cpu_has(X86_FEATURE_SMEP
))
2030 guest_efer
|= EFER_NX
;
2031 else if (!(guest_efer
& EFER_NX
))
2032 ignore_bits
|= EFER_NX
;
2036 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2038 ignore_bits
|= EFER_SCE
;
2039 #ifdef CONFIG_X86_64
2040 ignore_bits
|= EFER_LMA
| EFER_LME
;
2041 /* SCE is meaningful only in long mode on Intel */
2042 if (guest_efer
& EFER_LMA
)
2043 ignore_bits
&= ~(u64
)EFER_SCE
;
2046 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2049 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2050 * On CPUs that support "load IA32_EFER", always switch EFER
2051 * atomically, since it's faster than switching it manually.
2053 if (cpu_has_load_ia32_efer
||
2054 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2055 if (!(guest_efer
& EFER_LMA
))
2056 guest_efer
&= ~EFER_LME
;
2057 if (guest_efer
!= host_efer
)
2058 add_atomic_switch_msr(vmx
, MSR_EFER
,
2059 guest_efer
, host_efer
);
2062 guest_efer
&= ~ignore_bits
;
2063 guest_efer
|= host_efer
& ignore_bits
;
2065 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2066 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2072 #ifdef CONFIG_X86_32
2074 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2075 * VMCS rather than the segment table. KVM uses this helper to figure
2076 * out the current bases to poke them into the VMCS before entry.
2078 static unsigned long segment_base(u16 selector
)
2080 struct desc_struct
*table
;
2083 if (!(selector
& ~SEGMENT_RPL_MASK
))
2086 table
= get_current_gdt_ro();
2088 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2089 u16 ldt_selector
= kvm_read_ldt();
2091 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2094 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2096 v
= get_desc_base(&table
[selector
>> 3]);
2101 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2103 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2106 if (vmx
->host_state
.loaded
)
2109 vmx
->host_state
.loaded
= 1;
2111 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2112 * allow segment selectors with cpl > 0 or ti == 1.
2114 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2115 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2116 savesegment(fs
, vmx
->host_state
.fs_sel
);
2117 if (!(vmx
->host_state
.fs_sel
& 7)) {
2118 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2119 vmx
->host_state
.fs_reload_needed
= 0;
2121 vmcs_write16(HOST_FS_SELECTOR
, 0);
2122 vmx
->host_state
.fs_reload_needed
= 1;
2124 savesegment(gs
, vmx
->host_state
.gs_sel
);
2125 if (!(vmx
->host_state
.gs_sel
& 7))
2126 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2128 vmcs_write16(HOST_GS_SELECTOR
, 0);
2129 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2132 #ifdef CONFIG_X86_64
2133 savesegment(ds
, vmx
->host_state
.ds_sel
);
2134 savesegment(es
, vmx
->host_state
.es_sel
);
2137 #ifdef CONFIG_X86_64
2138 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2139 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2141 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2142 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2145 #ifdef CONFIG_X86_64
2146 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2147 if (is_long_mode(&vmx
->vcpu
))
2148 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2150 if (boot_cpu_has(X86_FEATURE_MPX
))
2151 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2152 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2153 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2154 vmx
->guest_msrs
[i
].data
,
2155 vmx
->guest_msrs
[i
].mask
);
2158 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2160 if (!vmx
->host_state
.loaded
)
2163 ++vmx
->vcpu
.stat
.host_state_reload
;
2164 vmx
->host_state
.loaded
= 0;
2165 #ifdef CONFIG_X86_64
2166 if (is_long_mode(&vmx
->vcpu
))
2167 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2169 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2170 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2171 #ifdef CONFIG_X86_64
2172 load_gs_index(vmx
->host_state
.gs_sel
);
2174 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2177 if (vmx
->host_state
.fs_reload_needed
)
2178 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2179 #ifdef CONFIG_X86_64
2180 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2181 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2182 loadsegment(es
, vmx
->host_state
.es_sel
);
2185 invalidate_tss_limit();
2186 #ifdef CONFIG_X86_64
2187 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2189 if (vmx
->host_state
.msr_host_bndcfgs
)
2190 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2191 load_fixmap_gdt(raw_smp_processor_id());
2194 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2197 __vmx_load_host_state(vmx
);
2201 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2203 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2204 struct pi_desc old
, new;
2207 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2208 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2209 !kvm_vcpu_apicv_active(vcpu
))
2213 old
.control
= new.control
= pi_desc
->control
;
2216 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2217 * are two possible cases:
2218 * 1. After running 'pre_block', context switch
2219 * happened. For this case, 'sn' was set in
2220 * vmx_vcpu_put(), so we need to clear it here.
2221 * 2. After running 'pre_block', we were blocked,
2222 * and woken up by some other guy. For this case,
2223 * we don't need to do anything, 'pi_post_block'
2224 * will do everything for us. However, we cannot
2225 * check whether it is case #1 or case #2 here
2226 * (maybe, not needed), so we also clear sn here,
2227 * I think it is not a big deal.
2229 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2230 if (vcpu
->cpu
!= cpu
) {
2231 dest
= cpu_physical_id(cpu
);
2233 if (x2apic_enabled())
2236 new.ndst
= (dest
<< 8) & 0xFF00;
2239 /* set 'NV' to 'notification vector' */
2240 new.nv
= POSTED_INTR_VECTOR
;
2243 /* Allow posting non-urgent interrupts */
2245 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2246 new.control
) != old
.control
);
2249 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2251 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2252 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2256 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2257 * vcpu mutex is already taken.
2259 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2261 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2262 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2264 if (!already_loaded
) {
2265 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2266 local_irq_disable();
2267 crash_disable_local_vmclear(cpu
);
2270 * Read loaded_vmcs->cpu should be before fetching
2271 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2272 * See the comments in __loaded_vmcs_clear().
2276 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2277 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2278 crash_enable_local_vmclear(cpu
);
2282 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2283 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2284 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2287 if (!already_loaded
) {
2288 void *gdt
= get_current_gdt_ro();
2289 unsigned long sysenter_esp
;
2291 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2294 * Linux uses per-cpu TSS and GDT, so set these when switching
2295 * processors. See 22.2.4.
2297 vmcs_writel(HOST_TR_BASE
,
2298 (unsigned long)this_cpu_ptr(&cpu_tss
));
2299 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2302 * VM exits change the host TR limit to 0x67 after a VM
2303 * exit. This is okay, since 0x67 covers everything except
2304 * the IO bitmap and have have code to handle the IO bitmap
2305 * being lost after a VM exit.
2307 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2309 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2310 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2312 vmx
->loaded_vmcs
->cpu
= cpu
;
2315 /* Setup TSC multiplier */
2316 if (kvm_has_tsc_control
&&
2317 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2318 decache_tsc_multiplier(vmx
);
2320 vmx_vcpu_pi_load(vcpu
, cpu
);
2321 vmx
->host_pkru
= read_pkru();
2324 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2326 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2328 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2329 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2330 !kvm_vcpu_apicv_active(vcpu
))
2333 /* Set SN when the vCPU is preempted */
2334 if (vcpu
->preempted
)
2338 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2340 vmx_vcpu_pi_put(vcpu
);
2342 __vmx_load_host_state(to_vmx(vcpu
));
2345 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2347 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2350 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2353 * Return the cr0 value that a nested guest would read. This is a combination
2354 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2355 * its hypervisor (cr0_read_shadow).
2357 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2359 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2360 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2362 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2364 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2365 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2368 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2370 unsigned long rflags
, save_rflags
;
2372 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2373 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2374 rflags
= vmcs_readl(GUEST_RFLAGS
);
2375 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2376 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2377 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2378 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2380 to_vmx(vcpu
)->rflags
= rflags
;
2382 return to_vmx(vcpu
)->rflags
;
2385 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2387 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2389 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2390 to_vmx(vcpu
)->rflags
= rflags
;
2391 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2392 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2393 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2395 vmcs_writel(GUEST_RFLAGS
, rflags
);
2397 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2398 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2401 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2403 return to_vmx(vcpu
)->guest_pkru
;
2406 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2408 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2411 if (interruptibility
& GUEST_INTR_STATE_STI
)
2412 ret
|= KVM_X86_SHADOW_INT_STI
;
2413 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2414 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2419 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2421 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2422 u32 interruptibility
= interruptibility_old
;
2424 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2426 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2427 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2428 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2429 interruptibility
|= GUEST_INTR_STATE_STI
;
2431 if ((interruptibility
!= interruptibility_old
))
2432 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2435 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2439 rip
= kvm_rip_read(vcpu
);
2440 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2441 kvm_rip_write(vcpu
, rip
);
2443 /* skipping an emulated instruction also counts */
2444 vmx_set_interrupt_shadow(vcpu
, 0);
2447 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2448 unsigned long exit_qual
)
2450 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2451 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2452 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2454 if (vcpu
->arch
.exception
.has_error_code
) {
2455 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2456 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2459 if (kvm_exception_is_soft(nr
))
2460 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2462 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2464 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2465 vmx_get_nmi_mask(vcpu
))
2466 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2468 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2472 * KVM wants to inject page-faults which it got to the guest. This function
2473 * checks whether in a nested guest, we need to inject them to L1 or L2.
2475 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2477 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2478 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2480 if (nr
== PF_VECTOR
) {
2481 if (vcpu
->arch
.exception
.nested_apf
) {
2482 nested_vmx_inject_exception_vmexit(vcpu
,
2483 vcpu
->arch
.apf
.nested_apf_token
);
2487 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2488 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2489 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2490 * can be written only when inject_pending_event runs. This should be
2491 * conditional on a new capability---if the capability is disabled,
2492 * kvm_multiple_exception would write the ancillary information to
2493 * CR2 or DR6, for backwards ABI-compatibility.
2495 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2496 vcpu
->arch
.exception
.error_code
)) {
2497 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2501 unsigned long exit_qual
= 0;
2502 if (nr
== DB_VECTOR
)
2503 exit_qual
= vcpu
->arch
.dr6
;
2505 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2506 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2514 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2517 unsigned nr
= vcpu
->arch
.exception
.nr
;
2518 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2519 bool reinject
= vcpu
->arch
.exception
.reinject
;
2520 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2521 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2523 if (!reinject
&& is_guest_mode(vcpu
) &&
2524 nested_vmx_check_exception(vcpu
))
2527 if (has_error_code
) {
2528 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2529 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2532 if (vmx
->rmode
.vm86_active
) {
2534 if (kvm_exception_is_soft(nr
))
2535 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2536 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2537 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2541 if (kvm_exception_is_soft(nr
)) {
2542 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2543 vmx
->vcpu
.arch
.event_exit_inst_len
);
2544 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2546 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2548 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2551 static bool vmx_rdtscp_supported(void)
2553 return cpu_has_vmx_rdtscp();
2556 static bool vmx_invpcid_supported(void)
2558 return cpu_has_vmx_invpcid() && enable_ept
;
2562 * Swap MSR entry in host/guest MSR entry array.
2564 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2566 struct shared_msr_entry tmp
;
2568 tmp
= vmx
->guest_msrs
[to
];
2569 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2570 vmx
->guest_msrs
[from
] = tmp
;
2573 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2575 unsigned long *msr_bitmap
;
2577 if (is_guest_mode(vcpu
))
2578 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2579 else if (cpu_has_secondary_exec_ctrls() &&
2580 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2581 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2582 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2583 if (is_long_mode(vcpu
))
2584 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2586 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2588 if (is_long_mode(vcpu
))
2589 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2591 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2594 if (is_long_mode(vcpu
))
2595 msr_bitmap
= vmx_msr_bitmap_longmode
;
2597 msr_bitmap
= vmx_msr_bitmap_legacy
;
2600 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2604 * Set up the vmcs to automatically save and restore system
2605 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2606 * mode, as fiddling with msrs is very expensive.
2608 static void setup_msrs(struct vcpu_vmx
*vmx
)
2610 int save_nmsrs
, index
;
2613 #ifdef CONFIG_X86_64
2614 if (is_long_mode(&vmx
->vcpu
)) {
2615 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2617 move_msr_up(vmx
, index
, save_nmsrs
++);
2618 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2620 move_msr_up(vmx
, index
, save_nmsrs
++);
2621 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2623 move_msr_up(vmx
, index
, save_nmsrs
++);
2624 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2625 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2626 move_msr_up(vmx
, index
, save_nmsrs
++);
2628 * MSR_STAR is only needed on long mode guests, and only
2629 * if efer.sce is enabled.
2631 index
= __find_msr_index(vmx
, MSR_STAR
);
2632 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2633 move_msr_up(vmx
, index
, save_nmsrs
++);
2636 index
= __find_msr_index(vmx
, MSR_EFER
);
2637 if (index
>= 0 && update_transition_efer(vmx
, index
))
2638 move_msr_up(vmx
, index
, save_nmsrs
++);
2640 vmx
->save_nmsrs
= save_nmsrs
;
2642 if (cpu_has_vmx_msr_bitmap())
2643 vmx_set_msr_bitmap(&vmx
->vcpu
);
2647 * reads and returns guest's timestamp counter "register"
2648 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2649 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2651 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2653 u64 host_tsc
, tsc_offset
;
2656 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2657 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2661 * writes 'offset' into guest's timestamp counter offset register
2663 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2665 if (is_guest_mode(vcpu
)) {
2667 * We're here if L1 chose not to trap WRMSR to TSC. According
2668 * to the spec, this should set L1's TSC; The offset that L1
2669 * set for L2 remains unchanged, and still needs to be added
2670 * to the newly set TSC to get L2's TSC.
2672 struct vmcs12
*vmcs12
;
2673 /* recalculate vmcs02.TSC_OFFSET: */
2674 vmcs12
= get_vmcs12(vcpu
);
2675 vmcs_write64(TSC_OFFSET
, offset
+
2676 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2677 vmcs12
->tsc_offset
: 0));
2679 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2680 vmcs_read64(TSC_OFFSET
), offset
);
2681 vmcs_write64(TSC_OFFSET
, offset
);
2686 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2687 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2688 * all guests if the "nested" module option is off, and can also be disabled
2689 * for a single guest by disabling its VMX cpuid bit.
2691 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2693 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2697 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2698 * returned for the various VMX controls MSRs when nested VMX is enabled.
2699 * The same values should also be used to verify that vmcs12 control fields are
2700 * valid during nested entry from L1 to L2.
2701 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2702 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2703 * bit in the high half is on if the corresponding bit in the control field
2704 * may be on. See also vmx_control_verify().
2706 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2709 * Note that as a general rule, the high half of the MSRs (bits in
2710 * the control fields which may be 1) should be initialized by the
2711 * intersection of the underlying hardware's MSR (i.e., features which
2712 * can be supported) and the list of features we want to expose -
2713 * because they are known to be properly supported in our code.
2714 * Also, usually, the low half of the MSRs (bits which must be 1) can
2715 * be set to 0, meaning that L1 may turn off any of these bits. The
2716 * reason is that if one of these bits is necessary, it will appear
2717 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2718 * fields of vmcs01 and vmcs02, will turn these bits off - and
2719 * nested_vmx_exit_reflected() will not pass related exits to L1.
2720 * These rules have exceptions below.
2723 /* pin-based controls */
2724 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2725 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2726 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2727 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2728 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2729 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2730 PIN_BASED_EXT_INTR_MASK
|
2731 PIN_BASED_NMI_EXITING
|
2732 PIN_BASED_VIRTUAL_NMIS
;
2733 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2734 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2735 PIN_BASED_VMX_PREEMPTION_TIMER
;
2736 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2737 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2738 PIN_BASED_POSTED_INTR
;
2741 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2742 vmx
->nested
.nested_vmx_exit_ctls_low
,
2743 vmx
->nested
.nested_vmx_exit_ctls_high
);
2744 vmx
->nested
.nested_vmx_exit_ctls_low
=
2745 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2747 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2748 #ifdef CONFIG_X86_64
2749 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2751 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2752 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2753 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2754 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2755 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2757 if (kvm_mpx_supported())
2758 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2760 /* We support free control of debug control saving. */
2761 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2763 /* entry controls */
2764 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2765 vmx
->nested
.nested_vmx_entry_ctls_low
,
2766 vmx
->nested
.nested_vmx_entry_ctls_high
);
2767 vmx
->nested
.nested_vmx_entry_ctls_low
=
2768 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2769 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2770 #ifdef CONFIG_X86_64
2771 VM_ENTRY_IA32E_MODE
|
2773 VM_ENTRY_LOAD_IA32_PAT
;
2774 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2775 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2776 if (kvm_mpx_supported())
2777 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2779 /* We support free control of debug control loading. */
2780 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2782 /* cpu-based controls */
2783 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2784 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2785 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2786 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2787 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2788 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2789 CPU_BASED_VIRTUAL_INTR_PENDING
|
2790 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2791 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2792 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2793 CPU_BASED_CR3_STORE_EXITING
|
2794 #ifdef CONFIG_X86_64
2795 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2797 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2798 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2799 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2800 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2801 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2803 * We can allow some features even when not supported by the
2804 * hardware. For example, L1 can specify an MSR bitmap - and we
2805 * can use it to avoid exits to L1 - even when L0 runs L2
2806 * without MSR bitmaps.
2808 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2809 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2810 CPU_BASED_USE_MSR_BITMAPS
;
2812 /* We support free control of CR3 access interception. */
2813 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2814 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2817 * secondary cpu-based controls. Do not include those that
2818 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2820 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2821 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2822 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2823 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2824 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2825 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2826 SECONDARY_EXEC_DESC
|
2827 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2828 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2829 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2830 SECONDARY_EXEC_WBINVD_EXITING
;
2833 /* nested EPT: emulate EPT also to L1 */
2834 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2835 SECONDARY_EXEC_ENABLE_EPT
;
2836 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2837 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2838 if (cpu_has_vmx_ept_execute_only())
2839 vmx
->nested
.nested_vmx_ept_caps
|=
2840 VMX_EPT_EXECUTE_ONLY_BIT
;
2841 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2842 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2843 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2844 VMX_EPT_1GB_PAGE_BIT
;
2845 if (enable_ept_ad_bits
) {
2846 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2847 SECONDARY_EXEC_ENABLE_PML
;
2848 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2851 vmx
->nested
.nested_vmx_ept_caps
= 0;
2853 if (cpu_has_vmx_vmfunc()) {
2854 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2855 SECONDARY_EXEC_ENABLE_VMFUNC
;
2857 * Advertise EPTP switching unconditionally
2858 * since we emulate it
2860 vmx
->nested
.nested_vmx_vmfunc_controls
=
2861 VMX_VMFUNC_EPTP_SWITCHING
;
2865 * Old versions of KVM use the single-context version without
2866 * checking for support, so declare that it is supported even
2867 * though it is treated as global context. The alternative is
2868 * not failing the single-context invvpid, and it is worse.
2871 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2872 SECONDARY_EXEC_ENABLE_VPID
;
2873 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2874 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2876 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2878 if (enable_unrestricted_guest
)
2879 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2880 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2882 /* miscellaneous data */
2883 rdmsr(MSR_IA32_VMX_MISC
,
2884 vmx
->nested
.nested_vmx_misc_low
,
2885 vmx
->nested
.nested_vmx_misc_high
);
2886 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2887 vmx
->nested
.nested_vmx_misc_low
|=
2888 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2889 VMX_MISC_ACTIVITY_HLT
;
2890 vmx
->nested
.nested_vmx_misc_high
= 0;
2893 * This MSR reports some information about VMX support. We
2894 * should return information about the VMX we emulate for the
2895 * guest, and the VMCS structure we give it - not about the
2896 * VMX support of the underlying hardware.
2898 vmx
->nested
.nested_vmx_basic
=
2900 VMX_BASIC_TRUE_CTLS
|
2901 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2902 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2904 if (cpu_has_vmx_basic_inout())
2905 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2908 * These MSRs specify bits which the guest must keep fixed on
2909 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2910 * We picked the standard core2 setting.
2912 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2913 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2914 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2915 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2917 /* These MSRs specify bits which the guest must keep fixed off. */
2918 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2919 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2921 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2922 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2926 * if fixed0[i] == 1: val[i] must be 1
2927 * if fixed1[i] == 0: val[i] must be 0
2929 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2931 return ((val
& fixed1
) | fixed0
) == val
;
2934 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2936 return fixed_bits_valid(control
, low
, high
);
2939 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2941 return low
| ((u64
)high
<< 32);
2944 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2949 return (superset
| subset
) == superset
;
2952 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2954 const u64 feature_and_reserved
=
2955 /* feature (except bit 48; see below) */
2956 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2958 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2959 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2961 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2965 * KVM does not emulate a version of VMX that constrains physical
2966 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2968 if (data
& BIT_ULL(48))
2971 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2972 vmx_basic_vmcs_revision_id(data
))
2975 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2978 vmx
->nested
.nested_vmx_basic
= data
;
2983 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2988 switch (msr_index
) {
2989 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2990 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2991 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2993 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2994 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2995 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2997 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2998 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2999 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
3001 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3002 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
3003 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
3005 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3006 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
3007 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3013 supported
= vmx_control_msr(*lowp
, *highp
);
3015 /* Check must-be-1 bits are still 1. */
3016 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3019 /* Check must-be-0 bits are still 0. */
3020 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3024 *highp
= data
>> 32;
3028 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3030 const u64 feature_and_reserved_bits
=
3032 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3033 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3035 GENMASK_ULL(13, 9) | BIT_ULL(31);
3038 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3039 vmx
->nested
.nested_vmx_misc_high
);
3041 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3044 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3045 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3046 vmx_misc_preemption_timer_rate(data
) !=
3047 vmx_misc_preemption_timer_rate(vmx_misc
))
3050 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3053 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3056 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3059 vmx
->nested
.nested_vmx_misc_low
= data
;
3060 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3064 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3066 u64 vmx_ept_vpid_cap
;
3068 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3069 vmx
->nested
.nested_vmx_vpid_caps
);
3071 /* Every bit is either reserved or a feature bit. */
3072 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3075 vmx
->nested
.nested_vmx_ept_caps
= data
;
3076 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3080 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3084 switch (msr_index
) {
3085 case MSR_IA32_VMX_CR0_FIXED0
:
3086 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3088 case MSR_IA32_VMX_CR4_FIXED0
:
3089 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3096 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3097 * must be 1 in the restored value.
3099 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3107 * Called when userspace is restoring VMX MSRs.
3109 * Returns 0 on success, non-0 otherwise.
3111 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3113 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3115 switch (msr_index
) {
3116 case MSR_IA32_VMX_BASIC
:
3117 return vmx_restore_vmx_basic(vmx
, data
);
3118 case MSR_IA32_VMX_PINBASED_CTLS
:
3119 case MSR_IA32_VMX_PROCBASED_CTLS
:
3120 case MSR_IA32_VMX_EXIT_CTLS
:
3121 case MSR_IA32_VMX_ENTRY_CTLS
:
3123 * The "non-true" VMX capability MSRs are generated from the
3124 * "true" MSRs, so we do not support restoring them directly.
3126 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3127 * should restore the "true" MSRs with the must-be-1 bits
3128 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3129 * DEFAULT SETTINGS".
3132 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3133 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3134 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3135 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3136 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3137 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3138 case MSR_IA32_VMX_MISC
:
3139 return vmx_restore_vmx_misc(vmx
, data
);
3140 case MSR_IA32_VMX_CR0_FIXED0
:
3141 case MSR_IA32_VMX_CR4_FIXED0
:
3142 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3143 case MSR_IA32_VMX_CR0_FIXED1
:
3144 case MSR_IA32_VMX_CR4_FIXED1
:
3146 * These MSRs are generated based on the vCPU's CPUID, so we
3147 * do not support restoring them directly.
3150 case MSR_IA32_VMX_EPT_VPID_CAP
:
3151 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3152 case MSR_IA32_VMX_VMCS_ENUM
:
3153 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3157 * The rest of the VMX capability MSRs do not support restore.
3163 /* Returns 0 on success, non-0 otherwise. */
3164 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3166 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3168 switch (msr_index
) {
3169 case MSR_IA32_VMX_BASIC
:
3170 *pdata
= vmx
->nested
.nested_vmx_basic
;
3172 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3173 case MSR_IA32_VMX_PINBASED_CTLS
:
3174 *pdata
= vmx_control_msr(
3175 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3176 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3177 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3178 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3180 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3181 case MSR_IA32_VMX_PROCBASED_CTLS
:
3182 *pdata
= vmx_control_msr(
3183 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3184 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3185 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3186 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3188 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3189 case MSR_IA32_VMX_EXIT_CTLS
:
3190 *pdata
= vmx_control_msr(
3191 vmx
->nested
.nested_vmx_exit_ctls_low
,
3192 vmx
->nested
.nested_vmx_exit_ctls_high
);
3193 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3194 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3196 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3197 case MSR_IA32_VMX_ENTRY_CTLS
:
3198 *pdata
= vmx_control_msr(
3199 vmx
->nested
.nested_vmx_entry_ctls_low
,
3200 vmx
->nested
.nested_vmx_entry_ctls_high
);
3201 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3202 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3204 case MSR_IA32_VMX_MISC
:
3205 *pdata
= vmx_control_msr(
3206 vmx
->nested
.nested_vmx_misc_low
,
3207 vmx
->nested
.nested_vmx_misc_high
);
3209 case MSR_IA32_VMX_CR0_FIXED0
:
3210 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3212 case MSR_IA32_VMX_CR0_FIXED1
:
3213 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3215 case MSR_IA32_VMX_CR4_FIXED0
:
3216 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3218 case MSR_IA32_VMX_CR4_FIXED1
:
3219 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3221 case MSR_IA32_VMX_VMCS_ENUM
:
3222 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3224 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3225 *pdata
= vmx_control_msr(
3226 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3227 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3229 case MSR_IA32_VMX_EPT_VPID_CAP
:
3230 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3231 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3233 case MSR_IA32_VMX_VMFUNC
:
3234 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3243 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3246 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3248 return !(val
& ~valid_bits
);
3252 * Reads an msr value (of 'msr_index') into 'pdata'.
3253 * Returns 0 on success, non-0 otherwise.
3254 * Assumes vcpu_load() was already called.
3256 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3258 struct shared_msr_entry
*msr
;
3260 switch (msr_info
->index
) {
3261 #ifdef CONFIG_X86_64
3263 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3266 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3268 case MSR_KERNEL_GS_BASE
:
3269 vmx_load_host_state(to_vmx(vcpu
));
3270 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3274 return kvm_get_msr_common(vcpu
, msr_info
);
3276 msr_info
->data
= guest_read_tsc(vcpu
);
3278 case MSR_IA32_SYSENTER_CS
:
3279 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3281 case MSR_IA32_SYSENTER_EIP
:
3282 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3284 case MSR_IA32_SYSENTER_ESP
:
3285 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3287 case MSR_IA32_BNDCFGS
:
3288 if (!kvm_mpx_supported() ||
3289 (!msr_info
->host_initiated
&&
3290 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3292 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3294 case MSR_IA32_MCG_EXT_CTL
:
3295 if (!msr_info
->host_initiated
&&
3296 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3297 FEATURE_CONTROL_LMCE
))
3299 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3301 case MSR_IA32_FEATURE_CONTROL
:
3302 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3304 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3305 if (!nested_vmx_allowed(vcpu
))
3307 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3309 if (!vmx_xsaves_supported())
3311 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3314 if (!msr_info
->host_initiated
&&
3315 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3317 /* Otherwise falls through */
3319 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3321 msr_info
->data
= msr
->data
;
3324 return kvm_get_msr_common(vcpu
, msr_info
);
3330 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3333 * Writes msr value into into the appropriate "register".
3334 * Returns 0 on success, non-0 otherwise.
3335 * Assumes vcpu_load() was already called.
3337 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3339 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3340 struct shared_msr_entry
*msr
;
3342 u32 msr_index
= msr_info
->index
;
3343 u64 data
= msr_info
->data
;
3345 switch (msr_index
) {
3347 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3349 #ifdef CONFIG_X86_64
3351 vmx_segment_cache_clear(vmx
);
3352 vmcs_writel(GUEST_FS_BASE
, data
);
3355 vmx_segment_cache_clear(vmx
);
3356 vmcs_writel(GUEST_GS_BASE
, data
);
3358 case MSR_KERNEL_GS_BASE
:
3359 vmx_load_host_state(vmx
);
3360 vmx
->msr_guest_kernel_gs_base
= data
;
3363 case MSR_IA32_SYSENTER_CS
:
3364 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3366 case MSR_IA32_SYSENTER_EIP
:
3367 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3369 case MSR_IA32_SYSENTER_ESP
:
3370 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3372 case MSR_IA32_BNDCFGS
:
3373 if (!kvm_mpx_supported() ||
3374 (!msr_info
->host_initiated
&&
3375 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3377 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3378 (data
& MSR_IA32_BNDCFGS_RSVD
))
3380 vmcs_write64(GUEST_BNDCFGS
, data
);
3383 kvm_write_tsc(vcpu
, msr_info
);
3385 case MSR_IA32_CR_PAT
:
3386 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3387 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3389 vmcs_write64(GUEST_IA32_PAT
, data
);
3390 vcpu
->arch
.pat
= data
;
3393 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3395 case MSR_IA32_TSC_ADJUST
:
3396 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3398 case MSR_IA32_MCG_EXT_CTL
:
3399 if ((!msr_info
->host_initiated
&&
3400 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3401 FEATURE_CONTROL_LMCE
)) ||
3402 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3404 vcpu
->arch
.mcg_ext_ctl
= data
;
3406 case MSR_IA32_FEATURE_CONTROL
:
3407 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3408 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3409 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3411 vmx
->msr_ia32_feature_control
= data
;
3412 if (msr_info
->host_initiated
&& data
== 0)
3413 vmx_leave_nested(vcpu
);
3415 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3416 if (!msr_info
->host_initiated
)
3417 return 1; /* they are read-only */
3418 if (!nested_vmx_allowed(vcpu
))
3420 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3422 if (!vmx_xsaves_supported())
3425 * The only supported bit as of Skylake is bit 8, but
3426 * it is not supported on KVM.
3430 vcpu
->arch
.ia32_xss
= data
;
3431 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3432 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3433 vcpu
->arch
.ia32_xss
, host_xss
);
3435 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3438 if (!msr_info
->host_initiated
&&
3439 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3441 /* Check reserved bit, higher 32 bits should be zero */
3442 if ((data
>> 32) != 0)
3444 /* Otherwise falls through */
3446 msr
= find_msr_entry(vmx
, msr_index
);
3448 u64 old_msr_data
= msr
->data
;
3450 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3452 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3456 msr
->data
= old_msr_data
;
3460 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3466 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3468 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3471 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3474 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3476 case VCPU_EXREG_PDPTR
:
3478 ept_save_pdptrs(vcpu
);
3485 static __init
int cpu_has_kvm_support(void)
3487 return cpu_has_vmx();
3490 static __init
int vmx_disabled_by_bios(void)
3494 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3495 if (msr
& FEATURE_CONTROL_LOCKED
) {
3496 /* launched w/ TXT and VMX disabled */
3497 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3500 /* launched w/o TXT and VMX only enabled w/ TXT */
3501 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3502 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3503 && !tboot_enabled()) {
3504 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3505 "activate TXT before enabling KVM\n");
3508 /* launched w/o TXT and VMX disabled */
3509 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3510 && !tboot_enabled())
3517 static void kvm_cpu_vmxon(u64 addr
)
3519 cr4_set_bits(X86_CR4_VMXE
);
3520 intel_pt_handle_vmx(1);
3522 asm volatile (ASM_VMX_VMXON_RAX
3523 : : "a"(&addr
), "m"(addr
)
3527 static int hardware_enable(void)
3529 int cpu
= raw_smp_processor_id();
3530 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3533 if (cr4_read_shadow() & X86_CR4_VMXE
)
3536 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3537 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3538 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3541 * Now we can enable the vmclear operation in kdump
3542 * since the loaded_vmcss_on_cpu list on this cpu
3543 * has been initialized.
3545 * Though the cpu is not in VMX operation now, there
3546 * is no problem to enable the vmclear operation
3547 * for the loaded_vmcss_on_cpu list is empty!
3549 crash_enable_local_vmclear(cpu
);
3551 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3553 test_bits
= FEATURE_CONTROL_LOCKED
;
3554 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3555 if (tboot_enabled())
3556 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3558 if ((old
& test_bits
) != test_bits
) {
3559 /* enable and lock */
3560 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3562 kvm_cpu_vmxon(phys_addr
);
3568 static void vmclear_local_loaded_vmcss(void)
3570 int cpu
= raw_smp_processor_id();
3571 struct loaded_vmcs
*v
, *n
;
3573 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3574 loaded_vmcss_on_cpu_link
)
3575 __loaded_vmcs_clear(v
);
3579 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3582 static void kvm_cpu_vmxoff(void)
3584 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3586 intel_pt_handle_vmx(0);
3587 cr4_clear_bits(X86_CR4_VMXE
);
3590 static void hardware_disable(void)
3592 vmclear_local_loaded_vmcss();
3596 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3597 u32 msr
, u32
*result
)
3599 u32 vmx_msr_low
, vmx_msr_high
;
3600 u32 ctl
= ctl_min
| ctl_opt
;
3602 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3604 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3605 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3607 /* Ensure minimum (required) set of control bits are supported. */
3615 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3617 u32 vmx_msr_low
, vmx_msr_high
;
3619 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3620 return vmx_msr_high
& ctl
;
3623 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3625 u32 vmx_msr_low
, vmx_msr_high
;
3626 u32 min
, opt
, min2
, opt2
;
3627 u32 _pin_based_exec_control
= 0;
3628 u32 _cpu_based_exec_control
= 0;
3629 u32 _cpu_based_2nd_exec_control
= 0;
3630 u32 _vmexit_control
= 0;
3631 u32 _vmentry_control
= 0;
3633 min
= CPU_BASED_HLT_EXITING
|
3634 #ifdef CONFIG_X86_64
3635 CPU_BASED_CR8_LOAD_EXITING
|
3636 CPU_BASED_CR8_STORE_EXITING
|
3638 CPU_BASED_CR3_LOAD_EXITING
|
3639 CPU_BASED_CR3_STORE_EXITING
|
3640 CPU_BASED_USE_IO_BITMAPS
|
3641 CPU_BASED_MOV_DR_EXITING
|
3642 CPU_BASED_USE_TSC_OFFSETING
|
3643 CPU_BASED_INVLPG_EXITING
|
3644 CPU_BASED_RDPMC_EXITING
;
3646 if (!kvm_mwait_in_guest())
3647 min
|= CPU_BASED_MWAIT_EXITING
|
3648 CPU_BASED_MONITOR_EXITING
;
3650 opt
= CPU_BASED_TPR_SHADOW
|
3651 CPU_BASED_USE_MSR_BITMAPS
|
3652 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3653 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3654 &_cpu_based_exec_control
) < 0)
3656 #ifdef CONFIG_X86_64
3657 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3658 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3659 ~CPU_BASED_CR8_STORE_EXITING
;
3661 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3663 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3664 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3665 SECONDARY_EXEC_WBINVD_EXITING
|
3666 SECONDARY_EXEC_ENABLE_VPID
|
3667 SECONDARY_EXEC_ENABLE_EPT
|
3668 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3669 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3670 SECONDARY_EXEC_RDTSCP
|
3671 SECONDARY_EXEC_ENABLE_INVPCID
|
3672 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3673 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3674 SECONDARY_EXEC_SHADOW_VMCS
|
3675 SECONDARY_EXEC_XSAVES
|
3676 SECONDARY_EXEC_RDSEED
|
3677 SECONDARY_EXEC_RDRAND
|
3678 SECONDARY_EXEC_ENABLE_PML
|
3679 SECONDARY_EXEC_TSC_SCALING
|
3680 SECONDARY_EXEC_ENABLE_VMFUNC
;
3681 if (adjust_vmx_controls(min2
, opt2
,
3682 MSR_IA32_VMX_PROCBASED_CTLS2
,
3683 &_cpu_based_2nd_exec_control
) < 0)
3686 #ifndef CONFIG_X86_64
3687 if (!(_cpu_based_2nd_exec_control
&
3688 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3689 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3692 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3693 _cpu_based_2nd_exec_control
&= ~(
3694 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3695 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3696 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3698 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3699 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3701 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3702 CPU_BASED_CR3_STORE_EXITING
|
3703 CPU_BASED_INVLPG_EXITING
);
3704 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3705 vmx_capability
.ept
, vmx_capability
.vpid
);
3708 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3709 #ifdef CONFIG_X86_64
3710 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3712 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3713 VM_EXIT_CLEAR_BNDCFGS
;
3714 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3715 &_vmexit_control
) < 0)
3718 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3719 PIN_BASED_VIRTUAL_NMIS
;
3720 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3721 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3722 &_pin_based_exec_control
) < 0)
3725 if (cpu_has_broken_vmx_preemption_timer())
3726 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3727 if (!(_cpu_based_2nd_exec_control
&
3728 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3729 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3731 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3732 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3733 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3734 &_vmentry_control
) < 0)
3737 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3739 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3740 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3743 #ifdef CONFIG_X86_64
3744 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3745 if (vmx_msr_high
& (1u<<16))
3749 /* Require Write-Back (WB) memory type for VMCS accesses. */
3750 if (((vmx_msr_high
>> 18) & 15) != 6)
3753 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3754 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3755 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3756 vmcs_conf
->revision_id
= vmx_msr_low
;
3758 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3759 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3760 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3761 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3762 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3764 cpu_has_load_ia32_efer
=
3765 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3766 VM_ENTRY_LOAD_IA32_EFER
)
3767 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3768 VM_EXIT_LOAD_IA32_EFER
);
3770 cpu_has_load_perf_global_ctrl
=
3771 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3772 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3773 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3774 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3777 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3778 * but due to errata below it can't be used. Workaround is to use
3779 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3781 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3786 * BC86,AAY89,BD102 (model 44)
3790 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3791 switch (boot_cpu_data
.x86_model
) {
3797 cpu_has_load_perf_global_ctrl
= false;
3798 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3799 "does not work properly. Using workaround\n");
3806 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3807 rdmsrl(MSR_IA32_XSS
, host_xss
);
3812 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3814 int node
= cpu_to_node(cpu
);
3818 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3821 vmcs
= page_address(pages
);
3822 memset(vmcs
, 0, vmcs_config
.size
);
3823 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3827 static struct vmcs
*alloc_vmcs(void)
3829 return alloc_vmcs_cpu(raw_smp_processor_id());
3832 static void free_vmcs(struct vmcs
*vmcs
)
3834 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3838 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3840 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3842 if (!loaded_vmcs
->vmcs
)
3844 loaded_vmcs_clear(loaded_vmcs
);
3845 free_vmcs(loaded_vmcs
->vmcs
);
3846 loaded_vmcs
->vmcs
= NULL
;
3847 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3850 static void free_kvm_area(void)
3854 for_each_possible_cpu(cpu
) {
3855 free_vmcs(per_cpu(vmxarea
, cpu
));
3856 per_cpu(vmxarea
, cpu
) = NULL
;
3860 enum vmcs_field_type
{
3861 VMCS_FIELD_TYPE_U16
= 0,
3862 VMCS_FIELD_TYPE_U64
= 1,
3863 VMCS_FIELD_TYPE_U32
= 2,
3864 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3867 static inline int vmcs_field_type(unsigned long field
)
3869 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3870 return VMCS_FIELD_TYPE_U32
;
3871 return (field
>> 13) & 0x3 ;
3874 static inline int vmcs_field_readonly(unsigned long field
)
3876 return (((field
>> 10) & 0x3) == 1);
3879 static void init_vmcs_shadow_fields(void)
3883 /* No checks for read only fields yet */
3885 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3886 switch (shadow_read_write_fields
[i
]) {
3888 if (!kvm_mpx_supported())
3896 shadow_read_write_fields
[j
] =
3897 shadow_read_write_fields
[i
];
3900 max_shadow_read_write_fields
= j
;
3902 /* shadowed fields guest access without vmexit */
3903 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3904 unsigned long field
= shadow_read_write_fields
[i
];
3906 clear_bit(field
, vmx_vmwrite_bitmap
);
3907 clear_bit(field
, vmx_vmread_bitmap
);
3908 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3909 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3910 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3913 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3914 unsigned long field
= shadow_read_only_fields
[i
];
3916 clear_bit(field
, vmx_vmread_bitmap
);
3917 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3918 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3922 static __init
int alloc_kvm_area(void)
3926 for_each_possible_cpu(cpu
) {
3929 vmcs
= alloc_vmcs_cpu(cpu
);
3935 per_cpu(vmxarea
, cpu
) = vmcs
;
3940 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3941 struct kvm_segment
*save
)
3943 if (!emulate_invalid_guest_state
) {
3945 * CS and SS RPL should be equal during guest entry according
3946 * to VMX spec, but in reality it is not always so. Since vcpu
3947 * is in the middle of the transition from real mode to
3948 * protected mode it is safe to assume that RPL 0 is a good
3951 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3952 save
->selector
&= ~SEGMENT_RPL_MASK
;
3953 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3956 vmx_set_segment(vcpu
, save
, seg
);
3959 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3961 unsigned long flags
;
3962 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3965 * Update real mode segment cache. It may be not up-to-date if sement
3966 * register was written while vcpu was in a guest mode.
3968 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3969 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3970 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3971 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3972 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3973 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3975 vmx
->rmode
.vm86_active
= 0;
3977 vmx_segment_cache_clear(vmx
);
3979 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3981 flags
= vmcs_readl(GUEST_RFLAGS
);
3982 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3983 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3984 vmcs_writel(GUEST_RFLAGS
, flags
);
3986 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3987 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3989 update_exception_bitmap(vcpu
);
3991 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3992 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3993 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3994 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3995 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3996 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3999 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4001 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4002 struct kvm_segment var
= *save
;
4005 if (seg
== VCPU_SREG_CS
)
4008 if (!emulate_invalid_guest_state
) {
4009 var
.selector
= var
.base
>> 4;
4010 var
.base
= var
.base
& 0xffff0;
4020 if (save
->base
& 0xf)
4021 printk_once(KERN_WARNING
"kvm: segment base is not "
4022 "paragraph aligned when entering "
4023 "protected mode (seg=%d)", seg
);
4026 vmcs_write16(sf
->selector
, var
.selector
);
4027 vmcs_writel(sf
->base
, var
.base
);
4028 vmcs_write32(sf
->limit
, var
.limit
);
4029 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4032 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4034 unsigned long flags
;
4035 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4037 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4038 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4039 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4040 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4041 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4042 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4043 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4045 vmx
->rmode
.vm86_active
= 1;
4048 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4049 * vcpu. Warn the user that an update is overdue.
4051 if (!vcpu
->kvm
->arch
.tss_addr
)
4052 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4053 "called before entering vcpu\n");
4055 vmx_segment_cache_clear(vmx
);
4057 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4058 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4059 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4061 flags
= vmcs_readl(GUEST_RFLAGS
);
4062 vmx
->rmode
.save_rflags
= flags
;
4064 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4066 vmcs_writel(GUEST_RFLAGS
, flags
);
4067 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4068 update_exception_bitmap(vcpu
);
4070 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4071 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4072 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4073 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4074 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4075 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4077 kvm_mmu_reset_context(vcpu
);
4080 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4082 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4083 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4089 * Force kernel_gs_base reloading before EFER changes, as control
4090 * of this msr depends on is_long_mode().
4092 vmx_load_host_state(to_vmx(vcpu
));
4093 vcpu
->arch
.efer
= efer
;
4094 if (efer
& EFER_LMA
) {
4095 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4098 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4100 msr
->data
= efer
& ~EFER_LME
;
4105 #ifdef CONFIG_X86_64
4107 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4111 vmx_segment_cache_clear(to_vmx(vcpu
));
4113 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4114 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4115 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4117 vmcs_write32(GUEST_TR_AR_BYTES
,
4118 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4119 | VMX_AR_TYPE_BUSY_64_TSS
);
4121 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4124 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4126 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4127 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4132 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4135 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4137 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4139 vpid_sync_context(vpid
);
4143 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4145 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4148 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4151 vmx_flush_tlb(vcpu
);
4154 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4156 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4158 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4159 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4162 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4164 if (enable_ept
&& is_paging(vcpu
))
4165 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4166 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4169 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4171 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4173 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4174 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4177 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4179 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4181 if (!test_bit(VCPU_EXREG_PDPTR
,
4182 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4185 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4186 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4187 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4188 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4189 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4193 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4195 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4197 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4198 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4199 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4200 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4201 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4204 __set_bit(VCPU_EXREG_PDPTR
,
4205 (unsigned long *)&vcpu
->arch
.regs_avail
);
4206 __set_bit(VCPU_EXREG_PDPTR
,
4207 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4210 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4212 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4213 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4214 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4216 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4217 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4218 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4219 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4221 return fixed_bits_valid(val
, fixed0
, fixed1
);
4224 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4226 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4227 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4229 return fixed_bits_valid(val
, fixed0
, fixed1
);
4232 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4234 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4235 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4237 return fixed_bits_valid(val
, fixed0
, fixed1
);
4240 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4241 #define nested_guest_cr4_valid nested_cr4_valid
4242 #define nested_host_cr4_valid nested_cr4_valid
4244 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4246 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4248 struct kvm_vcpu
*vcpu
)
4250 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4251 vmx_decache_cr3(vcpu
);
4252 if (!(cr0
& X86_CR0_PG
)) {
4253 /* From paging/starting to nonpaging */
4254 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4255 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4256 (CPU_BASED_CR3_LOAD_EXITING
|
4257 CPU_BASED_CR3_STORE_EXITING
));
4258 vcpu
->arch
.cr0
= cr0
;
4259 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4260 } else if (!is_paging(vcpu
)) {
4261 /* From nonpaging to paging */
4262 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4263 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4264 ~(CPU_BASED_CR3_LOAD_EXITING
|
4265 CPU_BASED_CR3_STORE_EXITING
));
4266 vcpu
->arch
.cr0
= cr0
;
4267 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4270 if (!(cr0
& X86_CR0_WP
))
4271 *hw_cr0
&= ~X86_CR0_WP
;
4274 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4276 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4277 unsigned long hw_cr0
;
4279 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4280 if (enable_unrestricted_guest
)
4281 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4283 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4285 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4288 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4292 #ifdef CONFIG_X86_64
4293 if (vcpu
->arch
.efer
& EFER_LME
) {
4294 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4296 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4302 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4304 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4305 vmcs_writel(GUEST_CR0
, hw_cr0
);
4306 vcpu
->arch
.cr0
= cr0
;
4308 /* depends on vcpu->arch.cr0 to be set to a new value */
4309 vmx
->emulation_required
= emulation_required(vcpu
);
4312 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4314 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4319 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4321 u64 eptp
= VMX_EPTP_MT_WB
;
4323 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4325 if (enable_ept_ad_bits
&&
4326 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4327 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4328 eptp
|= (root_hpa
& PAGE_MASK
);
4333 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4335 unsigned long guest_cr3
;
4340 eptp
= construct_eptp(vcpu
, cr3
);
4341 vmcs_write64(EPT_POINTER
, eptp
);
4342 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4343 guest_cr3
= kvm_read_cr3(vcpu
);
4345 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4346 ept_load_pdptrs(vcpu
);
4349 vmx_flush_tlb(vcpu
);
4350 vmcs_writel(GUEST_CR3
, guest_cr3
);
4353 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4356 * Pass through host's Machine Check Enable value to hw_cr4, which
4357 * is in force while we are in guest mode. Do not let guests control
4358 * this bit, even if host CR4.MCE == 0.
4360 unsigned long hw_cr4
=
4361 (cr4_read_shadow() & X86_CR4_MCE
) |
4362 (cr4
& ~X86_CR4_MCE
) |
4363 (to_vmx(vcpu
)->rmode
.vm86_active
?
4364 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4366 if (cr4
& X86_CR4_VMXE
) {
4368 * To use VMXON (and later other VMX instructions), a guest
4369 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4370 * So basically the check on whether to allow nested VMX
4373 if (!nested_vmx_allowed(vcpu
))
4377 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4380 vcpu
->arch
.cr4
= cr4
;
4382 if (!is_paging(vcpu
)) {
4383 hw_cr4
&= ~X86_CR4_PAE
;
4384 hw_cr4
|= X86_CR4_PSE
;
4385 } else if (!(cr4
& X86_CR4_PAE
)) {
4386 hw_cr4
&= ~X86_CR4_PAE
;
4390 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4392 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4393 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4394 * to be manually disabled when guest switches to non-paging
4397 * If !enable_unrestricted_guest, the CPU is always running
4398 * with CR0.PG=1 and CR4 needs to be modified.
4399 * If enable_unrestricted_guest, the CPU automatically
4400 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4402 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4404 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4405 vmcs_writel(GUEST_CR4
, hw_cr4
);
4409 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4410 struct kvm_segment
*var
, int seg
)
4412 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4415 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4416 *var
= vmx
->rmode
.segs
[seg
];
4417 if (seg
== VCPU_SREG_TR
4418 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4420 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4421 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4424 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4425 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4426 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4427 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4428 var
->unusable
= (ar
>> 16) & 1;
4429 var
->type
= ar
& 15;
4430 var
->s
= (ar
>> 4) & 1;
4431 var
->dpl
= (ar
>> 5) & 3;
4433 * Some userspaces do not preserve unusable property. Since usable
4434 * segment has to be present according to VMX spec we can use present
4435 * property to amend userspace bug by making unusable segment always
4436 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4437 * segment as unusable.
4439 var
->present
= !var
->unusable
;
4440 var
->avl
= (ar
>> 12) & 1;
4441 var
->l
= (ar
>> 13) & 1;
4442 var
->db
= (ar
>> 14) & 1;
4443 var
->g
= (ar
>> 15) & 1;
4446 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4448 struct kvm_segment s
;
4450 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4451 vmx_get_segment(vcpu
, &s
, seg
);
4454 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4457 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4459 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4461 if (unlikely(vmx
->rmode
.vm86_active
))
4464 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4465 return VMX_AR_DPL(ar
);
4469 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4473 if (var
->unusable
|| !var
->present
)
4476 ar
= var
->type
& 15;
4477 ar
|= (var
->s
& 1) << 4;
4478 ar
|= (var
->dpl
& 3) << 5;
4479 ar
|= (var
->present
& 1) << 7;
4480 ar
|= (var
->avl
& 1) << 12;
4481 ar
|= (var
->l
& 1) << 13;
4482 ar
|= (var
->db
& 1) << 14;
4483 ar
|= (var
->g
& 1) << 15;
4489 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4490 struct kvm_segment
*var
, int seg
)
4492 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4493 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4495 vmx_segment_cache_clear(vmx
);
4497 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4498 vmx
->rmode
.segs
[seg
] = *var
;
4499 if (seg
== VCPU_SREG_TR
)
4500 vmcs_write16(sf
->selector
, var
->selector
);
4502 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4506 vmcs_writel(sf
->base
, var
->base
);
4507 vmcs_write32(sf
->limit
, var
->limit
);
4508 vmcs_write16(sf
->selector
, var
->selector
);
4511 * Fix the "Accessed" bit in AR field of segment registers for older
4513 * IA32 arch specifies that at the time of processor reset the
4514 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4515 * is setting it to 0 in the userland code. This causes invalid guest
4516 * state vmexit when "unrestricted guest" mode is turned on.
4517 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4518 * tree. Newer qemu binaries with that qemu fix would not need this
4521 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4522 var
->type
|= 0x1; /* Accessed */
4524 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4527 vmx
->emulation_required
= emulation_required(vcpu
);
4530 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4532 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4534 *db
= (ar
>> 14) & 1;
4535 *l
= (ar
>> 13) & 1;
4538 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4540 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4541 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4544 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4546 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4547 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4550 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4552 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4553 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4556 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4558 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4559 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4562 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4564 struct kvm_segment var
;
4567 vmx_get_segment(vcpu
, &var
, seg
);
4569 if (seg
== VCPU_SREG_CS
)
4571 ar
= vmx_segment_access_rights(&var
);
4573 if (var
.base
!= (var
.selector
<< 4))
4575 if (var
.limit
!= 0xffff)
4583 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4585 struct kvm_segment cs
;
4586 unsigned int cs_rpl
;
4588 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4589 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4593 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4597 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4598 if (cs
.dpl
> cs_rpl
)
4601 if (cs
.dpl
!= cs_rpl
)
4607 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4611 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4613 struct kvm_segment ss
;
4614 unsigned int ss_rpl
;
4616 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4617 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4621 if (ss
.type
!= 3 && ss
.type
!= 7)
4625 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4633 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4635 struct kvm_segment var
;
4638 vmx_get_segment(vcpu
, &var
, seg
);
4639 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4647 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4648 if (var
.dpl
< rpl
) /* DPL < RPL */
4652 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4658 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4660 struct kvm_segment tr
;
4662 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4666 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4668 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4676 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4678 struct kvm_segment ldtr
;
4680 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4684 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4694 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4696 struct kvm_segment cs
, ss
;
4698 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4699 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4701 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4702 (ss
.selector
& SEGMENT_RPL_MASK
));
4706 * Check if guest state is valid. Returns true if valid, false if
4708 * We assume that registers are always usable
4710 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4712 if (enable_unrestricted_guest
)
4715 /* real mode guest state checks */
4716 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4717 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4719 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4721 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4723 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4725 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4727 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4730 /* protected mode guest state checks */
4731 if (!cs_ss_rpl_check(vcpu
))
4733 if (!code_segment_valid(vcpu
))
4735 if (!stack_segment_valid(vcpu
))
4737 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4739 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4741 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4743 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4745 if (!tr_valid(vcpu
))
4747 if (!ldtr_valid(vcpu
))
4751 * - Add checks on RIP
4752 * - Add checks on RFLAGS
4758 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4760 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4763 static int init_rmode_tss(struct kvm
*kvm
)
4769 idx
= srcu_read_lock(&kvm
->srcu
);
4770 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4771 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4774 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4775 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4776 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4779 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4782 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4786 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4787 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4790 srcu_read_unlock(&kvm
->srcu
, idx
);
4794 static int init_rmode_identity_map(struct kvm
*kvm
)
4797 kvm_pfn_t identity_map_pfn
;
4803 /* Protect kvm->arch.ept_identity_pagetable_done. */
4804 mutex_lock(&kvm
->slots_lock
);
4806 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4809 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4811 r
= alloc_identity_pagetable(kvm
);
4815 idx
= srcu_read_lock(&kvm
->srcu
);
4816 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4819 /* Set up identity-mapping pagetable for EPT in real mode */
4820 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4821 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4822 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4823 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4824 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4828 kvm
->arch
.ept_identity_pagetable_done
= true;
4831 srcu_read_unlock(&kvm
->srcu
, idx
);
4834 mutex_unlock(&kvm
->slots_lock
);
4838 static void seg_setup(int seg
)
4840 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4843 vmcs_write16(sf
->selector
, 0);
4844 vmcs_writel(sf
->base
, 0);
4845 vmcs_write32(sf
->limit
, 0xffff);
4847 if (seg
== VCPU_SREG_CS
)
4848 ar
|= 0x08; /* code segment */
4850 vmcs_write32(sf
->ar_bytes
, ar
);
4853 static int alloc_apic_access_page(struct kvm
*kvm
)
4858 mutex_lock(&kvm
->slots_lock
);
4859 if (kvm
->arch
.apic_access_page_done
)
4861 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4862 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4866 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4867 if (is_error_page(page
)) {
4873 * Do not pin the page in memory, so that memory hot-unplug
4874 * is able to migrate it.
4877 kvm
->arch
.apic_access_page_done
= true;
4879 mutex_unlock(&kvm
->slots_lock
);
4883 static int alloc_identity_pagetable(struct kvm
*kvm
)
4885 /* Called with kvm->slots_lock held. */
4889 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4891 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4892 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4897 static int allocate_vpid(void)
4903 spin_lock(&vmx_vpid_lock
);
4904 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4905 if (vpid
< VMX_NR_VPIDS
)
4906 __set_bit(vpid
, vmx_vpid_bitmap
);
4909 spin_unlock(&vmx_vpid_lock
);
4913 static void free_vpid(int vpid
)
4915 if (!enable_vpid
|| vpid
== 0)
4917 spin_lock(&vmx_vpid_lock
);
4918 __clear_bit(vpid
, vmx_vpid_bitmap
);
4919 spin_unlock(&vmx_vpid_lock
);
4922 #define MSR_TYPE_R 1
4923 #define MSR_TYPE_W 2
4924 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4927 int f
= sizeof(unsigned long);
4929 if (!cpu_has_vmx_msr_bitmap())
4933 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4934 * have the write-low and read-high bitmap offsets the wrong way round.
4935 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4937 if (msr
<= 0x1fff) {
4938 if (type
& MSR_TYPE_R
)
4940 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4942 if (type
& MSR_TYPE_W
)
4944 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4946 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4948 if (type
& MSR_TYPE_R
)
4950 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4952 if (type
& MSR_TYPE_W
)
4954 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4960 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4961 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4963 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4964 unsigned long *msr_bitmap_nested
,
4967 int f
= sizeof(unsigned long);
4969 if (!cpu_has_vmx_msr_bitmap()) {
4975 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4976 * have the write-low and read-high bitmap offsets the wrong way round.
4977 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4979 if (msr
<= 0x1fff) {
4980 if (type
& MSR_TYPE_R
&&
4981 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4983 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4985 if (type
& MSR_TYPE_W
&&
4986 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4988 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4990 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4992 if (type
& MSR_TYPE_R
&&
4993 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4995 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4997 if (type
& MSR_TYPE_W
&&
4998 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
5000 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
5005 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
5008 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
5009 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5010 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
5011 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5014 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5017 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5019 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5022 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5024 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5029 static bool vmx_get_enable_apicv(void)
5031 return enable_apicv
;
5034 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5036 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5040 * Don't need to mark the APIC access page dirty; it is never
5041 * written to by the CPU during APIC virtualization.
5044 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5045 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5046 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5049 if (nested_cpu_has_posted_intr(vmcs12
)) {
5050 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5051 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5056 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5063 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5066 vmx
->nested
.pi_pending
= false;
5067 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5070 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5071 if (max_irr
!= 256) {
5072 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5073 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5074 kunmap(vmx
->nested
.virtual_apic_page
);
5076 status
= vmcs_read16(GUEST_INTR_STATUS
);
5077 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5079 status
|= (u8
)max_irr
;
5080 vmcs_write16(GUEST_INTR_STATUS
, status
);
5084 nested_mark_vmcs12_pages_dirty(vcpu
);
5087 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5091 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5093 if (vcpu
->mode
== IN_GUEST_MODE
) {
5094 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5097 * Currently, we don't support urgent interrupt,
5098 * all interrupts are recognized as non-urgent
5099 * interrupt, so we cannot post interrupts when
5102 * If the vcpu is in guest mode, it means it is
5103 * running instead of being scheduled out and
5104 * waiting in the run queue, and that's the only
5105 * case when 'SN' is set currently, warning if
5108 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
5110 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5117 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5120 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5122 if (is_guest_mode(vcpu
) &&
5123 vector
== vmx
->nested
.posted_intr_nv
) {
5124 /* the PIR and ON have been set by L1. */
5125 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5127 * If a posted intr is not recognized by hardware,
5128 * we will accomplish it in the next vmentry.
5130 vmx
->nested
.pi_pending
= true;
5131 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5137 * Send interrupt to vcpu via posted interrupt way.
5138 * 1. If target vcpu is running(non-root mode), send posted interrupt
5139 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5140 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5141 * interrupt from PIR in next vmentry.
5143 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5145 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5148 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5152 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5155 /* If a previous notification has sent the IPI, nothing to do. */
5156 if (pi_test_and_set_on(&vmx
->pi_desc
))
5159 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5160 kvm_vcpu_kick(vcpu
);
5164 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5165 * will not change in the lifetime of the guest.
5166 * Note that host-state that does change is set elsewhere. E.g., host-state
5167 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5169 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5174 unsigned long cr0
, cr3
, cr4
;
5177 WARN_ON(cr0
& X86_CR0_TS
);
5178 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5181 * Save the most likely value for this task's CR3 in the VMCS.
5182 * We can't use __get_current_cr3_fast() because we're not atomic.
5185 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5186 vmx
->host_state
.vmcs_host_cr3
= cr3
;
5188 /* Save the most likely value for this task's CR4 in the VMCS. */
5189 cr4
= cr4_read_shadow();
5190 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5191 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5193 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5194 #ifdef CONFIG_X86_64
5196 * Load null selectors, so we can avoid reloading them in
5197 * __vmx_load_host_state(), in case userspace uses the null selectors
5198 * too (the expected case).
5200 vmcs_write16(HOST_DS_SELECTOR
, 0);
5201 vmcs_write16(HOST_ES_SELECTOR
, 0);
5203 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5204 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5206 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5207 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5209 native_store_idt(&dt
);
5210 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5211 vmx
->host_idt_base
= dt
.address
;
5213 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5215 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5216 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5217 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5218 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5220 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5221 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5222 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5226 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5228 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5230 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5231 if (is_guest_mode(&vmx
->vcpu
))
5232 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5233 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5234 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5237 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5239 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5241 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5242 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5243 /* Enable the preemption timer dynamically */
5244 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5245 return pin_based_exec_ctrl
;
5248 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5250 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5252 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5253 if (cpu_has_secondary_exec_ctrls()) {
5254 if (kvm_vcpu_apicv_active(vcpu
))
5255 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5256 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5257 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5259 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5260 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5261 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5264 if (cpu_has_vmx_msr_bitmap())
5265 vmx_set_msr_bitmap(vcpu
);
5268 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5270 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5272 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5273 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5275 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5276 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5277 #ifdef CONFIG_X86_64
5278 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5279 CPU_BASED_CR8_LOAD_EXITING
;
5283 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5284 CPU_BASED_CR3_LOAD_EXITING
|
5285 CPU_BASED_INVLPG_EXITING
;
5286 return exec_control
;
5289 static bool vmx_rdrand_supported(void)
5291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5292 SECONDARY_EXEC_RDRAND
;
5295 static bool vmx_rdseed_supported(void)
5297 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5298 SECONDARY_EXEC_RDSEED
;
5301 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5303 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5305 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5306 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5307 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5309 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5311 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5312 enable_unrestricted_guest
= 0;
5313 /* Enable INVPCID for non-ept guests may cause performance regression. */
5314 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5316 if (!enable_unrestricted_guest
)
5317 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5319 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5320 if (!kvm_vcpu_apicv_active(vcpu
))
5321 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5322 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5323 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5324 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5326 We can NOT enable shadow_vmcs here because we don't have yet
5329 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5332 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5334 if (vmx_xsaves_supported()) {
5335 /* Exposing XSAVES only when XSAVE is exposed */
5336 bool xsaves_enabled
=
5337 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5338 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5340 if (!xsaves_enabled
)
5341 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5345 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5346 SECONDARY_EXEC_XSAVES
;
5348 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5349 ~SECONDARY_EXEC_XSAVES
;
5353 if (vmx_rdtscp_supported()) {
5354 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5355 if (!rdtscp_enabled
)
5356 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5360 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5361 SECONDARY_EXEC_RDTSCP
;
5363 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5364 ~SECONDARY_EXEC_RDTSCP
;
5368 if (vmx_invpcid_supported()) {
5369 /* Exposing INVPCID only when PCID is exposed */
5370 bool invpcid_enabled
=
5371 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5372 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5374 if (!invpcid_enabled
) {
5375 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5376 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5380 if (invpcid_enabled
)
5381 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5382 SECONDARY_EXEC_ENABLE_INVPCID
;
5384 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5385 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5389 if (vmx_rdrand_supported()) {
5390 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5392 exec_control
&= ~SECONDARY_EXEC_RDRAND
;
5396 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5397 SECONDARY_EXEC_RDRAND
;
5399 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5400 ~SECONDARY_EXEC_RDRAND
;
5404 if (vmx_rdseed_supported()) {
5405 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5407 exec_control
&= ~SECONDARY_EXEC_RDSEED
;
5411 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5412 SECONDARY_EXEC_RDSEED
;
5414 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5415 ~SECONDARY_EXEC_RDSEED
;
5419 vmx
->secondary_exec_control
= exec_control
;
5422 static void ept_set_mmio_spte_mask(void)
5425 * EPT Misconfigurations can be generated if the value of bits 2:0
5426 * of an EPT paging-structure entry is 110b (write/execute).
5428 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5429 VMX_EPT_MISCONFIG_WX_VALUE
);
5432 #define VMX_XSS_EXIT_BITMAP 0
5434 * Sets up the vmcs for emulated real mode.
5436 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5438 #ifdef CONFIG_X86_64
5444 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5445 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5447 if (enable_shadow_vmcs
) {
5448 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5449 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5451 if (cpu_has_vmx_msr_bitmap())
5452 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5454 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5457 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5458 vmx
->hv_deadline_tsc
= -1;
5460 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5462 if (cpu_has_secondary_exec_ctrls()) {
5463 vmx_compute_secondary_exec_control(vmx
);
5464 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5465 vmx
->secondary_exec_control
);
5468 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5469 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5470 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5471 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5472 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5474 vmcs_write16(GUEST_INTR_STATUS
, 0);
5476 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5477 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5481 vmcs_write32(PLE_GAP
, ple_gap
);
5482 vmx
->ple_window
= ple_window
;
5483 vmx
->ple_window_dirty
= true;
5486 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5487 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5488 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5490 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5491 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5492 vmx_set_constant_host_state(vmx
);
5493 #ifdef CONFIG_X86_64
5494 rdmsrl(MSR_FS_BASE
, a
);
5495 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5496 rdmsrl(MSR_GS_BASE
, a
);
5497 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5499 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5500 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5503 if (cpu_has_vmx_vmfunc())
5504 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5506 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5507 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5508 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5509 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5510 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5512 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5513 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5515 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5516 u32 index
= vmx_msr_index
[i
];
5517 u32 data_low
, data_high
;
5520 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5522 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5524 vmx
->guest_msrs
[j
].index
= i
;
5525 vmx
->guest_msrs
[j
].data
= 0;
5526 vmx
->guest_msrs
[j
].mask
= -1ull;
5531 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5533 /* 22.2.1, 20.8.1 */
5534 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5536 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5537 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5539 set_cr4_guest_host_mask(vmx
);
5541 if (vmx_xsaves_supported())
5542 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5545 ASSERT(vmx
->pml_pg
);
5546 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5547 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5553 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5555 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5556 struct msr_data apic_base_msr
;
5559 vmx
->rmode
.vm86_active
= 0;
5561 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5562 kvm_set_cr8(vcpu
, 0);
5565 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5566 MSR_IA32_APICBASE_ENABLE
;
5567 if (kvm_vcpu_is_reset_bsp(vcpu
))
5568 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5569 apic_base_msr
.host_initiated
= true;
5570 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5573 vmx_segment_cache_clear(vmx
);
5575 seg_setup(VCPU_SREG_CS
);
5576 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5577 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5579 seg_setup(VCPU_SREG_DS
);
5580 seg_setup(VCPU_SREG_ES
);
5581 seg_setup(VCPU_SREG_FS
);
5582 seg_setup(VCPU_SREG_GS
);
5583 seg_setup(VCPU_SREG_SS
);
5585 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5586 vmcs_writel(GUEST_TR_BASE
, 0);
5587 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5588 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5590 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5591 vmcs_writel(GUEST_LDTR_BASE
, 0);
5592 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5593 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5596 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5597 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5598 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5599 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5602 vmcs_writel(GUEST_RFLAGS
, 0x02);
5603 kvm_rip_write(vcpu
, 0xfff0);
5605 vmcs_writel(GUEST_GDTR_BASE
, 0);
5606 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5608 vmcs_writel(GUEST_IDTR_BASE
, 0);
5609 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5611 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5612 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5613 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5617 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5619 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5620 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5621 if (cpu_need_tpr_shadow(vcpu
))
5622 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5623 __pa(vcpu
->arch
.apic
->regs
));
5624 vmcs_write32(TPR_THRESHOLD
, 0);
5627 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5629 if (kvm_vcpu_apicv_active(vcpu
))
5630 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5633 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5635 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5636 vmx
->vcpu
.arch
.cr0
= cr0
;
5637 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5638 vmx_set_cr4(vcpu
, 0);
5639 vmx_set_efer(vcpu
, 0);
5641 update_exception_bitmap(vcpu
);
5643 vpid_sync_context(vmx
->vpid
);
5647 * In nested virtualization, check if L1 asked to exit on external interrupts.
5648 * For most existing hypervisors, this will always return true.
5650 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5652 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5653 PIN_BASED_EXT_INTR_MASK
;
5657 * In nested virtualization, check if L1 has set
5658 * VM_EXIT_ACK_INTR_ON_EXIT
5660 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5662 return get_vmcs12(vcpu
)->vm_exit_controls
&
5663 VM_EXIT_ACK_INTR_ON_EXIT
;
5666 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5668 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5669 PIN_BASED_NMI_EXITING
;
5672 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5674 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5675 CPU_BASED_VIRTUAL_INTR_PENDING
);
5678 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5680 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5681 enable_irq_window(vcpu
);
5685 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5686 CPU_BASED_VIRTUAL_NMI_PENDING
);
5689 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5691 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5693 int irq
= vcpu
->arch
.interrupt
.nr
;
5695 trace_kvm_inj_virq(irq
);
5697 ++vcpu
->stat
.irq_injections
;
5698 if (vmx
->rmode
.vm86_active
) {
5700 if (vcpu
->arch
.interrupt
.soft
)
5701 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5702 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5703 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5706 intr
= irq
| INTR_INFO_VALID_MASK
;
5707 if (vcpu
->arch
.interrupt
.soft
) {
5708 intr
|= INTR_TYPE_SOFT_INTR
;
5709 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5710 vmx
->vcpu
.arch
.event_exit_inst_len
);
5712 intr
|= INTR_TYPE_EXT_INTR
;
5713 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5716 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5718 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5720 ++vcpu
->stat
.nmi_injections
;
5721 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5723 if (vmx
->rmode
.vm86_active
) {
5724 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5725 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5729 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5730 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5733 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5735 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5738 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5740 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5741 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5745 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5747 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5749 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5751 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5752 GUEST_INTR_STATE_NMI
);
5754 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5755 GUEST_INTR_STATE_NMI
);
5758 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5760 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5763 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5764 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5765 | GUEST_INTR_STATE_NMI
));
5768 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5770 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5771 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5772 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5773 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5776 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5780 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5784 kvm
->arch
.tss_addr
= addr
;
5785 return init_rmode_tss(kvm
);
5788 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5793 * Update instruction length as we may reinject the exception
5794 * from user space while in guest debugging mode.
5796 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5797 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5798 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5802 if (vcpu
->guest_debug
&
5803 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5820 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5821 int vec
, u32 err_code
)
5824 * Instruction with address size override prefix opcode 0x67
5825 * Cause the #SS fault with 0 error code in VM86 mode.
5827 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5828 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5829 if (vcpu
->arch
.halt_request
) {
5830 vcpu
->arch
.halt_request
= 0;
5831 return kvm_vcpu_halt(vcpu
);
5839 * Forward all other exceptions that are valid in real mode.
5840 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5841 * the required debugging infrastructure rework.
5843 kvm_queue_exception(vcpu
, vec
);
5848 * Trigger machine check on the host. We assume all the MSRs are already set up
5849 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5850 * We pass a fake environment to the machine check handler because we want
5851 * the guest to be always treated like user space, no matter what context
5852 * it used internally.
5854 static void kvm_machine_check(void)
5856 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5857 struct pt_regs regs
= {
5858 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5859 .flags
= X86_EFLAGS_IF
,
5862 do_machine_check(®s
, 0);
5866 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5868 /* already handled by vcpu_run */
5872 static int handle_exception(struct kvm_vcpu
*vcpu
)
5874 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5875 struct kvm_run
*kvm_run
= vcpu
->run
;
5876 u32 intr_info
, ex_no
, error_code
;
5877 unsigned long cr2
, rip
, dr6
;
5879 enum emulation_result er
;
5881 vect_info
= vmx
->idt_vectoring_info
;
5882 intr_info
= vmx
->exit_intr_info
;
5884 if (is_machine_check(intr_info
))
5885 return handle_machine_check(vcpu
);
5887 if (is_nmi(intr_info
))
5888 return 1; /* already handled by vmx_vcpu_run() */
5890 if (is_invalid_opcode(intr_info
)) {
5891 if (is_guest_mode(vcpu
)) {
5892 kvm_queue_exception(vcpu
, UD_VECTOR
);
5895 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5896 if (er
!= EMULATE_DONE
)
5897 kvm_queue_exception(vcpu
, UD_VECTOR
);
5902 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5903 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5906 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5907 * MMIO, it is better to report an internal error.
5908 * See the comments in vmx_handle_exit.
5910 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5911 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5912 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5913 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5914 vcpu
->run
->internal
.ndata
= 3;
5915 vcpu
->run
->internal
.data
[0] = vect_info
;
5916 vcpu
->run
->internal
.data
[1] = intr_info
;
5917 vcpu
->run
->internal
.data
[2] = error_code
;
5921 if (is_page_fault(intr_info
)) {
5922 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5923 /* EPT won't cause page fault directly */
5924 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5925 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5929 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5931 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5932 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5936 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5939 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5940 if (!(vcpu
->guest_debug
&
5941 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5942 vcpu
->arch
.dr6
&= ~15;
5943 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5944 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5945 skip_emulated_instruction(vcpu
);
5947 kvm_queue_exception(vcpu
, DB_VECTOR
);
5950 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5951 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5955 * Update instruction length as we may reinject #BP from
5956 * user space while in guest debugging mode. Reading it for
5957 * #DB as well causes no harm, it is not used in that case.
5959 vmx
->vcpu
.arch
.event_exit_inst_len
=
5960 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5961 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5962 rip
= kvm_rip_read(vcpu
);
5963 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5964 kvm_run
->debug
.arch
.exception
= ex_no
;
5967 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5968 kvm_run
->ex
.exception
= ex_no
;
5969 kvm_run
->ex
.error_code
= error_code
;
5975 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5977 ++vcpu
->stat
.irq_exits
;
5981 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5983 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5984 vcpu
->mmio_needed
= 0;
5988 static int handle_io(struct kvm_vcpu
*vcpu
)
5990 unsigned long exit_qualification
;
5991 int size
, in
, string
, ret
;
5994 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5995 string
= (exit_qualification
& 16) != 0;
5996 in
= (exit_qualification
& 8) != 0;
5998 ++vcpu
->stat
.io_exits
;
6001 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6003 port
= exit_qualification
>> 16;
6004 size
= (exit_qualification
& 7) + 1;
6006 ret
= kvm_skip_emulated_instruction(vcpu
);
6009 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6010 * KVM_EXIT_DEBUG here.
6012 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6016 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6019 * Patch in the VMCALL instruction:
6021 hypercall
[0] = 0x0f;
6022 hypercall
[1] = 0x01;
6023 hypercall
[2] = 0xc1;
6026 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6027 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6029 if (is_guest_mode(vcpu
)) {
6030 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6031 unsigned long orig_val
= val
;
6034 * We get here when L2 changed cr0 in a way that did not change
6035 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6036 * but did change L0 shadowed bits. So we first calculate the
6037 * effective cr0 value that L1 would like to write into the
6038 * hardware. It consists of the L2-owned bits from the new
6039 * value combined with the L1-owned bits from L1's guest_cr0.
6041 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6042 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6044 if (!nested_guest_cr0_valid(vcpu
, val
))
6047 if (kvm_set_cr0(vcpu
, val
))
6049 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6052 if (to_vmx(vcpu
)->nested
.vmxon
&&
6053 !nested_host_cr0_valid(vcpu
, val
))
6056 return kvm_set_cr0(vcpu
, val
);
6060 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6062 if (is_guest_mode(vcpu
)) {
6063 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6064 unsigned long orig_val
= val
;
6066 /* analogously to handle_set_cr0 */
6067 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6068 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6069 if (kvm_set_cr4(vcpu
, val
))
6071 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6074 return kvm_set_cr4(vcpu
, val
);
6077 static int handle_cr(struct kvm_vcpu
*vcpu
)
6079 unsigned long exit_qualification
, val
;
6085 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6086 cr
= exit_qualification
& 15;
6087 reg
= (exit_qualification
>> 8) & 15;
6088 switch ((exit_qualification
>> 4) & 3) {
6089 case 0: /* mov to cr */
6090 val
= kvm_register_readl(vcpu
, reg
);
6091 trace_kvm_cr_write(cr
, val
);
6094 err
= handle_set_cr0(vcpu
, val
);
6095 return kvm_complete_insn_gp(vcpu
, err
);
6097 err
= kvm_set_cr3(vcpu
, val
);
6098 return kvm_complete_insn_gp(vcpu
, err
);
6100 err
= handle_set_cr4(vcpu
, val
);
6101 return kvm_complete_insn_gp(vcpu
, err
);
6103 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6105 err
= kvm_set_cr8(vcpu
, cr8
);
6106 ret
= kvm_complete_insn_gp(vcpu
, err
);
6107 if (lapic_in_kernel(vcpu
))
6109 if (cr8_prev
<= cr8
)
6112 * TODO: we might be squashing a
6113 * KVM_GUESTDBG_SINGLESTEP-triggered
6114 * KVM_EXIT_DEBUG here.
6116 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6122 WARN_ONCE(1, "Guest should always own CR0.TS");
6123 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6124 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6125 return kvm_skip_emulated_instruction(vcpu
);
6126 case 1: /*mov from cr*/
6129 val
= kvm_read_cr3(vcpu
);
6130 kvm_register_write(vcpu
, reg
, val
);
6131 trace_kvm_cr_read(cr
, val
);
6132 return kvm_skip_emulated_instruction(vcpu
);
6134 val
= kvm_get_cr8(vcpu
);
6135 kvm_register_write(vcpu
, reg
, val
);
6136 trace_kvm_cr_read(cr
, val
);
6137 return kvm_skip_emulated_instruction(vcpu
);
6141 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6142 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6143 kvm_lmsw(vcpu
, val
);
6145 return kvm_skip_emulated_instruction(vcpu
);
6149 vcpu
->run
->exit_reason
= 0;
6150 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6151 (int)(exit_qualification
>> 4) & 3, cr
);
6155 static int handle_dr(struct kvm_vcpu
*vcpu
)
6157 unsigned long exit_qualification
;
6160 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6161 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6163 /* First, if DR does not exist, trigger UD */
6164 if (!kvm_require_dr(vcpu
, dr
))
6167 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6168 if (!kvm_require_cpl(vcpu
, 0))
6170 dr7
= vmcs_readl(GUEST_DR7
);
6173 * As the vm-exit takes precedence over the debug trap, we
6174 * need to emulate the latter, either for the host or the
6175 * guest debugging itself.
6177 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6178 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6179 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6180 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6181 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6182 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6185 vcpu
->arch
.dr6
&= ~15;
6186 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6187 kvm_queue_exception(vcpu
, DB_VECTOR
);
6192 if (vcpu
->guest_debug
== 0) {
6193 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6194 CPU_BASED_MOV_DR_EXITING
);
6197 * No more DR vmexits; force a reload of the debug registers
6198 * and reenter on this instruction. The next vmexit will
6199 * retrieve the full state of the debug registers.
6201 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6205 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6206 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6209 if (kvm_get_dr(vcpu
, dr
, &val
))
6211 kvm_register_write(vcpu
, reg
, val
);
6213 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6216 return kvm_skip_emulated_instruction(vcpu
);
6219 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6221 return vcpu
->arch
.dr6
;
6224 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6228 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6230 get_debugreg(vcpu
->arch
.db
[0], 0);
6231 get_debugreg(vcpu
->arch
.db
[1], 1);
6232 get_debugreg(vcpu
->arch
.db
[2], 2);
6233 get_debugreg(vcpu
->arch
.db
[3], 3);
6234 get_debugreg(vcpu
->arch
.dr6
, 6);
6235 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6237 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6238 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6241 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6243 vmcs_writel(GUEST_DR7
, val
);
6246 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6248 return kvm_emulate_cpuid(vcpu
);
6251 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6253 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6254 struct msr_data msr_info
;
6256 msr_info
.index
= ecx
;
6257 msr_info
.host_initiated
= false;
6258 if (vmx_get_msr(vcpu
, &msr_info
)) {
6259 trace_kvm_msr_read_ex(ecx
);
6260 kvm_inject_gp(vcpu
, 0);
6264 trace_kvm_msr_read(ecx
, msr_info
.data
);
6266 /* FIXME: handling of bits 32:63 of rax, rdx */
6267 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6268 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6269 return kvm_skip_emulated_instruction(vcpu
);
6272 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6274 struct msr_data msr
;
6275 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6276 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6277 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6281 msr
.host_initiated
= false;
6282 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6283 trace_kvm_msr_write_ex(ecx
, data
);
6284 kvm_inject_gp(vcpu
, 0);
6288 trace_kvm_msr_write(ecx
, data
);
6289 return kvm_skip_emulated_instruction(vcpu
);
6292 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6294 kvm_apic_update_ppr(vcpu
);
6298 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6300 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6301 CPU_BASED_VIRTUAL_INTR_PENDING
);
6303 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6305 ++vcpu
->stat
.irq_window_exits
;
6309 static int handle_halt(struct kvm_vcpu
*vcpu
)
6311 return kvm_emulate_halt(vcpu
);
6314 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6316 return kvm_emulate_hypercall(vcpu
);
6319 static int handle_invd(struct kvm_vcpu
*vcpu
)
6321 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6324 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6326 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6328 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6329 return kvm_skip_emulated_instruction(vcpu
);
6332 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6336 err
= kvm_rdpmc(vcpu
);
6337 return kvm_complete_insn_gp(vcpu
, err
);
6340 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6342 return kvm_emulate_wbinvd(vcpu
);
6345 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6347 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6348 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6350 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6351 return kvm_skip_emulated_instruction(vcpu
);
6355 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6357 kvm_skip_emulated_instruction(vcpu
);
6358 WARN(1, "this should never happen\n");
6362 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6364 kvm_skip_emulated_instruction(vcpu
);
6365 WARN(1, "this should never happen\n");
6369 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6371 if (likely(fasteoi
)) {
6372 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6373 int access_type
, offset
;
6375 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6376 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6378 * Sane guest uses MOV to write EOI, with written value
6379 * not cared. So make a short-circuit here by avoiding
6380 * heavy instruction emulation.
6382 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6383 (offset
== APIC_EOI
)) {
6384 kvm_lapic_set_eoi(vcpu
);
6385 return kvm_skip_emulated_instruction(vcpu
);
6388 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6391 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6393 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6394 int vector
= exit_qualification
& 0xff;
6396 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6397 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6401 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6403 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6404 u32 offset
= exit_qualification
& 0xfff;
6406 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6407 kvm_apic_write_nodecode(vcpu
, offset
);
6411 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6413 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6414 unsigned long exit_qualification
;
6415 bool has_error_code
= false;
6418 int reason
, type
, idt_v
, idt_index
;
6420 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6421 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6422 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6424 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6426 reason
= (u32
)exit_qualification
>> 30;
6427 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6429 case INTR_TYPE_NMI_INTR
:
6430 vcpu
->arch
.nmi_injected
= false;
6431 vmx_set_nmi_mask(vcpu
, true);
6433 case INTR_TYPE_EXT_INTR
:
6434 case INTR_TYPE_SOFT_INTR
:
6435 kvm_clear_interrupt_queue(vcpu
);
6437 case INTR_TYPE_HARD_EXCEPTION
:
6438 if (vmx
->idt_vectoring_info
&
6439 VECTORING_INFO_DELIVER_CODE_MASK
) {
6440 has_error_code
= true;
6442 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6445 case INTR_TYPE_SOFT_EXCEPTION
:
6446 kvm_clear_exception_queue(vcpu
);
6452 tss_selector
= exit_qualification
;
6454 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6455 type
!= INTR_TYPE_EXT_INTR
&&
6456 type
!= INTR_TYPE_NMI_INTR
))
6457 skip_emulated_instruction(vcpu
);
6459 if (kvm_task_switch(vcpu
, tss_selector
,
6460 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6461 has_error_code
, error_code
) == EMULATE_FAIL
) {
6462 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6463 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6464 vcpu
->run
->internal
.ndata
= 0;
6469 * TODO: What about debug traps on tss switch?
6470 * Are we supposed to inject them and update dr6?
6476 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6478 unsigned long exit_qualification
;
6482 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6485 * EPT violation happened while executing iret from NMI,
6486 * "blocked by NMI" bit has to be set before next VM entry.
6487 * There are errata that may cause this bit to not be set:
6490 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6491 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6492 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6494 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6495 trace_kvm_page_fault(gpa
, exit_qualification
);
6497 /* Is it a read fault? */
6498 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6499 ? PFERR_USER_MASK
: 0;
6500 /* Is it a write fault? */
6501 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6502 ? PFERR_WRITE_MASK
: 0;
6503 /* Is it a fetch fault? */
6504 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6505 ? PFERR_FETCH_MASK
: 0;
6506 /* ept page table entry is present? */
6507 error_code
|= (exit_qualification
&
6508 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6509 EPT_VIOLATION_EXECUTABLE
))
6510 ? PFERR_PRESENT_MASK
: 0;
6512 error_code
|= (exit_qualification
& 0x100) != 0 ?
6513 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6515 vcpu
->arch
.exit_qualification
= exit_qualification
;
6516 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6519 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6525 * A nested guest cannot optimize MMIO vmexits, because we have an
6526 * nGPA here instead of the required GPA.
6528 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6529 if (!is_guest_mode(vcpu
) &&
6530 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6531 trace_kvm_fast_mmio(gpa
);
6532 return kvm_skip_emulated_instruction(vcpu
);
6535 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6539 /* It is the real ept misconfig */
6542 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6543 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6548 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6550 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6551 CPU_BASED_VIRTUAL_NMI_PENDING
);
6552 ++vcpu
->stat
.nmi_window_exits
;
6553 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6558 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6560 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6561 enum emulation_result err
= EMULATE_DONE
;
6564 bool intr_window_requested
;
6565 unsigned count
= 130;
6567 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6568 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6570 while (vmx
->emulation_required
&& count
-- != 0) {
6571 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6572 return handle_interrupt_window(&vmx
->vcpu
);
6574 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6577 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6579 if (err
== EMULATE_USER_EXIT
) {
6580 ++vcpu
->stat
.mmio_exits
;
6585 if (err
!= EMULATE_DONE
) {
6586 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6587 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6588 vcpu
->run
->internal
.ndata
= 0;
6592 if (vcpu
->arch
.halt_request
) {
6593 vcpu
->arch
.halt_request
= 0;
6594 ret
= kvm_vcpu_halt(vcpu
);
6598 if (signal_pending(current
))
6608 static int __grow_ple_window(int val
)
6610 if (ple_window_grow
< 1)
6613 val
= min(val
, ple_window_actual_max
);
6615 if (ple_window_grow
< ple_window
)
6616 val
*= ple_window_grow
;
6618 val
+= ple_window_grow
;
6623 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6628 if (modifier
< ple_window
)
6633 return max(val
, minimum
);
6636 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6638 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6639 int old
= vmx
->ple_window
;
6641 vmx
->ple_window
= __grow_ple_window(old
);
6643 if (vmx
->ple_window
!= old
)
6644 vmx
->ple_window_dirty
= true;
6646 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6649 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6651 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6652 int old
= vmx
->ple_window
;
6654 vmx
->ple_window
= __shrink_ple_window(old
,
6655 ple_window_shrink
, ple_window
);
6657 if (vmx
->ple_window
!= old
)
6658 vmx
->ple_window_dirty
= true;
6660 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6664 * ple_window_actual_max is computed to be one grow_ple_window() below
6665 * ple_window_max. (See __grow_ple_window for the reason.)
6666 * This prevents overflows, because ple_window_max is int.
6667 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6669 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6671 static void update_ple_window_actual_max(void)
6673 ple_window_actual_max
=
6674 __shrink_ple_window(max(ple_window_max
, ple_window
),
6675 ple_window_grow
, INT_MIN
);
6679 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6681 static void wakeup_handler(void)
6683 struct kvm_vcpu
*vcpu
;
6684 int cpu
= smp_processor_id();
6686 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6687 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6688 blocked_vcpu_list
) {
6689 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6691 if (pi_test_on(pi_desc
) == 1)
6692 kvm_vcpu_kick(vcpu
);
6694 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6697 void vmx_enable_tdp(void)
6699 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6700 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6701 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6702 0ull, VMX_EPT_EXECUTABLE_MASK
,
6703 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6706 ept_set_mmio_spte_mask();
6710 static __init
int hardware_setup(void)
6712 int r
= -ENOMEM
, i
, msr
;
6714 rdmsrl_safe(MSR_EFER
, &host_efer
);
6716 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6717 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6719 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6720 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6725 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6726 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6727 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6730 * Allow direct access to the PC debug port (it is often used for I/O
6731 * delays, but the vmexits simply slow things down).
6733 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6734 clear_bit(0x80, vmx_io_bitmap_a
);
6736 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6738 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6739 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6741 if (setup_vmcs_config(&vmcs_config
) < 0) {
6746 if (boot_cpu_has(X86_FEATURE_NX
))
6747 kvm_enable_efer_bits(EFER_NX
);
6749 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6750 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6753 if (!cpu_has_vmx_shadow_vmcs())
6754 enable_shadow_vmcs
= 0;
6755 if (enable_shadow_vmcs
)
6756 init_vmcs_shadow_fields();
6758 if (!cpu_has_vmx_ept() ||
6759 !cpu_has_vmx_ept_4levels() ||
6760 !cpu_has_vmx_ept_mt_wb()) {
6762 enable_unrestricted_guest
= 0;
6763 enable_ept_ad_bits
= 0;
6766 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6767 enable_ept_ad_bits
= 0;
6769 if (!cpu_has_vmx_unrestricted_guest())
6770 enable_unrestricted_guest
= 0;
6772 if (!cpu_has_vmx_flexpriority())
6773 flexpriority_enabled
= 0;
6776 * set_apic_access_page_addr() is used to reload apic access
6777 * page upon invalidation. No need to do anything if not
6778 * using the APIC_ACCESS_ADDR VMCS field.
6780 if (!flexpriority_enabled
)
6781 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6783 if (!cpu_has_vmx_tpr_shadow())
6784 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6786 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6787 kvm_disable_largepages();
6789 if (!cpu_has_vmx_ple())
6792 if (!cpu_has_vmx_apicv()) {
6794 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6797 if (cpu_has_vmx_tsc_scaling()) {
6798 kvm_has_tsc_control
= true;
6799 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6800 kvm_tsc_scaling_ratio_frac_bits
= 48;
6803 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6804 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6805 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6806 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6807 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6808 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6810 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6811 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6812 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6813 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6814 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6815 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6816 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6817 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6819 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6821 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6822 if (msr
== 0x839 /* TMCCT */)
6824 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6828 * TPR reads and writes can be virtualized even if virtual interrupt
6829 * delivery is not in use.
6831 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6832 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6835 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6837 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6844 update_ple_window_actual_max();
6847 * Only enable PML when hardware supports PML feature, and both EPT
6848 * and EPT A/D bit features are enabled -- PML depends on them to work.
6850 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6854 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6855 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6856 kvm_x86_ops
->flush_log_dirty
= NULL
;
6857 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6860 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6863 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6864 cpu_preemption_timer_multi
=
6865 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6867 kvm_x86_ops
->set_hv_timer
= NULL
;
6868 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6871 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6873 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6875 return alloc_kvm_area();
6878 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6879 free_page((unsigned long)vmx_bitmap
[i
]);
6884 static __exit
void hardware_unsetup(void)
6888 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6889 free_page((unsigned long)vmx_bitmap
[i
]);
6895 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6896 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6898 static int handle_pause(struct kvm_vcpu
*vcpu
)
6901 grow_ple_window(vcpu
);
6904 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6905 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6906 * never set PAUSE_EXITING and just set PLE if supported,
6907 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6909 kvm_vcpu_on_spin(vcpu
, true);
6910 return kvm_skip_emulated_instruction(vcpu
);
6913 static int handle_nop(struct kvm_vcpu
*vcpu
)
6915 return kvm_skip_emulated_instruction(vcpu
);
6918 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6920 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6921 return handle_nop(vcpu
);
6924 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6926 kvm_queue_exception(vcpu
, UD_VECTOR
);
6930 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6935 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6937 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6938 return handle_nop(vcpu
);
6942 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6943 * We could reuse a single VMCS for all the L2 guests, but we also want the
6944 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6945 * allows keeping them loaded on the processor, and in the future will allow
6946 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6947 * every entry if they never change.
6948 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6949 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6951 * The following functions allocate and free a vmcs02 in this pool.
6954 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6955 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6957 struct vmcs02_list
*item
;
6958 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6959 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6960 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6961 return &item
->vmcs02
;
6964 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6965 /* Recycle the least recently used VMCS. */
6966 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6967 struct vmcs02_list
, list
);
6968 item
->vmptr
= vmx
->nested
.current_vmptr
;
6969 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6970 return &item
->vmcs02
;
6973 /* Create a new VMCS */
6974 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6977 item
->vmcs02
.vmcs
= alloc_vmcs();
6978 item
->vmcs02
.shadow_vmcs
= NULL
;
6979 if (!item
->vmcs02
.vmcs
) {
6983 loaded_vmcs_init(&item
->vmcs02
);
6984 item
->vmptr
= vmx
->nested
.current_vmptr
;
6985 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6986 vmx
->nested
.vmcs02_num
++;
6987 return &item
->vmcs02
;
6990 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6991 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6993 struct vmcs02_list
*item
;
6994 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6995 if (item
->vmptr
== vmptr
) {
6996 free_loaded_vmcs(&item
->vmcs02
);
6997 list_del(&item
->list
);
6999 vmx
->nested
.vmcs02_num
--;
7005 * Free all VMCSs saved for this vcpu, except the one pointed by
7006 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7007 * must be &vmx->vmcs01.
7009 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
7011 struct vmcs02_list
*item
, *n
;
7013 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7014 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7016 * Something will leak if the above WARN triggers. Better than
7019 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7022 free_loaded_vmcs(&item
->vmcs02
);
7023 list_del(&item
->list
);
7025 vmx
->nested
.vmcs02_num
--;
7030 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7031 * set the success or error code of an emulated VMX instruction, as specified
7032 * by Vol 2B, VMX Instruction Reference, "Conventions".
7034 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7036 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7037 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7038 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7041 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7043 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7044 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7045 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7049 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7050 u32 vm_instruction_error
)
7052 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7054 * failValid writes the error number to the current VMCS, which
7055 * can't be done there isn't a current VMCS.
7057 nested_vmx_failInvalid(vcpu
);
7060 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7061 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7062 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7064 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7066 * We don't need to force a shadow sync because
7067 * VM_INSTRUCTION_ERROR is not shadowed
7071 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7073 /* TODO: not to reset guest simply here. */
7074 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7075 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7078 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7080 struct vcpu_vmx
*vmx
=
7081 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7083 vmx
->nested
.preemption_timer_expired
= true;
7084 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7085 kvm_vcpu_kick(&vmx
->vcpu
);
7087 return HRTIMER_NORESTART
;
7091 * Decode the memory-address operand of a vmx instruction, as recorded on an
7092 * exit caused by such an instruction (run by a guest hypervisor).
7093 * On success, returns 0. When the operand is invalid, returns 1 and throws
7096 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7097 unsigned long exit_qualification
,
7098 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7102 struct kvm_segment s
;
7105 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7106 * Execution", on an exit, vmx_instruction_info holds most of the
7107 * addressing components of the operand. Only the displacement part
7108 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7109 * For how an actual address is calculated from all these components,
7110 * refer to Vol. 1, "Operand Addressing".
7112 int scaling
= vmx_instruction_info
& 3;
7113 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7114 bool is_reg
= vmx_instruction_info
& (1u << 10);
7115 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7116 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7117 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7118 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7119 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7122 kvm_queue_exception(vcpu
, UD_VECTOR
);
7126 /* Addr = segment_base + offset */
7127 /* offset = base + [index * scale] + displacement */
7128 off
= exit_qualification
; /* holds the displacement */
7130 off
+= kvm_register_read(vcpu
, base_reg
);
7132 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7133 vmx_get_segment(vcpu
, &s
, seg_reg
);
7134 *ret
= s
.base
+ off
;
7136 if (addr_size
== 1) /* 32 bit */
7139 /* Checks for #GP/#SS exceptions. */
7141 if (is_long_mode(vcpu
)) {
7142 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7143 * non-canonical form. This is the only check on the memory
7144 * destination for long mode!
7146 exn
= is_noncanonical_address(*ret
, vcpu
);
7147 } else if (is_protmode(vcpu
)) {
7148 /* Protected mode: apply checks for segment validity in the
7150 * - segment type check (#GP(0) may be thrown)
7151 * - usability check (#GP(0)/#SS(0))
7152 * - limit check (#GP(0)/#SS(0))
7155 /* #GP(0) if the destination operand is located in a
7156 * read-only data segment or any code segment.
7158 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7160 /* #GP(0) if the source operand is located in an
7161 * execute-only code segment
7163 exn
= ((s
.type
& 0xa) == 8);
7165 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7168 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7170 exn
= (s
.unusable
!= 0);
7171 /* Protected mode: #GP(0)/#SS(0) if the memory
7172 * operand is outside the segment limit.
7174 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7177 kvm_queue_exception_e(vcpu
,
7178 seg_reg
== VCPU_SREG_SS
?
7179 SS_VECTOR
: GP_VECTOR
,
7187 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7190 struct x86_exception e
;
7192 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7193 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7196 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7197 sizeof(*vmpointer
), &e
)) {
7198 kvm_inject_page_fault(vcpu
, &e
);
7205 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7207 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7208 struct vmcs
*shadow_vmcs
;
7210 if (cpu_has_vmx_msr_bitmap()) {
7211 vmx
->nested
.msr_bitmap
=
7212 (unsigned long *)__get_free_page(GFP_KERNEL
);
7213 if (!vmx
->nested
.msr_bitmap
)
7214 goto out_msr_bitmap
;
7217 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7218 if (!vmx
->nested
.cached_vmcs12
)
7219 goto out_cached_vmcs12
;
7221 if (enable_shadow_vmcs
) {
7222 shadow_vmcs
= alloc_vmcs();
7224 goto out_shadow_vmcs
;
7225 /* mark vmcs as shadow */
7226 shadow_vmcs
->revision_id
|= (1u << 31);
7227 /* init shadow vmcs */
7228 vmcs_clear(shadow_vmcs
);
7229 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7232 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7233 vmx
->nested
.vmcs02_num
= 0;
7235 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7236 HRTIMER_MODE_REL_PINNED
);
7237 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7239 vmx
->nested
.vmxon
= true;
7243 kfree(vmx
->nested
.cached_vmcs12
);
7246 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7253 * Emulate the VMXON instruction.
7254 * Currently, we just remember that VMX is active, and do not save or even
7255 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7256 * do not currently need to store anything in that guest-allocated memory
7257 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7258 * argument is different from the VMXON pointer (which the spec says they do).
7260 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7265 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7266 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7267 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7270 * The Intel VMX Instruction Reference lists a bunch of bits that are
7271 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7272 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7273 * Otherwise, we should fail with #UD. But most faulting conditions
7274 * have already been checked by hardware, prior to the VM-exit for
7275 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7276 * that bit set to 1 in non-root mode.
7278 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7279 kvm_queue_exception(vcpu
, UD_VECTOR
);
7283 if (vmx
->nested
.vmxon
) {
7284 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7285 return kvm_skip_emulated_instruction(vcpu
);
7288 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7289 != VMXON_NEEDED_FEATURES
) {
7290 kvm_inject_gp(vcpu
, 0);
7294 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7299 * The first 4 bytes of VMXON region contain the supported
7300 * VMCS revision identifier
7302 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7303 * which replaces physical address width with 32
7305 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7306 nested_vmx_failInvalid(vcpu
);
7307 return kvm_skip_emulated_instruction(vcpu
);
7310 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7311 if (is_error_page(page
)) {
7312 nested_vmx_failInvalid(vcpu
);
7313 return kvm_skip_emulated_instruction(vcpu
);
7315 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7317 kvm_release_page_clean(page
);
7318 nested_vmx_failInvalid(vcpu
);
7319 return kvm_skip_emulated_instruction(vcpu
);
7322 kvm_release_page_clean(page
);
7324 vmx
->nested
.vmxon_ptr
= vmptr
;
7325 ret
= enter_vmx_operation(vcpu
);
7329 nested_vmx_succeed(vcpu
);
7330 return kvm_skip_emulated_instruction(vcpu
);
7334 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7335 * for running VMX instructions (except VMXON, whose prerequisites are
7336 * slightly different). It also specifies what exception to inject otherwise.
7337 * Note that many of these exceptions have priority over VM exits, so they
7338 * don't have to be checked again here.
7340 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7342 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7343 kvm_queue_exception(vcpu
, UD_VECTOR
);
7349 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7351 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7352 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7355 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7357 if (vmx
->nested
.current_vmptr
== -1ull)
7360 if (enable_shadow_vmcs
) {
7361 /* copy to memory all shadowed fields in case
7362 they were modified */
7363 copy_shadow_to_vmcs12(vmx
);
7364 vmx
->nested
.sync_shadow_vmcs
= false;
7365 vmx_disable_shadow_vmcs(vmx
);
7367 vmx
->nested
.posted_intr_nv
= -1;
7369 /* Flush VMCS12 to guest memory */
7370 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7371 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7372 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7374 vmx
->nested
.current_vmptr
= -1ull;
7378 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7379 * just stops using VMX.
7381 static void free_nested(struct vcpu_vmx
*vmx
)
7383 if (!vmx
->nested
.vmxon
)
7386 vmx
->nested
.vmxon
= false;
7387 free_vpid(vmx
->nested
.vpid02
);
7388 vmx
->nested
.posted_intr_nv
= -1;
7389 vmx
->nested
.current_vmptr
= -1ull;
7390 if (vmx
->nested
.msr_bitmap
) {
7391 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7392 vmx
->nested
.msr_bitmap
= NULL
;
7394 if (enable_shadow_vmcs
) {
7395 vmx_disable_shadow_vmcs(vmx
);
7396 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7397 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7398 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7400 kfree(vmx
->nested
.cached_vmcs12
);
7401 /* Unpin physical memory we referred to in current vmcs02 */
7402 if (vmx
->nested
.apic_access_page
) {
7403 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7404 vmx
->nested
.apic_access_page
= NULL
;
7406 if (vmx
->nested
.virtual_apic_page
) {
7407 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7408 vmx
->nested
.virtual_apic_page
= NULL
;
7410 if (vmx
->nested
.pi_desc_page
) {
7411 kunmap(vmx
->nested
.pi_desc_page
);
7412 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7413 vmx
->nested
.pi_desc_page
= NULL
;
7414 vmx
->nested
.pi_desc
= NULL
;
7417 nested_free_all_saved_vmcss(vmx
);
7420 /* Emulate the VMXOFF instruction */
7421 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7423 if (!nested_vmx_check_permission(vcpu
))
7425 free_nested(to_vmx(vcpu
));
7426 nested_vmx_succeed(vcpu
);
7427 return kvm_skip_emulated_instruction(vcpu
);
7430 /* Emulate the VMCLEAR instruction */
7431 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7433 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7437 if (!nested_vmx_check_permission(vcpu
))
7440 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7443 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7444 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7445 return kvm_skip_emulated_instruction(vcpu
);
7448 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7449 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7450 return kvm_skip_emulated_instruction(vcpu
);
7453 if (vmptr
== vmx
->nested
.current_vmptr
)
7454 nested_release_vmcs12(vmx
);
7456 kvm_vcpu_write_guest(vcpu
,
7457 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7458 &zero
, sizeof(zero
));
7460 nested_free_vmcs02(vmx
, vmptr
);
7462 nested_vmx_succeed(vcpu
);
7463 return kvm_skip_emulated_instruction(vcpu
);
7466 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7468 /* Emulate the VMLAUNCH instruction */
7469 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7471 return nested_vmx_run(vcpu
, true);
7474 /* Emulate the VMRESUME instruction */
7475 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7478 return nested_vmx_run(vcpu
, false);
7482 * Read a vmcs12 field. Since these can have varying lengths and we return
7483 * one type, we chose the biggest type (u64) and zero-extend the return value
7484 * to that size. Note that the caller, handle_vmread, might need to use only
7485 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7486 * 64-bit fields are to be returned).
7488 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7489 unsigned long field
, u64
*ret
)
7491 short offset
= vmcs_field_to_offset(field
);
7497 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7499 switch (vmcs_field_type(field
)) {
7500 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7501 *ret
= *((natural_width
*)p
);
7503 case VMCS_FIELD_TYPE_U16
:
7506 case VMCS_FIELD_TYPE_U32
:
7509 case VMCS_FIELD_TYPE_U64
:
7519 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7520 unsigned long field
, u64 field_value
){
7521 short offset
= vmcs_field_to_offset(field
);
7522 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7526 switch (vmcs_field_type(field
)) {
7527 case VMCS_FIELD_TYPE_U16
:
7528 *(u16
*)p
= field_value
;
7530 case VMCS_FIELD_TYPE_U32
:
7531 *(u32
*)p
= field_value
;
7533 case VMCS_FIELD_TYPE_U64
:
7534 *(u64
*)p
= field_value
;
7536 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7537 *(natural_width
*)p
= field_value
;
7546 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7549 unsigned long field
;
7551 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7552 const unsigned long *fields
= shadow_read_write_fields
;
7553 const int num_fields
= max_shadow_read_write_fields
;
7557 vmcs_load(shadow_vmcs
);
7559 for (i
= 0; i
< num_fields
; i
++) {
7561 switch (vmcs_field_type(field
)) {
7562 case VMCS_FIELD_TYPE_U16
:
7563 field_value
= vmcs_read16(field
);
7565 case VMCS_FIELD_TYPE_U32
:
7566 field_value
= vmcs_read32(field
);
7568 case VMCS_FIELD_TYPE_U64
:
7569 field_value
= vmcs_read64(field
);
7571 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7572 field_value
= vmcs_readl(field
);
7578 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7581 vmcs_clear(shadow_vmcs
);
7582 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7587 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7589 const unsigned long *fields
[] = {
7590 shadow_read_write_fields
,
7591 shadow_read_only_fields
7593 const int max_fields
[] = {
7594 max_shadow_read_write_fields
,
7595 max_shadow_read_only_fields
7598 unsigned long field
;
7599 u64 field_value
= 0;
7600 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7602 vmcs_load(shadow_vmcs
);
7604 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7605 for (i
= 0; i
< max_fields
[q
]; i
++) {
7606 field
= fields
[q
][i
];
7607 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7609 switch (vmcs_field_type(field
)) {
7610 case VMCS_FIELD_TYPE_U16
:
7611 vmcs_write16(field
, (u16
)field_value
);
7613 case VMCS_FIELD_TYPE_U32
:
7614 vmcs_write32(field
, (u32
)field_value
);
7616 case VMCS_FIELD_TYPE_U64
:
7617 vmcs_write64(field
, (u64
)field_value
);
7619 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7620 vmcs_writel(field
, (long)field_value
);
7629 vmcs_clear(shadow_vmcs
);
7630 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7634 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7635 * used before) all generate the same failure when it is missing.
7637 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7639 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7640 if (vmx
->nested
.current_vmptr
== -1ull) {
7641 nested_vmx_failInvalid(vcpu
);
7647 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7649 unsigned long field
;
7651 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7652 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7655 if (!nested_vmx_check_permission(vcpu
))
7658 if (!nested_vmx_check_vmcs12(vcpu
))
7659 return kvm_skip_emulated_instruction(vcpu
);
7661 /* Decode instruction info and find the field to read */
7662 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7663 /* Read the field, zero-extended to a u64 field_value */
7664 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7665 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7666 return kvm_skip_emulated_instruction(vcpu
);
7669 * Now copy part of this value to register or memory, as requested.
7670 * Note that the number of bits actually copied is 32 or 64 depending
7671 * on the guest's mode (32 or 64 bit), not on the given field's length.
7673 if (vmx_instruction_info
& (1u << 10)) {
7674 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7677 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7678 vmx_instruction_info
, true, &gva
))
7680 /* _system ok, as hardware has verified cpl=0 */
7681 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7682 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7685 nested_vmx_succeed(vcpu
);
7686 return kvm_skip_emulated_instruction(vcpu
);
7690 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7692 unsigned long field
;
7694 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7695 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7696 /* The value to write might be 32 or 64 bits, depending on L1's long
7697 * mode, and eventually we need to write that into a field of several
7698 * possible lengths. The code below first zero-extends the value to 64
7699 * bit (field_value), and then copies only the appropriate number of
7700 * bits into the vmcs12 field.
7702 u64 field_value
= 0;
7703 struct x86_exception e
;
7705 if (!nested_vmx_check_permission(vcpu
))
7708 if (!nested_vmx_check_vmcs12(vcpu
))
7709 return kvm_skip_emulated_instruction(vcpu
);
7711 if (vmx_instruction_info
& (1u << 10))
7712 field_value
= kvm_register_readl(vcpu
,
7713 (((vmx_instruction_info
) >> 3) & 0xf));
7715 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7716 vmx_instruction_info
, false, &gva
))
7718 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7719 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7720 kvm_inject_page_fault(vcpu
, &e
);
7726 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7727 if (vmcs_field_readonly(field
)) {
7728 nested_vmx_failValid(vcpu
,
7729 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7730 return kvm_skip_emulated_instruction(vcpu
);
7733 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7734 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7735 return kvm_skip_emulated_instruction(vcpu
);
7738 nested_vmx_succeed(vcpu
);
7739 return kvm_skip_emulated_instruction(vcpu
);
7742 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7744 vmx
->nested
.current_vmptr
= vmptr
;
7745 if (enable_shadow_vmcs
) {
7746 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7747 SECONDARY_EXEC_SHADOW_VMCS
);
7748 vmcs_write64(VMCS_LINK_POINTER
,
7749 __pa(vmx
->vmcs01
.shadow_vmcs
));
7750 vmx
->nested
.sync_shadow_vmcs
= true;
7754 /* Emulate the VMPTRLD instruction */
7755 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7757 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7760 if (!nested_vmx_check_permission(vcpu
))
7763 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7766 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7767 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7768 return kvm_skip_emulated_instruction(vcpu
);
7771 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7772 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7773 return kvm_skip_emulated_instruction(vcpu
);
7776 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7777 struct vmcs12
*new_vmcs12
;
7779 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7780 if (is_error_page(page
)) {
7781 nested_vmx_failInvalid(vcpu
);
7782 return kvm_skip_emulated_instruction(vcpu
);
7784 new_vmcs12
= kmap(page
);
7785 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7787 kvm_release_page_clean(page
);
7788 nested_vmx_failValid(vcpu
,
7789 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7790 return kvm_skip_emulated_instruction(vcpu
);
7793 nested_release_vmcs12(vmx
);
7795 * Load VMCS12 from guest memory since it is not already
7798 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7800 kvm_release_page_clean(page
);
7802 set_current_vmptr(vmx
, vmptr
);
7805 nested_vmx_succeed(vcpu
);
7806 return kvm_skip_emulated_instruction(vcpu
);
7809 /* Emulate the VMPTRST instruction */
7810 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7812 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7813 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7815 struct x86_exception e
;
7817 if (!nested_vmx_check_permission(vcpu
))
7820 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7821 vmx_instruction_info
, true, &vmcs_gva
))
7823 /* ok to use *_system, as hardware has verified cpl=0 */
7824 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7825 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7827 kvm_inject_page_fault(vcpu
, &e
);
7830 nested_vmx_succeed(vcpu
);
7831 return kvm_skip_emulated_instruction(vcpu
);
7834 /* Emulate the INVEPT instruction */
7835 static int handle_invept(struct kvm_vcpu
*vcpu
)
7837 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7838 u32 vmx_instruction_info
, types
;
7841 struct x86_exception e
;
7846 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7847 SECONDARY_EXEC_ENABLE_EPT
) ||
7848 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7849 kvm_queue_exception(vcpu
, UD_VECTOR
);
7853 if (!nested_vmx_check_permission(vcpu
))
7856 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7857 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7859 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7861 if (type
>= 32 || !(types
& (1 << type
))) {
7862 nested_vmx_failValid(vcpu
,
7863 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7864 return kvm_skip_emulated_instruction(vcpu
);
7867 /* According to the Intel VMX instruction reference, the memory
7868 * operand is read even if it isn't needed (e.g., for type==global)
7870 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7871 vmx_instruction_info
, false, &gva
))
7873 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7874 sizeof(operand
), &e
)) {
7875 kvm_inject_page_fault(vcpu
, &e
);
7880 case VMX_EPT_EXTENT_GLOBAL
:
7882 * TODO: track mappings and invalidate
7883 * single context requests appropriately
7885 case VMX_EPT_EXTENT_CONTEXT
:
7886 kvm_mmu_sync_roots(vcpu
);
7887 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7888 nested_vmx_succeed(vcpu
);
7895 return kvm_skip_emulated_instruction(vcpu
);
7898 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7900 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7901 u32 vmx_instruction_info
;
7902 unsigned long type
, types
;
7904 struct x86_exception e
;
7910 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7911 SECONDARY_EXEC_ENABLE_VPID
) ||
7912 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7913 kvm_queue_exception(vcpu
, UD_VECTOR
);
7917 if (!nested_vmx_check_permission(vcpu
))
7920 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7921 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7923 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7924 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7926 if (type
>= 32 || !(types
& (1 << type
))) {
7927 nested_vmx_failValid(vcpu
,
7928 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7929 return kvm_skip_emulated_instruction(vcpu
);
7932 /* according to the intel vmx instruction reference, the memory
7933 * operand is read even if it isn't needed (e.g., for type==global)
7935 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7936 vmx_instruction_info
, false, &gva
))
7938 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7939 sizeof(operand
), &e
)) {
7940 kvm_inject_page_fault(vcpu
, &e
);
7943 if (operand
.vpid
>> 16) {
7944 nested_vmx_failValid(vcpu
,
7945 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7946 return kvm_skip_emulated_instruction(vcpu
);
7950 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7951 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7952 nested_vmx_failValid(vcpu
,
7953 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7954 return kvm_skip_emulated_instruction(vcpu
);
7957 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7958 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7959 if (!operand
.vpid
) {
7960 nested_vmx_failValid(vcpu
,
7961 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7962 return kvm_skip_emulated_instruction(vcpu
);
7965 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7969 return kvm_skip_emulated_instruction(vcpu
);
7972 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7973 nested_vmx_succeed(vcpu
);
7975 return kvm_skip_emulated_instruction(vcpu
);
7978 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7980 unsigned long exit_qualification
;
7982 trace_kvm_pml_full(vcpu
->vcpu_id
);
7984 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7987 * PML buffer FULL happened while executing iret from NMI,
7988 * "blocked by NMI" bit has to be set before next VM entry.
7990 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7991 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7992 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7993 GUEST_INTR_STATE_NMI
);
7996 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7997 * here.., and there's no userspace involvement needed for PML.
8002 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8004 kvm_lapic_expired_hv_timer(vcpu
);
8008 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8010 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8011 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8013 /* Check for memory type validity */
8014 switch (address
& VMX_EPTP_MT_MASK
) {
8015 case VMX_EPTP_MT_UC
:
8016 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8019 case VMX_EPTP_MT_WB
:
8020 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8027 /* only 4 levels page-walk length are valid */
8028 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8031 /* Reserved bits should not be set */
8032 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8035 /* AD, if set, should be supported */
8036 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8037 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8044 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8045 struct vmcs12
*vmcs12
)
8047 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8049 bool accessed_dirty
;
8050 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8052 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8053 !nested_cpu_has_ept(vmcs12
))
8056 if (index
>= VMFUNC_EPTP_ENTRIES
)
8060 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8061 &address
, index
* 8, 8))
8064 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8067 * If the (L2) guest does a vmfunc to the currently
8068 * active ept pointer, we don't have to do anything else
8070 if (vmcs12
->ept_pointer
!= address
) {
8071 if (!valid_ept_address(vcpu
, address
))
8074 kvm_mmu_unload(vcpu
);
8075 mmu
->ept_ad
= accessed_dirty
;
8076 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8077 vmcs12
->ept_pointer
= address
;
8079 * TODO: Check what's the correct approach in case
8080 * mmu reload fails. Currently, we just let the next
8081 * reload potentially fail
8083 kvm_mmu_reload(vcpu
);
8089 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8091 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8092 struct vmcs12
*vmcs12
;
8093 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8096 * VMFUNC is only supported for nested guests, but we always enable the
8097 * secondary control for simplicity; for non-nested mode, fake that we
8098 * didn't by injecting #UD.
8100 if (!is_guest_mode(vcpu
)) {
8101 kvm_queue_exception(vcpu
, UD_VECTOR
);
8105 vmcs12
= get_vmcs12(vcpu
);
8106 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8111 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8117 return kvm_skip_emulated_instruction(vcpu
);
8120 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8121 vmcs_read32(VM_EXIT_INTR_INFO
),
8122 vmcs_readl(EXIT_QUALIFICATION
));
8127 * The exit handlers return 1 if the exit was handled fully and guest execution
8128 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8129 * to be done to userspace and return 0.
8131 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8132 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8133 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8134 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8135 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8136 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8137 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8138 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8139 [EXIT_REASON_CPUID
] = handle_cpuid
,
8140 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8141 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8142 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8143 [EXIT_REASON_HLT
] = handle_halt
,
8144 [EXIT_REASON_INVD
] = handle_invd
,
8145 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8146 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8147 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8148 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8149 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8150 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8151 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8152 [EXIT_REASON_VMREAD
] = handle_vmread
,
8153 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8154 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8155 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8156 [EXIT_REASON_VMON
] = handle_vmon
,
8157 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8158 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8159 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8160 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8161 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8162 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8163 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8164 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8165 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8166 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8167 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8168 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8169 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8170 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8171 [EXIT_REASON_INVEPT
] = handle_invept
,
8172 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8173 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8174 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8175 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8176 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8177 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8178 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8179 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8182 static const int kvm_vmx_max_exit_handlers
=
8183 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8185 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8186 struct vmcs12
*vmcs12
)
8188 unsigned long exit_qualification
;
8189 gpa_t bitmap
, last_bitmap
;
8194 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8195 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8197 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8199 port
= exit_qualification
>> 16;
8200 size
= (exit_qualification
& 7) + 1;
8202 last_bitmap
= (gpa_t
)-1;
8207 bitmap
= vmcs12
->io_bitmap_a
;
8208 else if (port
< 0x10000)
8209 bitmap
= vmcs12
->io_bitmap_b
;
8212 bitmap
+= (port
& 0x7fff) / 8;
8214 if (last_bitmap
!= bitmap
)
8215 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8217 if (b
& (1 << (port
& 7)))
8222 last_bitmap
= bitmap
;
8229 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8230 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8231 * disinterest in the current event (read or write a specific MSR) by using an
8232 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8234 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8235 struct vmcs12
*vmcs12
, u32 exit_reason
)
8237 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8240 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8244 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8245 * for the four combinations of read/write and low/high MSR numbers.
8246 * First we need to figure out which of the four to use:
8248 bitmap
= vmcs12
->msr_bitmap
;
8249 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8251 if (msr_index
>= 0xc0000000) {
8252 msr_index
-= 0xc0000000;
8256 /* Then read the msr_index'th bit from this bitmap: */
8257 if (msr_index
< 1024*8) {
8259 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8261 return 1 & (b
>> (msr_index
& 7));
8263 return true; /* let L1 handle the wrong parameter */
8267 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8268 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8269 * intercept (via guest_host_mask etc.) the current event.
8271 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8272 struct vmcs12
*vmcs12
)
8274 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8275 int cr
= exit_qualification
& 15;
8279 switch ((exit_qualification
>> 4) & 3) {
8280 case 0: /* mov to cr */
8281 reg
= (exit_qualification
>> 8) & 15;
8282 val
= kvm_register_readl(vcpu
, reg
);
8285 if (vmcs12
->cr0_guest_host_mask
&
8286 (val
^ vmcs12
->cr0_read_shadow
))
8290 if ((vmcs12
->cr3_target_count
>= 1 &&
8291 vmcs12
->cr3_target_value0
== val
) ||
8292 (vmcs12
->cr3_target_count
>= 2 &&
8293 vmcs12
->cr3_target_value1
== val
) ||
8294 (vmcs12
->cr3_target_count
>= 3 &&
8295 vmcs12
->cr3_target_value2
== val
) ||
8296 (vmcs12
->cr3_target_count
>= 4 &&
8297 vmcs12
->cr3_target_value3
== val
))
8299 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8303 if (vmcs12
->cr4_guest_host_mask
&
8304 (vmcs12
->cr4_read_shadow
^ val
))
8308 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8314 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8315 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8318 case 1: /* mov from cr */
8321 if (vmcs12
->cpu_based_vm_exec_control
&
8322 CPU_BASED_CR3_STORE_EXITING
)
8326 if (vmcs12
->cpu_based_vm_exec_control
&
8327 CPU_BASED_CR8_STORE_EXITING
)
8334 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8335 * cr0. Other attempted changes are ignored, with no exit.
8337 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8338 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8339 (val
^ vmcs12
->cr0_read_shadow
))
8341 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8342 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8351 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8352 * should handle it ourselves in L0 (and then continue L2). Only call this
8353 * when in is_guest_mode (L2).
8355 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8357 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8358 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8359 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8361 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8362 vmcs_readl(EXIT_QUALIFICATION
),
8363 vmx
->idt_vectoring_info
,
8365 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8369 * The host physical addresses of some pages of guest memory
8370 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8371 * may write to these pages via their host physical address while
8372 * L2 is running, bypassing any address-translation-based dirty
8373 * tracking (e.g. EPT write protection).
8375 * Mark them dirty on every exit from L2 to prevent them from
8376 * getting out of sync with dirty tracking.
8378 nested_mark_vmcs12_pages_dirty(vcpu
);
8380 if (vmx
->nested
.nested_run_pending
)
8383 if (unlikely(vmx
->fail
)) {
8384 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8385 vmcs_read32(VM_INSTRUCTION_ERROR
));
8389 switch (exit_reason
) {
8390 case EXIT_REASON_EXCEPTION_NMI
:
8391 if (is_nmi(intr_info
))
8393 else if (is_page_fault(intr_info
))
8394 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8395 else if (is_no_device(intr_info
) &&
8396 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8398 else if (is_debug(intr_info
) &&
8400 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8402 else if (is_breakpoint(intr_info
) &&
8403 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8405 return vmcs12
->exception_bitmap
&
8406 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8407 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8409 case EXIT_REASON_TRIPLE_FAULT
:
8411 case EXIT_REASON_PENDING_INTERRUPT
:
8412 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8413 case EXIT_REASON_NMI_WINDOW
:
8414 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8415 case EXIT_REASON_TASK_SWITCH
:
8417 case EXIT_REASON_CPUID
:
8419 case EXIT_REASON_HLT
:
8420 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8421 case EXIT_REASON_INVD
:
8423 case EXIT_REASON_INVLPG
:
8424 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8425 case EXIT_REASON_RDPMC
:
8426 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8427 case EXIT_REASON_RDRAND
:
8428 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8429 case EXIT_REASON_RDSEED
:
8430 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8431 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8432 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8433 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8434 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8435 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8436 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8437 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8438 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8440 * VMX instructions trap unconditionally. This allows L1 to
8441 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8444 case EXIT_REASON_CR_ACCESS
:
8445 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8446 case EXIT_REASON_DR_ACCESS
:
8447 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8448 case EXIT_REASON_IO_INSTRUCTION
:
8449 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8450 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8451 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8452 case EXIT_REASON_MSR_READ
:
8453 case EXIT_REASON_MSR_WRITE
:
8454 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8455 case EXIT_REASON_INVALID_STATE
:
8457 case EXIT_REASON_MWAIT_INSTRUCTION
:
8458 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8459 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8460 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8461 case EXIT_REASON_MONITOR_INSTRUCTION
:
8462 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8463 case EXIT_REASON_PAUSE_INSTRUCTION
:
8464 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8465 nested_cpu_has2(vmcs12
,
8466 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8467 case EXIT_REASON_MCE_DURING_VMENTRY
:
8469 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8470 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8471 case EXIT_REASON_APIC_ACCESS
:
8472 return nested_cpu_has2(vmcs12
,
8473 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8474 case EXIT_REASON_APIC_WRITE
:
8475 case EXIT_REASON_EOI_INDUCED
:
8476 /* apic_write and eoi_induced should exit unconditionally. */
8478 case EXIT_REASON_EPT_VIOLATION
:
8480 * L0 always deals with the EPT violation. If nested EPT is
8481 * used, and the nested mmu code discovers that the address is
8482 * missing in the guest EPT table (EPT12), the EPT violation
8483 * will be injected with nested_ept_inject_page_fault()
8486 case EXIT_REASON_EPT_MISCONFIG
:
8488 * L2 never uses directly L1's EPT, but rather L0's own EPT
8489 * table (shadow on EPT) or a merged EPT table that L0 built
8490 * (EPT on EPT). So any problems with the structure of the
8491 * table is L0's fault.
8494 case EXIT_REASON_INVPCID
:
8496 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8497 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8498 case EXIT_REASON_WBINVD
:
8499 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8500 case EXIT_REASON_XSETBV
:
8502 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8504 * This should never happen, since it is not possible to
8505 * set XSS to a non-zero value---neither in L1 nor in L2.
8506 * If if it were, XSS would have to be checked against
8507 * the XSS exit bitmap in vmcs12.
8509 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8510 case EXIT_REASON_PREEMPTION_TIMER
:
8512 case EXIT_REASON_PML_FULL
:
8513 /* We emulate PML support to L1. */
8515 case EXIT_REASON_VMFUNC
:
8516 /* VM functions are emulated through L2->L0 vmexits. */
8523 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8525 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8528 * At this point, the exit interruption info in exit_intr_info
8529 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8530 * we need to query the in-kernel LAPIC.
8532 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8533 if ((exit_intr_info
&
8534 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8535 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8536 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8537 vmcs12
->vm_exit_intr_error_code
=
8538 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8541 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8542 vmcs_readl(EXIT_QUALIFICATION
));
8546 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8548 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8549 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8552 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8555 __free_page(vmx
->pml_pg
);
8560 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8562 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8566 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8568 /* Do nothing if PML buffer is empty */
8569 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8572 /* PML index always points to next available PML buffer entity */
8573 if (pml_idx
>= PML_ENTITY_NUM
)
8578 pml_buf
= page_address(vmx
->pml_pg
);
8579 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8582 gpa
= pml_buf
[pml_idx
];
8583 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8584 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8587 /* reset PML index */
8588 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8592 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8593 * Called before reporting dirty_bitmap to userspace.
8595 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8598 struct kvm_vcpu
*vcpu
;
8600 * We only need to kick vcpu out of guest mode here, as PML buffer
8601 * is flushed at beginning of all VMEXITs, and it's obvious that only
8602 * vcpus running in guest are possible to have unflushed GPAs in PML
8605 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8606 kvm_vcpu_kick(vcpu
);
8609 static void vmx_dump_sel(char *name
, uint32_t sel
)
8611 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8612 name
, vmcs_read16(sel
),
8613 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8614 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8615 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8618 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8620 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8621 name
, vmcs_read32(limit
),
8622 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8625 static void dump_vmcs(void)
8627 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8628 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8629 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8630 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8631 u32 secondary_exec_control
= 0;
8632 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8633 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8636 if (cpu_has_secondary_exec_ctrls())
8637 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8639 pr_err("*** Guest State ***\n");
8640 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8641 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8642 vmcs_readl(CR0_GUEST_HOST_MASK
));
8643 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8644 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8645 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8646 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8647 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8649 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8650 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8651 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8652 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8654 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8655 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8656 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8657 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8658 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8659 vmcs_readl(GUEST_SYSENTER_ESP
),
8660 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8661 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8662 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8663 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8664 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8665 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8666 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8667 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8668 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8669 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8670 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8671 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8672 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8673 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8674 efer
, vmcs_read64(GUEST_IA32_PAT
));
8675 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8676 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8677 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8678 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8679 pr_err("PerfGlobCtl = 0x%016llx\n",
8680 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8681 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8682 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8683 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8684 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8685 vmcs_read32(GUEST_ACTIVITY_STATE
));
8686 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8687 pr_err("InterruptStatus = %04x\n",
8688 vmcs_read16(GUEST_INTR_STATUS
));
8690 pr_err("*** Host State ***\n");
8691 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8692 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8693 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8694 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8695 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8696 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8697 vmcs_read16(HOST_TR_SELECTOR
));
8698 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8699 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8700 vmcs_readl(HOST_TR_BASE
));
8701 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8702 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8703 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8704 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8705 vmcs_readl(HOST_CR4
));
8706 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8707 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8708 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8709 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8710 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8711 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8712 vmcs_read64(HOST_IA32_EFER
),
8713 vmcs_read64(HOST_IA32_PAT
));
8714 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8715 pr_err("PerfGlobCtl = 0x%016llx\n",
8716 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8718 pr_err("*** Control State ***\n");
8719 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8720 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8721 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8722 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8723 vmcs_read32(EXCEPTION_BITMAP
),
8724 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8725 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8726 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8727 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8728 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8729 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8730 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8731 vmcs_read32(VM_EXIT_INTR_INFO
),
8732 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8733 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8734 pr_err(" reason=%08x qualification=%016lx\n",
8735 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8736 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8737 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8738 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8739 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8740 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8741 pr_err("TSC Multiplier = 0x%016llx\n",
8742 vmcs_read64(TSC_MULTIPLIER
));
8743 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8744 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8745 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8746 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8747 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8748 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8749 n
= vmcs_read32(CR3_TARGET_COUNT
);
8750 for (i
= 0; i
+ 1 < n
; i
+= 4)
8751 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8752 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8753 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8755 pr_err("CR3 target%u=%016lx\n",
8756 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8757 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8758 pr_err("PLE Gap=%08x Window=%08x\n",
8759 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8760 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8761 pr_err("Virtual processor ID = 0x%04x\n",
8762 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8766 * The guest has exited. See if we can fix it or if we need userspace
8769 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8772 u32 exit_reason
= vmx
->exit_reason
;
8773 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8775 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8778 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8779 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8780 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8781 * mode as if vcpus is in root mode, the PML buffer must has been
8785 vmx_flush_pml_buffer(vcpu
);
8787 /* If guest state is invalid, start emulating */
8788 if (vmx
->emulation_required
)
8789 return handle_invalid_guest_state(vcpu
);
8791 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8792 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8794 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8796 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8797 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8802 if (unlikely(vmx
->fail
)) {
8803 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8804 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8805 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8811 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8812 * delivery event since it indicates guest is accessing MMIO.
8813 * The vm-exit can be triggered again after return to guest that
8814 * will cause infinite loop.
8816 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8817 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8818 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8819 exit_reason
!= EXIT_REASON_PML_FULL
&&
8820 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8821 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8822 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8823 vcpu
->run
->internal
.ndata
= 3;
8824 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8825 vcpu
->run
->internal
.data
[1] = exit_reason
;
8826 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8827 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8828 vcpu
->run
->internal
.ndata
++;
8829 vcpu
->run
->internal
.data
[3] =
8830 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8835 if (exit_reason
< kvm_vmx_max_exit_handlers
8836 && kvm_vmx_exit_handlers
[exit_reason
])
8837 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8839 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8841 kvm_queue_exception(vcpu
, UD_VECTOR
);
8846 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8848 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8850 if (is_guest_mode(vcpu
) &&
8851 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8854 if (irr
== -1 || tpr
< irr
) {
8855 vmcs_write32(TPR_THRESHOLD
, 0);
8859 vmcs_write32(TPR_THRESHOLD
, irr
);
8862 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8864 u32 sec_exec_control
;
8866 /* Postpone execution until vmcs01 is the current VMCS. */
8867 if (is_guest_mode(vcpu
)) {
8868 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8872 if (!cpu_has_vmx_virtualize_x2apic_mode())
8875 if (!cpu_need_tpr_shadow(vcpu
))
8878 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8881 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8882 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8884 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8885 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8886 vmx_flush_tlb_ept_only(vcpu
);
8888 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8890 vmx_set_msr_bitmap(vcpu
);
8893 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8895 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8898 * Currently we do not handle the nested case where L2 has an
8899 * APIC access page of its own; that page is still pinned.
8900 * Hence, we skip the case where the VCPU is in guest mode _and_
8901 * L1 prepared an APIC access page for L2.
8903 * For the case where L1 and L2 share the same APIC access page
8904 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8905 * in the vmcs12), this function will only update either the vmcs01
8906 * or the vmcs02. If the former, the vmcs02 will be updated by
8907 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8908 * the next L2->L1 exit.
8910 if (!is_guest_mode(vcpu
) ||
8911 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8912 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8913 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8914 vmx_flush_tlb_ept_only(vcpu
);
8918 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8926 status
= vmcs_read16(GUEST_INTR_STATUS
);
8928 if (max_isr
!= old
) {
8930 status
|= max_isr
<< 8;
8931 vmcs_write16(GUEST_INTR_STATUS
, status
);
8935 static void vmx_set_rvi(int vector
)
8943 status
= vmcs_read16(GUEST_INTR_STATUS
);
8944 old
= (u8
)status
& 0xff;
8945 if ((u8
)vector
!= old
) {
8947 status
|= (u8
)vector
;
8948 vmcs_write16(GUEST_INTR_STATUS
, status
);
8952 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8954 if (!is_guest_mode(vcpu
)) {
8955 vmx_set_rvi(max_irr
);
8963 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8966 if (nested_exit_on_intr(vcpu
))
8970 * Else, fall back to pre-APICv interrupt injection since L2
8971 * is run without virtual interrupt delivery.
8973 if (!kvm_event_needs_reinjection(vcpu
) &&
8974 vmx_interrupt_allowed(vcpu
)) {
8975 kvm_queue_interrupt(vcpu
, max_irr
, false);
8976 vmx_inject_irq(vcpu
);
8980 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8985 WARN_ON(!vcpu
->arch
.apicv_active
);
8986 if (pi_test_on(&vmx
->pi_desc
)) {
8987 pi_clear_on(&vmx
->pi_desc
);
8989 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8990 * But on x86 this is just a compiler barrier anyway.
8992 smp_mb__after_atomic();
8993 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8995 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8997 vmx_hwapic_irr_update(vcpu
, max_irr
);
9001 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9003 if (!kvm_vcpu_apicv_active(vcpu
))
9006 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9007 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9008 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9009 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9012 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9014 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9016 pi_clear_on(&vmx
->pi_desc
);
9017 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9020 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9022 u32 exit_intr_info
= 0;
9023 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9025 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9026 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9029 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9030 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9031 vmx
->exit_intr_info
= exit_intr_info
;
9033 /* if exit due to PF check for async PF */
9034 if (is_page_fault(exit_intr_info
))
9035 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9037 /* Handle machine checks before interrupts are enabled */
9038 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9039 is_machine_check(exit_intr_info
))
9040 kvm_machine_check();
9042 /* We need to handle NMIs before interrupts are enabled */
9043 if (is_nmi(exit_intr_info
)) {
9044 kvm_before_handle_nmi(&vmx
->vcpu
);
9046 kvm_after_handle_nmi(&vmx
->vcpu
);
9050 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9052 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9053 register void *__sp
asm(_ASM_SP
);
9055 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9056 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9057 unsigned int vector
;
9058 unsigned long entry
;
9060 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9061 #ifdef CONFIG_X86_64
9065 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9066 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9067 entry
= gate_offset(*desc
);
9069 #ifdef CONFIG_X86_64
9070 "mov %%" _ASM_SP
", %[sp]\n\t"
9071 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9076 __ASM_SIZE(push
) " $%c[cs]\n\t"
9077 "call *%[entry]\n\t"
9079 #ifdef CONFIG_X86_64
9085 [ss
]"i"(__KERNEL_DS
),
9086 [cs
]"i"(__KERNEL_CS
)
9090 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9092 static bool vmx_has_high_real_mode_segbase(void)
9094 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9097 static bool vmx_mpx_supported(void)
9099 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9100 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9103 static bool vmx_xsaves_supported(void)
9105 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9106 SECONDARY_EXEC_XSAVES
;
9109 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9114 bool idtv_info_valid
;
9116 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9118 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9121 * Can't use vmx->exit_intr_info since we're not sure what
9122 * the exit reason is.
9124 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9125 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9126 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9128 * SDM 3: 27.7.1.2 (September 2008)
9129 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9130 * a guest IRET fault.
9131 * SDM 3: 23.2.2 (September 2008)
9132 * Bit 12 is undefined in any of the following cases:
9133 * If the VM exit sets the valid bit in the IDT-vectoring
9134 * information field.
9135 * If the VM exit is due to a double fault.
9137 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9138 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9139 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9140 GUEST_INTR_STATE_NMI
);
9142 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9143 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9144 & GUEST_INTR_STATE_NMI
);
9147 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9148 u32 idt_vectoring_info
,
9149 int instr_len_field
,
9150 int error_code_field
)
9154 bool idtv_info_valid
;
9156 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9158 vcpu
->arch
.nmi_injected
= false;
9159 kvm_clear_exception_queue(vcpu
);
9160 kvm_clear_interrupt_queue(vcpu
);
9162 if (!idtv_info_valid
)
9165 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9167 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9168 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9171 case INTR_TYPE_NMI_INTR
:
9172 vcpu
->arch
.nmi_injected
= true;
9174 * SDM 3: 27.7.1.2 (September 2008)
9175 * Clear bit "block by NMI" before VM entry if a NMI
9178 vmx_set_nmi_mask(vcpu
, false);
9180 case INTR_TYPE_SOFT_EXCEPTION
:
9181 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9183 case INTR_TYPE_HARD_EXCEPTION
:
9184 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9185 u32 err
= vmcs_read32(error_code_field
);
9186 kvm_requeue_exception_e(vcpu
, vector
, err
);
9188 kvm_requeue_exception(vcpu
, vector
);
9190 case INTR_TYPE_SOFT_INTR
:
9191 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9193 case INTR_TYPE_EXT_INTR
:
9194 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9201 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9203 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9204 VM_EXIT_INSTRUCTION_LEN
,
9205 IDT_VECTORING_ERROR_CODE
);
9208 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9210 __vmx_complete_interrupts(vcpu
,
9211 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9212 VM_ENTRY_INSTRUCTION_LEN
,
9213 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9215 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9218 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9221 struct perf_guest_switch_msr
*msrs
;
9223 msrs
= perf_guest_get_msrs(&nr_msrs
);
9228 for (i
= 0; i
< nr_msrs
; i
++)
9229 if (msrs
[i
].host
== msrs
[i
].guest
)
9230 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9232 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9236 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9238 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9242 if (vmx
->hv_deadline_tsc
== -1)
9246 if (vmx
->hv_deadline_tsc
> tscl
)
9247 /* sure to be 32 bit only because checked on set_hv_timer */
9248 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9249 cpu_preemption_timer_multi
);
9253 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9256 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9258 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9259 unsigned long debugctlmsr
, cr3
, cr4
;
9261 /* Don't enter VMX if guest state is invalid, let the exit handler
9262 start emulation until we arrive back to a valid state */
9263 if (vmx
->emulation_required
)
9266 if (vmx
->ple_window_dirty
) {
9267 vmx
->ple_window_dirty
= false;
9268 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9271 if (vmx
->nested
.sync_shadow_vmcs
) {
9272 copy_vmcs12_to_shadow(vmx
);
9273 vmx
->nested
.sync_shadow_vmcs
= false;
9276 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9277 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9278 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9279 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9281 cr3
= __get_current_cr3_fast();
9282 if (unlikely(cr3
!= vmx
->host_state
.vmcs_host_cr3
)) {
9283 vmcs_writel(HOST_CR3
, cr3
);
9284 vmx
->host_state
.vmcs_host_cr3
= cr3
;
9287 cr4
= cr4_read_shadow();
9288 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
9289 vmcs_writel(HOST_CR4
, cr4
);
9290 vmx
->host_state
.vmcs_host_cr4
= cr4
;
9293 /* When single-stepping over STI and MOV SS, we must clear the
9294 * corresponding interruptibility bits in the guest state. Otherwise
9295 * vmentry fails as it then expects bit 14 (BS) in pending debug
9296 * exceptions being set, but that's not correct for the guest debugging
9298 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9299 vmx_set_interrupt_shadow(vcpu
, 0);
9301 if (vmx
->guest_pkru_valid
)
9302 __write_pkru(vmx
->guest_pkru
);
9304 atomic_switch_perf_msrs(vmx
);
9305 debugctlmsr
= get_debugctlmsr();
9307 vmx_arm_hv_timer(vcpu
);
9309 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9311 /* Store host registers */
9312 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9313 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9314 "push %%" _ASM_CX
" \n\t"
9315 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9317 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9318 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9320 /* Reload cr2 if changed */
9321 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9322 "mov %%cr2, %%" _ASM_DX
" \n\t"
9323 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9325 "mov %%" _ASM_AX
", %%cr2 \n\t"
9327 /* Check if vmlaunch of vmresume is needed */
9328 "cmpl $0, %c[launched](%0) \n\t"
9329 /* Load guest registers. Don't clobber flags. */
9330 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9331 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9332 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9333 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9334 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9335 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9336 #ifdef CONFIG_X86_64
9337 "mov %c[r8](%0), %%r8 \n\t"
9338 "mov %c[r9](%0), %%r9 \n\t"
9339 "mov %c[r10](%0), %%r10 \n\t"
9340 "mov %c[r11](%0), %%r11 \n\t"
9341 "mov %c[r12](%0), %%r12 \n\t"
9342 "mov %c[r13](%0), %%r13 \n\t"
9343 "mov %c[r14](%0), %%r14 \n\t"
9344 "mov %c[r15](%0), %%r15 \n\t"
9346 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9348 /* Enter guest mode */
9350 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9352 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9354 /* Save guest registers, load host registers, keep flags */
9355 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9357 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9358 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9359 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9360 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9361 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9362 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9363 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9364 #ifdef CONFIG_X86_64
9365 "mov %%r8, %c[r8](%0) \n\t"
9366 "mov %%r9, %c[r9](%0) \n\t"
9367 "mov %%r10, %c[r10](%0) \n\t"
9368 "mov %%r11, %c[r11](%0) \n\t"
9369 "mov %%r12, %c[r12](%0) \n\t"
9370 "mov %%r13, %c[r13](%0) \n\t"
9371 "mov %%r14, %c[r14](%0) \n\t"
9372 "mov %%r15, %c[r15](%0) \n\t"
9374 "mov %%cr2, %%" _ASM_AX
" \n\t"
9375 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9377 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9378 "setbe %c[fail](%0) \n\t"
9379 ".pushsection .rodata \n\t"
9380 ".global vmx_return \n\t"
9381 "vmx_return: " _ASM_PTR
" 2b \n\t"
9383 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9384 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9385 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9386 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9387 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9388 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9389 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9390 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9391 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9392 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9393 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9394 #ifdef CONFIG_X86_64
9395 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9396 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9397 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9398 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9399 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9400 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9401 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9402 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9404 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9405 [wordsize
]"i"(sizeof(ulong
))
9407 #ifdef CONFIG_X86_64
9408 , "rax", "rbx", "rdi", "rsi"
9409 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9411 , "eax", "ebx", "edi", "esi"
9415 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9417 update_debugctlmsr(debugctlmsr
);
9419 #ifndef CONFIG_X86_64
9421 * The sysexit path does not restore ds/es, so we must set them to
9422 * a reasonable value ourselves.
9424 * We can't defer this to vmx_load_host_state() since that function
9425 * may be executed in interrupt context, which saves and restore segments
9426 * around it, nullifying its effect.
9428 loadsegment(ds
, __USER_DS
);
9429 loadsegment(es
, __USER_DS
);
9432 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9433 | (1 << VCPU_EXREG_RFLAGS
)
9434 | (1 << VCPU_EXREG_PDPTR
)
9435 | (1 << VCPU_EXREG_SEGMENTS
)
9436 | (1 << VCPU_EXREG_CR3
));
9437 vcpu
->arch
.regs_dirty
= 0;
9439 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9441 vmx
->loaded_vmcs
->launched
= 1;
9443 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9446 * eager fpu is enabled if PKEY is supported and CR4 is switched
9447 * back on host, so it is safe to read guest PKRU from current
9450 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9451 vmx
->guest_pkru
= __read_pkru();
9452 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9453 vmx
->guest_pkru_valid
= true;
9454 __write_pkru(vmx
->host_pkru
);
9456 vmx
->guest_pkru_valid
= false;
9460 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9461 * we did not inject a still-pending event to L1 now because of
9462 * nested_run_pending, we need to re-enable this bit.
9464 if (vmx
->nested
.nested_run_pending
)
9465 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9467 vmx
->nested
.nested_run_pending
= 0;
9469 vmx_complete_atomic_exit(vmx
);
9470 vmx_recover_nmi_blocking(vmx
);
9471 vmx_complete_interrupts(vmx
);
9473 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9475 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9477 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9480 if (vmx
->loaded_vmcs
== vmcs
)
9484 vmx
->loaded_vmcs
= vmcs
;
9486 vmx_vcpu_load(vcpu
, cpu
);
9492 * Ensure that the current vmcs of the logical processor is the
9493 * vmcs01 of the vcpu before calling free_nested().
9495 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9497 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9500 r
= vcpu_load(vcpu
);
9502 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9507 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9509 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9512 vmx_destroy_pml_buffer(vmx
);
9513 free_vpid(vmx
->vpid
);
9514 leave_guest_mode(vcpu
);
9515 vmx_free_vcpu_nested(vcpu
);
9516 free_loaded_vmcs(vmx
->loaded_vmcs
);
9517 kfree(vmx
->guest_msrs
);
9518 kvm_vcpu_uninit(vcpu
);
9519 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9522 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9525 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9529 return ERR_PTR(-ENOMEM
);
9531 vmx
->vpid
= allocate_vpid();
9533 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9540 * If PML is turned on, failure on enabling PML just results in failure
9541 * of creating the vcpu, therefore we can simplify PML logic (by
9542 * avoiding dealing with cases, such as enabling PML partially on vcpus
9543 * for the guest, etc.
9546 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9551 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9552 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9555 if (!vmx
->guest_msrs
)
9558 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9559 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9560 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9561 if (!vmx
->loaded_vmcs
->vmcs
)
9563 loaded_vmcs_init(vmx
->loaded_vmcs
);
9566 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9567 vmx
->vcpu
.cpu
= cpu
;
9568 err
= vmx_vcpu_setup(vmx
);
9569 vmx_vcpu_put(&vmx
->vcpu
);
9573 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9574 err
= alloc_apic_access_page(kvm
);
9580 if (!kvm
->arch
.ept_identity_map_addr
)
9581 kvm
->arch
.ept_identity_map_addr
=
9582 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9583 err
= init_rmode_identity_map(kvm
);
9589 nested_vmx_setup_ctls_msrs(vmx
);
9590 vmx
->nested
.vpid02
= allocate_vpid();
9593 vmx
->nested
.posted_intr_nv
= -1;
9594 vmx
->nested
.current_vmptr
= -1ull;
9596 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9601 free_vpid(vmx
->nested
.vpid02
);
9602 free_loaded_vmcs(vmx
->loaded_vmcs
);
9604 kfree(vmx
->guest_msrs
);
9606 vmx_destroy_pml_buffer(vmx
);
9608 kvm_vcpu_uninit(&vmx
->vcpu
);
9610 free_vpid(vmx
->vpid
);
9611 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9612 return ERR_PTR(err
);
9615 static void __init
vmx_check_processor_compat(void *rtn
)
9617 struct vmcs_config vmcs_conf
;
9620 if (setup_vmcs_config(&vmcs_conf
) < 0)
9622 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9623 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9624 smp_processor_id());
9629 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9634 /* For VT-d and EPT combination
9635 * 1. MMIO: always map as UC
9637 * a. VT-d without snooping control feature: can't guarantee the
9638 * result, try to trust guest.
9639 * b. VT-d with snooping control feature: snooping control feature of
9640 * VT-d engine can guarantee the cache correctness. Just set it
9641 * to WB to keep consistent with host. So the same as item 3.
9642 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9643 * consistent with host MTRR
9646 cache
= MTRR_TYPE_UNCACHABLE
;
9650 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9651 ipat
= VMX_EPT_IPAT_BIT
;
9652 cache
= MTRR_TYPE_WRBACK
;
9656 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9657 ipat
= VMX_EPT_IPAT_BIT
;
9658 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9659 cache
= MTRR_TYPE_WRBACK
;
9661 cache
= MTRR_TYPE_UNCACHABLE
;
9665 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9668 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9671 static int vmx_get_lpage_level(void)
9673 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9674 return PT_DIRECTORY_LEVEL
;
9676 /* For shadow and EPT supported 1GB page */
9677 return PT_PDPE_LEVEL
;
9680 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9683 * These bits in the secondary execution controls field
9684 * are dynamic, the others are mostly based on the hypervisor
9685 * architecture and the guest's CPUID. Do not touch the
9689 SECONDARY_EXEC_SHADOW_VMCS
|
9690 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9691 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9693 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9695 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9696 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9700 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9701 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9703 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9706 struct kvm_cpuid_entry2
*entry
;
9708 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9709 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9711 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9712 if (entry && (entry->_reg & (_cpuid_mask))) \
9713 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9716 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9717 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9718 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9719 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9720 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9721 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9722 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9723 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9724 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9725 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9726 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9727 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9728 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9729 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9730 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9732 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9733 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9734 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9735 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9736 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9737 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9738 cr4_fixed1_update(bit(11), ecx
, bit(2));
9740 #undef cr4_fixed1_update
9743 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9745 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9747 if (cpu_has_secondary_exec_ctrls()) {
9748 vmx_compute_secondary_exec_control(vmx
);
9749 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9752 if (nested_vmx_allowed(vcpu
))
9753 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9754 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9756 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9757 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9759 if (nested_vmx_allowed(vcpu
))
9760 nested_vmx_cr_fixed1_bits_update(vcpu
);
9763 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9765 if (func
== 1 && nested
)
9766 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9769 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9770 struct x86_exception
*fault
)
9772 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9773 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9775 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9777 if (vmx
->nested
.pml_full
) {
9778 exit_reason
= EXIT_REASON_PML_FULL
;
9779 vmx
->nested
.pml_full
= false;
9780 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9781 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9782 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9784 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9786 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9787 vmcs12
->guest_physical_address
= fault
->address
;
9790 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9792 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9795 /* Callbacks for nested_ept_init_mmu_context: */
9797 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9799 /* return the page table to be shadowed - in our case, EPT12 */
9800 return get_vmcs12(vcpu
)->ept_pointer
;
9803 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9805 WARN_ON(mmu_is_nested(vcpu
));
9806 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9809 kvm_mmu_unload(vcpu
);
9810 kvm_init_shadow_ept_mmu(vcpu
,
9811 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9812 VMX_EPT_EXECUTE_ONLY_BIT
,
9813 nested_ept_ad_enabled(vcpu
));
9814 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9815 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9816 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9818 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9822 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9824 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9827 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9830 bool inequality
, bit
;
9832 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9834 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9835 vmcs12
->page_fault_error_code_match
;
9836 return inequality
^ bit
;
9839 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9840 struct x86_exception
*fault
)
9842 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9844 WARN_ON(!is_guest_mode(vcpu
));
9846 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9847 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9848 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9849 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9850 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9853 kvm_inject_page_fault(vcpu
, fault
);
9857 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9858 struct vmcs12
*vmcs12
);
9860 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9861 struct vmcs12
*vmcs12
)
9863 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9867 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9869 * Translate L1 physical address to host physical
9870 * address for vmcs02. Keep the page pinned, so this
9871 * physical address remains valid. We keep a reference
9872 * to it so we can release it later.
9874 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9875 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9876 vmx
->nested
.apic_access_page
= NULL
;
9878 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9880 * If translation failed, no matter: This feature asks
9881 * to exit when accessing the given address, and if it
9882 * can never be accessed, this feature won't do
9885 if (!is_error_page(page
)) {
9886 vmx
->nested
.apic_access_page
= page
;
9887 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9888 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9890 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9891 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9893 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9894 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9895 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9896 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9897 kvm_vcpu_reload_apic_access_page(vcpu
);
9900 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9901 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9902 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9903 vmx
->nested
.virtual_apic_page
= NULL
;
9905 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9908 * If translation failed, VM entry will fail because
9909 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9910 * Failing the vm entry is _not_ what the processor
9911 * does but it's basically the only possibility we
9912 * have. We could still enter the guest if CR8 load
9913 * exits are enabled, CR8 store exits are enabled, and
9914 * virtualize APIC access is disabled; in this case
9915 * the processor would never use the TPR shadow and we
9916 * could simply clear the bit from the execution
9917 * control. But such a configuration is useless, so
9918 * let's keep the code simple.
9920 if (!is_error_page(page
)) {
9921 vmx
->nested
.virtual_apic_page
= page
;
9922 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9923 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9927 if (nested_cpu_has_posted_intr(vmcs12
)) {
9928 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9929 kunmap(vmx
->nested
.pi_desc_page
);
9930 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9931 vmx
->nested
.pi_desc_page
= NULL
;
9933 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9934 if (is_error_page(page
))
9936 vmx
->nested
.pi_desc_page
= page
;
9937 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9938 vmx
->nested
.pi_desc
=
9939 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9940 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9942 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9943 page_to_phys(vmx
->nested
.pi_desc_page
) +
9944 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9947 if (cpu_has_vmx_msr_bitmap() &&
9948 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9949 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9952 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9953 CPU_BASED_USE_MSR_BITMAPS
);
9956 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9958 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9961 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9964 /* Make sure short timeouts reliably trigger an immediate vmexit.
9965 * hrtimer_start does not guarantee this. */
9966 if (preemption_timeout
<= 1) {
9967 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9971 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9972 preemption_timeout
*= 1000000;
9973 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9974 hrtimer_start(&vmx
->nested
.preemption_timer
,
9975 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9978 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9979 struct vmcs12
*vmcs12
)
9981 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9984 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9985 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9991 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9992 struct vmcs12
*vmcs12
)
9994 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9997 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10004 * Merge L0's and L1's MSR bitmap, return false to indicate that
10005 * we do not use the hardware.
10007 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10008 struct vmcs12
*vmcs12
)
10012 unsigned long *msr_bitmap_l1
;
10013 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10015 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10016 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10019 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10020 if (is_error_page(page
))
10022 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10024 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10026 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10027 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10028 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10029 nested_vmx_disable_intercept_for_msr(
10030 msr_bitmap_l1
, msr_bitmap_l0
,
10033 nested_vmx_disable_intercept_for_msr(
10034 msr_bitmap_l1
, msr_bitmap_l0
,
10035 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10036 MSR_TYPE_R
| MSR_TYPE_W
);
10038 if (nested_cpu_has_vid(vmcs12
)) {
10039 nested_vmx_disable_intercept_for_msr(
10040 msr_bitmap_l1
, msr_bitmap_l0
,
10041 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10043 nested_vmx_disable_intercept_for_msr(
10044 msr_bitmap_l1
, msr_bitmap_l0
,
10045 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10050 kvm_release_page_clean(page
);
10055 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10056 struct vmcs12
*vmcs12
)
10058 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10059 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10060 !nested_cpu_has_vid(vmcs12
) &&
10061 !nested_cpu_has_posted_intr(vmcs12
))
10065 * If virtualize x2apic mode is enabled,
10066 * virtualize apic access must be disabled.
10068 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10069 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10073 * If virtual interrupt delivery is enabled,
10074 * we must exit on external interrupts.
10076 if (nested_cpu_has_vid(vmcs12
) &&
10077 !nested_exit_on_intr(vcpu
))
10081 * bits 15:8 should be zero in posted_intr_nv,
10082 * the descriptor address has been already checked
10083 * in nested_get_vmcs12_pages.
10085 if (nested_cpu_has_posted_intr(vmcs12
) &&
10086 (!nested_cpu_has_vid(vmcs12
) ||
10087 !nested_exit_intr_ack_set(vcpu
) ||
10088 vmcs12
->posted_intr_nv
& 0xff00))
10091 /* tpr shadow is needed by all apicv features. */
10092 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10098 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10099 unsigned long count_field
,
10100 unsigned long addr_field
)
10105 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10106 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10112 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10113 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10114 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10115 pr_debug_ratelimited(
10116 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10117 addr_field
, maxphyaddr
, count
, addr
);
10123 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10124 struct vmcs12
*vmcs12
)
10126 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10127 vmcs12
->vm_exit_msr_store_count
== 0 &&
10128 vmcs12
->vm_entry_msr_load_count
== 0)
10129 return 0; /* Fast path */
10130 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10131 VM_EXIT_MSR_LOAD_ADDR
) ||
10132 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10133 VM_EXIT_MSR_STORE_ADDR
) ||
10134 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10135 VM_ENTRY_MSR_LOAD_ADDR
))
10140 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10141 struct vmcs12
*vmcs12
)
10143 u64 address
= vmcs12
->pml_address
;
10144 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10146 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10147 if (!nested_cpu_has_ept(vmcs12
) ||
10148 !IS_ALIGNED(address
, 4096) ||
10149 address
>> maxphyaddr
)
10156 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10157 struct vmx_msr_entry
*e
)
10159 /* x2APIC MSR accesses are not allowed */
10160 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10162 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10163 e
->index
== MSR_IA32_UCODE_REV
)
10165 if (e
->reserved
!= 0)
10170 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10171 struct vmx_msr_entry
*e
)
10173 if (e
->index
== MSR_FS_BASE
||
10174 e
->index
== MSR_GS_BASE
||
10175 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10176 nested_vmx_msr_check_common(vcpu
, e
))
10181 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10182 struct vmx_msr_entry
*e
)
10184 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10185 nested_vmx_msr_check_common(vcpu
, e
))
10191 * Load guest's/host's msr at nested entry/exit.
10192 * return 0 for success, entry index for failure.
10194 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10197 struct vmx_msr_entry e
;
10198 struct msr_data msr
;
10200 msr
.host_initiated
= false;
10201 for (i
= 0; i
< count
; i
++) {
10202 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10204 pr_debug_ratelimited(
10205 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10206 __func__
, i
, gpa
+ i
* sizeof(e
));
10209 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10210 pr_debug_ratelimited(
10211 "%s check failed (%u, 0x%x, 0x%x)\n",
10212 __func__
, i
, e
.index
, e
.reserved
);
10215 msr
.index
= e
.index
;
10216 msr
.data
= e
.value
;
10217 if (kvm_set_msr(vcpu
, &msr
)) {
10218 pr_debug_ratelimited(
10219 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10220 __func__
, i
, e
.index
, e
.value
);
10229 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10232 struct vmx_msr_entry e
;
10234 for (i
= 0; i
< count
; i
++) {
10235 struct msr_data msr_info
;
10236 if (kvm_vcpu_read_guest(vcpu
,
10237 gpa
+ i
* sizeof(e
),
10238 &e
, 2 * sizeof(u32
))) {
10239 pr_debug_ratelimited(
10240 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10241 __func__
, i
, gpa
+ i
* sizeof(e
));
10244 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10245 pr_debug_ratelimited(
10246 "%s check failed (%u, 0x%x, 0x%x)\n",
10247 __func__
, i
, e
.index
, e
.reserved
);
10250 msr_info
.host_initiated
= false;
10251 msr_info
.index
= e
.index
;
10252 if (kvm_get_msr(vcpu
, &msr_info
)) {
10253 pr_debug_ratelimited(
10254 "%s cannot read MSR (%u, 0x%x)\n",
10255 __func__
, i
, e
.index
);
10258 if (kvm_vcpu_write_guest(vcpu
,
10259 gpa
+ i
* sizeof(e
) +
10260 offsetof(struct vmx_msr_entry
, value
),
10261 &msr_info
.data
, sizeof(msr_info
.data
))) {
10262 pr_debug_ratelimited(
10263 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10264 __func__
, i
, e
.index
, msr_info
.data
);
10271 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10273 unsigned long invalid_mask
;
10275 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10276 return (val
& invalid_mask
) == 0;
10280 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10281 * emulating VM entry into a guest with EPT enabled.
10282 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10283 * is assigned to entry_failure_code on failure.
10285 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10286 u32
*entry_failure_code
)
10288 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10289 if (!nested_cr3_valid(vcpu
, cr3
)) {
10290 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10295 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10296 * must not be dereferenced.
10298 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10300 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10301 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10306 vcpu
->arch
.cr3
= cr3
;
10307 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10310 kvm_mmu_reset_context(vcpu
);
10315 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10316 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10317 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10318 * guest in a way that will both be appropriate to L1's requests, and our
10319 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10320 * function also has additional necessary side-effects, like setting various
10321 * vcpu->arch fields.
10322 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10323 * is assigned to entry_failure_code on failure.
10325 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10326 bool from_vmentry
, u32
*entry_failure_code
)
10328 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10329 u32 exec_control
, vmcs12_exec_ctrl
;
10331 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10332 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10333 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10334 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10335 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10336 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10337 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10338 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10339 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10340 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10341 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10342 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10343 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10344 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10345 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10346 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10347 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10348 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10349 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10350 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10351 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10352 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10353 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10354 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10355 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10356 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10357 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10358 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10359 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10360 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10361 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10362 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10363 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10364 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10365 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10366 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10368 if (from_vmentry
&&
10369 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10370 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10371 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10373 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10374 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10376 if (from_vmentry
) {
10377 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10378 vmcs12
->vm_entry_intr_info_field
);
10379 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10380 vmcs12
->vm_entry_exception_error_code
);
10381 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10382 vmcs12
->vm_entry_instruction_len
);
10383 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10384 vmcs12
->guest_interruptibility_info
);
10385 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10386 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10388 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10390 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10391 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10392 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10393 vmcs12
->guest_pending_dbg_exceptions
);
10394 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10395 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10397 if (nested_cpu_has_xsaves(vmcs12
))
10398 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10399 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10401 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10403 /* Preemption timer setting is only taken from vmcs01. */
10404 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10405 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10406 if (vmx
->hv_deadline_tsc
== -1)
10407 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10409 /* Posted interrupts setting is only taken from vmcs12. */
10410 if (nested_cpu_has_posted_intr(vmcs12
)) {
10411 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10412 vmx
->nested
.pi_pending
= false;
10413 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10415 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10418 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10420 vmx
->nested
.preemption_timer_expired
= false;
10421 if (nested_cpu_has_preemption_timer(vmcs12
))
10422 vmx_start_preemption_timer(vcpu
);
10425 * Whether page-faults are trapped is determined by a combination of
10426 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10427 * If enable_ept, L0 doesn't care about page faults and we should
10428 * set all of these to L1's desires. However, if !enable_ept, L0 does
10429 * care about (at least some) page faults, and because it is not easy
10430 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10431 * to exit on each and every L2 page fault. This is done by setting
10432 * MASK=MATCH=0 and (see below) EB.PF=1.
10433 * Note that below we don't need special code to set EB.PF beyond the
10434 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10435 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10436 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10438 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10439 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10440 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10441 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10443 if (cpu_has_secondary_exec_ctrls()) {
10444 exec_control
= vmx
->secondary_exec_control
;
10446 /* Take the following fields only from vmcs12 */
10447 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10448 SECONDARY_EXEC_ENABLE_INVPCID
|
10449 SECONDARY_EXEC_RDTSCP
|
10450 SECONDARY_EXEC_XSAVES
|
10451 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10452 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10453 SECONDARY_EXEC_ENABLE_VMFUNC
);
10454 if (nested_cpu_has(vmcs12
,
10455 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10456 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10457 ~SECONDARY_EXEC_ENABLE_PML
;
10458 exec_control
|= vmcs12_exec_ctrl
;
10461 /* All VMFUNCs are currently emulated through L0 vmexits. */
10462 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10463 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10465 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10466 vmcs_write64(EOI_EXIT_BITMAP0
,
10467 vmcs12
->eoi_exit_bitmap0
);
10468 vmcs_write64(EOI_EXIT_BITMAP1
,
10469 vmcs12
->eoi_exit_bitmap1
);
10470 vmcs_write64(EOI_EXIT_BITMAP2
,
10471 vmcs12
->eoi_exit_bitmap2
);
10472 vmcs_write64(EOI_EXIT_BITMAP3
,
10473 vmcs12
->eoi_exit_bitmap3
);
10474 vmcs_write16(GUEST_INTR_STATUS
,
10475 vmcs12
->guest_intr_status
);
10479 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10480 * nested_get_vmcs12_pages will either fix it up or
10481 * remove the VM execution control.
10483 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10484 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10486 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10491 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10492 * Some constant fields are set here by vmx_set_constant_host_state().
10493 * Other fields are different per CPU, and will be set later when
10494 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10496 vmx_set_constant_host_state(vmx
);
10499 * Set the MSR load/store lists to match L0's settings.
10501 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10502 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10503 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10504 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10505 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10508 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10509 * entry, but only if the current (host) sp changed from the value
10510 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10511 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10512 * here we just force the write to happen on entry.
10516 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10517 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10518 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10519 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10520 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10523 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10524 * nested_get_vmcs12_pages can't fix it up, the illegal value
10525 * will result in a VM entry failure.
10527 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10528 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10529 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10533 * Merging of IO bitmap not currently supported.
10534 * Rather, exit every time.
10536 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10537 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10539 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10541 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10542 * bitwise-or of what L1 wants to trap for L2, and what we want to
10543 * trap. Note that CR0.TS also needs updating - we do this later.
10545 update_exception_bitmap(vcpu
);
10546 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10547 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10549 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10550 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10551 * bits are further modified by vmx_set_efer() below.
10553 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10555 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10556 * emulated by vmx_set_efer(), below.
10558 vm_entry_controls_init(vmx
,
10559 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10560 ~VM_ENTRY_IA32E_MODE
) |
10561 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10563 if (from_vmentry
&&
10564 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10565 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10566 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10567 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10568 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10571 set_cr4_guest_host_mask(vmx
);
10573 if (from_vmentry
&&
10574 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10575 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10577 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10578 vmcs_write64(TSC_OFFSET
,
10579 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10581 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10582 if (kvm_has_tsc_control
)
10583 decache_tsc_multiplier(vmx
);
10587 * There is no direct mapping between vpid02 and vpid12, the
10588 * vpid02 is per-vCPU for L0 and reused while the value of
10589 * vpid12 is changed w/ one invvpid during nested vmentry.
10590 * The vpid12 is allocated by L1 for L2, so it will not
10591 * influence global bitmap(for vpid01 and vpid02 allocation)
10592 * even if spawn a lot of nested vCPUs.
10594 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10595 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10596 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10597 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10598 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10601 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10602 vmx_flush_tlb(vcpu
);
10609 * Conceptually we want to copy the PML address and index from
10610 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10611 * since we always flush the log on each vmexit, this happens
10612 * to be equivalent to simply resetting the fields in vmcs02.
10614 ASSERT(vmx
->pml_pg
);
10615 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10616 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10619 if (nested_cpu_has_ept(vmcs12
)) {
10620 if (nested_ept_init_mmu_context(vcpu
)) {
10621 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10624 } else if (nested_cpu_has2(vmcs12
,
10625 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10626 vmx_flush_tlb_ept_only(vcpu
);
10630 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10631 * bits which we consider mandatory enabled.
10632 * The CR0_READ_SHADOW is what L2 should have expected to read given
10633 * the specifications by L1; It's not enough to take
10634 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10635 * have more bits than L1 expected.
10637 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10638 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10640 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10641 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10643 if (from_vmentry
&&
10644 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10645 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10646 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10647 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10649 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10650 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10651 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10653 /* Shadow page tables on either EPT or shadow page tables. */
10654 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10655 entry_failure_code
))
10659 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10662 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10665 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10666 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10667 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10668 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10671 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10672 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10676 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10678 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10680 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10681 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10682 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10684 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10685 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10687 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10688 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10690 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10691 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10693 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10694 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10696 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10697 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10699 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10700 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10701 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10702 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10703 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10704 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10705 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10706 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10707 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10708 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10709 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10710 vmx
->nested
.nested_vmx_exit_ctls_low
,
10711 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10712 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10713 vmx
->nested
.nested_vmx_entry_ctls_low
,
10714 vmx
->nested
.nested_vmx_entry_ctls_high
))
10715 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10717 if (nested_cpu_has_vmfunc(vmcs12
)) {
10718 if (vmcs12
->vm_function_control
&
10719 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10720 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10722 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10723 if (!nested_cpu_has_ept(vmcs12
) ||
10724 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10725 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10729 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10730 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10732 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10733 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10734 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10735 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10740 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10745 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10747 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10748 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10751 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10752 vmcs12
->vmcs_link_pointer
!= -1ull) {
10753 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10758 * If the load IA32_EFER VM-entry control is 1, the following checks
10759 * are performed on the field for the IA32_EFER MSR:
10760 * - Bits reserved in the IA32_EFER MSR must be 0.
10761 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10762 * the IA-32e mode guest VM-exit control. It must also be identical
10763 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10766 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10767 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10768 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10769 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10770 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10771 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10772 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10777 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10778 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10779 * the values of the LMA and LME bits in the field must each be that of
10780 * the host address-space size VM-exit control.
10782 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10783 ia32e
= (vmcs12
->vm_exit_controls
&
10784 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10785 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10786 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10787 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10794 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10796 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10797 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10798 struct loaded_vmcs
*vmcs02
;
10802 vmcs02
= nested_get_current_vmcs02(vmx
);
10806 enter_guest_mode(vcpu
);
10808 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10809 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10811 vmx_switch_vmcs(vcpu
, vmcs02
);
10812 vmx_segment_cache_clear(vmx
);
10814 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10815 leave_guest_mode(vcpu
);
10816 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10817 nested_vmx_entry_failure(vcpu
, vmcs12
,
10818 EXIT_REASON_INVALID_STATE
, exit_qual
);
10822 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10824 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10825 vmcs12
->vm_entry_msr_load_addr
,
10826 vmcs12
->vm_entry_msr_load_count
);
10827 if (msr_entry_idx
) {
10828 leave_guest_mode(vcpu
);
10829 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10830 nested_vmx_entry_failure(vcpu
, vmcs12
,
10831 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10836 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10837 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10838 * returned as far as L1 is concerned. It will only return (and set
10839 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10845 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10846 * for running an L2 nested guest.
10848 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10850 struct vmcs12
*vmcs12
;
10851 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10852 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10856 if (!nested_vmx_check_permission(vcpu
))
10859 if (!nested_vmx_check_vmcs12(vcpu
))
10862 vmcs12
= get_vmcs12(vcpu
);
10864 if (enable_shadow_vmcs
)
10865 copy_shadow_to_vmcs12(vmx
);
10868 * The nested entry process starts with enforcing various prerequisites
10869 * on vmcs12 as required by the Intel SDM, and act appropriately when
10870 * they fail: As the SDM explains, some conditions should cause the
10871 * instruction to fail, while others will cause the instruction to seem
10872 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10873 * To speed up the normal (success) code path, we should avoid checking
10874 * for misconfigurations which will anyway be caught by the processor
10875 * when using the merged vmcs02.
10877 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10878 nested_vmx_failValid(vcpu
,
10879 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10883 if (vmcs12
->launch_state
== launch
) {
10884 nested_vmx_failValid(vcpu
,
10885 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10886 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10890 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10892 nested_vmx_failValid(vcpu
, ret
);
10897 * After this point, the trap flag no longer triggers a singlestep trap
10898 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10899 * This is not 100% correct; for performance reasons, we delegate most
10900 * of the checks on host state to the processor. If those fail,
10901 * the singlestep trap is missed.
10903 skip_emulated_instruction(vcpu
);
10905 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10907 nested_vmx_entry_failure(vcpu
, vmcs12
,
10908 EXIT_REASON_INVALID_STATE
, exit_qual
);
10913 * We're finally done with prerequisite checking, and can start with
10914 * the nested entry.
10917 ret
= enter_vmx_non_root_mode(vcpu
, true);
10921 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10922 return kvm_vcpu_halt(vcpu
);
10924 vmx
->nested
.nested_run_pending
= 1;
10929 return kvm_skip_emulated_instruction(vcpu
);
10933 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10934 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10935 * This function returns the new value we should put in vmcs12.guest_cr0.
10936 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10937 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10938 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10939 * didn't trap the bit, because if L1 did, so would L0).
10940 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10941 * been modified by L2, and L1 knows it. So just leave the old value of
10942 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10943 * isn't relevant, because if L0 traps this bit it can set it to anything.
10944 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10945 * changed these bits, and therefore they need to be updated, but L0
10946 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10947 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10949 static inline unsigned long
10950 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10953 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10954 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10955 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10956 vcpu
->arch
.cr0_guest_owned_bits
));
10959 static inline unsigned long
10960 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10963 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10964 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10965 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10966 vcpu
->arch
.cr4_guest_owned_bits
));
10969 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10970 struct vmcs12
*vmcs12
)
10975 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10976 nr
= vcpu
->arch
.exception
.nr
;
10977 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10979 if (kvm_exception_is_soft(nr
)) {
10980 vmcs12
->vm_exit_instruction_len
=
10981 vcpu
->arch
.event_exit_inst_len
;
10982 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10984 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10986 if (vcpu
->arch
.exception
.has_error_code
) {
10987 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10988 vmcs12
->idt_vectoring_error_code
=
10989 vcpu
->arch
.exception
.error_code
;
10992 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10993 } else if (vcpu
->arch
.nmi_injected
) {
10994 vmcs12
->idt_vectoring_info_field
=
10995 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10996 } else if (vcpu
->arch
.interrupt
.pending
) {
10997 nr
= vcpu
->arch
.interrupt
.nr
;
10998 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11000 if (vcpu
->arch
.interrupt
.soft
) {
11001 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11002 vmcs12
->vm_entry_instruction_len
=
11003 vcpu
->arch
.event_exit_inst_len
;
11005 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11007 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11011 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11013 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11015 if (vcpu
->arch
.exception
.pending
||
11016 vcpu
->arch
.nmi_injected
||
11017 vcpu
->arch
.interrupt
.pending
)
11020 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11021 vmx
->nested
.preemption_timer_expired
) {
11022 if (vmx
->nested
.nested_run_pending
)
11024 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11028 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11029 if (vmx
->nested
.nested_run_pending
)
11031 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11032 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11033 INTR_INFO_VALID_MASK
, 0);
11035 * The NMI-triggered VM exit counts as injection:
11036 * clear this one and block further NMIs.
11038 vcpu
->arch
.nmi_pending
= 0;
11039 vmx_set_nmi_mask(vcpu
, true);
11043 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11044 nested_exit_on_intr(vcpu
)) {
11045 if (vmx
->nested
.nested_run_pending
)
11047 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11051 vmx_complete_nested_posted_interrupt(vcpu
);
11055 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11057 ktime_t remaining
=
11058 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11061 if (ktime_to_ns(remaining
) <= 0)
11064 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11065 do_div(value
, 1000000);
11066 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11070 * Update the guest state fields of vmcs12 to reflect changes that
11071 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11072 * VM-entry controls is also updated, since this is really a guest
11075 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11077 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11078 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11080 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11081 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11082 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11084 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11085 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11086 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11087 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11088 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11089 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11090 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11091 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11092 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11093 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11094 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11095 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11096 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11097 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11098 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11099 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11100 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11101 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11102 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11103 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11104 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11105 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11106 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11107 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11108 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11109 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11110 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11111 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11112 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11113 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11114 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11115 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11116 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11117 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11118 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11119 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11121 vmcs12
->guest_interruptibility_info
=
11122 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11123 vmcs12
->guest_pending_dbg_exceptions
=
11124 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11125 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11126 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11128 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11130 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11131 if (vmcs12
->vm_exit_controls
&
11132 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11133 vmcs12
->vmx_preemption_timer_value
=
11134 vmx_get_preemption_timer_value(vcpu
);
11135 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11139 * In some cases (usually, nested EPT), L2 is allowed to change its
11140 * own CR3 without exiting. If it has changed it, we must keep it.
11141 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11142 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11144 * Additionally, restore L2's PDPTR to vmcs12.
11147 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11148 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11149 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11150 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11151 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11154 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11156 if (nested_cpu_has_vid(vmcs12
))
11157 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11159 vmcs12
->vm_entry_controls
=
11160 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11161 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11163 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11164 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11165 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11168 /* TODO: These cannot have changed unless we have MSR bitmaps and
11169 * the relevant bit asks not to trap the change */
11170 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11171 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11172 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11173 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11174 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11175 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11176 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11177 if (kvm_mpx_supported())
11178 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11182 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11183 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11184 * and this function updates it to reflect the changes to the guest state while
11185 * L2 was running (and perhaps made some exits which were handled directly by L0
11186 * without going back to L1), and to reflect the exit reason.
11187 * Note that we do not have to copy here all VMCS fields, just those that
11188 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11189 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11190 * which already writes to vmcs12 directly.
11192 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11193 u32 exit_reason
, u32 exit_intr_info
,
11194 unsigned long exit_qualification
)
11196 /* update guest state fields: */
11197 sync_vmcs12(vcpu
, vmcs12
);
11199 /* update exit information fields: */
11201 vmcs12
->vm_exit_reason
= exit_reason
;
11202 vmcs12
->exit_qualification
= exit_qualification
;
11203 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11205 vmcs12
->idt_vectoring_info_field
= 0;
11206 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11207 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11209 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11210 vmcs12
->launch_state
= 1;
11212 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11213 * instead of reading the real value. */
11214 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11217 * Transfer the event that L0 or L1 may wanted to inject into
11218 * L2 to IDT_VECTORING_INFO_FIELD.
11220 vmcs12_save_pending_event(vcpu
, vmcs12
);
11224 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11225 * preserved above and would only end up incorrectly in L1.
11227 vcpu
->arch
.nmi_injected
= false;
11228 kvm_clear_exception_queue(vcpu
);
11229 kvm_clear_interrupt_queue(vcpu
);
11233 * A part of what we need to when the nested L2 guest exits and we want to
11234 * run its L1 parent, is to reset L1's guest state to the host state specified
11236 * This function is to be called not only on normal nested exit, but also on
11237 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11238 * Failures During or After Loading Guest State").
11239 * This function should be called when the active VMCS is L1's (vmcs01).
11241 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11242 struct vmcs12
*vmcs12
)
11244 struct kvm_segment seg
;
11245 u32 entry_failure_code
;
11247 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11248 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11249 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11250 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11252 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11253 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11255 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11256 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11257 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11259 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11260 * actually changed, because vmx_set_cr0 refers to efer set above.
11262 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11263 * (KVM doesn't change it);
11265 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11266 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11268 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11269 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11270 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
11272 nested_ept_uninit_mmu_context(vcpu
);
11275 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11276 * couldn't have changed.
11278 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11279 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11282 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11286 * Trivially support vpid by letting L2s share their parent
11287 * L1's vpid. TODO: move to a more elaborate solution, giving
11288 * each L2 its own vpid and exposing the vpid feature to L1.
11290 vmx_flush_tlb(vcpu
);
11292 /* Restore posted intr vector. */
11293 if (nested_cpu_has_posted_intr(vmcs12
))
11294 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11296 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11297 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11298 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11299 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11300 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11302 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11303 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11304 vmcs_write64(GUEST_BNDCFGS
, 0);
11306 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11307 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11308 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11310 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11311 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11312 vmcs12
->host_ia32_perf_global_ctrl
);
11314 /* Set L1 segment info according to Intel SDM
11315 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11316 seg
= (struct kvm_segment
) {
11318 .limit
= 0xFFFFFFFF,
11319 .selector
= vmcs12
->host_cs_selector
,
11325 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11329 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11330 seg
= (struct kvm_segment
) {
11332 .limit
= 0xFFFFFFFF,
11339 seg
.selector
= vmcs12
->host_ds_selector
;
11340 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11341 seg
.selector
= vmcs12
->host_es_selector
;
11342 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11343 seg
.selector
= vmcs12
->host_ss_selector
;
11344 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11345 seg
.selector
= vmcs12
->host_fs_selector
;
11346 seg
.base
= vmcs12
->host_fs_base
;
11347 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11348 seg
.selector
= vmcs12
->host_gs_selector
;
11349 seg
.base
= vmcs12
->host_gs_base
;
11350 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11351 seg
= (struct kvm_segment
) {
11352 .base
= vmcs12
->host_tr_base
,
11354 .selector
= vmcs12
->host_tr_selector
,
11358 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11360 kvm_set_dr(vcpu
, 7, 0x400);
11361 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11363 if (cpu_has_vmx_msr_bitmap())
11364 vmx_set_msr_bitmap(vcpu
);
11366 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11367 vmcs12
->vm_exit_msr_load_count
))
11368 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11372 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11373 * and modify vmcs12 to make it see what it would expect to see there if
11374 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11376 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11377 u32 exit_intr_info
,
11378 unsigned long exit_qualification
)
11380 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11381 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11382 u32 vm_inst_error
= 0;
11384 /* trying to cancel vmlaunch/vmresume is a bug */
11385 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11387 leave_guest_mode(vcpu
);
11388 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11389 exit_qualification
);
11391 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11392 vmcs12
->vm_exit_msr_store_count
))
11393 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11395 if (unlikely(vmx
->fail
))
11396 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11398 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11401 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11402 * the VM-exit interrupt information (valid interrupt) is always set to
11403 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11404 * kvm_cpu_has_interrupt(). See the commit message for details.
11406 if (nested_exit_intr_ack_set(vcpu
) &&
11407 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11408 kvm_cpu_has_interrupt(vcpu
)) {
11409 int irq
= kvm_cpu_get_interrupt(vcpu
);
11411 vmcs12
->vm_exit_intr_info
= irq
|
11412 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11415 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11416 vmcs12
->exit_qualification
,
11417 vmcs12
->idt_vectoring_info_field
,
11418 vmcs12
->vm_exit_intr_info
,
11419 vmcs12
->vm_exit_intr_error_code
,
11422 vm_entry_controls_reset_shadow(vmx
);
11423 vm_exit_controls_reset_shadow(vmx
);
11424 vmx_segment_cache_clear(vmx
);
11426 /* if no vmcs02 cache requested, remove the one we used */
11427 if (VMCS02_POOL_SIZE
== 0)
11428 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11430 load_vmcs12_host_state(vcpu
, vmcs12
);
11432 /* Update any VMCS fields that might have changed while L2 ran */
11433 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11434 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11435 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11436 if (vmx
->hv_deadline_tsc
== -1)
11437 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11438 PIN_BASED_VMX_PREEMPTION_TIMER
);
11440 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11441 PIN_BASED_VMX_PREEMPTION_TIMER
);
11442 if (kvm_has_tsc_control
)
11443 decache_tsc_multiplier(vmx
);
11445 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11446 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11447 vmx_set_virtual_x2apic_mode(vcpu
,
11448 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11449 } else if (!nested_cpu_has_ept(vmcs12
) &&
11450 nested_cpu_has2(vmcs12
,
11451 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11452 vmx_flush_tlb_ept_only(vcpu
);
11455 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11458 /* Unpin physical memory we referred to in vmcs02 */
11459 if (vmx
->nested
.apic_access_page
) {
11460 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11461 vmx
->nested
.apic_access_page
= NULL
;
11463 if (vmx
->nested
.virtual_apic_page
) {
11464 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11465 vmx
->nested
.virtual_apic_page
= NULL
;
11467 if (vmx
->nested
.pi_desc_page
) {
11468 kunmap(vmx
->nested
.pi_desc_page
);
11469 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11470 vmx
->nested
.pi_desc_page
= NULL
;
11471 vmx
->nested
.pi_desc
= NULL
;
11475 * We are now running in L2, mmu_notifier will force to reload the
11476 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11478 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11481 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11482 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11483 * success or failure flag accordingly.
11485 if (unlikely(vmx
->fail
)) {
11487 nested_vmx_failValid(vcpu
, vm_inst_error
);
11489 nested_vmx_succeed(vcpu
);
11490 if (enable_shadow_vmcs
)
11491 vmx
->nested
.sync_shadow_vmcs
= true;
11493 /* in case we halted in L2 */
11494 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11498 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11500 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11502 if (is_guest_mode(vcpu
)) {
11503 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11504 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11506 free_nested(to_vmx(vcpu
));
11510 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11511 * 23.7 "VM-entry failures during or after loading guest state" (this also
11512 * lists the acceptable exit-reason and exit-qualification parameters).
11513 * It should only be called before L2 actually succeeded to run, and when
11514 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11516 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11517 struct vmcs12
*vmcs12
,
11518 u32 reason
, unsigned long qualification
)
11520 load_vmcs12_host_state(vcpu
, vmcs12
);
11521 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11522 vmcs12
->exit_qualification
= qualification
;
11523 nested_vmx_succeed(vcpu
);
11524 if (enable_shadow_vmcs
)
11525 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11528 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11529 struct x86_instruction_info
*info
,
11530 enum x86_intercept_stage stage
)
11532 return X86EMUL_CONTINUE
;
11535 #ifdef CONFIG_X86_64
11536 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11537 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11538 u64 divisor
, u64
*result
)
11540 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11542 /* To avoid the overflow on divq */
11543 if (high
>= divisor
)
11546 /* Low hold the result, high hold rem which is discarded */
11547 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11548 "rm" (divisor
), "0" (low
), "1" (high
));
11554 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11556 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11557 u64 tscl
= rdtsc();
11558 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11559 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11561 /* Convert to host delta tsc if tsc scaling is enabled */
11562 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11563 u64_shl_div_u64(delta_tsc
,
11564 kvm_tsc_scaling_ratio_frac_bits
,
11565 vcpu
->arch
.tsc_scaling_ratio
,
11570 * If the delta tsc can't fit in the 32 bit after the multi shift,
11571 * we can't use the preemption timer.
11572 * It's possible that it fits on later vmentries, but checking
11573 * on every vmentry is costly so we just use an hrtimer.
11575 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11578 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11579 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11580 PIN_BASED_VMX_PREEMPTION_TIMER
);
11582 return delta_tsc
== 0;
11585 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11588 vmx
->hv_deadline_tsc
= -1;
11589 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11590 PIN_BASED_VMX_PREEMPTION_TIMER
);
11594 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11597 shrink_ple_window(vcpu
);
11600 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11601 struct kvm_memory_slot
*slot
)
11603 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11604 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11607 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11608 struct kvm_memory_slot
*slot
)
11610 kvm_mmu_slot_set_dirty(kvm
, slot
);
11613 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11615 kvm_flush_pml_buffers(kvm
);
11618 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11620 struct vmcs12
*vmcs12
;
11621 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11623 struct page
*page
= NULL
;
11626 if (is_guest_mode(vcpu
)) {
11627 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11630 * Check if PML is enabled for the nested guest.
11631 * Whether eptp bit 6 is set is already checked
11632 * as part of A/D emulation.
11634 vmcs12
= get_vmcs12(vcpu
);
11635 if (!nested_cpu_has_pml(vmcs12
))
11638 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11639 vmx
->nested
.pml_full
= true;
11643 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11645 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11646 if (is_error_page(page
))
11649 pml_address
= kmap(page
);
11650 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11652 kvm_release_page_clean(page
);
11658 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11659 struct kvm_memory_slot
*memslot
,
11660 gfn_t offset
, unsigned long mask
)
11662 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11666 * This routine does the following things for vCPU which is going
11667 * to be blocked if VT-d PI is enabled.
11668 * - Store the vCPU to the wakeup list, so when interrupts happen
11669 * we can find the right vCPU to wake up.
11670 * - Change the Posted-interrupt descriptor as below:
11671 * 'NDST' <-- vcpu->pre_pcpu
11672 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11673 * - If 'ON' is set during this process, which means at least one
11674 * interrupt is posted for this vCPU, we cannot block it, in
11675 * this case, return 1, otherwise, return 0.
11678 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11680 unsigned long flags
;
11682 struct pi_desc old
, new;
11683 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11685 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11686 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11687 !kvm_vcpu_apicv_active(vcpu
))
11690 vcpu
->pre_pcpu
= vcpu
->cpu
;
11691 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11692 vcpu
->pre_pcpu
), flags
);
11693 list_add_tail(&vcpu
->blocked_vcpu_list
,
11694 &per_cpu(blocked_vcpu_on_cpu
,
11696 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11697 vcpu
->pre_pcpu
), flags
);
11700 old
.control
= new.control
= pi_desc
->control
;
11703 * We should not block the vCPU if
11704 * an interrupt is posted for it.
11706 if (pi_test_on(pi_desc
) == 1) {
11707 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11708 vcpu
->pre_pcpu
), flags
);
11709 list_del(&vcpu
->blocked_vcpu_list
);
11710 spin_unlock_irqrestore(
11711 &per_cpu(blocked_vcpu_on_cpu_lock
,
11712 vcpu
->pre_pcpu
), flags
);
11713 vcpu
->pre_pcpu
= -1;
11718 WARN((pi_desc
->sn
== 1),
11719 "Warning: SN field of posted-interrupts "
11720 "is set before blocking\n");
11723 * Since vCPU can be preempted during this process,
11724 * vcpu->cpu could be different with pre_pcpu, we
11725 * need to set pre_pcpu as the destination of wakeup
11726 * notification event, then we can find the right vCPU
11727 * to wakeup in wakeup handler if interrupts happen
11728 * when the vCPU is in blocked state.
11730 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11732 if (x2apic_enabled())
11735 new.ndst
= (dest
<< 8) & 0xFF00;
11737 /* set 'NV' to 'wakeup vector' */
11738 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11739 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11740 new.control
) != old
.control
);
11745 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11747 if (pi_pre_block(vcpu
))
11750 if (kvm_lapic_hv_timer_in_use(vcpu
))
11751 kvm_lapic_switch_to_sw_timer(vcpu
);
11756 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11758 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11759 struct pi_desc old
, new;
11761 unsigned long flags
;
11763 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11764 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11765 !kvm_vcpu_apicv_active(vcpu
))
11769 old
.control
= new.control
= pi_desc
->control
;
11771 dest
= cpu_physical_id(vcpu
->cpu
);
11773 if (x2apic_enabled())
11776 new.ndst
= (dest
<< 8) & 0xFF00;
11778 /* Allow posting non-urgent interrupts */
11781 /* set 'NV' to 'notification vector' */
11782 new.nv
= POSTED_INTR_VECTOR
;
11783 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11784 new.control
) != old
.control
);
11786 if(vcpu
->pre_pcpu
!= -1) {
11788 &per_cpu(blocked_vcpu_on_cpu_lock
,
11789 vcpu
->pre_pcpu
), flags
);
11790 list_del(&vcpu
->blocked_vcpu_list
);
11791 spin_unlock_irqrestore(
11792 &per_cpu(blocked_vcpu_on_cpu_lock
,
11793 vcpu
->pre_pcpu
), flags
);
11794 vcpu
->pre_pcpu
= -1;
11798 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11800 if (kvm_x86_ops
->set_hv_timer
)
11801 kvm_lapic_switch_to_hv_timer(vcpu
);
11803 pi_post_block(vcpu
);
11807 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11810 * @host_irq: host irq of the interrupt
11811 * @guest_irq: gsi of the interrupt
11812 * @set: set or unset PI
11813 * returns 0 on success, < 0 on failure
11815 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11816 uint32_t guest_irq
, bool set
)
11818 struct kvm_kernel_irq_routing_entry
*e
;
11819 struct kvm_irq_routing_table
*irq_rt
;
11820 struct kvm_lapic_irq irq
;
11821 struct kvm_vcpu
*vcpu
;
11822 struct vcpu_data vcpu_info
;
11823 int idx
, ret
= -EINVAL
;
11825 if (!kvm_arch_has_assigned_device(kvm
) ||
11826 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11827 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11830 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11831 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11832 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11834 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11835 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11838 * VT-d PI cannot support posting multicast/broadcast
11839 * interrupts to a vCPU, we still use interrupt remapping
11840 * for these kind of interrupts.
11842 * For lowest-priority interrupts, we only support
11843 * those with single CPU as the destination, e.g. user
11844 * configures the interrupts via /proc/irq or uses
11845 * irqbalance to make the interrupts single-CPU.
11847 * We will support full lowest-priority interrupt later.
11850 kvm_set_msi_irq(kvm
, e
, &irq
);
11851 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11853 * Make sure the IRTE is in remapped mode if
11854 * we don't handle it in posted mode.
11856 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11859 "failed to back to remapped mode, irq: %u\n",
11867 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11868 vcpu_info
.vector
= irq
.vector
;
11870 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11871 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11874 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11876 /* suppress notification event before unposting */
11877 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11878 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11879 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11883 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11891 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11895 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11897 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11898 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11899 FEATURE_CONTROL_LMCE
;
11901 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11902 ~FEATURE_CONTROL_LMCE
;
11905 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11906 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11907 .disabled_by_bios
= vmx_disabled_by_bios
,
11908 .hardware_setup
= hardware_setup
,
11909 .hardware_unsetup
= hardware_unsetup
,
11910 .check_processor_compatibility
= vmx_check_processor_compat
,
11911 .hardware_enable
= hardware_enable
,
11912 .hardware_disable
= hardware_disable
,
11913 .cpu_has_accelerated_tpr
= report_flexpriority
,
11914 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11916 .vcpu_create
= vmx_create_vcpu
,
11917 .vcpu_free
= vmx_free_vcpu
,
11918 .vcpu_reset
= vmx_vcpu_reset
,
11920 .prepare_guest_switch
= vmx_save_host_state
,
11921 .vcpu_load
= vmx_vcpu_load
,
11922 .vcpu_put
= vmx_vcpu_put
,
11924 .update_bp_intercept
= update_exception_bitmap
,
11925 .get_msr
= vmx_get_msr
,
11926 .set_msr
= vmx_set_msr
,
11927 .get_segment_base
= vmx_get_segment_base
,
11928 .get_segment
= vmx_get_segment
,
11929 .set_segment
= vmx_set_segment
,
11930 .get_cpl
= vmx_get_cpl
,
11931 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11932 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11933 .decache_cr3
= vmx_decache_cr3
,
11934 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11935 .set_cr0
= vmx_set_cr0
,
11936 .set_cr3
= vmx_set_cr3
,
11937 .set_cr4
= vmx_set_cr4
,
11938 .set_efer
= vmx_set_efer
,
11939 .get_idt
= vmx_get_idt
,
11940 .set_idt
= vmx_set_idt
,
11941 .get_gdt
= vmx_get_gdt
,
11942 .set_gdt
= vmx_set_gdt
,
11943 .get_dr6
= vmx_get_dr6
,
11944 .set_dr6
= vmx_set_dr6
,
11945 .set_dr7
= vmx_set_dr7
,
11946 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11947 .cache_reg
= vmx_cache_reg
,
11948 .get_rflags
= vmx_get_rflags
,
11949 .set_rflags
= vmx_set_rflags
,
11951 .get_pkru
= vmx_get_pkru
,
11953 .tlb_flush
= vmx_flush_tlb
,
11955 .run
= vmx_vcpu_run
,
11956 .handle_exit
= vmx_handle_exit
,
11957 .skip_emulated_instruction
= skip_emulated_instruction
,
11958 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11959 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11960 .patch_hypercall
= vmx_patch_hypercall
,
11961 .set_irq
= vmx_inject_irq
,
11962 .set_nmi
= vmx_inject_nmi
,
11963 .queue_exception
= vmx_queue_exception
,
11964 .cancel_injection
= vmx_cancel_injection
,
11965 .interrupt_allowed
= vmx_interrupt_allowed
,
11966 .nmi_allowed
= vmx_nmi_allowed
,
11967 .get_nmi_mask
= vmx_get_nmi_mask
,
11968 .set_nmi_mask
= vmx_set_nmi_mask
,
11969 .enable_nmi_window
= enable_nmi_window
,
11970 .enable_irq_window
= enable_irq_window
,
11971 .update_cr8_intercept
= update_cr8_intercept
,
11972 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11973 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11974 .get_enable_apicv
= vmx_get_enable_apicv
,
11975 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11976 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11977 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11978 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11979 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11980 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11981 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11983 .set_tss_addr
= vmx_set_tss_addr
,
11984 .get_tdp_level
= get_ept_level
,
11985 .get_mt_mask
= vmx_get_mt_mask
,
11987 .get_exit_info
= vmx_get_exit_info
,
11989 .get_lpage_level
= vmx_get_lpage_level
,
11991 .cpuid_update
= vmx_cpuid_update
,
11993 .rdtscp_supported
= vmx_rdtscp_supported
,
11994 .invpcid_supported
= vmx_invpcid_supported
,
11996 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11998 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12000 .write_tsc_offset
= vmx_write_tsc_offset
,
12002 .set_tdp_cr3
= vmx_set_cr3
,
12004 .check_intercept
= vmx_check_intercept
,
12005 .handle_external_intr
= vmx_handle_external_intr
,
12006 .mpx_supported
= vmx_mpx_supported
,
12007 .xsaves_supported
= vmx_xsaves_supported
,
12009 .check_nested_events
= vmx_check_nested_events
,
12011 .sched_in
= vmx_sched_in
,
12013 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12014 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12015 .flush_log_dirty
= vmx_flush_log_dirty
,
12016 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12017 .write_log_dirty
= vmx_write_pml_buffer
,
12019 .pre_block
= vmx_pre_block
,
12020 .post_block
= vmx_post_block
,
12022 .pmu_ops
= &intel_pmu_ops
,
12024 .update_pi_irte
= vmx_update_pi_irte
,
12026 #ifdef CONFIG_X86_64
12027 .set_hv_timer
= vmx_set_hv_timer
,
12028 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12031 .setup_mce
= vmx_setup_mce
,
12034 static int __init
vmx_init(void)
12036 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12037 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12041 #ifdef CONFIG_KEXEC_CORE
12042 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12043 crash_vmclear_local_loaded_vmcss
);
12049 static void __exit
vmx_exit(void)
12051 #ifdef CONFIG_KEXEC_CORE
12052 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12059 module_init(vmx_init
)
12060 module_exit(vmx_exit
)