2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly fasteoi
= 1;
88 module_param(fasteoi
, bool, S_IRUGO
);
90 static bool __read_mostly enable_apicv
= 1;
91 module_param(enable_apicv
, bool, S_IRUGO
);
93 static bool __read_mostly enable_shadow_vmcs
= 1;
94 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested
= 0;
101 module_param(nested
, bool, S_IRUGO
);
103 static u64 __read_mostly host_xss
;
105 static bool __read_mostly enable_pml
= 1;
106 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
108 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
110 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
111 static int __read_mostly cpu_preemption_timer_multi
;
112 static bool __read_mostly enable_preemption_timer
= 1;
114 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
117 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
118 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
119 #define KVM_VM_CR0_ALWAYS_ON \
120 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
121 #define KVM_CR4_GUEST_OWNED_BITS \
122 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
123 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
125 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
126 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
128 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
130 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
133 * Hyper-V requires all of these, so mark them as supported even though
134 * they are just treated the same as all-context.
136 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
137 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
138 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
139 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
140 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
143 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
144 * ple_gap: upper bound on the amount of time between two successive
145 * executions of PAUSE in a loop. Also indicate if ple enabled.
146 * According to test, this time is usually smaller than 128 cycles.
147 * ple_window: upper bound on the amount of time a guest is allowed to execute
148 * in a PAUSE loop. Tests indicate that most spinlocks are held for
149 * less than 2^12 cycles
150 * Time is measured based on a counter that runs at the same rate as the TSC,
151 * refer SDM volume 3b section 21.6.13 & 22.1.3.
153 #define KVM_VMX_DEFAULT_PLE_GAP 128
154 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
155 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
156 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
158 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
160 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
161 module_param(ple_gap
, int, S_IRUGO
);
163 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
164 module_param(ple_window
, int, S_IRUGO
);
166 /* Default doubles per-vcpu window every exit. */
167 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
168 module_param(ple_window_grow
, int, S_IRUGO
);
170 /* Default resets per-vcpu window every exit to ple_window. */
171 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
172 module_param(ple_window_shrink
, int, S_IRUGO
);
174 /* Default is to compute the maximum so we can never overflow. */
175 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
176 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
177 module_param(ple_window_max
, int, S_IRUGO
);
179 extern const ulong vmx_return
;
181 #define NR_AUTOLOAD_MSRS 8
182 #define VMCS02_POOL_SIZE 1
191 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
192 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
193 * loaded on this CPU (so we can clear them if the CPU goes down).
197 struct vmcs
*shadow_vmcs
;
200 struct list_head loaded_vmcss_on_cpu_link
;
203 struct shared_msr_entry
{
210 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
211 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
212 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
213 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
214 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
215 * More than one of these structures may exist, if L1 runs multiple L2 guests.
216 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
217 * underlying hardware which will be used to run L2.
218 * This structure is packed to ensure that its layout is identical across
219 * machines (necessary for live migration).
220 * If there are changes in this struct, VMCS12_REVISION must be changed.
222 typedef u64 natural_width
;
223 struct __packed vmcs12
{
224 /* According to the Intel spec, a VMCS region must start with the
225 * following two fields. Then follow implementation-specific data.
230 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
231 u32 padding
[7]; /* room for future expansion */
236 u64 vm_exit_msr_store_addr
;
237 u64 vm_exit_msr_load_addr
;
238 u64 vm_entry_msr_load_addr
;
240 u64 virtual_apic_page_addr
;
241 u64 apic_access_addr
;
242 u64 posted_intr_desc_addr
;
244 u64 eoi_exit_bitmap0
;
245 u64 eoi_exit_bitmap1
;
246 u64 eoi_exit_bitmap2
;
247 u64 eoi_exit_bitmap3
;
249 u64 guest_physical_address
;
250 u64 vmcs_link_pointer
;
251 u64 guest_ia32_debugctl
;
254 u64 guest_ia32_perf_global_ctrl
;
262 u64 host_ia32_perf_global_ctrl
;
263 u64 padding64
[8]; /* room for future expansion */
265 * To allow migration of L1 (complete with its L2 guests) between
266 * machines of different natural widths (32 or 64 bit), we cannot have
267 * unsigned long fields with no explict size. We use u64 (aliased
268 * natural_width) instead. Luckily, x86 is little-endian.
270 natural_width cr0_guest_host_mask
;
271 natural_width cr4_guest_host_mask
;
272 natural_width cr0_read_shadow
;
273 natural_width cr4_read_shadow
;
274 natural_width cr3_target_value0
;
275 natural_width cr3_target_value1
;
276 natural_width cr3_target_value2
;
277 natural_width cr3_target_value3
;
278 natural_width exit_qualification
;
279 natural_width guest_linear_address
;
280 natural_width guest_cr0
;
281 natural_width guest_cr3
;
282 natural_width guest_cr4
;
283 natural_width guest_es_base
;
284 natural_width guest_cs_base
;
285 natural_width guest_ss_base
;
286 natural_width guest_ds_base
;
287 natural_width guest_fs_base
;
288 natural_width guest_gs_base
;
289 natural_width guest_ldtr_base
;
290 natural_width guest_tr_base
;
291 natural_width guest_gdtr_base
;
292 natural_width guest_idtr_base
;
293 natural_width guest_dr7
;
294 natural_width guest_rsp
;
295 natural_width guest_rip
;
296 natural_width guest_rflags
;
297 natural_width guest_pending_dbg_exceptions
;
298 natural_width guest_sysenter_esp
;
299 natural_width guest_sysenter_eip
;
300 natural_width host_cr0
;
301 natural_width host_cr3
;
302 natural_width host_cr4
;
303 natural_width host_fs_base
;
304 natural_width host_gs_base
;
305 natural_width host_tr_base
;
306 natural_width host_gdtr_base
;
307 natural_width host_idtr_base
;
308 natural_width host_ia32_sysenter_esp
;
309 natural_width host_ia32_sysenter_eip
;
310 natural_width host_rsp
;
311 natural_width host_rip
;
312 natural_width paddingl
[8]; /* room for future expansion */
313 u32 pin_based_vm_exec_control
;
314 u32 cpu_based_vm_exec_control
;
315 u32 exception_bitmap
;
316 u32 page_fault_error_code_mask
;
317 u32 page_fault_error_code_match
;
318 u32 cr3_target_count
;
319 u32 vm_exit_controls
;
320 u32 vm_exit_msr_store_count
;
321 u32 vm_exit_msr_load_count
;
322 u32 vm_entry_controls
;
323 u32 vm_entry_msr_load_count
;
324 u32 vm_entry_intr_info_field
;
325 u32 vm_entry_exception_error_code
;
326 u32 vm_entry_instruction_len
;
328 u32 secondary_vm_exec_control
;
329 u32 vm_instruction_error
;
331 u32 vm_exit_intr_info
;
332 u32 vm_exit_intr_error_code
;
333 u32 idt_vectoring_info_field
;
334 u32 idt_vectoring_error_code
;
335 u32 vm_exit_instruction_len
;
336 u32 vmx_instruction_info
;
343 u32 guest_ldtr_limit
;
345 u32 guest_gdtr_limit
;
346 u32 guest_idtr_limit
;
347 u32 guest_es_ar_bytes
;
348 u32 guest_cs_ar_bytes
;
349 u32 guest_ss_ar_bytes
;
350 u32 guest_ds_ar_bytes
;
351 u32 guest_fs_ar_bytes
;
352 u32 guest_gs_ar_bytes
;
353 u32 guest_ldtr_ar_bytes
;
354 u32 guest_tr_ar_bytes
;
355 u32 guest_interruptibility_info
;
356 u32 guest_activity_state
;
357 u32 guest_sysenter_cs
;
358 u32 host_ia32_sysenter_cs
;
359 u32 vmx_preemption_timer_value
;
360 u32 padding32
[7]; /* room for future expansion */
361 u16 virtual_processor_id
;
363 u16 guest_es_selector
;
364 u16 guest_cs_selector
;
365 u16 guest_ss_selector
;
366 u16 guest_ds_selector
;
367 u16 guest_fs_selector
;
368 u16 guest_gs_selector
;
369 u16 guest_ldtr_selector
;
370 u16 guest_tr_selector
;
371 u16 guest_intr_status
;
372 u16 host_es_selector
;
373 u16 host_cs_selector
;
374 u16 host_ss_selector
;
375 u16 host_ds_selector
;
376 u16 host_fs_selector
;
377 u16 host_gs_selector
;
378 u16 host_tr_selector
;
382 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
383 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
384 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
386 #define VMCS12_REVISION 0x11e57ed0
389 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
390 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
391 * current implementation, 4K are reserved to avoid future complications.
393 #define VMCS12_SIZE 0x1000
395 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
397 struct list_head list
;
399 struct loaded_vmcs vmcs02
;
403 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
404 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
407 /* Has the level1 guest done vmxon? */
411 /* The guest-physical address of the current VMCS L1 keeps for L2 */
413 /* The host-usable pointer to the above */
414 struct page
*current_vmcs12_page
;
415 struct vmcs12
*current_vmcs12
;
417 * Cache of the guest's VMCS, existing outside of guest memory.
418 * Loaded from guest memory during VMPTRLD. Flushed to guest
419 * memory during VMXOFF, VMCLEAR, VMPTRLD.
421 struct vmcs12
*cached_vmcs12
;
423 * Indicates if the shadow vmcs must be updated with the
424 * data hold by vmcs12
426 bool sync_shadow_vmcs
;
428 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
429 struct list_head vmcs02_pool
;
431 bool change_vmcs01_virtual_x2apic_mode
;
432 /* L2 must run next, and mustn't decide to exit to L1. */
433 bool nested_run_pending
;
435 * Guest pages referred to in vmcs02 with host-physical pointers, so
436 * we must keep them pinned while L2 runs.
438 struct page
*apic_access_page
;
439 struct page
*virtual_apic_page
;
440 struct page
*pi_desc_page
;
441 struct pi_desc
*pi_desc
;
445 unsigned long *msr_bitmap
;
447 struct hrtimer preemption_timer
;
448 bool preemption_timer_expired
;
450 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
457 * We only store the "true" versions of the VMX capability MSRs. We
458 * generate the "non-true" versions by setting the must-be-1 bits
459 * according to the SDM.
461 u32 nested_vmx_procbased_ctls_low
;
462 u32 nested_vmx_procbased_ctls_high
;
463 u32 nested_vmx_secondary_ctls_low
;
464 u32 nested_vmx_secondary_ctls_high
;
465 u32 nested_vmx_pinbased_ctls_low
;
466 u32 nested_vmx_pinbased_ctls_high
;
467 u32 nested_vmx_exit_ctls_low
;
468 u32 nested_vmx_exit_ctls_high
;
469 u32 nested_vmx_entry_ctls_low
;
470 u32 nested_vmx_entry_ctls_high
;
471 u32 nested_vmx_misc_low
;
472 u32 nested_vmx_misc_high
;
473 u32 nested_vmx_ept_caps
;
474 u32 nested_vmx_vpid_caps
;
475 u64 nested_vmx_basic
;
476 u64 nested_vmx_cr0_fixed0
;
477 u64 nested_vmx_cr0_fixed1
;
478 u64 nested_vmx_cr4_fixed0
;
479 u64 nested_vmx_cr4_fixed1
;
480 u64 nested_vmx_vmcs_enum
;
483 #define POSTED_INTR_ON 0
484 #define POSTED_INTR_SN 1
486 /* Posted-Interrupt Descriptor */
488 u32 pir
[8]; /* Posted interrupt requested */
491 /* bit 256 - Outstanding Notification */
493 /* bit 257 - Suppress Notification */
495 /* bit 271:258 - Reserved */
497 /* bit 279:272 - Notification Vector */
499 /* bit 287:280 - Reserved */
501 /* bit 319:288 - Notification Destination */
509 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
511 return test_and_set_bit(POSTED_INTR_ON
,
512 (unsigned long *)&pi_desc
->control
);
515 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
517 return test_and_clear_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
523 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
526 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
528 return clear_bit(POSTED_INTR_SN
,
529 (unsigned long *)&pi_desc
->control
);
532 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
534 return set_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
540 clear_bit(POSTED_INTR_ON
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline int pi_test_on(struct pi_desc
*pi_desc
)
546 return test_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_SN
,
553 (unsigned long *)&pi_desc
->control
);
557 struct kvm_vcpu vcpu
;
558 unsigned long host_rsp
;
560 bool nmi_known_unmasked
;
562 u32 idt_vectoring_info
;
564 struct shared_msr_entry
*guest_msrs
;
567 unsigned long host_idt_base
;
569 u64 msr_host_kernel_gs_base
;
570 u64 msr_guest_kernel_gs_base
;
572 u32 vm_entry_controls_shadow
;
573 u32 vm_exit_controls_shadow
;
575 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
576 * non-nested (L1) guest, it always points to vmcs01. For a nested
577 * guest (L2), it points to a different VMCS.
579 struct loaded_vmcs vmcs01
;
580 struct loaded_vmcs
*loaded_vmcs
;
581 bool __launched
; /* temporary, used in vmx_vcpu_run */
582 struct msr_autoload
{
584 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
585 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
589 u16 fs_sel
, gs_sel
, ldt_sel
;
593 int gs_ldt_reload_needed
;
594 int fs_reload_needed
;
595 u64 msr_host_bndcfgs
;
596 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
601 struct kvm_segment segs
[8];
604 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
605 struct kvm_save_segment
{
613 bool emulation_required
;
617 /* Posted interrupt descriptor */
618 struct pi_desc pi_desc
;
620 /* Support for a guest hypervisor (nested VMX) */
621 struct nested_vmx nested
;
623 /* Dynamic PLE window. */
625 bool ple_window_dirty
;
627 /* Support for PML */
628 #define PML_ENTITY_NUM 512
631 /* apic deadline value in host tsc */
634 u64 current_tsc_ratio
;
636 bool guest_pkru_valid
;
641 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
642 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
643 * in msr_ia32_feature_control_valid_bits.
645 u64 msr_ia32_feature_control
;
646 u64 msr_ia32_feature_control_valid_bits
;
649 enum segment_cache_field
{
658 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
660 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
663 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
665 return &(to_vmx(vcpu
)->pi_desc
);
668 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
669 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
670 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
671 [number##_HIGH] = VMCS12_OFFSET(name)+4
674 static unsigned long shadow_read_only_fields
[] = {
676 * We do NOT shadow fields that are modified when L0
677 * traps and emulates any vmx instruction (e.g. VMPTRLD,
678 * VMXON...) executed by L1.
679 * For example, VM_INSTRUCTION_ERROR is read
680 * by L1 if a vmx instruction fails (part of the error path).
681 * Note the code assumes this logic. If for some reason
682 * we start shadowing these fields then we need to
683 * force a shadow sync when L0 emulates vmx instructions
684 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
685 * by nested_vmx_failValid)
689 VM_EXIT_INSTRUCTION_LEN
,
690 IDT_VECTORING_INFO_FIELD
,
691 IDT_VECTORING_ERROR_CODE
,
692 VM_EXIT_INTR_ERROR_CODE
,
694 GUEST_LINEAR_ADDRESS
,
695 GUEST_PHYSICAL_ADDRESS
697 static int max_shadow_read_only_fields
=
698 ARRAY_SIZE(shadow_read_only_fields
);
700 static unsigned long shadow_read_write_fields
[] = {
707 GUEST_INTERRUPTIBILITY_INFO
,
720 CPU_BASED_VM_EXEC_CONTROL
,
721 VM_ENTRY_EXCEPTION_ERROR_CODE
,
722 VM_ENTRY_INTR_INFO_FIELD
,
723 VM_ENTRY_INSTRUCTION_LEN
,
724 VM_ENTRY_EXCEPTION_ERROR_CODE
,
730 static int max_shadow_read_write_fields
=
731 ARRAY_SIZE(shadow_read_write_fields
);
733 static const unsigned short vmcs_field_to_offset_table
[] = {
734 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
735 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
736 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
737 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
738 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
739 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
740 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
741 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
742 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
743 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
744 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
745 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
746 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
747 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
748 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
749 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
750 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
751 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
752 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
753 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
754 FIELD64(MSR_BITMAP
, msr_bitmap
),
755 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
756 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
757 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
758 FIELD64(TSC_OFFSET
, tsc_offset
),
759 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
760 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
761 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
762 FIELD64(EPT_POINTER
, ept_pointer
),
763 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
764 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
765 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
766 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
767 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
768 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
769 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
770 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
771 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
772 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
773 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
774 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
775 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
776 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
777 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
778 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
779 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
780 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
781 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
782 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
783 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
784 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
785 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
786 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
787 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
788 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
789 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
790 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
791 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
792 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
793 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
794 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
795 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
796 FIELD(TPR_THRESHOLD
, tpr_threshold
),
797 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
798 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
799 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
800 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
801 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
802 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
803 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
804 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
805 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
806 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
807 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
808 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
809 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
810 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
811 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
812 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
813 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
814 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
815 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
816 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
817 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
818 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
819 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
820 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
821 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
822 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
823 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
824 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
825 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
826 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
827 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
828 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
829 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
830 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
831 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
832 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
833 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
834 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
835 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
836 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
837 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
838 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
839 FIELD(GUEST_CR0
, guest_cr0
),
840 FIELD(GUEST_CR3
, guest_cr3
),
841 FIELD(GUEST_CR4
, guest_cr4
),
842 FIELD(GUEST_ES_BASE
, guest_es_base
),
843 FIELD(GUEST_CS_BASE
, guest_cs_base
),
844 FIELD(GUEST_SS_BASE
, guest_ss_base
),
845 FIELD(GUEST_DS_BASE
, guest_ds_base
),
846 FIELD(GUEST_FS_BASE
, guest_fs_base
),
847 FIELD(GUEST_GS_BASE
, guest_gs_base
),
848 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
849 FIELD(GUEST_TR_BASE
, guest_tr_base
),
850 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
851 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
852 FIELD(GUEST_DR7
, guest_dr7
),
853 FIELD(GUEST_RSP
, guest_rsp
),
854 FIELD(GUEST_RIP
, guest_rip
),
855 FIELD(GUEST_RFLAGS
, guest_rflags
),
856 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
857 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
858 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
859 FIELD(HOST_CR0
, host_cr0
),
860 FIELD(HOST_CR3
, host_cr3
),
861 FIELD(HOST_CR4
, host_cr4
),
862 FIELD(HOST_FS_BASE
, host_fs_base
),
863 FIELD(HOST_GS_BASE
, host_gs_base
),
864 FIELD(HOST_TR_BASE
, host_tr_base
),
865 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
866 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
867 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
868 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
869 FIELD(HOST_RSP
, host_rsp
),
870 FIELD(HOST_RIP
, host_rip
),
873 static inline short vmcs_field_to_offset(unsigned long field
)
875 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
877 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
878 vmcs_field_to_offset_table
[field
] == 0)
881 return vmcs_field_to_offset_table
[field
];
884 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
886 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
889 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
891 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
892 if (is_error_page(page
))
898 static void nested_release_page(struct page
*page
)
900 kvm_release_page_dirty(page
);
903 static void nested_release_page_clean(struct page
*page
)
905 kvm_release_page_clean(page
);
908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
909 static u64
construct_eptp(unsigned long root_hpa
);
910 static bool vmx_xsaves_supported(void);
911 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
912 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
913 struct kvm_segment
*var
, int seg
);
914 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
915 struct kvm_segment
*var
, int seg
);
916 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
917 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
918 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
919 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
920 static int alloc_identity_pagetable(struct kvm
*kvm
);
922 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
923 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
925 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
926 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
928 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
931 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
932 * can find which vCPU should be waken up.
934 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
935 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
940 VMX_MSR_BITMAP_LEGACY
,
941 VMX_MSR_BITMAP_LONGMODE
,
942 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
943 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
944 VMX_MSR_BITMAP_LEGACY_X2APIC
,
945 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
951 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
953 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
954 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
955 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
956 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
957 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
958 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
959 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
960 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
961 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
962 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
964 static bool cpu_has_load_ia32_efer
;
965 static bool cpu_has_load_perf_global_ctrl
;
967 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
968 static DEFINE_SPINLOCK(vmx_vpid_lock
);
970 static struct vmcs_config
{
975 u32 pin_based_exec_ctrl
;
976 u32 cpu_based_exec_ctrl
;
977 u32 cpu_based_2nd_exec_ctrl
;
982 static struct vmx_capability
{
987 #define VMX_SEGMENT_FIELD(seg) \
988 [VCPU_SREG_##seg] = { \
989 .selector = GUEST_##seg##_SELECTOR, \
990 .base = GUEST_##seg##_BASE, \
991 .limit = GUEST_##seg##_LIMIT, \
992 .ar_bytes = GUEST_##seg##_AR_BYTES, \
995 static const struct kvm_vmx_segment_field
{
1000 } kvm_vmx_segment_fields
[] = {
1001 VMX_SEGMENT_FIELD(CS
),
1002 VMX_SEGMENT_FIELD(DS
),
1003 VMX_SEGMENT_FIELD(ES
),
1004 VMX_SEGMENT_FIELD(FS
),
1005 VMX_SEGMENT_FIELD(GS
),
1006 VMX_SEGMENT_FIELD(SS
),
1007 VMX_SEGMENT_FIELD(TR
),
1008 VMX_SEGMENT_FIELD(LDTR
),
1011 static u64 host_efer
;
1013 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1016 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1017 * away by decrementing the array size.
1019 static const u32 vmx_msr_index
[] = {
1020 #ifdef CONFIG_X86_64
1021 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1023 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1026 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1028 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1029 INTR_INFO_VALID_MASK
)) ==
1030 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1033 static inline bool is_debug(u32 intr_info
)
1035 return is_exception_n(intr_info
, DB_VECTOR
);
1038 static inline bool is_breakpoint(u32 intr_info
)
1040 return is_exception_n(intr_info
, BP_VECTOR
);
1043 static inline bool is_page_fault(u32 intr_info
)
1045 return is_exception_n(intr_info
, PF_VECTOR
);
1048 static inline bool is_no_device(u32 intr_info
)
1050 return is_exception_n(intr_info
, NM_VECTOR
);
1053 static inline bool is_invalid_opcode(u32 intr_info
)
1055 return is_exception_n(intr_info
, UD_VECTOR
);
1058 static inline bool is_external_interrupt(u32 intr_info
)
1060 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1061 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1064 static inline bool is_machine_check(u32 intr_info
)
1066 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1067 INTR_INFO_VALID_MASK
)) ==
1068 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1071 static inline bool cpu_has_vmx_msr_bitmap(void)
1073 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1076 static inline bool cpu_has_vmx_tpr_shadow(void)
1078 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1081 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1083 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1086 static inline bool cpu_has_secondary_exec_ctrls(void)
1088 return vmcs_config
.cpu_based_exec_ctrl
&
1089 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1092 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1094 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1095 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1098 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1100 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1101 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1104 static inline bool cpu_has_vmx_apic_register_virt(void)
1106 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1107 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1110 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1112 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1113 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1117 * Comment's format: document - errata name - stepping - processor name.
1119 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1121 static u32 vmx_preemption_cpu_tfms
[] = {
1122 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1124 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1125 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1126 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1128 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1130 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1131 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1133 * 320767.pdf - AAP86 - B1 -
1134 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1137 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1139 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1141 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1143 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1144 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1145 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1149 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1151 u32 eax
= cpuid_eax(0x00000001), i
;
1153 /* Clear the reserved bits */
1154 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1155 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1156 if (eax
== vmx_preemption_cpu_tfms
[i
])
1162 static inline bool cpu_has_vmx_preemption_timer(void)
1164 return vmcs_config
.pin_based_exec_ctrl
&
1165 PIN_BASED_VMX_PREEMPTION_TIMER
;
1168 static inline bool cpu_has_vmx_posted_intr(void)
1170 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1171 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1174 static inline bool cpu_has_vmx_apicv(void)
1176 return cpu_has_vmx_apic_register_virt() &&
1177 cpu_has_vmx_virtual_intr_delivery() &&
1178 cpu_has_vmx_posted_intr();
1181 static inline bool cpu_has_vmx_flexpriority(void)
1183 return cpu_has_vmx_tpr_shadow() &&
1184 cpu_has_vmx_virtualize_apic_accesses();
1187 static inline bool cpu_has_vmx_ept_execute_only(void)
1189 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1192 static inline bool cpu_has_vmx_ept_2m_page(void)
1194 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1197 static inline bool cpu_has_vmx_ept_1g_page(void)
1199 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1202 static inline bool cpu_has_vmx_ept_4levels(void)
1204 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1207 static inline bool cpu_has_vmx_ept_ad_bits(void)
1209 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1212 static inline bool cpu_has_vmx_invept_context(void)
1214 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1217 static inline bool cpu_has_vmx_invept_global(void)
1219 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1222 static inline bool cpu_has_vmx_invvpid_single(void)
1224 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1227 static inline bool cpu_has_vmx_invvpid_global(void)
1229 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1232 static inline bool cpu_has_vmx_invvpid(void)
1234 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1237 static inline bool cpu_has_vmx_ept(void)
1239 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1240 SECONDARY_EXEC_ENABLE_EPT
;
1243 static inline bool cpu_has_vmx_unrestricted_guest(void)
1245 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1246 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1249 static inline bool cpu_has_vmx_ple(void)
1251 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1252 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1255 static inline bool cpu_has_vmx_basic_inout(void)
1257 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1260 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1262 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1265 static inline bool cpu_has_vmx_vpid(void)
1267 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1268 SECONDARY_EXEC_ENABLE_VPID
;
1271 static inline bool cpu_has_vmx_rdtscp(void)
1273 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1274 SECONDARY_EXEC_RDTSCP
;
1277 static inline bool cpu_has_vmx_invpcid(void)
1279 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1280 SECONDARY_EXEC_ENABLE_INVPCID
;
1283 static inline bool cpu_has_vmx_wbinvd_exit(void)
1285 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1286 SECONDARY_EXEC_WBINVD_EXITING
;
1289 static inline bool cpu_has_vmx_shadow_vmcs(void)
1292 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1293 /* check if the cpu supports writing r/o exit information fields */
1294 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1297 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1298 SECONDARY_EXEC_SHADOW_VMCS
;
1301 static inline bool cpu_has_vmx_pml(void)
1303 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1306 static inline bool cpu_has_vmx_tsc_scaling(void)
1308 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1309 SECONDARY_EXEC_TSC_SCALING
;
1312 static inline bool report_flexpriority(void)
1314 return flexpriority_enabled
;
1317 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1319 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1322 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1324 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1327 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1329 return (vmcs12
->cpu_based_vm_exec_control
&
1330 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1331 (vmcs12
->secondary_vm_exec_control
& bit
);
1334 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1336 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1339 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1341 return vmcs12
->pin_based_vm_exec_control
&
1342 PIN_BASED_VMX_PREEMPTION_TIMER
;
1345 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1347 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1350 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1352 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1353 vmx_xsaves_supported();
1356 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1358 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1361 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1363 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1366 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1368 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1371 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1373 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1376 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1378 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1381 static inline bool is_nmi(u32 intr_info
)
1383 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1384 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1387 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1389 unsigned long exit_qualification
);
1390 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1391 struct vmcs12
*vmcs12
,
1392 u32 reason
, unsigned long qualification
);
1394 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1398 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1399 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1404 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1410 } operand
= { vpid
, 0, gva
};
1412 asm volatile (__ex(ASM_VMX_INVVPID
)
1413 /* CF==1 or ZF==1 --> rc = -1 */
1414 "; ja 1f ; ud2 ; 1:"
1415 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1418 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1422 } operand
= {eptp
, gpa
};
1424 asm volatile (__ex(ASM_VMX_INVEPT
)
1425 /* CF==1 or ZF==1 --> rc = -1 */
1426 "; ja 1f ; ud2 ; 1:\n"
1427 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1430 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1434 i
= __find_msr_index(vmx
, msr
);
1436 return &vmx
->guest_msrs
[i
];
1440 static void vmcs_clear(struct vmcs
*vmcs
)
1442 u64 phys_addr
= __pa(vmcs
);
1445 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1446 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1449 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1453 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1455 vmcs_clear(loaded_vmcs
->vmcs
);
1456 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1457 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1458 loaded_vmcs
->cpu
= -1;
1459 loaded_vmcs
->launched
= 0;
1462 static void vmcs_load(struct vmcs
*vmcs
)
1464 u64 phys_addr
= __pa(vmcs
);
1467 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1468 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1471 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1475 #ifdef CONFIG_KEXEC_CORE
1477 * This bitmap is used to indicate whether the vmclear
1478 * operation is enabled on all cpus. All disabled by
1481 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1483 static inline void crash_enable_local_vmclear(int cpu
)
1485 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1488 static inline void crash_disable_local_vmclear(int cpu
)
1490 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1493 static inline int crash_local_vmclear_enabled(int cpu
)
1495 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1498 static void crash_vmclear_local_loaded_vmcss(void)
1500 int cpu
= raw_smp_processor_id();
1501 struct loaded_vmcs
*v
;
1503 if (!crash_local_vmclear_enabled(cpu
))
1506 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1507 loaded_vmcss_on_cpu_link
)
1508 vmcs_clear(v
->vmcs
);
1511 static inline void crash_enable_local_vmclear(int cpu
) { }
1512 static inline void crash_disable_local_vmclear(int cpu
) { }
1513 #endif /* CONFIG_KEXEC_CORE */
1515 static void __loaded_vmcs_clear(void *arg
)
1517 struct loaded_vmcs
*loaded_vmcs
= arg
;
1518 int cpu
= raw_smp_processor_id();
1520 if (loaded_vmcs
->cpu
!= cpu
)
1521 return; /* vcpu migration can race with cpu offline */
1522 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1523 per_cpu(current_vmcs
, cpu
) = NULL
;
1524 crash_disable_local_vmclear(cpu
);
1525 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1528 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1529 * is before setting loaded_vmcs->vcpu to -1 which is done in
1530 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1531 * then adds the vmcs into percpu list before it is deleted.
1535 loaded_vmcs_init(loaded_vmcs
);
1536 crash_enable_local_vmclear(cpu
);
1539 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1541 int cpu
= loaded_vmcs
->cpu
;
1544 smp_call_function_single(cpu
,
1545 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1548 static inline void vpid_sync_vcpu_single(int vpid
)
1553 if (cpu_has_vmx_invvpid_single())
1554 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1557 static inline void vpid_sync_vcpu_global(void)
1559 if (cpu_has_vmx_invvpid_global())
1560 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1563 static inline void vpid_sync_context(int vpid
)
1565 if (cpu_has_vmx_invvpid_single())
1566 vpid_sync_vcpu_single(vpid
);
1568 vpid_sync_vcpu_global();
1571 static inline void ept_sync_global(void)
1573 if (cpu_has_vmx_invept_global())
1574 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1577 static inline void ept_sync_context(u64 eptp
)
1580 if (cpu_has_vmx_invept_context())
1581 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1587 static __always_inline
void vmcs_check16(unsigned long field
)
1589 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1590 "16-bit accessor invalid for 64-bit field");
1591 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1592 "16-bit accessor invalid for 64-bit high field");
1593 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1594 "16-bit accessor invalid for 32-bit high field");
1595 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1596 "16-bit accessor invalid for natural width field");
1599 static __always_inline
void vmcs_check32(unsigned long field
)
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1602 "32-bit accessor invalid for 16-bit field");
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1604 "32-bit accessor invalid for natural width field");
1607 static __always_inline
void vmcs_check64(unsigned long field
)
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1610 "64-bit accessor invalid for 16-bit field");
1611 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1612 "64-bit accessor invalid for 64-bit high field");
1613 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1614 "64-bit accessor invalid for 32-bit field");
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1616 "64-bit accessor invalid for natural width field");
1619 static __always_inline
void vmcs_checkl(unsigned long field
)
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1622 "Natural width accessor invalid for 16-bit field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1624 "Natural width accessor invalid for 64-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1626 "Natural width accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1628 "Natural width accessor invalid for 32-bit field");
1631 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1633 unsigned long value
;
1635 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1636 : "=a"(value
) : "d"(field
) : "cc");
1640 static __always_inline u16
vmcs_read16(unsigned long field
)
1642 vmcs_check16(field
);
1643 return __vmcs_readl(field
);
1646 static __always_inline u32
vmcs_read32(unsigned long field
)
1648 vmcs_check32(field
);
1649 return __vmcs_readl(field
);
1652 static __always_inline u64
vmcs_read64(unsigned long field
)
1654 vmcs_check64(field
);
1655 #ifdef CONFIG_X86_64
1656 return __vmcs_readl(field
);
1658 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1662 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1665 return __vmcs_readl(field
);
1668 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1670 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1671 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1675 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1679 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1680 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1681 if (unlikely(error
))
1682 vmwrite_error(field
, value
);
1685 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1687 vmcs_check16(field
);
1688 __vmcs_writel(field
, value
);
1691 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1693 vmcs_check32(field
);
1694 __vmcs_writel(field
, value
);
1697 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1699 vmcs_check64(field
);
1700 __vmcs_writel(field
, value
);
1701 #ifndef CONFIG_X86_64
1703 __vmcs_writel(field
+1, value
>> 32);
1707 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1710 __vmcs_writel(field
, value
);
1713 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1715 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1716 "vmcs_clear_bits does not support 64-bit fields");
1717 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1720 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1722 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1723 "vmcs_set_bits does not support 64-bit fields");
1724 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1727 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1729 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1732 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1734 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1735 vmx
->vm_entry_controls_shadow
= val
;
1738 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1740 if (vmx
->vm_entry_controls_shadow
!= val
)
1741 vm_entry_controls_init(vmx
, val
);
1744 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1746 return vmx
->vm_entry_controls_shadow
;
1750 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1752 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1755 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1757 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1760 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1762 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1765 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1767 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1768 vmx
->vm_exit_controls_shadow
= val
;
1771 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1773 if (vmx
->vm_exit_controls_shadow
!= val
)
1774 vm_exit_controls_init(vmx
, val
);
1777 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1779 return vmx
->vm_exit_controls_shadow
;
1783 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1785 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1788 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1790 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1793 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1795 vmx
->segment_cache
.bitmask
= 0;
1798 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1802 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1804 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1805 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1806 vmx
->segment_cache
.bitmask
= 0;
1808 ret
= vmx
->segment_cache
.bitmask
& mask
;
1809 vmx
->segment_cache
.bitmask
|= mask
;
1813 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1815 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1817 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1818 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1822 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1824 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1826 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1827 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1831 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1833 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1835 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1836 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1840 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1842 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1844 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1845 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1849 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1853 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1854 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1855 if ((vcpu
->guest_debug
&
1856 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1857 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1858 eb
|= 1u << BP_VECTOR
;
1859 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1862 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1864 /* When we are running a nested L2 guest and L1 specified for it a
1865 * certain exception bitmap, we must trap the same exceptions and pass
1866 * them to L1. When running L2, we will only handle the exceptions
1867 * specified above if L1 did not want them.
1869 if (is_guest_mode(vcpu
))
1870 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1872 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1875 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1876 unsigned long entry
, unsigned long exit
)
1878 vm_entry_controls_clearbit(vmx
, entry
);
1879 vm_exit_controls_clearbit(vmx
, exit
);
1882 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1885 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1889 if (cpu_has_load_ia32_efer
) {
1890 clear_atomic_switch_msr_special(vmx
,
1891 VM_ENTRY_LOAD_IA32_EFER
,
1892 VM_EXIT_LOAD_IA32_EFER
);
1896 case MSR_CORE_PERF_GLOBAL_CTRL
:
1897 if (cpu_has_load_perf_global_ctrl
) {
1898 clear_atomic_switch_msr_special(vmx
,
1899 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1900 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1906 for (i
= 0; i
< m
->nr
; ++i
)
1907 if (m
->guest
[i
].index
== msr
)
1913 m
->guest
[i
] = m
->guest
[m
->nr
];
1914 m
->host
[i
] = m
->host
[m
->nr
];
1915 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1916 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1919 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1920 unsigned long entry
, unsigned long exit
,
1921 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1922 u64 guest_val
, u64 host_val
)
1924 vmcs_write64(guest_val_vmcs
, guest_val
);
1925 vmcs_write64(host_val_vmcs
, host_val
);
1926 vm_entry_controls_setbit(vmx
, entry
);
1927 vm_exit_controls_setbit(vmx
, exit
);
1930 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1931 u64 guest_val
, u64 host_val
)
1934 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1938 if (cpu_has_load_ia32_efer
) {
1939 add_atomic_switch_msr_special(vmx
,
1940 VM_ENTRY_LOAD_IA32_EFER
,
1941 VM_EXIT_LOAD_IA32_EFER
,
1944 guest_val
, host_val
);
1948 case MSR_CORE_PERF_GLOBAL_CTRL
:
1949 if (cpu_has_load_perf_global_ctrl
) {
1950 add_atomic_switch_msr_special(vmx
,
1951 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1952 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1953 GUEST_IA32_PERF_GLOBAL_CTRL
,
1954 HOST_IA32_PERF_GLOBAL_CTRL
,
1955 guest_val
, host_val
);
1959 case MSR_IA32_PEBS_ENABLE
:
1960 /* PEBS needs a quiescent period after being disabled (to write
1961 * a record). Disabling PEBS through VMX MSR swapping doesn't
1962 * provide that period, so a CPU could write host's record into
1965 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1968 for (i
= 0; i
< m
->nr
; ++i
)
1969 if (m
->guest
[i
].index
== msr
)
1972 if (i
== NR_AUTOLOAD_MSRS
) {
1973 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1974 "Can't add msr %x\n", msr
);
1976 } else if (i
== m
->nr
) {
1978 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1979 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1982 m
->guest
[i
].index
= msr
;
1983 m
->guest
[i
].value
= guest_val
;
1984 m
->host
[i
].index
= msr
;
1985 m
->host
[i
].value
= host_val
;
1988 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1990 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1991 u64 ignore_bits
= 0;
1995 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1996 * host CPUID is more efficient than testing guest CPUID
1997 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1999 if (boot_cpu_has(X86_FEATURE_SMEP
))
2000 guest_efer
|= EFER_NX
;
2001 else if (!(guest_efer
& EFER_NX
))
2002 ignore_bits
|= EFER_NX
;
2006 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2008 ignore_bits
|= EFER_SCE
;
2009 #ifdef CONFIG_X86_64
2010 ignore_bits
|= EFER_LMA
| EFER_LME
;
2011 /* SCE is meaningful only in long mode on Intel */
2012 if (guest_efer
& EFER_LMA
)
2013 ignore_bits
&= ~(u64
)EFER_SCE
;
2016 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2019 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2020 * On CPUs that support "load IA32_EFER", always switch EFER
2021 * atomically, since it's faster than switching it manually.
2023 if (cpu_has_load_ia32_efer
||
2024 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2025 if (!(guest_efer
& EFER_LMA
))
2026 guest_efer
&= ~EFER_LME
;
2027 if (guest_efer
!= host_efer
)
2028 add_atomic_switch_msr(vmx
, MSR_EFER
,
2029 guest_efer
, host_efer
);
2032 guest_efer
&= ~ignore_bits
;
2033 guest_efer
|= host_efer
& ignore_bits
;
2035 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2036 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2042 #ifdef CONFIG_X86_32
2044 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2045 * VMCS rather than the segment table. KVM uses this helper to figure
2046 * out the current bases to poke them into the VMCS before entry.
2048 static unsigned long segment_base(u16 selector
)
2050 struct desc_struct
*table
;
2053 if (!(selector
& ~SEGMENT_RPL_MASK
))
2056 table
= get_current_gdt_ro();
2058 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2059 u16 ldt_selector
= kvm_read_ldt();
2061 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2064 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2066 v
= get_desc_base(&table
[selector
>> 3]);
2071 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2073 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2076 if (vmx
->host_state
.loaded
)
2079 vmx
->host_state
.loaded
= 1;
2081 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2082 * allow segment selectors with cpl > 0 or ti == 1.
2084 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2085 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2086 savesegment(fs
, vmx
->host_state
.fs_sel
);
2087 if (!(vmx
->host_state
.fs_sel
& 7)) {
2088 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2089 vmx
->host_state
.fs_reload_needed
= 0;
2091 vmcs_write16(HOST_FS_SELECTOR
, 0);
2092 vmx
->host_state
.fs_reload_needed
= 1;
2094 savesegment(gs
, vmx
->host_state
.gs_sel
);
2095 if (!(vmx
->host_state
.gs_sel
& 7))
2096 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2098 vmcs_write16(HOST_GS_SELECTOR
, 0);
2099 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2102 #ifdef CONFIG_X86_64
2103 savesegment(ds
, vmx
->host_state
.ds_sel
);
2104 savesegment(es
, vmx
->host_state
.es_sel
);
2107 #ifdef CONFIG_X86_64
2108 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2109 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2111 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2112 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2115 #ifdef CONFIG_X86_64
2116 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2117 if (is_long_mode(&vmx
->vcpu
))
2118 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2120 if (boot_cpu_has(X86_FEATURE_MPX
))
2121 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2122 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2123 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2124 vmx
->guest_msrs
[i
].data
,
2125 vmx
->guest_msrs
[i
].mask
);
2128 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2130 if (!vmx
->host_state
.loaded
)
2133 ++vmx
->vcpu
.stat
.host_state_reload
;
2134 vmx
->host_state
.loaded
= 0;
2135 #ifdef CONFIG_X86_64
2136 if (is_long_mode(&vmx
->vcpu
))
2137 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2139 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2140 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2141 #ifdef CONFIG_X86_64
2142 load_gs_index(vmx
->host_state
.gs_sel
);
2144 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2147 if (vmx
->host_state
.fs_reload_needed
)
2148 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2149 #ifdef CONFIG_X86_64
2150 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2151 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2152 loadsegment(es
, vmx
->host_state
.es_sel
);
2155 invalidate_tss_limit();
2156 #ifdef CONFIG_X86_64
2157 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2159 if (vmx
->host_state
.msr_host_bndcfgs
)
2160 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2161 load_fixmap_gdt(raw_smp_processor_id());
2164 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2167 __vmx_load_host_state(vmx
);
2171 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2173 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2174 struct pi_desc old
, new;
2177 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2178 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2179 !kvm_vcpu_apicv_active(vcpu
))
2183 old
.control
= new.control
= pi_desc
->control
;
2186 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2187 * are two possible cases:
2188 * 1. After running 'pre_block', context switch
2189 * happened. For this case, 'sn' was set in
2190 * vmx_vcpu_put(), so we need to clear it here.
2191 * 2. After running 'pre_block', we were blocked,
2192 * and woken up by some other guy. For this case,
2193 * we don't need to do anything, 'pi_post_block'
2194 * will do everything for us. However, we cannot
2195 * check whether it is case #1 or case #2 here
2196 * (maybe, not needed), so we also clear sn here,
2197 * I think it is not a big deal.
2199 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2200 if (vcpu
->cpu
!= cpu
) {
2201 dest
= cpu_physical_id(cpu
);
2203 if (x2apic_enabled())
2206 new.ndst
= (dest
<< 8) & 0xFF00;
2209 /* set 'NV' to 'notification vector' */
2210 new.nv
= POSTED_INTR_VECTOR
;
2213 /* Allow posting non-urgent interrupts */
2215 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2216 new.control
) != old
.control
);
2219 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2221 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2222 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2226 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2227 * vcpu mutex is already taken.
2229 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2231 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2232 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2234 if (!already_loaded
) {
2235 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2236 local_irq_disable();
2237 crash_disable_local_vmclear(cpu
);
2240 * Read loaded_vmcs->cpu should be before fetching
2241 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2242 * See the comments in __loaded_vmcs_clear().
2246 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2247 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2248 crash_enable_local_vmclear(cpu
);
2252 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2253 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2254 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2257 if (!already_loaded
) {
2258 void *gdt
= get_current_gdt_ro();
2259 unsigned long sysenter_esp
;
2261 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2264 * Linux uses per-cpu TSS and GDT, so set these when switching
2265 * processors. See 22.2.4.
2267 vmcs_writel(HOST_TR_BASE
,
2268 (unsigned long)this_cpu_ptr(&cpu_tss
));
2269 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2272 * VM exits change the host TR limit to 0x67 after a VM
2273 * exit. This is okay, since 0x67 covers everything except
2274 * the IO bitmap and have have code to handle the IO bitmap
2275 * being lost after a VM exit.
2277 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2279 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2280 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2282 vmx
->loaded_vmcs
->cpu
= cpu
;
2285 /* Setup TSC multiplier */
2286 if (kvm_has_tsc_control
&&
2287 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2288 decache_tsc_multiplier(vmx
);
2290 vmx_vcpu_pi_load(vcpu
, cpu
);
2291 vmx
->host_pkru
= read_pkru();
2294 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2296 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2298 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2299 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2300 !kvm_vcpu_apicv_active(vcpu
))
2303 /* Set SN when the vCPU is preempted */
2304 if (vcpu
->preempted
)
2308 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2310 vmx_vcpu_pi_put(vcpu
);
2312 __vmx_load_host_state(to_vmx(vcpu
));
2315 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2318 * Return the cr0 value that a nested guest would read. This is a combination
2319 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2320 * its hypervisor (cr0_read_shadow).
2322 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2324 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2325 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2327 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2329 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2330 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2333 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2335 unsigned long rflags
, save_rflags
;
2337 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2338 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2339 rflags
= vmcs_readl(GUEST_RFLAGS
);
2340 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2341 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2342 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2343 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2345 to_vmx(vcpu
)->rflags
= rflags
;
2347 return to_vmx(vcpu
)->rflags
;
2350 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2352 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2353 to_vmx(vcpu
)->rflags
= rflags
;
2354 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2355 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2356 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2358 vmcs_writel(GUEST_RFLAGS
, rflags
);
2361 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2363 return to_vmx(vcpu
)->guest_pkru
;
2366 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2368 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2371 if (interruptibility
& GUEST_INTR_STATE_STI
)
2372 ret
|= KVM_X86_SHADOW_INT_STI
;
2373 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2374 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2379 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2381 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2382 u32 interruptibility
= interruptibility_old
;
2384 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2386 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2387 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2388 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2389 interruptibility
|= GUEST_INTR_STATE_STI
;
2391 if ((interruptibility
!= interruptibility_old
))
2392 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2395 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2399 rip
= kvm_rip_read(vcpu
);
2400 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2401 kvm_rip_write(vcpu
, rip
);
2403 /* skipping an emulated instruction also counts */
2404 vmx_set_interrupt_shadow(vcpu
, 0);
2408 * KVM wants to inject page-faults which it got to the guest. This function
2409 * checks whether in a nested guest, we need to inject them to L1 or L2.
2411 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2413 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2415 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2418 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2419 vmcs_read32(VM_EXIT_INTR_INFO
),
2420 vmcs_readl(EXIT_QUALIFICATION
));
2424 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2425 bool has_error_code
, u32 error_code
,
2428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2429 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2431 if (!reinject
&& is_guest_mode(vcpu
) &&
2432 nested_vmx_check_exception(vcpu
, nr
))
2435 if (has_error_code
) {
2436 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2437 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2440 if (vmx
->rmode
.vm86_active
) {
2442 if (kvm_exception_is_soft(nr
))
2443 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2444 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2445 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2449 if (kvm_exception_is_soft(nr
)) {
2450 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2451 vmx
->vcpu
.arch
.event_exit_inst_len
);
2452 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2454 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2456 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2459 static bool vmx_rdtscp_supported(void)
2461 return cpu_has_vmx_rdtscp();
2464 static bool vmx_invpcid_supported(void)
2466 return cpu_has_vmx_invpcid() && enable_ept
;
2470 * Swap MSR entry in host/guest MSR entry array.
2472 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2474 struct shared_msr_entry tmp
;
2476 tmp
= vmx
->guest_msrs
[to
];
2477 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2478 vmx
->guest_msrs
[from
] = tmp
;
2481 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2483 unsigned long *msr_bitmap
;
2485 if (is_guest_mode(vcpu
))
2486 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2487 else if (cpu_has_secondary_exec_ctrls() &&
2488 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2489 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2490 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2491 if (is_long_mode(vcpu
))
2492 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2494 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2496 if (is_long_mode(vcpu
))
2497 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2499 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2502 if (is_long_mode(vcpu
))
2503 msr_bitmap
= vmx_msr_bitmap_longmode
;
2505 msr_bitmap
= vmx_msr_bitmap_legacy
;
2508 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2512 * Set up the vmcs to automatically save and restore system
2513 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2514 * mode, as fiddling with msrs is very expensive.
2516 static void setup_msrs(struct vcpu_vmx
*vmx
)
2518 int save_nmsrs
, index
;
2521 #ifdef CONFIG_X86_64
2522 if (is_long_mode(&vmx
->vcpu
)) {
2523 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2525 move_msr_up(vmx
, index
, save_nmsrs
++);
2526 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2528 move_msr_up(vmx
, index
, save_nmsrs
++);
2529 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2531 move_msr_up(vmx
, index
, save_nmsrs
++);
2532 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2533 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2534 move_msr_up(vmx
, index
, save_nmsrs
++);
2536 * MSR_STAR is only needed on long mode guests, and only
2537 * if efer.sce is enabled.
2539 index
= __find_msr_index(vmx
, MSR_STAR
);
2540 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2541 move_msr_up(vmx
, index
, save_nmsrs
++);
2544 index
= __find_msr_index(vmx
, MSR_EFER
);
2545 if (index
>= 0 && update_transition_efer(vmx
, index
))
2546 move_msr_up(vmx
, index
, save_nmsrs
++);
2548 vmx
->save_nmsrs
= save_nmsrs
;
2550 if (cpu_has_vmx_msr_bitmap())
2551 vmx_set_msr_bitmap(&vmx
->vcpu
);
2555 * reads and returns guest's timestamp counter "register"
2556 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2557 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2559 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2561 u64 host_tsc
, tsc_offset
;
2564 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2565 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2569 * writes 'offset' into guest's timestamp counter offset register
2571 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2573 if (is_guest_mode(vcpu
)) {
2575 * We're here if L1 chose not to trap WRMSR to TSC. According
2576 * to the spec, this should set L1's TSC; The offset that L1
2577 * set for L2 remains unchanged, and still needs to be added
2578 * to the newly set TSC to get L2's TSC.
2580 struct vmcs12
*vmcs12
;
2581 /* recalculate vmcs02.TSC_OFFSET: */
2582 vmcs12
= get_vmcs12(vcpu
);
2583 vmcs_write64(TSC_OFFSET
, offset
+
2584 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2585 vmcs12
->tsc_offset
: 0));
2587 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2588 vmcs_read64(TSC_OFFSET
), offset
);
2589 vmcs_write64(TSC_OFFSET
, offset
);
2593 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2595 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2596 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2600 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2601 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2602 * all guests if the "nested" module option is off, and can also be disabled
2603 * for a single guest by disabling its VMX cpuid bit.
2605 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2607 return nested
&& guest_cpuid_has_vmx(vcpu
);
2611 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2612 * returned for the various VMX controls MSRs when nested VMX is enabled.
2613 * The same values should also be used to verify that vmcs12 control fields are
2614 * valid during nested entry from L1 to L2.
2615 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2616 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2617 * bit in the high half is on if the corresponding bit in the control field
2618 * may be on. See also vmx_control_verify().
2620 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2623 * Note that as a general rule, the high half of the MSRs (bits in
2624 * the control fields which may be 1) should be initialized by the
2625 * intersection of the underlying hardware's MSR (i.e., features which
2626 * can be supported) and the list of features we want to expose -
2627 * because they are known to be properly supported in our code.
2628 * Also, usually, the low half of the MSRs (bits which must be 1) can
2629 * be set to 0, meaning that L1 may turn off any of these bits. The
2630 * reason is that if one of these bits is necessary, it will appear
2631 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2632 * fields of vmcs01 and vmcs02, will turn these bits off - and
2633 * nested_vmx_exit_handled() will not pass related exits to L1.
2634 * These rules have exceptions below.
2637 /* pin-based controls */
2638 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2639 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2640 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2641 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2642 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2643 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2644 PIN_BASED_EXT_INTR_MASK
|
2645 PIN_BASED_NMI_EXITING
|
2646 PIN_BASED_VIRTUAL_NMIS
;
2647 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2648 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2649 PIN_BASED_VMX_PREEMPTION_TIMER
;
2650 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2651 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2652 PIN_BASED_POSTED_INTR
;
2655 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2656 vmx
->nested
.nested_vmx_exit_ctls_low
,
2657 vmx
->nested
.nested_vmx_exit_ctls_high
);
2658 vmx
->nested
.nested_vmx_exit_ctls_low
=
2659 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2661 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2662 #ifdef CONFIG_X86_64
2663 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2665 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2666 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2667 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2668 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2669 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2671 if (kvm_mpx_supported())
2672 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2674 /* We support free control of debug control saving. */
2675 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2677 /* entry controls */
2678 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2679 vmx
->nested
.nested_vmx_entry_ctls_low
,
2680 vmx
->nested
.nested_vmx_entry_ctls_high
);
2681 vmx
->nested
.nested_vmx_entry_ctls_low
=
2682 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2683 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2684 #ifdef CONFIG_X86_64
2685 VM_ENTRY_IA32E_MODE
|
2687 VM_ENTRY_LOAD_IA32_PAT
;
2688 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2689 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2690 if (kvm_mpx_supported())
2691 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2693 /* We support free control of debug control loading. */
2694 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2696 /* cpu-based controls */
2697 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2698 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2699 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2700 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2701 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2702 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2703 CPU_BASED_VIRTUAL_INTR_PENDING
|
2704 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2705 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2706 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2707 CPU_BASED_CR3_STORE_EXITING
|
2708 #ifdef CONFIG_X86_64
2709 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2711 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2712 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2713 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2714 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2715 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2717 * We can allow some features even when not supported by the
2718 * hardware. For example, L1 can specify an MSR bitmap - and we
2719 * can use it to avoid exits to L1 - even when L0 runs L2
2720 * without MSR bitmaps.
2722 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2723 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2724 CPU_BASED_USE_MSR_BITMAPS
;
2726 /* We support free control of CR3 access interception. */
2727 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2728 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2730 /* secondary cpu-based controls */
2731 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2732 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2733 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2734 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2735 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2736 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2737 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2738 SECONDARY_EXEC_RDTSCP
|
2739 SECONDARY_EXEC_DESC
|
2740 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2741 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2742 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2743 SECONDARY_EXEC_WBINVD_EXITING
|
2744 SECONDARY_EXEC_XSAVES
;
2747 /* nested EPT: emulate EPT also to L1 */
2748 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2749 SECONDARY_EXEC_ENABLE_EPT
;
2750 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2751 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2752 if (cpu_has_vmx_ept_execute_only())
2753 vmx
->nested
.nested_vmx_ept_caps
|=
2754 VMX_EPT_EXECUTE_ONLY_BIT
;
2755 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2756 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2757 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2758 VMX_EPT_1GB_PAGE_BIT
;
2759 if (enable_ept_ad_bits
)
2760 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2762 vmx
->nested
.nested_vmx_ept_caps
= 0;
2765 * Old versions of KVM use the single-context version without
2766 * checking for support, so declare that it is supported even
2767 * though it is treated as global context. The alternative is
2768 * not failing the single-context invvpid, and it is worse.
2771 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2772 SECONDARY_EXEC_ENABLE_VPID
;
2773 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2774 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2776 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2778 if (enable_unrestricted_guest
)
2779 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2780 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2782 /* miscellaneous data */
2783 rdmsr(MSR_IA32_VMX_MISC
,
2784 vmx
->nested
.nested_vmx_misc_low
,
2785 vmx
->nested
.nested_vmx_misc_high
);
2786 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2787 vmx
->nested
.nested_vmx_misc_low
|=
2788 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2789 VMX_MISC_ACTIVITY_HLT
;
2790 vmx
->nested
.nested_vmx_misc_high
= 0;
2793 * This MSR reports some information about VMX support. We
2794 * should return information about the VMX we emulate for the
2795 * guest, and the VMCS structure we give it - not about the
2796 * VMX support of the underlying hardware.
2798 vmx
->nested
.nested_vmx_basic
=
2800 VMX_BASIC_TRUE_CTLS
|
2801 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2802 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2804 if (cpu_has_vmx_basic_inout())
2805 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2808 * These MSRs specify bits which the guest must keep fixed on
2809 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2810 * We picked the standard core2 setting.
2812 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2813 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2814 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2815 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2817 /* These MSRs specify bits which the guest must keep fixed off. */
2818 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2819 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2821 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2822 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2826 * if fixed0[i] == 1: val[i] must be 1
2827 * if fixed1[i] == 0: val[i] must be 0
2829 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2831 return ((val
& fixed1
) | fixed0
) == val
;
2834 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2836 return fixed_bits_valid(control
, low
, high
);
2839 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2841 return low
| ((u64
)high
<< 32);
2844 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2849 return (superset
| subset
) == superset
;
2852 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2854 const u64 feature_and_reserved
=
2855 /* feature (except bit 48; see below) */
2856 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2858 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2859 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2861 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2865 * KVM does not emulate a version of VMX that constrains physical
2866 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2868 if (data
& BIT_ULL(48))
2871 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2872 vmx_basic_vmcs_revision_id(data
))
2875 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2878 vmx
->nested
.nested_vmx_basic
= data
;
2883 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2888 switch (msr_index
) {
2889 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2890 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2891 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2893 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2894 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2895 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2897 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2898 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2899 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2901 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2902 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2903 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2905 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2906 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2907 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2913 supported
= vmx_control_msr(*lowp
, *highp
);
2915 /* Check must-be-1 bits are still 1. */
2916 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2919 /* Check must-be-0 bits are still 0. */
2920 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2924 *highp
= data
>> 32;
2928 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
2930 const u64 feature_and_reserved_bits
=
2932 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
2933 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
2935 GENMASK_ULL(13, 9) | BIT_ULL(31);
2938 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
2939 vmx
->nested
.nested_vmx_misc_high
);
2941 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
2944 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
2945 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
2946 vmx_misc_preemption_timer_rate(data
) !=
2947 vmx_misc_preemption_timer_rate(vmx_misc
))
2950 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
2953 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
2956 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
2959 vmx
->nested
.nested_vmx_misc_low
= data
;
2960 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
2964 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
2966 u64 vmx_ept_vpid_cap
;
2968 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
2969 vmx
->nested
.nested_vmx_vpid_caps
);
2971 /* Every bit is either reserved or a feature bit. */
2972 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
2975 vmx
->nested
.nested_vmx_ept_caps
= data
;
2976 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
2980 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2984 switch (msr_index
) {
2985 case MSR_IA32_VMX_CR0_FIXED0
:
2986 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
2988 case MSR_IA32_VMX_CR4_FIXED0
:
2989 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
2996 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
2997 * must be 1 in the restored value.
2999 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3007 * Called when userspace is restoring VMX MSRs.
3009 * Returns 0 on success, non-0 otherwise.
3011 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3013 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3015 switch (msr_index
) {
3016 case MSR_IA32_VMX_BASIC
:
3017 return vmx_restore_vmx_basic(vmx
, data
);
3018 case MSR_IA32_VMX_PINBASED_CTLS
:
3019 case MSR_IA32_VMX_PROCBASED_CTLS
:
3020 case MSR_IA32_VMX_EXIT_CTLS
:
3021 case MSR_IA32_VMX_ENTRY_CTLS
:
3023 * The "non-true" VMX capability MSRs are generated from the
3024 * "true" MSRs, so we do not support restoring them directly.
3026 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3027 * should restore the "true" MSRs with the must-be-1 bits
3028 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3029 * DEFAULT SETTINGS".
3032 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3033 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3034 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3035 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3036 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3037 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3038 case MSR_IA32_VMX_MISC
:
3039 return vmx_restore_vmx_misc(vmx
, data
);
3040 case MSR_IA32_VMX_CR0_FIXED0
:
3041 case MSR_IA32_VMX_CR4_FIXED0
:
3042 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3043 case MSR_IA32_VMX_CR0_FIXED1
:
3044 case MSR_IA32_VMX_CR4_FIXED1
:
3046 * These MSRs are generated based on the vCPU's CPUID, so we
3047 * do not support restoring them directly.
3050 case MSR_IA32_VMX_EPT_VPID_CAP
:
3051 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3052 case MSR_IA32_VMX_VMCS_ENUM
:
3053 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3057 * The rest of the VMX capability MSRs do not support restore.
3063 /* Returns 0 on success, non-0 otherwise. */
3064 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3068 switch (msr_index
) {
3069 case MSR_IA32_VMX_BASIC
:
3070 *pdata
= vmx
->nested
.nested_vmx_basic
;
3072 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3073 case MSR_IA32_VMX_PINBASED_CTLS
:
3074 *pdata
= vmx_control_msr(
3075 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3076 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3077 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3078 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3080 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3081 case MSR_IA32_VMX_PROCBASED_CTLS
:
3082 *pdata
= vmx_control_msr(
3083 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3084 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3085 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3086 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3088 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3089 case MSR_IA32_VMX_EXIT_CTLS
:
3090 *pdata
= vmx_control_msr(
3091 vmx
->nested
.nested_vmx_exit_ctls_low
,
3092 vmx
->nested
.nested_vmx_exit_ctls_high
);
3093 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3094 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3096 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3097 case MSR_IA32_VMX_ENTRY_CTLS
:
3098 *pdata
= vmx_control_msr(
3099 vmx
->nested
.nested_vmx_entry_ctls_low
,
3100 vmx
->nested
.nested_vmx_entry_ctls_high
);
3101 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3102 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3104 case MSR_IA32_VMX_MISC
:
3105 *pdata
= vmx_control_msr(
3106 vmx
->nested
.nested_vmx_misc_low
,
3107 vmx
->nested
.nested_vmx_misc_high
);
3109 case MSR_IA32_VMX_CR0_FIXED0
:
3110 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3112 case MSR_IA32_VMX_CR0_FIXED1
:
3113 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3115 case MSR_IA32_VMX_CR4_FIXED0
:
3116 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3118 case MSR_IA32_VMX_CR4_FIXED1
:
3119 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3121 case MSR_IA32_VMX_VMCS_ENUM
:
3122 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3124 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3125 *pdata
= vmx_control_msr(
3126 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3127 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3129 case MSR_IA32_VMX_EPT_VPID_CAP
:
3130 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3131 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3140 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3143 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3145 return !(val
& ~valid_bits
);
3149 * Reads an msr value (of 'msr_index') into 'pdata'.
3150 * Returns 0 on success, non-0 otherwise.
3151 * Assumes vcpu_load() was already called.
3153 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3155 struct shared_msr_entry
*msr
;
3157 switch (msr_info
->index
) {
3158 #ifdef CONFIG_X86_64
3160 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3163 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3165 case MSR_KERNEL_GS_BASE
:
3166 vmx_load_host_state(to_vmx(vcpu
));
3167 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3171 return kvm_get_msr_common(vcpu
, msr_info
);
3173 msr_info
->data
= guest_read_tsc(vcpu
);
3175 case MSR_IA32_SYSENTER_CS
:
3176 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3178 case MSR_IA32_SYSENTER_EIP
:
3179 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3181 case MSR_IA32_SYSENTER_ESP
:
3182 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3184 case MSR_IA32_BNDCFGS
:
3185 if (!kvm_mpx_supported())
3187 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3189 case MSR_IA32_MCG_EXT_CTL
:
3190 if (!msr_info
->host_initiated
&&
3191 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3192 FEATURE_CONTROL_LMCE
))
3194 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3196 case MSR_IA32_FEATURE_CONTROL
:
3197 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3199 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3200 if (!nested_vmx_allowed(vcpu
))
3202 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3204 if (!vmx_xsaves_supported())
3206 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3209 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3211 /* Otherwise falls through */
3213 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3215 msr_info
->data
= msr
->data
;
3218 return kvm_get_msr_common(vcpu
, msr_info
);
3224 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3227 * Writes msr value into into the appropriate "register".
3228 * Returns 0 on success, non-0 otherwise.
3229 * Assumes vcpu_load() was already called.
3231 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3233 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3234 struct shared_msr_entry
*msr
;
3236 u32 msr_index
= msr_info
->index
;
3237 u64 data
= msr_info
->data
;
3239 switch (msr_index
) {
3241 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3243 #ifdef CONFIG_X86_64
3245 vmx_segment_cache_clear(vmx
);
3246 vmcs_writel(GUEST_FS_BASE
, data
);
3249 vmx_segment_cache_clear(vmx
);
3250 vmcs_writel(GUEST_GS_BASE
, data
);
3252 case MSR_KERNEL_GS_BASE
:
3253 vmx_load_host_state(vmx
);
3254 vmx
->msr_guest_kernel_gs_base
= data
;
3257 case MSR_IA32_SYSENTER_CS
:
3258 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3260 case MSR_IA32_SYSENTER_EIP
:
3261 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3263 case MSR_IA32_SYSENTER_ESP
:
3264 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3266 case MSR_IA32_BNDCFGS
:
3267 if (!kvm_mpx_supported())
3269 vmcs_write64(GUEST_BNDCFGS
, data
);
3272 kvm_write_tsc(vcpu
, msr_info
);
3274 case MSR_IA32_CR_PAT
:
3275 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3276 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3278 vmcs_write64(GUEST_IA32_PAT
, data
);
3279 vcpu
->arch
.pat
= data
;
3282 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3284 case MSR_IA32_TSC_ADJUST
:
3285 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3287 case MSR_IA32_MCG_EXT_CTL
:
3288 if ((!msr_info
->host_initiated
&&
3289 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3290 FEATURE_CONTROL_LMCE
)) ||
3291 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3293 vcpu
->arch
.mcg_ext_ctl
= data
;
3295 case MSR_IA32_FEATURE_CONTROL
:
3296 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3297 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3298 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3300 vmx
->msr_ia32_feature_control
= data
;
3301 if (msr_info
->host_initiated
&& data
== 0)
3302 vmx_leave_nested(vcpu
);
3304 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3305 if (!msr_info
->host_initiated
)
3306 return 1; /* they are read-only */
3307 if (!nested_vmx_allowed(vcpu
))
3309 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3311 if (!vmx_xsaves_supported())
3314 * The only supported bit as of Skylake is bit 8, but
3315 * it is not supported on KVM.
3319 vcpu
->arch
.ia32_xss
= data
;
3320 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3321 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3322 vcpu
->arch
.ia32_xss
, host_xss
);
3324 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3327 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3329 /* Check reserved bit, higher 32 bits should be zero */
3330 if ((data
>> 32) != 0)
3332 /* Otherwise falls through */
3334 msr
= find_msr_entry(vmx
, msr_index
);
3336 u64 old_msr_data
= msr
->data
;
3338 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3340 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3344 msr
->data
= old_msr_data
;
3348 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3354 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3356 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3359 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3362 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3364 case VCPU_EXREG_PDPTR
:
3366 ept_save_pdptrs(vcpu
);
3373 static __init
int cpu_has_kvm_support(void)
3375 return cpu_has_vmx();
3378 static __init
int vmx_disabled_by_bios(void)
3382 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3383 if (msr
& FEATURE_CONTROL_LOCKED
) {
3384 /* launched w/ TXT and VMX disabled */
3385 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3388 /* launched w/o TXT and VMX only enabled w/ TXT */
3389 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3390 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3391 && !tboot_enabled()) {
3392 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3393 "activate TXT before enabling KVM\n");
3396 /* launched w/o TXT and VMX disabled */
3397 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3398 && !tboot_enabled())
3405 static void kvm_cpu_vmxon(u64 addr
)
3407 cr4_set_bits(X86_CR4_VMXE
);
3408 intel_pt_handle_vmx(1);
3410 asm volatile (ASM_VMX_VMXON_RAX
3411 : : "a"(&addr
), "m"(addr
)
3415 static int hardware_enable(void)
3417 int cpu
= raw_smp_processor_id();
3418 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3421 if (cr4_read_shadow() & X86_CR4_VMXE
)
3424 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3425 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3426 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3429 * Now we can enable the vmclear operation in kdump
3430 * since the loaded_vmcss_on_cpu list on this cpu
3431 * has been initialized.
3433 * Though the cpu is not in VMX operation now, there
3434 * is no problem to enable the vmclear operation
3435 * for the loaded_vmcss_on_cpu list is empty!
3437 crash_enable_local_vmclear(cpu
);
3439 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3441 test_bits
= FEATURE_CONTROL_LOCKED
;
3442 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3443 if (tboot_enabled())
3444 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3446 if ((old
& test_bits
) != test_bits
) {
3447 /* enable and lock */
3448 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3450 kvm_cpu_vmxon(phys_addr
);
3456 static void vmclear_local_loaded_vmcss(void)
3458 int cpu
= raw_smp_processor_id();
3459 struct loaded_vmcs
*v
, *n
;
3461 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3462 loaded_vmcss_on_cpu_link
)
3463 __loaded_vmcs_clear(v
);
3467 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3470 static void kvm_cpu_vmxoff(void)
3472 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3474 intel_pt_handle_vmx(0);
3475 cr4_clear_bits(X86_CR4_VMXE
);
3478 static void hardware_disable(void)
3480 vmclear_local_loaded_vmcss();
3484 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3485 u32 msr
, u32
*result
)
3487 u32 vmx_msr_low
, vmx_msr_high
;
3488 u32 ctl
= ctl_min
| ctl_opt
;
3490 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3492 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3493 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3495 /* Ensure minimum (required) set of control bits are supported. */
3503 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3505 u32 vmx_msr_low
, vmx_msr_high
;
3507 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3508 return vmx_msr_high
& ctl
;
3511 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3513 u32 vmx_msr_low
, vmx_msr_high
;
3514 u32 min
, opt
, min2
, opt2
;
3515 u32 _pin_based_exec_control
= 0;
3516 u32 _cpu_based_exec_control
= 0;
3517 u32 _cpu_based_2nd_exec_control
= 0;
3518 u32 _vmexit_control
= 0;
3519 u32 _vmentry_control
= 0;
3521 min
= CPU_BASED_HLT_EXITING
|
3522 #ifdef CONFIG_X86_64
3523 CPU_BASED_CR8_LOAD_EXITING
|
3524 CPU_BASED_CR8_STORE_EXITING
|
3526 CPU_BASED_CR3_LOAD_EXITING
|
3527 CPU_BASED_CR3_STORE_EXITING
|
3528 CPU_BASED_USE_IO_BITMAPS
|
3529 CPU_BASED_MOV_DR_EXITING
|
3530 CPU_BASED_USE_TSC_OFFSETING
|
3531 CPU_BASED_INVLPG_EXITING
|
3532 CPU_BASED_RDPMC_EXITING
;
3534 if (!kvm_mwait_in_guest())
3535 min
|= CPU_BASED_MWAIT_EXITING
|
3536 CPU_BASED_MONITOR_EXITING
;
3538 opt
= CPU_BASED_TPR_SHADOW
|
3539 CPU_BASED_USE_MSR_BITMAPS
|
3540 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3541 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3542 &_cpu_based_exec_control
) < 0)
3544 #ifdef CONFIG_X86_64
3545 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3546 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3547 ~CPU_BASED_CR8_STORE_EXITING
;
3549 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3551 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3552 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3553 SECONDARY_EXEC_WBINVD_EXITING
|
3554 SECONDARY_EXEC_ENABLE_VPID
|
3555 SECONDARY_EXEC_ENABLE_EPT
|
3556 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3557 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3558 SECONDARY_EXEC_RDTSCP
|
3559 SECONDARY_EXEC_ENABLE_INVPCID
|
3560 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3561 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3562 SECONDARY_EXEC_SHADOW_VMCS
|
3563 SECONDARY_EXEC_XSAVES
|
3564 SECONDARY_EXEC_ENABLE_PML
|
3565 SECONDARY_EXEC_TSC_SCALING
;
3566 if (adjust_vmx_controls(min2
, opt2
,
3567 MSR_IA32_VMX_PROCBASED_CTLS2
,
3568 &_cpu_based_2nd_exec_control
) < 0)
3571 #ifndef CONFIG_X86_64
3572 if (!(_cpu_based_2nd_exec_control
&
3573 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3574 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3577 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3578 _cpu_based_2nd_exec_control
&= ~(
3579 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3580 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3581 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3583 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3584 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3586 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3587 CPU_BASED_CR3_STORE_EXITING
|
3588 CPU_BASED_INVLPG_EXITING
);
3589 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3590 vmx_capability
.ept
, vmx_capability
.vpid
);
3593 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3594 #ifdef CONFIG_X86_64
3595 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3597 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3598 VM_EXIT_CLEAR_BNDCFGS
;
3599 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3600 &_vmexit_control
) < 0)
3603 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3604 PIN_BASED_VIRTUAL_NMIS
;
3605 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3606 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3607 &_pin_based_exec_control
) < 0)
3610 if (cpu_has_broken_vmx_preemption_timer())
3611 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3612 if (!(_cpu_based_2nd_exec_control
&
3613 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3614 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3616 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3617 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3618 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3619 &_vmentry_control
) < 0)
3622 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3624 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3625 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3628 #ifdef CONFIG_X86_64
3629 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3630 if (vmx_msr_high
& (1u<<16))
3634 /* Require Write-Back (WB) memory type for VMCS accesses. */
3635 if (((vmx_msr_high
>> 18) & 15) != 6)
3638 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3639 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3640 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3641 vmcs_conf
->revision_id
= vmx_msr_low
;
3643 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3644 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3645 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3646 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3647 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3649 cpu_has_load_ia32_efer
=
3650 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3651 VM_ENTRY_LOAD_IA32_EFER
)
3652 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3653 VM_EXIT_LOAD_IA32_EFER
);
3655 cpu_has_load_perf_global_ctrl
=
3656 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3657 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3658 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3659 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3662 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3663 * but due to errata below it can't be used. Workaround is to use
3664 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3666 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3671 * BC86,AAY89,BD102 (model 44)
3675 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3676 switch (boot_cpu_data
.x86_model
) {
3682 cpu_has_load_perf_global_ctrl
= false;
3683 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3684 "does not work properly. Using workaround\n");
3691 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3692 rdmsrl(MSR_IA32_XSS
, host_xss
);
3697 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3699 int node
= cpu_to_node(cpu
);
3703 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3706 vmcs
= page_address(pages
);
3707 memset(vmcs
, 0, vmcs_config
.size
);
3708 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3712 static struct vmcs
*alloc_vmcs(void)
3714 return alloc_vmcs_cpu(raw_smp_processor_id());
3717 static void free_vmcs(struct vmcs
*vmcs
)
3719 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3723 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3725 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3727 if (!loaded_vmcs
->vmcs
)
3729 loaded_vmcs_clear(loaded_vmcs
);
3730 free_vmcs(loaded_vmcs
->vmcs
);
3731 loaded_vmcs
->vmcs
= NULL
;
3732 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3735 static void free_kvm_area(void)
3739 for_each_possible_cpu(cpu
) {
3740 free_vmcs(per_cpu(vmxarea
, cpu
));
3741 per_cpu(vmxarea
, cpu
) = NULL
;
3745 static void init_vmcs_shadow_fields(void)
3749 /* No checks for read only fields yet */
3751 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3752 switch (shadow_read_write_fields
[i
]) {
3754 if (!kvm_mpx_supported())
3762 shadow_read_write_fields
[j
] =
3763 shadow_read_write_fields
[i
];
3766 max_shadow_read_write_fields
= j
;
3768 /* shadowed fields guest access without vmexit */
3769 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3770 clear_bit(shadow_read_write_fields
[i
],
3771 vmx_vmwrite_bitmap
);
3772 clear_bit(shadow_read_write_fields
[i
],
3775 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3776 clear_bit(shadow_read_only_fields
[i
],
3780 static __init
int alloc_kvm_area(void)
3784 for_each_possible_cpu(cpu
) {
3787 vmcs
= alloc_vmcs_cpu(cpu
);
3793 per_cpu(vmxarea
, cpu
) = vmcs
;
3798 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3800 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3803 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3804 struct kvm_segment
*save
)
3806 if (!emulate_invalid_guest_state
) {
3808 * CS and SS RPL should be equal during guest entry according
3809 * to VMX spec, but in reality it is not always so. Since vcpu
3810 * is in the middle of the transition from real mode to
3811 * protected mode it is safe to assume that RPL 0 is a good
3814 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3815 save
->selector
&= ~SEGMENT_RPL_MASK
;
3816 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3819 vmx_set_segment(vcpu
, save
, seg
);
3822 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3824 unsigned long flags
;
3825 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3828 * Update real mode segment cache. It may be not up-to-date if sement
3829 * register was written while vcpu was in a guest mode.
3831 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3832 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3833 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3834 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3835 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3836 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3838 vmx
->rmode
.vm86_active
= 0;
3840 vmx_segment_cache_clear(vmx
);
3842 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3844 flags
= vmcs_readl(GUEST_RFLAGS
);
3845 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3846 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3847 vmcs_writel(GUEST_RFLAGS
, flags
);
3849 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3850 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3852 update_exception_bitmap(vcpu
);
3854 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3855 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3856 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3857 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3858 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3859 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3862 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3864 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3865 struct kvm_segment var
= *save
;
3868 if (seg
== VCPU_SREG_CS
)
3871 if (!emulate_invalid_guest_state
) {
3872 var
.selector
= var
.base
>> 4;
3873 var
.base
= var
.base
& 0xffff0;
3883 if (save
->base
& 0xf)
3884 printk_once(KERN_WARNING
"kvm: segment base is not "
3885 "paragraph aligned when entering "
3886 "protected mode (seg=%d)", seg
);
3889 vmcs_write16(sf
->selector
, var
.selector
);
3890 vmcs_writel(sf
->base
, var
.base
);
3891 vmcs_write32(sf
->limit
, var
.limit
);
3892 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3895 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3897 unsigned long flags
;
3898 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3900 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3901 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3902 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3903 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3904 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3905 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3906 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3908 vmx
->rmode
.vm86_active
= 1;
3911 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3912 * vcpu. Warn the user that an update is overdue.
3914 if (!vcpu
->kvm
->arch
.tss_addr
)
3915 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3916 "called before entering vcpu\n");
3918 vmx_segment_cache_clear(vmx
);
3920 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3921 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3922 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3924 flags
= vmcs_readl(GUEST_RFLAGS
);
3925 vmx
->rmode
.save_rflags
= flags
;
3927 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3929 vmcs_writel(GUEST_RFLAGS
, flags
);
3930 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3931 update_exception_bitmap(vcpu
);
3933 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3934 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3935 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3936 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3937 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3938 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3940 kvm_mmu_reset_context(vcpu
);
3943 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3945 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3946 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3952 * Force kernel_gs_base reloading before EFER changes, as control
3953 * of this msr depends on is_long_mode().
3955 vmx_load_host_state(to_vmx(vcpu
));
3956 vcpu
->arch
.efer
= efer
;
3957 if (efer
& EFER_LMA
) {
3958 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3961 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3963 msr
->data
= efer
& ~EFER_LME
;
3968 #ifdef CONFIG_X86_64
3970 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3974 vmx_segment_cache_clear(to_vmx(vcpu
));
3976 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3977 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3978 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3980 vmcs_write32(GUEST_TR_AR_BYTES
,
3981 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3982 | VMX_AR_TYPE_BUSY_64_TSS
);
3984 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3987 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3989 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3990 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3995 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3998 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4000 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
4002 vpid_sync_context(vpid
);
4006 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4008 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4011 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4014 vmx_flush_tlb(vcpu
);
4017 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4019 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4021 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4022 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4025 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4027 if (enable_ept
&& is_paging(vcpu
))
4028 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4029 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4032 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4034 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4036 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4037 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4040 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4042 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4044 if (!test_bit(VCPU_EXREG_PDPTR
,
4045 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4048 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4049 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4050 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4051 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4052 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4056 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4058 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4060 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4061 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4062 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4063 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4064 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4067 __set_bit(VCPU_EXREG_PDPTR
,
4068 (unsigned long *)&vcpu
->arch
.regs_avail
);
4069 __set_bit(VCPU_EXREG_PDPTR
,
4070 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4073 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4075 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4076 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4077 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4079 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4080 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4081 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4082 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4084 return fixed_bits_valid(val
, fixed0
, fixed1
);
4087 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4089 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4090 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4092 return fixed_bits_valid(val
, fixed0
, fixed1
);
4095 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4097 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4098 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4100 return fixed_bits_valid(val
, fixed0
, fixed1
);
4103 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4104 #define nested_guest_cr4_valid nested_cr4_valid
4105 #define nested_host_cr4_valid nested_cr4_valid
4107 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4109 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4111 struct kvm_vcpu
*vcpu
)
4113 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4114 vmx_decache_cr3(vcpu
);
4115 if (!(cr0
& X86_CR0_PG
)) {
4116 /* From paging/starting to nonpaging */
4117 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4118 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4119 (CPU_BASED_CR3_LOAD_EXITING
|
4120 CPU_BASED_CR3_STORE_EXITING
));
4121 vcpu
->arch
.cr0
= cr0
;
4122 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4123 } else if (!is_paging(vcpu
)) {
4124 /* From nonpaging to paging */
4125 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4126 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4127 ~(CPU_BASED_CR3_LOAD_EXITING
|
4128 CPU_BASED_CR3_STORE_EXITING
));
4129 vcpu
->arch
.cr0
= cr0
;
4130 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4133 if (!(cr0
& X86_CR0_WP
))
4134 *hw_cr0
&= ~X86_CR0_WP
;
4137 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4139 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4140 unsigned long hw_cr0
;
4142 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4143 if (enable_unrestricted_guest
)
4144 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4146 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4148 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4151 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4155 #ifdef CONFIG_X86_64
4156 if (vcpu
->arch
.efer
& EFER_LME
) {
4157 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4159 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4165 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4167 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4168 vmcs_writel(GUEST_CR0
, hw_cr0
);
4169 vcpu
->arch
.cr0
= cr0
;
4171 /* depends on vcpu->arch.cr0 to be set to a new value */
4172 vmx
->emulation_required
= emulation_required(vcpu
);
4175 static u64
construct_eptp(unsigned long root_hpa
)
4179 /* TODO write the value reading from MSR */
4180 eptp
= VMX_EPT_DEFAULT_MT
|
4181 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4182 if (enable_ept_ad_bits
)
4183 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4184 eptp
|= (root_hpa
& PAGE_MASK
);
4189 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4191 unsigned long guest_cr3
;
4196 eptp
= construct_eptp(cr3
);
4197 vmcs_write64(EPT_POINTER
, eptp
);
4198 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4199 guest_cr3
= kvm_read_cr3(vcpu
);
4201 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4202 ept_load_pdptrs(vcpu
);
4205 vmx_flush_tlb(vcpu
);
4206 vmcs_writel(GUEST_CR3
, guest_cr3
);
4209 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4212 * Pass through host's Machine Check Enable value to hw_cr4, which
4213 * is in force while we are in guest mode. Do not let guests control
4214 * this bit, even if host CR4.MCE == 0.
4216 unsigned long hw_cr4
=
4217 (cr4_read_shadow() & X86_CR4_MCE
) |
4218 (cr4
& ~X86_CR4_MCE
) |
4219 (to_vmx(vcpu
)->rmode
.vm86_active
?
4220 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4222 if (cr4
& X86_CR4_VMXE
) {
4224 * To use VMXON (and later other VMX instructions), a guest
4225 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4226 * So basically the check on whether to allow nested VMX
4229 if (!nested_vmx_allowed(vcpu
))
4233 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4236 vcpu
->arch
.cr4
= cr4
;
4238 if (!is_paging(vcpu
)) {
4239 hw_cr4
&= ~X86_CR4_PAE
;
4240 hw_cr4
|= X86_CR4_PSE
;
4241 } else if (!(cr4
& X86_CR4_PAE
)) {
4242 hw_cr4
&= ~X86_CR4_PAE
;
4246 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4248 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4249 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4250 * to be manually disabled when guest switches to non-paging
4253 * If !enable_unrestricted_guest, the CPU is always running
4254 * with CR0.PG=1 and CR4 needs to be modified.
4255 * If enable_unrestricted_guest, the CPU automatically
4256 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4258 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4260 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4261 vmcs_writel(GUEST_CR4
, hw_cr4
);
4265 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4266 struct kvm_segment
*var
, int seg
)
4268 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4271 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4272 *var
= vmx
->rmode
.segs
[seg
];
4273 if (seg
== VCPU_SREG_TR
4274 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4276 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4277 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4280 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4281 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4282 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4283 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4284 var
->unusable
= (ar
>> 16) & 1;
4285 var
->type
= ar
& 15;
4286 var
->s
= (ar
>> 4) & 1;
4287 var
->dpl
= (ar
>> 5) & 3;
4289 * Some userspaces do not preserve unusable property. Since usable
4290 * segment has to be present according to VMX spec we can use present
4291 * property to amend userspace bug by making unusable segment always
4292 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4293 * segment as unusable.
4295 var
->present
= !var
->unusable
;
4296 var
->avl
= (ar
>> 12) & 1;
4297 var
->l
= (ar
>> 13) & 1;
4298 var
->db
= (ar
>> 14) & 1;
4299 var
->g
= (ar
>> 15) & 1;
4302 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4304 struct kvm_segment s
;
4306 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4307 vmx_get_segment(vcpu
, &s
, seg
);
4310 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4313 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4315 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4317 if (unlikely(vmx
->rmode
.vm86_active
))
4320 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4321 return VMX_AR_DPL(ar
);
4325 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4329 if (var
->unusable
|| !var
->present
)
4332 ar
= var
->type
& 15;
4333 ar
|= (var
->s
& 1) << 4;
4334 ar
|= (var
->dpl
& 3) << 5;
4335 ar
|= (var
->present
& 1) << 7;
4336 ar
|= (var
->avl
& 1) << 12;
4337 ar
|= (var
->l
& 1) << 13;
4338 ar
|= (var
->db
& 1) << 14;
4339 ar
|= (var
->g
& 1) << 15;
4345 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4346 struct kvm_segment
*var
, int seg
)
4348 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4349 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4351 vmx_segment_cache_clear(vmx
);
4353 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4354 vmx
->rmode
.segs
[seg
] = *var
;
4355 if (seg
== VCPU_SREG_TR
)
4356 vmcs_write16(sf
->selector
, var
->selector
);
4358 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4362 vmcs_writel(sf
->base
, var
->base
);
4363 vmcs_write32(sf
->limit
, var
->limit
);
4364 vmcs_write16(sf
->selector
, var
->selector
);
4367 * Fix the "Accessed" bit in AR field of segment registers for older
4369 * IA32 arch specifies that at the time of processor reset the
4370 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4371 * is setting it to 0 in the userland code. This causes invalid guest
4372 * state vmexit when "unrestricted guest" mode is turned on.
4373 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4374 * tree. Newer qemu binaries with that qemu fix would not need this
4377 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4378 var
->type
|= 0x1; /* Accessed */
4380 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4383 vmx
->emulation_required
= emulation_required(vcpu
);
4386 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4388 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4390 *db
= (ar
>> 14) & 1;
4391 *l
= (ar
>> 13) & 1;
4394 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4396 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4397 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4400 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4402 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4403 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4406 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4408 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4409 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4412 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4414 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4415 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4418 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4420 struct kvm_segment var
;
4423 vmx_get_segment(vcpu
, &var
, seg
);
4425 if (seg
== VCPU_SREG_CS
)
4427 ar
= vmx_segment_access_rights(&var
);
4429 if (var
.base
!= (var
.selector
<< 4))
4431 if (var
.limit
!= 0xffff)
4439 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4441 struct kvm_segment cs
;
4442 unsigned int cs_rpl
;
4444 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4445 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4449 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4453 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4454 if (cs
.dpl
> cs_rpl
)
4457 if (cs
.dpl
!= cs_rpl
)
4463 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4467 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4469 struct kvm_segment ss
;
4470 unsigned int ss_rpl
;
4472 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4473 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4477 if (ss
.type
!= 3 && ss
.type
!= 7)
4481 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4489 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4491 struct kvm_segment var
;
4494 vmx_get_segment(vcpu
, &var
, seg
);
4495 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4503 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4504 if (var
.dpl
< rpl
) /* DPL < RPL */
4508 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4514 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4516 struct kvm_segment tr
;
4518 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4522 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4524 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4532 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4534 struct kvm_segment ldtr
;
4536 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4540 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4550 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4552 struct kvm_segment cs
, ss
;
4554 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4555 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4557 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4558 (ss
.selector
& SEGMENT_RPL_MASK
));
4562 * Check if guest state is valid. Returns true if valid, false if
4564 * We assume that registers are always usable
4566 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4568 if (enable_unrestricted_guest
)
4571 /* real mode guest state checks */
4572 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4573 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4575 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4577 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4579 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4581 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4583 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4586 /* protected mode guest state checks */
4587 if (!cs_ss_rpl_check(vcpu
))
4589 if (!code_segment_valid(vcpu
))
4591 if (!stack_segment_valid(vcpu
))
4593 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4595 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4597 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4599 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4601 if (!tr_valid(vcpu
))
4603 if (!ldtr_valid(vcpu
))
4607 * - Add checks on RIP
4608 * - Add checks on RFLAGS
4614 static int init_rmode_tss(struct kvm
*kvm
)
4620 idx
= srcu_read_lock(&kvm
->srcu
);
4621 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4622 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4625 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4626 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4627 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4630 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4633 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4637 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4638 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4641 srcu_read_unlock(&kvm
->srcu
, idx
);
4645 static int init_rmode_identity_map(struct kvm
*kvm
)
4648 kvm_pfn_t identity_map_pfn
;
4654 /* Protect kvm->arch.ept_identity_pagetable_done. */
4655 mutex_lock(&kvm
->slots_lock
);
4657 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4660 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4662 r
= alloc_identity_pagetable(kvm
);
4666 idx
= srcu_read_lock(&kvm
->srcu
);
4667 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4670 /* Set up identity-mapping pagetable for EPT in real mode */
4671 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4672 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4673 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4674 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4675 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4679 kvm
->arch
.ept_identity_pagetable_done
= true;
4682 srcu_read_unlock(&kvm
->srcu
, idx
);
4685 mutex_unlock(&kvm
->slots_lock
);
4689 static void seg_setup(int seg
)
4691 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4694 vmcs_write16(sf
->selector
, 0);
4695 vmcs_writel(sf
->base
, 0);
4696 vmcs_write32(sf
->limit
, 0xffff);
4698 if (seg
== VCPU_SREG_CS
)
4699 ar
|= 0x08; /* code segment */
4701 vmcs_write32(sf
->ar_bytes
, ar
);
4704 static int alloc_apic_access_page(struct kvm
*kvm
)
4709 mutex_lock(&kvm
->slots_lock
);
4710 if (kvm
->arch
.apic_access_page_done
)
4712 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4713 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4717 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4718 if (is_error_page(page
)) {
4724 * Do not pin the page in memory, so that memory hot-unplug
4725 * is able to migrate it.
4728 kvm
->arch
.apic_access_page_done
= true;
4730 mutex_unlock(&kvm
->slots_lock
);
4734 static int alloc_identity_pagetable(struct kvm
*kvm
)
4736 /* Called with kvm->slots_lock held. */
4740 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4742 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4743 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4748 static int allocate_vpid(void)
4754 spin_lock(&vmx_vpid_lock
);
4755 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4756 if (vpid
< VMX_NR_VPIDS
)
4757 __set_bit(vpid
, vmx_vpid_bitmap
);
4760 spin_unlock(&vmx_vpid_lock
);
4764 static void free_vpid(int vpid
)
4766 if (!enable_vpid
|| vpid
== 0)
4768 spin_lock(&vmx_vpid_lock
);
4769 __clear_bit(vpid
, vmx_vpid_bitmap
);
4770 spin_unlock(&vmx_vpid_lock
);
4773 #define MSR_TYPE_R 1
4774 #define MSR_TYPE_W 2
4775 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4778 int f
= sizeof(unsigned long);
4780 if (!cpu_has_vmx_msr_bitmap())
4784 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4785 * have the write-low and read-high bitmap offsets the wrong way round.
4786 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4788 if (msr
<= 0x1fff) {
4789 if (type
& MSR_TYPE_R
)
4791 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4793 if (type
& MSR_TYPE_W
)
4795 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4797 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4799 if (type
& MSR_TYPE_R
)
4801 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4803 if (type
& MSR_TYPE_W
)
4805 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4811 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4812 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4814 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4815 unsigned long *msr_bitmap_nested
,
4818 int f
= sizeof(unsigned long);
4820 if (!cpu_has_vmx_msr_bitmap()) {
4826 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4827 * have the write-low and read-high bitmap offsets the wrong way round.
4828 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4830 if (msr
<= 0x1fff) {
4831 if (type
& MSR_TYPE_R
&&
4832 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4834 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4836 if (type
& MSR_TYPE_W
&&
4837 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4839 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4841 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4843 if (type
& MSR_TYPE_R
&&
4844 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4846 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4848 if (type
& MSR_TYPE_W
&&
4849 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4851 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4856 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4859 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4860 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4861 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4862 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4865 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4868 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4870 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4873 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4875 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4880 static bool vmx_get_enable_apicv(void)
4882 return enable_apicv
;
4885 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4887 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4892 if (vmx
->nested
.pi_desc
&&
4893 vmx
->nested
.pi_pending
) {
4894 vmx
->nested
.pi_pending
= false;
4895 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4898 max_irr
= find_last_bit(
4899 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4904 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4905 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4906 kunmap(vmx
->nested
.virtual_apic_page
);
4908 status
= vmcs_read16(GUEST_INTR_STATUS
);
4909 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4911 status
|= (u8
)max_irr
;
4912 vmcs_write16(GUEST_INTR_STATUS
, status
);
4917 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4920 if (vcpu
->mode
== IN_GUEST_MODE
) {
4921 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4924 * Currently, we don't support urgent interrupt,
4925 * all interrupts are recognized as non-urgent
4926 * interrupt, so we cannot post interrupts when
4929 * If the vcpu is in guest mode, it means it is
4930 * running instead of being scheduled out and
4931 * waiting in the run queue, and that's the only
4932 * case when 'SN' is set currently, warning if
4935 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4937 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4938 POSTED_INTR_VECTOR
);
4945 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4948 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4950 if (is_guest_mode(vcpu
) &&
4951 vector
== vmx
->nested
.posted_intr_nv
) {
4952 /* the PIR and ON have been set by L1. */
4953 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4955 * If a posted intr is not recognized by hardware,
4956 * we will accomplish it in the next vmentry.
4958 vmx
->nested
.pi_pending
= true;
4959 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4965 * Send interrupt to vcpu via posted interrupt way.
4966 * 1. If target vcpu is running(non-root mode), send posted interrupt
4967 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4968 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4969 * interrupt from PIR in next vmentry.
4971 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4973 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4976 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4980 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4983 /* If a previous notification has sent the IPI, nothing to do. */
4984 if (pi_test_and_set_on(&vmx
->pi_desc
))
4987 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
))
4988 kvm_vcpu_kick(vcpu
);
4992 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4993 * will not change in the lifetime of the guest.
4994 * Note that host-state that does change is set elsewhere. E.g., host-state
4995 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4997 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5002 unsigned long cr0
, cr4
;
5005 WARN_ON(cr0
& X86_CR0_TS
);
5006 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5007 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
5009 /* Save the most likely value for this task's CR4 in the VMCS. */
5010 cr4
= cr4_read_shadow();
5011 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5012 vmx
->host_state
.vmcs_host_cr4
= cr4
;
5014 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5015 #ifdef CONFIG_X86_64
5017 * Load null selectors, so we can avoid reloading them in
5018 * __vmx_load_host_state(), in case userspace uses the null selectors
5019 * too (the expected case).
5021 vmcs_write16(HOST_DS_SELECTOR
, 0);
5022 vmcs_write16(HOST_ES_SELECTOR
, 0);
5024 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5025 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5027 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5028 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5030 native_store_idt(&dt
);
5031 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5032 vmx
->host_idt_base
= dt
.address
;
5034 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5036 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5037 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5038 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5039 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5041 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5042 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5043 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5047 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5049 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5051 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5052 if (is_guest_mode(&vmx
->vcpu
))
5053 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5054 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5055 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5058 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5060 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5062 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5063 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5064 /* Enable the preemption timer dynamically */
5065 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5066 return pin_based_exec_ctrl
;
5069 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5071 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5073 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5074 if (cpu_has_secondary_exec_ctrls()) {
5075 if (kvm_vcpu_apicv_active(vcpu
))
5076 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5077 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5078 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5080 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5081 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5082 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5085 if (cpu_has_vmx_msr_bitmap())
5086 vmx_set_msr_bitmap(vcpu
);
5089 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5091 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5093 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5094 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5096 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5097 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5098 #ifdef CONFIG_X86_64
5099 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5100 CPU_BASED_CR8_LOAD_EXITING
;
5104 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5105 CPU_BASED_CR3_LOAD_EXITING
|
5106 CPU_BASED_INVLPG_EXITING
;
5107 return exec_control
;
5110 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5112 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5113 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5114 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5116 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5118 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5119 enable_unrestricted_guest
= 0;
5120 /* Enable INVPCID for non-ept guests may cause performance regression. */
5121 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5123 if (!enable_unrestricted_guest
)
5124 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5126 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5127 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5128 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5129 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5130 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5131 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5133 We can NOT enable shadow_vmcs here because we don't have yet
5136 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5139 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5141 return exec_control
;
5144 static void ept_set_mmio_spte_mask(void)
5147 * EPT Misconfigurations can be generated if the value of bits 2:0
5148 * of an EPT paging-structure entry is 110b (write/execute).
5150 kvm_mmu_set_mmio_spte_mask(VMX_EPT_MISCONFIG_WX_VALUE
);
5153 #define VMX_XSS_EXIT_BITMAP 0
5155 * Sets up the vmcs for emulated real mode.
5157 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5159 #ifdef CONFIG_X86_64
5165 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5166 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5168 if (enable_shadow_vmcs
) {
5169 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5170 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5172 if (cpu_has_vmx_msr_bitmap())
5173 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5175 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5178 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5179 vmx
->hv_deadline_tsc
= -1;
5181 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5183 if (cpu_has_secondary_exec_ctrls()) {
5184 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5185 vmx_secondary_exec_control(vmx
));
5188 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5189 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5190 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5191 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5192 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5194 vmcs_write16(GUEST_INTR_STATUS
, 0);
5196 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5197 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5201 vmcs_write32(PLE_GAP
, ple_gap
);
5202 vmx
->ple_window
= ple_window
;
5203 vmx
->ple_window_dirty
= true;
5206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5207 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5208 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5210 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5211 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5212 vmx_set_constant_host_state(vmx
);
5213 #ifdef CONFIG_X86_64
5214 rdmsrl(MSR_FS_BASE
, a
);
5215 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5216 rdmsrl(MSR_GS_BASE
, a
);
5217 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5219 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5220 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5223 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5224 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5225 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5226 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5227 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5229 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5230 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5232 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5233 u32 index
= vmx_msr_index
[i
];
5234 u32 data_low
, data_high
;
5237 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5239 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5241 vmx
->guest_msrs
[j
].index
= i
;
5242 vmx
->guest_msrs
[j
].data
= 0;
5243 vmx
->guest_msrs
[j
].mask
= -1ull;
5248 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5250 /* 22.2.1, 20.8.1 */
5251 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5253 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5254 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5256 set_cr4_guest_host_mask(vmx
);
5258 if (vmx_xsaves_supported())
5259 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5262 ASSERT(vmx
->pml_pg
);
5263 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5264 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5270 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5272 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5273 struct msr_data apic_base_msr
;
5276 vmx
->rmode
.vm86_active
= 0;
5278 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5279 kvm_set_cr8(vcpu
, 0);
5282 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5283 MSR_IA32_APICBASE_ENABLE
;
5284 if (kvm_vcpu_is_reset_bsp(vcpu
))
5285 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5286 apic_base_msr
.host_initiated
= true;
5287 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5290 vmx_segment_cache_clear(vmx
);
5292 seg_setup(VCPU_SREG_CS
);
5293 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5294 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5296 seg_setup(VCPU_SREG_DS
);
5297 seg_setup(VCPU_SREG_ES
);
5298 seg_setup(VCPU_SREG_FS
);
5299 seg_setup(VCPU_SREG_GS
);
5300 seg_setup(VCPU_SREG_SS
);
5302 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5303 vmcs_writel(GUEST_TR_BASE
, 0);
5304 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5305 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5307 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5308 vmcs_writel(GUEST_LDTR_BASE
, 0);
5309 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5310 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5313 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5314 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5315 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5316 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5319 vmcs_writel(GUEST_RFLAGS
, 0x02);
5320 kvm_rip_write(vcpu
, 0xfff0);
5322 vmcs_writel(GUEST_GDTR_BASE
, 0);
5323 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5325 vmcs_writel(GUEST_IDTR_BASE
, 0);
5326 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5328 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5329 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5330 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5334 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5336 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5337 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5338 if (cpu_need_tpr_shadow(vcpu
))
5339 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5340 __pa(vcpu
->arch
.apic
->regs
));
5341 vmcs_write32(TPR_THRESHOLD
, 0);
5344 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5346 if (kvm_vcpu_apicv_active(vcpu
))
5347 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5350 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5352 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5353 vmx
->vcpu
.arch
.cr0
= cr0
;
5354 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5355 vmx_set_cr4(vcpu
, 0);
5356 vmx_set_efer(vcpu
, 0);
5358 update_exception_bitmap(vcpu
);
5360 vpid_sync_context(vmx
->vpid
);
5364 * In nested virtualization, check if L1 asked to exit on external interrupts.
5365 * For most existing hypervisors, this will always return true.
5367 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5369 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5370 PIN_BASED_EXT_INTR_MASK
;
5374 * In nested virtualization, check if L1 has set
5375 * VM_EXIT_ACK_INTR_ON_EXIT
5377 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5379 return get_vmcs12(vcpu
)->vm_exit_controls
&
5380 VM_EXIT_ACK_INTR_ON_EXIT
;
5383 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5385 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5386 PIN_BASED_NMI_EXITING
;
5389 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5391 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5392 CPU_BASED_VIRTUAL_INTR_PENDING
);
5395 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5397 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5398 enable_irq_window(vcpu
);
5402 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5403 CPU_BASED_VIRTUAL_NMI_PENDING
);
5406 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5408 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5410 int irq
= vcpu
->arch
.interrupt
.nr
;
5412 trace_kvm_inj_virq(irq
);
5414 ++vcpu
->stat
.irq_injections
;
5415 if (vmx
->rmode
.vm86_active
) {
5417 if (vcpu
->arch
.interrupt
.soft
)
5418 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5419 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5420 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5423 intr
= irq
| INTR_INFO_VALID_MASK
;
5424 if (vcpu
->arch
.interrupt
.soft
) {
5425 intr
|= INTR_TYPE_SOFT_INTR
;
5426 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5427 vmx
->vcpu
.arch
.event_exit_inst_len
);
5429 intr
|= INTR_TYPE_EXT_INTR
;
5430 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5433 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5435 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5437 if (!is_guest_mode(vcpu
)) {
5438 ++vcpu
->stat
.nmi_injections
;
5439 vmx
->nmi_known_unmasked
= false;
5442 if (vmx
->rmode
.vm86_active
) {
5443 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5444 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5448 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5449 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5452 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5454 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5456 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5459 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5461 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5463 vmx
->nmi_known_unmasked
= !masked
;
5465 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5466 GUEST_INTR_STATE_NMI
);
5468 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5469 GUEST_INTR_STATE_NMI
);
5472 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5474 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5477 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5478 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5479 | GUEST_INTR_STATE_NMI
));
5482 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5484 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5485 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5486 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5487 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5490 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5494 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5498 kvm
->arch
.tss_addr
= addr
;
5499 return init_rmode_tss(kvm
);
5502 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5507 * Update instruction length as we may reinject the exception
5508 * from user space while in guest debugging mode.
5510 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5511 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5512 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5516 if (vcpu
->guest_debug
&
5517 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5534 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5535 int vec
, u32 err_code
)
5538 * Instruction with address size override prefix opcode 0x67
5539 * Cause the #SS fault with 0 error code in VM86 mode.
5541 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5542 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5543 if (vcpu
->arch
.halt_request
) {
5544 vcpu
->arch
.halt_request
= 0;
5545 return kvm_vcpu_halt(vcpu
);
5553 * Forward all other exceptions that are valid in real mode.
5554 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5555 * the required debugging infrastructure rework.
5557 kvm_queue_exception(vcpu
, vec
);
5562 * Trigger machine check on the host. We assume all the MSRs are already set up
5563 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5564 * We pass a fake environment to the machine check handler because we want
5565 * the guest to be always treated like user space, no matter what context
5566 * it used internally.
5568 static void kvm_machine_check(void)
5570 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5571 struct pt_regs regs
= {
5572 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5573 .flags
= X86_EFLAGS_IF
,
5576 do_machine_check(®s
, 0);
5580 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5582 /* already handled by vcpu_run */
5586 static int handle_exception(struct kvm_vcpu
*vcpu
)
5588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5589 struct kvm_run
*kvm_run
= vcpu
->run
;
5590 u32 intr_info
, ex_no
, error_code
;
5591 unsigned long cr2
, rip
, dr6
;
5593 enum emulation_result er
;
5595 vect_info
= vmx
->idt_vectoring_info
;
5596 intr_info
= vmx
->exit_intr_info
;
5598 if (is_machine_check(intr_info
))
5599 return handle_machine_check(vcpu
);
5601 if (is_nmi(intr_info
))
5602 return 1; /* already handled by vmx_vcpu_run() */
5604 if (is_invalid_opcode(intr_info
)) {
5605 if (is_guest_mode(vcpu
)) {
5606 kvm_queue_exception(vcpu
, UD_VECTOR
);
5609 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5610 if (er
!= EMULATE_DONE
)
5611 kvm_queue_exception(vcpu
, UD_VECTOR
);
5616 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5617 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5620 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5621 * MMIO, it is better to report an internal error.
5622 * See the comments in vmx_handle_exit.
5624 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5625 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5626 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5627 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5628 vcpu
->run
->internal
.ndata
= 3;
5629 vcpu
->run
->internal
.data
[0] = vect_info
;
5630 vcpu
->run
->internal
.data
[1] = intr_info
;
5631 vcpu
->run
->internal
.data
[2] = error_code
;
5635 if (is_page_fault(intr_info
)) {
5636 /* EPT won't cause page fault directly */
5638 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5639 trace_kvm_page_fault(cr2
, error_code
);
5641 if (kvm_event_needs_reinjection(vcpu
))
5642 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5643 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5646 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5648 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5649 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5653 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5656 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5657 if (!(vcpu
->guest_debug
&
5658 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5659 vcpu
->arch
.dr6
&= ~15;
5660 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5661 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5662 skip_emulated_instruction(vcpu
);
5664 kvm_queue_exception(vcpu
, DB_VECTOR
);
5667 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5668 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5672 * Update instruction length as we may reinject #BP from
5673 * user space while in guest debugging mode. Reading it for
5674 * #DB as well causes no harm, it is not used in that case.
5676 vmx
->vcpu
.arch
.event_exit_inst_len
=
5677 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5678 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5679 rip
= kvm_rip_read(vcpu
);
5680 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5681 kvm_run
->debug
.arch
.exception
= ex_no
;
5684 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5685 kvm_run
->ex
.exception
= ex_no
;
5686 kvm_run
->ex
.error_code
= error_code
;
5692 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5694 ++vcpu
->stat
.irq_exits
;
5698 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5700 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5704 static int handle_io(struct kvm_vcpu
*vcpu
)
5706 unsigned long exit_qualification
;
5707 int size
, in
, string
, ret
;
5710 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5711 string
= (exit_qualification
& 16) != 0;
5712 in
= (exit_qualification
& 8) != 0;
5714 ++vcpu
->stat
.io_exits
;
5717 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5719 port
= exit_qualification
>> 16;
5720 size
= (exit_qualification
& 7) + 1;
5722 ret
= kvm_skip_emulated_instruction(vcpu
);
5725 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5726 * KVM_EXIT_DEBUG here.
5728 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5732 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5735 * Patch in the VMCALL instruction:
5737 hypercall
[0] = 0x0f;
5738 hypercall
[1] = 0x01;
5739 hypercall
[2] = 0xc1;
5742 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5743 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5745 if (is_guest_mode(vcpu
)) {
5746 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5747 unsigned long orig_val
= val
;
5750 * We get here when L2 changed cr0 in a way that did not change
5751 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5752 * but did change L0 shadowed bits. So we first calculate the
5753 * effective cr0 value that L1 would like to write into the
5754 * hardware. It consists of the L2-owned bits from the new
5755 * value combined with the L1-owned bits from L1's guest_cr0.
5757 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5758 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5760 if (!nested_guest_cr0_valid(vcpu
, val
))
5763 if (kvm_set_cr0(vcpu
, val
))
5765 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5768 if (to_vmx(vcpu
)->nested
.vmxon
&&
5769 !nested_host_cr0_valid(vcpu
, val
))
5772 return kvm_set_cr0(vcpu
, val
);
5776 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5778 if (is_guest_mode(vcpu
)) {
5779 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5780 unsigned long orig_val
= val
;
5782 /* analogously to handle_set_cr0 */
5783 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5784 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5785 if (kvm_set_cr4(vcpu
, val
))
5787 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5790 return kvm_set_cr4(vcpu
, val
);
5793 static int handle_cr(struct kvm_vcpu
*vcpu
)
5795 unsigned long exit_qualification
, val
;
5801 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5802 cr
= exit_qualification
& 15;
5803 reg
= (exit_qualification
>> 8) & 15;
5804 switch ((exit_qualification
>> 4) & 3) {
5805 case 0: /* mov to cr */
5806 val
= kvm_register_readl(vcpu
, reg
);
5807 trace_kvm_cr_write(cr
, val
);
5810 err
= handle_set_cr0(vcpu
, val
);
5811 return kvm_complete_insn_gp(vcpu
, err
);
5813 err
= kvm_set_cr3(vcpu
, val
);
5814 return kvm_complete_insn_gp(vcpu
, err
);
5816 err
= handle_set_cr4(vcpu
, val
);
5817 return kvm_complete_insn_gp(vcpu
, err
);
5819 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5821 err
= kvm_set_cr8(vcpu
, cr8
);
5822 ret
= kvm_complete_insn_gp(vcpu
, err
);
5823 if (lapic_in_kernel(vcpu
))
5825 if (cr8_prev
<= cr8
)
5828 * TODO: we might be squashing a
5829 * KVM_GUESTDBG_SINGLESTEP-triggered
5830 * KVM_EXIT_DEBUG here.
5832 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5838 WARN_ONCE(1, "Guest should always own CR0.TS");
5839 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5840 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5841 return kvm_skip_emulated_instruction(vcpu
);
5842 case 1: /*mov from cr*/
5845 val
= kvm_read_cr3(vcpu
);
5846 kvm_register_write(vcpu
, reg
, val
);
5847 trace_kvm_cr_read(cr
, val
);
5848 return kvm_skip_emulated_instruction(vcpu
);
5850 val
= kvm_get_cr8(vcpu
);
5851 kvm_register_write(vcpu
, reg
, val
);
5852 trace_kvm_cr_read(cr
, val
);
5853 return kvm_skip_emulated_instruction(vcpu
);
5857 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5858 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5859 kvm_lmsw(vcpu
, val
);
5861 return kvm_skip_emulated_instruction(vcpu
);
5865 vcpu
->run
->exit_reason
= 0;
5866 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5867 (int)(exit_qualification
>> 4) & 3, cr
);
5871 static int handle_dr(struct kvm_vcpu
*vcpu
)
5873 unsigned long exit_qualification
;
5876 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5877 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5879 /* First, if DR does not exist, trigger UD */
5880 if (!kvm_require_dr(vcpu
, dr
))
5883 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5884 if (!kvm_require_cpl(vcpu
, 0))
5886 dr7
= vmcs_readl(GUEST_DR7
);
5889 * As the vm-exit takes precedence over the debug trap, we
5890 * need to emulate the latter, either for the host or the
5891 * guest debugging itself.
5893 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5894 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5895 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5896 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5897 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5898 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5901 vcpu
->arch
.dr6
&= ~15;
5902 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5903 kvm_queue_exception(vcpu
, DB_VECTOR
);
5908 if (vcpu
->guest_debug
== 0) {
5909 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5910 CPU_BASED_MOV_DR_EXITING
);
5913 * No more DR vmexits; force a reload of the debug registers
5914 * and reenter on this instruction. The next vmexit will
5915 * retrieve the full state of the debug registers.
5917 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5921 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5922 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5925 if (kvm_get_dr(vcpu
, dr
, &val
))
5927 kvm_register_write(vcpu
, reg
, val
);
5929 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5932 return kvm_skip_emulated_instruction(vcpu
);
5935 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5937 return vcpu
->arch
.dr6
;
5940 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5944 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5946 get_debugreg(vcpu
->arch
.db
[0], 0);
5947 get_debugreg(vcpu
->arch
.db
[1], 1);
5948 get_debugreg(vcpu
->arch
.db
[2], 2);
5949 get_debugreg(vcpu
->arch
.db
[3], 3);
5950 get_debugreg(vcpu
->arch
.dr6
, 6);
5951 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5953 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5954 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5957 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5959 vmcs_writel(GUEST_DR7
, val
);
5962 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5964 return kvm_emulate_cpuid(vcpu
);
5967 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5969 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5970 struct msr_data msr_info
;
5972 msr_info
.index
= ecx
;
5973 msr_info
.host_initiated
= false;
5974 if (vmx_get_msr(vcpu
, &msr_info
)) {
5975 trace_kvm_msr_read_ex(ecx
);
5976 kvm_inject_gp(vcpu
, 0);
5980 trace_kvm_msr_read(ecx
, msr_info
.data
);
5982 /* FIXME: handling of bits 32:63 of rax, rdx */
5983 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5984 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5985 return kvm_skip_emulated_instruction(vcpu
);
5988 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5990 struct msr_data msr
;
5991 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5992 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5993 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5997 msr
.host_initiated
= false;
5998 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5999 trace_kvm_msr_write_ex(ecx
, data
);
6000 kvm_inject_gp(vcpu
, 0);
6004 trace_kvm_msr_write(ecx
, data
);
6005 return kvm_skip_emulated_instruction(vcpu
);
6008 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6010 kvm_apic_update_ppr(vcpu
);
6014 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6016 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6017 CPU_BASED_VIRTUAL_INTR_PENDING
);
6019 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6021 ++vcpu
->stat
.irq_window_exits
;
6025 static int handle_halt(struct kvm_vcpu
*vcpu
)
6027 return kvm_emulate_halt(vcpu
);
6030 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6032 return kvm_emulate_hypercall(vcpu
);
6035 static int handle_invd(struct kvm_vcpu
*vcpu
)
6037 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6040 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6042 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6044 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6045 return kvm_skip_emulated_instruction(vcpu
);
6048 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6052 err
= kvm_rdpmc(vcpu
);
6053 return kvm_complete_insn_gp(vcpu
, err
);
6056 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6058 return kvm_emulate_wbinvd(vcpu
);
6061 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6063 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6064 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6066 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6067 return kvm_skip_emulated_instruction(vcpu
);
6071 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6073 kvm_skip_emulated_instruction(vcpu
);
6074 WARN(1, "this should never happen\n");
6078 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6080 kvm_skip_emulated_instruction(vcpu
);
6081 WARN(1, "this should never happen\n");
6085 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6087 if (likely(fasteoi
)) {
6088 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6089 int access_type
, offset
;
6091 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6092 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6094 * Sane guest uses MOV to write EOI, with written value
6095 * not cared. So make a short-circuit here by avoiding
6096 * heavy instruction emulation.
6098 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6099 (offset
== APIC_EOI
)) {
6100 kvm_lapic_set_eoi(vcpu
);
6101 return kvm_skip_emulated_instruction(vcpu
);
6104 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6107 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6109 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6110 int vector
= exit_qualification
& 0xff;
6112 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6113 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6117 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6119 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6120 u32 offset
= exit_qualification
& 0xfff;
6122 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6123 kvm_apic_write_nodecode(vcpu
, offset
);
6127 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6129 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6130 unsigned long exit_qualification
;
6131 bool has_error_code
= false;
6134 int reason
, type
, idt_v
, idt_index
;
6136 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6137 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6138 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6140 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6142 reason
= (u32
)exit_qualification
>> 30;
6143 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6145 case INTR_TYPE_NMI_INTR
:
6146 vcpu
->arch
.nmi_injected
= false;
6147 vmx_set_nmi_mask(vcpu
, true);
6149 case INTR_TYPE_EXT_INTR
:
6150 case INTR_TYPE_SOFT_INTR
:
6151 kvm_clear_interrupt_queue(vcpu
);
6153 case INTR_TYPE_HARD_EXCEPTION
:
6154 if (vmx
->idt_vectoring_info
&
6155 VECTORING_INFO_DELIVER_CODE_MASK
) {
6156 has_error_code
= true;
6158 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6161 case INTR_TYPE_SOFT_EXCEPTION
:
6162 kvm_clear_exception_queue(vcpu
);
6168 tss_selector
= exit_qualification
;
6170 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6171 type
!= INTR_TYPE_EXT_INTR
&&
6172 type
!= INTR_TYPE_NMI_INTR
))
6173 skip_emulated_instruction(vcpu
);
6175 if (kvm_task_switch(vcpu
, tss_selector
,
6176 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6177 has_error_code
, error_code
) == EMULATE_FAIL
) {
6178 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6179 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6180 vcpu
->run
->internal
.ndata
= 0;
6185 * TODO: What about debug traps on tss switch?
6186 * Are we supposed to inject them and update dr6?
6192 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6194 unsigned long exit_qualification
;
6198 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6200 if (is_guest_mode(vcpu
)
6201 && !(exit_qualification
& EPT_VIOLATION_GVA_TRANSLATED
)) {
6203 * Fix up exit_qualification according to whether guest
6204 * page table accesses are reads or writes.
6206 u64 eptp
= nested_ept_get_cr3(vcpu
);
6207 if (!(eptp
& VMX_EPT_AD_ENABLE_BIT
))
6208 exit_qualification
&= ~EPT_VIOLATION_ACC_WRITE
;
6212 * EPT violation happened while executing iret from NMI,
6213 * "blocked by NMI" bit has to be set before next VM entry.
6214 * There are errata that may cause this bit to not be set:
6217 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6218 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6219 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6221 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6222 trace_kvm_page_fault(gpa
, exit_qualification
);
6224 /* Is it a read fault? */
6225 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6226 ? PFERR_USER_MASK
: 0;
6227 /* Is it a write fault? */
6228 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6229 ? PFERR_WRITE_MASK
: 0;
6230 /* Is it a fetch fault? */
6231 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6232 ? PFERR_FETCH_MASK
: 0;
6233 /* ept page table entry is present? */
6234 error_code
|= (exit_qualification
&
6235 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6236 EPT_VIOLATION_EXECUTABLE
))
6237 ? PFERR_PRESENT_MASK
: 0;
6239 vcpu
->arch
.gpa_available
= true;
6240 vcpu
->arch
.exit_qualification
= exit_qualification
;
6242 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6245 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6250 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6251 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6252 trace_kvm_fast_mmio(gpa
);
6253 return kvm_skip_emulated_instruction(vcpu
);
6256 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6257 vcpu
->arch
.gpa_available
= true;
6258 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6259 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6262 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6263 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6265 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6268 /* It is the real ept misconfig */
6271 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6272 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6277 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6279 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6280 CPU_BASED_VIRTUAL_NMI_PENDING
);
6281 ++vcpu
->stat
.nmi_window_exits
;
6282 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6287 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6289 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6290 enum emulation_result err
= EMULATE_DONE
;
6293 bool intr_window_requested
;
6294 unsigned count
= 130;
6296 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6297 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6299 while (vmx
->emulation_required
&& count
-- != 0) {
6300 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6301 return handle_interrupt_window(&vmx
->vcpu
);
6303 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6306 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6308 if (err
== EMULATE_USER_EXIT
) {
6309 ++vcpu
->stat
.mmio_exits
;
6314 if (err
!= EMULATE_DONE
) {
6315 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6316 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6317 vcpu
->run
->internal
.ndata
= 0;
6321 if (vcpu
->arch
.halt_request
) {
6322 vcpu
->arch
.halt_request
= 0;
6323 ret
= kvm_vcpu_halt(vcpu
);
6327 if (signal_pending(current
))
6337 static int __grow_ple_window(int val
)
6339 if (ple_window_grow
< 1)
6342 val
= min(val
, ple_window_actual_max
);
6344 if (ple_window_grow
< ple_window
)
6345 val
*= ple_window_grow
;
6347 val
+= ple_window_grow
;
6352 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6357 if (modifier
< ple_window
)
6362 return max(val
, minimum
);
6365 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6367 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6368 int old
= vmx
->ple_window
;
6370 vmx
->ple_window
= __grow_ple_window(old
);
6372 if (vmx
->ple_window
!= old
)
6373 vmx
->ple_window_dirty
= true;
6375 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6378 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6380 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6381 int old
= vmx
->ple_window
;
6383 vmx
->ple_window
= __shrink_ple_window(old
,
6384 ple_window_shrink
, ple_window
);
6386 if (vmx
->ple_window
!= old
)
6387 vmx
->ple_window_dirty
= true;
6389 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6393 * ple_window_actual_max is computed to be one grow_ple_window() below
6394 * ple_window_max. (See __grow_ple_window for the reason.)
6395 * This prevents overflows, because ple_window_max is int.
6396 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6398 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6400 static void update_ple_window_actual_max(void)
6402 ple_window_actual_max
=
6403 __shrink_ple_window(max(ple_window_max
, ple_window
),
6404 ple_window_grow
, INT_MIN
);
6408 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6410 static void wakeup_handler(void)
6412 struct kvm_vcpu
*vcpu
;
6413 int cpu
= smp_processor_id();
6415 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6416 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6417 blocked_vcpu_list
) {
6418 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6420 if (pi_test_on(pi_desc
) == 1)
6421 kvm_vcpu_kick(vcpu
);
6423 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6426 void vmx_enable_tdp(void)
6428 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6429 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6430 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6431 0ull, VMX_EPT_EXECUTABLE_MASK
,
6432 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6433 enable_ept_ad_bits
? 0ull : VMX_EPT_RWX_MASK
);
6435 ept_set_mmio_spte_mask();
6439 static __init
int hardware_setup(void)
6441 int r
= -ENOMEM
, i
, msr
;
6443 rdmsrl_safe(MSR_EFER
, &host_efer
);
6445 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6446 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6448 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6449 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6454 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6455 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6456 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6459 * Allow direct access to the PC debug port (it is often used for I/O
6460 * delays, but the vmexits simply slow things down).
6462 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6463 clear_bit(0x80, vmx_io_bitmap_a
);
6465 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6467 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6468 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6470 if (setup_vmcs_config(&vmcs_config
) < 0) {
6475 if (boot_cpu_has(X86_FEATURE_NX
))
6476 kvm_enable_efer_bits(EFER_NX
);
6478 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6479 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6482 if (!cpu_has_vmx_shadow_vmcs())
6483 enable_shadow_vmcs
= 0;
6484 if (enable_shadow_vmcs
)
6485 init_vmcs_shadow_fields();
6487 if (!cpu_has_vmx_ept() ||
6488 !cpu_has_vmx_ept_4levels()) {
6490 enable_unrestricted_guest
= 0;
6491 enable_ept_ad_bits
= 0;
6494 if (!cpu_has_vmx_ept_ad_bits())
6495 enable_ept_ad_bits
= 0;
6497 if (!cpu_has_vmx_unrestricted_guest())
6498 enable_unrestricted_guest
= 0;
6500 if (!cpu_has_vmx_flexpriority())
6501 flexpriority_enabled
= 0;
6504 * set_apic_access_page_addr() is used to reload apic access
6505 * page upon invalidation. No need to do anything if not
6506 * using the APIC_ACCESS_ADDR VMCS field.
6508 if (!flexpriority_enabled
)
6509 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6511 if (!cpu_has_vmx_tpr_shadow())
6512 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6514 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6515 kvm_disable_largepages();
6517 if (!cpu_has_vmx_ple())
6520 if (!cpu_has_vmx_apicv()) {
6522 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6525 if (cpu_has_vmx_tsc_scaling()) {
6526 kvm_has_tsc_control
= true;
6527 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6528 kvm_tsc_scaling_ratio_frac_bits
= 48;
6531 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6532 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6533 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6534 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6535 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6536 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6537 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6539 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6540 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6541 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6542 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6543 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6544 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6545 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6546 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6548 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6550 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6551 if (msr
== 0x839 /* TMCCT */)
6553 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6557 * TPR reads and writes can be virtualized even if virtual interrupt
6558 * delivery is not in use.
6560 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6561 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6564 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6566 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6573 update_ple_window_actual_max();
6576 * Only enable PML when hardware supports PML feature, and both EPT
6577 * and EPT A/D bit features are enabled -- PML depends on them to work.
6579 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6583 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6584 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6585 kvm_x86_ops
->flush_log_dirty
= NULL
;
6586 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6589 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6592 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6593 cpu_preemption_timer_multi
=
6594 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6596 kvm_x86_ops
->set_hv_timer
= NULL
;
6597 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6600 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6602 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6604 return alloc_kvm_area();
6607 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6608 free_page((unsigned long)vmx_bitmap
[i
]);
6613 static __exit
void hardware_unsetup(void)
6617 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6618 free_page((unsigned long)vmx_bitmap
[i
]);
6624 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6625 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6627 static int handle_pause(struct kvm_vcpu
*vcpu
)
6630 grow_ple_window(vcpu
);
6632 kvm_vcpu_on_spin(vcpu
);
6633 return kvm_skip_emulated_instruction(vcpu
);
6636 static int handle_nop(struct kvm_vcpu
*vcpu
)
6638 return kvm_skip_emulated_instruction(vcpu
);
6641 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6643 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6644 return handle_nop(vcpu
);
6647 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6652 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6654 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6655 return handle_nop(vcpu
);
6659 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6660 * We could reuse a single VMCS for all the L2 guests, but we also want the
6661 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6662 * allows keeping them loaded on the processor, and in the future will allow
6663 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6664 * every entry if they never change.
6665 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6666 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6668 * The following functions allocate and free a vmcs02 in this pool.
6671 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6672 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6674 struct vmcs02_list
*item
;
6675 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6676 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6677 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6678 return &item
->vmcs02
;
6681 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6682 /* Recycle the least recently used VMCS. */
6683 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6684 struct vmcs02_list
, list
);
6685 item
->vmptr
= vmx
->nested
.current_vmptr
;
6686 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6687 return &item
->vmcs02
;
6690 /* Create a new VMCS */
6691 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6694 item
->vmcs02
.vmcs
= alloc_vmcs();
6695 item
->vmcs02
.shadow_vmcs
= NULL
;
6696 if (!item
->vmcs02
.vmcs
) {
6700 loaded_vmcs_init(&item
->vmcs02
);
6701 item
->vmptr
= vmx
->nested
.current_vmptr
;
6702 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6703 vmx
->nested
.vmcs02_num
++;
6704 return &item
->vmcs02
;
6707 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6708 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6710 struct vmcs02_list
*item
;
6711 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6712 if (item
->vmptr
== vmptr
) {
6713 free_loaded_vmcs(&item
->vmcs02
);
6714 list_del(&item
->list
);
6716 vmx
->nested
.vmcs02_num
--;
6722 * Free all VMCSs saved for this vcpu, except the one pointed by
6723 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6724 * must be &vmx->vmcs01.
6726 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6728 struct vmcs02_list
*item
, *n
;
6730 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6731 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6733 * Something will leak if the above WARN triggers. Better than
6736 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6739 free_loaded_vmcs(&item
->vmcs02
);
6740 list_del(&item
->list
);
6742 vmx
->nested
.vmcs02_num
--;
6747 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6748 * set the success or error code of an emulated VMX instruction, as specified
6749 * by Vol 2B, VMX Instruction Reference, "Conventions".
6751 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6753 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6754 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6755 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6758 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6760 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6761 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6762 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6766 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6767 u32 vm_instruction_error
)
6769 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6771 * failValid writes the error number to the current VMCS, which
6772 * can't be done there isn't a current VMCS.
6774 nested_vmx_failInvalid(vcpu
);
6777 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6778 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6779 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6781 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6783 * We don't need to force a shadow sync because
6784 * VM_INSTRUCTION_ERROR is not shadowed
6788 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6790 /* TODO: not to reset guest simply here. */
6791 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6792 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6795 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6797 struct vcpu_vmx
*vmx
=
6798 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6800 vmx
->nested
.preemption_timer_expired
= true;
6801 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6802 kvm_vcpu_kick(&vmx
->vcpu
);
6804 return HRTIMER_NORESTART
;
6808 * Decode the memory-address operand of a vmx instruction, as recorded on an
6809 * exit caused by such an instruction (run by a guest hypervisor).
6810 * On success, returns 0. When the operand is invalid, returns 1 and throws
6813 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6814 unsigned long exit_qualification
,
6815 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6819 struct kvm_segment s
;
6822 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6823 * Execution", on an exit, vmx_instruction_info holds most of the
6824 * addressing components of the operand. Only the displacement part
6825 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6826 * For how an actual address is calculated from all these components,
6827 * refer to Vol. 1, "Operand Addressing".
6829 int scaling
= vmx_instruction_info
& 3;
6830 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6831 bool is_reg
= vmx_instruction_info
& (1u << 10);
6832 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6833 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6834 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6835 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6836 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6839 kvm_queue_exception(vcpu
, UD_VECTOR
);
6843 /* Addr = segment_base + offset */
6844 /* offset = base + [index * scale] + displacement */
6845 off
= exit_qualification
; /* holds the displacement */
6847 off
+= kvm_register_read(vcpu
, base_reg
);
6849 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6850 vmx_get_segment(vcpu
, &s
, seg_reg
);
6851 *ret
= s
.base
+ off
;
6853 if (addr_size
== 1) /* 32 bit */
6856 /* Checks for #GP/#SS exceptions. */
6858 if (is_long_mode(vcpu
)) {
6859 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6860 * non-canonical form. This is the only check on the memory
6861 * destination for long mode!
6863 exn
= is_noncanonical_address(*ret
);
6864 } else if (is_protmode(vcpu
)) {
6865 /* Protected mode: apply checks for segment validity in the
6867 * - segment type check (#GP(0) may be thrown)
6868 * - usability check (#GP(0)/#SS(0))
6869 * - limit check (#GP(0)/#SS(0))
6872 /* #GP(0) if the destination operand is located in a
6873 * read-only data segment or any code segment.
6875 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6877 /* #GP(0) if the source operand is located in an
6878 * execute-only code segment
6880 exn
= ((s
.type
& 0xa) == 8);
6882 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6885 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6887 exn
= (s
.unusable
!= 0);
6888 /* Protected mode: #GP(0)/#SS(0) if the memory
6889 * operand is outside the segment limit.
6891 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6894 kvm_queue_exception_e(vcpu
,
6895 seg_reg
== VCPU_SREG_SS
?
6896 SS_VECTOR
: GP_VECTOR
,
6905 * This function performs the various checks including
6906 * - if it's 4KB aligned
6907 * - No bits beyond the physical address width are set
6908 * - Returns 0 on success or else 1
6909 * (Intel SDM Section 30.3)
6911 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6916 struct x86_exception e
;
6918 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6919 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6921 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6922 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6925 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6926 sizeof(vmptr
), &e
)) {
6927 kvm_inject_page_fault(vcpu
, &e
);
6931 switch (exit_reason
) {
6932 case EXIT_REASON_VMON
:
6935 * The first 4 bytes of VMXON region contain the supported
6936 * VMCS revision identifier
6938 * Note - IA32_VMX_BASIC[48] will never be 1
6939 * for the nested case;
6940 * which replaces physical address width with 32
6943 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6944 nested_vmx_failInvalid(vcpu
);
6945 return kvm_skip_emulated_instruction(vcpu
);
6948 page
= nested_get_page(vcpu
, vmptr
);
6950 nested_vmx_failInvalid(vcpu
);
6951 return kvm_skip_emulated_instruction(vcpu
);
6953 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
6955 nested_release_page_clean(page
);
6956 nested_vmx_failInvalid(vcpu
);
6957 return kvm_skip_emulated_instruction(vcpu
);
6960 nested_release_page_clean(page
);
6961 vmx
->nested
.vmxon_ptr
= vmptr
;
6963 case EXIT_REASON_VMCLEAR
:
6964 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6965 nested_vmx_failValid(vcpu
,
6966 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6967 return kvm_skip_emulated_instruction(vcpu
);
6970 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6971 nested_vmx_failValid(vcpu
,
6972 VMXERR_VMCLEAR_VMXON_POINTER
);
6973 return kvm_skip_emulated_instruction(vcpu
);
6976 case EXIT_REASON_VMPTRLD
:
6977 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6978 nested_vmx_failValid(vcpu
,
6979 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6980 return kvm_skip_emulated_instruction(vcpu
);
6983 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6984 nested_vmx_failValid(vcpu
,
6985 VMXERR_VMPTRLD_VMXON_POINTER
);
6986 return kvm_skip_emulated_instruction(vcpu
);
6990 return 1; /* shouldn't happen */
6998 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7000 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7001 struct vmcs
*shadow_vmcs
;
7003 if (cpu_has_vmx_msr_bitmap()) {
7004 vmx
->nested
.msr_bitmap
=
7005 (unsigned long *)__get_free_page(GFP_KERNEL
);
7006 if (!vmx
->nested
.msr_bitmap
)
7007 goto out_msr_bitmap
;
7010 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7011 if (!vmx
->nested
.cached_vmcs12
)
7012 goto out_cached_vmcs12
;
7014 if (enable_shadow_vmcs
) {
7015 shadow_vmcs
= alloc_vmcs();
7017 goto out_shadow_vmcs
;
7018 /* mark vmcs as shadow */
7019 shadow_vmcs
->revision_id
|= (1u << 31);
7020 /* init shadow vmcs */
7021 vmcs_clear(shadow_vmcs
);
7022 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7025 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7026 vmx
->nested
.vmcs02_num
= 0;
7028 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7029 HRTIMER_MODE_REL_PINNED
);
7030 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7032 vmx
->nested
.vmxon
= true;
7036 kfree(vmx
->nested
.cached_vmcs12
);
7039 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7046 * Emulate the VMXON instruction.
7047 * Currently, we just remember that VMX is active, and do not save or even
7048 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7049 * do not currently need to store anything in that guest-allocated memory
7050 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7051 * argument is different from the VMXON pointer (which the spec says they do).
7053 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7056 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7057 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7058 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7061 * The Intel VMX Instruction Reference lists a bunch of bits that are
7062 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7063 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7064 * Otherwise, we should fail with #UD. But most faulting conditions
7065 * have already been checked by hardware, prior to the VM-exit for
7066 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7067 * that bit set to 1 in non-root mode.
7069 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7070 kvm_queue_exception(vcpu
, UD_VECTOR
);
7074 if (vmx
->nested
.vmxon
) {
7075 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7076 return kvm_skip_emulated_instruction(vcpu
);
7079 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7080 != VMXON_NEEDED_FEATURES
) {
7081 kvm_inject_gp(vcpu
, 0);
7085 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
7088 ret
= enter_vmx_operation(vcpu
);
7092 nested_vmx_succeed(vcpu
);
7093 return kvm_skip_emulated_instruction(vcpu
);
7097 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7098 * for running VMX instructions (except VMXON, whose prerequisites are
7099 * slightly different). It also specifies what exception to inject otherwise.
7100 * Note that many of these exceptions have priority over VM exits, so they
7101 * don't have to be checked again here.
7103 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7105 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7106 kvm_queue_exception(vcpu
, UD_VECTOR
);
7112 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7114 if (vmx
->nested
.current_vmptr
== -1ull)
7117 /* current_vmptr and current_vmcs12 are always set/reset together */
7118 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
7121 if (enable_shadow_vmcs
) {
7122 /* copy to memory all shadowed fields in case
7123 they were modified */
7124 copy_shadow_to_vmcs12(vmx
);
7125 vmx
->nested
.sync_shadow_vmcs
= false;
7126 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
7127 SECONDARY_EXEC_SHADOW_VMCS
);
7128 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7130 vmx
->nested
.posted_intr_nv
= -1;
7132 /* Flush VMCS12 to guest memory */
7133 memcpy(vmx
->nested
.current_vmcs12
, vmx
->nested
.cached_vmcs12
,
7136 kunmap(vmx
->nested
.current_vmcs12_page
);
7137 nested_release_page(vmx
->nested
.current_vmcs12_page
);
7138 vmx
->nested
.current_vmptr
= -1ull;
7139 vmx
->nested
.current_vmcs12
= NULL
;
7143 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7144 * just stops using VMX.
7146 static void free_nested(struct vcpu_vmx
*vmx
)
7148 if (!vmx
->nested
.vmxon
)
7151 vmx
->nested
.vmxon
= false;
7152 free_vpid(vmx
->nested
.vpid02
);
7153 nested_release_vmcs12(vmx
);
7154 if (vmx
->nested
.msr_bitmap
) {
7155 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7156 vmx
->nested
.msr_bitmap
= NULL
;
7158 if (enable_shadow_vmcs
) {
7159 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7160 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7161 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7163 kfree(vmx
->nested
.cached_vmcs12
);
7164 /* Unpin physical memory we referred to in current vmcs02 */
7165 if (vmx
->nested
.apic_access_page
) {
7166 nested_release_page(vmx
->nested
.apic_access_page
);
7167 vmx
->nested
.apic_access_page
= NULL
;
7169 if (vmx
->nested
.virtual_apic_page
) {
7170 nested_release_page(vmx
->nested
.virtual_apic_page
);
7171 vmx
->nested
.virtual_apic_page
= NULL
;
7173 if (vmx
->nested
.pi_desc_page
) {
7174 kunmap(vmx
->nested
.pi_desc_page
);
7175 nested_release_page(vmx
->nested
.pi_desc_page
);
7176 vmx
->nested
.pi_desc_page
= NULL
;
7177 vmx
->nested
.pi_desc
= NULL
;
7180 nested_free_all_saved_vmcss(vmx
);
7183 /* Emulate the VMXOFF instruction */
7184 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7186 if (!nested_vmx_check_permission(vcpu
))
7188 free_nested(to_vmx(vcpu
));
7189 nested_vmx_succeed(vcpu
);
7190 return kvm_skip_emulated_instruction(vcpu
);
7193 /* Emulate the VMCLEAR instruction */
7194 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7196 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7200 if (!nested_vmx_check_permission(vcpu
))
7203 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7206 if (vmptr
== vmx
->nested
.current_vmptr
)
7207 nested_release_vmcs12(vmx
);
7209 kvm_vcpu_write_guest(vcpu
,
7210 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7211 &zero
, sizeof(zero
));
7213 nested_free_vmcs02(vmx
, vmptr
);
7215 nested_vmx_succeed(vcpu
);
7216 return kvm_skip_emulated_instruction(vcpu
);
7219 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7221 /* Emulate the VMLAUNCH instruction */
7222 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7224 return nested_vmx_run(vcpu
, true);
7227 /* Emulate the VMRESUME instruction */
7228 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7231 return nested_vmx_run(vcpu
, false);
7234 enum vmcs_field_type
{
7235 VMCS_FIELD_TYPE_U16
= 0,
7236 VMCS_FIELD_TYPE_U64
= 1,
7237 VMCS_FIELD_TYPE_U32
= 2,
7238 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7241 static inline int vmcs_field_type(unsigned long field
)
7243 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7244 return VMCS_FIELD_TYPE_U32
;
7245 return (field
>> 13) & 0x3 ;
7248 static inline int vmcs_field_readonly(unsigned long field
)
7250 return (((field
>> 10) & 0x3) == 1);
7254 * Read a vmcs12 field. Since these can have varying lengths and we return
7255 * one type, we chose the biggest type (u64) and zero-extend the return value
7256 * to that size. Note that the caller, handle_vmread, might need to use only
7257 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7258 * 64-bit fields are to be returned).
7260 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7261 unsigned long field
, u64
*ret
)
7263 short offset
= vmcs_field_to_offset(field
);
7269 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7271 switch (vmcs_field_type(field
)) {
7272 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7273 *ret
= *((natural_width
*)p
);
7275 case VMCS_FIELD_TYPE_U16
:
7278 case VMCS_FIELD_TYPE_U32
:
7281 case VMCS_FIELD_TYPE_U64
:
7291 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7292 unsigned long field
, u64 field_value
){
7293 short offset
= vmcs_field_to_offset(field
);
7294 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7298 switch (vmcs_field_type(field
)) {
7299 case VMCS_FIELD_TYPE_U16
:
7300 *(u16
*)p
= field_value
;
7302 case VMCS_FIELD_TYPE_U32
:
7303 *(u32
*)p
= field_value
;
7305 case VMCS_FIELD_TYPE_U64
:
7306 *(u64
*)p
= field_value
;
7308 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7309 *(natural_width
*)p
= field_value
;
7318 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7321 unsigned long field
;
7323 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7324 const unsigned long *fields
= shadow_read_write_fields
;
7325 const int num_fields
= max_shadow_read_write_fields
;
7329 vmcs_load(shadow_vmcs
);
7331 for (i
= 0; i
< num_fields
; i
++) {
7333 switch (vmcs_field_type(field
)) {
7334 case VMCS_FIELD_TYPE_U16
:
7335 field_value
= vmcs_read16(field
);
7337 case VMCS_FIELD_TYPE_U32
:
7338 field_value
= vmcs_read32(field
);
7340 case VMCS_FIELD_TYPE_U64
:
7341 field_value
= vmcs_read64(field
);
7343 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7344 field_value
= vmcs_readl(field
);
7350 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7353 vmcs_clear(shadow_vmcs
);
7354 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7359 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7361 const unsigned long *fields
[] = {
7362 shadow_read_write_fields
,
7363 shadow_read_only_fields
7365 const int max_fields
[] = {
7366 max_shadow_read_write_fields
,
7367 max_shadow_read_only_fields
7370 unsigned long field
;
7371 u64 field_value
= 0;
7372 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7374 vmcs_load(shadow_vmcs
);
7376 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7377 for (i
= 0; i
< max_fields
[q
]; i
++) {
7378 field
= fields
[q
][i
];
7379 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7381 switch (vmcs_field_type(field
)) {
7382 case VMCS_FIELD_TYPE_U16
:
7383 vmcs_write16(field
, (u16
)field_value
);
7385 case VMCS_FIELD_TYPE_U32
:
7386 vmcs_write32(field
, (u32
)field_value
);
7388 case VMCS_FIELD_TYPE_U64
:
7389 vmcs_write64(field
, (u64
)field_value
);
7391 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7392 vmcs_writel(field
, (long)field_value
);
7401 vmcs_clear(shadow_vmcs
);
7402 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7406 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7407 * used before) all generate the same failure when it is missing.
7409 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7411 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7412 if (vmx
->nested
.current_vmptr
== -1ull) {
7413 nested_vmx_failInvalid(vcpu
);
7419 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7421 unsigned long field
;
7423 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7424 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7427 if (!nested_vmx_check_permission(vcpu
))
7430 if (!nested_vmx_check_vmcs12(vcpu
))
7431 return kvm_skip_emulated_instruction(vcpu
);
7433 /* Decode instruction info and find the field to read */
7434 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7435 /* Read the field, zero-extended to a u64 field_value */
7436 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7437 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7438 return kvm_skip_emulated_instruction(vcpu
);
7441 * Now copy part of this value to register or memory, as requested.
7442 * Note that the number of bits actually copied is 32 or 64 depending
7443 * on the guest's mode (32 or 64 bit), not on the given field's length.
7445 if (vmx_instruction_info
& (1u << 10)) {
7446 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7449 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7450 vmx_instruction_info
, true, &gva
))
7452 /* _system ok, as hardware has verified cpl=0 */
7453 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7454 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7457 nested_vmx_succeed(vcpu
);
7458 return kvm_skip_emulated_instruction(vcpu
);
7462 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7464 unsigned long field
;
7466 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7467 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7468 /* The value to write might be 32 or 64 bits, depending on L1's long
7469 * mode, and eventually we need to write that into a field of several
7470 * possible lengths. The code below first zero-extends the value to 64
7471 * bit (field_value), and then copies only the appropriate number of
7472 * bits into the vmcs12 field.
7474 u64 field_value
= 0;
7475 struct x86_exception e
;
7477 if (!nested_vmx_check_permission(vcpu
))
7480 if (!nested_vmx_check_vmcs12(vcpu
))
7481 return kvm_skip_emulated_instruction(vcpu
);
7483 if (vmx_instruction_info
& (1u << 10))
7484 field_value
= kvm_register_readl(vcpu
,
7485 (((vmx_instruction_info
) >> 3) & 0xf));
7487 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7488 vmx_instruction_info
, false, &gva
))
7490 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7491 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7492 kvm_inject_page_fault(vcpu
, &e
);
7498 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7499 if (vmcs_field_readonly(field
)) {
7500 nested_vmx_failValid(vcpu
,
7501 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7502 return kvm_skip_emulated_instruction(vcpu
);
7505 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7506 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7507 return kvm_skip_emulated_instruction(vcpu
);
7510 nested_vmx_succeed(vcpu
);
7511 return kvm_skip_emulated_instruction(vcpu
);
7514 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7516 vmx
->nested
.current_vmptr
= vmptr
;
7517 if (enable_shadow_vmcs
) {
7518 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7519 SECONDARY_EXEC_SHADOW_VMCS
);
7520 vmcs_write64(VMCS_LINK_POINTER
,
7521 __pa(vmx
->vmcs01
.shadow_vmcs
));
7522 vmx
->nested
.sync_shadow_vmcs
= true;
7526 /* Emulate the VMPTRLD instruction */
7527 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7529 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7532 if (!nested_vmx_check_permission(vcpu
))
7535 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7538 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7539 struct vmcs12
*new_vmcs12
;
7541 page
= nested_get_page(vcpu
, vmptr
);
7543 nested_vmx_failInvalid(vcpu
);
7544 return kvm_skip_emulated_instruction(vcpu
);
7546 new_vmcs12
= kmap(page
);
7547 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7549 nested_release_page_clean(page
);
7550 nested_vmx_failValid(vcpu
,
7551 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7552 return kvm_skip_emulated_instruction(vcpu
);
7555 nested_release_vmcs12(vmx
);
7556 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7557 vmx
->nested
.current_vmcs12_page
= page
;
7559 * Load VMCS12 from guest memory since it is not already
7562 memcpy(vmx
->nested
.cached_vmcs12
,
7563 vmx
->nested
.current_vmcs12
, VMCS12_SIZE
);
7564 set_current_vmptr(vmx
, vmptr
);
7567 nested_vmx_succeed(vcpu
);
7568 return kvm_skip_emulated_instruction(vcpu
);
7571 /* Emulate the VMPTRST instruction */
7572 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7574 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7575 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7577 struct x86_exception e
;
7579 if (!nested_vmx_check_permission(vcpu
))
7582 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7583 vmx_instruction_info
, true, &vmcs_gva
))
7585 /* ok to use *_system, as hardware has verified cpl=0 */
7586 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7587 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7589 kvm_inject_page_fault(vcpu
, &e
);
7592 nested_vmx_succeed(vcpu
);
7593 return kvm_skip_emulated_instruction(vcpu
);
7596 /* Emulate the INVEPT instruction */
7597 static int handle_invept(struct kvm_vcpu
*vcpu
)
7599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7600 u32 vmx_instruction_info
, types
;
7603 struct x86_exception e
;
7608 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7609 SECONDARY_EXEC_ENABLE_EPT
) ||
7610 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7611 kvm_queue_exception(vcpu
, UD_VECTOR
);
7615 if (!nested_vmx_check_permission(vcpu
))
7618 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7619 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7621 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7623 if (type
>= 32 || !(types
& (1 << type
))) {
7624 nested_vmx_failValid(vcpu
,
7625 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7626 return kvm_skip_emulated_instruction(vcpu
);
7629 /* According to the Intel VMX instruction reference, the memory
7630 * operand is read even if it isn't needed (e.g., for type==global)
7632 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7633 vmx_instruction_info
, false, &gva
))
7635 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7636 sizeof(operand
), &e
)) {
7637 kvm_inject_page_fault(vcpu
, &e
);
7642 case VMX_EPT_EXTENT_GLOBAL
:
7644 * TODO: track mappings and invalidate
7645 * single context requests appropriately
7647 case VMX_EPT_EXTENT_CONTEXT
:
7648 kvm_mmu_sync_roots(vcpu
);
7649 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7650 nested_vmx_succeed(vcpu
);
7657 return kvm_skip_emulated_instruction(vcpu
);
7660 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7663 u32 vmx_instruction_info
;
7664 unsigned long type
, types
;
7666 struct x86_exception e
;
7669 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7670 SECONDARY_EXEC_ENABLE_VPID
) ||
7671 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7672 kvm_queue_exception(vcpu
, UD_VECTOR
);
7676 if (!nested_vmx_check_permission(vcpu
))
7679 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7680 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7682 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7683 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7685 if (type
>= 32 || !(types
& (1 << type
))) {
7686 nested_vmx_failValid(vcpu
,
7687 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7688 return kvm_skip_emulated_instruction(vcpu
);
7691 /* according to the intel vmx instruction reference, the memory
7692 * operand is read even if it isn't needed (e.g., for type==global)
7694 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7695 vmx_instruction_info
, false, &gva
))
7697 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7699 kvm_inject_page_fault(vcpu
, &e
);
7704 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7705 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7706 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7708 nested_vmx_failValid(vcpu
,
7709 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7710 return kvm_skip_emulated_instruction(vcpu
);
7713 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7717 return kvm_skip_emulated_instruction(vcpu
);
7720 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7721 nested_vmx_succeed(vcpu
);
7723 return kvm_skip_emulated_instruction(vcpu
);
7726 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7728 unsigned long exit_qualification
;
7730 trace_kvm_pml_full(vcpu
->vcpu_id
);
7732 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7735 * PML buffer FULL happened while executing iret from NMI,
7736 * "blocked by NMI" bit has to be set before next VM entry.
7738 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7739 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7740 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7741 GUEST_INTR_STATE_NMI
);
7744 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7745 * here.., and there's no userspace involvement needed for PML.
7750 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7752 kvm_lapic_expired_hv_timer(vcpu
);
7757 * The exit handlers return 1 if the exit was handled fully and guest execution
7758 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7759 * to be done to userspace and return 0.
7761 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7762 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7763 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7764 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7765 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7766 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7767 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7768 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7769 [EXIT_REASON_CPUID
] = handle_cpuid
,
7770 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7771 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7772 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7773 [EXIT_REASON_HLT
] = handle_halt
,
7774 [EXIT_REASON_INVD
] = handle_invd
,
7775 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7776 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7777 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7778 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7779 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7780 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7781 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7782 [EXIT_REASON_VMREAD
] = handle_vmread
,
7783 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7784 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7785 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7786 [EXIT_REASON_VMON
] = handle_vmon
,
7787 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7788 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7789 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7790 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7791 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7792 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7793 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7794 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7795 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7796 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7797 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7798 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7799 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7800 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7801 [EXIT_REASON_INVEPT
] = handle_invept
,
7802 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7803 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7804 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7805 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7806 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7809 static const int kvm_vmx_max_exit_handlers
=
7810 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7812 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7813 struct vmcs12
*vmcs12
)
7815 unsigned long exit_qualification
;
7816 gpa_t bitmap
, last_bitmap
;
7821 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7822 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7824 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7826 port
= exit_qualification
>> 16;
7827 size
= (exit_qualification
& 7) + 1;
7829 last_bitmap
= (gpa_t
)-1;
7834 bitmap
= vmcs12
->io_bitmap_a
;
7835 else if (port
< 0x10000)
7836 bitmap
= vmcs12
->io_bitmap_b
;
7839 bitmap
+= (port
& 0x7fff) / 8;
7841 if (last_bitmap
!= bitmap
)
7842 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7844 if (b
& (1 << (port
& 7)))
7849 last_bitmap
= bitmap
;
7856 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7857 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7858 * disinterest in the current event (read or write a specific MSR) by using an
7859 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7861 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7862 struct vmcs12
*vmcs12
, u32 exit_reason
)
7864 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7867 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7871 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7872 * for the four combinations of read/write and low/high MSR numbers.
7873 * First we need to figure out which of the four to use:
7875 bitmap
= vmcs12
->msr_bitmap
;
7876 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7878 if (msr_index
>= 0xc0000000) {
7879 msr_index
-= 0xc0000000;
7883 /* Then read the msr_index'th bit from this bitmap: */
7884 if (msr_index
< 1024*8) {
7886 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7888 return 1 & (b
>> (msr_index
& 7));
7890 return true; /* let L1 handle the wrong parameter */
7894 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7895 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7896 * intercept (via guest_host_mask etc.) the current event.
7898 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7899 struct vmcs12
*vmcs12
)
7901 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7902 int cr
= exit_qualification
& 15;
7903 int reg
= (exit_qualification
>> 8) & 15;
7904 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7906 switch ((exit_qualification
>> 4) & 3) {
7907 case 0: /* mov to cr */
7910 if (vmcs12
->cr0_guest_host_mask
&
7911 (val
^ vmcs12
->cr0_read_shadow
))
7915 if ((vmcs12
->cr3_target_count
>= 1 &&
7916 vmcs12
->cr3_target_value0
== val
) ||
7917 (vmcs12
->cr3_target_count
>= 2 &&
7918 vmcs12
->cr3_target_value1
== val
) ||
7919 (vmcs12
->cr3_target_count
>= 3 &&
7920 vmcs12
->cr3_target_value2
== val
) ||
7921 (vmcs12
->cr3_target_count
>= 4 &&
7922 vmcs12
->cr3_target_value3
== val
))
7924 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7928 if (vmcs12
->cr4_guest_host_mask
&
7929 (vmcs12
->cr4_read_shadow
^ val
))
7933 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7939 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7940 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7943 case 1: /* mov from cr */
7946 if (vmcs12
->cpu_based_vm_exec_control
&
7947 CPU_BASED_CR3_STORE_EXITING
)
7951 if (vmcs12
->cpu_based_vm_exec_control
&
7952 CPU_BASED_CR8_STORE_EXITING
)
7959 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7960 * cr0. Other attempted changes are ignored, with no exit.
7962 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7963 (val
^ vmcs12
->cr0_read_shadow
))
7965 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7966 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7975 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7976 * should handle it ourselves in L0 (and then continue L2). Only call this
7977 * when in is_guest_mode (L2).
7979 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7981 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7983 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7984 u32 exit_reason
= vmx
->exit_reason
;
7986 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7987 vmcs_readl(EXIT_QUALIFICATION
),
7988 vmx
->idt_vectoring_info
,
7990 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7993 if (vmx
->nested
.nested_run_pending
)
7996 if (unlikely(vmx
->fail
)) {
7997 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7998 vmcs_read32(VM_INSTRUCTION_ERROR
));
8002 switch (exit_reason
) {
8003 case EXIT_REASON_EXCEPTION_NMI
:
8004 if (is_nmi(intr_info
))
8006 else if (is_page_fault(intr_info
))
8008 else if (is_no_device(intr_info
) &&
8009 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8011 else if (is_debug(intr_info
) &&
8013 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8015 else if (is_breakpoint(intr_info
) &&
8016 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8018 return vmcs12
->exception_bitmap
&
8019 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8020 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8022 case EXIT_REASON_TRIPLE_FAULT
:
8024 case EXIT_REASON_PENDING_INTERRUPT
:
8025 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8026 case EXIT_REASON_NMI_WINDOW
:
8027 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8028 case EXIT_REASON_TASK_SWITCH
:
8030 case EXIT_REASON_CPUID
:
8032 case EXIT_REASON_HLT
:
8033 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8034 case EXIT_REASON_INVD
:
8036 case EXIT_REASON_INVLPG
:
8037 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8038 case EXIT_REASON_RDPMC
:
8039 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8040 case EXIT_REASON_RDRAND
:
8041 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8042 case EXIT_REASON_RDSEED
:
8043 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8044 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8045 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8046 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8047 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8048 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8049 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8050 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8051 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8053 * VMX instructions trap unconditionally. This allows L1 to
8054 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8057 case EXIT_REASON_CR_ACCESS
:
8058 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8059 case EXIT_REASON_DR_ACCESS
:
8060 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8061 case EXIT_REASON_IO_INSTRUCTION
:
8062 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8063 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8064 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8065 case EXIT_REASON_MSR_READ
:
8066 case EXIT_REASON_MSR_WRITE
:
8067 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8068 case EXIT_REASON_INVALID_STATE
:
8070 case EXIT_REASON_MWAIT_INSTRUCTION
:
8071 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8072 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8073 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8074 case EXIT_REASON_MONITOR_INSTRUCTION
:
8075 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8076 case EXIT_REASON_PAUSE_INSTRUCTION
:
8077 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8078 nested_cpu_has2(vmcs12
,
8079 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8080 case EXIT_REASON_MCE_DURING_VMENTRY
:
8082 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8083 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8084 case EXIT_REASON_APIC_ACCESS
:
8085 return nested_cpu_has2(vmcs12
,
8086 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8087 case EXIT_REASON_APIC_WRITE
:
8088 case EXIT_REASON_EOI_INDUCED
:
8089 /* apic_write and eoi_induced should exit unconditionally. */
8091 case EXIT_REASON_EPT_VIOLATION
:
8093 * L0 always deals with the EPT violation. If nested EPT is
8094 * used, and the nested mmu code discovers that the address is
8095 * missing in the guest EPT table (EPT12), the EPT violation
8096 * will be injected with nested_ept_inject_page_fault()
8099 case EXIT_REASON_EPT_MISCONFIG
:
8101 * L2 never uses directly L1's EPT, but rather L0's own EPT
8102 * table (shadow on EPT) or a merged EPT table that L0 built
8103 * (EPT on EPT). So any problems with the structure of the
8104 * table is L0's fault.
8107 case EXIT_REASON_WBINVD
:
8108 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8109 case EXIT_REASON_XSETBV
:
8111 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8113 * This should never happen, since it is not possible to
8114 * set XSS to a non-zero value---neither in L1 nor in L2.
8115 * If if it were, XSS would have to be checked against
8116 * the XSS exit bitmap in vmcs12.
8118 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8119 case EXIT_REASON_PREEMPTION_TIMER
:
8121 case EXIT_REASON_PML_FULL
:
8122 /* We don't expose PML support to L1. */
8129 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8131 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8132 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8135 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8138 __free_page(vmx
->pml_pg
);
8143 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8145 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8149 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8151 /* Do nothing if PML buffer is empty */
8152 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8155 /* PML index always points to next available PML buffer entity */
8156 if (pml_idx
>= PML_ENTITY_NUM
)
8161 pml_buf
= page_address(vmx
->pml_pg
);
8162 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8165 gpa
= pml_buf
[pml_idx
];
8166 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8167 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8170 /* reset PML index */
8171 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8175 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8176 * Called before reporting dirty_bitmap to userspace.
8178 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8181 struct kvm_vcpu
*vcpu
;
8183 * We only need to kick vcpu out of guest mode here, as PML buffer
8184 * is flushed at beginning of all VMEXITs, and it's obvious that only
8185 * vcpus running in guest are possible to have unflushed GPAs in PML
8188 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8189 kvm_vcpu_kick(vcpu
);
8192 static void vmx_dump_sel(char *name
, uint32_t sel
)
8194 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8195 name
, vmcs_read16(sel
),
8196 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8197 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8198 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8201 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8203 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8204 name
, vmcs_read32(limit
),
8205 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8208 static void dump_vmcs(void)
8210 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8211 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8212 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8213 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8214 u32 secondary_exec_control
= 0;
8215 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8216 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8219 if (cpu_has_secondary_exec_ctrls())
8220 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8222 pr_err("*** Guest State ***\n");
8223 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8224 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8225 vmcs_readl(CR0_GUEST_HOST_MASK
));
8226 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8227 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8228 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8229 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8230 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8232 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8233 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8234 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8235 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8237 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8238 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8239 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8240 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8241 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8242 vmcs_readl(GUEST_SYSENTER_ESP
),
8243 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8244 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8245 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8246 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8247 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8248 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8249 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8250 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8251 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8252 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8253 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8254 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8255 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8256 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8257 efer
, vmcs_read64(GUEST_IA32_PAT
));
8258 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8259 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8260 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8261 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8262 pr_err("PerfGlobCtl = 0x%016llx\n",
8263 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8264 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8265 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8266 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8267 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8268 vmcs_read32(GUEST_ACTIVITY_STATE
));
8269 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8270 pr_err("InterruptStatus = %04x\n",
8271 vmcs_read16(GUEST_INTR_STATUS
));
8273 pr_err("*** Host State ***\n");
8274 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8275 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8276 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8277 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8278 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8279 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8280 vmcs_read16(HOST_TR_SELECTOR
));
8281 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8282 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8283 vmcs_readl(HOST_TR_BASE
));
8284 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8285 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8286 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8287 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8288 vmcs_readl(HOST_CR4
));
8289 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8290 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8291 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8292 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8293 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8294 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8295 vmcs_read64(HOST_IA32_EFER
),
8296 vmcs_read64(HOST_IA32_PAT
));
8297 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8298 pr_err("PerfGlobCtl = 0x%016llx\n",
8299 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8301 pr_err("*** Control State ***\n");
8302 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8303 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8304 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8305 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8306 vmcs_read32(EXCEPTION_BITMAP
),
8307 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8308 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8309 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8310 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8311 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8312 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8313 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8314 vmcs_read32(VM_EXIT_INTR_INFO
),
8315 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8316 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8317 pr_err(" reason=%08x qualification=%016lx\n",
8318 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8319 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8320 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8321 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8322 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8323 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8324 pr_err("TSC Multiplier = 0x%016llx\n",
8325 vmcs_read64(TSC_MULTIPLIER
));
8326 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8327 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8328 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8329 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8330 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8331 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8332 n
= vmcs_read32(CR3_TARGET_COUNT
);
8333 for (i
= 0; i
+ 1 < n
; i
+= 4)
8334 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8335 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8336 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8338 pr_err("CR3 target%u=%016lx\n",
8339 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8340 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8341 pr_err("PLE Gap=%08x Window=%08x\n",
8342 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8343 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8344 pr_err("Virtual processor ID = 0x%04x\n",
8345 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8349 * The guest has exited. See if we can fix it or if we need userspace
8352 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8354 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8355 u32 exit_reason
= vmx
->exit_reason
;
8356 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8358 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8359 vcpu
->arch
.gpa_available
= false;
8362 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8363 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8364 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8365 * mode as if vcpus is in root mode, the PML buffer must has been
8369 vmx_flush_pml_buffer(vcpu
);
8371 /* If guest state is invalid, start emulating */
8372 if (vmx
->emulation_required
)
8373 return handle_invalid_guest_state(vcpu
);
8375 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8376 nested_vmx_vmexit(vcpu
, exit_reason
,
8377 vmcs_read32(VM_EXIT_INTR_INFO
),
8378 vmcs_readl(EXIT_QUALIFICATION
));
8382 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8384 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8385 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8390 if (unlikely(vmx
->fail
)) {
8391 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8392 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8393 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8399 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8400 * delivery event since it indicates guest is accessing MMIO.
8401 * The vm-exit can be triggered again after return to guest that
8402 * will cause infinite loop.
8404 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8405 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8406 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8407 exit_reason
!= EXIT_REASON_PML_FULL
&&
8408 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8409 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8410 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8411 vcpu
->run
->internal
.ndata
= 2;
8412 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8413 vcpu
->run
->internal
.data
[1] = exit_reason
;
8417 if (exit_reason
< kvm_vmx_max_exit_handlers
8418 && kvm_vmx_exit_handlers
[exit_reason
])
8419 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8421 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8423 kvm_queue_exception(vcpu
, UD_VECTOR
);
8428 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8430 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8432 if (is_guest_mode(vcpu
) &&
8433 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8436 if (irr
== -1 || tpr
< irr
) {
8437 vmcs_write32(TPR_THRESHOLD
, 0);
8441 vmcs_write32(TPR_THRESHOLD
, irr
);
8444 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8446 u32 sec_exec_control
;
8448 /* Postpone execution until vmcs01 is the current VMCS. */
8449 if (is_guest_mode(vcpu
)) {
8450 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8454 if (!cpu_has_vmx_virtualize_x2apic_mode())
8457 if (!cpu_need_tpr_shadow(vcpu
))
8460 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8463 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8464 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8466 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8467 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8468 vmx_flush_tlb_ept_only(vcpu
);
8470 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8472 vmx_set_msr_bitmap(vcpu
);
8475 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8477 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8480 * Currently we do not handle the nested case where L2 has an
8481 * APIC access page of its own; that page is still pinned.
8482 * Hence, we skip the case where the VCPU is in guest mode _and_
8483 * L1 prepared an APIC access page for L2.
8485 * For the case where L1 and L2 share the same APIC access page
8486 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8487 * in the vmcs12), this function will only update either the vmcs01
8488 * or the vmcs02. If the former, the vmcs02 will be updated by
8489 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8490 * the next L2->L1 exit.
8492 if (!is_guest_mode(vcpu
) ||
8493 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8494 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8495 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8496 vmx_flush_tlb_ept_only(vcpu
);
8500 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8508 status
= vmcs_read16(GUEST_INTR_STATUS
);
8510 if (max_isr
!= old
) {
8512 status
|= max_isr
<< 8;
8513 vmcs_write16(GUEST_INTR_STATUS
, status
);
8517 static void vmx_set_rvi(int vector
)
8525 status
= vmcs_read16(GUEST_INTR_STATUS
);
8526 old
= (u8
)status
& 0xff;
8527 if ((u8
)vector
!= old
) {
8529 status
|= (u8
)vector
;
8530 vmcs_write16(GUEST_INTR_STATUS
, status
);
8534 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8536 if (!is_guest_mode(vcpu
)) {
8537 vmx_set_rvi(max_irr
);
8545 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8548 if (nested_exit_on_intr(vcpu
))
8552 * Else, fall back to pre-APICv interrupt injection since L2
8553 * is run without virtual interrupt delivery.
8555 if (!kvm_event_needs_reinjection(vcpu
) &&
8556 vmx_interrupt_allowed(vcpu
)) {
8557 kvm_queue_interrupt(vcpu
, max_irr
, false);
8558 vmx_inject_irq(vcpu
);
8562 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8564 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8567 WARN_ON(!vcpu
->arch
.apicv_active
);
8568 if (pi_test_on(&vmx
->pi_desc
)) {
8569 pi_clear_on(&vmx
->pi_desc
);
8571 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8572 * But on x86 this is just a compiler barrier anyway.
8574 smp_mb__after_atomic();
8575 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8577 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8579 vmx_hwapic_irr_update(vcpu
, max_irr
);
8583 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8585 if (!kvm_vcpu_apicv_active(vcpu
))
8588 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8589 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8590 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8591 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8594 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8596 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8598 pi_clear_on(&vmx
->pi_desc
);
8599 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8602 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8606 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8607 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8610 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8611 exit_intr_info
= vmx
->exit_intr_info
;
8613 /* Handle machine checks before interrupts are enabled */
8614 if (is_machine_check(exit_intr_info
))
8615 kvm_machine_check();
8617 /* We need to handle NMIs before interrupts are enabled */
8618 if (is_nmi(exit_intr_info
)) {
8619 kvm_before_handle_nmi(&vmx
->vcpu
);
8621 kvm_after_handle_nmi(&vmx
->vcpu
);
8625 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8627 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8628 register void *__sp
asm(_ASM_SP
);
8630 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8631 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8632 unsigned int vector
;
8633 unsigned long entry
;
8635 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8636 #ifdef CONFIG_X86_64
8640 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8641 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8642 entry
= gate_offset(*desc
);
8644 #ifdef CONFIG_X86_64
8645 "mov %%" _ASM_SP
", %[sp]\n\t"
8646 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8651 __ASM_SIZE(push
) " $%c[cs]\n\t"
8652 "call *%[entry]\n\t"
8654 #ifdef CONFIG_X86_64
8660 [ss
]"i"(__KERNEL_DS
),
8661 [cs
]"i"(__KERNEL_CS
)
8666 static bool vmx_has_high_real_mode_segbase(void)
8668 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8671 static bool vmx_mpx_supported(void)
8673 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8674 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8677 static bool vmx_xsaves_supported(void)
8679 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8680 SECONDARY_EXEC_XSAVES
;
8683 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8688 bool idtv_info_valid
;
8690 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8692 if (vmx
->nmi_known_unmasked
)
8695 * Can't use vmx->exit_intr_info since we're not sure what
8696 * the exit reason is.
8698 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8699 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8700 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8702 * SDM 3: 27.7.1.2 (September 2008)
8703 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8704 * a guest IRET fault.
8705 * SDM 3: 23.2.2 (September 2008)
8706 * Bit 12 is undefined in any of the following cases:
8707 * If the VM exit sets the valid bit in the IDT-vectoring
8708 * information field.
8709 * If the VM exit is due to a double fault.
8711 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8712 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8713 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8714 GUEST_INTR_STATE_NMI
);
8716 vmx
->nmi_known_unmasked
=
8717 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8718 & GUEST_INTR_STATE_NMI
);
8721 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8722 u32 idt_vectoring_info
,
8723 int instr_len_field
,
8724 int error_code_field
)
8728 bool idtv_info_valid
;
8730 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8732 vcpu
->arch
.nmi_injected
= false;
8733 kvm_clear_exception_queue(vcpu
);
8734 kvm_clear_interrupt_queue(vcpu
);
8736 if (!idtv_info_valid
)
8739 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8741 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8742 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8745 case INTR_TYPE_NMI_INTR
:
8746 vcpu
->arch
.nmi_injected
= true;
8748 * SDM 3: 27.7.1.2 (September 2008)
8749 * Clear bit "block by NMI" before VM entry if a NMI
8752 vmx_set_nmi_mask(vcpu
, false);
8754 case INTR_TYPE_SOFT_EXCEPTION
:
8755 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8757 case INTR_TYPE_HARD_EXCEPTION
:
8758 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8759 u32 err
= vmcs_read32(error_code_field
);
8760 kvm_requeue_exception_e(vcpu
, vector
, err
);
8762 kvm_requeue_exception(vcpu
, vector
);
8764 case INTR_TYPE_SOFT_INTR
:
8765 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8767 case INTR_TYPE_EXT_INTR
:
8768 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8775 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8777 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8778 VM_EXIT_INSTRUCTION_LEN
,
8779 IDT_VECTORING_ERROR_CODE
);
8782 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8784 __vmx_complete_interrupts(vcpu
,
8785 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8786 VM_ENTRY_INSTRUCTION_LEN
,
8787 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8789 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8792 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8795 struct perf_guest_switch_msr
*msrs
;
8797 msrs
= perf_guest_get_msrs(&nr_msrs
);
8802 for (i
= 0; i
< nr_msrs
; i
++)
8803 if (msrs
[i
].host
== msrs
[i
].guest
)
8804 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8806 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8810 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8812 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8816 if (vmx
->hv_deadline_tsc
== -1)
8820 if (vmx
->hv_deadline_tsc
> tscl
)
8821 /* sure to be 32 bit only because checked on set_hv_timer */
8822 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8823 cpu_preemption_timer_multi
);
8827 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8830 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8832 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8833 unsigned long debugctlmsr
, cr4
;
8835 /* Don't enter VMX if guest state is invalid, let the exit handler
8836 start emulation until we arrive back to a valid state */
8837 if (vmx
->emulation_required
)
8840 if (vmx
->ple_window_dirty
) {
8841 vmx
->ple_window_dirty
= false;
8842 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8845 if (vmx
->nested
.sync_shadow_vmcs
) {
8846 copy_vmcs12_to_shadow(vmx
);
8847 vmx
->nested
.sync_shadow_vmcs
= false;
8850 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8851 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8852 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8853 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8855 cr4
= cr4_read_shadow();
8856 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8857 vmcs_writel(HOST_CR4
, cr4
);
8858 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8861 /* When single-stepping over STI and MOV SS, we must clear the
8862 * corresponding interruptibility bits in the guest state. Otherwise
8863 * vmentry fails as it then expects bit 14 (BS) in pending debug
8864 * exceptions being set, but that's not correct for the guest debugging
8866 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8867 vmx_set_interrupt_shadow(vcpu
, 0);
8869 if (vmx
->guest_pkru_valid
)
8870 __write_pkru(vmx
->guest_pkru
);
8872 atomic_switch_perf_msrs(vmx
);
8873 debugctlmsr
= get_debugctlmsr();
8875 vmx_arm_hv_timer(vcpu
);
8877 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8879 /* Store host registers */
8880 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8881 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8882 "push %%" _ASM_CX
" \n\t"
8883 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8885 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8886 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8888 /* Reload cr2 if changed */
8889 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8890 "mov %%cr2, %%" _ASM_DX
" \n\t"
8891 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8893 "mov %%" _ASM_AX
", %%cr2 \n\t"
8895 /* Check if vmlaunch of vmresume is needed */
8896 "cmpl $0, %c[launched](%0) \n\t"
8897 /* Load guest registers. Don't clobber flags. */
8898 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8899 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8900 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8901 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8902 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8903 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8904 #ifdef CONFIG_X86_64
8905 "mov %c[r8](%0), %%r8 \n\t"
8906 "mov %c[r9](%0), %%r9 \n\t"
8907 "mov %c[r10](%0), %%r10 \n\t"
8908 "mov %c[r11](%0), %%r11 \n\t"
8909 "mov %c[r12](%0), %%r12 \n\t"
8910 "mov %c[r13](%0), %%r13 \n\t"
8911 "mov %c[r14](%0), %%r14 \n\t"
8912 "mov %c[r15](%0), %%r15 \n\t"
8914 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8916 /* Enter guest mode */
8918 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8920 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8922 /* Save guest registers, load host registers, keep flags */
8923 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8925 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8926 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8927 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8928 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8929 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8930 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8931 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8932 #ifdef CONFIG_X86_64
8933 "mov %%r8, %c[r8](%0) \n\t"
8934 "mov %%r9, %c[r9](%0) \n\t"
8935 "mov %%r10, %c[r10](%0) \n\t"
8936 "mov %%r11, %c[r11](%0) \n\t"
8937 "mov %%r12, %c[r12](%0) \n\t"
8938 "mov %%r13, %c[r13](%0) \n\t"
8939 "mov %%r14, %c[r14](%0) \n\t"
8940 "mov %%r15, %c[r15](%0) \n\t"
8942 "mov %%cr2, %%" _ASM_AX
" \n\t"
8943 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8945 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8946 "setbe %c[fail](%0) \n\t"
8947 ".pushsection .rodata \n\t"
8948 ".global vmx_return \n\t"
8949 "vmx_return: " _ASM_PTR
" 2b \n\t"
8951 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8952 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8953 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8954 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8955 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8956 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8957 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8958 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8959 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8960 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8961 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8962 #ifdef CONFIG_X86_64
8963 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8964 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8965 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8966 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8967 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8968 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8969 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8970 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8972 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8973 [wordsize
]"i"(sizeof(ulong
))
8975 #ifdef CONFIG_X86_64
8976 , "rax", "rbx", "rdi", "rsi"
8977 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8979 , "eax", "ebx", "edi", "esi"
8983 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8985 update_debugctlmsr(debugctlmsr
);
8987 #ifndef CONFIG_X86_64
8989 * The sysexit path does not restore ds/es, so we must set them to
8990 * a reasonable value ourselves.
8992 * We can't defer this to vmx_load_host_state() since that function
8993 * may be executed in interrupt context, which saves and restore segments
8994 * around it, nullifying its effect.
8996 loadsegment(ds
, __USER_DS
);
8997 loadsegment(es
, __USER_DS
);
9000 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9001 | (1 << VCPU_EXREG_RFLAGS
)
9002 | (1 << VCPU_EXREG_PDPTR
)
9003 | (1 << VCPU_EXREG_SEGMENTS
)
9004 | (1 << VCPU_EXREG_CR3
));
9005 vcpu
->arch
.regs_dirty
= 0;
9007 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9009 vmx
->loaded_vmcs
->launched
= 1;
9011 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9014 * eager fpu is enabled if PKEY is supported and CR4 is switched
9015 * back on host, so it is safe to read guest PKRU from current
9018 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
9019 vmx
->guest_pkru
= __read_pkru();
9020 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
9021 vmx
->guest_pkru_valid
= true;
9022 __write_pkru(vmx
->host_pkru
);
9024 vmx
->guest_pkru_valid
= false;
9028 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9029 * we did not inject a still-pending event to L1 now because of
9030 * nested_run_pending, we need to re-enable this bit.
9032 if (vmx
->nested
.nested_run_pending
)
9033 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9035 vmx
->nested
.nested_run_pending
= 0;
9037 vmx_complete_atomic_exit(vmx
);
9038 vmx_recover_nmi_blocking(vmx
);
9039 vmx_complete_interrupts(vmx
);
9042 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9047 if (vmx
->loaded_vmcs
== vmcs
)
9051 vmx
->loaded_vmcs
= vmcs
;
9053 vmx_vcpu_load(vcpu
, cpu
);
9059 * Ensure that the current vmcs of the logical processor is the
9060 * vmcs01 of the vcpu before calling free_nested().
9062 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9064 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9067 r
= vcpu_load(vcpu
);
9069 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9074 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9076 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9079 vmx_destroy_pml_buffer(vmx
);
9080 free_vpid(vmx
->vpid
);
9081 leave_guest_mode(vcpu
);
9082 vmx_free_vcpu_nested(vcpu
);
9083 free_loaded_vmcs(vmx
->loaded_vmcs
);
9084 kfree(vmx
->guest_msrs
);
9085 kvm_vcpu_uninit(vcpu
);
9086 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9089 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9092 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9096 return ERR_PTR(-ENOMEM
);
9098 vmx
->vpid
= allocate_vpid();
9100 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9107 * If PML is turned on, failure on enabling PML just results in failure
9108 * of creating the vcpu, therefore we can simplify PML logic (by
9109 * avoiding dealing with cases, such as enabling PML partially on vcpus
9110 * for the guest, etc.
9113 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9118 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9119 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9122 if (!vmx
->guest_msrs
)
9125 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9126 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9127 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9128 if (!vmx
->loaded_vmcs
->vmcs
)
9130 loaded_vmcs_init(vmx
->loaded_vmcs
);
9133 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9134 vmx
->vcpu
.cpu
= cpu
;
9135 err
= vmx_vcpu_setup(vmx
);
9136 vmx_vcpu_put(&vmx
->vcpu
);
9140 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9141 err
= alloc_apic_access_page(kvm
);
9147 if (!kvm
->arch
.ept_identity_map_addr
)
9148 kvm
->arch
.ept_identity_map_addr
=
9149 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9150 err
= init_rmode_identity_map(kvm
);
9156 nested_vmx_setup_ctls_msrs(vmx
);
9157 vmx
->nested
.vpid02
= allocate_vpid();
9160 vmx
->nested
.posted_intr_nv
= -1;
9161 vmx
->nested
.current_vmptr
= -1ull;
9162 vmx
->nested
.current_vmcs12
= NULL
;
9164 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9169 free_vpid(vmx
->nested
.vpid02
);
9170 free_loaded_vmcs(vmx
->loaded_vmcs
);
9172 kfree(vmx
->guest_msrs
);
9174 vmx_destroy_pml_buffer(vmx
);
9176 kvm_vcpu_uninit(&vmx
->vcpu
);
9178 free_vpid(vmx
->vpid
);
9179 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9180 return ERR_PTR(err
);
9183 static void __init
vmx_check_processor_compat(void *rtn
)
9185 struct vmcs_config vmcs_conf
;
9188 if (setup_vmcs_config(&vmcs_conf
) < 0)
9190 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9191 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9192 smp_processor_id());
9197 static int get_ept_level(void)
9199 return VMX_EPT_DEFAULT_GAW
+ 1;
9202 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9207 /* For VT-d and EPT combination
9208 * 1. MMIO: always map as UC
9210 * a. VT-d without snooping control feature: can't guarantee the
9211 * result, try to trust guest.
9212 * b. VT-d with snooping control feature: snooping control feature of
9213 * VT-d engine can guarantee the cache correctness. Just set it
9214 * to WB to keep consistent with host. So the same as item 3.
9215 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9216 * consistent with host MTRR
9219 cache
= MTRR_TYPE_UNCACHABLE
;
9223 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9224 ipat
= VMX_EPT_IPAT_BIT
;
9225 cache
= MTRR_TYPE_WRBACK
;
9229 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9230 ipat
= VMX_EPT_IPAT_BIT
;
9231 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9232 cache
= MTRR_TYPE_WRBACK
;
9234 cache
= MTRR_TYPE_UNCACHABLE
;
9238 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9241 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9244 static int vmx_get_lpage_level(void)
9246 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9247 return PT_DIRECTORY_LEVEL
;
9249 /* For shadow and EPT supported 1GB page */
9250 return PT_PDPE_LEVEL
;
9253 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9256 * These bits in the secondary execution controls field
9257 * are dynamic, the others are mostly based on the hypervisor
9258 * architecture and the guest's CPUID. Do not touch the
9262 SECONDARY_EXEC_SHADOW_VMCS
|
9263 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9264 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9266 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9268 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9269 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9273 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9274 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9276 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9278 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9279 struct kvm_cpuid_entry2
*entry
;
9281 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9282 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9284 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9285 if (entry && (entry->_reg & (_cpuid_mask))) \
9286 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9289 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9290 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9291 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9292 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9293 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9294 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9295 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9296 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9297 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9298 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9299 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9300 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9301 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9302 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9303 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9305 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9306 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9307 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9308 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9309 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9310 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9311 cr4_fixed1_update(bit(11), ecx
, bit(2));
9313 #undef cr4_fixed1_update
9316 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9318 struct kvm_cpuid_entry2
*best
;
9319 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9320 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9322 if (vmx_rdtscp_supported()) {
9323 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9324 if (!rdtscp_enabled
)
9325 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9329 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9330 SECONDARY_EXEC_RDTSCP
;
9332 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9333 ~SECONDARY_EXEC_RDTSCP
;
9337 /* Exposing INVPCID only when PCID is exposed */
9338 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9339 if (vmx_invpcid_supported() &&
9340 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9341 !guest_cpuid_has_pcid(vcpu
))) {
9342 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9345 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9348 if (cpu_has_secondary_exec_ctrls())
9349 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9351 if (nested_vmx_allowed(vcpu
))
9352 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9353 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9355 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9356 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9358 if (nested_vmx_allowed(vcpu
))
9359 nested_vmx_cr_fixed1_bits_update(vcpu
);
9362 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9364 if (func
== 1 && nested
)
9365 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9368 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9369 struct x86_exception
*fault
)
9371 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9374 if (fault
->error_code
& PFERR_RSVD_MASK
)
9375 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9377 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9378 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9379 vmcs12
->guest_physical_address
= fault
->address
;
9382 /* Callbacks for nested_ept_init_mmu_context: */
9384 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9386 /* return the page table to be shadowed - in our case, EPT12 */
9387 return get_vmcs12(vcpu
)->ept_pointer
;
9390 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9394 WARN_ON(mmu_is_nested(vcpu
));
9395 eptp
= nested_ept_get_cr3(vcpu
);
9396 if ((eptp
& VMX_EPT_AD_ENABLE_BIT
) && !enable_ept_ad_bits
)
9399 kvm_mmu_unload(vcpu
);
9400 kvm_init_shadow_ept_mmu(vcpu
,
9401 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9402 VMX_EPT_EXECUTE_ONLY_BIT
,
9403 eptp
& VMX_EPT_AD_ENABLE_BIT
);
9404 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9405 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9406 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9408 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9412 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9414 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9417 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9420 bool inequality
, bit
;
9422 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9424 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9425 vmcs12
->page_fault_error_code_match
;
9426 return inequality
^ bit
;
9429 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9430 struct x86_exception
*fault
)
9432 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9434 WARN_ON(!is_guest_mode(vcpu
));
9436 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9437 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9438 vmcs_read32(VM_EXIT_INTR_INFO
),
9439 vmcs_readl(EXIT_QUALIFICATION
));
9441 kvm_inject_page_fault(vcpu
, fault
);
9444 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9445 struct vmcs12
*vmcs12
);
9447 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9448 struct vmcs12
*vmcs12
)
9450 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9453 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9455 * Translate L1 physical address to host physical
9456 * address for vmcs02. Keep the page pinned, so this
9457 * physical address remains valid. We keep a reference
9458 * to it so we can release it later.
9460 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9461 nested_release_page(vmx
->nested
.apic_access_page
);
9462 vmx
->nested
.apic_access_page
=
9463 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9465 * If translation failed, no matter: This feature asks
9466 * to exit when accessing the given address, and if it
9467 * can never be accessed, this feature won't do
9470 if (vmx
->nested
.apic_access_page
) {
9471 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9472 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9474 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9475 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9477 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9478 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9479 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9480 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9481 kvm_vcpu_reload_apic_access_page(vcpu
);
9484 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9485 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9486 nested_release_page(vmx
->nested
.virtual_apic_page
);
9487 vmx
->nested
.virtual_apic_page
=
9488 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9491 * If translation failed, VM entry will fail because
9492 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9493 * Failing the vm entry is _not_ what the processor
9494 * does but it's basically the only possibility we
9495 * have. We could still enter the guest if CR8 load
9496 * exits are enabled, CR8 store exits are enabled, and
9497 * virtualize APIC access is disabled; in this case
9498 * the processor would never use the TPR shadow and we
9499 * could simply clear the bit from the execution
9500 * control. But such a configuration is useless, so
9501 * let's keep the code simple.
9503 if (vmx
->nested
.virtual_apic_page
) {
9504 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9505 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9509 if (nested_cpu_has_posted_intr(vmcs12
)) {
9510 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9511 kunmap(vmx
->nested
.pi_desc_page
);
9512 nested_release_page(vmx
->nested
.pi_desc_page
);
9514 vmx
->nested
.pi_desc_page
=
9515 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9516 vmx
->nested
.pi_desc
=
9517 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9518 if (!vmx
->nested
.pi_desc
) {
9519 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9522 vmx
->nested
.pi_desc
=
9523 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9524 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9526 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9527 page_to_phys(vmx
->nested
.pi_desc_page
) +
9528 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9531 if (cpu_has_vmx_msr_bitmap() &&
9532 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9533 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9536 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9537 CPU_BASED_USE_MSR_BITMAPS
);
9540 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9542 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9543 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9545 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9548 /* Make sure short timeouts reliably trigger an immediate vmexit.
9549 * hrtimer_start does not guarantee this. */
9550 if (preemption_timeout
<= 1) {
9551 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9555 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9556 preemption_timeout
*= 1000000;
9557 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9558 hrtimer_start(&vmx
->nested
.preemption_timer
,
9559 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9562 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9563 struct vmcs12
*vmcs12
)
9568 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9571 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9575 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9577 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9578 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9585 * Merge L0's and L1's MSR bitmap, return false to indicate that
9586 * we do not use the hardware.
9588 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9589 struct vmcs12
*vmcs12
)
9593 unsigned long *msr_bitmap_l1
;
9594 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9596 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9597 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9600 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9603 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9605 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9607 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9608 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9609 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9610 nested_vmx_disable_intercept_for_msr(
9611 msr_bitmap_l1
, msr_bitmap_l0
,
9614 nested_vmx_disable_intercept_for_msr(
9615 msr_bitmap_l1
, msr_bitmap_l0
,
9616 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9617 MSR_TYPE_R
| MSR_TYPE_W
);
9619 if (nested_cpu_has_vid(vmcs12
)) {
9620 nested_vmx_disable_intercept_for_msr(
9621 msr_bitmap_l1
, msr_bitmap_l0
,
9622 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9624 nested_vmx_disable_intercept_for_msr(
9625 msr_bitmap_l1
, msr_bitmap_l0
,
9626 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9631 nested_release_page_clean(page
);
9636 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9637 struct vmcs12
*vmcs12
)
9639 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9640 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9641 !nested_cpu_has_vid(vmcs12
) &&
9642 !nested_cpu_has_posted_intr(vmcs12
))
9646 * If virtualize x2apic mode is enabled,
9647 * virtualize apic access must be disabled.
9649 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9650 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9654 * If virtual interrupt delivery is enabled,
9655 * we must exit on external interrupts.
9657 if (nested_cpu_has_vid(vmcs12
) &&
9658 !nested_exit_on_intr(vcpu
))
9662 * bits 15:8 should be zero in posted_intr_nv,
9663 * the descriptor address has been already checked
9664 * in nested_get_vmcs12_pages.
9666 if (nested_cpu_has_posted_intr(vmcs12
) &&
9667 (!nested_cpu_has_vid(vmcs12
) ||
9668 !nested_exit_intr_ack_set(vcpu
) ||
9669 vmcs12
->posted_intr_nv
& 0xff00))
9672 /* tpr shadow is needed by all apicv features. */
9673 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9679 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9680 unsigned long count_field
,
9681 unsigned long addr_field
)
9686 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9687 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9693 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9694 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9695 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9696 pr_debug_ratelimited(
9697 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9698 addr_field
, maxphyaddr
, count
, addr
);
9704 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9705 struct vmcs12
*vmcs12
)
9707 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9708 vmcs12
->vm_exit_msr_store_count
== 0 &&
9709 vmcs12
->vm_entry_msr_load_count
== 0)
9710 return 0; /* Fast path */
9711 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9712 VM_EXIT_MSR_LOAD_ADDR
) ||
9713 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9714 VM_EXIT_MSR_STORE_ADDR
) ||
9715 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9716 VM_ENTRY_MSR_LOAD_ADDR
))
9721 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9722 struct vmx_msr_entry
*e
)
9724 /* x2APIC MSR accesses are not allowed */
9725 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9727 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9728 e
->index
== MSR_IA32_UCODE_REV
)
9730 if (e
->reserved
!= 0)
9735 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9736 struct vmx_msr_entry
*e
)
9738 if (e
->index
== MSR_FS_BASE
||
9739 e
->index
== MSR_GS_BASE
||
9740 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9741 nested_vmx_msr_check_common(vcpu
, e
))
9746 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9747 struct vmx_msr_entry
*e
)
9749 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9750 nested_vmx_msr_check_common(vcpu
, e
))
9756 * Load guest's/host's msr at nested entry/exit.
9757 * return 0 for success, entry index for failure.
9759 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9762 struct vmx_msr_entry e
;
9763 struct msr_data msr
;
9765 msr
.host_initiated
= false;
9766 for (i
= 0; i
< count
; i
++) {
9767 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9769 pr_debug_ratelimited(
9770 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9771 __func__
, i
, gpa
+ i
* sizeof(e
));
9774 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9775 pr_debug_ratelimited(
9776 "%s check failed (%u, 0x%x, 0x%x)\n",
9777 __func__
, i
, e
.index
, e
.reserved
);
9780 msr
.index
= e
.index
;
9782 if (kvm_set_msr(vcpu
, &msr
)) {
9783 pr_debug_ratelimited(
9784 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9785 __func__
, i
, e
.index
, e
.value
);
9794 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9797 struct vmx_msr_entry e
;
9799 for (i
= 0; i
< count
; i
++) {
9800 struct msr_data msr_info
;
9801 if (kvm_vcpu_read_guest(vcpu
,
9802 gpa
+ i
* sizeof(e
),
9803 &e
, 2 * sizeof(u32
))) {
9804 pr_debug_ratelimited(
9805 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9806 __func__
, i
, gpa
+ i
* sizeof(e
));
9809 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9810 pr_debug_ratelimited(
9811 "%s check failed (%u, 0x%x, 0x%x)\n",
9812 __func__
, i
, e
.index
, e
.reserved
);
9815 msr_info
.host_initiated
= false;
9816 msr_info
.index
= e
.index
;
9817 if (kvm_get_msr(vcpu
, &msr_info
)) {
9818 pr_debug_ratelimited(
9819 "%s cannot read MSR (%u, 0x%x)\n",
9820 __func__
, i
, e
.index
);
9823 if (kvm_vcpu_write_guest(vcpu
,
9824 gpa
+ i
* sizeof(e
) +
9825 offsetof(struct vmx_msr_entry
, value
),
9826 &msr_info
.data
, sizeof(msr_info
.data
))) {
9827 pr_debug_ratelimited(
9828 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9829 __func__
, i
, e
.index
, msr_info
.data
);
9836 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
9838 unsigned long invalid_mask
;
9840 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
9841 return (val
& invalid_mask
) == 0;
9845 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
9846 * emulating VM entry into a guest with EPT enabled.
9847 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9848 * is assigned to entry_failure_code on failure.
9850 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
9851 u32
*entry_failure_code
)
9853 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
9854 if (!nested_cr3_valid(vcpu
, cr3
)) {
9855 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
9860 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
9861 * must not be dereferenced.
9863 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
9865 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
9866 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
9871 vcpu
->arch
.cr3
= cr3
;
9872 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
9875 kvm_mmu_reset_context(vcpu
);
9880 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9881 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9882 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9883 * guest in a way that will both be appropriate to L1's requests, and our
9884 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9885 * function also has additional necessary side-effects, like setting various
9886 * vcpu->arch fields.
9887 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
9888 * is assigned to entry_failure_code on failure.
9890 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9891 bool from_vmentry
, u32
*entry_failure_code
)
9893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9896 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9897 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9898 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9899 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9900 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9901 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9902 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9903 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9904 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9905 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9906 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9907 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9908 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9909 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9910 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9911 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9912 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9913 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9914 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9915 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9916 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9917 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9918 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9919 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9920 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9921 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9922 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9923 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9924 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9925 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9926 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9927 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9928 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9929 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9930 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9931 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9934 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
9935 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9936 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9938 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9939 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9942 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9943 vmcs12
->vm_entry_intr_info_field
);
9944 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9945 vmcs12
->vm_entry_exception_error_code
);
9946 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9947 vmcs12
->vm_entry_instruction_len
);
9948 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9949 vmcs12
->guest_interruptibility_info
);
9951 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9953 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9954 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9955 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9956 vmcs12
->guest_pending_dbg_exceptions
);
9957 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9958 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9960 if (nested_cpu_has_xsaves(vmcs12
))
9961 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9962 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9964 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9966 /* Preemption timer setting is only taken from vmcs01. */
9967 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9968 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9969 if (vmx
->hv_deadline_tsc
== -1)
9970 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9972 /* Posted interrupts setting is only taken from vmcs12. */
9973 if (nested_cpu_has_posted_intr(vmcs12
)) {
9975 * Note that we use L0's vector here and in
9976 * vmx_deliver_nested_posted_interrupt.
9978 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9979 vmx
->nested
.pi_pending
= false;
9980 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9982 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9985 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9987 vmx
->nested
.preemption_timer_expired
= false;
9988 if (nested_cpu_has_preemption_timer(vmcs12
))
9989 vmx_start_preemption_timer(vcpu
);
9992 * Whether page-faults are trapped is determined by a combination of
9993 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9994 * If enable_ept, L0 doesn't care about page faults and we should
9995 * set all of these to L1's desires. However, if !enable_ept, L0 does
9996 * care about (at least some) page faults, and because it is not easy
9997 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9998 * to exit on each and every L2 page fault. This is done by setting
9999 * MASK=MATCH=0 and (see below) EB.PF=1.
10000 * Note that below we don't need special code to set EB.PF beyond the
10001 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10002 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10003 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10005 * A problem with this approach (when !enable_ept) is that L1 may be
10006 * injected with more page faults than it asked for. This could have
10007 * caused problems, but in practice existing hypervisors don't care.
10008 * To fix this, we will need to emulate the PFEC checking (on the L1
10009 * page tables), using walk_addr(), when injecting PFs to L1.
10011 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10012 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10013 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10014 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10016 if (cpu_has_secondary_exec_ctrls()) {
10017 exec_control
= vmx_secondary_exec_control(vmx
);
10019 /* Take the following fields only from vmcs12 */
10020 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10021 SECONDARY_EXEC_RDTSCP
|
10022 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10023 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10024 if (nested_cpu_has(vmcs12
,
10025 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
10026 exec_control
|= vmcs12
->secondary_vm_exec_control
;
10028 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10029 vmcs_write64(EOI_EXIT_BITMAP0
,
10030 vmcs12
->eoi_exit_bitmap0
);
10031 vmcs_write64(EOI_EXIT_BITMAP1
,
10032 vmcs12
->eoi_exit_bitmap1
);
10033 vmcs_write64(EOI_EXIT_BITMAP2
,
10034 vmcs12
->eoi_exit_bitmap2
);
10035 vmcs_write64(EOI_EXIT_BITMAP3
,
10036 vmcs12
->eoi_exit_bitmap3
);
10037 vmcs_write16(GUEST_INTR_STATUS
,
10038 vmcs12
->guest_intr_status
);
10042 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10043 * nested_get_vmcs12_pages will either fix it up or
10044 * remove the VM execution control.
10046 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10047 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10049 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10054 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10055 * Some constant fields are set here by vmx_set_constant_host_state().
10056 * Other fields are different per CPU, and will be set later when
10057 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10059 vmx_set_constant_host_state(vmx
);
10062 * Set the MSR load/store lists to match L0's settings.
10064 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10065 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10066 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10067 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10068 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10071 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10072 * entry, but only if the current (host) sp changed from the value
10073 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10074 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10075 * here we just force the write to happen on entry.
10079 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10080 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10081 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10082 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10083 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10086 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10087 * nested_get_vmcs12_pages can't fix it up, the illegal value
10088 * will result in a VM entry failure.
10090 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10091 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10092 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10096 * Merging of IO bitmap not currently supported.
10097 * Rather, exit every time.
10099 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10100 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10102 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10104 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10105 * bitwise-or of what L1 wants to trap for L2, and what we want to
10106 * trap. Note that CR0.TS also needs updating - we do this later.
10108 update_exception_bitmap(vcpu
);
10109 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10110 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10112 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10113 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10114 * bits are further modified by vmx_set_efer() below.
10116 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10118 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10119 * emulated by vmx_set_efer(), below.
10121 vm_entry_controls_init(vmx
,
10122 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10123 ~VM_ENTRY_IA32E_MODE
) |
10124 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10126 if (from_vmentry
&&
10127 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10128 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10129 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10130 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10131 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10134 set_cr4_guest_host_mask(vmx
);
10136 if (from_vmentry
&&
10137 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10138 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10140 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10141 vmcs_write64(TSC_OFFSET
,
10142 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10144 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10145 if (kvm_has_tsc_control
)
10146 decache_tsc_multiplier(vmx
);
10150 * There is no direct mapping between vpid02 and vpid12, the
10151 * vpid02 is per-vCPU for L0 and reused while the value of
10152 * vpid12 is changed w/ one invvpid during nested vmentry.
10153 * The vpid12 is allocated by L1 for L2, so it will not
10154 * influence global bitmap(for vpid01 and vpid02 allocation)
10155 * even if spawn a lot of nested vCPUs.
10157 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10158 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10159 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10160 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10161 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10164 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10165 vmx_flush_tlb(vcpu
);
10172 * Conceptually we want to copy the PML address and index from
10173 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10174 * since we always flush the log on each vmexit, this happens
10175 * to be equivalent to simply resetting the fields in vmcs02.
10177 ASSERT(vmx
->pml_pg
);
10178 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10179 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10182 if (nested_cpu_has_ept(vmcs12
)) {
10183 if (nested_ept_init_mmu_context(vcpu
)) {
10184 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10187 } else if (nested_cpu_has2(vmcs12
,
10188 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10189 vmx_flush_tlb_ept_only(vcpu
);
10193 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10194 * bits which we consider mandatory enabled.
10195 * The CR0_READ_SHADOW is what L2 should have expected to read given
10196 * the specifications by L1; It's not enough to take
10197 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10198 * have more bits than L1 expected.
10200 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10201 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10203 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10204 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10206 if (from_vmentry
&&
10207 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10208 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10209 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10210 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10212 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10213 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10214 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10216 /* Shadow page tables on either EPT or shadow page tables. */
10217 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10218 entry_failure_code
))
10222 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10225 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10228 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10229 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10230 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10231 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10234 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10235 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10239 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10243 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10244 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10245 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10247 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10248 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10250 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10251 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10253 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10254 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10256 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10257 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10258 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10259 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10260 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10261 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10262 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10263 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10264 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10265 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10266 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10267 vmx
->nested
.nested_vmx_exit_ctls_low
,
10268 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10269 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10270 vmx
->nested
.nested_vmx_entry_ctls_low
,
10271 vmx
->nested
.nested_vmx_entry_ctls_high
))
10272 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10274 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10275 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10277 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10278 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10279 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10280 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10285 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10290 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10292 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10293 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10296 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10297 vmcs12
->vmcs_link_pointer
!= -1ull) {
10298 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10303 * If the load IA32_EFER VM-entry control is 1, the following checks
10304 * are performed on the field for the IA32_EFER MSR:
10305 * - Bits reserved in the IA32_EFER MSR must be 0.
10306 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10307 * the IA-32e mode guest VM-exit control. It must also be identical
10308 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10311 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10312 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10313 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10314 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10315 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10316 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10317 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10322 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10323 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10324 * the values of the LMA and LME bits in the field must each be that of
10325 * the host address-space size VM-exit control.
10327 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10328 ia32e
= (vmcs12
->vm_exit_controls
&
10329 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10330 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10331 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10332 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10339 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10341 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10342 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10343 struct loaded_vmcs
*vmcs02
;
10347 vmcs02
= nested_get_current_vmcs02(vmx
);
10351 enter_guest_mode(vcpu
);
10353 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10354 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10356 vmx_switch_vmcs(vcpu
, vmcs02
);
10357 vmx_segment_cache_clear(vmx
);
10359 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10360 leave_guest_mode(vcpu
);
10361 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10362 nested_vmx_entry_failure(vcpu
, vmcs12
,
10363 EXIT_REASON_INVALID_STATE
, exit_qual
);
10367 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10369 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10370 vmcs12
->vm_entry_msr_load_addr
,
10371 vmcs12
->vm_entry_msr_load_count
);
10372 if (msr_entry_idx
) {
10373 leave_guest_mode(vcpu
);
10374 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10375 nested_vmx_entry_failure(vcpu
, vmcs12
,
10376 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10380 vmcs12
->launch_state
= 1;
10383 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10384 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10385 * returned as far as L1 is concerned. It will only return (and set
10386 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10392 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10393 * for running an L2 nested guest.
10395 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10397 struct vmcs12
*vmcs12
;
10398 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10402 if (!nested_vmx_check_permission(vcpu
))
10405 if (!nested_vmx_check_vmcs12(vcpu
))
10408 vmcs12
= get_vmcs12(vcpu
);
10410 if (enable_shadow_vmcs
)
10411 copy_shadow_to_vmcs12(vmx
);
10414 * The nested entry process starts with enforcing various prerequisites
10415 * on vmcs12 as required by the Intel SDM, and act appropriately when
10416 * they fail: As the SDM explains, some conditions should cause the
10417 * instruction to fail, while others will cause the instruction to seem
10418 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10419 * To speed up the normal (success) code path, we should avoid checking
10420 * for misconfigurations which will anyway be caught by the processor
10421 * when using the merged vmcs02.
10423 if (vmcs12
->launch_state
== launch
) {
10424 nested_vmx_failValid(vcpu
,
10425 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10426 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10430 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10432 nested_vmx_failValid(vcpu
, ret
);
10437 * After this point, the trap flag no longer triggers a singlestep trap
10438 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10439 * This is not 100% correct; for performance reasons, we delegate most
10440 * of the checks on host state to the processor. If those fail,
10441 * the singlestep trap is missed.
10443 skip_emulated_instruction(vcpu
);
10445 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10447 nested_vmx_entry_failure(vcpu
, vmcs12
,
10448 EXIT_REASON_INVALID_STATE
, exit_qual
);
10453 * We're finally done with prerequisite checking, and can start with
10454 * the nested entry.
10457 ret
= enter_vmx_non_root_mode(vcpu
, true);
10461 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10462 return kvm_vcpu_halt(vcpu
);
10464 vmx
->nested
.nested_run_pending
= 1;
10469 return kvm_skip_emulated_instruction(vcpu
);
10473 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10474 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10475 * This function returns the new value we should put in vmcs12.guest_cr0.
10476 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10477 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10478 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10479 * didn't trap the bit, because if L1 did, so would L0).
10480 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10481 * been modified by L2, and L1 knows it. So just leave the old value of
10482 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10483 * isn't relevant, because if L0 traps this bit it can set it to anything.
10484 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10485 * changed these bits, and therefore they need to be updated, but L0
10486 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10487 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10489 static inline unsigned long
10490 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10493 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10494 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10495 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10496 vcpu
->arch
.cr0_guest_owned_bits
));
10499 static inline unsigned long
10500 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10503 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10504 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10505 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10506 vcpu
->arch
.cr4_guest_owned_bits
));
10509 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10510 struct vmcs12
*vmcs12
)
10515 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10516 nr
= vcpu
->arch
.exception
.nr
;
10517 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10519 if (kvm_exception_is_soft(nr
)) {
10520 vmcs12
->vm_exit_instruction_len
=
10521 vcpu
->arch
.event_exit_inst_len
;
10522 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10524 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10526 if (vcpu
->arch
.exception
.has_error_code
) {
10527 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10528 vmcs12
->idt_vectoring_error_code
=
10529 vcpu
->arch
.exception
.error_code
;
10532 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10533 } else if (vcpu
->arch
.nmi_injected
) {
10534 vmcs12
->idt_vectoring_info_field
=
10535 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10536 } else if (vcpu
->arch
.interrupt
.pending
) {
10537 nr
= vcpu
->arch
.interrupt
.nr
;
10538 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10540 if (vcpu
->arch
.interrupt
.soft
) {
10541 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10542 vmcs12
->vm_entry_instruction_len
=
10543 vcpu
->arch
.event_exit_inst_len
;
10545 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10547 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10551 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10553 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10555 if (vcpu
->arch
.exception
.pending
||
10556 vcpu
->arch
.nmi_injected
||
10557 vcpu
->arch
.interrupt
.pending
)
10560 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10561 vmx
->nested
.preemption_timer_expired
) {
10562 if (vmx
->nested
.nested_run_pending
)
10564 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10568 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10569 if (vmx
->nested
.nested_run_pending
)
10571 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10572 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10573 INTR_INFO_VALID_MASK
, 0);
10575 * The NMI-triggered VM exit counts as injection:
10576 * clear this one and block further NMIs.
10578 vcpu
->arch
.nmi_pending
= 0;
10579 vmx_set_nmi_mask(vcpu
, true);
10583 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10584 nested_exit_on_intr(vcpu
)) {
10585 if (vmx
->nested
.nested_run_pending
)
10587 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10591 vmx_complete_nested_posted_interrupt(vcpu
);
10595 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10597 ktime_t remaining
=
10598 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10601 if (ktime_to_ns(remaining
) <= 0)
10604 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10605 do_div(value
, 1000000);
10606 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10610 * Update the guest state fields of vmcs12 to reflect changes that
10611 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10612 * VM-entry controls is also updated, since this is really a guest
10615 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10617 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10618 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10620 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10621 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10622 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10624 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10625 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10626 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10627 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10628 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10629 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10630 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10631 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10632 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10633 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10634 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10635 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10636 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10637 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10638 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10639 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10640 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10641 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10642 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10643 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10644 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10645 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10646 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10647 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10648 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10649 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10650 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10651 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10652 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10653 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10654 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10655 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10656 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10657 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10658 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10659 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10661 vmcs12
->guest_interruptibility_info
=
10662 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10663 vmcs12
->guest_pending_dbg_exceptions
=
10664 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10665 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10666 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10668 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10670 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10671 if (vmcs12
->vm_exit_controls
&
10672 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10673 vmcs12
->vmx_preemption_timer_value
=
10674 vmx_get_preemption_timer_value(vcpu
);
10675 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10679 * In some cases (usually, nested EPT), L2 is allowed to change its
10680 * own CR3 without exiting. If it has changed it, we must keep it.
10681 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10682 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10684 * Additionally, restore L2's PDPTR to vmcs12.
10687 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10688 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10689 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10690 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10691 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10694 if (nested_cpu_has_ept(vmcs12
))
10695 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10697 if (nested_cpu_has_vid(vmcs12
))
10698 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10700 vmcs12
->vm_entry_controls
=
10701 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10702 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10704 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10705 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10706 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10709 /* TODO: These cannot have changed unless we have MSR bitmaps and
10710 * the relevant bit asks not to trap the change */
10711 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10712 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10713 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10714 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10715 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10716 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10717 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10718 if (kvm_mpx_supported())
10719 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10720 if (nested_cpu_has_xsaves(vmcs12
))
10721 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10725 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10726 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10727 * and this function updates it to reflect the changes to the guest state while
10728 * L2 was running (and perhaps made some exits which were handled directly by L0
10729 * without going back to L1), and to reflect the exit reason.
10730 * Note that we do not have to copy here all VMCS fields, just those that
10731 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10732 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10733 * which already writes to vmcs12 directly.
10735 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10736 u32 exit_reason
, u32 exit_intr_info
,
10737 unsigned long exit_qualification
)
10739 /* update guest state fields: */
10740 sync_vmcs12(vcpu
, vmcs12
);
10742 /* update exit information fields: */
10744 vmcs12
->vm_exit_reason
= exit_reason
;
10745 vmcs12
->exit_qualification
= exit_qualification
;
10747 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10748 if ((vmcs12
->vm_exit_intr_info
&
10749 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10750 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10751 vmcs12
->vm_exit_intr_error_code
=
10752 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10753 vmcs12
->idt_vectoring_info_field
= 0;
10754 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10755 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10757 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10758 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10759 * instead of reading the real value. */
10760 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10763 * Transfer the event that L0 or L1 may wanted to inject into
10764 * L2 to IDT_VECTORING_INFO_FIELD.
10766 vmcs12_save_pending_event(vcpu
, vmcs12
);
10770 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10771 * preserved above and would only end up incorrectly in L1.
10773 vcpu
->arch
.nmi_injected
= false;
10774 kvm_clear_exception_queue(vcpu
);
10775 kvm_clear_interrupt_queue(vcpu
);
10779 * A part of what we need to when the nested L2 guest exits and we want to
10780 * run its L1 parent, is to reset L1's guest state to the host state specified
10782 * This function is to be called not only on normal nested exit, but also on
10783 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10784 * Failures During or After Loading Guest State").
10785 * This function should be called when the active VMCS is L1's (vmcs01).
10787 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10788 struct vmcs12
*vmcs12
)
10790 struct kvm_segment seg
;
10791 u32 entry_failure_code
;
10793 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10794 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10795 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10796 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10798 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10799 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10801 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10802 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10803 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10805 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10806 * actually changed, because vmx_set_cr0 refers to efer set above.
10808 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
10809 * (KVM doesn't change it);
10811 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
10812 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10814 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
10815 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10816 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10818 nested_ept_uninit_mmu_context(vcpu
);
10821 * Only PDPTE load can fail as the value of cr3 was checked on entry and
10822 * couldn't have changed.
10824 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
10825 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
10828 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10832 * Trivially support vpid by letting L2s share their parent
10833 * L1's vpid. TODO: move to a more elaborate solution, giving
10834 * each L2 its own vpid and exposing the vpid feature to L1.
10836 vmx_flush_tlb(vcpu
);
10840 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10841 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10842 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10843 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10844 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10846 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10847 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10848 vmcs_write64(GUEST_BNDCFGS
, 0);
10850 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10851 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10852 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10854 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10855 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10856 vmcs12
->host_ia32_perf_global_ctrl
);
10858 /* Set L1 segment info according to Intel SDM
10859 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10860 seg
= (struct kvm_segment
) {
10862 .limit
= 0xFFFFFFFF,
10863 .selector
= vmcs12
->host_cs_selector
,
10869 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10873 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10874 seg
= (struct kvm_segment
) {
10876 .limit
= 0xFFFFFFFF,
10883 seg
.selector
= vmcs12
->host_ds_selector
;
10884 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10885 seg
.selector
= vmcs12
->host_es_selector
;
10886 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10887 seg
.selector
= vmcs12
->host_ss_selector
;
10888 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10889 seg
.selector
= vmcs12
->host_fs_selector
;
10890 seg
.base
= vmcs12
->host_fs_base
;
10891 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10892 seg
.selector
= vmcs12
->host_gs_selector
;
10893 seg
.base
= vmcs12
->host_gs_base
;
10894 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10895 seg
= (struct kvm_segment
) {
10896 .base
= vmcs12
->host_tr_base
,
10898 .selector
= vmcs12
->host_tr_selector
,
10902 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10904 kvm_set_dr(vcpu
, 7, 0x400);
10905 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10907 if (cpu_has_vmx_msr_bitmap())
10908 vmx_set_msr_bitmap(vcpu
);
10910 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10911 vmcs12
->vm_exit_msr_load_count
))
10912 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10916 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10917 * and modify vmcs12 to make it see what it would expect to see there if
10918 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10920 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10921 u32 exit_intr_info
,
10922 unsigned long exit_qualification
)
10924 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10925 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10926 u32 vm_inst_error
= 0;
10928 /* trying to cancel vmlaunch/vmresume is a bug */
10929 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10931 leave_guest_mode(vcpu
);
10932 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10933 exit_qualification
);
10935 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10936 vmcs12
->vm_exit_msr_store_count
))
10937 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10939 if (unlikely(vmx
->fail
))
10940 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
10942 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10944 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10945 && nested_exit_intr_ack_set(vcpu
)) {
10946 int irq
= kvm_cpu_get_interrupt(vcpu
);
10948 vmcs12
->vm_exit_intr_info
= irq
|
10949 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10952 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10953 vmcs12
->exit_qualification
,
10954 vmcs12
->idt_vectoring_info_field
,
10955 vmcs12
->vm_exit_intr_info
,
10956 vmcs12
->vm_exit_intr_error_code
,
10959 vm_entry_controls_reset_shadow(vmx
);
10960 vm_exit_controls_reset_shadow(vmx
);
10961 vmx_segment_cache_clear(vmx
);
10963 /* if no vmcs02 cache requested, remove the one we used */
10964 if (VMCS02_POOL_SIZE
== 0)
10965 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10967 load_vmcs12_host_state(vcpu
, vmcs12
);
10969 /* Update any VMCS fields that might have changed while L2 ran */
10970 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10971 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10972 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10973 if (vmx
->hv_deadline_tsc
== -1)
10974 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
10975 PIN_BASED_VMX_PREEMPTION_TIMER
);
10977 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
10978 PIN_BASED_VMX_PREEMPTION_TIMER
);
10979 if (kvm_has_tsc_control
)
10980 decache_tsc_multiplier(vmx
);
10982 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
10983 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
10984 vmx_set_virtual_x2apic_mode(vcpu
,
10985 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
10986 } else if (!nested_cpu_has_ept(vmcs12
) &&
10987 nested_cpu_has2(vmcs12
,
10988 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10989 vmx_flush_tlb_ept_only(vcpu
);
10992 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10995 /* Unpin physical memory we referred to in vmcs02 */
10996 if (vmx
->nested
.apic_access_page
) {
10997 nested_release_page(vmx
->nested
.apic_access_page
);
10998 vmx
->nested
.apic_access_page
= NULL
;
11000 if (vmx
->nested
.virtual_apic_page
) {
11001 nested_release_page(vmx
->nested
.virtual_apic_page
);
11002 vmx
->nested
.virtual_apic_page
= NULL
;
11004 if (vmx
->nested
.pi_desc_page
) {
11005 kunmap(vmx
->nested
.pi_desc_page
);
11006 nested_release_page(vmx
->nested
.pi_desc_page
);
11007 vmx
->nested
.pi_desc_page
= NULL
;
11008 vmx
->nested
.pi_desc
= NULL
;
11012 * We are now running in L2, mmu_notifier will force to reload the
11013 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11015 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11018 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11019 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11020 * success or failure flag accordingly.
11022 if (unlikely(vmx
->fail
)) {
11024 nested_vmx_failValid(vcpu
, vm_inst_error
);
11026 nested_vmx_succeed(vcpu
);
11027 if (enable_shadow_vmcs
)
11028 vmx
->nested
.sync_shadow_vmcs
= true;
11030 /* in case we halted in L2 */
11031 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11035 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11037 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11039 if (is_guest_mode(vcpu
)) {
11040 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11041 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11043 free_nested(to_vmx(vcpu
));
11047 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11048 * 23.7 "VM-entry failures during or after loading guest state" (this also
11049 * lists the acceptable exit-reason and exit-qualification parameters).
11050 * It should only be called before L2 actually succeeded to run, and when
11051 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11053 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11054 struct vmcs12
*vmcs12
,
11055 u32 reason
, unsigned long qualification
)
11057 load_vmcs12_host_state(vcpu
, vmcs12
);
11058 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11059 vmcs12
->exit_qualification
= qualification
;
11060 nested_vmx_succeed(vcpu
);
11061 if (enable_shadow_vmcs
)
11062 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11065 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11066 struct x86_instruction_info
*info
,
11067 enum x86_intercept_stage stage
)
11069 return X86EMUL_CONTINUE
;
11072 #ifdef CONFIG_X86_64
11073 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11074 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11075 u64 divisor
, u64
*result
)
11077 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11079 /* To avoid the overflow on divq */
11080 if (high
>= divisor
)
11083 /* Low hold the result, high hold rem which is discarded */
11084 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11085 "rm" (divisor
), "0" (low
), "1" (high
));
11091 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11093 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11094 u64 tscl
= rdtsc();
11095 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11096 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11098 /* Convert to host delta tsc if tsc scaling is enabled */
11099 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11100 u64_shl_div_u64(delta_tsc
,
11101 kvm_tsc_scaling_ratio_frac_bits
,
11102 vcpu
->arch
.tsc_scaling_ratio
,
11107 * If the delta tsc can't fit in the 32 bit after the multi shift,
11108 * we can't use the preemption timer.
11109 * It's possible that it fits on later vmentries, but checking
11110 * on every vmentry is costly so we just use an hrtimer.
11112 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11115 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11116 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11117 PIN_BASED_VMX_PREEMPTION_TIMER
);
11121 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11123 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11124 vmx
->hv_deadline_tsc
= -1;
11125 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11126 PIN_BASED_VMX_PREEMPTION_TIMER
);
11130 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11133 shrink_ple_window(vcpu
);
11136 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11137 struct kvm_memory_slot
*slot
)
11139 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11140 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11143 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11144 struct kvm_memory_slot
*slot
)
11146 kvm_mmu_slot_set_dirty(kvm
, slot
);
11149 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11151 kvm_flush_pml_buffers(kvm
);
11154 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11155 struct kvm_memory_slot
*memslot
,
11156 gfn_t offset
, unsigned long mask
)
11158 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11162 * This routine does the following things for vCPU which is going
11163 * to be blocked if VT-d PI is enabled.
11164 * - Store the vCPU to the wakeup list, so when interrupts happen
11165 * we can find the right vCPU to wake up.
11166 * - Change the Posted-interrupt descriptor as below:
11167 * 'NDST' <-- vcpu->pre_pcpu
11168 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11169 * - If 'ON' is set during this process, which means at least one
11170 * interrupt is posted for this vCPU, we cannot block it, in
11171 * this case, return 1, otherwise, return 0.
11174 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11176 unsigned long flags
;
11178 struct pi_desc old
, new;
11179 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11181 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11182 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11183 !kvm_vcpu_apicv_active(vcpu
))
11186 vcpu
->pre_pcpu
= vcpu
->cpu
;
11187 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11188 vcpu
->pre_pcpu
), flags
);
11189 list_add_tail(&vcpu
->blocked_vcpu_list
,
11190 &per_cpu(blocked_vcpu_on_cpu
,
11192 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
11193 vcpu
->pre_pcpu
), flags
);
11196 old
.control
= new.control
= pi_desc
->control
;
11199 * We should not block the vCPU if
11200 * an interrupt is posted for it.
11202 if (pi_test_on(pi_desc
) == 1) {
11203 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
11204 vcpu
->pre_pcpu
), flags
);
11205 list_del(&vcpu
->blocked_vcpu_list
);
11206 spin_unlock_irqrestore(
11207 &per_cpu(blocked_vcpu_on_cpu_lock
,
11208 vcpu
->pre_pcpu
), flags
);
11209 vcpu
->pre_pcpu
= -1;
11214 WARN((pi_desc
->sn
== 1),
11215 "Warning: SN field of posted-interrupts "
11216 "is set before blocking\n");
11219 * Since vCPU can be preempted during this process,
11220 * vcpu->cpu could be different with pre_pcpu, we
11221 * need to set pre_pcpu as the destination of wakeup
11222 * notification event, then we can find the right vCPU
11223 * to wakeup in wakeup handler if interrupts happen
11224 * when the vCPU is in blocked state.
11226 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11228 if (x2apic_enabled())
11231 new.ndst
= (dest
<< 8) & 0xFF00;
11233 /* set 'NV' to 'wakeup vector' */
11234 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11235 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11236 new.control
) != old
.control
);
11241 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11243 if (pi_pre_block(vcpu
))
11246 if (kvm_lapic_hv_timer_in_use(vcpu
))
11247 kvm_lapic_switch_to_sw_timer(vcpu
);
11252 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11254 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11255 struct pi_desc old
, new;
11257 unsigned long flags
;
11259 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11260 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11261 !kvm_vcpu_apicv_active(vcpu
))
11265 old
.control
= new.control
= pi_desc
->control
;
11267 dest
= cpu_physical_id(vcpu
->cpu
);
11269 if (x2apic_enabled())
11272 new.ndst
= (dest
<< 8) & 0xFF00;
11274 /* Allow posting non-urgent interrupts */
11277 /* set 'NV' to 'notification vector' */
11278 new.nv
= POSTED_INTR_VECTOR
;
11279 } while (cmpxchg(&pi_desc
->control
, old
.control
,
11280 new.control
) != old
.control
);
11282 if(vcpu
->pre_pcpu
!= -1) {
11284 &per_cpu(blocked_vcpu_on_cpu_lock
,
11285 vcpu
->pre_pcpu
), flags
);
11286 list_del(&vcpu
->blocked_vcpu_list
);
11287 spin_unlock_irqrestore(
11288 &per_cpu(blocked_vcpu_on_cpu_lock
,
11289 vcpu
->pre_pcpu
), flags
);
11290 vcpu
->pre_pcpu
= -1;
11294 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11296 if (kvm_x86_ops
->set_hv_timer
)
11297 kvm_lapic_switch_to_hv_timer(vcpu
);
11299 pi_post_block(vcpu
);
11303 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11306 * @host_irq: host irq of the interrupt
11307 * @guest_irq: gsi of the interrupt
11308 * @set: set or unset PI
11309 * returns 0 on success, < 0 on failure
11311 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11312 uint32_t guest_irq
, bool set
)
11314 struct kvm_kernel_irq_routing_entry
*e
;
11315 struct kvm_irq_routing_table
*irq_rt
;
11316 struct kvm_lapic_irq irq
;
11317 struct kvm_vcpu
*vcpu
;
11318 struct vcpu_data vcpu_info
;
11319 int idx
, ret
= -EINVAL
;
11321 if (!kvm_arch_has_assigned_device(kvm
) ||
11322 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11323 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11326 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11327 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11328 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
11330 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11331 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11334 * VT-d PI cannot support posting multicast/broadcast
11335 * interrupts to a vCPU, we still use interrupt remapping
11336 * for these kind of interrupts.
11338 * For lowest-priority interrupts, we only support
11339 * those with single CPU as the destination, e.g. user
11340 * configures the interrupts via /proc/irq or uses
11341 * irqbalance to make the interrupts single-CPU.
11343 * We will support full lowest-priority interrupt later.
11346 kvm_set_msi_irq(kvm
, e
, &irq
);
11347 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11349 * Make sure the IRTE is in remapped mode if
11350 * we don't handle it in posted mode.
11352 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11355 "failed to back to remapped mode, irq: %u\n",
11363 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11364 vcpu_info
.vector
= irq
.vector
;
11366 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11367 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11370 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11372 /* suppress notification event before unposting */
11373 pi_set_sn(vcpu_to_pi_desc(vcpu
));
11374 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11375 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
11379 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11387 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11391 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11393 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11394 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11395 FEATURE_CONTROL_LMCE
;
11397 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11398 ~FEATURE_CONTROL_LMCE
;
11401 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11402 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11403 .disabled_by_bios
= vmx_disabled_by_bios
,
11404 .hardware_setup
= hardware_setup
,
11405 .hardware_unsetup
= hardware_unsetup
,
11406 .check_processor_compatibility
= vmx_check_processor_compat
,
11407 .hardware_enable
= hardware_enable
,
11408 .hardware_disable
= hardware_disable
,
11409 .cpu_has_accelerated_tpr
= report_flexpriority
,
11410 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11412 .vcpu_create
= vmx_create_vcpu
,
11413 .vcpu_free
= vmx_free_vcpu
,
11414 .vcpu_reset
= vmx_vcpu_reset
,
11416 .prepare_guest_switch
= vmx_save_host_state
,
11417 .vcpu_load
= vmx_vcpu_load
,
11418 .vcpu_put
= vmx_vcpu_put
,
11420 .update_bp_intercept
= update_exception_bitmap
,
11421 .get_msr
= vmx_get_msr
,
11422 .set_msr
= vmx_set_msr
,
11423 .get_segment_base
= vmx_get_segment_base
,
11424 .get_segment
= vmx_get_segment
,
11425 .set_segment
= vmx_set_segment
,
11426 .get_cpl
= vmx_get_cpl
,
11427 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11428 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11429 .decache_cr3
= vmx_decache_cr3
,
11430 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11431 .set_cr0
= vmx_set_cr0
,
11432 .set_cr3
= vmx_set_cr3
,
11433 .set_cr4
= vmx_set_cr4
,
11434 .set_efer
= vmx_set_efer
,
11435 .get_idt
= vmx_get_idt
,
11436 .set_idt
= vmx_set_idt
,
11437 .get_gdt
= vmx_get_gdt
,
11438 .set_gdt
= vmx_set_gdt
,
11439 .get_dr6
= vmx_get_dr6
,
11440 .set_dr6
= vmx_set_dr6
,
11441 .set_dr7
= vmx_set_dr7
,
11442 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11443 .cache_reg
= vmx_cache_reg
,
11444 .get_rflags
= vmx_get_rflags
,
11445 .set_rflags
= vmx_set_rflags
,
11447 .get_pkru
= vmx_get_pkru
,
11449 .tlb_flush
= vmx_flush_tlb
,
11451 .run
= vmx_vcpu_run
,
11452 .handle_exit
= vmx_handle_exit
,
11453 .skip_emulated_instruction
= skip_emulated_instruction
,
11454 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11455 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11456 .patch_hypercall
= vmx_patch_hypercall
,
11457 .set_irq
= vmx_inject_irq
,
11458 .set_nmi
= vmx_inject_nmi
,
11459 .queue_exception
= vmx_queue_exception
,
11460 .cancel_injection
= vmx_cancel_injection
,
11461 .interrupt_allowed
= vmx_interrupt_allowed
,
11462 .nmi_allowed
= vmx_nmi_allowed
,
11463 .get_nmi_mask
= vmx_get_nmi_mask
,
11464 .set_nmi_mask
= vmx_set_nmi_mask
,
11465 .enable_nmi_window
= enable_nmi_window
,
11466 .enable_irq_window
= enable_irq_window
,
11467 .update_cr8_intercept
= update_cr8_intercept
,
11468 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11469 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11470 .get_enable_apicv
= vmx_get_enable_apicv
,
11471 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11472 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11473 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11474 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11475 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11476 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11477 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11479 .set_tss_addr
= vmx_set_tss_addr
,
11480 .get_tdp_level
= get_ept_level
,
11481 .get_mt_mask
= vmx_get_mt_mask
,
11483 .get_exit_info
= vmx_get_exit_info
,
11485 .get_lpage_level
= vmx_get_lpage_level
,
11487 .cpuid_update
= vmx_cpuid_update
,
11489 .rdtscp_supported
= vmx_rdtscp_supported
,
11490 .invpcid_supported
= vmx_invpcid_supported
,
11492 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11494 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11496 .write_tsc_offset
= vmx_write_tsc_offset
,
11498 .set_tdp_cr3
= vmx_set_cr3
,
11500 .check_intercept
= vmx_check_intercept
,
11501 .handle_external_intr
= vmx_handle_external_intr
,
11502 .mpx_supported
= vmx_mpx_supported
,
11503 .xsaves_supported
= vmx_xsaves_supported
,
11505 .check_nested_events
= vmx_check_nested_events
,
11507 .sched_in
= vmx_sched_in
,
11509 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11510 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11511 .flush_log_dirty
= vmx_flush_log_dirty
,
11512 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11514 .pre_block
= vmx_pre_block
,
11515 .post_block
= vmx_post_block
,
11517 .pmu_ops
= &intel_pmu_ops
,
11519 .update_pi_irte
= vmx_update_pi_irte
,
11521 #ifdef CONFIG_X86_64
11522 .set_hv_timer
= vmx_set_hv_timer
,
11523 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11526 .setup_mce
= vmx_setup_mce
,
11529 static int __init
vmx_init(void)
11531 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11532 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11536 #ifdef CONFIG_KEXEC_CORE
11537 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11538 crash_vmclear_local_loaded_vmcss
);
11544 static void __exit
vmx_exit(void)
11546 #ifdef CONFIG_KEXEC_CORE
11547 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11554 module_init(vmx_init
)
11555 module_exit(vmx_exit
)