2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id vmx_cpu_id
[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
59 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
61 static bool __read_mostly enable_vpid
= 1;
62 module_param_named(vpid
, enable_vpid
, bool, 0444);
64 static bool __read_mostly flexpriority_enabled
= 1;
65 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
67 static bool __read_mostly enable_ept
= 1;
68 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
70 static bool __read_mostly enable_unrestricted_guest
= 1;
71 module_param_named(unrestricted_guest
,
72 enable_unrestricted_guest
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept_ad_bits
= 1;
75 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
77 static bool __read_mostly emulate_invalid_guest_state
= true;
78 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
80 static bool __read_mostly vmm_exclusive
= 1;
81 module_param(vmm_exclusive
, bool, S_IRUGO
);
83 static bool __read_mostly fasteoi
= 1;
84 module_param(fasteoi
, bool, S_IRUGO
);
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
91 static bool __read_mostly nested
= 0;
92 module_param(nested
, bool, S_IRUGO
);
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
125 module_param(ple_gap
, int, S_IRUGO
);
127 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
128 module_param(ple_window
, int, S_IRUGO
);
130 extern const ulong vmx_return
;
132 #define NR_AUTOLOAD_MSRS 8
133 #define VMCS02_POOL_SIZE 1
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
150 struct list_head loaded_vmcss_on_cpu_link
;
153 struct shared_msr_entry
{
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
172 typedef u64 natural_width
;
173 struct __packed vmcs12
{
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
180 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding
[7]; /* room for future expansion */
186 u64 vm_exit_msr_store_addr
;
187 u64 vm_exit_msr_load_addr
;
188 u64 vm_entry_msr_load_addr
;
190 u64 virtual_apic_page_addr
;
191 u64 apic_access_addr
;
193 u64 guest_physical_address
;
194 u64 vmcs_link_pointer
;
195 u64 guest_ia32_debugctl
;
198 u64 guest_ia32_perf_global_ctrl
;
205 u64 host_ia32_perf_global_ctrl
;
206 u64 padding64
[8]; /* room for future expansion */
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
213 natural_width cr0_guest_host_mask
;
214 natural_width cr4_guest_host_mask
;
215 natural_width cr0_read_shadow
;
216 natural_width cr4_read_shadow
;
217 natural_width cr3_target_value0
;
218 natural_width cr3_target_value1
;
219 natural_width cr3_target_value2
;
220 natural_width cr3_target_value3
;
221 natural_width exit_qualification
;
222 natural_width guest_linear_address
;
223 natural_width guest_cr0
;
224 natural_width guest_cr3
;
225 natural_width guest_cr4
;
226 natural_width guest_es_base
;
227 natural_width guest_cs_base
;
228 natural_width guest_ss_base
;
229 natural_width guest_ds_base
;
230 natural_width guest_fs_base
;
231 natural_width guest_gs_base
;
232 natural_width guest_ldtr_base
;
233 natural_width guest_tr_base
;
234 natural_width guest_gdtr_base
;
235 natural_width guest_idtr_base
;
236 natural_width guest_dr7
;
237 natural_width guest_rsp
;
238 natural_width guest_rip
;
239 natural_width guest_rflags
;
240 natural_width guest_pending_dbg_exceptions
;
241 natural_width guest_sysenter_esp
;
242 natural_width guest_sysenter_eip
;
243 natural_width host_cr0
;
244 natural_width host_cr3
;
245 natural_width host_cr4
;
246 natural_width host_fs_base
;
247 natural_width host_gs_base
;
248 natural_width host_tr_base
;
249 natural_width host_gdtr_base
;
250 natural_width host_idtr_base
;
251 natural_width host_ia32_sysenter_esp
;
252 natural_width host_ia32_sysenter_eip
;
253 natural_width host_rsp
;
254 natural_width host_rip
;
255 natural_width paddingl
[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control
;
257 u32 cpu_based_vm_exec_control
;
258 u32 exception_bitmap
;
259 u32 page_fault_error_code_mask
;
260 u32 page_fault_error_code_match
;
261 u32 cr3_target_count
;
262 u32 vm_exit_controls
;
263 u32 vm_exit_msr_store_count
;
264 u32 vm_exit_msr_load_count
;
265 u32 vm_entry_controls
;
266 u32 vm_entry_msr_load_count
;
267 u32 vm_entry_intr_info_field
;
268 u32 vm_entry_exception_error_code
;
269 u32 vm_entry_instruction_len
;
271 u32 secondary_vm_exec_control
;
272 u32 vm_instruction_error
;
274 u32 vm_exit_intr_info
;
275 u32 vm_exit_intr_error_code
;
276 u32 idt_vectoring_info_field
;
277 u32 idt_vectoring_error_code
;
278 u32 vm_exit_instruction_len
;
279 u32 vmx_instruction_info
;
286 u32 guest_ldtr_limit
;
288 u32 guest_gdtr_limit
;
289 u32 guest_idtr_limit
;
290 u32 guest_es_ar_bytes
;
291 u32 guest_cs_ar_bytes
;
292 u32 guest_ss_ar_bytes
;
293 u32 guest_ds_ar_bytes
;
294 u32 guest_fs_ar_bytes
;
295 u32 guest_gs_ar_bytes
;
296 u32 guest_ldtr_ar_bytes
;
297 u32 guest_tr_ar_bytes
;
298 u32 guest_interruptibility_info
;
299 u32 guest_activity_state
;
300 u32 guest_sysenter_cs
;
301 u32 host_ia32_sysenter_cs
;
302 u32 padding32
[8]; /* room for future expansion */
303 u16 virtual_processor_id
;
304 u16 guest_es_selector
;
305 u16 guest_cs_selector
;
306 u16 guest_ss_selector
;
307 u16 guest_ds_selector
;
308 u16 guest_fs_selector
;
309 u16 guest_gs_selector
;
310 u16 guest_ldtr_selector
;
311 u16 guest_tr_selector
;
312 u16 host_es_selector
;
313 u16 host_cs_selector
;
314 u16 host_ss_selector
;
315 u16 host_ds_selector
;
316 u16 host_fs_selector
;
317 u16 host_gs_selector
;
318 u16 host_tr_selector
;
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
326 #define VMCS12_REVISION 0x11e57ed0
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
333 #define VMCS12_SIZE 0x1000
335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
337 struct list_head list
;
339 struct loaded_vmcs vmcs02
;
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
347 /* Has the level1 guest done vmxon? */
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
352 /* The host-usable pointer to the above */
353 struct page
*current_vmcs12_page
;
354 struct vmcs12
*current_vmcs12
;
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool
;
359 u64 vmcs01_tsc_offset
;
360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending
;
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
366 struct page
*apic_access_page
;
370 struct kvm_vcpu vcpu
;
371 unsigned long host_rsp
;
374 bool nmi_known_unmasked
;
376 u32 idt_vectoring_info
;
378 struct shared_msr_entry
*guest_msrs
;
382 u64 msr_host_kernel_gs_base
;
383 u64 msr_guest_kernel_gs_base
;
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
390 struct loaded_vmcs vmcs01
;
391 struct loaded_vmcs
*loaded_vmcs
;
392 bool __launched
; /* temporary, used in vmx_vcpu_run */
393 struct msr_autoload
{
395 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
396 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
400 u16 fs_sel
, gs_sel
, ldt_sel
;
404 int gs_ldt_reload_needed
;
405 int fs_reload_needed
;
410 struct kvm_segment segs
[8];
413 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
414 struct kvm_save_segment
{
422 bool emulation_required
;
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked
;
427 s64 vnmi_blocked_time
;
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested
;
436 enum segment_cache_field
{
445 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
447 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
455 static const unsigned short vmcs_field_to_offset_table
[] = {
456 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
457 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
458 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
459 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
460 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
461 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
462 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
463 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
464 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
465 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
466 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
467 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
468 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
469 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
470 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
471 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
472 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
473 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
474 FIELD64(MSR_BITMAP
, msr_bitmap
),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
478 FIELD64(TSC_OFFSET
, tsc_offset
),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
480 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
481 FIELD64(EPT_POINTER
, ept_pointer
),
482 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
483 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
484 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
485 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
486 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
488 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
489 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
490 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
491 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
492 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
493 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
497 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
500 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
501 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
502 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
504 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
509 FIELD(TPR_THRESHOLD
, tpr_threshold
),
510 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
511 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
512 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
513 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
514 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
515 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
516 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
517 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
518 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
519 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
520 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
521 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
522 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
523 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
524 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
525 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
526 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
527 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
528 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
529 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
530 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
531 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
532 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
533 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
534 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
535 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
536 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
538 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
539 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
540 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
541 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
542 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
543 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
544 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
545 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
546 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
547 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
548 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
549 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
550 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
551 FIELD(GUEST_CR0
, guest_cr0
),
552 FIELD(GUEST_CR3
, guest_cr3
),
553 FIELD(GUEST_CR4
, guest_cr4
),
554 FIELD(GUEST_ES_BASE
, guest_es_base
),
555 FIELD(GUEST_CS_BASE
, guest_cs_base
),
556 FIELD(GUEST_SS_BASE
, guest_ss_base
),
557 FIELD(GUEST_DS_BASE
, guest_ds_base
),
558 FIELD(GUEST_FS_BASE
, guest_fs_base
),
559 FIELD(GUEST_GS_BASE
, guest_gs_base
),
560 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
561 FIELD(GUEST_TR_BASE
, guest_tr_base
),
562 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
563 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
564 FIELD(GUEST_DR7
, guest_dr7
),
565 FIELD(GUEST_RSP
, guest_rsp
),
566 FIELD(GUEST_RIP
, guest_rip
),
567 FIELD(GUEST_RFLAGS
, guest_rflags
),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
569 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
570 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
571 FIELD(HOST_CR0
, host_cr0
),
572 FIELD(HOST_CR3
, host_cr3
),
573 FIELD(HOST_CR4
, host_cr4
),
574 FIELD(HOST_FS_BASE
, host_fs_base
),
575 FIELD(HOST_GS_BASE
, host_gs_base
),
576 FIELD(HOST_TR_BASE
, host_tr_base
),
577 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
578 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
579 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
580 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
581 FIELD(HOST_RSP
, host_rsp
),
582 FIELD(HOST_RIP
, host_rip
),
584 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
586 static inline short vmcs_field_to_offset(unsigned long field
)
588 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
590 return vmcs_field_to_offset_table
[field
];
593 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
595 return to_vmx(vcpu
)->nested
.current_vmcs12
;
598 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
600 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
601 if (is_error_page(page
))
607 static void nested_release_page(struct page
*page
)
609 kvm_release_page_dirty(page
);
612 static void nested_release_page_clean(struct page
*page
)
614 kvm_release_page_clean(page
);
617 static u64
construct_eptp(unsigned long root_hpa
);
618 static void kvm_cpu_vmxon(u64 addr
);
619 static void kvm_cpu_vmxoff(void);
620 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
621 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
622 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
623 struct kvm_segment
*var
, int seg
);
624 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
625 struct kvm_segment
*var
, int seg
);
627 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
628 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
633 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
634 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
636 static unsigned long *vmx_io_bitmap_a
;
637 static unsigned long *vmx_io_bitmap_b
;
638 static unsigned long *vmx_msr_bitmap_legacy
;
639 static unsigned long *vmx_msr_bitmap_longmode
;
641 static bool cpu_has_load_ia32_efer
;
642 static bool cpu_has_load_perf_global_ctrl
;
644 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
645 static DEFINE_SPINLOCK(vmx_vpid_lock
);
647 static struct vmcs_config
{
651 u32 pin_based_exec_ctrl
;
652 u32 cpu_based_exec_ctrl
;
653 u32 cpu_based_2nd_exec_ctrl
;
658 static struct vmx_capability
{
663 #define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
671 static const struct kvm_vmx_segment_field
{
676 } kvm_vmx_segment_fields
[] = {
677 VMX_SEGMENT_FIELD(CS
),
678 VMX_SEGMENT_FIELD(DS
),
679 VMX_SEGMENT_FIELD(ES
),
680 VMX_SEGMENT_FIELD(FS
),
681 VMX_SEGMENT_FIELD(GS
),
682 VMX_SEGMENT_FIELD(SS
),
683 VMX_SEGMENT_FIELD(TR
),
684 VMX_SEGMENT_FIELD(LDTR
),
687 static u64 host_efer
;
689 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
693 * away by decrementing the array size.
695 static const u32 vmx_msr_index
[] = {
697 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
699 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
701 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
703 static inline bool is_page_fault(u32 intr_info
)
705 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
706 INTR_INFO_VALID_MASK
)) ==
707 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
710 static inline bool is_no_device(u32 intr_info
)
712 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
713 INTR_INFO_VALID_MASK
)) ==
714 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
717 static inline bool is_invalid_opcode(u32 intr_info
)
719 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
720 INTR_INFO_VALID_MASK
)) ==
721 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
724 static inline bool is_external_interrupt(u32 intr_info
)
726 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
727 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
730 static inline bool is_machine_check(u32 intr_info
)
732 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
733 INTR_INFO_VALID_MASK
)) ==
734 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
737 static inline bool cpu_has_vmx_msr_bitmap(void)
739 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
742 static inline bool cpu_has_vmx_tpr_shadow(void)
744 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
747 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
752 static inline bool cpu_has_secondary_exec_ctrls(void)
754 return vmcs_config
.cpu_based_exec_ctrl
&
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
758 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
760 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
764 static inline bool cpu_has_vmx_flexpriority(void)
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
770 static inline bool cpu_has_vmx_ept_execute_only(void)
772 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
775 static inline bool cpu_has_vmx_eptp_uncacheable(void)
777 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
780 static inline bool cpu_has_vmx_eptp_writeback(void)
782 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
785 static inline bool cpu_has_vmx_ept_2m_page(void)
787 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
790 static inline bool cpu_has_vmx_ept_1g_page(void)
792 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
795 static inline bool cpu_has_vmx_ept_4levels(void)
797 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
800 static inline bool cpu_has_vmx_ept_ad_bits(void)
802 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
805 static inline bool cpu_has_vmx_invept_individual_addr(void)
807 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
810 static inline bool cpu_has_vmx_invept_context(void)
812 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
815 static inline bool cpu_has_vmx_invept_global(void)
817 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
820 static inline bool cpu_has_vmx_invvpid_single(void)
822 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
825 static inline bool cpu_has_vmx_invvpid_global(void)
827 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
830 static inline bool cpu_has_vmx_ept(void)
832 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
833 SECONDARY_EXEC_ENABLE_EPT
;
836 static inline bool cpu_has_vmx_unrestricted_guest(void)
838 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
839 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
842 static inline bool cpu_has_vmx_ple(void)
844 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
848 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
850 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
853 static inline bool cpu_has_vmx_vpid(void)
855 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
856 SECONDARY_EXEC_ENABLE_VPID
;
859 static inline bool cpu_has_vmx_rdtscp(void)
861 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
862 SECONDARY_EXEC_RDTSCP
;
865 static inline bool cpu_has_vmx_invpcid(void)
867 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
868 SECONDARY_EXEC_ENABLE_INVPCID
;
871 static inline bool cpu_has_virtual_nmis(void)
873 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
876 static inline bool cpu_has_vmx_wbinvd_exit(void)
878 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
879 SECONDARY_EXEC_WBINVD_EXITING
;
882 static inline bool report_flexpriority(void)
884 return flexpriority_enabled
;
887 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
889 return vmcs12
->cpu_based_vm_exec_control
& bit
;
892 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
894 return (vmcs12
->cpu_based_vm_exec_control
&
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
896 (vmcs12
->secondary_vm_exec_control
& bit
);
899 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
900 struct kvm_vcpu
*vcpu
)
902 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
905 static inline bool is_exception(u32 intr_info
)
907 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
908 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
911 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
912 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
913 struct vmcs12
*vmcs12
,
914 u32 reason
, unsigned long qualification
);
916 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
920 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
921 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
926 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
932 } operand
= { vpid
, 0, gva
};
934 asm volatile (__ex(ASM_VMX_INVVPID
)
935 /* CF==1 or ZF==1 --> rc = -1 */
937 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
940 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
944 } operand
= {eptp
, gpa
};
946 asm volatile (__ex(ASM_VMX_INVEPT
)
947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
952 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
956 i
= __find_msr_index(vmx
, msr
);
958 return &vmx
->guest_msrs
[i
];
962 static void vmcs_clear(struct vmcs
*vmcs
)
964 u64 phys_addr
= __pa(vmcs
);
967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
968 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
971 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
975 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
977 vmcs_clear(loaded_vmcs
->vmcs
);
978 loaded_vmcs
->cpu
= -1;
979 loaded_vmcs
->launched
= 0;
982 static void vmcs_load(struct vmcs
*vmcs
)
984 u64 phys_addr
= __pa(vmcs
);
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
988 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
991 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
995 static void __loaded_vmcs_clear(void *arg
)
997 struct loaded_vmcs
*loaded_vmcs
= arg
;
998 int cpu
= raw_smp_processor_id();
1000 if (loaded_vmcs
->cpu
!= cpu
)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1003 per_cpu(current_vmcs
, cpu
) = NULL
;
1004 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1007 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1008 * is before setting loaded_vmcs->vcpu to -1 which is done in
1009 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1010 * then adds the vmcs into percpu list before it is deleted.
1014 loaded_vmcs_init(loaded_vmcs
);
1017 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1019 int cpu
= loaded_vmcs
->cpu
;
1022 smp_call_function_single(cpu
,
1023 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1026 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1031 if (cpu_has_vmx_invvpid_single())
1032 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1035 static inline void vpid_sync_vcpu_global(void)
1037 if (cpu_has_vmx_invvpid_global())
1038 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1041 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1043 if (cpu_has_vmx_invvpid_single())
1044 vpid_sync_vcpu_single(vmx
);
1046 vpid_sync_vcpu_global();
1049 static inline void ept_sync_global(void)
1051 if (cpu_has_vmx_invept_global())
1052 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1055 static inline void ept_sync_context(u64 eptp
)
1058 if (cpu_has_vmx_invept_context())
1059 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1065 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
1068 if (cpu_has_vmx_invept_individual_addr())
1069 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
1072 ept_sync_context(eptp
);
1076 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1078 unsigned long value
;
1080 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1081 : "=a"(value
) : "d"(field
) : "cc");
1085 static __always_inline u16
vmcs_read16(unsigned long field
)
1087 return vmcs_readl(field
);
1090 static __always_inline u32
vmcs_read32(unsigned long field
)
1092 return vmcs_readl(field
);
1095 static __always_inline u64
vmcs_read64(unsigned long field
)
1097 #ifdef CONFIG_X86_64
1098 return vmcs_readl(field
);
1100 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1104 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1106 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1107 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1111 static void vmcs_writel(unsigned long field
, unsigned long value
)
1115 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1116 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1117 if (unlikely(error
))
1118 vmwrite_error(field
, value
);
1121 static void vmcs_write16(unsigned long field
, u16 value
)
1123 vmcs_writel(field
, value
);
1126 static void vmcs_write32(unsigned long field
, u32 value
)
1128 vmcs_writel(field
, value
);
1131 static void vmcs_write64(unsigned long field
, u64 value
)
1133 vmcs_writel(field
, value
);
1134 #ifndef CONFIG_X86_64
1136 vmcs_writel(field
+1, value
>> 32);
1140 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1142 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1145 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1147 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1150 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1152 vmx
->segment_cache
.bitmask
= 0;
1155 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1159 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1161 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1162 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1163 vmx
->segment_cache
.bitmask
= 0;
1165 ret
= vmx
->segment_cache
.bitmask
& mask
;
1166 vmx
->segment_cache
.bitmask
|= mask
;
1170 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1172 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1174 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1175 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1179 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1181 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1183 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1184 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1188 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1190 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1192 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1193 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1197 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1199 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1201 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1202 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1206 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1210 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1211 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1212 if ((vcpu
->guest_debug
&
1213 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1214 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1215 eb
|= 1u << BP_VECTOR
;
1216 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1219 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1220 if (vcpu
->fpu_active
)
1221 eb
&= ~(1u << NM_VECTOR
);
1223 /* When we are running a nested L2 guest and L1 specified for it a
1224 * certain exception bitmap, we must trap the same exceptions and pass
1225 * them to L1. When running L2, we will only handle the exceptions
1226 * specified above if L1 did not want them.
1228 if (is_guest_mode(vcpu
))
1229 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1231 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1234 static void clear_atomic_switch_msr_special(unsigned long entry
,
1237 vmcs_clear_bits(VM_ENTRY_CONTROLS
, entry
);
1238 vmcs_clear_bits(VM_EXIT_CONTROLS
, exit
);
1241 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1244 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1248 if (cpu_has_load_ia32_efer
) {
1249 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1250 VM_EXIT_LOAD_IA32_EFER
);
1254 case MSR_CORE_PERF_GLOBAL_CTRL
:
1255 if (cpu_has_load_perf_global_ctrl
) {
1256 clear_atomic_switch_msr_special(
1257 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1258 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1264 for (i
= 0; i
< m
->nr
; ++i
)
1265 if (m
->guest
[i
].index
== msr
)
1271 m
->guest
[i
] = m
->guest
[m
->nr
];
1272 m
->host
[i
] = m
->host
[m
->nr
];
1273 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1274 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1277 static void add_atomic_switch_msr_special(unsigned long entry
,
1278 unsigned long exit
, unsigned long guest_val_vmcs
,
1279 unsigned long host_val_vmcs
, u64 guest_val
, u64 host_val
)
1281 vmcs_write64(guest_val_vmcs
, guest_val
);
1282 vmcs_write64(host_val_vmcs
, host_val
);
1283 vmcs_set_bits(VM_ENTRY_CONTROLS
, entry
);
1284 vmcs_set_bits(VM_EXIT_CONTROLS
, exit
);
1287 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1288 u64 guest_val
, u64 host_val
)
1291 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1295 if (cpu_has_load_ia32_efer
) {
1296 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER
,
1297 VM_EXIT_LOAD_IA32_EFER
,
1300 guest_val
, host_val
);
1304 case MSR_CORE_PERF_GLOBAL_CTRL
:
1305 if (cpu_has_load_perf_global_ctrl
) {
1306 add_atomic_switch_msr_special(
1307 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1308 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1309 GUEST_IA32_PERF_GLOBAL_CTRL
,
1310 HOST_IA32_PERF_GLOBAL_CTRL
,
1311 guest_val
, host_val
);
1317 for (i
= 0; i
< m
->nr
; ++i
)
1318 if (m
->guest
[i
].index
== msr
)
1321 if (i
== NR_AUTOLOAD_MSRS
) {
1322 printk_once(KERN_WARNING
"Not enough mst switch entries. "
1323 "Can't add msr %x\n", msr
);
1325 } else if (i
== m
->nr
) {
1327 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1328 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1331 m
->guest
[i
].index
= msr
;
1332 m
->guest
[i
].value
= guest_val
;
1333 m
->host
[i
].index
= msr
;
1334 m
->host
[i
].value
= host_val
;
1337 static void reload_tss(void)
1340 * VT restores TR but not its size. Useless.
1342 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1343 struct desc_struct
*descs
;
1345 descs
= (void *)gdt
->address
;
1346 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1350 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1355 guest_efer
= vmx
->vcpu
.arch
.efer
;
1358 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1361 ignore_bits
= EFER_NX
| EFER_SCE
;
1362 #ifdef CONFIG_X86_64
1363 ignore_bits
|= EFER_LMA
| EFER_LME
;
1364 /* SCE is meaningful only in long mode on Intel */
1365 if (guest_efer
& EFER_LMA
)
1366 ignore_bits
&= ~(u64
)EFER_SCE
;
1368 guest_efer
&= ~ignore_bits
;
1369 guest_efer
|= host_efer
& ignore_bits
;
1370 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1371 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1373 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1374 /* On ept, can't emulate nx, and must switch nx atomically */
1375 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1376 guest_efer
= vmx
->vcpu
.arch
.efer
;
1377 if (!(guest_efer
& EFER_LMA
))
1378 guest_efer
&= ~EFER_LME
;
1379 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1386 static unsigned long segment_base(u16 selector
)
1388 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1389 struct desc_struct
*d
;
1390 unsigned long table_base
;
1393 if (!(selector
& ~3))
1396 table_base
= gdt
->address
;
1398 if (selector
& 4) { /* from ldt */
1399 u16 ldt_selector
= kvm_read_ldt();
1401 if (!(ldt_selector
& ~3))
1404 table_base
= segment_base(ldt_selector
);
1406 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1407 v
= get_desc_base(d
);
1408 #ifdef CONFIG_X86_64
1409 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1410 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1415 static inline unsigned long kvm_read_tr_base(void)
1418 asm("str %0" : "=g"(tr
));
1419 return segment_base(tr
);
1422 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1424 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1427 if (vmx
->host_state
.loaded
)
1430 vmx
->host_state
.loaded
= 1;
1432 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1433 * allow segment selectors with cpl > 0 or ti == 1.
1435 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1436 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1437 savesegment(fs
, vmx
->host_state
.fs_sel
);
1438 if (!(vmx
->host_state
.fs_sel
& 7)) {
1439 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1440 vmx
->host_state
.fs_reload_needed
= 0;
1442 vmcs_write16(HOST_FS_SELECTOR
, 0);
1443 vmx
->host_state
.fs_reload_needed
= 1;
1445 savesegment(gs
, vmx
->host_state
.gs_sel
);
1446 if (!(vmx
->host_state
.gs_sel
& 7))
1447 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1449 vmcs_write16(HOST_GS_SELECTOR
, 0);
1450 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1453 #ifdef CONFIG_X86_64
1454 savesegment(ds
, vmx
->host_state
.ds_sel
);
1455 savesegment(es
, vmx
->host_state
.es_sel
);
1458 #ifdef CONFIG_X86_64
1459 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1460 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1462 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1463 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1466 #ifdef CONFIG_X86_64
1467 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1468 if (is_long_mode(&vmx
->vcpu
))
1469 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1471 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1472 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1473 vmx
->guest_msrs
[i
].data
,
1474 vmx
->guest_msrs
[i
].mask
);
1477 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1479 if (!vmx
->host_state
.loaded
)
1482 ++vmx
->vcpu
.stat
.host_state_reload
;
1483 vmx
->host_state
.loaded
= 0;
1484 #ifdef CONFIG_X86_64
1485 if (is_long_mode(&vmx
->vcpu
))
1486 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1488 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1489 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1490 #ifdef CONFIG_X86_64
1491 load_gs_index(vmx
->host_state
.gs_sel
);
1493 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1496 if (vmx
->host_state
.fs_reload_needed
)
1497 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1498 #ifdef CONFIG_X86_64
1499 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1500 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1501 loadsegment(es
, vmx
->host_state
.es_sel
);
1505 #ifdef CONFIG_X86_64
1506 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1509 * If the FPU is not active (through the host task or
1510 * the guest vcpu), then restore the cr0.TS bit.
1512 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1514 load_gdt(&__get_cpu_var(host_gdt
));
1517 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1520 __vmx_load_host_state(vmx
);
1525 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1526 * vcpu mutex is already taken.
1528 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1530 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1531 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1534 kvm_cpu_vmxon(phys_addr
);
1535 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1536 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1538 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1539 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1540 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1543 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1544 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1545 unsigned long sysenter_esp
;
1547 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1548 local_irq_disable();
1551 * Read loaded_vmcs->cpu should be before fetching
1552 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1553 * See the comments in __loaded_vmcs_clear().
1557 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1558 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1562 * Linux uses per-cpu TSS and GDT, so set these when switching
1565 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1566 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1568 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1569 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1570 vmx
->loaded_vmcs
->cpu
= cpu
;
1574 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1576 __vmx_load_host_state(to_vmx(vcpu
));
1577 if (!vmm_exclusive
) {
1578 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1584 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1588 if (vcpu
->fpu_active
)
1590 vcpu
->fpu_active
= 1;
1591 cr0
= vmcs_readl(GUEST_CR0
);
1592 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1593 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1594 vmcs_writel(GUEST_CR0
, cr0
);
1595 update_exception_bitmap(vcpu
);
1596 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1597 if (is_guest_mode(vcpu
))
1598 vcpu
->arch
.cr0_guest_owned_bits
&=
1599 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1600 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1603 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1606 * Return the cr0 value that a nested guest would read. This is a combination
1607 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1608 * its hypervisor (cr0_read_shadow).
1610 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1612 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1613 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1615 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1617 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1618 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1621 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1623 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1624 * set this *before* calling this function.
1626 vmx_decache_cr0_guest_bits(vcpu
);
1627 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1628 update_exception_bitmap(vcpu
);
1629 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1630 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1631 if (is_guest_mode(vcpu
)) {
1633 * L1's specified read shadow might not contain the TS bit,
1634 * so now that we turned on shadowing of this bit, we need to
1635 * set this bit of the shadow. Like in nested_vmx_run we need
1636 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1637 * up-to-date here because we just decached cr0.TS (and we'll
1638 * only update vmcs12->guest_cr0 on nested exit).
1640 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1641 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1642 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1643 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1645 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1648 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1650 unsigned long rflags
, save_rflags
;
1652 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1653 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1654 rflags
= vmcs_readl(GUEST_RFLAGS
);
1655 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1656 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1657 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1658 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1660 to_vmx(vcpu
)->rflags
= rflags
;
1662 return to_vmx(vcpu
)->rflags
;
1665 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1667 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1668 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1669 to_vmx(vcpu
)->rflags
= rflags
;
1670 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1671 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1672 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1674 vmcs_writel(GUEST_RFLAGS
, rflags
);
1677 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1679 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1682 if (interruptibility
& GUEST_INTR_STATE_STI
)
1683 ret
|= KVM_X86_SHADOW_INT_STI
;
1684 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1685 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1690 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1692 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1693 u32 interruptibility
= interruptibility_old
;
1695 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1697 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1698 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1699 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1700 interruptibility
|= GUEST_INTR_STATE_STI
;
1702 if ((interruptibility
!= interruptibility_old
))
1703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1706 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1710 rip
= kvm_rip_read(vcpu
);
1711 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1712 kvm_rip_write(vcpu
, rip
);
1714 /* skipping an emulated instruction also counts */
1715 vmx_set_interrupt_shadow(vcpu
, 0);
1719 * KVM wants to inject page-faults which it got to the guest. This function
1720 * checks whether in a nested guest, we need to inject them to L1 or L2.
1721 * This function assumes it is called with the exit reason in vmcs02 being
1722 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1725 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1727 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1729 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1730 if (!(vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)))
1733 nested_vmx_vmexit(vcpu
);
1737 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1738 bool has_error_code
, u32 error_code
,
1741 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1742 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1744 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1745 nested_pf_handled(vcpu
))
1748 if (has_error_code
) {
1749 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1750 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1753 if (vmx
->rmode
.vm86_active
) {
1755 if (kvm_exception_is_soft(nr
))
1756 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1757 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1758 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1762 if (kvm_exception_is_soft(nr
)) {
1763 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1764 vmx
->vcpu
.arch
.event_exit_inst_len
);
1765 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1767 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1772 static bool vmx_rdtscp_supported(void)
1774 return cpu_has_vmx_rdtscp();
1777 static bool vmx_invpcid_supported(void)
1779 return cpu_has_vmx_invpcid() && enable_ept
;
1783 * Swap MSR entry in host/guest MSR entry array.
1785 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1787 struct shared_msr_entry tmp
;
1789 tmp
= vmx
->guest_msrs
[to
];
1790 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1791 vmx
->guest_msrs
[from
] = tmp
;
1795 * Set up the vmcs to automatically save and restore system
1796 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1797 * mode, as fiddling with msrs is very expensive.
1799 static void setup_msrs(struct vcpu_vmx
*vmx
)
1801 int save_nmsrs
, index
;
1802 unsigned long *msr_bitmap
;
1805 #ifdef CONFIG_X86_64
1806 if (is_long_mode(&vmx
->vcpu
)) {
1807 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1809 move_msr_up(vmx
, index
, save_nmsrs
++);
1810 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1812 move_msr_up(vmx
, index
, save_nmsrs
++);
1813 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1815 move_msr_up(vmx
, index
, save_nmsrs
++);
1816 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1817 if (index
>= 0 && vmx
->rdtscp_enabled
)
1818 move_msr_up(vmx
, index
, save_nmsrs
++);
1820 * MSR_STAR is only needed on long mode guests, and only
1821 * if efer.sce is enabled.
1823 index
= __find_msr_index(vmx
, MSR_STAR
);
1824 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1825 move_msr_up(vmx
, index
, save_nmsrs
++);
1828 index
= __find_msr_index(vmx
, MSR_EFER
);
1829 if (index
>= 0 && update_transition_efer(vmx
, index
))
1830 move_msr_up(vmx
, index
, save_nmsrs
++);
1832 vmx
->save_nmsrs
= save_nmsrs
;
1834 if (cpu_has_vmx_msr_bitmap()) {
1835 if (is_long_mode(&vmx
->vcpu
))
1836 msr_bitmap
= vmx_msr_bitmap_longmode
;
1838 msr_bitmap
= vmx_msr_bitmap_legacy
;
1840 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1845 * reads and returns guest's timestamp counter "register"
1846 * guest_tsc = host_tsc + tsc_offset -- 21.3
1848 static u64
guest_read_tsc(void)
1850 u64 host_tsc
, tsc_offset
;
1853 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1854 return host_tsc
+ tsc_offset
;
1858 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1859 * counter, even if a nested guest (L2) is currently running.
1861 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
1865 tsc_offset
= is_guest_mode(vcpu
) ?
1866 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
1867 vmcs_read64(TSC_OFFSET
);
1868 return host_tsc
+ tsc_offset
;
1872 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1873 * software catchup for faster rates on slower CPUs.
1875 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
1880 if (user_tsc_khz
> tsc_khz
) {
1881 vcpu
->arch
.tsc_catchup
= 1;
1882 vcpu
->arch
.tsc_always_catchup
= 1;
1884 WARN(1, "user requested TSC rate below hardware speed\n");
1888 * writes 'offset' into guest's timestamp counter offset register
1890 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1892 if (is_guest_mode(vcpu
)) {
1894 * We're here if L1 chose not to trap WRMSR to TSC. According
1895 * to the spec, this should set L1's TSC; The offset that L1
1896 * set for L2 remains unchanged, and still needs to be added
1897 * to the newly set TSC to get L2's TSC.
1899 struct vmcs12
*vmcs12
;
1900 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
1901 /* recalculate vmcs02.TSC_OFFSET: */
1902 vmcs12
= get_vmcs12(vcpu
);
1903 vmcs_write64(TSC_OFFSET
, offset
+
1904 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
1905 vmcs12
->tsc_offset
: 0));
1907 vmcs_write64(TSC_OFFSET
, offset
);
1911 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
1913 u64 offset
= vmcs_read64(TSC_OFFSET
);
1914 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1915 if (is_guest_mode(vcpu
)) {
1916 /* Even when running L2, the adjustment needs to apply to L1 */
1917 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1921 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1923 return target_tsc
- native_read_tsc();
1926 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1928 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1929 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1933 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1934 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1935 * all guests if the "nested" module option is off, and can also be disabled
1936 * for a single guest by disabling its VMX cpuid bit.
1938 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1940 return nested
&& guest_cpuid_has_vmx(vcpu
);
1944 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1945 * returned for the various VMX controls MSRs when nested VMX is enabled.
1946 * The same values should also be used to verify that vmcs12 control fields are
1947 * valid during nested entry from L1 to L2.
1948 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1949 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1950 * bit in the high half is on if the corresponding bit in the control field
1951 * may be on. See also vmx_control_verify().
1952 * TODO: allow these variables to be modified (downgraded) by module options
1955 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1956 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1957 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1958 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1959 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1960 static __init
void nested_vmx_setup_ctls_msrs(void)
1963 * Note that as a general rule, the high half of the MSRs (bits in
1964 * the control fields which may be 1) should be initialized by the
1965 * intersection of the underlying hardware's MSR (i.e., features which
1966 * can be supported) and the list of features we want to expose -
1967 * because they are known to be properly supported in our code.
1968 * Also, usually, the low half of the MSRs (bits which must be 1) can
1969 * be set to 0, meaning that L1 may turn off any of these bits. The
1970 * reason is that if one of these bits is necessary, it will appear
1971 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1972 * fields of vmcs01 and vmcs02, will turn these bits off - and
1973 * nested_vmx_exit_handled() will not pass related exits to L1.
1974 * These rules have exceptions below.
1977 /* pin-based controls */
1979 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1980 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1982 nested_vmx_pinbased_ctls_low
= 0x16 ;
1983 nested_vmx_pinbased_ctls_high
= 0x16 |
1984 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1985 PIN_BASED_VIRTUAL_NMIS
;
1988 nested_vmx_exit_ctls_low
= 0;
1989 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1990 #ifdef CONFIG_X86_64
1991 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1993 nested_vmx_exit_ctls_high
= 0;
1996 /* entry controls */
1997 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1998 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1999 nested_vmx_entry_ctls_low
= 0;
2000 nested_vmx_entry_ctls_high
&=
2001 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
2003 /* cpu-based controls */
2004 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2005 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2006 nested_vmx_procbased_ctls_low
= 0;
2007 nested_vmx_procbased_ctls_high
&=
2008 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2009 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2010 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2011 CPU_BASED_CR3_STORE_EXITING
|
2012 #ifdef CONFIG_X86_64
2013 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2015 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2016 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2017 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2018 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2020 * We can allow some features even when not supported by the
2021 * hardware. For example, L1 can specify an MSR bitmap - and we
2022 * can use it to avoid exits to L1 - even when L0 runs L2
2023 * without MSR bitmaps.
2025 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2027 /* secondary cpu-based controls */
2028 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2029 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2030 nested_vmx_secondary_ctls_low
= 0;
2031 nested_vmx_secondary_ctls_high
&=
2032 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2035 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2038 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2040 return ((control
& high
) | low
) == control
;
2043 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2045 return low
| ((u64
)high
<< 32);
2049 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2050 * also let it use VMX-specific MSRs.
2051 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2052 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2053 * like all other MSRs).
2055 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2057 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2058 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2060 * According to the spec, processors which do not support VMX
2061 * should throw a #GP(0) when VMX capability MSRs are read.
2063 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2067 switch (msr_index
) {
2068 case MSR_IA32_FEATURE_CONTROL
:
2071 case MSR_IA32_VMX_BASIC
:
2073 * This MSR reports some information about VMX support. We
2074 * should return information about the VMX we emulate for the
2075 * guest, and the VMCS structure we give it - not about the
2076 * VMX support of the underlying hardware.
2078 *pdata
= VMCS12_REVISION
|
2079 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2080 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2082 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2083 case MSR_IA32_VMX_PINBASED_CTLS
:
2084 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2085 nested_vmx_pinbased_ctls_high
);
2087 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2088 case MSR_IA32_VMX_PROCBASED_CTLS
:
2089 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2090 nested_vmx_procbased_ctls_high
);
2092 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2093 case MSR_IA32_VMX_EXIT_CTLS
:
2094 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2095 nested_vmx_exit_ctls_high
);
2097 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2098 case MSR_IA32_VMX_ENTRY_CTLS
:
2099 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2100 nested_vmx_entry_ctls_high
);
2102 case MSR_IA32_VMX_MISC
:
2106 * These MSRs specify bits which the guest must keep fixed (on or off)
2107 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2108 * We picked the standard core2 setting.
2110 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2111 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2112 case MSR_IA32_VMX_CR0_FIXED0
:
2113 *pdata
= VMXON_CR0_ALWAYSON
;
2115 case MSR_IA32_VMX_CR0_FIXED1
:
2118 case MSR_IA32_VMX_CR4_FIXED0
:
2119 *pdata
= VMXON_CR4_ALWAYSON
;
2121 case MSR_IA32_VMX_CR4_FIXED1
:
2124 case MSR_IA32_VMX_VMCS_ENUM
:
2127 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2128 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2129 nested_vmx_secondary_ctls_high
);
2131 case MSR_IA32_VMX_EPT_VPID_CAP
:
2132 /* Currently, no nested ept or nested vpid */
2142 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2144 if (!nested_vmx_allowed(vcpu
))
2147 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2148 /* TODO: the right thing. */
2151 * No need to treat VMX capability MSRs specially: If we don't handle
2152 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2158 * Reads an msr value (of 'msr_index') into 'pdata'.
2159 * Returns 0 on success, non-0 otherwise.
2160 * Assumes vcpu_load() was already called.
2162 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2165 struct shared_msr_entry
*msr
;
2168 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2172 switch (msr_index
) {
2173 #ifdef CONFIG_X86_64
2175 data
= vmcs_readl(GUEST_FS_BASE
);
2178 data
= vmcs_readl(GUEST_GS_BASE
);
2180 case MSR_KERNEL_GS_BASE
:
2181 vmx_load_host_state(to_vmx(vcpu
));
2182 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2186 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2188 data
= guest_read_tsc();
2190 case MSR_IA32_SYSENTER_CS
:
2191 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2193 case MSR_IA32_SYSENTER_EIP
:
2194 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2196 case MSR_IA32_SYSENTER_ESP
:
2197 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2200 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2202 /* Otherwise falls through */
2204 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2206 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2211 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2219 * Writes msr value into into the appropriate "register".
2220 * Returns 0 on success, non-0 otherwise.
2221 * Assumes vcpu_load() was already called.
2223 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2225 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2226 struct shared_msr_entry
*msr
;
2228 u32 msr_index
= msr_info
->index
;
2229 u64 data
= msr_info
->data
;
2231 switch (msr_index
) {
2233 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2235 #ifdef CONFIG_X86_64
2237 vmx_segment_cache_clear(vmx
);
2238 vmcs_writel(GUEST_FS_BASE
, data
);
2241 vmx_segment_cache_clear(vmx
);
2242 vmcs_writel(GUEST_GS_BASE
, data
);
2244 case MSR_KERNEL_GS_BASE
:
2245 vmx_load_host_state(vmx
);
2246 vmx
->msr_guest_kernel_gs_base
= data
;
2249 case MSR_IA32_SYSENTER_CS
:
2250 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2252 case MSR_IA32_SYSENTER_EIP
:
2253 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2255 case MSR_IA32_SYSENTER_ESP
:
2256 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2259 kvm_write_tsc(vcpu
, msr_info
);
2261 case MSR_IA32_CR_PAT
:
2262 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2263 vmcs_write64(GUEST_IA32_PAT
, data
);
2264 vcpu
->arch
.pat
= data
;
2267 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2270 if (!vmx
->rdtscp_enabled
)
2272 /* Check reserved bit, higher 32 bits should be zero */
2273 if ((data
>> 32) != 0)
2275 /* Otherwise falls through */
2277 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2279 msr
= find_msr_entry(vmx
, msr_index
);
2282 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2284 kvm_set_shared_msr(msr
->index
, msr
->data
,
2290 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2296 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2298 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2301 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2304 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2306 case VCPU_EXREG_PDPTR
:
2308 ept_save_pdptrs(vcpu
);
2315 static __init
int cpu_has_kvm_support(void)
2317 return cpu_has_vmx();
2320 static __init
int vmx_disabled_by_bios(void)
2324 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2325 if (msr
& FEATURE_CONTROL_LOCKED
) {
2326 /* launched w/ TXT and VMX disabled */
2327 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2330 /* launched w/o TXT and VMX only enabled w/ TXT */
2331 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2332 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2333 && !tboot_enabled()) {
2334 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2335 "activate TXT before enabling KVM\n");
2338 /* launched w/o TXT and VMX disabled */
2339 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2340 && !tboot_enabled())
2347 static void kvm_cpu_vmxon(u64 addr
)
2349 asm volatile (ASM_VMX_VMXON_RAX
2350 : : "a"(&addr
), "m"(addr
)
2354 static int hardware_enable(void *garbage
)
2356 int cpu
= raw_smp_processor_id();
2357 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2360 if (read_cr4() & X86_CR4_VMXE
)
2363 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2364 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2366 test_bits
= FEATURE_CONTROL_LOCKED
;
2367 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2368 if (tboot_enabled())
2369 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2371 if ((old
& test_bits
) != test_bits
) {
2372 /* enable and lock */
2373 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2375 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2377 if (vmm_exclusive
) {
2378 kvm_cpu_vmxon(phys_addr
);
2382 store_gdt(&__get_cpu_var(host_gdt
));
2387 static void vmclear_local_loaded_vmcss(void)
2389 int cpu
= raw_smp_processor_id();
2390 struct loaded_vmcs
*v
, *n
;
2392 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2393 loaded_vmcss_on_cpu_link
)
2394 __loaded_vmcs_clear(v
);
2398 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2401 static void kvm_cpu_vmxoff(void)
2403 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2406 static void hardware_disable(void *garbage
)
2408 if (vmm_exclusive
) {
2409 vmclear_local_loaded_vmcss();
2412 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2415 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2416 u32 msr
, u32
*result
)
2418 u32 vmx_msr_low
, vmx_msr_high
;
2419 u32 ctl
= ctl_min
| ctl_opt
;
2421 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2423 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2424 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2426 /* Ensure minimum (required) set of control bits are supported. */
2434 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2436 u32 vmx_msr_low
, vmx_msr_high
;
2438 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2439 return vmx_msr_high
& ctl
;
2442 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2444 u32 vmx_msr_low
, vmx_msr_high
;
2445 u32 min
, opt
, min2
, opt2
;
2446 u32 _pin_based_exec_control
= 0;
2447 u32 _cpu_based_exec_control
= 0;
2448 u32 _cpu_based_2nd_exec_control
= 0;
2449 u32 _vmexit_control
= 0;
2450 u32 _vmentry_control
= 0;
2452 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2453 opt
= PIN_BASED_VIRTUAL_NMIS
;
2454 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2455 &_pin_based_exec_control
) < 0)
2458 min
= CPU_BASED_HLT_EXITING
|
2459 #ifdef CONFIG_X86_64
2460 CPU_BASED_CR8_LOAD_EXITING
|
2461 CPU_BASED_CR8_STORE_EXITING
|
2463 CPU_BASED_CR3_LOAD_EXITING
|
2464 CPU_BASED_CR3_STORE_EXITING
|
2465 CPU_BASED_USE_IO_BITMAPS
|
2466 CPU_BASED_MOV_DR_EXITING
|
2467 CPU_BASED_USE_TSC_OFFSETING
|
2468 CPU_BASED_MWAIT_EXITING
|
2469 CPU_BASED_MONITOR_EXITING
|
2470 CPU_BASED_INVLPG_EXITING
|
2471 CPU_BASED_RDPMC_EXITING
;
2473 opt
= CPU_BASED_TPR_SHADOW
|
2474 CPU_BASED_USE_MSR_BITMAPS
|
2475 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2476 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2477 &_cpu_based_exec_control
) < 0)
2479 #ifdef CONFIG_X86_64
2480 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2481 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2482 ~CPU_BASED_CR8_STORE_EXITING
;
2484 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2486 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2487 SECONDARY_EXEC_WBINVD_EXITING
|
2488 SECONDARY_EXEC_ENABLE_VPID
|
2489 SECONDARY_EXEC_ENABLE_EPT
|
2490 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2491 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2492 SECONDARY_EXEC_RDTSCP
|
2493 SECONDARY_EXEC_ENABLE_INVPCID
;
2494 if (adjust_vmx_controls(min2
, opt2
,
2495 MSR_IA32_VMX_PROCBASED_CTLS2
,
2496 &_cpu_based_2nd_exec_control
) < 0)
2499 #ifndef CONFIG_X86_64
2500 if (!(_cpu_based_2nd_exec_control
&
2501 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2502 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2504 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2505 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2507 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2508 CPU_BASED_CR3_STORE_EXITING
|
2509 CPU_BASED_INVLPG_EXITING
);
2510 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2511 vmx_capability
.ept
, vmx_capability
.vpid
);
2515 #ifdef CONFIG_X86_64
2516 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2518 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2519 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2520 &_vmexit_control
) < 0)
2524 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2525 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2526 &_vmentry_control
) < 0)
2529 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2531 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2532 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2535 #ifdef CONFIG_X86_64
2536 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2537 if (vmx_msr_high
& (1u<<16))
2541 /* Require Write-Back (WB) memory type for VMCS accesses. */
2542 if (((vmx_msr_high
>> 18) & 15) != 6)
2545 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2546 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2547 vmcs_conf
->revision_id
= vmx_msr_low
;
2549 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2550 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2551 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2552 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2553 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2555 cpu_has_load_ia32_efer
=
2556 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2557 VM_ENTRY_LOAD_IA32_EFER
)
2558 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2559 VM_EXIT_LOAD_IA32_EFER
);
2561 cpu_has_load_perf_global_ctrl
=
2562 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2563 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2564 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2565 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2568 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2569 * but due to arrata below it can't be used. Workaround is to use
2570 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2572 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2577 * BC86,AAY89,BD102 (model 44)
2581 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2582 switch (boot_cpu_data
.x86_model
) {
2588 cpu_has_load_perf_global_ctrl
= false;
2589 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2590 "does not work properly. Using workaround\n");
2600 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2602 int node
= cpu_to_node(cpu
);
2606 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2609 vmcs
= page_address(pages
);
2610 memset(vmcs
, 0, vmcs_config
.size
);
2611 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2615 static struct vmcs
*alloc_vmcs(void)
2617 return alloc_vmcs_cpu(raw_smp_processor_id());
2620 static void free_vmcs(struct vmcs
*vmcs
)
2622 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2626 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2628 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2630 if (!loaded_vmcs
->vmcs
)
2632 loaded_vmcs_clear(loaded_vmcs
);
2633 free_vmcs(loaded_vmcs
->vmcs
);
2634 loaded_vmcs
->vmcs
= NULL
;
2637 static void free_kvm_area(void)
2641 for_each_possible_cpu(cpu
) {
2642 free_vmcs(per_cpu(vmxarea
, cpu
));
2643 per_cpu(vmxarea
, cpu
) = NULL
;
2647 static __init
int alloc_kvm_area(void)
2651 for_each_possible_cpu(cpu
) {
2654 vmcs
= alloc_vmcs_cpu(cpu
);
2660 per_cpu(vmxarea
, cpu
) = vmcs
;
2665 static __init
int hardware_setup(void)
2667 if (setup_vmcs_config(&vmcs_config
) < 0)
2670 if (boot_cpu_has(X86_FEATURE_NX
))
2671 kvm_enable_efer_bits(EFER_NX
);
2673 if (!cpu_has_vmx_vpid())
2676 if (!cpu_has_vmx_ept() ||
2677 !cpu_has_vmx_ept_4levels()) {
2679 enable_unrestricted_guest
= 0;
2680 enable_ept_ad_bits
= 0;
2683 if (!cpu_has_vmx_ept_ad_bits())
2684 enable_ept_ad_bits
= 0;
2686 if (!cpu_has_vmx_unrestricted_guest())
2687 enable_unrestricted_guest
= 0;
2689 if (!cpu_has_vmx_flexpriority())
2690 flexpriority_enabled
= 0;
2692 if (!cpu_has_vmx_tpr_shadow())
2693 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2695 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2696 kvm_disable_largepages();
2698 if (!cpu_has_vmx_ple())
2702 nested_vmx_setup_ctls_msrs();
2704 return alloc_kvm_area();
2707 static __exit
void hardware_unsetup(void)
2712 static void fix_pmode_dataseg(struct kvm_vcpu
*vcpu
, int seg
, struct kvm_segment
*save
)
2714 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2715 struct kvm_segment tmp
= *save
;
2717 if (!(vmcs_readl(sf
->base
) == tmp
.base
&& tmp
.s
)) {
2718 tmp
.base
= vmcs_readl(sf
->base
);
2719 tmp
.selector
= vmcs_read16(sf
->selector
);
2722 vmx_set_segment(vcpu
, &tmp
, seg
);
2725 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2727 unsigned long flags
;
2728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2730 vmx
->emulation_required
= 1;
2731 vmx
->rmode
.vm86_active
= 0;
2733 vmx_segment_cache_clear(vmx
);
2735 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2737 flags
= vmcs_readl(GUEST_RFLAGS
);
2738 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2739 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2740 vmcs_writel(GUEST_RFLAGS
, flags
);
2742 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2743 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2745 update_exception_bitmap(vcpu
);
2747 if (emulate_invalid_guest_state
)
2750 fix_pmode_dataseg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
2751 fix_pmode_dataseg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
2752 fix_pmode_dataseg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
2753 fix_pmode_dataseg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
2755 vmx_segment_cache_clear(vmx
);
2757 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2758 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2760 vmcs_write16(GUEST_CS_SELECTOR
,
2761 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2762 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2765 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2767 if (!kvm
->arch
.tss_addr
) {
2768 struct kvm_memslots
*slots
;
2769 struct kvm_memory_slot
*slot
;
2772 slots
= kvm_memslots(kvm
);
2773 slot
= id_to_memslot(slots
, 0);
2774 base_gfn
= slot
->base_gfn
+ slot
->npages
- 3;
2776 return base_gfn
<< PAGE_SHIFT
;
2778 return kvm
->arch
.tss_addr
;
2781 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
2783 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2785 vmcs_write16(sf
->selector
, save
->base
>> 4);
2786 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2787 vmcs_write32(sf
->limit
, 0xffff);
2788 vmcs_write32(sf
->ar_bytes
, 0xf3);
2789 if (save
->base
& 0xf)
2790 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2791 " aligned when entering protected mode (seg=%d)",
2795 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2797 unsigned long flags
;
2798 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2799 struct kvm_segment var
;
2801 if (enable_unrestricted_guest
)
2804 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
2805 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
2806 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
2807 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
2808 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
2810 vmx
->emulation_required
= 1;
2811 vmx
->rmode
.vm86_active
= 1;
2815 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2816 * vcpu. Call it here with phys address pointing 16M below 4G.
2818 if (!vcpu
->kvm
->arch
.tss_addr
) {
2819 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2820 "called before entering vcpu\n");
2821 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2822 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2823 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2826 vmx_segment_cache_clear(vmx
);
2828 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2829 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2830 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2832 flags
= vmcs_readl(GUEST_RFLAGS
);
2833 vmx
->rmode
.save_rflags
= flags
;
2835 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2837 vmcs_writel(GUEST_RFLAGS
, flags
);
2838 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2839 update_exception_bitmap(vcpu
);
2841 if (emulate_invalid_guest_state
)
2842 goto continue_rmode
;
2844 vmx_get_segment(vcpu
, &var
, VCPU_SREG_SS
);
2845 vmx_set_segment(vcpu
, &var
, VCPU_SREG_SS
);
2847 vmx_get_segment(vcpu
, &var
, VCPU_SREG_CS
);
2848 vmx_set_segment(vcpu
, &var
, VCPU_SREG_CS
);
2850 vmx_get_segment(vcpu
, &var
, VCPU_SREG_ES
);
2851 vmx_set_segment(vcpu
, &var
, VCPU_SREG_ES
);
2853 vmx_get_segment(vcpu
, &var
, VCPU_SREG_DS
);
2854 vmx_set_segment(vcpu
, &var
, VCPU_SREG_DS
);
2856 vmx_get_segment(vcpu
, &var
, VCPU_SREG_GS
);
2857 vmx_set_segment(vcpu
, &var
, VCPU_SREG_GS
);
2859 vmx_get_segment(vcpu
, &var
, VCPU_SREG_FS
);
2860 vmx_set_segment(vcpu
, &var
, VCPU_SREG_FS
);
2863 kvm_mmu_reset_context(vcpu
);
2866 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2868 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2869 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2875 * Force kernel_gs_base reloading before EFER changes, as control
2876 * of this msr depends on is_long_mode().
2878 vmx_load_host_state(to_vmx(vcpu
));
2879 vcpu
->arch
.efer
= efer
;
2880 if (efer
& EFER_LMA
) {
2881 vmcs_write32(VM_ENTRY_CONTROLS
,
2882 vmcs_read32(VM_ENTRY_CONTROLS
) |
2883 VM_ENTRY_IA32E_MODE
);
2886 vmcs_write32(VM_ENTRY_CONTROLS
,
2887 vmcs_read32(VM_ENTRY_CONTROLS
) &
2888 ~VM_ENTRY_IA32E_MODE
);
2890 msr
->data
= efer
& ~EFER_LME
;
2895 #ifdef CONFIG_X86_64
2897 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2901 vmx_segment_cache_clear(to_vmx(vcpu
));
2903 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2904 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2905 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2907 vmcs_write32(GUEST_TR_AR_BYTES
,
2908 (guest_tr_ar
& ~AR_TYPE_MASK
)
2909 | AR_TYPE_BUSY_64_TSS
);
2911 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2914 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2916 vmcs_write32(VM_ENTRY_CONTROLS
,
2917 vmcs_read32(VM_ENTRY_CONTROLS
)
2918 & ~VM_ENTRY_IA32E_MODE
);
2919 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2924 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2926 vpid_sync_context(to_vmx(vcpu
));
2928 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2930 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2934 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2936 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2938 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2939 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2942 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2944 if (enable_ept
&& is_paging(vcpu
))
2945 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2946 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2949 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2951 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2953 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2954 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2957 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2959 if (!test_bit(VCPU_EXREG_PDPTR
,
2960 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2963 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2964 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2965 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2966 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2967 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2971 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2973 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2974 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2975 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2976 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2977 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2980 __set_bit(VCPU_EXREG_PDPTR
,
2981 (unsigned long *)&vcpu
->arch
.regs_avail
);
2982 __set_bit(VCPU_EXREG_PDPTR
,
2983 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2986 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2988 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2990 struct kvm_vcpu
*vcpu
)
2992 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2993 vmx_decache_cr3(vcpu
);
2994 if (!(cr0
& X86_CR0_PG
)) {
2995 /* From paging/starting to nonpaging */
2996 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2997 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2998 (CPU_BASED_CR3_LOAD_EXITING
|
2999 CPU_BASED_CR3_STORE_EXITING
));
3000 vcpu
->arch
.cr0
= cr0
;
3001 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3002 } else if (!is_paging(vcpu
)) {
3003 /* From nonpaging to paging */
3004 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3005 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3006 ~(CPU_BASED_CR3_LOAD_EXITING
|
3007 CPU_BASED_CR3_STORE_EXITING
));
3008 vcpu
->arch
.cr0
= cr0
;
3009 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3012 if (!(cr0
& X86_CR0_WP
))
3013 *hw_cr0
&= ~X86_CR0_WP
;
3016 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3018 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3019 unsigned long hw_cr0
;
3021 if (enable_unrestricted_guest
)
3022 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
3023 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3025 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
3027 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3030 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3033 #ifdef CONFIG_X86_64
3034 if (vcpu
->arch
.efer
& EFER_LME
) {
3035 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3037 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3043 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3045 if (!vcpu
->fpu_active
)
3046 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3048 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3049 vmcs_writel(GUEST_CR0
, hw_cr0
);
3050 vcpu
->arch
.cr0
= cr0
;
3051 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3054 static u64
construct_eptp(unsigned long root_hpa
)
3058 /* TODO write the value reading from MSR */
3059 eptp
= VMX_EPT_DEFAULT_MT
|
3060 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3061 if (enable_ept_ad_bits
)
3062 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3063 eptp
|= (root_hpa
& PAGE_MASK
);
3068 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3070 unsigned long guest_cr3
;
3075 eptp
= construct_eptp(cr3
);
3076 vmcs_write64(EPT_POINTER
, eptp
);
3077 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
3078 vcpu
->kvm
->arch
.ept_identity_map_addr
;
3079 ept_load_pdptrs(vcpu
);
3082 vmx_flush_tlb(vcpu
);
3083 vmcs_writel(GUEST_CR3
, guest_cr3
);
3086 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3088 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3089 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3091 if (cr4
& X86_CR4_VMXE
) {
3093 * To use VMXON (and later other VMX instructions), a guest
3094 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3095 * So basically the check on whether to allow nested VMX
3098 if (!nested_vmx_allowed(vcpu
))
3100 } else if (to_vmx(vcpu
)->nested
.vmxon
)
3103 vcpu
->arch
.cr4
= cr4
;
3105 if (!is_paging(vcpu
)) {
3106 hw_cr4
&= ~X86_CR4_PAE
;
3107 hw_cr4
|= X86_CR4_PSE
;
3108 } else if (!(cr4
& X86_CR4_PAE
)) {
3109 hw_cr4
&= ~X86_CR4_PAE
;
3113 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3114 vmcs_writel(GUEST_CR4
, hw_cr4
);
3118 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3119 struct kvm_segment
*var
, int seg
)
3121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3124 if (vmx
->rmode
.vm86_active
3125 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
3126 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
3127 || seg
== VCPU_SREG_GS
)) {
3128 *var
= vmx
->rmode
.segs
[seg
];
3129 if (seg
== VCPU_SREG_TR
3130 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3132 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3133 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3136 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3137 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3138 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3139 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3140 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
3142 var
->type
= ar
& 15;
3143 var
->s
= (ar
>> 4) & 1;
3144 var
->dpl
= (ar
>> 5) & 3;
3145 var
->present
= (ar
>> 7) & 1;
3146 var
->avl
= (ar
>> 12) & 1;
3147 var
->l
= (ar
>> 13) & 1;
3148 var
->db
= (ar
>> 14) & 1;
3149 var
->g
= (ar
>> 15) & 1;
3150 var
->unusable
= (ar
>> 16) & 1;
3153 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3155 struct kvm_segment s
;
3157 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3158 vmx_get_segment(vcpu
, &s
, seg
);
3161 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3164 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3166 if (!is_protmode(vcpu
))
3169 if (!is_long_mode(vcpu
)
3170 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3173 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
3176 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3178 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3181 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3182 * fail; use the cache instead.
3184 if (unlikely(vmx
->emulation_required
&& emulate_invalid_guest_state
)) {
3188 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3189 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3190 vmx
->cpl
= __vmx_get_cpl(vcpu
);
3197 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3201 if (var
->unusable
|| !var
->present
)
3204 ar
= var
->type
& 15;
3205 ar
|= (var
->s
& 1) << 4;
3206 ar
|= (var
->dpl
& 3) << 5;
3207 ar
|= (var
->present
& 1) << 7;
3208 ar
|= (var
->avl
& 1) << 12;
3209 ar
|= (var
->l
& 1) << 13;
3210 ar
|= (var
->db
& 1) << 14;
3211 ar
|= (var
->g
& 1) << 15;
3217 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3218 struct kvm_segment
*var
, int seg
)
3220 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3221 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3224 vmx_segment_cache_clear(vmx
);
3226 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
3227 vmcs_write16(sf
->selector
, var
->selector
);
3228 vmx
->rmode
.segs
[VCPU_SREG_TR
] = *var
;
3231 vmcs_writel(sf
->base
, var
->base
);
3232 vmcs_write32(sf
->limit
, var
->limit
);
3233 vmcs_write16(sf
->selector
, var
->selector
);
3234 if (vmx
->rmode
.vm86_active
&& var
->s
) {
3235 vmx
->rmode
.segs
[seg
] = *var
;
3237 * Hack real-mode segments into vm86 compatibility.
3239 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
3240 vmcs_writel(sf
->base
, 0xf0000);
3243 ar
= vmx_segment_access_rights(var
);
3246 * Fix the "Accessed" bit in AR field of segment registers for older
3248 * IA32 arch specifies that at the time of processor reset the
3249 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3250 * is setting it to 0 in the userland code. This causes invalid guest
3251 * state vmexit when "unrestricted guest" mode is turned on.
3252 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3253 * tree. Newer qemu binaries with that qemu fix would not need this
3256 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3257 ar
|= 0x1; /* Accessed */
3259 vmcs_write32(sf
->ar_bytes
, ar
);
3260 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3263 * Fix segments for real mode guest in hosts that don't have
3264 * "unrestricted_mode" or it was disabled.
3265 * This is done to allow migration of the guests from hosts with
3266 * unrestricted guest like Westmere to older host that don't have
3267 * unrestricted guest like Nehelem.
3269 if (!enable_unrestricted_guest
&& vmx
->rmode
.vm86_active
) {
3272 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
3273 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
3274 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
3275 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
3276 vmcs_write16(GUEST_CS_SELECTOR
,
3277 vmcs_readl(GUEST_CS_BASE
) >> 4);
3283 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3286 vmcs_write16(GUEST_SS_SELECTOR
,
3287 vmcs_readl(GUEST_SS_BASE
) >> 4);
3288 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
3289 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
3295 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3297 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3299 *db
= (ar
>> 14) & 1;
3300 *l
= (ar
>> 13) & 1;
3303 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3305 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3306 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3309 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3311 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3312 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3315 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3317 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3318 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3321 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3323 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3324 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3327 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3329 struct kvm_segment var
;
3332 vmx_get_segment(vcpu
, &var
, seg
);
3333 ar
= vmx_segment_access_rights(&var
);
3335 if (var
.base
!= (var
.selector
<< 4))
3337 if (var
.limit
< 0xffff)
3339 if (((ar
| (3 << AR_DPL_SHIFT
)) & ~(AR_G_MASK
| AR_DB_MASK
)) != 0xf3)
3345 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3347 struct kvm_segment cs
;
3348 unsigned int cs_rpl
;
3350 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3351 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3355 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3359 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3360 if (cs
.dpl
> cs_rpl
)
3363 if (cs
.dpl
!= cs_rpl
)
3369 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3373 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3375 struct kvm_segment ss
;
3376 unsigned int ss_rpl
;
3378 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3379 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3383 if (ss
.type
!= 3 && ss
.type
!= 7)
3387 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3395 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3397 struct kvm_segment var
;
3400 vmx_get_segment(vcpu
, &var
, seg
);
3401 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3409 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3410 if (var
.dpl
< rpl
) /* DPL < RPL */
3414 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3420 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3422 struct kvm_segment tr
;
3424 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3428 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3430 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3438 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3440 struct kvm_segment ldtr
;
3442 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3446 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3456 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3458 struct kvm_segment cs
, ss
;
3460 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3461 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3463 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3464 (ss
.selector
& SELECTOR_RPL_MASK
));
3468 * Check if guest state is valid. Returns true if valid, false if
3470 * We assume that registers are always usable
3472 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3474 /* real mode guest state checks */
3475 if (!is_protmode(vcpu
)) {
3476 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3478 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3480 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3482 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3484 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3486 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3489 /* protected mode guest state checks */
3490 if (!cs_ss_rpl_check(vcpu
))
3492 if (!code_segment_valid(vcpu
))
3494 if (!stack_segment_valid(vcpu
))
3496 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3498 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3500 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3502 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3504 if (!tr_valid(vcpu
))
3506 if (!ldtr_valid(vcpu
))
3510 * - Add checks on RIP
3511 * - Add checks on RFLAGS
3517 static int init_rmode_tss(struct kvm
*kvm
)
3521 int r
, idx
, ret
= 0;
3523 idx
= srcu_read_lock(&kvm
->srcu
);
3524 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3525 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3528 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3529 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3530 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3533 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3536 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3540 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3541 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3548 srcu_read_unlock(&kvm
->srcu
, idx
);
3552 static int init_rmode_identity_map(struct kvm
*kvm
)
3555 pfn_t identity_map_pfn
;
3560 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3561 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3562 "haven't been allocated!\n");
3565 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3568 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3569 idx
= srcu_read_lock(&kvm
->srcu
);
3570 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3573 /* Set up identity-mapping pagetable for EPT in real mode */
3574 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3575 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3576 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3577 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3578 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3582 kvm
->arch
.ept_identity_pagetable_done
= true;
3585 srcu_read_unlock(&kvm
->srcu
, idx
);
3589 static void seg_setup(int seg
)
3591 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3594 vmcs_write16(sf
->selector
, 0);
3595 vmcs_writel(sf
->base
, 0);
3596 vmcs_write32(sf
->limit
, 0xffff);
3597 if (enable_unrestricted_guest
) {
3599 if (seg
== VCPU_SREG_CS
)
3600 ar
|= 0x08; /* code segment */
3604 vmcs_write32(sf
->ar_bytes
, ar
);
3607 static int alloc_apic_access_page(struct kvm
*kvm
)
3610 struct kvm_userspace_memory_region kvm_userspace_mem
;
3613 mutex_lock(&kvm
->slots_lock
);
3614 if (kvm
->arch
.apic_access_page
)
3616 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3617 kvm_userspace_mem
.flags
= 0;
3618 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3619 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3620 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3624 page
= gfn_to_page(kvm
, 0xfee00);
3625 if (is_error_page(page
)) {
3630 kvm
->arch
.apic_access_page
= page
;
3632 mutex_unlock(&kvm
->slots_lock
);
3636 static int alloc_identity_pagetable(struct kvm
*kvm
)
3639 struct kvm_userspace_memory_region kvm_userspace_mem
;
3642 mutex_lock(&kvm
->slots_lock
);
3643 if (kvm
->arch
.ept_identity_pagetable
)
3645 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3646 kvm_userspace_mem
.flags
= 0;
3647 kvm_userspace_mem
.guest_phys_addr
=
3648 kvm
->arch
.ept_identity_map_addr
;
3649 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3650 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3654 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3655 if (is_error_page(page
)) {
3660 kvm
->arch
.ept_identity_pagetable
= page
;
3662 mutex_unlock(&kvm
->slots_lock
);
3666 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3673 spin_lock(&vmx_vpid_lock
);
3674 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3675 if (vpid
< VMX_NR_VPIDS
) {
3677 __set_bit(vpid
, vmx_vpid_bitmap
);
3679 spin_unlock(&vmx_vpid_lock
);
3682 static void free_vpid(struct vcpu_vmx
*vmx
)
3686 spin_lock(&vmx_vpid_lock
);
3688 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3689 spin_unlock(&vmx_vpid_lock
);
3692 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3694 int f
= sizeof(unsigned long);
3696 if (!cpu_has_vmx_msr_bitmap())
3700 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3701 * have the write-low and read-high bitmap offsets the wrong way round.
3702 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3704 if (msr
<= 0x1fff) {
3705 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3706 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3707 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3709 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3710 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3714 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3717 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3718 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3722 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3723 * will not change in the lifetime of the guest.
3724 * Note that host-state that does change is set elsewhere. E.g., host-state
3725 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3727 static void vmx_set_constant_host_state(void)
3733 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
3734 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3735 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3737 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3738 #ifdef CONFIG_X86_64
3740 * Load null selectors, so we can avoid reloading them in
3741 * __vmx_load_host_state(), in case userspace uses the null selectors
3742 * too (the expected case).
3744 vmcs_write16(HOST_DS_SELECTOR
, 0);
3745 vmcs_write16(HOST_ES_SELECTOR
, 0);
3747 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3748 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3750 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3751 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3753 native_store_idt(&dt
);
3754 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3756 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
3758 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3759 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3760 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3761 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3763 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3764 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3765 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3769 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3771 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3773 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3774 if (is_guest_mode(&vmx
->vcpu
))
3775 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3776 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3777 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3780 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3782 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3783 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3784 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3785 #ifdef CONFIG_X86_64
3786 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3787 CPU_BASED_CR8_LOAD_EXITING
;
3791 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3792 CPU_BASED_CR3_LOAD_EXITING
|
3793 CPU_BASED_INVLPG_EXITING
;
3794 return exec_control
;
3797 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3799 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3800 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3801 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3803 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3805 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3806 enable_unrestricted_guest
= 0;
3807 /* Enable INVPCID for non-ept guests may cause performance regression. */
3808 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
3810 if (!enable_unrestricted_guest
)
3811 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3813 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3814 return exec_control
;
3817 static void ept_set_mmio_spte_mask(void)
3820 * EPT Misconfigurations can be generated if the value of bits 2:0
3821 * of an EPT paging-structure entry is 110b (write/execute).
3822 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3825 kvm_mmu_set_mmio_spte_mask(0xffull
<< 49 | 0x6ull
);
3829 * Sets up the vmcs for emulated real mode.
3831 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3833 #ifdef CONFIG_X86_64
3839 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3840 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3842 if (cpu_has_vmx_msr_bitmap())
3843 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3845 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3848 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3849 vmcs_config
.pin_based_exec_ctrl
);
3851 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
3853 if (cpu_has_secondary_exec_ctrls()) {
3854 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
3855 vmx_secondary_exec_control(vmx
));
3859 vmcs_write32(PLE_GAP
, ple_gap
);
3860 vmcs_write32(PLE_WINDOW
, ple_window
);
3863 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
3864 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
3865 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3867 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3868 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3869 vmx_set_constant_host_state();
3870 #ifdef CONFIG_X86_64
3871 rdmsrl(MSR_FS_BASE
, a
);
3872 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3873 rdmsrl(MSR_GS_BASE
, a
);
3874 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3876 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3877 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3880 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3881 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3882 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3883 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3884 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3886 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3887 u32 msr_low
, msr_high
;
3889 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3890 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3891 /* Write the default value follow host pat */
3892 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3893 /* Keep arch.pat sync with GUEST_IA32_PAT */
3894 vmx
->vcpu
.arch
.pat
= host_pat
;
3897 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3898 u32 index
= vmx_msr_index
[i
];
3899 u32 data_low
, data_high
;
3902 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3904 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3906 vmx
->guest_msrs
[j
].index
= i
;
3907 vmx
->guest_msrs
[j
].data
= 0;
3908 vmx
->guest_msrs
[j
].mask
= -1ull;
3912 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3914 /* 22.2.1, 20.8.1 */
3915 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3917 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3918 set_cr4_guest_host_mask(vmx
);
3923 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3925 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3929 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3931 vmx
->rmode
.vm86_active
= 0;
3933 vmx
->soft_vnmi_blocked
= 0;
3935 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3936 kvm_set_cr8(&vmx
->vcpu
, 0);
3937 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3938 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3939 msr
|= MSR_IA32_APICBASE_BSP
;
3940 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3942 ret
= fx_init(&vmx
->vcpu
);
3946 vmx_segment_cache_clear(vmx
);
3948 seg_setup(VCPU_SREG_CS
);
3950 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3951 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3953 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3954 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3955 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3957 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3958 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3961 seg_setup(VCPU_SREG_DS
);
3962 seg_setup(VCPU_SREG_ES
);
3963 seg_setup(VCPU_SREG_FS
);
3964 seg_setup(VCPU_SREG_GS
);
3965 seg_setup(VCPU_SREG_SS
);
3967 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3968 vmcs_writel(GUEST_TR_BASE
, 0);
3969 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3970 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3972 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3973 vmcs_writel(GUEST_LDTR_BASE
, 0);
3974 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3975 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3977 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3978 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3979 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3981 vmcs_writel(GUEST_RFLAGS
, 0x02);
3982 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3983 kvm_rip_write(vcpu
, 0xfff0);
3985 kvm_rip_write(vcpu
, 0);
3986 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3988 vmcs_writel(GUEST_GDTR_BASE
, 0);
3989 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3991 vmcs_writel(GUEST_IDTR_BASE
, 0);
3992 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3994 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3995 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3996 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3998 /* Special registers */
3999 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4003 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4005 if (cpu_has_vmx_tpr_shadow()) {
4006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4007 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4008 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4009 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4010 vmcs_write32(TPR_THRESHOLD
, 0);
4013 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4014 vmcs_write64(APIC_ACCESS_ADDR
,
4015 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4018 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4020 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4021 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
4022 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4023 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
4024 vmx_set_cr4(&vmx
->vcpu
, 0);
4025 vmx_set_efer(&vmx
->vcpu
, 0);
4026 vmx_fpu_activate(&vmx
->vcpu
);
4027 update_exception_bitmap(&vmx
->vcpu
);
4029 vpid_sync_context(vmx
);
4033 /* HACK: Don't enable emulation on guest boot/reset */
4034 vmx
->emulation_required
= 0;
4041 * In nested virtualization, check if L1 asked to exit on external interrupts.
4042 * For most existing hypervisors, this will always return true.
4044 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4046 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4047 PIN_BASED_EXT_INTR_MASK
;
4050 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4052 u32 cpu_based_vm_exec_control
;
4053 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4055 * We get here if vmx_interrupt_allowed() said we can't
4056 * inject to L1 now because L2 must run. Ask L2 to exit
4057 * right after entry, so we can inject to L1 more promptly.
4059 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT
, vcpu
);
4063 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4064 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4065 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4068 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4070 u32 cpu_based_vm_exec_control
;
4072 if (!cpu_has_virtual_nmis()) {
4073 enable_irq_window(vcpu
);
4077 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4078 enable_irq_window(vcpu
);
4081 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4082 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4083 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4086 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4090 int irq
= vcpu
->arch
.interrupt
.nr
;
4092 trace_kvm_inj_virq(irq
);
4094 ++vcpu
->stat
.irq_injections
;
4095 if (vmx
->rmode
.vm86_active
) {
4097 if (vcpu
->arch
.interrupt
.soft
)
4098 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4099 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4100 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4103 intr
= irq
| INTR_INFO_VALID_MASK
;
4104 if (vcpu
->arch
.interrupt
.soft
) {
4105 intr
|= INTR_TYPE_SOFT_INTR
;
4106 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4107 vmx
->vcpu
.arch
.event_exit_inst_len
);
4109 intr
|= INTR_TYPE_EXT_INTR
;
4110 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4113 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4115 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4117 if (is_guest_mode(vcpu
))
4120 if (!cpu_has_virtual_nmis()) {
4122 * Tracking the NMI-blocked state in software is built upon
4123 * finding the next open IRQ window. This, in turn, depends on
4124 * well-behaving guests: They have to keep IRQs disabled at
4125 * least as long as the NMI handler runs. Otherwise we may
4126 * cause NMI nesting, maybe breaking the guest. But as this is
4127 * highly unlikely, we can live with the residual risk.
4129 vmx
->soft_vnmi_blocked
= 1;
4130 vmx
->vnmi_blocked_time
= 0;
4133 ++vcpu
->stat
.nmi_injections
;
4134 vmx
->nmi_known_unmasked
= false;
4135 if (vmx
->rmode
.vm86_active
) {
4136 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4137 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4140 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4141 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4144 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4146 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4149 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4150 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4151 | GUEST_INTR_STATE_NMI
));
4154 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4156 if (!cpu_has_virtual_nmis())
4157 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4158 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4160 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4163 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4165 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4167 if (!cpu_has_virtual_nmis()) {
4168 if (vmx
->soft_vnmi_blocked
!= masked
) {
4169 vmx
->soft_vnmi_blocked
= masked
;
4170 vmx
->vnmi_blocked_time
= 0;
4173 vmx
->nmi_known_unmasked
= !masked
;
4175 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4176 GUEST_INTR_STATE_NMI
);
4178 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4179 GUEST_INTR_STATE_NMI
);
4183 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4185 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
4186 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4187 if (to_vmx(vcpu
)->nested
.nested_run_pending
||
4188 (vmcs12
->idt_vectoring_info_field
&
4189 VECTORING_INFO_VALID_MASK
))
4191 nested_vmx_vmexit(vcpu
);
4192 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
4193 vmcs12
->vm_exit_intr_info
= 0;
4194 /* fall through to normal code, but now in L1, not L2 */
4197 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4198 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4199 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4202 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4205 struct kvm_userspace_memory_region tss_mem
= {
4206 .slot
= TSS_PRIVATE_MEMSLOT
,
4207 .guest_phys_addr
= addr
,
4208 .memory_size
= PAGE_SIZE
* 3,
4212 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
4215 kvm
->arch
.tss_addr
= addr
;
4216 if (!init_rmode_tss(kvm
))
4222 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4223 int vec
, u32 err_code
)
4226 * Instruction with address size override prefix opcode 0x67
4227 * Cause the #SS fault with 0 error code in VM86 mode.
4229 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
4230 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
4233 * Forward all other exceptions that are valid in real mode.
4234 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4235 * the required debugging infrastructure rework.
4239 if (vcpu
->guest_debug
&
4240 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4242 kvm_queue_exception(vcpu
, vec
);
4246 * Update instruction length as we may reinject the exception
4247 * from user space while in guest debugging mode.
4249 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4250 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4251 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4262 kvm_queue_exception(vcpu
, vec
);
4269 * Trigger machine check on the host. We assume all the MSRs are already set up
4270 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4271 * We pass a fake environment to the machine check handler because we want
4272 * the guest to be always treated like user space, no matter what context
4273 * it used internally.
4275 static void kvm_machine_check(void)
4277 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4278 struct pt_regs regs
= {
4279 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4280 .flags
= X86_EFLAGS_IF
,
4283 do_machine_check(®s
, 0);
4287 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4289 /* already handled by vcpu_run */
4293 static int handle_exception(struct kvm_vcpu
*vcpu
)
4295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4296 struct kvm_run
*kvm_run
= vcpu
->run
;
4297 u32 intr_info
, ex_no
, error_code
;
4298 unsigned long cr2
, rip
, dr6
;
4300 enum emulation_result er
;
4302 vect_info
= vmx
->idt_vectoring_info
;
4303 intr_info
= vmx
->exit_intr_info
;
4305 if (is_machine_check(intr_info
))
4306 return handle_machine_check(vcpu
);
4308 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4309 return 1; /* already handled by vmx_vcpu_run() */
4311 if (is_no_device(intr_info
)) {
4312 vmx_fpu_activate(vcpu
);
4316 if (is_invalid_opcode(intr_info
)) {
4317 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4318 if (er
!= EMULATE_DONE
)
4319 kvm_queue_exception(vcpu
, UD_VECTOR
);
4324 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4325 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4328 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4329 * MMIO, it is better to report an internal error.
4330 * See the comments in vmx_handle_exit.
4332 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4333 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4334 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4335 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4336 vcpu
->run
->internal
.ndata
= 2;
4337 vcpu
->run
->internal
.data
[0] = vect_info
;
4338 vcpu
->run
->internal
.data
[1] = intr_info
;
4342 if (is_page_fault(intr_info
)) {
4343 /* EPT won't cause page fault directly */
4345 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4346 trace_kvm_page_fault(cr2
, error_code
);
4348 if (kvm_event_needs_reinjection(vcpu
))
4349 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4350 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4353 if (vmx
->rmode
.vm86_active
&&
4354 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
4356 if (vcpu
->arch
.halt_request
) {
4357 vcpu
->arch
.halt_request
= 0;
4358 return kvm_emulate_halt(vcpu
);
4363 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4366 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4367 if (!(vcpu
->guest_debug
&
4368 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4369 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4370 kvm_queue_exception(vcpu
, DB_VECTOR
);
4373 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4374 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4378 * Update instruction length as we may reinject #BP from
4379 * user space while in guest debugging mode. Reading it for
4380 * #DB as well causes no harm, it is not used in that case.
4382 vmx
->vcpu
.arch
.event_exit_inst_len
=
4383 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4384 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4385 rip
= kvm_rip_read(vcpu
);
4386 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4387 kvm_run
->debug
.arch
.exception
= ex_no
;
4390 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4391 kvm_run
->ex
.exception
= ex_no
;
4392 kvm_run
->ex
.error_code
= error_code
;
4398 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4400 ++vcpu
->stat
.irq_exits
;
4404 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4406 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4410 static int handle_io(struct kvm_vcpu
*vcpu
)
4412 unsigned long exit_qualification
;
4413 int size
, in
, string
;
4416 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4417 string
= (exit_qualification
& 16) != 0;
4418 in
= (exit_qualification
& 8) != 0;
4420 ++vcpu
->stat
.io_exits
;
4423 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4425 port
= exit_qualification
>> 16;
4426 size
= (exit_qualification
& 7) + 1;
4427 skip_emulated_instruction(vcpu
);
4429 return kvm_fast_pio_out(vcpu
, size
, port
);
4433 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4436 * Patch in the VMCALL instruction:
4438 hypercall
[0] = 0x0f;
4439 hypercall
[1] = 0x01;
4440 hypercall
[2] = 0xc1;
4443 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4444 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4446 if (to_vmx(vcpu
)->nested
.vmxon
&&
4447 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4450 if (is_guest_mode(vcpu
)) {
4452 * We get here when L2 changed cr0 in a way that did not change
4453 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4454 * but did change L0 shadowed bits. This can currently happen
4455 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4456 * loading) while pretending to allow the guest to change it.
4458 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4459 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4461 vmcs_writel(CR0_READ_SHADOW
, val
);
4464 return kvm_set_cr0(vcpu
, val
);
4467 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4469 if (is_guest_mode(vcpu
)) {
4470 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4471 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4473 vmcs_writel(CR4_READ_SHADOW
, val
);
4476 return kvm_set_cr4(vcpu
, val
);
4479 /* called to set cr0 as approriate for clts instruction exit. */
4480 static void handle_clts(struct kvm_vcpu
*vcpu
)
4482 if (is_guest_mode(vcpu
)) {
4484 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4485 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4486 * just pretend it's off (also in arch.cr0 for fpu_activate).
4488 vmcs_writel(CR0_READ_SHADOW
,
4489 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4490 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4492 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4495 static int handle_cr(struct kvm_vcpu
*vcpu
)
4497 unsigned long exit_qualification
, val
;
4502 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4503 cr
= exit_qualification
& 15;
4504 reg
= (exit_qualification
>> 8) & 15;
4505 switch ((exit_qualification
>> 4) & 3) {
4506 case 0: /* mov to cr */
4507 val
= kvm_register_read(vcpu
, reg
);
4508 trace_kvm_cr_write(cr
, val
);
4511 err
= handle_set_cr0(vcpu
, val
);
4512 kvm_complete_insn_gp(vcpu
, err
);
4515 err
= kvm_set_cr3(vcpu
, val
);
4516 kvm_complete_insn_gp(vcpu
, err
);
4519 err
= handle_set_cr4(vcpu
, val
);
4520 kvm_complete_insn_gp(vcpu
, err
);
4523 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4524 u8 cr8
= kvm_register_read(vcpu
, reg
);
4525 err
= kvm_set_cr8(vcpu
, cr8
);
4526 kvm_complete_insn_gp(vcpu
, err
);
4527 if (irqchip_in_kernel(vcpu
->kvm
))
4529 if (cr8_prev
<= cr8
)
4531 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4538 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4539 skip_emulated_instruction(vcpu
);
4540 vmx_fpu_activate(vcpu
);
4542 case 1: /*mov from cr*/
4545 val
= kvm_read_cr3(vcpu
);
4546 kvm_register_write(vcpu
, reg
, val
);
4547 trace_kvm_cr_read(cr
, val
);
4548 skip_emulated_instruction(vcpu
);
4551 val
= kvm_get_cr8(vcpu
);
4552 kvm_register_write(vcpu
, reg
, val
);
4553 trace_kvm_cr_read(cr
, val
);
4554 skip_emulated_instruction(vcpu
);
4559 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4560 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4561 kvm_lmsw(vcpu
, val
);
4563 skip_emulated_instruction(vcpu
);
4568 vcpu
->run
->exit_reason
= 0;
4569 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4570 (int)(exit_qualification
>> 4) & 3, cr
);
4574 static int handle_dr(struct kvm_vcpu
*vcpu
)
4576 unsigned long exit_qualification
;
4579 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4580 if (!kvm_require_cpl(vcpu
, 0))
4582 dr
= vmcs_readl(GUEST_DR7
);
4585 * As the vm-exit takes precedence over the debug trap, we
4586 * need to emulate the latter, either for the host or the
4587 * guest debugging itself.
4589 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4590 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4591 vcpu
->run
->debug
.arch
.dr7
= dr
;
4592 vcpu
->run
->debug
.arch
.pc
=
4593 vmcs_readl(GUEST_CS_BASE
) +
4594 vmcs_readl(GUEST_RIP
);
4595 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4596 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4599 vcpu
->arch
.dr7
&= ~DR7_GD
;
4600 vcpu
->arch
.dr6
|= DR6_BD
;
4601 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4602 kvm_queue_exception(vcpu
, DB_VECTOR
);
4607 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4608 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4609 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4610 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4612 if (!kvm_get_dr(vcpu
, dr
, &val
))
4613 kvm_register_write(vcpu
, reg
, val
);
4615 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4616 skip_emulated_instruction(vcpu
);
4620 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4622 vmcs_writel(GUEST_DR7
, val
);
4625 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4627 kvm_emulate_cpuid(vcpu
);
4631 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4633 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4636 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4637 trace_kvm_msr_read_ex(ecx
);
4638 kvm_inject_gp(vcpu
, 0);
4642 trace_kvm_msr_read(ecx
, data
);
4644 /* FIXME: handling of bits 32:63 of rax, rdx */
4645 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4646 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4647 skip_emulated_instruction(vcpu
);
4651 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4653 struct msr_data msr
;
4654 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4655 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4656 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4660 msr
.host_initiated
= false;
4661 if (vmx_set_msr(vcpu
, &msr
) != 0) {
4662 trace_kvm_msr_write_ex(ecx
, data
);
4663 kvm_inject_gp(vcpu
, 0);
4667 trace_kvm_msr_write(ecx
, data
);
4668 skip_emulated_instruction(vcpu
);
4672 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4674 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4678 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4680 u32 cpu_based_vm_exec_control
;
4682 /* clear pending irq */
4683 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4684 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4685 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4687 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4689 ++vcpu
->stat
.irq_window_exits
;
4692 * If the user space waits to inject interrupts, exit as soon as
4695 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4696 vcpu
->run
->request_interrupt_window
&&
4697 !kvm_cpu_has_interrupt(vcpu
)) {
4698 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4704 static int handle_halt(struct kvm_vcpu
*vcpu
)
4706 skip_emulated_instruction(vcpu
);
4707 return kvm_emulate_halt(vcpu
);
4710 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4712 skip_emulated_instruction(vcpu
);
4713 kvm_emulate_hypercall(vcpu
);
4717 static int handle_invd(struct kvm_vcpu
*vcpu
)
4719 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4722 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4724 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4726 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4727 skip_emulated_instruction(vcpu
);
4731 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
4735 err
= kvm_rdpmc(vcpu
);
4736 kvm_complete_insn_gp(vcpu
, err
);
4741 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4743 skip_emulated_instruction(vcpu
);
4744 kvm_emulate_wbinvd(vcpu
);
4748 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4750 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4751 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4753 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4754 skip_emulated_instruction(vcpu
);
4758 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4760 if (likely(fasteoi
)) {
4761 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4762 int access_type
, offset
;
4764 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
4765 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
4767 * Sane guest uses MOV to write EOI, with written value
4768 * not cared. So make a short-circuit here by avoiding
4769 * heavy instruction emulation.
4771 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
4772 (offset
== APIC_EOI
)) {
4773 kvm_lapic_set_eoi(vcpu
);
4774 skip_emulated_instruction(vcpu
);
4778 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4781 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4783 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4784 unsigned long exit_qualification
;
4785 bool has_error_code
= false;
4788 int reason
, type
, idt_v
, idt_index
;
4790 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4791 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
4792 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4794 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4796 reason
= (u32
)exit_qualification
>> 30;
4797 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4799 case INTR_TYPE_NMI_INTR
:
4800 vcpu
->arch
.nmi_injected
= false;
4801 vmx_set_nmi_mask(vcpu
, true);
4803 case INTR_TYPE_EXT_INTR
:
4804 case INTR_TYPE_SOFT_INTR
:
4805 kvm_clear_interrupt_queue(vcpu
);
4807 case INTR_TYPE_HARD_EXCEPTION
:
4808 if (vmx
->idt_vectoring_info
&
4809 VECTORING_INFO_DELIVER_CODE_MASK
) {
4810 has_error_code
= true;
4812 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4815 case INTR_TYPE_SOFT_EXCEPTION
:
4816 kvm_clear_exception_queue(vcpu
);
4822 tss_selector
= exit_qualification
;
4824 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4825 type
!= INTR_TYPE_EXT_INTR
&&
4826 type
!= INTR_TYPE_NMI_INTR
))
4827 skip_emulated_instruction(vcpu
);
4829 if (kvm_task_switch(vcpu
, tss_selector
,
4830 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
4831 has_error_code
, error_code
) == EMULATE_FAIL
) {
4832 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4833 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4834 vcpu
->run
->internal
.ndata
= 0;
4838 /* clear all local breakpoint enable flags */
4839 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4842 * TODO: What about debug traps on tss switch?
4843 * Are we supposed to inject them and update dr6?
4849 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4851 unsigned long exit_qualification
;
4856 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4858 if (exit_qualification
& (1 << 6)) {
4859 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4863 gla_validity
= (exit_qualification
>> 7) & 0x3;
4864 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4865 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4866 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4867 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4868 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4869 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4870 (long unsigned int)exit_qualification
);
4871 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4872 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4876 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4877 trace_kvm_page_fault(gpa
, exit_qualification
);
4879 /* It is a write fault? */
4880 error_code
= exit_qualification
& (1U << 1);
4881 /* ept page table is present? */
4882 error_code
|= (exit_qualification
>> 3) & 0x1;
4884 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
4887 static u64
ept_rsvd_mask(u64 spte
, int level
)
4892 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4893 mask
|= (1ULL << i
);
4896 /* bits 7:3 reserved */
4898 else if (level
== 2) {
4899 if (spte
& (1ULL << 7))
4900 /* 2MB ref, bits 20:12 reserved */
4903 /* bits 6:3 reserved */
4910 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4913 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4915 /* 010b (write-only) */
4916 WARN_ON((spte
& 0x7) == 0x2);
4918 /* 110b (write/execute) */
4919 WARN_ON((spte
& 0x7) == 0x6);
4921 /* 100b (execute-only) and value not supported by logical processor */
4922 if (!cpu_has_vmx_ept_execute_only())
4923 WARN_ON((spte
& 0x7) == 0x4);
4927 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4929 if (rsvd_bits
!= 0) {
4930 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4931 __func__
, rsvd_bits
);
4935 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4936 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4938 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4939 ept_mem_type
== 7) {
4940 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4941 __func__
, ept_mem_type
);
4948 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4951 int nr_sptes
, i
, ret
;
4954 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4956 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
4957 if (likely(ret
== 1))
4958 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
4963 /* It is the real ept misconfig */
4964 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4965 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4967 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4969 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4970 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4972 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4973 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4978 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4980 u32 cpu_based_vm_exec_control
;
4982 /* clear pending NMI */
4983 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4984 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4985 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4986 ++vcpu
->stat
.nmi_window_exits
;
4987 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4992 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4994 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4995 enum emulation_result err
= EMULATE_DONE
;
4998 bool intr_window_requested
;
4999 unsigned count
= 130;
5001 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5002 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5004 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5005 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5006 return handle_interrupt_window(&vmx
->vcpu
);
5008 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5011 err
= emulate_instruction(vcpu
, 0);
5013 if (err
== EMULATE_DO_MMIO
) {
5018 if (err
!= EMULATE_DONE
) {
5019 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5020 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5021 vcpu
->run
->internal
.ndata
= 0;
5025 if (signal_pending(current
))
5031 vmx
->emulation_required
= !guest_state_valid(vcpu
);
5037 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5038 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5040 static int handle_pause(struct kvm_vcpu
*vcpu
)
5042 skip_emulated_instruction(vcpu
);
5043 kvm_vcpu_on_spin(vcpu
);
5048 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5050 kvm_queue_exception(vcpu
, UD_VECTOR
);
5055 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5056 * We could reuse a single VMCS for all the L2 guests, but we also want the
5057 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5058 * allows keeping them loaded on the processor, and in the future will allow
5059 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5060 * every entry if they never change.
5061 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5062 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5064 * The following functions allocate and free a vmcs02 in this pool.
5067 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5068 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5070 struct vmcs02_list
*item
;
5071 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5072 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5073 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5074 return &item
->vmcs02
;
5077 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5078 /* Recycle the least recently used VMCS. */
5079 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5080 struct vmcs02_list
, list
);
5081 item
->vmptr
= vmx
->nested
.current_vmptr
;
5082 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5083 return &item
->vmcs02
;
5086 /* Create a new VMCS */
5087 item
= (struct vmcs02_list
*)
5088 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5091 item
->vmcs02
.vmcs
= alloc_vmcs();
5092 if (!item
->vmcs02
.vmcs
) {
5096 loaded_vmcs_init(&item
->vmcs02
);
5097 item
->vmptr
= vmx
->nested
.current_vmptr
;
5098 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5099 vmx
->nested
.vmcs02_num
++;
5100 return &item
->vmcs02
;
5103 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5104 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5106 struct vmcs02_list
*item
;
5107 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5108 if (item
->vmptr
== vmptr
) {
5109 free_loaded_vmcs(&item
->vmcs02
);
5110 list_del(&item
->list
);
5112 vmx
->nested
.vmcs02_num
--;
5118 * Free all VMCSs saved for this vcpu, except the one pointed by
5119 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5120 * currently used, if running L2), and vmcs01 when running L2.
5122 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5124 struct vmcs02_list
*item
, *n
;
5125 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5126 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5127 free_loaded_vmcs(&item
->vmcs02
);
5128 list_del(&item
->list
);
5131 vmx
->nested
.vmcs02_num
= 0;
5133 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5134 free_loaded_vmcs(&vmx
->vmcs01
);
5138 * Emulate the VMXON instruction.
5139 * Currently, we just remember that VMX is active, and do not save or even
5140 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5141 * do not currently need to store anything in that guest-allocated memory
5142 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5143 * argument is different from the VMXON pointer (which the spec says they do).
5145 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5147 struct kvm_segment cs
;
5148 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5150 /* The Intel VMX Instruction Reference lists a bunch of bits that
5151 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5152 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5153 * Otherwise, we should fail with #UD. We test these now:
5155 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5156 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5157 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5158 kvm_queue_exception(vcpu
, UD_VECTOR
);
5162 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5163 if (is_long_mode(vcpu
) && !cs
.l
) {
5164 kvm_queue_exception(vcpu
, UD_VECTOR
);
5168 if (vmx_get_cpl(vcpu
)) {
5169 kvm_inject_gp(vcpu
, 0);
5173 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5174 vmx
->nested
.vmcs02_num
= 0;
5176 vmx
->nested
.vmxon
= true;
5178 skip_emulated_instruction(vcpu
);
5183 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5184 * for running VMX instructions (except VMXON, whose prerequisites are
5185 * slightly different). It also specifies what exception to inject otherwise.
5187 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5189 struct kvm_segment cs
;
5190 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5192 if (!vmx
->nested
.vmxon
) {
5193 kvm_queue_exception(vcpu
, UD_VECTOR
);
5197 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5198 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5199 (is_long_mode(vcpu
) && !cs
.l
)) {
5200 kvm_queue_exception(vcpu
, UD_VECTOR
);
5204 if (vmx_get_cpl(vcpu
)) {
5205 kvm_inject_gp(vcpu
, 0);
5213 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5214 * just stops using VMX.
5216 static void free_nested(struct vcpu_vmx
*vmx
)
5218 if (!vmx
->nested
.vmxon
)
5220 vmx
->nested
.vmxon
= false;
5221 if (vmx
->nested
.current_vmptr
!= -1ull) {
5222 kunmap(vmx
->nested
.current_vmcs12_page
);
5223 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5224 vmx
->nested
.current_vmptr
= -1ull;
5225 vmx
->nested
.current_vmcs12
= NULL
;
5227 /* Unpin physical memory we referred to in current vmcs02 */
5228 if (vmx
->nested
.apic_access_page
) {
5229 nested_release_page(vmx
->nested
.apic_access_page
);
5230 vmx
->nested
.apic_access_page
= 0;
5233 nested_free_all_saved_vmcss(vmx
);
5236 /* Emulate the VMXOFF instruction */
5237 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5239 if (!nested_vmx_check_permission(vcpu
))
5241 free_nested(to_vmx(vcpu
));
5242 skip_emulated_instruction(vcpu
);
5247 * Decode the memory-address operand of a vmx instruction, as recorded on an
5248 * exit caused by such an instruction (run by a guest hypervisor).
5249 * On success, returns 0. When the operand is invalid, returns 1 and throws
5252 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5253 unsigned long exit_qualification
,
5254 u32 vmx_instruction_info
, gva_t
*ret
)
5257 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5258 * Execution", on an exit, vmx_instruction_info holds most of the
5259 * addressing components of the operand. Only the displacement part
5260 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5261 * For how an actual address is calculated from all these components,
5262 * refer to Vol. 1, "Operand Addressing".
5264 int scaling
= vmx_instruction_info
& 3;
5265 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5266 bool is_reg
= vmx_instruction_info
& (1u << 10);
5267 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5268 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5269 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5270 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5271 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5274 kvm_queue_exception(vcpu
, UD_VECTOR
);
5278 /* Addr = segment_base + offset */
5279 /* offset = base + [index * scale] + displacement */
5280 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5282 *ret
+= kvm_register_read(vcpu
, base_reg
);
5284 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5285 *ret
+= exit_qualification
; /* holds the displacement */
5287 if (addr_size
== 1) /* 32 bit */
5291 * TODO: throw #GP (and return 1) in various cases that the VM*
5292 * instructions require it - e.g., offset beyond segment limit,
5293 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5294 * address, and so on. Currently these are not checked.
5300 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5301 * set the success or error code of an emulated VMX instruction, as specified
5302 * by Vol 2B, VMX Instruction Reference, "Conventions".
5304 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5306 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5307 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5308 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5311 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5313 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5314 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5315 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5319 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5320 u32 vm_instruction_error
)
5322 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5324 * failValid writes the error number to the current VMCS, which
5325 * can't be done there isn't a current VMCS.
5327 nested_vmx_failInvalid(vcpu
);
5330 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5331 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5332 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5334 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5337 /* Emulate the VMCLEAR instruction */
5338 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5340 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5343 struct vmcs12
*vmcs12
;
5345 struct x86_exception e
;
5347 if (!nested_vmx_check_permission(vcpu
))
5350 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5351 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5354 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5355 sizeof(vmptr
), &e
)) {
5356 kvm_inject_page_fault(vcpu
, &e
);
5360 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5361 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5362 skip_emulated_instruction(vcpu
);
5366 if (vmptr
== vmx
->nested
.current_vmptr
) {
5367 kunmap(vmx
->nested
.current_vmcs12_page
);
5368 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5369 vmx
->nested
.current_vmptr
= -1ull;
5370 vmx
->nested
.current_vmcs12
= NULL
;
5373 page
= nested_get_page(vcpu
, vmptr
);
5376 * For accurate processor emulation, VMCLEAR beyond available
5377 * physical memory should do nothing at all. However, it is
5378 * possible that a nested vmx bug, not a guest hypervisor bug,
5379 * resulted in this case, so let's shut down before doing any
5382 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5385 vmcs12
= kmap(page
);
5386 vmcs12
->launch_state
= 0;
5388 nested_release_page(page
);
5390 nested_free_vmcs02(vmx
, vmptr
);
5392 skip_emulated_instruction(vcpu
);
5393 nested_vmx_succeed(vcpu
);
5397 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5399 /* Emulate the VMLAUNCH instruction */
5400 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5402 return nested_vmx_run(vcpu
, true);
5405 /* Emulate the VMRESUME instruction */
5406 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5409 return nested_vmx_run(vcpu
, false);
5412 enum vmcs_field_type
{
5413 VMCS_FIELD_TYPE_U16
= 0,
5414 VMCS_FIELD_TYPE_U64
= 1,
5415 VMCS_FIELD_TYPE_U32
= 2,
5416 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5419 static inline int vmcs_field_type(unsigned long field
)
5421 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5422 return VMCS_FIELD_TYPE_U32
;
5423 return (field
>> 13) & 0x3 ;
5426 static inline int vmcs_field_readonly(unsigned long field
)
5428 return (((field
>> 10) & 0x3) == 1);
5432 * Read a vmcs12 field. Since these can have varying lengths and we return
5433 * one type, we chose the biggest type (u64) and zero-extend the return value
5434 * to that size. Note that the caller, handle_vmread, might need to use only
5435 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5436 * 64-bit fields are to be returned).
5438 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5439 unsigned long field
, u64
*ret
)
5441 short offset
= vmcs_field_to_offset(field
);
5447 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5449 switch (vmcs_field_type(field
)) {
5450 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5451 *ret
= *((natural_width
*)p
);
5453 case VMCS_FIELD_TYPE_U16
:
5456 case VMCS_FIELD_TYPE_U32
:
5459 case VMCS_FIELD_TYPE_U64
:
5463 return 0; /* can never happen. */
5468 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5469 * used before) all generate the same failure when it is missing.
5471 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5473 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5474 if (vmx
->nested
.current_vmptr
== -1ull) {
5475 nested_vmx_failInvalid(vcpu
);
5476 skip_emulated_instruction(vcpu
);
5482 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5484 unsigned long field
;
5486 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5487 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5490 if (!nested_vmx_check_permission(vcpu
) ||
5491 !nested_vmx_check_vmcs12(vcpu
))
5494 /* Decode instruction info and find the field to read */
5495 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5496 /* Read the field, zero-extended to a u64 field_value */
5497 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5498 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5499 skip_emulated_instruction(vcpu
);
5503 * Now copy part of this value to register or memory, as requested.
5504 * Note that the number of bits actually copied is 32 or 64 depending
5505 * on the guest's mode (32 or 64 bit), not on the given field's length.
5507 if (vmx_instruction_info
& (1u << 10)) {
5508 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5511 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5512 vmx_instruction_info
, &gva
))
5514 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5515 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5516 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5519 nested_vmx_succeed(vcpu
);
5520 skip_emulated_instruction(vcpu
);
5525 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5527 unsigned long field
;
5529 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5530 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5533 /* The value to write might be 32 or 64 bits, depending on L1's long
5534 * mode, and eventually we need to write that into a field of several
5535 * possible lengths. The code below first zero-extends the value to 64
5536 * bit (field_value), and then copies only the approriate number of
5537 * bits into the vmcs12 field.
5539 u64 field_value
= 0;
5540 struct x86_exception e
;
5542 if (!nested_vmx_check_permission(vcpu
) ||
5543 !nested_vmx_check_vmcs12(vcpu
))
5546 if (vmx_instruction_info
& (1u << 10))
5547 field_value
= kvm_register_read(vcpu
,
5548 (((vmx_instruction_info
) >> 3) & 0xf));
5550 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5551 vmx_instruction_info
, &gva
))
5553 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5554 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5555 kvm_inject_page_fault(vcpu
, &e
);
5561 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5562 if (vmcs_field_readonly(field
)) {
5563 nested_vmx_failValid(vcpu
,
5564 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5565 skip_emulated_instruction(vcpu
);
5569 offset
= vmcs_field_to_offset(field
);
5571 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5572 skip_emulated_instruction(vcpu
);
5575 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5577 switch (vmcs_field_type(field
)) {
5578 case VMCS_FIELD_TYPE_U16
:
5579 *(u16
*)p
= field_value
;
5581 case VMCS_FIELD_TYPE_U32
:
5582 *(u32
*)p
= field_value
;
5584 case VMCS_FIELD_TYPE_U64
:
5585 *(u64
*)p
= field_value
;
5587 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5588 *(natural_width
*)p
= field_value
;
5591 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5592 skip_emulated_instruction(vcpu
);
5596 nested_vmx_succeed(vcpu
);
5597 skip_emulated_instruction(vcpu
);
5601 /* Emulate the VMPTRLD instruction */
5602 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5604 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5607 struct x86_exception e
;
5609 if (!nested_vmx_check_permission(vcpu
))
5612 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5613 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5616 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5617 sizeof(vmptr
), &e
)) {
5618 kvm_inject_page_fault(vcpu
, &e
);
5622 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5623 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5624 skip_emulated_instruction(vcpu
);
5628 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5629 struct vmcs12
*new_vmcs12
;
5631 page
= nested_get_page(vcpu
, vmptr
);
5633 nested_vmx_failInvalid(vcpu
);
5634 skip_emulated_instruction(vcpu
);
5637 new_vmcs12
= kmap(page
);
5638 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5640 nested_release_page_clean(page
);
5641 nested_vmx_failValid(vcpu
,
5642 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5643 skip_emulated_instruction(vcpu
);
5646 if (vmx
->nested
.current_vmptr
!= -1ull) {
5647 kunmap(vmx
->nested
.current_vmcs12_page
);
5648 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5651 vmx
->nested
.current_vmptr
= vmptr
;
5652 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5653 vmx
->nested
.current_vmcs12_page
= page
;
5656 nested_vmx_succeed(vcpu
);
5657 skip_emulated_instruction(vcpu
);
5661 /* Emulate the VMPTRST instruction */
5662 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5664 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5665 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5667 struct x86_exception e
;
5669 if (!nested_vmx_check_permission(vcpu
))
5672 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5673 vmx_instruction_info
, &vmcs_gva
))
5675 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5676 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5677 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5679 kvm_inject_page_fault(vcpu
, &e
);
5682 nested_vmx_succeed(vcpu
);
5683 skip_emulated_instruction(vcpu
);
5688 * The exit handlers return 1 if the exit was handled fully and guest execution
5689 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5690 * to be done to userspace and return 0.
5692 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5693 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5694 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5695 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5696 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5697 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5698 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5699 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5700 [EXIT_REASON_CPUID
] = handle_cpuid
,
5701 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5702 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5703 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5704 [EXIT_REASON_HLT
] = handle_halt
,
5705 [EXIT_REASON_INVD
] = handle_invd
,
5706 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5707 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
5708 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5709 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5710 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5711 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5712 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5713 [EXIT_REASON_VMREAD
] = handle_vmread
,
5714 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5715 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5716 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5717 [EXIT_REASON_VMON
] = handle_vmon
,
5718 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5719 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5720 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5721 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5722 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5723 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5724 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5725 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5726 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5727 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5728 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5731 static const int kvm_vmx_max_exit_handlers
=
5732 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5735 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5736 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5737 * disinterest in the current event (read or write a specific MSR) by using an
5738 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5740 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5741 struct vmcs12
*vmcs12
, u32 exit_reason
)
5743 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5746 if (!nested_cpu_has(get_vmcs12(vcpu
), CPU_BASED_USE_MSR_BITMAPS
))
5750 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5751 * for the four combinations of read/write and low/high MSR numbers.
5752 * First we need to figure out which of the four to use:
5754 bitmap
= vmcs12
->msr_bitmap
;
5755 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5757 if (msr_index
>= 0xc0000000) {
5758 msr_index
-= 0xc0000000;
5762 /* Then read the msr_index'th bit from this bitmap: */
5763 if (msr_index
< 1024*8) {
5765 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5766 return 1 & (b
>> (msr_index
& 7));
5768 return 1; /* let L1 handle the wrong parameter */
5772 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5773 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5774 * intercept (via guest_host_mask etc.) the current event.
5776 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5777 struct vmcs12
*vmcs12
)
5779 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5780 int cr
= exit_qualification
& 15;
5781 int reg
= (exit_qualification
>> 8) & 15;
5782 unsigned long val
= kvm_register_read(vcpu
, reg
);
5784 switch ((exit_qualification
>> 4) & 3) {
5785 case 0: /* mov to cr */
5788 if (vmcs12
->cr0_guest_host_mask
&
5789 (val
^ vmcs12
->cr0_read_shadow
))
5793 if ((vmcs12
->cr3_target_count
>= 1 &&
5794 vmcs12
->cr3_target_value0
== val
) ||
5795 (vmcs12
->cr3_target_count
>= 2 &&
5796 vmcs12
->cr3_target_value1
== val
) ||
5797 (vmcs12
->cr3_target_count
>= 3 &&
5798 vmcs12
->cr3_target_value2
== val
) ||
5799 (vmcs12
->cr3_target_count
>= 4 &&
5800 vmcs12
->cr3_target_value3
== val
))
5802 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5806 if (vmcs12
->cr4_guest_host_mask
&
5807 (vmcs12
->cr4_read_shadow
^ val
))
5811 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5817 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5818 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5821 case 1: /* mov from cr */
5824 if (vmcs12
->cpu_based_vm_exec_control
&
5825 CPU_BASED_CR3_STORE_EXITING
)
5829 if (vmcs12
->cpu_based_vm_exec_control
&
5830 CPU_BASED_CR8_STORE_EXITING
)
5837 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5838 * cr0. Other attempted changes are ignored, with no exit.
5840 if (vmcs12
->cr0_guest_host_mask
& 0xe &
5841 (val
^ vmcs12
->cr0_read_shadow
))
5843 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
5844 !(vmcs12
->cr0_read_shadow
& 0x1) &&
5853 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5854 * should handle it ourselves in L0 (and then continue L2). Only call this
5855 * when in is_guest_mode (L2).
5857 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
5859 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5860 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5861 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5862 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5864 if (vmx
->nested
.nested_run_pending
)
5867 if (unlikely(vmx
->fail
)) {
5868 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
5869 vmcs_read32(VM_INSTRUCTION_ERROR
));
5873 switch (exit_reason
) {
5874 case EXIT_REASON_EXCEPTION_NMI
:
5875 if (!is_exception(intr_info
))
5877 else if (is_page_fault(intr_info
))
5879 return vmcs12
->exception_bitmap
&
5880 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
5881 case EXIT_REASON_EXTERNAL_INTERRUPT
:
5883 case EXIT_REASON_TRIPLE_FAULT
:
5885 case EXIT_REASON_PENDING_INTERRUPT
:
5886 case EXIT_REASON_NMI_WINDOW
:
5888 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5889 * (aka Interrupt Window Exiting) only when L1 turned it on,
5890 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5891 * Same for NMI Window Exiting.
5894 case EXIT_REASON_TASK_SWITCH
:
5896 case EXIT_REASON_CPUID
:
5898 case EXIT_REASON_HLT
:
5899 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
5900 case EXIT_REASON_INVD
:
5902 case EXIT_REASON_INVLPG
:
5903 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
5904 case EXIT_REASON_RDPMC
:
5905 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
5906 case EXIT_REASON_RDTSC
:
5907 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
5908 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
5909 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
5910 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
5911 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
5912 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
5914 * VMX instructions trap unconditionally. This allows L1 to
5915 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5918 case EXIT_REASON_CR_ACCESS
:
5919 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
5920 case EXIT_REASON_DR_ACCESS
:
5921 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
5922 case EXIT_REASON_IO_INSTRUCTION
:
5923 /* TODO: support IO bitmaps */
5925 case EXIT_REASON_MSR_READ
:
5926 case EXIT_REASON_MSR_WRITE
:
5927 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
5928 case EXIT_REASON_INVALID_STATE
:
5930 case EXIT_REASON_MWAIT_INSTRUCTION
:
5931 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
5932 case EXIT_REASON_MONITOR_INSTRUCTION
:
5933 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
5934 case EXIT_REASON_PAUSE_INSTRUCTION
:
5935 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
5936 nested_cpu_has2(vmcs12
,
5937 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
5938 case EXIT_REASON_MCE_DURING_VMENTRY
:
5940 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
5942 case EXIT_REASON_APIC_ACCESS
:
5943 return nested_cpu_has2(vmcs12
,
5944 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
5945 case EXIT_REASON_EPT_VIOLATION
:
5946 case EXIT_REASON_EPT_MISCONFIG
:
5948 case EXIT_REASON_WBINVD
:
5949 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
5950 case EXIT_REASON_XSETBV
:
5957 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
5959 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
5960 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
5964 * The guest has exited. See if we can fix it or if we need userspace
5967 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
5969 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5970 u32 exit_reason
= vmx
->exit_reason
;
5971 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5973 /* If guest state is invalid, start emulating */
5974 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5975 return handle_invalid_guest_state(vcpu
);
5978 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5979 * we did not inject a still-pending event to L1 now because of
5980 * nested_run_pending, we need to re-enable this bit.
5982 if (vmx
->nested
.nested_run_pending
)
5983 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5985 if (!is_guest_mode(vcpu
) && (exit_reason
== EXIT_REASON_VMLAUNCH
||
5986 exit_reason
== EXIT_REASON_VMRESUME
))
5987 vmx
->nested
.nested_run_pending
= 1;
5989 vmx
->nested
.nested_run_pending
= 0;
5991 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
5992 nested_vmx_vmexit(vcpu
);
5996 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
5997 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5998 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6003 if (unlikely(vmx
->fail
)) {
6004 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6005 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6006 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6012 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6013 * delivery event since it indicates guest is accessing MMIO.
6014 * The vm-exit can be triggered again after return to guest that
6015 * will cause infinite loop.
6017 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6018 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6019 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6020 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6021 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6022 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6023 vcpu
->run
->internal
.ndata
= 2;
6024 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6025 vcpu
->run
->internal
.data
[1] = exit_reason
;
6029 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6030 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6031 get_vmcs12(vcpu
), vcpu
)))) {
6032 if (vmx_interrupt_allowed(vcpu
)) {
6033 vmx
->soft_vnmi_blocked
= 0;
6034 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6035 vcpu
->arch
.nmi_pending
) {
6037 * This CPU don't support us in finding the end of an
6038 * NMI-blocked window if the guest runs with IRQs
6039 * disabled. So we pull the trigger after 1 s of
6040 * futile waiting, but inform the user about this.
6042 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6043 "state on VCPU %d after 1 s timeout\n",
6044 __func__
, vcpu
->vcpu_id
);
6045 vmx
->soft_vnmi_blocked
= 0;
6049 if (exit_reason
< kvm_vmx_max_exit_handlers
6050 && kvm_vmx_exit_handlers
[exit_reason
])
6051 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6053 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6054 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6059 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6061 if (irr
== -1 || tpr
< irr
) {
6062 vmcs_write32(TPR_THRESHOLD
, 0);
6066 vmcs_write32(TPR_THRESHOLD
, irr
);
6069 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
6073 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
6074 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
6077 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6078 exit_intr_info
= vmx
->exit_intr_info
;
6080 /* Handle machine checks before interrupts are enabled */
6081 if (is_machine_check(exit_intr_info
))
6082 kvm_machine_check();
6084 /* We need to handle NMIs before interrupts are enabled */
6085 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
6086 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
6087 kvm_before_handle_nmi(&vmx
->vcpu
);
6089 kvm_after_handle_nmi(&vmx
->vcpu
);
6093 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
6098 bool idtv_info_valid
;
6100 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6102 if (cpu_has_virtual_nmis()) {
6103 if (vmx
->nmi_known_unmasked
)
6106 * Can't use vmx->exit_intr_info since we're not sure what
6107 * the exit reason is.
6109 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6110 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
6111 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
6113 * SDM 3: 27.7.1.2 (September 2008)
6114 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6115 * a guest IRET fault.
6116 * SDM 3: 23.2.2 (September 2008)
6117 * Bit 12 is undefined in any of the following cases:
6118 * If the VM exit sets the valid bit in the IDT-vectoring
6119 * information field.
6120 * If the VM exit is due to a double fault.
6122 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
6123 vector
!= DF_VECTOR
&& !idtv_info_valid
)
6124 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
6125 GUEST_INTR_STATE_NMI
);
6127 vmx
->nmi_known_unmasked
=
6128 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
6129 & GUEST_INTR_STATE_NMI
);
6130 } else if (unlikely(vmx
->soft_vnmi_blocked
))
6131 vmx
->vnmi_blocked_time
+=
6132 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
6135 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
6136 u32 idt_vectoring_info
,
6137 int instr_len_field
,
6138 int error_code_field
)
6142 bool idtv_info_valid
;
6144 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
6146 vmx
->vcpu
.arch
.nmi_injected
= false;
6147 kvm_clear_exception_queue(&vmx
->vcpu
);
6148 kvm_clear_interrupt_queue(&vmx
->vcpu
);
6150 if (!idtv_info_valid
)
6153 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6155 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
6156 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
6159 case INTR_TYPE_NMI_INTR
:
6160 vmx
->vcpu
.arch
.nmi_injected
= true;
6162 * SDM 3: 27.7.1.2 (September 2008)
6163 * Clear bit "block by NMI" before VM entry if a NMI
6166 vmx_set_nmi_mask(&vmx
->vcpu
, false);
6168 case INTR_TYPE_SOFT_EXCEPTION
:
6169 vmx
->vcpu
.arch
.event_exit_inst_len
=
6170 vmcs_read32(instr_len_field
);
6172 case INTR_TYPE_HARD_EXCEPTION
:
6173 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
6174 u32 err
= vmcs_read32(error_code_field
);
6175 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
6177 kvm_queue_exception(&vmx
->vcpu
, vector
);
6179 case INTR_TYPE_SOFT_INTR
:
6180 vmx
->vcpu
.arch
.event_exit_inst_len
=
6181 vmcs_read32(instr_len_field
);
6183 case INTR_TYPE_EXT_INTR
:
6184 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
6185 type
== INTR_TYPE_SOFT_INTR
);
6192 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
6194 if (is_guest_mode(&vmx
->vcpu
))
6196 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
6197 VM_EXIT_INSTRUCTION_LEN
,
6198 IDT_VECTORING_ERROR_CODE
);
6201 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
6203 if (is_guest_mode(vcpu
))
6205 __vmx_complete_interrupts(to_vmx(vcpu
),
6206 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
6207 VM_ENTRY_INSTRUCTION_LEN
,
6208 VM_ENTRY_EXCEPTION_ERROR_CODE
);
6210 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
6213 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
6216 struct perf_guest_switch_msr
*msrs
;
6218 msrs
= perf_guest_get_msrs(&nr_msrs
);
6223 for (i
= 0; i
< nr_msrs
; i
++)
6224 if (msrs
[i
].host
== msrs
[i
].guest
)
6225 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
6227 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
6231 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
6233 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6234 unsigned long debugctlmsr
;
6236 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
6237 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6238 if (vmcs12
->idt_vectoring_info_field
&
6239 VECTORING_INFO_VALID_MASK
) {
6240 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6241 vmcs12
->idt_vectoring_info_field
);
6242 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6243 vmcs12
->vm_exit_instruction_len
);
6244 if (vmcs12
->idt_vectoring_info_field
&
6245 VECTORING_INFO_DELIVER_CODE_MASK
)
6246 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6247 vmcs12
->idt_vectoring_error_code
);
6251 /* Record the guest's net vcpu time for enforced NMI injections. */
6252 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
6253 vmx
->entry_time
= ktime_get();
6255 /* Don't enter VMX if guest state is invalid, let the exit handler
6256 start emulation until we arrive back to a valid state */
6257 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
6260 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6261 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
6262 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
6263 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
6265 /* When single-stepping over STI and MOV SS, we must clear the
6266 * corresponding interruptibility bits in the guest state. Otherwise
6267 * vmentry fails as it then expects bit 14 (BS) in pending debug
6268 * exceptions being set, but that's not correct for the guest debugging
6270 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
6271 vmx_set_interrupt_shadow(vcpu
, 0);
6273 atomic_switch_perf_msrs(vmx
);
6274 debugctlmsr
= get_debugctlmsr();
6276 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
6278 /* Store host registers */
6279 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
6280 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
6281 "push %%" _ASM_CX
" \n\t"
6282 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6284 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
6285 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
6287 /* Reload cr2 if changed */
6288 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
6289 "mov %%cr2, %%" _ASM_DX
" \n\t"
6290 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
6292 "mov %%" _ASM_AX
", %%cr2 \n\t"
6294 /* Check if vmlaunch of vmresume is needed */
6295 "cmpl $0, %c[launched](%0) \n\t"
6296 /* Load guest registers. Don't clobber flags. */
6297 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
6298 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
6299 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
6300 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
6301 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
6302 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
6303 #ifdef CONFIG_X86_64
6304 "mov %c[r8](%0), %%r8 \n\t"
6305 "mov %c[r9](%0), %%r9 \n\t"
6306 "mov %c[r10](%0), %%r10 \n\t"
6307 "mov %c[r11](%0), %%r11 \n\t"
6308 "mov %c[r12](%0), %%r12 \n\t"
6309 "mov %c[r13](%0), %%r13 \n\t"
6310 "mov %c[r14](%0), %%r14 \n\t"
6311 "mov %c[r15](%0), %%r15 \n\t"
6313 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
6315 /* Enter guest mode */
6317 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6319 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6321 /* Save guest registers, load host registers, keep flags */
6322 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
6324 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
6325 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
6326 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
6327 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
6328 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
6329 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
6330 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
6331 #ifdef CONFIG_X86_64
6332 "mov %%r8, %c[r8](%0) \n\t"
6333 "mov %%r9, %c[r9](%0) \n\t"
6334 "mov %%r10, %c[r10](%0) \n\t"
6335 "mov %%r11, %c[r11](%0) \n\t"
6336 "mov %%r12, %c[r12](%0) \n\t"
6337 "mov %%r13, %c[r13](%0) \n\t"
6338 "mov %%r14, %c[r14](%0) \n\t"
6339 "mov %%r15, %c[r15](%0) \n\t"
6341 "mov %%cr2, %%" _ASM_AX
" \n\t"
6342 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
6344 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
6345 "setbe %c[fail](%0) \n\t"
6346 ".pushsection .rodata \n\t"
6347 ".global vmx_return \n\t"
6348 "vmx_return: " _ASM_PTR
" 2b \n\t"
6350 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6351 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6352 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6353 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6354 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6355 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6356 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6357 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6358 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6359 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6360 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6361 #ifdef CONFIG_X86_64
6362 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6363 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6364 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6365 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6366 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6367 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6368 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6369 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6371 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6372 [wordsize
]"i"(sizeof(ulong
))
6374 #ifdef CONFIG_X86_64
6375 , "rax", "rbx", "rdi", "rsi"
6376 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6378 , "eax", "ebx", "edi", "esi"
6382 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6384 update_debugctlmsr(debugctlmsr
);
6386 #ifndef CONFIG_X86_64
6388 * The sysexit path does not restore ds/es, so we must set them to
6389 * a reasonable value ourselves.
6391 * We can't defer this to vmx_load_host_state() since that function
6392 * may be executed in interrupt context, which saves and restore segments
6393 * around it, nullifying its effect.
6395 loadsegment(ds
, __USER_DS
);
6396 loadsegment(es
, __USER_DS
);
6399 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6400 | (1 << VCPU_EXREG_RFLAGS
)
6401 | (1 << VCPU_EXREG_CPL
)
6402 | (1 << VCPU_EXREG_PDPTR
)
6403 | (1 << VCPU_EXREG_SEGMENTS
)
6404 | (1 << VCPU_EXREG_CR3
));
6405 vcpu
->arch
.regs_dirty
= 0;
6407 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6409 if (is_guest_mode(vcpu
)) {
6410 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6411 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6412 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6413 vmcs12
->idt_vectoring_error_code
=
6414 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6415 vmcs12
->vm_exit_instruction_len
=
6416 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6420 vmx
->loaded_vmcs
->launched
= 1;
6422 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6423 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
6425 vmx_complete_atomic_exit(vmx
);
6426 vmx_recover_nmi_blocking(vmx
);
6427 vmx_complete_interrupts(vmx
);
6430 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6432 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6436 free_loaded_vmcs(vmx
->loaded_vmcs
);
6437 kfree(vmx
->guest_msrs
);
6438 kvm_vcpu_uninit(vcpu
);
6439 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6442 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6445 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6449 return ERR_PTR(-ENOMEM
);
6453 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6457 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6459 if (!vmx
->guest_msrs
) {
6463 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6464 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6465 if (!vmx
->loaded_vmcs
->vmcs
)
6468 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6469 loaded_vmcs_init(vmx
->loaded_vmcs
);
6474 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6475 vmx
->vcpu
.cpu
= cpu
;
6476 err
= vmx_vcpu_setup(vmx
);
6477 vmx_vcpu_put(&vmx
->vcpu
);
6481 if (vm_need_virtualize_apic_accesses(kvm
))
6482 err
= alloc_apic_access_page(kvm
);
6487 if (!kvm
->arch
.ept_identity_map_addr
)
6488 kvm
->arch
.ept_identity_map_addr
=
6489 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6491 if (alloc_identity_pagetable(kvm
) != 0)
6493 if (!init_rmode_identity_map(kvm
))
6497 vmx
->nested
.current_vmptr
= -1ull;
6498 vmx
->nested
.current_vmcs12
= NULL
;
6503 free_loaded_vmcs(vmx
->loaded_vmcs
);
6505 kfree(vmx
->guest_msrs
);
6507 kvm_vcpu_uninit(&vmx
->vcpu
);
6510 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6511 return ERR_PTR(err
);
6514 static void __init
vmx_check_processor_compat(void *rtn
)
6516 struct vmcs_config vmcs_conf
;
6519 if (setup_vmcs_config(&vmcs_conf
) < 0)
6521 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6522 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6523 smp_processor_id());
6528 static int get_ept_level(void)
6530 return VMX_EPT_DEFAULT_GAW
+ 1;
6533 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6537 /* For VT-d and EPT combination
6538 * 1. MMIO: always map as UC
6540 * a. VT-d without snooping control feature: can't guarantee the
6541 * result, try to trust guest.
6542 * b. VT-d with snooping control feature: snooping control feature of
6543 * VT-d engine can guarantee the cache correctness. Just set it
6544 * to WB to keep consistent with host. So the same as item 3.
6545 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6546 * consistent with host MTRR
6549 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6550 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6551 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6552 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6553 VMX_EPT_MT_EPTE_SHIFT
;
6555 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6561 static int vmx_get_lpage_level(void)
6563 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6564 return PT_DIRECTORY_LEVEL
;
6566 /* For shadow and EPT supported 1GB page */
6567 return PT_PDPE_LEVEL
;
6570 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6572 struct kvm_cpuid_entry2
*best
;
6573 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6576 vmx
->rdtscp_enabled
= false;
6577 if (vmx_rdtscp_supported()) {
6578 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6579 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6580 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6581 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6582 vmx
->rdtscp_enabled
= true;
6584 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6585 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6591 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6592 /* Exposing INVPCID only when PCID is exposed */
6593 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
6594 if (vmx_invpcid_supported() &&
6595 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
6596 guest_cpuid_has_pcid(vcpu
)) {
6597 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
6598 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6601 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
6602 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6605 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
6609 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6611 if (func
== 1 && nested
)
6612 entry
->ecx
|= bit(X86_FEATURE_VMX
);
6616 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6617 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6618 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6619 * guest in a way that will both be appropriate to L1's requests, and our
6620 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6621 * function also has additional necessary side-effects, like setting various
6622 * vcpu->arch fields.
6624 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6626 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6629 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6630 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6631 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6632 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6633 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6634 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6635 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6636 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6637 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6638 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6639 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6640 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6641 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6642 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6643 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6644 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6645 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6646 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6647 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6648 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6649 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6650 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6651 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6652 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6653 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6654 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6655 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6656 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6657 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6658 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6659 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6660 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6661 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6662 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6663 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6664 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6666 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6667 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6668 vmcs12
->vm_entry_intr_info_field
);
6669 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6670 vmcs12
->vm_entry_exception_error_code
);
6671 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6672 vmcs12
->vm_entry_instruction_len
);
6673 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6674 vmcs12
->guest_interruptibility_info
);
6675 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6676 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6677 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6678 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6679 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6680 vmcs12
->guest_pending_dbg_exceptions
);
6681 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6682 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6684 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6686 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6687 (vmcs_config
.pin_based_exec_ctrl
|
6688 vmcs12
->pin_based_vm_exec_control
));
6691 * Whether page-faults are trapped is determined by a combination of
6692 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6693 * If enable_ept, L0 doesn't care about page faults and we should
6694 * set all of these to L1's desires. However, if !enable_ept, L0 does
6695 * care about (at least some) page faults, and because it is not easy
6696 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6697 * to exit on each and every L2 page fault. This is done by setting
6698 * MASK=MATCH=0 and (see below) EB.PF=1.
6699 * Note that below we don't need special code to set EB.PF beyond the
6700 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6701 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6702 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6704 * A problem with this approach (when !enable_ept) is that L1 may be
6705 * injected with more page faults than it asked for. This could have
6706 * caused problems, but in practice existing hypervisors don't care.
6707 * To fix this, we will need to emulate the PFEC checking (on the L1
6708 * page tables), using walk_addr(), when injecting PFs to L1.
6710 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6711 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6712 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6713 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6715 if (cpu_has_secondary_exec_ctrls()) {
6716 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6717 if (!vmx
->rdtscp_enabled
)
6718 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6719 /* Take the following fields only from vmcs12 */
6720 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6721 if (nested_cpu_has(vmcs12
,
6722 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6723 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6725 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6727 * Translate L1 physical address to host physical
6728 * address for vmcs02. Keep the page pinned, so this
6729 * physical address remains valid. We keep a reference
6730 * to it so we can release it later.
6732 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6733 nested_release_page(vmx
->nested
.apic_access_page
);
6734 vmx
->nested
.apic_access_page
=
6735 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6737 * If translation failed, no matter: This feature asks
6738 * to exit when accessing the given address, and if it
6739 * can never be accessed, this feature won't do
6742 if (!vmx
->nested
.apic_access_page
)
6744 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6746 vmcs_write64(APIC_ACCESS_ADDR
,
6747 page_to_phys(vmx
->nested
.apic_access_page
));
6750 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6755 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6756 * Some constant fields are set here by vmx_set_constant_host_state().
6757 * Other fields are different per CPU, and will be set later when
6758 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6760 vmx_set_constant_host_state();
6763 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6764 * entry, but only if the current (host) sp changed from the value
6765 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6766 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6767 * here we just force the write to happen on entry.
6771 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
6772 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
6773 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6774 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6775 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
6777 * Merging of IO and MSR bitmaps not currently supported.
6778 * Rather, exit every time.
6780 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
6781 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
6782 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
6784 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
6786 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6787 * bitwise-or of what L1 wants to trap for L2, and what we want to
6788 * trap. Note that CR0.TS also needs updating - we do this later.
6790 update_exception_bitmap(vcpu
);
6791 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
6792 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6794 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6795 vmcs_write32(VM_EXIT_CONTROLS
,
6796 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
6797 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
6798 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
6800 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
6801 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
6802 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6803 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6806 set_cr4_guest_host_mask(vmx
);
6808 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
6809 vmcs_write64(TSC_OFFSET
,
6810 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
6812 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6816 * Trivially support vpid by letting L2s share their parent
6817 * L1's vpid. TODO: move to a more elaborate solution, giving
6818 * each L2 its own vpid and exposing the vpid feature to L1.
6820 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6821 vmx_flush_tlb(vcpu
);
6824 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
6825 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
6826 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
6827 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6829 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6830 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6831 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6834 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6835 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6836 * The CR0_READ_SHADOW is what L2 should have expected to read given
6837 * the specifications by L1; It's not enough to take
6838 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6839 * have more bits than L1 expected.
6841 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
6842 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
6844 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
6845 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
6847 /* shadow page tables on either EPT or shadow page tables */
6848 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
6849 kvm_mmu_reset_context(vcpu
);
6851 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
6852 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
6856 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6857 * for running an L2 nested guest.
6859 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
6861 struct vmcs12
*vmcs12
;
6862 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6864 struct loaded_vmcs
*vmcs02
;
6866 if (!nested_vmx_check_permission(vcpu
) ||
6867 !nested_vmx_check_vmcs12(vcpu
))
6870 skip_emulated_instruction(vcpu
);
6871 vmcs12
= get_vmcs12(vcpu
);
6874 * The nested entry process starts with enforcing various prerequisites
6875 * on vmcs12 as required by the Intel SDM, and act appropriately when
6876 * they fail: As the SDM explains, some conditions should cause the
6877 * instruction to fail, while others will cause the instruction to seem
6878 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6879 * To speed up the normal (success) code path, we should avoid checking
6880 * for misconfigurations which will anyway be caught by the processor
6881 * when using the merged vmcs02.
6883 if (vmcs12
->launch_state
== launch
) {
6884 nested_vmx_failValid(vcpu
,
6885 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6886 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
6890 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
6891 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
6892 /*TODO: Also verify bits beyond physical address width are 0*/
6893 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6897 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
6898 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
6899 /*TODO: Also verify bits beyond physical address width are 0*/
6900 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6904 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
6905 vmcs12
->vm_exit_msr_load_count
> 0 ||
6906 vmcs12
->vm_exit_msr_store_count
> 0) {
6907 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6909 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6913 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
6914 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
6915 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
6916 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
6917 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
6918 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
6919 !vmx_control_verify(vmcs12
->vm_exit_controls
,
6920 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
6921 !vmx_control_verify(vmcs12
->vm_entry_controls
,
6922 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
6924 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6928 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6929 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6930 nested_vmx_failValid(vcpu
,
6931 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
6935 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6936 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6937 nested_vmx_entry_failure(vcpu
, vmcs12
,
6938 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
6941 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
6942 nested_vmx_entry_failure(vcpu
, vmcs12
,
6943 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
6948 * We're finally done with prerequisite checking, and can start with
6952 vmcs02
= nested_get_current_vmcs02(vmx
);
6956 enter_guest_mode(vcpu
);
6958 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
6961 vmx
->loaded_vmcs
= vmcs02
;
6963 vmx_vcpu_load(vcpu
, cpu
);
6967 vmcs12
->launch_state
= 1;
6969 prepare_vmcs02(vcpu
, vmcs12
);
6972 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6973 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6974 * returned as far as L1 is concerned. It will only return (and set
6975 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6981 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6982 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6983 * This function returns the new value we should put in vmcs12.guest_cr0.
6984 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6985 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6986 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6987 * didn't trap the bit, because if L1 did, so would L0).
6988 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6989 * been modified by L2, and L1 knows it. So just leave the old value of
6990 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6991 * isn't relevant, because if L0 traps this bit it can set it to anything.
6992 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6993 * changed these bits, and therefore they need to be updated, but L0
6994 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6995 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6997 static inline unsigned long
6998 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7001 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
7002 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
7003 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
7004 vcpu
->arch
.cr0_guest_owned_bits
));
7007 static inline unsigned long
7008 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7011 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
7012 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
7013 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
7014 vcpu
->arch
.cr4_guest_owned_bits
));
7018 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7019 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7020 * and this function updates it to reflect the changes to the guest state while
7021 * L2 was running (and perhaps made some exits which were handled directly by L0
7022 * without going back to L1), and to reflect the exit reason.
7023 * Note that we do not have to copy here all VMCS fields, just those that
7024 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7025 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7026 * which already writes to vmcs12 directly.
7028 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7030 /* update guest state fields: */
7031 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
7032 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
7034 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
7035 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
7036 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
7037 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
7039 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
7040 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
7041 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
7042 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
7043 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
7044 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
7045 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
7046 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
7047 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
7048 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
7049 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
7050 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
7051 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
7052 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
7053 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
7054 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
7055 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
7056 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
7057 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
7058 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
7059 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
7060 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
7061 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
7062 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
7063 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
7064 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
7065 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
7066 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
7067 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
7068 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
7069 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
7070 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
7071 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
7072 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
7073 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
7074 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
7076 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
7077 vmcs12
->guest_interruptibility_info
=
7078 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
7079 vmcs12
->guest_pending_dbg_exceptions
=
7080 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
7082 /* TODO: These cannot have changed unless we have MSR bitmaps and
7083 * the relevant bit asks not to trap the change */
7084 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
7085 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
7086 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
7087 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
7088 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
7089 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
7091 /* update exit information fields: */
7093 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7094 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7096 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7097 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
7098 vmcs12
->idt_vectoring_info_field
=
7099 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7100 vmcs12
->idt_vectoring_error_code
=
7101 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
7102 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
7103 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7105 /* clear vm-entry fields which are to be cleared on exit */
7106 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
7107 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
7111 * A part of what we need to when the nested L2 guest exits and we want to
7112 * run its L1 parent, is to reset L1's guest state to the host state specified
7114 * This function is to be called not only on normal nested exit, but also on
7115 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7116 * Failures During or After Loading Guest State").
7117 * This function should be called when the active VMCS is L1's (vmcs01).
7119 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7121 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
7122 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
7123 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
7124 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7126 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7127 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7129 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
7130 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
7132 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7133 * actually changed, because it depends on the current state of
7134 * fpu_active (which may have changed).
7135 * Note that vmx_set_cr0 refers to efer set above.
7137 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
7139 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7140 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7141 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7143 update_exception_bitmap(vcpu
);
7144 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
7145 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7148 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7149 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7151 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
7152 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
7154 /* shadow page tables on either EPT or shadow page tables */
7155 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
7156 kvm_mmu_reset_context(vcpu
);
7160 * Trivially support vpid by letting L2s share their parent
7161 * L1's vpid. TODO: move to a more elaborate solution, giving
7162 * each L2 its own vpid and exposing the vpid feature to L1.
7164 vmx_flush_tlb(vcpu
);
7168 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
7169 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
7170 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
7171 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
7172 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
7173 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
7174 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
7175 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
7176 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
7177 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
7178 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
7179 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
7180 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
7181 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
7182 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
7184 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
7185 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
7186 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
7187 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
7188 vmcs12
->host_ia32_perf_global_ctrl
);
7192 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7193 * and modify vmcs12 to make it see what it would expect to see there if
7194 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7196 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
7198 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7200 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7202 leave_guest_mode(vcpu
);
7203 prepare_vmcs12(vcpu
, vmcs12
);
7206 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7208 vmx_vcpu_load(vcpu
, cpu
);
7212 /* if no vmcs02 cache requested, remove the one we used */
7213 if (VMCS02_POOL_SIZE
== 0)
7214 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
7216 load_vmcs12_host_state(vcpu
, vmcs12
);
7218 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7219 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7221 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7224 /* Unpin physical memory we referred to in vmcs02 */
7225 if (vmx
->nested
.apic_access_page
) {
7226 nested_release_page(vmx
->nested
.apic_access_page
);
7227 vmx
->nested
.apic_access_page
= 0;
7231 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7232 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7233 * success or failure flag accordingly.
7235 if (unlikely(vmx
->fail
)) {
7237 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
7239 nested_vmx_succeed(vcpu
);
7243 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7244 * 23.7 "VM-entry failures during or after loading guest state" (this also
7245 * lists the acceptable exit-reason and exit-qualification parameters).
7246 * It should only be called before L2 actually succeeded to run, and when
7247 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7249 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
7250 struct vmcs12
*vmcs12
,
7251 u32 reason
, unsigned long qualification
)
7253 load_vmcs12_host_state(vcpu
, vmcs12
);
7254 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
7255 vmcs12
->exit_qualification
= qualification
;
7256 nested_vmx_succeed(vcpu
);
7259 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
7260 struct x86_instruction_info
*info
,
7261 enum x86_intercept_stage stage
)
7263 return X86EMUL_CONTINUE
;
7266 static struct kvm_x86_ops vmx_x86_ops
= {
7267 .cpu_has_kvm_support
= cpu_has_kvm_support
,
7268 .disabled_by_bios
= vmx_disabled_by_bios
,
7269 .hardware_setup
= hardware_setup
,
7270 .hardware_unsetup
= hardware_unsetup
,
7271 .check_processor_compatibility
= vmx_check_processor_compat
,
7272 .hardware_enable
= hardware_enable
,
7273 .hardware_disable
= hardware_disable
,
7274 .cpu_has_accelerated_tpr
= report_flexpriority
,
7276 .vcpu_create
= vmx_create_vcpu
,
7277 .vcpu_free
= vmx_free_vcpu
,
7278 .vcpu_reset
= vmx_vcpu_reset
,
7280 .prepare_guest_switch
= vmx_save_host_state
,
7281 .vcpu_load
= vmx_vcpu_load
,
7282 .vcpu_put
= vmx_vcpu_put
,
7284 .update_db_bp_intercept
= update_exception_bitmap
,
7285 .get_msr
= vmx_get_msr
,
7286 .set_msr
= vmx_set_msr
,
7287 .get_segment_base
= vmx_get_segment_base
,
7288 .get_segment
= vmx_get_segment
,
7289 .set_segment
= vmx_set_segment
,
7290 .get_cpl
= vmx_get_cpl
,
7291 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
7292 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
7293 .decache_cr3
= vmx_decache_cr3
,
7294 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
7295 .set_cr0
= vmx_set_cr0
,
7296 .set_cr3
= vmx_set_cr3
,
7297 .set_cr4
= vmx_set_cr4
,
7298 .set_efer
= vmx_set_efer
,
7299 .get_idt
= vmx_get_idt
,
7300 .set_idt
= vmx_set_idt
,
7301 .get_gdt
= vmx_get_gdt
,
7302 .set_gdt
= vmx_set_gdt
,
7303 .set_dr7
= vmx_set_dr7
,
7304 .cache_reg
= vmx_cache_reg
,
7305 .get_rflags
= vmx_get_rflags
,
7306 .set_rflags
= vmx_set_rflags
,
7307 .fpu_activate
= vmx_fpu_activate
,
7308 .fpu_deactivate
= vmx_fpu_deactivate
,
7310 .tlb_flush
= vmx_flush_tlb
,
7312 .run
= vmx_vcpu_run
,
7313 .handle_exit
= vmx_handle_exit
,
7314 .skip_emulated_instruction
= skip_emulated_instruction
,
7315 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7316 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7317 .patch_hypercall
= vmx_patch_hypercall
,
7318 .set_irq
= vmx_inject_irq
,
7319 .set_nmi
= vmx_inject_nmi
,
7320 .queue_exception
= vmx_queue_exception
,
7321 .cancel_injection
= vmx_cancel_injection
,
7322 .interrupt_allowed
= vmx_interrupt_allowed
,
7323 .nmi_allowed
= vmx_nmi_allowed
,
7324 .get_nmi_mask
= vmx_get_nmi_mask
,
7325 .set_nmi_mask
= vmx_set_nmi_mask
,
7326 .enable_nmi_window
= enable_nmi_window
,
7327 .enable_irq_window
= enable_irq_window
,
7328 .update_cr8_intercept
= update_cr8_intercept
,
7330 .set_tss_addr
= vmx_set_tss_addr
,
7331 .get_tdp_level
= get_ept_level
,
7332 .get_mt_mask
= vmx_get_mt_mask
,
7334 .get_exit_info
= vmx_get_exit_info
,
7336 .get_lpage_level
= vmx_get_lpage_level
,
7338 .cpuid_update
= vmx_cpuid_update
,
7340 .rdtscp_supported
= vmx_rdtscp_supported
,
7341 .invpcid_supported
= vmx_invpcid_supported
,
7343 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7345 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7347 .set_tsc_khz
= vmx_set_tsc_khz
,
7348 .write_tsc_offset
= vmx_write_tsc_offset
,
7349 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7350 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7351 .read_l1_tsc
= vmx_read_l1_tsc
,
7353 .set_tdp_cr3
= vmx_set_cr3
,
7355 .check_intercept
= vmx_check_intercept
,
7358 static int __init
vmx_init(void)
7362 rdmsrl_safe(MSR_EFER
, &host_efer
);
7364 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7365 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7367 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7368 if (!vmx_io_bitmap_a
)
7373 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7374 if (!vmx_io_bitmap_b
)
7377 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7378 if (!vmx_msr_bitmap_legacy
)
7382 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7383 if (!vmx_msr_bitmap_longmode
)
7388 * Allow direct access to the PC debug port (it is often used for I/O
7389 * delays, but the vmexits simply slow things down).
7391 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7392 clear_bit(0x80, vmx_io_bitmap_a
);
7394 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7396 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7397 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7399 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7401 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7402 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7406 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7407 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7408 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7409 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7410 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7411 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7414 kvm_mmu_set_mask_ptes(0ull,
7415 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
7416 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
7417 0ull, VMX_EPT_EXECUTABLE_MASK
);
7418 ept_set_mmio_spte_mask();
7426 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7428 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7430 free_page((unsigned long)vmx_io_bitmap_b
);
7432 free_page((unsigned long)vmx_io_bitmap_a
);
7436 static void __exit
vmx_exit(void)
7438 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7439 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7440 free_page((unsigned long)vmx_io_bitmap_b
);
7441 free_page((unsigned long)vmx_io_bitmap_a
);
7446 module_init(vmx_init
)
7447 module_exit(vmx_exit
)