2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
115 #define KVM_VM_CR0_ALWAYS_ON \
116 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
117 #define KVM_CR4_GUEST_OWNED_BITS \
118 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
119 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
129 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
130 * ple_gap: upper bound on the amount of time between two successive
131 * executions of PAUSE in a loop. Also indicate if ple enabled.
132 * According to test, this time is usually smaller than 128 cycles.
133 * ple_window: upper bound on the amount of time a guest is allowed to execute
134 * in a PAUSE loop. Tests indicate that most spinlocks are held for
135 * less than 2^12 cycles
136 * Time is measured based on a counter that runs at the same rate as the TSC,
137 * refer SDM volume 3b section 21.6.13 & 22.1.3.
139 #define KVM_VMX_DEFAULT_PLE_GAP 128
140 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
144 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
146 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
147 module_param(ple_gap
, int, S_IRUGO
);
149 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
150 module_param(ple_window
, int, S_IRUGO
);
152 /* Default doubles per-vcpu window every exit. */
153 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
154 module_param(ple_window_grow
, int, S_IRUGO
);
156 /* Default resets per-vcpu window every exit to ple_window. */
157 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
158 module_param(ple_window_shrink
, int, S_IRUGO
);
160 /* Default is to compute the maximum so we can never overflow. */
161 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
162 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
163 module_param(ple_window_max
, int, S_IRUGO
);
165 extern const ulong vmx_return
;
167 #define NR_AUTOLOAD_MSRS 8
168 #define VMCS02_POOL_SIZE 1
177 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
178 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
179 * loaded on this CPU (so we can clear them if the CPU goes down).
185 struct list_head loaded_vmcss_on_cpu_link
;
188 struct shared_msr_entry
{
195 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
196 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
197 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
198 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
199 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
200 * More than one of these structures may exist, if L1 runs multiple L2 guests.
201 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
202 * underlying hardware which will be used to run L2.
203 * This structure is packed to ensure that its layout is identical across
204 * machines (necessary for live migration).
205 * If there are changes in this struct, VMCS12_REVISION must be changed.
207 typedef u64 natural_width
;
208 struct __packed vmcs12
{
209 /* According to the Intel spec, a VMCS region must start with the
210 * following two fields. Then follow implementation-specific data.
215 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
216 u32 padding
[7]; /* room for future expansion */
221 u64 vm_exit_msr_store_addr
;
222 u64 vm_exit_msr_load_addr
;
223 u64 vm_entry_msr_load_addr
;
225 u64 virtual_apic_page_addr
;
226 u64 apic_access_addr
;
227 u64 posted_intr_desc_addr
;
229 u64 eoi_exit_bitmap0
;
230 u64 eoi_exit_bitmap1
;
231 u64 eoi_exit_bitmap2
;
232 u64 eoi_exit_bitmap3
;
234 u64 guest_physical_address
;
235 u64 vmcs_link_pointer
;
236 u64 guest_ia32_debugctl
;
239 u64 guest_ia32_perf_global_ctrl
;
247 u64 host_ia32_perf_global_ctrl
;
248 u64 padding64
[8]; /* room for future expansion */
250 * To allow migration of L1 (complete with its L2 guests) between
251 * machines of different natural widths (32 or 64 bit), we cannot have
252 * unsigned long fields with no explict size. We use u64 (aliased
253 * natural_width) instead. Luckily, x86 is little-endian.
255 natural_width cr0_guest_host_mask
;
256 natural_width cr4_guest_host_mask
;
257 natural_width cr0_read_shadow
;
258 natural_width cr4_read_shadow
;
259 natural_width cr3_target_value0
;
260 natural_width cr3_target_value1
;
261 natural_width cr3_target_value2
;
262 natural_width cr3_target_value3
;
263 natural_width exit_qualification
;
264 natural_width guest_linear_address
;
265 natural_width guest_cr0
;
266 natural_width guest_cr3
;
267 natural_width guest_cr4
;
268 natural_width guest_es_base
;
269 natural_width guest_cs_base
;
270 natural_width guest_ss_base
;
271 natural_width guest_ds_base
;
272 natural_width guest_fs_base
;
273 natural_width guest_gs_base
;
274 natural_width guest_ldtr_base
;
275 natural_width guest_tr_base
;
276 natural_width guest_gdtr_base
;
277 natural_width guest_idtr_base
;
278 natural_width guest_dr7
;
279 natural_width guest_rsp
;
280 natural_width guest_rip
;
281 natural_width guest_rflags
;
282 natural_width guest_pending_dbg_exceptions
;
283 natural_width guest_sysenter_esp
;
284 natural_width guest_sysenter_eip
;
285 natural_width host_cr0
;
286 natural_width host_cr3
;
287 natural_width host_cr4
;
288 natural_width host_fs_base
;
289 natural_width host_gs_base
;
290 natural_width host_tr_base
;
291 natural_width host_gdtr_base
;
292 natural_width host_idtr_base
;
293 natural_width host_ia32_sysenter_esp
;
294 natural_width host_ia32_sysenter_eip
;
295 natural_width host_rsp
;
296 natural_width host_rip
;
297 natural_width paddingl
[8]; /* room for future expansion */
298 u32 pin_based_vm_exec_control
;
299 u32 cpu_based_vm_exec_control
;
300 u32 exception_bitmap
;
301 u32 page_fault_error_code_mask
;
302 u32 page_fault_error_code_match
;
303 u32 cr3_target_count
;
304 u32 vm_exit_controls
;
305 u32 vm_exit_msr_store_count
;
306 u32 vm_exit_msr_load_count
;
307 u32 vm_entry_controls
;
308 u32 vm_entry_msr_load_count
;
309 u32 vm_entry_intr_info_field
;
310 u32 vm_entry_exception_error_code
;
311 u32 vm_entry_instruction_len
;
313 u32 secondary_vm_exec_control
;
314 u32 vm_instruction_error
;
316 u32 vm_exit_intr_info
;
317 u32 vm_exit_intr_error_code
;
318 u32 idt_vectoring_info_field
;
319 u32 idt_vectoring_error_code
;
320 u32 vm_exit_instruction_len
;
321 u32 vmx_instruction_info
;
328 u32 guest_ldtr_limit
;
330 u32 guest_gdtr_limit
;
331 u32 guest_idtr_limit
;
332 u32 guest_es_ar_bytes
;
333 u32 guest_cs_ar_bytes
;
334 u32 guest_ss_ar_bytes
;
335 u32 guest_ds_ar_bytes
;
336 u32 guest_fs_ar_bytes
;
337 u32 guest_gs_ar_bytes
;
338 u32 guest_ldtr_ar_bytes
;
339 u32 guest_tr_ar_bytes
;
340 u32 guest_interruptibility_info
;
341 u32 guest_activity_state
;
342 u32 guest_sysenter_cs
;
343 u32 host_ia32_sysenter_cs
;
344 u32 vmx_preemption_timer_value
;
345 u32 padding32
[7]; /* room for future expansion */
346 u16 virtual_processor_id
;
348 u16 guest_es_selector
;
349 u16 guest_cs_selector
;
350 u16 guest_ss_selector
;
351 u16 guest_ds_selector
;
352 u16 guest_fs_selector
;
353 u16 guest_gs_selector
;
354 u16 guest_ldtr_selector
;
355 u16 guest_tr_selector
;
356 u16 guest_intr_status
;
357 u16 host_es_selector
;
358 u16 host_cs_selector
;
359 u16 host_ss_selector
;
360 u16 host_ds_selector
;
361 u16 host_fs_selector
;
362 u16 host_gs_selector
;
363 u16 host_tr_selector
;
367 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
368 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
369 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
371 #define VMCS12_REVISION 0x11e57ed0
374 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
375 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
376 * current implementation, 4K are reserved to avoid future complications.
378 #define VMCS12_SIZE 0x1000
380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
382 struct list_head list
;
384 struct loaded_vmcs vmcs02
;
388 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
389 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
392 /* Has the level1 guest done vmxon? */
396 /* The guest-physical address of the current VMCS L1 keeps for L2 */
398 /* The host-usable pointer to the above */
399 struct page
*current_vmcs12_page
;
400 struct vmcs12
*current_vmcs12
;
401 struct vmcs
*current_shadow_vmcs
;
403 * Indicates if the shadow vmcs must be updated with the
404 * data hold by vmcs12
406 bool sync_shadow_vmcs
;
408 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
409 struct list_head vmcs02_pool
;
411 u64 vmcs01_tsc_offset
;
412 /* L2 must run next, and mustn't decide to exit to L1. */
413 bool nested_run_pending
;
415 * Guest pages referred to in vmcs02 with host-physical pointers, so
416 * we must keep them pinned while L2 runs.
418 struct page
*apic_access_page
;
419 struct page
*virtual_apic_page
;
420 struct page
*pi_desc_page
;
421 struct pi_desc
*pi_desc
;
424 u64 msr_ia32_feature_control
;
426 struct hrtimer preemption_timer
;
427 bool preemption_timer_expired
;
429 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
435 u32 nested_vmx_procbased_ctls_low
;
436 u32 nested_vmx_procbased_ctls_high
;
437 u32 nested_vmx_true_procbased_ctls_low
;
438 u32 nested_vmx_secondary_ctls_low
;
439 u32 nested_vmx_secondary_ctls_high
;
440 u32 nested_vmx_pinbased_ctls_low
;
441 u32 nested_vmx_pinbased_ctls_high
;
442 u32 nested_vmx_exit_ctls_low
;
443 u32 nested_vmx_exit_ctls_high
;
444 u32 nested_vmx_true_exit_ctls_low
;
445 u32 nested_vmx_entry_ctls_low
;
446 u32 nested_vmx_entry_ctls_high
;
447 u32 nested_vmx_true_entry_ctls_low
;
448 u32 nested_vmx_misc_low
;
449 u32 nested_vmx_misc_high
;
450 u32 nested_vmx_ept_caps
;
451 u32 nested_vmx_vpid_caps
;
454 #define POSTED_INTR_ON 0
455 #define POSTED_INTR_SN 1
457 /* Posted-Interrupt Descriptor */
459 u32 pir
[8]; /* Posted interrupt requested */
462 /* bit 256 - Outstanding Notification */
464 /* bit 257 - Suppress Notification */
466 /* bit 271:258 - Reserved */
468 /* bit 279:272 - Notification Vector */
470 /* bit 287:280 - Reserved */
472 /* bit 319:288 - Notification Destination */
480 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
482 return test_and_set_bit(POSTED_INTR_ON
,
483 (unsigned long *)&pi_desc
->control
);
486 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
488 return test_and_clear_bit(POSTED_INTR_ON
,
489 (unsigned long *)&pi_desc
->control
);
492 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
494 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
497 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
499 return clear_bit(POSTED_INTR_SN
,
500 (unsigned long *)&pi_desc
->control
);
503 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
505 return set_bit(POSTED_INTR_SN
,
506 (unsigned long *)&pi_desc
->control
);
509 static inline int pi_test_on(struct pi_desc
*pi_desc
)
511 return test_bit(POSTED_INTR_ON
,
512 (unsigned long *)&pi_desc
->control
);
515 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
517 return test_bit(POSTED_INTR_SN
,
518 (unsigned long *)&pi_desc
->control
);
522 struct kvm_vcpu vcpu
;
523 unsigned long host_rsp
;
525 bool nmi_known_unmasked
;
527 u32 idt_vectoring_info
;
529 struct shared_msr_entry
*guest_msrs
;
532 unsigned long host_idt_base
;
534 u64 msr_host_kernel_gs_base
;
535 u64 msr_guest_kernel_gs_base
;
537 u32 vm_entry_controls_shadow
;
538 u32 vm_exit_controls_shadow
;
540 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541 * non-nested (L1) guest, it always points to vmcs01. For a nested
542 * guest (L2), it points to a different VMCS.
544 struct loaded_vmcs vmcs01
;
545 struct loaded_vmcs
*loaded_vmcs
;
546 bool __launched
; /* temporary, used in vmx_vcpu_run */
547 struct msr_autoload
{
549 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
550 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
554 u16 fs_sel
, gs_sel
, ldt_sel
;
558 int gs_ldt_reload_needed
;
559 int fs_reload_needed
;
560 u64 msr_host_bndcfgs
;
561 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
566 struct kvm_segment segs
[8];
569 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
570 struct kvm_save_segment
{
578 bool emulation_required
;
580 /* Support for vnmi-less CPUs */
581 int soft_vnmi_blocked
;
583 s64 vnmi_blocked_time
;
586 /* Posted interrupt descriptor */
587 struct pi_desc pi_desc
;
589 /* Support for a guest hypervisor (nested VMX) */
590 struct nested_vmx nested
;
592 /* Dynamic PLE window. */
594 bool ple_window_dirty
;
596 /* Support for PML */
597 #define PML_ENTITY_NUM 512
600 u64 current_tsc_ratio
;
602 bool guest_pkru_valid
;
607 enum segment_cache_field
{
616 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
618 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
621 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
623 return &(to_vmx(vcpu
)->pi_desc
);
626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
627 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
628 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
629 [number##_HIGH] = VMCS12_OFFSET(name)+4
632 static unsigned long shadow_read_only_fields
[] = {
634 * We do NOT shadow fields that are modified when L0
635 * traps and emulates any vmx instruction (e.g. VMPTRLD,
636 * VMXON...) executed by L1.
637 * For example, VM_INSTRUCTION_ERROR is read
638 * by L1 if a vmx instruction fails (part of the error path).
639 * Note the code assumes this logic. If for some reason
640 * we start shadowing these fields then we need to
641 * force a shadow sync when L0 emulates vmx instructions
642 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
643 * by nested_vmx_failValid)
647 VM_EXIT_INSTRUCTION_LEN
,
648 IDT_VECTORING_INFO_FIELD
,
649 IDT_VECTORING_ERROR_CODE
,
650 VM_EXIT_INTR_ERROR_CODE
,
652 GUEST_LINEAR_ADDRESS
,
653 GUEST_PHYSICAL_ADDRESS
655 static int max_shadow_read_only_fields
=
656 ARRAY_SIZE(shadow_read_only_fields
);
658 static unsigned long shadow_read_write_fields
[] = {
665 GUEST_INTERRUPTIBILITY_INFO
,
678 CPU_BASED_VM_EXEC_CONTROL
,
679 VM_ENTRY_EXCEPTION_ERROR_CODE
,
680 VM_ENTRY_INTR_INFO_FIELD
,
681 VM_ENTRY_INSTRUCTION_LEN
,
682 VM_ENTRY_EXCEPTION_ERROR_CODE
,
688 static int max_shadow_read_write_fields
=
689 ARRAY_SIZE(shadow_read_write_fields
);
691 static const unsigned short vmcs_field_to_offset_table
[] = {
692 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
693 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
694 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
695 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
696 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
697 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
698 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
699 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
700 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
701 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
702 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
703 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
704 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
705 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
706 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
707 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
708 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
709 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
710 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
711 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
712 FIELD64(MSR_BITMAP
, msr_bitmap
),
713 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
714 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
715 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
716 FIELD64(TSC_OFFSET
, tsc_offset
),
717 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
718 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
719 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
720 FIELD64(EPT_POINTER
, ept_pointer
),
721 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
722 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
723 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
724 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
725 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
726 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
727 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
728 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
729 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
730 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
731 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
732 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
733 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
734 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
735 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
736 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
737 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
738 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
739 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
740 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
741 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
742 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
743 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
744 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
745 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
746 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
747 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
748 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
749 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
750 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
751 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
752 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
753 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
754 FIELD(TPR_THRESHOLD
, tpr_threshold
),
755 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
756 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
757 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
758 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
759 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
760 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
761 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
762 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
763 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
764 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
765 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
766 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
767 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
768 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
769 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
770 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
771 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
772 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
773 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
774 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
775 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
776 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
777 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
778 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
779 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
780 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
781 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
782 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
783 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
784 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
785 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
786 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
787 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
788 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
789 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
790 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
791 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
792 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
793 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
794 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
795 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
796 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
797 FIELD(GUEST_CR0
, guest_cr0
),
798 FIELD(GUEST_CR3
, guest_cr3
),
799 FIELD(GUEST_CR4
, guest_cr4
),
800 FIELD(GUEST_ES_BASE
, guest_es_base
),
801 FIELD(GUEST_CS_BASE
, guest_cs_base
),
802 FIELD(GUEST_SS_BASE
, guest_ss_base
),
803 FIELD(GUEST_DS_BASE
, guest_ds_base
),
804 FIELD(GUEST_FS_BASE
, guest_fs_base
),
805 FIELD(GUEST_GS_BASE
, guest_gs_base
),
806 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
807 FIELD(GUEST_TR_BASE
, guest_tr_base
),
808 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
809 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
810 FIELD(GUEST_DR7
, guest_dr7
),
811 FIELD(GUEST_RSP
, guest_rsp
),
812 FIELD(GUEST_RIP
, guest_rip
),
813 FIELD(GUEST_RFLAGS
, guest_rflags
),
814 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
815 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
816 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
817 FIELD(HOST_CR0
, host_cr0
),
818 FIELD(HOST_CR3
, host_cr3
),
819 FIELD(HOST_CR4
, host_cr4
),
820 FIELD(HOST_FS_BASE
, host_fs_base
),
821 FIELD(HOST_GS_BASE
, host_gs_base
),
822 FIELD(HOST_TR_BASE
, host_tr_base
),
823 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
824 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
825 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
826 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
827 FIELD(HOST_RSP
, host_rsp
),
828 FIELD(HOST_RIP
, host_rip
),
831 static inline short vmcs_field_to_offset(unsigned long field
)
833 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
835 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
836 vmcs_field_to_offset_table
[field
] == 0)
839 return vmcs_field_to_offset_table
[field
];
842 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
844 return to_vmx(vcpu
)->nested
.current_vmcs12
;
847 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
849 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
850 if (is_error_page(page
))
856 static void nested_release_page(struct page
*page
)
858 kvm_release_page_dirty(page
);
861 static void nested_release_page_clean(struct page
*page
)
863 kvm_release_page_clean(page
);
866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
867 static u64
construct_eptp(unsigned long root_hpa
);
868 static void kvm_cpu_vmxon(u64 addr
);
869 static void kvm_cpu_vmxoff(void);
870 static bool vmx_xsaves_supported(void);
871 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
872 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
873 struct kvm_segment
*var
, int seg
);
874 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
875 struct kvm_segment
*var
, int seg
);
876 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
877 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
878 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
879 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
880 static int alloc_identity_pagetable(struct kvm
*kvm
);
882 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
883 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
885 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
886 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
888 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
889 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
892 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
893 * can find which vCPU should be waken up.
895 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
896 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
898 static unsigned long *vmx_io_bitmap_a
;
899 static unsigned long *vmx_io_bitmap_b
;
900 static unsigned long *vmx_msr_bitmap_legacy
;
901 static unsigned long *vmx_msr_bitmap_longmode
;
902 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
903 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
904 static unsigned long *vmx_msr_bitmap_nested
;
905 static unsigned long *vmx_vmread_bitmap
;
906 static unsigned long *vmx_vmwrite_bitmap
;
908 static bool cpu_has_load_ia32_efer
;
909 static bool cpu_has_load_perf_global_ctrl
;
911 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
912 static DEFINE_SPINLOCK(vmx_vpid_lock
);
914 static struct vmcs_config
{
918 u32 pin_based_exec_ctrl
;
919 u32 cpu_based_exec_ctrl
;
920 u32 cpu_based_2nd_exec_ctrl
;
925 static struct vmx_capability
{
930 #define VMX_SEGMENT_FIELD(seg) \
931 [VCPU_SREG_##seg] = { \
932 .selector = GUEST_##seg##_SELECTOR, \
933 .base = GUEST_##seg##_BASE, \
934 .limit = GUEST_##seg##_LIMIT, \
935 .ar_bytes = GUEST_##seg##_AR_BYTES, \
938 static const struct kvm_vmx_segment_field
{
943 } kvm_vmx_segment_fields
[] = {
944 VMX_SEGMENT_FIELD(CS
),
945 VMX_SEGMENT_FIELD(DS
),
946 VMX_SEGMENT_FIELD(ES
),
947 VMX_SEGMENT_FIELD(FS
),
948 VMX_SEGMENT_FIELD(GS
),
949 VMX_SEGMENT_FIELD(SS
),
950 VMX_SEGMENT_FIELD(TR
),
951 VMX_SEGMENT_FIELD(LDTR
),
954 static u64 host_efer
;
956 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
959 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
960 * away by decrementing the array size.
962 static const u32 vmx_msr_index
[] = {
964 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
966 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
969 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
971 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
972 INTR_INFO_VALID_MASK
)) ==
973 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
976 static inline bool is_debug(u32 intr_info
)
978 return is_exception_n(intr_info
, DB_VECTOR
);
981 static inline bool is_breakpoint(u32 intr_info
)
983 return is_exception_n(intr_info
, BP_VECTOR
);
986 static inline bool is_page_fault(u32 intr_info
)
988 return is_exception_n(intr_info
, PF_VECTOR
);
991 static inline bool is_no_device(u32 intr_info
)
993 return is_exception_n(intr_info
, NM_VECTOR
);
996 static inline bool is_invalid_opcode(u32 intr_info
)
998 return is_exception_n(intr_info
, UD_VECTOR
);
1001 static inline bool is_external_interrupt(u32 intr_info
)
1003 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1004 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1007 static inline bool is_machine_check(u32 intr_info
)
1009 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1010 INTR_INFO_VALID_MASK
)) ==
1011 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1016 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1021 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1026 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1031 return vmcs_config
.cpu_based_exec_ctrl
&
1032 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1037 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1038 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1043 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1044 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1049 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1050 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1055 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1056 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1059 static inline bool cpu_has_vmx_posted_intr(void)
1061 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1062 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1065 static inline bool cpu_has_vmx_apicv(void)
1067 return cpu_has_vmx_apic_register_virt() &&
1068 cpu_has_vmx_virtual_intr_delivery() &&
1069 cpu_has_vmx_posted_intr();
1072 static inline bool cpu_has_vmx_flexpriority(void)
1074 return cpu_has_vmx_tpr_shadow() &&
1075 cpu_has_vmx_virtualize_apic_accesses();
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1080 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1085 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1090 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1095 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1100 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1103 static inline bool cpu_has_vmx_invept_context(void)
1105 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1108 static inline bool cpu_has_vmx_invept_global(void)
1110 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1115 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1120 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1123 static inline bool cpu_has_vmx_ept(void)
1125 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1126 SECONDARY_EXEC_ENABLE_EPT
;
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1131 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1132 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1135 static inline bool cpu_has_vmx_ple(void)
1137 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1138 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1143 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1146 static inline bool cpu_has_vmx_vpid(void)
1148 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1149 SECONDARY_EXEC_ENABLE_VPID
;
1152 static inline bool cpu_has_vmx_rdtscp(void)
1154 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1155 SECONDARY_EXEC_RDTSCP
;
1158 static inline bool cpu_has_vmx_invpcid(void)
1160 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1161 SECONDARY_EXEC_ENABLE_INVPCID
;
1164 static inline bool cpu_has_virtual_nmis(void)
1166 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1171 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1172 SECONDARY_EXEC_WBINVD_EXITING
;
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1178 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1179 /* check if the cpu supports writing r/o exit information fields */
1180 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1183 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1184 SECONDARY_EXEC_SHADOW_VMCS
;
1187 static inline bool cpu_has_vmx_pml(void)
1189 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1194 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1195 SECONDARY_EXEC_TSC_SCALING
;
1198 static inline bool report_flexpriority(void)
1200 return flexpriority_enabled
;
1203 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1205 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1208 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1210 return (vmcs12
->cpu_based_vm_exec_control
&
1211 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1212 (vmcs12
->secondary_vm_exec_control
& bit
);
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1217 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1222 return vmcs12
->pin_based_vm_exec_control
&
1223 PIN_BASED_VMX_PREEMPTION_TIMER
;
1226 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1228 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1233 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1234 vmx_xsaves_supported();
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1239 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1242 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1244 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1249 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1252 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1254 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1259 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1262 static inline bool is_exception(u32 intr_info
)
1264 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1265 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1268 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1270 unsigned long exit_qualification
);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1272 struct vmcs12
*vmcs12
,
1273 u32 reason
, unsigned long qualification
);
1275 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1279 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1280 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1285 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1291 } operand
= { vpid
, 0, gva
};
1293 asm volatile (__ex(ASM_VMX_INVVPID
)
1294 /* CF==1 or ZF==1 --> rc = -1 */
1295 "; ja 1f ; ud2 ; 1:"
1296 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1299 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1303 } operand
= {eptp
, gpa
};
1305 asm volatile (__ex(ASM_VMX_INVEPT
)
1306 /* CF==1 or ZF==1 --> rc = -1 */
1307 "; ja 1f ; ud2 ; 1:\n"
1308 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1311 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1315 i
= __find_msr_index(vmx
, msr
);
1317 return &vmx
->guest_msrs
[i
];
1321 static void vmcs_clear(struct vmcs
*vmcs
)
1323 u64 phys_addr
= __pa(vmcs
);
1326 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1327 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1330 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1334 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1336 vmcs_clear(loaded_vmcs
->vmcs
);
1337 loaded_vmcs
->cpu
= -1;
1338 loaded_vmcs
->launched
= 0;
1341 static void vmcs_load(struct vmcs
*vmcs
)
1343 u64 phys_addr
= __pa(vmcs
);
1346 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1347 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1350 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1354 #ifdef CONFIG_KEXEC_CORE
1356 * This bitmap is used to indicate whether the vmclear
1357 * operation is enabled on all cpus. All disabled by
1360 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1362 static inline void crash_enable_local_vmclear(int cpu
)
1364 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1367 static inline void crash_disable_local_vmclear(int cpu
)
1369 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1372 static inline int crash_local_vmclear_enabled(int cpu
)
1374 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1377 static void crash_vmclear_local_loaded_vmcss(void)
1379 int cpu
= raw_smp_processor_id();
1380 struct loaded_vmcs
*v
;
1382 if (!crash_local_vmclear_enabled(cpu
))
1385 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1386 loaded_vmcss_on_cpu_link
)
1387 vmcs_clear(v
->vmcs
);
1390 static inline void crash_enable_local_vmclear(int cpu
) { }
1391 static inline void crash_disable_local_vmclear(int cpu
) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1394 static void __loaded_vmcs_clear(void *arg
)
1396 struct loaded_vmcs
*loaded_vmcs
= arg
;
1397 int cpu
= raw_smp_processor_id();
1399 if (loaded_vmcs
->cpu
!= cpu
)
1400 return; /* vcpu migration can race with cpu offline */
1401 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1402 per_cpu(current_vmcs
, cpu
) = NULL
;
1403 crash_disable_local_vmclear(cpu
);
1404 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1407 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408 * is before setting loaded_vmcs->vcpu to -1 which is done in
1409 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410 * then adds the vmcs into percpu list before it is deleted.
1414 loaded_vmcs_init(loaded_vmcs
);
1415 crash_enable_local_vmclear(cpu
);
1418 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1420 int cpu
= loaded_vmcs
->cpu
;
1423 smp_call_function_single(cpu
,
1424 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1427 static inline void vpid_sync_vcpu_single(int vpid
)
1432 if (cpu_has_vmx_invvpid_single())
1433 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1436 static inline void vpid_sync_vcpu_global(void)
1438 if (cpu_has_vmx_invvpid_global())
1439 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1442 static inline void vpid_sync_context(int vpid
)
1444 if (cpu_has_vmx_invvpid_single())
1445 vpid_sync_vcpu_single(vpid
);
1447 vpid_sync_vcpu_global();
1450 static inline void ept_sync_global(void)
1452 if (cpu_has_vmx_invept_global())
1453 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1456 static inline void ept_sync_context(u64 eptp
)
1459 if (cpu_has_vmx_invept_context())
1460 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1466 static __always_inline
void vmcs_check16(unsigned long field
)
1468 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1469 "16-bit accessor invalid for 64-bit field");
1470 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1471 "16-bit accessor invalid for 64-bit high field");
1472 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1473 "16-bit accessor invalid for 32-bit high field");
1474 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1475 "16-bit accessor invalid for natural width field");
1478 static __always_inline
void vmcs_check32(unsigned long field
)
1480 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1481 "32-bit accessor invalid for 16-bit field");
1482 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1483 "32-bit accessor invalid for natural width field");
1486 static __always_inline
void vmcs_check64(unsigned long field
)
1488 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1489 "64-bit accessor invalid for 16-bit field");
1490 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1491 "64-bit accessor invalid for 64-bit high field");
1492 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1493 "64-bit accessor invalid for 32-bit field");
1494 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1495 "64-bit accessor invalid for natural width field");
1498 static __always_inline
void vmcs_checkl(unsigned long field
)
1500 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1501 "Natural width accessor invalid for 16-bit field");
1502 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1503 "Natural width accessor invalid for 64-bit field");
1504 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1505 "Natural width accessor invalid for 64-bit high field");
1506 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1507 "Natural width accessor invalid for 32-bit field");
1510 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1512 unsigned long value
;
1514 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1515 : "=a"(value
) : "d"(field
) : "cc");
1519 static __always_inline u16
vmcs_read16(unsigned long field
)
1521 vmcs_check16(field
);
1522 return __vmcs_readl(field
);
1525 static __always_inline u32
vmcs_read32(unsigned long field
)
1527 vmcs_check32(field
);
1528 return __vmcs_readl(field
);
1531 static __always_inline u64
vmcs_read64(unsigned long field
)
1533 vmcs_check64(field
);
1534 #ifdef CONFIG_X86_64
1535 return __vmcs_readl(field
);
1537 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1541 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1544 return __vmcs_readl(field
);
1547 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1549 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1550 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1554 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1558 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1559 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1560 if (unlikely(error
))
1561 vmwrite_error(field
, value
);
1564 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1566 vmcs_check16(field
);
1567 __vmcs_writel(field
, value
);
1570 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1572 vmcs_check32(field
);
1573 __vmcs_writel(field
, value
);
1576 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1578 vmcs_check64(field
);
1579 __vmcs_writel(field
, value
);
1580 #ifndef CONFIG_X86_64
1582 __vmcs_writel(field
+1, value
>> 32);
1586 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1589 __vmcs_writel(field
, value
);
1592 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1594 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1595 "vmcs_clear_bits does not support 64-bit fields");
1596 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1599 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1601 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1602 "vmcs_set_bits does not support 64-bit fields");
1603 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1606 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1608 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1609 vmx
->vm_entry_controls_shadow
= val
;
1612 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1614 if (vmx
->vm_entry_controls_shadow
!= val
)
1615 vm_entry_controls_init(vmx
, val
);
1618 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1620 return vmx
->vm_entry_controls_shadow
;
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1626 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1631 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1634 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1636 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1637 vmx
->vm_exit_controls_shadow
= val
;
1640 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1642 if (vmx
->vm_exit_controls_shadow
!= val
)
1643 vm_exit_controls_init(vmx
, val
);
1646 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1648 return vmx
->vm_exit_controls_shadow
;
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1654 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1659 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1662 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1664 vmx
->segment_cache
.bitmask
= 0;
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1671 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1673 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1674 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1675 vmx
->segment_cache
.bitmask
= 0;
1677 ret
= vmx
->segment_cache
.bitmask
& mask
;
1678 vmx
->segment_cache
.bitmask
|= mask
;
1682 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1684 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1686 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1687 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1691 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1693 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1695 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1696 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1700 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1702 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1704 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1705 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1709 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1711 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1713 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1714 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1718 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1722 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1723 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1724 if ((vcpu
->guest_debug
&
1725 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1726 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1727 eb
|= 1u << BP_VECTOR
;
1728 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1731 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1732 if (vcpu
->fpu_active
)
1733 eb
&= ~(1u << NM_VECTOR
);
1735 /* When we are running a nested L2 guest and L1 specified for it a
1736 * certain exception bitmap, we must trap the same exceptions and pass
1737 * them to L1. When running L2, we will only handle the exceptions
1738 * specified above if L1 did not want them.
1740 if (is_guest_mode(vcpu
))
1741 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1743 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1747 unsigned long entry
, unsigned long exit
)
1749 vm_entry_controls_clearbit(vmx
, entry
);
1750 vm_exit_controls_clearbit(vmx
, exit
);
1753 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1756 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1760 if (cpu_has_load_ia32_efer
) {
1761 clear_atomic_switch_msr_special(vmx
,
1762 VM_ENTRY_LOAD_IA32_EFER
,
1763 VM_EXIT_LOAD_IA32_EFER
);
1767 case MSR_CORE_PERF_GLOBAL_CTRL
:
1768 if (cpu_has_load_perf_global_ctrl
) {
1769 clear_atomic_switch_msr_special(vmx
,
1770 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1771 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1777 for (i
= 0; i
< m
->nr
; ++i
)
1778 if (m
->guest
[i
].index
== msr
)
1784 m
->guest
[i
] = m
->guest
[m
->nr
];
1785 m
->host
[i
] = m
->host
[m
->nr
];
1786 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1787 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1791 unsigned long entry
, unsigned long exit
,
1792 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1793 u64 guest_val
, u64 host_val
)
1795 vmcs_write64(guest_val_vmcs
, guest_val
);
1796 vmcs_write64(host_val_vmcs
, host_val
);
1797 vm_entry_controls_setbit(vmx
, entry
);
1798 vm_exit_controls_setbit(vmx
, exit
);
1801 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1802 u64 guest_val
, u64 host_val
)
1805 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1809 if (cpu_has_load_ia32_efer
) {
1810 add_atomic_switch_msr_special(vmx
,
1811 VM_ENTRY_LOAD_IA32_EFER
,
1812 VM_EXIT_LOAD_IA32_EFER
,
1815 guest_val
, host_val
);
1819 case MSR_CORE_PERF_GLOBAL_CTRL
:
1820 if (cpu_has_load_perf_global_ctrl
) {
1821 add_atomic_switch_msr_special(vmx
,
1822 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1823 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1824 GUEST_IA32_PERF_GLOBAL_CTRL
,
1825 HOST_IA32_PERF_GLOBAL_CTRL
,
1826 guest_val
, host_val
);
1830 case MSR_IA32_PEBS_ENABLE
:
1831 /* PEBS needs a quiescent period after being disabled (to write
1832 * a record). Disabling PEBS through VMX MSR swapping doesn't
1833 * provide that period, so a CPU could write host's record into
1836 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1839 for (i
= 0; i
< m
->nr
; ++i
)
1840 if (m
->guest
[i
].index
== msr
)
1843 if (i
== NR_AUTOLOAD_MSRS
) {
1844 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1845 "Can't add msr %x\n", msr
);
1847 } else if (i
== m
->nr
) {
1849 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1850 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1853 m
->guest
[i
].index
= msr
;
1854 m
->guest
[i
].value
= guest_val
;
1855 m
->host
[i
].index
= msr
;
1856 m
->host
[i
].value
= host_val
;
1859 static void reload_tss(void)
1862 * VT restores TR but not its size. Useless.
1864 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1865 struct desc_struct
*descs
;
1867 descs
= (void *)gdt
->address
;
1868 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1872 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1874 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1875 u64 ignore_bits
= 0;
1879 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1880 * host CPUID is more efficient than testing guest CPUID
1881 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1883 if (boot_cpu_has(X86_FEATURE_SMEP
))
1884 guest_efer
|= EFER_NX
;
1885 else if (!(guest_efer
& EFER_NX
))
1886 ignore_bits
|= EFER_NX
;
1890 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1892 ignore_bits
|= EFER_SCE
;
1893 #ifdef CONFIG_X86_64
1894 ignore_bits
|= EFER_LMA
| EFER_LME
;
1895 /* SCE is meaningful only in long mode on Intel */
1896 if (guest_efer
& EFER_LMA
)
1897 ignore_bits
&= ~(u64
)EFER_SCE
;
1900 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1903 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904 * On CPUs that support "load IA32_EFER", always switch EFER
1905 * atomically, since it's faster than switching it manually.
1907 if (cpu_has_load_ia32_efer
||
1908 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1909 if (!(guest_efer
& EFER_LMA
))
1910 guest_efer
&= ~EFER_LME
;
1911 if (guest_efer
!= host_efer
)
1912 add_atomic_switch_msr(vmx
, MSR_EFER
,
1913 guest_efer
, host_efer
);
1916 guest_efer
&= ~ignore_bits
;
1917 guest_efer
|= host_efer
& ignore_bits
;
1919 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1920 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1926 static unsigned long segment_base(u16 selector
)
1928 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1929 struct desc_struct
*d
;
1930 unsigned long table_base
;
1933 if (!(selector
& ~3))
1936 table_base
= gdt
->address
;
1938 if (selector
& 4) { /* from ldt */
1939 u16 ldt_selector
= kvm_read_ldt();
1941 if (!(ldt_selector
& ~3))
1944 table_base
= segment_base(ldt_selector
);
1946 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1947 v
= get_desc_base(d
);
1948 #ifdef CONFIG_X86_64
1949 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1950 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1955 static inline unsigned long kvm_read_tr_base(void)
1958 asm("str %0" : "=g"(tr
));
1959 return segment_base(tr
);
1962 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1964 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1967 if (vmx
->host_state
.loaded
)
1970 vmx
->host_state
.loaded
= 1;
1972 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1973 * allow segment selectors with cpl > 0 or ti == 1.
1975 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1976 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1977 savesegment(fs
, vmx
->host_state
.fs_sel
);
1978 if (!(vmx
->host_state
.fs_sel
& 7)) {
1979 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1980 vmx
->host_state
.fs_reload_needed
= 0;
1982 vmcs_write16(HOST_FS_SELECTOR
, 0);
1983 vmx
->host_state
.fs_reload_needed
= 1;
1985 savesegment(gs
, vmx
->host_state
.gs_sel
);
1986 if (!(vmx
->host_state
.gs_sel
& 7))
1987 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1989 vmcs_write16(HOST_GS_SELECTOR
, 0);
1990 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1993 #ifdef CONFIG_X86_64
1994 savesegment(ds
, vmx
->host_state
.ds_sel
);
1995 savesegment(es
, vmx
->host_state
.es_sel
);
1998 #ifdef CONFIG_X86_64
1999 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2000 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2002 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2003 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2006 #ifdef CONFIG_X86_64
2007 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2008 if (is_long_mode(&vmx
->vcpu
))
2009 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2011 if (boot_cpu_has(X86_FEATURE_MPX
))
2012 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2013 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2014 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2015 vmx
->guest_msrs
[i
].data
,
2016 vmx
->guest_msrs
[i
].mask
);
2019 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2021 if (!vmx
->host_state
.loaded
)
2024 ++vmx
->vcpu
.stat
.host_state_reload
;
2025 vmx
->host_state
.loaded
= 0;
2026 #ifdef CONFIG_X86_64
2027 if (is_long_mode(&vmx
->vcpu
))
2028 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2030 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2031 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2032 #ifdef CONFIG_X86_64
2033 load_gs_index(vmx
->host_state
.gs_sel
);
2035 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2038 if (vmx
->host_state
.fs_reload_needed
)
2039 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2040 #ifdef CONFIG_X86_64
2041 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2042 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2043 loadsegment(es
, vmx
->host_state
.es_sel
);
2047 #ifdef CONFIG_X86_64
2048 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2050 if (vmx
->host_state
.msr_host_bndcfgs
)
2051 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2053 * If the FPU is not active (through the host task or
2054 * the guest vcpu), then restore the cr0.TS bit.
2056 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2058 load_gdt(this_cpu_ptr(&host_gdt
));
2061 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2064 __vmx_load_host_state(vmx
);
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2070 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2071 struct pi_desc old
, new;
2074 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2075 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2076 !kvm_vcpu_apicv_active(vcpu
))
2080 old
.control
= new.control
= pi_desc
->control
;
2083 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2084 * are two possible cases:
2085 * 1. After running 'pre_block', context switch
2086 * happened. For this case, 'sn' was set in
2087 * vmx_vcpu_put(), so we need to clear it here.
2088 * 2. After running 'pre_block', we were blocked,
2089 * and woken up by some other guy. For this case,
2090 * we don't need to do anything, 'pi_post_block'
2091 * will do everything for us. However, we cannot
2092 * check whether it is case #1 or case #2 here
2093 * (maybe, not needed), so we also clear sn here,
2094 * I think it is not a big deal.
2096 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2097 if (vcpu
->cpu
!= cpu
) {
2098 dest
= cpu_physical_id(cpu
);
2100 if (x2apic_enabled())
2103 new.ndst
= (dest
<< 8) & 0xFF00;
2106 /* set 'NV' to 'notification vector' */
2107 new.nv
= POSTED_INTR_VECTOR
;
2110 /* Allow posting non-urgent interrupts */
2112 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2113 new.control
) != old
.control
);
2117 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2118 * vcpu mutex is already taken.
2120 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2123 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2126 kvm_cpu_vmxon(phys_addr
);
2127 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2128 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2130 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2131 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2132 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2135 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2136 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2137 unsigned long sysenter_esp
;
2139 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2140 local_irq_disable();
2141 crash_disable_local_vmclear(cpu
);
2144 * Read loaded_vmcs->cpu should be before fetching
2145 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2146 * See the comments in __loaded_vmcs_clear().
2150 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2151 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2152 crash_enable_local_vmclear(cpu
);
2156 * Linux uses per-cpu TSS and GDT, so set these when switching
2159 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2160 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2162 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2163 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2165 vmx
->loaded_vmcs
->cpu
= cpu
;
2168 /* Setup TSC multiplier */
2169 if (kvm_has_tsc_control
&&
2170 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
) {
2171 vmx
->current_tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2172 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2175 vmx_vcpu_pi_load(vcpu
, cpu
);
2176 vmx
->host_pkru
= read_pkru();
2179 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2181 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2183 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2184 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2185 !kvm_vcpu_apicv_active(vcpu
))
2188 /* Set SN when the vCPU is preempted */
2189 if (vcpu
->preempted
)
2193 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2195 vmx_vcpu_pi_put(vcpu
);
2197 __vmx_load_host_state(to_vmx(vcpu
));
2198 if (!vmm_exclusive
) {
2199 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2205 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2209 if (vcpu
->fpu_active
)
2211 vcpu
->fpu_active
= 1;
2212 cr0
= vmcs_readl(GUEST_CR0
);
2213 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2214 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2215 vmcs_writel(GUEST_CR0
, cr0
);
2216 update_exception_bitmap(vcpu
);
2217 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2218 if (is_guest_mode(vcpu
))
2219 vcpu
->arch
.cr0_guest_owned_bits
&=
2220 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2221 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2224 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2227 * Return the cr0 value that a nested guest would read. This is a combination
2228 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2229 * its hypervisor (cr0_read_shadow).
2231 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2233 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2234 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2236 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2238 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2239 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2242 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2244 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2245 * set this *before* calling this function.
2247 vmx_decache_cr0_guest_bits(vcpu
);
2248 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2249 update_exception_bitmap(vcpu
);
2250 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2251 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2252 if (is_guest_mode(vcpu
)) {
2254 * L1's specified read shadow might not contain the TS bit,
2255 * so now that we turned on shadowing of this bit, we need to
2256 * set this bit of the shadow. Like in nested_vmx_run we need
2257 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2258 * up-to-date here because we just decached cr0.TS (and we'll
2259 * only update vmcs12->guest_cr0 on nested exit).
2261 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2262 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2263 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2264 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2266 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2269 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2271 unsigned long rflags
, save_rflags
;
2273 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2274 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2275 rflags
= vmcs_readl(GUEST_RFLAGS
);
2276 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2277 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2278 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2279 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2281 to_vmx(vcpu
)->rflags
= rflags
;
2283 return to_vmx(vcpu
)->rflags
;
2286 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2288 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2289 to_vmx(vcpu
)->rflags
= rflags
;
2290 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2291 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2292 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2294 vmcs_writel(GUEST_RFLAGS
, rflags
);
2297 static u32
vmx_get_pkru(struct kvm_vcpu
*vcpu
)
2299 return to_vmx(vcpu
)->guest_pkru
;
2302 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2304 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2307 if (interruptibility
& GUEST_INTR_STATE_STI
)
2308 ret
|= KVM_X86_SHADOW_INT_STI
;
2309 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2310 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2315 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2317 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2318 u32 interruptibility
= interruptibility_old
;
2320 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2322 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2323 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2324 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2325 interruptibility
|= GUEST_INTR_STATE_STI
;
2327 if ((interruptibility
!= interruptibility_old
))
2328 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2331 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2335 rip
= kvm_rip_read(vcpu
);
2336 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2337 kvm_rip_write(vcpu
, rip
);
2339 /* skipping an emulated instruction also counts */
2340 vmx_set_interrupt_shadow(vcpu
, 0);
2344 * KVM wants to inject page-faults which it got to the guest. This function
2345 * checks whether in a nested guest, we need to inject them to L1 or L2.
2347 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2349 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2351 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2354 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2355 vmcs_read32(VM_EXIT_INTR_INFO
),
2356 vmcs_readl(EXIT_QUALIFICATION
));
2360 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2361 bool has_error_code
, u32 error_code
,
2364 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2365 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2367 if (!reinject
&& is_guest_mode(vcpu
) &&
2368 nested_vmx_check_exception(vcpu
, nr
))
2371 if (has_error_code
) {
2372 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2373 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2376 if (vmx
->rmode
.vm86_active
) {
2378 if (kvm_exception_is_soft(nr
))
2379 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2380 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2381 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2385 if (kvm_exception_is_soft(nr
)) {
2386 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2387 vmx
->vcpu
.arch
.event_exit_inst_len
);
2388 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2390 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2392 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2395 static bool vmx_rdtscp_supported(void)
2397 return cpu_has_vmx_rdtscp();
2400 static bool vmx_invpcid_supported(void)
2402 return cpu_has_vmx_invpcid() && enable_ept
;
2406 * Swap MSR entry in host/guest MSR entry array.
2408 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2410 struct shared_msr_entry tmp
;
2412 tmp
= vmx
->guest_msrs
[to
];
2413 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2414 vmx
->guest_msrs
[from
] = tmp
;
2417 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2419 unsigned long *msr_bitmap
;
2421 if (is_guest_mode(vcpu
))
2422 msr_bitmap
= vmx_msr_bitmap_nested
;
2423 else if (cpu_has_secondary_exec_ctrls() &&
2424 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2425 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2426 if (is_long_mode(vcpu
))
2427 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2429 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2431 if (is_long_mode(vcpu
))
2432 msr_bitmap
= vmx_msr_bitmap_longmode
;
2434 msr_bitmap
= vmx_msr_bitmap_legacy
;
2437 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2441 * Set up the vmcs to automatically save and restore system
2442 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2443 * mode, as fiddling with msrs is very expensive.
2445 static void setup_msrs(struct vcpu_vmx
*vmx
)
2447 int save_nmsrs
, index
;
2450 #ifdef CONFIG_X86_64
2451 if (is_long_mode(&vmx
->vcpu
)) {
2452 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2454 move_msr_up(vmx
, index
, save_nmsrs
++);
2455 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2457 move_msr_up(vmx
, index
, save_nmsrs
++);
2458 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2460 move_msr_up(vmx
, index
, save_nmsrs
++);
2461 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2462 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2463 move_msr_up(vmx
, index
, save_nmsrs
++);
2465 * MSR_STAR is only needed on long mode guests, and only
2466 * if efer.sce is enabled.
2468 index
= __find_msr_index(vmx
, MSR_STAR
);
2469 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2470 move_msr_up(vmx
, index
, save_nmsrs
++);
2473 index
= __find_msr_index(vmx
, MSR_EFER
);
2474 if (index
>= 0 && update_transition_efer(vmx
, index
))
2475 move_msr_up(vmx
, index
, save_nmsrs
++);
2477 vmx
->save_nmsrs
= save_nmsrs
;
2479 if (cpu_has_vmx_msr_bitmap())
2480 vmx_set_msr_bitmap(&vmx
->vcpu
);
2484 * reads and returns guest's timestamp counter "register"
2485 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2486 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2488 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2490 u64 host_tsc
, tsc_offset
;
2493 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2494 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2498 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2499 * counter, even if a nested guest (L2) is currently running.
2501 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2505 tsc_offset
= is_guest_mode(vcpu
) ?
2506 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2507 vmcs_read64(TSC_OFFSET
);
2508 return host_tsc
+ tsc_offset
;
2511 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2513 return vmcs_read64(TSC_OFFSET
);
2517 * writes 'offset' into guest's timestamp counter offset register
2519 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2521 if (is_guest_mode(vcpu
)) {
2523 * We're here if L1 chose not to trap WRMSR to TSC. According
2524 * to the spec, this should set L1's TSC; The offset that L1
2525 * set for L2 remains unchanged, and still needs to be added
2526 * to the newly set TSC to get L2's TSC.
2528 struct vmcs12
*vmcs12
;
2529 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2530 /* recalculate vmcs02.TSC_OFFSET: */
2531 vmcs12
= get_vmcs12(vcpu
);
2532 vmcs_write64(TSC_OFFSET
, offset
+
2533 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2534 vmcs12
->tsc_offset
: 0));
2536 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2537 vmcs_read64(TSC_OFFSET
), offset
);
2538 vmcs_write64(TSC_OFFSET
, offset
);
2542 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2544 u64 offset
= vmcs_read64(TSC_OFFSET
);
2546 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2547 if (is_guest_mode(vcpu
)) {
2548 /* Even when running L2, the adjustment needs to apply to L1 */
2549 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2551 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2552 offset
+ adjustment
);
2555 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2557 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2558 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2562 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2563 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2564 * all guests if the "nested" module option is off, and can also be disabled
2565 * for a single guest by disabling its VMX cpuid bit.
2567 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2569 return nested
&& guest_cpuid_has_vmx(vcpu
);
2573 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2574 * returned for the various VMX controls MSRs when nested VMX is enabled.
2575 * The same values should also be used to verify that vmcs12 control fields are
2576 * valid during nested entry from L1 to L2.
2577 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2578 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2579 * bit in the high half is on if the corresponding bit in the control field
2580 * may be on. See also vmx_control_verify().
2582 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2585 * Note that as a general rule, the high half of the MSRs (bits in
2586 * the control fields which may be 1) should be initialized by the
2587 * intersection of the underlying hardware's MSR (i.e., features which
2588 * can be supported) and the list of features we want to expose -
2589 * because they are known to be properly supported in our code.
2590 * Also, usually, the low half of the MSRs (bits which must be 1) can
2591 * be set to 0, meaning that L1 may turn off any of these bits. The
2592 * reason is that if one of these bits is necessary, it will appear
2593 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2594 * fields of vmcs01 and vmcs02, will turn these bits off - and
2595 * nested_vmx_exit_handled() will not pass related exits to L1.
2596 * These rules have exceptions below.
2599 /* pin-based controls */
2600 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2601 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2602 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2603 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2604 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2605 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2606 PIN_BASED_EXT_INTR_MASK
|
2607 PIN_BASED_NMI_EXITING
|
2608 PIN_BASED_VIRTUAL_NMIS
;
2609 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2610 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2611 PIN_BASED_VMX_PREEMPTION_TIMER
;
2612 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2613 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2614 PIN_BASED_POSTED_INTR
;
2617 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2618 vmx
->nested
.nested_vmx_exit_ctls_low
,
2619 vmx
->nested
.nested_vmx_exit_ctls_high
);
2620 vmx
->nested
.nested_vmx_exit_ctls_low
=
2621 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2623 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2624 #ifdef CONFIG_X86_64
2625 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2627 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2628 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2629 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2630 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2631 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2633 if (kvm_mpx_supported())
2634 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2636 /* We support free control of debug control saving. */
2637 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2638 vmx
->nested
.nested_vmx_exit_ctls_low
&
2639 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2641 /* entry controls */
2642 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2643 vmx
->nested
.nested_vmx_entry_ctls_low
,
2644 vmx
->nested
.nested_vmx_entry_ctls_high
);
2645 vmx
->nested
.nested_vmx_entry_ctls_low
=
2646 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2647 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2648 #ifdef CONFIG_X86_64
2649 VM_ENTRY_IA32E_MODE
|
2651 VM_ENTRY_LOAD_IA32_PAT
;
2652 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2653 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2654 if (kvm_mpx_supported())
2655 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2657 /* We support free control of debug control loading. */
2658 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2659 vmx
->nested
.nested_vmx_entry_ctls_low
&
2660 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2662 /* cpu-based controls */
2663 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2664 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2665 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2666 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2667 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2668 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2669 CPU_BASED_VIRTUAL_INTR_PENDING
|
2670 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2671 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2672 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2673 CPU_BASED_CR3_STORE_EXITING
|
2674 #ifdef CONFIG_X86_64
2675 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2677 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2678 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2679 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2680 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2681 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2683 * We can allow some features even when not supported by the
2684 * hardware. For example, L1 can specify an MSR bitmap - and we
2685 * can use it to avoid exits to L1 - even when L0 runs L2
2686 * without MSR bitmaps.
2688 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2689 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2690 CPU_BASED_USE_MSR_BITMAPS
;
2692 /* We support free control of CR3 access interception. */
2693 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2694 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2695 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2697 /* secondary cpu-based controls */
2698 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2699 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2700 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2701 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2702 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2703 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2704 SECONDARY_EXEC_RDTSCP
|
2705 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2706 SECONDARY_EXEC_ENABLE_VPID
|
2707 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2708 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2709 SECONDARY_EXEC_WBINVD_EXITING
|
2710 SECONDARY_EXEC_XSAVES
;
2713 /* nested EPT: emulate EPT also to L1 */
2714 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2715 SECONDARY_EXEC_ENABLE_EPT
;
2716 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2717 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2719 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2721 * For nested guests, we don't do anything specific
2722 * for single context invalidation. Hence, only advertise
2723 * support for global context invalidation.
2725 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2727 vmx
->nested
.nested_vmx_ept_caps
= 0;
2730 * Old versions of KVM use the single-context version without
2731 * checking for support, so declare that it is supported even
2732 * though it is treated as global context. The alternative is
2733 * not failing the single-context invvpid, and it is worse.
2736 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2737 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
|
2738 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2740 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2742 if (enable_unrestricted_guest
)
2743 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2744 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2746 /* miscellaneous data */
2747 rdmsr(MSR_IA32_VMX_MISC
,
2748 vmx
->nested
.nested_vmx_misc_low
,
2749 vmx
->nested
.nested_vmx_misc_high
);
2750 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2751 vmx
->nested
.nested_vmx_misc_low
|=
2752 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2753 VMX_MISC_ACTIVITY_HLT
;
2754 vmx
->nested
.nested_vmx_misc_high
= 0;
2757 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2760 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2762 return ((control
& high
) | low
) == control
;
2765 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2767 return low
| ((u64
)high
<< 32);
2770 /* Returns 0 on success, non-0 otherwise. */
2771 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2773 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2775 switch (msr_index
) {
2776 case MSR_IA32_VMX_BASIC
:
2778 * This MSR reports some information about VMX support. We
2779 * should return information about the VMX we emulate for the
2780 * guest, and the VMCS structure we give it - not about the
2781 * VMX support of the underlying hardware.
2783 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2784 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2785 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2787 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2788 case MSR_IA32_VMX_PINBASED_CTLS
:
2789 *pdata
= vmx_control_msr(
2790 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2791 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2793 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2794 *pdata
= vmx_control_msr(
2795 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2796 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2798 case MSR_IA32_VMX_PROCBASED_CTLS
:
2799 *pdata
= vmx_control_msr(
2800 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2801 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2803 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2804 *pdata
= vmx_control_msr(
2805 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2806 vmx
->nested
.nested_vmx_exit_ctls_high
);
2808 case MSR_IA32_VMX_EXIT_CTLS
:
2809 *pdata
= vmx_control_msr(
2810 vmx
->nested
.nested_vmx_exit_ctls_low
,
2811 vmx
->nested
.nested_vmx_exit_ctls_high
);
2813 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2814 *pdata
= vmx_control_msr(
2815 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2816 vmx
->nested
.nested_vmx_entry_ctls_high
);
2818 case MSR_IA32_VMX_ENTRY_CTLS
:
2819 *pdata
= vmx_control_msr(
2820 vmx
->nested
.nested_vmx_entry_ctls_low
,
2821 vmx
->nested
.nested_vmx_entry_ctls_high
);
2823 case MSR_IA32_VMX_MISC
:
2824 *pdata
= vmx_control_msr(
2825 vmx
->nested
.nested_vmx_misc_low
,
2826 vmx
->nested
.nested_vmx_misc_high
);
2829 * These MSRs specify bits which the guest must keep fixed (on or off)
2830 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2831 * We picked the standard core2 setting.
2833 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2834 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2835 case MSR_IA32_VMX_CR0_FIXED0
:
2836 *pdata
= VMXON_CR0_ALWAYSON
;
2838 case MSR_IA32_VMX_CR0_FIXED1
:
2841 case MSR_IA32_VMX_CR4_FIXED0
:
2842 *pdata
= VMXON_CR4_ALWAYSON
;
2844 case MSR_IA32_VMX_CR4_FIXED1
:
2847 case MSR_IA32_VMX_VMCS_ENUM
:
2848 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2850 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2851 *pdata
= vmx_control_msr(
2852 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2853 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2855 case MSR_IA32_VMX_EPT_VPID_CAP
:
2856 /* Currently, no nested vpid support */
2857 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2858 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2868 * Reads an msr value (of 'msr_index') into 'pdata'.
2869 * Returns 0 on success, non-0 otherwise.
2870 * Assumes vcpu_load() was already called.
2872 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2874 struct shared_msr_entry
*msr
;
2876 switch (msr_info
->index
) {
2877 #ifdef CONFIG_X86_64
2879 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2882 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2884 case MSR_KERNEL_GS_BASE
:
2885 vmx_load_host_state(to_vmx(vcpu
));
2886 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2890 return kvm_get_msr_common(vcpu
, msr_info
);
2892 msr_info
->data
= guest_read_tsc(vcpu
);
2894 case MSR_IA32_SYSENTER_CS
:
2895 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2897 case MSR_IA32_SYSENTER_EIP
:
2898 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2900 case MSR_IA32_SYSENTER_ESP
:
2901 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2903 case MSR_IA32_BNDCFGS
:
2904 if (!kvm_mpx_supported())
2906 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2908 case MSR_IA32_FEATURE_CONTROL
:
2909 if (!nested_vmx_allowed(vcpu
))
2911 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2913 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2914 if (!nested_vmx_allowed(vcpu
))
2916 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2918 if (!vmx_xsaves_supported())
2920 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2923 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2925 /* Otherwise falls through */
2927 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2929 msr_info
->data
= msr
->data
;
2932 return kvm_get_msr_common(vcpu
, msr_info
);
2938 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2941 * Writes msr value into into the appropriate "register".
2942 * Returns 0 on success, non-0 otherwise.
2943 * Assumes vcpu_load() was already called.
2945 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2947 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2948 struct shared_msr_entry
*msr
;
2950 u32 msr_index
= msr_info
->index
;
2951 u64 data
= msr_info
->data
;
2953 switch (msr_index
) {
2955 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2957 #ifdef CONFIG_X86_64
2959 vmx_segment_cache_clear(vmx
);
2960 vmcs_writel(GUEST_FS_BASE
, data
);
2963 vmx_segment_cache_clear(vmx
);
2964 vmcs_writel(GUEST_GS_BASE
, data
);
2966 case MSR_KERNEL_GS_BASE
:
2967 vmx_load_host_state(vmx
);
2968 vmx
->msr_guest_kernel_gs_base
= data
;
2971 case MSR_IA32_SYSENTER_CS
:
2972 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2974 case MSR_IA32_SYSENTER_EIP
:
2975 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2977 case MSR_IA32_SYSENTER_ESP
:
2978 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2980 case MSR_IA32_BNDCFGS
:
2981 if (!kvm_mpx_supported())
2983 vmcs_write64(GUEST_BNDCFGS
, data
);
2986 kvm_write_tsc(vcpu
, msr_info
);
2988 case MSR_IA32_CR_PAT
:
2989 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2990 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2992 vmcs_write64(GUEST_IA32_PAT
, data
);
2993 vcpu
->arch
.pat
= data
;
2996 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2998 case MSR_IA32_TSC_ADJUST
:
2999 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3001 case MSR_IA32_FEATURE_CONTROL
:
3002 if (!nested_vmx_allowed(vcpu
) ||
3003 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
3004 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3006 vmx
->nested
.msr_ia32_feature_control
= data
;
3007 if (msr_info
->host_initiated
&& data
== 0)
3008 vmx_leave_nested(vcpu
);
3010 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3011 return 1; /* they are read-only */
3013 if (!vmx_xsaves_supported())
3016 * The only supported bit as of Skylake is bit 8, but
3017 * it is not supported on KVM.
3021 vcpu
->arch
.ia32_xss
= data
;
3022 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3023 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3024 vcpu
->arch
.ia32_xss
, host_xss
);
3026 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3029 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3031 /* Check reserved bit, higher 32 bits should be zero */
3032 if ((data
>> 32) != 0)
3034 /* Otherwise falls through */
3036 msr
= find_msr_entry(vmx
, msr_index
);
3038 u64 old_msr_data
= msr
->data
;
3040 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3042 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3046 msr
->data
= old_msr_data
;
3050 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3056 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3058 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3061 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3064 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3066 case VCPU_EXREG_PDPTR
:
3068 ept_save_pdptrs(vcpu
);
3075 static __init
int cpu_has_kvm_support(void)
3077 return cpu_has_vmx();
3080 static __init
int vmx_disabled_by_bios(void)
3084 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3085 if (msr
& FEATURE_CONTROL_LOCKED
) {
3086 /* launched w/ TXT and VMX disabled */
3087 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3090 /* launched w/o TXT and VMX only enabled w/ TXT */
3091 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3092 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3093 && !tboot_enabled()) {
3094 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3095 "activate TXT before enabling KVM\n");
3098 /* launched w/o TXT and VMX disabled */
3099 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3100 && !tboot_enabled())
3107 static void kvm_cpu_vmxon(u64 addr
)
3109 intel_pt_handle_vmx(1);
3111 asm volatile (ASM_VMX_VMXON_RAX
3112 : : "a"(&addr
), "m"(addr
)
3116 static int hardware_enable(void)
3118 int cpu
= raw_smp_processor_id();
3119 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3122 if (cr4_read_shadow() & X86_CR4_VMXE
)
3125 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3126 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3127 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3130 * Now we can enable the vmclear operation in kdump
3131 * since the loaded_vmcss_on_cpu list on this cpu
3132 * has been initialized.
3134 * Though the cpu is not in VMX operation now, there
3135 * is no problem to enable the vmclear operation
3136 * for the loaded_vmcss_on_cpu list is empty!
3138 crash_enable_local_vmclear(cpu
);
3140 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3142 test_bits
= FEATURE_CONTROL_LOCKED
;
3143 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3144 if (tboot_enabled())
3145 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3147 if ((old
& test_bits
) != test_bits
) {
3148 /* enable and lock */
3149 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3151 cr4_set_bits(X86_CR4_VMXE
);
3153 if (vmm_exclusive
) {
3154 kvm_cpu_vmxon(phys_addr
);
3158 native_store_gdt(this_cpu_ptr(&host_gdt
));
3163 static void vmclear_local_loaded_vmcss(void)
3165 int cpu
= raw_smp_processor_id();
3166 struct loaded_vmcs
*v
, *n
;
3168 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3169 loaded_vmcss_on_cpu_link
)
3170 __loaded_vmcs_clear(v
);
3174 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3177 static void kvm_cpu_vmxoff(void)
3179 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3181 intel_pt_handle_vmx(0);
3184 static void hardware_disable(void)
3186 if (vmm_exclusive
) {
3187 vmclear_local_loaded_vmcss();
3190 cr4_clear_bits(X86_CR4_VMXE
);
3193 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3194 u32 msr
, u32
*result
)
3196 u32 vmx_msr_low
, vmx_msr_high
;
3197 u32 ctl
= ctl_min
| ctl_opt
;
3199 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3201 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3202 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3204 /* Ensure minimum (required) set of control bits are supported. */
3212 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3214 u32 vmx_msr_low
, vmx_msr_high
;
3216 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3217 return vmx_msr_high
& ctl
;
3220 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3222 u32 vmx_msr_low
, vmx_msr_high
;
3223 u32 min
, opt
, min2
, opt2
;
3224 u32 _pin_based_exec_control
= 0;
3225 u32 _cpu_based_exec_control
= 0;
3226 u32 _cpu_based_2nd_exec_control
= 0;
3227 u32 _vmexit_control
= 0;
3228 u32 _vmentry_control
= 0;
3230 min
= CPU_BASED_HLT_EXITING
|
3231 #ifdef CONFIG_X86_64
3232 CPU_BASED_CR8_LOAD_EXITING
|
3233 CPU_BASED_CR8_STORE_EXITING
|
3235 CPU_BASED_CR3_LOAD_EXITING
|
3236 CPU_BASED_CR3_STORE_EXITING
|
3237 CPU_BASED_USE_IO_BITMAPS
|
3238 CPU_BASED_MOV_DR_EXITING
|
3239 CPU_BASED_USE_TSC_OFFSETING
|
3240 CPU_BASED_MWAIT_EXITING
|
3241 CPU_BASED_MONITOR_EXITING
|
3242 CPU_BASED_INVLPG_EXITING
|
3243 CPU_BASED_RDPMC_EXITING
;
3245 opt
= CPU_BASED_TPR_SHADOW
|
3246 CPU_BASED_USE_MSR_BITMAPS
|
3247 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3248 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3249 &_cpu_based_exec_control
) < 0)
3251 #ifdef CONFIG_X86_64
3252 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3253 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3254 ~CPU_BASED_CR8_STORE_EXITING
;
3256 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3258 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3259 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3260 SECONDARY_EXEC_WBINVD_EXITING
|
3261 SECONDARY_EXEC_ENABLE_VPID
|
3262 SECONDARY_EXEC_ENABLE_EPT
|
3263 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3264 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3265 SECONDARY_EXEC_RDTSCP
|
3266 SECONDARY_EXEC_ENABLE_INVPCID
|
3267 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3268 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3269 SECONDARY_EXEC_SHADOW_VMCS
|
3270 SECONDARY_EXEC_XSAVES
|
3271 SECONDARY_EXEC_ENABLE_PML
|
3272 SECONDARY_EXEC_TSC_SCALING
;
3273 if (adjust_vmx_controls(min2
, opt2
,
3274 MSR_IA32_VMX_PROCBASED_CTLS2
,
3275 &_cpu_based_2nd_exec_control
) < 0)
3278 #ifndef CONFIG_X86_64
3279 if (!(_cpu_based_2nd_exec_control
&
3280 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3281 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3284 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3285 _cpu_based_2nd_exec_control
&= ~(
3286 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3287 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3288 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3290 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3291 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3293 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3294 CPU_BASED_CR3_STORE_EXITING
|
3295 CPU_BASED_INVLPG_EXITING
);
3296 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3297 vmx_capability
.ept
, vmx_capability
.vpid
);
3300 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3301 #ifdef CONFIG_X86_64
3302 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3304 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3305 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3306 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3307 &_vmexit_control
) < 0)
3310 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3311 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3312 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3313 &_pin_based_exec_control
) < 0)
3316 if (!(_cpu_based_2nd_exec_control
&
3317 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3318 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3319 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3321 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3322 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3323 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3324 &_vmentry_control
) < 0)
3327 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3329 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3330 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3333 #ifdef CONFIG_X86_64
3334 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3335 if (vmx_msr_high
& (1u<<16))
3339 /* Require Write-Back (WB) memory type for VMCS accesses. */
3340 if (((vmx_msr_high
>> 18) & 15) != 6)
3343 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3344 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3345 vmcs_conf
->revision_id
= vmx_msr_low
;
3347 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3348 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3349 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3350 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3351 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3353 cpu_has_load_ia32_efer
=
3354 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3355 VM_ENTRY_LOAD_IA32_EFER
)
3356 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3357 VM_EXIT_LOAD_IA32_EFER
);
3359 cpu_has_load_perf_global_ctrl
=
3360 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3361 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3362 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3363 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3366 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3367 * but due to arrata below it can't be used. Workaround is to use
3368 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3370 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3375 * BC86,AAY89,BD102 (model 44)
3379 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3380 switch (boot_cpu_data
.x86_model
) {
3386 cpu_has_load_perf_global_ctrl
= false;
3387 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3388 "does not work properly. Using workaround\n");
3395 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3396 rdmsrl(MSR_IA32_XSS
, host_xss
);
3401 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3403 int node
= cpu_to_node(cpu
);
3407 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3410 vmcs
= page_address(pages
);
3411 memset(vmcs
, 0, vmcs_config
.size
);
3412 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3416 static struct vmcs
*alloc_vmcs(void)
3418 return alloc_vmcs_cpu(raw_smp_processor_id());
3421 static void free_vmcs(struct vmcs
*vmcs
)
3423 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3427 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3429 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3431 if (!loaded_vmcs
->vmcs
)
3433 loaded_vmcs_clear(loaded_vmcs
);
3434 free_vmcs(loaded_vmcs
->vmcs
);
3435 loaded_vmcs
->vmcs
= NULL
;
3438 static void free_kvm_area(void)
3442 for_each_possible_cpu(cpu
) {
3443 free_vmcs(per_cpu(vmxarea
, cpu
));
3444 per_cpu(vmxarea
, cpu
) = NULL
;
3448 static void init_vmcs_shadow_fields(void)
3452 /* No checks for read only fields yet */
3454 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3455 switch (shadow_read_write_fields
[i
]) {
3457 if (!kvm_mpx_supported())
3465 shadow_read_write_fields
[j
] =
3466 shadow_read_write_fields
[i
];
3469 max_shadow_read_write_fields
= j
;
3471 /* shadowed fields guest access without vmexit */
3472 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3473 clear_bit(shadow_read_write_fields
[i
],
3474 vmx_vmwrite_bitmap
);
3475 clear_bit(shadow_read_write_fields
[i
],
3478 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3479 clear_bit(shadow_read_only_fields
[i
],
3483 static __init
int alloc_kvm_area(void)
3487 for_each_possible_cpu(cpu
) {
3490 vmcs
= alloc_vmcs_cpu(cpu
);
3496 per_cpu(vmxarea
, cpu
) = vmcs
;
3501 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3503 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3506 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3507 struct kvm_segment
*save
)
3509 if (!emulate_invalid_guest_state
) {
3511 * CS and SS RPL should be equal during guest entry according
3512 * to VMX spec, but in reality it is not always so. Since vcpu
3513 * is in the middle of the transition from real mode to
3514 * protected mode it is safe to assume that RPL 0 is a good
3517 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3518 save
->selector
&= ~SEGMENT_RPL_MASK
;
3519 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3522 vmx_set_segment(vcpu
, save
, seg
);
3525 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3527 unsigned long flags
;
3528 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3531 * Update real mode segment cache. It may be not up-to-date if sement
3532 * register was written while vcpu was in a guest mode.
3534 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3535 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3536 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3537 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3538 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3539 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3541 vmx
->rmode
.vm86_active
= 0;
3543 vmx_segment_cache_clear(vmx
);
3545 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3547 flags
= vmcs_readl(GUEST_RFLAGS
);
3548 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3549 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3550 vmcs_writel(GUEST_RFLAGS
, flags
);
3552 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3553 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3555 update_exception_bitmap(vcpu
);
3557 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3558 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3559 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3560 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3561 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3562 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3565 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3567 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3568 struct kvm_segment var
= *save
;
3571 if (seg
== VCPU_SREG_CS
)
3574 if (!emulate_invalid_guest_state
) {
3575 var
.selector
= var
.base
>> 4;
3576 var
.base
= var
.base
& 0xffff0;
3586 if (save
->base
& 0xf)
3587 printk_once(KERN_WARNING
"kvm: segment base is not "
3588 "paragraph aligned when entering "
3589 "protected mode (seg=%d)", seg
);
3592 vmcs_write16(sf
->selector
, var
.selector
);
3593 vmcs_write32(sf
->base
, var
.base
);
3594 vmcs_write32(sf
->limit
, var
.limit
);
3595 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3598 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3600 unsigned long flags
;
3601 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3603 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3604 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3605 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3606 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3607 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3608 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3609 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3611 vmx
->rmode
.vm86_active
= 1;
3614 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3615 * vcpu. Warn the user that an update is overdue.
3617 if (!vcpu
->kvm
->arch
.tss_addr
)
3618 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3619 "called before entering vcpu\n");
3621 vmx_segment_cache_clear(vmx
);
3623 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3624 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3625 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3627 flags
= vmcs_readl(GUEST_RFLAGS
);
3628 vmx
->rmode
.save_rflags
= flags
;
3630 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3632 vmcs_writel(GUEST_RFLAGS
, flags
);
3633 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3634 update_exception_bitmap(vcpu
);
3636 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3637 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3638 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3639 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3640 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3641 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3643 kvm_mmu_reset_context(vcpu
);
3646 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3648 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3649 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3655 * Force kernel_gs_base reloading before EFER changes, as control
3656 * of this msr depends on is_long_mode().
3658 vmx_load_host_state(to_vmx(vcpu
));
3659 vcpu
->arch
.efer
= efer
;
3660 if (efer
& EFER_LMA
) {
3661 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3664 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3666 msr
->data
= efer
& ~EFER_LME
;
3671 #ifdef CONFIG_X86_64
3673 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3677 vmx_segment_cache_clear(to_vmx(vcpu
));
3679 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3680 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3681 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3683 vmcs_write32(GUEST_TR_AR_BYTES
,
3684 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3685 | VMX_AR_TYPE_BUSY_64_TSS
);
3687 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3690 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3692 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3693 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3698 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3700 vpid_sync_context(vpid
);
3702 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3704 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3708 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3710 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3713 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3715 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3717 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3718 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3721 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3723 if (enable_ept
&& is_paging(vcpu
))
3724 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3725 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3728 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3730 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3732 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3733 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3736 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3738 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3740 if (!test_bit(VCPU_EXREG_PDPTR
,
3741 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3744 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3745 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3746 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3747 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3748 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3752 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3754 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3756 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3757 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3758 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3759 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3760 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3763 __set_bit(VCPU_EXREG_PDPTR
,
3764 (unsigned long *)&vcpu
->arch
.regs_avail
);
3765 __set_bit(VCPU_EXREG_PDPTR
,
3766 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3769 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3771 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3773 struct kvm_vcpu
*vcpu
)
3775 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3776 vmx_decache_cr3(vcpu
);
3777 if (!(cr0
& X86_CR0_PG
)) {
3778 /* From paging/starting to nonpaging */
3779 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3780 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3781 (CPU_BASED_CR3_LOAD_EXITING
|
3782 CPU_BASED_CR3_STORE_EXITING
));
3783 vcpu
->arch
.cr0
= cr0
;
3784 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3785 } else if (!is_paging(vcpu
)) {
3786 /* From nonpaging to paging */
3787 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3788 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3789 ~(CPU_BASED_CR3_LOAD_EXITING
|
3790 CPU_BASED_CR3_STORE_EXITING
));
3791 vcpu
->arch
.cr0
= cr0
;
3792 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3795 if (!(cr0
& X86_CR0_WP
))
3796 *hw_cr0
&= ~X86_CR0_WP
;
3799 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3801 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3802 unsigned long hw_cr0
;
3804 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3805 if (enable_unrestricted_guest
)
3806 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3808 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3810 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3813 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3817 #ifdef CONFIG_X86_64
3818 if (vcpu
->arch
.efer
& EFER_LME
) {
3819 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3821 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3827 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3829 if (!vcpu
->fpu_active
)
3830 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3832 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3833 vmcs_writel(GUEST_CR0
, hw_cr0
);
3834 vcpu
->arch
.cr0
= cr0
;
3836 /* depends on vcpu->arch.cr0 to be set to a new value */
3837 vmx
->emulation_required
= emulation_required(vcpu
);
3840 static u64
construct_eptp(unsigned long root_hpa
)
3844 /* TODO write the value reading from MSR */
3845 eptp
= VMX_EPT_DEFAULT_MT
|
3846 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3847 if (enable_ept_ad_bits
)
3848 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3849 eptp
|= (root_hpa
& PAGE_MASK
);
3854 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3856 unsigned long guest_cr3
;
3861 eptp
= construct_eptp(cr3
);
3862 vmcs_write64(EPT_POINTER
, eptp
);
3863 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3864 guest_cr3
= kvm_read_cr3(vcpu
);
3866 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3867 ept_load_pdptrs(vcpu
);
3870 vmx_flush_tlb(vcpu
);
3871 vmcs_writel(GUEST_CR3
, guest_cr3
);
3874 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3877 * Pass through host's Machine Check Enable value to hw_cr4, which
3878 * is in force while we are in guest mode. Do not let guests control
3879 * this bit, even if host CR4.MCE == 0.
3881 unsigned long hw_cr4
=
3882 (cr4_read_shadow() & X86_CR4_MCE
) |
3883 (cr4
& ~X86_CR4_MCE
) |
3884 (to_vmx(vcpu
)->rmode
.vm86_active
?
3885 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3887 if (cr4
& X86_CR4_VMXE
) {
3889 * To use VMXON (and later other VMX instructions), a guest
3890 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3891 * So basically the check on whether to allow nested VMX
3894 if (!nested_vmx_allowed(vcpu
))
3897 if (to_vmx(vcpu
)->nested
.vmxon
&&
3898 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3901 vcpu
->arch
.cr4
= cr4
;
3903 if (!is_paging(vcpu
)) {
3904 hw_cr4
&= ~X86_CR4_PAE
;
3905 hw_cr4
|= X86_CR4_PSE
;
3906 } else if (!(cr4
& X86_CR4_PAE
)) {
3907 hw_cr4
&= ~X86_CR4_PAE
;
3911 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
3913 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3914 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
3915 * to be manually disabled when guest switches to non-paging
3918 * If !enable_unrestricted_guest, the CPU is always running
3919 * with CR0.PG=1 and CR4 needs to be modified.
3920 * If enable_unrestricted_guest, the CPU automatically
3921 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3923 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
3925 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3926 vmcs_writel(GUEST_CR4
, hw_cr4
);
3930 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3931 struct kvm_segment
*var
, int seg
)
3933 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3936 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3937 *var
= vmx
->rmode
.segs
[seg
];
3938 if (seg
== VCPU_SREG_TR
3939 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3941 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3942 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3945 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3946 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3947 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3948 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3949 var
->unusable
= (ar
>> 16) & 1;
3950 var
->type
= ar
& 15;
3951 var
->s
= (ar
>> 4) & 1;
3952 var
->dpl
= (ar
>> 5) & 3;
3954 * Some userspaces do not preserve unusable property. Since usable
3955 * segment has to be present according to VMX spec we can use present
3956 * property to amend userspace bug by making unusable segment always
3957 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3958 * segment as unusable.
3960 var
->present
= !var
->unusable
;
3961 var
->avl
= (ar
>> 12) & 1;
3962 var
->l
= (ar
>> 13) & 1;
3963 var
->db
= (ar
>> 14) & 1;
3964 var
->g
= (ar
>> 15) & 1;
3967 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3969 struct kvm_segment s
;
3971 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3972 vmx_get_segment(vcpu
, &s
, seg
);
3975 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3978 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3980 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3982 if (unlikely(vmx
->rmode
.vm86_active
))
3985 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3986 return VMX_AR_DPL(ar
);
3990 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3994 if (var
->unusable
|| !var
->present
)
3997 ar
= var
->type
& 15;
3998 ar
|= (var
->s
& 1) << 4;
3999 ar
|= (var
->dpl
& 3) << 5;
4000 ar
|= (var
->present
& 1) << 7;
4001 ar
|= (var
->avl
& 1) << 12;
4002 ar
|= (var
->l
& 1) << 13;
4003 ar
|= (var
->db
& 1) << 14;
4004 ar
|= (var
->g
& 1) << 15;
4010 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4011 struct kvm_segment
*var
, int seg
)
4013 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4014 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4016 vmx_segment_cache_clear(vmx
);
4018 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4019 vmx
->rmode
.segs
[seg
] = *var
;
4020 if (seg
== VCPU_SREG_TR
)
4021 vmcs_write16(sf
->selector
, var
->selector
);
4023 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4027 vmcs_writel(sf
->base
, var
->base
);
4028 vmcs_write32(sf
->limit
, var
->limit
);
4029 vmcs_write16(sf
->selector
, var
->selector
);
4032 * Fix the "Accessed" bit in AR field of segment registers for older
4034 * IA32 arch specifies that at the time of processor reset the
4035 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4036 * is setting it to 0 in the userland code. This causes invalid guest
4037 * state vmexit when "unrestricted guest" mode is turned on.
4038 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4039 * tree. Newer qemu binaries with that qemu fix would not need this
4042 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4043 var
->type
|= 0x1; /* Accessed */
4045 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4048 vmx
->emulation_required
= emulation_required(vcpu
);
4051 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4053 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4055 *db
= (ar
>> 14) & 1;
4056 *l
= (ar
>> 13) & 1;
4059 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4061 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4062 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4065 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4067 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4068 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4071 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4073 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4074 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4077 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4079 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4080 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4083 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4085 struct kvm_segment var
;
4088 vmx_get_segment(vcpu
, &var
, seg
);
4090 if (seg
== VCPU_SREG_CS
)
4092 ar
= vmx_segment_access_rights(&var
);
4094 if (var
.base
!= (var
.selector
<< 4))
4096 if (var
.limit
!= 0xffff)
4104 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4106 struct kvm_segment cs
;
4107 unsigned int cs_rpl
;
4109 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4110 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4114 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4118 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4119 if (cs
.dpl
> cs_rpl
)
4122 if (cs
.dpl
!= cs_rpl
)
4128 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4132 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4134 struct kvm_segment ss
;
4135 unsigned int ss_rpl
;
4137 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4138 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4142 if (ss
.type
!= 3 && ss
.type
!= 7)
4146 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4154 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4156 struct kvm_segment var
;
4159 vmx_get_segment(vcpu
, &var
, seg
);
4160 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4168 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4169 if (var
.dpl
< rpl
) /* DPL < RPL */
4173 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4179 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4181 struct kvm_segment tr
;
4183 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4187 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4189 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4197 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4199 struct kvm_segment ldtr
;
4201 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4205 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4215 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4217 struct kvm_segment cs
, ss
;
4219 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4220 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4222 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4223 (ss
.selector
& SEGMENT_RPL_MASK
));
4227 * Check if guest state is valid. Returns true if valid, false if
4229 * We assume that registers are always usable
4231 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4233 if (enable_unrestricted_guest
)
4236 /* real mode guest state checks */
4237 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4238 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4240 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4242 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4244 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4246 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4248 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4251 /* protected mode guest state checks */
4252 if (!cs_ss_rpl_check(vcpu
))
4254 if (!code_segment_valid(vcpu
))
4256 if (!stack_segment_valid(vcpu
))
4258 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4260 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4262 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4264 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4266 if (!tr_valid(vcpu
))
4268 if (!ldtr_valid(vcpu
))
4272 * - Add checks on RIP
4273 * - Add checks on RFLAGS
4279 static int init_rmode_tss(struct kvm
*kvm
)
4285 idx
= srcu_read_lock(&kvm
->srcu
);
4286 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4287 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4290 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4291 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4292 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4295 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4298 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4302 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4303 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4306 srcu_read_unlock(&kvm
->srcu
, idx
);
4310 static int init_rmode_identity_map(struct kvm
*kvm
)
4313 kvm_pfn_t identity_map_pfn
;
4319 /* Protect kvm->arch.ept_identity_pagetable_done. */
4320 mutex_lock(&kvm
->slots_lock
);
4322 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4325 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4327 r
= alloc_identity_pagetable(kvm
);
4331 idx
= srcu_read_lock(&kvm
->srcu
);
4332 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4335 /* Set up identity-mapping pagetable for EPT in real mode */
4336 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4337 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4338 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4339 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4340 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4344 kvm
->arch
.ept_identity_pagetable_done
= true;
4347 srcu_read_unlock(&kvm
->srcu
, idx
);
4350 mutex_unlock(&kvm
->slots_lock
);
4354 static void seg_setup(int seg
)
4356 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4359 vmcs_write16(sf
->selector
, 0);
4360 vmcs_writel(sf
->base
, 0);
4361 vmcs_write32(sf
->limit
, 0xffff);
4363 if (seg
== VCPU_SREG_CS
)
4364 ar
|= 0x08; /* code segment */
4366 vmcs_write32(sf
->ar_bytes
, ar
);
4369 static int alloc_apic_access_page(struct kvm
*kvm
)
4374 mutex_lock(&kvm
->slots_lock
);
4375 if (kvm
->arch
.apic_access_page_done
)
4377 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4378 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4382 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4383 if (is_error_page(page
)) {
4389 * Do not pin the page in memory, so that memory hot-unplug
4390 * is able to migrate it.
4393 kvm
->arch
.apic_access_page_done
= true;
4395 mutex_unlock(&kvm
->slots_lock
);
4399 static int alloc_identity_pagetable(struct kvm
*kvm
)
4401 /* Called with kvm->slots_lock held. */
4405 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4407 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4408 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4413 static int allocate_vpid(void)
4419 spin_lock(&vmx_vpid_lock
);
4420 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4421 if (vpid
< VMX_NR_VPIDS
)
4422 __set_bit(vpid
, vmx_vpid_bitmap
);
4425 spin_unlock(&vmx_vpid_lock
);
4429 static void free_vpid(int vpid
)
4431 if (!enable_vpid
|| vpid
== 0)
4433 spin_lock(&vmx_vpid_lock
);
4434 __clear_bit(vpid
, vmx_vpid_bitmap
);
4435 spin_unlock(&vmx_vpid_lock
);
4438 #define MSR_TYPE_R 1
4439 #define MSR_TYPE_W 2
4440 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4443 int f
= sizeof(unsigned long);
4445 if (!cpu_has_vmx_msr_bitmap())
4449 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4450 * have the write-low and read-high bitmap offsets the wrong way round.
4451 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4453 if (msr
<= 0x1fff) {
4454 if (type
& MSR_TYPE_R
)
4456 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4458 if (type
& MSR_TYPE_W
)
4460 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4462 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4464 if (type
& MSR_TYPE_R
)
4466 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4468 if (type
& MSR_TYPE_W
)
4470 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4475 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4478 int f
= sizeof(unsigned long);
4480 if (!cpu_has_vmx_msr_bitmap())
4484 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4485 * have the write-low and read-high bitmap offsets the wrong way round.
4486 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4488 if (msr
<= 0x1fff) {
4489 if (type
& MSR_TYPE_R
)
4491 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4493 if (type
& MSR_TYPE_W
)
4495 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4497 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4499 if (type
& MSR_TYPE_R
)
4501 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4503 if (type
& MSR_TYPE_W
)
4505 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4511 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4512 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4514 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4515 unsigned long *msr_bitmap_nested
,
4518 int f
= sizeof(unsigned long);
4520 if (!cpu_has_vmx_msr_bitmap()) {
4526 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4527 * have the write-low and read-high bitmap offsets the wrong way round.
4528 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4530 if (msr
<= 0x1fff) {
4531 if (type
& MSR_TYPE_R
&&
4532 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4534 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4536 if (type
& MSR_TYPE_W
&&
4537 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4539 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4541 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4543 if (type
& MSR_TYPE_R
&&
4544 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4546 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4548 if (type
& MSR_TYPE_W
&&
4549 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4551 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4556 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4559 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4560 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4561 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4562 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4565 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4567 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4569 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4573 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4575 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4577 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4581 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4583 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4585 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4589 static bool vmx_get_enable_apicv(void)
4591 return enable_apicv
;
4594 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4596 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4601 if (vmx
->nested
.pi_desc
&&
4602 vmx
->nested
.pi_pending
) {
4603 vmx
->nested
.pi_pending
= false;
4604 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4607 max_irr
= find_last_bit(
4608 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4613 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4618 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4619 kunmap(vmx
->nested
.virtual_apic_page
);
4621 status
= vmcs_read16(GUEST_INTR_STATUS
);
4622 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4624 status
|= (u8
)max_irr
;
4625 vmcs_write16(GUEST_INTR_STATUS
, status
);
4631 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4634 if (vcpu
->mode
== IN_GUEST_MODE
) {
4635 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4638 * Currently, we don't support urgent interrupt,
4639 * all interrupts are recognized as non-urgent
4640 * interrupt, so we cannot post interrupts when
4643 * If the vcpu is in guest mode, it means it is
4644 * running instead of being scheduled out and
4645 * waiting in the run queue, and that's the only
4646 * case when 'SN' is set currently, warning if
4649 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4651 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4652 POSTED_INTR_VECTOR
);
4659 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4664 if (is_guest_mode(vcpu
) &&
4665 vector
== vmx
->nested
.posted_intr_nv
) {
4666 /* the PIR and ON have been set by L1. */
4667 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4669 * If a posted intr is not recognized by hardware,
4670 * we will accomplish it in the next vmentry.
4672 vmx
->nested
.pi_pending
= true;
4673 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4679 * Send interrupt to vcpu via posted interrupt way.
4680 * 1. If target vcpu is running(non-root mode), send posted interrupt
4681 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4682 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4683 * interrupt from PIR in next vmentry.
4685 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4687 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4690 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4694 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4697 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4698 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4699 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4700 kvm_vcpu_kick(vcpu
);
4703 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4707 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4710 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4714 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4715 * will not change in the lifetime of the guest.
4716 * Note that host-state that does change is set elsewhere. E.g., host-state
4717 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4719 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4726 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4727 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4729 /* Save the most likely value for this task's CR4 in the VMCS. */
4730 cr4
= cr4_read_shadow();
4731 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4732 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4734 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4735 #ifdef CONFIG_X86_64
4737 * Load null selectors, so we can avoid reloading them in
4738 * __vmx_load_host_state(), in case userspace uses the null selectors
4739 * too (the expected case).
4741 vmcs_write16(HOST_DS_SELECTOR
, 0);
4742 vmcs_write16(HOST_ES_SELECTOR
, 0);
4744 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4745 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4747 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4748 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4750 native_store_idt(&dt
);
4751 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4752 vmx
->host_idt_base
= dt
.address
;
4754 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4756 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4757 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4758 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4759 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4761 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4762 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4763 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4767 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4769 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4771 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4772 if (is_guest_mode(&vmx
->vcpu
))
4773 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4774 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4775 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4778 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4780 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4782 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4783 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4784 return pin_based_exec_ctrl
;
4787 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4789 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4791 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4792 if (cpu_has_secondary_exec_ctrls()) {
4793 if (kvm_vcpu_apicv_active(vcpu
))
4794 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
4795 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4796 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4798 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
4799 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4800 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4803 if (cpu_has_vmx_msr_bitmap())
4804 vmx_set_msr_bitmap(vcpu
);
4807 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4809 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4811 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4812 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4814 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4815 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4816 #ifdef CONFIG_X86_64
4817 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4818 CPU_BASED_CR8_LOAD_EXITING
;
4822 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4823 CPU_BASED_CR3_LOAD_EXITING
|
4824 CPU_BASED_INVLPG_EXITING
;
4825 return exec_control
;
4828 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4830 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4831 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4832 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4834 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4836 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4837 enable_unrestricted_guest
= 0;
4838 /* Enable INVPCID for non-ept guests may cause performance regression. */
4839 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4841 if (!enable_unrestricted_guest
)
4842 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4844 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4845 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4846 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4847 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4848 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4849 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4851 We can NOT enable shadow_vmcs here because we don't have yet
4854 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4857 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4859 return exec_control
;
4862 static void ept_set_mmio_spte_mask(void)
4865 * EPT Misconfigurations can be generated if the value of bits 2:0
4866 * of an EPT paging-structure entry is 110b (write/execute).
4867 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4870 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4873 #define VMX_XSS_EXIT_BITMAP 0
4875 * Sets up the vmcs for emulated real mode.
4877 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4879 #ifdef CONFIG_X86_64
4885 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4886 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4888 if (enable_shadow_vmcs
) {
4889 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4890 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4892 if (cpu_has_vmx_msr_bitmap())
4893 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4895 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4898 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4900 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4902 if (cpu_has_secondary_exec_ctrls()) {
4903 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4904 vmx_secondary_exec_control(vmx
));
4907 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
4908 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4909 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4910 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4911 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4913 vmcs_write16(GUEST_INTR_STATUS
, 0);
4915 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4916 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4920 vmcs_write32(PLE_GAP
, ple_gap
);
4921 vmx
->ple_window
= ple_window
;
4922 vmx
->ple_window_dirty
= true;
4925 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4926 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4927 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4929 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4930 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4931 vmx_set_constant_host_state(vmx
);
4932 #ifdef CONFIG_X86_64
4933 rdmsrl(MSR_FS_BASE
, a
);
4934 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4935 rdmsrl(MSR_GS_BASE
, a
);
4936 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4938 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4939 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4942 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4943 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4944 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4945 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4946 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4948 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4949 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4951 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4952 u32 index
= vmx_msr_index
[i
];
4953 u32 data_low
, data_high
;
4956 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4958 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4960 vmx
->guest_msrs
[j
].index
= i
;
4961 vmx
->guest_msrs
[j
].data
= 0;
4962 vmx
->guest_msrs
[j
].mask
= -1ull;
4967 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4969 /* 22.2.1, 20.8.1 */
4970 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4972 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4973 set_cr4_guest_host_mask(vmx
);
4975 if (vmx_xsaves_supported())
4976 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4981 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4983 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4984 struct msr_data apic_base_msr
;
4987 vmx
->rmode
.vm86_active
= 0;
4989 vmx
->soft_vnmi_blocked
= 0;
4991 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4992 kvm_set_cr8(vcpu
, 0);
4995 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4996 MSR_IA32_APICBASE_ENABLE
;
4997 if (kvm_vcpu_is_reset_bsp(vcpu
))
4998 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4999 apic_base_msr
.host_initiated
= true;
5000 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5003 vmx_segment_cache_clear(vmx
);
5005 seg_setup(VCPU_SREG_CS
);
5006 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5007 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5009 seg_setup(VCPU_SREG_DS
);
5010 seg_setup(VCPU_SREG_ES
);
5011 seg_setup(VCPU_SREG_FS
);
5012 seg_setup(VCPU_SREG_GS
);
5013 seg_setup(VCPU_SREG_SS
);
5015 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5016 vmcs_writel(GUEST_TR_BASE
, 0);
5017 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5018 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5020 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5021 vmcs_writel(GUEST_LDTR_BASE
, 0);
5022 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5023 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5026 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5027 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5028 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5029 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5032 vmcs_writel(GUEST_RFLAGS
, 0x02);
5033 kvm_rip_write(vcpu
, 0xfff0);
5035 vmcs_writel(GUEST_GDTR_BASE
, 0);
5036 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5038 vmcs_writel(GUEST_IDTR_BASE
, 0);
5039 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5041 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5042 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5043 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5047 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5049 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5050 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5051 if (cpu_need_tpr_shadow(vcpu
))
5052 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5053 __pa(vcpu
->arch
.apic
->regs
));
5054 vmcs_write32(TPR_THRESHOLD
, 0);
5057 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5059 if (kvm_vcpu_apicv_active(vcpu
))
5060 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5063 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5065 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5066 vmx
->vcpu
.arch
.cr0
= cr0
;
5067 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5068 vmx_set_cr4(vcpu
, 0);
5069 vmx_set_efer(vcpu
, 0);
5070 vmx_fpu_activate(vcpu
);
5071 update_exception_bitmap(vcpu
);
5073 vpid_sync_context(vmx
->vpid
);
5077 * In nested virtualization, check if L1 asked to exit on external interrupts.
5078 * For most existing hypervisors, this will always return true.
5080 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5082 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5083 PIN_BASED_EXT_INTR_MASK
;
5087 * In nested virtualization, check if L1 has set
5088 * VM_EXIT_ACK_INTR_ON_EXIT
5090 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5092 return get_vmcs12(vcpu
)->vm_exit_controls
&
5093 VM_EXIT_ACK_INTR_ON_EXIT
;
5096 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5098 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5099 PIN_BASED_NMI_EXITING
;
5102 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5104 u32 cpu_based_vm_exec_control
;
5106 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5107 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5108 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5111 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5113 u32 cpu_based_vm_exec_control
;
5115 if (!cpu_has_virtual_nmis() ||
5116 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5117 enable_irq_window(vcpu
);
5121 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5122 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5123 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5126 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5130 int irq
= vcpu
->arch
.interrupt
.nr
;
5132 trace_kvm_inj_virq(irq
);
5134 ++vcpu
->stat
.irq_injections
;
5135 if (vmx
->rmode
.vm86_active
) {
5137 if (vcpu
->arch
.interrupt
.soft
)
5138 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5139 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5140 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5143 intr
= irq
| INTR_INFO_VALID_MASK
;
5144 if (vcpu
->arch
.interrupt
.soft
) {
5145 intr
|= INTR_TYPE_SOFT_INTR
;
5146 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5147 vmx
->vcpu
.arch
.event_exit_inst_len
);
5149 intr
|= INTR_TYPE_EXT_INTR
;
5150 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5153 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5155 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5157 if (is_guest_mode(vcpu
))
5160 if (!cpu_has_virtual_nmis()) {
5162 * Tracking the NMI-blocked state in software is built upon
5163 * finding the next open IRQ window. This, in turn, depends on
5164 * well-behaving guests: They have to keep IRQs disabled at
5165 * least as long as the NMI handler runs. Otherwise we may
5166 * cause NMI nesting, maybe breaking the guest. But as this is
5167 * highly unlikely, we can live with the residual risk.
5169 vmx
->soft_vnmi_blocked
= 1;
5170 vmx
->vnmi_blocked_time
= 0;
5173 ++vcpu
->stat
.nmi_injections
;
5174 vmx
->nmi_known_unmasked
= false;
5175 if (vmx
->rmode
.vm86_active
) {
5176 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5177 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5180 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5181 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5184 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5186 if (!cpu_has_virtual_nmis())
5187 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5188 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5190 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5193 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5195 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5197 if (!cpu_has_virtual_nmis()) {
5198 if (vmx
->soft_vnmi_blocked
!= masked
) {
5199 vmx
->soft_vnmi_blocked
= masked
;
5200 vmx
->vnmi_blocked_time
= 0;
5203 vmx
->nmi_known_unmasked
= !masked
;
5205 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5206 GUEST_INTR_STATE_NMI
);
5208 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5209 GUEST_INTR_STATE_NMI
);
5213 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5215 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5218 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5221 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5222 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5223 | GUEST_INTR_STATE_NMI
));
5226 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5228 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5229 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5230 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5231 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5234 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5238 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5242 kvm
->arch
.tss_addr
= addr
;
5243 return init_rmode_tss(kvm
);
5246 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5251 * Update instruction length as we may reinject the exception
5252 * from user space while in guest debugging mode.
5254 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5255 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5256 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5260 if (vcpu
->guest_debug
&
5261 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5278 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5279 int vec
, u32 err_code
)
5282 * Instruction with address size override prefix opcode 0x67
5283 * Cause the #SS fault with 0 error code in VM86 mode.
5285 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5286 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5287 if (vcpu
->arch
.halt_request
) {
5288 vcpu
->arch
.halt_request
= 0;
5289 return kvm_vcpu_halt(vcpu
);
5297 * Forward all other exceptions that are valid in real mode.
5298 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5299 * the required debugging infrastructure rework.
5301 kvm_queue_exception(vcpu
, vec
);
5306 * Trigger machine check on the host. We assume all the MSRs are already set up
5307 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5308 * We pass a fake environment to the machine check handler because we want
5309 * the guest to be always treated like user space, no matter what context
5310 * it used internally.
5312 static void kvm_machine_check(void)
5314 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5315 struct pt_regs regs
= {
5316 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5317 .flags
= X86_EFLAGS_IF
,
5320 do_machine_check(®s
, 0);
5324 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5326 /* already handled by vcpu_run */
5330 static int handle_exception(struct kvm_vcpu
*vcpu
)
5332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5333 struct kvm_run
*kvm_run
= vcpu
->run
;
5334 u32 intr_info
, ex_no
, error_code
;
5335 unsigned long cr2
, rip
, dr6
;
5337 enum emulation_result er
;
5339 vect_info
= vmx
->idt_vectoring_info
;
5340 intr_info
= vmx
->exit_intr_info
;
5342 if (is_machine_check(intr_info
))
5343 return handle_machine_check(vcpu
);
5345 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5346 return 1; /* already handled by vmx_vcpu_run() */
5348 if (is_no_device(intr_info
)) {
5349 vmx_fpu_activate(vcpu
);
5353 if (is_invalid_opcode(intr_info
)) {
5354 if (is_guest_mode(vcpu
)) {
5355 kvm_queue_exception(vcpu
, UD_VECTOR
);
5358 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5359 if (er
!= EMULATE_DONE
)
5360 kvm_queue_exception(vcpu
, UD_VECTOR
);
5365 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5366 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5369 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5370 * MMIO, it is better to report an internal error.
5371 * See the comments in vmx_handle_exit.
5373 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5374 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5375 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5376 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5377 vcpu
->run
->internal
.ndata
= 3;
5378 vcpu
->run
->internal
.data
[0] = vect_info
;
5379 vcpu
->run
->internal
.data
[1] = intr_info
;
5380 vcpu
->run
->internal
.data
[2] = error_code
;
5384 if (is_page_fault(intr_info
)) {
5385 /* EPT won't cause page fault directly */
5387 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5388 trace_kvm_page_fault(cr2
, error_code
);
5390 if (kvm_event_needs_reinjection(vcpu
))
5391 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5392 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5395 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5397 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5398 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5402 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5405 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5406 if (!(vcpu
->guest_debug
&
5407 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5408 vcpu
->arch
.dr6
&= ~15;
5409 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5410 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5411 skip_emulated_instruction(vcpu
);
5413 kvm_queue_exception(vcpu
, DB_VECTOR
);
5416 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5417 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5421 * Update instruction length as we may reinject #BP from
5422 * user space while in guest debugging mode. Reading it for
5423 * #DB as well causes no harm, it is not used in that case.
5425 vmx
->vcpu
.arch
.event_exit_inst_len
=
5426 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5427 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5428 rip
= kvm_rip_read(vcpu
);
5429 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5430 kvm_run
->debug
.arch
.exception
= ex_no
;
5433 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5434 kvm_run
->ex
.exception
= ex_no
;
5435 kvm_run
->ex
.error_code
= error_code
;
5441 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5443 ++vcpu
->stat
.irq_exits
;
5447 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5449 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5453 static int handle_io(struct kvm_vcpu
*vcpu
)
5455 unsigned long exit_qualification
;
5456 int size
, in
, string
;
5459 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5460 string
= (exit_qualification
& 16) != 0;
5461 in
= (exit_qualification
& 8) != 0;
5463 ++vcpu
->stat
.io_exits
;
5466 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5468 port
= exit_qualification
>> 16;
5469 size
= (exit_qualification
& 7) + 1;
5470 skip_emulated_instruction(vcpu
);
5472 return kvm_fast_pio_out(vcpu
, size
, port
);
5476 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5479 * Patch in the VMCALL instruction:
5481 hypercall
[0] = 0x0f;
5482 hypercall
[1] = 0x01;
5483 hypercall
[2] = 0xc1;
5486 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5488 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5489 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5491 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5492 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5493 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5494 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5495 return (val
& always_on
) == always_on
;
5498 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5499 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5501 if (is_guest_mode(vcpu
)) {
5502 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5503 unsigned long orig_val
= val
;
5506 * We get here when L2 changed cr0 in a way that did not change
5507 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5508 * but did change L0 shadowed bits. So we first calculate the
5509 * effective cr0 value that L1 would like to write into the
5510 * hardware. It consists of the L2-owned bits from the new
5511 * value combined with the L1-owned bits from L1's guest_cr0.
5513 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5514 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5516 if (!nested_cr0_valid(vcpu
, val
))
5519 if (kvm_set_cr0(vcpu
, val
))
5521 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5524 if (to_vmx(vcpu
)->nested
.vmxon
&&
5525 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5527 return kvm_set_cr0(vcpu
, val
);
5531 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5533 if (is_guest_mode(vcpu
)) {
5534 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5535 unsigned long orig_val
= val
;
5537 /* analogously to handle_set_cr0 */
5538 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5539 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5540 if (kvm_set_cr4(vcpu
, val
))
5542 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5545 return kvm_set_cr4(vcpu
, val
);
5548 /* called to set cr0 as appropriate for clts instruction exit. */
5549 static void handle_clts(struct kvm_vcpu
*vcpu
)
5551 if (is_guest_mode(vcpu
)) {
5553 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5554 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5555 * just pretend it's off (also in arch.cr0 for fpu_activate).
5557 vmcs_writel(CR0_READ_SHADOW
,
5558 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5559 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5561 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5564 static int handle_cr(struct kvm_vcpu
*vcpu
)
5566 unsigned long exit_qualification
, val
;
5571 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5572 cr
= exit_qualification
& 15;
5573 reg
= (exit_qualification
>> 8) & 15;
5574 switch ((exit_qualification
>> 4) & 3) {
5575 case 0: /* mov to cr */
5576 val
= kvm_register_readl(vcpu
, reg
);
5577 trace_kvm_cr_write(cr
, val
);
5580 err
= handle_set_cr0(vcpu
, val
);
5581 kvm_complete_insn_gp(vcpu
, err
);
5584 err
= kvm_set_cr3(vcpu
, val
);
5585 kvm_complete_insn_gp(vcpu
, err
);
5588 err
= handle_set_cr4(vcpu
, val
);
5589 kvm_complete_insn_gp(vcpu
, err
);
5592 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5594 err
= kvm_set_cr8(vcpu
, cr8
);
5595 kvm_complete_insn_gp(vcpu
, err
);
5596 if (lapic_in_kernel(vcpu
))
5598 if (cr8_prev
<= cr8
)
5600 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5607 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5608 skip_emulated_instruction(vcpu
);
5609 vmx_fpu_activate(vcpu
);
5611 case 1: /*mov from cr*/
5614 val
= kvm_read_cr3(vcpu
);
5615 kvm_register_write(vcpu
, reg
, val
);
5616 trace_kvm_cr_read(cr
, val
);
5617 skip_emulated_instruction(vcpu
);
5620 val
= kvm_get_cr8(vcpu
);
5621 kvm_register_write(vcpu
, reg
, val
);
5622 trace_kvm_cr_read(cr
, val
);
5623 skip_emulated_instruction(vcpu
);
5628 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5629 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5630 kvm_lmsw(vcpu
, val
);
5632 skip_emulated_instruction(vcpu
);
5637 vcpu
->run
->exit_reason
= 0;
5638 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5639 (int)(exit_qualification
>> 4) & 3, cr
);
5643 static int handle_dr(struct kvm_vcpu
*vcpu
)
5645 unsigned long exit_qualification
;
5648 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5649 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5651 /* First, if DR does not exist, trigger UD */
5652 if (!kvm_require_dr(vcpu
, dr
))
5655 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5656 if (!kvm_require_cpl(vcpu
, 0))
5658 dr7
= vmcs_readl(GUEST_DR7
);
5661 * As the vm-exit takes precedence over the debug trap, we
5662 * need to emulate the latter, either for the host or the
5663 * guest debugging itself.
5665 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5666 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5667 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5668 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5669 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5670 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5673 vcpu
->arch
.dr6
&= ~15;
5674 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5675 kvm_queue_exception(vcpu
, DB_VECTOR
);
5680 if (vcpu
->guest_debug
== 0) {
5681 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
5682 CPU_BASED_MOV_DR_EXITING
);
5685 * No more DR vmexits; force a reload of the debug registers
5686 * and reenter on this instruction. The next vmexit will
5687 * retrieve the full state of the debug registers.
5689 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5693 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5694 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5697 if (kvm_get_dr(vcpu
, dr
, &val
))
5699 kvm_register_write(vcpu
, reg
, val
);
5701 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5704 skip_emulated_instruction(vcpu
);
5708 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5710 return vcpu
->arch
.dr6
;
5713 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5717 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5719 get_debugreg(vcpu
->arch
.db
[0], 0);
5720 get_debugreg(vcpu
->arch
.db
[1], 1);
5721 get_debugreg(vcpu
->arch
.db
[2], 2);
5722 get_debugreg(vcpu
->arch
.db
[3], 3);
5723 get_debugreg(vcpu
->arch
.dr6
, 6);
5724 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5726 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5727 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
5730 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5732 vmcs_writel(GUEST_DR7
, val
);
5735 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5737 kvm_emulate_cpuid(vcpu
);
5741 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5743 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5744 struct msr_data msr_info
;
5746 msr_info
.index
= ecx
;
5747 msr_info
.host_initiated
= false;
5748 if (vmx_get_msr(vcpu
, &msr_info
)) {
5749 trace_kvm_msr_read_ex(ecx
);
5750 kvm_inject_gp(vcpu
, 0);
5754 trace_kvm_msr_read(ecx
, msr_info
.data
);
5756 /* FIXME: handling of bits 32:63 of rax, rdx */
5757 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5758 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5759 skip_emulated_instruction(vcpu
);
5763 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5765 struct msr_data msr
;
5766 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5767 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5768 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5772 msr
.host_initiated
= false;
5773 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5774 trace_kvm_msr_write_ex(ecx
, data
);
5775 kvm_inject_gp(vcpu
, 0);
5779 trace_kvm_msr_write(ecx
, data
);
5780 skip_emulated_instruction(vcpu
);
5784 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5786 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5790 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5792 u32 cpu_based_vm_exec_control
;
5794 /* clear pending irq */
5795 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5796 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5797 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5799 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5801 ++vcpu
->stat
.irq_window_exits
;
5805 static int handle_halt(struct kvm_vcpu
*vcpu
)
5807 return kvm_emulate_halt(vcpu
);
5810 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5812 return kvm_emulate_hypercall(vcpu
);
5815 static int handle_invd(struct kvm_vcpu
*vcpu
)
5817 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5820 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5822 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5824 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5825 skip_emulated_instruction(vcpu
);
5829 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5833 err
= kvm_rdpmc(vcpu
);
5834 kvm_complete_insn_gp(vcpu
, err
);
5839 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5841 kvm_emulate_wbinvd(vcpu
);
5845 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5847 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5848 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5850 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5851 skip_emulated_instruction(vcpu
);
5855 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5857 skip_emulated_instruction(vcpu
);
5858 WARN(1, "this should never happen\n");
5862 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5864 skip_emulated_instruction(vcpu
);
5865 WARN(1, "this should never happen\n");
5869 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5871 if (likely(fasteoi
)) {
5872 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5873 int access_type
, offset
;
5875 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5876 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5878 * Sane guest uses MOV to write EOI, with written value
5879 * not cared. So make a short-circuit here by avoiding
5880 * heavy instruction emulation.
5882 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5883 (offset
== APIC_EOI
)) {
5884 kvm_lapic_set_eoi(vcpu
);
5885 skip_emulated_instruction(vcpu
);
5889 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5892 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5894 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5895 int vector
= exit_qualification
& 0xff;
5897 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5898 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5902 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5904 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5905 u32 offset
= exit_qualification
& 0xfff;
5907 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5908 kvm_apic_write_nodecode(vcpu
, offset
);
5912 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5914 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5915 unsigned long exit_qualification
;
5916 bool has_error_code
= false;
5919 int reason
, type
, idt_v
, idt_index
;
5921 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5922 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5923 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5925 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5927 reason
= (u32
)exit_qualification
>> 30;
5928 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5930 case INTR_TYPE_NMI_INTR
:
5931 vcpu
->arch
.nmi_injected
= false;
5932 vmx_set_nmi_mask(vcpu
, true);
5934 case INTR_TYPE_EXT_INTR
:
5935 case INTR_TYPE_SOFT_INTR
:
5936 kvm_clear_interrupt_queue(vcpu
);
5938 case INTR_TYPE_HARD_EXCEPTION
:
5939 if (vmx
->idt_vectoring_info
&
5940 VECTORING_INFO_DELIVER_CODE_MASK
) {
5941 has_error_code
= true;
5943 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5946 case INTR_TYPE_SOFT_EXCEPTION
:
5947 kvm_clear_exception_queue(vcpu
);
5953 tss_selector
= exit_qualification
;
5955 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5956 type
!= INTR_TYPE_EXT_INTR
&&
5957 type
!= INTR_TYPE_NMI_INTR
))
5958 skip_emulated_instruction(vcpu
);
5960 if (kvm_task_switch(vcpu
, tss_selector
,
5961 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5962 has_error_code
, error_code
) == EMULATE_FAIL
) {
5963 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5964 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5965 vcpu
->run
->internal
.ndata
= 0;
5970 * TODO: What about debug traps on tss switch?
5971 * Are we supposed to inject them and update dr6?
5977 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5979 unsigned long exit_qualification
;
5984 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5986 gla_validity
= (exit_qualification
>> 7) & 0x3;
5987 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5988 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5989 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5990 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5991 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5992 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5993 (long unsigned int)exit_qualification
);
5994 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5995 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
6000 * EPT violation happened while executing iret from NMI,
6001 * "blocked by NMI" bit has to be set before next VM entry.
6002 * There are errata that may cause this bit to not be set:
6005 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6006 cpu_has_virtual_nmis() &&
6007 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6008 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6010 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6011 trace_kvm_page_fault(gpa
, exit_qualification
);
6013 /* It is a write fault? */
6014 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
6015 /* It is a fetch fault? */
6016 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
6017 /* ept page table is present? */
6018 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
6020 vcpu
->arch
.exit_qualification
= exit_qualification
;
6022 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6025 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6030 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6031 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6032 skip_emulated_instruction(vcpu
);
6033 trace_kvm_fast_mmio(gpa
);
6037 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6038 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6039 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6042 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6043 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6045 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6048 /* It is the real ept misconfig */
6051 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6052 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6057 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6059 u32 cpu_based_vm_exec_control
;
6061 /* clear pending NMI */
6062 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6063 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6064 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6065 ++vcpu
->stat
.nmi_window_exits
;
6066 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6071 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6073 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6074 enum emulation_result err
= EMULATE_DONE
;
6077 bool intr_window_requested
;
6078 unsigned count
= 130;
6080 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6081 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6083 while (vmx
->emulation_required
&& count
-- != 0) {
6084 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6085 return handle_interrupt_window(&vmx
->vcpu
);
6087 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6090 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6092 if (err
== EMULATE_USER_EXIT
) {
6093 ++vcpu
->stat
.mmio_exits
;
6098 if (err
!= EMULATE_DONE
) {
6099 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6100 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6101 vcpu
->run
->internal
.ndata
= 0;
6105 if (vcpu
->arch
.halt_request
) {
6106 vcpu
->arch
.halt_request
= 0;
6107 ret
= kvm_vcpu_halt(vcpu
);
6111 if (signal_pending(current
))
6121 static int __grow_ple_window(int val
)
6123 if (ple_window_grow
< 1)
6126 val
= min(val
, ple_window_actual_max
);
6128 if (ple_window_grow
< ple_window
)
6129 val
*= ple_window_grow
;
6131 val
+= ple_window_grow
;
6136 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6141 if (modifier
< ple_window
)
6146 return max(val
, minimum
);
6149 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6151 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6152 int old
= vmx
->ple_window
;
6154 vmx
->ple_window
= __grow_ple_window(old
);
6156 if (vmx
->ple_window
!= old
)
6157 vmx
->ple_window_dirty
= true;
6159 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6162 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6165 int old
= vmx
->ple_window
;
6167 vmx
->ple_window
= __shrink_ple_window(old
,
6168 ple_window_shrink
, ple_window
);
6170 if (vmx
->ple_window
!= old
)
6171 vmx
->ple_window_dirty
= true;
6173 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6177 * ple_window_actual_max is computed to be one grow_ple_window() below
6178 * ple_window_max. (See __grow_ple_window for the reason.)
6179 * This prevents overflows, because ple_window_max is int.
6180 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6182 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6184 static void update_ple_window_actual_max(void)
6186 ple_window_actual_max
=
6187 __shrink_ple_window(max(ple_window_max
, ple_window
),
6188 ple_window_grow
, INT_MIN
);
6192 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6194 static void wakeup_handler(void)
6196 struct kvm_vcpu
*vcpu
;
6197 int cpu
= smp_processor_id();
6199 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6200 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6201 blocked_vcpu_list
) {
6202 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6204 if (pi_test_on(pi_desc
) == 1)
6205 kvm_vcpu_kick(vcpu
);
6207 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6210 static __init
int hardware_setup(void)
6212 int r
= -ENOMEM
, i
, msr
;
6214 rdmsrl_safe(MSR_EFER
, &host_efer
);
6216 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6217 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6219 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6220 if (!vmx_io_bitmap_a
)
6223 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6224 if (!vmx_io_bitmap_b
)
6227 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6228 if (!vmx_msr_bitmap_legacy
)
6231 vmx_msr_bitmap_legacy_x2apic
=
6232 (unsigned long *)__get_free_page(GFP_KERNEL
);
6233 if (!vmx_msr_bitmap_legacy_x2apic
)
6236 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6237 if (!vmx_msr_bitmap_longmode
)
6240 vmx_msr_bitmap_longmode_x2apic
=
6241 (unsigned long *)__get_free_page(GFP_KERNEL
);
6242 if (!vmx_msr_bitmap_longmode_x2apic
)
6246 vmx_msr_bitmap_nested
=
6247 (unsigned long *)__get_free_page(GFP_KERNEL
);
6248 if (!vmx_msr_bitmap_nested
)
6252 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6253 if (!vmx_vmread_bitmap
)
6256 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6257 if (!vmx_vmwrite_bitmap
)
6260 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6261 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6264 * Allow direct access to the PC debug port (it is often used for I/O
6265 * delays, but the vmexits simply slow things down).
6267 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6268 clear_bit(0x80, vmx_io_bitmap_a
);
6270 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6272 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6273 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6275 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6277 if (setup_vmcs_config(&vmcs_config
) < 0) {
6282 if (boot_cpu_has(X86_FEATURE_NX
))
6283 kvm_enable_efer_bits(EFER_NX
);
6285 if (!cpu_has_vmx_vpid())
6287 if (!cpu_has_vmx_shadow_vmcs())
6288 enable_shadow_vmcs
= 0;
6289 if (enable_shadow_vmcs
)
6290 init_vmcs_shadow_fields();
6292 if (!cpu_has_vmx_ept() ||
6293 !cpu_has_vmx_ept_4levels()) {
6295 enable_unrestricted_guest
= 0;
6296 enable_ept_ad_bits
= 0;
6299 if (!cpu_has_vmx_ept_ad_bits())
6300 enable_ept_ad_bits
= 0;
6302 if (!cpu_has_vmx_unrestricted_guest())
6303 enable_unrestricted_guest
= 0;
6305 if (!cpu_has_vmx_flexpriority())
6306 flexpriority_enabled
= 0;
6309 * set_apic_access_page_addr() is used to reload apic access
6310 * page upon invalidation. No need to do anything if not
6311 * using the APIC_ACCESS_ADDR VMCS field.
6313 if (!flexpriority_enabled
)
6314 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6316 if (!cpu_has_vmx_tpr_shadow())
6317 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6319 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6320 kvm_disable_largepages();
6322 if (!cpu_has_vmx_ple())
6325 if (!cpu_has_vmx_apicv())
6328 if (cpu_has_vmx_tsc_scaling()) {
6329 kvm_has_tsc_control
= true;
6330 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6331 kvm_tsc_scaling_ratio_frac_bits
= 48;
6334 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6335 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6336 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6337 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6338 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6339 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6340 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6342 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6343 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6344 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6345 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6347 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6349 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6350 vmx_disable_intercept_msr_read_x2apic(msr
);
6352 /* According SDM, in x2apic mode, the whole id reg is used. But in
6353 * KVM, it only use the highest eight bits. Need to intercept it */
6354 vmx_enable_intercept_msr_read_x2apic(0x802);
6356 vmx_enable_intercept_msr_read_x2apic(0x839);
6358 vmx_disable_intercept_msr_write_x2apic(0x808);
6360 vmx_disable_intercept_msr_write_x2apic(0x80b);
6362 vmx_disable_intercept_msr_write_x2apic(0x83f);
6365 kvm_mmu_set_mask_ptes(0ull,
6366 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6367 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6368 0ull, VMX_EPT_EXECUTABLE_MASK
);
6369 ept_set_mmio_spte_mask();
6374 update_ple_window_actual_max();
6377 * Only enable PML when hardware supports PML feature, and both EPT
6378 * and EPT A/D bit features are enabled -- PML depends on them to work.
6380 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6384 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6385 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6386 kvm_x86_ops
->flush_log_dirty
= NULL
;
6387 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6390 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6392 return alloc_kvm_area();
6395 free_page((unsigned long)vmx_vmwrite_bitmap
);
6397 free_page((unsigned long)vmx_vmread_bitmap
);
6400 free_page((unsigned long)vmx_msr_bitmap_nested
);
6402 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6404 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6406 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6408 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6410 free_page((unsigned long)vmx_io_bitmap_b
);
6412 free_page((unsigned long)vmx_io_bitmap_a
);
6417 static __exit
void hardware_unsetup(void)
6419 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6420 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6421 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6422 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6423 free_page((unsigned long)vmx_io_bitmap_b
);
6424 free_page((unsigned long)vmx_io_bitmap_a
);
6425 free_page((unsigned long)vmx_vmwrite_bitmap
);
6426 free_page((unsigned long)vmx_vmread_bitmap
);
6428 free_page((unsigned long)vmx_msr_bitmap_nested
);
6434 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6435 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6437 static int handle_pause(struct kvm_vcpu
*vcpu
)
6440 grow_ple_window(vcpu
);
6442 skip_emulated_instruction(vcpu
);
6443 kvm_vcpu_on_spin(vcpu
);
6448 static int handle_nop(struct kvm_vcpu
*vcpu
)
6450 skip_emulated_instruction(vcpu
);
6454 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6456 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6457 return handle_nop(vcpu
);
6460 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6465 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6467 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6468 return handle_nop(vcpu
);
6472 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6473 * We could reuse a single VMCS for all the L2 guests, but we also want the
6474 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6475 * allows keeping them loaded on the processor, and in the future will allow
6476 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6477 * every entry if they never change.
6478 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6479 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6481 * The following functions allocate and free a vmcs02 in this pool.
6484 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6485 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6487 struct vmcs02_list
*item
;
6488 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6489 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6490 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6491 return &item
->vmcs02
;
6494 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6495 /* Recycle the least recently used VMCS. */
6496 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6497 struct vmcs02_list
, list
);
6498 item
->vmptr
= vmx
->nested
.current_vmptr
;
6499 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6500 return &item
->vmcs02
;
6503 /* Create a new VMCS */
6504 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6507 item
->vmcs02
.vmcs
= alloc_vmcs();
6508 if (!item
->vmcs02
.vmcs
) {
6512 loaded_vmcs_init(&item
->vmcs02
);
6513 item
->vmptr
= vmx
->nested
.current_vmptr
;
6514 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6515 vmx
->nested
.vmcs02_num
++;
6516 return &item
->vmcs02
;
6519 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6520 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6522 struct vmcs02_list
*item
;
6523 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6524 if (item
->vmptr
== vmptr
) {
6525 free_loaded_vmcs(&item
->vmcs02
);
6526 list_del(&item
->list
);
6528 vmx
->nested
.vmcs02_num
--;
6534 * Free all VMCSs saved for this vcpu, except the one pointed by
6535 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6536 * must be &vmx->vmcs01.
6538 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6540 struct vmcs02_list
*item
, *n
;
6542 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6543 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6545 * Something will leak if the above WARN triggers. Better than
6548 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6551 free_loaded_vmcs(&item
->vmcs02
);
6552 list_del(&item
->list
);
6554 vmx
->nested
.vmcs02_num
--;
6559 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6560 * set the success or error code of an emulated VMX instruction, as specified
6561 * by Vol 2B, VMX Instruction Reference, "Conventions".
6563 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6565 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6566 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6567 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6570 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6572 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6573 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6574 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6578 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6579 u32 vm_instruction_error
)
6581 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6583 * failValid writes the error number to the current VMCS, which
6584 * can't be done there isn't a current VMCS.
6586 nested_vmx_failInvalid(vcpu
);
6589 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6590 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6591 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6593 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6595 * We don't need to force a shadow sync because
6596 * VM_INSTRUCTION_ERROR is not shadowed
6600 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6602 /* TODO: not to reset guest simply here. */
6603 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6604 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6607 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6609 struct vcpu_vmx
*vmx
=
6610 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6612 vmx
->nested
.preemption_timer_expired
= true;
6613 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6614 kvm_vcpu_kick(&vmx
->vcpu
);
6616 return HRTIMER_NORESTART
;
6620 * Decode the memory-address operand of a vmx instruction, as recorded on an
6621 * exit caused by such an instruction (run by a guest hypervisor).
6622 * On success, returns 0. When the operand is invalid, returns 1 and throws
6625 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6626 unsigned long exit_qualification
,
6627 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6631 struct kvm_segment s
;
6634 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6635 * Execution", on an exit, vmx_instruction_info holds most of the
6636 * addressing components of the operand. Only the displacement part
6637 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6638 * For how an actual address is calculated from all these components,
6639 * refer to Vol. 1, "Operand Addressing".
6641 int scaling
= vmx_instruction_info
& 3;
6642 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6643 bool is_reg
= vmx_instruction_info
& (1u << 10);
6644 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6645 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6646 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6647 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6648 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6651 kvm_queue_exception(vcpu
, UD_VECTOR
);
6655 /* Addr = segment_base + offset */
6656 /* offset = base + [index * scale] + displacement */
6657 off
= exit_qualification
; /* holds the displacement */
6659 off
+= kvm_register_read(vcpu
, base_reg
);
6661 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6662 vmx_get_segment(vcpu
, &s
, seg_reg
);
6663 *ret
= s
.base
+ off
;
6665 if (addr_size
== 1) /* 32 bit */
6668 /* Checks for #GP/#SS exceptions. */
6670 if (is_long_mode(vcpu
)) {
6671 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6672 * non-canonical form. This is the only check on the memory
6673 * destination for long mode!
6675 exn
= is_noncanonical_address(*ret
);
6676 } else if (is_protmode(vcpu
)) {
6677 /* Protected mode: apply checks for segment validity in the
6679 * - segment type check (#GP(0) may be thrown)
6680 * - usability check (#GP(0)/#SS(0))
6681 * - limit check (#GP(0)/#SS(0))
6684 /* #GP(0) if the destination operand is located in a
6685 * read-only data segment or any code segment.
6687 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6689 /* #GP(0) if the source operand is located in an
6690 * execute-only code segment
6692 exn
= ((s
.type
& 0xa) == 8);
6694 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6697 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6699 exn
= (s
.unusable
!= 0);
6700 /* Protected mode: #GP(0)/#SS(0) if the memory
6701 * operand is outside the segment limit.
6703 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6706 kvm_queue_exception_e(vcpu
,
6707 seg_reg
== VCPU_SREG_SS
?
6708 SS_VECTOR
: GP_VECTOR
,
6717 * This function performs the various checks including
6718 * - if it's 4KB aligned
6719 * - No bits beyond the physical address width are set
6720 * - Returns 0 on success or else 1
6721 * (Intel SDM Section 30.3)
6723 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6728 struct x86_exception e
;
6730 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6731 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6733 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6734 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6737 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6738 sizeof(vmptr
), &e
)) {
6739 kvm_inject_page_fault(vcpu
, &e
);
6743 switch (exit_reason
) {
6744 case EXIT_REASON_VMON
:
6747 * The first 4 bytes of VMXON region contain the supported
6748 * VMCS revision identifier
6750 * Note - IA32_VMX_BASIC[48] will never be 1
6751 * for the nested case;
6752 * which replaces physical address width with 32
6755 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6756 nested_vmx_failInvalid(vcpu
);
6757 skip_emulated_instruction(vcpu
);
6761 page
= nested_get_page(vcpu
, vmptr
);
6763 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6764 nested_vmx_failInvalid(vcpu
);
6766 skip_emulated_instruction(vcpu
);
6770 vmx
->nested
.vmxon_ptr
= vmptr
;
6772 case EXIT_REASON_VMCLEAR
:
6773 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6774 nested_vmx_failValid(vcpu
,
6775 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6776 skip_emulated_instruction(vcpu
);
6780 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6781 nested_vmx_failValid(vcpu
,
6782 VMXERR_VMCLEAR_VMXON_POINTER
);
6783 skip_emulated_instruction(vcpu
);
6787 case EXIT_REASON_VMPTRLD
:
6788 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6789 nested_vmx_failValid(vcpu
,
6790 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6791 skip_emulated_instruction(vcpu
);
6795 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6796 nested_vmx_failValid(vcpu
,
6797 VMXERR_VMCLEAR_VMXON_POINTER
);
6798 skip_emulated_instruction(vcpu
);
6803 return 1; /* shouldn't happen */
6812 * Emulate the VMXON instruction.
6813 * Currently, we just remember that VMX is active, and do not save or even
6814 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6815 * do not currently need to store anything in that guest-allocated memory
6816 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6817 * argument is different from the VMXON pointer (which the spec says they do).
6819 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6821 struct kvm_segment cs
;
6822 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6823 struct vmcs
*shadow_vmcs
;
6824 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6825 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6827 /* The Intel VMX Instruction Reference lists a bunch of bits that
6828 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6829 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6830 * Otherwise, we should fail with #UD. We test these now:
6832 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6833 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6834 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6835 kvm_queue_exception(vcpu
, UD_VECTOR
);
6839 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6840 if (is_long_mode(vcpu
) && !cs
.l
) {
6841 kvm_queue_exception(vcpu
, UD_VECTOR
);
6845 if (vmx_get_cpl(vcpu
)) {
6846 kvm_inject_gp(vcpu
, 0);
6850 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6853 if (vmx
->nested
.vmxon
) {
6854 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6855 skip_emulated_instruction(vcpu
);
6859 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6860 != VMXON_NEEDED_FEATURES
) {
6861 kvm_inject_gp(vcpu
, 0);
6865 if (enable_shadow_vmcs
) {
6866 shadow_vmcs
= alloc_vmcs();
6869 /* mark vmcs as shadow */
6870 shadow_vmcs
->revision_id
|= (1u << 31);
6871 /* init shadow vmcs */
6872 vmcs_clear(shadow_vmcs
);
6873 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6876 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6877 vmx
->nested
.vmcs02_num
= 0;
6879 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6881 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6883 vmx
->nested
.vmxon
= true;
6885 skip_emulated_instruction(vcpu
);
6886 nested_vmx_succeed(vcpu
);
6891 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6892 * for running VMX instructions (except VMXON, whose prerequisites are
6893 * slightly different). It also specifies what exception to inject otherwise.
6895 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6897 struct kvm_segment cs
;
6898 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6900 if (!vmx
->nested
.vmxon
) {
6901 kvm_queue_exception(vcpu
, UD_VECTOR
);
6905 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6906 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6907 (is_long_mode(vcpu
) && !cs
.l
)) {
6908 kvm_queue_exception(vcpu
, UD_VECTOR
);
6912 if (vmx_get_cpl(vcpu
)) {
6913 kvm_inject_gp(vcpu
, 0);
6920 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6922 if (vmx
->nested
.current_vmptr
== -1ull)
6925 /* current_vmptr and current_vmcs12 are always set/reset together */
6926 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6929 if (enable_shadow_vmcs
) {
6930 /* copy to memory all shadowed fields in case
6931 they were modified */
6932 copy_shadow_to_vmcs12(vmx
);
6933 vmx
->nested
.sync_shadow_vmcs
= false;
6934 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6935 SECONDARY_EXEC_SHADOW_VMCS
);
6936 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6938 vmx
->nested
.posted_intr_nv
= -1;
6939 kunmap(vmx
->nested
.current_vmcs12_page
);
6940 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6941 vmx
->nested
.current_vmptr
= -1ull;
6942 vmx
->nested
.current_vmcs12
= NULL
;
6946 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6947 * just stops using VMX.
6949 static void free_nested(struct vcpu_vmx
*vmx
)
6951 if (!vmx
->nested
.vmxon
)
6954 vmx
->nested
.vmxon
= false;
6955 free_vpid(vmx
->nested
.vpid02
);
6956 nested_release_vmcs12(vmx
);
6957 if (enable_shadow_vmcs
)
6958 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6959 /* Unpin physical memory we referred to in current vmcs02 */
6960 if (vmx
->nested
.apic_access_page
) {
6961 nested_release_page(vmx
->nested
.apic_access_page
);
6962 vmx
->nested
.apic_access_page
= NULL
;
6964 if (vmx
->nested
.virtual_apic_page
) {
6965 nested_release_page(vmx
->nested
.virtual_apic_page
);
6966 vmx
->nested
.virtual_apic_page
= NULL
;
6968 if (vmx
->nested
.pi_desc_page
) {
6969 kunmap(vmx
->nested
.pi_desc_page
);
6970 nested_release_page(vmx
->nested
.pi_desc_page
);
6971 vmx
->nested
.pi_desc_page
= NULL
;
6972 vmx
->nested
.pi_desc
= NULL
;
6975 nested_free_all_saved_vmcss(vmx
);
6978 /* Emulate the VMXOFF instruction */
6979 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6981 if (!nested_vmx_check_permission(vcpu
))
6983 free_nested(to_vmx(vcpu
));
6984 skip_emulated_instruction(vcpu
);
6985 nested_vmx_succeed(vcpu
);
6989 /* Emulate the VMCLEAR instruction */
6990 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6992 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6994 struct vmcs12
*vmcs12
;
6997 if (!nested_vmx_check_permission(vcpu
))
7000 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
7003 if (vmptr
== vmx
->nested
.current_vmptr
)
7004 nested_release_vmcs12(vmx
);
7006 page
= nested_get_page(vcpu
, vmptr
);
7009 * For accurate processor emulation, VMCLEAR beyond available
7010 * physical memory should do nothing at all. However, it is
7011 * possible that a nested vmx bug, not a guest hypervisor bug,
7012 * resulted in this case, so let's shut down before doing any
7015 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7018 vmcs12
= kmap(page
);
7019 vmcs12
->launch_state
= 0;
7021 nested_release_page(page
);
7023 nested_free_vmcs02(vmx
, vmptr
);
7025 skip_emulated_instruction(vcpu
);
7026 nested_vmx_succeed(vcpu
);
7030 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7032 /* Emulate the VMLAUNCH instruction */
7033 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7035 return nested_vmx_run(vcpu
, true);
7038 /* Emulate the VMRESUME instruction */
7039 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7042 return nested_vmx_run(vcpu
, false);
7045 enum vmcs_field_type
{
7046 VMCS_FIELD_TYPE_U16
= 0,
7047 VMCS_FIELD_TYPE_U64
= 1,
7048 VMCS_FIELD_TYPE_U32
= 2,
7049 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7052 static inline int vmcs_field_type(unsigned long field
)
7054 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7055 return VMCS_FIELD_TYPE_U32
;
7056 return (field
>> 13) & 0x3 ;
7059 static inline int vmcs_field_readonly(unsigned long field
)
7061 return (((field
>> 10) & 0x3) == 1);
7065 * Read a vmcs12 field. Since these can have varying lengths and we return
7066 * one type, we chose the biggest type (u64) and zero-extend the return value
7067 * to that size. Note that the caller, handle_vmread, might need to use only
7068 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7069 * 64-bit fields are to be returned).
7071 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7072 unsigned long field
, u64
*ret
)
7074 short offset
= vmcs_field_to_offset(field
);
7080 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7082 switch (vmcs_field_type(field
)) {
7083 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7084 *ret
= *((natural_width
*)p
);
7086 case VMCS_FIELD_TYPE_U16
:
7089 case VMCS_FIELD_TYPE_U32
:
7092 case VMCS_FIELD_TYPE_U64
:
7102 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7103 unsigned long field
, u64 field_value
){
7104 short offset
= vmcs_field_to_offset(field
);
7105 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7109 switch (vmcs_field_type(field
)) {
7110 case VMCS_FIELD_TYPE_U16
:
7111 *(u16
*)p
= field_value
;
7113 case VMCS_FIELD_TYPE_U32
:
7114 *(u32
*)p
= field_value
;
7116 case VMCS_FIELD_TYPE_U64
:
7117 *(u64
*)p
= field_value
;
7119 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7120 *(natural_width
*)p
= field_value
;
7129 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7132 unsigned long field
;
7134 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7135 const unsigned long *fields
= shadow_read_write_fields
;
7136 const int num_fields
= max_shadow_read_write_fields
;
7140 vmcs_load(shadow_vmcs
);
7142 for (i
= 0; i
< num_fields
; i
++) {
7144 switch (vmcs_field_type(field
)) {
7145 case VMCS_FIELD_TYPE_U16
:
7146 field_value
= vmcs_read16(field
);
7148 case VMCS_FIELD_TYPE_U32
:
7149 field_value
= vmcs_read32(field
);
7151 case VMCS_FIELD_TYPE_U64
:
7152 field_value
= vmcs_read64(field
);
7154 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7155 field_value
= vmcs_readl(field
);
7161 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7164 vmcs_clear(shadow_vmcs
);
7165 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7170 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7172 const unsigned long *fields
[] = {
7173 shadow_read_write_fields
,
7174 shadow_read_only_fields
7176 const int max_fields
[] = {
7177 max_shadow_read_write_fields
,
7178 max_shadow_read_only_fields
7181 unsigned long field
;
7182 u64 field_value
= 0;
7183 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7185 vmcs_load(shadow_vmcs
);
7187 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7188 for (i
= 0; i
< max_fields
[q
]; i
++) {
7189 field
= fields
[q
][i
];
7190 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7192 switch (vmcs_field_type(field
)) {
7193 case VMCS_FIELD_TYPE_U16
:
7194 vmcs_write16(field
, (u16
)field_value
);
7196 case VMCS_FIELD_TYPE_U32
:
7197 vmcs_write32(field
, (u32
)field_value
);
7199 case VMCS_FIELD_TYPE_U64
:
7200 vmcs_write64(field
, (u64
)field_value
);
7202 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7203 vmcs_writel(field
, (long)field_value
);
7212 vmcs_clear(shadow_vmcs
);
7213 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7217 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7218 * used before) all generate the same failure when it is missing.
7220 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7222 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7223 if (vmx
->nested
.current_vmptr
== -1ull) {
7224 nested_vmx_failInvalid(vcpu
);
7225 skip_emulated_instruction(vcpu
);
7231 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7233 unsigned long field
;
7235 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7236 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7239 if (!nested_vmx_check_permission(vcpu
) ||
7240 !nested_vmx_check_vmcs12(vcpu
))
7243 /* Decode instruction info and find the field to read */
7244 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7245 /* Read the field, zero-extended to a u64 field_value */
7246 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7247 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7248 skip_emulated_instruction(vcpu
);
7252 * Now copy part of this value to register or memory, as requested.
7253 * Note that the number of bits actually copied is 32 or 64 depending
7254 * on the guest's mode (32 or 64 bit), not on the given field's length.
7256 if (vmx_instruction_info
& (1u << 10)) {
7257 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7260 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7261 vmx_instruction_info
, true, &gva
))
7263 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7264 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7265 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7268 nested_vmx_succeed(vcpu
);
7269 skip_emulated_instruction(vcpu
);
7274 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7276 unsigned long field
;
7278 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7279 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7280 /* The value to write might be 32 or 64 bits, depending on L1's long
7281 * mode, and eventually we need to write that into a field of several
7282 * possible lengths. The code below first zero-extends the value to 64
7283 * bit (field_value), and then copies only the appropriate number of
7284 * bits into the vmcs12 field.
7286 u64 field_value
= 0;
7287 struct x86_exception e
;
7289 if (!nested_vmx_check_permission(vcpu
) ||
7290 !nested_vmx_check_vmcs12(vcpu
))
7293 if (vmx_instruction_info
& (1u << 10))
7294 field_value
= kvm_register_readl(vcpu
,
7295 (((vmx_instruction_info
) >> 3) & 0xf));
7297 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7298 vmx_instruction_info
, false, &gva
))
7300 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7301 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7302 kvm_inject_page_fault(vcpu
, &e
);
7308 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7309 if (vmcs_field_readonly(field
)) {
7310 nested_vmx_failValid(vcpu
,
7311 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7312 skip_emulated_instruction(vcpu
);
7316 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7317 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7318 skip_emulated_instruction(vcpu
);
7322 nested_vmx_succeed(vcpu
);
7323 skip_emulated_instruction(vcpu
);
7327 /* Emulate the VMPTRLD instruction */
7328 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7330 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7333 if (!nested_vmx_check_permission(vcpu
))
7336 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7339 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7340 struct vmcs12
*new_vmcs12
;
7342 page
= nested_get_page(vcpu
, vmptr
);
7344 nested_vmx_failInvalid(vcpu
);
7345 skip_emulated_instruction(vcpu
);
7348 new_vmcs12
= kmap(page
);
7349 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7351 nested_release_page_clean(page
);
7352 nested_vmx_failValid(vcpu
,
7353 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7354 skip_emulated_instruction(vcpu
);
7358 nested_release_vmcs12(vmx
);
7359 vmx
->nested
.current_vmptr
= vmptr
;
7360 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7361 vmx
->nested
.current_vmcs12_page
= page
;
7362 if (enable_shadow_vmcs
) {
7363 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7364 SECONDARY_EXEC_SHADOW_VMCS
);
7365 vmcs_write64(VMCS_LINK_POINTER
,
7366 __pa(vmx
->nested
.current_shadow_vmcs
));
7367 vmx
->nested
.sync_shadow_vmcs
= true;
7371 nested_vmx_succeed(vcpu
);
7372 skip_emulated_instruction(vcpu
);
7376 /* Emulate the VMPTRST instruction */
7377 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7379 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7380 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7382 struct x86_exception e
;
7384 if (!nested_vmx_check_permission(vcpu
))
7387 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7388 vmx_instruction_info
, true, &vmcs_gva
))
7390 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7391 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7392 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7394 kvm_inject_page_fault(vcpu
, &e
);
7397 nested_vmx_succeed(vcpu
);
7398 skip_emulated_instruction(vcpu
);
7402 /* Emulate the INVEPT instruction */
7403 static int handle_invept(struct kvm_vcpu
*vcpu
)
7405 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7406 u32 vmx_instruction_info
, types
;
7409 struct x86_exception e
;
7414 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7415 SECONDARY_EXEC_ENABLE_EPT
) ||
7416 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7417 kvm_queue_exception(vcpu
, UD_VECTOR
);
7421 if (!nested_vmx_check_permission(vcpu
))
7424 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7425 kvm_queue_exception(vcpu
, UD_VECTOR
);
7429 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7430 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7432 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7434 if (!(types
& (1UL << type
))) {
7435 nested_vmx_failValid(vcpu
,
7436 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7437 skip_emulated_instruction(vcpu
);
7441 /* According to the Intel VMX instruction reference, the memory
7442 * operand is read even if it isn't needed (e.g., for type==global)
7444 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7445 vmx_instruction_info
, false, &gva
))
7447 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7448 sizeof(operand
), &e
)) {
7449 kvm_inject_page_fault(vcpu
, &e
);
7454 case VMX_EPT_EXTENT_GLOBAL
:
7455 kvm_mmu_sync_roots(vcpu
);
7456 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7457 nested_vmx_succeed(vcpu
);
7460 /* Trap single context invalidation invept calls */
7465 skip_emulated_instruction(vcpu
);
7469 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7471 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7472 u32 vmx_instruction_info
;
7473 unsigned long type
, types
;
7475 struct x86_exception e
;
7478 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7479 SECONDARY_EXEC_ENABLE_VPID
) ||
7480 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7481 kvm_queue_exception(vcpu
, UD_VECTOR
);
7485 if (!nested_vmx_check_permission(vcpu
))
7488 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7489 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7491 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7493 if (!(types
& (1UL << type
))) {
7494 nested_vmx_failValid(vcpu
,
7495 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7496 skip_emulated_instruction(vcpu
);
7500 /* according to the intel vmx instruction reference, the memory
7501 * operand is read even if it isn't needed (e.g., for type==global)
7503 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7504 vmx_instruction_info
, false, &gva
))
7506 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7508 kvm_inject_page_fault(vcpu
, &e
);
7513 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7515 * Old versions of KVM use the single-context version so we
7516 * have to support it; just treat it the same as all-context.
7518 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7519 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7520 nested_vmx_succeed(vcpu
);
7523 /* Trap individual address invalidation invvpid calls */
7528 skip_emulated_instruction(vcpu
);
7532 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7534 unsigned long exit_qualification
;
7536 trace_kvm_pml_full(vcpu
->vcpu_id
);
7538 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7541 * PML buffer FULL happened while executing iret from NMI,
7542 * "blocked by NMI" bit has to be set before next VM entry.
7544 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7545 cpu_has_virtual_nmis() &&
7546 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7547 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7548 GUEST_INTR_STATE_NMI
);
7551 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7552 * here.., and there's no userspace involvement needed for PML.
7558 * The exit handlers return 1 if the exit was handled fully and guest execution
7559 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7560 * to be done to userspace and return 0.
7562 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7563 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7564 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7565 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7566 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7567 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7568 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7569 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7570 [EXIT_REASON_CPUID
] = handle_cpuid
,
7571 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7572 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7573 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7574 [EXIT_REASON_HLT
] = handle_halt
,
7575 [EXIT_REASON_INVD
] = handle_invd
,
7576 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7577 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7578 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7579 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7580 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7581 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7582 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7583 [EXIT_REASON_VMREAD
] = handle_vmread
,
7584 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7585 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7586 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7587 [EXIT_REASON_VMON
] = handle_vmon
,
7588 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7589 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7590 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7591 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7592 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7593 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7594 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7595 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7596 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7597 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7598 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7599 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7600 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7601 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7602 [EXIT_REASON_INVEPT
] = handle_invept
,
7603 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7604 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7605 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7606 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7609 static const int kvm_vmx_max_exit_handlers
=
7610 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7612 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7613 struct vmcs12
*vmcs12
)
7615 unsigned long exit_qualification
;
7616 gpa_t bitmap
, last_bitmap
;
7621 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7622 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7624 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7626 port
= exit_qualification
>> 16;
7627 size
= (exit_qualification
& 7) + 1;
7629 last_bitmap
= (gpa_t
)-1;
7634 bitmap
= vmcs12
->io_bitmap_a
;
7635 else if (port
< 0x10000)
7636 bitmap
= vmcs12
->io_bitmap_b
;
7639 bitmap
+= (port
& 0x7fff) / 8;
7641 if (last_bitmap
!= bitmap
)
7642 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7644 if (b
& (1 << (port
& 7)))
7649 last_bitmap
= bitmap
;
7656 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7657 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7658 * disinterest in the current event (read or write a specific MSR) by using an
7659 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7661 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7662 struct vmcs12
*vmcs12
, u32 exit_reason
)
7664 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7667 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7671 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7672 * for the four combinations of read/write and low/high MSR numbers.
7673 * First we need to figure out which of the four to use:
7675 bitmap
= vmcs12
->msr_bitmap
;
7676 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7678 if (msr_index
>= 0xc0000000) {
7679 msr_index
-= 0xc0000000;
7683 /* Then read the msr_index'th bit from this bitmap: */
7684 if (msr_index
< 1024*8) {
7686 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7688 return 1 & (b
>> (msr_index
& 7));
7690 return true; /* let L1 handle the wrong parameter */
7694 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7695 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7696 * intercept (via guest_host_mask etc.) the current event.
7698 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7699 struct vmcs12
*vmcs12
)
7701 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7702 int cr
= exit_qualification
& 15;
7703 int reg
= (exit_qualification
>> 8) & 15;
7704 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7706 switch ((exit_qualification
>> 4) & 3) {
7707 case 0: /* mov to cr */
7710 if (vmcs12
->cr0_guest_host_mask
&
7711 (val
^ vmcs12
->cr0_read_shadow
))
7715 if ((vmcs12
->cr3_target_count
>= 1 &&
7716 vmcs12
->cr3_target_value0
== val
) ||
7717 (vmcs12
->cr3_target_count
>= 2 &&
7718 vmcs12
->cr3_target_value1
== val
) ||
7719 (vmcs12
->cr3_target_count
>= 3 &&
7720 vmcs12
->cr3_target_value2
== val
) ||
7721 (vmcs12
->cr3_target_count
>= 4 &&
7722 vmcs12
->cr3_target_value3
== val
))
7724 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7728 if (vmcs12
->cr4_guest_host_mask
&
7729 (vmcs12
->cr4_read_shadow
^ val
))
7733 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7739 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7740 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7743 case 1: /* mov from cr */
7746 if (vmcs12
->cpu_based_vm_exec_control
&
7747 CPU_BASED_CR3_STORE_EXITING
)
7751 if (vmcs12
->cpu_based_vm_exec_control
&
7752 CPU_BASED_CR8_STORE_EXITING
)
7759 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7760 * cr0. Other attempted changes are ignored, with no exit.
7762 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7763 (val
^ vmcs12
->cr0_read_shadow
))
7765 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7766 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7775 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7776 * should handle it ourselves in L0 (and then continue L2). Only call this
7777 * when in is_guest_mode (L2).
7779 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7781 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7782 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7783 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7784 u32 exit_reason
= vmx
->exit_reason
;
7786 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7787 vmcs_readl(EXIT_QUALIFICATION
),
7788 vmx
->idt_vectoring_info
,
7790 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7793 if (vmx
->nested
.nested_run_pending
)
7796 if (unlikely(vmx
->fail
)) {
7797 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7798 vmcs_read32(VM_INSTRUCTION_ERROR
));
7802 switch (exit_reason
) {
7803 case EXIT_REASON_EXCEPTION_NMI
:
7804 if (!is_exception(intr_info
))
7806 else if (is_page_fault(intr_info
))
7808 else if (is_no_device(intr_info
) &&
7809 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7811 else if (is_debug(intr_info
) &&
7813 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7815 else if (is_breakpoint(intr_info
) &&
7816 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7818 return vmcs12
->exception_bitmap
&
7819 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7820 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7822 case EXIT_REASON_TRIPLE_FAULT
:
7824 case EXIT_REASON_PENDING_INTERRUPT
:
7825 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7826 case EXIT_REASON_NMI_WINDOW
:
7827 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7828 case EXIT_REASON_TASK_SWITCH
:
7830 case EXIT_REASON_CPUID
:
7831 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7834 case EXIT_REASON_HLT
:
7835 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7836 case EXIT_REASON_INVD
:
7838 case EXIT_REASON_INVLPG
:
7839 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7840 case EXIT_REASON_RDPMC
:
7841 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7842 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7843 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7844 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7845 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7846 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7847 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7848 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7849 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7851 * VMX instructions trap unconditionally. This allows L1 to
7852 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7855 case EXIT_REASON_CR_ACCESS
:
7856 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7857 case EXIT_REASON_DR_ACCESS
:
7858 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7859 case EXIT_REASON_IO_INSTRUCTION
:
7860 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7861 case EXIT_REASON_MSR_READ
:
7862 case EXIT_REASON_MSR_WRITE
:
7863 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7864 case EXIT_REASON_INVALID_STATE
:
7866 case EXIT_REASON_MWAIT_INSTRUCTION
:
7867 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7868 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7869 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7870 case EXIT_REASON_MONITOR_INSTRUCTION
:
7871 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7872 case EXIT_REASON_PAUSE_INSTRUCTION
:
7873 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7874 nested_cpu_has2(vmcs12
,
7875 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7876 case EXIT_REASON_MCE_DURING_VMENTRY
:
7878 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7879 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7880 case EXIT_REASON_APIC_ACCESS
:
7881 return nested_cpu_has2(vmcs12
,
7882 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7883 case EXIT_REASON_APIC_WRITE
:
7884 case EXIT_REASON_EOI_INDUCED
:
7885 /* apic_write and eoi_induced should exit unconditionally. */
7887 case EXIT_REASON_EPT_VIOLATION
:
7889 * L0 always deals with the EPT violation. If nested EPT is
7890 * used, and the nested mmu code discovers that the address is
7891 * missing in the guest EPT table (EPT12), the EPT violation
7892 * will be injected with nested_ept_inject_page_fault()
7895 case EXIT_REASON_EPT_MISCONFIG
:
7897 * L2 never uses directly L1's EPT, but rather L0's own EPT
7898 * table (shadow on EPT) or a merged EPT table that L0 built
7899 * (EPT on EPT). So any problems with the structure of the
7900 * table is L0's fault.
7903 case EXIT_REASON_WBINVD
:
7904 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7905 case EXIT_REASON_XSETBV
:
7907 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7909 * This should never happen, since it is not possible to
7910 * set XSS to a non-zero value---neither in L1 nor in L2.
7911 * If if it were, XSS would have to be checked against
7912 * the XSS exit bitmap in vmcs12.
7914 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7920 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7922 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7923 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7926 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
7928 struct page
*pml_pg
;
7930 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7934 vmx
->pml_pg
= pml_pg
;
7936 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7937 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7942 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
7945 __free_page(vmx
->pml_pg
);
7950 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7952 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7956 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7958 /* Do nothing if PML buffer is empty */
7959 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7962 /* PML index always points to next available PML buffer entity */
7963 if (pml_idx
>= PML_ENTITY_NUM
)
7968 pml_buf
= page_address(vmx
->pml_pg
);
7969 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7972 gpa
= pml_buf
[pml_idx
];
7973 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7974 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7977 /* reset PML index */
7978 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7982 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7983 * Called before reporting dirty_bitmap to userspace.
7985 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7988 struct kvm_vcpu
*vcpu
;
7990 * We only need to kick vcpu out of guest mode here, as PML buffer
7991 * is flushed at beginning of all VMEXITs, and it's obvious that only
7992 * vcpus running in guest are possible to have unflushed GPAs in PML
7995 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7996 kvm_vcpu_kick(vcpu
);
7999 static void vmx_dump_sel(char *name
, uint32_t sel
)
8001 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8002 name
, vmcs_read32(sel
),
8003 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8004 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8005 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8008 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8010 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8011 name
, vmcs_read32(limit
),
8012 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8015 static void dump_vmcs(void)
8017 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8018 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8019 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8020 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8021 u32 secondary_exec_control
= 0;
8022 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8023 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8026 if (cpu_has_secondary_exec_ctrls())
8027 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8029 pr_err("*** Guest State ***\n");
8030 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8031 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8032 vmcs_readl(CR0_GUEST_HOST_MASK
));
8033 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8034 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8035 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8036 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8037 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8039 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8040 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8041 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8042 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8044 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8045 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8046 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8047 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8048 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8049 vmcs_readl(GUEST_SYSENTER_ESP
),
8050 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8051 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8052 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8053 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8054 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8055 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8056 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8057 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8058 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8059 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8060 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8061 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8062 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8063 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8064 efer
, vmcs_read64(GUEST_IA32_PAT
));
8065 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8066 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8067 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8068 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8069 pr_err("PerfGlobCtl = 0x%016llx\n",
8070 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8071 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8072 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8073 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8074 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8075 vmcs_read32(GUEST_ACTIVITY_STATE
));
8076 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8077 pr_err("InterruptStatus = %04x\n",
8078 vmcs_read16(GUEST_INTR_STATUS
));
8080 pr_err("*** Host State ***\n");
8081 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8082 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8083 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8084 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8085 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8086 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8087 vmcs_read16(HOST_TR_SELECTOR
));
8088 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8089 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8090 vmcs_readl(HOST_TR_BASE
));
8091 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8092 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8093 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8094 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8095 vmcs_readl(HOST_CR4
));
8096 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8097 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8098 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8099 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8100 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8101 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8102 vmcs_read64(HOST_IA32_EFER
),
8103 vmcs_read64(HOST_IA32_PAT
));
8104 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8105 pr_err("PerfGlobCtl = 0x%016llx\n",
8106 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8108 pr_err("*** Control State ***\n");
8109 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8110 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8111 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8112 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8113 vmcs_read32(EXCEPTION_BITMAP
),
8114 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8115 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8116 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8117 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8118 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8119 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8120 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8121 vmcs_read32(VM_EXIT_INTR_INFO
),
8122 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8123 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8124 pr_err(" reason=%08x qualification=%016lx\n",
8125 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8126 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8127 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8128 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8129 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8130 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8131 pr_err("TSC Multiplier = 0x%016llx\n",
8132 vmcs_read64(TSC_MULTIPLIER
));
8133 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8134 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8135 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8136 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8137 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8138 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8139 n
= vmcs_read32(CR3_TARGET_COUNT
);
8140 for (i
= 0; i
+ 1 < n
; i
+= 4)
8141 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8142 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8143 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8145 pr_err("CR3 target%u=%016lx\n",
8146 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8147 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8148 pr_err("PLE Gap=%08x Window=%08x\n",
8149 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8150 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8151 pr_err("Virtual processor ID = 0x%04x\n",
8152 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8156 * The guest has exited. See if we can fix it or if we need userspace
8159 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8161 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8162 u32 exit_reason
= vmx
->exit_reason
;
8163 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8165 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8168 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8169 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8170 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8171 * mode as if vcpus is in root mode, the PML buffer must has been
8175 vmx_flush_pml_buffer(vcpu
);
8177 /* If guest state is invalid, start emulating */
8178 if (vmx
->emulation_required
)
8179 return handle_invalid_guest_state(vcpu
);
8181 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8182 nested_vmx_vmexit(vcpu
, exit_reason
,
8183 vmcs_read32(VM_EXIT_INTR_INFO
),
8184 vmcs_readl(EXIT_QUALIFICATION
));
8188 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8190 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8191 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8196 if (unlikely(vmx
->fail
)) {
8197 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8198 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8199 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8205 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8206 * delivery event since it indicates guest is accessing MMIO.
8207 * The vm-exit can be triggered again after return to guest that
8208 * will cause infinite loop.
8210 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8211 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8212 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8213 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8214 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8215 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8216 vcpu
->run
->internal
.ndata
= 2;
8217 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8218 vcpu
->run
->internal
.data
[1] = exit_reason
;
8222 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8223 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8224 get_vmcs12(vcpu
))))) {
8225 if (vmx_interrupt_allowed(vcpu
)) {
8226 vmx
->soft_vnmi_blocked
= 0;
8227 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8228 vcpu
->arch
.nmi_pending
) {
8230 * This CPU don't support us in finding the end of an
8231 * NMI-blocked window if the guest runs with IRQs
8232 * disabled. So we pull the trigger after 1 s of
8233 * futile waiting, but inform the user about this.
8235 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8236 "state on VCPU %d after 1 s timeout\n",
8237 __func__
, vcpu
->vcpu_id
);
8238 vmx
->soft_vnmi_blocked
= 0;
8242 if (exit_reason
< kvm_vmx_max_exit_handlers
8243 && kvm_vmx_exit_handlers
[exit_reason
])
8244 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8246 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8247 kvm_queue_exception(vcpu
, UD_VECTOR
);
8252 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8254 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8256 if (is_guest_mode(vcpu
) &&
8257 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8260 if (irr
== -1 || tpr
< irr
) {
8261 vmcs_write32(TPR_THRESHOLD
, 0);
8265 vmcs_write32(TPR_THRESHOLD
, irr
);
8268 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8270 u32 sec_exec_control
;
8273 * There is not point to enable virtualize x2apic without enable
8276 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8277 !kvm_vcpu_apicv_active(vcpu
))
8280 if (!cpu_need_tpr_shadow(vcpu
))
8283 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8286 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8287 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8289 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8290 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8292 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8294 vmx_set_msr_bitmap(vcpu
);
8297 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8299 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8302 * Currently we do not handle the nested case where L2 has an
8303 * APIC access page of its own; that page is still pinned.
8304 * Hence, we skip the case where the VCPU is in guest mode _and_
8305 * L1 prepared an APIC access page for L2.
8307 * For the case where L1 and L2 share the same APIC access page
8308 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8309 * in the vmcs12), this function will only update either the vmcs01
8310 * or the vmcs02. If the former, the vmcs02 will be updated by
8311 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8312 * the next L2->L1 exit.
8314 if (!is_guest_mode(vcpu
) ||
8315 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8316 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8317 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8320 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8328 status
= vmcs_read16(GUEST_INTR_STATUS
);
8330 if (max_isr
!= old
) {
8332 status
|= max_isr
<< 8;
8333 vmcs_write16(GUEST_INTR_STATUS
, status
);
8337 static void vmx_set_rvi(int vector
)
8345 status
= vmcs_read16(GUEST_INTR_STATUS
);
8346 old
= (u8
)status
& 0xff;
8347 if ((u8
)vector
!= old
) {
8349 status
|= (u8
)vector
;
8350 vmcs_write16(GUEST_INTR_STATUS
, status
);
8354 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8356 if (!is_guest_mode(vcpu
)) {
8357 vmx_set_rvi(max_irr
);
8365 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8368 if (nested_exit_on_intr(vcpu
))
8372 * Else, fall back to pre-APICv interrupt injection since L2
8373 * is run without virtual interrupt delivery.
8375 if (!kvm_event_needs_reinjection(vcpu
) &&
8376 vmx_interrupt_allowed(vcpu
)) {
8377 kvm_queue_interrupt(vcpu
, max_irr
, false);
8378 vmx_inject_irq(vcpu
);
8382 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8384 if (!kvm_vcpu_apicv_active(vcpu
))
8387 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8388 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8389 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8390 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8393 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8397 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8398 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8401 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8402 exit_intr_info
= vmx
->exit_intr_info
;
8404 /* Handle machine checks before interrupts are enabled */
8405 if (is_machine_check(exit_intr_info
))
8406 kvm_machine_check();
8408 /* We need to handle NMIs before interrupts are enabled */
8409 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8410 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8411 kvm_before_handle_nmi(&vmx
->vcpu
);
8413 kvm_after_handle_nmi(&vmx
->vcpu
);
8417 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8419 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8420 register void *__sp
asm(_ASM_SP
);
8423 * If external interrupt exists, IF bit is set in rflags/eflags on the
8424 * interrupt stack frame, and interrupt will be enabled on a return
8425 * from interrupt handler.
8427 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8428 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8429 unsigned int vector
;
8430 unsigned long entry
;
8432 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8433 #ifdef CONFIG_X86_64
8437 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8438 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8439 entry
= gate_offset(*desc
);
8441 #ifdef CONFIG_X86_64
8442 "mov %%" _ASM_SP
", %[sp]\n\t"
8443 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8448 "orl $0x200, (%%" _ASM_SP
")\n\t"
8449 __ASM_SIZE(push
) " $%c[cs]\n\t"
8450 "call *%[entry]\n\t"
8452 #ifdef CONFIG_X86_64
8458 [ss
]"i"(__KERNEL_DS
),
8459 [cs
]"i"(__KERNEL_CS
)
8465 static bool vmx_has_high_real_mode_segbase(void)
8467 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8470 static bool vmx_mpx_supported(void)
8472 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8473 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8476 static bool vmx_xsaves_supported(void)
8478 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8479 SECONDARY_EXEC_XSAVES
;
8482 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8487 bool idtv_info_valid
;
8489 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8491 if (cpu_has_virtual_nmis()) {
8492 if (vmx
->nmi_known_unmasked
)
8495 * Can't use vmx->exit_intr_info since we're not sure what
8496 * the exit reason is.
8498 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8499 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8500 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8502 * SDM 3: 27.7.1.2 (September 2008)
8503 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8504 * a guest IRET fault.
8505 * SDM 3: 23.2.2 (September 2008)
8506 * Bit 12 is undefined in any of the following cases:
8507 * If the VM exit sets the valid bit in the IDT-vectoring
8508 * information field.
8509 * If the VM exit is due to a double fault.
8511 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8512 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8513 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8514 GUEST_INTR_STATE_NMI
);
8516 vmx
->nmi_known_unmasked
=
8517 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8518 & GUEST_INTR_STATE_NMI
);
8519 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8520 vmx
->vnmi_blocked_time
+=
8521 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8524 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8525 u32 idt_vectoring_info
,
8526 int instr_len_field
,
8527 int error_code_field
)
8531 bool idtv_info_valid
;
8533 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8535 vcpu
->arch
.nmi_injected
= false;
8536 kvm_clear_exception_queue(vcpu
);
8537 kvm_clear_interrupt_queue(vcpu
);
8539 if (!idtv_info_valid
)
8542 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8544 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8545 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8548 case INTR_TYPE_NMI_INTR
:
8549 vcpu
->arch
.nmi_injected
= true;
8551 * SDM 3: 27.7.1.2 (September 2008)
8552 * Clear bit "block by NMI" before VM entry if a NMI
8555 vmx_set_nmi_mask(vcpu
, false);
8557 case INTR_TYPE_SOFT_EXCEPTION
:
8558 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8560 case INTR_TYPE_HARD_EXCEPTION
:
8561 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8562 u32 err
= vmcs_read32(error_code_field
);
8563 kvm_requeue_exception_e(vcpu
, vector
, err
);
8565 kvm_requeue_exception(vcpu
, vector
);
8567 case INTR_TYPE_SOFT_INTR
:
8568 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8570 case INTR_TYPE_EXT_INTR
:
8571 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8578 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8580 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8581 VM_EXIT_INSTRUCTION_LEN
,
8582 IDT_VECTORING_ERROR_CODE
);
8585 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8587 __vmx_complete_interrupts(vcpu
,
8588 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8589 VM_ENTRY_INSTRUCTION_LEN
,
8590 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8592 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8595 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8598 struct perf_guest_switch_msr
*msrs
;
8600 msrs
= perf_guest_get_msrs(&nr_msrs
);
8605 for (i
= 0; i
< nr_msrs
; i
++)
8606 if (msrs
[i
].host
== msrs
[i
].guest
)
8607 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8609 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8613 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8615 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8616 unsigned long debugctlmsr
, cr4
;
8618 /* Record the guest's net vcpu time for enforced NMI injections. */
8619 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8620 vmx
->entry_time
= ktime_get();
8622 /* Don't enter VMX if guest state is invalid, let the exit handler
8623 start emulation until we arrive back to a valid state */
8624 if (vmx
->emulation_required
)
8627 if (vmx
->ple_window_dirty
) {
8628 vmx
->ple_window_dirty
= false;
8629 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8632 if (vmx
->nested
.sync_shadow_vmcs
) {
8633 copy_vmcs12_to_shadow(vmx
);
8634 vmx
->nested
.sync_shadow_vmcs
= false;
8637 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8638 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8639 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8640 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8642 cr4
= cr4_read_shadow();
8643 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8644 vmcs_writel(HOST_CR4
, cr4
);
8645 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8648 /* When single-stepping over STI and MOV SS, we must clear the
8649 * corresponding interruptibility bits in the guest state. Otherwise
8650 * vmentry fails as it then expects bit 14 (BS) in pending debug
8651 * exceptions being set, but that's not correct for the guest debugging
8653 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8654 vmx_set_interrupt_shadow(vcpu
, 0);
8656 if (vmx
->guest_pkru_valid
)
8657 __write_pkru(vmx
->guest_pkru
);
8659 atomic_switch_perf_msrs(vmx
);
8660 debugctlmsr
= get_debugctlmsr();
8662 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8664 /* Store host registers */
8665 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8666 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8667 "push %%" _ASM_CX
" \n\t"
8668 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8670 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8671 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8673 /* Reload cr2 if changed */
8674 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8675 "mov %%cr2, %%" _ASM_DX
" \n\t"
8676 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8678 "mov %%" _ASM_AX
", %%cr2 \n\t"
8680 /* Check if vmlaunch of vmresume is needed */
8681 "cmpl $0, %c[launched](%0) \n\t"
8682 /* Load guest registers. Don't clobber flags. */
8683 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8684 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8685 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8686 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8687 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8688 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8689 #ifdef CONFIG_X86_64
8690 "mov %c[r8](%0), %%r8 \n\t"
8691 "mov %c[r9](%0), %%r9 \n\t"
8692 "mov %c[r10](%0), %%r10 \n\t"
8693 "mov %c[r11](%0), %%r11 \n\t"
8694 "mov %c[r12](%0), %%r12 \n\t"
8695 "mov %c[r13](%0), %%r13 \n\t"
8696 "mov %c[r14](%0), %%r14 \n\t"
8697 "mov %c[r15](%0), %%r15 \n\t"
8699 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8701 /* Enter guest mode */
8703 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8705 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8707 /* Save guest registers, load host registers, keep flags */
8708 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8710 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8711 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8712 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8713 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8714 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8715 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8716 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8717 #ifdef CONFIG_X86_64
8718 "mov %%r8, %c[r8](%0) \n\t"
8719 "mov %%r9, %c[r9](%0) \n\t"
8720 "mov %%r10, %c[r10](%0) \n\t"
8721 "mov %%r11, %c[r11](%0) \n\t"
8722 "mov %%r12, %c[r12](%0) \n\t"
8723 "mov %%r13, %c[r13](%0) \n\t"
8724 "mov %%r14, %c[r14](%0) \n\t"
8725 "mov %%r15, %c[r15](%0) \n\t"
8727 "mov %%cr2, %%" _ASM_AX
" \n\t"
8728 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8730 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8731 "setbe %c[fail](%0) \n\t"
8732 ".pushsection .rodata \n\t"
8733 ".global vmx_return \n\t"
8734 "vmx_return: " _ASM_PTR
" 2b \n\t"
8736 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8737 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8738 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8739 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8740 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8741 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8742 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8743 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8744 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8745 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8746 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8747 #ifdef CONFIG_X86_64
8748 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8749 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8750 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8751 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8752 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8753 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8754 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8755 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8757 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8758 [wordsize
]"i"(sizeof(ulong
))
8760 #ifdef CONFIG_X86_64
8761 , "rax", "rbx", "rdi", "rsi"
8762 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8764 , "eax", "ebx", "edi", "esi"
8768 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8770 update_debugctlmsr(debugctlmsr
);
8772 #ifndef CONFIG_X86_64
8774 * The sysexit path does not restore ds/es, so we must set them to
8775 * a reasonable value ourselves.
8777 * We can't defer this to vmx_load_host_state() since that function
8778 * may be executed in interrupt context, which saves and restore segments
8779 * around it, nullifying its effect.
8781 loadsegment(ds
, __USER_DS
);
8782 loadsegment(es
, __USER_DS
);
8785 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8786 | (1 << VCPU_EXREG_RFLAGS
)
8787 | (1 << VCPU_EXREG_PDPTR
)
8788 | (1 << VCPU_EXREG_SEGMENTS
)
8789 | (1 << VCPU_EXREG_CR3
));
8790 vcpu
->arch
.regs_dirty
= 0;
8792 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8794 vmx
->loaded_vmcs
->launched
= 1;
8796 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8799 * eager fpu is enabled if PKEY is supported and CR4 is switched
8800 * back on host, so it is safe to read guest PKRU from current
8803 if (boot_cpu_has(X86_FEATURE_OSPKE
)) {
8804 vmx
->guest_pkru
= __read_pkru();
8805 if (vmx
->guest_pkru
!= vmx
->host_pkru
) {
8806 vmx
->guest_pkru_valid
= true;
8807 __write_pkru(vmx
->host_pkru
);
8809 vmx
->guest_pkru_valid
= false;
8813 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8814 * we did not inject a still-pending event to L1 now because of
8815 * nested_run_pending, we need to re-enable this bit.
8817 if (vmx
->nested
.nested_run_pending
)
8818 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8820 vmx
->nested
.nested_run_pending
= 0;
8822 vmx_complete_atomic_exit(vmx
);
8823 vmx_recover_nmi_blocking(vmx
);
8824 vmx_complete_interrupts(vmx
);
8827 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8829 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8832 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8836 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8838 vmx_vcpu_load(vcpu
, cpu
);
8843 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8845 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8848 vmx_destroy_pml_buffer(vmx
);
8849 free_vpid(vmx
->vpid
);
8850 leave_guest_mode(vcpu
);
8851 vmx_load_vmcs01(vcpu
);
8853 free_loaded_vmcs(vmx
->loaded_vmcs
);
8854 kfree(vmx
->guest_msrs
);
8855 kvm_vcpu_uninit(vcpu
);
8856 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8859 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8862 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8866 return ERR_PTR(-ENOMEM
);
8868 vmx
->vpid
= allocate_vpid();
8870 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8874 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8875 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8879 if (!vmx
->guest_msrs
) {
8883 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8884 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8885 if (!vmx
->loaded_vmcs
->vmcs
)
8888 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8889 loaded_vmcs_init(vmx
->loaded_vmcs
);
8894 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8895 vmx
->vcpu
.cpu
= cpu
;
8896 err
= vmx_vcpu_setup(vmx
);
8897 vmx_vcpu_put(&vmx
->vcpu
);
8901 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8902 err
= alloc_apic_access_page(kvm
);
8908 if (!kvm
->arch
.ept_identity_map_addr
)
8909 kvm
->arch
.ept_identity_map_addr
=
8910 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8911 err
= init_rmode_identity_map(kvm
);
8917 nested_vmx_setup_ctls_msrs(vmx
);
8918 vmx
->nested
.vpid02
= allocate_vpid();
8921 vmx
->nested
.posted_intr_nv
= -1;
8922 vmx
->nested
.current_vmptr
= -1ull;
8923 vmx
->nested
.current_vmcs12
= NULL
;
8926 * If PML is turned on, failure on enabling PML just results in failure
8927 * of creating the vcpu, therefore we can simplify PML logic (by
8928 * avoiding dealing with cases, such as enabling PML partially on vcpus
8929 * for the guest, etc.
8932 err
= vmx_create_pml_buffer(vmx
);
8940 free_vpid(vmx
->nested
.vpid02
);
8941 free_loaded_vmcs(vmx
->loaded_vmcs
);
8943 kfree(vmx
->guest_msrs
);
8945 kvm_vcpu_uninit(&vmx
->vcpu
);
8947 free_vpid(vmx
->vpid
);
8948 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8949 return ERR_PTR(err
);
8952 static void __init
vmx_check_processor_compat(void *rtn
)
8954 struct vmcs_config vmcs_conf
;
8957 if (setup_vmcs_config(&vmcs_conf
) < 0)
8959 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8960 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8961 smp_processor_id());
8966 static int get_ept_level(void)
8968 return VMX_EPT_DEFAULT_GAW
+ 1;
8971 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8976 /* For VT-d and EPT combination
8977 * 1. MMIO: always map as UC
8979 * a. VT-d without snooping control feature: can't guarantee the
8980 * result, try to trust guest.
8981 * b. VT-d with snooping control feature: snooping control feature of
8982 * VT-d engine can guarantee the cache correctness. Just set it
8983 * to WB to keep consistent with host. So the same as item 3.
8984 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8985 * consistent with host MTRR
8988 cache
= MTRR_TYPE_UNCACHABLE
;
8992 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8993 ipat
= VMX_EPT_IPAT_BIT
;
8994 cache
= MTRR_TYPE_WRBACK
;
8998 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8999 ipat
= VMX_EPT_IPAT_BIT
;
9000 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9001 cache
= MTRR_TYPE_WRBACK
;
9003 cache
= MTRR_TYPE_UNCACHABLE
;
9007 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9010 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9013 static int vmx_get_lpage_level(void)
9015 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9016 return PT_DIRECTORY_LEVEL
;
9018 /* For shadow and EPT supported 1GB page */
9019 return PT_PDPE_LEVEL
;
9022 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9025 * These bits in the secondary execution controls field
9026 * are dynamic, the others are mostly based on the hypervisor
9027 * architecture and the guest's CPUID. Do not touch the
9031 SECONDARY_EXEC_SHADOW_VMCS
|
9032 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9033 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9035 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9037 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9038 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9041 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9043 struct kvm_cpuid_entry2
*best
;
9044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9045 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9047 if (vmx_rdtscp_supported()) {
9048 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9049 if (!rdtscp_enabled
)
9050 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9054 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9055 SECONDARY_EXEC_RDTSCP
;
9057 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9058 ~SECONDARY_EXEC_RDTSCP
;
9062 /* Exposing INVPCID only when PCID is exposed */
9063 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9064 if (vmx_invpcid_supported() &&
9065 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9066 !guest_cpuid_has_pcid(vcpu
))) {
9067 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9070 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9073 if (cpu_has_secondary_exec_ctrls())
9074 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9077 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9079 if (func
== 1 && nested
)
9080 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9083 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9084 struct x86_exception
*fault
)
9086 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9089 if (fault
->error_code
& PFERR_RSVD_MASK
)
9090 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9092 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9093 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9094 vmcs12
->guest_physical_address
= fault
->address
;
9097 /* Callbacks for nested_ept_init_mmu_context: */
9099 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9101 /* return the page table to be shadowed - in our case, EPT12 */
9102 return get_vmcs12(vcpu
)->ept_pointer
;
9105 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9107 WARN_ON(mmu_is_nested(vcpu
));
9108 kvm_init_shadow_ept_mmu(vcpu
,
9109 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9110 VMX_EPT_EXECUTE_ONLY_BIT
);
9111 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9112 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9113 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9115 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9118 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9120 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9123 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9126 bool inequality
, bit
;
9128 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9130 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9131 vmcs12
->page_fault_error_code_match
;
9132 return inequality
^ bit
;
9135 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9136 struct x86_exception
*fault
)
9138 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9140 WARN_ON(!is_guest_mode(vcpu
));
9142 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9143 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9144 vmcs_read32(VM_EXIT_INTR_INFO
),
9145 vmcs_readl(EXIT_QUALIFICATION
));
9147 kvm_inject_page_fault(vcpu
, fault
);
9150 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9151 struct vmcs12
*vmcs12
)
9153 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9154 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9156 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9157 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9158 vmcs12
->apic_access_addr
>> maxphyaddr
)
9162 * Translate L1 physical address to host physical
9163 * address for vmcs02. Keep the page pinned, so this
9164 * physical address remains valid. We keep a reference
9165 * to it so we can release it later.
9167 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9168 nested_release_page(vmx
->nested
.apic_access_page
);
9169 vmx
->nested
.apic_access_page
=
9170 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9173 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9174 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9175 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9178 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9179 nested_release_page(vmx
->nested
.virtual_apic_page
);
9180 vmx
->nested
.virtual_apic_page
=
9181 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9184 * Failing the vm entry is _not_ what the processor does
9185 * but it's basically the only possibility we have.
9186 * We could still enter the guest if CR8 load exits are
9187 * enabled, CR8 store exits are enabled, and virtualize APIC
9188 * access is disabled; in this case the processor would never
9189 * use the TPR shadow and we could simply clear the bit from
9190 * the execution control. But such a configuration is useless,
9191 * so let's keep the code simple.
9193 if (!vmx
->nested
.virtual_apic_page
)
9197 if (nested_cpu_has_posted_intr(vmcs12
)) {
9198 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9199 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9202 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9203 kunmap(vmx
->nested
.pi_desc_page
);
9204 nested_release_page(vmx
->nested
.pi_desc_page
);
9206 vmx
->nested
.pi_desc_page
=
9207 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9208 if (!vmx
->nested
.pi_desc_page
)
9211 vmx
->nested
.pi_desc
=
9212 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9213 if (!vmx
->nested
.pi_desc
) {
9214 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9217 vmx
->nested
.pi_desc
=
9218 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9219 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9226 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9228 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9229 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9231 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9234 /* Make sure short timeouts reliably trigger an immediate vmexit.
9235 * hrtimer_start does not guarantee this. */
9236 if (preemption_timeout
<= 1) {
9237 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9241 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9242 preemption_timeout
*= 1000000;
9243 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9244 hrtimer_start(&vmx
->nested
.preemption_timer
,
9245 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9248 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9249 struct vmcs12
*vmcs12
)
9254 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9257 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9261 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9263 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9264 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9271 * Merge L0's and L1's MSR bitmap, return false to indicate that
9272 * we do not use the hardware.
9274 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9275 struct vmcs12
*vmcs12
)
9279 unsigned long *msr_bitmap
;
9281 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9284 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9289 msr_bitmap
= (unsigned long *)kmap(page
);
9291 nested_release_page_clean(page
);
9296 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9297 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9298 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9299 nested_vmx_disable_intercept_for_msr(
9301 vmx_msr_bitmap_nested
,
9303 /* TPR is allowed */
9304 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9305 vmx_msr_bitmap_nested
,
9306 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9307 MSR_TYPE_R
| MSR_TYPE_W
);
9308 if (nested_cpu_has_vid(vmcs12
)) {
9309 /* EOI and self-IPI are allowed */
9310 nested_vmx_disable_intercept_for_msr(
9312 vmx_msr_bitmap_nested
,
9313 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9315 nested_vmx_disable_intercept_for_msr(
9317 vmx_msr_bitmap_nested
,
9318 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9323 * Enable reading intercept of all the x2apic
9324 * MSRs. We should not rely on vmcs12 to do any
9325 * optimizations here, it may have been modified
9328 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9329 __vmx_enable_intercept_for_msr(
9330 vmx_msr_bitmap_nested
,
9334 __vmx_enable_intercept_for_msr(
9335 vmx_msr_bitmap_nested
,
9336 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9338 __vmx_enable_intercept_for_msr(
9339 vmx_msr_bitmap_nested
,
9340 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9342 __vmx_enable_intercept_for_msr(
9343 vmx_msr_bitmap_nested
,
9344 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9348 nested_release_page_clean(page
);
9353 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9354 struct vmcs12
*vmcs12
)
9356 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9357 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9358 !nested_cpu_has_vid(vmcs12
) &&
9359 !nested_cpu_has_posted_intr(vmcs12
))
9363 * If virtualize x2apic mode is enabled,
9364 * virtualize apic access must be disabled.
9366 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9367 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9371 * If virtual interrupt delivery is enabled,
9372 * we must exit on external interrupts.
9374 if (nested_cpu_has_vid(vmcs12
) &&
9375 !nested_exit_on_intr(vcpu
))
9379 * bits 15:8 should be zero in posted_intr_nv,
9380 * the descriptor address has been already checked
9381 * in nested_get_vmcs12_pages.
9383 if (nested_cpu_has_posted_intr(vmcs12
) &&
9384 (!nested_cpu_has_vid(vmcs12
) ||
9385 !nested_exit_intr_ack_set(vcpu
) ||
9386 vmcs12
->posted_intr_nv
& 0xff00))
9389 /* tpr shadow is needed by all apicv features. */
9390 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9396 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9397 unsigned long count_field
,
9398 unsigned long addr_field
)
9403 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9404 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9410 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9411 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9412 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9413 pr_warn_ratelimited(
9414 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9415 addr_field
, maxphyaddr
, count
, addr
);
9421 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9422 struct vmcs12
*vmcs12
)
9424 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9425 vmcs12
->vm_exit_msr_store_count
== 0 &&
9426 vmcs12
->vm_entry_msr_load_count
== 0)
9427 return 0; /* Fast path */
9428 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9429 VM_EXIT_MSR_LOAD_ADDR
) ||
9430 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9431 VM_EXIT_MSR_STORE_ADDR
) ||
9432 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9433 VM_ENTRY_MSR_LOAD_ADDR
))
9438 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9439 struct vmx_msr_entry
*e
)
9441 /* x2APIC MSR accesses are not allowed */
9442 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9444 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9445 e
->index
== MSR_IA32_UCODE_REV
)
9447 if (e
->reserved
!= 0)
9452 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9453 struct vmx_msr_entry
*e
)
9455 if (e
->index
== MSR_FS_BASE
||
9456 e
->index
== MSR_GS_BASE
||
9457 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9458 nested_vmx_msr_check_common(vcpu
, e
))
9463 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9464 struct vmx_msr_entry
*e
)
9466 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9467 nested_vmx_msr_check_common(vcpu
, e
))
9473 * Load guest's/host's msr at nested entry/exit.
9474 * return 0 for success, entry index for failure.
9476 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9479 struct vmx_msr_entry e
;
9480 struct msr_data msr
;
9482 msr
.host_initiated
= false;
9483 for (i
= 0; i
< count
; i
++) {
9484 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9486 pr_warn_ratelimited(
9487 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9488 __func__
, i
, gpa
+ i
* sizeof(e
));
9491 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9492 pr_warn_ratelimited(
9493 "%s check failed (%u, 0x%x, 0x%x)\n",
9494 __func__
, i
, e
.index
, e
.reserved
);
9497 msr
.index
= e
.index
;
9499 if (kvm_set_msr(vcpu
, &msr
)) {
9500 pr_warn_ratelimited(
9501 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9502 __func__
, i
, e
.index
, e
.value
);
9511 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9514 struct vmx_msr_entry e
;
9516 for (i
= 0; i
< count
; i
++) {
9517 struct msr_data msr_info
;
9518 if (kvm_vcpu_read_guest(vcpu
,
9519 gpa
+ i
* sizeof(e
),
9520 &e
, 2 * sizeof(u32
))) {
9521 pr_warn_ratelimited(
9522 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9523 __func__
, i
, gpa
+ i
* sizeof(e
));
9526 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9527 pr_warn_ratelimited(
9528 "%s check failed (%u, 0x%x, 0x%x)\n",
9529 __func__
, i
, e
.index
, e
.reserved
);
9532 msr_info
.host_initiated
= false;
9533 msr_info
.index
= e
.index
;
9534 if (kvm_get_msr(vcpu
, &msr_info
)) {
9535 pr_warn_ratelimited(
9536 "%s cannot read MSR (%u, 0x%x)\n",
9537 __func__
, i
, e
.index
);
9540 if (kvm_vcpu_write_guest(vcpu
,
9541 gpa
+ i
* sizeof(e
) +
9542 offsetof(struct vmx_msr_entry
, value
),
9543 &msr_info
.data
, sizeof(msr_info
.data
))) {
9544 pr_warn_ratelimited(
9545 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9546 __func__
, i
, e
.index
, msr_info
.data
);
9554 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9555 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9556 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9557 * guest in a way that will both be appropriate to L1's requests, and our
9558 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9559 * function also has additional necessary side-effects, like setting various
9560 * vcpu->arch fields.
9562 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9564 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9567 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9568 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9569 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9570 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9571 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9572 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9573 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9574 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9575 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9576 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9577 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9578 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9579 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9580 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9581 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9582 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9583 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9584 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9585 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9586 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9587 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9588 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9589 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9590 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9591 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9592 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9593 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9594 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9595 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9596 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9597 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9598 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9599 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9600 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9601 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9602 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9604 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9605 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9606 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9608 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9609 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9611 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9612 vmcs12
->vm_entry_intr_info_field
);
9613 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9614 vmcs12
->vm_entry_exception_error_code
);
9615 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9616 vmcs12
->vm_entry_instruction_len
);
9617 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9618 vmcs12
->guest_interruptibility_info
);
9619 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9620 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9621 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9622 vmcs12
->guest_pending_dbg_exceptions
);
9623 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9624 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9626 if (nested_cpu_has_xsaves(vmcs12
))
9627 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9628 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9630 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9631 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9632 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9634 if (nested_cpu_has_posted_intr(vmcs12
)) {
9636 * Note that we use L0's vector here and in
9637 * vmx_deliver_nested_posted_interrupt.
9639 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9640 vmx
->nested
.pi_pending
= false;
9641 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9642 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9643 page_to_phys(vmx
->nested
.pi_desc_page
) +
9644 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9647 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9649 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9651 vmx
->nested
.preemption_timer_expired
= false;
9652 if (nested_cpu_has_preemption_timer(vmcs12
))
9653 vmx_start_preemption_timer(vcpu
);
9656 * Whether page-faults are trapped is determined by a combination of
9657 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9658 * If enable_ept, L0 doesn't care about page faults and we should
9659 * set all of these to L1's desires. However, if !enable_ept, L0 does
9660 * care about (at least some) page faults, and because it is not easy
9661 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9662 * to exit on each and every L2 page fault. This is done by setting
9663 * MASK=MATCH=0 and (see below) EB.PF=1.
9664 * Note that below we don't need special code to set EB.PF beyond the
9665 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9666 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9667 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9669 * A problem with this approach (when !enable_ept) is that L1 may be
9670 * injected with more page faults than it asked for. This could have
9671 * caused problems, but in practice existing hypervisors don't care.
9672 * To fix this, we will need to emulate the PFEC checking (on the L1
9673 * page tables), using walk_addr(), when injecting PFs to L1.
9675 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9676 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9677 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9678 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9680 if (cpu_has_secondary_exec_ctrls()) {
9681 exec_control
= vmx_secondary_exec_control(vmx
);
9683 /* Take the following fields only from vmcs12 */
9684 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9685 SECONDARY_EXEC_RDTSCP
|
9686 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9687 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
9688 if (nested_cpu_has(vmcs12
,
9689 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9690 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9692 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9694 * If translation failed, no matter: This feature asks
9695 * to exit when accessing the given address, and if it
9696 * can never be accessed, this feature won't do
9699 if (!vmx
->nested
.apic_access_page
)
9701 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9703 vmcs_write64(APIC_ACCESS_ADDR
,
9704 page_to_phys(vmx
->nested
.apic_access_page
));
9705 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9706 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9708 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9709 kvm_vcpu_reload_apic_access_page(vcpu
);
9712 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9713 vmcs_write64(EOI_EXIT_BITMAP0
,
9714 vmcs12
->eoi_exit_bitmap0
);
9715 vmcs_write64(EOI_EXIT_BITMAP1
,
9716 vmcs12
->eoi_exit_bitmap1
);
9717 vmcs_write64(EOI_EXIT_BITMAP2
,
9718 vmcs12
->eoi_exit_bitmap2
);
9719 vmcs_write64(EOI_EXIT_BITMAP3
,
9720 vmcs12
->eoi_exit_bitmap3
);
9721 vmcs_write16(GUEST_INTR_STATUS
,
9722 vmcs12
->guest_intr_status
);
9725 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9730 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9731 * Some constant fields are set here by vmx_set_constant_host_state().
9732 * Other fields are different per CPU, and will be set later when
9733 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9735 vmx_set_constant_host_state(vmx
);
9738 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9739 * entry, but only if the current (host) sp changed from the value
9740 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9741 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9742 * here we just force the write to happen on entry.
9746 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9747 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9748 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9749 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9750 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9752 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9753 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9754 page_to_phys(vmx
->nested
.virtual_apic_page
));
9755 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9758 if (cpu_has_vmx_msr_bitmap() &&
9759 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9760 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9761 /* MSR_BITMAP will be set by following vmx_set_efer. */
9763 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9766 * Merging of IO bitmap not currently supported.
9767 * Rather, exit every time.
9769 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9770 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9772 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9774 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9775 * bitwise-or of what L1 wants to trap for L2, and what we want to
9776 * trap. Note that CR0.TS also needs updating - we do this later.
9778 update_exception_bitmap(vcpu
);
9779 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9780 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9782 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9783 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9784 * bits are further modified by vmx_set_efer() below.
9786 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9788 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9789 * emulated by vmx_set_efer(), below.
9791 vm_entry_controls_init(vmx
,
9792 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9793 ~VM_ENTRY_IA32E_MODE
) |
9794 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9796 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9797 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9798 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9799 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9800 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9803 set_cr4_guest_host_mask(vmx
);
9805 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9806 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9808 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9809 vmcs_write64(TSC_OFFSET
,
9810 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9812 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9816 * There is no direct mapping between vpid02 and vpid12, the
9817 * vpid02 is per-vCPU for L0 and reused while the value of
9818 * vpid12 is changed w/ one invvpid during nested vmentry.
9819 * The vpid12 is allocated by L1 for L2, so it will not
9820 * influence global bitmap(for vpid01 and vpid02 allocation)
9821 * even if spawn a lot of nested vCPUs.
9823 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9824 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9825 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9826 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9827 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9830 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9831 vmx_flush_tlb(vcpu
);
9836 if (nested_cpu_has_ept(vmcs12
)) {
9837 kvm_mmu_unload(vcpu
);
9838 nested_ept_init_mmu_context(vcpu
);
9841 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9842 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9843 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9844 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9846 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9847 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9848 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9851 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9852 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9853 * The CR0_READ_SHADOW is what L2 should have expected to read given
9854 * the specifications by L1; It's not enough to take
9855 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9856 * have more bits than L1 expected.
9858 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9859 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9861 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9862 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9864 /* shadow page tables on either EPT or shadow page tables */
9865 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9866 kvm_mmu_reset_context(vcpu
);
9869 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9872 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9875 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9876 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9877 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9878 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9881 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9882 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9886 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9887 * for running an L2 nested guest.
9889 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9891 struct vmcs12
*vmcs12
;
9892 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9894 struct loaded_vmcs
*vmcs02
;
9898 if (!nested_vmx_check_permission(vcpu
) ||
9899 !nested_vmx_check_vmcs12(vcpu
))
9902 skip_emulated_instruction(vcpu
);
9903 vmcs12
= get_vmcs12(vcpu
);
9905 if (enable_shadow_vmcs
)
9906 copy_shadow_to_vmcs12(vmx
);
9909 * The nested entry process starts with enforcing various prerequisites
9910 * on vmcs12 as required by the Intel SDM, and act appropriately when
9911 * they fail: As the SDM explains, some conditions should cause the
9912 * instruction to fail, while others will cause the instruction to seem
9913 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9914 * To speed up the normal (success) code path, we should avoid checking
9915 * for misconfigurations which will anyway be caught by the processor
9916 * when using the merged vmcs02.
9918 if (vmcs12
->launch_state
== launch
) {
9919 nested_vmx_failValid(vcpu
,
9920 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9921 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9925 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9926 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9927 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9931 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9932 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9936 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9937 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9941 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9942 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9946 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9947 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9951 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9952 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9953 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9954 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9955 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9956 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9957 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9958 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9959 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9960 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9961 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9962 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9963 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9964 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9965 vmx
->nested
.nested_vmx_entry_ctls_high
))
9967 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9971 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9972 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9973 nested_vmx_failValid(vcpu
,
9974 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9978 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9979 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9980 nested_vmx_entry_failure(vcpu
, vmcs12
,
9981 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9984 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9985 nested_vmx_entry_failure(vcpu
, vmcs12
,
9986 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9991 * If the load IA32_EFER VM-entry control is 1, the following checks
9992 * are performed on the field for the IA32_EFER MSR:
9993 * - Bits reserved in the IA32_EFER MSR must be 0.
9994 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9995 * the IA-32e mode guest VM-exit control. It must also be identical
9996 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9999 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
10000 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10001 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10002 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10003 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10004 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
10005 nested_vmx_entry_failure(vcpu
, vmcs12
,
10006 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10012 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10013 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10014 * the values of the LMA and LME bits in the field must each be that of
10015 * the host address-space size VM-exit control.
10017 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10018 ia32e
= (vmcs12
->vm_exit_controls
&
10019 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10020 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10021 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10022 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
10023 nested_vmx_entry_failure(vcpu
, vmcs12
,
10024 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
10030 * We're finally done with prerequisite checking, and can start with
10031 * the nested entry.
10034 vmcs02
= nested_get_current_vmcs02(vmx
);
10038 enter_guest_mode(vcpu
);
10040 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
10042 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10043 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10046 vmx
->loaded_vmcs
= vmcs02
;
10047 vmx_vcpu_put(vcpu
);
10048 vmx_vcpu_load(vcpu
, cpu
);
10052 vmx_segment_cache_clear(vmx
);
10054 prepare_vmcs02(vcpu
, vmcs12
);
10056 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10057 vmcs12
->vm_entry_msr_load_addr
,
10058 vmcs12
->vm_entry_msr_load_count
);
10059 if (msr_entry_idx
) {
10060 leave_guest_mode(vcpu
);
10061 vmx_load_vmcs01(vcpu
);
10062 nested_vmx_entry_failure(vcpu
, vmcs12
,
10063 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10067 vmcs12
->launch_state
= 1;
10069 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10070 return kvm_vcpu_halt(vcpu
);
10072 vmx
->nested
.nested_run_pending
= 1;
10075 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10076 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10077 * returned as far as L1 is concerned. It will only return (and set
10078 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10084 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10085 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10086 * This function returns the new value we should put in vmcs12.guest_cr0.
10087 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10088 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10089 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10090 * didn't trap the bit, because if L1 did, so would L0).
10091 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10092 * been modified by L2, and L1 knows it. So just leave the old value of
10093 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10094 * isn't relevant, because if L0 traps this bit it can set it to anything.
10095 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10096 * changed these bits, and therefore they need to be updated, but L0
10097 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10098 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10100 static inline unsigned long
10101 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10104 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10105 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10106 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10107 vcpu
->arch
.cr0_guest_owned_bits
));
10110 static inline unsigned long
10111 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10114 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10115 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10116 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10117 vcpu
->arch
.cr4_guest_owned_bits
));
10120 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10121 struct vmcs12
*vmcs12
)
10126 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10127 nr
= vcpu
->arch
.exception
.nr
;
10128 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10130 if (kvm_exception_is_soft(nr
)) {
10131 vmcs12
->vm_exit_instruction_len
=
10132 vcpu
->arch
.event_exit_inst_len
;
10133 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10135 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10137 if (vcpu
->arch
.exception
.has_error_code
) {
10138 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10139 vmcs12
->idt_vectoring_error_code
=
10140 vcpu
->arch
.exception
.error_code
;
10143 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10144 } else if (vcpu
->arch
.nmi_injected
) {
10145 vmcs12
->idt_vectoring_info_field
=
10146 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10147 } else if (vcpu
->arch
.interrupt
.pending
) {
10148 nr
= vcpu
->arch
.interrupt
.nr
;
10149 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10151 if (vcpu
->arch
.interrupt
.soft
) {
10152 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10153 vmcs12
->vm_entry_instruction_len
=
10154 vcpu
->arch
.event_exit_inst_len
;
10156 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10158 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10162 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10164 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10166 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10167 vmx
->nested
.preemption_timer_expired
) {
10168 if (vmx
->nested
.nested_run_pending
)
10170 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10174 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10175 if (vmx
->nested
.nested_run_pending
||
10176 vcpu
->arch
.interrupt
.pending
)
10178 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10179 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10180 INTR_INFO_VALID_MASK
, 0);
10182 * The NMI-triggered VM exit counts as injection:
10183 * clear this one and block further NMIs.
10185 vcpu
->arch
.nmi_pending
= 0;
10186 vmx_set_nmi_mask(vcpu
, true);
10190 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10191 nested_exit_on_intr(vcpu
)) {
10192 if (vmx
->nested
.nested_run_pending
)
10194 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10198 return vmx_complete_nested_posted_interrupt(vcpu
);
10201 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10203 ktime_t remaining
=
10204 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10207 if (ktime_to_ns(remaining
) <= 0)
10210 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10211 do_div(value
, 1000000);
10212 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10216 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10217 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10218 * and this function updates it to reflect the changes to the guest state while
10219 * L2 was running (and perhaps made some exits which were handled directly by L0
10220 * without going back to L1), and to reflect the exit reason.
10221 * Note that we do not have to copy here all VMCS fields, just those that
10222 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10223 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10224 * which already writes to vmcs12 directly.
10226 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10227 u32 exit_reason
, u32 exit_intr_info
,
10228 unsigned long exit_qualification
)
10230 /* update guest state fields: */
10231 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10232 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10234 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10235 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10236 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10238 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10239 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10240 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10241 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10242 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10243 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10244 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10245 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10246 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10247 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10248 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10249 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10250 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10251 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10252 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10253 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10254 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10255 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10256 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10257 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10258 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10259 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10260 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10261 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10262 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10263 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10264 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10265 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10266 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10267 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10268 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10269 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10270 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10271 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10272 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10273 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10275 vmcs12
->guest_interruptibility_info
=
10276 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10277 vmcs12
->guest_pending_dbg_exceptions
=
10278 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10279 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10280 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10282 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10284 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10285 if (vmcs12
->vm_exit_controls
&
10286 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10287 vmcs12
->vmx_preemption_timer_value
=
10288 vmx_get_preemption_timer_value(vcpu
);
10289 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10293 * In some cases (usually, nested EPT), L2 is allowed to change its
10294 * own CR3 without exiting. If it has changed it, we must keep it.
10295 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10296 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10298 * Additionally, restore L2's PDPTR to vmcs12.
10301 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10302 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10303 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10304 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10305 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10308 if (nested_cpu_has_vid(vmcs12
))
10309 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10311 vmcs12
->vm_entry_controls
=
10312 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10313 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10315 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10316 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10317 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10320 /* TODO: These cannot have changed unless we have MSR bitmaps and
10321 * the relevant bit asks not to trap the change */
10322 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10323 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10324 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10325 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10326 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10327 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10328 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10329 if (kvm_mpx_supported())
10330 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10331 if (nested_cpu_has_xsaves(vmcs12
))
10332 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10334 /* update exit information fields: */
10336 vmcs12
->vm_exit_reason
= exit_reason
;
10337 vmcs12
->exit_qualification
= exit_qualification
;
10339 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10340 if ((vmcs12
->vm_exit_intr_info
&
10341 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10342 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10343 vmcs12
->vm_exit_intr_error_code
=
10344 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10345 vmcs12
->idt_vectoring_info_field
= 0;
10346 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10347 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10349 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10350 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10351 * instead of reading the real value. */
10352 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10355 * Transfer the event that L0 or L1 may wanted to inject into
10356 * L2 to IDT_VECTORING_INFO_FIELD.
10358 vmcs12_save_pending_event(vcpu
, vmcs12
);
10362 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10363 * preserved above and would only end up incorrectly in L1.
10365 vcpu
->arch
.nmi_injected
= false;
10366 kvm_clear_exception_queue(vcpu
);
10367 kvm_clear_interrupt_queue(vcpu
);
10371 * A part of what we need to when the nested L2 guest exits and we want to
10372 * run its L1 parent, is to reset L1's guest state to the host state specified
10374 * This function is to be called not only on normal nested exit, but also on
10375 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10376 * Failures During or After Loading Guest State").
10377 * This function should be called when the active VMCS is L1's (vmcs01).
10379 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10380 struct vmcs12
*vmcs12
)
10382 struct kvm_segment seg
;
10384 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10385 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10386 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10387 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10389 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10390 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10392 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10393 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10394 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10396 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10397 * actually changed, because it depends on the current state of
10398 * fpu_active (which may have changed).
10399 * Note that vmx_set_cr0 refers to efer set above.
10401 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10403 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10404 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10405 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10407 update_exception_bitmap(vcpu
);
10408 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10409 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10412 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10413 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10415 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10416 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10418 nested_ept_uninit_mmu_context(vcpu
);
10420 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10421 kvm_mmu_reset_context(vcpu
);
10424 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10428 * Trivially support vpid by letting L2s share their parent
10429 * L1's vpid. TODO: move to a more elaborate solution, giving
10430 * each L2 its own vpid and exposing the vpid feature to L1.
10432 vmx_flush_tlb(vcpu
);
10436 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10437 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10438 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10439 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10440 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10442 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10443 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10444 vmcs_write64(GUEST_BNDCFGS
, 0);
10446 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10447 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10448 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10450 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10451 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10452 vmcs12
->host_ia32_perf_global_ctrl
);
10454 /* Set L1 segment info according to Intel SDM
10455 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10456 seg
= (struct kvm_segment
) {
10458 .limit
= 0xFFFFFFFF,
10459 .selector
= vmcs12
->host_cs_selector
,
10465 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10469 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10470 seg
= (struct kvm_segment
) {
10472 .limit
= 0xFFFFFFFF,
10479 seg
.selector
= vmcs12
->host_ds_selector
;
10480 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10481 seg
.selector
= vmcs12
->host_es_selector
;
10482 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10483 seg
.selector
= vmcs12
->host_ss_selector
;
10484 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10485 seg
.selector
= vmcs12
->host_fs_selector
;
10486 seg
.base
= vmcs12
->host_fs_base
;
10487 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10488 seg
.selector
= vmcs12
->host_gs_selector
;
10489 seg
.base
= vmcs12
->host_gs_base
;
10490 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10491 seg
= (struct kvm_segment
) {
10492 .base
= vmcs12
->host_tr_base
,
10494 .selector
= vmcs12
->host_tr_selector
,
10498 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10500 kvm_set_dr(vcpu
, 7, 0x400);
10501 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10503 if (cpu_has_vmx_msr_bitmap())
10504 vmx_set_msr_bitmap(vcpu
);
10506 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10507 vmcs12
->vm_exit_msr_load_count
))
10508 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10512 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10513 * and modify vmcs12 to make it see what it would expect to see there if
10514 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10516 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10517 u32 exit_intr_info
,
10518 unsigned long exit_qualification
)
10520 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10521 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10523 /* trying to cancel vmlaunch/vmresume is a bug */
10524 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10526 leave_guest_mode(vcpu
);
10527 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10528 exit_qualification
);
10530 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10531 vmcs12
->vm_exit_msr_store_count
))
10532 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10534 vmx_load_vmcs01(vcpu
);
10536 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10537 && nested_exit_intr_ack_set(vcpu
)) {
10538 int irq
= kvm_cpu_get_interrupt(vcpu
);
10540 vmcs12
->vm_exit_intr_info
= irq
|
10541 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10544 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10545 vmcs12
->exit_qualification
,
10546 vmcs12
->idt_vectoring_info_field
,
10547 vmcs12
->vm_exit_intr_info
,
10548 vmcs12
->vm_exit_intr_error_code
,
10551 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10552 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10553 vmx_segment_cache_clear(vmx
);
10555 /* if no vmcs02 cache requested, remove the one we used */
10556 if (VMCS02_POOL_SIZE
== 0)
10557 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10559 load_vmcs12_host_state(vcpu
, vmcs12
);
10561 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10562 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10564 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10567 /* Unpin physical memory we referred to in vmcs02 */
10568 if (vmx
->nested
.apic_access_page
) {
10569 nested_release_page(vmx
->nested
.apic_access_page
);
10570 vmx
->nested
.apic_access_page
= NULL
;
10572 if (vmx
->nested
.virtual_apic_page
) {
10573 nested_release_page(vmx
->nested
.virtual_apic_page
);
10574 vmx
->nested
.virtual_apic_page
= NULL
;
10576 if (vmx
->nested
.pi_desc_page
) {
10577 kunmap(vmx
->nested
.pi_desc_page
);
10578 nested_release_page(vmx
->nested
.pi_desc_page
);
10579 vmx
->nested
.pi_desc_page
= NULL
;
10580 vmx
->nested
.pi_desc
= NULL
;
10584 * We are now running in L2, mmu_notifier will force to reload the
10585 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10587 kvm_vcpu_reload_apic_access_page(vcpu
);
10590 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10591 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10592 * success or failure flag accordingly.
10594 if (unlikely(vmx
->fail
)) {
10596 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10598 nested_vmx_succeed(vcpu
);
10599 if (enable_shadow_vmcs
)
10600 vmx
->nested
.sync_shadow_vmcs
= true;
10602 /* in case we halted in L2 */
10603 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10607 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10609 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10611 if (is_guest_mode(vcpu
))
10612 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10613 free_nested(to_vmx(vcpu
));
10617 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10618 * 23.7 "VM-entry failures during or after loading guest state" (this also
10619 * lists the acceptable exit-reason and exit-qualification parameters).
10620 * It should only be called before L2 actually succeeded to run, and when
10621 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10623 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10624 struct vmcs12
*vmcs12
,
10625 u32 reason
, unsigned long qualification
)
10627 load_vmcs12_host_state(vcpu
, vmcs12
);
10628 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10629 vmcs12
->exit_qualification
= qualification
;
10630 nested_vmx_succeed(vcpu
);
10631 if (enable_shadow_vmcs
)
10632 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10635 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10636 struct x86_instruction_info
*info
,
10637 enum x86_intercept_stage stage
)
10639 return X86EMUL_CONTINUE
;
10642 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10645 shrink_ple_window(vcpu
);
10648 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10649 struct kvm_memory_slot
*slot
)
10651 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10652 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10655 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10656 struct kvm_memory_slot
*slot
)
10658 kvm_mmu_slot_set_dirty(kvm
, slot
);
10661 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10663 kvm_flush_pml_buffers(kvm
);
10666 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10667 struct kvm_memory_slot
*memslot
,
10668 gfn_t offset
, unsigned long mask
)
10670 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10674 * This routine does the following things for vCPU which is going
10675 * to be blocked if VT-d PI is enabled.
10676 * - Store the vCPU to the wakeup list, so when interrupts happen
10677 * we can find the right vCPU to wake up.
10678 * - Change the Posted-interrupt descriptor as below:
10679 * 'NDST' <-- vcpu->pre_pcpu
10680 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10681 * - If 'ON' is set during this process, which means at least one
10682 * interrupt is posted for this vCPU, we cannot block it, in
10683 * this case, return 1, otherwise, return 0.
10686 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10688 unsigned long flags
;
10690 struct pi_desc old
, new;
10691 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10693 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10694 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10695 !kvm_vcpu_apicv_active(vcpu
))
10698 vcpu
->pre_pcpu
= vcpu
->cpu
;
10699 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10700 vcpu
->pre_pcpu
), flags
);
10701 list_add_tail(&vcpu
->blocked_vcpu_list
,
10702 &per_cpu(blocked_vcpu_on_cpu
,
10704 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10705 vcpu
->pre_pcpu
), flags
);
10708 old
.control
= new.control
= pi_desc
->control
;
10711 * We should not block the vCPU if
10712 * an interrupt is posted for it.
10714 if (pi_test_on(pi_desc
) == 1) {
10715 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10716 vcpu
->pre_pcpu
), flags
);
10717 list_del(&vcpu
->blocked_vcpu_list
);
10718 spin_unlock_irqrestore(
10719 &per_cpu(blocked_vcpu_on_cpu_lock
,
10720 vcpu
->pre_pcpu
), flags
);
10721 vcpu
->pre_pcpu
= -1;
10726 WARN((pi_desc
->sn
== 1),
10727 "Warning: SN field of posted-interrupts "
10728 "is set before blocking\n");
10731 * Since vCPU can be preempted during this process,
10732 * vcpu->cpu could be different with pre_pcpu, we
10733 * need to set pre_pcpu as the destination of wakeup
10734 * notification event, then we can find the right vCPU
10735 * to wakeup in wakeup handler if interrupts happen
10736 * when the vCPU is in blocked state.
10738 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10740 if (x2apic_enabled())
10743 new.ndst
= (dest
<< 8) & 0xFF00;
10745 /* set 'NV' to 'wakeup vector' */
10746 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10747 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10748 new.control
) != old
.control
);
10753 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10755 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10756 struct pi_desc old
, new;
10758 unsigned long flags
;
10760 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10761 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10762 !kvm_vcpu_apicv_active(vcpu
))
10766 old
.control
= new.control
= pi_desc
->control
;
10768 dest
= cpu_physical_id(vcpu
->cpu
);
10770 if (x2apic_enabled())
10773 new.ndst
= (dest
<< 8) & 0xFF00;
10775 /* Allow posting non-urgent interrupts */
10778 /* set 'NV' to 'notification vector' */
10779 new.nv
= POSTED_INTR_VECTOR
;
10780 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10781 new.control
) != old
.control
);
10783 if(vcpu
->pre_pcpu
!= -1) {
10785 &per_cpu(blocked_vcpu_on_cpu_lock
,
10786 vcpu
->pre_pcpu
), flags
);
10787 list_del(&vcpu
->blocked_vcpu_list
);
10788 spin_unlock_irqrestore(
10789 &per_cpu(blocked_vcpu_on_cpu_lock
,
10790 vcpu
->pre_pcpu
), flags
);
10791 vcpu
->pre_pcpu
= -1;
10796 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10799 * @host_irq: host irq of the interrupt
10800 * @guest_irq: gsi of the interrupt
10801 * @set: set or unset PI
10802 * returns 0 on success, < 0 on failure
10804 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10805 uint32_t guest_irq
, bool set
)
10807 struct kvm_kernel_irq_routing_entry
*e
;
10808 struct kvm_irq_routing_table
*irq_rt
;
10809 struct kvm_lapic_irq irq
;
10810 struct kvm_vcpu
*vcpu
;
10811 struct vcpu_data vcpu_info
;
10812 int idx
, ret
= -EINVAL
;
10814 if (!kvm_arch_has_assigned_device(kvm
) ||
10815 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
10816 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
10819 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10820 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10821 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10823 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10824 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10827 * VT-d PI cannot support posting multicast/broadcast
10828 * interrupts to a vCPU, we still use interrupt remapping
10829 * for these kind of interrupts.
10831 * For lowest-priority interrupts, we only support
10832 * those with single CPU as the destination, e.g. user
10833 * configures the interrupts via /proc/irq or uses
10834 * irqbalance to make the interrupts single-CPU.
10836 * We will support full lowest-priority interrupt later.
10839 kvm_set_msi_irq(e
, &irq
);
10840 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
10842 * Make sure the IRTE is in remapped mode if
10843 * we don't handle it in posted mode.
10845 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10848 "failed to back to remapped mode, irq: %u\n",
10856 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10857 vcpu_info
.vector
= irq
.vector
;
10859 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
10860 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10863 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10865 /* suppress notification event before unposting */
10866 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10867 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10868 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10872 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10880 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10884 static struct kvm_x86_ops vmx_x86_ops
= {
10885 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10886 .disabled_by_bios
= vmx_disabled_by_bios
,
10887 .hardware_setup
= hardware_setup
,
10888 .hardware_unsetup
= hardware_unsetup
,
10889 .check_processor_compatibility
= vmx_check_processor_compat
,
10890 .hardware_enable
= hardware_enable
,
10891 .hardware_disable
= hardware_disable
,
10892 .cpu_has_accelerated_tpr
= report_flexpriority
,
10893 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10895 .vcpu_create
= vmx_create_vcpu
,
10896 .vcpu_free
= vmx_free_vcpu
,
10897 .vcpu_reset
= vmx_vcpu_reset
,
10899 .prepare_guest_switch
= vmx_save_host_state
,
10900 .vcpu_load
= vmx_vcpu_load
,
10901 .vcpu_put
= vmx_vcpu_put
,
10903 .update_bp_intercept
= update_exception_bitmap
,
10904 .get_msr
= vmx_get_msr
,
10905 .set_msr
= vmx_set_msr
,
10906 .get_segment_base
= vmx_get_segment_base
,
10907 .get_segment
= vmx_get_segment
,
10908 .set_segment
= vmx_set_segment
,
10909 .get_cpl
= vmx_get_cpl
,
10910 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10911 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10912 .decache_cr3
= vmx_decache_cr3
,
10913 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10914 .set_cr0
= vmx_set_cr0
,
10915 .set_cr3
= vmx_set_cr3
,
10916 .set_cr4
= vmx_set_cr4
,
10917 .set_efer
= vmx_set_efer
,
10918 .get_idt
= vmx_get_idt
,
10919 .set_idt
= vmx_set_idt
,
10920 .get_gdt
= vmx_get_gdt
,
10921 .set_gdt
= vmx_set_gdt
,
10922 .get_dr6
= vmx_get_dr6
,
10923 .set_dr6
= vmx_set_dr6
,
10924 .set_dr7
= vmx_set_dr7
,
10925 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10926 .cache_reg
= vmx_cache_reg
,
10927 .get_rflags
= vmx_get_rflags
,
10928 .set_rflags
= vmx_set_rflags
,
10930 .get_pkru
= vmx_get_pkru
,
10932 .fpu_activate
= vmx_fpu_activate
,
10933 .fpu_deactivate
= vmx_fpu_deactivate
,
10935 .tlb_flush
= vmx_flush_tlb
,
10937 .run
= vmx_vcpu_run
,
10938 .handle_exit
= vmx_handle_exit
,
10939 .skip_emulated_instruction
= skip_emulated_instruction
,
10940 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10941 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10942 .patch_hypercall
= vmx_patch_hypercall
,
10943 .set_irq
= vmx_inject_irq
,
10944 .set_nmi
= vmx_inject_nmi
,
10945 .queue_exception
= vmx_queue_exception
,
10946 .cancel_injection
= vmx_cancel_injection
,
10947 .interrupt_allowed
= vmx_interrupt_allowed
,
10948 .nmi_allowed
= vmx_nmi_allowed
,
10949 .get_nmi_mask
= vmx_get_nmi_mask
,
10950 .set_nmi_mask
= vmx_set_nmi_mask
,
10951 .enable_nmi_window
= enable_nmi_window
,
10952 .enable_irq_window
= enable_irq_window
,
10953 .update_cr8_intercept
= update_cr8_intercept
,
10954 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10955 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10956 .get_enable_apicv
= vmx_get_enable_apicv
,
10957 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
10958 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10959 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10960 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10961 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10962 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10964 .set_tss_addr
= vmx_set_tss_addr
,
10965 .get_tdp_level
= get_ept_level
,
10966 .get_mt_mask
= vmx_get_mt_mask
,
10968 .get_exit_info
= vmx_get_exit_info
,
10970 .get_lpage_level
= vmx_get_lpage_level
,
10972 .cpuid_update
= vmx_cpuid_update
,
10974 .rdtscp_supported
= vmx_rdtscp_supported
,
10975 .invpcid_supported
= vmx_invpcid_supported
,
10977 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10979 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10981 .read_tsc_offset
= vmx_read_tsc_offset
,
10982 .write_tsc_offset
= vmx_write_tsc_offset
,
10983 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
10984 .read_l1_tsc
= vmx_read_l1_tsc
,
10986 .set_tdp_cr3
= vmx_set_cr3
,
10988 .check_intercept
= vmx_check_intercept
,
10989 .handle_external_intr
= vmx_handle_external_intr
,
10990 .mpx_supported
= vmx_mpx_supported
,
10991 .xsaves_supported
= vmx_xsaves_supported
,
10993 .check_nested_events
= vmx_check_nested_events
,
10995 .sched_in
= vmx_sched_in
,
10997 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10998 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10999 .flush_log_dirty
= vmx_flush_log_dirty
,
11000 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11002 .pre_block
= vmx_pre_block
,
11003 .post_block
= vmx_post_block
,
11005 .pmu_ops
= &intel_pmu_ops
,
11007 .update_pi_irte
= vmx_update_pi_irte
,
11010 static int __init
vmx_init(void)
11012 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11013 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11017 #ifdef CONFIG_KEXEC_CORE
11018 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11019 crash_vmclear_local_loaded_vmcss
);
11025 static void __exit
vmx_exit(void)
11027 #ifdef CONFIG_KEXEC_CORE
11028 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11035 module_init(vmx_init
)
11036 module_exit(vmx_exit
)