2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly enable_vnmi
= 1;
74 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
76 static bool __read_mostly flexpriority_enabled
= 1;
77 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
79 static bool __read_mostly enable_ept
= 1;
80 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
82 static bool __read_mostly enable_unrestricted_guest
= 1;
83 module_param_named(unrestricted_guest
,
84 enable_unrestricted_guest
, bool, S_IRUGO
);
86 static bool __read_mostly enable_ept_ad_bits
= 1;
87 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
89 static bool __read_mostly emulate_invalid_guest_state
= true;
90 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
92 static bool __read_mostly fasteoi
= 1;
93 module_param(fasteoi
, bool, S_IRUGO
);
95 static bool __read_mostly enable_apicv
= 1;
96 module_param(enable_apicv
, bool, S_IRUGO
);
98 static bool __read_mostly enable_shadow_vmcs
= 1;
99 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
101 * If nested=1, nested virtualization is supported, i.e., guests may use
102 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
103 * use VMX instructions.
105 static bool __read_mostly nested
= 0;
106 module_param(nested
, bool, S_IRUGO
);
108 static u64 __read_mostly host_xss
;
110 static bool __read_mostly enable_pml
= 1;
111 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
113 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
115 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
116 static int __read_mostly cpu_preemption_timer_multi
;
117 static bool __read_mostly enable_preemption_timer
= 1;
119 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
122 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
123 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
124 #define KVM_VM_CR0_ALWAYS_ON \
125 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
126 #define KVM_CR4_GUEST_OWNED_BITS \
127 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
128 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
130 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
131 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
133 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
135 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
138 * Hyper-V requires all of these, so mark them as supported even though
139 * they are just treated the same as all-context.
141 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
142 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
143 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
144 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
145 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
148 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
149 * ple_gap: upper bound on the amount of time between two successive
150 * executions of PAUSE in a loop. Also indicate if ple enabled.
151 * According to test, this time is usually smaller than 128 cycles.
152 * ple_window: upper bound on the amount of time a guest is allowed to execute
153 * in a PAUSE loop. Tests indicate that most spinlocks are held for
154 * less than 2^12 cycles
155 * Time is measured based on a counter that runs at the same rate as the TSC,
156 * refer SDM volume 3b section 21.6.13 & 22.1.3.
158 #define KVM_VMX_DEFAULT_PLE_GAP 128
159 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
161 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
162 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
163 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
165 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
166 module_param(ple_gap
, int, S_IRUGO
);
168 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
169 module_param(ple_window
, int, S_IRUGO
);
171 /* Default doubles per-vcpu window every exit. */
172 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
173 module_param(ple_window_grow
, int, S_IRUGO
);
175 /* Default resets per-vcpu window every exit to ple_window. */
176 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
177 module_param(ple_window_shrink
, int, S_IRUGO
);
179 /* Default is to compute the maximum so we can never overflow. */
180 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
181 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
182 module_param(ple_window_max
, int, S_IRUGO
);
184 extern const ulong vmx_return
;
186 #define NR_AUTOLOAD_MSRS 8
187 #define VMCS02_POOL_SIZE 1
196 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
197 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
198 * loaded on this CPU (so we can clear them if the CPU goes down).
202 struct vmcs
*shadow_vmcs
;
205 bool nmi_known_unmasked
;
206 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
207 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
208 /* Support for vnmi-less CPUs */
209 int soft_vnmi_blocked
;
211 s64 vnmi_blocked_time
;
212 struct list_head loaded_vmcss_on_cpu_link
;
215 struct shared_msr_entry
{
222 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
223 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
224 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
225 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
226 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
227 * More than one of these structures may exist, if L1 runs multiple L2 guests.
228 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
229 * underlying hardware which will be used to run L2.
230 * This structure is packed to ensure that its layout is identical across
231 * machines (necessary for live migration).
232 * If there are changes in this struct, VMCS12_REVISION must be changed.
234 typedef u64 natural_width
;
235 struct __packed vmcs12
{
236 /* According to the Intel spec, a VMCS region must start with the
237 * following two fields. Then follow implementation-specific data.
242 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
243 u32 padding
[7]; /* room for future expansion */
248 u64 vm_exit_msr_store_addr
;
249 u64 vm_exit_msr_load_addr
;
250 u64 vm_entry_msr_load_addr
;
252 u64 virtual_apic_page_addr
;
253 u64 apic_access_addr
;
254 u64 posted_intr_desc_addr
;
255 u64 vm_function_control
;
257 u64 eoi_exit_bitmap0
;
258 u64 eoi_exit_bitmap1
;
259 u64 eoi_exit_bitmap2
;
260 u64 eoi_exit_bitmap3
;
261 u64 eptp_list_address
;
263 u64 guest_physical_address
;
264 u64 vmcs_link_pointer
;
266 u64 guest_ia32_debugctl
;
269 u64 guest_ia32_perf_global_ctrl
;
277 u64 host_ia32_perf_global_ctrl
;
278 u64 padding64
[8]; /* room for future expansion */
280 * To allow migration of L1 (complete with its L2 guests) between
281 * machines of different natural widths (32 or 64 bit), we cannot have
282 * unsigned long fields with no explict size. We use u64 (aliased
283 * natural_width) instead. Luckily, x86 is little-endian.
285 natural_width cr0_guest_host_mask
;
286 natural_width cr4_guest_host_mask
;
287 natural_width cr0_read_shadow
;
288 natural_width cr4_read_shadow
;
289 natural_width cr3_target_value0
;
290 natural_width cr3_target_value1
;
291 natural_width cr3_target_value2
;
292 natural_width cr3_target_value3
;
293 natural_width exit_qualification
;
294 natural_width guest_linear_address
;
295 natural_width guest_cr0
;
296 natural_width guest_cr3
;
297 natural_width guest_cr4
;
298 natural_width guest_es_base
;
299 natural_width guest_cs_base
;
300 natural_width guest_ss_base
;
301 natural_width guest_ds_base
;
302 natural_width guest_fs_base
;
303 natural_width guest_gs_base
;
304 natural_width guest_ldtr_base
;
305 natural_width guest_tr_base
;
306 natural_width guest_gdtr_base
;
307 natural_width guest_idtr_base
;
308 natural_width guest_dr7
;
309 natural_width guest_rsp
;
310 natural_width guest_rip
;
311 natural_width guest_rflags
;
312 natural_width guest_pending_dbg_exceptions
;
313 natural_width guest_sysenter_esp
;
314 natural_width guest_sysenter_eip
;
315 natural_width host_cr0
;
316 natural_width host_cr3
;
317 natural_width host_cr4
;
318 natural_width host_fs_base
;
319 natural_width host_gs_base
;
320 natural_width host_tr_base
;
321 natural_width host_gdtr_base
;
322 natural_width host_idtr_base
;
323 natural_width host_ia32_sysenter_esp
;
324 natural_width host_ia32_sysenter_eip
;
325 natural_width host_rsp
;
326 natural_width host_rip
;
327 natural_width paddingl
[8]; /* room for future expansion */
328 u32 pin_based_vm_exec_control
;
329 u32 cpu_based_vm_exec_control
;
330 u32 exception_bitmap
;
331 u32 page_fault_error_code_mask
;
332 u32 page_fault_error_code_match
;
333 u32 cr3_target_count
;
334 u32 vm_exit_controls
;
335 u32 vm_exit_msr_store_count
;
336 u32 vm_exit_msr_load_count
;
337 u32 vm_entry_controls
;
338 u32 vm_entry_msr_load_count
;
339 u32 vm_entry_intr_info_field
;
340 u32 vm_entry_exception_error_code
;
341 u32 vm_entry_instruction_len
;
343 u32 secondary_vm_exec_control
;
344 u32 vm_instruction_error
;
346 u32 vm_exit_intr_info
;
347 u32 vm_exit_intr_error_code
;
348 u32 idt_vectoring_info_field
;
349 u32 idt_vectoring_error_code
;
350 u32 vm_exit_instruction_len
;
351 u32 vmx_instruction_info
;
358 u32 guest_ldtr_limit
;
360 u32 guest_gdtr_limit
;
361 u32 guest_idtr_limit
;
362 u32 guest_es_ar_bytes
;
363 u32 guest_cs_ar_bytes
;
364 u32 guest_ss_ar_bytes
;
365 u32 guest_ds_ar_bytes
;
366 u32 guest_fs_ar_bytes
;
367 u32 guest_gs_ar_bytes
;
368 u32 guest_ldtr_ar_bytes
;
369 u32 guest_tr_ar_bytes
;
370 u32 guest_interruptibility_info
;
371 u32 guest_activity_state
;
372 u32 guest_sysenter_cs
;
373 u32 host_ia32_sysenter_cs
;
374 u32 vmx_preemption_timer_value
;
375 u32 padding32
[7]; /* room for future expansion */
376 u16 virtual_processor_id
;
378 u16 guest_es_selector
;
379 u16 guest_cs_selector
;
380 u16 guest_ss_selector
;
381 u16 guest_ds_selector
;
382 u16 guest_fs_selector
;
383 u16 guest_gs_selector
;
384 u16 guest_ldtr_selector
;
385 u16 guest_tr_selector
;
386 u16 guest_intr_status
;
388 u16 host_es_selector
;
389 u16 host_cs_selector
;
390 u16 host_ss_selector
;
391 u16 host_ds_selector
;
392 u16 host_fs_selector
;
393 u16 host_gs_selector
;
394 u16 host_tr_selector
;
398 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
399 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
400 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
402 #define VMCS12_REVISION 0x11e57ed0
405 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
406 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
407 * current implementation, 4K are reserved to avoid future complications.
409 #define VMCS12_SIZE 0x1000
411 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
413 struct list_head list
;
415 struct loaded_vmcs vmcs02
;
419 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
420 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
423 /* Has the level1 guest done vmxon? */
428 /* The guest-physical address of the current VMCS L1 keeps for L2 */
431 * Cache of the guest's VMCS, existing outside of guest memory.
432 * Loaded from guest memory during VMPTRLD. Flushed to guest
433 * memory during VMCLEAR and VMPTRLD.
435 struct vmcs12
*cached_vmcs12
;
437 * Indicates if the shadow vmcs must be updated with the
438 * data hold by vmcs12
440 bool sync_shadow_vmcs
;
442 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
443 struct list_head vmcs02_pool
;
445 bool change_vmcs01_virtual_x2apic_mode
;
446 /* L2 must run next, and mustn't decide to exit to L1. */
447 bool nested_run_pending
;
449 * Guest pages referred to in vmcs02 with host-physical pointers, so
450 * we must keep them pinned while L2 runs.
452 struct page
*apic_access_page
;
453 struct page
*virtual_apic_page
;
454 struct page
*pi_desc_page
;
455 struct pi_desc
*pi_desc
;
459 unsigned long *msr_bitmap
;
461 struct hrtimer preemption_timer
;
462 bool preemption_timer_expired
;
464 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
471 * We only store the "true" versions of the VMX capability MSRs. We
472 * generate the "non-true" versions by setting the must-be-1 bits
473 * according to the SDM.
475 u32 nested_vmx_procbased_ctls_low
;
476 u32 nested_vmx_procbased_ctls_high
;
477 u32 nested_vmx_secondary_ctls_low
;
478 u32 nested_vmx_secondary_ctls_high
;
479 u32 nested_vmx_pinbased_ctls_low
;
480 u32 nested_vmx_pinbased_ctls_high
;
481 u32 nested_vmx_exit_ctls_low
;
482 u32 nested_vmx_exit_ctls_high
;
483 u32 nested_vmx_entry_ctls_low
;
484 u32 nested_vmx_entry_ctls_high
;
485 u32 nested_vmx_misc_low
;
486 u32 nested_vmx_misc_high
;
487 u32 nested_vmx_ept_caps
;
488 u32 nested_vmx_vpid_caps
;
489 u64 nested_vmx_basic
;
490 u64 nested_vmx_cr0_fixed0
;
491 u64 nested_vmx_cr0_fixed1
;
492 u64 nested_vmx_cr4_fixed0
;
493 u64 nested_vmx_cr4_fixed1
;
494 u64 nested_vmx_vmcs_enum
;
495 u64 nested_vmx_vmfunc_controls
;
497 /* SMM related state */
499 /* in VMX operation on SMM entry? */
501 /* in guest mode on SMM entry? */
506 #define POSTED_INTR_ON 0
507 #define POSTED_INTR_SN 1
509 /* Posted-Interrupt Descriptor */
511 u32 pir
[8]; /* Posted interrupt requested */
514 /* bit 256 - Outstanding Notification */
516 /* bit 257 - Suppress Notification */
518 /* bit 271:258 - Reserved */
520 /* bit 279:272 - Notification Vector */
522 /* bit 287:280 - Reserved */
524 /* bit 319:288 - Notification Destination */
532 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
534 return test_and_set_bit(POSTED_INTR_ON
,
535 (unsigned long *)&pi_desc
->control
);
538 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
540 return test_and_clear_bit(POSTED_INTR_ON
,
541 (unsigned long *)&pi_desc
->control
);
544 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
546 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
549 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
551 return clear_bit(POSTED_INTR_SN
,
552 (unsigned long *)&pi_desc
->control
);
555 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
557 return set_bit(POSTED_INTR_SN
,
558 (unsigned long *)&pi_desc
->control
);
561 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
563 clear_bit(POSTED_INTR_ON
,
564 (unsigned long *)&pi_desc
->control
);
567 static inline int pi_test_on(struct pi_desc
*pi_desc
)
569 return test_bit(POSTED_INTR_ON
,
570 (unsigned long *)&pi_desc
->control
);
573 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
575 return test_bit(POSTED_INTR_SN
,
576 (unsigned long *)&pi_desc
->control
);
580 struct kvm_vcpu vcpu
;
581 unsigned long host_rsp
;
584 u32 idt_vectoring_info
;
586 struct shared_msr_entry
*guest_msrs
;
589 unsigned long host_idt_base
;
591 u64 msr_host_kernel_gs_base
;
592 u64 msr_guest_kernel_gs_base
;
594 u32 vm_entry_controls_shadow
;
595 u32 vm_exit_controls_shadow
;
596 u32 secondary_exec_control
;
599 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
600 * non-nested (L1) guest, it always points to vmcs01. For a nested
601 * guest (L2), it points to a different VMCS.
603 struct loaded_vmcs vmcs01
;
604 struct loaded_vmcs
*loaded_vmcs
;
605 bool __launched
; /* temporary, used in vmx_vcpu_run */
606 struct msr_autoload
{
608 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
609 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
613 u16 fs_sel
, gs_sel
, ldt_sel
;
617 int gs_ldt_reload_needed
;
618 int fs_reload_needed
;
619 u64 msr_host_bndcfgs
;
624 struct kvm_segment segs
[8];
627 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
628 struct kvm_save_segment
{
636 bool emulation_required
;
640 /* Posted interrupt descriptor */
641 struct pi_desc pi_desc
;
643 /* Support for a guest hypervisor (nested VMX) */
644 struct nested_vmx nested
;
646 /* Dynamic PLE window. */
648 bool ple_window_dirty
;
650 /* Support for PML */
651 #define PML_ENTITY_NUM 512
654 /* apic deadline value in host tsc */
657 u64 current_tsc_ratio
;
662 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
663 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
664 * in msr_ia32_feature_control_valid_bits.
666 u64 msr_ia32_feature_control
;
667 u64 msr_ia32_feature_control_valid_bits
;
670 enum segment_cache_field
{
679 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
681 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
684 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
686 return &(to_vmx(vcpu
)->pi_desc
);
689 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
690 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
691 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
692 [number##_HIGH] = VMCS12_OFFSET(name)+4
695 static unsigned long shadow_read_only_fields
[] = {
697 * We do NOT shadow fields that are modified when L0
698 * traps and emulates any vmx instruction (e.g. VMPTRLD,
699 * VMXON...) executed by L1.
700 * For example, VM_INSTRUCTION_ERROR is read
701 * by L1 if a vmx instruction fails (part of the error path).
702 * Note the code assumes this logic. If for some reason
703 * we start shadowing these fields then we need to
704 * force a shadow sync when L0 emulates vmx instructions
705 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
706 * by nested_vmx_failValid)
710 VM_EXIT_INSTRUCTION_LEN
,
711 IDT_VECTORING_INFO_FIELD
,
712 IDT_VECTORING_ERROR_CODE
,
713 VM_EXIT_INTR_ERROR_CODE
,
715 GUEST_LINEAR_ADDRESS
,
716 GUEST_PHYSICAL_ADDRESS
718 static int max_shadow_read_only_fields
=
719 ARRAY_SIZE(shadow_read_only_fields
);
721 static unsigned long shadow_read_write_fields
[] = {
728 GUEST_INTERRUPTIBILITY_INFO
,
741 CPU_BASED_VM_EXEC_CONTROL
,
742 VM_ENTRY_EXCEPTION_ERROR_CODE
,
743 VM_ENTRY_INTR_INFO_FIELD
,
744 VM_ENTRY_INSTRUCTION_LEN
,
745 VM_ENTRY_EXCEPTION_ERROR_CODE
,
751 static int max_shadow_read_write_fields
=
752 ARRAY_SIZE(shadow_read_write_fields
);
754 static const unsigned short vmcs_field_to_offset_table
[] = {
755 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
756 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
757 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
758 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
759 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
760 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
761 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
762 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
763 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
764 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
765 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
766 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
767 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
768 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
769 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
770 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
771 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
772 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
773 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
774 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
775 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
776 FIELD64(MSR_BITMAP
, msr_bitmap
),
777 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
778 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
779 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
780 FIELD64(TSC_OFFSET
, tsc_offset
),
781 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
782 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
783 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
784 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
785 FIELD64(EPT_POINTER
, ept_pointer
),
786 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
787 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
788 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
789 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
790 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
791 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
792 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
793 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
794 FIELD64(PML_ADDRESS
, pml_address
),
795 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
796 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
797 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
798 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
799 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
800 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
801 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
802 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
803 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
804 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
805 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
806 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
807 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
808 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
809 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
810 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
811 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
812 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
813 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
814 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
815 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
816 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
817 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
818 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
819 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
820 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
821 FIELD(TPR_THRESHOLD
, tpr_threshold
),
822 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
823 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
824 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
825 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
826 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
827 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
828 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
829 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
830 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
831 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
832 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
833 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
834 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
835 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
836 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
837 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
838 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
839 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
840 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
841 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
842 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
843 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
844 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
845 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
846 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
847 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
848 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
849 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
850 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
851 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
852 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
853 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
854 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
855 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
856 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
857 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
858 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
859 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
860 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
861 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
862 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
863 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
864 FIELD(GUEST_CR0
, guest_cr0
),
865 FIELD(GUEST_CR3
, guest_cr3
),
866 FIELD(GUEST_CR4
, guest_cr4
),
867 FIELD(GUEST_ES_BASE
, guest_es_base
),
868 FIELD(GUEST_CS_BASE
, guest_cs_base
),
869 FIELD(GUEST_SS_BASE
, guest_ss_base
),
870 FIELD(GUEST_DS_BASE
, guest_ds_base
),
871 FIELD(GUEST_FS_BASE
, guest_fs_base
),
872 FIELD(GUEST_GS_BASE
, guest_gs_base
),
873 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
874 FIELD(GUEST_TR_BASE
, guest_tr_base
),
875 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
876 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
877 FIELD(GUEST_DR7
, guest_dr7
),
878 FIELD(GUEST_RSP
, guest_rsp
),
879 FIELD(GUEST_RIP
, guest_rip
),
880 FIELD(GUEST_RFLAGS
, guest_rflags
),
881 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
882 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
883 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
884 FIELD(HOST_CR0
, host_cr0
),
885 FIELD(HOST_CR3
, host_cr3
),
886 FIELD(HOST_CR4
, host_cr4
),
887 FIELD(HOST_FS_BASE
, host_fs_base
),
888 FIELD(HOST_GS_BASE
, host_gs_base
),
889 FIELD(HOST_TR_BASE
, host_tr_base
),
890 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
891 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
892 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
893 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
894 FIELD(HOST_RSP
, host_rsp
),
895 FIELD(HOST_RIP
, host_rip
),
898 static inline short vmcs_field_to_offset(unsigned long field
)
900 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
902 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
903 vmcs_field_to_offset_table
[field
] == 0)
906 return vmcs_field_to_offset_table
[field
];
909 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
911 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
914 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
915 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
916 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
917 static bool vmx_xsaves_supported(void);
918 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
919 struct kvm_segment
*var
, int seg
);
920 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
921 struct kvm_segment
*var
, int seg
);
922 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
923 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
924 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
925 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
926 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
927 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
930 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
931 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
933 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
934 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
936 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
939 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
940 * can find which vCPU should be waken up.
942 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
943 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
948 VMX_MSR_BITMAP_LEGACY
,
949 VMX_MSR_BITMAP_LONGMODE
,
950 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
951 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
952 VMX_MSR_BITMAP_LEGACY_X2APIC
,
953 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
959 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
961 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
962 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
963 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
964 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
965 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
966 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
967 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
968 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
969 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
970 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
972 static bool cpu_has_load_ia32_efer
;
973 static bool cpu_has_load_perf_global_ctrl
;
975 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
976 static DEFINE_SPINLOCK(vmx_vpid_lock
);
978 static struct vmcs_config
{
983 u32 pin_based_exec_ctrl
;
984 u32 cpu_based_exec_ctrl
;
985 u32 cpu_based_2nd_exec_ctrl
;
990 static struct vmx_capability
{
995 #define VMX_SEGMENT_FIELD(seg) \
996 [VCPU_SREG_##seg] = { \
997 .selector = GUEST_##seg##_SELECTOR, \
998 .base = GUEST_##seg##_BASE, \
999 .limit = GUEST_##seg##_LIMIT, \
1000 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1003 static const struct kvm_vmx_segment_field
{
1008 } kvm_vmx_segment_fields
[] = {
1009 VMX_SEGMENT_FIELD(CS
),
1010 VMX_SEGMENT_FIELD(DS
),
1011 VMX_SEGMENT_FIELD(ES
),
1012 VMX_SEGMENT_FIELD(FS
),
1013 VMX_SEGMENT_FIELD(GS
),
1014 VMX_SEGMENT_FIELD(SS
),
1015 VMX_SEGMENT_FIELD(TR
),
1016 VMX_SEGMENT_FIELD(LDTR
),
1019 static u64 host_efer
;
1021 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1024 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1025 * away by decrementing the array size.
1027 static const u32 vmx_msr_index
[] = {
1028 #ifdef CONFIG_X86_64
1029 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1031 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1034 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1036 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1037 INTR_INFO_VALID_MASK
)) ==
1038 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1041 static inline bool is_debug(u32 intr_info
)
1043 return is_exception_n(intr_info
, DB_VECTOR
);
1046 static inline bool is_breakpoint(u32 intr_info
)
1048 return is_exception_n(intr_info
, BP_VECTOR
);
1051 static inline bool is_page_fault(u32 intr_info
)
1053 return is_exception_n(intr_info
, PF_VECTOR
);
1056 static inline bool is_no_device(u32 intr_info
)
1058 return is_exception_n(intr_info
, NM_VECTOR
);
1061 static inline bool is_invalid_opcode(u32 intr_info
)
1063 return is_exception_n(intr_info
, UD_VECTOR
);
1066 static inline bool is_external_interrupt(u32 intr_info
)
1068 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1069 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1072 static inline bool is_machine_check(u32 intr_info
)
1074 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1075 INTR_INFO_VALID_MASK
)) ==
1076 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1079 static inline bool cpu_has_vmx_msr_bitmap(void)
1081 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1084 static inline bool cpu_has_vmx_tpr_shadow(void)
1086 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1089 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1091 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1094 static inline bool cpu_has_secondary_exec_ctrls(void)
1096 return vmcs_config
.cpu_based_exec_ctrl
&
1097 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1100 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1102 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1103 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1106 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1108 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1109 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1112 static inline bool cpu_has_vmx_apic_register_virt(void)
1114 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1115 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1118 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1120 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1121 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1125 * Comment's format: document - errata name - stepping - processor name.
1127 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1129 static u32 vmx_preemption_cpu_tfms
[] = {
1130 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1132 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1133 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1134 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1136 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1138 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1139 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1141 * 320767.pdf - AAP86 - B1 -
1142 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1145 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1147 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1149 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1151 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1152 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1153 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1157 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1159 u32 eax
= cpuid_eax(0x00000001), i
;
1161 /* Clear the reserved bits */
1162 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1163 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1164 if (eax
== vmx_preemption_cpu_tfms
[i
])
1170 static inline bool cpu_has_vmx_preemption_timer(void)
1172 return vmcs_config
.pin_based_exec_ctrl
&
1173 PIN_BASED_VMX_PREEMPTION_TIMER
;
1176 static inline bool cpu_has_vmx_posted_intr(void)
1178 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1179 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1182 static inline bool cpu_has_vmx_apicv(void)
1184 return cpu_has_vmx_apic_register_virt() &&
1185 cpu_has_vmx_virtual_intr_delivery() &&
1186 cpu_has_vmx_posted_intr();
1189 static inline bool cpu_has_vmx_flexpriority(void)
1191 return cpu_has_vmx_tpr_shadow() &&
1192 cpu_has_vmx_virtualize_apic_accesses();
1195 static inline bool cpu_has_vmx_ept_execute_only(void)
1197 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1200 static inline bool cpu_has_vmx_ept_2m_page(void)
1202 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1205 static inline bool cpu_has_vmx_ept_1g_page(void)
1207 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1210 static inline bool cpu_has_vmx_ept_4levels(void)
1212 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1215 static inline bool cpu_has_vmx_ept_mt_wb(void)
1217 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1220 static inline bool cpu_has_vmx_ept_5levels(void)
1222 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1225 static inline bool cpu_has_vmx_ept_ad_bits(void)
1227 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1230 static inline bool cpu_has_vmx_invept_context(void)
1232 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1235 static inline bool cpu_has_vmx_invept_global(void)
1237 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1240 static inline bool cpu_has_vmx_invvpid_single(void)
1242 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1245 static inline bool cpu_has_vmx_invvpid_global(void)
1247 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1250 static inline bool cpu_has_vmx_invvpid(void)
1252 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1255 static inline bool cpu_has_vmx_ept(void)
1257 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1258 SECONDARY_EXEC_ENABLE_EPT
;
1261 static inline bool cpu_has_vmx_unrestricted_guest(void)
1263 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1264 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1267 static inline bool cpu_has_vmx_ple(void)
1269 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1270 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1273 static inline bool cpu_has_vmx_basic_inout(void)
1275 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1278 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1280 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1283 static inline bool cpu_has_vmx_vpid(void)
1285 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1286 SECONDARY_EXEC_ENABLE_VPID
;
1289 static inline bool cpu_has_vmx_rdtscp(void)
1291 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1292 SECONDARY_EXEC_RDTSCP
;
1295 static inline bool cpu_has_vmx_invpcid(void)
1297 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1298 SECONDARY_EXEC_ENABLE_INVPCID
;
1301 static inline bool cpu_has_virtual_nmis(void)
1303 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1306 static inline bool cpu_has_vmx_wbinvd_exit(void)
1308 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1309 SECONDARY_EXEC_WBINVD_EXITING
;
1312 static inline bool cpu_has_vmx_shadow_vmcs(void)
1315 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1316 /* check if the cpu supports writing r/o exit information fields */
1317 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1320 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1321 SECONDARY_EXEC_SHADOW_VMCS
;
1324 static inline bool cpu_has_vmx_pml(void)
1326 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1329 static inline bool cpu_has_vmx_tsc_scaling(void)
1331 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1332 SECONDARY_EXEC_TSC_SCALING
;
1335 static inline bool cpu_has_vmx_vmfunc(void)
1337 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1338 SECONDARY_EXEC_ENABLE_VMFUNC
;
1341 static inline bool report_flexpriority(void)
1343 return flexpriority_enabled
;
1346 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1348 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1351 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1353 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1356 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1358 return (vmcs12
->cpu_based_vm_exec_control
&
1359 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1360 (vmcs12
->secondary_vm_exec_control
& bit
);
1363 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1365 return vmcs12
->pin_based_vm_exec_control
&
1366 PIN_BASED_VMX_PREEMPTION_TIMER
;
1369 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1371 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1374 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1376 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1379 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1381 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1384 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1386 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1389 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1391 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1394 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1396 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1399 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1401 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1404 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1406 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1409 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1411 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1414 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1416 return nested_cpu_has_vmfunc(vmcs12
) &&
1417 (vmcs12
->vm_function_control
&
1418 VMX_VMFUNC_EPTP_SWITCHING
);
1421 static inline bool is_nmi(u32 intr_info
)
1423 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1424 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1427 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1429 unsigned long exit_qualification
);
1430 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1431 struct vmcs12
*vmcs12
,
1432 u32 reason
, unsigned long qualification
);
1434 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1438 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1439 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1444 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1450 } operand
= { vpid
, 0, gva
};
1452 asm volatile (__ex(ASM_VMX_INVVPID
)
1453 /* CF==1 or ZF==1 --> rc = -1 */
1454 "; ja 1f ; ud2 ; 1:"
1455 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1458 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1462 } operand
= {eptp
, gpa
};
1464 asm volatile (__ex(ASM_VMX_INVEPT
)
1465 /* CF==1 or ZF==1 --> rc = -1 */
1466 "; ja 1f ; ud2 ; 1:\n"
1467 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1470 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1474 i
= __find_msr_index(vmx
, msr
);
1476 return &vmx
->guest_msrs
[i
];
1480 static void vmcs_clear(struct vmcs
*vmcs
)
1482 u64 phys_addr
= __pa(vmcs
);
1485 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1486 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1489 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1493 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1495 vmcs_clear(loaded_vmcs
->vmcs
);
1496 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1497 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1498 loaded_vmcs
->cpu
= -1;
1499 loaded_vmcs
->launched
= 0;
1502 static void vmcs_load(struct vmcs
*vmcs
)
1504 u64 phys_addr
= __pa(vmcs
);
1507 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1508 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1511 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1515 #ifdef CONFIG_KEXEC_CORE
1517 * This bitmap is used to indicate whether the vmclear
1518 * operation is enabled on all cpus. All disabled by
1521 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1523 static inline void crash_enable_local_vmclear(int cpu
)
1525 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1528 static inline void crash_disable_local_vmclear(int cpu
)
1530 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1533 static inline int crash_local_vmclear_enabled(int cpu
)
1535 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1538 static void crash_vmclear_local_loaded_vmcss(void)
1540 int cpu
= raw_smp_processor_id();
1541 struct loaded_vmcs
*v
;
1543 if (!crash_local_vmclear_enabled(cpu
))
1546 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1547 loaded_vmcss_on_cpu_link
)
1548 vmcs_clear(v
->vmcs
);
1551 static inline void crash_enable_local_vmclear(int cpu
) { }
1552 static inline void crash_disable_local_vmclear(int cpu
) { }
1553 #endif /* CONFIG_KEXEC_CORE */
1555 static void __loaded_vmcs_clear(void *arg
)
1557 struct loaded_vmcs
*loaded_vmcs
= arg
;
1558 int cpu
= raw_smp_processor_id();
1560 if (loaded_vmcs
->cpu
!= cpu
)
1561 return; /* vcpu migration can race with cpu offline */
1562 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1563 per_cpu(current_vmcs
, cpu
) = NULL
;
1564 crash_disable_local_vmclear(cpu
);
1565 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1568 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1569 * is before setting loaded_vmcs->vcpu to -1 which is done in
1570 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1571 * then adds the vmcs into percpu list before it is deleted.
1575 loaded_vmcs_init(loaded_vmcs
);
1576 crash_enable_local_vmclear(cpu
);
1579 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1581 int cpu
= loaded_vmcs
->cpu
;
1584 smp_call_function_single(cpu
,
1585 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1588 static inline void vpid_sync_vcpu_single(int vpid
)
1593 if (cpu_has_vmx_invvpid_single())
1594 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1597 static inline void vpid_sync_vcpu_global(void)
1599 if (cpu_has_vmx_invvpid_global())
1600 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1603 static inline void vpid_sync_context(int vpid
)
1605 if (cpu_has_vmx_invvpid_single())
1606 vpid_sync_vcpu_single(vpid
);
1608 vpid_sync_vcpu_global();
1611 static inline void ept_sync_global(void)
1613 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1616 static inline void ept_sync_context(u64 eptp
)
1618 if (cpu_has_vmx_invept_context())
1619 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1624 static __always_inline
void vmcs_check16(unsigned long field
)
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1627 "16-bit accessor invalid for 64-bit field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1629 "16-bit accessor invalid for 64-bit high field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1631 "16-bit accessor invalid for 32-bit high field");
1632 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1633 "16-bit accessor invalid for natural width field");
1636 static __always_inline
void vmcs_check32(unsigned long field
)
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1639 "32-bit accessor invalid for 16-bit field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1641 "32-bit accessor invalid for natural width field");
1644 static __always_inline
void vmcs_check64(unsigned long field
)
1646 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1647 "64-bit accessor invalid for 16-bit field");
1648 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1649 "64-bit accessor invalid for 64-bit high field");
1650 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1651 "64-bit accessor invalid for 32-bit field");
1652 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1653 "64-bit accessor invalid for natural width field");
1656 static __always_inline
void vmcs_checkl(unsigned long field
)
1658 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1659 "Natural width accessor invalid for 16-bit field");
1660 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1661 "Natural width accessor invalid for 64-bit field");
1662 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1663 "Natural width accessor invalid for 64-bit high field");
1664 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1665 "Natural width accessor invalid for 32-bit field");
1668 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1670 unsigned long value
;
1672 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1673 : "=a"(value
) : "d"(field
) : "cc");
1677 static __always_inline u16
vmcs_read16(unsigned long field
)
1679 vmcs_check16(field
);
1680 return __vmcs_readl(field
);
1683 static __always_inline u32
vmcs_read32(unsigned long field
)
1685 vmcs_check32(field
);
1686 return __vmcs_readl(field
);
1689 static __always_inline u64
vmcs_read64(unsigned long field
)
1691 vmcs_check64(field
);
1692 #ifdef CONFIG_X86_64
1693 return __vmcs_readl(field
);
1695 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1699 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1702 return __vmcs_readl(field
);
1705 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1707 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1708 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1712 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1716 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1717 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1718 if (unlikely(error
))
1719 vmwrite_error(field
, value
);
1722 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1724 vmcs_check16(field
);
1725 __vmcs_writel(field
, value
);
1728 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1730 vmcs_check32(field
);
1731 __vmcs_writel(field
, value
);
1734 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1736 vmcs_check64(field
);
1737 __vmcs_writel(field
, value
);
1738 #ifndef CONFIG_X86_64
1740 __vmcs_writel(field
+1, value
>> 32);
1744 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1747 __vmcs_writel(field
, value
);
1750 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1752 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1753 "vmcs_clear_bits does not support 64-bit fields");
1754 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1757 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1759 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1760 "vmcs_set_bits does not support 64-bit fields");
1761 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1764 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1766 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1769 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1771 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1772 vmx
->vm_entry_controls_shadow
= val
;
1775 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1777 if (vmx
->vm_entry_controls_shadow
!= val
)
1778 vm_entry_controls_init(vmx
, val
);
1781 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1783 return vmx
->vm_entry_controls_shadow
;
1787 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1789 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1792 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1794 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1797 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1799 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1802 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1804 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1805 vmx
->vm_exit_controls_shadow
= val
;
1808 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1810 if (vmx
->vm_exit_controls_shadow
!= val
)
1811 vm_exit_controls_init(vmx
, val
);
1814 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1816 return vmx
->vm_exit_controls_shadow
;
1820 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1822 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1825 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1827 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1830 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1832 vmx
->segment_cache
.bitmask
= 0;
1835 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1839 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1841 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1842 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1843 vmx
->segment_cache
.bitmask
= 0;
1845 ret
= vmx
->segment_cache
.bitmask
& mask
;
1846 vmx
->segment_cache
.bitmask
|= mask
;
1850 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1852 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1854 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1855 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1859 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1861 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1863 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1864 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1868 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1870 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1872 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1873 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1877 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1879 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1881 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1882 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1886 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1890 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1891 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1892 if ((vcpu
->guest_debug
&
1893 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1894 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1895 eb
|= 1u << BP_VECTOR
;
1896 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1899 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1901 /* When we are running a nested L2 guest and L1 specified for it a
1902 * certain exception bitmap, we must trap the same exceptions and pass
1903 * them to L1. When running L2, we will only handle the exceptions
1904 * specified above if L1 did not want them.
1906 if (is_guest_mode(vcpu
))
1907 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1909 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1912 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1913 unsigned long entry
, unsigned long exit
)
1915 vm_entry_controls_clearbit(vmx
, entry
);
1916 vm_exit_controls_clearbit(vmx
, exit
);
1919 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1922 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1926 if (cpu_has_load_ia32_efer
) {
1927 clear_atomic_switch_msr_special(vmx
,
1928 VM_ENTRY_LOAD_IA32_EFER
,
1929 VM_EXIT_LOAD_IA32_EFER
);
1933 case MSR_CORE_PERF_GLOBAL_CTRL
:
1934 if (cpu_has_load_perf_global_ctrl
) {
1935 clear_atomic_switch_msr_special(vmx
,
1936 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1937 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1943 for (i
= 0; i
< m
->nr
; ++i
)
1944 if (m
->guest
[i
].index
== msr
)
1950 m
->guest
[i
] = m
->guest
[m
->nr
];
1951 m
->host
[i
] = m
->host
[m
->nr
];
1952 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1953 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1956 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1957 unsigned long entry
, unsigned long exit
,
1958 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1959 u64 guest_val
, u64 host_val
)
1961 vmcs_write64(guest_val_vmcs
, guest_val
);
1962 vmcs_write64(host_val_vmcs
, host_val
);
1963 vm_entry_controls_setbit(vmx
, entry
);
1964 vm_exit_controls_setbit(vmx
, exit
);
1967 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1968 u64 guest_val
, u64 host_val
)
1971 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1975 if (cpu_has_load_ia32_efer
) {
1976 add_atomic_switch_msr_special(vmx
,
1977 VM_ENTRY_LOAD_IA32_EFER
,
1978 VM_EXIT_LOAD_IA32_EFER
,
1981 guest_val
, host_val
);
1985 case MSR_CORE_PERF_GLOBAL_CTRL
:
1986 if (cpu_has_load_perf_global_ctrl
) {
1987 add_atomic_switch_msr_special(vmx
,
1988 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1989 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1990 GUEST_IA32_PERF_GLOBAL_CTRL
,
1991 HOST_IA32_PERF_GLOBAL_CTRL
,
1992 guest_val
, host_val
);
1996 case MSR_IA32_PEBS_ENABLE
:
1997 /* PEBS needs a quiescent period after being disabled (to write
1998 * a record). Disabling PEBS through VMX MSR swapping doesn't
1999 * provide that period, so a CPU could write host's record into
2002 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2005 for (i
= 0; i
< m
->nr
; ++i
)
2006 if (m
->guest
[i
].index
== msr
)
2009 if (i
== NR_AUTOLOAD_MSRS
) {
2010 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2011 "Can't add msr %x\n", msr
);
2013 } else if (i
== m
->nr
) {
2015 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2016 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2019 m
->guest
[i
].index
= msr
;
2020 m
->guest
[i
].value
= guest_val
;
2021 m
->host
[i
].index
= msr
;
2022 m
->host
[i
].value
= host_val
;
2025 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2027 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2028 u64 ignore_bits
= 0;
2032 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2033 * host CPUID is more efficient than testing guest CPUID
2034 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2036 if (boot_cpu_has(X86_FEATURE_SMEP
))
2037 guest_efer
|= EFER_NX
;
2038 else if (!(guest_efer
& EFER_NX
))
2039 ignore_bits
|= EFER_NX
;
2043 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2045 ignore_bits
|= EFER_SCE
;
2046 #ifdef CONFIG_X86_64
2047 ignore_bits
|= EFER_LMA
| EFER_LME
;
2048 /* SCE is meaningful only in long mode on Intel */
2049 if (guest_efer
& EFER_LMA
)
2050 ignore_bits
&= ~(u64
)EFER_SCE
;
2053 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2056 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2057 * On CPUs that support "load IA32_EFER", always switch EFER
2058 * atomically, since it's faster than switching it manually.
2060 if (cpu_has_load_ia32_efer
||
2061 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2062 if (!(guest_efer
& EFER_LMA
))
2063 guest_efer
&= ~EFER_LME
;
2064 if (guest_efer
!= host_efer
)
2065 add_atomic_switch_msr(vmx
, MSR_EFER
,
2066 guest_efer
, host_efer
);
2069 guest_efer
&= ~ignore_bits
;
2070 guest_efer
|= host_efer
& ignore_bits
;
2072 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2073 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2079 #ifdef CONFIG_X86_32
2081 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2082 * VMCS rather than the segment table. KVM uses this helper to figure
2083 * out the current bases to poke them into the VMCS before entry.
2085 static unsigned long segment_base(u16 selector
)
2087 struct desc_struct
*table
;
2090 if (!(selector
& ~SEGMENT_RPL_MASK
))
2093 table
= get_current_gdt_ro();
2095 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2096 u16 ldt_selector
= kvm_read_ldt();
2098 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2101 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2103 v
= get_desc_base(&table
[selector
>> 3]);
2108 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2110 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2113 if (vmx
->host_state
.loaded
)
2116 vmx
->host_state
.loaded
= 1;
2118 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2119 * allow segment selectors with cpl > 0 or ti == 1.
2121 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2122 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2123 savesegment(fs
, vmx
->host_state
.fs_sel
);
2124 if (!(vmx
->host_state
.fs_sel
& 7)) {
2125 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2126 vmx
->host_state
.fs_reload_needed
= 0;
2128 vmcs_write16(HOST_FS_SELECTOR
, 0);
2129 vmx
->host_state
.fs_reload_needed
= 1;
2131 savesegment(gs
, vmx
->host_state
.gs_sel
);
2132 if (!(vmx
->host_state
.gs_sel
& 7))
2133 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2135 vmcs_write16(HOST_GS_SELECTOR
, 0);
2136 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2139 #ifdef CONFIG_X86_64
2140 savesegment(ds
, vmx
->host_state
.ds_sel
);
2141 savesegment(es
, vmx
->host_state
.es_sel
);
2144 #ifdef CONFIG_X86_64
2145 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2146 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2148 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2149 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2152 #ifdef CONFIG_X86_64
2153 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2154 if (is_long_mode(&vmx
->vcpu
))
2155 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2157 if (boot_cpu_has(X86_FEATURE_MPX
))
2158 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2159 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2160 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2161 vmx
->guest_msrs
[i
].data
,
2162 vmx
->guest_msrs
[i
].mask
);
2165 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2167 if (!vmx
->host_state
.loaded
)
2170 ++vmx
->vcpu
.stat
.host_state_reload
;
2171 vmx
->host_state
.loaded
= 0;
2172 #ifdef CONFIG_X86_64
2173 if (is_long_mode(&vmx
->vcpu
))
2174 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2176 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2177 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2178 #ifdef CONFIG_X86_64
2179 load_gs_index(vmx
->host_state
.gs_sel
);
2181 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2184 if (vmx
->host_state
.fs_reload_needed
)
2185 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2186 #ifdef CONFIG_X86_64
2187 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2188 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2189 loadsegment(es
, vmx
->host_state
.es_sel
);
2192 invalidate_tss_limit();
2193 #ifdef CONFIG_X86_64
2194 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2196 if (vmx
->host_state
.msr_host_bndcfgs
)
2197 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2198 load_fixmap_gdt(raw_smp_processor_id());
2201 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2204 __vmx_load_host_state(vmx
);
2208 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2210 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2211 struct pi_desc old
, new;
2215 * In case of hot-plug or hot-unplug, we may have to undo
2216 * vmx_vcpu_pi_put even if there is no assigned device. And we
2217 * always keep PI.NDST up to date for simplicity: it makes the
2218 * code easier, and CPU migration is not a fast path.
2220 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2224 * First handle the simple case where no cmpxchg is necessary; just
2225 * allow posting non-urgent interrupts.
2227 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2228 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2229 * expects the VCPU to be on the blocked_vcpu_list that matches
2232 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2234 pi_clear_sn(pi_desc
);
2238 /* The full case. */
2240 old
.control
= new.control
= pi_desc
->control
;
2242 dest
= cpu_physical_id(cpu
);
2244 if (x2apic_enabled())
2247 new.ndst
= (dest
<< 8) & 0xFF00;
2250 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2251 new.control
) != old
.control
);
2254 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2256 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2257 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2261 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2262 * vcpu mutex is already taken.
2264 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2266 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2267 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2269 if (!already_loaded
) {
2270 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2271 local_irq_disable();
2272 crash_disable_local_vmclear(cpu
);
2275 * Read loaded_vmcs->cpu should be before fetching
2276 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2277 * See the comments in __loaded_vmcs_clear().
2281 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2282 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2283 crash_enable_local_vmclear(cpu
);
2287 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2288 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2289 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2292 if (!already_loaded
) {
2293 void *gdt
= get_current_gdt_ro();
2294 unsigned long sysenter_esp
;
2296 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2299 * Linux uses per-cpu TSS and GDT, so set these when switching
2300 * processors. See 22.2.4.
2302 vmcs_writel(HOST_TR_BASE
,
2303 (unsigned long)this_cpu_ptr(&cpu_tss
));
2304 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2307 * VM exits change the host TR limit to 0x67 after a VM
2308 * exit. This is okay, since 0x67 covers everything except
2309 * the IO bitmap and have have code to handle the IO bitmap
2310 * being lost after a VM exit.
2312 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2314 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2315 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2317 vmx
->loaded_vmcs
->cpu
= cpu
;
2320 /* Setup TSC multiplier */
2321 if (kvm_has_tsc_control
&&
2322 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2323 decache_tsc_multiplier(vmx
);
2325 vmx_vcpu_pi_load(vcpu
, cpu
);
2326 vmx
->host_pkru
= read_pkru();
2329 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2331 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2333 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2334 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2335 !kvm_vcpu_apicv_active(vcpu
))
2338 /* Set SN when the vCPU is preempted */
2339 if (vcpu
->preempted
)
2343 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2345 vmx_vcpu_pi_put(vcpu
);
2347 __vmx_load_host_state(to_vmx(vcpu
));
2350 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2352 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2355 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2358 * Return the cr0 value that a nested guest would read. This is a combination
2359 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2360 * its hypervisor (cr0_read_shadow).
2362 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2364 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2365 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2367 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2369 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2370 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2373 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2375 unsigned long rflags
, save_rflags
;
2377 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2378 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2379 rflags
= vmcs_readl(GUEST_RFLAGS
);
2380 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2381 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2382 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2383 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2385 to_vmx(vcpu
)->rflags
= rflags
;
2387 return to_vmx(vcpu
)->rflags
;
2390 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2392 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2394 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2395 to_vmx(vcpu
)->rflags
= rflags
;
2396 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2397 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2398 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2400 vmcs_writel(GUEST_RFLAGS
, rflags
);
2402 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2403 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2406 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2408 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2411 if (interruptibility
& GUEST_INTR_STATE_STI
)
2412 ret
|= KVM_X86_SHADOW_INT_STI
;
2413 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2414 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2419 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2421 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2422 u32 interruptibility
= interruptibility_old
;
2424 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2426 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2427 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2428 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2429 interruptibility
|= GUEST_INTR_STATE_STI
;
2431 if ((interruptibility
!= interruptibility_old
))
2432 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2435 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2439 rip
= kvm_rip_read(vcpu
);
2440 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2441 kvm_rip_write(vcpu
, rip
);
2443 /* skipping an emulated instruction also counts */
2444 vmx_set_interrupt_shadow(vcpu
, 0);
2447 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2448 unsigned long exit_qual
)
2450 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2451 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2452 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2454 if (vcpu
->arch
.exception
.has_error_code
) {
2455 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2456 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2459 if (kvm_exception_is_soft(nr
))
2460 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2462 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2464 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2465 vmx_get_nmi_mask(vcpu
))
2466 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2468 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2472 * KVM wants to inject page-faults which it got to the guest. This function
2473 * checks whether in a nested guest, we need to inject them to L1 or L2.
2475 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2477 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2478 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2480 if (nr
== PF_VECTOR
) {
2481 if (vcpu
->arch
.exception
.nested_apf
) {
2482 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2486 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2487 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2488 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2489 * can be written only when inject_pending_event runs. This should be
2490 * conditional on a new capability---if the capability is disabled,
2491 * kvm_multiple_exception would write the ancillary information to
2492 * CR2 or DR6, for backwards ABI-compatibility.
2494 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2495 vcpu
->arch
.exception
.error_code
)) {
2496 *exit_qual
= vcpu
->arch
.cr2
;
2500 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2501 if (nr
== DB_VECTOR
)
2502 *exit_qual
= vcpu
->arch
.dr6
;
2512 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2514 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2515 unsigned nr
= vcpu
->arch
.exception
.nr
;
2516 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2517 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2518 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2520 if (has_error_code
) {
2521 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2522 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2525 if (vmx
->rmode
.vm86_active
) {
2527 if (kvm_exception_is_soft(nr
))
2528 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2529 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2530 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2534 if (kvm_exception_is_soft(nr
)) {
2535 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2536 vmx
->vcpu
.arch
.event_exit_inst_len
);
2537 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2539 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2541 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2544 static bool vmx_rdtscp_supported(void)
2546 return cpu_has_vmx_rdtscp();
2549 static bool vmx_invpcid_supported(void)
2551 return cpu_has_vmx_invpcid() && enable_ept
;
2555 * Swap MSR entry in host/guest MSR entry array.
2557 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2559 struct shared_msr_entry tmp
;
2561 tmp
= vmx
->guest_msrs
[to
];
2562 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2563 vmx
->guest_msrs
[from
] = tmp
;
2566 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2568 unsigned long *msr_bitmap
;
2570 if (is_guest_mode(vcpu
))
2571 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2572 else if (cpu_has_secondary_exec_ctrls() &&
2573 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2574 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2575 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2576 if (is_long_mode(vcpu
))
2577 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2579 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2581 if (is_long_mode(vcpu
))
2582 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2584 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2587 if (is_long_mode(vcpu
))
2588 msr_bitmap
= vmx_msr_bitmap_longmode
;
2590 msr_bitmap
= vmx_msr_bitmap_legacy
;
2593 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2597 * Set up the vmcs to automatically save and restore system
2598 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2599 * mode, as fiddling with msrs is very expensive.
2601 static void setup_msrs(struct vcpu_vmx
*vmx
)
2603 int save_nmsrs
, index
;
2606 #ifdef CONFIG_X86_64
2607 if (is_long_mode(&vmx
->vcpu
)) {
2608 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2610 move_msr_up(vmx
, index
, save_nmsrs
++);
2611 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2613 move_msr_up(vmx
, index
, save_nmsrs
++);
2614 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2616 move_msr_up(vmx
, index
, save_nmsrs
++);
2617 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2618 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2621 * MSR_STAR is only needed on long mode guests, and only
2622 * if efer.sce is enabled.
2624 index
= __find_msr_index(vmx
, MSR_STAR
);
2625 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2626 move_msr_up(vmx
, index
, save_nmsrs
++);
2629 index
= __find_msr_index(vmx
, MSR_EFER
);
2630 if (index
>= 0 && update_transition_efer(vmx
, index
))
2631 move_msr_up(vmx
, index
, save_nmsrs
++);
2633 vmx
->save_nmsrs
= save_nmsrs
;
2635 if (cpu_has_vmx_msr_bitmap())
2636 vmx_set_msr_bitmap(&vmx
->vcpu
);
2640 * reads and returns guest's timestamp counter "register"
2641 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2642 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2644 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2646 u64 host_tsc
, tsc_offset
;
2649 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2650 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2654 * writes 'offset' into guest's timestamp counter offset register
2656 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2658 if (is_guest_mode(vcpu
)) {
2660 * We're here if L1 chose not to trap WRMSR to TSC. According
2661 * to the spec, this should set L1's TSC; The offset that L1
2662 * set for L2 remains unchanged, and still needs to be added
2663 * to the newly set TSC to get L2's TSC.
2665 struct vmcs12
*vmcs12
;
2666 /* recalculate vmcs02.TSC_OFFSET: */
2667 vmcs12
= get_vmcs12(vcpu
);
2668 vmcs_write64(TSC_OFFSET
, offset
+
2669 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2670 vmcs12
->tsc_offset
: 0));
2672 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2673 vmcs_read64(TSC_OFFSET
), offset
);
2674 vmcs_write64(TSC_OFFSET
, offset
);
2679 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2680 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2681 * all guests if the "nested" module option is off, and can also be disabled
2682 * for a single guest by disabling its VMX cpuid bit.
2684 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2686 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2690 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2691 * returned for the various VMX controls MSRs when nested VMX is enabled.
2692 * The same values should also be used to verify that vmcs12 control fields are
2693 * valid during nested entry from L1 to L2.
2694 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2695 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2696 * bit in the high half is on if the corresponding bit in the control field
2697 * may be on. See also vmx_control_verify().
2699 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2702 * Note that as a general rule, the high half of the MSRs (bits in
2703 * the control fields which may be 1) should be initialized by the
2704 * intersection of the underlying hardware's MSR (i.e., features which
2705 * can be supported) and the list of features we want to expose -
2706 * because they are known to be properly supported in our code.
2707 * Also, usually, the low half of the MSRs (bits which must be 1) can
2708 * be set to 0, meaning that L1 may turn off any of these bits. The
2709 * reason is that if one of these bits is necessary, it will appear
2710 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2711 * fields of vmcs01 and vmcs02, will turn these bits off - and
2712 * nested_vmx_exit_reflected() will not pass related exits to L1.
2713 * These rules have exceptions below.
2716 /* pin-based controls */
2717 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2718 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2720 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2721 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2722 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2723 PIN_BASED_EXT_INTR_MASK
|
2724 PIN_BASED_NMI_EXITING
|
2725 PIN_BASED_VIRTUAL_NMIS
;
2726 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2727 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2728 PIN_BASED_VMX_PREEMPTION_TIMER
;
2729 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2730 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2731 PIN_BASED_POSTED_INTR
;
2734 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2735 vmx
->nested
.nested_vmx_exit_ctls_low
,
2736 vmx
->nested
.nested_vmx_exit_ctls_high
);
2737 vmx
->nested
.nested_vmx_exit_ctls_low
=
2738 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2740 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2741 #ifdef CONFIG_X86_64
2742 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2744 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2745 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2746 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2747 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2748 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2750 if (kvm_mpx_supported())
2751 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2753 /* We support free control of debug control saving. */
2754 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2756 /* entry controls */
2757 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2758 vmx
->nested
.nested_vmx_entry_ctls_low
,
2759 vmx
->nested
.nested_vmx_entry_ctls_high
);
2760 vmx
->nested
.nested_vmx_entry_ctls_low
=
2761 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2762 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2763 #ifdef CONFIG_X86_64
2764 VM_ENTRY_IA32E_MODE
|
2766 VM_ENTRY_LOAD_IA32_PAT
;
2767 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2768 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2769 if (kvm_mpx_supported())
2770 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2772 /* We support free control of debug control loading. */
2773 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2775 /* cpu-based controls */
2776 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2777 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2778 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2779 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2780 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2781 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2782 CPU_BASED_VIRTUAL_INTR_PENDING
|
2783 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2784 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2785 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2786 CPU_BASED_CR3_STORE_EXITING
|
2787 #ifdef CONFIG_X86_64
2788 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2790 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2791 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2792 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2793 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2794 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2796 * We can allow some features even when not supported by the
2797 * hardware. For example, L1 can specify an MSR bitmap - and we
2798 * can use it to avoid exits to L1 - even when L0 runs L2
2799 * without MSR bitmaps.
2801 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2802 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2803 CPU_BASED_USE_MSR_BITMAPS
;
2805 /* We support free control of CR3 access interception. */
2806 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2807 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2810 * secondary cpu-based controls. Do not include those that
2811 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2813 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2814 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2815 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2816 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2817 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2818 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2819 SECONDARY_EXEC_DESC
|
2820 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2821 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2822 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2823 SECONDARY_EXEC_WBINVD_EXITING
;
2826 /* nested EPT: emulate EPT also to L1 */
2827 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2828 SECONDARY_EXEC_ENABLE_EPT
;
2829 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2830 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2831 if (cpu_has_vmx_ept_execute_only())
2832 vmx
->nested
.nested_vmx_ept_caps
|=
2833 VMX_EPT_EXECUTE_ONLY_BIT
;
2834 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2835 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2836 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2837 VMX_EPT_1GB_PAGE_BIT
;
2838 if (enable_ept_ad_bits
) {
2839 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2840 SECONDARY_EXEC_ENABLE_PML
;
2841 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2845 if (cpu_has_vmx_vmfunc()) {
2846 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2847 SECONDARY_EXEC_ENABLE_VMFUNC
;
2849 * Advertise EPTP switching unconditionally
2850 * since we emulate it
2853 vmx
->nested
.nested_vmx_vmfunc_controls
=
2854 VMX_VMFUNC_EPTP_SWITCHING
;
2858 * Old versions of KVM use the single-context version without
2859 * checking for support, so declare that it is supported even
2860 * though it is treated as global context. The alternative is
2861 * not failing the single-context invvpid, and it is worse.
2864 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2865 SECONDARY_EXEC_ENABLE_VPID
;
2866 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2867 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2870 if (enable_unrestricted_guest
)
2871 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2872 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2874 /* miscellaneous data */
2875 rdmsr(MSR_IA32_VMX_MISC
,
2876 vmx
->nested
.nested_vmx_misc_low
,
2877 vmx
->nested
.nested_vmx_misc_high
);
2878 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2879 vmx
->nested
.nested_vmx_misc_low
|=
2880 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2881 VMX_MISC_ACTIVITY_HLT
;
2882 vmx
->nested
.nested_vmx_misc_high
= 0;
2885 * This MSR reports some information about VMX support. We
2886 * should return information about the VMX we emulate for the
2887 * guest, and the VMCS structure we give it - not about the
2888 * VMX support of the underlying hardware.
2890 vmx
->nested
.nested_vmx_basic
=
2892 VMX_BASIC_TRUE_CTLS
|
2893 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2894 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2896 if (cpu_has_vmx_basic_inout())
2897 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2900 * These MSRs specify bits which the guest must keep fixed on
2901 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2902 * We picked the standard core2 setting.
2904 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2905 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2906 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2907 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2909 /* These MSRs specify bits which the guest must keep fixed off. */
2910 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2911 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2913 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2914 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2918 * if fixed0[i] == 1: val[i] must be 1
2919 * if fixed1[i] == 0: val[i] must be 0
2921 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2923 return ((val
& fixed1
) | fixed0
) == val
;
2926 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2928 return fixed_bits_valid(control
, low
, high
);
2931 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2933 return low
| ((u64
)high
<< 32);
2936 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2941 return (superset
| subset
) == superset
;
2944 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2946 const u64 feature_and_reserved
=
2947 /* feature (except bit 48; see below) */
2948 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2950 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2951 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2953 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2957 * KVM does not emulate a version of VMX that constrains physical
2958 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2960 if (data
& BIT_ULL(48))
2963 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2964 vmx_basic_vmcs_revision_id(data
))
2967 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2970 vmx
->nested
.nested_vmx_basic
= data
;
2975 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2980 switch (msr_index
) {
2981 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2982 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2983 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2985 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2986 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2987 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2989 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2990 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2991 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2993 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2994 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2995 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2997 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2998 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2999 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3005 supported
= vmx_control_msr(*lowp
, *highp
);
3007 /* Check must-be-1 bits are still 1. */
3008 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3011 /* Check must-be-0 bits are still 0. */
3012 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3016 *highp
= data
>> 32;
3020 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3022 const u64 feature_and_reserved_bits
=
3024 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3025 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3027 GENMASK_ULL(13, 9) | BIT_ULL(31);
3030 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3031 vmx
->nested
.nested_vmx_misc_high
);
3033 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3036 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3037 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3038 vmx_misc_preemption_timer_rate(data
) !=
3039 vmx_misc_preemption_timer_rate(vmx_misc
))
3042 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3045 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3048 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3051 vmx
->nested
.nested_vmx_misc_low
= data
;
3052 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3056 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3058 u64 vmx_ept_vpid_cap
;
3060 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3061 vmx
->nested
.nested_vmx_vpid_caps
);
3063 /* Every bit is either reserved or a feature bit. */
3064 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3067 vmx
->nested
.nested_vmx_ept_caps
= data
;
3068 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3072 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3076 switch (msr_index
) {
3077 case MSR_IA32_VMX_CR0_FIXED0
:
3078 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3080 case MSR_IA32_VMX_CR4_FIXED0
:
3081 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3088 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3089 * must be 1 in the restored value.
3091 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3099 * Called when userspace is restoring VMX MSRs.
3101 * Returns 0 on success, non-0 otherwise.
3103 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3105 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3107 switch (msr_index
) {
3108 case MSR_IA32_VMX_BASIC
:
3109 return vmx_restore_vmx_basic(vmx
, data
);
3110 case MSR_IA32_VMX_PINBASED_CTLS
:
3111 case MSR_IA32_VMX_PROCBASED_CTLS
:
3112 case MSR_IA32_VMX_EXIT_CTLS
:
3113 case MSR_IA32_VMX_ENTRY_CTLS
:
3115 * The "non-true" VMX capability MSRs are generated from the
3116 * "true" MSRs, so we do not support restoring them directly.
3118 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3119 * should restore the "true" MSRs with the must-be-1 bits
3120 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3121 * DEFAULT SETTINGS".
3124 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3125 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3126 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3127 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3128 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3129 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3130 case MSR_IA32_VMX_MISC
:
3131 return vmx_restore_vmx_misc(vmx
, data
);
3132 case MSR_IA32_VMX_CR0_FIXED0
:
3133 case MSR_IA32_VMX_CR4_FIXED0
:
3134 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3135 case MSR_IA32_VMX_CR0_FIXED1
:
3136 case MSR_IA32_VMX_CR4_FIXED1
:
3138 * These MSRs are generated based on the vCPU's CPUID, so we
3139 * do not support restoring them directly.
3142 case MSR_IA32_VMX_EPT_VPID_CAP
:
3143 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3144 case MSR_IA32_VMX_VMCS_ENUM
:
3145 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3149 * The rest of the VMX capability MSRs do not support restore.
3155 /* Returns 0 on success, non-0 otherwise. */
3156 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3158 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3160 switch (msr_index
) {
3161 case MSR_IA32_VMX_BASIC
:
3162 *pdata
= vmx
->nested
.nested_vmx_basic
;
3164 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3165 case MSR_IA32_VMX_PINBASED_CTLS
:
3166 *pdata
= vmx_control_msr(
3167 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3168 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3169 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3170 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3172 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3173 case MSR_IA32_VMX_PROCBASED_CTLS
:
3174 *pdata
= vmx_control_msr(
3175 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3176 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3177 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3178 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3180 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3181 case MSR_IA32_VMX_EXIT_CTLS
:
3182 *pdata
= vmx_control_msr(
3183 vmx
->nested
.nested_vmx_exit_ctls_low
,
3184 vmx
->nested
.nested_vmx_exit_ctls_high
);
3185 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3186 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3188 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3189 case MSR_IA32_VMX_ENTRY_CTLS
:
3190 *pdata
= vmx_control_msr(
3191 vmx
->nested
.nested_vmx_entry_ctls_low
,
3192 vmx
->nested
.nested_vmx_entry_ctls_high
);
3193 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3194 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3196 case MSR_IA32_VMX_MISC
:
3197 *pdata
= vmx_control_msr(
3198 vmx
->nested
.nested_vmx_misc_low
,
3199 vmx
->nested
.nested_vmx_misc_high
);
3201 case MSR_IA32_VMX_CR0_FIXED0
:
3202 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3204 case MSR_IA32_VMX_CR0_FIXED1
:
3205 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3207 case MSR_IA32_VMX_CR4_FIXED0
:
3208 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3210 case MSR_IA32_VMX_CR4_FIXED1
:
3211 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3213 case MSR_IA32_VMX_VMCS_ENUM
:
3214 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3216 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3217 *pdata
= vmx_control_msr(
3218 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3219 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3221 case MSR_IA32_VMX_EPT_VPID_CAP
:
3222 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3223 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3225 case MSR_IA32_VMX_VMFUNC
:
3226 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3235 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3238 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3240 return !(val
& ~valid_bits
);
3244 * Reads an msr value (of 'msr_index') into 'pdata'.
3245 * Returns 0 on success, non-0 otherwise.
3246 * Assumes vcpu_load() was already called.
3248 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3250 struct shared_msr_entry
*msr
;
3252 switch (msr_info
->index
) {
3253 #ifdef CONFIG_X86_64
3255 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3258 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3260 case MSR_KERNEL_GS_BASE
:
3261 vmx_load_host_state(to_vmx(vcpu
));
3262 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3266 return kvm_get_msr_common(vcpu
, msr_info
);
3268 msr_info
->data
= guest_read_tsc(vcpu
);
3270 case MSR_IA32_SYSENTER_CS
:
3271 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3273 case MSR_IA32_SYSENTER_EIP
:
3274 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3276 case MSR_IA32_SYSENTER_ESP
:
3277 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3279 case MSR_IA32_BNDCFGS
:
3280 if (!kvm_mpx_supported() ||
3281 (!msr_info
->host_initiated
&&
3282 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3284 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3286 case MSR_IA32_MCG_EXT_CTL
:
3287 if (!msr_info
->host_initiated
&&
3288 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3289 FEATURE_CONTROL_LMCE
))
3291 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3293 case MSR_IA32_FEATURE_CONTROL
:
3294 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3296 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3297 if (!nested_vmx_allowed(vcpu
))
3299 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3301 if (!vmx_xsaves_supported())
3303 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3306 if (!msr_info
->host_initiated
&&
3307 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3309 /* Otherwise falls through */
3311 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3313 msr_info
->data
= msr
->data
;
3316 return kvm_get_msr_common(vcpu
, msr_info
);
3322 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3325 * Writes msr value into into the appropriate "register".
3326 * Returns 0 on success, non-0 otherwise.
3327 * Assumes vcpu_load() was already called.
3329 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3332 struct shared_msr_entry
*msr
;
3334 u32 msr_index
= msr_info
->index
;
3335 u64 data
= msr_info
->data
;
3337 switch (msr_index
) {
3339 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3341 #ifdef CONFIG_X86_64
3343 vmx_segment_cache_clear(vmx
);
3344 vmcs_writel(GUEST_FS_BASE
, data
);
3347 vmx_segment_cache_clear(vmx
);
3348 vmcs_writel(GUEST_GS_BASE
, data
);
3350 case MSR_KERNEL_GS_BASE
:
3351 vmx_load_host_state(vmx
);
3352 vmx
->msr_guest_kernel_gs_base
= data
;
3355 case MSR_IA32_SYSENTER_CS
:
3356 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3358 case MSR_IA32_SYSENTER_EIP
:
3359 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3361 case MSR_IA32_SYSENTER_ESP
:
3362 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3364 case MSR_IA32_BNDCFGS
:
3365 if (!kvm_mpx_supported() ||
3366 (!msr_info
->host_initiated
&&
3367 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3369 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3370 (data
& MSR_IA32_BNDCFGS_RSVD
))
3372 vmcs_write64(GUEST_BNDCFGS
, data
);
3375 kvm_write_tsc(vcpu
, msr_info
);
3377 case MSR_IA32_CR_PAT
:
3378 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3379 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3381 vmcs_write64(GUEST_IA32_PAT
, data
);
3382 vcpu
->arch
.pat
= data
;
3385 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3387 case MSR_IA32_TSC_ADJUST
:
3388 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3390 case MSR_IA32_MCG_EXT_CTL
:
3391 if ((!msr_info
->host_initiated
&&
3392 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3393 FEATURE_CONTROL_LMCE
)) ||
3394 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3396 vcpu
->arch
.mcg_ext_ctl
= data
;
3398 case MSR_IA32_FEATURE_CONTROL
:
3399 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3400 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3401 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3403 vmx
->msr_ia32_feature_control
= data
;
3404 if (msr_info
->host_initiated
&& data
== 0)
3405 vmx_leave_nested(vcpu
);
3407 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3408 if (!msr_info
->host_initiated
)
3409 return 1; /* they are read-only */
3410 if (!nested_vmx_allowed(vcpu
))
3412 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3414 if (!vmx_xsaves_supported())
3417 * The only supported bit as of Skylake is bit 8, but
3418 * it is not supported on KVM.
3422 vcpu
->arch
.ia32_xss
= data
;
3423 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3424 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3425 vcpu
->arch
.ia32_xss
, host_xss
);
3427 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3430 if (!msr_info
->host_initiated
&&
3431 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3433 /* Check reserved bit, higher 32 bits should be zero */
3434 if ((data
>> 32) != 0)
3436 /* Otherwise falls through */
3438 msr
= find_msr_entry(vmx
, msr_index
);
3440 u64 old_msr_data
= msr
->data
;
3442 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3444 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3448 msr
->data
= old_msr_data
;
3452 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3458 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3460 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3463 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3466 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3468 case VCPU_EXREG_PDPTR
:
3470 ept_save_pdptrs(vcpu
);
3477 static __init
int cpu_has_kvm_support(void)
3479 return cpu_has_vmx();
3482 static __init
int vmx_disabled_by_bios(void)
3486 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3487 if (msr
& FEATURE_CONTROL_LOCKED
) {
3488 /* launched w/ TXT and VMX disabled */
3489 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3492 /* launched w/o TXT and VMX only enabled w/ TXT */
3493 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3494 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3495 && !tboot_enabled()) {
3496 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3497 "activate TXT before enabling KVM\n");
3500 /* launched w/o TXT and VMX disabled */
3501 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3502 && !tboot_enabled())
3509 static void kvm_cpu_vmxon(u64 addr
)
3511 cr4_set_bits(X86_CR4_VMXE
);
3512 intel_pt_handle_vmx(1);
3514 asm volatile (ASM_VMX_VMXON_RAX
3515 : : "a"(&addr
), "m"(addr
)
3519 static int hardware_enable(void)
3521 int cpu
= raw_smp_processor_id();
3522 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3525 if (cr4_read_shadow() & X86_CR4_VMXE
)
3528 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3529 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3530 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3533 * Now we can enable the vmclear operation in kdump
3534 * since the loaded_vmcss_on_cpu list on this cpu
3535 * has been initialized.
3537 * Though the cpu is not in VMX operation now, there
3538 * is no problem to enable the vmclear operation
3539 * for the loaded_vmcss_on_cpu list is empty!
3541 crash_enable_local_vmclear(cpu
);
3543 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3545 test_bits
= FEATURE_CONTROL_LOCKED
;
3546 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3547 if (tboot_enabled())
3548 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3550 if ((old
& test_bits
) != test_bits
) {
3551 /* enable and lock */
3552 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3554 kvm_cpu_vmxon(phys_addr
);
3561 static void vmclear_local_loaded_vmcss(void)
3563 int cpu
= raw_smp_processor_id();
3564 struct loaded_vmcs
*v
, *n
;
3566 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3567 loaded_vmcss_on_cpu_link
)
3568 __loaded_vmcs_clear(v
);
3572 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3575 static void kvm_cpu_vmxoff(void)
3577 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3579 intel_pt_handle_vmx(0);
3580 cr4_clear_bits(X86_CR4_VMXE
);
3583 static void hardware_disable(void)
3585 vmclear_local_loaded_vmcss();
3589 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3590 u32 msr
, u32
*result
)
3592 u32 vmx_msr_low
, vmx_msr_high
;
3593 u32 ctl
= ctl_min
| ctl_opt
;
3595 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3597 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3598 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3600 /* Ensure minimum (required) set of control bits are supported. */
3608 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3610 u32 vmx_msr_low
, vmx_msr_high
;
3612 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3613 return vmx_msr_high
& ctl
;
3616 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3618 u32 vmx_msr_low
, vmx_msr_high
;
3619 u32 min
, opt
, min2
, opt2
;
3620 u32 _pin_based_exec_control
= 0;
3621 u32 _cpu_based_exec_control
= 0;
3622 u32 _cpu_based_2nd_exec_control
= 0;
3623 u32 _vmexit_control
= 0;
3624 u32 _vmentry_control
= 0;
3626 min
= CPU_BASED_HLT_EXITING
|
3627 #ifdef CONFIG_X86_64
3628 CPU_BASED_CR8_LOAD_EXITING
|
3629 CPU_BASED_CR8_STORE_EXITING
|
3631 CPU_BASED_CR3_LOAD_EXITING
|
3632 CPU_BASED_CR3_STORE_EXITING
|
3633 CPU_BASED_USE_IO_BITMAPS
|
3634 CPU_BASED_MOV_DR_EXITING
|
3635 CPU_BASED_USE_TSC_OFFSETING
|
3636 CPU_BASED_INVLPG_EXITING
|
3637 CPU_BASED_RDPMC_EXITING
;
3639 if (!kvm_mwait_in_guest())
3640 min
|= CPU_BASED_MWAIT_EXITING
|
3641 CPU_BASED_MONITOR_EXITING
;
3643 opt
= CPU_BASED_TPR_SHADOW
|
3644 CPU_BASED_USE_MSR_BITMAPS
|
3645 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3646 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3647 &_cpu_based_exec_control
) < 0)
3649 #ifdef CONFIG_X86_64
3650 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3651 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3652 ~CPU_BASED_CR8_STORE_EXITING
;
3654 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3656 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3657 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3658 SECONDARY_EXEC_WBINVD_EXITING
|
3659 SECONDARY_EXEC_ENABLE_VPID
|
3660 SECONDARY_EXEC_ENABLE_EPT
|
3661 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3662 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3663 SECONDARY_EXEC_RDTSCP
|
3664 SECONDARY_EXEC_ENABLE_INVPCID
|
3665 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3666 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3667 SECONDARY_EXEC_SHADOW_VMCS
|
3668 SECONDARY_EXEC_XSAVES
|
3669 SECONDARY_EXEC_RDSEED_EXITING
|
3670 SECONDARY_EXEC_RDRAND_EXITING
|
3671 SECONDARY_EXEC_ENABLE_PML
|
3672 SECONDARY_EXEC_TSC_SCALING
|
3673 SECONDARY_EXEC_ENABLE_VMFUNC
;
3674 if (adjust_vmx_controls(min2
, opt2
,
3675 MSR_IA32_VMX_PROCBASED_CTLS2
,
3676 &_cpu_based_2nd_exec_control
) < 0)
3679 #ifndef CONFIG_X86_64
3680 if (!(_cpu_based_2nd_exec_control
&
3681 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3682 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3685 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3686 _cpu_based_2nd_exec_control
&= ~(
3687 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3688 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3689 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3691 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3692 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3694 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3695 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3697 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3698 CPU_BASED_CR3_STORE_EXITING
|
3699 CPU_BASED_INVLPG_EXITING
);
3700 } else if (vmx_capability
.ept
) {
3701 vmx_capability
.ept
= 0;
3702 pr_warn_once("EPT CAP should not exist if not support "
3703 "1-setting enable EPT VM-execution control\n");
3705 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3706 vmx_capability
.vpid
) {
3707 vmx_capability
.vpid
= 0;
3708 pr_warn_once("VPID CAP should not exist if not support "
3709 "1-setting enable VPID VM-execution control\n");
3712 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3713 #ifdef CONFIG_X86_64
3714 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3716 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3717 VM_EXIT_CLEAR_BNDCFGS
;
3718 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3719 &_vmexit_control
) < 0)
3722 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3723 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3724 PIN_BASED_VMX_PREEMPTION_TIMER
;
3725 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3726 &_pin_based_exec_control
) < 0)
3729 if (cpu_has_broken_vmx_preemption_timer())
3730 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3731 if (!(_cpu_based_2nd_exec_control
&
3732 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3733 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3735 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3736 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3737 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3738 &_vmentry_control
) < 0)
3741 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3743 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3744 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3747 #ifdef CONFIG_X86_64
3748 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3749 if (vmx_msr_high
& (1u<<16))
3753 /* Require Write-Back (WB) memory type for VMCS accesses. */
3754 if (((vmx_msr_high
>> 18) & 15) != 6)
3757 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3758 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3759 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3760 vmcs_conf
->revision_id
= vmx_msr_low
;
3762 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3763 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3764 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3765 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3766 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3768 cpu_has_load_ia32_efer
=
3769 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3770 VM_ENTRY_LOAD_IA32_EFER
)
3771 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3772 VM_EXIT_LOAD_IA32_EFER
);
3774 cpu_has_load_perf_global_ctrl
=
3775 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3776 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3777 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3778 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3781 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3782 * but due to errata below it can't be used. Workaround is to use
3783 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3785 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3790 * BC86,AAY89,BD102 (model 44)
3794 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3795 switch (boot_cpu_data
.x86_model
) {
3801 cpu_has_load_perf_global_ctrl
= false;
3802 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3803 "does not work properly. Using workaround\n");
3810 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3811 rdmsrl(MSR_IA32_XSS
, host_xss
);
3816 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3818 int node
= cpu_to_node(cpu
);
3822 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3825 vmcs
= page_address(pages
);
3826 memset(vmcs
, 0, vmcs_config
.size
);
3827 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3831 static struct vmcs
*alloc_vmcs(void)
3833 return alloc_vmcs_cpu(raw_smp_processor_id());
3836 static void free_vmcs(struct vmcs
*vmcs
)
3838 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3842 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3844 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3846 if (!loaded_vmcs
->vmcs
)
3848 loaded_vmcs_clear(loaded_vmcs
);
3849 free_vmcs(loaded_vmcs
->vmcs
);
3850 loaded_vmcs
->vmcs
= NULL
;
3851 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3854 static void free_kvm_area(void)
3858 for_each_possible_cpu(cpu
) {
3859 free_vmcs(per_cpu(vmxarea
, cpu
));
3860 per_cpu(vmxarea
, cpu
) = NULL
;
3864 enum vmcs_field_type
{
3865 VMCS_FIELD_TYPE_U16
= 0,
3866 VMCS_FIELD_TYPE_U64
= 1,
3867 VMCS_FIELD_TYPE_U32
= 2,
3868 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3871 static inline int vmcs_field_type(unsigned long field
)
3873 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3874 return VMCS_FIELD_TYPE_U32
;
3875 return (field
>> 13) & 0x3 ;
3878 static inline int vmcs_field_readonly(unsigned long field
)
3880 return (((field
>> 10) & 0x3) == 1);
3883 static void init_vmcs_shadow_fields(void)
3887 /* No checks for read only fields yet */
3889 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3890 switch (shadow_read_write_fields
[i
]) {
3892 if (!kvm_mpx_supported())
3900 shadow_read_write_fields
[j
] =
3901 shadow_read_write_fields
[i
];
3904 max_shadow_read_write_fields
= j
;
3906 /* shadowed fields guest access without vmexit */
3907 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3908 unsigned long field
= shadow_read_write_fields
[i
];
3910 clear_bit(field
, vmx_vmwrite_bitmap
);
3911 clear_bit(field
, vmx_vmread_bitmap
);
3912 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3913 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3914 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3917 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3918 unsigned long field
= shadow_read_only_fields
[i
];
3920 clear_bit(field
, vmx_vmread_bitmap
);
3921 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3922 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3926 static __init
int alloc_kvm_area(void)
3930 for_each_possible_cpu(cpu
) {
3933 vmcs
= alloc_vmcs_cpu(cpu
);
3939 per_cpu(vmxarea
, cpu
) = vmcs
;
3944 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3945 struct kvm_segment
*save
)
3947 if (!emulate_invalid_guest_state
) {
3949 * CS and SS RPL should be equal during guest entry according
3950 * to VMX spec, but in reality it is not always so. Since vcpu
3951 * is in the middle of the transition from real mode to
3952 * protected mode it is safe to assume that RPL 0 is a good
3955 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3956 save
->selector
&= ~SEGMENT_RPL_MASK
;
3957 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3960 vmx_set_segment(vcpu
, save
, seg
);
3963 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3965 unsigned long flags
;
3966 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3969 * Update real mode segment cache. It may be not up-to-date if sement
3970 * register was written while vcpu was in a guest mode.
3972 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3973 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3974 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3975 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3976 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3977 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3979 vmx
->rmode
.vm86_active
= 0;
3981 vmx_segment_cache_clear(vmx
);
3983 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3985 flags
= vmcs_readl(GUEST_RFLAGS
);
3986 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3987 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3988 vmcs_writel(GUEST_RFLAGS
, flags
);
3990 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3991 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3993 update_exception_bitmap(vcpu
);
3995 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3996 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3997 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3998 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3999 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4000 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4003 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4005 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4006 struct kvm_segment var
= *save
;
4009 if (seg
== VCPU_SREG_CS
)
4012 if (!emulate_invalid_guest_state
) {
4013 var
.selector
= var
.base
>> 4;
4014 var
.base
= var
.base
& 0xffff0;
4024 if (save
->base
& 0xf)
4025 printk_once(KERN_WARNING
"kvm: segment base is not "
4026 "paragraph aligned when entering "
4027 "protected mode (seg=%d)", seg
);
4030 vmcs_write16(sf
->selector
, var
.selector
);
4031 vmcs_writel(sf
->base
, var
.base
);
4032 vmcs_write32(sf
->limit
, var
.limit
);
4033 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4036 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4038 unsigned long flags
;
4039 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4041 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4042 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4043 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4044 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4045 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4046 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4047 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4049 vmx
->rmode
.vm86_active
= 1;
4052 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4053 * vcpu. Warn the user that an update is overdue.
4055 if (!vcpu
->kvm
->arch
.tss_addr
)
4056 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4057 "called before entering vcpu\n");
4059 vmx_segment_cache_clear(vmx
);
4061 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4062 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4063 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4065 flags
= vmcs_readl(GUEST_RFLAGS
);
4066 vmx
->rmode
.save_rflags
= flags
;
4068 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4070 vmcs_writel(GUEST_RFLAGS
, flags
);
4071 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4072 update_exception_bitmap(vcpu
);
4074 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4075 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4076 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4077 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4078 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4079 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4081 kvm_mmu_reset_context(vcpu
);
4084 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4086 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4087 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4093 * Force kernel_gs_base reloading before EFER changes, as control
4094 * of this msr depends on is_long_mode().
4096 vmx_load_host_state(to_vmx(vcpu
));
4097 vcpu
->arch
.efer
= efer
;
4098 if (efer
& EFER_LMA
) {
4099 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4102 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4104 msr
->data
= efer
& ~EFER_LME
;
4109 #ifdef CONFIG_X86_64
4111 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4115 vmx_segment_cache_clear(to_vmx(vcpu
));
4117 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4118 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4119 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4121 vmcs_write32(GUEST_TR_AR_BYTES
,
4122 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4123 | VMX_AR_TYPE_BUSY_64_TSS
);
4125 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4128 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4130 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4131 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4136 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4139 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4141 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4143 vpid_sync_context(vpid
);
4147 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4149 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4152 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4155 vmx_flush_tlb(vcpu
);
4158 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4160 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4162 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4163 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4166 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4168 if (enable_ept
&& is_paging(vcpu
))
4169 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4170 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4173 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4175 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4177 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4178 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4181 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4183 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4185 if (!test_bit(VCPU_EXREG_PDPTR
,
4186 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4189 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4190 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4191 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4192 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4193 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4197 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4199 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4201 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4202 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4203 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4204 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4205 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4208 __set_bit(VCPU_EXREG_PDPTR
,
4209 (unsigned long *)&vcpu
->arch
.regs_avail
);
4210 __set_bit(VCPU_EXREG_PDPTR
,
4211 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4214 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4216 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4217 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4218 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4220 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4221 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4222 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4223 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4225 return fixed_bits_valid(val
, fixed0
, fixed1
);
4228 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4230 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4231 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4233 return fixed_bits_valid(val
, fixed0
, fixed1
);
4236 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4238 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4239 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4241 return fixed_bits_valid(val
, fixed0
, fixed1
);
4244 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4245 #define nested_guest_cr4_valid nested_cr4_valid
4246 #define nested_host_cr4_valid nested_cr4_valid
4248 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4250 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4252 struct kvm_vcpu
*vcpu
)
4254 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4255 vmx_decache_cr3(vcpu
);
4256 if (!(cr0
& X86_CR0_PG
)) {
4257 /* From paging/starting to nonpaging */
4258 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4259 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4260 (CPU_BASED_CR3_LOAD_EXITING
|
4261 CPU_BASED_CR3_STORE_EXITING
));
4262 vcpu
->arch
.cr0
= cr0
;
4263 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4264 } else if (!is_paging(vcpu
)) {
4265 /* From nonpaging to paging */
4266 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4267 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4268 ~(CPU_BASED_CR3_LOAD_EXITING
|
4269 CPU_BASED_CR3_STORE_EXITING
));
4270 vcpu
->arch
.cr0
= cr0
;
4271 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4274 if (!(cr0
& X86_CR0_WP
))
4275 *hw_cr0
&= ~X86_CR0_WP
;
4278 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4280 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4281 unsigned long hw_cr0
;
4283 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4284 if (enable_unrestricted_guest
)
4285 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4287 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4289 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4292 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4296 #ifdef CONFIG_X86_64
4297 if (vcpu
->arch
.efer
& EFER_LME
) {
4298 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4300 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4306 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4308 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4309 vmcs_writel(GUEST_CR0
, hw_cr0
);
4310 vcpu
->arch
.cr0
= cr0
;
4312 /* depends on vcpu->arch.cr0 to be set to a new value */
4313 vmx
->emulation_required
= emulation_required(vcpu
);
4316 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4318 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4323 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4325 u64 eptp
= VMX_EPTP_MT_WB
;
4327 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4329 if (enable_ept_ad_bits
&&
4330 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4331 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4332 eptp
|= (root_hpa
& PAGE_MASK
);
4337 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4339 unsigned long guest_cr3
;
4344 eptp
= construct_eptp(vcpu
, cr3
);
4345 vmcs_write64(EPT_POINTER
, eptp
);
4346 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4347 guest_cr3
= kvm_read_cr3(vcpu
);
4349 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4350 ept_load_pdptrs(vcpu
);
4353 vmx_flush_tlb(vcpu
);
4354 vmcs_writel(GUEST_CR3
, guest_cr3
);
4357 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4360 * Pass through host's Machine Check Enable value to hw_cr4, which
4361 * is in force while we are in guest mode. Do not let guests control
4362 * this bit, even if host CR4.MCE == 0.
4364 unsigned long hw_cr4
=
4365 (cr4_read_shadow() & X86_CR4_MCE
) |
4366 (cr4
& ~X86_CR4_MCE
) |
4367 (to_vmx(vcpu
)->rmode
.vm86_active
?
4368 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4370 if (cr4
& X86_CR4_VMXE
) {
4372 * To use VMXON (and later other VMX instructions), a guest
4373 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4374 * So basically the check on whether to allow nested VMX
4377 if (!nested_vmx_allowed(vcpu
))
4381 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4384 vcpu
->arch
.cr4
= cr4
;
4386 if (!is_paging(vcpu
)) {
4387 hw_cr4
&= ~X86_CR4_PAE
;
4388 hw_cr4
|= X86_CR4_PSE
;
4389 } else if (!(cr4
& X86_CR4_PAE
)) {
4390 hw_cr4
&= ~X86_CR4_PAE
;
4394 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4396 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4397 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4398 * to be manually disabled when guest switches to non-paging
4401 * If !enable_unrestricted_guest, the CPU is always running
4402 * with CR0.PG=1 and CR4 needs to be modified.
4403 * If enable_unrestricted_guest, the CPU automatically
4404 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4406 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4408 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4409 vmcs_writel(GUEST_CR4
, hw_cr4
);
4413 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4414 struct kvm_segment
*var
, int seg
)
4416 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4419 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4420 *var
= vmx
->rmode
.segs
[seg
];
4421 if (seg
== VCPU_SREG_TR
4422 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4424 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4425 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4428 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4429 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4430 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4431 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4432 var
->unusable
= (ar
>> 16) & 1;
4433 var
->type
= ar
& 15;
4434 var
->s
= (ar
>> 4) & 1;
4435 var
->dpl
= (ar
>> 5) & 3;
4437 * Some userspaces do not preserve unusable property. Since usable
4438 * segment has to be present according to VMX spec we can use present
4439 * property to amend userspace bug by making unusable segment always
4440 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4441 * segment as unusable.
4443 var
->present
= !var
->unusable
;
4444 var
->avl
= (ar
>> 12) & 1;
4445 var
->l
= (ar
>> 13) & 1;
4446 var
->db
= (ar
>> 14) & 1;
4447 var
->g
= (ar
>> 15) & 1;
4450 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4452 struct kvm_segment s
;
4454 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4455 vmx_get_segment(vcpu
, &s
, seg
);
4458 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4461 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4463 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4465 if (unlikely(vmx
->rmode
.vm86_active
))
4468 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4469 return VMX_AR_DPL(ar
);
4473 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4477 if (var
->unusable
|| !var
->present
)
4480 ar
= var
->type
& 15;
4481 ar
|= (var
->s
& 1) << 4;
4482 ar
|= (var
->dpl
& 3) << 5;
4483 ar
|= (var
->present
& 1) << 7;
4484 ar
|= (var
->avl
& 1) << 12;
4485 ar
|= (var
->l
& 1) << 13;
4486 ar
|= (var
->db
& 1) << 14;
4487 ar
|= (var
->g
& 1) << 15;
4493 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4494 struct kvm_segment
*var
, int seg
)
4496 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4497 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4499 vmx_segment_cache_clear(vmx
);
4501 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4502 vmx
->rmode
.segs
[seg
] = *var
;
4503 if (seg
== VCPU_SREG_TR
)
4504 vmcs_write16(sf
->selector
, var
->selector
);
4506 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4510 vmcs_writel(sf
->base
, var
->base
);
4511 vmcs_write32(sf
->limit
, var
->limit
);
4512 vmcs_write16(sf
->selector
, var
->selector
);
4515 * Fix the "Accessed" bit in AR field of segment registers for older
4517 * IA32 arch specifies that at the time of processor reset the
4518 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4519 * is setting it to 0 in the userland code. This causes invalid guest
4520 * state vmexit when "unrestricted guest" mode is turned on.
4521 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4522 * tree. Newer qemu binaries with that qemu fix would not need this
4525 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4526 var
->type
|= 0x1; /* Accessed */
4528 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4531 vmx
->emulation_required
= emulation_required(vcpu
);
4534 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4536 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4538 *db
= (ar
>> 14) & 1;
4539 *l
= (ar
>> 13) & 1;
4542 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4544 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4545 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4548 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4550 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4551 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4554 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4556 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4557 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4560 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4562 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4563 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4566 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4568 struct kvm_segment var
;
4571 vmx_get_segment(vcpu
, &var
, seg
);
4573 if (seg
== VCPU_SREG_CS
)
4575 ar
= vmx_segment_access_rights(&var
);
4577 if (var
.base
!= (var
.selector
<< 4))
4579 if (var
.limit
!= 0xffff)
4587 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4589 struct kvm_segment cs
;
4590 unsigned int cs_rpl
;
4592 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4593 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4597 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4601 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4602 if (cs
.dpl
> cs_rpl
)
4605 if (cs
.dpl
!= cs_rpl
)
4611 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4615 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4617 struct kvm_segment ss
;
4618 unsigned int ss_rpl
;
4620 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4621 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4625 if (ss
.type
!= 3 && ss
.type
!= 7)
4629 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4637 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4639 struct kvm_segment var
;
4642 vmx_get_segment(vcpu
, &var
, seg
);
4643 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4651 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4652 if (var
.dpl
< rpl
) /* DPL < RPL */
4656 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4662 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4664 struct kvm_segment tr
;
4666 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4670 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4672 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4680 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4682 struct kvm_segment ldtr
;
4684 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4688 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4698 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4700 struct kvm_segment cs
, ss
;
4702 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4703 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4705 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4706 (ss
.selector
& SEGMENT_RPL_MASK
));
4710 * Check if guest state is valid. Returns true if valid, false if
4712 * We assume that registers are always usable
4714 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4716 if (enable_unrestricted_guest
)
4719 /* real mode guest state checks */
4720 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4721 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4723 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4725 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4727 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4729 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4731 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4734 /* protected mode guest state checks */
4735 if (!cs_ss_rpl_check(vcpu
))
4737 if (!code_segment_valid(vcpu
))
4739 if (!stack_segment_valid(vcpu
))
4741 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4743 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4745 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4747 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4749 if (!tr_valid(vcpu
))
4751 if (!ldtr_valid(vcpu
))
4755 * - Add checks on RIP
4756 * - Add checks on RFLAGS
4762 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4764 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4767 static int init_rmode_tss(struct kvm
*kvm
)
4773 idx
= srcu_read_lock(&kvm
->srcu
);
4774 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4775 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4778 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4779 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4780 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4783 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4786 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4790 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4791 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4794 srcu_read_unlock(&kvm
->srcu
, idx
);
4798 static int init_rmode_identity_map(struct kvm
*kvm
)
4801 kvm_pfn_t identity_map_pfn
;
4804 /* Protect kvm->arch.ept_identity_pagetable_done. */
4805 mutex_lock(&kvm
->slots_lock
);
4807 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4810 if (!kvm
->arch
.ept_identity_map_addr
)
4811 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4812 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4814 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4815 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4819 idx
= srcu_read_lock(&kvm
->srcu
);
4820 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4823 /* Set up identity-mapping pagetable for EPT in real mode */
4824 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4825 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4826 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4827 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4828 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4832 kvm
->arch
.ept_identity_pagetable_done
= true;
4835 srcu_read_unlock(&kvm
->srcu
, idx
);
4838 mutex_unlock(&kvm
->slots_lock
);
4842 static void seg_setup(int seg
)
4844 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4847 vmcs_write16(sf
->selector
, 0);
4848 vmcs_writel(sf
->base
, 0);
4849 vmcs_write32(sf
->limit
, 0xffff);
4851 if (seg
== VCPU_SREG_CS
)
4852 ar
|= 0x08; /* code segment */
4854 vmcs_write32(sf
->ar_bytes
, ar
);
4857 static int alloc_apic_access_page(struct kvm
*kvm
)
4862 mutex_lock(&kvm
->slots_lock
);
4863 if (kvm
->arch
.apic_access_page_done
)
4865 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4866 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4870 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4871 if (is_error_page(page
)) {
4877 * Do not pin the page in memory, so that memory hot-unplug
4878 * is able to migrate it.
4881 kvm
->arch
.apic_access_page_done
= true;
4883 mutex_unlock(&kvm
->slots_lock
);
4887 static int allocate_vpid(void)
4893 spin_lock(&vmx_vpid_lock
);
4894 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4895 if (vpid
< VMX_NR_VPIDS
)
4896 __set_bit(vpid
, vmx_vpid_bitmap
);
4899 spin_unlock(&vmx_vpid_lock
);
4903 static void free_vpid(int vpid
)
4905 if (!enable_vpid
|| vpid
== 0)
4907 spin_lock(&vmx_vpid_lock
);
4908 __clear_bit(vpid
, vmx_vpid_bitmap
);
4909 spin_unlock(&vmx_vpid_lock
);
4912 #define MSR_TYPE_R 1
4913 #define MSR_TYPE_W 2
4914 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4917 int f
= sizeof(unsigned long);
4919 if (!cpu_has_vmx_msr_bitmap())
4923 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4924 * have the write-low and read-high bitmap offsets the wrong way round.
4925 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4927 if (msr
<= 0x1fff) {
4928 if (type
& MSR_TYPE_R
)
4930 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4932 if (type
& MSR_TYPE_W
)
4934 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4936 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4938 if (type
& MSR_TYPE_R
)
4940 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4942 if (type
& MSR_TYPE_W
)
4944 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4950 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4951 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4953 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4954 unsigned long *msr_bitmap_nested
,
4957 int f
= sizeof(unsigned long);
4959 if (!cpu_has_vmx_msr_bitmap()) {
4965 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4966 * have the write-low and read-high bitmap offsets the wrong way round.
4967 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4969 if (msr
<= 0x1fff) {
4970 if (type
& MSR_TYPE_R
&&
4971 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4973 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4975 if (type
& MSR_TYPE_W
&&
4976 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4978 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4980 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4982 if (type
& MSR_TYPE_R
&&
4983 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4985 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4987 if (type
& MSR_TYPE_W
&&
4988 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4990 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4995 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4998 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4999 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
5001 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5004 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5007 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5009 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5012 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5014 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5019 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5021 return enable_apicv
;
5024 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5026 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5030 * Don't need to mark the APIC access page dirty; it is never
5031 * written to by the CPU during APIC virtualization.
5034 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5035 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5036 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5039 if (nested_cpu_has_posted_intr(vmcs12
)) {
5040 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5041 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5046 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5048 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5053 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5056 vmx
->nested
.pi_pending
= false;
5057 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5060 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5061 if (max_irr
!= 256) {
5062 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5063 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5064 kunmap(vmx
->nested
.virtual_apic_page
);
5066 status
= vmcs_read16(GUEST_INTR_STATUS
);
5067 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5069 status
|= (u8
)max_irr
;
5070 vmcs_write16(GUEST_INTR_STATUS
, status
);
5074 nested_mark_vmcs12_pages_dirty(vcpu
);
5077 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5081 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5083 if (vcpu
->mode
== IN_GUEST_MODE
) {
5085 * The vector of interrupt to be delivered to vcpu had
5086 * been set in PIR before this function.
5088 * Following cases will be reached in this block, and
5089 * we always send a notification event in all cases as
5092 * Case 1: vcpu keeps in non-root mode. Sending a
5093 * notification event posts the interrupt to vcpu.
5095 * Case 2: vcpu exits to root mode and is still
5096 * runnable. PIR will be synced to vIRR before the
5097 * next vcpu entry. Sending a notification event in
5098 * this case has no effect, as vcpu is not in root
5101 * Case 3: vcpu exits to root mode and is blocked.
5102 * vcpu_block() has already synced PIR to vIRR and
5103 * never blocks vcpu if vIRR is not cleared. Therefore,
5104 * a blocked vcpu here does not wait for any requested
5105 * interrupts in PIR, and sending a notification event
5106 * which has no effect is safe here.
5109 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5116 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5119 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5121 if (is_guest_mode(vcpu
) &&
5122 vector
== vmx
->nested
.posted_intr_nv
) {
5123 /* the PIR and ON have been set by L1. */
5124 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5126 * If a posted intr is not recognized by hardware,
5127 * we will accomplish it in the next vmentry.
5129 vmx
->nested
.pi_pending
= true;
5130 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5136 * Send interrupt to vcpu via posted interrupt way.
5137 * 1. If target vcpu is running(non-root mode), send posted interrupt
5138 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5139 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5140 * interrupt from PIR in next vmentry.
5142 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5147 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5151 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5154 /* If a previous notification has sent the IPI, nothing to do. */
5155 if (pi_test_and_set_on(&vmx
->pi_desc
))
5158 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5159 kvm_vcpu_kick(vcpu
);
5163 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5164 * will not change in the lifetime of the guest.
5165 * Note that host-state that does change is set elsewhere. E.g., host-state
5166 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5168 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5173 unsigned long cr0
, cr3
, cr4
;
5176 WARN_ON(cr0
& X86_CR0_TS
);
5177 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5180 * Save the most likely value for this task's CR3 in the VMCS.
5181 * We can't use __get_current_cr3_fast() because we're not atomic.
5184 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5185 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5187 /* Save the most likely value for this task's CR4 in the VMCS. */
5188 cr4
= cr4_read_shadow();
5189 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5190 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5192 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5193 #ifdef CONFIG_X86_64
5195 * Load null selectors, so we can avoid reloading them in
5196 * __vmx_load_host_state(), in case userspace uses the null selectors
5197 * too (the expected case).
5199 vmcs_write16(HOST_DS_SELECTOR
, 0);
5200 vmcs_write16(HOST_ES_SELECTOR
, 0);
5202 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5203 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5205 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5206 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5209 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5210 vmx
->host_idt_base
= dt
.address
;
5212 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5214 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5215 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5216 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5217 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5219 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5220 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5221 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5225 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5227 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5229 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5230 if (is_guest_mode(&vmx
->vcpu
))
5231 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5232 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5233 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5236 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5238 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5240 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5241 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5244 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5246 /* Enable the preemption timer dynamically */
5247 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5248 return pin_based_exec_ctrl
;
5251 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5253 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5255 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5256 if (cpu_has_secondary_exec_ctrls()) {
5257 if (kvm_vcpu_apicv_active(vcpu
))
5258 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5259 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5260 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5262 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5263 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5264 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5267 if (cpu_has_vmx_msr_bitmap())
5268 vmx_set_msr_bitmap(vcpu
);
5271 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5273 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5275 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5276 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5278 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5279 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5280 #ifdef CONFIG_X86_64
5281 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5282 CPU_BASED_CR8_LOAD_EXITING
;
5286 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5287 CPU_BASED_CR3_LOAD_EXITING
|
5288 CPU_BASED_INVLPG_EXITING
;
5289 return exec_control
;
5292 static bool vmx_rdrand_supported(void)
5294 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5295 SECONDARY_EXEC_RDRAND_EXITING
;
5298 static bool vmx_rdseed_supported(void)
5300 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5301 SECONDARY_EXEC_RDSEED_EXITING
;
5304 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5306 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5308 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5309 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5310 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5312 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5314 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5315 enable_unrestricted_guest
= 0;
5316 /* Enable INVPCID for non-ept guests may cause performance regression. */
5317 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5319 if (!enable_unrestricted_guest
)
5320 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5322 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5323 if (!kvm_vcpu_apicv_active(vcpu
))
5324 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5325 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5326 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5327 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5329 We can NOT enable shadow_vmcs here because we don't have yet
5332 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5335 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5337 if (vmx_xsaves_supported()) {
5338 /* Exposing XSAVES only when XSAVE is exposed */
5339 bool xsaves_enabled
=
5340 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5341 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5343 if (!xsaves_enabled
)
5344 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5348 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5349 SECONDARY_EXEC_XSAVES
;
5351 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5352 ~SECONDARY_EXEC_XSAVES
;
5356 if (vmx_rdtscp_supported()) {
5357 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5358 if (!rdtscp_enabled
)
5359 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5363 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5364 SECONDARY_EXEC_RDTSCP
;
5366 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5367 ~SECONDARY_EXEC_RDTSCP
;
5371 if (vmx_invpcid_supported()) {
5372 /* Exposing INVPCID only when PCID is exposed */
5373 bool invpcid_enabled
=
5374 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5375 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5377 if (!invpcid_enabled
) {
5378 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5379 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5383 if (invpcid_enabled
)
5384 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5385 SECONDARY_EXEC_ENABLE_INVPCID
;
5387 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5388 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5392 if (vmx_rdrand_supported()) {
5393 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5395 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5399 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5400 SECONDARY_EXEC_RDRAND_EXITING
;
5402 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5403 ~SECONDARY_EXEC_RDRAND_EXITING
;
5407 if (vmx_rdseed_supported()) {
5408 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5410 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5414 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5415 SECONDARY_EXEC_RDSEED_EXITING
;
5417 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5418 ~SECONDARY_EXEC_RDSEED_EXITING
;
5422 vmx
->secondary_exec_control
= exec_control
;
5425 static void ept_set_mmio_spte_mask(void)
5428 * EPT Misconfigurations can be generated if the value of bits 2:0
5429 * of an EPT paging-structure entry is 110b (write/execute).
5431 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5432 VMX_EPT_MISCONFIG_WX_VALUE
);
5435 #define VMX_XSS_EXIT_BITMAP 0
5437 * Sets up the vmcs for emulated real mode.
5439 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5441 #ifdef CONFIG_X86_64
5447 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5448 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5450 if (enable_shadow_vmcs
) {
5451 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5452 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5454 if (cpu_has_vmx_msr_bitmap())
5455 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5457 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5460 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5461 vmx
->hv_deadline_tsc
= -1;
5463 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5465 if (cpu_has_secondary_exec_ctrls()) {
5466 vmx_compute_secondary_exec_control(vmx
);
5467 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5468 vmx
->secondary_exec_control
);
5471 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5472 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5473 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5474 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5475 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5477 vmcs_write16(GUEST_INTR_STATUS
, 0);
5479 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5480 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5484 vmcs_write32(PLE_GAP
, ple_gap
);
5485 vmx
->ple_window
= ple_window
;
5486 vmx
->ple_window_dirty
= true;
5489 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5490 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5491 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5493 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5494 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5495 vmx_set_constant_host_state(vmx
);
5496 #ifdef CONFIG_X86_64
5497 rdmsrl(MSR_FS_BASE
, a
);
5498 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5499 rdmsrl(MSR_GS_BASE
, a
);
5500 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5502 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5503 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5506 if (cpu_has_vmx_vmfunc())
5507 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5509 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5510 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5511 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5512 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5513 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5515 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5516 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5518 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5519 u32 index
= vmx_msr_index
[i
];
5520 u32 data_low
, data_high
;
5523 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5525 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5527 vmx
->guest_msrs
[j
].index
= i
;
5528 vmx
->guest_msrs
[j
].data
= 0;
5529 vmx
->guest_msrs
[j
].mask
= -1ull;
5534 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5536 /* 22.2.1, 20.8.1 */
5537 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5539 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5540 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5542 set_cr4_guest_host_mask(vmx
);
5544 if (vmx_xsaves_supported())
5545 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5548 ASSERT(vmx
->pml_pg
);
5549 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5550 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5554 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5556 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5557 struct msr_data apic_base_msr
;
5560 vmx
->rmode
.vm86_active
= 0;
5562 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5563 kvm_set_cr8(vcpu
, 0);
5566 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5567 MSR_IA32_APICBASE_ENABLE
;
5568 if (kvm_vcpu_is_reset_bsp(vcpu
))
5569 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5570 apic_base_msr
.host_initiated
= true;
5571 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5574 vmx_segment_cache_clear(vmx
);
5576 seg_setup(VCPU_SREG_CS
);
5577 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5578 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5580 seg_setup(VCPU_SREG_DS
);
5581 seg_setup(VCPU_SREG_ES
);
5582 seg_setup(VCPU_SREG_FS
);
5583 seg_setup(VCPU_SREG_GS
);
5584 seg_setup(VCPU_SREG_SS
);
5586 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5587 vmcs_writel(GUEST_TR_BASE
, 0);
5588 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5589 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5591 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5592 vmcs_writel(GUEST_LDTR_BASE
, 0);
5593 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5594 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5597 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5598 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5599 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5600 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5603 vmcs_writel(GUEST_RFLAGS
, 0x02);
5604 kvm_rip_write(vcpu
, 0xfff0);
5606 vmcs_writel(GUEST_GDTR_BASE
, 0);
5607 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5609 vmcs_writel(GUEST_IDTR_BASE
, 0);
5610 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5612 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5613 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5614 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5615 if (kvm_mpx_supported())
5616 vmcs_write64(GUEST_BNDCFGS
, 0);
5620 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5622 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5623 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5624 if (cpu_need_tpr_shadow(vcpu
))
5625 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5626 __pa(vcpu
->arch
.apic
->regs
));
5627 vmcs_write32(TPR_THRESHOLD
, 0);
5630 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5633 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5635 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5636 vmx
->vcpu
.arch
.cr0
= cr0
;
5637 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5638 vmx_set_cr4(vcpu
, 0);
5639 vmx_set_efer(vcpu
, 0);
5641 update_exception_bitmap(vcpu
);
5643 vpid_sync_context(vmx
->vpid
);
5647 * In nested virtualization, check if L1 asked to exit on external interrupts.
5648 * For most existing hypervisors, this will always return true.
5650 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5652 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5653 PIN_BASED_EXT_INTR_MASK
;
5657 * In nested virtualization, check if L1 has set
5658 * VM_EXIT_ACK_INTR_ON_EXIT
5660 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5662 return get_vmcs12(vcpu
)->vm_exit_controls
&
5663 VM_EXIT_ACK_INTR_ON_EXIT
;
5666 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5668 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5669 PIN_BASED_NMI_EXITING
;
5672 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5674 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5675 CPU_BASED_VIRTUAL_INTR_PENDING
);
5678 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5681 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5682 enable_irq_window(vcpu
);
5686 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5687 CPU_BASED_VIRTUAL_NMI_PENDING
);
5690 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5692 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5694 int irq
= vcpu
->arch
.interrupt
.nr
;
5696 trace_kvm_inj_virq(irq
);
5698 ++vcpu
->stat
.irq_injections
;
5699 if (vmx
->rmode
.vm86_active
) {
5701 if (vcpu
->arch
.interrupt
.soft
)
5702 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5703 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5704 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5707 intr
= irq
| INTR_INFO_VALID_MASK
;
5708 if (vcpu
->arch
.interrupt
.soft
) {
5709 intr
|= INTR_TYPE_SOFT_INTR
;
5710 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5711 vmx
->vcpu
.arch
.event_exit_inst_len
);
5713 intr
|= INTR_TYPE_EXT_INTR
;
5714 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5717 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5719 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5723 * Tracking the NMI-blocked state in software is built upon
5724 * finding the next open IRQ window. This, in turn, depends on
5725 * well-behaving guests: They have to keep IRQs disabled at
5726 * least as long as the NMI handler runs. Otherwise we may
5727 * cause NMI nesting, maybe breaking the guest. But as this is
5728 * highly unlikely, we can live with the residual risk.
5730 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5731 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5734 ++vcpu
->stat
.nmi_injections
;
5735 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5737 if (vmx
->rmode
.vm86_active
) {
5738 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5739 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5743 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5744 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5747 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5749 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5753 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5754 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5756 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5757 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5761 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5763 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5766 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5767 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5768 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5771 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5773 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5774 GUEST_INTR_STATE_NMI
);
5776 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5777 GUEST_INTR_STATE_NMI
);
5781 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5783 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5787 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
5790 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5791 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5792 | GUEST_INTR_STATE_NMI
));
5795 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5797 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5798 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5799 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5800 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5803 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5807 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5811 kvm
->arch
.tss_addr
= addr
;
5812 return init_rmode_tss(kvm
);
5815 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5820 * Update instruction length as we may reinject the exception
5821 * from user space while in guest debugging mode.
5823 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5824 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5825 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5829 if (vcpu
->guest_debug
&
5830 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5847 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5848 int vec
, u32 err_code
)
5851 * Instruction with address size override prefix opcode 0x67
5852 * Cause the #SS fault with 0 error code in VM86 mode.
5854 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5855 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5856 if (vcpu
->arch
.halt_request
) {
5857 vcpu
->arch
.halt_request
= 0;
5858 return kvm_vcpu_halt(vcpu
);
5866 * Forward all other exceptions that are valid in real mode.
5867 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5868 * the required debugging infrastructure rework.
5870 kvm_queue_exception(vcpu
, vec
);
5875 * Trigger machine check on the host. We assume all the MSRs are already set up
5876 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5877 * We pass a fake environment to the machine check handler because we want
5878 * the guest to be always treated like user space, no matter what context
5879 * it used internally.
5881 static void kvm_machine_check(void)
5883 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5884 struct pt_regs regs
= {
5885 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5886 .flags
= X86_EFLAGS_IF
,
5889 do_machine_check(®s
, 0);
5893 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5895 /* already handled by vcpu_run */
5899 static int handle_exception(struct kvm_vcpu
*vcpu
)
5901 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5902 struct kvm_run
*kvm_run
= vcpu
->run
;
5903 u32 intr_info
, ex_no
, error_code
;
5904 unsigned long cr2
, rip
, dr6
;
5906 enum emulation_result er
;
5908 vect_info
= vmx
->idt_vectoring_info
;
5909 intr_info
= vmx
->exit_intr_info
;
5911 if (is_machine_check(intr_info
))
5912 return handle_machine_check(vcpu
);
5914 if (is_nmi(intr_info
))
5915 return 1; /* already handled by vmx_vcpu_run() */
5917 if (is_invalid_opcode(intr_info
)) {
5918 if (is_guest_mode(vcpu
)) {
5919 kvm_queue_exception(vcpu
, UD_VECTOR
);
5922 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5923 if (er
!= EMULATE_DONE
)
5924 kvm_queue_exception(vcpu
, UD_VECTOR
);
5929 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5930 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5933 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5934 * MMIO, it is better to report an internal error.
5935 * See the comments in vmx_handle_exit.
5937 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5938 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5939 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5940 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5941 vcpu
->run
->internal
.ndata
= 3;
5942 vcpu
->run
->internal
.data
[0] = vect_info
;
5943 vcpu
->run
->internal
.data
[1] = intr_info
;
5944 vcpu
->run
->internal
.data
[2] = error_code
;
5948 if (is_page_fault(intr_info
)) {
5949 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5950 /* EPT won't cause page fault directly */
5951 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5952 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
5955 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5957 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5958 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5962 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5965 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5966 if (!(vcpu
->guest_debug
&
5967 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5968 vcpu
->arch
.dr6
&= ~15;
5969 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5970 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5971 skip_emulated_instruction(vcpu
);
5973 kvm_queue_exception(vcpu
, DB_VECTOR
);
5976 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5977 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5981 * Update instruction length as we may reinject #BP from
5982 * user space while in guest debugging mode. Reading it for
5983 * #DB as well causes no harm, it is not used in that case.
5985 vmx
->vcpu
.arch
.event_exit_inst_len
=
5986 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5987 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5988 rip
= kvm_rip_read(vcpu
);
5989 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5990 kvm_run
->debug
.arch
.exception
= ex_no
;
5993 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5994 kvm_run
->ex
.exception
= ex_no
;
5995 kvm_run
->ex
.error_code
= error_code
;
6001 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6003 ++vcpu
->stat
.irq_exits
;
6007 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6009 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6010 vcpu
->mmio_needed
= 0;
6014 static int handle_io(struct kvm_vcpu
*vcpu
)
6016 unsigned long exit_qualification
;
6017 int size
, in
, string
, ret
;
6020 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6021 string
= (exit_qualification
& 16) != 0;
6022 in
= (exit_qualification
& 8) != 0;
6024 ++vcpu
->stat
.io_exits
;
6027 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6029 port
= exit_qualification
>> 16;
6030 size
= (exit_qualification
& 7) + 1;
6032 ret
= kvm_skip_emulated_instruction(vcpu
);
6035 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6036 * KVM_EXIT_DEBUG here.
6038 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6042 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6045 * Patch in the VMCALL instruction:
6047 hypercall
[0] = 0x0f;
6048 hypercall
[1] = 0x01;
6049 hypercall
[2] = 0xc1;
6052 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6053 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6055 if (is_guest_mode(vcpu
)) {
6056 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6057 unsigned long orig_val
= val
;
6060 * We get here when L2 changed cr0 in a way that did not change
6061 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6062 * but did change L0 shadowed bits. So we first calculate the
6063 * effective cr0 value that L1 would like to write into the
6064 * hardware. It consists of the L2-owned bits from the new
6065 * value combined with the L1-owned bits from L1's guest_cr0.
6067 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6068 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6070 if (!nested_guest_cr0_valid(vcpu
, val
))
6073 if (kvm_set_cr0(vcpu
, val
))
6075 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6078 if (to_vmx(vcpu
)->nested
.vmxon
&&
6079 !nested_host_cr0_valid(vcpu
, val
))
6082 return kvm_set_cr0(vcpu
, val
);
6086 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6088 if (is_guest_mode(vcpu
)) {
6089 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6090 unsigned long orig_val
= val
;
6092 /* analogously to handle_set_cr0 */
6093 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6094 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6095 if (kvm_set_cr4(vcpu
, val
))
6097 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6100 return kvm_set_cr4(vcpu
, val
);
6103 static int handle_cr(struct kvm_vcpu
*vcpu
)
6105 unsigned long exit_qualification
, val
;
6111 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6112 cr
= exit_qualification
& 15;
6113 reg
= (exit_qualification
>> 8) & 15;
6114 switch ((exit_qualification
>> 4) & 3) {
6115 case 0: /* mov to cr */
6116 val
= kvm_register_readl(vcpu
, reg
);
6117 trace_kvm_cr_write(cr
, val
);
6120 err
= handle_set_cr0(vcpu
, val
);
6121 return kvm_complete_insn_gp(vcpu
, err
);
6123 err
= kvm_set_cr3(vcpu
, val
);
6124 return kvm_complete_insn_gp(vcpu
, err
);
6126 err
= handle_set_cr4(vcpu
, val
);
6127 return kvm_complete_insn_gp(vcpu
, err
);
6129 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6131 err
= kvm_set_cr8(vcpu
, cr8
);
6132 ret
= kvm_complete_insn_gp(vcpu
, err
);
6133 if (lapic_in_kernel(vcpu
))
6135 if (cr8_prev
<= cr8
)
6138 * TODO: we might be squashing a
6139 * KVM_GUESTDBG_SINGLESTEP-triggered
6140 * KVM_EXIT_DEBUG here.
6142 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6148 WARN_ONCE(1, "Guest should always own CR0.TS");
6149 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6150 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6151 return kvm_skip_emulated_instruction(vcpu
);
6152 case 1: /*mov from cr*/
6155 val
= kvm_read_cr3(vcpu
);
6156 kvm_register_write(vcpu
, reg
, val
);
6157 trace_kvm_cr_read(cr
, val
);
6158 return kvm_skip_emulated_instruction(vcpu
);
6160 val
= kvm_get_cr8(vcpu
);
6161 kvm_register_write(vcpu
, reg
, val
);
6162 trace_kvm_cr_read(cr
, val
);
6163 return kvm_skip_emulated_instruction(vcpu
);
6167 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6168 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6169 kvm_lmsw(vcpu
, val
);
6171 return kvm_skip_emulated_instruction(vcpu
);
6175 vcpu
->run
->exit_reason
= 0;
6176 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6177 (int)(exit_qualification
>> 4) & 3, cr
);
6181 static int handle_dr(struct kvm_vcpu
*vcpu
)
6183 unsigned long exit_qualification
;
6186 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6187 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6189 /* First, if DR does not exist, trigger UD */
6190 if (!kvm_require_dr(vcpu
, dr
))
6193 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6194 if (!kvm_require_cpl(vcpu
, 0))
6196 dr7
= vmcs_readl(GUEST_DR7
);
6199 * As the vm-exit takes precedence over the debug trap, we
6200 * need to emulate the latter, either for the host or the
6201 * guest debugging itself.
6203 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6204 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6205 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6206 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6207 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6208 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6211 vcpu
->arch
.dr6
&= ~15;
6212 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6213 kvm_queue_exception(vcpu
, DB_VECTOR
);
6218 if (vcpu
->guest_debug
== 0) {
6219 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6220 CPU_BASED_MOV_DR_EXITING
);
6223 * No more DR vmexits; force a reload of the debug registers
6224 * and reenter on this instruction. The next vmexit will
6225 * retrieve the full state of the debug registers.
6227 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6231 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6232 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6235 if (kvm_get_dr(vcpu
, dr
, &val
))
6237 kvm_register_write(vcpu
, reg
, val
);
6239 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6242 return kvm_skip_emulated_instruction(vcpu
);
6245 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6247 return vcpu
->arch
.dr6
;
6250 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6254 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6256 get_debugreg(vcpu
->arch
.db
[0], 0);
6257 get_debugreg(vcpu
->arch
.db
[1], 1);
6258 get_debugreg(vcpu
->arch
.db
[2], 2);
6259 get_debugreg(vcpu
->arch
.db
[3], 3);
6260 get_debugreg(vcpu
->arch
.dr6
, 6);
6261 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6263 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6264 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6267 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6269 vmcs_writel(GUEST_DR7
, val
);
6272 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6274 return kvm_emulate_cpuid(vcpu
);
6277 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6279 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6280 struct msr_data msr_info
;
6282 msr_info
.index
= ecx
;
6283 msr_info
.host_initiated
= false;
6284 if (vmx_get_msr(vcpu
, &msr_info
)) {
6285 trace_kvm_msr_read_ex(ecx
);
6286 kvm_inject_gp(vcpu
, 0);
6290 trace_kvm_msr_read(ecx
, msr_info
.data
);
6292 /* FIXME: handling of bits 32:63 of rax, rdx */
6293 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6294 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6295 return kvm_skip_emulated_instruction(vcpu
);
6298 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6300 struct msr_data msr
;
6301 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6302 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6303 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6307 msr
.host_initiated
= false;
6308 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6309 trace_kvm_msr_write_ex(ecx
, data
);
6310 kvm_inject_gp(vcpu
, 0);
6314 trace_kvm_msr_write(ecx
, data
);
6315 return kvm_skip_emulated_instruction(vcpu
);
6318 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6320 kvm_apic_update_ppr(vcpu
);
6324 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6326 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6327 CPU_BASED_VIRTUAL_INTR_PENDING
);
6329 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6331 ++vcpu
->stat
.irq_window_exits
;
6335 static int handle_halt(struct kvm_vcpu
*vcpu
)
6337 return kvm_emulate_halt(vcpu
);
6340 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6342 return kvm_emulate_hypercall(vcpu
);
6345 static int handle_invd(struct kvm_vcpu
*vcpu
)
6347 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6350 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6352 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6354 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6355 return kvm_skip_emulated_instruction(vcpu
);
6358 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6362 err
= kvm_rdpmc(vcpu
);
6363 return kvm_complete_insn_gp(vcpu
, err
);
6366 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6368 return kvm_emulate_wbinvd(vcpu
);
6371 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6373 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6374 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6376 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6377 return kvm_skip_emulated_instruction(vcpu
);
6381 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6383 kvm_skip_emulated_instruction(vcpu
);
6384 WARN(1, "this should never happen\n");
6388 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6390 kvm_skip_emulated_instruction(vcpu
);
6391 WARN(1, "this should never happen\n");
6395 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6397 if (likely(fasteoi
)) {
6398 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6399 int access_type
, offset
;
6401 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6402 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6404 * Sane guest uses MOV to write EOI, with written value
6405 * not cared. So make a short-circuit here by avoiding
6406 * heavy instruction emulation.
6408 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6409 (offset
== APIC_EOI
)) {
6410 kvm_lapic_set_eoi(vcpu
);
6411 return kvm_skip_emulated_instruction(vcpu
);
6414 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6417 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6419 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6420 int vector
= exit_qualification
& 0xff;
6422 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6423 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6427 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6429 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6430 u32 offset
= exit_qualification
& 0xfff;
6432 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6433 kvm_apic_write_nodecode(vcpu
, offset
);
6437 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6439 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6440 unsigned long exit_qualification
;
6441 bool has_error_code
= false;
6444 int reason
, type
, idt_v
, idt_index
;
6446 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6447 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6448 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6450 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6452 reason
= (u32
)exit_qualification
>> 30;
6453 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6455 case INTR_TYPE_NMI_INTR
:
6456 vcpu
->arch
.nmi_injected
= false;
6457 vmx_set_nmi_mask(vcpu
, true);
6459 case INTR_TYPE_EXT_INTR
:
6460 case INTR_TYPE_SOFT_INTR
:
6461 kvm_clear_interrupt_queue(vcpu
);
6463 case INTR_TYPE_HARD_EXCEPTION
:
6464 if (vmx
->idt_vectoring_info
&
6465 VECTORING_INFO_DELIVER_CODE_MASK
) {
6466 has_error_code
= true;
6468 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6471 case INTR_TYPE_SOFT_EXCEPTION
:
6472 kvm_clear_exception_queue(vcpu
);
6478 tss_selector
= exit_qualification
;
6480 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6481 type
!= INTR_TYPE_EXT_INTR
&&
6482 type
!= INTR_TYPE_NMI_INTR
))
6483 skip_emulated_instruction(vcpu
);
6485 if (kvm_task_switch(vcpu
, tss_selector
,
6486 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6487 has_error_code
, error_code
) == EMULATE_FAIL
) {
6488 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6489 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6490 vcpu
->run
->internal
.ndata
= 0;
6495 * TODO: What about debug traps on tss switch?
6496 * Are we supposed to inject them and update dr6?
6502 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6504 unsigned long exit_qualification
;
6508 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6511 * EPT violation happened while executing iret from NMI,
6512 * "blocked by NMI" bit has to be set before next VM entry.
6513 * There are errata that may cause this bit to not be set:
6516 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6518 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6519 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6521 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6522 trace_kvm_page_fault(gpa
, exit_qualification
);
6524 /* Is it a read fault? */
6525 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6526 ? PFERR_USER_MASK
: 0;
6527 /* Is it a write fault? */
6528 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6529 ? PFERR_WRITE_MASK
: 0;
6530 /* Is it a fetch fault? */
6531 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6532 ? PFERR_FETCH_MASK
: 0;
6533 /* ept page table entry is present? */
6534 error_code
|= (exit_qualification
&
6535 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6536 EPT_VIOLATION_EXECUTABLE
))
6537 ? PFERR_PRESENT_MASK
: 0;
6539 error_code
|= (exit_qualification
& 0x100) != 0 ?
6540 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6542 vcpu
->arch
.exit_qualification
= exit_qualification
;
6543 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6546 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6552 * A nested guest cannot optimize MMIO vmexits, because we have an
6553 * nGPA here instead of the required GPA.
6555 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6556 if (!is_guest_mode(vcpu
) &&
6557 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6558 trace_kvm_fast_mmio(gpa
);
6559 return kvm_skip_emulated_instruction(vcpu
);
6562 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6566 /* It is the real ept misconfig */
6569 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6570 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6575 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6577 WARN_ON_ONCE(!enable_vnmi
);
6578 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6579 CPU_BASED_VIRTUAL_NMI_PENDING
);
6580 ++vcpu
->stat
.nmi_window_exits
;
6581 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6586 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6589 enum emulation_result err
= EMULATE_DONE
;
6592 bool intr_window_requested
;
6593 unsigned count
= 130;
6595 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6596 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6598 while (vmx
->emulation_required
&& count
-- != 0) {
6599 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6600 return handle_interrupt_window(&vmx
->vcpu
);
6602 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6605 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6607 if (err
== EMULATE_USER_EXIT
) {
6608 ++vcpu
->stat
.mmio_exits
;
6613 if (err
!= EMULATE_DONE
) {
6614 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6615 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6616 vcpu
->run
->internal
.ndata
= 0;
6620 if (vcpu
->arch
.halt_request
) {
6621 vcpu
->arch
.halt_request
= 0;
6622 ret
= kvm_vcpu_halt(vcpu
);
6626 if (signal_pending(current
))
6636 static int __grow_ple_window(int val
)
6638 if (ple_window_grow
< 1)
6641 val
= min(val
, ple_window_actual_max
);
6643 if (ple_window_grow
< ple_window
)
6644 val
*= ple_window_grow
;
6646 val
+= ple_window_grow
;
6651 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6656 if (modifier
< ple_window
)
6661 return max(val
, minimum
);
6664 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6666 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6667 int old
= vmx
->ple_window
;
6669 vmx
->ple_window
= __grow_ple_window(old
);
6671 if (vmx
->ple_window
!= old
)
6672 vmx
->ple_window_dirty
= true;
6674 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6677 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6679 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6680 int old
= vmx
->ple_window
;
6682 vmx
->ple_window
= __shrink_ple_window(old
,
6683 ple_window_shrink
, ple_window
);
6685 if (vmx
->ple_window
!= old
)
6686 vmx
->ple_window_dirty
= true;
6688 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6692 * ple_window_actual_max is computed to be one grow_ple_window() below
6693 * ple_window_max. (See __grow_ple_window for the reason.)
6694 * This prevents overflows, because ple_window_max is int.
6695 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6697 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6699 static void update_ple_window_actual_max(void)
6701 ple_window_actual_max
=
6702 __shrink_ple_window(max(ple_window_max
, ple_window
),
6703 ple_window_grow
, INT_MIN
);
6707 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6709 static void wakeup_handler(void)
6711 struct kvm_vcpu
*vcpu
;
6712 int cpu
= smp_processor_id();
6714 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6715 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6716 blocked_vcpu_list
) {
6717 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6719 if (pi_test_on(pi_desc
) == 1)
6720 kvm_vcpu_kick(vcpu
);
6722 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6725 void vmx_enable_tdp(void)
6727 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6728 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6729 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6730 0ull, VMX_EPT_EXECUTABLE_MASK
,
6731 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6732 VMX_EPT_RWX_MASK
, 0ull);
6734 ept_set_mmio_spte_mask();
6738 static __init
int hardware_setup(void)
6740 int r
= -ENOMEM
, i
, msr
;
6742 rdmsrl_safe(MSR_EFER
, &host_efer
);
6744 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6745 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6747 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6748 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6753 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6754 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6755 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6758 * Allow direct access to the PC debug port (it is often used for I/O
6759 * delays, but the vmexits simply slow things down).
6761 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6762 clear_bit(0x80, vmx_io_bitmap_a
);
6764 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6766 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6767 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6769 if (setup_vmcs_config(&vmcs_config
) < 0) {
6774 if (boot_cpu_has(X86_FEATURE_NX
))
6775 kvm_enable_efer_bits(EFER_NX
);
6777 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6778 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6781 if (!cpu_has_vmx_shadow_vmcs())
6782 enable_shadow_vmcs
= 0;
6783 if (enable_shadow_vmcs
)
6784 init_vmcs_shadow_fields();
6786 if (!cpu_has_vmx_ept() ||
6787 !cpu_has_vmx_ept_4levels() ||
6788 !cpu_has_vmx_ept_mt_wb() ||
6789 !cpu_has_vmx_invept_global())
6792 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6793 enable_ept_ad_bits
= 0;
6795 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
6796 enable_unrestricted_guest
= 0;
6798 if (!cpu_has_vmx_flexpriority())
6799 flexpriority_enabled
= 0;
6801 if (!cpu_has_virtual_nmis())
6805 * set_apic_access_page_addr() is used to reload apic access
6806 * page upon invalidation. No need to do anything if not
6807 * using the APIC_ACCESS_ADDR VMCS field.
6809 if (!flexpriority_enabled
)
6810 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6812 if (!cpu_has_vmx_tpr_shadow())
6813 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6815 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6816 kvm_disable_largepages();
6818 if (!cpu_has_vmx_ple()) {
6821 ple_window_grow
= 0;
6823 ple_window_shrink
= 0;
6826 if (!cpu_has_vmx_apicv()) {
6828 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6831 if (cpu_has_vmx_tsc_scaling()) {
6832 kvm_has_tsc_control
= true;
6833 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6834 kvm_tsc_scaling_ratio_frac_bits
= 48;
6837 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6838 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6839 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6840 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6841 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6842 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6844 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6845 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6846 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6847 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6848 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6849 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6850 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6851 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6853 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6855 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6856 if (msr
== 0x839 /* TMCCT */)
6858 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6862 * TPR reads and writes can be virtualized even if virtual interrupt
6863 * delivery is not in use.
6865 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6866 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6869 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6871 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6878 update_ple_window_actual_max();
6881 * Only enable PML when hardware supports PML feature, and both EPT
6882 * and EPT A/D bit features are enabled -- PML depends on them to work.
6884 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6888 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6889 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6890 kvm_x86_ops
->flush_log_dirty
= NULL
;
6891 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6894 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6897 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6898 cpu_preemption_timer_multi
=
6899 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6901 kvm_x86_ops
->set_hv_timer
= NULL
;
6902 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6905 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6907 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6909 return alloc_kvm_area();
6912 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6913 free_page((unsigned long)vmx_bitmap
[i
]);
6918 static __exit
void hardware_unsetup(void)
6922 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6923 free_page((unsigned long)vmx_bitmap
[i
]);
6929 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6930 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6932 static int handle_pause(struct kvm_vcpu
*vcpu
)
6935 grow_ple_window(vcpu
);
6938 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6939 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6940 * never set PAUSE_EXITING and just set PLE if supported,
6941 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6943 kvm_vcpu_on_spin(vcpu
, true);
6944 return kvm_skip_emulated_instruction(vcpu
);
6947 static int handle_nop(struct kvm_vcpu
*vcpu
)
6949 return kvm_skip_emulated_instruction(vcpu
);
6952 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6954 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6955 return handle_nop(vcpu
);
6958 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6960 kvm_queue_exception(vcpu
, UD_VECTOR
);
6964 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6969 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6971 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6972 return handle_nop(vcpu
);
6976 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6977 * We could reuse a single VMCS for all the L2 guests, but we also want the
6978 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6979 * allows keeping them loaded on the processor, and in the future will allow
6980 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6981 * every entry if they never change.
6982 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6983 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6985 * The following functions allocate and free a vmcs02 in this pool.
6988 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6989 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6991 struct vmcs02_list
*item
;
6992 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6993 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6994 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6995 return &item
->vmcs02
;
6998 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6999 /* Recycle the least recently used VMCS. */
7000 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
7001 struct vmcs02_list
, list
);
7002 item
->vmptr
= vmx
->nested
.current_vmptr
;
7003 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
7004 return &item
->vmcs02
;
7007 /* Create a new VMCS */
7008 item
= kzalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
7011 item
->vmcs02
.vmcs
= alloc_vmcs();
7012 item
->vmcs02
.shadow_vmcs
= NULL
;
7013 if (!item
->vmcs02
.vmcs
) {
7017 loaded_vmcs_init(&item
->vmcs02
);
7018 item
->vmptr
= vmx
->nested
.current_vmptr
;
7019 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
7020 vmx
->nested
.vmcs02_num
++;
7021 return &item
->vmcs02
;
7024 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
7025 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7027 struct vmcs02_list
*item
;
7028 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
7029 if (item
->vmptr
== vmptr
) {
7030 free_loaded_vmcs(&item
->vmcs02
);
7031 list_del(&item
->list
);
7033 vmx
->nested
.vmcs02_num
--;
7039 * Free all VMCSs saved for this vcpu, except the one pointed by
7040 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7041 * must be &vmx->vmcs01.
7043 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
7045 struct vmcs02_list
*item
, *n
;
7047 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7048 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7050 * Something will leak if the above WARN triggers. Better than
7053 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7056 free_loaded_vmcs(&item
->vmcs02
);
7057 list_del(&item
->list
);
7059 vmx
->nested
.vmcs02_num
--;
7064 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7065 * set the success or error code of an emulated VMX instruction, as specified
7066 * by Vol 2B, VMX Instruction Reference, "Conventions".
7068 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7070 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7071 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7072 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7075 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7077 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7078 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7079 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7083 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7084 u32 vm_instruction_error
)
7086 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7088 * failValid writes the error number to the current VMCS, which
7089 * can't be done there isn't a current VMCS.
7091 nested_vmx_failInvalid(vcpu
);
7094 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7095 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7096 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7098 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7100 * We don't need to force a shadow sync because
7101 * VM_INSTRUCTION_ERROR is not shadowed
7105 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7107 /* TODO: not to reset guest simply here. */
7108 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7109 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7112 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7114 struct vcpu_vmx
*vmx
=
7115 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7117 vmx
->nested
.preemption_timer_expired
= true;
7118 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7119 kvm_vcpu_kick(&vmx
->vcpu
);
7121 return HRTIMER_NORESTART
;
7125 * Decode the memory-address operand of a vmx instruction, as recorded on an
7126 * exit caused by such an instruction (run by a guest hypervisor).
7127 * On success, returns 0. When the operand is invalid, returns 1 and throws
7130 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7131 unsigned long exit_qualification
,
7132 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7136 struct kvm_segment s
;
7139 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7140 * Execution", on an exit, vmx_instruction_info holds most of the
7141 * addressing components of the operand. Only the displacement part
7142 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7143 * For how an actual address is calculated from all these components,
7144 * refer to Vol. 1, "Operand Addressing".
7146 int scaling
= vmx_instruction_info
& 3;
7147 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7148 bool is_reg
= vmx_instruction_info
& (1u << 10);
7149 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7150 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7151 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7152 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7153 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7156 kvm_queue_exception(vcpu
, UD_VECTOR
);
7160 /* Addr = segment_base + offset */
7161 /* offset = base + [index * scale] + displacement */
7162 off
= exit_qualification
; /* holds the displacement */
7164 off
+= kvm_register_read(vcpu
, base_reg
);
7166 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7167 vmx_get_segment(vcpu
, &s
, seg_reg
);
7168 *ret
= s
.base
+ off
;
7170 if (addr_size
== 1) /* 32 bit */
7173 /* Checks for #GP/#SS exceptions. */
7175 if (is_long_mode(vcpu
)) {
7176 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7177 * non-canonical form. This is the only check on the memory
7178 * destination for long mode!
7180 exn
= is_noncanonical_address(*ret
, vcpu
);
7181 } else if (is_protmode(vcpu
)) {
7182 /* Protected mode: apply checks for segment validity in the
7184 * - segment type check (#GP(0) may be thrown)
7185 * - usability check (#GP(0)/#SS(0))
7186 * - limit check (#GP(0)/#SS(0))
7189 /* #GP(0) if the destination operand is located in a
7190 * read-only data segment or any code segment.
7192 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7194 /* #GP(0) if the source operand is located in an
7195 * execute-only code segment
7197 exn
= ((s
.type
& 0xa) == 8);
7199 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7202 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7204 exn
= (s
.unusable
!= 0);
7205 /* Protected mode: #GP(0)/#SS(0) if the memory
7206 * operand is outside the segment limit.
7208 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7211 kvm_queue_exception_e(vcpu
,
7212 seg_reg
== VCPU_SREG_SS
?
7213 SS_VECTOR
: GP_VECTOR
,
7221 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7224 struct x86_exception e
;
7226 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7227 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7230 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7231 sizeof(*vmpointer
), &e
)) {
7232 kvm_inject_page_fault(vcpu
, &e
);
7239 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7242 struct vmcs
*shadow_vmcs
;
7244 if (cpu_has_vmx_msr_bitmap()) {
7245 vmx
->nested
.msr_bitmap
=
7246 (unsigned long *)__get_free_page(GFP_KERNEL
);
7247 if (!vmx
->nested
.msr_bitmap
)
7248 goto out_msr_bitmap
;
7251 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7252 if (!vmx
->nested
.cached_vmcs12
)
7253 goto out_cached_vmcs12
;
7255 if (enable_shadow_vmcs
) {
7256 shadow_vmcs
= alloc_vmcs();
7258 goto out_shadow_vmcs
;
7259 /* mark vmcs as shadow */
7260 shadow_vmcs
->revision_id
|= (1u << 31);
7261 /* init shadow vmcs */
7262 vmcs_clear(shadow_vmcs
);
7263 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7266 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7267 vmx
->nested
.vmcs02_num
= 0;
7269 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7270 HRTIMER_MODE_REL_PINNED
);
7271 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7273 vmx
->nested
.vmxon
= true;
7277 kfree(vmx
->nested
.cached_vmcs12
);
7280 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7287 * Emulate the VMXON instruction.
7288 * Currently, we just remember that VMX is active, and do not save or even
7289 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7290 * do not currently need to store anything in that guest-allocated memory
7291 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7292 * argument is different from the VMXON pointer (which the spec says they do).
7294 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7299 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7300 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7301 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7304 * The Intel VMX Instruction Reference lists a bunch of bits that are
7305 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7306 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7307 * Otherwise, we should fail with #UD. But most faulting conditions
7308 * have already been checked by hardware, prior to the VM-exit for
7309 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7310 * that bit set to 1 in non-root mode.
7312 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7313 kvm_queue_exception(vcpu
, UD_VECTOR
);
7317 if (vmx
->nested
.vmxon
) {
7318 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7319 return kvm_skip_emulated_instruction(vcpu
);
7322 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7323 != VMXON_NEEDED_FEATURES
) {
7324 kvm_inject_gp(vcpu
, 0);
7328 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7333 * The first 4 bytes of VMXON region contain the supported
7334 * VMCS revision identifier
7336 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7337 * which replaces physical address width with 32
7339 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7340 nested_vmx_failInvalid(vcpu
);
7341 return kvm_skip_emulated_instruction(vcpu
);
7344 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7345 if (is_error_page(page
)) {
7346 nested_vmx_failInvalid(vcpu
);
7347 return kvm_skip_emulated_instruction(vcpu
);
7349 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7351 kvm_release_page_clean(page
);
7352 nested_vmx_failInvalid(vcpu
);
7353 return kvm_skip_emulated_instruction(vcpu
);
7356 kvm_release_page_clean(page
);
7358 vmx
->nested
.vmxon_ptr
= vmptr
;
7359 ret
= enter_vmx_operation(vcpu
);
7363 nested_vmx_succeed(vcpu
);
7364 return kvm_skip_emulated_instruction(vcpu
);
7368 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7369 * for running VMX instructions (except VMXON, whose prerequisites are
7370 * slightly different). It also specifies what exception to inject otherwise.
7371 * Note that many of these exceptions have priority over VM exits, so they
7372 * don't have to be checked again here.
7374 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7376 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7377 kvm_queue_exception(vcpu
, UD_VECTOR
);
7383 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7385 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7386 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7389 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7391 if (vmx
->nested
.current_vmptr
== -1ull)
7394 if (enable_shadow_vmcs
) {
7395 /* copy to memory all shadowed fields in case
7396 they were modified */
7397 copy_shadow_to_vmcs12(vmx
);
7398 vmx
->nested
.sync_shadow_vmcs
= false;
7399 vmx_disable_shadow_vmcs(vmx
);
7401 vmx
->nested
.posted_intr_nv
= -1;
7403 /* Flush VMCS12 to guest memory */
7404 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7405 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7406 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7408 vmx
->nested
.current_vmptr
= -1ull;
7412 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7413 * just stops using VMX.
7415 static void free_nested(struct vcpu_vmx
*vmx
)
7417 if (!vmx
->nested
.vmxon
)
7420 vmx
->nested
.vmxon
= false;
7421 free_vpid(vmx
->nested
.vpid02
);
7422 vmx
->nested
.posted_intr_nv
= -1;
7423 vmx
->nested
.current_vmptr
= -1ull;
7424 if (vmx
->nested
.msr_bitmap
) {
7425 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7426 vmx
->nested
.msr_bitmap
= NULL
;
7428 if (enable_shadow_vmcs
) {
7429 vmx_disable_shadow_vmcs(vmx
);
7430 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7431 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7432 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7434 kfree(vmx
->nested
.cached_vmcs12
);
7435 /* Unpin physical memory we referred to in current vmcs02 */
7436 if (vmx
->nested
.apic_access_page
) {
7437 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7438 vmx
->nested
.apic_access_page
= NULL
;
7440 if (vmx
->nested
.virtual_apic_page
) {
7441 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7442 vmx
->nested
.virtual_apic_page
= NULL
;
7444 if (vmx
->nested
.pi_desc_page
) {
7445 kunmap(vmx
->nested
.pi_desc_page
);
7446 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7447 vmx
->nested
.pi_desc_page
= NULL
;
7448 vmx
->nested
.pi_desc
= NULL
;
7451 nested_free_all_saved_vmcss(vmx
);
7454 /* Emulate the VMXOFF instruction */
7455 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7457 if (!nested_vmx_check_permission(vcpu
))
7459 free_nested(to_vmx(vcpu
));
7460 nested_vmx_succeed(vcpu
);
7461 return kvm_skip_emulated_instruction(vcpu
);
7464 /* Emulate the VMCLEAR instruction */
7465 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7467 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7471 if (!nested_vmx_check_permission(vcpu
))
7474 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7477 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7478 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7479 return kvm_skip_emulated_instruction(vcpu
);
7482 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7483 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7484 return kvm_skip_emulated_instruction(vcpu
);
7487 if (vmptr
== vmx
->nested
.current_vmptr
)
7488 nested_release_vmcs12(vmx
);
7490 kvm_vcpu_write_guest(vcpu
,
7491 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7492 &zero
, sizeof(zero
));
7494 nested_free_vmcs02(vmx
, vmptr
);
7496 nested_vmx_succeed(vcpu
);
7497 return kvm_skip_emulated_instruction(vcpu
);
7500 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7502 /* Emulate the VMLAUNCH instruction */
7503 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7505 return nested_vmx_run(vcpu
, true);
7508 /* Emulate the VMRESUME instruction */
7509 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7512 return nested_vmx_run(vcpu
, false);
7516 * Read a vmcs12 field. Since these can have varying lengths and we return
7517 * one type, we chose the biggest type (u64) and zero-extend the return value
7518 * to that size. Note that the caller, handle_vmread, might need to use only
7519 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7520 * 64-bit fields are to be returned).
7522 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7523 unsigned long field
, u64
*ret
)
7525 short offset
= vmcs_field_to_offset(field
);
7531 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7533 switch (vmcs_field_type(field
)) {
7534 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7535 *ret
= *((natural_width
*)p
);
7537 case VMCS_FIELD_TYPE_U16
:
7540 case VMCS_FIELD_TYPE_U32
:
7543 case VMCS_FIELD_TYPE_U64
:
7553 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7554 unsigned long field
, u64 field_value
){
7555 short offset
= vmcs_field_to_offset(field
);
7556 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7560 switch (vmcs_field_type(field
)) {
7561 case VMCS_FIELD_TYPE_U16
:
7562 *(u16
*)p
= field_value
;
7564 case VMCS_FIELD_TYPE_U32
:
7565 *(u32
*)p
= field_value
;
7567 case VMCS_FIELD_TYPE_U64
:
7568 *(u64
*)p
= field_value
;
7570 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7571 *(natural_width
*)p
= field_value
;
7580 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7583 unsigned long field
;
7585 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7586 const unsigned long *fields
= shadow_read_write_fields
;
7587 const int num_fields
= max_shadow_read_write_fields
;
7591 vmcs_load(shadow_vmcs
);
7593 for (i
= 0; i
< num_fields
; i
++) {
7595 switch (vmcs_field_type(field
)) {
7596 case VMCS_FIELD_TYPE_U16
:
7597 field_value
= vmcs_read16(field
);
7599 case VMCS_FIELD_TYPE_U32
:
7600 field_value
= vmcs_read32(field
);
7602 case VMCS_FIELD_TYPE_U64
:
7603 field_value
= vmcs_read64(field
);
7605 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7606 field_value
= vmcs_readl(field
);
7612 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7615 vmcs_clear(shadow_vmcs
);
7616 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7621 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7623 const unsigned long *fields
[] = {
7624 shadow_read_write_fields
,
7625 shadow_read_only_fields
7627 const int max_fields
[] = {
7628 max_shadow_read_write_fields
,
7629 max_shadow_read_only_fields
7632 unsigned long field
;
7633 u64 field_value
= 0;
7634 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7636 vmcs_load(shadow_vmcs
);
7638 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7639 for (i
= 0; i
< max_fields
[q
]; i
++) {
7640 field
= fields
[q
][i
];
7641 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7643 switch (vmcs_field_type(field
)) {
7644 case VMCS_FIELD_TYPE_U16
:
7645 vmcs_write16(field
, (u16
)field_value
);
7647 case VMCS_FIELD_TYPE_U32
:
7648 vmcs_write32(field
, (u32
)field_value
);
7650 case VMCS_FIELD_TYPE_U64
:
7651 vmcs_write64(field
, (u64
)field_value
);
7653 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7654 vmcs_writel(field
, (long)field_value
);
7663 vmcs_clear(shadow_vmcs
);
7664 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7668 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7669 * used before) all generate the same failure when it is missing.
7671 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7673 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7674 if (vmx
->nested
.current_vmptr
== -1ull) {
7675 nested_vmx_failInvalid(vcpu
);
7681 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7683 unsigned long field
;
7685 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7686 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7689 if (!nested_vmx_check_permission(vcpu
))
7692 if (!nested_vmx_check_vmcs12(vcpu
))
7693 return kvm_skip_emulated_instruction(vcpu
);
7695 /* Decode instruction info and find the field to read */
7696 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7697 /* Read the field, zero-extended to a u64 field_value */
7698 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7699 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7700 return kvm_skip_emulated_instruction(vcpu
);
7703 * Now copy part of this value to register or memory, as requested.
7704 * Note that the number of bits actually copied is 32 or 64 depending
7705 * on the guest's mode (32 or 64 bit), not on the given field's length.
7707 if (vmx_instruction_info
& (1u << 10)) {
7708 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7711 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7712 vmx_instruction_info
, true, &gva
))
7714 /* _system ok, as hardware has verified cpl=0 */
7715 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7716 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7719 nested_vmx_succeed(vcpu
);
7720 return kvm_skip_emulated_instruction(vcpu
);
7724 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7726 unsigned long field
;
7728 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7729 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7730 /* The value to write might be 32 or 64 bits, depending on L1's long
7731 * mode, and eventually we need to write that into a field of several
7732 * possible lengths. The code below first zero-extends the value to 64
7733 * bit (field_value), and then copies only the appropriate number of
7734 * bits into the vmcs12 field.
7736 u64 field_value
= 0;
7737 struct x86_exception e
;
7739 if (!nested_vmx_check_permission(vcpu
))
7742 if (!nested_vmx_check_vmcs12(vcpu
))
7743 return kvm_skip_emulated_instruction(vcpu
);
7745 if (vmx_instruction_info
& (1u << 10))
7746 field_value
= kvm_register_readl(vcpu
,
7747 (((vmx_instruction_info
) >> 3) & 0xf));
7749 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7750 vmx_instruction_info
, false, &gva
))
7752 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7753 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7754 kvm_inject_page_fault(vcpu
, &e
);
7760 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7761 if (vmcs_field_readonly(field
)) {
7762 nested_vmx_failValid(vcpu
,
7763 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7764 return kvm_skip_emulated_instruction(vcpu
);
7767 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7768 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7769 return kvm_skip_emulated_instruction(vcpu
);
7772 nested_vmx_succeed(vcpu
);
7773 return kvm_skip_emulated_instruction(vcpu
);
7776 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7778 vmx
->nested
.current_vmptr
= vmptr
;
7779 if (enable_shadow_vmcs
) {
7780 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7781 SECONDARY_EXEC_SHADOW_VMCS
);
7782 vmcs_write64(VMCS_LINK_POINTER
,
7783 __pa(vmx
->vmcs01
.shadow_vmcs
));
7784 vmx
->nested
.sync_shadow_vmcs
= true;
7788 /* Emulate the VMPTRLD instruction */
7789 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7791 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7794 if (!nested_vmx_check_permission(vcpu
))
7797 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7800 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7801 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7802 return kvm_skip_emulated_instruction(vcpu
);
7805 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7806 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7807 return kvm_skip_emulated_instruction(vcpu
);
7810 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7811 struct vmcs12
*new_vmcs12
;
7813 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7814 if (is_error_page(page
)) {
7815 nested_vmx_failInvalid(vcpu
);
7816 return kvm_skip_emulated_instruction(vcpu
);
7818 new_vmcs12
= kmap(page
);
7819 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7821 kvm_release_page_clean(page
);
7822 nested_vmx_failValid(vcpu
,
7823 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7824 return kvm_skip_emulated_instruction(vcpu
);
7827 nested_release_vmcs12(vmx
);
7829 * Load VMCS12 from guest memory since it is not already
7832 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7834 kvm_release_page_clean(page
);
7836 set_current_vmptr(vmx
, vmptr
);
7839 nested_vmx_succeed(vcpu
);
7840 return kvm_skip_emulated_instruction(vcpu
);
7843 /* Emulate the VMPTRST instruction */
7844 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7846 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7847 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7849 struct x86_exception e
;
7851 if (!nested_vmx_check_permission(vcpu
))
7854 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7855 vmx_instruction_info
, true, &vmcs_gva
))
7857 /* ok to use *_system, as hardware has verified cpl=0 */
7858 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7859 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7861 kvm_inject_page_fault(vcpu
, &e
);
7864 nested_vmx_succeed(vcpu
);
7865 return kvm_skip_emulated_instruction(vcpu
);
7868 /* Emulate the INVEPT instruction */
7869 static int handle_invept(struct kvm_vcpu
*vcpu
)
7871 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7872 u32 vmx_instruction_info
, types
;
7875 struct x86_exception e
;
7880 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7881 SECONDARY_EXEC_ENABLE_EPT
) ||
7882 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7883 kvm_queue_exception(vcpu
, UD_VECTOR
);
7887 if (!nested_vmx_check_permission(vcpu
))
7890 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7891 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7893 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7895 if (type
>= 32 || !(types
& (1 << type
))) {
7896 nested_vmx_failValid(vcpu
,
7897 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7898 return kvm_skip_emulated_instruction(vcpu
);
7901 /* According to the Intel VMX instruction reference, the memory
7902 * operand is read even if it isn't needed (e.g., for type==global)
7904 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7905 vmx_instruction_info
, false, &gva
))
7907 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7908 sizeof(operand
), &e
)) {
7909 kvm_inject_page_fault(vcpu
, &e
);
7914 case VMX_EPT_EXTENT_GLOBAL
:
7916 * TODO: track mappings and invalidate
7917 * single context requests appropriately
7919 case VMX_EPT_EXTENT_CONTEXT
:
7920 kvm_mmu_sync_roots(vcpu
);
7921 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7922 nested_vmx_succeed(vcpu
);
7929 return kvm_skip_emulated_instruction(vcpu
);
7932 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7934 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7935 u32 vmx_instruction_info
;
7936 unsigned long type
, types
;
7938 struct x86_exception e
;
7944 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7945 SECONDARY_EXEC_ENABLE_VPID
) ||
7946 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7947 kvm_queue_exception(vcpu
, UD_VECTOR
);
7951 if (!nested_vmx_check_permission(vcpu
))
7954 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7955 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7957 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7958 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7960 if (type
>= 32 || !(types
& (1 << type
))) {
7961 nested_vmx_failValid(vcpu
,
7962 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7963 return kvm_skip_emulated_instruction(vcpu
);
7966 /* according to the intel vmx instruction reference, the memory
7967 * operand is read even if it isn't needed (e.g., for type==global)
7969 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7970 vmx_instruction_info
, false, &gva
))
7972 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7973 sizeof(operand
), &e
)) {
7974 kvm_inject_page_fault(vcpu
, &e
);
7977 if (operand
.vpid
>> 16) {
7978 nested_vmx_failValid(vcpu
,
7979 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7980 return kvm_skip_emulated_instruction(vcpu
);
7984 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7985 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7986 nested_vmx_failValid(vcpu
,
7987 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7988 return kvm_skip_emulated_instruction(vcpu
);
7991 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7992 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7993 if (!operand
.vpid
) {
7994 nested_vmx_failValid(vcpu
,
7995 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7996 return kvm_skip_emulated_instruction(vcpu
);
7999 case VMX_VPID_EXTENT_ALL_CONTEXT
:
8003 return kvm_skip_emulated_instruction(vcpu
);
8006 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
8007 nested_vmx_succeed(vcpu
);
8009 return kvm_skip_emulated_instruction(vcpu
);
8012 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
8014 unsigned long exit_qualification
;
8016 trace_kvm_pml_full(vcpu
->vcpu_id
);
8018 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8021 * PML buffer FULL happened while executing iret from NMI,
8022 * "blocked by NMI" bit has to be set before next VM entry.
8024 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8026 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
8027 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8028 GUEST_INTR_STATE_NMI
);
8031 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8032 * here.., and there's no userspace involvement needed for PML.
8037 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8039 kvm_lapic_expired_hv_timer(vcpu
);
8043 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8045 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8046 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8048 /* Check for memory type validity */
8049 switch (address
& VMX_EPTP_MT_MASK
) {
8050 case VMX_EPTP_MT_UC
:
8051 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8054 case VMX_EPTP_MT_WB
:
8055 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8062 /* only 4 levels page-walk length are valid */
8063 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8066 /* Reserved bits should not be set */
8067 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8070 /* AD, if set, should be supported */
8071 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8072 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8079 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8080 struct vmcs12
*vmcs12
)
8082 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8084 bool accessed_dirty
;
8085 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8087 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8088 !nested_cpu_has_ept(vmcs12
))
8091 if (index
>= VMFUNC_EPTP_ENTRIES
)
8095 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8096 &address
, index
* 8, 8))
8099 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8102 * If the (L2) guest does a vmfunc to the currently
8103 * active ept pointer, we don't have to do anything else
8105 if (vmcs12
->ept_pointer
!= address
) {
8106 if (!valid_ept_address(vcpu
, address
))
8109 kvm_mmu_unload(vcpu
);
8110 mmu
->ept_ad
= accessed_dirty
;
8111 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8112 vmcs12
->ept_pointer
= address
;
8114 * TODO: Check what's the correct approach in case
8115 * mmu reload fails. Currently, we just let the next
8116 * reload potentially fail
8118 kvm_mmu_reload(vcpu
);
8124 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8126 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8127 struct vmcs12
*vmcs12
;
8128 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8131 * VMFUNC is only supported for nested guests, but we always enable the
8132 * secondary control for simplicity; for non-nested mode, fake that we
8133 * didn't by injecting #UD.
8135 if (!is_guest_mode(vcpu
)) {
8136 kvm_queue_exception(vcpu
, UD_VECTOR
);
8140 vmcs12
= get_vmcs12(vcpu
);
8141 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8146 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8152 return kvm_skip_emulated_instruction(vcpu
);
8155 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8156 vmcs_read32(VM_EXIT_INTR_INFO
),
8157 vmcs_readl(EXIT_QUALIFICATION
));
8162 * The exit handlers return 1 if the exit was handled fully and guest execution
8163 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8164 * to be done to userspace and return 0.
8166 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8167 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8168 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8169 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8170 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8171 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8172 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8173 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8174 [EXIT_REASON_CPUID
] = handle_cpuid
,
8175 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8176 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8177 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8178 [EXIT_REASON_HLT
] = handle_halt
,
8179 [EXIT_REASON_INVD
] = handle_invd
,
8180 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8181 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8182 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8183 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8184 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8185 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8186 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8187 [EXIT_REASON_VMREAD
] = handle_vmread
,
8188 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8189 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8190 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8191 [EXIT_REASON_VMON
] = handle_vmon
,
8192 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8193 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8194 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8195 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8196 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8197 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8198 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8199 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8200 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8201 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8202 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8203 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8204 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8205 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8206 [EXIT_REASON_INVEPT
] = handle_invept
,
8207 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8208 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8209 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8210 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8211 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8212 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8213 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8214 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8217 static const int kvm_vmx_max_exit_handlers
=
8218 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8220 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8221 struct vmcs12
*vmcs12
)
8223 unsigned long exit_qualification
;
8224 gpa_t bitmap
, last_bitmap
;
8229 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8230 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8232 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8234 port
= exit_qualification
>> 16;
8235 size
= (exit_qualification
& 7) + 1;
8237 last_bitmap
= (gpa_t
)-1;
8242 bitmap
= vmcs12
->io_bitmap_a
;
8243 else if (port
< 0x10000)
8244 bitmap
= vmcs12
->io_bitmap_b
;
8247 bitmap
+= (port
& 0x7fff) / 8;
8249 if (last_bitmap
!= bitmap
)
8250 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8252 if (b
& (1 << (port
& 7)))
8257 last_bitmap
= bitmap
;
8264 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8265 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8266 * disinterest in the current event (read or write a specific MSR) by using an
8267 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8269 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8270 struct vmcs12
*vmcs12
, u32 exit_reason
)
8272 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8275 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8279 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8280 * for the four combinations of read/write and low/high MSR numbers.
8281 * First we need to figure out which of the four to use:
8283 bitmap
= vmcs12
->msr_bitmap
;
8284 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8286 if (msr_index
>= 0xc0000000) {
8287 msr_index
-= 0xc0000000;
8291 /* Then read the msr_index'th bit from this bitmap: */
8292 if (msr_index
< 1024*8) {
8294 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8296 return 1 & (b
>> (msr_index
& 7));
8298 return true; /* let L1 handle the wrong parameter */
8302 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8303 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8304 * intercept (via guest_host_mask etc.) the current event.
8306 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8307 struct vmcs12
*vmcs12
)
8309 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8310 int cr
= exit_qualification
& 15;
8314 switch ((exit_qualification
>> 4) & 3) {
8315 case 0: /* mov to cr */
8316 reg
= (exit_qualification
>> 8) & 15;
8317 val
= kvm_register_readl(vcpu
, reg
);
8320 if (vmcs12
->cr0_guest_host_mask
&
8321 (val
^ vmcs12
->cr0_read_shadow
))
8325 if ((vmcs12
->cr3_target_count
>= 1 &&
8326 vmcs12
->cr3_target_value0
== val
) ||
8327 (vmcs12
->cr3_target_count
>= 2 &&
8328 vmcs12
->cr3_target_value1
== val
) ||
8329 (vmcs12
->cr3_target_count
>= 3 &&
8330 vmcs12
->cr3_target_value2
== val
) ||
8331 (vmcs12
->cr3_target_count
>= 4 &&
8332 vmcs12
->cr3_target_value3
== val
))
8334 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8338 if (vmcs12
->cr4_guest_host_mask
&
8339 (vmcs12
->cr4_read_shadow
^ val
))
8343 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8349 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8350 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8353 case 1: /* mov from cr */
8356 if (vmcs12
->cpu_based_vm_exec_control
&
8357 CPU_BASED_CR3_STORE_EXITING
)
8361 if (vmcs12
->cpu_based_vm_exec_control
&
8362 CPU_BASED_CR8_STORE_EXITING
)
8369 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8370 * cr0. Other attempted changes are ignored, with no exit.
8372 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8373 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8374 (val
^ vmcs12
->cr0_read_shadow
))
8376 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8377 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8386 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8387 * should handle it ourselves in L0 (and then continue L2). Only call this
8388 * when in is_guest_mode (L2).
8390 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8392 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8393 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8394 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8396 if (vmx
->nested
.nested_run_pending
)
8399 if (unlikely(vmx
->fail
)) {
8400 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8401 vmcs_read32(VM_INSTRUCTION_ERROR
));
8406 * The host physical addresses of some pages of guest memory
8407 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8408 * may write to these pages via their host physical address while
8409 * L2 is running, bypassing any address-translation-based dirty
8410 * tracking (e.g. EPT write protection).
8412 * Mark them dirty on every exit from L2 to prevent them from
8413 * getting out of sync with dirty tracking.
8415 nested_mark_vmcs12_pages_dirty(vcpu
);
8417 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8418 vmcs_readl(EXIT_QUALIFICATION
),
8419 vmx
->idt_vectoring_info
,
8421 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8424 switch (exit_reason
) {
8425 case EXIT_REASON_EXCEPTION_NMI
:
8426 if (is_nmi(intr_info
))
8428 else if (is_page_fault(intr_info
))
8429 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8430 else if (is_no_device(intr_info
) &&
8431 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8433 else if (is_debug(intr_info
) &&
8435 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8437 else if (is_breakpoint(intr_info
) &&
8438 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8440 return vmcs12
->exception_bitmap
&
8441 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8442 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8444 case EXIT_REASON_TRIPLE_FAULT
:
8446 case EXIT_REASON_PENDING_INTERRUPT
:
8447 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8448 case EXIT_REASON_NMI_WINDOW
:
8449 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8450 case EXIT_REASON_TASK_SWITCH
:
8452 case EXIT_REASON_CPUID
:
8454 case EXIT_REASON_HLT
:
8455 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8456 case EXIT_REASON_INVD
:
8458 case EXIT_REASON_INVLPG
:
8459 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8460 case EXIT_REASON_RDPMC
:
8461 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8462 case EXIT_REASON_RDRAND
:
8463 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8464 case EXIT_REASON_RDSEED
:
8465 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8466 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8467 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8468 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8469 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8470 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8471 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8472 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8473 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8475 * VMX instructions trap unconditionally. This allows L1 to
8476 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8479 case EXIT_REASON_CR_ACCESS
:
8480 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8481 case EXIT_REASON_DR_ACCESS
:
8482 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8483 case EXIT_REASON_IO_INSTRUCTION
:
8484 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8485 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8486 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8487 case EXIT_REASON_MSR_READ
:
8488 case EXIT_REASON_MSR_WRITE
:
8489 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8490 case EXIT_REASON_INVALID_STATE
:
8492 case EXIT_REASON_MWAIT_INSTRUCTION
:
8493 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8494 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8495 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8496 case EXIT_REASON_MONITOR_INSTRUCTION
:
8497 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8498 case EXIT_REASON_PAUSE_INSTRUCTION
:
8499 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8500 nested_cpu_has2(vmcs12
,
8501 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8502 case EXIT_REASON_MCE_DURING_VMENTRY
:
8504 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8505 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8506 case EXIT_REASON_APIC_ACCESS
:
8507 return nested_cpu_has2(vmcs12
,
8508 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8509 case EXIT_REASON_APIC_WRITE
:
8510 case EXIT_REASON_EOI_INDUCED
:
8511 /* apic_write and eoi_induced should exit unconditionally. */
8513 case EXIT_REASON_EPT_VIOLATION
:
8515 * L0 always deals with the EPT violation. If nested EPT is
8516 * used, and the nested mmu code discovers that the address is
8517 * missing in the guest EPT table (EPT12), the EPT violation
8518 * will be injected with nested_ept_inject_page_fault()
8521 case EXIT_REASON_EPT_MISCONFIG
:
8523 * L2 never uses directly L1's EPT, but rather L0's own EPT
8524 * table (shadow on EPT) or a merged EPT table that L0 built
8525 * (EPT on EPT). So any problems with the structure of the
8526 * table is L0's fault.
8529 case EXIT_REASON_INVPCID
:
8531 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8532 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8533 case EXIT_REASON_WBINVD
:
8534 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8535 case EXIT_REASON_XSETBV
:
8537 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8539 * This should never happen, since it is not possible to
8540 * set XSS to a non-zero value---neither in L1 nor in L2.
8541 * If if it were, XSS would have to be checked against
8542 * the XSS exit bitmap in vmcs12.
8544 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8545 case EXIT_REASON_PREEMPTION_TIMER
:
8547 case EXIT_REASON_PML_FULL
:
8548 /* We emulate PML support to L1. */
8550 case EXIT_REASON_VMFUNC
:
8551 /* VM functions are emulated through L2->L0 vmexits. */
8558 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8560 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8563 * At this point, the exit interruption info in exit_intr_info
8564 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8565 * we need to query the in-kernel LAPIC.
8567 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8568 if ((exit_intr_info
&
8569 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8570 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8571 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8572 vmcs12
->vm_exit_intr_error_code
=
8573 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8576 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8577 vmcs_readl(EXIT_QUALIFICATION
));
8581 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8583 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8584 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8587 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8590 __free_page(vmx
->pml_pg
);
8595 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8597 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8601 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8603 /* Do nothing if PML buffer is empty */
8604 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8607 /* PML index always points to next available PML buffer entity */
8608 if (pml_idx
>= PML_ENTITY_NUM
)
8613 pml_buf
= page_address(vmx
->pml_pg
);
8614 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8617 gpa
= pml_buf
[pml_idx
];
8618 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8619 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8622 /* reset PML index */
8623 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8627 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8628 * Called before reporting dirty_bitmap to userspace.
8630 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8633 struct kvm_vcpu
*vcpu
;
8635 * We only need to kick vcpu out of guest mode here, as PML buffer
8636 * is flushed at beginning of all VMEXITs, and it's obvious that only
8637 * vcpus running in guest are possible to have unflushed GPAs in PML
8640 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8641 kvm_vcpu_kick(vcpu
);
8644 static void vmx_dump_sel(char *name
, uint32_t sel
)
8646 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8647 name
, vmcs_read16(sel
),
8648 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8649 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8650 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8653 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8655 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8656 name
, vmcs_read32(limit
),
8657 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8660 static void dump_vmcs(void)
8662 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8663 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8664 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8665 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8666 u32 secondary_exec_control
= 0;
8667 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8668 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8671 if (cpu_has_secondary_exec_ctrls())
8672 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8674 pr_err("*** Guest State ***\n");
8675 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8676 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8677 vmcs_readl(CR0_GUEST_HOST_MASK
));
8678 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8679 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8680 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8681 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8682 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8684 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8685 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8686 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8687 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8689 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8690 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8691 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8692 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8693 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8694 vmcs_readl(GUEST_SYSENTER_ESP
),
8695 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8696 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8697 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8698 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8699 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8700 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8701 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8702 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8703 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8704 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8705 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8706 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8707 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8708 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8709 efer
, vmcs_read64(GUEST_IA32_PAT
));
8710 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8711 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8712 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8713 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8714 pr_err("PerfGlobCtl = 0x%016llx\n",
8715 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8716 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8717 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8718 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8719 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8720 vmcs_read32(GUEST_ACTIVITY_STATE
));
8721 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8722 pr_err("InterruptStatus = %04x\n",
8723 vmcs_read16(GUEST_INTR_STATUS
));
8725 pr_err("*** Host State ***\n");
8726 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8727 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8728 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8729 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8730 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8731 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8732 vmcs_read16(HOST_TR_SELECTOR
));
8733 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8734 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8735 vmcs_readl(HOST_TR_BASE
));
8736 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8737 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8738 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8739 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8740 vmcs_readl(HOST_CR4
));
8741 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8742 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8743 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8744 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8745 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8746 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8747 vmcs_read64(HOST_IA32_EFER
),
8748 vmcs_read64(HOST_IA32_PAT
));
8749 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8750 pr_err("PerfGlobCtl = 0x%016llx\n",
8751 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8753 pr_err("*** Control State ***\n");
8754 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8755 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8756 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8757 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8758 vmcs_read32(EXCEPTION_BITMAP
),
8759 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8760 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8761 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8762 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8763 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8764 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8765 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8766 vmcs_read32(VM_EXIT_INTR_INFO
),
8767 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8768 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8769 pr_err(" reason=%08x qualification=%016lx\n",
8770 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8771 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8772 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8773 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8774 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8775 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8776 pr_err("TSC Multiplier = 0x%016llx\n",
8777 vmcs_read64(TSC_MULTIPLIER
));
8778 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8779 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8780 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8781 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8782 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8783 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8784 n
= vmcs_read32(CR3_TARGET_COUNT
);
8785 for (i
= 0; i
+ 1 < n
; i
+= 4)
8786 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8787 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8788 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8790 pr_err("CR3 target%u=%016lx\n",
8791 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8792 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8793 pr_err("PLE Gap=%08x Window=%08x\n",
8794 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8795 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8796 pr_err("Virtual processor ID = 0x%04x\n",
8797 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8801 * The guest has exited. See if we can fix it or if we need userspace
8804 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8806 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8807 u32 exit_reason
= vmx
->exit_reason
;
8808 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8810 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8813 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8814 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8815 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8816 * mode as if vcpus is in root mode, the PML buffer must has been
8820 vmx_flush_pml_buffer(vcpu
);
8822 /* If guest state is invalid, start emulating */
8823 if (vmx
->emulation_required
)
8824 return handle_invalid_guest_state(vcpu
);
8826 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8827 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8829 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8831 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8832 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8837 if (unlikely(vmx
->fail
)) {
8838 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8839 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8840 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8846 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8847 * delivery event since it indicates guest is accessing MMIO.
8848 * The vm-exit can be triggered again after return to guest that
8849 * will cause infinite loop.
8851 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8852 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8853 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8854 exit_reason
!= EXIT_REASON_PML_FULL
&&
8855 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8856 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8857 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8858 vcpu
->run
->internal
.ndata
= 3;
8859 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8860 vcpu
->run
->internal
.data
[1] = exit_reason
;
8861 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8862 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8863 vcpu
->run
->internal
.ndata
++;
8864 vcpu
->run
->internal
.data
[3] =
8865 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8870 if (unlikely(!enable_vnmi
&&
8871 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8872 if (vmx_interrupt_allowed(vcpu
)) {
8873 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8874 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8875 vcpu
->arch
.nmi_pending
) {
8877 * This CPU don't support us in finding the end of an
8878 * NMI-blocked window if the guest runs with IRQs
8879 * disabled. So we pull the trigger after 1 s of
8880 * futile waiting, but inform the user about this.
8882 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8883 "state on VCPU %d after 1 s timeout\n",
8884 __func__
, vcpu
->vcpu_id
);
8885 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8889 if (exit_reason
< kvm_vmx_max_exit_handlers
8890 && kvm_vmx_exit_handlers
[exit_reason
])
8891 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8893 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8895 kvm_queue_exception(vcpu
, UD_VECTOR
);
8900 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8902 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8904 if (is_guest_mode(vcpu
) &&
8905 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8908 if (irr
== -1 || tpr
< irr
) {
8909 vmcs_write32(TPR_THRESHOLD
, 0);
8913 vmcs_write32(TPR_THRESHOLD
, irr
);
8916 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8918 u32 sec_exec_control
;
8920 /* Postpone execution until vmcs01 is the current VMCS. */
8921 if (is_guest_mode(vcpu
)) {
8922 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8926 if (!cpu_has_vmx_virtualize_x2apic_mode())
8929 if (!cpu_need_tpr_shadow(vcpu
))
8932 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8935 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8936 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8938 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8939 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8940 vmx_flush_tlb_ept_only(vcpu
);
8942 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8944 vmx_set_msr_bitmap(vcpu
);
8947 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8949 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8952 * Currently we do not handle the nested case where L2 has an
8953 * APIC access page of its own; that page is still pinned.
8954 * Hence, we skip the case where the VCPU is in guest mode _and_
8955 * L1 prepared an APIC access page for L2.
8957 * For the case where L1 and L2 share the same APIC access page
8958 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8959 * in the vmcs12), this function will only update either the vmcs01
8960 * or the vmcs02. If the former, the vmcs02 will be updated by
8961 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8962 * the next L2->L1 exit.
8964 if (!is_guest_mode(vcpu
) ||
8965 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8966 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8967 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8968 vmx_flush_tlb_ept_only(vcpu
);
8972 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8980 status
= vmcs_read16(GUEST_INTR_STATUS
);
8982 if (max_isr
!= old
) {
8984 status
|= max_isr
<< 8;
8985 vmcs_write16(GUEST_INTR_STATUS
, status
);
8989 static void vmx_set_rvi(int vector
)
8997 status
= vmcs_read16(GUEST_INTR_STATUS
);
8998 old
= (u8
)status
& 0xff;
8999 if ((u8
)vector
!= old
) {
9001 status
|= (u8
)vector
;
9002 vmcs_write16(GUEST_INTR_STATUS
, status
);
9006 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
9008 if (!is_guest_mode(vcpu
)) {
9009 vmx_set_rvi(max_irr
);
9017 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9020 if (nested_exit_on_intr(vcpu
))
9024 * Else, fall back to pre-APICv interrupt injection since L2
9025 * is run without virtual interrupt delivery.
9027 if (!kvm_event_needs_reinjection(vcpu
) &&
9028 vmx_interrupt_allowed(vcpu
)) {
9029 kvm_queue_interrupt(vcpu
, max_irr
, false);
9030 vmx_inject_irq(vcpu
);
9034 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
9036 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9039 WARN_ON(!vcpu
->arch
.apicv_active
);
9040 if (pi_test_on(&vmx
->pi_desc
)) {
9041 pi_clear_on(&vmx
->pi_desc
);
9043 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9044 * But on x86 this is just a compiler barrier anyway.
9046 smp_mb__after_atomic();
9047 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
9049 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
9051 vmx_hwapic_irr_update(vcpu
, max_irr
);
9055 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9057 if (!kvm_vcpu_apicv_active(vcpu
))
9060 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9061 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9062 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9063 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9066 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9068 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9070 pi_clear_on(&vmx
->pi_desc
);
9071 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9074 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9076 u32 exit_intr_info
= 0;
9077 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9079 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9080 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9083 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9084 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9085 vmx
->exit_intr_info
= exit_intr_info
;
9087 /* if exit due to PF check for async PF */
9088 if (is_page_fault(exit_intr_info
))
9089 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9091 /* Handle machine checks before interrupts are enabled */
9092 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9093 is_machine_check(exit_intr_info
))
9094 kvm_machine_check();
9096 /* We need to handle NMIs before interrupts are enabled */
9097 if (is_nmi(exit_intr_info
)) {
9098 kvm_before_handle_nmi(&vmx
->vcpu
);
9100 kvm_after_handle_nmi(&vmx
->vcpu
);
9104 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9106 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9108 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9109 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9110 unsigned int vector
;
9111 unsigned long entry
;
9113 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9114 #ifdef CONFIG_X86_64
9118 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9119 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9120 entry
= gate_offset(desc
);
9122 #ifdef CONFIG_X86_64
9123 "mov %%" _ASM_SP
", %[sp]\n\t"
9124 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9129 __ASM_SIZE(push
) " $%c[cs]\n\t"
9130 "call *%[entry]\n\t"
9132 #ifdef CONFIG_X86_64
9138 [ss
]"i"(__KERNEL_DS
),
9139 [cs
]"i"(__KERNEL_CS
)
9143 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9145 static bool vmx_has_high_real_mode_segbase(void)
9147 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9150 static bool vmx_mpx_supported(void)
9152 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9153 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9156 static bool vmx_xsaves_supported(void)
9158 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9159 SECONDARY_EXEC_XSAVES
;
9162 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9167 bool idtv_info_valid
;
9169 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9172 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9175 * Can't use vmx->exit_intr_info since we're not sure what
9176 * the exit reason is.
9178 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9179 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9180 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9182 * SDM 3: 27.7.1.2 (September 2008)
9183 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9184 * a guest IRET fault.
9185 * SDM 3: 23.2.2 (September 2008)
9186 * Bit 12 is undefined in any of the following cases:
9187 * If the VM exit sets the valid bit in the IDT-vectoring
9188 * information field.
9189 * If the VM exit is due to a double fault.
9191 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9192 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9193 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9194 GUEST_INTR_STATE_NMI
);
9196 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9197 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9198 & GUEST_INTR_STATE_NMI
);
9199 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9200 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9201 ktime_to_ns(ktime_sub(ktime_get(),
9202 vmx
->loaded_vmcs
->entry_time
));
9205 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9206 u32 idt_vectoring_info
,
9207 int instr_len_field
,
9208 int error_code_field
)
9212 bool idtv_info_valid
;
9214 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9216 vcpu
->arch
.nmi_injected
= false;
9217 kvm_clear_exception_queue(vcpu
);
9218 kvm_clear_interrupt_queue(vcpu
);
9220 if (!idtv_info_valid
)
9223 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9225 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9226 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9229 case INTR_TYPE_NMI_INTR
:
9230 vcpu
->arch
.nmi_injected
= true;
9232 * SDM 3: 27.7.1.2 (September 2008)
9233 * Clear bit "block by NMI" before VM entry if a NMI
9236 vmx_set_nmi_mask(vcpu
, false);
9238 case INTR_TYPE_SOFT_EXCEPTION
:
9239 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9241 case INTR_TYPE_HARD_EXCEPTION
:
9242 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9243 u32 err
= vmcs_read32(error_code_field
);
9244 kvm_requeue_exception_e(vcpu
, vector
, err
);
9246 kvm_requeue_exception(vcpu
, vector
);
9248 case INTR_TYPE_SOFT_INTR
:
9249 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9251 case INTR_TYPE_EXT_INTR
:
9252 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9259 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9261 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9262 VM_EXIT_INSTRUCTION_LEN
,
9263 IDT_VECTORING_ERROR_CODE
);
9266 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9268 __vmx_complete_interrupts(vcpu
,
9269 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9270 VM_ENTRY_INSTRUCTION_LEN
,
9271 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9273 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9276 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9279 struct perf_guest_switch_msr
*msrs
;
9281 msrs
= perf_guest_get_msrs(&nr_msrs
);
9286 for (i
= 0; i
< nr_msrs
; i
++)
9287 if (msrs
[i
].host
== msrs
[i
].guest
)
9288 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9290 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9294 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9300 if (vmx
->hv_deadline_tsc
== -1)
9304 if (vmx
->hv_deadline_tsc
> tscl
)
9305 /* sure to be 32 bit only because checked on set_hv_timer */
9306 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9307 cpu_preemption_timer_multi
);
9311 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9314 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9316 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9317 unsigned long debugctlmsr
, cr3
, cr4
;
9319 /* Record the guest's net vcpu time for enforced NMI injections. */
9320 if (unlikely(!enable_vnmi
&&
9321 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9322 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9324 /* Don't enter VMX if guest state is invalid, let the exit handler
9325 start emulation until we arrive back to a valid state */
9326 if (vmx
->emulation_required
)
9329 if (vmx
->ple_window_dirty
) {
9330 vmx
->ple_window_dirty
= false;
9331 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9334 if (vmx
->nested
.sync_shadow_vmcs
) {
9335 copy_vmcs12_to_shadow(vmx
);
9336 vmx
->nested
.sync_shadow_vmcs
= false;
9339 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9340 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9341 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9342 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9344 cr3
= __get_current_cr3_fast();
9345 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9346 vmcs_writel(HOST_CR3
, cr3
);
9347 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9350 cr4
= cr4_read_shadow();
9351 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9352 vmcs_writel(HOST_CR4
, cr4
);
9353 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9356 /* When single-stepping over STI and MOV SS, we must clear the
9357 * corresponding interruptibility bits in the guest state. Otherwise
9358 * vmentry fails as it then expects bit 14 (BS) in pending debug
9359 * exceptions being set, but that's not correct for the guest debugging
9361 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9362 vmx_set_interrupt_shadow(vcpu
, 0);
9364 if (static_cpu_has(X86_FEATURE_PKU
) &&
9365 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9366 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9367 __write_pkru(vcpu
->arch
.pkru
);
9369 atomic_switch_perf_msrs(vmx
);
9370 debugctlmsr
= get_debugctlmsr();
9372 vmx_arm_hv_timer(vcpu
);
9374 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9376 /* Store host registers */
9377 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9378 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9379 "push %%" _ASM_CX
" \n\t"
9380 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9382 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9383 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9385 /* Reload cr2 if changed */
9386 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9387 "mov %%cr2, %%" _ASM_DX
" \n\t"
9388 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9390 "mov %%" _ASM_AX
", %%cr2 \n\t"
9392 /* Check if vmlaunch of vmresume is needed */
9393 "cmpl $0, %c[launched](%0) \n\t"
9394 /* Load guest registers. Don't clobber flags. */
9395 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9396 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9397 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9398 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9399 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9400 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9401 #ifdef CONFIG_X86_64
9402 "mov %c[r8](%0), %%r8 \n\t"
9403 "mov %c[r9](%0), %%r9 \n\t"
9404 "mov %c[r10](%0), %%r10 \n\t"
9405 "mov %c[r11](%0), %%r11 \n\t"
9406 "mov %c[r12](%0), %%r12 \n\t"
9407 "mov %c[r13](%0), %%r13 \n\t"
9408 "mov %c[r14](%0), %%r14 \n\t"
9409 "mov %c[r15](%0), %%r15 \n\t"
9411 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9413 /* Enter guest mode */
9415 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9417 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9419 /* Save guest registers, load host registers, keep flags */
9420 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9422 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9423 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9424 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9425 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9426 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9427 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9428 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9429 #ifdef CONFIG_X86_64
9430 "mov %%r8, %c[r8](%0) \n\t"
9431 "mov %%r9, %c[r9](%0) \n\t"
9432 "mov %%r10, %c[r10](%0) \n\t"
9433 "mov %%r11, %c[r11](%0) \n\t"
9434 "mov %%r12, %c[r12](%0) \n\t"
9435 "mov %%r13, %c[r13](%0) \n\t"
9436 "mov %%r14, %c[r14](%0) \n\t"
9437 "mov %%r15, %c[r15](%0) \n\t"
9439 "mov %%cr2, %%" _ASM_AX
" \n\t"
9440 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9442 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9443 "setbe %c[fail](%0) \n\t"
9444 ".pushsection .rodata \n\t"
9445 ".global vmx_return \n\t"
9446 "vmx_return: " _ASM_PTR
" 2b \n\t"
9448 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9449 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9450 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9451 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9452 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9453 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9454 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9455 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9456 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9457 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9458 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9459 #ifdef CONFIG_X86_64
9460 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9461 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9462 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9463 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9464 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9465 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9466 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9467 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9469 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9470 [wordsize
]"i"(sizeof(ulong
))
9472 #ifdef CONFIG_X86_64
9473 , "rax", "rbx", "rdi", "rsi"
9474 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9476 , "eax", "ebx", "edi", "esi"
9480 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9482 update_debugctlmsr(debugctlmsr
);
9484 #ifndef CONFIG_X86_64
9486 * The sysexit path does not restore ds/es, so we must set them to
9487 * a reasonable value ourselves.
9489 * We can't defer this to vmx_load_host_state() since that function
9490 * may be executed in interrupt context, which saves and restore segments
9491 * around it, nullifying its effect.
9493 loadsegment(ds
, __USER_DS
);
9494 loadsegment(es
, __USER_DS
);
9497 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9498 | (1 << VCPU_EXREG_RFLAGS
)
9499 | (1 << VCPU_EXREG_PDPTR
)
9500 | (1 << VCPU_EXREG_SEGMENTS
)
9501 | (1 << VCPU_EXREG_CR3
));
9502 vcpu
->arch
.regs_dirty
= 0;
9505 * eager fpu is enabled if PKEY is supported and CR4 is switched
9506 * back on host, so it is safe to read guest PKRU from current
9509 if (static_cpu_has(X86_FEATURE_PKU
) &&
9510 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9511 vcpu
->arch
.pkru
= __read_pkru();
9512 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9513 __write_pkru(vmx
->host_pkru
);
9517 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9518 * we did not inject a still-pending event to L1 now because of
9519 * nested_run_pending, we need to re-enable this bit.
9521 if (vmx
->nested
.nested_run_pending
)
9522 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9524 vmx
->nested
.nested_run_pending
= 0;
9525 vmx
->idt_vectoring_info
= 0;
9527 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9528 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9531 vmx
->loaded_vmcs
->launched
= 1;
9532 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9534 vmx_complete_atomic_exit(vmx
);
9535 vmx_recover_nmi_blocking(vmx
);
9536 vmx_complete_interrupts(vmx
);
9538 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9540 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9545 if (vmx
->loaded_vmcs
== vmcs
)
9549 vmx
->loaded_vmcs
= vmcs
;
9551 vmx_vcpu_load(vcpu
, cpu
);
9556 * Ensure that the current vmcs of the logical processor is the
9557 * vmcs01 of the vcpu before calling free_nested().
9559 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9561 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9564 r
= vcpu_load(vcpu
);
9566 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9571 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9573 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9576 vmx_destroy_pml_buffer(vmx
);
9577 free_vpid(vmx
->vpid
);
9578 leave_guest_mode(vcpu
);
9579 vmx_free_vcpu_nested(vcpu
);
9580 free_loaded_vmcs(vmx
->loaded_vmcs
);
9581 kfree(vmx
->guest_msrs
);
9582 kvm_vcpu_uninit(vcpu
);
9583 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9586 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9589 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9593 return ERR_PTR(-ENOMEM
);
9595 vmx
->vpid
= allocate_vpid();
9597 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9604 * If PML is turned on, failure on enabling PML just results in failure
9605 * of creating the vcpu, therefore we can simplify PML logic (by
9606 * avoiding dealing with cases, such as enabling PML partially on vcpus
9607 * for the guest, etc.
9610 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9615 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9616 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9619 if (!vmx
->guest_msrs
)
9622 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9623 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9624 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9625 if (!vmx
->loaded_vmcs
->vmcs
)
9627 loaded_vmcs_init(vmx
->loaded_vmcs
);
9630 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9631 vmx
->vcpu
.cpu
= cpu
;
9632 vmx_vcpu_setup(vmx
);
9633 vmx_vcpu_put(&vmx
->vcpu
);
9635 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9636 err
= alloc_apic_access_page(kvm
);
9642 err
= init_rmode_identity_map(kvm
);
9648 nested_vmx_setup_ctls_msrs(vmx
);
9649 vmx
->nested
.vpid02
= allocate_vpid();
9652 vmx
->nested
.posted_intr_nv
= -1;
9653 vmx
->nested
.current_vmptr
= -1ull;
9655 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9658 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9659 * or POSTED_INTR_WAKEUP_VECTOR.
9661 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9662 vmx
->pi_desc
.sn
= 1;
9667 free_vpid(vmx
->nested
.vpid02
);
9668 free_loaded_vmcs(vmx
->loaded_vmcs
);
9670 kfree(vmx
->guest_msrs
);
9672 vmx_destroy_pml_buffer(vmx
);
9674 kvm_vcpu_uninit(&vmx
->vcpu
);
9676 free_vpid(vmx
->vpid
);
9677 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9678 return ERR_PTR(err
);
9681 static void __init
vmx_check_processor_compat(void *rtn
)
9683 struct vmcs_config vmcs_conf
;
9686 if (setup_vmcs_config(&vmcs_conf
) < 0)
9688 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9689 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9690 smp_processor_id());
9695 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9700 /* For VT-d and EPT combination
9701 * 1. MMIO: always map as UC
9703 * a. VT-d without snooping control feature: can't guarantee the
9704 * result, try to trust guest.
9705 * b. VT-d with snooping control feature: snooping control feature of
9706 * VT-d engine can guarantee the cache correctness. Just set it
9707 * to WB to keep consistent with host. So the same as item 3.
9708 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9709 * consistent with host MTRR
9712 cache
= MTRR_TYPE_UNCACHABLE
;
9716 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9717 ipat
= VMX_EPT_IPAT_BIT
;
9718 cache
= MTRR_TYPE_WRBACK
;
9722 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9723 ipat
= VMX_EPT_IPAT_BIT
;
9724 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9725 cache
= MTRR_TYPE_WRBACK
;
9727 cache
= MTRR_TYPE_UNCACHABLE
;
9731 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9734 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9737 static int vmx_get_lpage_level(void)
9739 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9740 return PT_DIRECTORY_LEVEL
;
9742 /* For shadow and EPT supported 1GB page */
9743 return PT_PDPE_LEVEL
;
9746 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9749 * These bits in the secondary execution controls field
9750 * are dynamic, the others are mostly based on the hypervisor
9751 * architecture and the guest's CPUID. Do not touch the
9755 SECONDARY_EXEC_SHADOW_VMCS
|
9756 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9757 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9759 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9761 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9762 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9766 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9767 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9769 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9772 struct kvm_cpuid_entry2
*entry
;
9774 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9775 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9777 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9778 if (entry && (entry->_reg & (_cpuid_mask))) \
9779 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9782 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9783 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9784 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9785 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9786 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9787 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9788 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9789 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9790 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9791 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9792 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9793 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9794 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9795 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9796 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9798 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9799 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9800 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9801 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9802 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9803 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9804 cr4_fixed1_update(bit(11), ecx
, bit(2));
9806 #undef cr4_fixed1_update
9809 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9811 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9813 if (cpu_has_secondary_exec_ctrls()) {
9814 vmx_compute_secondary_exec_control(vmx
);
9815 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9818 if (nested_vmx_allowed(vcpu
))
9819 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9820 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9822 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9823 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9825 if (nested_vmx_allowed(vcpu
))
9826 nested_vmx_cr_fixed1_bits_update(vcpu
);
9829 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9831 if (func
== 1 && nested
)
9832 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9835 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9836 struct x86_exception
*fault
)
9838 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9839 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9841 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9843 if (vmx
->nested
.pml_full
) {
9844 exit_reason
= EXIT_REASON_PML_FULL
;
9845 vmx
->nested
.pml_full
= false;
9846 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9847 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9848 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9850 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9852 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9853 vmcs12
->guest_physical_address
= fault
->address
;
9856 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9858 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9861 /* Callbacks for nested_ept_init_mmu_context: */
9863 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9865 /* return the page table to be shadowed - in our case, EPT12 */
9866 return get_vmcs12(vcpu
)->ept_pointer
;
9869 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9871 WARN_ON(mmu_is_nested(vcpu
));
9872 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9875 kvm_mmu_unload(vcpu
);
9876 kvm_init_shadow_ept_mmu(vcpu
,
9877 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9878 VMX_EPT_EXECUTE_ONLY_BIT
,
9879 nested_ept_ad_enabled(vcpu
));
9880 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9881 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9882 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9884 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9888 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9890 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9893 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9896 bool inequality
, bit
;
9898 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9900 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9901 vmcs12
->page_fault_error_code_match
;
9902 return inequality
^ bit
;
9905 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9906 struct x86_exception
*fault
)
9908 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9910 WARN_ON(!is_guest_mode(vcpu
));
9912 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9913 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9914 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9915 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9916 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9917 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9920 kvm_inject_page_fault(vcpu
, fault
);
9924 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9925 struct vmcs12
*vmcs12
);
9927 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9928 struct vmcs12
*vmcs12
)
9930 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9934 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9936 * Translate L1 physical address to host physical
9937 * address for vmcs02. Keep the page pinned, so this
9938 * physical address remains valid. We keep a reference
9939 * to it so we can release it later.
9941 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9942 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9943 vmx
->nested
.apic_access_page
= NULL
;
9945 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9947 * If translation failed, no matter: This feature asks
9948 * to exit when accessing the given address, and if it
9949 * can never be accessed, this feature won't do
9952 if (!is_error_page(page
)) {
9953 vmx
->nested
.apic_access_page
= page
;
9954 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9955 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9957 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9958 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9960 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9961 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9962 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9964 kvm_vcpu_reload_apic_access_page(vcpu
);
9967 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9968 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9969 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9970 vmx
->nested
.virtual_apic_page
= NULL
;
9972 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9975 * If translation failed, VM entry will fail because
9976 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9977 * Failing the vm entry is _not_ what the processor
9978 * does but it's basically the only possibility we
9979 * have. We could still enter the guest if CR8 load
9980 * exits are enabled, CR8 store exits are enabled, and
9981 * virtualize APIC access is disabled; in this case
9982 * the processor would never use the TPR shadow and we
9983 * could simply clear the bit from the execution
9984 * control. But such a configuration is useless, so
9985 * let's keep the code simple.
9987 if (!is_error_page(page
)) {
9988 vmx
->nested
.virtual_apic_page
= page
;
9989 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9990 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9994 if (nested_cpu_has_posted_intr(vmcs12
)) {
9995 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9996 kunmap(vmx
->nested
.pi_desc_page
);
9997 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9998 vmx
->nested
.pi_desc_page
= NULL
;
10000 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
10001 if (is_error_page(page
))
10003 vmx
->nested
.pi_desc_page
= page
;
10004 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
10005 vmx
->nested
.pi_desc
=
10006 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
10007 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10009 vmcs_write64(POSTED_INTR_DESC_ADDR
,
10010 page_to_phys(vmx
->nested
.pi_desc_page
) +
10011 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10014 if (cpu_has_vmx_msr_bitmap() &&
10015 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
10016 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
10019 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
10020 CPU_BASED_USE_MSR_BITMAPS
);
10023 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
10025 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
10026 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10028 if (vcpu
->arch
.virtual_tsc_khz
== 0)
10031 /* Make sure short timeouts reliably trigger an immediate vmexit.
10032 * hrtimer_start does not guarantee this. */
10033 if (preemption_timeout
<= 1) {
10034 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
10038 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10039 preemption_timeout
*= 1000000;
10040 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
10041 hrtimer_start(&vmx
->nested
.preemption_timer
,
10042 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
10045 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
10046 struct vmcs12
*vmcs12
)
10048 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
10051 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
10052 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
10058 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10059 struct vmcs12
*vmcs12
)
10061 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10064 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10070 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10071 struct vmcs12
*vmcs12
)
10073 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10076 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10083 * Merge L0's and L1's MSR bitmap, return false to indicate that
10084 * we do not use the hardware.
10086 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10087 struct vmcs12
*vmcs12
)
10091 unsigned long *msr_bitmap_l1
;
10092 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10094 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10095 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10098 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10099 if (is_error_page(page
))
10101 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10103 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10105 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10106 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10107 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10108 nested_vmx_disable_intercept_for_msr(
10109 msr_bitmap_l1
, msr_bitmap_l0
,
10112 nested_vmx_disable_intercept_for_msr(
10113 msr_bitmap_l1
, msr_bitmap_l0
,
10114 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10115 MSR_TYPE_R
| MSR_TYPE_W
);
10117 if (nested_cpu_has_vid(vmcs12
)) {
10118 nested_vmx_disable_intercept_for_msr(
10119 msr_bitmap_l1
, msr_bitmap_l0
,
10120 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10122 nested_vmx_disable_intercept_for_msr(
10123 msr_bitmap_l1
, msr_bitmap_l0
,
10124 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10129 kvm_release_page_clean(page
);
10134 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10135 struct vmcs12
*vmcs12
)
10137 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10138 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10139 !nested_cpu_has_vid(vmcs12
) &&
10140 !nested_cpu_has_posted_intr(vmcs12
))
10144 * If virtualize x2apic mode is enabled,
10145 * virtualize apic access must be disabled.
10147 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10148 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10152 * If virtual interrupt delivery is enabled,
10153 * we must exit on external interrupts.
10155 if (nested_cpu_has_vid(vmcs12
) &&
10156 !nested_exit_on_intr(vcpu
))
10160 * bits 15:8 should be zero in posted_intr_nv,
10161 * the descriptor address has been already checked
10162 * in nested_get_vmcs12_pages.
10164 if (nested_cpu_has_posted_intr(vmcs12
) &&
10165 (!nested_cpu_has_vid(vmcs12
) ||
10166 !nested_exit_intr_ack_set(vcpu
) ||
10167 vmcs12
->posted_intr_nv
& 0xff00))
10170 /* tpr shadow is needed by all apicv features. */
10171 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10177 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10178 unsigned long count_field
,
10179 unsigned long addr_field
)
10184 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10185 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10191 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10192 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10193 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10194 pr_debug_ratelimited(
10195 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10196 addr_field
, maxphyaddr
, count
, addr
);
10202 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10203 struct vmcs12
*vmcs12
)
10205 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10206 vmcs12
->vm_exit_msr_store_count
== 0 &&
10207 vmcs12
->vm_entry_msr_load_count
== 0)
10208 return 0; /* Fast path */
10209 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10210 VM_EXIT_MSR_LOAD_ADDR
) ||
10211 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10212 VM_EXIT_MSR_STORE_ADDR
) ||
10213 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10214 VM_ENTRY_MSR_LOAD_ADDR
))
10219 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10220 struct vmcs12
*vmcs12
)
10222 u64 address
= vmcs12
->pml_address
;
10223 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10225 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10226 if (!nested_cpu_has_ept(vmcs12
) ||
10227 !IS_ALIGNED(address
, 4096) ||
10228 address
>> maxphyaddr
)
10235 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10236 struct vmx_msr_entry
*e
)
10238 /* x2APIC MSR accesses are not allowed */
10239 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10241 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10242 e
->index
== MSR_IA32_UCODE_REV
)
10244 if (e
->reserved
!= 0)
10249 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10250 struct vmx_msr_entry
*e
)
10252 if (e
->index
== MSR_FS_BASE
||
10253 e
->index
== MSR_GS_BASE
||
10254 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10255 nested_vmx_msr_check_common(vcpu
, e
))
10260 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10261 struct vmx_msr_entry
*e
)
10263 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10264 nested_vmx_msr_check_common(vcpu
, e
))
10270 * Load guest's/host's msr at nested entry/exit.
10271 * return 0 for success, entry index for failure.
10273 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10276 struct vmx_msr_entry e
;
10277 struct msr_data msr
;
10279 msr
.host_initiated
= false;
10280 for (i
= 0; i
< count
; i
++) {
10281 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10283 pr_debug_ratelimited(
10284 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10285 __func__
, i
, gpa
+ i
* sizeof(e
));
10288 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10289 pr_debug_ratelimited(
10290 "%s check failed (%u, 0x%x, 0x%x)\n",
10291 __func__
, i
, e
.index
, e
.reserved
);
10294 msr
.index
= e
.index
;
10295 msr
.data
= e
.value
;
10296 if (kvm_set_msr(vcpu
, &msr
)) {
10297 pr_debug_ratelimited(
10298 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10299 __func__
, i
, e
.index
, e
.value
);
10308 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10311 struct vmx_msr_entry e
;
10313 for (i
= 0; i
< count
; i
++) {
10314 struct msr_data msr_info
;
10315 if (kvm_vcpu_read_guest(vcpu
,
10316 gpa
+ i
* sizeof(e
),
10317 &e
, 2 * sizeof(u32
))) {
10318 pr_debug_ratelimited(
10319 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10320 __func__
, i
, gpa
+ i
* sizeof(e
));
10323 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10324 pr_debug_ratelimited(
10325 "%s check failed (%u, 0x%x, 0x%x)\n",
10326 __func__
, i
, e
.index
, e
.reserved
);
10329 msr_info
.host_initiated
= false;
10330 msr_info
.index
= e
.index
;
10331 if (kvm_get_msr(vcpu
, &msr_info
)) {
10332 pr_debug_ratelimited(
10333 "%s cannot read MSR (%u, 0x%x)\n",
10334 __func__
, i
, e
.index
);
10337 if (kvm_vcpu_write_guest(vcpu
,
10338 gpa
+ i
* sizeof(e
) +
10339 offsetof(struct vmx_msr_entry
, value
),
10340 &msr_info
.data
, sizeof(msr_info
.data
))) {
10341 pr_debug_ratelimited(
10342 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10343 __func__
, i
, e
.index
, msr_info
.data
);
10350 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10352 unsigned long invalid_mask
;
10354 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10355 return (val
& invalid_mask
) == 0;
10359 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10360 * emulating VM entry into a guest with EPT enabled.
10361 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10362 * is assigned to entry_failure_code on failure.
10364 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10365 u32
*entry_failure_code
)
10367 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10368 if (!nested_cr3_valid(vcpu
, cr3
)) {
10369 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10374 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10375 * must not be dereferenced.
10377 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10379 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10380 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10385 vcpu
->arch
.cr3
= cr3
;
10386 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10389 kvm_mmu_reset_context(vcpu
);
10394 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10395 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10396 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10397 * guest in a way that will both be appropriate to L1's requests, and our
10398 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10399 * function also has additional necessary side-effects, like setting various
10400 * vcpu->arch fields.
10401 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10402 * is assigned to entry_failure_code on failure.
10404 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10405 bool from_vmentry
, u32
*entry_failure_code
)
10407 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10408 u32 exec_control
, vmcs12_exec_ctrl
;
10410 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10411 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10412 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10413 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10414 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10415 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10416 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10417 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10418 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10419 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10420 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10421 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10422 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10423 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10424 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10425 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10426 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10427 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10428 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10429 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10430 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10431 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10432 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10433 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10434 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10435 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10436 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10437 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10438 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10439 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10440 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10441 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10442 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10443 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10444 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10445 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10447 if (from_vmentry
&&
10448 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10449 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10450 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10452 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10453 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10455 if (from_vmentry
) {
10456 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10457 vmcs12
->vm_entry_intr_info_field
);
10458 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10459 vmcs12
->vm_entry_exception_error_code
);
10460 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10461 vmcs12
->vm_entry_instruction_len
);
10462 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10463 vmcs12
->guest_interruptibility_info
);
10464 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10465 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10467 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10469 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10470 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10471 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10472 vmcs12
->guest_pending_dbg_exceptions
);
10473 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10474 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10476 if (nested_cpu_has_xsaves(vmcs12
))
10477 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10478 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10480 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10482 /* Preemption timer setting is only taken from vmcs01. */
10483 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10484 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10485 if (vmx
->hv_deadline_tsc
== -1)
10486 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10488 /* Posted interrupts setting is only taken from vmcs12. */
10489 if (nested_cpu_has_posted_intr(vmcs12
)) {
10490 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10491 vmx
->nested
.pi_pending
= false;
10492 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10494 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10497 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10499 vmx
->nested
.preemption_timer_expired
= false;
10500 if (nested_cpu_has_preemption_timer(vmcs12
))
10501 vmx_start_preemption_timer(vcpu
);
10504 * Whether page-faults are trapped is determined by a combination of
10505 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10506 * If enable_ept, L0 doesn't care about page faults and we should
10507 * set all of these to L1's desires. However, if !enable_ept, L0 does
10508 * care about (at least some) page faults, and because it is not easy
10509 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10510 * to exit on each and every L2 page fault. This is done by setting
10511 * MASK=MATCH=0 and (see below) EB.PF=1.
10512 * Note that below we don't need special code to set EB.PF beyond the
10513 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10514 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10515 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10517 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10518 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10519 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10520 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10522 if (cpu_has_secondary_exec_ctrls()) {
10523 exec_control
= vmx
->secondary_exec_control
;
10525 /* Take the following fields only from vmcs12 */
10526 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10527 SECONDARY_EXEC_ENABLE_INVPCID
|
10528 SECONDARY_EXEC_RDTSCP
|
10529 SECONDARY_EXEC_XSAVES
|
10530 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10531 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10532 SECONDARY_EXEC_ENABLE_VMFUNC
);
10533 if (nested_cpu_has(vmcs12
,
10534 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10535 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10536 ~SECONDARY_EXEC_ENABLE_PML
;
10537 exec_control
|= vmcs12_exec_ctrl
;
10540 /* All VMFUNCs are currently emulated through L0 vmexits. */
10541 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10542 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10544 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10545 vmcs_write64(EOI_EXIT_BITMAP0
,
10546 vmcs12
->eoi_exit_bitmap0
);
10547 vmcs_write64(EOI_EXIT_BITMAP1
,
10548 vmcs12
->eoi_exit_bitmap1
);
10549 vmcs_write64(EOI_EXIT_BITMAP2
,
10550 vmcs12
->eoi_exit_bitmap2
);
10551 vmcs_write64(EOI_EXIT_BITMAP3
,
10552 vmcs12
->eoi_exit_bitmap3
);
10553 vmcs_write16(GUEST_INTR_STATUS
,
10554 vmcs12
->guest_intr_status
);
10558 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10559 * nested_get_vmcs12_pages will either fix it up or
10560 * remove the VM execution control.
10562 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10563 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10565 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10570 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10571 * Some constant fields are set here by vmx_set_constant_host_state().
10572 * Other fields are different per CPU, and will be set later when
10573 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10575 vmx_set_constant_host_state(vmx
);
10578 * Set the MSR load/store lists to match L0's settings.
10580 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10581 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10582 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10583 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10584 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10587 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10588 * entry, but only if the current (host) sp changed from the value
10589 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10590 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10591 * here we just force the write to happen on entry.
10595 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10596 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10597 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10598 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10599 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10602 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10603 * nested_get_vmcs12_pages can't fix it up, the illegal value
10604 * will result in a VM entry failure.
10606 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10607 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10608 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10610 #ifdef CONFIG_X86_64
10611 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10612 CPU_BASED_CR8_STORE_EXITING
;
10617 * Merging of IO bitmap not currently supported.
10618 * Rather, exit every time.
10620 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10621 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10623 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10625 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10626 * bitwise-or of what L1 wants to trap for L2, and what we want to
10627 * trap. Note that CR0.TS also needs updating - we do this later.
10629 update_exception_bitmap(vcpu
);
10630 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10631 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10633 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10634 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10635 * bits are further modified by vmx_set_efer() below.
10637 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10639 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10640 * emulated by vmx_set_efer(), below.
10642 vm_entry_controls_init(vmx
,
10643 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10644 ~VM_ENTRY_IA32E_MODE
) |
10645 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10647 if (from_vmentry
&&
10648 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10649 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10650 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10651 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10652 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10655 set_cr4_guest_host_mask(vmx
);
10657 if (from_vmentry
&&
10658 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10659 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10661 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10662 vmcs_write64(TSC_OFFSET
,
10663 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10665 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10666 if (kvm_has_tsc_control
)
10667 decache_tsc_multiplier(vmx
);
10671 * There is no direct mapping between vpid02 and vpid12, the
10672 * vpid02 is per-vCPU for L0 and reused while the value of
10673 * vpid12 is changed w/ one invvpid during nested vmentry.
10674 * The vpid12 is allocated by L1 for L2, so it will not
10675 * influence global bitmap(for vpid01 and vpid02 allocation)
10676 * even if spawn a lot of nested vCPUs.
10678 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10679 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10680 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10681 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10682 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10685 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10686 vmx_flush_tlb(vcpu
);
10693 * Conceptually we want to copy the PML address and index from
10694 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10695 * since we always flush the log on each vmexit, this happens
10696 * to be equivalent to simply resetting the fields in vmcs02.
10698 ASSERT(vmx
->pml_pg
);
10699 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10700 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10703 if (nested_cpu_has_ept(vmcs12
)) {
10704 if (nested_ept_init_mmu_context(vcpu
)) {
10705 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10708 } else if (nested_cpu_has2(vmcs12
,
10709 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10710 vmx_flush_tlb_ept_only(vcpu
);
10714 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10715 * bits which we consider mandatory enabled.
10716 * The CR0_READ_SHADOW is what L2 should have expected to read given
10717 * the specifications by L1; It's not enough to take
10718 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10719 * have more bits than L1 expected.
10721 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10722 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10724 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10725 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10727 if (from_vmentry
&&
10728 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10729 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10730 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10731 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10733 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10734 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10735 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10737 /* Shadow page tables on either EPT or shadow page tables. */
10738 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10739 entry_failure_code
))
10743 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10746 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10749 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10750 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10751 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10752 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10755 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10756 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10760 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10764 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10765 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10766 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10768 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10769 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10771 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10772 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10774 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10775 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10777 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10778 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10780 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10781 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10783 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10784 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10786 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10787 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10788 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10789 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10790 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10791 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10792 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10793 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10794 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10795 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10796 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10797 vmx
->nested
.nested_vmx_exit_ctls_low
,
10798 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10799 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10800 vmx
->nested
.nested_vmx_entry_ctls_low
,
10801 vmx
->nested
.nested_vmx_entry_ctls_high
))
10802 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10804 if (nested_cpu_has_vmfunc(vmcs12
)) {
10805 if (vmcs12
->vm_function_control
&
10806 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10807 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10809 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10810 if (!nested_cpu_has_ept(vmcs12
) ||
10811 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10812 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10816 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10817 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10819 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10820 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10821 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10822 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10827 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10832 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10834 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10835 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10838 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10839 vmcs12
->vmcs_link_pointer
!= -1ull) {
10840 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10845 * If the load IA32_EFER VM-entry control is 1, the following checks
10846 * are performed on the field for the IA32_EFER MSR:
10847 * - Bits reserved in the IA32_EFER MSR must be 0.
10848 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10849 * the IA-32e mode guest VM-exit control. It must also be identical
10850 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10853 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10854 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10855 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10856 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10857 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10858 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10859 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10864 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10865 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10866 * the values of the LMA and LME bits in the field must each be that of
10867 * the host address-space size VM-exit control.
10869 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10870 ia32e
= (vmcs12
->vm_exit_controls
&
10871 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10872 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10873 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10874 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10881 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10883 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10884 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10885 struct loaded_vmcs
*vmcs02
;
10889 vmcs02
= nested_get_current_vmcs02(vmx
);
10893 enter_guest_mode(vcpu
);
10895 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10896 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10898 vmx_switch_vmcs(vcpu
, vmcs02
);
10899 vmx_segment_cache_clear(vmx
);
10901 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10902 leave_guest_mode(vcpu
);
10903 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10904 nested_vmx_entry_failure(vcpu
, vmcs12
,
10905 EXIT_REASON_INVALID_STATE
, exit_qual
);
10909 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10911 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10912 vmcs12
->vm_entry_msr_load_addr
,
10913 vmcs12
->vm_entry_msr_load_count
);
10914 if (msr_entry_idx
) {
10915 leave_guest_mode(vcpu
);
10916 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10917 nested_vmx_entry_failure(vcpu
, vmcs12
,
10918 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10923 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10924 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10925 * returned as far as L1 is concerned. It will only return (and set
10926 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10932 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10933 * for running an L2 nested guest.
10935 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10937 struct vmcs12
*vmcs12
;
10938 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10939 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10943 if (!nested_vmx_check_permission(vcpu
))
10946 if (!nested_vmx_check_vmcs12(vcpu
))
10949 vmcs12
= get_vmcs12(vcpu
);
10951 if (enable_shadow_vmcs
)
10952 copy_shadow_to_vmcs12(vmx
);
10955 * The nested entry process starts with enforcing various prerequisites
10956 * on vmcs12 as required by the Intel SDM, and act appropriately when
10957 * they fail: As the SDM explains, some conditions should cause the
10958 * instruction to fail, while others will cause the instruction to seem
10959 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10960 * To speed up the normal (success) code path, we should avoid checking
10961 * for misconfigurations which will anyway be caught by the processor
10962 * when using the merged vmcs02.
10964 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10965 nested_vmx_failValid(vcpu
,
10966 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10970 if (vmcs12
->launch_state
== launch
) {
10971 nested_vmx_failValid(vcpu
,
10972 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10973 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10977 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10979 nested_vmx_failValid(vcpu
, ret
);
10984 * After this point, the trap flag no longer triggers a singlestep trap
10985 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10986 * This is not 100% correct; for performance reasons, we delegate most
10987 * of the checks on host state to the processor. If those fail,
10988 * the singlestep trap is missed.
10990 skip_emulated_instruction(vcpu
);
10992 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10994 nested_vmx_entry_failure(vcpu
, vmcs12
,
10995 EXIT_REASON_INVALID_STATE
, exit_qual
);
11000 * We're finally done with prerequisite checking, and can start with
11001 * the nested entry.
11004 ret
= enter_vmx_non_root_mode(vcpu
, true);
11008 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
11009 return kvm_vcpu_halt(vcpu
);
11011 vmx
->nested
.nested_run_pending
= 1;
11016 return kvm_skip_emulated_instruction(vcpu
);
11020 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11021 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11022 * This function returns the new value we should put in vmcs12.guest_cr0.
11023 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11024 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11025 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11026 * didn't trap the bit, because if L1 did, so would L0).
11027 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11028 * been modified by L2, and L1 knows it. So just leave the old value of
11029 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11030 * isn't relevant, because if L0 traps this bit it can set it to anything.
11031 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11032 * changed these bits, and therefore they need to be updated, but L0
11033 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11034 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11036 static inline unsigned long
11037 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11040 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11041 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11042 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11043 vcpu
->arch
.cr0_guest_owned_bits
));
11046 static inline unsigned long
11047 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11050 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11051 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11052 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11053 vcpu
->arch
.cr4_guest_owned_bits
));
11056 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11057 struct vmcs12
*vmcs12
)
11062 if (vcpu
->arch
.exception
.injected
) {
11063 nr
= vcpu
->arch
.exception
.nr
;
11064 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11066 if (kvm_exception_is_soft(nr
)) {
11067 vmcs12
->vm_exit_instruction_len
=
11068 vcpu
->arch
.event_exit_inst_len
;
11069 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11071 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11073 if (vcpu
->arch
.exception
.has_error_code
) {
11074 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11075 vmcs12
->idt_vectoring_error_code
=
11076 vcpu
->arch
.exception
.error_code
;
11079 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11080 } else if (vcpu
->arch
.nmi_injected
) {
11081 vmcs12
->idt_vectoring_info_field
=
11082 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11083 } else if (vcpu
->arch
.interrupt
.pending
) {
11084 nr
= vcpu
->arch
.interrupt
.nr
;
11085 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11087 if (vcpu
->arch
.interrupt
.soft
) {
11088 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11089 vmcs12
->vm_entry_instruction_len
=
11090 vcpu
->arch
.event_exit_inst_len
;
11092 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11094 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11098 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11100 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11101 unsigned long exit_qual
;
11103 if (kvm_event_needs_reinjection(vcpu
))
11106 if (vcpu
->arch
.exception
.pending
&&
11107 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11108 if (vmx
->nested
.nested_run_pending
)
11110 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11111 vcpu
->arch
.exception
.pending
= false;
11115 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11116 vmx
->nested
.preemption_timer_expired
) {
11117 if (vmx
->nested
.nested_run_pending
)
11119 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11123 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11124 if (vmx
->nested
.nested_run_pending
)
11126 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11127 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11128 INTR_INFO_VALID_MASK
, 0);
11130 * The NMI-triggered VM exit counts as injection:
11131 * clear this one and block further NMIs.
11133 vcpu
->arch
.nmi_pending
= 0;
11134 vmx_set_nmi_mask(vcpu
, true);
11138 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11139 nested_exit_on_intr(vcpu
)) {
11140 if (vmx
->nested
.nested_run_pending
)
11142 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11146 vmx_complete_nested_posted_interrupt(vcpu
);
11150 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11152 ktime_t remaining
=
11153 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11156 if (ktime_to_ns(remaining
) <= 0)
11159 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11160 do_div(value
, 1000000);
11161 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11165 * Update the guest state fields of vmcs12 to reflect changes that
11166 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11167 * VM-entry controls is also updated, since this is really a guest
11170 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11172 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11173 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11175 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11176 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11177 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11179 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11180 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11181 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11182 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11183 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11184 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11185 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11186 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11187 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11188 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11189 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11190 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11191 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11192 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11193 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11194 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11195 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11196 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11197 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11198 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11199 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11200 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11201 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11202 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11203 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11204 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11205 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11206 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11207 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11208 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11209 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11210 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11211 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11212 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11213 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11214 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11216 vmcs12
->guest_interruptibility_info
=
11217 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11218 vmcs12
->guest_pending_dbg_exceptions
=
11219 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11220 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11221 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11223 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11225 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11226 if (vmcs12
->vm_exit_controls
&
11227 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11228 vmcs12
->vmx_preemption_timer_value
=
11229 vmx_get_preemption_timer_value(vcpu
);
11230 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11234 * In some cases (usually, nested EPT), L2 is allowed to change its
11235 * own CR3 without exiting. If it has changed it, we must keep it.
11236 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11237 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11239 * Additionally, restore L2's PDPTR to vmcs12.
11242 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11243 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11244 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11245 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11246 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11249 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11251 if (nested_cpu_has_vid(vmcs12
))
11252 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11254 vmcs12
->vm_entry_controls
=
11255 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11256 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11258 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11259 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11260 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11263 /* TODO: These cannot have changed unless we have MSR bitmaps and
11264 * the relevant bit asks not to trap the change */
11265 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11266 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11267 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11268 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11269 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11270 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11271 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11272 if (kvm_mpx_supported())
11273 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11277 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11278 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11279 * and this function updates it to reflect the changes to the guest state while
11280 * L2 was running (and perhaps made some exits which were handled directly by L0
11281 * without going back to L1), and to reflect the exit reason.
11282 * Note that we do not have to copy here all VMCS fields, just those that
11283 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11284 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11285 * which already writes to vmcs12 directly.
11287 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11288 u32 exit_reason
, u32 exit_intr_info
,
11289 unsigned long exit_qualification
)
11291 /* update guest state fields: */
11292 sync_vmcs12(vcpu
, vmcs12
);
11294 /* update exit information fields: */
11296 vmcs12
->vm_exit_reason
= exit_reason
;
11297 vmcs12
->exit_qualification
= exit_qualification
;
11298 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11300 vmcs12
->idt_vectoring_info_field
= 0;
11301 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11302 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11304 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11305 vmcs12
->launch_state
= 1;
11307 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11308 * instead of reading the real value. */
11309 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11312 * Transfer the event that L0 or L1 may wanted to inject into
11313 * L2 to IDT_VECTORING_INFO_FIELD.
11315 vmcs12_save_pending_event(vcpu
, vmcs12
);
11319 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11320 * preserved above and would only end up incorrectly in L1.
11322 vcpu
->arch
.nmi_injected
= false;
11323 kvm_clear_exception_queue(vcpu
);
11324 kvm_clear_interrupt_queue(vcpu
);
11328 * A part of what we need to when the nested L2 guest exits and we want to
11329 * run its L1 parent, is to reset L1's guest state to the host state specified
11331 * This function is to be called not only on normal nested exit, but also on
11332 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11333 * Failures During or After Loading Guest State").
11334 * This function should be called when the active VMCS is L1's (vmcs01).
11336 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11337 struct vmcs12
*vmcs12
)
11339 struct kvm_segment seg
;
11340 u32 entry_failure_code
;
11342 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11343 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11344 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11345 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11347 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11348 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11350 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11351 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11352 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11354 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11355 * actually changed, because vmx_set_cr0 refers to efer set above.
11357 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11358 * (KVM doesn't change it);
11360 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11361 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11363 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11364 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11365 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11367 nested_ept_uninit_mmu_context(vcpu
);
11370 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11371 * couldn't have changed.
11373 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11374 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11377 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11381 * Trivially support vpid by letting L2s share their parent
11382 * L1's vpid. TODO: move to a more elaborate solution, giving
11383 * each L2 its own vpid and exposing the vpid feature to L1.
11385 vmx_flush_tlb(vcpu
);
11387 /* Restore posted intr vector. */
11388 if (nested_cpu_has_posted_intr(vmcs12
))
11389 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11391 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11392 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11393 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11394 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11395 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11396 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11397 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11399 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11400 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11401 vmcs_write64(GUEST_BNDCFGS
, 0);
11403 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11404 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11405 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11407 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11408 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11409 vmcs12
->host_ia32_perf_global_ctrl
);
11411 /* Set L1 segment info according to Intel SDM
11412 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11413 seg
= (struct kvm_segment
) {
11415 .limit
= 0xFFFFFFFF,
11416 .selector
= vmcs12
->host_cs_selector
,
11422 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11426 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11427 seg
= (struct kvm_segment
) {
11429 .limit
= 0xFFFFFFFF,
11436 seg
.selector
= vmcs12
->host_ds_selector
;
11437 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11438 seg
.selector
= vmcs12
->host_es_selector
;
11439 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11440 seg
.selector
= vmcs12
->host_ss_selector
;
11441 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11442 seg
.selector
= vmcs12
->host_fs_selector
;
11443 seg
.base
= vmcs12
->host_fs_base
;
11444 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11445 seg
.selector
= vmcs12
->host_gs_selector
;
11446 seg
.base
= vmcs12
->host_gs_base
;
11447 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11448 seg
= (struct kvm_segment
) {
11449 .base
= vmcs12
->host_tr_base
,
11451 .selector
= vmcs12
->host_tr_selector
,
11455 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11457 kvm_set_dr(vcpu
, 7, 0x400);
11458 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11460 if (cpu_has_vmx_msr_bitmap())
11461 vmx_set_msr_bitmap(vcpu
);
11463 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11464 vmcs12
->vm_exit_msr_load_count
))
11465 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11469 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11470 * and modify vmcs12 to make it see what it would expect to see there if
11471 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11473 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11474 u32 exit_intr_info
,
11475 unsigned long exit_qualification
)
11477 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11478 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11480 /* trying to cancel vmlaunch/vmresume is a bug */
11481 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11484 * The only expected VM-instruction error is "VM entry with
11485 * invalid control field(s)." Anything else indicates a
11488 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11489 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11491 leave_guest_mode(vcpu
);
11493 if (likely(!vmx
->fail
)) {
11494 if (exit_reason
== -1)
11495 sync_vmcs12(vcpu
, vmcs12
);
11497 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11498 exit_qualification
);
11500 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11501 vmcs12
->vm_exit_msr_store_count
))
11502 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11505 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11506 vm_entry_controls_reset_shadow(vmx
);
11507 vm_exit_controls_reset_shadow(vmx
);
11508 vmx_segment_cache_clear(vmx
);
11510 /* if no vmcs02 cache requested, remove the one we used */
11511 if (VMCS02_POOL_SIZE
== 0)
11512 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11514 /* Update any VMCS fields that might have changed while L2 ran */
11515 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11516 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11517 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11518 if (vmx
->hv_deadline_tsc
== -1)
11519 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11520 PIN_BASED_VMX_PREEMPTION_TIMER
);
11522 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11523 PIN_BASED_VMX_PREEMPTION_TIMER
);
11524 if (kvm_has_tsc_control
)
11525 decache_tsc_multiplier(vmx
);
11527 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11528 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11529 vmx_set_virtual_x2apic_mode(vcpu
,
11530 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11531 } else if (!nested_cpu_has_ept(vmcs12
) &&
11532 nested_cpu_has2(vmcs12
,
11533 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11534 vmx_flush_tlb_ept_only(vcpu
);
11537 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11540 /* Unpin physical memory we referred to in vmcs02 */
11541 if (vmx
->nested
.apic_access_page
) {
11542 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11543 vmx
->nested
.apic_access_page
= NULL
;
11545 if (vmx
->nested
.virtual_apic_page
) {
11546 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11547 vmx
->nested
.virtual_apic_page
= NULL
;
11549 if (vmx
->nested
.pi_desc_page
) {
11550 kunmap(vmx
->nested
.pi_desc_page
);
11551 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11552 vmx
->nested
.pi_desc_page
= NULL
;
11553 vmx
->nested
.pi_desc
= NULL
;
11557 * We are now running in L2, mmu_notifier will force to reload the
11558 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11560 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11562 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11563 vmx
->nested
.sync_shadow_vmcs
= true;
11565 /* in case we halted in L2 */
11566 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11568 if (likely(!vmx
->fail
)) {
11570 * TODO: SDM says that with acknowledge interrupt on
11571 * exit, bit 31 of the VM-exit interrupt information
11572 * (valid interrupt) is always set to 1 on
11573 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11574 * need kvm_cpu_has_interrupt(). See the commit
11575 * message for details.
11577 if (nested_exit_intr_ack_set(vcpu
) &&
11578 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11579 kvm_cpu_has_interrupt(vcpu
)) {
11580 int irq
= kvm_cpu_get_interrupt(vcpu
);
11582 vmcs12
->vm_exit_intr_info
= irq
|
11583 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11586 if (exit_reason
!= -1)
11587 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11588 vmcs12
->exit_qualification
,
11589 vmcs12
->idt_vectoring_info_field
,
11590 vmcs12
->vm_exit_intr_info
,
11591 vmcs12
->vm_exit_intr_error_code
,
11594 load_vmcs12_host_state(vcpu
, vmcs12
);
11600 * After an early L2 VM-entry failure, we're now back
11601 * in L1 which thinks it just finished a VMLAUNCH or
11602 * VMRESUME instruction, so we need to set the failure
11603 * flag and the VM-instruction error field of the VMCS
11606 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11608 * The emulated instruction was already skipped in
11609 * nested_vmx_run, but the updated RIP was never
11610 * written back to the vmcs01.
11612 skip_emulated_instruction(vcpu
);
11617 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11619 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11621 if (is_guest_mode(vcpu
)) {
11622 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11623 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11625 free_nested(to_vmx(vcpu
));
11629 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11630 * 23.7 "VM-entry failures during or after loading guest state" (this also
11631 * lists the acceptable exit-reason and exit-qualification parameters).
11632 * It should only be called before L2 actually succeeded to run, and when
11633 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11635 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11636 struct vmcs12
*vmcs12
,
11637 u32 reason
, unsigned long qualification
)
11639 load_vmcs12_host_state(vcpu
, vmcs12
);
11640 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11641 vmcs12
->exit_qualification
= qualification
;
11642 nested_vmx_succeed(vcpu
);
11643 if (enable_shadow_vmcs
)
11644 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11647 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11648 struct x86_instruction_info
*info
,
11649 enum x86_intercept_stage stage
)
11651 return X86EMUL_CONTINUE
;
11654 #ifdef CONFIG_X86_64
11655 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11656 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11657 u64 divisor
, u64
*result
)
11659 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11661 /* To avoid the overflow on divq */
11662 if (high
>= divisor
)
11665 /* Low hold the result, high hold rem which is discarded */
11666 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11667 "rm" (divisor
), "0" (low
), "1" (high
));
11673 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11675 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11676 u64 tscl
= rdtsc();
11677 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11678 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11680 /* Convert to host delta tsc if tsc scaling is enabled */
11681 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11682 u64_shl_div_u64(delta_tsc
,
11683 kvm_tsc_scaling_ratio_frac_bits
,
11684 vcpu
->arch
.tsc_scaling_ratio
,
11689 * If the delta tsc can't fit in the 32 bit after the multi shift,
11690 * we can't use the preemption timer.
11691 * It's possible that it fits on later vmentries, but checking
11692 * on every vmentry is costly so we just use an hrtimer.
11694 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11697 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11698 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11699 PIN_BASED_VMX_PREEMPTION_TIMER
);
11701 return delta_tsc
== 0;
11704 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11707 vmx
->hv_deadline_tsc
= -1;
11708 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11709 PIN_BASED_VMX_PREEMPTION_TIMER
);
11713 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11716 shrink_ple_window(vcpu
);
11719 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11720 struct kvm_memory_slot
*slot
)
11722 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11723 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11726 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11727 struct kvm_memory_slot
*slot
)
11729 kvm_mmu_slot_set_dirty(kvm
, slot
);
11732 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11734 kvm_flush_pml_buffers(kvm
);
11737 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11739 struct vmcs12
*vmcs12
;
11740 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11742 struct page
*page
= NULL
;
11745 if (is_guest_mode(vcpu
)) {
11746 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11749 * Check if PML is enabled for the nested guest.
11750 * Whether eptp bit 6 is set is already checked
11751 * as part of A/D emulation.
11753 vmcs12
= get_vmcs12(vcpu
);
11754 if (!nested_cpu_has_pml(vmcs12
))
11757 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11758 vmx
->nested
.pml_full
= true;
11762 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11764 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11765 if (is_error_page(page
))
11768 pml_address
= kmap(page
);
11769 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11771 kvm_release_page_clean(page
);
11777 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11778 struct kvm_memory_slot
*memslot
,
11779 gfn_t offset
, unsigned long mask
)
11781 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11784 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11786 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11787 struct pi_desc old
, new;
11791 old
.control
= new.control
= pi_desc
->control
;
11792 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11793 "Wakeup handler not enabled while the VCPU is blocked\n");
11795 dest
= cpu_physical_id(vcpu
->cpu
);
11797 if (x2apic_enabled())
11800 new.ndst
= (dest
<< 8) & 0xFF00;
11802 /* set 'NV' to 'notification vector' */
11803 new.nv
= POSTED_INTR_VECTOR
;
11804 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11805 new.control
) != old
.control
);
11807 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11808 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11809 list_del(&vcpu
->blocked_vcpu_list
);
11810 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11811 vcpu
->pre_pcpu
= -1;
11816 * This routine does the following things for vCPU which is going
11817 * to be blocked if VT-d PI is enabled.
11818 * - Store the vCPU to the wakeup list, so when interrupts happen
11819 * we can find the right vCPU to wake up.
11820 * - Change the Posted-interrupt descriptor as below:
11821 * 'NDST' <-- vcpu->pre_pcpu
11822 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11823 * - If 'ON' is set during this process, which means at least one
11824 * interrupt is posted for this vCPU, we cannot block it, in
11825 * this case, return 1, otherwise, return 0.
11828 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11831 struct pi_desc old
, new;
11832 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11834 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11835 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11836 !kvm_vcpu_apicv_active(vcpu
))
11839 WARN_ON(irqs_disabled());
11840 local_irq_disable();
11841 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11842 vcpu
->pre_pcpu
= vcpu
->cpu
;
11843 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11844 list_add_tail(&vcpu
->blocked_vcpu_list
,
11845 &per_cpu(blocked_vcpu_on_cpu
,
11847 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11851 old
.control
= new.control
= pi_desc
->control
;
11853 WARN((pi_desc
->sn
== 1),
11854 "Warning: SN field of posted-interrupts "
11855 "is set before blocking\n");
11858 * Since vCPU can be preempted during this process,
11859 * vcpu->cpu could be different with pre_pcpu, we
11860 * need to set pre_pcpu as the destination of wakeup
11861 * notification event, then we can find the right vCPU
11862 * to wakeup in wakeup handler if interrupts happen
11863 * when the vCPU is in blocked state.
11865 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11867 if (x2apic_enabled())
11870 new.ndst
= (dest
<< 8) & 0xFF00;
11872 /* set 'NV' to 'wakeup vector' */
11873 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11874 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11875 new.control
) != old
.control
);
11877 /* We should not block the vCPU if an interrupt is posted for it. */
11878 if (pi_test_on(pi_desc
) == 1)
11879 __pi_post_block(vcpu
);
11881 local_irq_enable();
11882 return (vcpu
->pre_pcpu
== -1);
11885 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11887 if (pi_pre_block(vcpu
))
11890 if (kvm_lapic_hv_timer_in_use(vcpu
))
11891 kvm_lapic_switch_to_sw_timer(vcpu
);
11896 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11898 if (vcpu
->pre_pcpu
== -1)
11901 WARN_ON(irqs_disabled());
11902 local_irq_disable();
11903 __pi_post_block(vcpu
);
11904 local_irq_enable();
11907 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11909 if (kvm_x86_ops
->set_hv_timer
)
11910 kvm_lapic_switch_to_hv_timer(vcpu
);
11912 pi_post_block(vcpu
);
11916 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11919 * @host_irq: host irq of the interrupt
11920 * @guest_irq: gsi of the interrupt
11921 * @set: set or unset PI
11922 * returns 0 on success, < 0 on failure
11924 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11925 uint32_t guest_irq
, bool set
)
11927 struct kvm_kernel_irq_routing_entry
*e
;
11928 struct kvm_irq_routing_table
*irq_rt
;
11929 struct kvm_lapic_irq irq
;
11930 struct kvm_vcpu
*vcpu
;
11931 struct vcpu_data vcpu_info
;
11934 if (!kvm_arch_has_assigned_device(kvm
) ||
11935 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11936 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11939 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11940 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11941 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11942 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11943 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11944 guest_irq
, irq_rt
->nr_rt_entries
);
11948 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11949 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11952 * VT-d PI cannot support posting multicast/broadcast
11953 * interrupts to a vCPU, we still use interrupt remapping
11954 * for these kind of interrupts.
11956 * For lowest-priority interrupts, we only support
11957 * those with single CPU as the destination, e.g. user
11958 * configures the interrupts via /proc/irq or uses
11959 * irqbalance to make the interrupts single-CPU.
11961 * We will support full lowest-priority interrupt later.
11964 kvm_set_msi_irq(kvm
, e
, &irq
);
11965 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11967 * Make sure the IRTE is in remapped mode if
11968 * we don't handle it in posted mode.
11970 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11973 "failed to back to remapped mode, irq: %u\n",
11981 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11982 vcpu_info
.vector
= irq
.vector
;
11984 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11985 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11988 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11990 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11993 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12001 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12005 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12007 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12008 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12009 FEATURE_CONTROL_LMCE
;
12011 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12012 ~FEATURE_CONTROL_LMCE
;
12015 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12017 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12018 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12023 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12025 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12027 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12028 if (vmx
->nested
.smm
.guest_mode
)
12029 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12031 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12032 vmx
->nested
.vmxon
= false;
12036 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12041 if (vmx
->nested
.smm
.vmxon
) {
12042 vmx
->nested
.vmxon
= true;
12043 vmx
->nested
.smm
.vmxon
= false;
12046 if (vmx
->nested
.smm
.guest_mode
) {
12047 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12048 ret
= enter_vmx_non_root_mode(vcpu
, false);
12049 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12053 vmx
->nested
.smm
.guest_mode
= false;
12058 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12063 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
12064 .cpu_has_kvm_support
= cpu_has_kvm_support
,
12065 .disabled_by_bios
= vmx_disabled_by_bios
,
12066 .hardware_setup
= hardware_setup
,
12067 .hardware_unsetup
= hardware_unsetup
,
12068 .check_processor_compatibility
= vmx_check_processor_compat
,
12069 .hardware_enable
= hardware_enable
,
12070 .hardware_disable
= hardware_disable
,
12071 .cpu_has_accelerated_tpr
= report_flexpriority
,
12072 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
12074 .vcpu_create
= vmx_create_vcpu
,
12075 .vcpu_free
= vmx_free_vcpu
,
12076 .vcpu_reset
= vmx_vcpu_reset
,
12078 .prepare_guest_switch
= vmx_save_host_state
,
12079 .vcpu_load
= vmx_vcpu_load
,
12080 .vcpu_put
= vmx_vcpu_put
,
12082 .update_bp_intercept
= update_exception_bitmap
,
12083 .get_msr
= vmx_get_msr
,
12084 .set_msr
= vmx_set_msr
,
12085 .get_segment_base
= vmx_get_segment_base
,
12086 .get_segment
= vmx_get_segment
,
12087 .set_segment
= vmx_set_segment
,
12088 .get_cpl
= vmx_get_cpl
,
12089 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12090 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12091 .decache_cr3
= vmx_decache_cr3
,
12092 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12093 .set_cr0
= vmx_set_cr0
,
12094 .set_cr3
= vmx_set_cr3
,
12095 .set_cr4
= vmx_set_cr4
,
12096 .set_efer
= vmx_set_efer
,
12097 .get_idt
= vmx_get_idt
,
12098 .set_idt
= vmx_set_idt
,
12099 .get_gdt
= vmx_get_gdt
,
12100 .set_gdt
= vmx_set_gdt
,
12101 .get_dr6
= vmx_get_dr6
,
12102 .set_dr6
= vmx_set_dr6
,
12103 .set_dr7
= vmx_set_dr7
,
12104 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12105 .cache_reg
= vmx_cache_reg
,
12106 .get_rflags
= vmx_get_rflags
,
12107 .set_rflags
= vmx_set_rflags
,
12109 .tlb_flush
= vmx_flush_tlb
,
12111 .run
= vmx_vcpu_run
,
12112 .handle_exit
= vmx_handle_exit
,
12113 .skip_emulated_instruction
= skip_emulated_instruction
,
12114 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12115 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12116 .patch_hypercall
= vmx_patch_hypercall
,
12117 .set_irq
= vmx_inject_irq
,
12118 .set_nmi
= vmx_inject_nmi
,
12119 .queue_exception
= vmx_queue_exception
,
12120 .cancel_injection
= vmx_cancel_injection
,
12121 .interrupt_allowed
= vmx_interrupt_allowed
,
12122 .nmi_allowed
= vmx_nmi_allowed
,
12123 .get_nmi_mask
= vmx_get_nmi_mask
,
12124 .set_nmi_mask
= vmx_set_nmi_mask
,
12125 .enable_nmi_window
= enable_nmi_window
,
12126 .enable_irq_window
= enable_irq_window
,
12127 .update_cr8_intercept
= update_cr8_intercept
,
12128 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12129 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12130 .get_enable_apicv
= vmx_get_enable_apicv
,
12131 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12132 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12133 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12134 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12135 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12136 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12137 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12139 .set_tss_addr
= vmx_set_tss_addr
,
12140 .get_tdp_level
= get_ept_level
,
12141 .get_mt_mask
= vmx_get_mt_mask
,
12143 .get_exit_info
= vmx_get_exit_info
,
12145 .get_lpage_level
= vmx_get_lpage_level
,
12147 .cpuid_update
= vmx_cpuid_update
,
12149 .rdtscp_supported
= vmx_rdtscp_supported
,
12150 .invpcid_supported
= vmx_invpcid_supported
,
12152 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12154 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12156 .write_tsc_offset
= vmx_write_tsc_offset
,
12158 .set_tdp_cr3
= vmx_set_cr3
,
12160 .check_intercept
= vmx_check_intercept
,
12161 .handle_external_intr
= vmx_handle_external_intr
,
12162 .mpx_supported
= vmx_mpx_supported
,
12163 .xsaves_supported
= vmx_xsaves_supported
,
12165 .check_nested_events
= vmx_check_nested_events
,
12167 .sched_in
= vmx_sched_in
,
12169 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12170 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12171 .flush_log_dirty
= vmx_flush_log_dirty
,
12172 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12173 .write_log_dirty
= vmx_write_pml_buffer
,
12175 .pre_block
= vmx_pre_block
,
12176 .post_block
= vmx_post_block
,
12178 .pmu_ops
= &intel_pmu_ops
,
12180 .update_pi_irte
= vmx_update_pi_irte
,
12182 #ifdef CONFIG_X86_64
12183 .set_hv_timer
= vmx_set_hv_timer
,
12184 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12187 .setup_mce
= vmx_setup_mce
,
12189 .smi_allowed
= vmx_smi_allowed
,
12190 .pre_enter_smm
= vmx_pre_enter_smm
,
12191 .pre_leave_smm
= vmx_pre_leave_smm
,
12192 .enable_smi_window
= enable_smi_window
,
12195 static int __init
vmx_init(void)
12197 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12198 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12202 #ifdef CONFIG_KEXEC_CORE
12203 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12204 crash_vmclear_local_loaded_vmcss
);
12210 static void __exit
vmx_exit(void)
12212 #ifdef CONFIG_KEXEC_CORE
12213 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12220 module_init(vmx_init
)
12221 module_exit(vmx_exit
)