2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
40 #include <asm/virtext.h>
44 #include <asm/perf_event.h>
45 #include <asm/kexec.h>
49 #define __ex(x) __kvm_handle_fault_on_reboot(x)
50 #define __ex_clear(x, reg) \
51 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
53 MODULE_AUTHOR("Qumranet");
54 MODULE_LICENSE("GPL");
56 static const struct x86_cpu_id vmx_cpu_id
[] = {
57 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
60 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
62 static bool __read_mostly enable_vpid
= 1;
63 module_param_named(vpid
, enable_vpid
, bool, 0444);
65 static bool __read_mostly flexpriority_enabled
= 1;
66 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
68 static bool __read_mostly enable_ept
= 1;
69 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
71 static bool __read_mostly enable_unrestricted_guest
= 1;
72 module_param_named(unrestricted_guest
,
73 enable_unrestricted_guest
, bool, S_IRUGO
);
75 static bool __read_mostly enable_ept_ad_bits
= 1;
76 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
78 static bool __read_mostly emulate_invalid_guest_state
= true;
79 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
81 static bool __read_mostly vmm_exclusive
= 1;
82 module_param(vmm_exclusive
, bool, S_IRUGO
);
84 static bool __read_mostly fasteoi
= 1;
85 module_param(fasteoi
, bool, S_IRUGO
);
87 static bool __read_mostly enable_apicv
= 1;
88 module_param(enable_apicv
, bool, S_IRUGO
);
90 static bool __read_mostly enable_shadow_vmcs
= 1;
91 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
93 * If nested=1, nested virtualization is supported, i.e., guests may use
94 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
95 * use VMX instructions.
97 static bool __read_mostly nested
= 0;
98 module_param(nested
, bool, S_IRUGO
);
100 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
101 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
102 #define KVM_VM_CR0_ALWAYS_ON \
103 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
104 #define KVM_CR4_GUEST_OWNED_BITS \
105 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
106 | X86_CR4_OSXMMEXCPT)
108 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
109 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
111 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
114 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
115 * ple_gap: upper bound on the amount of time between two successive
116 * executions of PAUSE in a loop. Also indicate if ple enabled.
117 * According to test, this time is usually smaller than 128 cycles.
118 * ple_window: upper bound on the amount of time a guest is allowed to execute
119 * in a PAUSE loop. Tests indicate that most spinlocks are held for
120 * less than 2^12 cycles
121 * Time is measured based on a counter that runs at the same rate as the TSC,
122 * refer SDM volume 3b section 21.6.13 & 22.1.3.
124 #define KVM_VMX_DEFAULT_PLE_GAP 128
125 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
126 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
127 module_param(ple_gap
, int, S_IRUGO
);
129 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
130 module_param(ple_window
, int, S_IRUGO
);
132 extern const ulong vmx_return
;
134 #define NR_AUTOLOAD_MSRS 8
135 #define VMCS02_POOL_SIZE 1
144 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
145 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
146 * loaded on this CPU (so we can clear them if the CPU goes down).
152 struct list_head loaded_vmcss_on_cpu_link
;
155 struct shared_msr_entry
{
162 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
163 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
164 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
165 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
166 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
167 * More than one of these structures may exist, if L1 runs multiple L2 guests.
168 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
169 * underlying hardware which will be used to run L2.
170 * This structure is packed to ensure that its layout is identical across
171 * machines (necessary for live migration).
172 * If there are changes in this struct, VMCS12_REVISION must be changed.
174 typedef u64 natural_width
;
175 struct __packed vmcs12
{
176 /* According to the Intel spec, a VMCS region must start with the
177 * following two fields. Then follow implementation-specific data.
182 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
183 u32 padding
[7]; /* room for future expansion */
188 u64 vm_exit_msr_store_addr
;
189 u64 vm_exit_msr_load_addr
;
190 u64 vm_entry_msr_load_addr
;
192 u64 virtual_apic_page_addr
;
193 u64 apic_access_addr
;
195 u64 guest_physical_address
;
196 u64 vmcs_link_pointer
;
197 u64 guest_ia32_debugctl
;
200 u64 guest_ia32_perf_global_ctrl
;
207 u64 host_ia32_perf_global_ctrl
;
208 u64 padding64
[8]; /* room for future expansion */
210 * To allow migration of L1 (complete with its L2 guests) between
211 * machines of different natural widths (32 or 64 bit), we cannot have
212 * unsigned long fields with no explict size. We use u64 (aliased
213 * natural_width) instead. Luckily, x86 is little-endian.
215 natural_width cr0_guest_host_mask
;
216 natural_width cr4_guest_host_mask
;
217 natural_width cr0_read_shadow
;
218 natural_width cr4_read_shadow
;
219 natural_width cr3_target_value0
;
220 natural_width cr3_target_value1
;
221 natural_width cr3_target_value2
;
222 natural_width cr3_target_value3
;
223 natural_width exit_qualification
;
224 natural_width guest_linear_address
;
225 natural_width guest_cr0
;
226 natural_width guest_cr3
;
227 natural_width guest_cr4
;
228 natural_width guest_es_base
;
229 natural_width guest_cs_base
;
230 natural_width guest_ss_base
;
231 natural_width guest_ds_base
;
232 natural_width guest_fs_base
;
233 natural_width guest_gs_base
;
234 natural_width guest_ldtr_base
;
235 natural_width guest_tr_base
;
236 natural_width guest_gdtr_base
;
237 natural_width guest_idtr_base
;
238 natural_width guest_dr7
;
239 natural_width guest_rsp
;
240 natural_width guest_rip
;
241 natural_width guest_rflags
;
242 natural_width guest_pending_dbg_exceptions
;
243 natural_width guest_sysenter_esp
;
244 natural_width guest_sysenter_eip
;
245 natural_width host_cr0
;
246 natural_width host_cr3
;
247 natural_width host_cr4
;
248 natural_width host_fs_base
;
249 natural_width host_gs_base
;
250 natural_width host_tr_base
;
251 natural_width host_gdtr_base
;
252 natural_width host_idtr_base
;
253 natural_width host_ia32_sysenter_esp
;
254 natural_width host_ia32_sysenter_eip
;
255 natural_width host_rsp
;
256 natural_width host_rip
;
257 natural_width paddingl
[8]; /* room for future expansion */
258 u32 pin_based_vm_exec_control
;
259 u32 cpu_based_vm_exec_control
;
260 u32 exception_bitmap
;
261 u32 page_fault_error_code_mask
;
262 u32 page_fault_error_code_match
;
263 u32 cr3_target_count
;
264 u32 vm_exit_controls
;
265 u32 vm_exit_msr_store_count
;
266 u32 vm_exit_msr_load_count
;
267 u32 vm_entry_controls
;
268 u32 vm_entry_msr_load_count
;
269 u32 vm_entry_intr_info_field
;
270 u32 vm_entry_exception_error_code
;
271 u32 vm_entry_instruction_len
;
273 u32 secondary_vm_exec_control
;
274 u32 vm_instruction_error
;
276 u32 vm_exit_intr_info
;
277 u32 vm_exit_intr_error_code
;
278 u32 idt_vectoring_info_field
;
279 u32 idt_vectoring_error_code
;
280 u32 vm_exit_instruction_len
;
281 u32 vmx_instruction_info
;
288 u32 guest_ldtr_limit
;
290 u32 guest_gdtr_limit
;
291 u32 guest_idtr_limit
;
292 u32 guest_es_ar_bytes
;
293 u32 guest_cs_ar_bytes
;
294 u32 guest_ss_ar_bytes
;
295 u32 guest_ds_ar_bytes
;
296 u32 guest_fs_ar_bytes
;
297 u32 guest_gs_ar_bytes
;
298 u32 guest_ldtr_ar_bytes
;
299 u32 guest_tr_ar_bytes
;
300 u32 guest_interruptibility_info
;
301 u32 guest_activity_state
;
302 u32 guest_sysenter_cs
;
303 u32 host_ia32_sysenter_cs
;
304 u32 vmx_preemption_timer_value
;
305 u32 padding32
[7]; /* room for future expansion */
306 u16 virtual_processor_id
;
307 u16 guest_es_selector
;
308 u16 guest_cs_selector
;
309 u16 guest_ss_selector
;
310 u16 guest_ds_selector
;
311 u16 guest_fs_selector
;
312 u16 guest_gs_selector
;
313 u16 guest_ldtr_selector
;
314 u16 guest_tr_selector
;
315 u16 host_es_selector
;
316 u16 host_cs_selector
;
317 u16 host_ss_selector
;
318 u16 host_ds_selector
;
319 u16 host_fs_selector
;
320 u16 host_gs_selector
;
321 u16 host_tr_selector
;
325 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
326 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
327 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
329 #define VMCS12_REVISION 0x11e57ed0
332 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
333 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
334 * current implementation, 4K are reserved to avoid future complications.
336 #define VMCS12_SIZE 0x1000
338 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
340 struct list_head list
;
342 struct loaded_vmcs vmcs02
;
346 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
347 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
350 /* Has the level1 guest done vmxon? */
353 /* The guest-physical address of the current VMCS L1 keeps for L2 */
355 /* The host-usable pointer to the above */
356 struct page
*current_vmcs12_page
;
357 struct vmcs12
*current_vmcs12
;
358 struct vmcs
*current_shadow_vmcs
;
360 * Indicates if the shadow vmcs must be updated with the
361 * data hold by vmcs12
363 bool sync_shadow_vmcs
;
365 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
366 struct list_head vmcs02_pool
;
368 u64 vmcs01_tsc_offset
;
369 /* L2 must run next, and mustn't decide to exit to L1. */
370 bool nested_run_pending
;
372 * Guest pages referred to in vmcs02 with host-physical pointers, so
373 * we must keep them pinned while L2 runs.
375 struct page
*apic_access_page
;
376 u64 msr_ia32_feature_control
;
379 #define POSTED_INTR_ON 0
380 /* Posted-Interrupt Descriptor */
382 u32 pir
[8]; /* Posted interrupt requested */
383 u32 control
; /* bit 0 of control is outstanding notification bit */
387 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
389 return test_and_set_bit(POSTED_INTR_ON
,
390 (unsigned long *)&pi_desc
->control
);
393 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
395 return test_and_clear_bit(POSTED_INTR_ON
,
396 (unsigned long *)&pi_desc
->control
);
399 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
401 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
405 struct kvm_vcpu vcpu
;
406 unsigned long host_rsp
;
409 bool nmi_known_unmasked
;
411 u32 idt_vectoring_info
;
413 struct shared_msr_entry
*guest_msrs
;
416 unsigned long host_idt_base
;
418 u64 msr_host_kernel_gs_base
;
419 u64 msr_guest_kernel_gs_base
;
421 u32 vm_entry_controls_shadow
;
422 u32 vm_exit_controls_shadow
;
424 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
425 * non-nested (L1) guest, it always points to vmcs01. For a nested
426 * guest (L2), it points to a different VMCS.
428 struct loaded_vmcs vmcs01
;
429 struct loaded_vmcs
*loaded_vmcs
;
430 bool __launched
; /* temporary, used in vmx_vcpu_run */
431 struct msr_autoload
{
433 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
434 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
438 u16 fs_sel
, gs_sel
, ldt_sel
;
442 int gs_ldt_reload_needed
;
443 int fs_reload_needed
;
448 struct kvm_segment segs
[8];
451 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
452 struct kvm_save_segment
{
460 bool emulation_required
;
462 /* Support for vnmi-less CPUs */
463 int soft_vnmi_blocked
;
465 s64 vnmi_blocked_time
;
470 /* Posted interrupt descriptor */
471 struct pi_desc pi_desc
;
473 /* Support for a guest hypervisor (nested VMX) */
474 struct nested_vmx nested
;
477 enum segment_cache_field
{
486 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
488 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
491 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
492 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
493 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
494 [number##_HIGH] = VMCS12_OFFSET(name)+4
497 static const unsigned long shadow_read_only_fields
[] = {
499 * We do NOT shadow fields that are modified when L0
500 * traps and emulates any vmx instruction (e.g. VMPTRLD,
501 * VMXON...) executed by L1.
502 * For example, VM_INSTRUCTION_ERROR is read
503 * by L1 if a vmx instruction fails (part of the error path).
504 * Note the code assumes this logic. If for some reason
505 * we start shadowing these fields then we need to
506 * force a shadow sync when L0 emulates vmx instructions
507 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
508 * by nested_vmx_failValid)
512 VM_EXIT_INSTRUCTION_LEN
,
513 IDT_VECTORING_INFO_FIELD
,
514 IDT_VECTORING_ERROR_CODE
,
515 VM_EXIT_INTR_ERROR_CODE
,
517 GUEST_LINEAR_ADDRESS
,
518 GUEST_PHYSICAL_ADDRESS
520 static const int max_shadow_read_only_fields
=
521 ARRAY_SIZE(shadow_read_only_fields
);
523 static const unsigned long shadow_read_write_fields
[] = {
529 GUEST_INTERRUPTIBILITY_INFO
,
541 CPU_BASED_VM_EXEC_CONTROL
,
542 VM_ENTRY_EXCEPTION_ERROR_CODE
,
543 VM_ENTRY_INTR_INFO_FIELD
,
544 VM_ENTRY_INSTRUCTION_LEN
,
545 VM_ENTRY_EXCEPTION_ERROR_CODE
,
551 static const int max_shadow_read_write_fields
=
552 ARRAY_SIZE(shadow_read_write_fields
);
554 static const unsigned short vmcs_field_to_offset_table
[] = {
555 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
556 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
557 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
558 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
559 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
560 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
561 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
562 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
563 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
564 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
565 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
566 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
567 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
568 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
569 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
570 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
571 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
572 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
573 FIELD64(MSR_BITMAP
, msr_bitmap
),
574 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
575 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
576 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
577 FIELD64(TSC_OFFSET
, tsc_offset
),
578 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
579 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
580 FIELD64(EPT_POINTER
, ept_pointer
),
581 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
582 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
583 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
584 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
585 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
586 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
587 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
588 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
589 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
590 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
591 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
592 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
593 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
594 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
595 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
596 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
597 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
598 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
599 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
600 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
601 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
602 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
603 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
604 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
605 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
606 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
607 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
608 FIELD(TPR_THRESHOLD
, tpr_threshold
),
609 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
610 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
611 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
612 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
613 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
614 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
615 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
616 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
617 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
618 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
619 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
620 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
621 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
622 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
623 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
624 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
625 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
626 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
627 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
628 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
629 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
630 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
631 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
632 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
633 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
634 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
635 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
636 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
637 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
638 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
639 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
640 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
641 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
642 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
643 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
644 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
645 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
646 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
647 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
648 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
649 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
650 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
651 FIELD(GUEST_CR0
, guest_cr0
),
652 FIELD(GUEST_CR3
, guest_cr3
),
653 FIELD(GUEST_CR4
, guest_cr4
),
654 FIELD(GUEST_ES_BASE
, guest_es_base
),
655 FIELD(GUEST_CS_BASE
, guest_cs_base
),
656 FIELD(GUEST_SS_BASE
, guest_ss_base
),
657 FIELD(GUEST_DS_BASE
, guest_ds_base
),
658 FIELD(GUEST_FS_BASE
, guest_fs_base
),
659 FIELD(GUEST_GS_BASE
, guest_gs_base
),
660 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
661 FIELD(GUEST_TR_BASE
, guest_tr_base
),
662 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
663 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
664 FIELD(GUEST_DR7
, guest_dr7
),
665 FIELD(GUEST_RSP
, guest_rsp
),
666 FIELD(GUEST_RIP
, guest_rip
),
667 FIELD(GUEST_RFLAGS
, guest_rflags
),
668 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
669 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
670 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
671 FIELD(HOST_CR0
, host_cr0
),
672 FIELD(HOST_CR3
, host_cr3
),
673 FIELD(HOST_CR4
, host_cr4
),
674 FIELD(HOST_FS_BASE
, host_fs_base
),
675 FIELD(HOST_GS_BASE
, host_gs_base
),
676 FIELD(HOST_TR_BASE
, host_tr_base
),
677 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
678 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
679 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
680 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
681 FIELD(HOST_RSP
, host_rsp
),
682 FIELD(HOST_RIP
, host_rip
),
684 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
686 static inline short vmcs_field_to_offset(unsigned long field
)
688 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
690 return vmcs_field_to_offset_table
[field
];
693 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
695 return to_vmx(vcpu
)->nested
.current_vmcs12
;
698 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
700 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
701 if (is_error_page(page
))
707 static void nested_release_page(struct page
*page
)
709 kvm_release_page_dirty(page
);
712 static void nested_release_page_clean(struct page
*page
)
714 kvm_release_page_clean(page
);
717 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
718 static u64
construct_eptp(unsigned long root_hpa
);
719 static void kvm_cpu_vmxon(u64 addr
);
720 static void kvm_cpu_vmxoff(void);
721 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
722 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
723 struct kvm_segment
*var
, int seg
);
724 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
725 struct kvm_segment
*var
, int seg
);
726 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
727 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
728 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
729 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
730 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
732 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
733 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
735 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
736 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
738 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
739 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
741 static unsigned long *vmx_io_bitmap_a
;
742 static unsigned long *vmx_io_bitmap_b
;
743 static unsigned long *vmx_msr_bitmap_legacy
;
744 static unsigned long *vmx_msr_bitmap_longmode
;
745 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
746 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
747 static unsigned long *vmx_vmread_bitmap
;
748 static unsigned long *vmx_vmwrite_bitmap
;
750 static bool cpu_has_load_ia32_efer
;
751 static bool cpu_has_load_perf_global_ctrl
;
753 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
754 static DEFINE_SPINLOCK(vmx_vpid_lock
);
756 static struct vmcs_config
{
760 u32 pin_based_exec_ctrl
;
761 u32 cpu_based_exec_ctrl
;
762 u32 cpu_based_2nd_exec_ctrl
;
767 static struct vmx_capability
{
772 #define VMX_SEGMENT_FIELD(seg) \
773 [VCPU_SREG_##seg] = { \
774 .selector = GUEST_##seg##_SELECTOR, \
775 .base = GUEST_##seg##_BASE, \
776 .limit = GUEST_##seg##_LIMIT, \
777 .ar_bytes = GUEST_##seg##_AR_BYTES, \
780 static const struct kvm_vmx_segment_field
{
785 } kvm_vmx_segment_fields
[] = {
786 VMX_SEGMENT_FIELD(CS
),
787 VMX_SEGMENT_FIELD(DS
),
788 VMX_SEGMENT_FIELD(ES
),
789 VMX_SEGMENT_FIELD(FS
),
790 VMX_SEGMENT_FIELD(GS
),
791 VMX_SEGMENT_FIELD(SS
),
792 VMX_SEGMENT_FIELD(TR
),
793 VMX_SEGMENT_FIELD(LDTR
),
796 static u64 host_efer
;
798 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
801 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
802 * away by decrementing the array size.
804 static const u32 vmx_msr_index
[] = {
806 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
808 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
810 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
812 static inline bool is_page_fault(u32 intr_info
)
814 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
815 INTR_INFO_VALID_MASK
)) ==
816 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
819 static inline bool is_no_device(u32 intr_info
)
821 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
822 INTR_INFO_VALID_MASK
)) ==
823 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
826 static inline bool is_invalid_opcode(u32 intr_info
)
828 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
829 INTR_INFO_VALID_MASK
)) ==
830 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
833 static inline bool is_external_interrupt(u32 intr_info
)
835 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
836 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
839 static inline bool is_machine_check(u32 intr_info
)
841 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
842 INTR_INFO_VALID_MASK
)) ==
843 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
846 static inline bool cpu_has_vmx_msr_bitmap(void)
848 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
851 static inline bool cpu_has_vmx_tpr_shadow(void)
853 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
856 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
858 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
861 static inline bool cpu_has_secondary_exec_ctrls(void)
863 return vmcs_config
.cpu_based_exec_ctrl
&
864 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
867 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
869 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
870 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
873 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
875 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
876 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
879 static inline bool cpu_has_vmx_apic_register_virt(void)
881 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
882 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
885 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
887 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
888 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
891 static inline bool cpu_has_vmx_posted_intr(void)
893 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
896 static inline bool cpu_has_vmx_apicv(void)
898 return cpu_has_vmx_apic_register_virt() &&
899 cpu_has_vmx_virtual_intr_delivery() &&
900 cpu_has_vmx_posted_intr();
903 static inline bool cpu_has_vmx_flexpriority(void)
905 return cpu_has_vmx_tpr_shadow() &&
906 cpu_has_vmx_virtualize_apic_accesses();
909 static inline bool cpu_has_vmx_ept_execute_only(void)
911 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
914 static inline bool cpu_has_vmx_eptp_uncacheable(void)
916 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
919 static inline bool cpu_has_vmx_eptp_writeback(void)
921 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
924 static inline bool cpu_has_vmx_ept_2m_page(void)
926 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
929 static inline bool cpu_has_vmx_ept_1g_page(void)
931 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
934 static inline bool cpu_has_vmx_ept_4levels(void)
936 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
939 static inline bool cpu_has_vmx_ept_ad_bits(void)
941 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
944 static inline bool cpu_has_vmx_invept_context(void)
946 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
949 static inline bool cpu_has_vmx_invept_global(void)
951 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
954 static inline bool cpu_has_vmx_invvpid_single(void)
956 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
959 static inline bool cpu_has_vmx_invvpid_global(void)
961 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
964 static inline bool cpu_has_vmx_ept(void)
966 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
967 SECONDARY_EXEC_ENABLE_EPT
;
970 static inline bool cpu_has_vmx_unrestricted_guest(void)
972 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
973 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
976 static inline bool cpu_has_vmx_ple(void)
978 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
979 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
982 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
984 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
987 static inline bool cpu_has_vmx_vpid(void)
989 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
990 SECONDARY_EXEC_ENABLE_VPID
;
993 static inline bool cpu_has_vmx_rdtscp(void)
995 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
996 SECONDARY_EXEC_RDTSCP
;
999 static inline bool cpu_has_vmx_invpcid(void)
1001 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1002 SECONDARY_EXEC_ENABLE_INVPCID
;
1005 static inline bool cpu_has_virtual_nmis(void)
1007 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1010 static inline bool cpu_has_vmx_wbinvd_exit(void)
1012 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1013 SECONDARY_EXEC_WBINVD_EXITING
;
1016 static inline bool cpu_has_vmx_shadow_vmcs(void)
1019 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1020 /* check if the cpu supports writing r/o exit information fields */
1021 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1024 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1025 SECONDARY_EXEC_SHADOW_VMCS
;
1028 static inline bool report_flexpriority(void)
1030 return flexpriority_enabled
;
1033 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1035 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1038 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1040 return (vmcs12
->cpu_based_vm_exec_control
&
1041 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1042 (vmcs12
->secondary_vm_exec_control
& bit
);
1045 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1047 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1050 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1052 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1055 static inline bool is_exception(u32 intr_info
)
1057 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1058 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1061 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
1062 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1063 struct vmcs12
*vmcs12
,
1064 u32 reason
, unsigned long qualification
);
1066 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1070 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1071 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1076 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1082 } operand
= { vpid
, 0, gva
};
1084 asm volatile (__ex(ASM_VMX_INVVPID
)
1085 /* CF==1 or ZF==1 --> rc = -1 */
1086 "; ja 1f ; ud2 ; 1:"
1087 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1090 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1094 } operand
= {eptp
, gpa
};
1096 asm volatile (__ex(ASM_VMX_INVEPT
)
1097 /* CF==1 or ZF==1 --> rc = -1 */
1098 "; ja 1f ; ud2 ; 1:\n"
1099 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1102 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1106 i
= __find_msr_index(vmx
, msr
);
1108 return &vmx
->guest_msrs
[i
];
1112 static void vmcs_clear(struct vmcs
*vmcs
)
1114 u64 phys_addr
= __pa(vmcs
);
1117 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1118 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1121 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1125 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1127 vmcs_clear(loaded_vmcs
->vmcs
);
1128 loaded_vmcs
->cpu
= -1;
1129 loaded_vmcs
->launched
= 0;
1132 static void vmcs_load(struct vmcs
*vmcs
)
1134 u64 phys_addr
= __pa(vmcs
);
1137 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1138 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1141 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1147 * This bitmap is used to indicate whether the vmclear
1148 * operation is enabled on all cpus. All disabled by
1151 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1153 static inline void crash_enable_local_vmclear(int cpu
)
1155 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1158 static inline void crash_disable_local_vmclear(int cpu
)
1160 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1163 static inline int crash_local_vmclear_enabled(int cpu
)
1165 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1168 static void crash_vmclear_local_loaded_vmcss(void)
1170 int cpu
= raw_smp_processor_id();
1171 struct loaded_vmcs
*v
;
1173 if (!crash_local_vmclear_enabled(cpu
))
1176 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1177 loaded_vmcss_on_cpu_link
)
1178 vmcs_clear(v
->vmcs
);
1181 static inline void crash_enable_local_vmclear(int cpu
) { }
1182 static inline void crash_disable_local_vmclear(int cpu
) { }
1183 #endif /* CONFIG_KEXEC */
1185 static void __loaded_vmcs_clear(void *arg
)
1187 struct loaded_vmcs
*loaded_vmcs
= arg
;
1188 int cpu
= raw_smp_processor_id();
1190 if (loaded_vmcs
->cpu
!= cpu
)
1191 return; /* vcpu migration can race with cpu offline */
1192 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1193 per_cpu(current_vmcs
, cpu
) = NULL
;
1194 crash_disable_local_vmclear(cpu
);
1195 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1198 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1199 * is before setting loaded_vmcs->vcpu to -1 which is done in
1200 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1201 * then adds the vmcs into percpu list before it is deleted.
1205 loaded_vmcs_init(loaded_vmcs
);
1206 crash_enable_local_vmclear(cpu
);
1209 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1211 int cpu
= loaded_vmcs
->cpu
;
1214 smp_call_function_single(cpu
,
1215 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1218 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1223 if (cpu_has_vmx_invvpid_single())
1224 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1227 static inline void vpid_sync_vcpu_global(void)
1229 if (cpu_has_vmx_invvpid_global())
1230 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1233 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1235 if (cpu_has_vmx_invvpid_single())
1236 vpid_sync_vcpu_single(vmx
);
1238 vpid_sync_vcpu_global();
1241 static inline void ept_sync_global(void)
1243 if (cpu_has_vmx_invept_global())
1244 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1247 static inline void ept_sync_context(u64 eptp
)
1250 if (cpu_has_vmx_invept_context())
1251 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1257 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1259 unsigned long value
;
1261 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1262 : "=a"(value
) : "d"(field
) : "cc");
1266 static __always_inline u16
vmcs_read16(unsigned long field
)
1268 return vmcs_readl(field
);
1271 static __always_inline u32
vmcs_read32(unsigned long field
)
1273 return vmcs_readl(field
);
1276 static __always_inline u64
vmcs_read64(unsigned long field
)
1278 #ifdef CONFIG_X86_64
1279 return vmcs_readl(field
);
1281 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1285 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1287 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1288 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1292 static void vmcs_writel(unsigned long field
, unsigned long value
)
1296 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1297 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1298 if (unlikely(error
))
1299 vmwrite_error(field
, value
);
1302 static void vmcs_write16(unsigned long field
, u16 value
)
1304 vmcs_writel(field
, value
);
1307 static void vmcs_write32(unsigned long field
, u32 value
)
1309 vmcs_writel(field
, value
);
1312 static void vmcs_write64(unsigned long field
, u64 value
)
1314 vmcs_writel(field
, value
);
1315 #ifndef CONFIG_X86_64
1317 vmcs_writel(field
+1, value
>> 32);
1321 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1323 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1326 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1328 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1331 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1333 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1334 vmx
->vm_entry_controls_shadow
= val
;
1337 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1339 if (vmx
->vm_entry_controls_shadow
!= val
)
1340 vm_entry_controls_init(vmx
, val
);
1343 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1345 return vmx
->vm_entry_controls_shadow
;
1349 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1351 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1354 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1356 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1359 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1361 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1362 vmx
->vm_exit_controls_shadow
= val
;
1365 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1367 if (vmx
->vm_exit_controls_shadow
!= val
)
1368 vm_exit_controls_init(vmx
, val
);
1371 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1373 return vmx
->vm_exit_controls_shadow
;
1377 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1379 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1382 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1384 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1387 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1389 vmx
->segment_cache
.bitmask
= 0;
1392 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1396 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1398 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1399 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1400 vmx
->segment_cache
.bitmask
= 0;
1402 ret
= vmx
->segment_cache
.bitmask
& mask
;
1403 vmx
->segment_cache
.bitmask
|= mask
;
1407 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1409 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1411 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1412 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1416 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1418 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1420 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1421 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1425 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1427 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1429 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1430 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1434 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1436 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1438 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1439 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1443 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1447 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1448 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1449 if ((vcpu
->guest_debug
&
1450 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1451 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1452 eb
|= 1u << BP_VECTOR
;
1453 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1456 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1457 if (vcpu
->fpu_active
)
1458 eb
&= ~(1u << NM_VECTOR
);
1460 /* When we are running a nested L2 guest and L1 specified for it a
1461 * certain exception bitmap, we must trap the same exceptions and pass
1462 * them to L1. When running L2, we will only handle the exceptions
1463 * specified above if L1 did not want them.
1465 if (is_guest_mode(vcpu
))
1466 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1468 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1471 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1472 unsigned long entry
, unsigned long exit
)
1474 vm_entry_controls_clearbit(vmx
, entry
);
1475 vm_exit_controls_clearbit(vmx
, exit
);
1478 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1481 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1485 if (cpu_has_load_ia32_efer
) {
1486 clear_atomic_switch_msr_special(vmx
,
1487 VM_ENTRY_LOAD_IA32_EFER
,
1488 VM_EXIT_LOAD_IA32_EFER
);
1492 case MSR_CORE_PERF_GLOBAL_CTRL
:
1493 if (cpu_has_load_perf_global_ctrl
) {
1494 clear_atomic_switch_msr_special(vmx
,
1495 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1496 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1502 for (i
= 0; i
< m
->nr
; ++i
)
1503 if (m
->guest
[i
].index
== msr
)
1509 m
->guest
[i
] = m
->guest
[m
->nr
];
1510 m
->host
[i
] = m
->host
[m
->nr
];
1511 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1512 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1515 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1516 unsigned long entry
, unsigned long exit
,
1517 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1518 u64 guest_val
, u64 host_val
)
1520 vmcs_write64(guest_val_vmcs
, guest_val
);
1521 vmcs_write64(host_val_vmcs
, host_val
);
1522 vm_entry_controls_setbit(vmx
, entry
);
1523 vm_exit_controls_setbit(vmx
, exit
);
1526 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1527 u64 guest_val
, u64 host_val
)
1530 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1534 if (cpu_has_load_ia32_efer
) {
1535 add_atomic_switch_msr_special(vmx
,
1536 VM_ENTRY_LOAD_IA32_EFER
,
1537 VM_EXIT_LOAD_IA32_EFER
,
1540 guest_val
, host_val
);
1544 case MSR_CORE_PERF_GLOBAL_CTRL
:
1545 if (cpu_has_load_perf_global_ctrl
) {
1546 add_atomic_switch_msr_special(vmx
,
1547 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1548 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1549 GUEST_IA32_PERF_GLOBAL_CTRL
,
1550 HOST_IA32_PERF_GLOBAL_CTRL
,
1551 guest_val
, host_val
);
1557 for (i
= 0; i
< m
->nr
; ++i
)
1558 if (m
->guest
[i
].index
== msr
)
1561 if (i
== NR_AUTOLOAD_MSRS
) {
1562 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1563 "Can't add msr %x\n", msr
);
1565 } else if (i
== m
->nr
) {
1567 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1568 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1571 m
->guest
[i
].index
= msr
;
1572 m
->guest
[i
].value
= guest_val
;
1573 m
->host
[i
].index
= msr
;
1574 m
->host
[i
].value
= host_val
;
1577 static void reload_tss(void)
1580 * VT restores TR but not its size. Useless.
1582 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1583 struct desc_struct
*descs
;
1585 descs
= (void *)gdt
->address
;
1586 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1590 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1595 guest_efer
= vmx
->vcpu
.arch
.efer
;
1598 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1601 ignore_bits
= EFER_NX
| EFER_SCE
;
1602 #ifdef CONFIG_X86_64
1603 ignore_bits
|= EFER_LMA
| EFER_LME
;
1604 /* SCE is meaningful only in long mode on Intel */
1605 if (guest_efer
& EFER_LMA
)
1606 ignore_bits
&= ~(u64
)EFER_SCE
;
1608 guest_efer
&= ~ignore_bits
;
1609 guest_efer
|= host_efer
& ignore_bits
;
1610 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1611 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1613 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1614 /* On ept, can't emulate nx, and must switch nx atomically */
1615 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1616 guest_efer
= vmx
->vcpu
.arch
.efer
;
1617 if (!(guest_efer
& EFER_LMA
))
1618 guest_efer
&= ~EFER_LME
;
1619 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1626 static unsigned long segment_base(u16 selector
)
1628 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1629 struct desc_struct
*d
;
1630 unsigned long table_base
;
1633 if (!(selector
& ~3))
1636 table_base
= gdt
->address
;
1638 if (selector
& 4) { /* from ldt */
1639 u16 ldt_selector
= kvm_read_ldt();
1641 if (!(ldt_selector
& ~3))
1644 table_base
= segment_base(ldt_selector
);
1646 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1647 v
= get_desc_base(d
);
1648 #ifdef CONFIG_X86_64
1649 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1650 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1655 static inline unsigned long kvm_read_tr_base(void)
1658 asm("str %0" : "=g"(tr
));
1659 return segment_base(tr
);
1662 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1664 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1667 if (vmx
->host_state
.loaded
)
1670 vmx
->host_state
.loaded
= 1;
1672 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1673 * allow segment selectors with cpl > 0 or ti == 1.
1675 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1676 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1677 savesegment(fs
, vmx
->host_state
.fs_sel
);
1678 if (!(vmx
->host_state
.fs_sel
& 7)) {
1679 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1680 vmx
->host_state
.fs_reload_needed
= 0;
1682 vmcs_write16(HOST_FS_SELECTOR
, 0);
1683 vmx
->host_state
.fs_reload_needed
= 1;
1685 savesegment(gs
, vmx
->host_state
.gs_sel
);
1686 if (!(vmx
->host_state
.gs_sel
& 7))
1687 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1689 vmcs_write16(HOST_GS_SELECTOR
, 0);
1690 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1693 #ifdef CONFIG_X86_64
1694 savesegment(ds
, vmx
->host_state
.ds_sel
);
1695 savesegment(es
, vmx
->host_state
.es_sel
);
1698 #ifdef CONFIG_X86_64
1699 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1700 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1702 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1703 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1706 #ifdef CONFIG_X86_64
1707 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1708 if (is_long_mode(&vmx
->vcpu
))
1709 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1711 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1712 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1713 vmx
->guest_msrs
[i
].data
,
1714 vmx
->guest_msrs
[i
].mask
);
1717 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1719 if (!vmx
->host_state
.loaded
)
1722 ++vmx
->vcpu
.stat
.host_state_reload
;
1723 vmx
->host_state
.loaded
= 0;
1724 #ifdef CONFIG_X86_64
1725 if (is_long_mode(&vmx
->vcpu
))
1726 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1728 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1729 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1730 #ifdef CONFIG_X86_64
1731 load_gs_index(vmx
->host_state
.gs_sel
);
1733 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1736 if (vmx
->host_state
.fs_reload_needed
)
1737 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1738 #ifdef CONFIG_X86_64
1739 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1740 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1741 loadsegment(es
, vmx
->host_state
.es_sel
);
1745 #ifdef CONFIG_X86_64
1746 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1749 * If the FPU is not active (through the host task or
1750 * the guest vcpu), then restore the cr0.TS bit.
1752 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1754 load_gdt(&__get_cpu_var(host_gdt
));
1757 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1760 __vmx_load_host_state(vmx
);
1765 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1766 * vcpu mutex is already taken.
1768 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1770 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1771 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1774 kvm_cpu_vmxon(phys_addr
);
1775 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1776 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1778 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1779 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1780 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1783 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1784 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1785 unsigned long sysenter_esp
;
1787 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1788 local_irq_disable();
1789 crash_disable_local_vmclear(cpu
);
1792 * Read loaded_vmcs->cpu should be before fetching
1793 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1794 * See the comments in __loaded_vmcs_clear().
1798 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1799 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1800 crash_enable_local_vmclear(cpu
);
1804 * Linux uses per-cpu TSS and GDT, so set these when switching
1807 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1808 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1810 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1811 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1812 vmx
->loaded_vmcs
->cpu
= cpu
;
1816 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1818 __vmx_load_host_state(to_vmx(vcpu
));
1819 if (!vmm_exclusive
) {
1820 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1826 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1830 if (vcpu
->fpu_active
)
1832 vcpu
->fpu_active
= 1;
1833 cr0
= vmcs_readl(GUEST_CR0
);
1834 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1835 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1836 vmcs_writel(GUEST_CR0
, cr0
);
1837 update_exception_bitmap(vcpu
);
1838 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1839 if (is_guest_mode(vcpu
))
1840 vcpu
->arch
.cr0_guest_owned_bits
&=
1841 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1842 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1845 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1848 * Return the cr0 value that a nested guest would read. This is a combination
1849 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1850 * its hypervisor (cr0_read_shadow).
1852 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1854 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1855 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1857 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1859 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1860 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1863 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1865 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1866 * set this *before* calling this function.
1868 vmx_decache_cr0_guest_bits(vcpu
);
1869 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1870 update_exception_bitmap(vcpu
);
1871 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1872 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1873 if (is_guest_mode(vcpu
)) {
1875 * L1's specified read shadow might not contain the TS bit,
1876 * so now that we turned on shadowing of this bit, we need to
1877 * set this bit of the shadow. Like in nested_vmx_run we need
1878 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1879 * up-to-date here because we just decached cr0.TS (and we'll
1880 * only update vmcs12->guest_cr0 on nested exit).
1882 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1883 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1884 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1885 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1887 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1890 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1892 unsigned long rflags
, save_rflags
;
1894 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1895 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1896 rflags
= vmcs_readl(GUEST_RFLAGS
);
1897 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1898 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1899 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1900 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1902 to_vmx(vcpu
)->rflags
= rflags
;
1904 return to_vmx(vcpu
)->rflags
;
1907 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1909 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1910 to_vmx(vcpu
)->rflags
= rflags
;
1911 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1912 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1913 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1915 vmcs_writel(GUEST_RFLAGS
, rflags
);
1918 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1920 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1923 if (interruptibility
& GUEST_INTR_STATE_STI
)
1924 ret
|= KVM_X86_SHADOW_INT_STI
;
1925 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1926 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1931 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1933 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1934 u32 interruptibility
= interruptibility_old
;
1936 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1938 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1939 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1940 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1941 interruptibility
|= GUEST_INTR_STATE_STI
;
1943 if ((interruptibility
!= interruptibility_old
))
1944 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1947 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1951 rip
= kvm_rip_read(vcpu
);
1952 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1953 kvm_rip_write(vcpu
, rip
);
1955 /* skipping an emulated instruction also counts */
1956 vmx_set_interrupt_shadow(vcpu
, 0);
1960 * KVM wants to inject page-faults which it got to the guest. This function
1961 * checks whether in a nested guest, we need to inject them to L1 or L2.
1963 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1965 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1967 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1970 nested_vmx_vmexit(vcpu
);
1974 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1975 bool has_error_code
, u32 error_code
,
1978 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1979 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1981 if (!reinject
&& is_guest_mode(vcpu
) &&
1982 nested_vmx_check_exception(vcpu
, nr
))
1985 if (has_error_code
) {
1986 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1987 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1990 if (vmx
->rmode
.vm86_active
) {
1992 if (kvm_exception_is_soft(nr
))
1993 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1994 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1995 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1999 if (kvm_exception_is_soft(nr
)) {
2000 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2001 vmx
->vcpu
.arch
.event_exit_inst_len
);
2002 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2004 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2006 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2009 static bool vmx_rdtscp_supported(void)
2011 return cpu_has_vmx_rdtscp();
2014 static bool vmx_invpcid_supported(void)
2016 return cpu_has_vmx_invpcid() && enable_ept
;
2020 * Swap MSR entry in host/guest MSR entry array.
2022 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2024 struct shared_msr_entry tmp
;
2026 tmp
= vmx
->guest_msrs
[to
];
2027 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2028 vmx
->guest_msrs
[from
] = tmp
;
2031 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2033 unsigned long *msr_bitmap
;
2035 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2036 if (is_long_mode(vcpu
))
2037 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2039 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2041 if (is_long_mode(vcpu
))
2042 msr_bitmap
= vmx_msr_bitmap_longmode
;
2044 msr_bitmap
= vmx_msr_bitmap_legacy
;
2047 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2051 * Set up the vmcs to automatically save and restore system
2052 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2053 * mode, as fiddling with msrs is very expensive.
2055 static void setup_msrs(struct vcpu_vmx
*vmx
)
2057 int save_nmsrs
, index
;
2060 #ifdef CONFIG_X86_64
2061 if (is_long_mode(&vmx
->vcpu
)) {
2062 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2064 move_msr_up(vmx
, index
, save_nmsrs
++);
2065 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2067 move_msr_up(vmx
, index
, save_nmsrs
++);
2068 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2070 move_msr_up(vmx
, index
, save_nmsrs
++);
2071 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2072 if (index
>= 0 && vmx
->rdtscp_enabled
)
2073 move_msr_up(vmx
, index
, save_nmsrs
++);
2075 * MSR_STAR is only needed on long mode guests, and only
2076 * if efer.sce is enabled.
2078 index
= __find_msr_index(vmx
, MSR_STAR
);
2079 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2080 move_msr_up(vmx
, index
, save_nmsrs
++);
2083 index
= __find_msr_index(vmx
, MSR_EFER
);
2084 if (index
>= 0 && update_transition_efer(vmx
, index
))
2085 move_msr_up(vmx
, index
, save_nmsrs
++);
2087 vmx
->save_nmsrs
= save_nmsrs
;
2089 if (cpu_has_vmx_msr_bitmap())
2090 vmx_set_msr_bitmap(&vmx
->vcpu
);
2094 * reads and returns guest's timestamp counter "register"
2095 * guest_tsc = host_tsc + tsc_offset -- 21.3
2097 static u64
guest_read_tsc(void)
2099 u64 host_tsc
, tsc_offset
;
2102 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2103 return host_tsc
+ tsc_offset
;
2107 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2108 * counter, even if a nested guest (L2) is currently running.
2110 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2114 tsc_offset
= is_guest_mode(vcpu
) ?
2115 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2116 vmcs_read64(TSC_OFFSET
);
2117 return host_tsc
+ tsc_offset
;
2121 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2122 * software catchup for faster rates on slower CPUs.
2124 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2129 if (user_tsc_khz
> tsc_khz
) {
2130 vcpu
->arch
.tsc_catchup
= 1;
2131 vcpu
->arch
.tsc_always_catchup
= 1;
2133 WARN(1, "user requested TSC rate below hardware speed\n");
2136 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2138 return vmcs_read64(TSC_OFFSET
);
2142 * writes 'offset' into guest's timestamp counter offset register
2144 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2146 if (is_guest_mode(vcpu
)) {
2148 * We're here if L1 chose not to trap WRMSR to TSC. According
2149 * to the spec, this should set L1's TSC; The offset that L1
2150 * set for L2 remains unchanged, and still needs to be added
2151 * to the newly set TSC to get L2's TSC.
2153 struct vmcs12
*vmcs12
;
2154 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2155 /* recalculate vmcs02.TSC_OFFSET: */
2156 vmcs12
= get_vmcs12(vcpu
);
2157 vmcs_write64(TSC_OFFSET
, offset
+
2158 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2159 vmcs12
->tsc_offset
: 0));
2161 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2162 vmcs_read64(TSC_OFFSET
), offset
);
2163 vmcs_write64(TSC_OFFSET
, offset
);
2167 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2169 u64 offset
= vmcs_read64(TSC_OFFSET
);
2171 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2172 if (is_guest_mode(vcpu
)) {
2173 /* Even when running L2, the adjustment needs to apply to L1 */
2174 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2176 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2177 offset
+ adjustment
);
2180 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2182 return target_tsc
- native_read_tsc();
2185 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2187 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2188 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2192 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2193 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2194 * all guests if the "nested" module option is off, and can also be disabled
2195 * for a single guest by disabling its VMX cpuid bit.
2197 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2199 return nested
&& guest_cpuid_has_vmx(vcpu
);
2203 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2204 * returned for the various VMX controls MSRs when nested VMX is enabled.
2205 * The same values should also be used to verify that vmcs12 control fields are
2206 * valid during nested entry from L1 to L2.
2207 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2208 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2209 * bit in the high half is on if the corresponding bit in the control field
2210 * may be on. See also vmx_control_verify().
2211 * TODO: allow these variables to be modified (downgraded) by module options
2214 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2215 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2216 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2217 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2218 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2219 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2220 static u32 nested_vmx_ept_caps
;
2221 static __init
void nested_vmx_setup_ctls_msrs(void)
2224 * Note that as a general rule, the high half of the MSRs (bits in
2225 * the control fields which may be 1) should be initialized by the
2226 * intersection of the underlying hardware's MSR (i.e., features which
2227 * can be supported) and the list of features we want to expose -
2228 * because they are known to be properly supported in our code.
2229 * Also, usually, the low half of the MSRs (bits which must be 1) can
2230 * be set to 0, meaning that L1 may turn off any of these bits. The
2231 * reason is that if one of these bits is necessary, it will appear
2232 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2233 * fields of vmcs01 and vmcs02, will turn these bits off - and
2234 * nested_vmx_exit_handled() will not pass related exits to L1.
2235 * These rules have exceptions below.
2238 /* pin-based controls */
2239 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2240 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2242 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2243 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2245 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2246 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2247 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
|
2248 PIN_BASED_VMX_PREEMPTION_TIMER
;
2249 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2253 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2256 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2257 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2258 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2259 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
2260 nested_vmx_exit_ctls_high
&=
2261 #ifdef CONFIG_X86_64
2262 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2264 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
|
2265 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2266 if (!(nested_vmx_pinbased_ctls_high
& PIN_BASED_VMX_PREEMPTION_TIMER
) ||
2267 !(nested_vmx_exit_ctls_high
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)) {
2268 nested_vmx_exit_ctls_high
&= ~VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
2269 nested_vmx_pinbased_ctls_high
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
2271 nested_vmx_exit_ctls_high
|= (VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2272 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
);
2274 /* entry controls */
2275 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2276 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2277 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2278 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2279 nested_vmx_entry_ctls_high
&=
2280 #ifdef CONFIG_X86_64
2281 VM_ENTRY_IA32E_MODE
|
2283 VM_ENTRY_LOAD_IA32_PAT
;
2284 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2285 VM_ENTRY_LOAD_IA32_EFER
);
2287 /* cpu-based controls */
2288 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2289 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2290 nested_vmx_procbased_ctls_low
= 0;
2291 nested_vmx_procbased_ctls_high
&=
2292 CPU_BASED_VIRTUAL_INTR_PENDING
|
2293 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2294 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2295 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2296 CPU_BASED_CR3_STORE_EXITING
|
2297 #ifdef CONFIG_X86_64
2298 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2300 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2301 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2302 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2303 CPU_BASED_PAUSE_EXITING
|
2304 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2306 * We can allow some features even when not supported by the
2307 * hardware. For example, L1 can specify an MSR bitmap - and we
2308 * can use it to avoid exits to L1 - even when L0 runs L2
2309 * without MSR bitmaps.
2311 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2313 /* secondary cpu-based controls */
2314 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2315 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2316 nested_vmx_secondary_ctls_low
= 0;
2317 nested_vmx_secondary_ctls_high
&=
2318 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2319 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2320 SECONDARY_EXEC_WBINVD_EXITING
;
2323 /* nested EPT: emulate EPT also to L1 */
2324 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2325 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2326 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2328 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2330 * Since invept is completely emulated we support both global
2331 * and context invalidation independent of what host cpu
2334 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2335 VMX_EPT_EXTENT_CONTEXT_BIT
;
2337 nested_vmx_ept_caps
= 0;
2339 /* miscellaneous data */
2340 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2341 nested_vmx_misc_low
&= VMX_MISC_PREEMPTION_TIMER_RATE_MASK
|
2342 VMX_MISC_SAVE_EFER_LMA
;
2343 nested_vmx_misc_low
|= VMX_MISC_ACTIVITY_HLT
;
2344 nested_vmx_misc_high
= 0;
2347 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2350 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2352 return ((control
& high
) | low
) == control
;
2355 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2357 return low
| ((u64
)high
<< 32);
2361 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2362 * also let it use VMX-specific MSRs.
2363 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2364 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2365 * like all other MSRs).
2367 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2369 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
2370 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
2372 * According to the spec, processors which do not support VMX
2373 * should throw a #GP(0) when VMX capability MSRs are read.
2375 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
2379 switch (msr_index
) {
2380 case MSR_IA32_FEATURE_CONTROL
:
2381 if (nested_vmx_allowed(vcpu
)) {
2382 *pdata
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2386 case MSR_IA32_VMX_BASIC
:
2388 * This MSR reports some information about VMX support. We
2389 * should return information about the VMX we emulate for the
2390 * guest, and the VMCS structure we give it - not about the
2391 * VMX support of the underlying hardware.
2393 *pdata
= VMCS12_REVISION
|
2394 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2395 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2397 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2398 case MSR_IA32_VMX_PINBASED_CTLS
:
2399 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2400 nested_vmx_pinbased_ctls_high
);
2402 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2403 case MSR_IA32_VMX_PROCBASED_CTLS
:
2404 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2405 nested_vmx_procbased_ctls_high
);
2407 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2408 case MSR_IA32_VMX_EXIT_CTLS
:
2409 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2410 nested_vmx_exit_ctls_high
);
2412 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2413 case MSR_IA32_VMX_ENTRY_CTLS
:
2414 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2415 nested_vmx_entry_ctls_high
);
2417 case MSR_IA32_VMX_MISC
:
2418 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2419 nested_vmx_misc_high
);
2422 * These MSRs specify bits which the guest must keep fixed (on or off)
2423 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2424 * We picked the standard core2 setting.
2426 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2427 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2428 case MSR_IA32_VMX_CR0_FIXED0
:
2429 *pdata
= VMXON_CR0_ALWAYSON
;
2431 case MSR_IA32_VMX_CR0_FIXED1
:
2434 case MSR_IA32_VMX_CR4_FIXED0
:
2435 *pdata
= VMXON_CR4_ALWAYSON
;
2437 case MSR_IA32_VMX_CR4_FIXED1
:
2440 case MSR_IA32_VMX_VMCS_ENUM
:
2443 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2444 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2445 nested_vmx_secondary_ctls_high
);
2447 case MSR_IA32_VMX_EPT_VPID_CAP
:
2448 /* Currently, no nested vpid support */
2449 *pdata
= nested_vmx_ept_caps
;
2458 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2460 u32 msr_index
= msr_info
->index
;
2461 u64 data
= msr_info
->data
;
2462 bool host_initialized
= msr_info
->host_initiated
;
2464 if (!nested_vmx_allowed(vcpu
))
2467 if (msr_index
== MSR_IA32_FEATURE_CONTROL
) {
2468 if (!host_initialized
&&
2469 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
2470 & FEATURE_CONTROL_LOCKED
)
2472 to_vmx(vcpu
)->nested
.msr_ia32_feature_control
= data
;
2477 * No need to treat VMX capability MSRs specially: If we don't handle
2478 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2484 * Reads an msr value (of 'msr_index') into 'pdata'.
2485 * Returns 0 on success, non-0 otherwise.
2486 * Assumes vcpu_load() was already called.
2488 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2491 struct shared_msr_entry
*msr
;
2494 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2498 switch (msr_index
) {
2499 #ifdef CONFIG_X86_64
2501 data
= vmcs_readl(GUEST_FS_BASE
);
2504 data
= vmcs_readl(GUEST_GS_BASE
);
2506 case MSR_KERNEL_GS_BASE
:
2507 vmx_load_host_state(to_vmx(vcpu
));
2508 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2512 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2514 data
= guest_read_tsc();
2516 case MSR_IA32_SYSENTER_CS
:
2517 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2519 case MSR_IA32_SYSENTER_EIP
:
2520 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2522 case MSR_IA32_SYSENTER_ESP
:
2523 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2526 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2528 /* Otherwise falls through */
2530 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2532 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2537 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2545 * Writes msr value into into the appropriate "register".
2546 * Returns 0 on success, non-0 otherwise.
2547 * Assumes vcpu_load() was already called.
2549 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2551 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2552 struct shared_msr_entry
*msr
;
2554 u32 msr_index
= msr_info
->index
;
2555 u64 data
= msr_info
->data
;
2557 switch (msr_index
) {
2559 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2561 #ifdef CONFIG_X86_64
2563 vmx_segment_cache_clear(vmx
);
2564 vmcs_writel(GUEST_FS_BASE
, data
);
2567 vmx_segment_cache_clear(vmx
);
2568 vmcs_writel(GUEST_GS_BASE
, data
);
2570 case MSR_KERNEL_GS_BASE
:
2571 vmx_load_host_state(vmx
);
2572 vmx
->msr_guest_kernel_gs_base
= data
;
2575 case MSR_IA32_SYSENTER_CS
:
2576 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2578 case MSR_IA32_SYSENTER_EIP
:
2579 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2581 case MSR_IA32_SYSENTER_ESP
:
2582 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2585 kvm_write_tsc(vcpu
, msr_info
);
2587 case MSR_IA32_CR_PAT
:
2588 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2589 vmcs_write64(GUEST_IA32_PAT
, data
);
2590 vcpu
->arch
.pat
= data
;
2593 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2595 case MSR_IA32_TSC_ADJUST
:
2596 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2599 if (!vmx
->rdtscp_enabled
)
2601 /* Check reserved bit, higher 32 bits should be zero */
2602 if ((data
>> 32) != 0)
2604 /* Otherwise falls through */
2606 if (vmx_set_vmx_msr(vcpu
, msr_info
))
2608 msr
= find_msr_entry(vmx
, msr_index
);
2611 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2613 kvm_set_shared_msr(msr
->index
, msr
->data
,
2619 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2625 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2627 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2630 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2633 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2635 case VCPU_EXREG_PDPTR
:
2637 ept_save_pdptrs(vcpu
);
2644 static __init
int cpu_has_kvm_support(void)
2646 return cpu_has_vmx();
2649 static __init
int vmx_disabled_by_bios(void)
2653 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2654 if (msr
& FEATURE_CONTROL_LOCKED
) {
2655 /* launched w/ TXT and VMX disabled */
2656 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2659 /* launched w/o TXT and VMX only enabled w/ TXT */
2660 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2661 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2662 && !tboot_enabled()) {
2663 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2664 "activate TXT before enabling KVM\n");
2667 /* launched w/o TXT and VMX disabled */
2668 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2669 && !tboot_enabled())
2676 static void kvm_cpu_vmxon(u64 addr
)
2678 asm volatile (ASM_VMX_VMXON_RAX
2679 : : "a"(&addr
), "m"(addr
)
2683 static int hardware_enable(void *garbage
)
2685 int cpu
= raw_smp_processor_id();
2686 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2689 if (read_cr4() & X86_CR4_VMXE
)
2692 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2695 * Now we can enable the vmclear operation in kdump
2696 * since the loaded_vmcss_on_cpu list on this cpu
2697 * has been initialized.
2699 * Though the cpu is not in VMX operation now, there
2700 * is no problem to enable the vmclear operation
2701 * for the loaded_vmcss_on_cpu list is empty!
2703 crash_enable_local_vmclear(cpu
);
2705 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2707 test_bits
= FEATURE_CONTROL_LOCKED
;
2708 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2709 if (tboot_enabled())
2710 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2712 if ((old
& test_bits
) != test_bits
) {
2713 /* enable and lock */
2714 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2716 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2718 if (vmm_exclusive
) {
2719 kvm_cpu_vmxon(phys_addr
);
2723 native_store_gdt(&__get_cpu_var(host_gdt
));
2728 static void vmclear_local_loaded_vmcss(void)
2730 int cpu
= raw_smp_processor_id();
2731 struct loaded_vmcs
*v
, *n
;
2733 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2734 loaded_vmcss_on_cpu_link
)
2735 __loaded_vmcs_clear(v
);
2739 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2742 static void kvm_cpu_vmxoff(void)
2744 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2747 static void hardware_disable(void *garbage
)
2749 if (vmm_exclusive
) {
2750 vmclear_local_loaded_vmcss();
2753 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2756 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2757 u32 msr
, u32
*result
)
2759 u32 vmx_msr_low
, vmx_msr_high
;
2760 u32 ctl
= ctl_min
| ctl_opt
;
2762 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2764 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2765 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2767 /* Ensure minimum (required) set of control bits are supported. */
2775 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2777 u32 vmx_msr_low
, vmx_msr_high
;
2779 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2780 return vmx_msr_high
& ctl
;
2783 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2785 u32 vmx_msr_low
, vmx_msr_high
;
2786 u32 min
, opt
, min2
, opt2
;
2787 u32 _pin_based_exec_control
= 0;
2788 u32 _cpu_based_exec_control
= 0;
2789 u32 _cpu_based_2nd_exec_control
= 0;
2790 u32 _vmexit_control
= 0;
2791 u32 _vmentry_control
= 0;
2793 min
= CPU_BASED_HLT_EXITING
|
2794 #ifdef CONFIG_X86_64
2795 CPU_BASED_CR8_LOAD_EXITING
|
2796 CPU_BASED_CR8_STORE_EXITING
|
2798 CPU_BASED_CR3_LOAD_EXITING
|
2799 CPU_BASED_CR3_STORE_EXITING
|
2800 CPU_BASED_USE_IO_BITMAPS
|
2801 CPU_BASED_MOV_DR_EXITING
|
2802 CPU_BASED_USE_TSC_OFFSETING
|
2803 CPU_BASED_MWAIT_EXITING
|
2804 CPU_BASED_MONITOR_EXITING
|
2805 CPU_BASED_INVLPG_EXITING
|
2806 CPU_BASED_RDPMC_EXITING
;
2808 opt
= CPU_BASED_TPR_SHADOW
|
2809 CPU_BASED_USE_MSR_BITMAPS
|
2810 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2811 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2812 &_cpu_based_exec_control
) < 0)
2814 #ifdef CONFIG_X86_64
2815 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2816 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2817 ~CPU_BASED_CR8_STORE_EXITING
;
2819 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2821 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2822 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2823 SECONDARY_EXEC_WBINVD_EXITING
|
2824 SECONDARY_EXEC_ENABLE_VPID
|
2825 SECONDARY_EXEC_ENABLE_EPT
|
2826 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2827 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2828 SECONDARY_EXEC_RDTSCP
|
2829 SECONDARY_EXEC_ENABLE_INVPCID
|
2830 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2831 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2832 SECONDARY_EXEC_SHADOW_VMCS
;
2833 if (adjust_vmx_controls(min2
, opt2
,
2834 MSR_IA32_VMX_PROCBASED_CTLS2
,
2835 &_cpu_based_2nd_exec_control
) < 0)
2838 #ifndef CONFIG_X86_64
2839 if (!(_cpu_based_2nd_exec_control
&
2840 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2841 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2844 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2845 _cpu_based_2nd_exec_control
&= ~(
2846 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2847 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2848 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2850 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2851 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2853 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2854 CPU_BASED_CR3_STORE_EXITING
|
2855 CPU_BASED_INVLPG_EXITING
);
2856 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2857 vmx_capability
.ept
, vmx_capability
.vpid
);
2861 #ifdef CONFIG_X86_64
2862 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2864 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2865 VM_EXIT_ACK_INTR_ON_EXIT
;
2866 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2867 &_vmexit_control
) < 0)
2870 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2871 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2872 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2873 &_pin_based_exec_control
) < 0)
2876 if (!(_cpu_based_2nd_exec_control
&
2877 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2878 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2879 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2882 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2883 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2884 &_vmentry_control
) < 0)
2887 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2889 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2890 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2893 #ifdef CONFIG_X86_64
2894 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2895 if (vmx_msr_high
& (1u<<16))
2899 /* Require Write-Back (WB) memory type for VMCS accesses. */
2900 if (((vmx_msr_high
>> 18) & 15) != 6)
2903 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2904 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2905 vmcs_conf
->revision_id
= vmx_msr_low
;
2907 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2908 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2909 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2910 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2911 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2913 cpu_has_load_ia32_efer
=
2914 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2915 VM_ENTRY_LOAD_IA32_EFER
)
2916 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2917 VM_EXIT_LOAD_IA32_EFER
);
2919 cpu_has_load_perf_global_ctrl
=
2920 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2921 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2922 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2923 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2926 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2927 * but due to arrata below it can't be used. Workaround is to use
2928 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2930 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2935 * BC86,AAY89,BD102 (model 44)
2939 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2940 switch (boot_cpu_data
.x86_model
) {
2946 cpu_has_load_perf_global_ctrl
= false;
2947 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2948 "does not work properly. Using workaround\n");
2958 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2960 int node
= cpu_to_node(cpu
);
2964 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2967 vmcs
= page_address(pages
);
2968 memset(vmcs
, 0, vmcs_config
.size
);
2969 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2973 static struct vmcs
*alloc_vmcs(void)
2975 return alloc_vmcs_cpu(raw_smp_processor_id());
2978 static void free_vmcs(struct vmcs
*vmcs
)
2980 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2984 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2986 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2988 if (!loaded_vmcs
->vmcs
)
2990 loaded_vmcs_clear(loaded_vmcs
);
2991 free_vmcs(loaded_vmcs
->vmcs
);
2992 loaded_vmcs
->vmcs
= NULL
;
2995 static void free_kvm_area(void)
2999 for_each_possible_cpu(cpu
) {
3000 free_vmcs(per_cpu(vmxarea
, cpu
));
3001 per_cpu(vmxarea
, cpu
) = NULL
;
3005 static __init
int alloc_kvm_area(void)
3009 for_each_possible_cpu(cpu
) {
3012 vmcs
= alloc_vmcs_cpu(cpu
);
3018 per_cpu(vmxarea
, cpu
) = vmcs
;
3023 static __init
int hardware_setup(void)
3025 if (setup_vmcs_config(&vmcs_config
) < 0)
3028 if (boot_cpu_has(X86_FEATURE_NX
))
3029 kvm_enable_efer_bits(EFER_NX
);
3031 if (!cpu_has_vmx_vpid())
3033 if (!cpu_has_vmx_shadow_vmcs())
3034 enable_shadow_vmcs
= 0;
3036 if (!cpu_has_vmx_ept() ||
3037 !cpu_has_vmx_ept_4levels()) {
3039 enable_unrestricted_guest
= 0;
3040 enable_ept_ad_bits
= 0;
3043 if (!cpu_has_vmx_ept_ad_bits())
3044 enable_ept_ad_bits
= 0;
3046 if (!cpu_has_vmx_unrestricted_guest())
3047 enable_unrestricted_guest
= 0;
3049 if (!cpu_has_vmx_flexpriority())
3050 flexpriority_enabled
= 0;
3052 if (!cpu_has_vmx_tpr_shadow())
3053 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3055 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3056 kvm_disable_largepages();
3058 if (!cpu_has_vmx_ple())
3061 if (!cpu_has_vmx_apicv())
3065 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3067 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3068 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3069 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3073 nested_vmx_setup_ctls_msrs();
3075 return alloc_kvm_area();
3078 static __exit
void hardware_unsetup(void)
3083 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3085 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3088 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3089 struct kvm_segment
*save
)
3091 if (!emulate_invalid_guest_state
) {
3093 * CS and SS RPL should be equal during guest entry according
3094 * to VMX spec, but in reality it is not always so. Since vcpu
3095 * is in the middle of the transition from real mode to
3096 * protected mode it is safe to assume that RPL 0 is a good
3099 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3100 save
->selector
&= ~SELECTOR_RPL_MASK
;
3101 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3104 vmx_set_segment(vcpu
, save
, seg
);
3107 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3109 unsigned long flags
;
3110 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3113 * Update real mode segment cache. It may be not up-to-date if sement
3114 * register was written while vcpu was in a guest mode.
3116 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3117 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3118 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3119 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3120 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3121 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3123 vmx
->rmode
.vm86_active
= 0;
3125 vmx_segment_cache_clear(vmx
);
3127 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3129 flags
= vmcs_readl(GUEST_RFLAGS
);
3130 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3131 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3132 vmcs_writel(GUEST_RFLAGS
, flags
);
3134 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3135 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3137 update_exception_bitmap(vcpu
);
3139 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3140 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3141 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3142 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3143 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3144 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3146 /* CPL is always 0 when CPU enters protected mode */
3147 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3151 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3153 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3154 struct kvm_segment var
= *save
;
3157 if (seg
== VCPU_SREG_CS
)
3160 if (!emulate_invalid_guest_state
) {
3161 var
.selector
= var
.base
>> 4;
3162 var
.base
= var
.base
& 0xffff0;
3172 if (save
->base
& 0xf)
3173 printk_once(KERN_WARNING
"kvm: segment base is not "
3174 "paragraph aligned when entering "
3175 "protected mode (seg=%d)", seg
);
3178 vmcs_write16(sf
->selector
, var
.selector
);
3179 vmcs_write32(sf
->base
, var
.base
);
3180 vmcs_write32(sf
->limit
, var
.limit
);
3181 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3184 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3186 unsigned long flags
;
3187 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3189 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3190 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3191 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3192 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3193 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3194 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3195 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3197 vmx
->rmode
.vm86_active
= 1;
3200 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3201 * vcpu. Warn the user that an update is overdue.
3203 if (!vcpu
->kvm
->arch
.tss_addr
)
3204 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3205 "called before entering vcpu\n");
3207 vmx_segment_cache_clear(vmx
);
3209 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3210 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3211 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3213 flags
= vmcs_readl(GUEST_RFLAGS
);
3214 vmx
->rmode
.save_rflags
= flags
;
3216 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3218 vmcs_writel(GUEST_RFLAGS
, flags
);
3219 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3220 update_exception_bitmap(vcpu
);
3222 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3223 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3224 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3225 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3226 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3227 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3229 kvm_mmu_reset_context(vcpu
);
3232 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3234 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3235 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3241 * Force kernel_gs_base reloading before EFER changes, as control
3242 * of this msr depends on is_long_mode().
3244 vmx_load_host_state(to_vmx(vcpu
));
3245 vcpu
->arch
.efer
= efer
;
3246 if (efer
& EFER_LMA
) {
3247 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3250 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3252 msr
->data
= efer
& ~EFER_LME
;
3257 #ifdef CONFIG_X86_64
3259 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3263 vmx_segment_cache_clear(to_vmx(vcpu
));
3265 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3266 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3267 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3269 vmcs_write32(GUEST_TR_AR_BYTES
,
3270 (guest_tr_ar
& ~AR_TYPE_MASK
)
3271 | AR_TYPE_BUSY_64_TSS
);
3273 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3276 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3278 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3279 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3284 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3286 vpid_sync_context(to_vmx(vcpu
));
3288 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3290 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3294 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3296 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3298 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3299 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3302 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3304 if (enable_ept
&& is_paging(vcpu
))
3305 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3306 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3309 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3311 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3313 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3314 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3317 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3319 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3321 if (!test_bit(VCPU_EXREG_PDPTR
,
3322 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3325 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3326 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3327 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3328 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3329 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3333 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3335 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3337 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3338 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3339 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3340 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3341 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3344 __set_bit(VCPU_EXREG_PDPTR
,
3345 (unsigned long *)&vcpu
->arch
.regs_avail
);
3346 __set_bit(VCPU_EXREG_PDPTR
,
3347 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3350 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3352 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3354 struct kvm_vcpu
*vcpu
)
3356 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3357 vmx_decache_cr3(vcpu
);
3358 if (!(cr0
& X86_CR0_PG
)) {
3359 /* From paging/starting to nonpaging */
3360 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3361 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3362 (CPU_BASED_CR3_LOAD_EXITING
|
3363 CPU_BASED_CR3_STORE_EXITING
));
3364 vcpu
->arch
.cr0
= cr0
;
3365 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3366 } else if (!is_paging(vcpu
)) {
3367 /* From nonpaging to paging */
3368 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3369 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3370 ~(CPU_BASED_CR3_LOAD_EXITING
|
3371 CPU_BASED_CR3_STORE_EXITING
));
3372 vcpu
->arch
.cr0
= cr0
;
3373 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3376 if (!(cr0
& X86_CR0_WP
))
3377 *hw_cr0
&= ~X86_CR0_WP
;
3380 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3382 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3383 unsigned long hw_cr0
;
3385 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3386 if (enable_unrestricted_guest
)
3387 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3389 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3391 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3394 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3398 #ifdef CONFIG_X86_64
3399 if (vcpu
->arch
.efer
& EFER_LME
) {
3400 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3402 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3408 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3410 if (!vcpu
->fpu_active
)
3411 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3413 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3414 vmcs_writel(GUEST_CR0
, hw_cr0
);
3415 vcpu
->arch
.cr0
= cr0
;
3417 /* depends on vcpu->arch.cr0 to be set to a new value */
3418 vmx
->emulation_required
= emulation_required(vcpu
);
3421 static u64
construct_eptp(unsigned long root_hpa
)
3425 /* TODO write the value reading from MSR */
3426 eptp
= VMX_EPT_DEFAULT_MT
|
3427 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3428 if (enable_ept_ad_bits
)
3429 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3430 eptp
|= (root_hpa
& PAGE_MASK
);
3435 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3437 unsigned long guest_cr3
;
3442 eptp
= construct_eptp(cr3
);
3443 vmcs_write64(EPT_POINTER
, eptp
);
3444 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3445 guest_cr3
= kvm_read_cr3(vcpu
);
3447 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3448 ept_load_pdptrs(vcpu
);
3451 vmx_flush_tlb(vcpu
);
3452 vmcs_writel(GUEST_CR3
, guest_cr3
);
3455 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3457 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3458 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3460 if (cr4
& X86_CR4_VMXE
) {
3462 * To use VMXON (and later other VMX instructions), a guest
3463 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3464 * So basically the check on whether to allow nested VMX
3467 if (!nested_vmx_allowed(vcpu
))
3470 if (to_vmx(vcpu
)->nested
.vmxon
&&
3471 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3474 vcpu
->arch
.cr4
= cr4
;
3476 if (!is_paging(vcpu
)) {
3477 hw_cr4
&= ~X86_CR4_PAE
;
3478 hw_cr4
|= X86_CR4_PSE
;
3480 * SMEP is disabled if CPU is in non-paging mode in
3481 * hardware. However KVM always uses paging mode to
3482 * emulate guest non-paging mode with TDP.
3483 * To emulate this behavior, SMEP needs to be manually
3484 * disabled when guest switches to non-paging mode.
3486 hw_cr4
&= ~X86_CR4_SMEP
;
3487 } else if (!(cr4
& X86_CR4_PAE
)) {
3488 hw_cr4
&= ~X86_CR4_PAE
;
3492 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3493 vmcs_writel(GUEST_CR4
, hw_cr4
);
3497 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3498 struct kvm_segment
*var
, int seg
)
3500 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3503 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3504 *var
= vmx
->rmode
.segs
[seg
];
3505 if (seg
== VCPU_SREG_TR
3506 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3508 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3509 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3512 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3513 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3514 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3515 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3516 var
->unusable
= (ar
>> 16) & 1;
3517 var
->type
= ar
& 15;
3518 var
->s
= (ar
>> 4) & 1;
3519 var
->dpl
= (ar
>> 5) & 3;
3521 * Some userspaces do not preserve unusable property. Since usable
3522 * segment has to be present according to VMX spec we can use present
3523 * property to amend userspace bug by making unusable segment always
3524 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3525 * segment as unusable.
3527 var
->present
= !var
->unusable
;
3528 var
->avl
= (ar
>> 12) & 1;
3529 var
->l
= (ar
>> 13) & 1;
3530 var
->db
= (ar
>> 14) & 1;
3531 var
->g
= (ar
>> 15) & 1;
3534 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3536 struct kvm_segment s
;
3538 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3539 vmx_get_segment(vcpu
, &s
, seg
);
3542 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3545 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3547 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3549 if (!is_protmode(vcpu
))
3552 if (!is_long_mode(vcpu
)
3553 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3556 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3557 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3558 vmx
->cpl
= vmx_read_guest_seg_selector(vmx
, VCPU_SREG_CS
) & 3;
3565 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3569 if (var
->unusable
|| !var
->present
)
3572 ar
= var
->type
& 15;
3573 ar
|= (var
->s
& 1) << 4;
3574 ar
|= (var
->dpl
& 3) << 5;
3575 ar
|= (var
->present
& 1) << 7;
3576 ar
|= (var
->avl
& 1) << 12;
3577 ar
|= (var
->l
& 1) << 13;
3578 ar
|= (var
->db
& 1) << 14;
3579 ar
|= (var
->g
& 1) << 15;
3585 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3586 struct kvm_segment
*var
, int seg
)
3588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3589 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3591 vmx_segment_cache_clear(vmx
);
3592 if (seg
== VCPU_SREG_CS
)
3593 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3595 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3596 vmx
->rmode
.segs
[seg
] = *var
;
3597 if (seg
== VCPU_SREG_TR
)
3598 vmcs_write16(sf
->selector
, var
->selector
);
3600 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3604 vmcs_writel(sf
->base
, var
->base
);
3605 vmcs_write32(sf
->limit
, var
->limit
);
3606 vmcs_write16(sf
->selector
, var
->selector
);
3609 * Fix the "Accessed" bit in AR field of segment registers for older
3611 * IA32 arch specifies that at the time of processor reset the
3612 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3613 * is setting it to 0 in the userland code. This causes invalid guest
3614 * state vmexit when "unrestricted guest" mode is turned on.
3615 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3616 * tree. Newer qemu binaries with that qemu fix would not need this
3619 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3620 var
->type
|= 0x1; /* Accessed */
3622 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3625 vmx
->emulation_required
|= emulation_required(vcpu
);
3628 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3630 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3632 *db
= (ar
>> 14) & 1;
3633 *l
= (ar
>> 13) & 1;
3636 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3638 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3639 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3642 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3644 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3645 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3648 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3650 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3651 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3654 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3656 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3657 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3660 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3662 struct kvm_segment var
;
3665 vmx_get_segment(vcpu
, &var
, seg
);
3667 if (seg
== VCPU_SREG_CS
)
3669 ar
= vmx_segment_access_rights(&var
);
3671 if (var
.base
!= (var
.selector
<< 4))
3673 if (var
.limit
!= 0xffff)
3681 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3683 struct kvm_segment cs
;
3684 unsigned int cs_rpl
;
3686 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3687 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3691 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3695 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3696 if (cs
.dpl
> cs_rpl
)
3699 if (cs
.dpl
!= cs_rpl
)
3705 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3709 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3711 struct kvm_segment ss
;
3712 unsigned int ss_rpl
;
3714 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3715 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3719 if (ss
.type
!= 3 && ss
.type
!= 7)
3723 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3731 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3733 struct kvm_segment var
;
3736 vmx_get_segment(vcpu
, &var
, seg
);
3737 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3745 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3746 if (var
.dpl
< rpl
) /* DPL < RPL */
3750 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3756 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3758 struct kvm_segment tr
;
3760 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3764 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3766 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3774 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3776 struct kvm_segment ldtr
;
3778 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3782 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3792 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3794 struct kvm_segment cs
, ss
;
3796 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3797 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3799 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3800 (ss
.selector
& SELECTOR_RPL_MASK
));
3804 * Check if guest state is valid. Returns true if valid, false if
3806 * We assume that registers are always usable
3808 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3810 if (enable_unrestricted_guest
)
3813 /* real mode guest state checks */
3814 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3815 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3817 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3819 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3821 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3823 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3825 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3828 /* protected mode guest state checks */
3829 if (!cs_ss_rpl_check(vcpu
))
3831 if (!code_segment_valid(vcpu
))
3833 if (!stack_segment_valid(vcpu
))
3835 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3837 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3839 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3841 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3843 if (!tr_valid(vcpu
))
3845 if (!ldtr_valid(vcpu
))
3849 * - Add checks on RIP
3850 * - Add checks on RFLAGS
3856 static int init_rmode_tss(struct kvm
*kvm
)
3860 int r
, idx
, ret
= 0;
3862 idx
= srcu_read_lock(&kvm
->srcu
);
3863 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3864 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3867 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3868 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3869 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3872 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3875 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3879 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3880 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3887 srcu_read_unlock(&kvm
->srcu
, idx
);
3891 static int init_rmode_identity_map(struct kvm
*kvm
)
3894 pfn_t identity_map_pfn
;
3899 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3900 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3901 "haven't been allocated!\n");
3904 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3907 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3908 idx
= srcu_read_lock(&kvm
->srcu
);
3909 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3912 /* Set up identity-mapping pagetable for EPT in real mode */
3913 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3914 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3915 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3916 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3917 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3921 kvm
->arch
.ept_identity_pagetable_done
= true;
3924 srcu_read_unlock(&kvm
->srcu
, idx
);
3928 static void seg_setup(int seg
)
3930 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3933 vmcs_write16(sf
->selector
, 0);
3934 vmcs_writel(sf
->base
, 0);
3935 vmcs_write32(sf
->limit
, 0xffff);
3937 if (seg
== VCPU_SREG_CS
)
3938 ar
|= 0x08; /* code segment */
3940 vmcs_write32(sf
->ar_bytes
, ar
);
3943 static int alloc_apic_access_page(struct kvm
*kvm
)
3946 struct kvm_userspace_memory_region kvm_userspace_mem
;
3949 mutex_lock(&kvm
->slots_lock
);
3950 if (kvm
->arch
.apic_access_page
)
3952 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3953 kvm_userspace_mem
.flags
= 0;
3954 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3955 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3956 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3960 page
= gfn_to_page(kvm
, 0xfee00);
3961 if (is_error_page(page
)) {
3966 kvm
->arch
.apic_access_page
= page
;
3968 mutex_unlock(&kvm
->slots_lock
);
3972 static int alloc_identity_pagetable(struct kvm
*kvm
)
3975 struct kvm_userspace_memory_region kvm_userspace_mem
;
3978 mutex_lock(&kvm
->slots_lock
);
3979 if (kvm
->arch
.ept_identity_pagetable
)
3981 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3982 kvm_userspace_mem
.flags
= 0;
3983 kvm_userspace_mem
.guest_phys_addr
=
3984 kvm
->arch
.ept_identity_map_addr
;
3985 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3986 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3990 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3991 if (is_error_page(page
)) {
3996 kvm
->arch
.ept_identity_pagetable
= page
;
3998 mutex_unlock(&kvm
->slots_lock
);
4002 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4009 spin_lock(&vmx_vpid_lock
);
4010 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4011 if (vpid
< VMX_NR_VPIDS
) {
4013 __set_bit(vpid
, vmx_vpid_bitmap
);
4015 spin_unlock(&vmx_vpid_lock
);
4018 static void free_vpid(struct vcpu_vmx
*vmx
)
4022 spin_lock(&vmx_vpid_lock
);
4024 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4025 spin_unlock(&vmx_vpid_lock
);
4028 #define MSR_TYPE_R 1
4029 #define MSR_TYPE_W 2
4030 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4033 int f
= sizeof(unsigned long);
4035 if (!cpu_has_vmx_msr_bitmap())
4039 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4040 * have the write-low and read-high bitmap offsets the wrong way round.
4041 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4043 if (msr
<= 0x1fff) {
4044 if (type
& MSR_TYPE_R
)
4046 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4048 if (type
& MSR_TYPE_W
)
4050 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4052 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4054 if (type
& MSR_TYPE_R
)
4056 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4058 if (type
& MSR_TYPE_W
)
4060 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4065 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4068 int f
= sizeof(unsigned long);
4070 if (!cpu_has_vmx_msr_bitmap())
4074 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4075 * have the write-low and read-high bitmap offsets the wrong way round.
4076 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4078 if (msr
<= 0x1fff) {
4079 if (type
& MSR_TYPE_R
)
4081 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4083 if (type
& MSR_TYPE_W
)
4085 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4087 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4089 if (type
& MSR_TYPE_R
)
4091 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4093 if (type
& MSR_TYPE_W
)
4095 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4100 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4103 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4104 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4105 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4106 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4109 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4111 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4113 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4117 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4119 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4121 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4125 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4127 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4129 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4133 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4135 return enable_apicv
&& irqchip_in_kernel(kvm
);
4139 * Send interrupt to vcpu via posted interrupt way.
4140 * 1. If target vcpu is running(non-root mode), send posted interrupt
4141 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4142 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4143 * interrupt from PIR in next vmentry.
4145 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4147 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4150 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4153 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4154 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4156 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4157 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4158 POSTED_INTR_VECTOR
);
4161 kvm_vcpu_kick(vcpu
);
4164 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4166 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4168 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4171 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4174 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4180 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4181 * will not change in the lifetime of the guest.
4182 * Note that host-state that does change is set elsewhere. E.g., host-state
4183 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4185 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4191 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4192 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4193 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4195 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4196 #ifdef CONFIG_X86_64
4198 * Load null selectors, so we can avoid reloading them in
4199 * __vmx_load_host_state(), in case userspace uses the null selectors
4200 * too (the expected case).
4202 vmcs_write16(HOST_DS_SELECTOR
, 0);
4203 vmcs_write16(HOST_ES_SELECTOR
, 0);
4205 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4206 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4208 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4209 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4211 native_store_idt(&dt
);
4212 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4213 vmx
->host_idt_base
= dt
.address
;
4215 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4217 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4218 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4219 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4220 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4222 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4223 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4224 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4228 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4230 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4232 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4233 if (is_guest_mode(&vmx
->vcpu
))
4234 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4235 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4236 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4239 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4241 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4243 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4244 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4245 return pin_based_exec_ctrl
;
4248 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4250 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4251 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4252 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4253 #ifdef CONFIG_X86_64
4254 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4255 CPU_BASED_CR8_LOAD_EXITING
;
4259 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4260 CPU_BASED_CR3_LOAD_EXITING
|
4261 CPU_BASED_INVLPG_EXITING
;
4262 return exec_control
;
4265 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4267 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4268 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4269 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4271 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4273 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4274 enable_unrestricted_guest
= 0;
4275 /* Enable INVPCID for non-ept guests may cause performance regression. */
4276 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4278 if (!enable_unrestricted_guest
)
4279 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4281 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4282 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4283 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4284 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4285 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4286 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4288 We can NOT enable shadow_vmcs here because we don't have yet
4291 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4292 return exec_control
;
4295 static void ept_set_mmio_spte_mask(void)
4298 * EPT Misconfigurations can be generated if the value of bits 2:0
4299 * of an EPT paging-structure entry is 110b (write/execute).
4300 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4303 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4307 * Sets up the vmcs for emulated real mode.
4309 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4311 #ifdef CONFIG_X86_64
4317 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4318 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4320 if (enable_shadow_vmcs
) {
4321 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4322 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4324 if (cpu_has_vmx_msr_bitmap())
4325 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4327 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4330 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4332 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4334 if (cpu_has_secondary_exec_ctrls()) {
4335 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4336 vmx_secondary_exec_control(vmx
));
4339 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4340 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4341 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4342 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4343 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4345 vmcs_write16(GUEST_INTR_STATUS
, 0);
4347 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4348 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4352 vmcs_write32(PLE_GAP
, ple_gap
);
4353 vmcs_write32(PLE_WINDOW
, ple_window
);
4356 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4357 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4358 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4360 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4361 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4362 vmx_set_constant_host_state(vmx
);
4363 #ifdef CONFIG_X86_64
4364 rdmsrl(MSR_FS_BASE
, a
);
4365 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4366 rdmsrl(MSR_GS_BASE
, a
);
4367 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4369 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4370 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4373 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4374 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4375 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4376 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4377 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4379 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4380 u32 msr_low
, msr_high
;
4382 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4383 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4384 /* Write the default value follow host pat */
4385 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4386 /* Keep arch.pat sync with GUEST_IA32_PAT */
4387 vmx
->vcpu
.arch
.pat
= host_pat
;
4390 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4391 u32 index
= vmx_msr_index
[i
];
4392 u32 data_low
, data_high
;
4395 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4397 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4399 vmx
->guest_msrs
[j
].index
= i
;
4400 vmx
->guest_msrs
[j
].data
= 0;
4401 vmx
->guest_msrs
[j
].mask
= -1ull;
4406 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4408 /* 22.2.1, 20.8.1 */
4409 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4411 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4412 set_cr4_guest_host_mask(vmx
);
4417 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4419 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4422 vmx
->rmode
.vm86_active
= 0;
4424 vmx
->soft_vnmi_blocked
= 0;
4426 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4427 kvm_set_cr8(&vmx
->vcpu
, 0);
4428 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4429 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4430 msr
|= MSR_IA32_APICBASE_BSP
;
4431 kvm_set_apic_base(&vmx
->vcpu
, msr
);
4433 vmx_segment_cache_clear(vmx
);
4435 seg_setup(VCPU_SREG_CS
);
4436 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4437 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4439 seg_setup(VCPU_SREG_DS
);
4440 seg_setup(VCPU_SREG_ES
);
4441 seg_setup(VCPU_SREG_FS
);
4442 seg_setup(VCPU_SREG_GS
);
4443 seg_setup(VCPU_SREG_SS
);
4445 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4446 vmcs_writel(GUEST_TR_BASE
, 0);
4447 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4448 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4450 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4451 vmcs_writel(GUEST_LDTR_BASE
, 0);
4452 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4453 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4455 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4456 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4457 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4459 vmcs_writel(GUEST_RFLAGS
, 0x02);
4460 kvm_rip_write(vcpu
, 0xfff0);
4462 vmcs_writel(GUEST_GDTR_BASE
, 0);
4463 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4465 vmcs_writel(GUEST_IDTR_BASE
, 0);
4466 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4468 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4469 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4470 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4472 /* Special registers */
4473 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4477 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4479 if (cpu_has_vmx_tpr_shadow()) {
4480 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4481 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4482 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4483 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4484 vmcs_write32(TPR_THRESHOLD
, 0);
4487 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4488 vmcs_write64(APIC_ACCESS_ADDR
,
4489 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4491 if (vmx_vm_has_apicv(vcpu
->kvm
))
4492 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4495 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4497 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4498 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4499 vmx_set_cr4(&vmx
->vcpu
, 0);
4500 vmx_set_efer(&vmx
->vcpu
, 0);
4501 vmx_fpu_activate(&vmx
->vcpu
);
4502 update_exception_bitmap(&vmx
->vcpu
);
4504 vpid_sync_context(vmx
);
4508 * In nested virtualization, check if L1 asked to exit on external interrupts.
4509 * For most existing hypervisors, this will always return true.
4511 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4513 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4514 PIN_BASED_EXT_INTR_MASK
;
4517 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4519 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4520 PIN_BASED_NMI_EXITING
;
4523 static int enable_irq_window(struct kvm_vcpu
*vcpu
)
4525 u32 cpu_based_vm_exec_control
;
4527 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
4529 * We get here if vmx_interrupt_allowed() said we can't
4530 * inject to L1 now because L2 must run. The caller will have
4531 * to make L2 exit right after entry, so we can inject to L1
4536 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4537 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4538 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4542 static int enable_nmi_window(struct kvm_vcpu
*vcpu
)
4544 u32 cpu_based_vm_exec_control
;
4546 if (!cpu_has_virtual_nmis())
4547 return enable_irq_window(vcpu
);
4549 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
)
4550 return enable_irq_window(vcpu
);
4552 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4553 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4554 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4558 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4560 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4562 int irq
= vcpu
->arch
.interrupt
.nr
;
4564 trace_kvm_inj_virq(irq
);
4566 ++vcpu
->stat
.irq_injections
;
4567 if (vmx
->rmode
.vm86_active
) {
4569 if (vcpu
->arch
.interrupt
.soft
)
4570 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4571 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4572 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4575 intr
= irq
| INTR_INFO_VALID_MASK
;
4576 if (vcpu
->arch
.interrupt
.soft
) {
4577 intr
|= INTR_TYPE_SOFT_INTR
;
4578 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4579 vmx
->vcpu
.arch
.event_exit_inst_len
);
4581 intr
|= INTR_TYPE_EXT_INTR
;
4582 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4585 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4589 if (is_guest_mode(vcpu
))
4592 if (!cpu_has_virtual_nmis()) {
4594 * Tracking the NMI-blocked state in software is built upon
4595 * finding the next open IRQ window. This, in turn, depends on
4596 * well-behaving guests: They have to keep IRQs disabled at
4597 * least as long as the NMI handler runs. Otherwise we may
4598 * cause NMI nesting, maybe breaking the guest. But as this is
4599 * highly unlikely, we can live with the residual risk.
4601 vmx
->soft_vnmi_blocked
= 1;
4602 vmx
->vnmi_blocked_time
= 0;
4605 ++vcpu
->stat
.nmi_injections
;
4606 vmx
->nmi_known_unmasked
= false;
4607 if (vmx
->rmode
.vm86_active
) {
4608 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4609 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4612 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4613 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4616 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4618 if (!cpu_has_virtual_nmis())
4619 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4620 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4622 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4625 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4627 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4629 if (!cpu_has_virtual_nmis()) {
4630 if (vmx
->soft_vnmi_blocked
!= masked
) {
4631 vmx
->soft_vnmi_blocked
= masked
;
4632 vmx
->vnmi_blocked_time
= 0;
4635 vmx
->nmi_known_unmasked
= !masked
;
4637 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4638 GUEST_INTR_STATE_NMI
);
4640 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4641 GUEST_INTR_STATE_NMI
);
4645 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4647 if (is_guest_mode(vcpu
)) {
4648 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4650 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4652 if (nested_exit_on_nmi(vcpu
)) {
4653 nested_vmx_vmexit(vcpu
);
4654 vmcs12
->vm_exit_reason
= EXIT_REASON_EXCEPTION_NMI
;
4655 vmcs12
->vm_exit_intr_info
= NMI_VECTOR
|
4656 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
;
4658 * The NMI-triggered VM exit counts as injection:
4659 * clear this one and block further NMIs.
4661 vcpu
->arch
.nmi_pending
= 0;
4662 vmx_set_nmi_mask(vcpu
, true);
4667 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4670 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4671 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4672 | GUEST_INTR_STATE_NMI
));
4675 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4677 if (is_guest_mode(vcpu
)) {
4678 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4680 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4682 if (nested_exit_on_intr(vcpu
)) {
4683 nested_vmx_vmexit(vcpu
);
4684 vmcs12
->vm_exit_reason
=
4685 EXIT_REASON_EXTERNAL_INTERRUPT
;
4686 vmcs12
->vm_exit_intr_info
= 0;
4688 * fall through to normal code, but now in L1, not L2
4693 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4694 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4695 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4698 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4701 struct kvm_userspace_memory_region tss_mem
= {
4702 .slot
= TSS_PRIVATE_MEMSLOT
,
4703 .guest_phys_addr
= addr
,
4704 .memory_size
= PAGE_SIZE
* 3,
4708 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4711 kvm
->arch
.tss_addr
= addr
;
4712 if (!init_rmode_tss(kvm
))
4718 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4723 * Update instruction length as we may reinject the exception
4724 * from user space while in guest debugging mode.
4726 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4727 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4728 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4732 if (vcpu
->guest_debug
&
4733 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4750 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4751 int vec
, u32 err_code
)
4754 * Instruction with address size override prefix opcode 0x67
4755 * Cause the #SS fault with 0 error code in VM86 mode.
4757 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4758 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4759 if (vcpu
->arch
.halt_request
) {
4760 vcpu
->arch
.halt_request
= 0;
4761 return kvm_emulate_halt(vcpu
);
4769 * Forward all other exceptions that are valid in real mode.
4770 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4771 * the required debugging infrastructure rework.
4773 kvm_queue_exception(vcpu
, vec
);
4778 * Trigger machine check on the host. We assume all the MSRs are already set up
4779 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4780 * We pass a fake environment to the machine check handler because we want
4781 * the guest to be always treated like user space, no matter what context
4782 * it used internally.
4784 static void kvm_machine_check(void)
4786 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4787 struct pt_regs regs
= {
4788 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4789 .flags
= X86_EFLAGS_IF
,
4792 do_machine_check(®s
, 0);
4796 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4798 /* already handled by vcpu_run */
4802 static int handle_exception(struct kvm_vcpu
*vcpu
)
4804 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4805 struct kvm_run
*kvm_run
= vcpu
->run
;
4806 u32 intr_info
, ex_no
, error_code
;
4807 unsigned long cr2
, rip
, dr6
;
4809 enum emulation_result er
;
4811 vect_info
= vmx
->idt_vectoring_info
;
4812 intr_info
= vmx
->exit_intr_info
;
4814 if (is_machine_check(intr_info
))
4815 return handle_machine_check(vcpu
);
4817 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4818 return 1; /* already handled by vmx_vcpu_run() */
4820 if (is_no_device(intr_info
)) {
4821 vmx_fpu_activate(vcpu
);
4825 if (is_invalid_opcode(intr_info
)) {
4826 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4827 if (er
!= EMULATE_DONE
)
4828 kvm_queue_exception(vcpu
, UD_VECTOR
);
4833 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4834 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4837 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4838 * MMIO, it is better to report an internal error.
4839 * See the comments in vmx_handle_exit.
4841 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4842 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4843 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4844 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4845 vcpu
->run
->internal
.ndata
= 2;
4846 vcpu
->run
->internal
.data
[0] = vect_info
;
4847 vcpu
->run
->internal
.data
[1] = intr_info
;
4851 if (is_page_fault(intr_info
)) {
4852 /* EPT won't cause page fault directly */
4854 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4855 trace_kvm_page_fault(cr2
, error_code
);
4857 if (kvm_event_needs_reinjection(vcpu
))
4858 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4859 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4862 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4864 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4865 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4869 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4870 if (!(vcpu
->guest_debug
&
4871 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4872 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4873 kvm_queue_exception(vcpu
, DB_VECTOR
);
4876 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4877 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4881 * Update instruction length as we may reinject #BP from
4882 * user space while in guest debugging mode. Reading it for
4883 * #DB as well causes no harm, it is not used in that case.
4885 vmx
->vcpu
.arch
.event_exit_inst_len
=
4886 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4887 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4888 rip
= kvm_rip_read(vcpu
);
4889 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4890 kvm_run
->debug
.arch
.exception
= ex_no
;
4893 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4894 kvm_run
->ex
.exception
= ex_no
;
4895 kvm_run
->ex
.error_code
= error_code
;
4901 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4903 ++vcpu
->stat
.irq_exits
;
4907 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4909 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4913 static int handle_io(struct kvm_vcpu
*vcpu
)
4915 unsigned long exit_qualification
;
4916 int size
, in
, string
;
4919 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4920 string
= (exit_qualification
& 16) != 0;
4921 in
= (exit_qualification
& 8) != 0;
4923 ++vcpu
->stat
.io_exits
;
4926 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4928 port
= exit_qualification
>> 16;
4929 size
= (exit_qualification
& 7) + 1;
4930 skip_emulated_instruction(vcpu
);
4932 return kvm_fast_pio_out(vcpu
, size
, port
);
4936 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4939 * Patch in the VMCALL instruction:
4941 hypercall
[0] = 0x0f;
4942 hypercall
[1] = 0x01;
4943 hypercall
[2] = 0xc1;
4946 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4948 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4950 if (nested_vmx_secondary_ctls_high
&
4951 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4952 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4953 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4954 return (val
& always_on
) == always_on
;
4957 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4958 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4960 if (is_guest_mode(vcpu
)) {
4961 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4962 unsigned long orig_val
= val
;
4965 * We get here when L2 changed cr0 in a way that did not change
4966 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4967 * but did change L0 shadowed bits. So we first calculate the
4968 * effective cr0 value that L1 would like to write into the
4969 * hardware. It consists of the L2-owned bits from the new
4970 * value combined with the L1-owned bits from L1's guest_cr0.
4972 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4973 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4975 if (!nested_cr0_valid(vmcs12
, val
))
4978 if (kvm_set_cr0(vcpu
, val
))
4980 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4983 if (to_vmx(vcpu
)->nested
.vmxon
&&
4984 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4986 return kvm_set_cr0(vcpu
, val
);
4990 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4992 if (is_guest_mode(vcpu
)) {
4993 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4994 unsigned long orig_val
= val
;
4996 /* analogously to handle_set_cr0 */
4997 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
4998 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
4999 if (kvm_set_cr4(vcpu
, val
))
5001 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5004 return kvm_set_cr4(vcpu
, val
);
5007 /* called to set cr0 as approriate for clts instruction exit. */
5008 static void handle_clts(struct kvm_vcpu
*vcpu
)
5010 if (is_guest_mode(vcpu
)) {
5012 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5013 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5014 * just pretend it's off (also in arch.cr0 for fpu_activate).
5016 vmcs_writel(CR0_READ_SHADOW
,
5017 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5018 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5020 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5023 static int handle_cr(struct kvm_vcpu
*vcpu
)
5025 unsigned long exit_qualification
, val
;
5030 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5031 cr
= exit_qualification
& 15;
5032 reg
= (exit_qualification
>> 8) & 15;
5033 switch ((exit_qualification
>> 4) & 3) {
5034 case 0: /* mov to cr */
5035 val
= kvm_register_read(vcpu
, reg
);
5036 trace_kvm_cr_write(cr
, val
);
5039 err
= handle_set_cr0(vcpu
, val
);
5040 kvm_complete_insn_gp(vcpu
, err
);
5043 err
= kvm_set_cr3(vcpu
, val
);
5044 kvm_complete_insn_gp(vcpu
, err
);
5047 err
= handle_set_cr4(vcpu
, val
);
5048 kvm_complete_insn_gp(vcpu
, err
);
5051 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5052 u8 cr8
= kvm_register_read(vcpu
, reg
);
5053 err
= kvm_set_cr8(vcpu
, cr8
);
5054 kvm_complete_insn_gp(vcpu
, err
);
5055 if (irqchip_in_kernel(vcpu
->kvm
))
5057 if (cr8_prev
<= cr8
)
5059 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5066 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5067 skip_emulated_instruction(vcpu
);
5068 vmx_fpu_activate(vcpu
);
5070 case 1: /*mov from cr*/
5073 val
= kvm_read_cr3(vcpu
);
5074 kvm_register_write(vcpu
, reg
, val
);
5075 trace_kvm_cr_read(cr
, val
);
5076 skip_emulated_instruction(vcpu
);
5079 val
= kvm_get_cr8(vcpu
);
5080 kvm_register_write(vcpu
, reg
, val
);
5081 trace_kvm_cr_read(cr
, val
);
5082 skip_emulated_instruction(vcpu
);
5087 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5088 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5089 kvm_lmsw(vcpu
, val
);
5091 skip_emulated_instruction(vcpu
);
5096 vcpu
->run
->exit_reason
= 0;
5097 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5098 (int)(exit_qualification
>> 4) & 3, cr
);
5102 static int handle_dr(struct kvm_vcpu
*vcpu
)
5104 unsigned long exit_qualification
;
5107 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5108 if (!kvm_require_cpl(vcpu
, 0))
5110 dr
= vmcs_readl(GUEST_DR7
);
5113 * As the vm-exit takes precedence over the debug trap, we
5114 * need to emulate the latter, either for the host or the
5115 * guest debugging itself.
5117 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5118 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5119 vcpu
->run
->debug
.arch
.dr7
= dr
;
5120 vcpu
->run
->debug
.arch
.pc
=
5121 vmcs_readl(GUEST_CS_BASE
) +
5122 vmcs_readl(GUEST_RIP
);
5123 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5124 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5127 vcpu
->arch
.dr7
&= ~DR7_GD
;
5128 vcpu
->arch
.dr6
|= DR6_BD
;
5129 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5130 kvm_queue_exception(vcpu
, DB_VECTOR
);
5135 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5136 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5137 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5138 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5141 if (kvm_get_dr(vcpu
, dr
, &val
))
5143 kvm_register_write(vcpu
, reg
, val
);
5145 if (kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]))
5148 skip_emulated_instruction(vcpu
);
5152 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5154 return vcpu
->arch
.dr6
;
5157 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5161 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5163 vmcs_writel(GUEST_DR7
, val
);
5166 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5168 kvm_emulate_cpuid(vcpu
);
5172 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5174 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5177 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5178 trace_kvm_msr_read_ex(ecx
);
5179 kvm_inject_gp(vcpu
, 0);
5183 trace_kvm_msr_read(ecx
, data
);
5185 /* FIXME: handling of bits 32:63 of rax, rdx */
5186 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5187 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5188 skip_emulated_instruction(vcpu
);
5192 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5194 struct msr_data msr
;
5195 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5196 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5197 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5201 msr
.host_initiated
= false;
5202 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5203 trace_kvm_msr_write_ex(ecx
, data
);
5204 kvm_inject_gp(vcpu
, 0);
5208 trace_kvm_msr_write(ecx
, data
);
5209 skip_emulated_instruction(vcpu
);
5213 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5215 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5219 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5221 u32 cpu_based_vm_exec_control
;
5223 /* clear pending irq */
5224 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5225 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5226 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5228 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5230 ++vcpu
->stat
.irq_window_exits
;
5233 * If the user space waits to inject interrupts, exit as soon as
5236 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5237 vcpu
->run
->request_interrupt_window
&&
5238 !kvm_cpu_has_interrupt(vcpu
)) {
5239 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5245 static int handle_halt(struct kvm_vcpu
*vcpu
)
5247 skip_emulated_instruction(vcpu
);
5248 return kvm_emulate_halt(vcpu
);
5251 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5253 skip_emulated_instruction(vcpu
);
5254 kvm_emulate_hypercall(vcpu
);
5258 static int handle_invd(struct kvm_vcpu
*vcpu
)
5260 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5263 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5265 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5267 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5268 skip_emulated_instruction(vcpu
);
5272 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5276 err
= kvm_rdpmc(vcpu
);
5277 kvm_complete_insn_gp(vcpu
, err
);
5282 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5284 skip_emulated_instruction(vcpu
);
5285 kvm_emulate_wbinvd(vcpu
);
5289 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5291 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5292 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5294 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5295 skip_emulated_instruction(vcpu
);
5299 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5301 if (likely(fasteoi
)) {
5302 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5303 int access_type
, offset
;
5305 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5306 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5308 * Sane guest uses MOV to write EOI, with written value
5309 * not cared. So make a short-circuit here by avoiding
5310 * heavy instruction emulation.
5312 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5313 (offset
== APIC_EOI
)) {
5314 kvm_lapic_set_eoi(vcpu
);
5315 skip_emulated_instruction(vcpu
);
5319 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5322 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5324 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5325 int vector
= exit_qualification
& 0xff;
5327 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5328 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5332 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5334 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5335 u32 offset
= exit_qualification
& 0xfff;
5337 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5338 kvm_apic_write_nodecode(vcpu
, offset
);
5342 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5344 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5345 unsigned long exit_qualification
;
5346 bool has_error_code
= false;
5349 int reason
, type
, idt_v
, idt_index
;
5351 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5352 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5353 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5355 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5357 reason
= (u32
)exit_qualification
>> 30;
5358 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5360 case INTR_TYPE_NMI_INTR
:
5361 vcpu
->arch
.nmi_injected
= false;
5362 vmx_set_nmi_mask(vcpu
, true);
5364 case INTR_TYPE_EXT_INTR
:
5365 case INTR_TYPE_SOFT_INTR
:
5366 kvm_clear_interrupt_queue(vcpu
);
5368 case INTR_TYPE_HARD_EXCEPTION
:
5369 if (vmx
->idt_vectoring_info
&
5370 VECTORING_INFO_DELIVER_CODE_MASK
) {
5371 has_error_code
= true;
5373 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5376 case INTR_TYPE_SOFT_EXCEPTION
:
5377 kvm_clear_exception_queue(vcpu
);
5383 tss_selector
= exit_qualification
;
5385 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5386 type
!= INTR_TYPE_EXT_INTR
&&
5387 type
!= INTR_TYPE_NMI_INTR
))
5388 skip_emulated_instruction(vcpu
);
5390 if (kvm_task_switch(vcpu
, tss_selector
,
5391 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5392 has_error_code
, error_code
) == EMULATE_FAIL
) {
5393 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5394 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5395 vcpu
->run
->internal
.ndata
= 0;
5399 /* clear all local breakpoint enable flags */
5400 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
5403 * TODO: What about debug traps on tss switch?
5404 * Are we supposed to inject them and update dr6?
5410 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5412 unsigned long exit_qualification
;
5417 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5419 gla_validity
= (exit_qualification
>> 7) & 0x3;
5420 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5421 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5422 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5423 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5424 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5425 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5426 (long unsigned int)exit_qualification
);
5427 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5428 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5433 * EPT violation happened while executing iret from NMI,
5434 * "blocked by NMI" bit has to be set before next VM entry.
5435 * There are errata that may cause this bit to not be set:
5438 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5439 cpu_has_virtual_nmis() &&
5440 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5441 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5443 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5444 trace_kvm_page_fault(gpa
, exit_qualification
);
5446 /* It is a write fault? */
5447 error_code
= exit_qualification
& (1U << 1);
5448 /* It is a fetch fault? */
5449 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5450 /* ept page table is present? */
5451 error_code
|= (exit_qualification
>> 3) & 0x1;
5453 vcpu
->arch
.exit_qualification
= exit_qualification
;
5455 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5458 static u64
ept_rsvd_mask(u64 spte
, int level
)
5463 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5464 mask
|= (1ULL << i
);
5467 /* bits 7:3 reserved */
5469 else if (level
== 2) {
5470 if (spte
& (1ULL << 7))
5471 /* 2MB ref, bits 20:12 reserved */
5474 /* bits 6:3 reserved */
5481 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5484 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5486 /* 010b (write-only) */
5487 WARN_ON((spte
& 0x7) == 0x2);
5489 /* 110b (write/execute) */
5490 WARN_ON((spte
& 0x7) == 0x6);
5492 /* 100b (execute-only) and value not supported by logical processor */
5493 if (!cpu_has_vmx_ept_execute_only())
5494 WARN_ON((spte
& 0x7) == 0x4);
5498 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5500 if (rsvd_bits
!= 0) {
5501 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5502 __func__
, rsvd_bits
);
5506 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5507 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5509 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5510 ept_mem_type
== 7) {
5511 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5512 __func__
, ept_mem_type
);
5519 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5522 int nr_sptes
, i
, ret
;
5525 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5527 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5528 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5529 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5532 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5533 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5535 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5538 /* It is the real ept misconfig */
5539 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5540 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5542 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5544 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5545 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5547 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5548 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5553 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5555 u32 cpu_based_vm_exec_control
;
5557 /* clear pending NMI */
5558 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5559 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5560 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5561 ++vcpu
->stat
.nmi_window_exits
;
5562 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5567 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5569 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5570 enum emulation_result err
= EMULATE_DONE
;
5573 bool intr_window_requested
;
5574 unsigned count
= 130;
5576 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5577 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5579 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5580 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5581 return handle_interrupt_window(&vmx
->vcpu
);
5583 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5586 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5588 if (err
== EMULATE_USER_EXIT
) {
5589 ++vcpu
->stat
.mmio_exits
;
5594 if (err
!= EMULATE_DONE
) {
5595 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5596 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5597 vcpu
->run
->internal
.ndata
= 0;
5601 if (vcpu
->arch
.halt_request
) {
5602 vcpu
->arch
.halt_request
= 0;
5603 ret
= kvm_emulate_halt(vcpu
);
5607 if (signal_pending(current
))
5613 vmx
->emulation_required
= emulation_required(vcpu
);
5619 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5620 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5622 static int handle_pause(struct kvm_vcpu
*vcpu
)
5624 skip_emulated_instruction(vcpu
);
5625 kvm_vcpu_on_spin(vcpu
);
5630 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
5632 kvm_queue_exception(vcpu
, UD_VECTOR
);
5637 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5638 * We could reuse a single VMCS for all the L2 guests, but we also want the
5639 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5640 * allows keeping them loaded on the processor, and in the future will allow
5641 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5642 * every entry if they never change.
5643 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5644 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5646 * The following functions allocate and free a vmcs02 in this pool.
5649 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5650 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5652 struct vmcs02_list
*item
;
5653 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5654 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5655 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5656 return &item
->vmcs02
;
5659 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5660 /* Recycle the least recently used VMCS. */
5661 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5662 struct vmcs02_list
, list
);
5663 item
->vmptr
= vmx
->nested
.current_vmptr
;
5664 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5665 return &item
->vmcs02
;
5668 /* Create a new VMCS */
5669 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5672 item
->vmcs02
.vmcs
= alloc_vmcs();
5673 if (!item
->vmcs02
.vmcs
) {
5677 loaded_vmcs_init(&item
->vmcs02
);
5678 item
->vmptr
= vmx
->nested
.current_vmptr
;
5679 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5680 vmx
->nested
.vmcs02_num
++;
5681 return &item
->vmcs02
;
5684 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5685 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5687 struct vmcs02_list
*item
;
5688 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5689 if (item
->vmptr
== vmptr
) {
5690 free_loaded_vmcs(&item
->vmcs02
);
5691 list_del(&item
->list
);
5693 vmx
->nested
.vmcs02_num
--;
5699 * Free all VMCSs saved for this vcpu, except the one pointed by
5700 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5701 * currently used, if running L2), and vmcs01 when running L2.
5703 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5705 struct vmcs02_list
*item
, *n
;
5706 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5707 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5708 free_loaded_vmcs(&item
->vmcs02
);
5709 list_del(&item
->list
);
5712 vmx
->nested
.vmcs02_num
= 0;
5714 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5715 free_loaded_vmcs(&vmx
->vmcs01
);
5719 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5720 * set the success or error code of an emulated VMX instruction, as specified
5721 * by Vol 2B, VMX Instruction Reference, "Conventions".
5723 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5725 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5726 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5727 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5730 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5732 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5733 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5734 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5738 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5739 u32 vm_instruction_error
)
5741 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5743 * failValid writes the error number to the current VMCS, which
5744 * can't be done there isn't a current VMCS.
5746 nested_vmx_failInvalid(vcpu
);
5749 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5750 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5751 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5753 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5755 * We don't need to force a shadow sync because
5756 * VM_INSTRUCTION_ERROR is not shadowed
5761 * Emulate the VMXON instruction.
5762 * Currently, we just remember that VMX is active, and do not save or even
5763 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5764 * do not currently need to store anything in that guest-allocated memory
5765 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5766 * argument is different from the VMXON pointer (which the spec says they do).
5768 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5770 struct kvm_segment cs
;
5771 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5772 struct vmcs
*shadow_vmcs
;
5773 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5774 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5776 /* The Intel VMX Instruction Reference lists a bunch of bits that
5777 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5778 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5779 * Otherwise, we should fail with #UD. We test these now:
5781 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5782 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
5783 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
5784 kvm_queue_exception(vcpu
, UD_VECTOR
);
5788 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5789 if (is_long_mode(vcpu
) && !cs
.l
) {
5790 kvm_queue_exception(vcpu
, UD_VECTOR
);
5794 if (vmx_get_cpl(vcpu
)) {
5795 kvm_inject_gp(vcpu
, 0);
5798 if (vmx
->nested
.vmxon
) {
5799 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
5800 skip_emulated_instruction(vcpu
);
5804 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
5805 != VMXON_NEEDED_FEATURES
) {
5806 kvm_inject_gp(vcpu
, 0);
5810 if (enable_shadow_vmcs
) {
5811 shadow_vmcs
= alloc_vmcs();
5814 /* mark vmcs as shadow */
5815 shadow_vmcs
->revision_id
|= (1u << 31);
5816 /* init shadow vmcs */
5817 vmcs_clear(shadow_vmcs
);
5818 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
5821 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
5822 vmx
->nested
.vmcs02_num
= 0;
5824 vmx
->nested
.vmxon
= true;
5826 skip_emulated_instruction(vcpu
);
5827 nested_vmx_succeed(vcpu
);
5832 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5833 * for running VMX instructions (except VMXON, whose prerequisites are
5834 * slightly different). It also specifies what exception to inject otherwise.
5836 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
5838 struct kvm_segment cs
;
5839 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5841 if (!vmx
->nested
.vmxon
) {
5842 kvm_queue_exception(vcpu
, UD_VECTOR
);
5846 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
5847 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
5848 (is_long_mode(vcpu
) && !cs
.l
)) {
5849 kvm_queue_exception(vcpu
, UD_VECTOR
);
5853 if (vmx_get_cpl(vcpu
)) {
5854 kvm_inject_gp(vcpu
, 0);
5861 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
5864 if (enable_shadow_vmcs
) {
5865 if (vmx
->nested
.current_vmcs12
!= NULL
) {
5866 /* copy to memory all shadowed fields in case
5867 they were modified */
5868 copy_shadow_to_vmcs12(vmx
);
5869 vmx
->nested
.sync_shadow_vmcs
= false;
5870 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5871 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5872 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
5873 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
5876 kunmap(vmx
->nested
.current_vmcs12_page
);
5877 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5881 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5882 * just stops using VMX.
5884 static void free_nested(struct vcpu_vmx
*vmx
)
5886 if (!vmx
->nested
.vmxon
)
5888 vmx
->nested
.vmxon
= false;
5889 if (vmx
->nested
.current_vmptr
!= -1ull) {
5890 nested_release_vmcs12(vmx
);
5891 vmx
->nested
.current_vmptr
= -1ull;
5892 vmx
->nested
.current_vmcs12
= NULL
;
5894 if (enable_shadow_vmcs
)
5895 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
5896 /* Unpin physical memory we referred to in current vmcs02 */
5897 if (vmx
->nested
.apic_access_page
) {
5898 nested_release_page(vmx
->nested
.apic_access_page
);
5899 vmx
->nested
.apic_access_page
= 0;
5902 nested_free_all_saved_vmcss(vmx
);
5905 /* Emulate the VMXOFF instruction */
5906 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
5908 if (!nested_vmx_check_permission(vcpu
))
5910 free_nested(to_vmx(vcpu
));
5911 skip_emulated_instruction(vcpu
);
5912 nested_vmx_succeed(vcpu
);
5917 * Decode the memory-address operand of a vmx instruction, as recorded on an
5918 * exit caused by such an instruction (run by a guest hypervisor).
5919 * On success, returns 0. When the operand is invalid, returns 1 and throws
5922 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5923 unsigned long exit_qualification
,
5924 u32 vmx_instruction_info
, gva_t
*ret
)
5927 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5928 * Execution", on an exit, vmx_instruction_info holds most of the
5929 * addressing components of the operand. Only the displacement part
5930 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5931 * For how an actual address is calculated from all these components,
5932 * refer to Vol. 1, "Operand Addressing".
5934 int scaling
= vmx_instruction_info
& 3;
5935 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5936 bool is_reg
= vmx_instruction_info
& (1u << 10);
5937 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5938 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5939 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5940 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5941 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5944 kvm_queue_exception(vcpu
, UD_VECTOR
);
5948 /* Addr = segment_base + offset */
5949 /* offset = base + [index * scale] + displacement */
5950 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5952 *ret
+= kvm_register_read(vcpu
, base_reg
);
5954 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5955 *ret
+= exit_qualification
; /* holds the displacement */
5957 if (addr_size
== 1) /* 32 bit */
5961 * TODO: throw #GP (and return 1) in various cases that the VM*
5962 * instructions require it - e.g., offset beyond segment limit,
5963 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5964 * address, and so on. Currently these are not checked.
5969 /* Emulate the VMCLEAR instruction */
5970 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5975 struct vmcs12
*vmcs12
;
5977 struct x86_exception e
;
5979 if (!nested_vmx_check_permission(vcpu
))
5982 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5983 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5986 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5987 sizeof(vmptr
), &e
)) {
5988 kvm_inject_page_fault(vcpu
, &e
);
5992 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5993 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5994 skip_emulated_instruction(vcpu
);
5998 if (vmptr
== vmx
->nested
.current_vmptr
) {
5999 nested_release_vmcs12(vmx
);
6000 vmx
->nested
.current_vmptr
= -1ull;
6001 vmx
->nested
.current_vmcs12
= NULL
;
6004 page
= nested_get_page(vcpu
, vmptr
);
6007 * For accurate processor emulation, VMCLEAR beyond available
6008 * physical memory should do nothing at all. However, it is
6009 * possible that a nested vmx bug, not a guest hypervisor bug,
6010 * resulted in this case, so let's shut down before doing any
6013 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6016 vmcs12
= kmap(page
);
6017 vmcs12
->launch_state
= 0;
6019 nested_release_page(page
);
6021 nested_free_vmcs02(vmx
, vmptr
);
6023 skip_emulated_instruction(vcpu
);
6024 nested_vmx_succeed(vcpu
);
6028 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6030 /* Emulate the VMLAUNCH instruction */
6031 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6033 return nested_vmx_run(vcpu
, true);
6036 /* Emulate the VMRESUME instruction */
6037 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6040 return nested_vmx_run(vcpu
, false);
6043 enum vmcs_field_type
{
6044 VMCS_FIELD_TYPE_U16
= 0,
6045 VMCS_FIELD_TYPE_U64
= 1,
6046 VMCS_FIELD_TYPE_U32
= 2,
6047 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6050 static inline int vmcs_field_type(unsigned long field
)
6052 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6053 return VMCS_FIELD_TYPE_U32
;
6054 return (field
>> 13) & 0x3 ;
6057 static inline int vmcs_field_readonly(unsigned long field
)
6059 return (((field
>> 10) & 0x3) == 1);
6063 * Read a vmcs12 field. Since these can have varying lengths and we return
6064 * one type, we chose the biggest type (u64) and zero-extend the return value
6065 * to that size. Note that the caller, handle_vmread, might need to use only
6066 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6067 * 64-bit fields are to be returned).
6069 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6070 unsigned long field
, u64
*ret
)
6072 short offset
= vmcs_field_to_offset(field
);
6078 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6080 switch (vmcs_field_type(field
)) {
6081 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6082 *ret
= *((natural_width
*)p
);
6084 case VMCS_FIELD_TYPE_U16
:
6087 case VMCS_FIELD_TYPE_U32
:
6090 case VMCS_FIELD_TYPE_U64
:
6094 return 0; /* can never happen. */
6099 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6100 unsigned long field
, u64 field_value
){
6101 short offset
= vmcs_field_to_offset(field
);
6102 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6106 switch (vmcs_field_type(field
)) {
6107 case VMCS_FIELD_TYPE_U16
:
6108 *(u16
*)p
= field_value
;
6110 case VMCS_FIELD_TYPE_U32
:
6111 *(u32
*)p
= field_value
;
6113 case VMCS_FIELD_TYPE_U64
:
6114 *(u64
*)p
= field_value
;
6116 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6117 *(natural_width
*)p
= field_value
;
6120 return false; /* can never happen. */
6125 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6128 unsigned long field
;
6130 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6131 const unsigned long *fields
= shadow_read_write_fields
;
6132 const int num_fields
= max_shadow_read_write_fields
;
6134 vmcs_load(shadow_vmcs
);
6136 for (i
= 0; i
< num_fields
; i
++) {
6138 switch (vmcs_field_type(field
)) {
6139 case VMCS_FIELD_TYPE_U16
:
6140 field_value
= vmcs_read16(field
);
6142 case VMCS_FIELD_TYPE_U32
:
6143 field_value
= vmcs_read32(field
);
6145 case VMCS_FIELD_TYPE_U64
:
6146 field_value
= vmcs_read64(field
);
6148 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6149 field_value
= vmcs_readl(field
);
6152 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6155 vmcs_clear(shadow_vmcs
);
6156 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6159 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6161 const unsigned long *fields
[] = {
6162 shadow_read_write_fields
,
6163 shadow_read_only_fields
6165 const int max_fields
[] = {
6166 max_shadow_read_write_fields
,
6167 max_shadow_read_only_fields
6170 unsigned long field
;
6171 u64 field_value
= 0;
6172 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6174 vmcs_load(shadow_vmcs
);
6176 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6177 for (i
= 0; i
< max_fields
[q
]; i
++) {
6178 field
= fields
[q
][i
];
6179 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6181 switch (vmcs_field_type(field
)) {
6182 case VMCS_FIELD_TYPE_U16
:
6183 vmcs_write16(field
, (u16
)field_value
);
6185 case VMCS_FIELD_TYPE_U32
:
6186 vmcs_write32(field
, (u32
)field_value
);
6188 case VMCS_FIELD_TYPE_U64
:
6189 vmcs_write64(field
, (u64
)field_value
);
6191 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6192 vmcs_writel(field
, (long)field_value
);
6198 vmcs_clear(shadow_vmcs
);
6199 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6203 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6204 * used before) all generate the same failure when it is missing.
6206 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6208 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6209 if (vmx
->nested
.current_vmptr
== -1ull) {
6210 nested_vmx_failInvalid(vcpu
);
6211 skip_emulated_instruction(vcpu
);
6217 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6219 unsigned long field
;
6221 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6222 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6225 if (!nested_vmx_check_permission(vcpu
) ||
6226 !nested_vmx_check_vmcs12(vcpu
))
6229 /* Decode instruction info and find the field to read */
6230 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6231 /* Read the field, zero-extended to a u64 field_value */
6232 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6233 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6234 skip_emulated_instruction(vcpu
);
6238 * Now copy part of this value to register or memory, as requested.
6239 * Note that the number of bits actually copied is 32 or 64 depending
6240 * on the guest's mode (32 or 64 bit), not on the given field's length.
6242 if (vmx_instruction_info
& (1u << 10)) {
6243 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6246 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6247 vmx_instruction_info
, &gva
))
6249 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6250 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6251 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6254 nested_vmx_succeed(vcpu
);
6255 skip_emulated_instruction(vcpu
);
6260 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6262 unsigned long field
;
6264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6265 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6266 /* The value to write might be 32 or 64 bits, depending on L1's long
6267 * mode, and eventually we need to write that into a field of several
6268 * possible lengths. The code below first zero-extends the value to 64
6269 * bit (field_value), and then copies only the approriate number of
6270 * bits into the vmcs12 field.
6272 u64 field_value
= 0;
6273 struct x86_exception e
;
6275 if (!nested_vmx_check_permission(vcpu
) ||
6276 !nested_vmx_check_vmcs12(vcpu
))
6279 if (vmx_instruction_info
& (1u << 10))
6280 field_value
= kvm_register_read(vcpu
,
6281 (((vmx_instruction_info
) >> 3) & 0xf));
6283 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6284 vmx_instruction_info
, &gva
))
6286 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6287 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6288 kvm_inject_page_fault(vcpu
, &e
);
6294 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6295 if (vmcs_field_readonly(field
)) {
6296 nested_vmx_failValid(vcpu
,
6297 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6298 skip_emulated_instruction(vcpu
);
6302 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6303 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6304 skip_emulated_instruction(vcpu
);
6308 nested_vmx_succeed(vcpu
);
6309 skip_emulated_instruction(vcpu
);
6313 /* Emulate the VMPTRLD instruction */
6314 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6316 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6319 struct x86_exception e
;
6322 if (!nested_vmx_check_permission(vcpu
))
6325 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6326 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6329 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6330 sizeof(vmptr
), &e
)) {
6331 kvm_inject_page_fault(vcpu
, &e
);
6335 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
6336 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
6337 skip_emulated_instruction(vcpu
);
6341 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6342 struct vmcs12
*new_vmcs12
;
6344 page
= nested_get_page(vcpu
, vmptr
);
6346 nested_vmx_failInvalid(vcpu
);
6347 skip_emulated_instruction(vcpu
);
6350 new_vmcs12
= kmap(page
);
6351 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6353 nested_release_page_clean(page
);
6354 nested_vmx_failValid(vcpu
,
6355 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6356 skip_emulated_instruction(vcpu
);
6359 if (vmx
->nested
.current_vmptr
!= -1ull)
6360 nested_release_vmcs12(vmx
);
6362 vmx
->nested
.current_vmptr
= vmptr
;
6363 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6364 vmx
->nested
.current_vmcs12_page
= page
;
6365 if (enable_shadow_vmcs
) {
6366 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6367 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6368 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6369 vmcs_write64(VMCS_LINK_POINTER
,
6370 __pa(vmx
->nested
.current_shadow_vmcs
));
6371 vmx
->nested
.sync_shadow_vmcs
= true;
6375 nested_vmx_succeed(vcpu
);
6376 skip_emulated_instruction(vcpu
);
6380 /* Emulate the VMPTRST instruction */
6381 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6383 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6384 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6386 struct x86_exception e
;
6388 if (!nested_vmx_check_permission(vcpu
))
6391 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6392 vmx_instruction_info
, &vmcs_gva
))
6394 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6395 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6396 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6398 kvm_inject_page_fault(vcpu
, &e
);
6401 nested_vmx_succeed(vcpu
);
6402 skip_emulated_instruction(vcpu
);
6406 /* Emulate the INVEPT instruction */
6407 static int handle_invept(struct kvm_vcpu
*vcpu
)
6409 u32 vmx_instruction_info
, types
;
6412 struct x86_exception e
;
6416 u64 eptp_mask
= ((1ull << 51) - 1) & PAGE_MASK
;
6418 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6419 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6420 kvm_queue_exception(vcpu
, UD_VECTOR
);
6424 if (!nested_vmx_check_permission(vcpu
))
6427 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6428 kvm_queue_exception(vcpu
, UD_VECTOR
);
6432 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6433 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6435 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6437 if (!(types
& (1UL << type
))) {
6438 nested_vmx_failValid(vcpu
,
6439 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6443 /* According to the Intel VMX instruction reference, the memory
6444 * operand is read even if it isn't needed (e.g., for type==global)
6446 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6447 vmx_instruction_info
, &gva
))
6449 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6450 sizeof(operand
), &e
)) {
6451 kvm_inject_page_fault(vcpu
, &e
);
6456 case VMX_EPT_EXTENT_CONTEXT
:
6457 if ((operand
.eptp
& eptp_mask
) !=
6458 (nested_ept_get_cr3(vcpu
) & eptp_mask
))
6460 case VMX_EPT_EXTENT_GLOBAL
:
6461 kvm_mmu_sync_roots(vcpu
);
6462 kvm_mmu_flush_tlb(vcpu
);
6463 nested_vmx_succeed(vcpu
);
6470 skip_emulated_instruction(vcpu
);
6475 * The exit handlers return 1 if the exit was handled fully and guest execution
6476 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6477 * to be done to userspace and return 0.
6479 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6480 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6481 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6482 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6483 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6484 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6485 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6486 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6487 [EXIT_REASON_CPUID
] = handle_cpuid
,
6488 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6489 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6490 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6491 [EXIT_REASON_HLT
] = handle_halt
,
6492 [EXIT_REASON_INVD
] = handle_invd
,
6493 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6494 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6495 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6496 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6497 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6498 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6499 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6500 [EXIT_REASON_VMREAD
] = handle_vmread
,
6501 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6502 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6503 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6504 [EXIT_REASON_VMON
] = handle_vmon
,
6505 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6506 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6507 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6508 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6509 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6510 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6511 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6512 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6513 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6514 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6515 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6516 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
6517 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
6518 [EXIT_REASON_INVEPT
] = handle_invept
,
6521 static const int kvm_vmx_max_exit_handlers
=
6522 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6524 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6525 struct vmcs12
*vmcs12
)
6527 unsigned long exit_qualification
;
6528 gpa_t bitmap
, last_bitmap
;
6533 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6534 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6536 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6538 port
= exit_qualification
>> 16;
6539 size
= (exit_qualification
& 7) + 1;
6541 last_bitmap
= (gpa_t
)-1;
6546 bitmap
= vmcs12
->io_bitmap_a
;
6547 else if (port
< 0x10000)
6548 bitmap
= vmcs12
->io_bitmap_b
;
6551 bitmap
+= (port
& 0x7fff) / 8;
6553 if (last_bitmap
!= bitmap
)
6554 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6556 if (b
& (1 << (port
& 7)))
6561 last_bitmap
= bitmap
;
6568 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6569 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6570 * disinterest in the current event (read or write a specific MSR) by using an
6571 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6573 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6574 struct vmcs12
*vmcs12
, u32 exit_reason
)
6576 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6579 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6583 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6584 * for the four combinations of read/write and low/high MSR numbers.
6585 * First we need to figure out which of the four to use:
6587 bitmap
= vmcs12
->msr_bitmap
;
6588 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6590 if (msr_index
>= 0xc0000000) {
6591 msr_index
-= 0xc0000000;
6595 /* Then read the msr_index'th bit from this bitmap: */
6596 if (msr_index
< 1024*8) {
6598 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6600 return 1 & (b
>> (msr_index
& 7));
6602 return 1; /* let L1 handle the wrong parameter */
6606 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6607 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6608 * intercept (via guest_host_mask etc.) the current event.
6610 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6611 struct vmcs12
*vmcs12
)
6613 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6614 int cr
= exit_qualification
& 15;
6615 int reg
= (exit_qualification
>> 8) & 15;
6616 unsigned long val
= kvm_register_read(vcpu
, reg
);
6618 switch ((exit_qualification
>> 4) & 3) {
6619 case 0: /* mov to cr */
6622 if (vmcs12
->cr0_guest_host_mask
&
6623 (val
^ vmcs12
->cr0_read_shadow
))
6627 if ((vmcs12
->cr3_target_count
>= 1 &&
6628 vmcs12
->cr3_target_value0
== val
) ||
6629 (vmcs12
->cr3_target_count
>= 2 &&
6630 vmcs12
->cr3_target_value1
== val
) ||
6631 (vmcs12
->cr3_target_count
>= 3 &&
6632 vmcs12
->cr3_target_value2
== val
) ||
6633 (vmcs12
->cr3_target_count
>= 4 &&
6634 vmcs12
->cr3_target_value3
== val
))
6636 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6640 if (vmcs12
->cr4_guest_host_mask
&
6641 (vmcs12
->cr4_read_shadow
^ val
))
6645 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6651 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6652 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6655 case 1: /* mov from cr */
6658 if (vmcs12
->cpu_based_vm_exec_control
&
6659 CPU_BASED_CR3_STORE_EXITING
)
6663 if (vmcs12
->cpu_based_vm_exec_control
&
6664 CPU_BASED_CR8_STORE_EXITING
)
6671 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6672 * cr0. Other attempted changes are ignored, with no exit.
6674 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6675 (val
^ vmcs12
->cr0_read_shadow
))
6677 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6678 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6687 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6688 * should handle it ourselves in L0 (and then continue L2). Only call this
6689 * when in is_guest_mode (L2).
6691 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6693 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6694 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6695 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6696 u32 exit_reason
= vmx
->exit_reason
;
6698 if (vmx
->nested
.nested_run_pending
)
6701 if (unlikely(vmx
->fail
)) {
6702 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6703 vmcs_read32(VM_INSTRUCTION_ERROR
));
6707 switch (exit_reason
) {
6708 case EXIT_REASON_EXCEPTION_NMI
:
6709 if (!is_exception(intr_info
))
6711 else if (is_page_fault(intr_info
))
6713 else if (is_no_device(intr_info
) &&
6714 !(nested_read_cr0(vmcs12
) & X86_CR0_TS
))
6716 return vmcs12
->exception_bitmap
&
6717 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6718 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6720 case EXIT_REASON_TRIPLE_FAULT
:
6722 case EXIT_REASON_PENDING_INTERRUPT
:
6723 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6724 case EXIT_REASON_NMI_WINDOW
:
6725 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6726 case EXIT_REASON_TASK_SWITCH
:
6728 case EXIT_REASON_CPUID
:
6730 case EXIT_REASON_HLT
:
6731 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6732 case EXIT_REASON_INVD
:
6734 case EXIT_REASON_INVLPG
:
6735 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6736 case EXIT_REASON_RDPMC
:
6737 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6738 case EXIT_REASON_RDTSC
:
6739 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6740 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6741 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6742 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6743 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6744 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6745 case EXIT_REASON_INVEPT
:
6747 * VMX instructions trap unconditionally. This allows L1 to
6748 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6751 case EXIT_REASON_CR_ACCESS
:
6752 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6753 case EXIT_REASON_DR_ACCESS
:
6754 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6755 case EXIT_REASON_IO_INSTRUCTION
:
6756 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6757 case EXIT_REASON_MSR_READ
:
6758 case EXIT_REASON_MSR_WRITE
:
6759 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6760 case EXIT_REASON_INVALID_STATE
:
6762 case EXIT_REASON_MWAIT_INSTRUCTION
:
6763 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6764 case EXIT_REASON_MONITOR_INSTRUCTION
:
6765 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6766 case EXIT_REASON_PAUSE_INSTRUCTION
:
6767 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6768 nested_cpu_has2(vmcs12
,
6769 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6770 case EXIT_REASON_MCE_DURING_VMENTRY
:
6772 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6774 case EXIT_REASON_APIC_ACCESS
:
6775 return nested_cpu_has2(vmcs12
,
6776 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6777 case EXIT_REASON_EPT_VIOLATION
:
6779 * L0 always deals with the EPT violation. If nested EPT is
6780 * used, and the nested mmu code discovers that the address is
6781 * missing in the guest EPT table (EPT12), the EPT violation
6782 * will be injected with nested_ept_inject_page_fault()
6785 case EXIT_REASON_EPT_MISCONFIG
:
6787 * L2 never uses directly L1's EPT, but rather L0's own EPT
6788 * table (shadow on EPT) or a merged EPT table that L0 built
6789 * (EPT on EPT). So any problems with the structure of the
6790 * table is L0's fault.
6793 case EXIT_REASON_PREEMPTION_TIMER
:
6794 return vmcs12
->pin_based_vm_exec_control
&
6795 PIN_BASED_VMX_PREEMPTION_TIMER
;
6796 case EXIT_REASON_WBINVD
:
6797 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6798 case EXIT_REASON_XSETBV
:
6805 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6807 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6808 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6811 static void nested_adjust_preemption_timer(struct kvm_vcpu
*vcpu
)
6814 u32 preempt_val_l1
, preempt_val_l2
, preempt_scale
;
6816 if (!(get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
6817 PIN_BASED_VMX_PREEMPTION_TIMER
))
6819 preempt_scale
= native_read_msr(MSR_IA32_VMX_MISC
) &
6820 MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE
;
6821 preempt_val_l2
= vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
6822 delta_tsc_l1
= vmx_read_l1_tsc(vcpu
, native_read_tsc())
6823 - vcpu
->arch
.last_guest_tsc
;
6824 preempt_val_l1
= delta_tsc_l1
>> preempt_scale
;
6825 if (preempt_val_l2
<= preempt_val_l1
)
6828 preempt_val_l2
-= preempt_val_l1
;
6829 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, preempt_val_l2
);
6833 * The guest has exited. See if we can fix it or if we need userspace
6836 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6838 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6839 u32 exit_reason
= vmx
->exit_reason
;
6840 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6842 /* If guest state is invalid, start emulating */
6843 if (vmx
->emulation_required
)
6844 return handle_invalid_guest_state(vcpu
);
6846 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6847 nested_vmx_vmexit(vcpu
);
6851 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6852 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6853 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6858 if (unlikely(vmx
->fail
)) {
6859 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6860 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6861 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6867 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6868 * delivery event since it indicates guest is accessing MMIO.
6869 * The vm-exit can be triggered again after return to guest that
6870 * will cause infinite loop.
6872 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6873 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6874 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6875 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6876 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6877 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
6878 vcpu
->run
->internal
.ndata
= 2;
6879 vcpu
->run
->internal
.data
[0] = vectoring_info
;
6880 vcpu
->run
->internal
.data
[1] = exit_reason
;
6884 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
6885 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
6886 get_vmcs12(vcpu
))))) {
6887 if (vmx_interrupt_allowed(vcpu
)) {
6888 vmx
->soft_vnmi_blocked
= 0;
6889 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
6890 vcpu
->arch
.nmi_pending
) {
6892 * This CPU don't support us in finding the end of an
6893 * NMI-blocked window if the guest runs with IRQs
6894 * disabled. So we pull the trigger after 1 s of
6895 * futile waiting, but inform the user about this.
6897 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
6898 "state on VCPU %d after 1 s timeout\n",
6899 __func__
, vcpu
->vcpu_id
);
6900 vmx
->soft_vnmi_blocked
= 0;
6904 if (exit_reason
< kvm_vmx_max_exit_handlers
6905 && kvm_vmx_exit_handlers
[exit_reason
])
6906 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
6908 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6909 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
6914 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
6916 if (irr
== -1 || tpr
< irr
) {
6917 vmcs_write32(TPR_THRESHOLD
, 0);
6921 vmcs_write32(TPR_THRESHOLD
, irr
);
6924 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
6926 u32 sec_exec_control
;
6929 * There is not point to enable virtualize x2apic without enable
6932 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
6933 !vmx_vm_has_apicv(vcpu
->kvm
))
6936 if (!vm_need_tpr_shadow(vcpu
->kvm
))
6939 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6942 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6943 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6945 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
6946 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6948 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
6950 vmx_set_msr_bitmap(vcpu
);
6953 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
6958 if (!vmx_vm_has_apicv(kvm
))
6964 status
= vmcs_read16(GUEST_INTR_STATUS
);
6969 vmcs_write16(GUEST_INTR_STATUS
, status
);
6973 static void vmx_set_rvi(int vector
)
6978 status
= vmcs_read16(GUEST_INTR_STATUS
);
6979 old
= (u8
)status
& 0xff;
6980 if ((u8
)vector
!= old
) {
6982 status
|= (u8
)vector
;
6983 vmcs_write16(GUEST_INTR_STATUS
, status
);
6987 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
6992 vmx_set_rvi(max_irr
);
6995 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
6997 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7000 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7001 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7002 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7003 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7006 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7010 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7011 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7014 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7015 exit_intr_info
= vmx
->exit_intr_info
;
7017 /* Handle machine checks before interrupts are enabled */
7018 if (is_machine_check(exit_intr_info
))
7019 kvm_machine_check();
7021 /* We need to handle NMIs before interrupts are enabled */
7022 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7023 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7024 kvm_before_handle_nmi(&vmx
->vcpu
);
7026 kvm_after_handle_nmi(&vmx
->vcpu
);
7030 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7032 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7035 * If external interrupt exists, IF bit is set in rflags/eflags on the
7036 * interrupt stack frame, and interrupt will be enabled on a return
7037 * from interrupt handler.
7039 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7040 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7041 unsigned int vector
;
7042 unsigned long entry
;
7044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7045 #ifdef CONFIG_X86_64
7049 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7050 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7051 entry
= gate_offset(*desc
);
7053 #ifdef CONFIG_X86_64
7054 "mov %%" _ASM_SP
", %[sp]\n\t"
7055 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7060 "orl $0x200, (%%" _ASM_SP
")\n\t"
7061 __ASM_SIZE(push
) " $%c[cs]\n\t"
7062 "call *%[entry]\n\t"
7064 #ifdef CONFIG_X86_64
7069 [ss
]"i"(__KERNEL_DS
),
7070 [cs
]"i"(__KERNEL_CS
)
7076 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7081 bool idtv_info_valid
;
7083 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7085 if (cpu_has_virtual_nmis()) {
7086 if (vmx
->nmi_known_unmasked
)
7089 * Can't use vmx->exit_intr_info since we're not sure what
7090 * the exit reason is.
7092 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7093 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7094 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7096 * SDM 3: 27.7.1.2 (September 2008)
7097 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7098 * a guest IRET fault.
7099 * SDM 3: 23.2.2 (September 2008)
7100 * Bit 12 is undefined in any of the following cases:
7101 * If the VM exit sets the valid bit in the IDT-vectoring
7102 * information field.
7103 * If the VM exit is due to a double fault.
7105 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7106 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7107 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7108 GUEST_INTR_STATE_NMI
);
7110 vmx
->nmi_known_unmasked
=
7111 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7112 & GUEST_INTR_STATE_NMI
);
7113 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7114 vmx
->vnmi_blocked_time
+=
7115 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7118 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7119 u32 idt_vectoring_info
,
7120 int instr_len_field
,
7121 int error_code_field
)
7125 bool idtv_info_valid
;
7127 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7129 vcpu
->arch
.nmi_injected
= false;
7130 kvm_clear_exception_queue(vcpu
);
7131 kvm_clear_interrupt_queue(vcpu
);
7133 if (!idtv_info_valid
)
7136 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7138 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7139 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7142 case INTR_TYPE_NMI_INTR
:
7143 vcpu
->arch
.nmi_injected
= true;
7145 * SDM 3: 27.7.1.2 (September 2008)
7146 * Clear bit "block by NMI" before VM entry if a NMI
7149 vmx_set_nmi_mask(vcpu
, false);
7151 case INTR_TYPE_SOFT_EXCEPTION
:
7152 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7154 case INTR_TYPE_HARD_EXCEPTION
:
7155 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7156 u32 err
= vmcs_read32(error_code_field
);
7157 kvm_requeue_exception_e(vcpu
, vector
, err
);
7159 kvm_requeue_exception(vcpu
, vector
);
7161 case INTR_TYPE_SOFT_INTR
:
7162 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7164 case INTR_TYPE_EXT_INTR
:
7165 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7172 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7174 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7175 VM_EXIT_INSTRUCTION_LEN
,
7176 IDT_VECTORING_ERROR_CODE
);
7179 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7181 __vmx_complete_interrupts(vcpu
,
7182 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7183 VM_ENTRY_INSTRUCTION_LEN
,
7184 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7186 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7189 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7192 struct perf_guest_switch_msr
*msrs
;
7194 msrs
= perf_guest_get_msrs(&nr_msrs
);
7199 for (i
= 0; i
< nr_msrs
; i
++)
7200 if (msrs
[i
].host
== msrs
[i
].guest
)
7201 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7203 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7207 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7210 unsigned long debugctlmsr
;
7212 /* Record the guest's net vcpu time for enforced NMI injections. */
7213 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7214 vmx
->entry_time
= ktime_get();
7216 /* Don't enter VMX if guest state is invalid, let the exit handler
7217 start emulation until we arrive back to a valid state */
7218 if (vmx
->emulation_required
)
7221 if (vmx
->nested
.sync_shadow_vmcs
) {
7222 copy_vmcs12_to_shadow(vmx
);
7223 vmx
->nested
.sync_shadow_vmcs
= false;
7226 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7227 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7228 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7229 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7231 /* When single-stepping over STI and MOV SS, we must clear the
7232 * corresponding interruptibility bits in the guest state. Otherwise
7233 * vmentry fails as it then expects bit 14 (BS) in pending debug
7234 * exceptions being set, but that's not correct for the guest debugging
7236 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7237 vmx_set_interrupt_shadow(vcpu
, 0);
7239 atomic_switch_perf_msrs(vmx
);
7240 debugctlmsr
= get_debugctlmsr();
7242 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
)
7243 nested_adjust_preemption_timer(vcpu
);
7244 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7246 /* Store host registers */
7247 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7248 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7249 "push %%" _ASM_CX
" \n\t"
7250 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7252 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7253 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7255 /* Reload cr2 if changed */
7256 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7257 "mov %%cr2, %%" _ASM_DX
" \n\t"
7258 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7260 "mov %%" _ASM_AX
", %%cr2 \n\t"
7262 /* Check if vmlaunch of vmresume is needed */
7263 "cmpl $0, %c[launched](%0) \n\t"
7264 /* Load guest registers. Don't clobber flags. */
7265 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7266 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7267 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7268 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7269 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7270 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7271 #ifdef CONFIG_X86_64
7272 "mov %c[r8](%0), %%r8 \n\t"
7273 "mov %c[r9](%0), %%r9 \n\t"
7274 "mov %c[r10](%0), %%r10 \n\t"
7275 "mov %c[r11](%0), %%r11 \n\t"
7276 "mov %c[r12](%0), %%r12 \n\t"
7277 "mov %c[r13](%0), %%r13 \n\t"
7278 "mov %c[r14](%0), %%r14 \n\t"
7279 "mov %c[r15](%0), %%r15 \n\t"
7281 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7283 /* Enter guest mode */
7285 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7287 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7289 /* Save guest registers, load host registers, keep flags */
7290 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7292 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7293 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7294 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7295 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7296 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7297 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7298 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7299 #ifdef CONFIG_X86_64
7300 "mov %%r8, %c[r8](%0) \n\t"
7301 "mov %%r9, %c[r9](%0) \n\t"
7302 "mov %%r10, %c[r10](%0) \n\t"
7303 "mov %%r11, %c[r11](%0) \n\t"
7304 "mov %%r12, %c[r12](%0) \n\t"
7305 "mov %%r13, %c[r13](%0) \n\t"
7306 "mov %%r14, %c[r14](%0) \n\t"
7307 "mov %%r15, %c[r15](%0) \n\t"
7309 "mov %%cr2, %%" _ASM_AX
" \n\t"
7310 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7312 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7313 "setbe %c[fail](%0) \n\t"
7314 ".pushsection .rodata \n\t"
7315 ".global vmx_return \n\t"
7316 "vmx_return: " _ASM_PTR
" 2b \n\t"
7318 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7319 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7320 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7321 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7322 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7323 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7324 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7325 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7326 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7327 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7328 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7329 #ifdef CONFIG_X86_64
7330 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7331 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7332 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7333 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7334 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7335 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7336 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7337 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7339 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7340 [wordsize
]"i"(sizeof(ulong
))
7342 #ifdef CONFIG_X86_64
7343 , "rax", "rbx", "rdi", "rsi"
7344 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7346 , "eax", "ebx", "edi", "esi"
7350 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7352 update_debugctlmsr(debugctlmsr
);
7354 #ifndef CONFIG_X86_64
7356 * The sysexit path does not restore ds/es, so we must set them to
7357 * a reasonable value ourselves.
7359 * We can't defer this to vmx_load_host_state() since that function
7360 * may be executed in interrupt context, which saves and restore segments
7361 * around it, nullifying its effect.
7363 loadsegment(ds
, __USER_DS
);
7364 loadsegment(es
, __USER_DS
);
7367 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7368 | (1 << VCPU_EXREG_RFLAGS
)
7369 | (1 << VCPU_EXREG_CPL
)
7370 | (1 << VCPU_EXREG_PDPTR
)
7371 | (1 << VCPU_EXREG_SEGMENTS
)
7372 | (1 << VCPU_EXREG_CR3
));
7373 vcpu
->arch
.regs_dirty
= 0;
7375 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7377 vmx
->loaded_vmcs
->launched
= 1;
7379 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7380 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7383 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7384 * we did not inject a still-pending event to L1 now because of
7385 * nested_run_pending, we need to re-enable this bit.
7387 if (vmx
->nested
.nested_run_pending
)
7388 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7390 vmx
->nested
.nested_run_pending
= 0;
7392 vmx_complete_atomic_exit(vmx
);
7393 vmx_recover_nmi_blocking(vmx
);
7394 vmx_complete_interrupts(vmx
);
7397 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7399 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7402 free_loaded_vmcs(vmx
->loaded_vmcs
);
7404 kfree(vmx
->guest_msrs
);
7405 kvm_vcpu_uninit(vcpu
);
7406 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7409 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7412 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7416 return ERR_PTR(-ENOMEM
);
7420 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7424 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7426 if (!vmx
->guest_msrs
) {
7430 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7431 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7432 if (!vmx
->loaded_vmcs
->vmcs
)
7435 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7436 loaded_vmcs_init(vmx
->loaded_vmcs
);
7441 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7442 vmx
->vcpu
.cpu
= cpu
;
7443 err
= vmx_vcpu_setup(vmx
);
7444 vmx_vcpu_put(&vmx
->vcpu
);
7448 if (vm_need_virtualize_apic_accesses(kvm
)) {
7449 err
= alloc_apic_access_page(kvm
);
7455 if (!kvm
->arch
.ept_identity_map_addr
)
7456 kvm
->arch
.ept_identity_map_addr
=
7457 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7459 if (alloc_identity_pagetable(kvm
) != 0)
7461 if (!init_rmode_identity_map(kvm
))
7465 vmx
->nested
.current_vmptr
= -1ull;
7466 vmx
->nested
.current_vmcs12
= NULL
;
7471 free_loaded_vmcs(vmx
->loaded_vmcs
);
7473 kfree(vmx
->guest_msrs
);
7475 kvm_vcpu_uninit(&vmx
->vcpu
);
7478 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7479 return ERR_PTR(err
);
7482 static void __init
vmx_check_processor_compat(void *rtn
)
7484 struct vmcs_config vmcs_conf
;
7487 if (setup_vmcs_config(&vmcs_conf
) < 0)
7489 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7490 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7491 smp_processor_id());
7496 static int get_ept_level(void)
7498 return VMX_EPT_DEFAULT_GAW
+ 1;
7501 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7505 /* For VT-d and EPT combination
7506 * 1. MMIO: always map as UC
7508 * a. VT-d without snooping control feature: can't guarantee the
7509 * result, try to trust guest.
7510 * b. VT-d with snooping control feature: snooping control feature of
7511 * VT-d engine can guarantee the cache correctness. Just set it
7512 * to WB to keep consistent with host. So the same as item 3.
7513 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7514 * consistent with host MTRR
7517 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7518 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7519 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7520 VMX_EPT_MT_EPTE_SHIFT
;
7522 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7528 static int vmx_get_lpage_level(void)
7530 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7531 return PT_DIRECTORY_LEVEL
;
7533 /* For shadow and EPT supported 1GB page */
7534 return PT_PDPE_LEVEL
;
7537 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7539 struct kvm_cpuid_entry2
*best
;
7540 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7543 vmx
->rdtscp_enabled
= false;
7544 if (vmx_rdtscp_supported()) {
7545 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7546 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7547 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7548 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7549 vmx
->rdtscp_enabled
= true;
7551 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7552 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7558 /* Exposing INVPCID only when PCID is exposed */
7559 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7560 if (vmx_invpcid_supported() &&
7561 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7562 guest_cpuid_has_pcid(vcpu
)) {
7563 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7564 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7565 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7568 if (cpu_has_secondary_exec_ctrls()) {
7569 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7570 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7571 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7575 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7579 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7581 if (func
== 1 && nested
)
7582 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7585 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7586 struct x86_exception
*fault
)
7588 struct vmcs12
*vmcs12
;
7589 nested_vmx_vmexit(vcpu
);
7590 vmcs12
= get_vmcs12(vcpu
);
7592 if (fault
->error_code
& PFERR_RSVD_MASK
)
7593 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7595 vmcs12
->vm_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7596 vmcs12
->exit_qualification
= vcpu
->arch
.exit_qualification
;
7597 vmcs12
->guest_physical_address
= fault
->address
;
7600 /* Callbacks for nested_ept_init_mmu_context: */
7602 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7604 /* return the page table to be shadowed - in our case, EPT12 */
7605 return get_vmcs12(vcpu
)->ept_pointer
;
7608 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7610 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7611 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7613 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7614 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7615 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7617 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7620 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7622 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7625 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7626 struct x86_exception
*fault
)
7628 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7630 WARN_ON(!is_guest_mode(vcpu
));
7632 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7633 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7634 nested_vmx_vmexit(vcpu
);
7636 kvm_inject_page_fault(vcpu
, fault
);
7640 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7641 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7642 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7643 * guest in a way that will both be appropriate to L1's requests, and our
7644 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7645 * function also has additional necessary side-effects, like setting various
7646 * vcpu->arch fields.
7648 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7654 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7655 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7656 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7657 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7658 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7659 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7660 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7661 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7662 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7663 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7664 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7665 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7666 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7667 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7668 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7669 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7670 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7671 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7672 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7673 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7674 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7675 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7676 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7677 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7678 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7679 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7680 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7681 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7682 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7683 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7684 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7685 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7686 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7687 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7688 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7689 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7691 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7692 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7693 vmcs12
->vm_entry_intr_info_field
);
7694 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7695 vmcs12
->vm_entry_exception_error_code
);
7696 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7697 vmcs12
->vm_entry_instruction_len
);
7698 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7699 vmcs12
->guest_interruptibility_info
);
7700 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7701 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7702 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7703 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7704 vmcs12
->guest_pending_dbg_exceptions
);
7705 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7706 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7708 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7710 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
7711 (vmcs_config
.pin_based_exec_ctrl
|
7712 vmcs12
->pin_based_vm_exec_control
));
7714 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7715 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
,
7716 vmcs12
->vmx_preemption_timer_value
);
7719 * Whether page-faults are trapped is determined by a combination of
7720 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7721 * If enable_ept, L0 doesn't care about page faults and we should
7722 * set all of these to L1's desires. However, if !enable_ept, L0 does
7723 * care about (at least some) page faults, and because it is not easy
7724 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7725 * to exit on each and every L2 page fault. This is done by setting
7726 * MASK=MATCH=0 and (see below) EB.PF=1.
7727 * Note that below we don't need special code to set EB.PF beyond the
7728 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7729 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7730 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7732 * A problem with this approach (when !enable_ept) is that L1 may be
7733 * injected with more page faults than it asked for. This could have
7734 * caused problems, but in practice existing hypervisors don't care.
7735 * To fix this, we will need to emulate the PFEC checking (on the L1
7736 * page tables), using walk_addr(), when injecting PFs to L1.
7738 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7739 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7740 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7741 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7743 if (cpu_has_secondary_exec_ctrls()) {
7744 u32 exec_control
= vmx_secondary_exec_control(vmx
);
7745 if (!vmx
->rdtscp_enabled
)
7746 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7747 /* Take the following fields only from vmcs12 */
7748 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7749 if (nested_cpu_has(vmcs12
,
7750 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7751 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7753 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7755 * Translate L1 physical address to host physical
7756 * address for vmcs02. Keep the page pinned, so this
7757 * physical address remains valid. We keep a reference
7758 * to it so we can release it later.
7760 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7761 nested_release_page(vmx
->nested
.apic_access_page
);
7762 vmx
->nested
.apic_access_page
=
7763 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7765 * If translation failed, no matter: This feature asks
7766 * to exit when accessing the given address, and if it
7767 * can never be accessed, this feature won't do
7770 if (!vmx
->nested
.apic_access_page
)
7772 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7774 vmcs_write64(APIC_ACCESS_ADDR
,
7775 page_to_phys(vmx
->nested
.apic_access_page
));
7776 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
7778 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7779 vmcs_write64(APIC_ACCESS_ADDR
,
7780 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
7783 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7788 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7789 * Some constant fields are set here by vmx_set_constant_host_state().
7790 * Other fields are different per CPU, and will be set later when
7791 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7793 vmx_set_constant_host_state(vmx
);
7796 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7797 * entry, but only if the current (host) sp changed from the value
7798 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7799 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7800 * here we just force the write to happen on entry.
7804 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7805 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7806 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7807 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7808 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7810 * Merging of IO and MSR bitmaps not currently supported.
7811 * Rather, exit every time.
7813 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7814 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7815 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7817 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7819 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7820 * bitwise-or of what L1 wants to trap for L2, and what we want to
7821 * trap. Note that CR0.TS also needs updating - we do this later.
7823 update_exception_bitmap(vcpu
);
7824 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7825 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7827 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7828 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7829 * bits are further modified by vmx_set_efer() below.
7831 exit_control
= vmcs_config
.vmexit_ctrl
;
7832 if (vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
)
7833 exit_control
|= VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
;
7834 vm_exit_controls_init(vmx
, exit_control
);
7836 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7837 * emulated by vmx_set_efer(), below.
7839 vm_entry_controls_init(vmx
,
7840 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7841 ~VM_ENTRY_IA32E_MODE
) |
7842 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7844 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7845 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7846 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7847 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7848 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
7851 set_cr4_guest_host_mask(vmx
);
7853 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
7854 vmcs_write64(TSC_OFFSET
,
7855 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
7857 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
7861 * Trivially support vpid by letting L2s share their parent
7862 * L1's vpid. TODO: move to a more elaborate solution, giving
7863 * each L2 its own vpid and exposing the vpid feature to L1.
7865 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
7866 vmx_flush_tlb(vcpu
);
7869 if (nested_cpu_has_ept(vmcs12
)) {
7870 kvm_mmu_unload(vcpu
);
7871 nested_ept_init_mmu_context(vcpu
);
7874 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
7875 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
7876 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
7877 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
7879 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
7880 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
7881 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
7884 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
7885 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
7886 * The CR0_READ_SHADOW is what L2 should have expected to read given
7887 * the specifications by L1; It's not enough to take
7888 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
7889 * have more bits than L1 expected.
7891 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
7892 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
7894 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
7895 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
7897 /* shadow page tables on either EPT or shadow page tables */
7898 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
7899 kvm_mmu_reset_context(vcpu
);
7902 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
7905 * L1 may access the L2's PDPTR, so save them to construct vmcs12
7908 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
7909 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
7910 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
7911 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
7914 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
7915 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
7919 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
7920 * for running an L2 nested guest.
7922 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
7924 struct vmcs12
*vmcs12
;
7925 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7927 struct loaded_vmcs
*vmcs02
;
7930 if (!nested_vmx_check_permission(vcpu
) ||
7931 !nested_vmx_check_vmcs12(vcpu
))
7934 skip_emulated_instruction(vcpu
);
7935 vmcs12
= get_vmcs12(vcpu
);
7937 if (enable_shadow_vmcs
)
7938 copy_shadow_to_vmcs12(vmx
);
7941 * The nested entry process starts with enforcing various prerequisites
7942 * on vmcs12 as required by the Intel SDM, and act appropriately when
7943 * they fail: As the SDM explains, some conditions should cause the
7944 * instruction to fail, while others will cause the instruction to seem
7945 * to succeed, but return an EXIT_REASON_INVALID_STATE.
7946 * To speed up the normal (success) code path, we should avoid checking
7947 * for misconfigurations which will anyway be caught by the processor
7948 * when using the merged vmcs02.
7950 if (vmcs12
->launch_state
== launch
) {
7951 nested_vmx_failValid(vcpu
,
7952 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
7953 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
7957 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
7958 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
7959 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7963 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
7964 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
7965 /*TODO: Also verify bits beyond physical address width are 0*/
7966 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7970 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
7971 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
7972 /*TODO: Also verify bits beyond physical address width are 0*/
7973 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7977 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
7978 vmcs12
->vm_exit_msr_load_count
> 0 ||
7979 vmcs12
->vm_exit_msr_store_count
> 0) {
7980 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
7982 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
7986 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
7987 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
7988 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
7989 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
7990 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
7991 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
7992 !vmx_control_verify(vmcs12
->vm_exit_controls
,
7993 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
7994 !vmx_control_verify(vmcs12
->vm_entry_controls
,
7995 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
7997 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8001 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8002 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8003 nested_vmx_failValid(vcpu
,
8004 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8008 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8009 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8010 nested_vmx_entry_failure(vcpu
, vmcs12
,
8011 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8014 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8015 nested_vmx_entry_failure(vcpu
, vmcs12
,
8016 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8021 * If the load IA32_EFER VM-entry control is 1, the following checks
8022 * are performed on the field for the IA32_EFER MSR:
8023 * - Bits reserved in the IA32_EFER MSR must be 0.
8024 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8025 * the IA-32e mode guest VM-exit control. It must also be identical
8026 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8029 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8030 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8031 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8032 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8033 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8034 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8035 nested_vmx_entry_failure(vcpu
, vmcs12
,
8036 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8042 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8043 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8044 * the values of the LMA and LME bits in the field must each be that of
8045 * the host address-space size VM-exit control.
8047 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8048 ia32e
= (vmcs12
->vm_exit_controls
&
8049 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8050 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8051 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8052 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8053 nested_vmx_entry_failure(vcpu
, vmcs12
,
8054 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8060 * We're finally done with prerequisite checking, and can start with
8064 vmcs02
= nested_get_current_vmcs02(vmx
);
8068 enter_guest_mode(vcpu
);
8070 vmx
->nested
.nested_run_pending
= 1;
8072 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8075 vmx
->loaded_vmcs
= vmcs02
;
8077 vmx_vcpu_load(vcpu
, cpu
);
8081 vmx_segment_cache_clear(vmx
);
8083 vmcs12
->launch_state
= 1;
8085 prepare_vmcs02(vcpu
, vmcs12
);
8087 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8088 return kvm_emulate_halt(vcpu
);
8091 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8092 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8093 * returned as far as L1 is concerned. It will only return (and set
8094 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8100 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8101 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8102 * This function returns the new value we should put in vmcs12.guest_cr0.
8103 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8104 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8105 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8106 * didn't trap the bit, because if L1 did, so would L0).
8107 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8108 * been modified by L2, and L1 knows it. So just leave the old value of
8109 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8110 * isn't relevant, because if L0 traps this bit it can set it to anything.
8111 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8112 * changed these bits, and therefore they need to be updated, but L0
8113 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8114 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8116 static inline unsigned long
8117 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8120 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8121 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8122 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8123 vcpu
->arch
.cr0_guest_owned_bits
));
8126 static inline unsigned long
8127 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8130 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8131 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8132 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8133 vcpu
->arch
.cr4_guest_owned_bits
));
8136 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8137 struct vmcs12
*vmcs12
)
8142 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8143 nr
= vcpu
->arch
.exception
.nr
;
8144 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8146 if (kvm_exception_is_soft(nr
)) {
8147 vmcs12
->vm_exit_instruction_len
=
8148 vcpu
->arch
.event_exit_inst_len
;
8149 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8151 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8153 if (vcpu
->arch
.exception
.has_error_code
) {
8154 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8155 vmcs12
->idt_vectoring_error_code
=
8156 vcpu
->arch
.exception
.error_code
;
8159 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8160 } else if (vcpu
->arch
.nmi_injected
) {
8161 vmcs12
->idt_vectoring_info_field
=
8162 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8163 } else if (vcpu
->arch
.interrupt
.pending
) {
8164 nr
= vcpu
->arch
.interrupt
.nr
;
8165 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8167 if (vcpu
->arch
.interrupt
.soft
) {
8168 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8169 vmcs12
->vm_entry_instruction_len
=
8170 vcpu
->arch
.event_exit_inst_len
;
8172 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8174 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8179 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8180 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8181 * and this function updates it to reflect the changes to the guest state while
8182 * L2 was running (and perhaps made some exits which were handled directly by L0
8183 * without going back to L1), and to reflect the exit reason.
8184 * Note that we do not have to copy here all VMCS fields, just those that
8185 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8186 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8187 * which already writes to vmcs12 directly.
8189 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8191 /* update guest state fields: */
8192 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8193 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8195 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8196 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8197 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8198 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8200 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8201 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8202 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8203 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8204 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8205 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8206 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8207 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8208 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8209 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8210 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8211 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8212 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8213 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8214 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8215 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8216 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8217 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8218 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8219 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8220 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8221 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8222 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8223 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8224 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8225 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8226 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8227 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8228 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8229 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8230 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8231 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8232 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8233 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8234 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8235 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8237 vmcs12
->guest_interruptibility_info
=
8238 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8239 vmcs12
->guest_pending_dbg_exceptions
=
8240 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8242 if ((vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VMX_PREEMPTION_TIMER
) &&
8243 (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
))
8244 vmcs12
->vmx_preemption_timer_value
=
8245 vmcs_read32(VMX_PREEMPTION_TIMER_VALUE
);
8248 * In some cases (usually, nested EPT), L2 is allowed to change its
8249 * own CR3 without exiting. If it has changed it, we must keep it.
8250 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8251 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8253 * Additionally, restore L2's PDPTR to vmcs12.
8256 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8257 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8258 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8259 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8260 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8263 vmcs12
->vm_entry_controls
=
8264 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8265 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8267 /* TODO: These cannot have changed unless we have MSR bitmaps and
8268 * the relevant bit asks not to trap the change */
8269 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8270 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8271 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8272 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8273 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8274 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8275 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8276 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8278 /* update exit information fields: */
8280 vmcs12
->vm_exit_reason
= to_vmx(vcpu
)->exit_reason
;
8281 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8283 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8284 if ((vmcs12
->vm_exit_intr_info
&
8285 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8286 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8287 vmcs12
->vm_exit_intr_error_code
=
8288 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8289 vmcs12
->idt_vectoring_info_field
= 0;
8290 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8291 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8293 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8294 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8295 * instead of reading the real value. */
8296 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8299 * Transfer the event that L0 or L1 may wanted to inject into
8300 * L2 to IDT_VECTORING_INFO_FIELD.
8302 vmcs12_save_pending_event(vcpu
, vmcs12
);
8306 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8307 * preserved above and would only end up incorrectly in L1.
8309 vcpu
->arch
.nmi_injected
= false;
8310 kvm_clear_exception_queue(vcpu
);
8311 kvm_clear_interrupt_queue(vcpu
);
8315 * A part of what we need to when the nested L2 guest exits and we want to
8316 * run its L1 parent, is to reset L1's guest state to the host state specified
8318 * This function is to be called not only on normal nested exit, but also on
8319 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8320 * Failures During or After Loading Guest State").
8321 * This function should be called when the active VMCS is L1's (vmcs01).
8323 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8324 struct vmcs12
*vmcs12
)
8326 struct kvm_segment seg
;
8328 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8329 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8330 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8331 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8333 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8334 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8336 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8337 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8338 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8340 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8341 * actually changed, because it depends on the current state of
8342 * fpu_active (which may have changed).
8343 * Note that vmx_set_cr0 refers to efer set above.
8345 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8347 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8348 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8349 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8351 update_exception_bitmap(vcpu
);
8352 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8353 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8356 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8357 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8359 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8360 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8362 if (nested_cpu_has_ept(vmcs12
))
8363 nested_ept_uninit_mmu_context(vcpu
);
8365 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8366 kvm_mmu_reset_context(vcpu
);
8369 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8373 * Trivially support vpid by letting L2s share their parent
8374 * L1's vpid. TODO: move to a more elaborate solution, giving
8375 * each L2 its own vpid and exposing the vpid feature to L1.
8377 vmx_flush_tlb(vcpu
);
8381 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8382 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8383 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8384 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8385 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8387 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8388 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8389 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8391 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8392 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8393 vmcs12
->host_ia32_perf_global_ctrl
);
8395 /* Set L1 segment info according to Intel SDM
8396 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8397 seg
= (struct kvm_segment
) {
8399 .limit
= 0xFFFFFFFF,
8400 .selector
= vmcs12
->host_cs_selector
,
8406 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8410 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8411 seg
= (struct kvm_segment
) {
8413 .limit
= 0xFFFFFFFF,
8420 seg
.selector
= vmcs12
->host_ds_selector
;
8421 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8422 seg
.selector
= vmcs12
->host_es_selector
;
8423 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8424 seg
.selector
= vmcs12
->host_ss_selector
;
8425 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8426 seg
.selector
= vmcs12
->host_fs_selector
;
8427 seg
.base
= vmcs12
->host_fs_base
;
8428 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8429 seg
.selector
= vmcs12
->host_gs_selector
;
8430 seg
.base
= vmcs12
->host_gs_base
;
8431 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8432 seg
= (struct kvm_segment
) {
8433 .base
= vmcs12
->host_tr_base
,
8435 .selector
= vmcs12
->host_tr_selector
,
8439 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8441 kvm_set_dr(vcpu
, 7, 0x400);
8442 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8446 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8447 * and modify vmcs12 to make it see what it would expect to see there if
8448 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8450 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
8452 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8454 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8456 /* trying to cancel vmlaunch/vmresume is a bug */
8457 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8459 leave_guest_mode(vcpu
);
8460 prepare_vmcs12(vcpu
, vmcs12
);
8463 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8465 vmx_vcpu_load(vcpu
, cpu
);
8469 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8470 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8471 vmx_segment_cache_clear(vmx
);
8473 /* if no vmcs02 cache requested, remove the one we used */
8474 if (VMCS02_POOL_SIZE
== 0)
8475 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8477 load_vmcs12_host_state(vcpu
, vmcs12
);
8479 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8480 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8482 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8485 /* Unpin physical memory we referred to in vmcs02 */
8486 if (vmx
->nested
.apic_access_page
) {
8487 nested_release_page(vmx
->nested
.apic_access_page
);
8488 vmx
->nested
.apic_access_page
= 0;
8492 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8493 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8494 * success or failure flag accordingly.
8496 if (unlikely(vmx
->fail
)) {
8498 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8500 nested_vmx_succeed(vcpu
);
8501 if (enable_shadow_vmcs
)
8502 vmx
->nested
.sync_shadow_vmcs
= true;
8506 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8507 * 23.7 "VM-entry failures during or after loading guest state" (this also
8508 * lists the acceptable exit-reason and exit-qualification parameters).
8509 * It should only be called before L2 actually succeeded to run, and when
8510 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8512 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8513 struct vmcs12
*vmcs12
,
8514 u32 reason
, unsigned long qualification
)
8516 load_vmcs12_host_state(vcpu
, vmcs12
);
8517 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8518 vmcs12
->exit_qualification
= qualification
;
8519 nested_vmx_succeed(vcpu
);
8520 if (enable_shadow_vmcs
)
8521 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8524 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8525 struct x86_instruction_info
*info
,
8526 enum x86_intercept_stage stage
)
8528 return X86EMUL_CONTINUE
;
8531 static struct kvm_x86_ops vmx_x86_ops
= {
8532 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8533 .disabled_by_bios
= vmx_disabled_by_bios
,
8534 .hardware_setup
= hardware_setup
,
8535 .hardware_unsetup
= hardware_unsetup
,
8536 .check_processor_compatibility
= vmx_check_processor_compat
,
8537 .hardware_enable
= hardware_enable
,
8538 .hardware_disable
= hardware_disable
,
8539 .cpu_has_accelerated_tpr
= report_flexpriority
,
8541 .vcpu_create
= vmx_create_vcpu
,
8542 .vcpu_free
= vmx_free_vcpu
,
8543 .vcpu_reset
= vmx_vcpu_reset
,
8545 .prepare_guest_switch
= vmx_save_host_state
,
8546 .vcpu_load
= vmx_vcpu_load
,
8547 .vcpu_put
= vmx_vcpu_put
,
8549 .update_db_bp_intercept
= update_exception_bitmap
,
8550 .get_msr
= vmx_get_msr
,
8551 .set_msr
= vmx_set_msr
,
8552 .get_segment_base
= vmx_get_segment_base
,
8553 .get_segment
= vmx_get_segment
,
8554 .set_segment
= vmx_set_segment
,
8555 .get_cpl
= vmx_get_cpl
,
8556 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8557 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8558 .decache_cr3
= vmx_decache_cr3
,
8559 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8560 .set_cr0
= vmx_set_cr0
,
8561 .set_cr3
= vmx_set_cr3
,
8562 .set_cr4
= vmx_set_cr4
,
8563 .set_efer
= vmx_set_efer
,
8564 .get_idt
= vmx_get_idt
,
8565 .set_idt
= vmx_set_idt
,
8566 .get_gdt
= vmx_get_gdt
,
8567 .set_gdt
= vmx_set_gdt
,
8568 .get_dr6
= vmx_get_dr6
,
8569 .set_dr6
= vmx_set_dr6
,
8570 .set_dr7
= vmx_set_dr7
,
8571 .cache_reg
= vmx_cache_reg
,
8572 .get_rflags
= vmx_get_rflags
,
8573 .set_rflags
= vmx_set_rflags
,
8574 .fpu_activate
= vmx_fpu_activate
,
8575 .fpu_deactivate
= vmx_fpu_deactivate
,
8577 .tlb_flush
= vmx_flush_tlb
,
8579 .run
= vmx_vcpu_run
,
8580 .handle_exit
= vmx_handle_exit
,
8581 .skip_emulated_instruction
= skip_emulated_instruction
,
8582 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8583 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8584 .patch_hypercall
= vmx_patch_hypercall
,
8585 .set_irq
= vmx_inject_irq
,
8586 .set_nmi
= vmx_inject_nmi
,
8587 .queue_exception
= vmx_queue_exception
,
8588 .cancel_injection
= vmx_cancel_injection
,
8589 .interrupt_allowed
= vmx_interrupt_allowed
,
8590 .nmi_allowed
= vmx_nmi_allowed
,
8591 .get_nmi_mask
= vmx_get_nmi_mask
,
8592 .set_nmi_mask
= vmx_set_nmi_mask
,
8593 .enable_nmi_window
= enable_nmi_window
,
8594 .enable_irq_window
= enable_irq_window
,
8595 .update_cr8_intercept
= update_cr8_intercept
,
8596 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8597 .vm_has_apicv
= vmx_vm_has_apicv
,
8598 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8599 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8600 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8601 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8602 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8604 .set_tss_addr
= vmx_set_tss_addr
,
8605 .get_tdp_level
= get_ept_level
,
8606 .get_mt_mask
= vmx_get_mt_mask
,
8608 .get_exit_info
= vmx_get_exit_info
,
8610 .get_lpage_level
= vmx_get_lpage_level
,
8612 .cpuid_update
= vmx_cpuid_update
,
8614 .rdtscp_supported
= vmx_rdtscp_supported
,
8615 .invpcid_supported
= vmx_invpcid_supported
,
8617 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8619 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8621 .set_tsc_khz
= vmx_set_tsc_khz
,
8622 .read_tsc_offset
= vmx_read_tsc_offset
,
8623 .write_tsc_offset
= vmx_write_tsc_offset
,
8624 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8625 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8626 .read_l1_tsc
= vmx_read_l1_tsc
,
8628 .set_tdp_cr3
= vmx_set_cr3
,
8630 .check_intercept
= vmx_check_intercept
,
8631 .handle_external_intr
= vmx_handle_external_intr
,
8634 static int __init
vmx_init(void)
8638 rdmsrl_safe(MSR_EFER
, &host_efer
);
8640 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8641 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8643 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8644 if (!vmx_io_bitmap_a
)
8649 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8650 if (!vmx_io_bitmap_b
)
8653 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8654 if (!vmx_msr_bitmap_legacy
)
8657 vmx_msr_bitmap_legacy_x2apic
=
8658 (unsigned long *)__get_free_page(GFP_KERNEL
);
8659 if (!vmx_msr_bitmap_legacy_x2apic
)
8662 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8663 if (!vmx_msr_bitmap_longmode
)
8666 vmx_msr_bitmap_longmode_x2apic
=
8667 (unsigned long *)__get_free_page(GFP_KERNEL
);
8668 if (!vmx_msr_bitmap_longmode_x2apic
)
8670 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8671 if (!vmx_vmread_bitmap
)
8674 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8675 if (!vmx_vmwrite_bitmap
)
8678 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8679 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8680 /* shadowed read/write fields */
8681 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
8682 clear_bit(shadow_read_write_fields
[i
], vmx_vmwrite_bitmap
);
8683 clear_bit(shadow_read_write_fields
[i
], vmx_vmread_bitmap
);
8685 /* shadowed read only fields */
8686 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
8687 clear_bit(shadow_read_only_fields
[i
], vmx_vmread_bitmap
);
8690 * Allow direct access to the PC debug port (it is often used for I/O
8691 * delays, but the vmexits simply slow things down).
8693 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8694 clear_bit(0x80, vmx_io_bitmap_a
);
8696 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8698 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8699 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8701 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8703 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8704 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8709 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8710 crash_vmclear_local_loaded_vmcss
);
8713 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8714 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8715 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8716 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8717 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8718 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8719 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8720 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8721 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8722 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8725 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8726 vmx_disable_intercept_msr_read_x2apic(msr
);
8728 /* According SDM, in x2apic mode, the whole id reg is used.
8729 * But in KVM, it only use the highest eight bits. Need to
8731 vmx_enable_intercept_msr_read_x2apic(0x802);
8733 vmx_enable_intercept_msr_read_x2apic(0x839);
8735 vmx_disable_intercept_msr_write_x2apic(0x808);
8737 vmx_disable_intercept_msr_write_x2apic(0x80b);
8739 vmx_disable_intercept_msr_write_x2apic(0x83f);
8743 kvm_mmu_set_mask_ptes(0ull,
8744 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8745 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8746 0ull, VMX_EPT_EXECUTABLE_MASK
);
8747 ept_set_mmio_spte_mask();
8755 free_page((unsigned long)vmx_vmwrite_bitmap
);
8757 free_page((unsigned long)vmx_vmread_bitmap
);
8759 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8761 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8763 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8765 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8767 free_page((unsigned long)vmx_io_bitmap_b
);
8769 free_page((unsigned long)vmx_io_bitmap_a
);
8773 static void __exit
vmx_exit(void)
8775 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
8776 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
8777 free_page((unsigned long)vmx_msr_bitmap_legacy
);
8778 free_page((unsigned long)vmx_msr_bitmap_longmode
);
8779 free_page((unsigned long)vmx_io_bitmap_b
);
8780 free_page((unsigned long)vmx_io_bitmap_a
);
8781 free_page((unsigned long)vmx_vmwrite_bitmap
);
8782 free_page((unsigned long)vmx_vmread_bitmap
);
8785 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
8792 module_init(vmx_init
)
8793 module_exit(vmx_exit
)