2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
57 #define __ex(x) __kvm_handle_fault_on_reboot(x)
58 #define __ex_clear(x, reg) \
59 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
61 MODULE_AUTHOR("Qumranet");
62 MODULE_LICENSE("GPL");
64 static const struct x86_cpu_id vmx_cpu_id
[] = {
65 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
68 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
70 static bool __read_mostly enable_vpid
= 1;
71 module_param_named(vpid
, enable_vpid
, bool, 0444);
73 static bool __read_mostly flexpriority_enabled
= 1;
74 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
76 static bool __read_mostly enable_ept
= 1;
77 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
79 static bool __read_mostly enable_unrestricted_guest
= 1;
80 module_param_named(unrestricted_guest
,
81 enable_unrestricted_guest
, bool, S_IRUGO
);
83 static bool __read_mostly enable_ept_ad_bits
= 1;
84 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
86 static bool __read_mostly emulate_invalid_guest_state
= true;
87 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
113 static int __read_mostly cpu_preemption_timer_multi
;
114 static bool __read_mostly enable_preemption_timer
= 1;
116 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
119 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
120 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
121 #define KVM_VM_CR0_ALWAYS_ON \
122 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
123 #define KVM_CR4_GUEST_OWNED_BITS \
124 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
125 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
127 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
128 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
130 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
132 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
135 * Hyper-V requires all of these, so mark them as supported even though
136 * they are just treated the same as all-context.
138 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
139 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
140 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
141 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
145 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
146 * ple_gap: upper bound on the amount of time between two successive
147 * executions of PAUSE in a loop. Also indicate if ple enabled.
148 * According to test, this time is usually smaller than 128 cycles.
149 * ple_window: upper bound on the amount of time a guest is allowed to execute
150 * in a PAUSE loop. Tests indicate that most spinlocks are held for
151 * less than 2^12 cycles
152 * Time is measured based on a counter that runs at the same rate as the TSC,
153 * refer SDM volume 3b section 21.6.13 & 22.1.3.
155 #define KVM_VMX_DEFAULT_PLE_GAP 128
156 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
157 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
160 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
162 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
163 module_param(ple_gap
, int, S_IRUGO
);
165 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
166 module_param(ple_window
, int, S_IRUGO
);
168 /* Default doubles per-vcpu window every exit. */
169 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
170 module_param(ple_window_grow
, int, S_IRUGO
);
172 /* Default resets per-vcpu window every exit to ple_window. */
173 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
174 module_param(ple_window_shrink
, int, S_IRUGO
);
176 /* Default is to compute the maximum so we can never overflow. */
177 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
178 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 module_param(ple_window_max
, int, S_IRUGO
);
181 extern const ulong vmx_return
;
183 #define NR_AUTOLOAD_MSRS 8
184 #define VMCS02_POOL_SIZE 1
193 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
194 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
195 * loaded on this CPU (so we can clear them if the CPU goes down).
199 struct vmcs
*shadow_vmcs
;
202 bool nmi_known_unmasked
;
203 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
204 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
205 struct list_head loaded_vmcss_on_cpu_link
;
208 struct shared_msr_entry
{
215 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
216 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
217 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
218 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
219 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
220 * More than one of these structures may exist, if L1 runs multiple L2 guests.
221 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
222 * underlying hardware which will be used to run L2.
223 * This structure is packed to ensure that its layout is identical across
224 * machines (necessary for live migration).
225 * If there are changes in this struct, VMCS12_REVISION must be changed.
227 typedef u64 natural_width
;
228 struct __packed vmcs12
{
229 /* According to the Intel spec, a VMCS region must start with the
230 * following two fields. Then follow implementation-specific data.
235 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
236 u32 padding
[7]; /* room for future expansion */
241 u64 vm_exit_msr_store_addr
;
242 u64 vm_exit_msr_load_addr
;
243 u64 vm_entry_msr_load_addr
;
245 u64 virtual_apic_page_addr
;
246 u64 apic_access_addr
;
247 u64 posted_intr_desc_addr
;
248 u64 vm_function_control
;
250 u64 eoi_exit_bitmap0
;
251 u64 eoi_exit_bitmap1
;
252 u64 eoi_exit_bitmap2
;
253 u64 eoi_exit_bitmap3
;
254 u64 eptp_list_address
;
256 u64 guest_physical_address
;
257 u64 vmcs_link_pointer
;
259 u64 guest_ia32_debugctl
;
262 u64 guest_ia32_perf_global_ctrl
;
270 u64 host_ia32_perf_global_ctrl
;
271 u64 padding64
[8]; /* room for future expansion */
273 * To allow migration of L1 (complete with its L2 guests) between
274 * machines of different natural widths (32 or 64 bit), we cannot have
275 * unsigned long fields with no explict size. We use u64 (aliased
276 * natural_width) instead. Luckily, x86 is little-endian.
278 natural_width cr0_guest_host_mask
;
279 natural_width cr4_guest_host_mask
;
280 natural_width cr0_read_shadow
;
281 natural_width cr4_read_shadow
;
282 natural_width cr3_target_value0
;
283 natural_width cr3_target_value1
;
284 natural_width cr3_target_value2
;
285 natural_width cr3_target_value3
;
286 natural_width exit_qualification
;
287 natural_width guest_linear_address
;
288 natural_width guest_cr0
;
289 natural_width guest_cr3
;
290 natural_width guest_cr4
;
291 natural_width guest_es_base
;
292 natural_width guest_cs_base
;
293 natural_width guest_ss_base
;
294 natural_width guest_ds_base
;
295 natural_width guest_fs_base
;
296 natural_width guest_gs_base
;
297 natural_width guest_ldtr_base
;
298 natural_width guest_tr_base
;
299 natural_width guest_gdtr_base
;
300 natural_width guest_idtr_base
;
301 natural_width guest_dr7
;
302 natural_width guest_rsp
;
303 natural_width guest_rip
;
304 natural_width guest_rflags
;
305 natural_width guest_pending_dbg_exceptions
;
306 natural_width guest_sysenter_esp
;
307 natural_width guest_sysenter_eip
;
308 natural_width host_cr0
;
309 natural_width host_cr3
;
310 natural_width host_cr4
;
311 natural_width host_fs_base
;
312 natural_width host_gs_base
;
313 natural_width host_tr_base
;
314 natural_width host_gdtr_base
;
315 natural_width host_idtr_base
;
316 natural_width host_ia32_sysenter_esp
;
317 natural_width host_ia32_sysenter_eip
;
318 natural_width host_rsp
;
319 natural_width host_rip
;
320 natural_width paddingl
[8]; /* room for future expansion */
321 u32 pin_based_vm_exec_control
;
322 u32 cpu_based_vm_exec_control
;
323 u32 exception_bitmap
;
324 u32 page_fault_error_code_mask
;
325 u32 page_fault_error_code_match
;
326 u32 cr3_target_count
;
327 u32 vm_exit_controls
;
328 u32 vm_exit_msr_store_count
;
329 u32 vm_exit_msr_load_count
;
330 u32 vm_entry_controls
;
331 u32 vm_entry_msr_load_count
;
332 u32 vm_entry_intr_info_field
;
333 u32 vm_entry_exception_error_code
;
334 u32 vm_entry_instruction_len
;
336 u32 secondary_vm_exec_control
;
337 u32 vm_instruction_error
;
339 u32 vm_exit_intr_info
;
340 u32 vm_exit_intr_error_code
;
341 u32 idt_vectoring_info_field
;
342 u32 idt_vectoring_error_code
;
343 u32 vm_exit_instruction_len
;
344 u32 vmx_instruction_info
;
351 u32 guest_ldtr_limit
;
353 u32 guest_gdtr_limit
;
354 u32 guest_idtr_limit
;
355 u32 guest_es_ar_bytes
;
356 u32 guest_cs_ar_bytes
;
357 u32 guest_ss_ar_bytes
;
358 u32 guest_ds_ar_bytes
;
359 u32 guest_fs_ar_bytes
;
360 u32 guest_gs_ar_bytes
;
361 u32 guest_ldtr_ar_bytes
;
362 u32 guest_tr_ar_bytes
;
363 u32 guest_interruptibility_info
;
364 u32 guest_activity_state
;
365 u32 guest_sysenter_cs
;
366 u32 host_ia32_sysenter_cs
;
367 u32 vmx_preemption_timer_value
;
368 u32 padding32
[7]; /* room for future expansion */
369 u16 virtual_processor_id
;
371 u16 guest_es_selector
;
372 u16 guest_cs_selector
;
373 u16 guest_ss_selector
;
374 u16 guest_ds_selector
;
375 u16 guest_fs_selector
;
376 u16 guest_gs_selector
;
377 u16 guest_ldtr_selector
;
378 u16 guest_tr_selector
;
379 u16 guest_intr_status
;
381 u16 host_es_selector
;
382 u16 host_cs_selector
;
383 u16 host_ss_selector
;
384 u16 host_ds_selector
;
385 u16 host_fs_selector
;
386 u16 host_gs_selector
;
387 u16 host_tr_selector
;
391 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
392 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
393 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
395 #define VMCS12_REVISION 0x11e57ed0
398 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
399 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
400 * current implementation, 4K are reserved to avoid future complications.
402 #define VMCS12_SIZE 0x1000
404 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
406 struct list_head list
;
408 struct loaded_vmcs vmcs02
;
412 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
413 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
416 /* Has the level1 guest done vmxon? */
421 /* The guest-physical address of the current VMCS L1 keeps for L2 */
424 * Cache of the guest's VMCS, existing outside of guest memory.
425 * Loaded from guest memory during VMPTRLD. Flushed to guest
426 * memory during VMCLEAR and VMPTRLD.
428 struct vmcs12
*cached_vmcs12
;
430 * Indicates if the shadow vmcs must be updated with the
431 * data hold by vmcs12
433 bool sync_shadow_vmcs
;
435 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
436 struct list_head vmcs02_pool
;
438 bool change_vmcs01_virtual_x2apic_mode
;
439 /* L2 must run next, and mustn't decide to exit to L1. */
440 bool nested_run_pending
;
442 * Guest pages referred to in vmcs02 with host-physical pointers, so
443 * we must keep them pinned while L2 runs.
445 struct page
*apic_access_page
;
446 struct page
*virtual_apic_page
;
447 struct page
*pi_desc_page
;
448 struct pi_desc
*pi_desc
;
452 unsigned long *msr_bitmap
;
454 struct hrtimer preemption_timer
;
455 bool preemption_timer_expired
;
457 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
464 * We only store the "true" versions of the VMX capability MSRs. We
465 * generate the "non-true" versions by setting the must-be-1 bits
466 * according to the SDM.
468 u32 nested_vmx_procbased_ctls_low
;
469 u32 nested_vmx_procbased_ctls_high
;
470 u32 nested_vmx_secondary_ctls_low
;
471 u32 nested_vmx_secondary_ctls_high
;
472 u32 nested_vmx_pinbased_ctls_low
;
473 u32 nested_vmx_pinbased_ctls_high
;
474 u32 nested_vmx_exit_ctls_low
;
475 u32 nested_vmx_exit_ctls_high
;
476 u32 nested_vmx_entry_ctls_low
;
477 u32 nested_vmx_entry_ctls_high
;
478 u32 nested_vmx_misc_low
;
479 u32 nested_vmx_misc_high
;
480 u32 nested_vmx_ept_caps
;
481 u32 nested_vmx_vpid_caps
;
482 u64 nested_vmx_basic
;
483 u64 nested_vmx_cr0_fixed0
;
484 u64 nested_vmx_cr0_fixed1
;
485 u64 nested_vmx_cr4_fixed0
;
486 u64 nested_vmx_cr4_fixed1
;
487 u64 nested_vmx_vmcs_enum
;
488 u64 nested_vmx_vmfunc_controls
;
490 /* SMM related state */
492 /* in VMX operation on SMM entry? */
494 /* in guest mode on SMM entry? */
499 #define POSTED_INTR_ON 0
500 #define POSTED_INTR_SN 1
502 /* Posted-Interrupt Descriptor */
504 u32 pir
[8]; /* Posted interrupt requested */
507 /* bit 256 - Outstanding Notification */
509 /* bit 257 - Suppress Notification */
511 /* bit 271:258 - Reserved */
513 /* bit 279:272 - Notification Vector */
515 /* bit 287:280 - Reserved */
517 /* bit 319:288 - Notification Destination */
525 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
527 return test_and_set_bit(POSTED_INTR_ON
,
528 (unsigned long *)&pi_desc
->control
);
531 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
533 return test_and_clear_bit(POSTED_INTR_ON
,
534 (unsigned long *)&pi_desc
->control
);
537 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
539 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
542 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
544 return clear_bit(POSTED_INTR_SN
,
545 (unsigned long *)&pi_desc
->control
);
548 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
550 return set_bit(POSTED_INTR_SN
,
551 (unsigned long *)&pi_desc
->control
);
554 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
556 clear_bit(POSTED_INTR_ON
,
557 (unsigned long *)&pi_desc
->control
);
560 static inline int pi_test_on(struct pi_desc
*pi_desc
)
562 return test_bit(POSTED_INTR_ON
,
563 (unsigned long *)&pi_desc
->control
);
566 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
568 return test_bit(POSTED_INTR_SN
,
569 (unsigned long *)&pi_desc
->control
);
573 struct kvm_vcpu vcpu
;
574 unsigned long host_rsp
;
577 u32 idt_vectoring_info
;
579 struct shared_msr_entry
*guest_msrs
;
582 unsigned long host_idt_base
;
584 u64 msr_host_kernel_gs_base
;
585 u64 msr_guest_kernel_gs_base
;
587 u32 vm_entry_controls_shadow
;
588 u32 vm_exit_controls_shadow
;
589 u32 secondary_exec_control
;
592 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
593 * non-nested (L1) guest, it always points to vmcs01. For a nested
594 * guest (L2), it points to a different VMCS.
596 struct loaded_vmcs vmcs01
;
597 struct loaded_vmcs
*loaded_vmcs
;
598 bool __launched
; /* temporary, used in vmx_vcpu_run */
599 struct msr_autoload
{
601 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
602 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
606 u16 fs_sel
, gs_sel
, ldt_sel
;
610 int gs_ldt_reload_needed
;
611 int fs_reload_needed
;
612 u64 msr_host_bndcfgs
;
617 struct kvm_segment segs
[8];
620 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
621 struct kvm_save_segment
{
629 bool emulation_required
;
633 /* Posted interrupt descriptor */
634 struct pi_desc pi_desc
;
636 /* Support for a guest hypervisor (nested VMX) */
637 struct nested_vmx nested
;
639 /* Dynamic PLE window. */
641 bool ple_window_dirty
;
643 /* Support for PML */
644 #define PML_ENTITY_NUM 512
647 /* apic deadline value in host tsc */
650 u64 current_tsc_ratio
;
655 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
656 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
657 * in msr_ia32_feature_control_valid_bits.
659 u64 msr_ia32_feature_control
;
660 u64 msr_ia32_feature_control_valid_bits
;
663 enum segment_cache_field
{
672 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
674 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
677 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
679 return &(to_vmx(vcpu
)->pi_desc
);
682 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
683 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
684 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
685 [number##_HIGH] = VMCS12_OFFSET(name)+4
688 static unsigned long shadow_read_only_fields
[] = {
690 * We do NOT shadow fields that are modified when L0
691 * traps and emulates any vmx instruction (e.g. VMPTRLD,
692 * VMXON...) executed by L1.
693 * For example, VM_INSTRUCTION_ERROR is read
694 * by L1 if a vmx instruction fails (part of the error path).
695 * Note the code assumes this logic. If for some reason
696 * we start shadowing these fields then we need to
697 * force a shadow sync when L0 emulates vmx instructions
698 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
699 * by nested_vmx_failValid)
703 VM_EXIT_INSTRUCTION_LEN
,
704 IDT_VECTORING_INFO_FIELD
,
705 IDT_VECTORING_ERROR_CODE
,
706 VM_EXIT_INTR_ERROR_CODE
,
708 GUEST_LINEAR_ADDRESS
,
709 GUEST_PHYSICAL_ADDRESS
711 static int max_shadow_read_only_fields
=
712 ARRAY_SIZE(shadow_read_only_fields
);
714 static unsigned long shadow_read_write_fields
[] = {
721 GUEST_INTERRUPTIBILITY_INFO
,
734 CPU_BASED_VM_EXEC_CONTROL
,
735 VM_ENTRY_EXCEPTION_ERROR_CODE
,
736 VM_ENTRY_INTR_INFO_FIELD
,
737 VM_ENTRY_INSTRUCTION_LEN
,
738 VM_ENTRY_EXCEPTION_ERROR_CODE
,
744 static int max_shadow_read_write_fields
=
745 ARRAY_SIZE(shadow_read_write_fields
);
747 static const unsigned short vmcs_field_to_offset_table
[] = {
748 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
749 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
750 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
751 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
752 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
753 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
754 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
755 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
756 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
757 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
758 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
759 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
760 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
761 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
762 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
763 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
764 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
765 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
766 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
767 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
768 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
769 FIELD64(MSR_BITMAP
, msr_bitmap
),
770 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
771 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
772 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
773 FIELD64(TSC_OFFSET
, tsc_offset
),
774 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
775 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
776 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
777 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
778 FIELD64(EPT_POINTER
, ept_pointer
),
779 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
780 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
781 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
782 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
783 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
784 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
785 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
786 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
787 FIELD64(PML_ADDRESS
, pml_address
),
788 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
789 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
790 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
791 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
792 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
793 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
794 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
795 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
796 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
797 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
798 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
799 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
800 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
801 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
802 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
803 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
804 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
805 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
806 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
807 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
808 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
809 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
810 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
811 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
812 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
813 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
814 FIELD(TPR_THRESHOLD
, tpr_threshold
),
815 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
816 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
817 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
818 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
819 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
820 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
821 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
822 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
823 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
824 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
825 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
826 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
827 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
828 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
829 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
830 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
831 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
832 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
833 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
834 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
835 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
836 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
837 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
838 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
839 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
840 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
841 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
842 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
843 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
844 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
845 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
846 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
847 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
848 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
849 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
850 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
851 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
852 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
853 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
854 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
855 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
856 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
857 FIELD(GUEST_CR0
, guest_cr0
),
858 FIELD(GUEST_CR3
, guest_cr3
),
859 FIELD(GUEST_CR4
, guest_cr4
),
860 FIELD(GUEST_ES_BASE
, guest_es_base
),
861 FIELD(GUEST_CS_BASE
, guest_cs_base
),
862 FIELD(GUEST_SS_BASE
, guest_ss_base
),
863 FIELD(GUEST_DS_BASE
, guest_ds_base
),
864 FIELD(GUEST_FS_BASE
, guest_fs_base
),
865 FIELD(GUEST_GS_BASE
, guest_gs_base
),
866 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
867 FIELD(GUEST_TR_BASE
, guest_tr_base
),
868 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
869 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
870 FIELD(GUEST_DR7
, guest_dr7
),
871 FIELD(GUEST_RSP
, guest_rsp
),
872 FIELD(GUEST_RIP
, guest_rip
),
873 FIELD(GUEST_RFLAGS
, guest_rflags
),
874 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
875 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
876 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
877 FIELD(HOST_CR0
, host_cr0
),
878 FIELD(HOST_CR3
, host_cr3
),
879 FIELD(HOST_CR4
, host_cr4
),
880 FIELD(HOST_FS_BASE
, host_fs_base
),
881 FIELD(HOST_GS_BASE
, host_gs_base
),
882 FIELD(HOST_TR_BASE
, host_tr_base
),
883 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
884 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
885 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
886 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
887 FIELD(HOST_RSP
, host_rsp
),
888 FIELD(HOST_RIP
, host_rip
),
891 static inline short vmcs_field_to_offset(unsigned long field
)
893 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
895 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
896 vmcs_field_to_offset_table
[field
] == 0)
899 return vmcs_field_to_offset_table
[field
];
902 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
904 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
907 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
908 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
909 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
910 static bool vmx_xsaves_supported(void);
911 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
912 struct kvm_segment
*var
, int seg
);
913 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
914 struct kvm_segment
*var
, int seg
);
915 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
916 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
917 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
918 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
919 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
920 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
923 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
924 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
926 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
927 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
929 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
932 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
933 * can find which vCPU should be waken up.
935 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
936 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
941 VMX_MSR_BITMAP_LEGACY
,
942 VMX_MSR_BITMAP_LONGMODE
,
943 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
944 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
945 VMX_MSR_BITMAP_LEGACY_X2APIC
,
946 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
952 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
954 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
955 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
956 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
957 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
958 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
959 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
960 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
961 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
962 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
963 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
965 static bool cpu_has_load_ia32_efer
;
966 static bool cpu_has_load_perf_global_ctrl
;
968 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
969 static DEFINE_SPINLOCK(vmx_vpid_lock
);
971 static struct vmcs_config
{
976 u32 pin_based_exec_ctrl
;
977 u32 cpu_based_exec_ctrl
;
978 u32 cpu_based_2nd_exec_ctrl
;
983 static struct vmx_capability
{
988 #define VMX_SEGMENT_FIELD(seg) \
989 [VCPU_SREG_##seg] = { \
990 .selector = GUEST_##seg##_SELECTOR, \
991 .base = GUEST_##seg##_BASE, \
992 .limit = GUEST_##seg##_LIMIT, \
993 .ar_bytes = GUEST_##seg##_AR_BYTES, \
996 static const struct kvm_vmx_segment_field
{
1001 } kvm_vmx_segment_fields
[] = {
1002 VMX_SEGMENT_FIELD(CS
),
1003 VMX_SEGMENT_FIELD(DS
),
1004 VMX_SEGMENT_FIELD(ES
),
1005 VMX_SEGMENT_FIELD(FS
),
1006 VMX_SEGMENT_FIELD(GS
),
1007 VMX_SEGMENT_FIELD(SS
),
1008 VMX_SEGMENT_FIELD(TR
),
1009 VMX_SEGMENT_FIELD(LDTR
),
1012 static u64 host_efer
;
1014 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1017 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1018 * away by decrementing the array size.
1020 static const u32 vmx_msr_index
[] = {
1021 #ifdef CONFIG_X86_64
1022 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1024 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1027 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1029 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1030 INTR_INFO_VALID_MASK
)) ==
1031 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1034 static inline bool is_debug(u32 intr_info
)
1036 return is_exception_n(intr_info
, DB_VECTOR
);
1039 static inline bool is_breakpoint(u32 intr_info
)
1041 return is_exception_n(intr_info
, BP_VECTOR
);
1044 static inline bool is_page_fault(u32 intr_info
)
1046 return is_exception_n(intr_info
, PF_VECTOR
);
1049 static inline bool is_no_device(u32 intr_info
)
1051 return is_exception_n(intr_info
, NM_VECTOR
);
1054 static inline bool is_invalid_opcode(u32 intr_info
)
1056 return is_exception_n(intr_info
, UD_VECTOR
);
1059 static inline bool is_external_interrupt(u32 intr_info
)
1061 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1062 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1065 static inline bool is_machine_check(u32 intr_info
)
1067 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1068 INTR_INFO_VALID_MASK
)) ==
1069 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1072 static inline bool cpu_has_vmx_msr_bitmap(void)
1074 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1077 static inline bool cpu_has_vmx_tpr_shadow(void)
1079 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1082 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1084 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1087 static inline bool cpu_has_secondary_exec_ctrls(void)
1089 return vmcs_config
.cpu_based_exec_ctrl
&
1090 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1093 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1095 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1096 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1099 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1101 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1102 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1105 static inline bool cpu_has_vmx_apic_register_virt(void)
1107 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1108 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1111 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1113 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1114 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1118 * Comment's format: document - errata name - stepping - processor name.
1120 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1122 static u32 vmx_preemption_cpu_tfms
[] = {
1123 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1125 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1126 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1127 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1129 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1131 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1132 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1134 * 320767.pdf - AAP86 - B1 -
1135 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1138 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1140 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1142 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1144 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1145 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1146 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1150 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1152 u32 eax
= cpuid_eax(0x00000001), i
;
1154 /* Clear the reserved bits */
1155 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1156 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1157 if (eax
== vmx_preemption_cpu_tfms
[i
])
1163 static inline bool cpu_has_vmx_preemption_timer(void)
1165 return vmcs_config
.pin_based_exec_ctrl
&
1166 PIN_BASED_VMX_PREEMPTION_TIMER
;
1169 static inline bool cpu_has_vmx_posted_intr(void)
1171 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1172 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1175 static inline bool cpu_has_vmx_apicv(void)
1177 return cpu_has_vmx_apic_register_virt() &&
1178 cpu_has_vmx_virtual_intr_delivery() &&
1179 cpu_has_vmx_posted_intr();
1182 static inline bool cpu_has_vmx_flexpriority(void)
1184 return cpu_has_vmx_tpr_shadow() &&
1185 cpu_has_vmx_virtualize_apic_accesses();
1188 static inline bool cpu_has_vmx_ept_execute_only(void)
1190 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1193 static inline bool cpu_has_vmx_ept_2m_page(void)
1195 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1198 static inline bool cpu_has_vmx_ept_1g_page(void)
1200 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1203 static inline bool cpu_has_vmx_ept_4levels(void)
1205 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1208 static inline bool cpu_has_vmx_ept_mt_wb(void)
1210 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1213 static inline bool cpu_has_vmx_ept_5levels(void)
1215 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1218 static inline bool cpu_has_vmx_ept_ad_bits(void)
1220 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1223 static inline bool cpu_has_vmx_invept_context(void)
1225 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1228 static inline bool cpu_has_vmx_invept_global(void)
1230 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1233 static inline bool cpu_has_vmx_invvpid_single(void)
1235 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1238 static inline bool cpu_has_vmx_invvpid_global(void)
1240 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1243 static inline bool cpu_has_vmx_invvpid(void)
1245 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1248 static inline bool cpu_has_vmx_ept(void)
1250 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1251 SECONDARY_EXEC_ENABLE_EPT
;
1254 static inline bool cpu_has_vmx_unrestricted_guest(void)
1256 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1257 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1260 static inline bool cpu_has_vmx_ple(void)
1262 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1263 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1266 static inline bool cpu_has_vmx_basic_inout(void)
1268 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1271 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1273 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1276 static inline bool cpu_has_vmx_vpid(void)
1278 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1279 SECONDARY_EXEC_ENABLE_VPID
;
1282 static inline bool cpu_has_vmx_rdtscp(void)
1284 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1285 SECONDARY_EXEC_RDTSCP
;
1288 static inline bool cpu_has_vmx_invpcid(void)
1290 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1291 SECONDARY_EXEC_ENABLE_INVPCID
;
1294 static inline bool cpu_has_vmx_wbinvd_exit(void)
1296 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1297 SECONDARY_EXEC_WBINVD_EXITING
;
1300 static inline bool cpu_has_vmx_shadow_vmcs(void)
1303 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1304 /* check if the cpu supports writing r/o exit information fields */
1305 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1308 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1309 SECONDARY_EXEC_SHADOW_VMCS
;
1312 static inline bool cpu_has_vmx_pml(void)
1314 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1317 static inline bool cpu_has_vmx_tsc_scaling(void)
1319 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1320 SECONDARY_EXEC_TSC_SCALING
;
1323 static inline bool cpu_has_vmx_vmfunc(void)
1325 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1326 SECONDARY_EXEC_ENABLE_VMFUNC
;
1329 static inline bool report_flexpriority(void)
1331 return flexpriority_enabled
;
1334 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1336 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1339 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1341 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1344 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1346 return (vmcs12
->cpu_based_vm_exec_control
&
1347 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1348 (vmcs12
->secondary_vm_exec_control
& bit
);
1351 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1353 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1356 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1358 return vmcs12
->pin_based_vm_exec_control
&
1359 PIN_BASED_VMX_PREEMPTION_TIMER
;
1362 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1364 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1367 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1369 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1372 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1374 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1377 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1379 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1382 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1384 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1387 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1389 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1392 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1394 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1397 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1399 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1402 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1404 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1407 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1409 return nested_cpu_has_vmfunc(vmcs12
) &&
1410 (vmcs12
->vm_function_control
&
1411 VMX_VMFUNC_EPTP_SWITCHING
);
1414 static inline bool is_nmi(u32 intr_info
)
1416 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1417 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1420 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1422 unsigned long exit_qualification
);
1423 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1424 struct vmcs12
*vmcs12
,
1425 u32 reason
, unsigned long qualification
);
1427 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1431 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1432 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1437 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1443 } operand
= { vpid
, 0, gva
};
1445 asm volatile (__ex(ASM_VMX_INVVPID
)
1446 /* CF==1 or ZF==1 --> rc = -1 */
1447 "; ja 1f ; ud2 ; 1:"
1448 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1451 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1455 } operand
= {eptp
, gpa
};
1457 asm volatile (__ex(ASM_VMX_INVEPT
)
1458 /* CF==1 or ZF==1 --> rc = -1 */
1459 "; ja 1f ; ud2 ; 1:\n"
1460 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1463 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1467 i
= __find_msr_index(vmx
, msr
);
1469 return &vmx
->guest_msrs
[i
];
1473 static void vmcs_clear(struct vmcs
*vmcs
)
1475 u64 phys_addr
= __pa(vmcs
);
1478 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1479 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1482 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1486 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1488 vmcs_clear(loaded_vmcs
->vmcs
);
1489 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1490 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1491 loaded_vmcs
->cpu
= -1;
1492 loaded_vmcs
->launched
= 0;
1495 static void vmcs_load(struct vmcs
*vmcs
)
1497 u64 phys_addr
= __pa(vmcs
);
1500 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1501 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1504 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1508 #ifdef CONFIG_KEXEC_CORE
1510 * This bitmap is used to indicate whether the vmclear
1511 * operation is enabled on all cpus. All disabled by
1514 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1516 static inline void crash_enable_local_vmclear(int cpu
)
1518 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1521 static inline void crash_disable_local_vmclear(int cpu
)
1523 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1526 static inline int crash_local_vmclear_enabled(int cpu
)
1528 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1531 static void crash_vmclear_local_loaded_vmcss(void)
1533 int cpu
= raw_smp_processor_id();
1534 struct loaded_vmcs
*v
;
1536 if (!crash_local_vmclear_enabled(cpu
))
1539 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1540 loaded_vmcss_on_cpu_link
)
1541 vmcs_clear(v
->vmcs
);
1544 static inline void crash_enable_local_vmclear(int cpu
) { }
1545 static inline void crash_disable_local_vmclear(int cpu
) { }
1546 #endif /* CONFIG_KEXEC_CORE */
1548 static void __loaded_vmcs_clear(void *arg
)
1550 struct loaded_vmcs
*loaded_vmcs
= arg
;
1551 int cpu
= raw_smp_processor_id();
1553 if (loaded_vmcs
->cpu
!= cpu
)
1554 return; /* vcpu migration can race with cpu offline */
1555 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1556 per_cpu(current_vmcs
, cpu
) = NULL
;
1557 crash_disable_local_vmclear(cpu
);
1558 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1561 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1562 * is before setting loaded_vmcs->vcpu to -1 which is done in
1563 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1564 * then adds the vmcs into percpu list before it is deleted.
1568 loaded_vmcs_init(loaded_vmcs
);
1569 crash_enable_local_vmclear(cpu
);
1572 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1574 int cpu
= loaded_vmcs
->cpu
;
1577 smp_call_function_single(cpu
,
1578 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1581 static inline void vpid_sync_vcpu_single(int vpid
)
1586 if (cpu_has_vmx_invvpid_single())
1587 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1590 static inline void vpid_sync_vcpu_global(void)
1592 if (cpu_has_vmx_invvpid_global())
1593 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1596 static inline void vpid_sync_context(int vpid
)
1598 if (cpu_has_vmx_invvpid_single())
1599 vpid_sync_vcpu_single(vpid
);
1601 vpid_sync_vcpu_global();
1604 static inline void ept_sync_global(void)
1606 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1609 static inline void ept_sync_context(u64 eptp
)
1611 if (cpu_has_vmx_invept_context())
1612 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1617 static __always_inline
void vmcs_check16(unsigned long field
)
1619 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1620 "16-bit accessor invalid for 64-bit field");
1621 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1622 "16-bit accessor invalid for 64-bit high field");
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1624 "16-bit accessor invalid for 32-bit high field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1626 "16-bit accessor invalid for natural width field");
1629 static __always_inline
void vmcs_check32(unsigned long field
)
1631 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1632 "32-bit accessor invalid for 16-bit field");
1633 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1634 "32-bit accessor invalid for natural width field");
1637 static __always_inline
void vmcs_check64(unsigned long field
)
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1640 "64-bit accessor invalid for 16-bit field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1642 "64-bit accessor invalid for 64-bit high field");
1643 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1644 "64-bit accessor invalid for 32-bit field");
1645 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1646 "64-bit accessor invalid for natural width field");
1649 static __always_inline
void vmcs_checkl(unsigned long field
)
1651 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1652 "Natural width accessor invalid for 16-bit field");
1653 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1654 "Natural width accessor invalid for 64-bit field");
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1656 "Natural width accessor invalid for 64-bit high field");
1657 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1658 "Natural width accessor invalid for 32-bit field");
1661 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1663 unsigned long value
;
1665 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1666 : "=a"(value
) : "d"(field
) : "cc");
1670 static __always_inline u16
vmcs_read16(unsigned long field
)
1672 vmcs_check16(field
);
1673 return __vmcs_readl(field
);
1676 static __always_inline u32
vmcs_read32(unsigned long field
)
1678 vmcs_check32(field
);
1679 return __vmcs_readl(field
);
1682 static __always_inline u64
vmcs_read64(unsigned long field
)
1684 vmcs_check64(field
);
1685 #ifdef CONFIG_X86_64
1686 return __vmcs_readl(field
);
1688 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1692 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1695 return __vmcs_readl(field
);
1698 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1700 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1701 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1705 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1709 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1710 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1711 if (unlikely(error
))
1712 vmwrite_error(field
, value
);
1715 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1717 vmcs_check16(field
);
1718 __vmcs_writel(field
, value
);
1721 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1723 vmcs_check32(field
);
1724 __vmcs_writel(field
, value
);
1727 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1729 vmcs_check64(field
);
1730 __vmcs_writel(field
, value
);
1731 #ifndef CONFIG_X86_64
1733 __vmcs_writel(field
+1, value
>> 32);
1737 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1740 __vmcs_writel(field
, value
);
1743 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1745 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1746 "vmcs_clear_bits does not support 64-bit fields");
1747 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1750 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1752 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1753 "vmcs_set_bits does not support 64-bit fields");
1754 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1757 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1759 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1762 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1764 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1765 vmx
->vm_entry_controls_shadow
= val
;
1768 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1770 if (vmx
->vm_entry_controls_shadow
!= val
)
1771 vm_entry_controls_init(vmx
, val
);
1774 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1776 return vmx
->vm_entry_controls_shadow
;
1780 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1782 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1785 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1787 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1790 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1792 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1795 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1797 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1798 vmx
->vm_exit_controls_shadow
= val
;
1801 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1803 if (vmx
->vm_exit_controls_shadow
!= val
)
1804 vm_exit_controls_init(vmx
, val
);
1807 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1809 return vmx
->vm_exit_controls_shadow
;
1813 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1815 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1818 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1820 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1823 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1825 vmx
->segment_cache
.bitmask
= 0;
1828 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1832 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1834 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1835 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1836 vmx
->segment_cache
.bitmask
= 0;
1838 ret
= vmx
->segment_cache
.bitmask
& mask
;
1839 vmx
->segment_cache
.bitmask
|= mask
;
1843 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1845 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1847 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1848 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1852 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1854 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1856 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1857 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1861 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1863 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1865 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1866 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1870 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1872 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1874 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1875 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1879 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1883 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1884 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1885 if ((vcpu
->guest_debug
&
1886 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1887 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1888 eb
|= 1u << BP_VECTOR
;
1889 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1892 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1894 /* When we are running a nested L2 guest and L1 specified for it a
1895 * certain exception bitmap, we must trap the same exceptions and pass
1896 * them to L1. When running L2, we will only handle the exceptions
1897 * specified above if L1 did not want them.
1899 if (is_guest_mode(vcpu
))
1900 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1902 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1905 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1906 unsigned long entry
, unsigned long exit
)
1908 vm_entry_controls_clearbit(vmx
, entry
);
1909 vm_exit_controls_clearbit(vmx
, exit
);
1912 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1915 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1919 if (cpu_has_load_ia32_efer
) {
1920 clear_atomic_switch_msr_special(vmx
,
1921 VM_ENTRY_LOAD_IA32_EFER
,
1922 VM_EXIT_LOAD_IA32_EFER
);
1926 case MSR_CORE_PERF_GLOBAL_CTRL
:
1927 if (cpu_has_load_perf_global_ctrl
) {
1928 clear_atomic_switch_msr_special(vmx
,
1929 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1936 for (i
= 0; i
< m
->nr
; ++i
)
1937 if (m
->guest
[i
].index
== msr
)
1943 m
->guest
[i
] = m
->guest
[m
->nr
];
1944 m
->host
[i
] = m
->host
[m
->nr
];
1945 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1946 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1949 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1950 unsigned long entry
, unsigned long exit
,
1951 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1952 u64 guest_val
, u64 host_val
)
1954 vmcs_write64(guest_val_vmcs
, guest_val
);
1955 vmcs_write64(host_val_vmcs
, host_val
);
1956 vm_entry_controls_setbit(vmx
, entry
);
1957 vm_exit_controls_setbit(vmx
, exit
);
1960 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1961 u64 guest_val
, u64 host_val
)
1964 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1968 if (cpu_has_load_ia32_efer
) {
1969 add_atomic_switch_msr_special(vmx
,
1970 VM_ENTRY_LOAD_IA32_EFER
,
1971 VM_EXIT_LOAD_IA32_EFER
,
1974 guest_val
, host_val
);
1978 case MSR_CORE_PERF_GLOBAL_CTRL
:
1979 if (cpu_has_load_perf_global_ctrl
) {
1980 add_atomic_switch_msr_special(vmx
,
1981 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1982 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1983 GUEST_IA32_PERF_GLOBAL_CTRL
,
1984 HOST_IA32_PERF_GLOBAL_CTRL
,
1985 guest_val
, host_val
);
1989 case MSR_IA32_PEBS_ENABLE
:
1990 /* PEBS needs a quiescent period after being disabled (to write
1991 * a record). Disabling PEBS through VMX MSR swapping doesn't
1992 * provide that period, so a CPU could write host's record into
1995 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1998 for (i
= 0; i
< m
->nr
; ++i
)
1999 if (m
->guest
[i
].index
== msr
)
2002 if (i
== NR_AUTOLOAD_MSRS
) {
2003 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2004 "Can't add msr %x\n", msr
);
2006 } else if (i
== m
->nr
) {
2008 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2009 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2012 m
->guest
[i
].index
= msr
;
2013 m
->guest
[i
].value
= guest_val
;
2014 m
->host
[i
].index
= msr
;
2015 m
->host
[i
].value
= host_val
;
2018 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2020 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2021 u64 ignore_bits
= 0;
2025 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2026 * host CPUID is more efficient than testing guest CPUID
2027 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2029 if (boot_cpu_has(X86_FEATURE_SMEP
))
2030 guest_efer
|= EFER_NX
;
2031 else if (!(guest_efer
& EFER_NX
))
2032 ignore_bits
|= EFER_NX
;
2036 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2038 ignore_bits
|= EFER_SCE
;
2039 #ifdef CONFIG_X86_64
2040 ignore_bits
|= EFER_LMA
| EFER_LME
;
2041 /* SCE is meaningful only in long mode on Intel */
2042 if (guest_efer
& EFER_LMA
)
2043 ignore_bits
&= ~(u64
)EFER_SCE
;
2046 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2049 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2050 * On CPUs that support "load IA32_EFER", always switch EFER
2051 * atomically, since it's faster than switching it manually.
2053 if (cpu_has_load_ia32_efer
||
2054 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2055 if (!(guest_efer
& EFER_LMA
))
2056 guest_efer
&= ~EFER_LME
;
2057 if (guest_efer
!= host_efer
)
2058 add_atomic_switch_msr(vmx
, MSR_EFER
,
2059 guest_efer
, host_efer
);
2062 guest_efer
&= ~ignore_bits
;
2063 guest_efer
|= host_efer
& ignore_bits
;
2065 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2066 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2072 #ifdef CONFIG_X86_32
2074 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2075 * VMCS rather than the segment table. KVM uses this helper to figure
2076 * out the current bases to poke them into the VMCS before entry.
2078 static unsigned long segment_base(u16 selector
)
2080 struct desc_struct
*table
;
2083 if (!(selector
& ~SEGMENT_RPL_MASK
))
2086 table
= get_current_gdt_ro();
2088 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2089 u16 ldt_selector
= kvm_read_ldt();
2091 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2094 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2096 v
= get_desc_base(&table
[selector
>> 3]);
2101 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2103 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2106 if (vmx
->host_state
.loaded
)
2109 vmx
->host_state
.loaded
= 1;
2111 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2112 * allow segment selectors with cpl > 0 or ti == 1.
2114 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2115 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2116 savesegment(fs
, vmx
->host_state
.fs_sel
);
2117 if (!(vmx
->host_state
.fs_sel
& 7)) {
2118 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2119 vmx
->host_state
.fs_reload_needed
= 0;
2121 vmcs_write16(HOST_FS_SELECTOR
, 0);
2122 vmx
->host_state
.fs_reload_needed
= 1;
2124 savesegment(gs
, vmx
->host_state
.gs_sel
);
2125 if (!(vmx
->host_state
.gs_sel
& 7))
2126 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2128 vmcs_write16(HOST_GS_SELECTOR
, 0);
2129 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2132 #ifdef CONFIG_X86_64
2133 savesegment(ds
, vmx
->host_state
.ds_sel
);
2134 savesegment(es
, vmx
->host_state
.es_sel
);
2137 #ifdef CONFIG_X86_64
2138 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2139 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2141 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2142 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2145 #ifdef CONFIG_X86_64
2146 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2147 if (is_long_mode(&vmx
->vcpu
))
2148 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2150 if (boot_cpu_has(X86_FEATURE_MPX
))
2151 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2152 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2153 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2154 vmx
->guest_msrs
[i
].data
,
2155 vmx
->guest_msrs
[i
].mask
);
2158 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2160 if (!vmx
->host_state
.loaded
)
2163 ++vmx
->vcpu
.stat
.host_state_reload
;
2164 vmx
->host_state
.loaded
= 0;
2165 #ifdef CONFIG_X86_64
2166 if (is_long_mode(&vmx
->vcpu
))
2167 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2169 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2170 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2171 #ifdef CONFIG_X86_64
2172 load_gs_index(vmx
->host_state
.gs_sel
);
2174 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2177 if (vmx
->host_state
.fs_reload_needed
)
2178 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2179 #ifdef CONFIG_X86_64
2180 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2181 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2182 loadsegment(es
, vmx
->host_state
.es_sel
);
2185 invalidate_tss_limit();
2186 #ifdef CONFIG_X86_64
2187 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2189 if (vmx
->host_state
.msr_host_bndcfgs
)
2190 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2191 load_fixmap_gdt(raw_smp_processor_id());
2194 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2197 __vmx_load_host_state(vmx
);
2201 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2203 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2204 struct pi_desc old
, new;
2208 * In case of hot-plug or hot-unplug, we may have to undo
2209 * vmx_vcpu_pi_put even if there is no assigned device. And we
2210 * always keep PI.NDST up to date for simplicity: it makes the
2211 * code easier, and CPU migration is not a fast path.
2213 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2217 * First handle the simple case where no cmpxchg is necessary; just
2218 * allow posting non-urgent interrupts.
2220 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2221 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2222 * expects the VCPU to be on the blocked_vcpu_list that matches
2225 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2227 pi_clear_sn(pi_desc
);
2231 /* The full case. */
2233 old
.control
= new.control
= pi_desc
->control
;
2235 dest
= cpu_physical_id(cpu
);
2237 if (x2apic_enabled())
2240 new.ndst
= (dest
<< 8) & 0xFF00;
2243 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2244 new.control
) != old
.control
);
2247 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2249 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2250 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2254 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2255 * vcpu mutex is already taken.
2257 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2259 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2260 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2262 if (!already_loaded
) {
2263 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2264 local_irq_disable();
2265 crash_disable_local_vmclear(cpu
);
2268 * Read loaded_vmcs->cpu should be before fetching
2269 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2270 * See the comments in __loaded_vmcs_clear().
2274 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2275 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2276 crash_enable_local_vmclear(cpu
);
2280 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2281 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2282 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2285 if (!already_loaded
) {
2286 void *gdt
= get_current_gdt_ro();
2287 unsigned long sysenter_esp
;
2289 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2292 * Linux uses per-cpu TSS and GDT, so set these when switching
2293 * processors. See 22.2.4.
2295 vmcs_writel(HOST_TR_BASE
,
2296 (unsigned long)this_cpu_ptr(&cpu_tss
));
2297 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2300 * VM exits change the host TR limit to 0x67 after a VM
2301 * exit. This is okay, since 0x67 covers everything except
2302 * the IO bitmap and have have code to handle the IO bitmap
2303 * being lost after a VM exit.
2305 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2307 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2308 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2310 vmx
->loaded_vmcs
->cpu
= cpu
;
2313 /* Setup TSC multiplier */
2314 if (kvm_has_tsc_control
&&
2315 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2316 decache_tsc_multiplier(vmx
);
2318 vmx_vcpu_pi_load(vcpu
, cpu
);
2319 vmx
->host_pkru
= read_pkru();
2322 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2324 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2326 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2327 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2328 !kvm_vcpu_apicv_active(vcpu
))
2331 /* Set SN when the vCPU is preempted */
2332 if (vcpu
->preempted
)
2336 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2338 vmx_vcpu_pi_put(vcpu
);
2340 __vmx_load_host_state(to_vmx(vcpu
));
2343 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2345 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2348 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2351 * Return the cr0 value that a nested guest would read. This is a combination
2352 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2353 * its hypervisor (cr0_read_shadow).
2355 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2357 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2358 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2360 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2362 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2363 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2366 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2368 unsigned long rflags
, save_rflags
;
2370 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2371 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2372 rflags
= vmcs_readl(GUEST_RFLAGS
);
2373 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2374 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2375 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2376 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2378 to_vmx(vcpu
)->rflags
= rflags
;
2380 return to_vmx(vcpu
)->rflags
;
2383 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2385 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2387 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2388 to_vmx(vcpu
)->rflags
= rflags
;
2389 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2390 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2391 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2393 vmcs_writel(GUEST_RFLAGS
, rflags
);
2395 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2396 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2399 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2401 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2404 if (interruptibility
& GUEST_INTR_STATE_STI
)
2405 ret
|= KVM_X86_SHADOW_INT_STI
;
2406 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2407 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2412 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2414 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2415 u32 interruptibility
= interruptibility_old
;
2417 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2419 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2420 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2421 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2422 interruptibility
|= GUEST_INTR_STATE_STI
;
2424 if ((interruptibility
!= interruptibility_old
))
2425 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2428 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2432 rip
= kvm_rip_read(vcpu
);
2433 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2434 kvm_rip_write(vcpu
, rip
);
2436 /* skipping an emulated instruction also counts */
2437 vmx_set_interrupt_shadow(vcpu
, 0);
2440 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2441 unsigned long exit_qual
)
2443 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2444 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2445 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2447 if (vcpu
->arch
.exception
.has_error_code
) {
2448 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2449 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2452 if (kvm_exception_is_soft(nr
))
2453 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2455 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2457 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2458 vmx_get_nmi_mask(vcpu
))
2459 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2461 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2465 * KVM wants to inject page-faults which it got to the guest. This function
2466 * checks whether in a nested guest, we need to inject them to L1 or L2.
2468 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2470 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2471 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2473 if (nr
== PF_VECTOR
) {
2474 if (vcpu
->arch
.exception
.nested_apf
) {
2475 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2479 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2480 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2481 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2482 * can be written only when inject_pending_event runs. This should be
2483 * conditional on a new capability---if the capability is disabled,
2484 * kvm_multiple_exception would write the ancillary information to
2485 * CR2 or DR6, for backwards ABI-compatibility.
2487 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2488 vcpu
->arch
.exception
.error_code
)) {
2489 *exit_qual
= vcpu
->arch
.cr2
;
2493 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2494 if (nr
== DB_VECTOR
)
2495 *exit_qual
= vcpu
->arch
.dr6
;
2505 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2507 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2508 unsigned nr
= vcpu
->arch
.exception
.nr
;
2509 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2510 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2511 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2513 if (has_error_code
) {
2514 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2515 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2518 if (vmx
->rmode
.vm86_active
) {
2520 if (kvm_exception_is_soft(nr
))
2521 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2522 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2523 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2527 if (kvm_exception_is_soft(nr
)) {
2528 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2529 vmx
->vcpu
.arch
.event_exit_inst_len
);
2530 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2532 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2534 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2537 static bool vmx_rdtscp_supported(void)
2539 return cpu_has_vmx_rdtscp();
2542 static bool vmx_invpcid_supported(void)
2544 return cpu_has_vmx_invpcid() && enable_ept
;
2548 * Swap MSR entry in host/guest MSR entry array.
2550 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2552 struct shared_msr_entry tmp
;
2554 tmp
= vmx
->guest_msrs
[to
];
2555 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2556 vmx
->guest_msrs
[from
] = tmp
;
2559 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2561 unsigned long *msr_bitmap
;
2563 if (is_guest_mode(vcpu
))
2564 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2565 else if (cpu_has_secondary_exec_ctrls() &&
2566 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2567 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2568 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2569 if (is_long_mode(vcpu
))
2570 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2572 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2574 if (is_long_mode(vcpu
))
2575 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2577 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2580 if (is_long_mode(vcpu
))
2581 msr_bitmap
= vmx_msr_bitmap_longmode
;
2583 msr_bitmap
= vmx_msr_bitmap_legacy
;
2586 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2590 * Set up the vmcs to automatically save and restore system
2591 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2592 * mode, as fiddling with msrs is very expensive.
2594 static void setup_msrs(struct vcpu_vmx
*vmx
)
2596 int save_nmsrs
, index
;
2599 #ifdef CONFIG_X86_64
2600 if (is_long_mode(&vmx
->vcpu
)) {
2601 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2603 move_msr_up(vmx
, index
, save_nmsrs
++);
2604 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2606 move_msr_up(vmx
, index
, save_nmsrs
++);
2607 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2609 move_msr_up(vmx
, index
, save_nmsrs
++);
2610 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2611 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2612 move_msr_up(vmx
, index
, save_nmsrs
++);
2614 * MSR_STAR is only needed on long mode guests, and only
2615 * if efer.sce is enabled.
2617 index
= __find_msr_index(vmx
, MSR_STAR
);
2618 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2622 index
= __find_msr_index(vmx
, MSR_EFER
);
2623 if (index
>= 0 && update_transition_efer(vmx
, index
))
2624 move_msr_up(vmx
, index
, save_nmsrs
++);
2626 vmx
->save_nmsrs
= save_nmsrs
;
2628 if (cpu_has_vmx_msr_bitmap())
2629 vmx_set_msr_bitmap(&vmx
->vcpu
);
2633 * reads and returns guest's timestamp counter "register"
2634 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2635 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2637 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2639 u64 host_tsc
, tsc_offset
;
2642 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2643 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2647 * writes 'offset' into guest's timestamp counter offset register
2649 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2651 if (is_guest_mode(vcpu
)) {
2653 * We're here if L1 chose not to trap WRMSR to TSC. According
2654 * to the spec, this should set L1's TSC; The offset that L1
2655 * set for L2 remains unchanged, and still needs to be added
2656 * to the newly set TSC to get L2's TSC.
2658 struct vmcs12
*vmcs12
;
2659 /* recalculate vmcs02.TSC_OFFSET: */
2660 vmcs12
= get_vmcs12(vcpu
);
2661 vmcs_write64(TSC_OFFSET
, offset
+
2662 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2663 vmcs12
->tsc_offset
: 0));
2665 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2666 vmcs_read64(TSC_OFFSET
), offset
);
2667 vmcs_write64(TSC_OFFSET
, offset
);
2672 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2673 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2674 * all guests if the "nested" module option is off, and can also be disabled
2675 * for a single guest by disabling its VMX cpuid bit.
2677 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2679 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2683 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2684 * returned for the various VMX controls MSRs when nested VMX is enabled.
2685 * The same values should also be used to verify that vmcs12 control fields are
2686 * valid during nested entry from L1 to L2.
2687 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2688 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2689 * bit in the high half is on if the corresponding bit in the control field
2690 * may be on. See also vmx_control_verify().
2692 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2695 * Note that as a general rule, the high half of the MSRs (bits in
2696 * the control fields which may be 1) should be initialized by the
2697 * intersection of the underlying hardware's MSR (i.e., features which
2698 * can be supported) and the list of features we want to expose -
2699 * because they are known to be properly supported in our code.
2700 * Also, usually, the low half of the MSRs (bits which must be 1) can
2701 * be set to 0, meaning that L1 may turn off any of these bits. The
2702 * reason is that if one of these bits is necessary, it will appear
2703 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2704 * fields of vmcs01 and vmcs02, will turn these bits off - and
2705 * nested_vmx_exit_reflected() will not pass related exits to L1.
2706 * These rules have exceptions below.
2709 /* pin-based controls */
2710 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2711 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2712 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2713 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2714 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2716 PIN_BASED_EXT_INTR_MASK
|
2717 PIN_BASED_NMI_EXITING
|
2718 PIN_BASED_VIRTUAL_NMIS
;
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2720 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2721 PIN_BASED_VMX_PREEMPTION_TIMER
;
2722 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2723 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2724 PIN_BASED_POSTED_INTR
;
2727 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2728 vmx
->nested
.nested_vmx_exit_ctls_low
,
2729 vmx
->nested
.nested_vmx_exit_ctls_high
);
2730 vmx
->nested
.nested_vmx_exit_ctls_low
=
2731 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2733 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2734 #ifdef CONFIG_X86_64
2735 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2737 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2738 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2740 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2741 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2743 if (kvm_mpx_supported())
2744 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2746 /* We support free control of debug control saving. */
2747 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2749 /* entry controls */
2750 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2751 vmx
->nested
.nested_vmx_entry_ctls_low
,
2752 vmx
->nested
.nested_vmx_entry_ctls_high
);
2753 vmx
->nested
.nested_vmx_entry_ctls_low
=
2754 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2755 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2756 #ifdef CONFIG_X86_64
2757 VM_ENTRY_IA32E_MODE
|
2759 VM_ENTRY_LOAD_IA32_PAT
;
2760 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2761 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2762 if (kvm_mpx_supported())
2763 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2765 /* We support free control of debug control loading. */
2766 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2768 /* cpu-based controls */
2769 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2772 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2773 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2775 CPU_BASED_VIRTUAL_INTR_PENDING
|
2776 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2777 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2778 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 #ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2784 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2785 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2786 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2787 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2789 * We can allow some features even when not supported by the
2790 * hardware. For example, L1 can specify an MSR bitmap - and we
2791 * can use it to avoid exits to L1 - even when L0 runs L2
2792 * without MSR bitmaps.
2794 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2795 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2796 CPU_BASED_USE_MSR_BITMAPS
;
2798 /* We support free control of CR3 access interception. */
2799 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2800 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2803 * secondary cpu-based controls. Do not include those that
2804 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2806 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2807 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2808 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2809 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2810 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2811 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2812 SECONDARY_EXEC_DESC
|
2813 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2814 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2815 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2816 SECONDARY_EXEC_WBINVD_EXITING
;
2819 /* nested EPT: emulate EPT also to L1 */
2820 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2821 SECONDARY_EXEC_ENABLE_EPT
;
2822 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2823 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2824 if (cpu_has_vmx_ept_execute_only())
2825 vmx
->nested
.nested_vmx_ept_caps
|=
2826 VMX_EPT_EXECUTE_ONLY_BIT
;
2827 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2828 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2829 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2830 VMX_EPT_1GB_PAGE_BIT
;
2831 if (enable_ept_ad_bits
) {
2832 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2833 SECONDARY_EXEC_ENABLE_PML
;
2834 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2838 if (cpu_has_vmx_vmfunc()) {
2839 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2840 SECONDARY_EXEC_ENABLE_VMFUNC
;
2842 * Advertise EPTP switching unconditionally
2843 * since we emulate it
2846 vmx
->nested
.nested_vmx_vmfunc_controls
=
2847 VMX_VMFUNC_EPTP_SWITCHING
;
2851 * Old versions of KVM use the single-context version without
2852 * checking for support, so declare that it is supported even
2853 * though it is treated as global context. The alternative is
2854 * not failing the single-context invvpid, and it is worse.
2857 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2858 SECONDARY_EXEC_ENABLE_VPID
;
2859 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2860 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2863 if (enable_unrestricted_guest
)
2864 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2865 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2867 /* miscellaneous data */
2868 rdmsr(MSR_IA32_VMX_MISC
,
2869 vmx
->nested
.nested_vmx_misc_low
,
2870 vmx
->nested
.nested_vmx_misc_high
);
2871 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2872 vmx
->nested
.nested_vmx_misc_low
|=
2873 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2874 VMX_MISC_ACTIVITY_HLT
;
2875 vmx
->nested
.nested_vmx_misc_high
= 0;
2878 * This MSR reports some information about VMX support. We
2879 * should return information about the VMX we emulate for the
2880 * guest, and the VMCS structure we give it - not about the
2881 * VMX support of the underlying hardware.
2883 vmx
->nested
.nested_vmx_basic
=
2885 VMX_BASIC_TRUE_CTLS
|
2886 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2887 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2889 if (cpu_has_vmx_basic_inout())
2890 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2893 * These MSRs specify bits which the guest must keep fixed on
2894 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2895 * We picked the standard core2 setting.
2897 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2898 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2899 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2900 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2902 /* These MSRs specify bits which the guest must keep fixed off. */
2903 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2904 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2906 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2907 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2911 * if fixed0[i] == 1: val[i] must be 1
2912 * if fixed1[i] == 0: val[i] must be 0
2914 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2916 return ((val
& fixed1
) | fixed0
) == val
;
2919 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2921 return fixed_bits_valid(control
, low
, high
);
2924 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2926 return low
| ((u64
)high
<< 32);
2929 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2934 return (superset
| subset
) == superset
;
2937 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2939 const u64 feature_and_reserved
=
2940 /* feature (except bit 48; see below) */
2941 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2943 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2944 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2946 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2950 * KVM does not emulate a version of VMX that constrains physical
2951 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2953 if (data
& BIT_ULL(48))
2956 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2957 vmx_basic_vmcs_revision_id(data
))
2960 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2963 vmx
->nested
.nested_vmx_basic
= data
;
2968 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2973 switch (msr_index
) {
2974 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2975 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2976 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2978 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2979 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2980 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2982 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2983 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2984 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2986 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2987 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2988 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2990 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2991 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2992 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2998 supported
= vmx_control_msr(*lowp
, *highp
);
3000 /* Check must-be-1 bits are still 1. */
3001 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3004 /* Check must-be-0 bits are still 0. */
3005 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3009 *highp
= data
>> 32;
3013 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3015 const u64 feature_and_reserved_bits
=
3017 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3018 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3020 GENMASK_ULL(13, 9) | BIT_ULL(31);
3023 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3024 vmx
->nested
.nested_vmx_misc_high
);
3026 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3029 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3030 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3031 vmx_misc_preemption_timer_rate(data
) !=
3032 vmx_misc_preemption_timer_rate(vmx_misc
))
3035 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3038 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3041 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3044 vmx
->nested
.nested_vmx_misc_low
= data
;
3045 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3049 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3051 u64 vmx_ept_vpid_cap
;
3053 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3054 vmx
->nested
.nested_vmx_vpid_caps
);
3056 /* Every bit is either reserved or a feature bit. */
3057 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3060 vmx
->nested
.nested_vmx_ept_caps
= data
;
3061 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3065 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3069 switch (msr_index
) {
3070 case MSR_IA32_VMX_CR0_FIXED0
:
3071 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3073 case MSR_IA32_VMX_CR4_FIXED0
:
3074 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3081 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3082 * must be 1 in the restored value.
3084 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3092 * Called when userspace is restoring VMX MSRs.
3094 * Returns 0 on success, non-0 otherwise.
3096 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3100 switch (msr_index
) {
3101 case MSR_IA32_VMX_BASIC
:
3102 return vmx_restore_vmx_basic(vmx
, data
);
3103 case MSR_IA32_VMX_PINBASED_CTLS
:
3104 case MSR_IA32_VMX_PROCBASED_CTLS
:
3105 case MSR_IA32_VMX_EXIT_CTLS
:
3106 case MSR_IA32_VMX_ENTRY_CTLS
:
3108 * The "non-true" VMX capability MSRs are generated from the
3109 * "true" MSRs, so we do not support restoring them directly.
3111 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3112 * should restore the "true" MSRs with the must-be-1 bits
3113 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3114 * DEFAULT SETTINGS".
3117 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3118 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3119 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3120 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3121 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3122 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3123 case MSR_IA32_VMX_MISC
:
3124 return vmx_restore_vmx_misc(vmx
, data
);
3125 case MSR_IA32_VMX_CR0_FIXED0
:
3126 case MSR_IA32_VMX_CR4_FIXED0
:
3127 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3128 case MSR_IA32_VMX_CR0_FIXED1
:
3129 case MSR_IA32_VMX_CR4_FIXED1
:
3131 * These MSRs are generated based on the vCPU's CPUID, so we
3132 * do not support restoring them directly.
3135 case MSR_IA32_VMX_EPT_VPID_CAP
:
3136 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3137 case MSR_IA32_VMX_VMCS_ENUM
:
3138 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3142 * The rest of the VMX capability MSRs do not support restore.
3148 /* Returns 0 on success, non-0 otherwise. */
3149 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3151 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3153 switch (msr_index
) {
3154 case MSR_IA32_VMX_BASIC
:
3155 *pdata
= vmx
->nested
.nested_vmx_basic
;
3157 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3158 case MSR_IA32_VMX_PINBASED_CTLS
:
3159 *pdata
= vmx_control_msr(
3160 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3161 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3162 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3163 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3165 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3166 case MSR_IA32_VMX_PROCBASED_CTLS
:
3167 *pdata
= vmx_control_msr(
3168 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3169 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3170 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3171 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3173 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3174 case MSR_IA32_VMX_EXIT_CTLS
:
3175 *pdata
= vmx_control_msr(
3176 vmx
->nested
.nested_vmx_exit_ctls_low
,
3177 vmx
->nested
.nested_vmx_exit_ctls_high
);
3178 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3179 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3181 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3182 case MSR_IA32_VMX_ENTRY_CTLS
:
3183 *pdata
= vmx_control_msr(
3184 vmx
->nested
.nested_vmx_entry_ctls_low
,
3185 vmx
->nested
.nested_vmx_entry_ctls_high
);
3186 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3187 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3189 case MSR_IA32_VMX_MISC
:
3190 *pdata
= vmx_control_msr(
3191 vmx
->nested
.nested_vmx_misc_low
,
3192 vmx
->nested
.nested_vmx_misc_high
);
3194 case MSR_IA32_VMX_CR0_FIXED0
:
3195 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3197 case MSR_IA32_VMX_CR0_FIXED1
:
3198 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3200 case MSR_IA32_VMX_CR4_FIXED0
:
3201 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3203 case MSR_IA32_VMX_CR4_FIXED1
:
3204 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3206 case MSR_IA32_VMX_VMCS_ENUM
:
3207 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3209 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3210 *pdata
= vmx_control_msr(
3211 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3212 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3214 case MSR_IA32_VMX_EPT_VPID_CAP
:
3215 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3216 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3218 case MSR_IA32_VMX_VMFUNC
:
3219 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3228 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3231 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3233 return !(val
& ~valid_bits
);
3237 * Reads an msr value (of 'msr_index') into 'pdata'.
3238 * Returns 0 on success, non-0 otherwise.
3239 * Assumes vcpu_load() was already called.
3241 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3243 struct shared_msr_entry
*msr
;
3245 switch (msr_info
->index
) {
3246 #ifdef CONFIG_X86_64
3248 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3251 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3253 case MSR_KERNEL_GS_BASE
:
3254 vmx_load_host_state(to_vmx(vcpu
));
3255 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3259 return kvm_get_msr_common(vcpu
, msr_info
);
3261 msr_info
->data
= guest_read_tsc(vcpu
);
3263 case MSR_IA32_SYSENTER_CS
:
3264 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3266 case MSR_IA32_SYSENTER_EIP
:
3267 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3269 case MSR_IA32_SYSENTER_ESP
:
3270 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3272 case MSR_IA32_BNDCFGS
:
3273 if (!kvm_mpx_supported() ||
3274 (!msr_info
->host_initiated
&&
3275 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3277 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3279 case MSR_IA32_MCG_EXT_CTL
:
3280 if (!msr_info
->host_initiated
&&
3281 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3282 FEATURE_CONTROL_LMCE
))
3284 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3286 case MSR_IA32_FEATURE_CONTROL
:
3287 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3289 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3290 if (!nested_vmx_allowed(vcpu
))
3292 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3294 if (!vmx_xsaves_supported())
3296 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3299 if (!msr_info
->host_initiated
&&
3300 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3302 /* Otherwise falls through */
3304 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3306 msr_info
->data
= msr
->data
;
3309 return kvm_get_msr_common(vcpu
, msr_info
);
3315 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3318 * Writes msr value into into the appropriate "register".
3319 * Returns 0 on success, non-0 otherwise.
3320 * Assumes vcpu_load() was already called.
3322 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3324 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3325 struct shared_msr_entry
*msr
;
3327 u32 msr_index
= msr_info
->index
;
3328 u64 data
= msr_info
->data
;
3330 switch (msr_index
) {
3332 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3334 #ifdef CONFIG_X86_64
3336 vmx_segment_cache_clear(vmx
);
3337 vmcs_writel(GUEST_FS_BASE
, data
);
3340 vmx_segment_cache_clear(vmx
);
3341 vmcs_writel(GUEST_GS_BASE
, data
);
3343 case MSR_KERNEL_GS_BASE
:
3344 vmx_load_host_state(vmx
);
3345 vmx
->msr_guest_kernel_gs_base
= data
;
3348 case MSR_IA32_SYSENTER_CS
:
3349 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3351 case MSR_IA32_SYSENTER_EIP
:
3352 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3354 case MSR_IA32_SYSENTER_ESP
:
3355 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3357 case MSR_IA32_BNDCFGS
:
3358 if (!kvm_mpx_supported() ||
3359 (!msr_info
->host_initiated
&&
3360 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3362 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3363 (data
& MSR_IA32_BNDCFGS_RSVD
))
3365 vmcs_write64(GUEST_BNDCFGS
, data
);
3368 kvm_write_tsc(vcpu
, msr_info
);
3370 case MSR_IA32_CR_PAT
:
3371 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3372 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3374 vmcs_write64(GUEST_IA32_PAT
, data
);
3375 vcpu
->arch
.pat
= data
;
3378 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3380 case MSR_IA32_TSC_ADJUST
:
3381 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3383 case MSR_IA32_MCG_EXT_CTL
:
3384 if ((!msr_info
->host_initiated
&&
3385 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3386 FEATURE_CONTROL_LMCE
)) ||
3387 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3389 vcpu
->arch
.mcg_ext_ctl
= data
;
3391 case MSR_IA32_FEATURE_CONTROL
:
3392 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3393 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3394 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3396 vmx
->msr_ia32_feature_control
= data
;
3397 if (msr_info
->host_initiated
&& data
== 0)
3398 vmx_leave_nested(vcpu
);
3400 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3401 if (!msr_info
->host_initiated
)
3402 return 1; /* they are read-only */
3403 if (!nested_vmx_allowed(vcpu
))
3405 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3407 if (!vmx_xsaves_supported())
3410 * The only supported bit as of Skylake is bit 8, but
3411 * it is not supported on KVM.
3415 vcpu
->arch
.ia32_xss
= data
;
3416 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3417 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3418 vcpu
->arch
.ia32_xss
, host_xss
);
3420 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3423 if (!msr_info
->host_initiated
&&
3424 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3426 /* Check reserved bit, higher 32 bits should be zero */
3427 if ((data
>> 32) != 0)
3429 /* Otherwise falls through */
3431 msr
= find_msr_entry(vmx
, msr_index
);
3433 u64 old_msr_data
= msr
->data
;
3435 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3437 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3441 msr
->data
= old_msr_data
;
3445 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3451 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3453 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3456 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3459 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3461 case VCPU_EXREG_PDPTR
:
3463 ept_save_pdptrs(vcpu
);
3470 static __init
int cpu_has_kvm_support(void)
3472 return cpu_has_vmx();
3475 static __init
int vmx_disabled_by_bios(void)
3479 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3480 if (msr
& FEATURE_CONTROL_LOCKED
) {
3481 /* launched w/ TXT and VMX disabled */
3482 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3485 /* launched w/o TXT and VMX only enabled w/ TXT */
3486 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3487 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3488 && !tboot_enabled()) {
3489 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3490 "activate TXT before enabling KVM\n");
3493 /* launched w/o TXT and VMX disabled */
3494 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3495 && !tboot_enabled())
3502 static void kvm_cpu_vmxon(u64 addr
)
3504 cr4_set_bits(X86_CR4_VMXE
);
3505 intel_pt_handle_vmx(1);
3507 asm volatile (ASM_VMX_VMXON_RAX
3508 : : "a"(&addr
), "m"(addr
)
3512 static int hardware_enable(void)
3514 int cpu
= raw_smp_processor_id();
3515 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3518 if (cr4_read_shadow() & X86_CR4_VMXE
)
3521 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3522 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3523 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3526 * Now we can enable the vmclear operation in kdump
3527 * since the loaded_vmcss_on_cpu list on this cpu
3528 * has been initialized.
3530 * Though the cpu is not in VMX operation now, there
3531 * is no problem to enable the vmclear operation
3532 * for the loaded_vmcss_on_cpu list is empty!
3534 crash_enable_local_vmclear(cpu
);
3536 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3538 test_bits
= FEATURE_CONTROL_LOCKED
;
3539 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3540 if (tboot_enabled())
3541 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3543 if ((old
& test_bits
) != test_bits
) {
3544 /* enable and lock */
3545 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3547 kvm_cpu_vmxon(phys_addr
);
3554 static void vmclear_local_loaded_vmcss(void)
3556 int cpu
= raw_smp_processor_id();
3557 struct loaded_vmcs
*v
, *n
;
3559 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3560 loaded_vmcss_on_cpu_link
)
3561 __loaded_vmcs_clear(v
);
3565 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3568 static void kvm_cpu_vmxoff(void)
3570 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3572 intel_pt_handle_vmx(0);
3573 cr4_clear_bits(X86_CR4_VMXE
);
3576 static void hardware_disable(void)
3578 vmclear_local_loaded_vmcss();
3582 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3583 u32 msr
, u32
*result
)
3585 u32 vmx_msr_low
, vmx_msr_high
;
3586 u32 ctl
= ctl_min
| ctl_opt
;
3588 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3590 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3591 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3593 /* Ensure minimum (required) set of control bits are supported. */
3601 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3603 u32 vmx_msr_low
, vmx_msr_high
;
3605 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3606 return vmx_msr_high
& ctl
;
3609 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3611 u32 vmx_msr_low
, vmx_msr_high
;
3612 u32 min
, opt
, min2
, opt2
;
3613 u32 _pin_based_exec_control
= 0;
3614 u32 _cpu_based_exec_control
= 0;
3615 u32 _cpu_based_2nd_exec_control
= 0;
3616 u32 _vmexit_control
= 0;
3617 u32 _vmentry_control
= 0;
3619 min
= CPU_BASED_HLT_EXITING
|
3620 #ifdef CONFIG_X86_64
3621 CPU_BASED_CR8_LOAD_EXITING
|
3622 CPU_BASED_CR8_STORE_EXITING
|
3624 CPU_BASED_CR3_LOAD_EXITING
|
3625 CPU_BASED_CR3_STORE_EXITING
|
3626 CPU_BASED_USE_IO_BITMAPS
|
3627 CPU_BASED_MOV_DR_EXITING
|
3628 CPU_BASED_USE_TSC_OFFSETING
|
3629 CPU_BASED_INVLPG_EXITING
|
3630 CPU_BASED_RDPMC_EXITING
;
3632 if (!kvm_mwait_in_guest())
3633 min
|= CPU_BASED_MWAIT_EXITING
|
3634 CPU_BASED_MONITOR_EXITING
;
3636 opt
= CPU_BASED_TPR_SHADOW
|
3637 CPU_BASED_USE_MSR_BITMAPS
|
3638 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3639 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3640 &_cpu_based_exec_control
) < 0)
3642 #ifdef CONFIG_X86_64
3643 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3644 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3645 ~CPU_BASED_CR8_STORE_EXITING
;
3647 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3649 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3650 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3651 SECONDARY_EXEC_WBINVD_EXITING
|
3652 SECONDARY_EXEC_ENABLE_VPID
|
3653 SECONDARY_EXEC_ENABLE_EPT
|
3654 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3655 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3656 SECONDARY_EXEC_RDTSCP
|
3657 SECONDARY_EXEC_ENABLE_INVPCID
|
3658 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3659 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3660 SECONDARY_EXEC_SHADOW_VMCS
|
3661 SECONDARY_EXEC_XSAVES
|
3662 SECONDARY_EXEC_RDSEED_EXITING
|
3663 SECONDARY_EXEC_RDRAND_EXITING
|
3664 SECONDARY_EXEC_ENABLE_PML
|
3665 SECONDARY_EXEC_TSC_SCALING
|
3666 SECONDARY_EXEC_ENABLE_VMFUNC
;
3667 if (adjust_vmx_controls(min2
, opt2
,
3668 MSR_IA32_VMX_PROCBASED_CTLS2
,
3669 &_cpu_based_2nd_exec_control
) < 0)
3672 #ifndef CONFIG_X86_64
3673 if (!(_cpu_based_2nd_exec_control
&
3674 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3675 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3678 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3679 _cpu_based_2nd_exec_control
&= ~(
3680 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3681 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3682 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3684 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3685 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3687 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3688 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3690 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3691 CPU_BASED_CR3_STORE_EXITING
|
3692 CPU_BASED_INVLPG_EXITING
);
3693 } else if (vmx_capability
.ept
) {
3694 vmx_capability
.ept
= 0;
3695 pr_warn_once("EPT CAP should not exist if not support "
3696 "1-setting enable EPT VM-execution control\n");
3698 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3699 vmx_capability
.vpid
) {
3700 vmx_capability
.vpid
= 0;
3701 pr_warn_once("VPID CAP should not exist if not support "
3702 "1-setting enable VPID VM-execution control\n");
3705 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3706 #ifdef CONFIG_X86_64
3707 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3709 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3710 VM_EXIT_CLEAR_BNDCFGS
;
3711 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3712 &_vmexit_control
) < 0)
3715 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3716 PIN_BASED_VIRTUAL_NMIS
;
3717 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3718 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3719 &_pin_based_exec_control
) < 0)
3722 if (cpu_has_broken_vmx_preemption_timer())
3723 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3724 if (!(_cpu_based_2nd_exec_control
&
3725 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3726 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3728 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3729 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3730 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3731 &_vmentry_control
) < 0)
3734 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3736 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3737 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3740 #ifdef CONFIG_X86_64
3741 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3742 if (vmx_msr_high
& (1u<<16))
3746 /* Require Write-Back (WB) memory type for VMCS accesses. */
3747 if (((vmx_msr_high
>> 18) & 15) != 6)
3750 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3751 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3752 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3753 vmcs_conf
->revision_id
= vmx_msr_low
;
3755 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3756 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3757 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3758 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3759 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3761 cpu_has_load_ia32_efer
=
3762 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3763 VM_ENTRY_LOAD_IA32_EFER
)
3764 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3765 VM_EXIT_LOAD_IA32_EFER
);
3767 cpu_has_load_perf_global_ctrl
=
3768 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3769 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3770 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3771 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3774 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3775 * but due to errata below it can't be used. Workaround is to use
3776 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3778 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3783 * BC86,AAY89,BD102 (model 44)
3787 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3788 switch (boot_cpu_data
.x86_model
) {
3794 cpu_has_load_perf_global_ctrl
= false;
3795 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3796 "does not work properly. Using workaround\n");
3803 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3804 rdmsrl(MSR_IA32_XSS
, host_xss
);
3809 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3811 int node
= cpu_to_node(cpu
);
3815 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3818 vmcs
= page_address(pages
);
3819 memset(vmcs
, 0, vmcs_config
.size
);
3820 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3824 static struct vmcs
*alloc_vmcs(void)
3826 return alloc_vmcs_cpu(raw_smp_processor_id());
3829 static void free_vmcs(struct vmcs
*vmcs
)
3831 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3835 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3837 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3839 if (!loaded_vmcs
->vmcs
)
3841 loaded_vmcs_clear(loaded_vmcs
);
3842 free_vmcs(loaded_vmcs
->vmcs
);
3843 loaded_vmcs
->vmcs
= NULL
;
3844 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3847 static void free_kvm_area(void)
3851 for_each_possible_cpu(cpu
) {
3852 free_vmcs(per_cpu(vmxarea
, cpu
));
3853 per_cpu(vmxarea
, cpu
) = NULL
;
3857 enum vmcs_field_type
{
3858 VMCS_FIELD_TYPE_U16
= 0,
3859 VMCS_FIELD_TYPE_U64
= 1,
3860 VMCS_FIELD_TYPE_U32
= 2,
3861 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3864 static inline int vmcs_field_type(unsigned long field
)
3866 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3867 return VMCS_FIELD_TYPE_U32
;
3868 return (field
>> 13) & 0x3 ;
3871 static inline int vmcs_field_readonly(unsigned long field
)
3873 return (((field
>> 10) & 0x3) == 1);
3876 static void init_vmcs_shadow_fields(void)
3880 /* No checks for read only fields yet */
3882 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3883 switch (shadow_read_write_fields
[i
]) {
3885 if (!kvm_mpx_supported())
3893 shadow_read_write_fields
[j
] =
3894 shadow_read_write_fields
[i
];
3897 max_shadow_read_write_fields
= j
;
3899 /* shadowed fields guest access without vmexit */
3900 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3901 unsigned long field
= shadow_read_write_fields
[i
];
3903 clear_bit(field
, vmx_vmwrite_bitmap
);
3904 clear_bit(field
, vmx_vmread_bitmap
);
3905 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3906 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3907 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3910 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3911 unsigned long field
= shadow_read_only_fields
[i
];
3913 clear_bit(field
, vmx_vmread_bitmap
);
3914 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3915 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3919 static __init
int alloc_kvm_area(void)
3923 for_each_possible_cpu(cpu
) {
3926 vmcs
= alloc_vmcs_cpu(cpu
);
3932 per_cpu(vmxarea
, cpu
) = vmcs
;
3937 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3938 struct kvm_segment
*save
)
3940 if (!emulate_invalid_guest_state
) {
3942 * CS and SS RPL should be equal during guest entry according
3943 * to VMX spec, but in reality it is not always so. Since vcpu
3944 * is in the middle of the transition from real mode to
3945 * protected mode it is safe to assume that RPL 0 is a good
3948 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3949 save
->selector
&= ~SEGMENT_RPL_MASK
;
3950 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3953 vmx_set_segment(vcpu
, save
, seg
);
3956 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3958 unsigned long flags
;
3959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3962 * Update real mode segment cache. It may be not up-to-date if sement
3963 * register was written while vcpu was in a guest mode.
3965 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3966 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3967 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3968 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3969 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3970 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3972 vmx
->rmode
.vm86_active
= 0;
3974 vmx_segment_cache_clear(vmx
);
3976 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3978 flags
= vmcs_readl(GUEST_RFLAGS
);
3979 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3980 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3981 vmcs_writel(GUEST_RFLAGS
, flags
);
3983 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3984 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3986 update_exception_bitmap(vcpu
);
3988 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3989 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3990 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3991 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3992 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3993 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3996 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3998 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3999 struct kvm_segment var
= *save
;
4002 if (seg
== VCPU_SREG_CS
)
4005 if (!emulate_invalid_guest_state
) {
4006 var
.selector
= var
.base
>> 4;
4007 var
.base
= var
.base
& 0xffff0;
4017 if (save
->base
& 0xf)
4018 printk_once(KERN_WARNING
"kvm: segment base is not "
4019 "paragraph aligned when entering "
4020 "protected mode (seg=%d)", seg
);
4023 vmcs_write16(sf
->selector
, var
.selector
);
4024 vmcs_writel(sf
->base
, var
.base
);
4025 vmcs_write32(sf
->limit
, var
.limit
);
4026 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4029 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4031 unsigned long flags
;
4032 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4034 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4035 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4036 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4037 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4038 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4039 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4040 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4042 vmx
->rmode
.vm86_active
= 1;
4045 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4046 * vcpu. Warn the user that an update is overdue.
4048 if (!vcpu
->kvm
->arch
.tss_addr
)
4049 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4050 "called before entering vcpu\n");
4052 vmx_segment_cache_clear(vmx
);
4054 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4055 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4056 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4058 flags
= vmcs_readl(GUEST_RFLAGS
);
4059 vmx
->rmode
.save_rflags
= flags
;
4061 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4063 vmcs_writel(GUEST_RFLAGS
, flags
);
4064 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4065 update_exception_bitmap(vcpu
);
4067 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4068 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4069 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4070 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4071 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4072 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4074 kvm_mmu_reset_context(vcpu
);
4077 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4079 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4080 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4086 * Force kernel_gs_base reloading before EFER changes, as control
4087 * of this msr depends on is_long_mode().
4089 vmx_load_host_state(to_vmx(vcpu
));
4090 vcpu
->arch
.efer
= efer
;
4091 if (efer
& EFER_LMA
) {
4092 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4095 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4097 msr
->data
= efer
& ~EFER_LME
;
4102 #ifdef CONFIG_X86_64
4104 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4108 vmx_segment_cache_clear(to_vmx(vcpu
));
4110 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4111 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4112 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4114 vmcs_write32(GUEST_TR_AR_BYTES
,
4115 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4116 | VMX_AR_TYPE_BUSY_64_TSS
);
4118 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4121 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4123 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4124 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4129 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4132 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4134 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4136 vpid_sync_context(vpid
);
4140 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4142 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4145 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4148 vmx_flush_tlb(vcpu
);
4151 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4153 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4155 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4156 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4159 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4161 if (enable_ept
&& is_paging(vcpu
))
4162 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4163 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4166 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4168 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4170 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4171 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4174 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4176 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4178 if (!test_bit(VCPU_EXREG_PDPTR
,
4179 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4182 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4183 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4184 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4185 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4186 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4190 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4192 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4194 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4195 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4196 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4197 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4198 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4201 __set_bit(VCPU_EXREG_PDPTR
,
4202 (unsigned long *)&vcpu
->arch
.regs_avail
);
4203 __set_bit(VCPU_EXREG_PDPTR
,
4204 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4207 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4209 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4210 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4211 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4213 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4214 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4215 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4216 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4218 return fixed_bits_valid(val
, fixed0
, fixed1
);
4221 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4223 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4224 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4226 return fixed_bits_valid(val
, fixed0
, fixed1
);
4229 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4231 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4232 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4234 return fixed_bits_valid(val
, fixed0
, fixed1
);
4237 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4238 #define nested_guest_cr4_valid nested_cr4_valid
4239 #define nested_host_cr4_valid nested_cr4_valid
4241 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4243 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4245 struct kvm_vcpu
*vcpu
)
4247 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4248 vmx_decache_cr3(vcpu
);
4249 if (!(cr0
& X86_CR0_PG
)) {
4250 /* From paging/starting to nonpaging */
4251 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4252 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4253 (CPU_BASED_CR3_LOAD_EXITING
|
4254 CPU_BASED_CR3_STORE_EXITING
));
4255 vcpu
->arch
.cr0
= cr0
;
4256 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4257 } else if (!is_paging(vcpu
)) {
4258 /* From nonpaging to paging */
4259 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4260 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4261 ~(CPU_BASED_CR3_LOAD_EXITING
|
4262 CPU_BASED_CR3_STORE_EXITING
));
4263 vcpu
->arch
.cr0
= cr0
;
4264 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4267 if (!(cr0
& X86_CR0_WP
))
4268 *hw_cr0
&= ~X86_CR0_WP
;
4271 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4273 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4274 unsigned long hw_cr0
;
4276 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4277 if (enable_unrestricted_guest
)
4278 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4280 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4282 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4285 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4289 #ifdef CONFIG_X86_64
4290 if (vcpu
->arch
.efer
& EFER_LME
) {
4291 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4293 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4299 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4301 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4302 vmcs_writel(GUEST_CR0
, hw_cr0
);
4303 vcpu
->arch
.cr0
= cr0
;
4305 /* depends on vcpu->arch.cr0 to be set to a new value */
4306 vmx
->emulation_required
= emulation_required(vcpu
);
4309 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4311 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4316 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4318 u64 eptp
= VMX_EPTP_MT_WB
;
4320 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4322 if (enable_ept_ad_bits
&&
4323 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4324 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4325 eptp
|= (root_hpa
& PAGE_MASK
);
4330 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4332 unsigned long guest_cr3
;
4337 eptp
= construct_eptp(vcpu
, cr3
);
4338 vmcs_write64(EPT_POINTER
, eptp
);
4339 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4340 guest_cr3
= kvm_read_cr3(vcpu
);
4342 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4343 ept_load_pdptrs(vcpu
);
4346 vmx_flush_tlb(vcpu
);
4347 vmcs_writel(GUEST_CR3
, guest_cr3
);
4350 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4353 * Pass through host's Machine Check Enable value to hw_cr4, which
4354 * is in force while we are in guest mode. Do not let guests control
4355 * this bit, even if host CR4.MCE == 0.
4357 unsigned long hw_cr4
=
4358 (cr4_read_shadow() & X86_CR4_MCE
) |
4359 (cr4
& ~X86_CR4_MCE
) |
4360 (to_vmx(vcpu
)->rmode
.vm86_active
?
4361 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4363 if (cr4
& X86_CR4_VMXE
) {
4365 * To use VMXON (and later other VMX instructions), a guest
4366 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4367 * So basically the check on whether to allow nested VMX
4370 if (!nested_vmx_allowed(vcpu
))
4374 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4377 vcpu
->arch
.cr4
= cr4
;
4379 if (!is_paging(vcpu
)) {
4380 hw_cr4
&= ~X86_CR4_PAE
;
4381 hw_cr4
|= X86_CR4_PSE
;
4382 } else if (!(cr4
& X86_CR4_PAE
)) {
4383 hw_cr4
&= ~X86_CR4_PAE
;
4387 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4389 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4390 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4391 * to be manually disabled when guest switches to non-paging
4394 * If !enable_unrestricted_guest, the CPU is always running
4395 * with CR0.PG=1 and CR4 needs to be modified.
4396 * If enable_unrestricted_guest, the CPU automatically
4397 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4399 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4401 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4402 vmcs_writel(GUEST_CR4
, hw_cr4
);
4406 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4407 struct kvm_segment
*var
, int seg
)
4409 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4412 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4413 *var
= vmx
->rmode
.segs
[seg
];
4414 if (seg
== VCPU_SREG_TR
4415 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4417 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4418 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4421 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4422 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4423 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4424 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4425 var
->unusable
= (ar
>> 16) & 1;
4426 var
->type
= ar
& 15;
4427 var
->s
= (ar
>> 4) & 1;
4428 var
->dpl
= (ar
>> 5) & 3;
4430 * Some userspaces do not preserve unusable property. Since usable
4431 * segment has to be present according to VMX spec we can use present
4432 * property to amend userspace bug by making unusable segment always
4433 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4434 * segment as unusable.
4436 var
->present
= !var
->unusable
;
4437 var
->avl
= (ar
>> 12) & 1;
4438 var
->l
= (ar
>> 13) & 1;
4439 var
->db
= (ar
>> 14) & 1;
4440 var
->g
= (ar
>> 15) & 1;
4443 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4445 struct kvm_segment s
;
4447 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4448 vmx_get_segment(vcpu
, &s
, seg
);
4451 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4454 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4456 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4458 if (unlikely(vmx
->rmode
.vm86_active
))
4461 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4462 return VMX_AR_DPL(ar
);
4466 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4470 if (var
->unusable
|| !var
->present
)
4473 ar
= var
->type
& 15;
4474 ar
|= (var
->s
& 1) << 4;
4475 ar
|= (var
->dpl
& 3) << 5;
4476 ar
|= (var
->present
& 1) << 7;
4477 ar
|= (var
->avl
& 1) << 12;
4478 ar
|= (var
->l
& 1) << 13;
4479 ar
|= (var
->db
& 1) << 14;
4480 ar
|= (var
->g
& 1) << 15;
4486 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4487 struct kvm_segment
*var
, int seg
)
4489 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4490 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4492 vmx_segment_cache_clear(vmx
);
4494 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4495 vmx
->rmode
.segs
[seg
] = *var
;
4496 if (seg
== VCPU_SREG_TR
)
4497 vmcs_write16(sf
->selector
, var
->selector
);
4499 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4503 vmcs_writel(sf
->base
, var
->base
);
4504 vmcs_write32(sf
->limit
, var
->limit
);
4505 vmcs_write16(sf
->selector
, var
->selector
);
4508 * Fix the "Accessed" bit in AR field of segment registers for older
4510 * IA32 arch specifies that at the time of processor reset the
4511 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4512 * is setting it to 0 in the userland code. This causes invalid guest
4513 * state vmexit when "unrestricted guest" mode is turned on.
4514 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4515 * tree. Newer qemu binaries with that qemu fix would not need this
4518 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4519 var
->type
|= 0x1; /* Accessed */
4521 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4524 vmx
->emulation_required
= emulation_required(vcpu
);
4527 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4529 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4531 *db
= (ar
>> 14) & 1;
4532 *l
= (ar
>> 13) & 1;
4535 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4537 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4538 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4541 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4543 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4544 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4547 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4549 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4550 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4553 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4555 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4556 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4559 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4561 struct kvm_segment var
;
4564 vmx_get_segment(vcpu
, &var
, seg
);
4566 if (seg
== VCPU_SREG_CS
)
4568 ar
= vmx_segment_access_rights(&var
);
4570 if (var
.base
!= (var
.selector
<< 4))
4572 if (var
.limit
!= 0xffff)
4580 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4582 struct kvm_segment cs
;
4583 unsigned int cs_rpl
;
4585 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4586 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4590 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4594 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4595 if (cs
.dpl
> cs_rpl
)
4598 if (cs
.dpl
!= cs_rpl
)
4604 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4608 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4610 struct kvm_segment ss
;
4611 unsigned int ss_rpl
;
4613 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4614 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4618 if (ss
.type
!= 3 && ss
.type
!= 7)
4622 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4630 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4632 struct kvm_segment var
;
4635 vmx_get_segment(vcpu
, &var
, seg
);
4636 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4644 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4645 if (var
.dpl
< rpl
) /* DPL < RPL */
4649 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4655 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4657 struct kvm_segment tr
;
4659 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4663 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4665 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4673 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4675 struct kvm_segment ldtr
;
4677 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4681 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4691 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4693 struct kvm_segment cs
, ss
;
4695 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4696 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4698 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4699 (ss
.selector
& SEGMENT_RPL_MASK
));
4703 * Check if guest state is valid. Returns true if valid, false if
4705 * We assume that registers are always usable
4707 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4709 if (enable_unrestricted_guest
)
4712 /* real mode guest state checks */
4713 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4714 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4716 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4718 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4720 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4722 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4724 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4727 /* protected mode guest state checks */
4728 if (!cs_ss_rpl_check(vcpu
))
4730 if (!code_segment_valid(vcpu
))
4732 if (!stack_segment_valid(vcpu
))
4734 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4736 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4738 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4740 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4742 if (!tr_valid(vcpu
))
4744 if (!ldtr_valid(vcpu
))
4748 * - Add checks on RIP
4749 * - Add checks on RFLAGS
4755 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4757 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4760 static int init_rmode_tss(struct kvm
*kvm
)
4766 idx
= srcu_read_lock(&kvm
->srcu
);
4767 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4768 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4771 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4772 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4773 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4776 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4779 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4783 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4784 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4787 srcu_read_unlock(&kvm
->srcu
, idx
);
4791 static int init_rmode_identity_map(struct kvm
*kvm
)
4794 kvm_pfn_t identity_map_pfn
;
4797 /* Protect kvm->arch.ept_identity_pagetable_done. */
4798 mutex_lock(&kvm
->slots_lock
);
4800 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4803 if (!kvm
->arch
.ept_identity_map_addr
)
4804 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4805 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4807 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4808 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4812 idx
= srcu_read_lock(&kvm
->srcu
);
4813 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4816 /* Set up identity-mapping pagetable for EPT in real mode */
4817 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4818 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4819 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4820 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4821 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4825 kvm
->arch
.ept_identity_pagetable_done
= true;
4828 srcu_read_unlock(&kvm
->srcu
, idx
);
4831 mutex_unlock(&kvm
->slots_lock
);
4835 static void seg_setup(int seg
)
4837 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4840 vmcs_write16(sf
->selector
, 0);
4841 vmcs_writel(sf
->base
, 0);
4842 vmcs_write32(sf
->limit
, 0xffff);
4844 if (seg
== VCPU_SREG_CS
)
4845 ar
|= 0x08; /* code segment */
4847 vmcs_write32(sf
->ar_bytes
, ar
);
4850 static int alloc_apic_access_page(struct kvm
*kvm
)
4855 mutex_lock(&kvm
->slots_lock
);
4856 if (kvm
->arch
.apic_access_page_done
)
4858 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4859 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4863 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4864 if (is_error_page(page
)) {
4870 * Do not pin the page in memory, so that memory hot-unplug
4871 * is able to migrate it.
4874 kvm
->arch
.apic_access_page_done
= true;
4876 mutex_unlock(&kvm
->slots_lock
);
4880 static int allocate_vpid(void)
4886 spin_lock(&vmx_vpid_lock
);
4887 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4888 if (vpid
< VMX_NR_VPIDS
)
4889 __set_bit(vpid
, vmx_vpid_bitmap
);
4892 spin_unlock(&vmx_vpid_lock
);
4896 static void free_vpid(int vpid
)
4898 if (!enable_vpid
|| vpid
== 0)
4900 spin_lock(&vmx_vpid_lock
);
4901 __clear_bit(vpid
, vmx_vpid_bitmap
);
4902 spin_unlock(&vmx_vpid_lock
);
4905 #define MSR_TYPE_R 1
4906 #define MSR_TYPE_W 2
4907 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4910 int f
= sizeof(unsigned long);
4912 if (!cpu_has_vmx_msr_bitmap())
4916 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4917 * have the write-low and read-high bitmap offsets the wrong way round.
4918 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4920 if (msr
<= 0x1fff) {
4921 if (type
& MSR_TYPE_R
)
4923 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4925 if (type
& MSR_TYPE_W
)
4927 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4929 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4931 if (type
& MSR_TYPE_R
)
4933 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4935 if (type
& MSR_TYPE_W
)
4937 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4943 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4944 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4946 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4947 unsigned long *msr_bitmap_nested
,
4950 int f
= sizeof(unsigned long);
4952 if (!cpu_has_vmx_msr_bitmap()) {
4958 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4959 * have the write-low and read-high bitmap offsets the wrong way round.
4960 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4962 if (msr
<= 0x1fff) {
4963 if (type
& MSR_TYPE_R
&&
4964 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4966 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4968 if (type
& MSR_TYPE_W
&&
4969 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4971 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4973 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4975 if (type
& MSR_TYPE_R
&&
4976 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4978 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4980 if (type
& MSR_TYPE_W
&&
4981 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4983 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4988 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4991 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4992 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4993 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4994 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4997 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5000 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5002 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5005 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5007 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5012 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5014 return enable_apicv
;
5017 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5019 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5023 * Don't need to mark the APIC access page dirty; it is never
5024 * written to by the CPU during APIC virtualization.
5027 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5028 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5029 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5032 if (nested_cpu_has_posted_intr(vmcs12
)) {
5033 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5034 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5039 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5041 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5046 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5049 vmx
->nested
.pi_pending
= false;
5050 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5053 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5054 if (max_irr
!= 256) {
5055 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5056 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5057 kunmap(vmx
->nested
.virtual_apic_page
);
5059 status
= vmcs_read16(GUEST_INTR_STATUS
);
5060 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5062 status
|= (u8
)max_irr
;
5063 vmcs_write16(GUEST_INTR_STATUS
, status
);
5067 nested_mark_vmcs12_pages_dirty(vcpu
);
5070 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5074 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5076 if (vcpu
->mode
== IN_GUEST_MODE
) {
5078 * The vector of interrupt to be delivered to vcpu had
5079 * been set in PIR before this function.
5081 * Following cases will be reached in this block, and
5082 * we always send a notification event in all cases as
5085 * Case 1: vcpu keeps in non-root mode. Sending a
5086 * notification event posts the interrupt to vcpu.
5088 * Case 2: vcpu exits to root mode and is still
5089 * runnable. PIR will be synced to vIRR before the
5090 * next vcpu entry. Sending a notification event in
5091 * this case has no effect, as vcpu is not in root
5094 * Case 3: vcpu exits to root mode and is blocked.
5095 * vcpu_block() has already synced PIR to vIRR and
5096 * never blocks vcpu if vIRR is not cleared. Therefore,
5097 * a blocked vcpu here does not wait for any requested
5098 * interrupts in PIR, and sending a notification event
5099 * which has no effect is safe here.
5102 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5109 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5112 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5114 if (is_guest_mode(vcpu
) &&
5115 vector
== vmx
->nested
.posted_intr_nv
) {
5116 /* the PIR and ON have been set by L1. */
5117 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5119 * If a posted intr is not recognized by hardware,
5120 * we will accomplish it in the next vmentry.
5122 vmx
->nested
.pi_pending
= true;
5123 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5129 * Send interrupt to vcpu via posted interrupt way.
5130 * 1. If target vcpu is running(non-root mode), send posted interrupt
5131 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5132 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5133 * interrupt from PIR in next vmentry.
5135 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5137 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5140 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5144 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5147 /* If a previous notification has sent the IPI, nothing to do. */
5148 if (pi_test_and_set_on(&vmx
->pi_desc
))
5151 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5152 kvm_vcpu_kick(vcpu
);
5156 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5157 * will not change in the lifetime of the guest.
5158 * Note that host-state that does change is set elsewhere. E.g., host-state
5159 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5161 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5166 unsigned long cr0
, cr3
, cr4
;
5169 WARN_ON(cr0
& X86_CR0_TS
);
5170 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5173 * Save the most likely value for this task's CR3 in the VMCS.
5174 * We can't use __get_current_cr3_fast() because we're not atomic.
5177 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5178 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5180 /* Save the most likely value for this task's CR4 in the VMCS. */
5181 cr4
= cr4_read_shadow();
5182 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5183 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5185 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5186 #ifdef CONFIG_X86_64
5188 * Load null selectors, so we can avoid reloading them in
5189 * __vmx_load_host_state(), in case userspace uses the null selectors
5190 * too (the expected case).
5192 vmcs_write16(HOST_DS_SELECTOR
, 0);
5193 vmcs_write16(HOST_ES_SELECTOR
, 0);
5195 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5196 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5198 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5199 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5202 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5203 vmx
->host_idt_base
= dt
.address
;
5205 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5207 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5208 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5209 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5210 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5212 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5213 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5214 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5218 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5220 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5222 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5223 if (is_guest_mode(&vmx
->vcpu
))
5224 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5225 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5226 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5229 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5231 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5233 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5234 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5235 /* Enable the preemption timer dynamically */
5236 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5237 return pin_based_exec_ctrl
;
5240 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5242 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5244 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5245 if (cpu_has_secondary_exec_ctrls()) {
5246 if (kvm_vcpu_apicv_active(vcpu
))
5247 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5248 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5249 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5251 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5252 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5253 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5256 if (cpu_has_vmx_msr_bitmap())
5257 vmx_set_msr_bitmap(vcpu
);
5260 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5262 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5264 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5265 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5267 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5268 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5269 #ifdef CONFIG_X86_64
5270 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5271 CPU_BASED_CR8_LOAD_EXITING
;
5275 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5276 CPU_BASED_CR3_LOAD_EXITING
|
5277 CPU_BASED_INVLPG_EXITING
;
5278 return exec_control
;
5281 static bool vmx_rdrand_supported(void)
5283 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5284 SECONDARY_EXEC_RDRAND_EXITING
;
5287 static bool vmx_rdseed_supported(void)
5289 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5290 SECONDARY_EXEC_RDSEED_EXITING
;
5293 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5295 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5297 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5298 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5299 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5301 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5303 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5304 enable_unrestricted_guest
= 0;
5305 /* Enable INVPCID for non-ept guests may cause performance regression. */
5306 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5308 if (!enable_unrestricted_guest
)
5309 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5311 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5312 if (!kvm_vcpu_apicv_active(vcpu
))
5313 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5314 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5315 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5316 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5318 We can NOT enable shadow_vmcs here because we don't have yet
5321 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5324 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5326 if (vmx_xsaves_supported()) {
5327 /* Exposing XSAVES only when XSAVE is exposed */
5328 bool xsaves_enabled
=
5329 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5330 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5332 if (!xsaves_enabled
)
5333 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5337 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5338 SECONDARY_EXEC_XSAVES
;
5340 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5341 ~SECONDARY_EXEC_XSAVES
;
5345 if (vmx_rdtscp_supported()) {
5346 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5347 if (!rdtscp_enabled
)
5348 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5352 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5353 SECONDARY_EXEC_RDTSCP
;
5355 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5356 ~SECONDARY_EXEC_RDTSCP
;
5360 if (vmx_invpcid_supported()) {
5361 /* Exposing INVPCID only when PCID is exposed */
5362 bool invpcid_enabled
=
5363 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5364 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5366 if (!invpcid_enabled
) {
5367 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5368 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5372 if (invpcid_enabled
)
5373 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5374 SECONDARY_EXEC_ENABLE_INVPCID
;
5376 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5377 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5381 if (vmx_rdrand_supported()) {
5382 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5384 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5388 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5389 SECONDARY_EXEC_RDRAND_EXITING
;
5391 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5392 ~SECONDARY_EXEC_RDRAND_EXITING
;
5396 if (vmx_rdseed_supported()) {
5397 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5399 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5403 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5404 SECONDARY_EXEC_RDSEED_EXITING
;
5406 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5407 ~SECONDARY_EXEC_RDSEED_EXITING
;
5411 vmx
->secondary_exec_control
= exec_control
;
5414 static void ept_set_mmio_spte_mask(void)
5417 * EPT Misconfigurations can be generated if the value of bits 2:0
5418 * of an EPT paging-structure entry is 110b (write/execute).
5420 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5421 VMX_EPT_MISCONFIG_WX_VALUE
);
5424 #define VMX_XSS_EXIT_BITMAP 0
5426 * Sets up the vmcs for emulated real mode.
5428 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5430 #ifdef CONFIG_X86_64
5436 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5437 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5439 if (enable_shadow_vmcs
) {
5440 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5441 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5443 if (cpu_has_vmx_msr_bitmap())
5444 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5446 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5449 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5450 vmx
->hv_deadline_tsc
= -1;
5452 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5454 if (cpu_has_secondary_exec_ctrls()) {
5455 vmx_compute_secondary_exec_control(vmx
);
5456 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5457 vmx
->secondary_exec_control
);
5460 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5461 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5462 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5463 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5464 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5466 vmcs_write16(GUEST_INTR_STATUS
, 0);
5468 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5469 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5473 vmcs_write32(PLE_GAP
, ple_gap
);
5474 vmx
->ple_window
= ple_window
;
5475 vmx
->ple_window_dirty
= true;
5478 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5479 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5480 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5482 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5483 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5484 vmx_set_constant_host_state(vmx
);
5485 #ifdef CONFIG_X86_64
5486 rdmsrl(MSR_FS_BASE
, a
);
5487 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5488 rdmsrl(MSR_GS_BASE
, a
);
5489 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5491 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5492 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5495 if (cpu_has_vmx_vmfunc())
5496 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5498 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5499 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5500 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5501 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5502 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5504 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5505 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5507 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5508 u32 index
= vmx_msr_index
[i
];
5509 u32 data_low
, data_high
;
5512 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5514 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5516 vmx
->guest_msrs
[j
].index
= i
;
5517 vmx
->guest_msrs
[j
].data
= 0;
5518 vmx
->guest_msrs
[j
].mask
= -1ull;
5523 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5525 /* 22.2.1, 20.8.1 */
5526 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5528 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5529 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5531 set_cr4_guest_host_mask(vmx
);
5533 if (vmx_xsaves_supported())
5534 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5537 ASSERT(vmx
->pml_pg
);
5538 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5539 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5543 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5545 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5546 struct msr_data apic_base_msr
;
5549 vmx
->rmode
.vm86_active
= 0;
5551 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5552 kvm_set_cr8(vcpu
, 0);
5555 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5556 MSR_IA32_APICBASE_ENABLE
;
5557 if (kvm_vcpu_is_reset_bsp(vcpu
))
5558 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5559 apic_base_msr
.host_initiated
= true;
5560 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5563 vmx_segment_cache_clear(vmx
);
5565 seg_setup(VCPU_SREG_CS
);
5566 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5567 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5569 seg_setup(VCPU_SREG_DS
);
5570 seg_setup(VCPU_SREG_ES
);
5571 seg_setup(VCPU_SREG_FS
);
5572 seg_setup(VCPU_SREG_GS
);
5573 seg_setup(VCPU_SREG_SS
);
5575 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5576 vmcs_writel(GUEST_TR_BASE
, 0);
5577 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5578 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5580 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5581 vmcs_writel(GUEST_LDTR_BASE
, 0);
5582 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5583 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5586 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5587 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5588 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5589 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5592 vmcs_writel(GUEST_RFLAGS
, 0x02);
5593 kvm_rip_write(vcpu
, 0xfff0);
5595 vmcs_writel(GUEST_GDTR_BASE
, 0);
5596 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5598 vmcs_writel(GUEST_IDTR_BASE
, 0);
5599 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5601 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5602 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5603 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5604 if (kvm_mpx_supported())
5605 vmcs_write64(GUEST_BNDCFGS
, 0);
5609 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5611 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5612 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5613 if (cpu_need_tpr_shadow(vcpu
))
5614 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5615 __pa(vcpu
->arch
.apic
->regs
));
5616 vmcs_write32(TPR_THRESHOLD
, 0);
5619 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5622 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5624 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5625 vmx
->vcpu
.arch
.cr0
= cr0
;
5626 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5627 vmx_set_cr4(vcpu
, 0);
5628 vmx_set_efer(vcpu
, 0);
5630 update_exception_bitmap(vcpu
);
5632 vpid_sync_context(vmx
->vpid
);
5636 * In nested virtualization, check if L1 asked to exit on external interrupts.
5637 * For most existing hypervisors, this will always return true.
5639 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5641 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5642 PIN_BASED_EXT_INTR_MASK
;
5646 * In nested virtualization, check if L1 has set
5647 * VM_EXIT_ACK_INTR_ON_EXIT
5649 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5651 return get_vmcs12(vcpu
)->vm_exit_controls
&
5652 VM_EXIT_ACK_INTR_ON_EXIT
;
5655 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5657 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5658 PIN_BASED_NMI_EXITING
;
5661 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5663 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5664 CPU_BASED_VIRTUAL_INTR_PENDING
);
5667 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5669 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5670 enable_irq_window(vcpu
);
5674 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5675 CPU_BASED_VIRTUAL_NMI_PENDING
);
5678 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5680 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5682 int irq
= vcpu
->arch
.interrupt
.nr
;
5684 trace_kvm_inj_virq(irq
);
5686 ++vcpu
->stat
.irq_injections
;
5687 if (vmx
->rmode
.vm86_active
) {
5689 if (vcpu
->arch
.interrupt
.soft
)
5690 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5691 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5692 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5695 intr
= irq
| INTR_INFO_VALID_MASK
;
5696 if (vcpu
->arch
.interrupt
.soft
) {
5697 intr
|= INTR_TYPE_SOFT_INTR
;
5698 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5699 vmx
->vcpu
.arch
.event_exit_inst_len
);
5701 intr
|= INTR_TYPE_EXT_INTR
;
5702 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5705 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5707 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5709 ++vcpu
->stat
.nmi_injections
;
5710 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5712 if (vmx
->rmode
.vm86_active
) {
5713 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5714 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5718 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5719 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5722 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5724 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5727 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5729 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5730 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5734 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5736 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5738 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5740 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5741 GUEST_INTR_STATE_NMI
);
5743 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5744 GUEST_INTR_STATE_NMI
);
5747 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5749 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5752 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5753 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5754 | GUEST_INTR_STATE_NMI
));
5757 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5759 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5760 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5761 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5762 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5765 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5769 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5773 kvm
->arch
.tss_addr
= addr
;
5774 return init_rmode_tss(kvm
);
5777 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5782 * Update instruction length as we may reinject the exception
5783 * from user space while in guest debugging mode.
5785 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5786 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5787 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5791 if (vcpu
->guest_debug
&
5792 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5809 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5810 int vec
, u32 err_code
)
5813 * Instruction with address size override prefix opcode 0x67
5814 * Cause the #SS fault with 0 error code in VM86 mode.
5816 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5817 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5818 if (vcpu
->arch
.halt_request
) {
5819 vcpu
->arch
.halt_request
= 0;
5820 return kvm_vcpu_halt(vcpu
);
5828 * Forward all other exceptions that are valid in real mode.
5829 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5830 * the required debugging infrastructure rework.
5832 kvm_queue_exception(vcpu
, vec
);
5837 * Trigger machine check on the host. We assume all the MSRs are already set up
5838 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5839 * We pass a fake environment to the machine check handler because we want
5840 * the guest to be always treated like user space, no matter what context
5841 * it used internally.
5843 static void kvm_machine_check(void)
5845 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5846 struct pt_regs regs
= {
5847 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5848 .flags
= X86_EFLAGS_IF
,
5851 do_machine_check(®s
, 0);
5855 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5857 /* already handled by vcpu_run */
5861 static int handle_exception(struct kvm_vcpu
*vcpu
)
5863 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5864 struct kvm_run
*kvm_run
= vcpu
->run
;
5865 u32 intr_info
, ex_no
, error_code
;
5866 unsigned long cr2
, rip
, dr6
;
5868 enum emulation_result er
;
5870 vect_info
= vmx
->idt_vectoring_info
;
5871 intr_info
= vmx
->exit_intr_info
;
5873 if (is_machine_check(intr_info
))
5874 return handle_machine_check(vcpu
);
5876 if (is_nmi(intr_info
))
5877 return 1; /* already handled by vmx_vcpu_run() */
5879 if (is_invalid_opcode(intr_info
)) {
5880 if (is_guest_mode(vcpu
)) {
5881 kvm_queue_exception(vcpu
, UD_VECTOR
);
5884 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5885 if (er
!= EMULATE_DONE
)
5886 kvm_queue_exception(vcpu
, UD_VECTOR
);
5891 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5892 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5895 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5896 * MMIO, it is better to report an internal error.
5897 * See the comments in vmx_handle_exit.
5899 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5900 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5901 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5902 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5903 vcpu
->run
->internal
.ndata
= 3;
5904 vcpu
->run
->internal
.data
[0] = vect_info
;
5905 vcpu
->run
->internal
.data
[1] = intr_info
;
5906 vcpu
->run
->internal
.data
[2] = error_code
;
5910 if (is_page_fault(intr_info
)) {
5911 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5912 /* EPT won't cause page fault directly */
5913 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5914 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
5917 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5919 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5920 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5924 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5927 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5928 if (!(vcpu
->guest_debug
&
5929 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5930 vcpu
->arch
.dr6
&= ~15;
5931 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5932 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5933 skip_emulated_instruction(vcpu
);
5935 kvm_queue_exception(vcpu
, DB_VECTOR
);
5938 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5939 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5943 * Update instruction length as we may reinject #BP from
5944 * user space while in guest debugging mode. Reading it for
5945 * #DB as well causes no harm, it is not used in that case.
5947 vmx
->vcpu
.arch
.event_exit_inst_len
=
5948 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5949 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5950 rip
= kvm_rip_read(vcpu
);
5951 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5952 kvm_run
->debug
.arch
.exception
= ex_no
;
5955 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5956 kvm_run
->ex
.exception
= ex_no
;
5957 kvm_run
->ex
.error_code
= error_code
;
5963 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5965 ++vcpu
->stat
.irq_exits
;
5969 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5971 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5972 vcpu
->mmio_needed
= 0;
5976 static int handle_io(struct kvm_vcpu
*vcpu
)
5978 unsigned long exit_qualification
;
5979 int size
, in
, string
, ret
;
5982 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5983 string
= (exit_qualification
& 16) != 0;
5984 in
= (exit_qualification
& 8) != 0;
5986 ++vcpu
->stat
.io_exits
;
5989 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5991 port
= exit_qualification
>> 16;
5992 size
= (exit_qualification
& 7) + 1;
5994 ret
= kvm_skip_emulated_instruction(vcpu
);
5997 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5998 * KVM_EXIT_DEBUG here.
6000 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6004 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6007 * Patch in the VMCALL instruction:
6009 hypercall
[0] = 0x0f;
6010 hypercall
[1] = 0x01;
6011 hypercall
[2] = 0xc1;
6014 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6015 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6017 if (is_guest_mode(vcpu
)) {
6018 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6019 unsigned long orig_val
= val
;
6022 * We get here when L2 changed cr0 in a way that did not change
6023 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6024 * but did change L0 shadowed bits. So we first calculate the
6025 * effective cr0 value that L1 would like to write into the
6026 * hardware. It consists of the L2-owned bits from the new
6027 * value combined with the L1-owned bits from L1's guest_cr0.
6029 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6030 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6032 if (!nested_guest_cr0_valid(vcpu
, val
))
6035 if (kvm_set_cr0(vcpu
, val
))
6037 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6040 if (to_vmx(vcpu
)->nested
.vmxon
&&
6041 !nested_host_cr0_valid(vcpu
, val
))
6044 return kvm_set_cr0(vcpu
, val
);
6048 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6050 if (is_guest_mode(vcpu
)) {
6051 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6052 unsigned long orig_val
= val
;
6054 /* analogously to handle_set_cr0 */
6055 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6056 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6057 if (kvm_set_cr4(vcpu
, val
))
6059 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6062 return kvm_set_cr4(vcpu
, val
);
6065 static int handle_cr(struct kvm_vcpu
*vcpu
)
6067 unsigned long exit_qualification
, val
;
6073 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6074 cr
= exit_qualification
& 15;
6075 reg
= (exit_qualification
>> 8) & 15;
6076 switch ((exit_qualification
>> 4) & 3) {
6077 case 0: /* mov to cr */
6078 val
= kvm_register_readl(vcpu
, reg
);
6079 trace_kvm_cr_write(cr
, val
);
6082 err
= handle_set_cr0(vcpu
, val
);
6083 return kvm_complete_insn_gp(vcpu
, err
);
6085 err
= kvm_set_cr3(vcpu
, val
);
6086 return kvm_complete_insn_gp(vcpu
, err
);
6088 err
= handle_set_cr4(vcpu
, val
);
6089 return kvm_complete_insn_gp(vcpu
, err
);
6091 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6093 err
= kvm_set_cr8(vcpu
, cr8
);
6094 ret
= kvm_complete_insn_gp(vcpu
, err
);
6095 if (lapic_in_kernel(vcpu
))
6097 if (cr8_prev
<= cr8
)
6100 * TODO: we might be squashing a
6101 * KVM_GUESTDBG_SINGLESTEP-triggered
6102 * KVM_EXIT_DEBUG here.
6104 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6110 WARN_ONCE(1, "Guest should always own CR0.TS");
6111 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6112 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6113 return kvm_skip_emulated_instruction(vcpu
);
6114 case 1: /*mov from cr*/
6117 val
= kvm_read_cr3(vcpu
);
6118 kvm_register_write(vcpu
, reg
, val
);
6119 trace_kvm_cr_read(cr
, val
);
6120 return kvm_skip_emulated_instruction(vcpu
);
6122 val
= kvm_get_cr8(vcpu
);
6123 kvm_register_write(vcpu
, reg
, val
);
6124 trace_kvm_cr_read(cr
, val
);
6125 return kvm_skip_emulated_instruction(vcpu
);
6129 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6130 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6131 kvm_lmsw(vcpu
, val
);
6133 return kvm_skip_emulated_instruction(vcpu
);
6137 vcpu
->run
->exit_reason
= 0;
6138 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6139 (int)(exit_qualification
>> 4) & 3, cr
);
6143 static int handle_dr(struct kvm_vcpu
*vcpu
)
6145 unsigned long exit_qualification
;
6148 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6149 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6151 /* First, if DR does not exist, trigger UD */
6152 if (!kvm_require_dr(vcpu
, dr
))
6155 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6156 if (!kvm_require_cpl(vcpu
, 0))
6158 dr7
= vmcs_readl(GUEST_DR7
);
6161 * As the vm-exit takes precedence over the debug trap, we
6162 * need to emulate the latter, either for the host or the
6163 * guest debugging itself.
6165 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6166 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6167 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6168 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6169 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6170 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6173 vcpu
->arch
.dr6
&= ~15;
6174 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6175 kvm_queue_exception(vcpu
, DB_VECTOR
);
6180 if (vcpu
->guest_debug
== 0) {
6181 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6182 CPU_BASED_MOV_DR_EXITING
);
6185 * No more DR vmexits; force a reload of the debug registers
6186 * and reenter on this instruction. The next vmexit will
6187 * retrieve the full state of the debug registers.
6189 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6193 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6194 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6197 if (kvm_get_dr(vcpu
, dr
, &val
))
6199 kvm_register_write(vcpu
, reg
, val
);
6201 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6204 return kvm_skip_emulated_instruction(vcpu
);
6207 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6209 return vcpu
->arch
.dr6
;
6212 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6216 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6218 get_debugreg(vcpu
->arch
.db
[0], 0);
6219 get_debugreg(vcpu
->arch
.db
[1], 1);
6220 get_debugreg(vcpu
->arch
.db
[2], 2);
6221 get_debugreg(vcpu
->arch
.db
[3], 3);
6222 get_debugreg(vcpu
->arch
.dr6
, 6);
6223 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6225 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6226 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6229 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6231 vmcs_writel(GUEST_DR7
, val
);
6234 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6236 return kvm_emulate_cpuid(vcpu
);
6239 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6241 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6242 struct msr_data msr_info
;
6244 msr_info
.index
= ecx
;
6245 msr_info
.host_initiated
= false;
6246 if (vmx_get_msr(vcpu
, &msr_info
)) {
6247 trace_kvm_msr_read_ex(ecx
);
6248 kvm_inject_gp(vcpu
, 0);
6252 trace_kvm_msr_read(ecx
, msr_info
.data
);
6254 /* FIXME: handling of bits 32:63 of rax, rdx */
6255 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6256 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6257 return kvm_skip_emulated_instruction(vcpu
);
6260 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6262 struct msr_data msr
;
6263 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6264 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6265 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6269 msr
.host_initiated
= false;
6270 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6271 trace_kvm_msr_write_ex(ecx
, data
);
6272 kvm_inject_gp(vcpu
, 0);
6276 trace_kvm_msr_write(ecx
, data
);
6277 return kvm_skip_emulated_instruction(vcpu
);
6280 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6282 kvm_apic_update_ppr(vcpu
);
6286 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6288 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6289 CPU_BASED_VIRTUAL_INTR_PENDING
);
6291 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6293 ++vcpu
->stat
.irq_window_exits
;
6297 static int handle_halt(struct kvm_vcpu
*vcpu
)
6299 return kvm_emulate_halt(vcpu
);
6302 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6304 return kvm_emulate_hypercall(vcpu
);
6307 static int handle_invd(struct kvm_vcpu
*vcpu
)
6309 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6312 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6314 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6316 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6317 return kvm_skip_emulated_instruction(vcpu
);
6320 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6324 err
= kvm_rdpmc(vcpu
);
6325 return kvm_complete_insn_gp(vcpu
, err
);
6328 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6330 return kvm_emulate_wbinvd(vcpu
);
6333 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6335 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6336 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6338 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6339 return kvm_skip_emulated_instruction(vcpu
);
6343 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6345 kvm_skip_emulated_instruction(vcpu
);
6346 WARN(1, "this should never happen\n");
6350 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6352 kvm_skip_emulated_instruction(vcpu
);
6353 WARN(1, "this should never happen\n");
6357 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6359 if (likely(fasteoi
)) {
6360 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6361 int access_type
, offset
;
6363 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6364 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6366 * Sane guest uses MOV to write EOI, with written value
6367 * not cared. So make a short-circuit here by avoiding
6368 * heavy instruction emulation.
6370 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6371 (offset
== APIC_EOI
)) {
6372 kvm_lapic_set_eoi(vcpu
);
6373 return kvm_skip_emulated_instruction(vcpu
);
6376 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6379 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6381 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6382 int vector
= exit_qualification
& 0xff;
6384 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6385 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6389 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6391 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6392 u32 offset
= exit_qualification
& 0xfff;
6394 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6395 kvm_apic_write_nodecode(vcpu
, offset
);
6399 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6401 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6402 unsigned long exit_qualification
;
6403 bool has_error_code
= false;
6406 int reason
, type
, idt_v
, idt_index
;
6408 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6409 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6410 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6412 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6414 reason
= (u32
)exit_qualification
>> 30;
6415 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6417 case INTR_TYPE_NMI_INTR
:
6418 vcpu
->arch
.nmi_injected
= false;
6419 vmx_set_nmi_mask(vcpu
, true);
6421 case INTR_TYPE_EXT_INTR
:
6422 case INTR_TYPE_SOFT_INTR
:
6423 kvm_clear_interrupt_queue(vcpu
);
6425 case INTR_TYPE_HARD_EXCEPTION
:
6426 if (vmx
->idt_vectoring_info
&
6427 VECTORING_INFO_DELIVER_CODE_MASK
) {
6428 has_error_code
= true;
6430 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6433 case INTR_TYPE_SOFT_EXCEPTION
:
6434 kvm_clear_exception_queue(vcpu
);
6440 tss_selector
= exit_qualification
;
6442 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6443 type
!= INTR_TYPE_EXT_INTR
&&
6444 type
!= INTR_TYPE_NMI_INTR
))
6445 skip_emulated_instruction(vcpu
);
6447 if (kvm_task_switch(vcpu
, tss_selector
,
6448 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6449 has_error_code
, error_code
) == EMULATE_FAIL
) {
6450 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6451 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6452 vcpu
->run
->internal
.ndata
= 0;
6457 * TODO: What about debug traps on tss switch?
6458 * Are we supposed to inject them and update dr6?
6464 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6466 unsigned long exit_qualification
;
6470 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6473 * EPT violation happened while executing iret from NMI,
6474 * "blocked by NMI" bit has to be set before next VM entry.
6475 * There are errata that may cause this bit to not be set:
6478 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6479 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6480 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6482 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6483 trace_kvm_page_fault(gpa
, exit_qualification
);
6485 /* Is it a read fault? */
6486 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6487 ? PFERR_USER_MASK
: 0;
6488 /* Is it a write fault? */
6489 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6490 ? PFERR_WRITE_MASK
: 0;
6491 /* Is it a fetch fault? */
6492 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6493 ? PFERR_FETCH_MASK
: 0;
6494 /* ept page table entry is present? */
6495 error_code
|= (exit_qualification
&
6496 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6497 EPT_VIOLATION_EXECUTABLE
))
6498 ? PFERR_PRESENT_MASK
: 0;
6500 error_code
|= (exit_qualification
& 0x100) != 0 ?
6501 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6503 vcpu
->arch
.exit_qualification
= exit_qualification
;
6504 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6507 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6513 * A nested guest cannot optimize MMIO vmexits, because we have an
6514 * nGPA here instead of the required GPA.
6516 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6517 if (!is_guest_mode(vcpu
) &&
6518 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6519 trace_kvm_fast_mmio(gpa
);
6520 return kvm_skip_emulated_instruction(vcpu
);
6523 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6527 /* It is the real ept misconfig */
6530 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6531 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6536 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6538 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6539 CPU_BASED_VIRTUAL_NMI_PENDING
);
6540 ++vcpu
->stat
.nmi_window_exits
;
6541 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6546 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6549 enum emulation_result err
= EMULATE_DONE
;
6552 bool intr_window_requested
;
6553 unsigned count
= 130;
6555 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6556 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6558 while (vmx
->emulation_required
&& count
-- != 0) {
6559 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6560 return handle_interrupt_window(&vmx
->vcpu
);
6562 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6565 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6567 if (err
== EMULATE_USER_EXIT
) {
6568 ++vcpu
->stat
.mmio_exits
;
6573 if (err
!= EMULATE_DONE
) {
6574 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6575 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6576 vcpu
->run
->internal
.ndata
= 0;
6580 if (vcpu
->arch
.halt_request
) {
6581 vcpu
->arch
.halt_request
= 0;
6582 ret
= kvm_vcpu_halt(vcpu
);
6586 if (signal_pending(current
))
6596 static int __grow_ple_window(int val
)
6598 if (ple_window_grow
< 1)
6601 val
= min(val
, ple_window_actual_max
);
6603 if (ple_window_grow
< ple_window
)
6604 val
*= ple_window_grow
;
6606 val
+= ple_window_grow
;
6611 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6616 if (modifier
< ple_window
)
6621 return max(val
, minimum
);
6624 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6626 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6627 int old
= vmx
->ple_window
;
6629 vmx
->ple_window
= __grow_ple_window(old
);
6631 if (vmx
->ple_window
!= old
)
6632 vmx
->ple_window_dirty
= true;
6634 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6637 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6639 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6640 int old
= vmx
->ple_window
;
6642 vmx
->ple_window
= __shrink_ple_window(old
,
6643 ple_window_shrink
, ple_window
);
6645 if (vmx
->ple_window
!= old
)
6646 vmx
->ple_window_dirty
= true;
6648 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6652 * ple_window_actual_max is computed to be one grow_ple_window() below
6653 * ple_window_max. (See __grow_ple_window for the reason.)
6654 * This prevents overflows, because ple_window_max is int.
6655 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6657 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6659 static void update_ple_window_actual_max(void)
6661 ple_window_actual_max
=
6662 __shrink_ple_window(max(ple_window_max
, ple_window
),
6663 ple_window_grow
, INT_MIN
);
6667 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6669 static void wakeup_handler(void)
6671 struct kvm_vcpu
*vcpu
;
6672 int cpu
= smp_processor_id();
6674 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6675 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6676 blocked_vcpu_list
) {
6677 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6679 if (pi_test_on(pi_desc
) == 1)
6680 kvm_vcpu_kick(vcpu
);
6682 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6685 void vmx_enable_tdp(void)
6687 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6688 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6689 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6690 0ull, VMX_EPT_EXECUTABLE_MASK
,
6691 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6692 VMX_EPT_RWX_MASK
, 0ull);
6694 ept_set_mmio_spte_mask();
6698 static __init
int hardware_setup(void)
6700 int r
= -ENOMEM
, i
, msr
;
6702 rdmsrl_safe(MSR_EFER
, &host_efer
);
6704 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6705 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6707 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6708 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6713 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6714 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6715 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6718 * Allow direct access to the PC debug port (it is often used for I/O
6719 * delays, but the vmexits simply slow things down).
6721 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6722 clear_bit(0x80, vmx_io_bitmap_a
);
6724 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6726 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6727 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6729 if (setup_vmcs_config(&vmcs_config
) < 0) {
6734 if (boot_cpu_has(X86_FEATURE_NX
))
6735 kvm_enable_efer_bits(EFER_NX
);
6737 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6738 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6741 if (!cpu_has_vmx_shadow_vmcs())
6742 enable_shadow_vmcs
= 0;
6743 if (enable_shadow_vmcs
)
6744 init_vmcs_shadow_fields();
6746 if (!cpu_has_vmx_ept() ||
6747 !cpu_has_vmx_ept_4levels() ||
6748 !cpu_has_vmx_ept_mt_wb() ||
6749 !cpu_has_vmx_invept_global())
6752 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6753 enable_ept_ad_bits
= 0;
6755 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
6756 enable_unrestricted_guest
= 0;
6758 if (!cpu_has_vmx_flexpriority())
6759 flexpriority_enabled
= 0;
6762 * set_apic_access_page_addr() is used to reload apic access
6763 * page upon invalidation. No need to do anything if not
6764 * using the APIC_ACCESS_ADDR VMCS field.
6766 if (!flexpriority_enabled
)
6767 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6769 if (!cpu_has_vmx_tpr_shadow())
6770 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6772 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6773 kvm_disable_largepages();
6775 if (!cpu_has_vmx_ple()) {
6778 ple_window_grow
= 0;
6780 ple_window_shrink
= 0;
6783 if (!cpu_has_vmx_apicv()) {
6785 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6788 if (cpu_has_vmx_tsc_scaling()) {
6789 kvm_has_tsc_control
= true;
6790 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6791 kvm_tsc_scaling_ratio_frac_bits
= 48;
6794 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6795 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6796 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6797 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6798 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6799 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6801 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6802 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6803 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6804 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6805 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6806 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6807 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6808 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6810 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6812 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6813 if (msr
== 0x839 /* TMCCT */)
6815 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6819 * TPR reads and writes can be virtualized even if virtual interrupt
6820 * delivery is not in use.
6822 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6823 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6826 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6828 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6835 update_ple_window_actual_max();
6838 * Only enable PML when hardware supports PML feature, and both EPT
6839 * and EPT A/D bit features are enabled -- PML depends on them to work.
6841 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6845 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6846 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6847 kvm_x86_ops
->flush_log_dirty
= NULL
;
6848 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6851 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6854 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6855 cpu_preemption_timer_multi
=
6856 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6858 kvm_x86_ops
->set_hv_timer
= NULL
;
6859 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6862 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6864 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6866 return alloc_kvm_area();
6869 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6870 free_page((unsigned long)vmx_bitmap
[i
]);
6875 static __exit
void hardware_unsetup(void)
6879 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6880 free_page((unsigned long)vmx_bitmap
[i
]);
6886 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6887 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6889 static int handle_pause(struct kvm_vcpu
*vcpu
)
6892 grow_ple_window(vcpu
);
6895 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6896 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6897 * never set PAUSE_EXITING and just set PLE if supported,
6898 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6900 kvm_vcpu_on_spin(vcpu
, true);
6901 return kvm_skip_emulated_instruction(vcpu
);
6904 static int handle_nop(struct kvm_vcpu
*vcpu
)
6906 return kvm_skip_emulated_instruction(vcpu
);
6909 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6911 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6912 return handle_nop(vcpu
);
6915 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6917 kvm_queue_exception(vcpu
, UD_VECTOR
);
6921 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6926 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6928 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6929 return handle_nop(vcpu
);
6933 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6934 * We could reuse a single VMCS for all the L2 guests, but we also want the
6935 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6936 * allows keeping them loaded on the processor, and in the future will allow
6937 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6938 * every entry if they never change.
6939 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6940 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6942 * The following functions allocate and free a vmcs02 in this pool.
6945 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6946 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6948 struct vmcs02_list
*item
;
6949 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6950 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6951 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6952 return &item
->vmcs02
;
6955 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6956 /* Recycle the least recently used VMCS. */
6957 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6958 struct vmcs02_list
, list
);
6959 item
->vmptr
= vmx
->nested
.current_vmptr
;
6960 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6961 return &item
->vmcs02
;
6964 /* Create a new VMCS */
6965 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6968 item
->vmcs02
.vmcs
= alloc_vmcs();
6969 item
->vmcs02
.shadow_vmcs
= NULL
;
6970 if (!item
->vmcs02
.vmcs
) {
6974 loaded_vmcs_init(&item
->vmcs02
);
6975 item
->vmptr
= vmx
->nested
.current_vmptr
;
6976 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6977 vmx
->nested
.vmcs02_num
++;
6978 return &item
->vmcs02
;
6981 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6982 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6984 struct vmcs02_list
*item
;
6985 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6986 if (item
->vmptr
== vmptr
) {
6987 free_loaded_vmcs(&item
->vmcs02
);
6988 list_del(&item
->list
);
6990 vmx
->nested
.vmcs02_num
--;
6996 * Free all VMCSs saved for this vcpu, except the one pointed by
6997 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6998 * must be &vmx->vmcs01.
7000 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
7002 struct vmcs02_list
*item
, *n
;
7004 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7005 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7007 * Something will leak if the above WARN triggers. Better than
7010 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7013 free_loaded_vmcs(&item
->vmcs02
);
7014 list_del(&item
->list
);
7016 vmx
->nested
.vmcs02_num
--;
7021 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7022 * set the success or error code of an emulated VMX instruction, as specified
7023 * by Vol 2B, VMX Instruction Reference, "Conventions".
7025 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7027 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7028 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7029 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7032 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7034 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7035 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7036 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7040 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7041 u32 vm_instruction_error
)
7043 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7045 * failValid writes the error number to the current VMCS, which
7046 * can't be done there isn't a current VMCS.
7048 nested_vmx_failInvalid(vcpu
);
7051 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7052 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7053 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7055 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7057 * We don't need to force a shadow sync because
7058 * VM_INSTRUCTION_ERROR is not shadowed
7062 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7064 /* TODO: not to reset guest simply here. */
7065 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7066 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7069 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7071 struct vcpu_vmx
*vmx
=
7072 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7074 vmx
->nested
.preemption_timer_expired
= true;
7075 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7076 kvm_vcpu_kick(&vmx
->vcpu
);
7078 return HRTIMER_NORESTART
;
7082 * Decode the memory-address operand of a vmx instruction, as recorded on an
7083 * exit caused by such an instruction (run by a guest hypervisor).
7084 * On success, returns 0. When the operand is invalid, returns 1 and throws
7087 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7088 unsigned long exit_qualification
,
7089 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7093 struct kvm_segment s
;
7096 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7097 * Execution", on an exit, vmx_instruction_info holds most of the
7098 * addressing components of the operand. Only the displacement part
7099 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7100 * For how an actual address is calculated from all these components,
7101 * refer to Vol. 1, "Operand Addressing".
7103 int scaling
= vmx_instruction_info
& 3;
7104 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7105 bool is_reg
= vmx_instruction_info
& (1u << 10);
7106 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7107 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7108 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7109 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7110 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7113 kvm_queue_exception(vcpu
, UD_VECTOR
);
7117 /* Addr = segment_base + offset */
7118 /* offset = base + [index * scale] + displacement */
7119 off
= exit_qualification
; /* holds the displacement */
7121 off
+= kvm_register_read(vcpu
, base_reg
);
7123 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7124 vmx_get_segment(vcpu
, &s
, seg_reg
);
7125 *ret
= s
.base
+ off
;
7127 if (addr_size
== 1) /* 32 bit */
7130 /* Checks for #GP/#SS exceptions. */
7132 if (is_long_mode(vcpu
)) {
7133 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7134 * non-canonical form. This is the only check on the memory
7135 * destination for long mode!
7137 exn
= is_noncanonical_address(*ret
, vcpu
);
7138 } else if (is_protmode(vcpu
)) {
7139 /* Protected mode: apply checks for segment validity in the
7141 * - segment type check (#GP(0) may be thrown)
7142 * - usability check (#GP(0)/#SS(0))
7143 * - limit check (#GP(0)/#SS(0))
7146 /* #GP(0) if the destination operand is located in a
7147 * read-only data segment or any code segment.
7149 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7151 /* #GP(0) if the source operand is located in an
7152 * execute-only code segment
7154 exn
= ((s
.type
& 0xa) == 8);
7156 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7159 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7161 exn
= (s
.unusable
!= 0);
7162 /* Protected mode: #GP(0)/#SS(0) if the memory
7163 * operand is outside the segment limit.
7165 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7168 kvm_queue_exception_e(vcpu
,
7169 seg_reg
== VCPU_SREG_SS
?
7170 SS_VECTOR
: GP_VECTOR
,
7178 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7181 struct x86_exception e
;
7183 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7184 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7187 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7188 sizeof(*vmpointer
), &e
)) {
7189 kvm_inject_page_fault(vcpu
, &e
);
7196 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7198 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7199 struct vmcs
*shadow_vmcs
;
7201 if (cpu_has_vmx_msr_bitmap()) {
7202 vmx
->nested
.msr_bitmap
=
7203 (unsigned long *)__get_free_page(GFP_KERNEL
);
7204 if (!vmx
->nested
.msr_bitmap
)
7205 goto out_msr_bitmap
;
7208 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7209 if (!vmx
->nested
.cached_vmcs12
)
7210 goto out_cached_vmcs12
;
7212 if (enable_shadow_vmcs
) {
7213 shadow_vmcs
= alloc_vmcs();
7215 goto out_shadow_vmcs
;
7216 /* mark vmcs as shadow */
7217 shadow_vmcs
->revision_id
|= (1u << 31);
7218 /* init shadow vmcs */
7219 vmcs_clear(shadow_vmcs
);
7220 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7223 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7224 vmx
->nested
.vmcs02_num
= 0;
7226 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7227 HRTIMER_MODE_REL_PINNED
);
7228 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7230 vmx
->nested
.vmxon
= true;
7234 kfree(vmx
->nested
.cached_vmcs12
);
7237 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7244 * Emulate the VMXON instruction.
7245 * Currently, we just remember that VMX is active, and do not save or even
7246 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7247 * do not currently need to store anything in that guest-allocated memory
7248 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7249 * argument is different from the VMXON pointer (which the spec says they do).
7251 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7257 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7258 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7261 * The Intel VMX Instruction Reference lists a bunch of bits that are
7262 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7263 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7264 * Otherwise, we should fail with #UD. But most faulting conditions
7265 * have already been checked by hardware, prior to the VM-exit for
7266 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7267 * that bit set to 1 in non-root mode.
7269 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7270 kvm_queue_exception(vcpu
, UD_VECTOR
);
7274 if (vmx
->nested
.vmxon
) {
7275 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7276 return kvm_skip_emulated_instruction(vcpu
);
7279 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7280 != VMXON_NEEDED_FEATURES
) {
7281 kvm_inject_gp(vcpu
, 0);
7285 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7290 * The first 4 bytes of VMXON region contain the supported
7291 * VMCS revision identifier
7293 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7294 * which replaces physical address width with 32
7296 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7297 nested_vmx_failInvalid(vcpu
);
7298 return kvm_skip_emulated_instruction(vcpu
);
7301 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7302 if (is_error_page(page
)) {
7303 nested_vmx_failInvalid(vcpu
);
7304 return kvm_skip_emulated_instruction(vcpu
);
7306 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7308 kvm_release_page_clean(page
);
7309 nested_vmx_failInvalid(vcpu
);
7310 return kvm_skip_emulated_instruction(vcpu
);
7313 kvm_release_page_clean(page
);
7315 vmx
->nested
.vmxon_ptr
= vmptr
;
7316 ret
= enter_vmx_operation(vcpu
);
7320 nested_vmx_succeed(vcpu
);
7321 return kvm_skip_emulated_instruction(vcpu
);
7325 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7326 * for running VMX instructions (except VMXON, whose prerequisites are
7327 * slightly different). It also specifies what exception to inject otherwise.
7328 * Note that many of these exceptions have priority over VM exits, so they
7329 * don't have to be checked again here.
7331 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7333 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7334 kvm_queue_exception(vcpu
, UD_VECTOR
);
7340 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7342 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7343 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7346 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7348 if (vmx
->nested
.current_vmptr
== -1ull)
7351 if (enable_shadow_vmcs
) {
7352 /* copy to memory all shadowed fields in case
7353 they were modified */
7354 copy_shadow_to_vmcs12(vmx
);
7355 vmx
->nested
.sync_shadow_vmcs
= false;
7356 vmx_disable_shadow_vmcs(vmx
);
7358 vmx
->nested
.posted_intr_nv
= -1;
7360 /* Flush VMCS12 to guest memory */
7361 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7362 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7363 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7365 vmx
->nested
.current_vmptr
= -1ull;
7369 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7370 * just stops using VMX.
7372 static void free_nested(struct vcpu_vmx
*vmx
)
7374 if (!vmx
->nested
.vmxon
)
7377 vmx
->nested
.vmxon
= false;
7378 free_vpid(vmx
->nested
.vpid02
);
7379 vmx
->nested
.posted_intr_nv
= -1;
7380 vmx
->nested
.current_vmptr
= -1ull;
7381 if (vmx
->nested
.msr_bitmap
) {
7382 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7383 vmx
->nested
.msr_bitmap
= NULL
;
7385 if (enable_shadow_vmcs
) {
7386 vmx_disable_shadow_vmcs(vmx
);
7387 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7388 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7389 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7391 kfree(vmx
->nested
.cached_vmcs12
);
7392 /* Unpin physical memory we referred to in current vmcs02 */
7393 if (vmx
->nested
.apic_access_page
) {
7394 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7395 vmx
->nested
.apic_access_page
= NULL
;
7397 if (vmx
->nested
.virtual_apic_page
) {
7398 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7399 vmx
->nested
.virtual_apic_page
= NULL
;
7401 if (vmx
->nested
.pi_desc_page
) {
7402 kunmap(vmx
->nested
.pi_desc_page
);
7403 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7404 vmx
->nested
.pi_desc_page
= NULL
;
7405 vmx
->nested
.pi_desc
= NULL
;
7408 nested_free_all_saved_vmcss(vmx
);
7411 /* Emulate the VMXOFF instruction */
7412 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7414 if (!nested_vmx_check_permission(vcpu
))
7416 free_nested(to_vmx(vcpu
));
7417 nested_vmx_succeed(vcpu
);
7418 return kvm_skip_emulated_instruction(vcpu
);
7421 /* Emulate the VMCLEAR instruction */
7422 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7424 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7428 if (!nested_vmx_check_permission(vcpu
))
7431 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7434 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7435 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7436 return kvm_skip_emulated_instruction(vcpu
);
7439 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7440 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7441 return kvm_skip_emulated_instruction(vcpu
);
7444 if (vmptr
== vmx
->nested
.current_vmptr
)
7445 nested_release_vmcs12(vmx
);
7447 kvm_vcpu_write_guest(vcpu
,
7448 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7449 &zero
, sizeof(zero
));
7451 nested_free_vmcs02(vmx
, vmptr
);
7453 nested_vmx_succeed(vcpu
);
7454 return kvm_skip_emulated_instruction(vcpu
);
7457 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7459 /* Emulate the VMLAUNCH instruction */
7460 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7462 return nested_vmx_run(vcpu
, true);
7465 /* Emulate the VMRESUME instruction */
7466 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7469 return nested_vmx_run(vcpu
, false);
7473 * Read a vmcs12 field. Since these can have varying lengths and we return
7474 * one type, we chose the biggest type (u64) and zero-extend the return value
7475 * to that size. Note that the caller, handle_vmread, might need to use only
7476 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7477 * 64-bit fields are to be returned).
7479 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7480 unsigned long field
, u64
*ret
)
7482 short offset
= vmcs_field_to_offset(field
);
7488 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7490 switch (vmcs_field_type(field
)) {
7491 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7492 *ret
= *((natural_width
*)p
);
7494 case VMCS_FIELD_TYPE_U16
:
7497 case VMCS_FIELD_TYPE_U32
:
7500 case VMCS_FIELD_TYPE_U64
:
7510 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7511 unsigned long field
, u64 field_value
){
7512 short offset
= vmcs_field_to_offset(field
);
7513 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7517 switch (vmcs_field_type(field
)) {
7518 case VMCS_FIELD_TYPE_U16
:
7519 *(u16
*)p
= field_value
;
7521 case VMCS_FIELD_TYPE_U32
:
7522 *(u32
*)p
= field_value
;
7524 case VMCS_FIELD_TYPE_U64
:
7525 *(u64
*)p
= field_value
;
7527 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7528 *(natural_width
*)p
= field_value
;
7537 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7540 unsigned long field
;
7542 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7543 const unsigned long *fields
= shadow_read_write_fields
;
7544 const int num_fields
= max_shadow_read_write_fields
;
7548 vmcs_load(shadow_vmcs
);
7550 for (i
= 0; i
< num_fields
; i
++) {
7552 switch (vmcs_field_type(field
)) {
7553 case VMCS_FIELD_TYPE_U16
:
7554 field_value
= vmcs_read16(field
);
7556 case VMCS_FIELD_TYPE_U32
:
7557 field_value
= vmcs_read32(field
);
7559 case VMCS_FIELD_TYPE_U64
:
7560 field_value
= vmcs_read64(field
);
7562 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7563 field_value
= vmcs_readl(field
);
7569 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7572 vmcs_clear(shadow_vmcs
);
7573 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7578 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7580 const unsigned long *fields
[] = {
7581 shadow_read_write_fields
,
7582 shadow_read_only_fields
7584 const int max_fields
[] = {
7585 max_shadow_read_write_fields
,
7586 max_shadow_read_only_fields
7589 unsigned long field
;
7590 u64 field_value
= 0;
7591 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7593 vmcs_load(shadow_vmcs
);
7595 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7596 for (i
= 0; i
< max_fields
[q
]; i
++) {
7597 field
= fields
[q
][i
];
7598 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7600 switch (vmcs_field_type(field
)) {
7601 case VMCS_FIELD_TYPE_U16
:
7602 vmcs_write16(field
, (u16
)field_value
);
7604 case VMCS_FIELD_TYPE_U32
:
7605 vmcs_write32(field
, (u32
)field_value
);
7607 case VMCS_FIELD_TYPE_U64
:
7608 vmcs_write64(field
, (u64
)field_value
);
7610 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7611 vmcs_writel(field
, (long)field_value
);
7620 vmcs_clear(shadow_vmcs
);
7621 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7625 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7626 * used before) all generate the same failure when it is missing.
7628 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7631 if (vmx
->nested
.current_vmptr
== -1ull) {
7632 nested_vmx_failInvalid(vcpu
);
7638 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7640 unsigned long field
;
7642 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7643 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7646 if (!nested_vmx_check_permission(vcpu
))
7649 if (!nested_vmx_check_vmcs12(vcpu
))
7650 return kvm_skip_emulated_instruction(vcpu
);
7652 /* Decode instruction info and find the field to read */
7653 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7654 /* Read the field, zero-extended to a u64 field_value */
7655 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7656 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7657 return kvm_skip_emulated_instruction(vcpu
);
7660 * Now copy part of this value to register or memory, as requested.
7661 * Note that the number of bits actually copied is 32 or 64 depending
7662 * on the guest's mode (32 or 64 bit), not on the given field's length.
7664 if (vmx_instruction_info
& (1u << 10)) {
7665 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7668 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7669 vmx_instruction_info
, true, &gva
))
7671 /* _system ok, as hardware has verified cpl=0 */
7672 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7673 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7676 nested_vmx_succeed(vcpu
);
7677 return kvm_skip_emulated_instruction(vcpu
);
7681 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7683 unsigned long field
;
7685 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7686 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7687 /* The value to write might be 32 or 64 bits, depending on L1's long
7688 * mode, and eventually we need to write that into a field of several
7689 * possible lengths. The code below first zero-extends the value to 64
7690 * bit (field_value), and then copies only the appropriate number of
7691 * bits into the vmcs12 field.
7693 u64 field_value
= 0;
7694 struct x86_exception e
;
7696 if (!nested_vmx_check_permission(vcpu
))
7699 if (!nested_vmx_check_vmcs12(vcpu
))
7700 return kvm_skip_emulated_instruction(vcpu
);
7702 if (vmx_instruction_info
& (1u << 10))
7703 field_value
= kvm_register_readl(vcpu
,
7704 (((vmx_instruction_info
) >> 3) & 0xf));
7706 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7707 vmx_instruction_info
, false, &gva
))
7709 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7710 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7711 kvm_inject_page_fault(vcpu
, &e
);
7717 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7718 if (vmcs_field_readonly(field
)) {
7719 nested_vmx_failValid(vcpu
,
7720 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7721 return kvm_skip_emulated_instruction(vcpu
);
7724 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7725 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7726 return kvm_skip_emulated_instruction(vcpu
);
7729 nested_vmx_succeed(vcpu
);
7730 return kvm_skip_emulated_instruction(vcpu
);
7733 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7735 vmx
->nested
.current_vmptr
= vmptr
;
7736 if (enable_shadow_vmcs
) {
7737 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7738 SECONDARY_EXEC_SHADOW_VMCS
);
7739 vmcs_write64(VMCS_LINK_POINTER
,
7740 __pa(vmx
->vmcs01
.shadow_vmcs
));
7741 vmx
->nested
.sync_shadow_vmcs
= true;
7745 /* Emulate the VMPTRLD instruction */
7746 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7748 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7751 if (!nested_vmx_check_permission(vcpu
))
7754 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7757 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7758 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7759 return kvm_skip_emulated_instruction(vcpu
);
7762 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7763 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7764 return kvm_skip_emulated_instruction(vcpu
);
7767 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7768 struct vmcs12
*new_vmcs12
;
7770 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7771 if (is_error_page(page
)) {
7772 nested_vmx_failInvalid(vcpu
);
7773 return kvm_skip_emulated_instruction(vcpu
);
7775 new_vmcs12
= kmap(page
);
7776 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7778 kvm_release_page_clean(page
);
7779 nested_vmx_failValid(vcpu
,
7780 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7781 return kvm_skip_emulated_instruction(vcpu
);
7784 nested_release_vmcs12(vmx
);
7786 * Load VMCS12 from guest memory since it is not already
7789 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7791 kvm_release_page_clean(page
);
7793 set_current_vmptr(vmx
, vmptr
);
7796 nested_vmx_succeed(vcpu
);
7797 return kvm_skip_emulated_instruction(vcpu
);
7800 /* Emulate the VMPTRST instruction */
7801 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7803 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7804 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7806 struct x86_exception e
;
7808 if (!nested_vmx_check_permission(vcpu
))
7811 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7812 vmx_instruction_info
, true, &vmcs_gva
))
7814 /* ok to use *_system, as hardware has verified cpl=0 */
7815 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7816 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7818 kvm_inject_page_fault(vcpu
, &e
);
7821 nested_vmx_succeed(vcpu
);
7822 return kvm_skip_emulated_instruction(vcpu
);
7825 /* Emulate the INVEPT instruction */
7826 static int handle_invept(struct kvm_vcpu
*vcpu
)
7828 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7829 u32 vmx_instruction_info
, types
;
7832 struct x86_exception e
;
7837 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7838 SECONDARY_EXEC_ENABLE_EPT
) ||
7839 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7840 kvm_queue_exception(vcpu
, UD_VECTOR
);
7844 if (!nested_vmx_check_permission(vcpu
))
7847 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7848 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7850 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7852 if (type
>= 32 || !(types
& (1 << type
))) {
7853 nested_vmx_failValid(vcpu
,
7854 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7855 return kvm_skip_emulated_instruction(vcpu
);
7858 /* According to the Intel VMX instruction reference, the memory
7859 * operand is read even if it isn't needed (e.g., for type==global)
7861 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7862 vmx_instruction_info
, false, &gva
))
7864 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7865 sizeof(operand
), &e
)) {
7866 kvm_inject_page_fault(vcpu
, &e
);
7871 case VMX_EPT_EXTENT_GLOBAL
:
7873 * TODO: track mappings and invalidate
7874 * single context requests appropriately
7876 case VMX_EPT_EXTENT_CONTEXT
:
7877 kvm_mmu_sync_roots(vcpu
);
7878 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7879 nested_vmx_succeed(vcpu
);
7886 return kvm_skip_emulated_instruction(vcpu
);
7889 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7891 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7892 u32 vmx_instruction_info
;
7893 unsigned long type
, types
;
7895 struct x86_exception e
;
7901 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7902 SECONDARY_EXEC_ENABLE_VPID
) ||
7903 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7904 kvm_queue_exception(vcpu
, UD_VECTOR
);
7908 if (!nested_vmx_check_permission(vcpu
))
7911 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7912 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7914 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7915 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7917 if (type
>= 32 || !(types
& (1 << type
))) {
7918 nested_vmx_failValid(vcpu
,
7919 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7920 return kvm_skip_emulated_instruction(vcpu
);
7923 /* according to the intel vmx instruction reference, the memory
7924 * operand is read even if it isn't needed (e.g., for type==global)
7926 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7927 vmx_instruction_info
, false, &gva
))
7929 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7930 sizeof(operand
), &e
)) {
7931 kvm_inject_page_fault(vcpu
, &e
);
7934 if (operand
.vpid
>> 16) {
7935 nested_vmx_failValid(vcpu
,
7936 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7937 return kvm_skip_emulated_instruction(vcpu
);
7941 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7942 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7943 nested_vmx_failValid(vcpu
,
7944 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7945 return kvm_skip_emulated_instruction(vcpu
);
7948 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7949 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7950 if (!operand
.vpid
) {
7951 nested_vmx_failValid(vcpu
,
7952 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7953 return kvm_skip_emulated_instruction(vcpu
);
7956 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7960 return kvm_skip_emulated_instruction(vcpu
);
7963 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7964 nested_vmx_succeed(vcpu
);
7966 return kvm_skip_emulated_instruction(vcpu
);
7969 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7971 unsigned long exit_qualification
;
7973 trace_kvm_pml_full(vcpu
->vcpu_id
);
7975 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7978 * PML buffer FULL happened while executing iret from NMI,
7979 * "blocked by NMI" bit has to be set before next VM entry.
7981 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7982 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7983 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7984 GUEST_INTR_STATE_NMI
);
7987 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7988 * here.., and there's no userspace involvement needed for PML.
7993 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7995 kvm_lapic_expired_hv_timer(vcpu
);
7999 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8001 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8002 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8004 /* Check for memory type validity */
8005 switch (address
& VMX_EPTP_MT_MASK
) {
8006 case VMX_EPTP_MT_UC
:
8007 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8010 case VMX_EPTP_MT_WB
:
8011 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8018 /* only 4 levels page-walk length are valid */
8019 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8022 /* Reserved bits should not be set */
8023 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8026 /* AD, if set, should be supported */
8027 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8028 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8035 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8036 struct vmcs12
*vmcs12
)
8038 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8040 bool accessed_dirty
;
8041 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8043 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8044 !nested_cpu_has_ept(vmcs12
))
8047 if (index
>= VMFUNC_EPTP_ENTRIES
)
8051 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8052 &address
, index
* 8, 8))
8055 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8058 * If the (L2) guest does a vmfunc to the currently
8059 * active ept pointer, we don't have to do anything else
8061 if (vmcs12
->ept_pointer
!= address
) {
8062 if (!valid_ept_address(vcpu
, address
))
8065 kvm_mmu_unload(vcpu
);
8066 mmu
->ept_ad
= accessed_dirty
;
8067 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8068 vmcs12
->ept_pointer
= address
;
8070 * TODO: Check what's the correct approach in case
8071 * mmu reload fails. Currently, we just let the next
8072 * reload potentially fail
8074 kvm_mmu_reload(vcpu
);
8080 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8082 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8083 struct vmcs12
*vmcs12
;
8084 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8087 * VMFUNC is only supported for nested guests, but we always enable the
8088 * secondary control for simplicity; for non-nested mode, fake that we
8089 * didn't by injecting #UD.
8091 if (!is_guest_mode(vcpu
)) {
8092 kvm_queue_exception(vcpu
, UD_VECTOR
);
8096 vmcs12
= get_vmcs12(vcpu
);
8097 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8102 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8108 return kvm_skip_emulated_instruction(vcpu
);
8111 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8112 vmcs_read32(VM_EXIT_INTR_INFO
),
8113 vmcs_readl(EXIT_QUALIFICATION
));
8118 * The exit handlers return 1 if the exit was handled fully and guest execution
8119 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8120 * to be done to userspace and return 0.
8122 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8123 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8124 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8125 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8126 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8127 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8128 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8129 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8130 [EXIT_REASON_CPUID
] = handle_cpuid
,
8131 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8132 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8133 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8134 [EXIT_REASON_HLT
] = handle_halt
,
8135 [EXIT_REASON_INVD
] = handle_invd
,
8136 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8137 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8138 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8139 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8140 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8141 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8142 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8143 [EXIT_REASON_VMREAD
] = handle_vmread
,
8144 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8145 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8146 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8147 [EXIT_REASON_VMON
] = handle_vmon
,
8148 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8149 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8150 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8151 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8152 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8153 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8154 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8155 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8156 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8157 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8158 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8159 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8160 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8161 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8162 [EXIT_REASON_INVEPT
] = handle_invept
,
8163 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8164 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8165 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8166 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8167 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8168 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8169 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8170 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8173 static const int kvm_vmx_max_exit_handlers
=
8174 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8176 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8177 struct vmcs12
*vmcs12
)
8179 unsigned long exit_qualification
;
8180 gpa_t bitmap
, last_bitmap
;
8185 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8186 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8188 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8190 port
= exit_qualification
>> 16;
8191 size
= (exit_qualification
& 7) + 1;
8193 last_bitmap
= (gpa_t
)-1;
8198 bitmap
= vmcs12
->io_bitmap_a
;
8199 else if (port
< 0x10000)
8200 bitmap
= vmcs12
->io_bitmap_b
;
8203 bitmap
+= (port
& 0x7fff) / 8;
8205 if (last_bitmap
!= bitmap
)
8206 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8208 if (b
& (1 << (port
& 7)))
8213 last_bitmap
= bitmap
;
8220 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8221 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8222 * disinterest in the current event (read or write a specific MSR) by using an
8223 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8225 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8226 struct vmcs12
*vmcs12
, u32 exit_reason
)
8228 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8231 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8235 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8236 * for the four combinations of read/write and low/high MSR numbers.
8237 * First we need to figure out which of the four to use:
8239 bitmap
= vmcs12
->msr_bitmap
;
8240 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8242 if (msr_index
>= 0xc0000000) {
8243 msr_index
-= 0xc0000000;
8247 /* Then read the msr_index'th bit from this bitmap: */
8248 if (msr_index
< 1024*8) {
8250 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8252 return 1 & (b
>> (msr_index
& 7));
8254 return true; /* let L1 handle the wrong parameter */
8258 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8259 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8260 * intercept (via guest_host_mask etc.) the current event.
8262 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8263 struct vmcs12
*vmcs12
)
8265 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8266 int cr
= exit_qualification
& 15;
8270 switch ((exit_qualification
>> 4) & 3) {
8271 case 0: /* mov to cr */
8272 reg
= (exit_qualification
>> 8) & 15;
8273 val
= kvm_register_readl(vcpu
, reg
);
8276 if (vmcs12
->cr0_guest_host_mask
&
8277 (val
^ vmcs12
->cr0_read_shadow
))
8281 if ((vmcs12
->cr3_target_count
>= 1 &&
8282 vmcs12
->cr3_target_value0
== val
) ||
8283 (vmcs12
->cr3_target_count
>= 2 &&
8284 vmcs12
->cr3_target_value1
== val
) ||
8285 (vmcs12
->cr3_target_count
>= 3 &&
8286 vmcs12
->cr3_target_value2
== val
) ||
8287 (vmcs12
->cr3_target_count
>= 4 &&
8288 vmcs12
->cr3_target_value3
== val
))
8290 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8294 if (vmcs12
->cr4_guest_host_mask
&
8295 (vmcs12
->cr4_read_shadow
^ val
))
8299 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8305 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8306 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8309 case 1: /* mov from cr */
8312 if (vmcs12
->cpu_based_vm_exec_control
&
8313 CPU_BASED_CR3_STORE_EXITING
)
8317 if (vmcs12
->cpu_based_vm_exec_control
&
8318 CPU_BASED_CR8_STORE_EXITING
)
8325 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8326 * cr0. Other attempted changes are ignored, with no exit.
8328 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8329 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8330 (val
^ vmcs12
->cr0_read_shadow
))
8332 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8333 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8342 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8343 * should handle it ourselves in L0 (and then continue L2). Only call this
8344 * when in is_guest_mode (L2).
8346 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8348 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8349 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8350 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8352 if (vmx
->nested
.nested_run_pending
)
8355 if (unlikely(vmx
->fail
)) {
8356 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8357 vmcs_read32(VM_INSTRUCTION_ERROR
));
8362 * The host physical addresses of some pages of guest memory
8363 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8364 * may write to these pages via their host physical address while
8365 * L2 is running, bypassing any address-translation-based dirty
8366 * tracking (e.g. EPT write protection).
8368 * Mark them dirty on every exit from L2 to prevent them from
8369 * getting out of sync with dirty tracking.
8371 nested_mark_vmcs12_pages_dirty(vcpu
);
8373 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8374 vmcs_readl(EXIT_QUALIFICATION
),
8375 vmx
->idt_vectoring_info
,
8377 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8380 switch (exit_reason
) {
8381 case EXIT_REASON_EXCEPTION_NMI
:
8382 if (is_nmi(intr_info
))
8384 else if (is_page_fault(intr_info
))
8385 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8386 else if (is_no_device(intr_info
) &&
8387 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8389 else if (is_debug(intr_info
) &&
8391 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8393 else if (is_breakpoint(intr_info
) &&
8394 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8396 return vmcs12
->exception_bitmap
&
8397 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8398 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8400 case EXIT_REASON_TRIPLE_FAULT
:
8402 case EXIT_REASON_PENDING_INTERRUPT
:
8403 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8404 case EXIT_REASON_NMI_WINDOW
:
8405 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8406 case EXIT_REASON_TASK_SWITCH
:
8408 case EXIT_REASON_CPUID
:
8410 case EXIT_REASON_HLT
:
8411 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8412 case EXIT_REASON_INVD
:
8414 case EXIT_REASON_INVLPG
:
8415 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8416 case EXIT_REASON_RDPMC
:
8417 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8418 case EXIT_REASON_RDRAND
:
8419 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8420 case EXIT_REASON_RDSEED
:
8421 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8422 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8423 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8424 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8425 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8426 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8427 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8428 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8429 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8431 * VMX instructions trap unconditionally. This allows L1 to
8432 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8435 case EXIT_REASON_CR_ACCESS
:
8436 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8437 case EXIT_REASON_DR_ACCESS
:
8438 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8439 case EXIT_REASON_IO_INSTRUCTION
:
8440 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8441 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8442 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8443 case EXIT_REASON_MSR_READ
:
8444 case EXIT_REASON_MSR_WRITE
:
8445 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8446 case EXIT_REASON_INVALID_STATE
:
8448 case EXIT_REASON_MWAIT_INSTRUCTION
:
8449 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8450 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8451 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8452 case EXIT_REASON_MONITOR_INSTRUCTION
:
8453 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8454 case EXIT_REASON_PAUSE_INSTRUCTION
:
8455 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8456 nested_cpu_has2(vmcs12
,
8457 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8458 case EXIT_REASON_MCE_DURING_VMENTRY
:
8460 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8461 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8462 case EXIT_REASON_APIC_ACCESS
:
8463 return nested_cpu_has2(vmcs12
,
8464 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8465 case EXIT_REASON_APIC_WRITE
:
8466 case EXIT_REASON_EOI_INDUCED
:
8467 /* apic_write and eoi_induced should exit unconditionally. */
8469 case EXIT_REASON_EPT_VIOLATION
:
8471 * L0 always deals with the EPT violation. If nested EPT is
8472 * used, and the nested mmu code discovers that the address is
8473 * missing in the guest EPT table (EPT12), the EPT violation
8474 * will be injected with nested_ept_inject_page_fault()
8477 case EXIT_REASON_EPT_MISCONFIG
:
8479 * L2 never uses directly L1's EPT, but rather L0's own EPT
8480 * table (shadow on EPT) or a merged EPT table that L0 built
8481 * (EPT on EPT). So any problems with the structure of the
8482 * table is L0's fault.
8485 case EXIT_REASON_INVPCID
:
8487 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8488 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8489 case EXIT_REASON_WBINVD
:
8490 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8491 case EXIT_REASON_XSETBV
:
8493 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8495 * This should never happen, since it is not possible to
8496 * set XSS to a non-zero value---neither in L1 nor in L2.
8497 * If if it were, XSS would have to be checked against
8498 * the XSS exit bitmap in vmcs12.
8500 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8501 case EXIT_REASON_PREEMPTION_TIMER
:
8503 case EXIT_REASON_PML_FULL
:
8504 /* We emulate PML support to L1. */
8506 case EXIT_REASON_VMFUNC
:
8507 /* VM functions are emulated through L2->L0 vmexits. */
8514 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8516 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8519 * At this point, the exit interruption info in exit_intr_info
8520 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8521 * we need to query the in-kernel LAPIC.
8523 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8524 if ((exit_intr_info
&
8525 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8526 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8527 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8528 vmcs12
->vm_exit_intr_error_code
=
8529 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8532 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8533 vmcs_readl(EXIT_QUALIFICATION
));
8537 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8539 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8540 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8543 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8546 __free_page(vmx
->pml_pg
);
8551 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8553 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8557 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8559 /* Do nothing if PML buffer is empty */
8560 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8563 /* PML index always points to next available PML buffer entity */
8564 if (pml_idx
>= PML_ENTITY_NUM
)
8569 pml_buf
= page_address(vmx
->pml_pg
);
8570 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8573 gpa
= pml_buf
[pml_idx
];
8574 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8575 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8578 /* reset PML index */
8579 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8583 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8584 * Called before reporting dirty_bitmap to userspace.
8586 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8589 struct kvm_vcpu
*vcpu
;
8591 * We only need to kick vcpu out of guest mode here, as PML buffer
8592 * is flushed at beginning of all VMEXITs, and it's obvious that only
8593 * vcpus running in guest are possible to have unflushed GPAs in PML
8596 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8597 kvm_vcpu_kick(vcpu
);
8600 static void vmx_dump_sel(char *name
, uint32_t sel
)
8602 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8603 name
, vmcs_read16(sel
),
8604 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8605 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8606 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8609 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8611 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8612 name
, vmcs_read32(limit
),
8613 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8616 static void dump_vmcs(void)
8618 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8619 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8620 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8621 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8622 u32 secondary_exec_control
= 0;
8623 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8624 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8627 if (cpu_has_secondary_exec_ctrls())
8628 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8630 pr_err("*** Guest State ***\n");
8631 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8632 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8633 vmcs_readl(CR0_GUEST_HOST_MASK
));
8634 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8635 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8636 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8637 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8638 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8640 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8641 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8642 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8643 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8645 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8646 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8647 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8648 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8649 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8650 vmcs_readl(GUEST_SYSENTER_ESP
),
8651 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8652 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8653 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8654 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8655 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8656 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8657 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8658 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8659 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8660 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8661 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8662 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8663 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8664 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8665 efer
, vmcs_read64(GUEST_IA32_PAT
));
8666 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8667 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8668 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8669 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8670 pr_err("PerfGlobCtl = 0x%016llx\n",
8671 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8672 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8673 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8674 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8675 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8676 vmcs_read32(GUEST_ACTIVITY_STATE
));
8677 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8678 pr_err("InterruptStatus = %04x\n",
8679 vmcs_read16(GUEST_INTR_STATUS
));
8681 pr_err("*** Host State ***\n");
8682 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8683 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8684 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8685 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8686 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8687 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8688 vmcs_read16(HOST_TR_SELECTOR
));
8689 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8690 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8691 vmcs_readl(HOST_TR_BASE
));
8692 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8693 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8694 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8695 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8696 vmcs_readl(HOST_CR4
));
8697 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8698 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8699 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8700 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8701 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8702 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8703 vmcs_read64(HOST_IA32_EFER
),
8704 vmcs_read64(HOST_IA32_PAT
));
8705 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8706 pr_err("PerfGlobCtl = 0x%016llx\n",
8707 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8709 pr_err("*** Control State ***\n");
8710 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8711 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8712 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8713 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8714 vmcs_read32(EXCEPTION_BITMAP
),
8715 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8716 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8717 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8718 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8719 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8720 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8721 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8722 vmcs_read32(VM_EXIT_INTR_INFO
),
8723 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8724 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8725 pr_err(" reason=%08x qualification=%016lx\n",
8726 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8727 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8728 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8729 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8730 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8731 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8732 pr_err("TSC Multiplier = 0x%016llx\n",
8733 vmcs_read64(TSC_MULTIPLIER
));
8734 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8735 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8736 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8737 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8738 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8739 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8740 n
= vmcs_read32(CR3_TARGET_COUNT
);
8741 for (i
= 0; i
+ 1 < n
; i
+= 4)
8742 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8743 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8744 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8746 pr_err("CR3 target%u=%016lx\n",
8747 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8748 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8749 pr_err("PLE Gap=%08x Window=%08x\n",
8750 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8751 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8752 pr_err("Virtual processor ID = 0x%04x\n",
8753 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8757 * The guest has exited. See if we can fix it or if we need userspace
8760 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8763 u32 exit_reason
= vmx
->exit_reason
;
8764 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8766 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8769 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8770 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8771 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8772 * mode as if vcpus is in root mode, the PML buffer must has been
8776 vmx_flush_pml_buffer(vcpu
);
8778 /* If guest state is invalid, start emulating */
8779 if (vmx
->emulation_required
)
8780 return handle_invalid_guest_state(vcpu
);
8782 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8783 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8785 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8787 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8788 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8793 if (unlikely(vmx
->fail
)) {
8794 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8795 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8796 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8802 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8803 * delivery event since it indicates guest is accessing MMIO.
8804 * The vm-exit can be triggered again after return to guest that
8805 * will cause infinite loop.
8807 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8808 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8809 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8810 exit_reason
!= EXIT_REASON_PML_FULL
&&
8811 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8812 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8813 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8814 vcpu
->run
->internal
.ndata
= 3;
8815 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8816 vcpu
->run
->internal
.data
[1] = exit_reason
;
8817 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8818 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8819 vcpu
->run
->internal
.ndata
++;
8820 vcpu
->run
->internal
.data
[3] =
8821 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8826 if (exit_reason
< kvm_vmx_max_exit_handlers
8827 && kvm_vmx_exit_handlers
[exit_reason
])
8828 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8830 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8832 kvm_queue_exception(vcpu
, UD_VECTOR
);
8837 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8839 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8841 if (is_guest_mode(vcpu
) &&
8842 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8845 if (irr
== -1 || tpr
< irr
) {
8846 vmcs_write32(TPR_THRESHOLD
, 0);
8850 vmcs_write32(TPR_THRESHOLD
, irr
);
8853 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8855 u32 sec_exec_control
;
8857 /* Postpone execution until vmcs01 is the current VMCS. */
8858 if (is_guest_mode(vcpu
)) {
8859 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8863 if (!cpu_has_vmx_virtualize_x2apic_mode())
8866 if (!cpu_need_tpr_shadow(vcpu
))
8869 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8872 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8873 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8875 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8876 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8877 vmx_flush_tlb_ept_only(vcpu
);
8879 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8881 vmx_set_msr_bitmap(vcpu
);
8884 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8886 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8889 * Currently we do not handle the nested case where L2 has an
8890 * APIC access page of its own; that page is still pinned.
8891 * Hence, we skip the case where the VCPU is in guest mode _and_
8892 * L1 prepared an APIC access page for L2.
8894 * For the case where L1 and L2 share the same APIC access page
8895 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8896 * in the vmcs12), this function will only update either the vmcs01
8897 * or the vmcs02. If the former, the vmcs02 will be updated by
8898 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8899 * the next L2->L1 exit.
8901 if (!is_guest_mode(vcpu
) ||
8902 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8903 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8904 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8905 vmx_flush_tlb_ept_only(vcpu
);
8909 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8917 status
= vmcs_read16(GUEST_INTR_STATUS
);
8919 if (max_isr
!= old
) {
8921 status
|= max_isr
<< 8;
8922 vmcs_write16(GUEST_INTR_STATUS
, status
);
8926 static void vmx_set_rvi(int vector
)
8934 status
= vmcs_read16(GUEST_INTR_STATUS
);
8935 old
= (u8
)status
& 0xff;
8936 if ((u8
)vector
!= old
) {
8938 status
|= (u8
)vector
;
8939 vmcs_write16(GUEST_INTR_STATUS
, status
);
8943 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8945 if (!is_guest_mode(vcpu
)) {
8946 vmx_set_rvi(max_irr
);
8954 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8957 if (nested_exit_on_intr(vcpu
))
8961 * Else, fall back to pre-APICv interrupt injection since L2
8962 * is run without virtual interrupt delivery.
8964 if (!kvm_event_needs_reinjection(vcpu
) &&
8965 vmx_interrupt_allowed(vcpu
)) {
8966 kvm_queue_interrupt(vcpu
, max_irr
, false);
8967 vmx_inject_irq(vcpu
);
8971 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8973 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8976 WARN_ON(!vcpu
->arch
.apicv_active
);
8977 if (pi_test_on(&vmx
->pi_desc
)) {
8978 pi_clear_on(&vmx
->pi_desc
);
8980 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8981 * But on x86 this is just a compiler barrier anyway.
8983 smp_mb__after_atomic();
8984 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8986 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8988 vmx_hwapic_irr_update(vcpu
, max_irr
);
8992 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8994 if (!kvm_vcpu_apicv_active(vcpu
))
8997 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8998 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8999 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9000 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9003 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9007 pi_clear_on(&vmx
->pi_desc
);
9008 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9011 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9013 u32 exit_intr_info
= 0;
9014 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9016 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9017 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9020 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9021 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9022 vmx
->exit_intr_info
= exit_intr_info
;
9024 /* if exit due to PF check for async PF */
9025 if (is_page_fault(exit_intr_info
))
9026 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9028 /* Handle machine checks before interrupts are enabled */
9029 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9030 is_machine_check(exit_intr_info
))
9031 kvm_machine_check();
9033 /* We need to handle NMIs before interrupts are enabled */
9034 if (is_nmi(exit_intr_info
)) {
9035 kvm_before_handle_nmi(&vmx
->vcpu
);
9037 kvm_after_handle_nmi(&vmx
->vcpu
);
9041 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9043 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9045 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9046 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9047 unsigned int vector
;
9048 unsigned long entry
;
9050 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9051 #ifdef CONFIG_X86_64
9055 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9056 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9057 entry
= gate_offset(desc
);
9059 #ifdef CONFIG_X86_64
9060 "mov %%" _ASM_SP
", %[sp]\n\t"
9061 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9066 __ASM_SIZE(push
) " $%c[cs]\n\t"
9067 "call *%[entry]\n\t"
9069 #ifdef CONFIG_X86_64
9075 [ss
]"i"(__KERNEL_DS
),
9076 [cs
]"i"(__KERNEL_CS
)
9080 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9082 static bool vmx_has_high_real_mode_segbase(void)
9084 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9087 static bool vmx_mpx_supported(void)
9089 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9090 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9093 static bool vmx_xsaves_supported(void)
9095 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9096 SECONDARY_EXEC_XSAVES
;
9099 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9104 bool idtv_info_valid
;
9106 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9108 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9111 * Can't use vmx->exit_intr_info since we're not sure what
9112 * the exit reason is.
9114 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9115 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9116 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9118 * SDM 3: 27.7.1.2 (September 2008)
9119 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9120 * a guest IRET fault.
9121 * SDM 3: 23.2.2 (September 2008)
9122 * Bit 12 is undefined in any of the following cases:
9123 * If the VM exit sets the valid bit in the IDT-vectoring
9124 * information field.
9125 * If the VM exit is due to a double fault.
9127 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9128 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9129 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9130 GUEST_INTR_STATE_NMI
);
9132 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9133 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9134 & GUEST_INTR_STATE_NMI
);
9137 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9138 u32 idt_vectoring_info
,
9139 int instr_len_field
,
9140 int error_code_field
)
9144 bool idtv_info_valid
;
9146 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9148 vcpu
->arch
.nmi_injected
= false;
9149 kvm_clear_exception_queue(vcpu
);
9150 kvm_clear_interrupt_queue(vcpu
);
9152 if (!idtv_info_valid
)
9155 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9157 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9158 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9161 case INTR_TYPE_NMI_INTR
:
9162 vcpu
->arch
.nmi_injected
= true;
9164 * SDM 3: 27.7.1.2 (September 2008)
9165 * Clear bit "block by NMI" before VM entry if a NMI
9168 vmx_set_nmi_mask(vcpu
, false);
9170 case INTR_TYPE_SOFT_EXCEPTION
:
9171 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9173 case INTR_TYPE_HARD_EXCEPTION
:
9174 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9175 u32 err
= vmcs_read32(error_code_field
);
9176 kvm_requeue_exception_e(vcpu
, vector
, err
);
9178 kvm_requeue_exception(vcpu
, vector
);
9180 case INTR_TYPE_SOFT_INTR
:
9181 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9183 case INTR_TYPE_EXT_INTR
:
9184 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9191 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9193 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9194 VM_EXIT_INSTRUCTION_LEN
,
9195 IDT_VECTORING_ERROR_CODE
);
9198 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9200 __vmx_complete_interrupts(vcpu
,
9201 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9202 VM_ENTRY_INSTRUCTION_LEN
,
9203 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9205 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9208 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9211 struct perf_guest_switch_msr
*msrs
;
9213 msrs
= perf_guest_get_msrs(&nr_msrs
);
9218 for (i
= 0; i
< nr_msrs
; i
++)
9219 if (msrs
[i
].host
== msrs
[i
].guest
)
9220 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9222 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9226 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9228 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9232 if (vmx
->hv_deadline_tsc
== -1)
9236 if (vmx
->hv_deadline_tsc
> tscl
)
9237 /* sure to be 32 bit only because checked on set_hv_timer */
9238 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9239 cpu_preemption_timer_multi
);
9243 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9246 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9248 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9249 unsigned long debugctlmsr
, cr3
, cr4
;
9251 /* Don't enter VMX if guest state is invalid, let the exit handler
9252 start emulation until we arrive back to a valid state */
9253 if (vmx
->emulation_required
)
9256 if (vmx
->ple_window_dirty
) {
9257 vmx
->ple_window_dirty
= false;
9258 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9261 if (vmx
->nested
.sync_shadow_vmcs
) {
9262 copy_vmcs12_to_shadow(vmx
);
9263 vmx
->nested
.sync_shadow_vmcs
= false;
9266 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9267 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9268 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9269 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9271 cr3
= __get_current_cr3_fast();
9272 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9273 vmcs_writel(HOST_CR3
, cr3
);
9274 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9277 cr4
= cr4_read_shadow();
9278 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9279 vmcs_writel(HOST_CR4
, cr4
);
9280 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9283 /* When single-stepping over STI and MOV SS, we must clear the
9284 * corresponding interruptibility bits in the guest state. Otherwise
9285 * vmentry fails as it then expects bit 14 (BS) in pending debug
9286 * exceptions being set, but that's not correct for the guest debugging
9288 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9289 vmx_set_interrupt_shadow(vcpu
, 0);
9291 if (static_cpu_has(X86_FEATURE_PKU
) &&
9292 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9293 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9294 __write_pkru(vcpu
->arch
.pkru
);
9296 atomic_switch_perf_msrs(vmx
);
9297 debugctlmsr
= get_debugctlmsr();
9299 vmx_arm_hv_timer(vcpu
);
9301 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9303 /* Store host registers */
9304 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9305 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9306 "push %%" _ASM_CX
" \n\t"
9307 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9309 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9310 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9312 /* Reload cr2 if changed */
9313 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9314 "mov %%cr2, %%" _ASM_DX
" \n\t"
9315 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9317 "mov %%" _ASM_AX
", %%cr2 \n\t"
9319 /* Check if vmlaunch of vmresume is needed */
9320 "cmpl $0, %c[launched](%0) \n\t"
9321 /* Load guest registers. Don't clobber flags. */
9322 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9323 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9324 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9325 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9326 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9327 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9328 #ifdef CONFIG_X86_64
9329 "mov %c[r8](%0), %%r8 \n\t"
9330 "mov %c[r9](%0), %%r9 \n\t"
9331 "mov %c[r10](%0), %%r10 \n\t"
9332 "mov %c[r11](%0), %%r11 \n\t"
9333 "mov %c[r12](%0), %%r12 \n\t"
9334 "mov %c[r13](%0), %%r13 \n\t"
9335 "mov %c[r14](%0), %%r14 \n\t"
9336 "mov %c[r15](%0), %%r15 \n\t"
9338 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9340 /* Enter guest mode */
9342 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9344 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9346 /* Save guest registers, load host registers, keep flags */
9347 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9349 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9350 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9351 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9352 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9353 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9354 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9355 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9356 #ifdef CONFIG_X86_64
9357 "mov %%r8, %c[r8](%0) \n\t"
9358 "mov %%r9, %c[r9](%0) \n\t"
9359 "mov %%r10, %c[r10](%0) \n\t"
9360 "mov %%r11, %c[r11](%0) \n\t"
9361 "mov %%r12, %c[r12](%0) \n\t"
9362 "mov %%r13, %c[r13](%0) \n\t"
9363 "mov %%r14, %c[r14](%0) \n\t"
9364 "mov %%r15, %c[r15](%0) \n\t"
9366 "mov %%cr2, %%" _ASM_AX
" \n\t"
9367 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9369 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9370 "setbe %c[fail](%0) \n\t"
9371 ".pushsection .rodata \n\t"
9372 ".global vmx_return \n\t"
9373 "vmx_return: " _ASM_PTR
" 2b \n\t"
9375 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9376 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9377 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9378 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9379 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9380 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9381 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9382 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9383 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9384 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9385 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9386 #ifdef CONFIG_X86_64
9387 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9388 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9389 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9390 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9391 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9392 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9393 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9394 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9396 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9397 [wordsize
]"i"(sizeof(ulong
))
9399 #ifdef CONFIG_X86_64
9400 , "rax", "rbx", "rdi", "rsi"
9401 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9403 , "eax", "ebx", "edi", "esi"
9407 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9409 update_debugctlmsr(debugctlmsr
);
9411 #ifndef CONFIG_X86_64
9413 * The sysexit path does not restore ds/es, so we must set them to
9414 * a reasonable value ourselves.
9416 * We can't defer this to vmx_load_host_state() since that function
9417 * may be executed in interrupt context, which saves and restore segments
9418 * around it, nullifying its effect.
9420 loadsegment(ds
, __USER_DS
);
9421 loadsegment(es
, __USER_DS
);
9424 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9425 | (1 << VCPU_EXREG_RFLAGS
)
9426 | (1 << VCPU_EXREG_PDPTR
)
9427 | (1 << VCPU_EXREG_SEGMENTS
)
9428 | (1 << VCPU_EXREG_CR3
));
9429 vcpu
->arch
.regs_dirty
= 0;
9432 * eager fpu is enabled if PKEY is supported and CR4 is switched
9433 * back on host, so it is safe to read guest PKRU from current
9436 if (static_cpu_has(X86_FEATURE_PKU
) &&
9437 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9438 vcpu
->arch
.pkru
= __read_pkru();
9439 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9440 __write_pkru(vmx
->host_pkru
);
9444 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9445 * we did not inject a still-pending event to L1 now because of
9446 * nested_run_pending, we need to re-enable this bit.
9448 if (vmx
->nested
.nested_run_pending
)
9449 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9451 vmx
->nested
.nested_run_pending
= 0;
9452 vmx
->idt_vectoring_info
= 0;
9454 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9455 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9458 vmx
->loaded_vmcs
->launched
= 1;
9459 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9461 vmx_complete_atomic_exit(vmx
);
9462 vmx_recover_nmi_blocking(vmx
);
9463 vmx_complete_interrupts(vmx
);
9465 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9467 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9472 if (vmx
->loaded_vmcs
== vmcs
)
9476 vmx
->loaded_vmcs
= vmcs
;
9478 vmx_vcpu_load(vcpu
, cpu
);
9483 * Ensure that the current vmcs of the logical processor is the
9484 * vmcs01 of the vcpu before calling free_nested().
9486 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9488 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9491 r
= vcpu_load(vcpu
);
9493 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9498 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9500 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9503 vmx_destroy_pml_buffer(vmx
);
9504 free_vpid(vmx
->vpid
);
9505 leave_guest_mode(vcpu
);
9506 vmx_free_vcpu_nested(vcpu
);
9507 free_loaded_vmcs(vmx
->loaded_vmcs
);
9508 kfree(vmx
->guest_msrs
);
9509 kvm_vcpu_uninit(vcpu
);
9510 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9513 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9516 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9520 return ERR_PTR(-ENOMEM
);
9522 vmx
->vpid
= allocate_vpid();
9524 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9531 * If PML is turned on, failure on enabling PML just results in failure
9532 * of creating the vcpu, therefore we can simplify PML logic (by
9533 * avoiding dealing with cases, such as enabling PML partially on vcpus
9534 * for the guest, etc.
9537 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9542 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9543 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9546 if (!vmx
->guest_msrs
)
9549 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9550 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9551 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9552 if (!vmx
->loaded_vmcs
->vmcs
)
9554 loaded_vmcs_init(vmx
->loaded_vmcs
);
9557 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9558 vmx
->vcpu
.cpu
= cpu
;
9559 vmx_vcpu_setup(vmx
);
9560 vmx_vcpu_put(&vmx
->vcpu
);
9562 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9563 err
= alloc_apic_access_page(kvm
);
9569 err
= init_rmode_identity_map(kvm
);
9575 nested_vmx_setup_ctls_msrs(vmx
);
9576 vmx
->nested
.vpid02
= allocate_vpid();
9579 vmx
->nested
.posted_intr_nv
= -1;
9580 vmx
->nested
.current_vmptr
= -1ull;
9582 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9585 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9586 * or POSTED_INTR_WAKEUP_VECTOR.
9588 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9589 vmx
->pi_desc
.sn
= 1;
9594 free_vpid(vmx
->nested
.vpid02
);
9595 free_loaded_vmcs(vmx
->loaded_vmcs
);
9597 kfree(vmx
->guest_msrs
);
9599 vmx_destroy_pml_buffer(vmx
);
9601 kvm_vcpu_uninit(&vmx
->vcpu
);
9603 free_vpid(vmx
->vpid
);
9604 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9605 return ERR_PTR(err
);
9608 static void __init
vmx_check_processor_compat(void *rtn
)
9610 struct vmcs_config vmcs_conf
;
9613 if (setup_vmcs_config(&vmcs_conf
) < 0)
9615 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9616 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9617 smp_processor_id());
9622 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9627 /* For VT-d and EPT combination
9628 * 1. MMIO: always map as UC
9630 * a. VT-d without snooping control feature: can't guarantee the
9631 * result, try to trust guest.
9632 * b. VT-d with snooping control feature: snooping control feature of
9633 * VT-d engine can guarantee the cache correctness. Just set it
9634 * to WB to keep consistent with host. So the same as item 3.
9635 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9636 * consistent with host MTRR
9639 cache
= MTRR_TYPE_UNCACHABLE
;
9643 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9644 ipat
= VMX_EPT_IPAT_BIT
;
9645 cache
= MTRR_TYPE_WRBACK
;
9649 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9650 ipat
= VMX_EPT_IPAT_BIT
;
9651 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9652 cache
= MTRR_TYPE_WRBACK
;
9654 cache
= MTRR_TYPE_UNCACHABLE
;
9658 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9661 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9664 static int vmx_get_lpage_level(void)
9666 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9667 return PT_DIRECTORY_LEVEL
;
9669 /* For shadow and EPT supported 1GB page */
9670 return PT_PDPE_LEVEL
;
9673 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9676 * These bits in the secondary execution controls field
9677 * are dynamic, the others are mostly based on the hypervisor
9678 * architecture and the guest's CPUID. Do not touch the
9682 SECONDARY_EXEC_SHADOW_VMCS
|
9683 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9684 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9686 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9688 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9689 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9693 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9694 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9696 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9698 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9699 struct kvm_cpuid_entry2
*entry
;
9701 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9702 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9704 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9705 if (entry && (entry->_reg & (_cpuid_mask))) \
9706 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9709 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9710 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9711 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9712 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9713 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9714 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9715 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9716 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9717 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9718 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9719 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9720 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9721 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9722 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9723 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9725 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9726 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9727 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9728 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9729 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9730 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9731 cr4_fixed1_update(bit(11), ecx
, bit(2));
9733 #undef cr4_fixed1_update
9736 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9738 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9740 if (cpu_has_secondary_exec_ctrls()) {
9741 vmx_compute_secondary_exec_control(vmx
);
9742 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9745 if (nested_vmx_allowed(vcpu
))
9746 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9747 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9749 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9750 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9752 if (nested_vmx_allowed(vcpu
))
9753 nested_vmx_cr_fixed1_bits_update(vcpu
);
9756 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9758 if (func
== 1 && nested
)
9759 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9762 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9763 struct x86_exception
*fault
)
9765 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9766 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9768 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9770 if (vmx
->nested
.pml_full
) {
9771 exit_reason
= EXIT_REASON_PML_FULL
;
9772 vmx
->nested
.pml_full
= false;
9773 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9774 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9775 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9777 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9779 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9780 vmcs12
->guest_physical_address
= fault
->address
;
9783 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9785 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9788 /* Callbacks for nested_ept_init_mmu_context: */
9790 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9792 /* return the page table to be shadowed - in our case, EPT12 */
9793 return get_vmcs12(vcpu
)->ept_pointer
;
9796 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9798 WARN_ON(mmu_is_nested(vcpu
));
9799 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9802 kvm_mmu_unload(vcpu
);
9803 kvm_init_shadow_ept_mmu(vcpu
,
9804 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9805 VMX_EPT_EXECUTE_ONLY_BIT
,
9806 nested_ept_ad_enabled(vcpu
));
9807 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9808 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9809 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9811 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9815 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9817 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9820 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9823 bool inequality
, bit
;
9825 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9827 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9828 vmcs12
->page_fault_error_code_match
;
9829 return inequality
^ bit
;
9832 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9833 struct x86_exception
*fault
)
9835 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9837 WARN_ON(!is_guest_mode(vcpu
));
9839 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9840 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9841 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9842 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9843 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9844 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9847 kvm_inject_page_fault(vcpu
, fault
);
9851 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9852 struct vmcs12
*vmcs12
);
9854 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9855 struct vmcs12
*vmcs12
)
9857 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9861 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9863 * Translate L1 physical address to host physical
9864 * address for vmcs02. Keep the page pinned, so this
9865 * physical address remains valid. We keep a reference
9866 * to it so we can release it later.
9868 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9869 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9870 vmx
->nested
.apic_access_page
= NULL
;
9872 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9874 * If translation failed, no matter: This feature asks
9875 * to exit when accessing the given address, and if it
9876 * can never be accessed, this feature won't do
9879 if (!is_error_page(page
)) {
9880 vmx
->nested
.apic_access_page
= page
;
9881 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9882 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9884 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9885 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9887 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9888 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9889 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9890 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9891 kvm_vcpu_reload_apic_access_page(vcpu
);
9894 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9895 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9896 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9897 vmx
->nested
.virtual_apic_page
= NULL
;
9899 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9902 * If translation failed, VM entry will fail because
9903 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9904 * Failing the vm entry is _not_ what the processor
9905 * does but it's basically the only possibility we
9906 * have. We could still enter the guest if CR8 load
9907 * exits are enabled, CR8 store exits are enabled, and
9908 * virtualize APIC access is disabled; in this case
9909 * the processor would never use the TPR shadow and we
9910 * could simply clear the bit from the execution
9911 * control. But such a configuration is useless, so
9912 * let's keep the code simple.
9914 if (!is_error_page(page
)) {
9915 vmx
->nested
.virtual_apic_page
= page
;
9916 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9917 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9921 if (nested_cpu_has_posted_intr(vmcs12
)) {
9922 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9923 kunmap(vmx
->nested
.pi_desc_page
);
9924 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
9925 vmx
->nested
.pi_desc_page
= NULL
;
9927 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9928 if (is_error_page(page
))
9930 vmx
->nested
.pi_desc_page
= page
;
9931 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
9932 vmx
->nested
.pi_desc
=
9933 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9934 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9936 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9937 page_to_phys(vmx
->nested
.pi_desc_page
) +
9938 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9941 if (cpu_has_vmx_msr_bitmap() &&
9942 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9943 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9946 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9947 CPU_BASED_USE_MSR_BITMAPS
);
9950 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9952 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9953 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9955 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9958 /* Make sure short timeouts reliably trigger an immediate vmexit.
9959 * hrtimer_start does not guarantee this. */
9960 if (preemption_timeout
<= 1) {
9961 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9965 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9966 preemption_timeout
*= 1000000;
9967 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9968 hrtimer_start(&vmx
->nested
.preemption_timer
,
9969 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9972 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9973 struct vmcs12
*vmcs12
)
9975 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9978 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9979 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9985 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9986 struct vmcs12
*vmcs12
)
9988 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9991 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9997 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
9998 struct vmcs12
*vmcs12
)
10000 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10003 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10010 * Merge L0's and L1's MSR bitmap, return false to indicate that
10011 * we do not use the hardware.
10013 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10014 struct vmcs12
*vmcs12
)
10018 unsigned long *msr_bitmap_l1
;
10019 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10021 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10022 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10025 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10026 if (is_error_page(page
))
10028 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10030 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10032 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10033 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10034 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10035 nested_vmx_disable_intercept_for_msr(
10036 msr_bitmap_l1
, msr_bitmap_l0
,
10039 nested_vmx_disable_intercept_for_msr(
10040 msr_bitmap_l1
, msr_bitmap_l0
,
10041 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10042 MSR_TYPE_R
| MSR_TYPE_W
);
10044 if (nested_cpu_has_vid(vmcs12
)) {
10045 nested_vmx_disable_intercept_for_msr(
10046 msr_bitmap_l1
, msr_bitmap_l0
,
10047 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10049 nested_vmx_disable_intercept_for_msr(
10050 msr_bitmap_l1
, msr_bitmap_l0
,
10051 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10056 kvm_release_page_clean(page
);
10061 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10062 struct vmcs12
*vmcs12
)
10064 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10065 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10066 !nested_cpu_has_vid(vmcs12
) &&
10067 !nested_cpu_has_posted_intr(vmcs12
))
10071 * If virtualize x2apic mode is enabled,
10072 * virtualize apic access must be disabled.
10074 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10075 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10079 * If virtual interrupt delivery is enabled,
10080 * we must exit on external interrupts.
10082 if (nested_cpu_has_vid(vmcs12
) &&
10083 !nested_exit_on_intr(vcpu
))
10087 * bits 15:8 should be zero in posted_intr_nv,
10088 * the descriptor address has been already checked
10089 * in nested_get_vmcs12_pages.
10091 if (nested_cpu_has_posted_intr(vmcs12
) &&
10092 (!nested_cpu_has_vid(vmcs12
) ||
10093 !nested_exit_intr_ack_set(vcpu
) ||
10094 vmcs12
->posted_intr_nv
& 0xff00))
10097 /* tpr shadow is needed by all apicv features. */
10098 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10104 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10105 unsigned long count_field
,
10106 unsigned long addr_field
)
10111 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10112 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10118 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10119 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10120 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10121 pr_debug_ratelimited(
10122 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10123 addr_field
, maxphyaddr
, count
, addr
);
10129 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10130 struct vmcs12
*vmcs12
)
10132 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10133 vmcs12
->vm_exit_msr_store_count
== 0 &&
10134 vmcs12
->vm_entry_msr_load_count
== 0)
10135 return 0; /* Fast path */
10136 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10137 VM_EXIT_MSR_LOAD_ADDR
) ||
10138 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10139 VM_EXIT_MSR_STORE_ADDR
) ||
10140 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10141 VM_ENTRY_MSR_LOAD_ADDR
))
10146 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10147 struct vmcs12
*vmcs12
)
10149 u64 address
= vmcs12
->pml_address
;
10150 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10152 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10153 if (!nested_cpu_has_ept(vmcs12
) ||
10154 !IS_ALIGNED(address
, 4096) ||
10155 address
>> maxphyaddr
)
10162 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10163 struct vmx_msr_entry
*e
)
10165 /* x2APIC MSR accesses are not allowed */
10166 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10168 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10169 e
->index
== MSR_IA32_UCODE_REV
)
10171 if (e
->reserved
!= 0)
10176 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10177 struct vmx_msr_entry
*e
)
10179 if (e
->index
== MSR_FS_BASE
||
10180 e
->index
== MSR_GS_BASE
||
10181 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10182 nested_vmx_msr_check_common(vcpu
, e
))
10187 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10188 struct vmx_msr_entry
*e
)
10190 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10191 nested_vmx_msr_check_common(vcpu
, e
))
10197 * Load guest's/host's msr at nested entry/exit.
10198 * return 0 for success, entry index for failure.
10200 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10203 struct vmx_msr_entry e
;
10204 struct msr_data msr
;
10206 msr
.host_initiated
= false;
10207 for (i
= 0; i
< count
; i
++) {
10208 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10210 pr_debug_ratelimited(
10211 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10212 __func__
, i
, gpa
+ i
* sizeof(e
));
10215 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10216 pr_debug_ratelimited(
10217 "%s check failed (%u, 0x%x, 0x%x)\n",
10218 __func__
, i
, e
.index
, e
.reserved
);
10221 msr
.index
= e
.index
;
10222 msr
.data
= e
.value
;
10223 if (kvm_set_msr(vcpu
, &msr
)) {
10224 pr_debug_ratelimited(
10225 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10226 __func__
, i
, e
.index
, e
.value
);
10235 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10238 struct vmx_msr_entry e
;
10240 for (i
= 0; i
< count
; i
++) {
10241 struct msr_data msr_info
;
10242 if (kvm_vcpu_read_guest(vcpu
,
10243 gpa
+ i
* sizeof(e
),
10244 &e
, 2 * sizeof(u32
))) {
10245 pr_debug_ratelimited(
10246 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10247 __func__
, i
, gpa
+ i
* sizeof(e
));
10250 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10251 pr_debug_ratelimited(
10252 "%s check failed (%u, 0x%x, 0x%x)\n",
10253 __func__
, i
, e
.index
, e
.reserved
);
10256 msr_info
.host_initiated
= false;
10257 msr_info
.index
= e
.index
;
10258 if (kvm_get_msr(vcpu
, &msr_info
)) {
10259 pr_debug_ratelimited(
10260 "%s cannot read MSR (%u, 0x%x)\n",
10261 __func__
, i
, e
.index
);
10264 if (kvm_vcpu_write_guest(vcpu
,
10265 gpa
+ i
* sizeof(e
) +
10266 offsetof(struct vmx_msr_entry
, value
),
10267 &msr_info
.data
, sizeof(msr_info
.data
))) {
10268 pr_debug_ratelimited(
10269 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10270 __func__
, i
, e
.index
, msr_info
.data
);
10277 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10279 unsigned long invalid_mask
;
10281 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10282 return (val
& invalid_mask
) == 0;
10286 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10287 * emulating VM entry into a guest with EPT enabled.
10288 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10289 * is assigned to entry_failure_code on failure.
10291 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10292 u32
*entry_failure_code
)
10294 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10295 if (!nested_cr3_valid(vcpu
, cr3
)) {
10296 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10301 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10302 * must not be dereferenced.
10304 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10306 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10307 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10312 vcpu
->arch
.cr3
= cr3
;
10313 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10316 kvm_mmu_reset_context(vcpu
);
10321 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10322 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10323 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10324 * guest in a way that will both be appropriate to L1's requests, and our
10325 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10326 * function also has additional necessary side-effects, like setting various
10327 * vcpu->arch fields.
10328 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10329 * is assigned to entry_failure_code on failure.
10331 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10332 bool from_vmentry
, u32
*entry_failure_code
)
10334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10335 u32 exec_control
, vmcs12_exec_ctrl
;
10337 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10338 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10339 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10340 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10341 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10342 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10343 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10344 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10345 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10346 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10347 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10348 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10349 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10350 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10351 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10352 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10353 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10354 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10355 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10356 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10357 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10358 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10359 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10360 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10361 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10362 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10363 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10364 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10365 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10366 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10367 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10368 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10369 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10370 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10371 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10372 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10374 if (from_vmentry
&&
10375 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10376 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10377 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10379 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10380 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10382 if (from_vmentry
) {
10383 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10384 vmcs12
->vm_entry_intr_info_field
);
10385 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10386 vmcs12
->vm_entry_exception_error_code
);
10387 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10388 vmcs12
->vm_entry_instruction_len
);
10389 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10390 vmcs12
->guest_interruptibility_info
);
10391 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10392 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10394 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10396 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10397 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10398 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10399 vmcs12
->guest_pending_dbg_exceptions
);
10400 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10401 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10403 if (nested_cpu_has_xsaves(vmcs12
))
10404 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10405 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10407 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10409 /* Preemption timer setting is only taken from vmcs01. */
10410 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10411 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10412 if (vmx
->hv_deadline_tsc
== -1)
10413 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10415 /* Posted interrupts setting is only taken from vmcs12. */
10416 if (nested_cpu_has_posted_intr(vmcs12
)) {
10417 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10418 vmx
->nested
.pi_pending
= false;
10419 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10421 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10424 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10426 vmx
->nested
.preemption_timer_expired
= false;
10427 if (nested_cpu_has_preemption_timer(vmcs12
))
10428 vmx_start_preemption_timer(vcpu
);
10431 * Whether page-faults are trapped is determined by a combination of
10432 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10433 * If enable_ept, L0 doesn't care about page faults and we should
10434 * set all of these to L1's desires. However, if !enable_ept, L0 does
10435 * care about (at least some) page faults, and because it is not easy
10436 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10437 * to exit on each and every L2 page fault. This is done by setting
10438 * MASK=MATCH=0 and (see below) EB.PF=1.
10439 * Note that below we don't need special code to set EB.PF beyond the
10440 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10441 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10442 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10444 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10445 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10446 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10447 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10449 if (cpu_has_secondary_exec_ctrls()) {
10450 exec_control
= vmx
->secondary_exec_control
;
10452 /* Take the following fields only from vmcs12 */
10453 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10454 SECONDARY_EXEC_ENABLE_INVPCID
|
10455 SECONDARY_EXEC_RDTSCP
|
10456 SECONDARY_EXEC_XSAVES
|
10457 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10458 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10459 SECONDARY_EXEC_ENABLE_VMFUNC
);
10460 if (nested_cpu_has(vmcs12
,
10461 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10462 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10463 ~SECONDARY_EXEC_ENABLE_PML
;
10464 exec_control
|= vmcs12_exec_ctrl
;
10467 /* All VMFUNCs are currently emulated through L0 vmexits. */
10468 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10469 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10471 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10472 vmcs_write64(EOI_EXIT_BITMAP0
,
10473 vmcs12
->eoi_exit_bitmap0
);
10474 vmcs_write64(EOI_EXIT_BITMAP1
,
10475 vmcs12
->eoi_exit_bitmap1
);
10476 vmcs_write64(EOI_EXIT_BITMAP2
,
10477 vmcs12
->eoi_exit_bitmap2
);
10478 vmcs_write64(EOI_EXIT_BITMAP3
,
10479 vmcs12
->eoi_exit_bitmap3
);
10480 vmcs_write16(GUEST_INTR_STATUS
,
10481 vmcs12
->guest_intr_status
);
10485 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10486 * nested_get_vmcs12_pages will either fix it up or
10487 * remove the VM execution control.
10489 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10490 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10492 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10497 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10498 * Some constant fields are set here by vmx_set_constant_host_state().
10499 * Other fields are different per CPU, and will be set later when
10500 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10502 vmx_set_constant_host_state(vmx
);
10505 * Set the MSR load/store lists to match L0's settings.
10507 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10508 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10509 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10510 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10511 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10514 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10515 * entry, but only if the current (host) sp changed from the value
10516 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10517 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10518 * here we just force the write to happen on entry.
10522 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10523 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10524 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10525 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10526 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10529 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10530 * nested_get_vmcs12_pages can't fix it up, the illegal value
10531 * will result in a VM entry failure.
10533 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10534 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10535 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10537 #ifdef CONFIG_X86_64
10538 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10539 CPU_BASED_CR8_STORE_EXITING
;
10544 * Merging of IO bitmap not currently supported.
10545 * Rather, exit every time.
10547 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10548 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10550 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10552 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10553 * bitwise-or of what L1 wants to trap for L2, and what we want to
10554 * trap. Note that CR0.TS also needs updating - we do this later.
10556 update_exception_bitmap(vcpu
);
10557 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10558 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10560 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10561 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10562 * bits are further modified by vmx_set_efer() below.
10564 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10566 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10567 * emulated by vmx_set_efer(), below.
10569 vm_entry_controls_init(vmx
,
10570 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10571 ~VM_ENTRY_IA32E_MODE
) |
10572 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10574 if (from_vmentry
&&
10575 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10576 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10577 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10578 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10579 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10582 set_cr4_guest_host_mask(vmx
);
10584 if (from_vmentry
&&
10585 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10586 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10588 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10589 vmcs_write64(TSC_OFFSET
,
10590 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10592 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10593 if (kvm_has_tsc_control
)
10594 decache_tsc_multiplier(vmx
);
10598 * There is no direct mapping between vpid02 and vpid12, the
10599 * vpid02 is per-vCPU for L0 and reused while the value of
10600 * vpid12 is changed w/ one invvpid during nested vmentry.
10601 * The vpid12 is allocated by L1 for L2, so it will not
10602 * influence global bitmap(for vpid01 and vpid02 allocation)
10603 * even if spawn a lot of nested vCPUs.
10605 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10606 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10607 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10608 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10609 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10612 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10613 vmx_flush_tlb(vcpu
);
10620 * Conceptually we want to copy the PML address and index from
10621 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10622 * since we always flush the log on each vmexit, this happens
10623 * to be equivalent to simply resetting the fields in vmcs02.
10625 ASSERT(vmx
->pml_pg
);
10626 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10627 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10630 if (nested_cpu_has_ept(vmcs12
)) {
10631 if (nested_ept_init_mmu_context(vcpu
)) {
10632 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10635 } else if (nested_cpu_has2(vmcs12
,
10636 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10637 vmx_flush_tlb_ept_only(vcpu
);
10641 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10642 * bits which we consider mandatory enabled.
10643 * The CR0_READ_SHADOW is what L2 should have expected to read given
10644 * the specifications by L1; It's not enough to take
10645 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10646 * have more bits than L1 expected.
10648 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10649 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10651 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10652 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10654 if (from_vmentry
&&
10655 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10656 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10657 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10658 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10660 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10661 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10662 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10664 /* Shadow page tables on either EPT or shadow page tables. */
10665 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10666 entry_failure_code
))
10670 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10673 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10676 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10677 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10678 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10679 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10682 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10683 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10687 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10689 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10691 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10692 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10693 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10695 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10696 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10698 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10699 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10701 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10702 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10704 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10705 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10707 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10708 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10710 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10711 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10713 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10714 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10715 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10716 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10717 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10718 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10719 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10720 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10721 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10722 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10723 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10724 vmx
->nested
.nested_vmx_exit_ctls_low
,
10725 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10726 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10727 vmx
->nested
.nested_vmx_entry_ctls_low
,
10728 vmx
->nested
.nested_vmx_entry_ctls_high
))
10729 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10731 if (nested_cpu_has_vmfunc(vmcs12
)) {
10732 if (vmcs12
->vm_function_control
&
10733 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10734 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10736 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10737 if (!nested_cpu_has_ept(vmcs12
) ||
10738 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10739 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10743 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10744 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10746 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10747 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10748 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10749 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10754 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10759 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10761 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10762 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10765 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10766 vmcs12
->vmcs_link_pointer
!= -1ull) {
10767 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10772 * If the load IA32_EFER VM-entry control is 1, the following checks
10773 * are performed on the field for the IA32_EFER MSR:
10774 * - Bits reserved in the IA32_EFER MSR must be 0.
10775 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10776 * the IA-32e mode guest VM-exit control. It must also be identical
10777 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10780 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10781 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10782 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10783 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10784 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10785 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10786 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10791 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10792 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10793 * the values of the LMA and LME bits in the field must each be that of
10794 * the host address-space size VM-exit control.
10796 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10797 ia32e
= (vmcs12
->vm_exit_controls
&
10798 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10799 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10800 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10801 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10808 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10810 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10811 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10812 struct loaded_vmcs
*vmcs02
;
10816 vmcs02
= nested_get_current_vmcs02(vmx
);
10820 enter_guest_mode(vcpu
);
10822 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10823 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10825 vmx_switch_vmcs(vcpu
, vmcs02
);
10826 vmx_segment_cache_clear(vmx
);
10828 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10829 leave_guest_mode(vcpu
);
10830 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10831 nested_vmx_entry_failure(vcpu
, vmcs12
,
10832 EXIT_REASON_INVALID_STATE
, exit_qual
);
10836 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10838 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10839 vmcs12
->vm_entry_msr_load_addr
,
10840 vmcs12
->vm_entry_msr_load_count
);
10841 if (msr_entry_idx
) {
10842 leave_guest_mode(vcpu
);
10843 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10844 nested_vmx_entry_failure(vcpu
, vmcs12
,
10845 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10850 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10851 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10852 * returned as far as L1 is concerned. It will only return (and set
10853 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10859 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10860 * for running an L2 nested guest.
10862 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10864 struct vmcs12
*vmcs12
;
10865 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10866 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10870 if (!nested_vmx_check_permission(vcpu
))
10873 if (!nested_vmx_check_vmcs12(vcpu
))
10876 vmcs12
= get_vmcs12(vcpu
);
10878 if (enable_shadow_vmcs
)
10879 copy_shadow_to_vmcs12(vmx
);
10882 * The nested entry process starts with enforcing various prerequisites
10883 * on vmcs12 as required by the Intel SDM, and act appropriately when
10884 * they fail: As the SDM explains, some conditions should cause the
10885 * instruction to fail, while others will cause the instruction to seem
10886 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10887 * To speed up the normal (success) code path, we should avoid checking
10888 * for misconfigurations which will anyway be caught by the processor
10889 * when using the merged vmcs02.
10891 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10892 nested_vmx_failValid(vcpu
,
10893 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10897 if (vmcs12
->launch_state
== launch
) {
10898 nested_vmx_failValid(vcpu
,
10899 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10900 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10904 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10906 nested_vmx_failValid(vcpu
, ret
);
10911 * After this point, the trap flag no longer triggers a singlestep trap
10912 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10913 * This is not 100% correct; for performance reasons, we delegate most
10914 * of the checks on host state to the processor. If those fail,
10915 * the singlestep trap is missed.
10917 skip_emulated_instruction(vcpu
);
10919 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10921 nested_vmx_entry_failure(vcpu
, vmcs12
,
10922 EXIT_REASON_INVALID_STATE
, exit_qual
);
10927 * We're finally done with prerequisite checking, and can start with
10928 * the nested entry.
10931 ret
= enter_vmx_non_root_mode(vcpu
, true);
10935 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10936 return kvm_vcpu_halt(vcpu
);
10938 vmx
->nested
.nested_run_pending
= 1;
10943 return kvm_skip_emulated_instruction(vcpu
);
10947 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10948 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10949 * This function returns the new value we should put in vmcs12.guest_cr0.
10950 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10951 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10952 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10953 * didn't trap the bit, because if L1 did, so would L0).
10954 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10955 * been modified by L2, and L1 knows it. So just leave the old value of
10956 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10957 * isn't relevant, because if L0 traps this bit it can set it to anything.
10958 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10959 * changed these bits, and therefore they need to be updated, but L0
10960 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10961 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10963 static inline unsigned long
10964 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10967 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10968 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10969 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10970 vcpu
->arch
.cr0_guest_owned_bits
));
10973 static inline unsigned long
10974 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10977 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10978 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10979 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10980 vcpu
->arch
.cr4_guest_owned_bits
));
10983 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10984 struct vmcs12
*vmcs12
)
10989 if (vcpu
->arch
.exception
.injected
) {
10990 nr
= vcpu
->arch
.exception
.nr
;
10991 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10993 if (kvm_exception_is_soft(nr
)) {
10994 vmcs12
->vm_exit_instruction_len
=
10995 vcpu
->arch
.event_exit_inst_len
;
10996 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10998 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11000 if (vcpu
->arch
.exception
.has_error_code
) {
11001 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11002 vmcs12
->idt_vectoring_error_code
=
11003 vcpu
->arch
.exception
.error_code
;
11006 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11007 } else if (vcpu
->arch
.nmi_injected
) {
11008 vmcs12
->idt_vectoring_info_field
=
11009 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11010 } else if (vcpu
->arch
.interrupt
.pending
) {
11011 nr
= vcpu
->arch
.interrupt
.nr
;
11012 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11014 if (vcpu
->arch
.interrupt
.soft
) {
11015 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11016 vmcs12
->vm_entry_instruction_len
=
11017 vcpu
->arch
.event_exit_inst_len
;
11019 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11021 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11025 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11027 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11028 unsigned long exit_qual
;
11030 if (kvm_event_needs_reinjection(vcpu
))
11033 if (vcpu
->arch
.exception
.pending
&&
11034 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11035 if (vmx
->nested
.nested_run_pending
)
11037 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11038 vcpu
->arch
.exception
.pending
= false;
11042 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11043 vmx
->nested
.preemption_timer_expired
) {
11044 if (vmx
->nested
.nested_run_pending
)
11046 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11050 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11051 if (vmx
->nested
.nested_run_pending
)
11053 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11054 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11055 INTR_INFO_VALID_MASK
, 0);
11057 * The NMI-triggered VM exit counts as injection:
11058 * clear this one and block further NMIs.
11060 vcpu
->arch
.nmi_pending
= 0;
11061 vmx_set_nmi_mask(vcpu
, true);
11065 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11066 nested_exit_on_intr(vcpu
)) {
11067 if (vmx
->nested
.nested_run_pending
)
11069 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11073 vmx_complete_nested_posted_interrupt(vcpu
);
11077 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11079 ktime_t remaining
=
11080 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11083 if (ktime_to_ns(remaining
) <= 0)
11086 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11087 do_div(value
, 1000000);
11088 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11092 * Update the guest state fields of vmcs12 to reflect changes that
11093 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11094 * VM-entry controls is also updated, since this is really a guest
11097 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11099 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11100 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11102 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11103 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11104 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11106 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11107 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11108 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11109 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11110 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11111 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11112 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11113 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11114 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11115 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11116 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11117 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11118 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11119 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11120 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11121 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11122 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11123 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11124 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11125 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11126 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11127 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11128 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11129 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11130 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11131 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11132 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11133 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11134 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11135 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11136 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11137 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11138 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11139 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11140 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11141 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11143 vmcs12
->guest_interruptibility_info
=
11144 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11145 vmcs12
->guest_pending_dbg_exceptions
=
11146 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11147 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11148 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11150 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11152 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11153 if (vmcs12
->vm_exit_controls
&
11154 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11155 vmcs12
->vmx_preemption_timer_value
=
11156 vmx_get_preemption_timer_value(vcpu
);
11157 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11161 * In some cases (usually, nested EPT), L2 is allowed to change its
11162 * own CR3 without exiting. If it has changed it, we must keep it.
11163 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11164 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11166 * Additionally, restore L2's PDPTR to vmcs12.
11169 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11170 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11171 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11172 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11173 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11176 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11178 if (nested_cpu_has_vid(vmcs12
))
11179 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11181 vmcs12
->vm_entry_controls
=
11182 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11183 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11185 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11186 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11187 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11190 /* TODO: These cannot have changed unless we have MSR bitmaps and
11191 * the relevant bit asks not to trap the change */
11192 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11193 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11194 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11195 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11196 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11197 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11198 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11199 if (kvm_mpx_supported())
11200 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11204 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11205 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11206 * and this function updates it to reflect the changes to the guest state while
11207 * L2 was running (and perhaps made some exits which were handled directly by L0
11208 * without going back to L1), and to reflect the exit reason.
11209 * Note that we do not have to copy here all VMCS fields, just those that
11210 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11211 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11212 * which already writes to vmcs12 directly.
11214 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11215 u32 exit_reason
, u32 exit_intr_info
,
11216 unsigned long exit_qualification
)
11218 /* update guest state fields: */
11219 sync_vmcs12(vcpu
, vmcs12
);
11221 /* update exit information fields: */
11223 vmcs12
->vm_exit_reason
= exit_reason
;
11224 vmcs12
->exit_qualification
= exit_qualification
;
11225 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11227 vmcs12
->idt_vectoring_info_field
= 0;
11228 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11229 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11231 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11232 vmcs12
->launch_state
= 1;
11234 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11235 * instead of reading the real value. */
11236 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11239 * Transfer the event that L0 or L1 may wanted to inject into
11240 * L2 to IDT_VECTORING_INFO_FIELD.
11242 vmcs12_save_pending_event(vcpu
, vmcs12
);
11246 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11247 * preserved above and would only end up incorrectly in L1.
11249 vcpu
->arch
.nmi_injected
= false;
11250 kvm_clear_exception_queue(vcpu
);
11251 kvm_clear_interrupt_queue(vcpu
);
11255 * A part of what we need to when the nested L2 guest exits and we want to
11256 * run its L1 parent, is to reset L1's guest state to the host state specified
11258 * This function is to be called not only on normal nested exit, but also on
11259 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11260 * Failures During or After Loading Guest State").
11261 * This function should be called when the active VMCS is L1's (vmcs01).
11263 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11264 struct vmcs12
*vmcs12
)
11266 struct kvm_segment seg
;
11267 u32 entry_failure_code
;
11269 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11270 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11271 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11272 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11274 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11275 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11277 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11278 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11279 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11281 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11282 * actually changed, because vmx_set_cr0 refers to efer set above.
11284 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11285 * (KVM doesn't change it);
11287 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11288 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11290 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11291 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11292 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11294 nested_ept_uninit_mmu_context(vcpu
);
11297 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11298 * couldn't have changed.
11300 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11301 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11304 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11308 * Trivially support vpid by letting L2s share their parent
11309 * L1's vpid. TODO: move to a more elaborate solution, giving
11310 * each L2 its own vpid and exposing the vpid feature to L1.
11312 vmx_flush_tlb(vcpu
);
11314 /* Restore posted intr vector. */
11315 if (nested_cpu_has_posted_intr(vmcs12
))
11316 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11318 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11319 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11320 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11321 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11322 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11323 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11324 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11326 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11327 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11328 vmcs_write64(GUEST_BNDCFGS
, 0);
11330 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11331 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11332 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11334 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11335 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11336 vmcs12
->host_ia32_perf_global_ctrl
);
11338 /* Set L1 segment info according to Intel SDM
11339 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11340 seg
= (struct kvm_segment
) {
11342 .limit
= 0xFFFFFFFF,
11343 .selector
= vmcs12
->host_cs_selector
,
11349 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11353 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11354 seg
= (struct kvm_segment
) {
11356 .limit
= 0xFFFFFFFF,
11363 seg
.selector
= vmcs12
->host_ds_selector
;
11364 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11365 seg
.selector
= vmcs12
->host_es_selector
;
11366 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11367 seg
.selector
= vmcs12
->host_ss_selector
;
11368 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11369 seg
.selector
= vmcs12
->host_fs_selector
;
11370 seg
.base
= vmcs12
->host_fs_base
;
11371 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11372 seg
.selector
= vmcs12
->host_gs_selector
;
11373 seg
.base
= vmcs12
->host_gs_base
;
11374 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11375 seg
= (struct kvm_segment
) {
11376 .base
= vmcs12
->host_tr_base
,
11378 .selector
= vmcs12
->host_tr_selector
,
11382 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11384 kvm_set_dr(vcpu
, 7, 0x400);
11385 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11387 if (cpu_has_vmx_msr_bitmap())
11388 vmx_set_msr_bitmap(vcpu
);
11390 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11391 vmcs12
->vm_exit_msr_load_count
))
11392 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11396 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11397 * and modify vmcs12 to make it see what it would expect to see there if
11398 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11400 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11401 u32 exit_intr_info
,
11402 unsigned long exit_qualification
)
11404 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11405 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11407 /* trying to cancel vmlaunch/vmresume is a bug */
11408 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11411 * The only expected VM-instruction error is "VM entry with
11412 * invalid control field(s)." Anything else indicates a
11415 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11416 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11418 leave_guest_mode(vcpu
);
11420 if (likely(!vmx
->fail
)) {
11421 if (exit_reason
== -1)
11422 sync_vmcs12(vcpu
, vmcs12
);
11424 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11425 exit_qualification
);
11427 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11428 vmcs12
->vm_exit_msr_store_count
))
11429 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11432 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11433 vm_entry_controls_reset_shadow(vmx
);
11434 vm_exit_controls_reset_shadow(vmx
);
11435 vmx_segment_cache_clear(vmx
);
11437 /* if no vmcs02 cache requested, remove the one we used */
11438 if (VMCS02_POOL_SIZE
== 0)
11439 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11441 /* Update any VMCS fields that might have changed while L2 ran */
11442 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11443 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11444 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11445 if (vmx
->hv_deadline_tsc
== -1)
11446 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11447 PIN_BASED_VMX_PREEMPTION_TIMER
);
11449 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11450 PIN_BASED_VMX_PREEMPTION_TIMER
);
11451 if (kvm_has_tsc_control
)
11452 decache_tsc_multiplier(vmx
);
11454 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11455 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11456 vmx_set_virtual_x2apic_mode(vcpu
,
11457 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11458 } else if (!nested_cpu_has_ept(vmcs12
) &&
11459 nested_cpu_has2(vmcs12
,
11460 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11461 vmx_flush_tlb_ept_only(vcpu
);
11464 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11467 /* Unpin physical memory we referred to in vmcs02 */
11468 if (vmx
->nested
.apic_access_page
) {
11469 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11470 vmx
->nested
.apic_access_page
= NULL
;
11472 if (vmx
->nested
.virtual_apic_page
) {
11473 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11474 vmx
->nested
.virtual_apic_page
= NULL
;
11476 if (vmx
->nested
.pi_desc_page
) {
11477 kunmap(vmx
->nested
.pi_desc_page
);
11478 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11479 vmx
->nested
.pi_desc_page
= NULL
;
11480 vmx
->nested
.pi_desc
= NULL
;
11484 * We are now running in L2, mmu_notifier will force to reload the
11485 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11487 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11489 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11490 vmx
->nested
.sync_shadow_vmcs
= true;
11492 /* in case we halted in L2 */
11493 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11495 if (likely(!vmx
->fail
)) {
11497 * TODO: SDM says that with acknowledge interrupt on
11498 * exit, bit 31 of the VM-exit interrupt information
11499 * (valid interrupt) is always set to 1 on
11500 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11501 * need kvm_cpu_has_interrupt(). See the commit
11502 * message for details.
11504 if (nested_exit_intr_ack_set(vcpu
) &&
11505 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11506 kvm_cpu_has_interrupt(vcpu
)) {
11507 int irq
= kvm_cpu_get_interrupt(vcpu
);
11509 vmcs12
->vm_exit_intr_info
= irq
|
11510 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11513 if (exit_reason
!= -1)
11514 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11515 vmcs12
->exit_qualification
,
11516 vmcs12
->idt_vectoring_info_field
,
11517 vmcs12
->vm_exit_intr_info
,
11518 vmcs12
->vm_exit_intr_error_code
,
11521 load_vmcs12_host_state(vcpu
, vmcs12
);
11527 * After an early L2 VM-entry failure, we're now back
11528 * in L1 which thinks it just finished a VMLAUNCH or
11529 * VMRESUME instruction, so we need to set the failure
11530 * flag and the VM-instruction error field of the VMCS
11533 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11535 * The emulated instruction was already skipped in
11536 * nested_vmx_run, but the updated RIP was never
11537 * written back to the vmcs01.
11539 skip_emulated_instruction(vcpu
);
11544 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11546 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11548 if (is_guest_mode(vcpu
)) {
11549 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11550 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11552 free_nested(to_vmx(vcpu
));
11556 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11557 * 23.7 "VM-entry failures during or after loading guest state" (this also
11558 * lists the acceptable exit-reason and exit-qualification parameters).
11559 * It should only be called before L2 actually succeeded to run, and when
11560 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11562 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11563 struct vmcs12
*vmcs12
,
11564 u32 reason
, unsigned long qualification
)
11566 load_vmcs12_host_state(vcpu
, vmcs12
);
11567 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11568 vmcs12
->exit_qualification
= qualification
;
11569 nested_vmx_succeed(vcpu
);
11570 if (enable_shadow_vmcs
)
11571 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11574 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11575 struct x86_instruction_info
*info
,
11576 enum x86_intercept_stage stage
)
11578 return X86EMUL_CONTINUE
;
11581 #ifdef CONFIG_X86_64
11582 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11583 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11584 u64 divisor
, u64
*result
)
11586 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11588 /* To avoid the overflow on divq */
11589 if (high
>= divisor
)
11592 /* Low hold the result, high hold rem which is discarded */
11593 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11594 "rm" (divisor
), "0" (low
), "1" (high
));
11600 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11602 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11603 u64 tscl
= rdtsc();
11604 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11605 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11607 /* Convert to host delta tsc if tsc scaling is enabled */
11608 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11609 u64_shl_div_u64(delta_tsc
,
11610 kvm_tsc_scaling_ratio_frac_bits
,
11611 vcpu
->arch
.tsc_scaling_ratio
,
11616 * If the delta tsc can't fit in the 32 bit after the multi shift,
11617 * we can't use the preemption timer.
11618 * It's possible that it fits on later vmentries, but checking
11619 * on every vmentry is costly so we just use an hrtimer.
11621 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11624 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11625 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11626 PIN_BASED_VMX_PREEMPTION_TIMER
);
11628 return delta_tsc
== 0;
11631 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11633 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11634 vmx
->hv_deadline_tsc
= -1;
11635 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11636 PIN_BASED_VMX_PREEMPTION_TIMER
);
11640 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11643 shrink_ple_window(vcpu
);
11646 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11647 struct kvm_memory_slot
*slot
)
11649 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11650 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11653 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11654 struct kvm_memory_slot
*slot
)
11656 kvm_mmu_slot_set_dirty(kvm
, slot
);
11659 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11661 kvm_flush_pml_buffers(kvm
);
11664 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11666 struct vmcs12
*vmcs12
;
11667 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11669 struct page
*page
= NULL
;
11672 if (is_guest_mode(vcpu
)) {
11673 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11676 * Check if PML is enabled for the nested guest.
11677 * Whether eptp bit 6 is set is already checked
11678 * as part of A/D emulation.
11680 vmcs12
= get_vmcs12(vcpu
);
11681 if (!nested_cpu_has_pml(vmcs12
))
11684 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11685 vmx
->nested
.pml_full
= true;
11689 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11691 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11692 if (is_error_page(page
))
11695 pml_address
= kmap(page
);
11696 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11698 kvm_release_page_clean(page
);
11704 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11705 struct kvm_memory_slot
*memslot
,
11706 gfn_t offset
, unsigned long mask
)
11708 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11711 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11713 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11714 struct pi_desc old
, new;
11718 old
.control
= new.control
= pi_desc
->control
;
11719 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11720 "Wakeup handler not enabled while the VCPU is blocked\n");
11722 dest
= cpu_physical_id(vcpu
->cpu
);
11724 if (x2apic_enabled())
11727 new.ndst
= (dest
<< 8) & 0xFF00;
11729 /* set 'NV' to 'notification vector' */
11730 new.nv
= POSTED_INTR_VECTOR
;
11731 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11732 new.control
) != old
.control
);
11734 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11735 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11736 list_del(&vcpu
->blocked_vcpu_list
);
11737 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11738 vcpu
->pre_pcpu
= -1;
11743 * This routine does the following things for vCPU which is going
11744 * to be blocked if VT-d PI is enabled.
11745 * - Store the vCPU to the wakeup list, so when interrupts happen
11746 * we can find the right vCPU to wake up.
11747 * - Change the Posted-interrupt descriptor as below:
11748 * 'NDST' <-- vcpu->pre_pcpu
11749 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11750 * - If 'ON' is set during this process, which means at least one
11751 * interrupt is posted for this vCPU, we cannot block it, in
11752 * this case, return 1, otherwise, return 0.
11755 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11758 struct pi_desc old
, new;
11759 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11761 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11762 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11763 !kvm_vcpu_apicv_active(vcpu
))
11766 WARN_ON(irqs_disabled());
11767 local_irq_disable();
11768 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11769 vcpu
->pre_pcpu
= vcpu
->cpu
;
11770 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11771 list_add_tail(&vcpu
->blocked_vcpu_list
,
11772 &per_cpu(blocked_vcpu_on_cpu
,
11774 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11778 old
.control
= new.control
= pi_desc
->control
;
11780 WARN((pi_desc
->sn
== 1),
11781 "Warning: SN field of posted-interrupts "
11782 "is set before blocking\n");
11785 * Since vCPU can be preempted during this process,
11786 * vcpu->cpu could be different with pre_pcpu, we
11787 * need to set pre_pcpu as the destination of wakeup
11788 * notification event, then we can find the right vCPU
11789 * to wakeup in wakeup handler if interrupts happen
11790 * when the vCPU is in blocked state.
11792 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11794 if (x2apic_enabled())
11797 new.ndst
= (dest
<< 8) & 0xFF00;
11799 /* set 'NV' to 'wakeup vector' */
11800 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11801 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11802 new.control
) != old
.control
);
11804 /* We should not block the vCPU if an interrupt is posted for it. */
11805 if (pi_test_on(pi_desc
) == 1)
11806 __pi_post_block(vcpu
);
11808 local_irq_enable();
11809 return (vcpu
->pre_pcpu
== -1);
11812 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11814 if (pi_pre_block(vcpu
))
11817 if (kvm_lapic_hv_timer_in_use(vcpu
))
11818 kvm_lapic_switch_to_sw_timer(vcpu
);
11823 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11825 if (vcpu
->pre_pcpu
== -1)
11828 WARN_ON(irqs_disabled());
11829 local_irq_disable();
11830 __pi_post_block(vcpu
);
11831 local_irq_enable();
11834 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11836 if (kvm_x86_ops
->set_hv_timer
)
11837 kvm_lapic_switch_to_hv_timer(vcpu
);
11839 pi_post_block(vcpu
);
11843 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11846 * @host_irq: host irq of the interrupt
11847 * @guest_irq: gsi of the interrupt
11848 * @set: set or unset PI
11849 * returns 0 on success, < 0 on failure
11851 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11852 uint32_t guest_irq
, bool set
)
11854 struct kvm_kernel_irq_routing_entry
*e
;
11855 struct kvm_irq_routing_table
*irq_rt
;
11856 struct kvm_lapic_irq irq
;
11857 struct kvm_vcpu
*vcpu
;
11858 struct vcpu_data vcpu_info
;
11861 if (!kvm_arch_has_assigned_device(kvm
) ||
11862 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11863 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11866 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11867 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11868 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11869 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11870 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11871 guest_irq
, irq_rt
->nr_rt_entries
);
11875 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11876 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11879 * VT-d PI cannot support posting multicast/broadcast
11880 * interrupts to a vCPU, we still use interrupt remapping
11881 * for these kind of interrupts.
11883 * For lowest-priority interrupts, we only support
11884 * those with single CPU as the destination, e.g. user
11885 * configures the interrupts via /proc/irq or uses
11886 * irqbalance to make the interrupts single-CPU.
11888 * We will support full lowest-priority interrupt later.
11891 kvm_set_msi_irq(kvm
, e
, &irq
);
11892 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11894 * Make sure the IRTE is in remapped mode if
11895 * we don't handle it in posted mode.
11897 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11900 "failed to back to remapped mode, irq: %u\n",
11908 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11909 vcpu_info
.vector
= irq
.vector
;
11911 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11912 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11915 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11917 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11920 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11928 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11932 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11934 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11935 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11936 FEATURE_CONTROL_LMCE
;
11938 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11939 ~FEATURE_CONTROL_LMCE
;
11942 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
11944 /* we need a nested vmexit to enter SMM, postpone if run is pending */
11945 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
11950 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
11952 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11954 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
11955 if (vmx
->nested
.smm
.guest_mode
)
11956 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11958 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
11959 vmx
->nested
.vmxon
= false;
11963 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
11965 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11968 if (vmx
->nested
.smm
.vmxon
) {
11969 vmx
->nested
.vmxon
= true;
11970 vmx
->nested
.smm
.vmxon
= false;
11973 if (vmx
->nested
.smm
.guest_mode
) {
11974 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
11975 ret
= enter_vmx_non_root_mode(vcpu
, false);
11976 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
11980 vmx
->nested
.smm
.guest_mode
= false;
11985 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
11990 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11991 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11992 .disabled_by_bios
= vmx_disabled_by_bios
,
11993 .hardware_setup
= hardware_setup
,
11994 .hardware_unsetup
= hardware_unsetup
,
11995 .check_processor_compatibility
= vmx_check_processor_compat
,
11996 .hardware_enable
= hardware_enable
,
11997 .hardware_disable
= hardware_disable
,
11998 .cpu_has_accelerated_tpr
= report_flexpriority
,
11999 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
12001 .vcpu_create
= vmx_create_vcpu
,
12002 .vcpu_free
= vmx_free_vcpu
,
12003 .vcpu_reset
= vmx_vcpu_reset
,
12005 .prepare_guest_switch
= vmx_save_host_state
,
12006 .vcpu_load
= vmx_vcpu_load
,
12007 .vcpu_put
= vmx_vcpu_put
,
12009 .update_bp_intercept
= update_exception_bitmap
,
12010 .get_msr
= vmx_get_msr
,
12011 .set_msr
= vmx_set_msr
,
12012 .get_segment_base
= vmx_get_segment_base
,
12013 .get_segment
= vmx_get_segment
,
12014 .set_segment
= vmx_set_segment
,
12015 .get_cpl
= vmx_get_cpl
,
12016 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12017 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12018 .decache_cr3
= vmx_decache_cr3
,
12019 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12020 .set_cr0
= vmx_set_cr0
,
12021 .set_cr3
= vmx_set_cr3
,
12022 .set_cr4
= vmx_set_cr4
,
12023 .set_efer
= vmx_set_efer
,
12024 .get_idt
= vmx_get_idt
,
12025 .set_idt
= vmx_set_idt
,
12026 .get_gdt
= vmx_get_gdt
,
12027 .set_gdt
= vmx_set_gdt
,
12028 .get_dr6
= vmx_get_dr6
,
12029 .set_dr6
= vmx_set_dr6
,
12030 .set_dr7
= vmx_set_dr7
,
12031 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12032 .cache_reg
= vmx_cache_reg
,
12033 .get_rflags
= vmx_get_rflags
,
12034 .set_rflags
= vmx_set_rflags
,
12036 .tlb_flush
= vmx_flush_tlb
,
12038 .run
= vmx_vcpu_run
,
12039 .handle_exit
= vmx_handle_exit
,
12040 .skip_emulated_instruction
= skip_emulated_instruction
,
12041 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12042 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12043 .patch_hypercall
= vmx_patch_hypercall
,
12044 .set_irq
= vmx_inject_irq
,
12045 .set_nmi
= vmx_inject_nmi
,
12046 .queue_exception
= vmx_queue_exception
,
12047 .cancel_injection
= vmx_cancel_injection
,
12048 .interrupt_allowed
= vmx_interrupt_allowed
,
12049 .nmi_allowed
= vmx_nmi_allowed
,
12050 .get_nmi_mask
= vmx_get_nmi_mask
,
12051 .set_nmi_mask
= vmx_set_nmi_mask
,
12052 .enable_nmi_window
= enable_nmi_window
,
12053 .enable_irq_window
= enable_irq_window
,
12054 .update_cr8_intercept
= update_cr8_intercept
,
12055 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12056 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12057 .get_enable_apicv
= vmx_get_enable_apicv
,
12058 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12059 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12060 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12061 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12062 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12063 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12064 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12066 .set_tss_addr
= vmx_set_tss_addr
,
12067 .get_tdp_level
= get_ept_level
,
12068 .get_mt_mask
= vmx_get_mt_mask
,
12070 .get_exit_info
= vmx_get_exit_info
,
12072 .get_lpage_level
= vmx_get_lpage_level
,
12074 .cpuid_update
= vmx_cpuid_update
,
12076 .rdtscp_supported
= vmx_rdtscp_supported
,
12077 .invpcid_supported
= vmx_invpcid_supported
,
12079 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12081 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12083 .write_tsc_offset
= vmx_write_tsc_offset
,
12085 .set_tdp_cr3
= vmx_set_cr3
,
12087 .check_intercept
= vmx_check_intercept
,
12088 .handle_external_intr
= vmx_handle_external_intr
,
12089 .mpx_supported
= vmx_mpx_supported
,
12090 .xsaves_supported
= vmx_xsaves_supported
,
12092 .check_nested_events
= vmx_check_nested_events
,
12094 .sched_in
= vmx_sched_in
,
12096 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12097 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12098 .flush_log_dirty
= vmx_flush_log_dirty
,
12099 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12100 .write_log_dirty
= vmx_write_pml_buffer
,
12102 .pre_block
= vmx_pre_block
,
12103 .post_block
= vmx_post_block
,
12105 .pmu_ops
= &intel_pmu_ops
,
12107 .update_pi_irte
= vmx_update_pi_irte
,
12109 #ifdef CONFIG_X86_64
12110 .set_hv_timer
= vmx_set_hv_timer
,
12111 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12114 .setup_mce
= vmx_setup_mce
,
12116 .smi_allowed
= vmx_smi_allowed
,
12117 .pre_enter_smm
= vmx_pre_enter_smm
,
12118 .pre_leave_smm
= vmx_pre_leave_smm
,
12119 .enable_smi_window
= enable_smi_window
,
12122 static int __init
vmx_init(void)
12124 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12125 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12129 #ifdef CONFIG_KEXEC_CORE
12130 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12131 crash_vmclear_local_loaded_vmcss
);
12137 static void __exit
vmx_exit(void)
12139 #ifdef CONFIG_KEXEC_CORE
12140 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12147 module_init(vmx_init
)
12148 module_exit(vmx_exit
)