2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/trace_events.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
42 #include <asm/virtext.h>
44 #include <asm/fpu/internal.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
49 #include <asm/irq_remapping.h>
54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
55 #define __ex_clear(x, reg) \
56 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
58 MODULE_AUTHOR("Qumranet");
59 MODULE_LICENSE("GPL");
61 static const struct x86_cpu_id vmx_cpu_id
[] = {
62 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
65 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
67 static bool __read_mostly enable_vpid
= 1;
68 module_param_named(vpid
, enable_vpid
, bool, 0444);
70 static bool __read_mostly flexpriority_enabled
= 1;
71 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
73 static bool __read_mostly enable_ept
= 1;
74 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
76 static bool __read_mostly enable_unrestricted_guest
= 1;
77 module_param_named(unrestricted_guest
,
78 enable_unrestricted_guest
, bool, S_IRUGO
);
80 static bool __read_mostly enable_ept_ad_bits
= 1;
81 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
83 static bool __read_mostly emulate_invalid_guest_state
= true;
84 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
86 static bool __read_mostly vmm_exclusive
= 1;
87 module_param(vmm_exclusive
, bool, S_IRUGO
);
89 static bool __read_mostly fasteoi
= 1;
90 module_param(fasteoi
, bool, S_IRUGO
);
92 static bool __read_mostly enable_apicv
= 1;
93 module_param(enable_apicv
, bool, S_IRUGO
);
95 static bool __read_mostly enable_shadow_vmcs
= 1;
96 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
98 * If nested=1, nested virtualization is supported, i.e., guests may use
99 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
100 * use VMX instructions.
102 static bool __read_mostly nested
= 0;
103 module_param(nested
, bool, S_IRUGO
);
105 static u64 __read_mostly host_xss
;
107 static bool __read_mostly enable_pml
= 1;
108 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
110 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
114 #define KVM_VM_CR0_ALWAYS_ON \
115 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
116 #define KVM_CR4_GUEST_OWNED_BITS \
117 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
118 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
128 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
129 * ple_gap: upper bound on the amount of time between two successive
130 * executions of PAUSE in a loop. Also indicate if ple enabled.
131 * According to test, this time is usually smaller than 128 cycles.
132 * ple_window: upper bound on the amount of time a guest is allowed to execute
133 * in a PAUSE loop. Tests indicate that most spinlocks are held for
134 * less than 2^12 cycles
135 * Time is measured based on a counter that runs at the same rate as the TSC,
136 * refer SDM volume 3b section 21.6.13 & 22.1.3.
138 #define KVM_VMX_DEFAULT_PLE_GAP 128
139 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
143 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
145 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
146 module_param(ple_gap
, int, S_IRUGO
);
148 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
149 module_param(ple_window
, int, S_IRUGO
);
151 /* Default doubles per-vcpu window every exit. */
152 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
153 module_param(ple_window_grow
, int, S_IRUGO
);
155 /* Default resets per-vcpu window every exit to ple_window. */
156 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
157 module_param(ple_window_shrink
, int, S_IRUGO
);
159 /* Default is to compute the maximum so we can never overflow. */
160 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
161 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
162 module_param(ple_window_max
, int, S_IRUGO
);
164 extern const ulong vmx_return
;
166 #define NR_AUTOLOAD_MSRS 8
167 #define VMCS02_POOL_SIZE 1
176 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
177 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
178 * loaded on this CPU (so we can clear them if the CPU goes down).
184 struct list_head loaded_vmcss_on_cpu_link
;
187 struct shared_msr_entry
{
194 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
195 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
196 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
197 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
198 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
199 * More than one of these structures may exist, if L1 runs multiple L2 guests.
200 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
201 * underlying hardware which will be used to run L2.
202 * This structure is packed to ensure that its layout is identical across
203 * machines (necessary for live migration).
204 * If there are changes in this struct, VMCS12_REVISION must be changed.
206 typedef u64 natural_width
;
207 struct __packed vmcs12
{
208 /* According to the Intel spec, a VMCS region must start with the
209 * following two fields. Then follow implementation-specific data.
214 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
215 u32 padding
[7]; /* room for future expansion */
220 u64 vm_exit_msr_store_addr
;
221 u64 vm_exit_msr_load_addr
;
222 u64 vm_entry_msr_load_addr
;
224 u64 virtual_apic_page_addr
;
225 u64 apic_access_addr
;
226 u64 posted_intr_desc_addr
;
228 u64 eoi_exit_bitmap0
;
229 u64 eoi_exit_bitmap1
;
230 u64 eoi_exit_bitmap2
;
231 u64 eoi_exit_bitmap3
;
233 u64 guest_physical_address
;
234 u64 vmcs_link_pointer
;
235 u64 guest_ia32_debugctl
;
238 u64 guest_ia32_perf_global_ctrl
;
246 u64 host_ia32_perf_global_ctrl
;
247 u64 padding64
[8]; /* room for future expansion */
249 * To allow migration of L1 (complete with its L2 guests) between
250 * machines of different natural widths (32 or 64 bit), we cannot have
251 * unsigned long fields with no explict size. We use u64 (aliased
252 * natural_width) instead. Luckily, x86 is little-endian.
254 natural_width cr0_guest_host_mask
;
255 natural_width cr4_guest_host_mask
;
256 natural_width cr0_read_shadow
;
257 natural_width cr4_read_shadow
;
258 natural_width cr3_target_value0
;
259 natural_width cr3_target_value1
;
260 natural_width cr3_target_value2
;
261 natural_width cr3_target_value3
;
262 natural_width exit_qualification
;
263 natural_width guest_linear_address
;
264 natural_width guest_cr0
;
265 natural_width guest_cr3
;
266 natural_width guest_cr4
;
267 natural_width guest_es_base
;
268 natural_width guest_cs_base
;
269 natural_width guest_ss_base
;
270 natural_width guest_ds_base
;
271 natural_width guest_fs_base
;
272 natural_width guest_gs_base
;
273 natural_width guest_ldtr_base
;
274 natural_width guest_tr_base
;
275 natural_width guest_gdtr_base
;
276 natural_width guest_idtr_base
;
277 natural_width guest_dr7
;
278 natural_width guest_rsp
;
279 natural_width guest_rip
;
280 natural_width guest_rflags
;
281 natural_width guest_pending_dbg_exceptions
;
282 natural_width guest_sysenter_esp
;
283 natural_width guest_sysenter_eip
;
284 natural_width host_cr0
;
285 natural_width host_cr3
;
286 natural_width host_cr4
;
287 natural_width host_fs_base
;
288 natural_width host_gs_base
;
289 natural_width host_tr_base
;
290 natural_width host_gdtr_base
;
291 natural_width host_idtr_base
;
292 natural_width host_ia32_sysenter_esp
;
293 natural_width host_ia32_sysenter_eip
;
294 natural_width host_rsp
;
295 natural_width host_rip
;
296 natural_width paddingl
[8]; /* room for future expansion */
297 u32 pin_based_vm_exec_control
;
298 u32 cpu_based_vm_exec_control
;
299 u32 exception_bitmap
;
300 u32 page_fault_error_code_mask
;
301 u32 page_fault_error_code_match
;
302 u32 cr3_target_count
;
303 u32 vm_exit_controls
;
304 u32 vm_exit_msr_store_count
;
305 u32 vm_exit_msr_load_count
;
306 u32 vm_entry_controls
;
307 u32 vm_entry_msr_load_count
;
308 u32 vm_entry_intr_info_field
;
309 u32 vm_entry_exception_error_code
;
310 u32 vm_entry_instruction_len
;
312 u32 secondary_vm_exec_control
;
313 u32 vm_instruction_error
;
315 u32 vm_exit_intr_info
;
316 u32 vm_exit_intr_error_code
;
317 u32 idt_vectoring_info_field
;
318 u32 idt_vectoring_error_code
;
319 u32 vm_exit_instruction_len
;
320 u32 vmx_instruction_info
;
327 u32 guest_ldtr_limit
;
329 u32 guest_gdtr_limit
;
330 u32 guest_idtr_limit
;
331 u32 guest_es_ar_bytes
;
332 u32 guest_cs_ar_bytes
;
333 u32 guest_ss_ar_bytes
;
334 u32 guest_ds_ar_bytes
;
335 u32 guest_fs_ar_bytes
;
336 u32 guest_gs_ar_bytes
;
337 u32 guest_ldtr_ar_bytes
;
338 u32 guest_tr_ar_bytes
;
339 u32 guest_interruptibility_info
;
340 u32 guest_activity_state
;
341 u32 guest_sysenter_cs
;
342 u32 host_ia32_sysenter_cs
;
343 u32 vmx_preemption_timer_value
;
344 u32 padding32
[7]; /* room for future expansion */
345 u16 virtual_processor_id
;
347 u16 guest_es_selector
;
348 u16 guest_cs_selector
;
349 u16 guest_ss_selector
;
350 u16 guest_ds_selector
;
351 u16 guest_fs_selector
;
352 u16 guest_gs_selector
;
353 u16 guest_ldtr_selector
;
354 u16 guest_tr_selector
;
355 u16 guest_intr_status
;
356 u16 host_es_selector
;
357 u16 host_cs_selector
;
358 u16 host_ss_selector
;
359 u16 host_ds_selector
;
360 u16 host_fs_selector
;
361 u16 host_gs_selector
;
362 u16 host_tr_selector
;
366 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
367 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
368 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
370 #define VMCS12_REVISION 0x11e57ed0
373 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
374 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
375 * current implementation, 4K are reserved to avoid future complications.
377 #define VMCS12_SIZE 0x1000
379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
381 struct list_head list
;
383 struct loaded_vmcs vmcs02
;
387 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
388 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
391 /* Has the level1 guest done vmxon? */
395 /* The guest-physical address of the current VMCS L1 keeps for L2 */
397 /* The host-usable pointer to the above */
398 struct page
*current_vmcs12_page
;
399 struct vmcs12
*current_vmcs12
;
400 struct vmcs
*current_shadow_vmcs
;
402 * Indicates if the shadow vmcs must be updated with the
403 * data hold by vmcs12
405 bool sync_shadow_vmcs
;
407 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
408 struct list_head vmcs02_pool
;
410 u64 vmcs01_tsc_offset
;
411 /* L2 must run next, and mustn't decide to exit to L1. */
412 bool nested_run_pending
;
414 * Guest pages referred to in vmcs02 with host-physical pointers, so
415 * we must keep them pinned while L2 runs.
417 struct page
*apic_access_page
;
418 struct page
*virtual_apic_page
;
419 struct page
*pi_desc_page
;
420 struct pi_desc
*pi_desc
;
423 u64 msr_ia32_feature_control
;
425 struct hrtimer preemption_timer
;
426 bool preemption_timer_expired
;
428 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
434 u32 nested_vmx_procbased_ctls_low
;
435 u32 nested_vmx_procbased_ctls_high
;
436 u32 nested_vmx_true_procbased_ctls_low
;
437 u32 nested_vmx_secondary_ctls_low
;
438 u32 nested_vmx_secondary_ctls_high
;
439 u32 nested_vmx_pinbased_ctls_low
;
440 u32 nested_vmx_pinbased_ctls_high
;
441 u32 nested_vmx_exit_ctls_low
;
442 u32 nested_vmx_exit_ctls_high
;
443 u32 nested_vmx_true_exit_ctls_low
;
444 u32 nested_vmx_entry_ctls_low
;
445 u32 nested_vmx_entry_ctls_high
;
446 u32 nested_vmx_true_entry_ctls_low
;
447 u32 nested_vmx_misc_low
;
448 u32 nested_vmx_misc_high
;
449 u32 nested_vmx_ept_caps
;
450 u32 nested_vmx_vpid_caps
;
453 #define POSTED_INTR_ON 0
454 #define POSTED_INTR_SN 1
456 /* Posted-Interrupt Descriptor */
458 u32 pir
[8]; /* Posted interrupt requested */
461 /* bit 256 - Outstanding Notification */
463 /* bit 257 - Suppress Notification */
465 /* bit 271:258 - Reserved */
467 /* bit 279:272 - Notification Vector */
469 /* bit 287:280 - Reserved */
471 /* bit 319:288 - Notification Destination */
479 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
481 return test_and_set_bit(POSTED_INTR_ON
,
482 (unsigned long *)&pi_desc
->control
);
485 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
487 return test_and_clear_bit(POSTED_INTR_ON
,
488 (unsigned long *)&pi_desc
->control
);
491 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
493 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
496 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
498 return clear_bit(POSTED_INTR_SN
,
499 (unsigned long *)&pi_desc
->control
);
502 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
504 return set_bit(POSTED_INTR_SN
,
505 (unsigned long *)&pi_desc
->control
);
508 static inline int pi_test_on(struct pi_desc
*pi_desc
)
510 return test_bit(POSTED_INTR_ON
,
511 (unsigned long *)&pi_desc
->control
);
514 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
516 return test_bit(POSTED_INTR_SN
,
517 (unsigned long *)&pi_desc
->control
);
521 struct kvm_vcpu vcpu
;
522 unsigned long host_rsp
;
524 bool nmi_known_unmasked
;
526 u32 idt_vectoring_info
;
528 struct shared_msr_entry
*guest_msrs
;
531 unsigned long host_idt_base
;
533 u64 msr_host_kernel_gs_base
;
534 u64 msr_guest_kernel_gs_base
;
536 u32 vm_entry_controls_shadow
;
537 u32 vm_exit_controls_shadow
;
539 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
540 * non-nested (L1) guest, it always points to vmcs01. For a nested
541 * guest (L2), it points to a different VMCS.
543 struct loaded_vmcs vmcs01
;
544 struct loaded_vmcs
*loaded_vmcs
;
545 bool __launched
; /* temporary, used in vmx_vcpu_run */
546 struct msr_autoload
{
548 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
549 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
553 u16 fs_sel
, gs_sel
, ldt_sel
;
557 int gs_ldt_reload_needed
;
558 int fs_reload_needed
;
559 u64 msr_host_bndcfgs
;
560 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
565 struct kvm_segment segs
[8];
568 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
569 struct kvm_save_segment
{
577 bool emulation_required
;
579 /* Support for vnmi-less CPUs */
580 int soft_vnmi_blocked
;
582 s64 vnmi_blocked_time
;
585 /* Posted interrupt descriptor */
586 struct pi_desc pi_desc
;
588 /* Support for a guest hypervisor (nested VMX) */
589 struct nested_vmx nested
;
591 /* Dynamic PLE window. */
593 bool ple_window_dirty
;
595 /* Support for PML */
596 #define PML_ENTITY_NUM 512
599 u64 current_tsc_ratio
;
602 enum segment_cache_field
{
611 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
613 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
616 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
618 return &(to_vmx(vcpu
)->pi_desc
);
621 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
622 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
623 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
624 [number##_HIGH] = VMCS12_OFFSET(name)+4
627 static unsigned long shadow_read_only_fields
[] = {
629 * We do NOT shadow fields that are modified when L0
630 * traps and emulates any vmx instruction (e.g. VMPTRLD,
631 * VMXON...) executed by L1.
632 * For example, VM_INSTRUCTION_ERROR is read
633 * by L1 if a vmx instruction fails (part of the error path).
634 * Note the code assumes this logic. If for some reason
635 * we start shadowing these fields then we need to
636 * force a shadow sync when L0 emulates vmx instructions
637 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
638 * by nested_vmx_failValid)
642 VM_EXIT_INSTRUCTION_LEN
,
643 IDT_VECTORING_INFO_FIELD
,
644 IDT_VECTORING_ERROR_CODE
,
645 VM_EXIT_INTR_ERROR_CODE
,
647 GUEST_LINEAR_ADDRESS
,
648 GUEST_PHYSICAL_ADDRESS
650 static int max_shadow_read_only_fields
=
651 ARRAY_SIZE(shadow_read_only_fields
);
653 static unsigned long shadow_read_write_fields
[] = {
660 GUEST_INTERRUPTIBILITY_INFO
,
673 CPU_BASED_VM_EXEC_CONTROL
,
674 VM_ENTRY_EXCEPTION_ERROR_CODE
,
675 VM_ENTRY_INTR_INFO_FIELD
,
676 VM_ENTRY_INSTRUCTION_LEN
,
677 VM_ENTRY_EXCEPTION_ERROR_CODE
,
683 static int max_shadow_read_write_fields
=
684 ARRAY_SIZE(shadow_read_write_fields
);
686 static const unsigned short vmcs_field_to_offset_table
[] = {
687 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
688 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
689 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
690 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
691 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
692 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
693 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
694 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
695 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
696 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
697 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
698 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
699 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
700 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
701 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
702 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
703 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
704 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
705 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
706 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
707 FIELD64(MSR_BITMAP
, msr_bitmap
),
708 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
709 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
710 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
711 FIELD64(TSC_OFFSET
, tsc_offset
),
712 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
713 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
714 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
715 FIELD64(EPT_POINTER
, ept_pointer
),
716 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
717 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
718 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
719 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
720 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
721 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
722 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
723 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
724 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
725 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
726 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
727 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
728 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
729 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
730 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
731 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
732 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
733 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
734 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
735 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
736 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
737 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
738 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
739 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
740 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
741 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
742 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
743 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
744 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
745 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
746 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
747 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
748 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
749 FIELD(TPR_THRESHOLD
, tpr_threshold
),
750 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
751 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
752 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
753 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
754 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
755 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
756 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
757 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
758 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
759 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
760 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
761 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
762 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
763 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
764 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
765 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
766 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
767 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
768 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
769 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
770 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
771 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
772 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
773 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
774 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
775 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
776 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
777 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
778 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
779 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
780 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
781 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
782 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
783 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
784 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
785 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
786 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
787 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
788 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
789 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
790 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
791 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
792 FIELD(GUEST_CR0
, guest_cr0
),
793 FIELD(GUEST_CR3
, guest_cr3
),
794 FIELD(GUEST_CR4
, guest_cr4
),
795 FIELD(GUEST_ES_BASE
, guest_es_base
),
796 FIELD(GUEST_CS_BASE
, guest_cs_base
),
797 FIELD(GUEST_SS_BASE
, guest_ss_base
),
798 FIELD(GUEST_DS_BASE
, guest_ds_base
),
799 FIELD(GUEST_FS_BASE
, guest_fs_base
),
800 FIELD(GUEST_GS_BASE
, guest_gs_base
),
801 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
802 FIELD(GUEST_TR_BASE
, guest_tr_base
),
803 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
804 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
805 FIELD(GUEST_DR7
, guest_dr7
),
806 FIELD(GUEST_RSP
, guest_rsp
),
807 FIELD(GUEST_RIP
, guest_rip
),
808 FIELD(GUEST_RFLAGS
, guest_rflags
),
809 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
810 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
811 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
812 FIELD(HOST_CR0
, host_cr0
),
813 FIELD(HOST_CR3
, host_cr3
),
814 FIELD(HOST_CR4
, host_cr4
),
815 FIELD(HOST_FS_BASE
, host_fs_base
),
816 FIELD(HOST_GS_BASE
, host_gs_base
),
817 FIELD(HOST_TR_BASE
, host_tr_base
),
818 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
819 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
820 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
821 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
822 FIELD(HOST_RSP
, host_rsp
),
823 FIELD(HOST_RIP
, host_rip
),
826 static inline short vmcs_field_to_offset(unsigned long field
)
828 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
830 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
831 vmcs_field_to_offset_table
[field
] == 0)
834 return vmcs_field_to_offset_table
[field
];
837 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
839 return to_vmx(vcpu
)->nested
.current_vmcs12
;
842 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
844 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
845 if (is_error_page(page
))
851 static void nested_release_page(struct page
*page
)
853 kvm_release_page_dirty(page
);
856 static void nested_release_page_clean(struct page
*page
)
858 kvm_release_page_clean(page
);
861 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
862 static u64
construct_eptp(unsigned long root_hpa
);
863 static void kvm_cpu_vmxon(u64 addr
);
864 static void kvm_cpu_vmxoff(void);
865 static bool vmx_mpx_supported(void);
866 static bool vmx_xsaves_supported(void);
867 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
);
868 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
869 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
870 struct kvm_segment
*var
, int seg
);
871 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
872 struct kvm_segment
*var
, int seg
);
873 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
874 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
876 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
877 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
878 static int alloc_identity_pagetable(struct kvm
*kvm
);
880 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
881 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
883 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
884 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
886 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
887 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
890 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
891 * can find which vCPU should be waken up.
893 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
894 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
896 static unsigned long *vmx_io_bitmap_a
;
897 static unsigned long *vmx_io_bitmap_b
;
898 static unsigned long *vmx_msr_bitmap_legacy
;
899 static unsigned long *vmx_msr_bitmap_longmode
;
900 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
901 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
902 static unsigned long *vmx_msr_bitmap_nested
;
903 static unsigned long *vmx_vmread_bitmap
;
904 static unsigned long *vmx_vmwrite_bitmap
;
906 static bool cpu_has_load_ia32_efer
;
907 static bool cpu_has_load_perf_global_ctrl
;
909 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
910 static DEFINE_SPINLOCK(vmx_vpid_lock
);
912 static struct vmcs_config
{
916 u32 pin_based_exec_ctrl
;
917 u32 cpu_based_exec_ctrl
;
918 u32 cpu_based_2nd_exec_ctrl
;
923 static struct vmx_capability
{
928 #define VMX_SEGMENT_FIELD(seg) \
929 [VCPU_SREG_##seg] = { \
930 .selector = GUEST_##seg##_SELECTOR, \
931 .base = GUEST_##seg##_BASE, \
932 .limit = GUEST_##seg##_LIMIT, \
933 .ar_bytes = GUEST_##seg##_AR_BYTES, \
936 static const struct kvm_vmx_segment_field
{
941 } kvm_vmx_segment_fields
[] = {
942 VMX_SEGMENT_FIELD(CS
),
943 VMX_SEGMENT_FIELD(DS
),
944 VMX_SEGMENT_FIELD(ES
),
945 VMX_SEGMENT_FIELD(FS
),
946 VMX_SEGMENT_FIELD(GS
),
947 VMX_SEGMENT_FIELD(SS
),
948 VMX_SEGMENT_FIELD(TR
),
949 VMX_SEGMENT_FIELD(LDTR
),
952 static u64 host_efer
;
954 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
957 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
958 * away by decrementing the array size.
960 static const u32 vmx_msr_index
[] = {
962 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
964 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
967 static inline bool is_page_fault(u32 intr_info
)
969 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
970 INTR_INFO_VALID_MASK
)) ==
971 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
974 static inline bool is_no_device(u32 intr_info
)
976 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
977 INTR_INFO_VALID_MASK
)) ==
978 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
981 static inline bool is_invalid_opcode(u32 intr_info
)
983 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
984 INTR_INFO_VALID_MASK
)) ==
985 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
988 static inline bool is_external_interrupt(u32 intr_info
)
990 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
991 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
994 static inline bool is_machine_check(u32 intr_info
)
996 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
997 INTR_INFO_VALID_MASK
)) ==
998 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1003 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1008 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1013 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1018 return vmcs_config
.cpu_based_exec_ctrl
&
1019 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1024 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1025 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1030 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1031 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1036 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1037 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1042 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1043 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1046 static inline bool cpu_has_vmx_posted_intr(void)
1048 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1049 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1052 static inline bool cpu_has_vmx_apicv(void)
1054 return cpu_has_vmx_apic_register_virt() &&
1055 cpu_has_vmx_virtual_intr_delivery() &&
1056 cpu_has_vmx_posted_intr();
1059 static inline bool cpu_has_vmx_flexpriority(void)
1061 return cpu_has_vmx_tpr_shadow() &&
1062 cpu_has_vmx_virtualize_apic_accesses();
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1067 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1072 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1077 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1082 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1087 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1090 static inline bool cpu_has_vmx_invept_context(void)
1092 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1095 static inline bool cpu_has_vmx_invept_global(void)
1097 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1102 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1107 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1110 static inline bool cpu_has_vmx_ept(void)
1112 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1113 SECONDARY_EXEC_ENABLE_EPT
;
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1118 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1119 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1122 static inline bool cpu_has_vmx_ple(void)
1124 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1125 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1130 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1133 static inline bool cpu_has_vmx_vpid(void)
1135 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1136 SECONDARY_EXEC_ENABLE_VPID
;
1139 static inline bool cpu_has_vmx_rdtscp(void)
1141 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1142 SECONDARY_EXEC_RDTSCP
;
1145 static inline bool cpu_has_vmx_invpcid(void)
1147 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1148 SECONDARY_EXEC_ENABLE_INVPCID
;
1151 static inline bool cpu_has_virtual_nmis(void)
1153 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1158 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1159 SECONDARY_EXEC_WBINVD_EXITING
;
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1165 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1166 /* check if the cpu supports writing r/o exit information fields */
1167 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1170 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1171 SECONDARY_EXEC_SHADOW_VMCS
;
1174 static inline bool cpu_has_vmx_pml(void)
1176 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1181 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1182 SECONDARY_EXEC_TSC_SCALING
;
1185 static inline bool report_flexpriority(void)
1187 return flexpriority_enabled
;
1190 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1192 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1195 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1197 return (vmcs12
->cpu_based_vm_exec_control
&
1198 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1199 (vmcs12
->secondary_vm_exec_control
& bit
);
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1204 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1209 return vmcs12
->pin_based_vm_exec_control
&
1210 PIN_BASED_VMX_PREEMPTION_TIMER
;
1213 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1215 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1220 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1221 vmx_xsaves_supported();
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1226 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1229 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1231 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1236 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1239 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1241 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1246 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1249 static inline bool is_exception(u32 intr_info
)
1251 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1252 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1255 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1257 unsigned long exit_qualification
);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1259 struct vmcs12
*vmcs12
,
1260 u32 reason
, unsigned long qualification
);
1262 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1266 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1267 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1272 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1278 } operand
= { vpid
, 0, gva
};
1280 asm volatile (__ex(ASM_VMX_INVVPID
)
1281 /* CF==1 or ZF==1 --> rc = -1 */
1282 "; ja 1f ; ud2 ; 1:"
1283 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1286 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1290 } operand
= {eptp
, gpa
};
1292 asm volatile (__ex(ASM_VMX_INVEPT
)
1293 /* CF==1 or ZF==1 --> rc = -1 */
1294 "; ja 1f ; ud2 ; 1:\n"
1295 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1298 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1302 i
= __find_msr_index(vmx
, msr
);
1304 return &vmx
->guest_msrs
[i
];
1308 static void vmcs_clear(struct vmcs
*vmcs
)
1310 u64 phys_addr
= __pa(vmcs
);
1313 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1314 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1317 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1321 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1323 vmcs_clear(loaded_vmcs
->vmcs
);
1324 loaded_vmcs
->cpu
= -1;
1325 loaded_vmcs
->launched
= 0;
1328 static void vmcs_load(struct vmcs
*vmcs
)
1330 u64 phys_addr
= __pa(vmcs
);
1333 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1334 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1337 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1341 #ifdef CONFIG_KEXEC_CORE
1343 * This bitmap is used to indicate whether the vmclear
1344 * operation is enabled on all cpus. All disabled by
1347 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1349 static inline void crash_enable_local_vmclear(int cpu
)
1351 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1354 static inline void crash_disable_local_vmclear(int cpu
)
1356 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1359 static inline int crash_local_vmclear_enabled(int cpu
)
1361 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1364 static void crash_vmclear_local_loaded_vmcss(void)
1366 int cpu
= raw_smp_processor_id();
1367 struct loaded_vmcs
*v
;
1369 if (!crash_local_vmclear_enabled(cpu
))
1372 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1373 loaded_vmcss_on_cpu_link
)
1374 vmcs_clear(v
->vmcs
);
1377 static inline void crash_enable_local_vmclear(int cpu
) { }
1378 static inline void crash_disable_local_vmclear(int cpu
) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1381 static void __loaded_vmcs_clear(void *arg
)
1383 struct loaded_vmcs
*loaded_vmcs
= arg
;
1384 int cpu
= raw_smp_processor_id();
1386 if (loaded_vmcs
->cpu
!= cpu
)
1387 return; /* vcpu migration can race with cpu offline */
1388 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1389 per_cpu(current_vmcs
, cpu
) = NULL
;
1390 crash_disable_local_vmclear(cpu
);
1391 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1394 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395 * is before setting loaded_vmcs->vcpu to -1 which is done in
1396 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397 * then adds the vmcs into percpu list before it is deleted.
1401 loaded_vmcs_init(loaded_vmcs
);
1402 crash_enable_local_vmclear(cpu
);
1405 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1407 int cpu
= loaded_vmcs
->cpu
;
1410 smp_call_function_single(cpu
,
1411 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1414 static inline void vpid_sync_vcpu_single(int vpid
)
1419 if (cpu_has_vmx_invvpid_single())
1420 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1423 static inline void vpid_sync_vcpu_global(void)
1425 if (cpu_has_vmx_invvpid_global())
1426 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1429 static inline void vpid_sync_context(int vpid
)
1431 if (cpu_has_vmx_invvpid_single())
1432 vpid_sync_vcpu_single(vpid
);
1434 vpid_sync_vcpu_global();
1437 static inline void ept_sync_global(void)
1439 if (cpu_has_vmx_invept_global())
1440 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1443 static inline void ept_sync_context(u64 eptp
)
1446 if (cpu_has_vmx_invept_context())
1447 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1453 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1455 unsigned long value
;
1457 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1458 : "=a"(value
) : "d"(field
) : "cc");
1462 static __always_inline u16
vmcs_read16(unsigned long field
)
1464 return vmcs_readl(field
);
1467 static __always_inline u32
vmcs_read32(unsigned long field
)
1469 return vmcs_readl(field
);
1472 static __always_inline u64
vmcs_read64(unsigned long field
)
1474 #ifdef CONFIG_X86_64
1475 return vmcs_readl(field
);
1477 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1481 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1483 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1484 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1488 static void vmcs_writel(unsigned long field
, unsigned long value
)
1492 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1493 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1494 if (unlikely(error
))
1495 vmwrite_error(field
, value
);
1498 static void vmcs_write16(unsigned long field
, u16 value
)
1500 vmcs_writel(field
, value
);
1503 static void vmcs_write32(unsigned long field
, u32 value
)
1505 vmcs_writel(field
, value
);
1508 static void vmcs_write64(unsigned long field
, u64 value
)
1510 vmcs_writel(field
, value
);
1511 #ifndef CONFIG_X86_64
1513 vmcs_writel(field
+1, value
>> 32);
1517 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1519 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1522 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1524 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1527 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1529 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1530 vmx
->vm_entry_controls_shadow
= val
;
1533 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1535 if (vmx
->vm_entry_controls_shadow
!= val
)
1536 vm_entry_controls_init(vmx
, val
);
1539 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1541 return vmx
->vm_entry_controls_shadow
;
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1547 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1552 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1555 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1557 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1558 vmx
->vm_exit_controls_shadow
= val
;
1561 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1563 if (vmx
->vm_exit_controls_shadow
!= val
)
1564 vm_exit_controls_init(vmx
, val
);
1567 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1569 return vmx
->vm_exit_controls_shadow
;
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1575 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1580 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1583 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1585 vmx
->segment_cache
.bitmask
= 0;
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1592 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1594 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1595 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1596 vmx
->segment_cache
.bitmask
= 0;
1598 ret
= vmx
->segment_cache
.bitmask
& mask
;
1599 vmx
->segment_cache
.bitmask
|= mask
;
1603 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1605 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1607 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1608 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1612 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1614 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1616 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1617 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1621 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1623 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1625 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1626 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1630 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1632 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1634 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1635 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1639 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1643 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1644 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1645 if ((vcpu
->guest_debug
&
1646 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1647 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1648 eb
|= 1u << BP_VECTOR
;
1649 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1652 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1653 if (vcpu
->fpu_active
)
1654 eb
&= ~(1u << NM_VECTOR
);
1656 /* When we are running a nested L2 guest and L1 specified for it a
1657 * certain exception bitmap, we must trap the same exceptions and pass
1658 * them to L1. When running L2, we will only handle the exceptions
1659 * specified above if L1 did not want them.
1661 if (is_guest_mode(vcpu
))
1662 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1664 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1668 unsigned long entry
, unsigned long exit
)
1670 vm_entry_controls_clearbit(vmx
, entry
);
1671 vm_exit_controls_clearbit(vmx
, exit
);
1674 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1677 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1681 if (cpu_has_load_ia32_efer
) {
1682 clear_atomic_switch_msr_special(vmx
,
1683 VM_ENTRY_LOAD_IA32_EFER
,
1684 VM_EXIT_LOAD_IA32_EFER
);
1688 case MSR_CORE_PERF_GLOBAL_CTRL
:
1689 if (cpu_has_load_perf_global_ctrl
) {
1690 clear_atomic_switch_msr_special(vmx
,
1691 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1692 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1698 for (i
= 0; i
< m
->nr
; ++i
)
1699 if (m
->guest
[i
].index
== msr
)
1705 m
->guest
[i
] = m
->guest
[m
->nr
];
1706 m
->host
[i
] = m
->host
[m
->nr
];
1707 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1708 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1712 unsigned long entry
, unsigned long exit
,
1713 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1714 u64 guest_val
, u64 host_val
)
1716 vmcs_write64(guest_val_vmcs
, guest_val
);
1717 vmcs_write64(host_val_vmcs
, host_val
);
1718 vm_entry_controls_setbit(vmx
, entry
);
1719 vm_exit_controls_setbit(vmx
, exit
);
1722 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1723 u64 guest_val
, u64 host_val
)
1726 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1730 if (cpu_has_load_ia32_efer
) {
1731 add_atomic_switch_msr_special(vmx
,
1732 VM_ENTRY_LOAD_IA32_EFER
,
1733 VM_EXIT_LOAD_IA32_EFER
,
1736 guest_val
, host_val
);
1740 case MSR_CORE_PERF_GLOBAL_CTRL
:
1741 if (cpu_has_load_perf_global_ctrl
) {
1742 add_atomic_switch_msr_special(vmx
,
1743 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1744 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1745 GUEST_IA32_PERF_GLOBAL_CTRL
,
1746 HOST_IA32_PERF_GLOBAL_CTRL
,
1747 guest_val
, host_val
);
1751 case MSR_IA32_PEBS_ENABLE
:
1752 /* PEBS needs a quiescent period after being disabled (to write
1753 * a record). Disabling PEBS through VMX MSR swapping doesn't
1754 * provide that period, so a CPU could write host's record into
1757 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1760 for (i
= 0; i
< m
->nr
; ++i
)
1761 if (m
->guest
[i
].index
== msr
)
1764 if (i
== NR_AUTOLOAD_MSRS
) {
1765 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1766 "Can't add msr %x\n", msr
);
1768 } else if (i
== m
->nr
) {
1770 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1771 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1774 m
->guest
[i
].index
= msr
;
1775 m
->guest
[i
].value
= guest_val
;
1776 m
->host
[i
].index
= msr
;
1777 m
->host
[i
].value
= host_val
;
1780 static void reload_tss(void)
1783 * VT restores TR but not its size. Useless.
1785 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1786 struct desc_struct
*descs
;
1788 descs
= (void *)gdt
->address
;
1789 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1793 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1795 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
1796 u64 ignore_bits
= 0;
1800 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
1801 * host CPUID is more efficient than testing guest CPUID
1802 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
1804 if (boot_cpu_has(X86_FEATURE_SMEP
))
1805 guest_efer
|= EFER_NX
;
1806 else if (!(guest_efer
& EFER_NX
))
1807 ignore_bits
|= EFER_NX
;
1811 * LMA and LME handled by hardware; SCE meaningless outside long mode.
1813 ignore_bits
|= EFER_SCE
;
1814 #ifdef CONFIG_X86_64
1815 ignore_bits
|= EFER_LMA
| EFER_LME
;
1816 /* SCE is meaningful only in long mode on Intel */
1817 if (guest_efer
& EFER_LMA
)
1818 ignore_bits
&= ~(u64
)EFER_SCE
;
1821 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1824 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1825 * On CPUs that support "load IA32_EFER", always switch EFER
1826 * atomically, since it's faster than switching it manually.
1828 if (cpu_has_load_ia32_efer
||
1829 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1830 if (!(guest_efer
& EFER_LMA
))
1831 guest_efer
&= ~EFER_LME
;
1832 if (guest_efer
!= host_efer
)
1833 add_atomic_switch_msr(vmx
, MSR_EFER
,
1834 guest_efer
, host_efer
);
1837 guest_efer
&= ~ignore_bits
;
1838 guest_efer
|= host_efer
& ignore_bits
;
1840 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1841 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1847 static unsigned long segment_base(u16 selector
)
1849 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1850 struct desc_struct
*d
;
1851 unsigned long table_base
;
1854 if (!(selector
& ~3))
1857 table_base
= gdt
->address
;
1859 if (selector
& 4) { /* from ldt */
1860 u16 ldt_selector
= kvm_read_ldt();
1862 if (!(ldt_selector
& ~3))
1865 table_base
= segment_base(ldt_selector
);
1867 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1868 v
= get_desc_base(d
);
1869 #ifdef CONFIG_X86_64
1870 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1871 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1876 static inline unsigned long kvm_read_tr_base(void)
1879 asm("str %0" : "=g"(tr
));
1880 return segment_base(tr
);
1883 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1888 if (vmx
->host_state
.loaded
)
1891 vmx
->host_state
.loaded
= 1;
1893 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1894 * allow segment selectors with cpl > 0 or ti == 1.
1896 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1897 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1898 savesegment(fs
, vmx
->host_state
.fs_sel
);
1899 if (!(vmx
->host_state
.fs_sel
& 7)) {
1900 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1901 vmx
->host_state
.fs_reload_needed
= 0;
1903 vmcs_write16(HOST_FS_SELECTOR
, 0);
1904 vmx
->host_state
.fs_reload_needed
= 1;
1906 savesegment(gs
, vmx
->host_state
.gs_sel
);
1907 if (!(vmx
->host_state
.gs_sel
& 7))
1908 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1910 vmcs_write16(HOST_GS_SELECTOR
, 0);
1911 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1914 #ifdef CONFIG_X86_64
1915 savesegment(ds
, vmx
->host_state
.ds_sel
);
1916 savesegment(es
, vmx
->host_state
.es_sel
);
1919 #ifdef CONFIG_X86_64
1920 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1921 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1923 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1924 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1927 #ifdef CONFIG_X86_64
1928 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1929 if (is_long_mode(&vmx
->vcpu
))
1930 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1932 if (boot_cpu_has(X86_FEATURE_MPX
))
1933 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1934 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1935 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1936 vmx
->guest_msrs
[i
].data
,
1937 vmx
->guest_msrs
[i
].mask
);
1940 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1942 if (!vmx
->host_state
.loaded
)
1945 ++vmx
->vcpu
.stat
.host_state_reload
;
1946 vmx
->host_state
.loaded
= 0;
1947 #ifdef CONFIG_X86_64
1948 if (is_long_mode(&vmx
->vcpu
))
1949 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1951 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1952 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1953 #ifdef CONFIG_X86_64
1954 load_gs_index(vmx
->host_state
.gs_sel
);
1956 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1959 if (vmx
->host_state
.fs_reload_needed
)
1960 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1961 #ifdef CONFIG_X86_64
1962 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1963 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1964 loadsegment(es
, vmx
->host_state
.es_sel
);
1968 #ifdef CONFIG_X86_64
1969 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1971 if (vmx
->host_state
.msr_host_bndcfgs
)
1972 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1974 * If the FPU is not active (through the host task or
1975 * the guest vcpu), then restore the cr0.TS bit.
1977 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
1979 load_gdt(this_cpu_ptr(&host_gdt
));
1982 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1985 __vmx_load_host_state(vmx
);
1989 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
1991 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
1992 struct pi_desc old
, new;
1995 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
1996 !irq_remapping_cap(IRQ_POSTING_CAP
))
2000 old
.control
= new.control
= pi_desc
->control
;
2003 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2004 * are two possible cases:
2005 * 1. After running 'pre_block', context switch
2006 * happened. For this case, 'sn' was set in
2007 * vmx_vcpu_put(), so we need to clear it here.
2008 * 2. After running 'pre_block', we were blocked,
2009 * and woken up by some other guy. For this case,
2010 * we don't need to do anything, 'pi_post_block'
2011 * will do everything for us. However, we cannot
2012 * check whether it is case #1 or case #2 here
2013 * (maybe, not needed), so we also clear sn here,
2014 * I think it is not a big deal.
2016 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2017 if (vcpu
->cpu
!= cpu
) {
2018 dest
= cpu_physical_id(cpu
);
2020 if (x2apic_enabled())
2023 new.ndst
= (dest
<< 8) & 0xFF00;
2026 /* set 'NV' to 'notification vector' */
2027 new.nv
= POSTED_INTR_VECTOR
;
2030 /* Allow posting non-urgent interrupts */
2032 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2033 new.control
) != old
.control
);
2036 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2037 * vcpu mutex is already taken.
2039 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2041 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2042 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2045 kvm_cpu_vmxon(phys_addr
);
2046 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2047 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2049 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2050 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2051 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2054 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2055 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2056 unsigned long sysenter_esp
;
2058 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2059 local_irq_disable();
2060 crash_disable_local_vmclear(cpu
);
2063 * Read loaded_vmcs->cpu should be before fetching
2064 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2065 * See the comments in __loaded_vmcs_clear().
2069 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2070 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2071 crash_enable_local_vmclear(cpu
);
2075 * Linux uses per-cpu TSS and GDT, so set these when switching
2078 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2079 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2081 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2082 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2084 vmx
->loaded_vmcs
->cpu
= cpu
;
2087 /* Setup TSC multiplier */
2088 if (kvm_has_tsc_control
&&
2089 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
) {
2090 vmx
->current_tsc_ratio
= vcpu
->arch
.tsc_scaling_ratio
;
2091 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2094 vmx_vcpu_pi_load(vcpu
, cpu
);
2097 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2099 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2101 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2102 !irq_remapping_cap(IRQ_POSTING_CAP
))
2105 /* Set SN when the vCPU is preempted */
2106 if (vcpu
->preempted
)
2110 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2112 vmx_vcpu_pi_put(vcpu
);
2114 __vmx_load_host_state(to_vmx(vcpu
));
2115 if (!vmm_exclusive
) {
2116 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2122 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2126 if (vcpu
->fpu_active
)
2128 vcpu
->fpu_active
= 1;
2129 cr0
= vmcs_readl(GUEST_CR0
);
2130 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2131 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2132 vmcs_writel(GUEST_CR0
, cr0
);
2133 update_exception_bitmap(vcpu
);
2134 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2135 if (is_guest_mode(vcpu
))
2136 vcpu
->arch
.cr0_guest_owned_bits
&=
2137 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2138 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2144 * Return the cr0 value that a nested guest would read. This is a combination
2145 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2146 * its hypervisor (cr0_read_shadow).
2148 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2150 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2151 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2153 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2155 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2156 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2159 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2161 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2162 * set this *before* calling this function.
2164 vmx_decache_cr0_guest_bits(vcpu
);
2165 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2166 update_exception_bitmap(vcpu
);
2167 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2168 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2169 if (is_guest_mode(vcpu
)) {
2171 * L1's specified read shadow might not contain the TS bit,
2172 * so now that we turned on shadowing of this bit, we need to
2173 * set this bit of the shadow. Like in nested_vmx_run we need
2174 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2175 * up-to-date here because we just decached cr0.TS (and we'll
2176 * only update vmcs12->guest_cr0 on nested exit).
2178 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2179 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2180 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2181 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2183 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2186 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2188 unsigned long rflags
, save_rflags
;
2190 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2191 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2192 rflags
= vmcs_readl(GUEST_RFLAGS
);
2193 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2194 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2195 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2196 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2198 to_vmx(vcpu
)->rflags
= rflags
;
2200 return to_vmx(vcpu
)->rflags
;
2203 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2205 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2206 to_vmx(vcpu
)->rflags
= rflags
;
2207 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2208 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2209 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2211 vmcs_writel(GUEST_RFLAGS
, rflags
);
2214 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2216 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2219 if (interruptibility
& GUEST_INTR_STATE_STI
)
2220 ret
|= KVM_X86_SHADOW_INT_STI
;
2221 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2222 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2227 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2229 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2230 u32 interruptibility
= interruptibility_old
;
2232 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2234 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2235 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2236 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2237 interruptibility
|= GUEST_INTR_STATE_STI
;
2239 if ((interruptibility
!= interruptibility_old
))
2240 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2243 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2247 rip
= kvm_rip_read(vcpu
);
2248 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2249 kvm_rip_write(vcpu
, rip
);
2251 /* skipping an emulated instruction also counts */
2252 vmx_set_interrupt_shadow(vcpu
, 0);
2256 * KVM wants to inject page-faults which it got to the guest. This function
2257 * checks whether in a nested guest, we need to inject them to L1 or L2.
2259 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2261 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2263 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2266 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2267 vmcs_read32(VM_EXIT_INTR_INFO
),
2268 vmcs_readl(EXIT_QUALIFICATION
));
2272 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2273 bool has_error_code
, u32 error_code
,
2276 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2277 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2279 if (!reinject
&& is_guest_mode(vcpu
) &&
2280 nested_vmx_check_exception(vcpu
, nr
))
2283 if (has_error_code
) {
2284 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2285 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2288 if (vmx
->rmode
.vm86_active
) {
2290 if (kvm_exception_is_soft(nr
))
2291 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2292 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2293 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2297 if (kvm_exception_is_soft(nr
)) {
2298 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2299 vmx
->vcpu
.arch
.event_exit_inst_len
);
2300 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2302 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2304 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2307 static bool vmx_rdtscp_supported(void)
2309 return cpu_has_vmx_rdtscp();
2312 static bool vmx_invpcid_supported(void)
2314 return cpu_has_vmx_invpcid() && enable_ept
;
2318 * Swap MSR entry in host/guest MSR entry array.
2320 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2322 struct shared_msr_entry tmp
;
2324 tmp
= vmx
->guest_msrs
[to
];
2325 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2326 vmx
->guest_msrs
[from
] = tmp
;
2329 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2331 unsigned long *msr_bitmap
;
2333 if (is_guest_mode(vcpu
))
2334 msr_bitmap
= vmx_msr_bitmap_nested
;
2335 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2336 if (is_long_mode(vcpu
))
2337 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2339 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2341 if (is_long_mode(vcpu
))
2342 msr_bitmap
= vmx_msr_bitmap_longmode
;
2344 msr_bitmap
= vmx_msr_bitmap_legacy
;
2347 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2351 * Set up the vmcs to automatically save and restore system
2352 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2353 * mode, as fiddling with msrs is very expensive.
2355 static void setup_msrs(struct vcpu_vmx
*vmx
)
2357 int save_nmsrs
, index
;
2360 #ifdef CONFIG_X86_64
2361 if (is_long_mode(&vmx
->vcpu
)) {
2362 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2364 move_msr_up(vmx
, index
, save_nmsrs
++);
2365 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2367 move_msr_up(vmx
, index
, save_nmsrs
++);
2368 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2370 move_msr_up(vmx
, index
, save_nmsrs
++);
2371 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2372 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2373 move_msr_up(vmx
, index
, save_nmsrs
++);
2375 * MSR_STAR is only needed on long mode guests, and only
2376 * if efer.sce is enabled.
2378 index
= __find_msr_index(vmx
, MSR_STAR
);
2379 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2380 move_msr_up(vmx
, index
, save_nmsrs
++);
2383 index
= __find_msr_index(vmx
, MSR_EFER
);
2384 if (index
>= 0 && update_transition_efer(vmx
, index
))
2385 move_msr_up(vmx
, index
, save_nmsrs
++);
2387 vmx
->save_nmsrs
= save_nmsrs
;
2389 if (cpu_has_vmx_msr_bitmap())
2390 vmx_set_msr_bitmap(&vmx
->vcpu
);
2394 * reads and returns guest's timestamp counter "register"
2395 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2396 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2398 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2400 u64 host_tsc
, tsc_offset
;
2403 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2404 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2408 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2409 * counter, even if a nested guest (L2) is currently running.
2411 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2415 tsc_offset
= is_guest_mode(vcpu
) ?
2416 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2417 vmcs_read64(TSC_OFFSET
);
2418 return host_tsc
+ tsc_offset
;
2421 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2423 return vmcs_read64(TSC_OFFSET
);
2427 * writes 'offset' into guest's timestamp counter offset register
2429 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2431 if (is_guest_mode(vcpu
)) {
2433 * We're here if L1 chose not to trap WRMSR to TSC. According
2434 * to the spec, this should set L1's TSC; The offset that L1
2435 * set for L2 remains unchanged, and still needs to be added
2436 * to the newly set TSC to get L2's TSC.
2438 struct vmcs12
*vmcs12
;
2439 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2440 /* recalculate vmcs02.TSC_OFFSET: */
2441 vmcs12
= get_vmcs12(vcpu
);
2442 vmcs_write64(TSC_OFFSET
, offset
+
2443 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2444 vmcs12
->tsc_offset
: 0));
2446 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2447 vmcs_read64(TSC_OFFSET
), offset
);
2448 vmcs_write64(TSC_OFFSET
, offset
);
2452 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2454 u64 offset
= vmcs_read64(TSC_OFFSET
);
2456 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2457 if (is_guest_mode(vcpu
)) {
2458 /* Even when running L2, the adjustment needs to apply to L1 */
2459 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2461 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2462 offset
+ adjustment
);
2465 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2467 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2468 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2472 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2473 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2474 * all guests if the "nested" module option is off, and can also be disabled
2475 * for a single guest by disabling its VMX cpuid bit.
2477 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2479 return nested
&& guest_cpuid_has_vmx(vcpu
);
2483 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2484 * returned for the various VMX controls MSRs when nested VMX is enabled.
2485 * The same values should also be used to verify that vmcs12 control fields are
2486 * valid during nested entry from L1 to L2.
2487 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2488 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2489 * bit in the high half is on if the corresponding bit in the control field
2490 * may be on. See also vmx_control_verify().
2492 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2495 * Note that as a general rule, the high half of the MSRs (bits in
2496 * the control fields which may be 1) should be initialized by the
2497 * intersection of the underlying hardware's MSR (i.e., features which
2498 * can be supported) and the list of features we want to expose -
2499 * because they are known to be properly supported in our code.
2500 * Also, usually, the low half of the MSRs (bits which must be 1) can
2501 * be set to 0, meaning that L1 may turn off any of these bits. The
2502 * reason is that if one of these bits is necessary, it will appear
2503 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2504 * fields of vmcs01 and vmcs02, will turn these bits off - and
2505 * nested_vmx_exit_handled() will not pass related exits to L1.
2506 * These rules have exceptions below.
2509 /* pin-based controls */
2510 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2511 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2512 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2513 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2514 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2515 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2516 PIN_BASED_EXT_INTR_MASK
|
2517 PIN_BASED_NMI_EXITING
|
2518 PIN_BASED_VIRTUAL_NMIS
;
2519 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2520 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2521 PIN_BASED_VMX_PREEMPTION_TIMER
;
2522 if (vmx_cpu_uses_apicv(&vmx
->vcpu
))
2523 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2524 PIN_BASED_POSTED_INTR
;
2527 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2528 vmx
->nested
.nested_vmx_exit_ctls_low
,
2529 vmx
->nested
.nested_vmx_exit_ctls_high
);
2530 vmx
->nested
.nested_vmx_exit_ctls_low
=
2531 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2533 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2534 #ifdef CONFIG_X86_64
2535 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2537 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2538 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2539 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2540 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2541 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2543 if (vmx_mpx_supported())
2544 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2546 /* We support free control of debug control saving. */
2547 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2548 vmx
->nested
.nested_vmx_exit_ctls_low
&
2549 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2551 /* entry controls */
2552 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2553 vmx
->nested
.nested_vmx_entry_ctls_low
,
2554 vmx
->nested
.nested_vmx_entry_ctls_high
);
2555 vmx
->nested
.nested_vmx_entry_ctls_low
=
2556 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2557 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2558 #ifdef CONFIG_X86_64
2559 VM_ENTRY_IA32E_MODE
|
2561 VM_ENTRY_LOAD_IA32_PAT
;
2562 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2563 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2564 if (vmx_mpx_supported())
2565 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2567 /* We support free control of debug control loading. */
2568 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2569 vmx
->nested
.nested_vmx_entry_ctls_low
&
2570 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2572 /* cpu-based controls */
2573 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2574 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2575 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2576 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2577 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2578 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2579 CPU_BASED_VIRTUAL_INTR_PENDING
|
2580 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2581 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2582 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2583 CPU_BASED_CR3_STORE_EXITING
|
2584 #ifdef CONFIG_X86_64
2585 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2587 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2588 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2589 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2590 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2591 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2593 * We can allow some features even when not supported by the
2594 * hardware. For example, L1 can specify an MSR bitmap - and we
2595 * can use it to avoid exits to L1 - even when L0 runs L2
2596 * without MSR bitmaps.
2598 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2599 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2600 CPU_BASED_USE_MSR_BITMAPS
;
2602 /* We support free control of CR3 access interception. */
2603 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2604 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2605 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2607 /* secondary cpu-based controls */
2608 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2609 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2610 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2611 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2612 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2613 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2614 SECONDARY_EXEC_RDTSCP
|
2615 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2616 SECONDARY_EXEC_ENABLE_VPID
|
2617 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2618 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2619 SECONDARY_EXEC_WBINVD_EXITING
|
2620 SECONDARY_EXEC_XSAVES
|
2621 SECONDARY_EXEC_PCOMMIT
;
2624 /* nested EPT: emulate EPT also to L1 */
2625 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2626 SECONDARY_EXEC_ENABLE_EPT
;
2627 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2628 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2630 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2632 * For nested guests, we don't do anything specific
2633 * for single context invalidation. Hence, only advertise
2634 * support for global context invalidation.
2636 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2638 vmx
->nested
.nested_vmx_ept_caps
= 0;
2641 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2642 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2644 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2646 if (enable_unrestricted_guest
)
2647 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2648 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2650 /* miscellaneous data */
2651 rdmsr(MSR_IA32_VMX_MISC
,
2652 vmx
->nested
.nested_vmx_misc_low
,
2653 vmx
->nested
.nested_vmx_misc_high
);
2654 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2655 vmx
->nested
.nested_vmx_misc_low
|=
2656 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2657 VMX_MISC_ACTIVITY_HLT
;
2658 vmx
->nested
.nested_vmx_misc_high
= 0;
2661 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2664 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2666 return ((control
& high
) | low
) == control
;
2669 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2671 return low
| ((u64
)high
<< 32);
2674 /* Returns 0 on success, non-0 otherwise. */
2675 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2679 switch (msr_index
) {
2680 case MSR_IA32_VMX_BASIC
:
2682 * This MSR reports some information about VMX support. We
2683 * should return information about the VMX we emulate for the
2684 * guest, and the VMCS structure we give it - not about the
2685 * VMX support of the underlying hardware.
2687 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2688 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2689 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2691 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2692 case MSR_IA32_VMX_PINBASED_CTLS
:
2693 *pdata
= vmx_control_msr(
2694 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2695 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2697 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2698 *pdata
= vmx_control_msr(
2699 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2700 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2702 case MSR_IA32_VMX_PROCBASED_CTLS
:
2703 *pdata
= vmx_control_msr(
2704 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2705 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2707 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2708 *pdata
= vmx_control_msr(
2709 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2710 vmx
->nested
.nested_vmx_exit_ctls_high
);
2712 case MSR_IA32_VMX_EXIT_CTLS
:
2713 *pdata
= vmx_control_msr(
2714 vmx
->nested
.nested_vmx_exit_ctls_low
,
2715 vmx
->nested
.nested_vmx_exit_ctls_high
);
2717 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2718 *pdata
= vmx_control_msr(
2719 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2720 vmx
->nested
.nested_vmx_entry_ctls_high
);
2722 case MSR_IA32_VMX_ENTRY_CTLS
:
2723 *pdata
= vmx_control_msr(
2724 vmx
->nested
.nested_vmx_entry_ctls_low
,
2725 vmx
->nested
.nested_vmx_entry_ctls_high
);
2727 case MSR_IA32_VMX_MISC
:
2728 *pdata
= vmx_control_msr(
2729 vmx
->nested
.nested_vmx_misc_low
,
2730 vmx
->nested
.nested_vmx_misc_high
);
2733 * These MSRs specify bits which the guest must keep fixed (on or off)
2734 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2735 * We picked the standard core2 setting.
2737 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2738 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2739 case MSR_IA32_VMX_CR0_FIXED0
:
2740 *pdata
= VMXON_CR0_ALWAYSON
;
2742 case MSR_IA32_VMX_CR0_FIXED1
:
2745 case MSR_IA32_VMX_CR4_FIXED0
:
2746 *pdata
= VMXON_CR4_ALWAYSON
;
2748 case MSR_IA32_VMX_CR4_FIXED1
:
2751 case MSR_IA32_VMX_VMCS_ENUM
:
2752 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2754 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2755 *pdata
= vmx_control_msr(
2756 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2757 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2759 case MSR_IA32_VMX_EPT_VPID_CAP
:
2760 /* Currently, no nested vpid support */
2761 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2762 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2772 * Reads an msr value (of 'msr_index') into 'pdata'.
2773 * Returns 0 on success, non-0 otherwise.
2774 * Assumes vcpu_load() was already called.
2776 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2778 struct shared_msr_entry
*msr
;
2780 switch (msr_info
->index
) {
2781 #ifdef CONFIG_X86_64
2783 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2786 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2788 case MSR_KERNEL_GS_BASE
:
2789 vmx_load_host_state(to_vmx(vcpu
));
2790 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2794 return kvm_get_msr_common(vcpu
, msr_info
);
2796 msr_info
->data
= guest_read_tsc(vcpu
);
2798 case MSR_IA32_SYSENTER_CS
:
2799 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2801 case MSR_IA32_SYSENTER_EIP
:
2802 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2804 case MSR_IA32_SYSENTER_ESP
:
2805 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2807 case MSR_IA32_BNDCFGS
:
2808 if (!vmx_mpx_supported())
2810 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2812 case MSR_IA32_FEATURE_CONTROL
:
2813 if (!nested_vmx_allowed(vcpu
))
2815 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2817 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2818 if (!nested_vmx_allowed(vcpu
))
2820 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2822 if (!vmx_xsaves_supported())
2824 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2827 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2829 /* Otherwise falls through */
2831 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2833 msr_info
->data
= msr
->data
;
2836 return kvm_get_msr_common(vcpu
, msr_info
);
2842 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2845 * Writes msr value into into the appropriate "register".
2846 * Returns 0 on success, non-0 otherwise.
2847 * Assumes vcpu_load() was already called.
2849 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2851 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2852 struct shared_msr_entry
*msr
;
2854 u32 msr_index
= msr_info
->index
;
2855 u64 data
= msr_info
->data
;
2857 switch (msr_index
) {
2859 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2861 #ifdef CONFIG_X86_64
2863 vmx_segment_cache_clear(vmx
);
2864 vmcs_writel(GUEST_FS_BASE
, data
);
2867 vmx_segment_cache_clear(vmx
);
2868 vmcs_writel(GUEST_GS_BASE
, data
);
2870 case MSR_KERNEL_GS_BASE
:
2871 vmx_load_host_state(vmx
);
2872 vmx
->msr_guest_kernel_gs_base
= data
;
2875 case MSR_IA32_SYSENTER_CS
:
2876 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2878 case MSR_IA32_SYSENTER_EIP
:
2879 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2881 case MSR_IA32_SYSENTER_ESP
:
2882 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2884 case MSR_IA32_BNDCFGS
:
2885 if (!vmx_mpx_supported())
2887 vmcs_write64(GUEST_BNDCFGS
, data
);
2890 kvm_write_tsc(vcpu
, msr_info
);
2892 case MSR_IA32_CR_PAT
:
2893 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2894 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2896 vmcs_write64(GUEST_IA32_PAT
, data
);
2897 vcpu
->arch
.pat
= data
;
2900 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2902 case MSR_IA32_TSC_ADJUST
:
2903 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2905 case MSR_IA32_FEATURE_CONTROL
:
2906 if (!nested_vmx_allowed(vcpu
) ||
2907 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2908 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2910 vmx
->nested
.msr_ia32_feature_control
= data
;
2911 if (msr_info
->host_initiated
&& data
== 0)
2912 vmx_leave_nested(vcpu
);
2914 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2915 return 1; /* they are read-only */
2917 if (!vmx_xsaves_supported())
2920 * The only supported bit as of Skylake is bit 8, but
2921 * it is not supported on KVM.
2925 vcpu
->arch
.ia32_xss
= data
;
2926 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2927 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2928 vcpu
->arch
.ia32_xss
, host_xss
);
2930 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2933 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2935 /* Check reserved bit, higher 32 bits should be zero */
2936 if ((data
>> 32) != 0)
2938 /* Otherwise falls through */
2940 msr
= find_msr_entry(vmx
, msr_index
);
2942 u64 old_msr_data
= msr
->data
;
2944 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2946 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2950 msr
->data
= old_msr_data
;
2954 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2960 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2962 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2965 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2968 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2970 case VCPU_EXREG_PDPTR
:
2972 ept_save_pdptrs(vcpu
);
2979 static __init
int cpu_has_kvm_support(void)
2981 return cpu_has_vmx();
2984 static __init
int vmx_disabled_by_bios(void)
2988 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2989 if (msr
& FEATURE_CONTROL_LOCKED
) {
2990 /* launched w/ TXT and VMX disabled */
2991 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2994 /* launched w/o TXT and VMX only enabled w/ TXT */
2995 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2996 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2997 && !tboot_enabled()) {
2998 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2999 "activate TXT before enabling KVM\n");
3002 /* launched w/o TXT and VMX disabled */
3003 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3004 && !tboot_enabled())
3011 static void kvm_cpu_vmxon(u64 addr
)
3013 asm volatile (ASM_VMX_VMXON_RAX
3014 : : "a"(&addr
), "m"(addr
)
3018 static int hardware_enable(void)
3020 int cpu
= raw_smp_processor_id();
3021 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3024 if (cr4_read_shadow() & X86_CR4_VMXE
)
3027 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3028 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3029 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3032 * Now we can enable the vmclear operation in kdump
3033 * since the loaded_vmcss_on_cpu list on this cpu
3034 * has been initialized.
3036 * Though the cpu is not in VMX operation now, there
3037 * is no problem to enable the vmclear operation
3038 * for the loaded_vmcss_on_cpu list is empty!
3040 crash_enable_local_vmclear(cpu
);
3042 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3044 test_bits
= FEATURE_CONTROL_LOCKED
;
3045 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3046 if (tboot_enabled())
3047 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3049 if ((old
& test_bits
) != test_bits
) {
3050 /* enable and lock */
3051 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3053 cr4_set_bits(X86_CR4_VMXE
);
3055 if (vmm_exclusive
) {
3056 kvm_cpu_vmxon(phys_addr
);
3060 native_store_gdt(this_cpu_ptr(&host_gdt
));
3065 static void vmclear_local_loaded_vmcss(void)
3067 int cpu
= raw_smp_processor_id();
3068 struct loaded_vmcs
*v
, *n
;
3070 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3071 loaded_vmcss_on_cpu_link
)
3072 __loaded_vmcs_clear(v
);
3076 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3079 static void kvm_cpu_vmxoff(void)
3081 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3084 static void hardware_disable(void)
3086 if (vmm_exclusive
) {
3087 vmclear_local_loaded_vmcss();
3090 cr4_clear_bits(X86_CR4_VMXE
);
3093 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3094 u32 msr
, u32
*result
)
3096 u32 vmx_msr_low
, vmx_msr_high
;
3097 u32 ctl
= ctl_min
| ctl_opt
;
3099 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3101 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3102 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3104 /* Ensure minimum (required) set of control bits are supported. */
3112 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3114 u32 vmx_msr_low
, vmx_msr_high
;
3116 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3117 return vmx_msr_high
& ctl
;
3120 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3122 u32 vmx_msr_low
, vmx_msr_high
;
3123 u32 min
, opt
, min2
, opt2
;
3124 u32 _pin_based_exec_control
= 0;
3125 u32 _cpu_based_exec_control
= 0;
3126 u32 _cpu_based_2nd_exec_control
= 0;
3127 u32 _vmexit_control
= 0;
3128 u32 _vmentry_control
= 0;
3130 min
= CPU_BASED_HLT_EXITING
|
3131 #ifdef CONFIG_X86_64
3132 CPU_BASED_CR8_LOAD_EXITING
|
3133 CPU_BASED_CR8_STORE_EXITING
|
3135 CPU_BASED_CR3_LOAD_EXITING
|
3136 CPU_BASED_CR3_STORE_EXITING
|
3137 CPU_BASED_USE_IO_BITMAPS
|
3138 CPU_BASED_MOV_DR_EXITING
|
3139 CPU_BASED_USE_TSC_OFFSETING
|
3140 CPU_BASED_MWAIT_EXITING
|
3141 CPU_BASED_MONITOR_EXITING
|
3142 CPU_BASED_INVLPG_EXITING
|
3143 CPU_BASED_RDPMC_EXITING
;
3145 opt
= CPU_BASED_TPR_SHADOW
|
3146 CPU_BASED_USE_MSR_BITMAPS
|
3147 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3148 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3149 &_cpu_based_exec_control
) < 0)
3151 #ifdef CONFIG_X86_64
3152 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3153 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3154 ~CPU_BASED_CR8_STORE_EXITING
;
3156 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3158 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3159 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3160 SECONDARY_EXEC_WBINVD_EXITING
|
3161 SECONDARY_EXEC_ENABLE_VPID
|
3162 SECONDARY_EXEC_ENABLE_EPT
|
3163 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3164 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3165 SECONDARY_EXEC_RDTSCP
|
3166 SECONDARY_EXEC_ENABLE_INVPCID
|
3167 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3168 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3169 SECONDARY_EXEC_SHADOW_VMCS
|
3170 SECONDARY_EXEC_XSAVES
|
3171 SECONDARY_EXEC_ENABLE_PML
|
3172 SECONDARY_EXEC_PCOMMIT
|
3173 SECONDARY_EXEC_TSC_SCALING
;
3174 if (adjust_vmx_controls(min2
, opt2
,
3175 MSR_IA32_VMX_PROCBASED_CTLS2
,
3176 &_cpu_based_2nd_exec_control
) < 0)
3179 #ifndef CONFIG_X86_64
3180 if (!(_cpu_based_2nd_exec_control
&
3181 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3182 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3185 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3186 _cpu_based_2nd_exec_control
&= ~(
3187 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3188 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3189 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3191 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3192 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3194 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3195 CPU_BASED_CR3_STORE_EXITING
|
3196 CPU_BASED_INVLPG_EXITING
);
3197 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3198 vmx_capability
.ept
, vmx_capability
.vpid
);
3201 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3202 #ifdef CONFIG_X86_64
3203 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3205 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3206 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3207 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3208 &_vmexit_control
) < 0)
3211 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3212 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3213 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3214 &_pin_based_exec_control
) < 0)
3217 if (!(_cpu_based_2nd_exec_control
&
3218 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3219 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3220 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3222 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3223 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3224 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3225 &_vmentry_control
) < 0)
3228 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3230 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3231 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3234 #ifdef CONFIG_X86_64
3235 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3236 if (vmx_msr_high
& (1u<<16))
3240 /* Require Write-Back (WB) memory type for VMCS accesses. */
3241 if (((vmx_msr_high
>> 18) & 15) != 6)
3244 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3245 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3246 vmcs_conf
->revision_id
= vmx_msr_low
;
3248 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3249 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3250 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3251 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3252 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3254 cpu_has_load_ia32_efer
=
3255 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3256 VM_ENTRY_LOAD_IA32_EFER
)
3257 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3258 VM_EXIT_LOAD_IA32_EFER
);
3260 cpu_has_load_perf_global_ctrl
=
3261 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3262 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3263 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3264 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3267 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3268 * but due to arrata below it can't be used. Workaround is to use
3269 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3271 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3276 * BC86,AAY89,BD102 (model 44)
3280 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3281 switch (boot_cpu_data
.x86_model
) {
3287 cpu_has_load_perf_global_ctrl
= false;
3288 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3289 "does not work properly. Using workaround\n");
3297 rdmsrl(MSR_IA32_XSS
, host_xss
);
3302 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3304 int node
= cpu_to_node(cpu
);
3308 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3311 vmcs
= page_address(pages
);
3312 memset(vmcs
, 0, vmcs_config
.size
);
3313 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3317 static struct vmcs
*alloc_vmcs(void)
3319 return alloc_vmcs_cpu(raw_smp_processor_id());
3322 static void free_vmcs(struct vmcs
*vmcs
)
3324 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3328 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3330 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3332 if (!loaded_vmcs
->vmcs
)
3334 loaded_vmcs_clear(loaded_vmcs
);
3335 free_vmcs(loaded_vmcs
->vmcs
);
3336 loaded_vmcs
->vmcs
= NULL
;
3339 static void free_kvm_area(void)
3343 for_each_possible_cpu(cpu
) {
3344 free_vmcs(per_cpu(vmxarea
, cpu
));
3345 per_cpu(vmxarea
, cpu
) = NULL
;
3349 static void init_vmcs_shadow_fields(void)
3353 /* No checks for read only fields yet */
3355 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3356 switch (shadow_read_write_fields
[i
]) {
3358 if (!vmx_mpx_supported())
3366 shadow_read_write_fields
[j
] =
3367 shadow_read_write_fields
[i
];
3370 max_shadow_read_write_fields
= j
;
3372 /* shadowed fields guest access without vmexit */
3373 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3374 clear_bit(shadow_read_write_fields
[i
],
3375 vmx_vmwrite_bitmap
);
3376 clear_bit(shadow_read_write_fields
[i
],
3379 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3380 clear_bit(shadow_read_only_fields
[i
],
3384 static __init
int alloc_kvm_area(void)
3388 for_each_possible_cpu(cpu
) {
3391 vmcs
= alloc_vmcs_cpu(cpu
);
3397 per_cpu(vmxarea
, cpu
) = vmcs
;
3402 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3404 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3407 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3408 struct kvm_segment
*save
)
3410 if (!emulate_invalid_guest_state
) {
3412 * CS and SS RPL should be equal during guest entry according
3413 * to VMX spec, but in reality it is not always so. Since vcpu
3414 * is in the middle of the transition from real mode to
3415 * protected mode it is safe to assume that RPL 0 is a good
3418 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3419 save
->selector
&= ~SEGMENT_RPL_MASK
;
3420 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3423 vmx_set_segment(vcpu
, save
, seg
);
3426 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3428 unsigned long flags
;
3429 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3432 * Update real mode segment cache. It may be not up-to-date if sement
3433 * register was written while vcpu was in a guest mode.
3435 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3436 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3437 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3438 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3439 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3440 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3442 vmx
->rmode
.vm86_active
= 0;
3444 vmx_segment_cache_clear(vmx
);
3446 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3448 flags
= vmcs_readl(GUEST_RFLAGS
);
3449 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3450 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3451 vmcs_writel(GUEST_RFLAGS
, flags
);
3453 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3454 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3456 update_exception_bitmap(vcpu
);
3458 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3459 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3460 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3461 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3462 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3463 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3466 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3468 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3469 struct kvm_segment var
= *save
;
3472 if (seg
== VCPU_SREG_CS
)
3475 if (!emulate_invalid_guest_state
) {
3476 var
.selector
= var
.base
>> 4;
3477 var
.base
= var
.base
& 0xffff0;
3487 if (save
->base
& 0xf)
3488 printk_once(KERN_WARNING
"kvm: segment base is not "
3489 "paragraph aligned when entering "
3490 "protected mode (seg=%d)", seg
);
3493 vmcs_write16(sf
->selector
, var
.selector
);
3494 vmcs_write32(sf
->base
, var
.base
);
3495 vmcs_write32(sf
->limit
, var
.limit
);
3496 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3499 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3501 unsigned long flags
;
3502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3504 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3505 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3506 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3507 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3508 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3509 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3510 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3512 vmx
->rmode
.vm86_active
= 1;
3515 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3516 * vcpu. Warn the user that an update is overdue.
3518 if (!vcpu
->kvm
->arch
.tss_addr
)
3519 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3520 "called before entering vcpu\n");
3522 vmx_segment_cache_clear(vmx
);
3524 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3525 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3526 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3528 flags
= vmcs_readl(GUEST_RFLAGS
);
3529 vmx
->rmode
.save_rflags
= flags
;
3531 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3533 vmcs_writel(GUEST_RFLAGS
, flags
);
3534 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3535 update_exception_bitmap(vcpu
);
3537 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3538 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3539 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3540 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3541 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3542 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3544 kvm_mmu_reset_context(vcpu
);
3547 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3549 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3550 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3556 * Force kernel_gs_base reloading before EFER changes, as control
3557 * of this msr depends on is_long_mode().
3559 vmx_load_host_state(to_vmx(vcpu
));
3560 vcpu
->arch
.efer
= efer
;
3561 if (efer
& EFER_LMA
) {
3562 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3565 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3567 msr
->data
= efer
& ~EFER_LME
;
3572 #ifdef CONFIG_X86_64
3574 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3578 vmx_segment_cache_clear(to_vmx(vcpu
));
3580 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3581 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3582 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3584 vmcs_write32(GUEST_TR_AR_BYTES
,
3585 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3586 | VMX_AR_TYPE_BUSY_64_TSS
);
3588 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3591 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3593 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3594 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3599 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3601 vpid_sync_context(vpid
);
3603 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3605 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3609 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3611 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3614 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3616 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3618 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3619 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3622 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3624 if (enable_ept
&& is_paging(vcpu
))
3625 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3626 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3629 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3631 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3633 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3634 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3637 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3639 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3641 if (!test_bit(VCPU_EXREG_PDPTR
,
3642 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3645 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3646 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3647 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3648 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3649 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3653 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3655 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3657 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3658 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3659 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3660 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3661 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3664 __set_bit(VCPU_EXREG_PDPTR
,
3665 (unsigned long *)&vcpu
->arch
.regs_avail
);
3666 __set_bit(VCPU_EXREG_PDPTR
,
3667 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3670 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3672 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3674 struct kvm_vcpu
*vcpu
)
3676 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3677 vmx_decache_cr3(vcpu
);
3678 if (!(cr0
& X86_CR0_PG
)) {
3679 /* From paging/starting to nonpaging */
3680 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3681 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3682 (CPU_BASED_CR3_LOAD_EXITING
|
3683 CPU_BASED_CR3_STORE_EXITING
));
3684 vcpu
->arch
.cr0
= cr0
;
3685 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3686 } else if (!is_paging(vcpu
)) {
3687 /* From nonpaging to paging */
3688 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3689 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3690 ~(CPU_BASED_CR3_LOAD_EXITING
|
3691 CPU_BASED_CR3_STORE_EXITING
));
3692 vcpu
->arch
.cr0
= cr0
;
3693 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3696 if (!(cr0
& X86_CR0_WP
))
3697 *hw_cr0
&= ~X86_CR0_WP
;
3700 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3702 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3703 unsigned long hw_cr0
;
3705 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3706 if (enable_unrestricted_guest
)
3707 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3709 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3711 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3714 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3718 #ifdef CONFIG_X86_64
3719 if (vcpu
->arch
.efer
& EFER_LME
) {
3720 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3722 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3728 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3730 if (!vcpu
->fpu_active
)
3731 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3733 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3734 vmcs_writel(GUEST_CR0
, hw_cr0
);
3735 vcpu
->arch
.cr0
= cr0
;
3737 /* depends on vcpu->arch.cr0 to be set to a new value */
3738 vmx
->emulation_required
= emulation_required(vcpu
);
3741 static u64
construct_eptp(unsigned long root_hpa
)
3745 /* TODO write the value reading from MSR */
3746 eptp
= VMX_EPT_DEFAULT_MT
|
3747 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3748 if (enable_ept_ad_bits
)
3749 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3750 eptp
|= (root_hpa
& PAGE_MASK
);
3755 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3757 unsigned long guest_cr3
;
3762 eptp
= construct_eptp(cr3
);
3763 vmcs_write64(EPT_POINTER
, eptp
);
3764 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3765 guest_cr3
= kvm_read_cr3(vcpu
);
3767 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3768 ept_load_pdptrs(vcpu
);
3771 vmx_flush_tlb(vcpu
);
3772 vmcs_writel(GUEST_CR3
, guest_cr3
);
3775 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3778 * Pass through host's Machine Check Enable value to hw_cr4, which
3779 * is in force while we are in guest mode. Do not let guests control
3780 * this bit, even if host CR4.MCE == 0.
3782 unsigned long hw_cr4
=
3783 (cr4_read_shadow() & X86_CR4_MCE
) |
3784 (cr4
& ~X86_CR4_MCE
) |
3785 (to_vmx(vcpu
)->rmode
.vm86_active
?
3786 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3788 if (cr4
& X86_CR4_VMXE
) {
3790 * To use VMXON (and later other VMX instructions), a guest
3791 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3792 * So basically the check on whether to allow nested VMX
3795 if (!nested_vmx_allowed(vcpu
))
3798 if (to_vmx(vcpu
)->nested
.vmxon
&&
3799 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3802 vcpu
->arch
.cr4
= cr4
;
3804 if (!is_paging(vcpu
)) {
3805 hw_cr4
&= ~X86_CR4_PAE
;
3806 hw_cr4
|= X86_CR4_PSE
;
3807 } else if (!(cr4
& X86_CR4_PAE
)) {
3808 hw_cr4
&= ~X86_CR4_PAE
;
3812 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
3814 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3815 * hardware. However KVM always uses paging mode without
3816 * unrestricted guest.
3817 * To emulate this behavior, SMEP/SMAP needs to be manually
3818 * disabled when guest switches to non-paging mode.
3820 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3822 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3823 vmcs_writel(GUEST_CR4
, hw_cr4
);
3827 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3828 struct kvm_segment
*var
, int seg
)
3830 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3833 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3834 *var
= vmx
->rmode
.segs
[seg
];
3835 if (seg
== VCPU_SREG_TR
3836 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3838 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3839 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3842 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3843 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3844 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3845 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3846 var
->unusable
= (ar
>> 16) & 1;
3847 var
->type
= ar
& 15;
3848 var
->s
= (ar
>> 4) & 1;
3849 var
->dpl
= (ar
>> 5) & 3;
3851 * Some userspaces do not preserve unusable property. Since usable
3852 * segment has to be present according to VMX spec we can use present
3853 * property to amend userspace bug by making unusable segment always
3854 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3855 * segment as unusable.
3857 var
->present
= !var
->unusable
;
3858 var
->avl
= (ar
>> 12) & 1;
3859 var
->l
= (ar
>> 13) & 1;
3860 var
->db
= (ar
>> 14) & 1;
3861 var
->g
= (ar
>> 15) & 1;
3864 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3866 struct kvm_segment s
;
3868 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3869 vmx_get_segment(vcpu
, &s
, seg
);
3872 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3875 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3877 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3879 if (unlikely(vmx
->rmode
.vm86_active
))
3882 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3883 return VMX_AR_DPL(ar
);
3887 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3891 if (var
->unusable
|| !var
->present
)
3894 ar
= var
->type
& 15;
3895 ar
|= (var
->s
& 1) << 4;
3896 ar
|= (var
->dpl
& 3) << 5;
3897 ar
|= (var
->present
& 1) << 7;
3898 ar
|= (var
->avl
& 1) << 12;
3899 ar
|= (var
->l
& 1) << 13;
3900 ar
|= (var
->db
& 1) << 14;
3901 ar
|= (var
->g
& 1) << 15;
3907 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3908 struct kvm_segment
*var
, int seg
)
3910 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3911 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3913 vmx_segment_cache_clear(vmx
);
3915 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3916 vmx
->rmode
.segs
[seg
] = *var
;
3917 if (seg
== VCPU_SREG_TR
)
3918 vmcs_write16(sf
->selector
, var
->selector
);
3920 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3924 vmcs_writel(sf
->base
, var
->base
);
3925 vmcs_write32(sf
->limit
, var
->limit
);
3926 vmcs_write16(sf
->selector
, var
->selector
);
3929 * Fix the "Accessed" bit in AR field of segment registers for older
3931 * IA32 arch specifies that at the time of processor reset the
3932 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3933 * is setting it to 0 in the userland code. This causes invalid guest
3934 * state vmexit when "unrestricted guest" mode is turned on.
3935 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3936 * tree. Newer qemu binaries with that qemu fix would not need this
3939 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3940 var
->type
|= 0x1; /* Accessed */
3942 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3945 vmx
->emulation_required
= emulation_required(vcpu
);
3948 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3950 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3952 *db
= (ar
>> 14) & 1;
3953 *l
= (ar
>> 13) & 1;
3956 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3958 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3959 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3962 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3964 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3965 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3968 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3970 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3971 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3974 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3976 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3977 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3980 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3982 struct kvm_segment var
;
3985 vmx_get_segment(vcpu
, &var
, seg
);
3987 if (seg
== VCPU_SREG_CS
)
3989 ar
= vmx_segment_access_rights(&var
);
3991 if (var
.base
!= (var
.selector
<< 4))
3993 if (var
.limit
!= 0xffff)
4001 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4003 struct kvm_segment cs
;
4004 unsigned int cs_rpl
;
4006 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4007 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4011 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4015 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4016 if (cs
.dpl
> cs_rpl
)
4019 if (cs
.dpl
!= cs_rpl
)
4025 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4029 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4031 struct kvm_segment ss
;
4032 unsigned int ss_rpl
;
4034 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4035 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4039 if (ss
.type
!= 3 && ss
.type
!= 7)
4043 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4051 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4053 struct kvm_segment var
;
4056 vmx_get_segment(vcpu
, &var
, seg
);
4057 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4065 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4066 if (var
.dpl
< rpl
) /* DPL < RPL */
4070 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4076 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4078 struct kvm_segment tr
;
4080 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4084 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4086 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4094 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4096 struct kvm_segment ldtr
;
4098 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4102 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4112 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4114 struct kvm_segment cs
, ss
;
4116 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4117 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4119 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4120 (ss
.selector
& SEGMENT_RPL_MASK
));
4124 * Check if guest state is valid. Returns true if valid, false if
4126 * We assume that registers are always usable
4128 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4130 if (enable_unrestricted_guest
)
4133 /* real mode guest state checks */
4134 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4135 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4137 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4139 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4141 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4143 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4145 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4148 /* protected mode guest state checks */
4149 if (!cs_ss_rpl_check(vcpu
))
4151 if (!code_segment_valid(vcpu
))
4153 if (!stack_segment_valid(vcpu
))
4155 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4157 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4159 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4161 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4163 if (!tr_valid(vcpu
))
4165 if (!ldtr_valid(vcpu
))
4169 * - Add checks on RIP
4170 * - Add checks on RFLAGS
4176 static int init_rmode_tss(struct kvm
*kvm
)
4182 idx
= srcu_read_lock(&kvm
->srcu
);
4183 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4184 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4187 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4188 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4189 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4192 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4195 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4199 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4200 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4203 srcu_read_unlock(&kvm
->srcu
, idx
);
4207 static int init_rmode_identity_map(struct kvm
*kvm
)
4210 pfn_t identity_map_pfn
;
4216 /* Protect kvm->arch.ept_identity_pagetable_done. */
4217 mutex_lock(&kvm
->slots_lock
);
4219 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4222 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4224 r
= alloc_identity_pagetable(kvm
);
4228 idx
= srcu_read_lock(&kvm
->srcu
);
4229 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4232 /* Set up identity-mapping pagetable for EPT in real mode */
4233 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4234 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4235 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4236 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4237 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4241 kvm
->arch
.ept_identity_pagetable_done
= true;
4244 srcu_read_unlock(&kvm
->srcu
, idx
);
4247 mutex_unlock(&kvm
->slots_lock
);
4251 static void seg_setup(int seg
)
4253 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4256 vmcs_write16(sf
->selector
, 0);
4257 vmcs_writel(sf
->base
, 0);
4258 vmcs_write32(sf
->limit
, 0xffff);
4260 if (seg
== VCPU_SREG_CS
)
4261 ar
|= 0x08; /* code segment */
4263 vmcs_write32(sf
->ar_bytes
, ar
);
4266 static int alloc_apic_access_page(struct kvm
*kvm
)
4271 mutex_lock(&kvm
->slots_lock
);
4272 if (kvm
->arch
.apic_access_page_done
)
4274 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4275 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4279 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4280 if (is_error_page(page
)) {
4286 * Do not pin the page in memory, so that memory hot-unplug
4287 * is able to migrate it.
4290 kvm
->arch
.apic_access_page_done
= true;
4292 mutex_unlock(&kvm
->slots_lock
);
4296 static int alloc_identity_pagetable(struct kvm
*kvm
)
4298 /* Called with kvm->slots_lock held. */
4302 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4304 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4305 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4310 static int allocate_vpid(void)
4316 spin_lock(&vmx_vpid_lock
);
4317 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4318 if (vpid
< VMX_NR_VPIDS
)
4319 __set_bit(vpid
, vmx_vpid_bitmap
);
4322 spin_unlock(&vmx_vpid_lock
);
4326 static void free_vpid(int vpid
)
4328 if (!enable_vpid
|| vpid
== 0)
4330 spin_lock(&vmx_vpid_lock
);
4331 __clear_bit(vpid
, vmx_vpid_bitmap
);
4332 spin_unlock(&vmx_vpid_lock
);
4335 #define MSR_TYPE_R 1
4336 #define MSR_TYPE_W 2
4337 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4340 int f
= sizeof(unsigned long);
4342 if (!cpu_has_vmx_msr_bitmap())
4346 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4347 * have the write-low and read-high bitmap offsets the wrong way round.
4348 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4350 if (msr
<= 0x1fff) {
4351 if (type
& MSR_TYPE_R
)
4353 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4355 if (type
& MSR_TYPE_W
)
4357 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4359 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4361 if (type
& MSR_TYPE_R
)
4363 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4365 if (type
& MSR_TYPE_W
)
4367 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4372 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4375 int f
= sizeof(unsigned long);
4377 if (!cpu_has_vmx_msr_bitmap())
4381 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4382 * have the write-low and read-high bitmap offsets the wrong way round.
4383 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4385 if (msr
<= 0x1fff) {
4386 if (type
& MSR_TYPE_R
)
4388 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4390 if (type
& MSR_TYPE_W
)
4392 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4394 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4396 if (type
& MSR_TYPE_R
)
4398 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4400 if (type
& MSR_TYPE_W
)
4402 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4408 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4409 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4411 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4412 unsigned long *msr_bitmap_nested
,
4415 int f
= sizeof(unsigned long);
4417 if (!cpu_has_vmx_msr_bitmap()) {
4423 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4424 * have the write-low and read-high bitmap offsets the wrong way round.
4425 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4427 if (msr
<= 0x1fff) {
4428 if (type
& MSR_TYPE_R
&&
4429 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4431 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4433 if (type
& MSR_TYPE_W
&&
4434 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4436 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4438 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4440 if (type
& MSR_TYPE_R
&&
4441 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4443 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4445 if (type
& MSR_TYPE_W
&&
4446 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4448 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4453 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4456 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4457 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4458 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4459 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4462 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4464 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4466 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4470 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4472 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4474 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4478 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4480 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4482 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4486 static int vmx_cpu_uses_apicv(struct kvm_vcpu
*vcpu
)
4488 return enable_apicv
&& lapic_in_kernel(vcpu
);
4491 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4493 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4498 if (vmx
->nested
.pi_desc
&&
4499 vmx
->nested
.pi_pending
) {
4500 vmx
->nested
.pi_pending
= false;
4501 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4504 max_irr
= find_last_bit(
4505 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4510 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4515 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4516 kunmap(vmx
->nested
.virtual_apic_page
);
4518 status
= vmcs_read16(GUEST_INTR_STATUS
);
4519 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4521 status
|= (u8
)max_irr
;
4522 vmcs_write16(GUEST_INTR_STATUS
, status
);
4528 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4531 if (vcpu
->mode
== IN_GUEST_MODE
) {
4532 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4535 * Currently, we don't support urgent interrupt,
4536 * all interrupts are recognized as non-urgent
4537 * interrupt, so we cannot post interrupts when
4540 * If the vcpu is in guest mode, it means it is
4541 * running instead of being scheduled out and
4542 * waiting in the run queue, and that's the only
4543 * case when 'SN' is set currently, warning if
4546 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4548 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4549 POSTED_INTR_VECTOR
);
4556 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4559 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4561 if (is_guest_mode(vcpu
) &&
4562 vector
== vmx
->nested
.posted_intr_nv
) {
4563 /* the PIR and ON have been set by L1. */
4564 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4566 * If a posted intr is not recognized by hardware,
4567 * we will accomplish it in the next vmentry.
4569 vmx
->nested
.pi_pending
= true;
4570 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4576 * Send interrupt to vcpu via posted interrupt way.
4577 * 1. If target vcpu is running(non-root mode), send posted interrupt
4578 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4579 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4580 * interrupt from PIR in next vmentry.
4582 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4584 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4587 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4591 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4594 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4595 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4596 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4597 kvm_vcpu_kick(vcpu
);
4600 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4602 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4604 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4607 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4610 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4616 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4617 * will not change in the lifetime of the guest.
4618 * Note that host-state that does change is set elsewhere. E.g., host-state
4619 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4621 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4628 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4629 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4631 /* Save the most likely value for this task's CR4 in the VMCS. */
4632 cr4
= cr4_read_shadow();
4633 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4634 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4636 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4637 #ifdef CONFIG_X86_64
4639 * Load null selectors, so we can avoid reloading them in
4640 * __vmx_load_host_state(), in case userspace uses the null selectors
4641 * too (the expected case).
4643 vmcs_write16(HOST_DS_SELECTOR
, 0);
4644 vmcs_write16(HOST_ES_SELECTOR
, 0);
4646 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4647 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4649 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4650 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4652 native_store_idt(&dt
);
4653 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4654 vmx
->host_idt_base
= dt
.address
;
4656 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4658 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4659 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4660 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4661 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4663 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4664 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4665 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4669 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4671 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4673 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4674 if (is_guest_mode(&vmx
->vcpu
))
4675 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4676 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4677 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4680 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4682 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4684 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4685 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4686 return pin_based_exec_ctrl
;
4689 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4691 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4693 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4694 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4696 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4697 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4698 #ifdef CONFIG_X86_64
4699 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4700 CPU_BASED_CR8_LOAD_EXITING
;
4704 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4705 CPU_BASED_CR3_LOAD_EXITING
|
4706 CPU_BASED_INVLPG_EXITING
;
4707 return exec_control
;
4710 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4712 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4713 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4714 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4716 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4718 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4719 enable_unrestricted_guest
= 0;
4720 /* Enable INVPCID for non-ept guests may cause performance regression. */
4721 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4723 if (!enable_unrestricted_guest
)
4724 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4726 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4727 if (!vmx_cpu_uses_apicv(&vmx
->vcpu
))
4728 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4729 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4730 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4731 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4733 We can NOT enable shadow_vmcs here because we don't have yet
4736 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4739 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4741 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4742 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4744 return exec_control
;
4747 static void ept_set_mmio_spte_mask(void)
4750 * EPT Misconfigurations can be generated if the value of bits 2:0
4751 * of an EPT paging-structure entry is 110b (write/execute).
4752 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4755 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4758 #define VMX_XSS_EXIT_BITMAP 0
4760 * Sets up the vmcs for emulated real mode.
4762 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4764 #ifdef CONFIG_X86_64
4770 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4771 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4773 if (enable_shadow_vmcs
) {
4774 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4775 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4777 if (cpu_has_vmx_msr_bitmap())
4778 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4780 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4783 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4785 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4787 if (cpu_has_secondary_exec_ctrls())
4788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4789 vmx_secondary_exec_control(vmx
));
4791 if (vmx_cpu_uses_apicv(&vmx
->vcpu
)) {
4792 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4793 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4794 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4795 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4797 vmcs_write16(GUEST_INTR_STATUS
, 0);
4799 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4800 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4804 vmcs_write32(PLE_GAP
, ple_gap
);
4805 vmx
->ple_window
= ple_window
;
4806 vmx
->ple_window_dirty
= true;
4809 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4810 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4811 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4813 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4814 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4815 vmx_set_constant_host_state(vmx
);
4816 #ifdef CONFIG_X86_64
4817 rdmsrl(MSR_FS_BASE
, a
);
4818 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4819 rdmsrl(MSR_GS_BASE
, a
);
4820 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4822 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4823 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4826 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4827 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4828 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4829 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4830 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4832 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4833 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4835 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4836 u32 index
= vmx_msr_index
[i
];
4837 u32 data_low
, data_high
;
4840 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4842 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4844 vmx
->guest_msrs
[j
].index
= i
;
4845 vmx
->guest_msrs
[j
].data
= 0;
4846 vmx
->guest_msrs
[j
].mask
= -1ull;
4851 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4853 /* 22.2.1, 20.8.1 */
4854 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4856 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4857 set_cr4_guest_host_mask(vmx
);
4859 if (vmx_xsaves_supported())
4860 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4865 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4867 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4868 struct msr_data apic_base_msr
;
4871 vmx
->rmode
.vm86_active
= 0;
4873 vmx
->soft_vnmi_blocked
= 0;
4875 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4876 kvm_set_cr8(vcpu
, 0);
4879 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4880 MSR_IA32_APICBASE_ENABLE
;
4881 if (kvm_vcpu_is_reset_bsp(vcpu
))
4882 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4883 apic_base_msr
.host_initiated
= true;
4884 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4887 vmx_segment_cache_clear(vmx
);
4889 seg_setup(VCPU_SREG_CS
);
4890 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4891 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4893 seg_setup(VCPU_SREG_DS
);
4894 seg_setup(VCPU_SREG_ES
);
4895 seg_setup(VCPU_SREG_FS
);
4896 seg_setup(VCPU_SREG_GS
);
4897 seg_setup(VCPU_SREG_SS
);
4899 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4900 vmcs_writel(GUEST_TR_BASE
, 0);
4901 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4902 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4904 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4905 vmcs_writel(GUEST_LDTR_BASE
, 0);
4906 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4907 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4910 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4911 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4912 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4913 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4916 vmcs_writel(GUEST_RFLAGS
, 0x02);
4917 kvm_rip_write(vcpu
, 0xfff0);
4919 vmcs_writel(GUEST_GDTR_BASE
, 0);
4920 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4922 vmcs_writel(GUEST_IDTR_BASE
, 0);
4923 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4925 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4926 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4927 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4931 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4933 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4934 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4935 if (cpu_need_tpr_shadow(vcpu
))
4936 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4937 __pa(vcpu
->arch
.apic
->regs
));
4938 vmcs_write32(TPR_THRESHOLD
, 0);
4941 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4943 if (vmx_cpu_uses_apicv(vcpu
))
4944 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4947 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4949 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4950 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
4951 vmx
->vcpu
.arch
.cr0
= cr0
;
4952 vmx_set_cr4(vcpu
, 0);
4953 vmx_set_efer(vcpu
, 0);
4954 vmx_fpu_activate(vcpu
);
4955 update_exception_bitmap(vcpu
);
4957 vpid_sync_context(vmx
->vpid
);
4961 * In nested virtualization, check if L1 asked to exit on external interrupts.
4962 * For most existing hypervisors, this will always return true.
4964 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4966 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4967 PIN_BASED_EXT_INTR_MASK
;
4971 * In nested virtualization, check if L1 has set
4972 * VM_EXIT_ACK_INTR_ON_EXIT
4974 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4976 return get_vmcs12(vcpu
)->vm_exit_controls
&
4977 VM_EXIT_ACK_INTR_ON_EXIT
;
4980 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4982 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4983 PIN_BASED_NMI_EXITING
;
4986 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4988 u32 cpu_based_vm_exec_control
;
4990 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4991 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4992 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4995 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4997 u32 cpu_based_vm_exec_control
;
4999 if (!cpu_has_virtual_nmis() ||
5000 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5001 enable_irq_window(vcpu
);
5005 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5006 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5007 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5010 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5012 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5014 int irq
= vcpu
->arch
.interrupt
.nr
;
5016 trace_kvm_inj_virq(irq
);
5018 ++vcpu
->stat
.irq_injections
;
5019 if (vmx
->rmode
.vm86_active
) {
5021 if (vcpu
->arch
.interrupt
.soft
)
5022 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5023 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5024 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5027 intr
= irq
| INTR_INFO_VALID_MASK
;
5028 if (vcpu
->arch
.interrupt
.soft
) {
5029 intr
|= INTR_TYPE_SOFT_INTR
;
5030 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5031 vmx
->vcpu
.arch
.event_exit_inst_len
);
5033 intr
|= INTR_TYPE_EXT_INTR
;
5034 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5037 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5039 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5041 if (is_guest_mode(vcpu
))
5044 if (!cpu_has_virtual_nmis()) {
5046 * Tracking the NMI-blocked state in software is built upon
5047 * finding the next open IRQ window. This, in turn, depends on
5048 * well-behaving guests: They have to keep IRQs disabled at
5049 * least as long as the NMI handler runs. Otherwise we may
5050 * cause NMI nesting, maybe breaking the guest. But as this is
5051 * highly unlikely, we can live with the residual risk.
5053 vmx
->soft_vnmi_blocked
= 1;
5054 vmx
->vnmi_blocked_time
= 0;
5057 ++vcpu
->stat
.nmi_injections
;
5058 vmx
->nmi_known_unmasked
= false;
5059 if (vmx
->rmode
.vm86_active
) {
5060 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5061 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5064 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5065 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5068 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5070 if (!cpu_has_virtual_nmis())
5071 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5072 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5074 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5077 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5079 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5081 if (!cpu_has_virtual_nmis()) {
5082 if (vmx
->soft_vnmi_blocked
!= masked
) {
5083 vmx
->soft_vnmi_blocked
= masked
;
5084 vmx
->vnmi_blocked_time
= 0;
5087 vmx
->nmi_known_unmasked
= !masked
;
5089 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5090 GUEST_INTR_STATE_NMI
);
5092 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5093 GUEST_INTR_STATE_NMI
);
5097 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5099 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5102 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5105 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5106 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5107 | GUEST_INTR_STATE_NMI
));
5110 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5112 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5113 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5114 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5115 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5118 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5122 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5126 kvm
->arch
.tss_addr
= addr
;
5127 return init_rmode_tss(kvm
);
5130 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5135 * Update instruction length as we may reinject the exception
5136 * from user space while in guest debugging mode.
5138 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5139 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5140 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5144 if (vcpu
->guest_debug
&
5145 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5162 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5163 int vec
, u32 err_code
)
5166 * Instruction with address size override prefix opcode 0x67
5167 * Cause the #SS fault with 0 error code in VM86 mode.
5169 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5170 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5171 if (vcpu
->arch
.halt_request
) {
5172 vcpu
->arch
.halt_request
= 0;
5173 return kvm_vcpu_halt(vcpu
);
5181 * Forward all other exceptions that are valid in real mode.
5182 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5183 * the required debugging infrastructure rework.
5185 kvm_queue_exception(vcpu
, vec
);
5190 * Trigger machine check on the host. We assume all the MSRs are already set up
5191 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5192 * We pass a fake environment to the machine check handler because we want
5193 * the guest to be always treated like user space, no matter what context
5194 * it used internally.
5196 static void kvm_machine_check(void)
5198 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5199 struct pt_regs regs
= {
5200 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5201 .flags
= X86_EFLAGS_IF
,
5204 do_machine_check(®s
, 0);
5208 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5210 /* already handled by vcpu_run */
5214 static int handle_exception(struct kvm_vcpu
*vcpu
)
5216 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5217 struct kvm_run
*kvm_run
= vcpu
->run
;
5218 u32 intr_info
, ex_no
, error_code
;
5219 unsigned long cr2
, rip
, dr6
;
5221 enum emulation_result er
;
5223 vect_info
= vmx
->idt_vectoring_info
;
5224 intr_info
= vmx
->exit_intr_info
;
5226 if (is_machine_check(intr_info
))
5227 return handle_machine_check(vcpu
);
5229 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5230 return 1; /* already handled by vmx_vcpu_run() */
5232 if (is_no_device(intr_info
)) {
5233 vmx_fpu_activate(vcpu
);
5237 if (is_invalid_opcode(intr_info
)) {
5238 if (is_guest_mode(vcpu
)) {
5239 kvm_queue_exception(vcpu
, UD_VECTOR
);
5242 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5243 if (er
!= EMULATE_DONE
)
5244 kvm_queue_exception(vcpu
, UD_VECTOR
);
5249 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5250 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5253 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5254 * MMIO, it is better to report an internal error.
5255 * See the comments in vmx_handle_exit.
5257 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5258 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5259 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5260 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5261 vcpu
->run
->internal
.ndata
= 3;
5262 vcpu
->run
->internal
.data
[0] = vect_info
;
5263 vcpu
->run
->internal
.data
[1] = intr_info
;
5264 vcpu
->run
->internal
.data
[2] = error_code
;
5268 if (is_page_fault(intr_info
)) {
5269 /* EPT won't cause page fault directly */
5271 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5272 trace_kvm_page_fault(cr2
, error_code
);
5274 if (kvm_event_needs_reinjection(vcpu
))
5275 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5276 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5279 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5281 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5282 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5286 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5289 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5290 if (!(vcpu
->guest_debug
&
5291 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5292 vcpu
->arch
.dr6
&= ~15;
5293 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5294 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5295 skip_emulated_instruction(vcpu
);
5297 kvm_queue_exception(vcpu
, DB_VECTOR
);
5300 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5301 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5305 * Update instruction length as we may reinject #BP from
5306 * user space while in guest debugging mode. Reading it for
5307 * #DB as well causes no harm, it is not used in that case.
5309 vmx
->vcpu
.arch
.event_exit_inst_len
=
5310 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5311 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5312 rip
= kvm_rip_read(vcpu
);
5313 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5314 kvm_run
->debug
.arch
.exception
= ex_no
;
5317 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5318 kvm_run
->ex
.exception
= ex_no
;
5319 kvm_run
->ex
.error_code
= error_code
;
5325 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5327 ++vcpu
->stat
.irq_exits
;
5331 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5333 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5337 static int handle_io(struct kvm_vcpu
*vcpu
)
5339 unsigned long exit_qualification
;
5340 int size
, in
, string
;
5343 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5344 string
= (exit_qualification
& 16) != 0;
5345 in
= (exit_qualification
& 8) != 0;
5347 ++vcpu
->stat
.io_exits
;
5350 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5352 port
= exit_qualification
>> 16;
5353 size
= (exit_qualification
& 7) + 1;
5354 skip_emulated_instruction(vcpu
);
5356 return kvm_fast_pio_out(vcpu
, size
, port
);
5360 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5363 * Patch in the VMCALL instruction:
5365 hypercall
[0] = 0x0f;
5366 hypercall
[1] = 0x01;
5367 hypercall
[2] = 0xc1;
5370 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5372 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5373 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5375 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5376 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5377 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5378 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5379 return (val
& always_on
) == always_on
;
5382 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5383 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5385 if (is_guest_mode(vcpu
)) {
5386 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5387 unsigned long orig_val
= val
;
5390 * We get here when L2 changed cr0 in a way that did not change
5391 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5392 * but did change L0 shadowed bits. So we first calculate the
5393 * effective cr0 value that L1 would like to write into the
5394 * hardware. It consists of the L2-owned bits from the new
5395 * value combined with the L1-owned bits from L1's guest_cr0.
5397 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5398 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5400 if (!nested_cr0_valid(vcpu
, val
))
5403 if (kvm_set_cr0(vcpu
, val
))
5405 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5408 if (to_vmx(vcpu
)->nested
.vmxon
&&
5409 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5411 return kvm_set_cr0(vcpu
, val
);
5415 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5417 if (is_guest_mode(vcpu
)) {
5418 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5419 unsigned long orig_val
= val
;
5421 /* analogously to handle_set_cr0 */
5422 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5423 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5424 if (kvm_set_cr4(vcpu
, val
))
5426 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5429 return kvm_set_cr4(vcpu
, val
);
5432 /* called to set cr0 as approriate for clts instruction exit. */
5433 static void handle_clts(struct kvm_vcpu
*vcpu
)
5435 if (is_guest_mode(vcpu
)) {
5437 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5438 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5439 * just pretend it's off (also in arch.cr0 for fpu_activate).
5441 vmcs_writel(CR0_READ_SHADOW
,
5442 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5443 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5445 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5448 static int handle_cr(struct kvm_vcpu
*vcpu
)
5450 unsigned long exit_qualification
, val
;
5455 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5456 cr
= exit_qualification
& 15;
5457 reg
= (exit_qualification
>> 8) & 15;
5458 switch ((exit_qualification
>> 4) & 3) {
5459 case 0: /* mov to cr */
5460 val
= kvm_register_readl(vcpu
, reg
);
5461 trace_kvm_cr_write(cr
, val
);
5464 err
= handle_set_cr0(vcpu
, val
);
5465 kvm_complete_insn_gp(vcpu
, err
);
5468 err
= kvm_set_cr3(vcpu
, val
);
5469 kvm_complete_insn_gp(vcpu
, err
);
5472 err
= handle_set_cr4(vcpu
, val
);
5473 kvm_complete_insn_gp(vcpu
, err
);
5476 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5478 err
= kvm_set_cr8(vcpu
, cr8
);
5479 kvm_complete_insn_gp(vcpu
, err
);
5480 if (lapic_in_kernel(vcpu
))
5482 if (cr8_prev
<= cr8
)
5484 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5491 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5492 skip_emulated_instruction(vcpu
);
5493 vmx_fpu_activate(vcpu
);
5495 case 1: /*mov from cr*/
5498 val
= kvm_read_cr3(vcpu
);
5499 kvm_register_write(vcpu
, reg
, val
);
5500 trace_kvm_cr_read(cr
, val
);
5501 skip_emulated_instruction(vcpu
);
5504 val
= kvm_get_cr8(vcpu
);
5505 kvm_register_write(vcpu
, reg
, val
);
5506 trace_kvm_cr_read(cr
, val
);
5507 skip_emulated_instruction(vcpu
);
5512 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5513 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5514 kvm_lmsw(vcpu
, val
);
5516 skip_emulated_instruction(vcpu
);
5521 vcpu
->run
->exit_reason
= 0;
5522 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5523 (int)(exit_qualification
>> 4) & 3, cr
);
5527 static int handle_dr(struct kvm_vcpu
*vcpu
)
5529 unsigned long exit_qualification
;
5532 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5533 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5535 /* First, if DR does not exist, trigger UD */
5536 if (!kvm_require_dr(vcpu
, dr
))
5539 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5540 if (!kvm_require_cpl(vcpu
, 0))
5542 dr7
= vmcs_readl(GUEST_DR7
);
5545 * As the vm-exit takes precedence over the debug trap, we
5546 * need to emulate the latter, either for the host or the
5547 * guest debugging itself.
5549 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5550 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5551 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5552 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5553 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5554 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5557 vcpu
->arch
.dr6
&= ~15;
5558 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5559 kvm_queue_exception(vcpu
, DB_VECTOR
);
5564 if (vcpu
->guest_debug
== 0) {
5565 u32 cpu_based_vm_exec_control
;
5567 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5568 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5572 * No more DR vmexits; force a reload of the debug registers
5573 * and reenter on this instruction. The next vmexit will
5574 * retrieve the full state of the debug registers.
5576 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5580 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5581 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5584 if (kvm_get_dr(vcpu
, dr
, &val
))
5586 kvm_register_write(vcpu
, reg
, val
);
5588 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5591 skip_emulated_instruction(vcpu
);
5595 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5597 return vcpu
->arch
.dr6
;
5600 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5604 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5606 u32 cpu_based_vm_exec_control
;
5608 get_debugreg(vcpu
->arch
.db
[0], 0);
5609 get_debugreg(vcpu
->arch
.db
[1], 1);
5610 get_debugreg(vcpu
->arch
.db
[2], 2);
5611 get_debugreg(vcpu
->arch
.db
[3], 3);
5612 get_debugreg(vcpu
->arch
.dr6
, 6);
5613 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5615 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5617 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5618 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5619 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5622 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5624 vmcs_writel(GUEST_DR7
, val
);
5627 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5629 kvm_emulate_cpuid(vcpu
);
5633 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5635 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5636 struct msr_data msr_info
;
5638 msr_info
.index
= ecx
;
5639 msr_info
.host_initiated
= false;
5640 if (vmx_get_msr(vcpu
, &msr_info
)) {
5641 trace_kvm_msr_read_ex(ecx
);
5642 kvm_inject_gp(vcpu
, 0);
5646 trace_kvm_msr_read(ecx
, msr_info
.data
);
5648 /* FIXME: handling of bits 32:63 of rax, rdx */
5649 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5650 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5651 skip_emulated_instruction(vcpu
);
5655 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5657 struct msr_data msr
;
5658 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5659 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5660 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5664 msr
.host_initiated
= false;
5665 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5666 trace_kvm_msr_write_ex(ecx
, data
);
5667 kvm_inject_gp(vcpu
, 0);
5671 trace_kvm_msr_write(ecx
, data
);
5672 skip_emulated_instruction(vcpu
);
5676 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5678 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5682 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5684 u32 cpu_based_vm_exec_control
;
5686 /* clear pending irq */
5687 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5688 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5689 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5691 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5693 ++vcpu
->stat
.irq_window_exits
;
5697 static int handle_halt(struct kvm_vcpu
*vcpu
)
5699 return kvm_emulate_halt(vcpu
);
5702 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5704 kvm_emulate_hypercall(vcpu
);
5708 static int handle_invd(struct kvm_vcpu
*vcpu
)
5710 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5713 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5715 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5717 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5718 skip_emulated_instruction(vcpu
);
5722 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5726 err
= kvm_rdpmc(vcpu
);
5727 kvm_complete_insn_gp(vcpu
, err
);
5732 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5734 kvm_emulate_wbinvd(vcpu
);
5738 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5740 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5741 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5743 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5744 skip_emulated_instruction(vcpu
);
5748 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5750 skip_emulated_instruction(vcpu
);
5751 WARN(1, "this should never happen\n");
5755 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5757 skip_emulated_instruction(vcpu
);
5758 WARN(1, "this should never happen\n");
5762 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5764 if (likely(fasteoi
)) {
5765 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5766 int access_type
, offset
;
5768 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5769 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5771 * Sane guest uses MOV to write EOI, with written value
5772 * not cared. So make a short-circuit here by avoiding
5773 * heavy instruction emulation.
5775 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5776 (offset
== APIC_EOI
)) {
5777 kvm_lapic_set_eoi(vcpu
);
5778 skip_emulated_instruction(vcpu
);
5782 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5785 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5787 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5788 int vector
= exit_qualification
& 0xff;
5790 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5791 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5795 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5797 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5798 u32 offset
= exit_qualification
& 0xfff;
5800 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5801 kvm_apic_write_nodecode(vcpu
, offset
);
5805 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5807 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5808 unsigned long exit_qualification
;
5809 bool has_error_code
= false;
5812 int reason
, type
, idt_v
, idt_index
;
5814 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5815 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5816 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5818 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5820 reason
= (u32
)exit_qualification
>> 30;
5821 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5823 case INTR_TYPE_NMI_INTR
:
5824 vcpu
->arch
.nmi_injected
= false;
5825 vmx_set_nmi_mask(vcpu
, true);
5827 case INTR_TYPE_EXT_INTR
:
5828 case INTR_TYPE_SOFT_INTR
:
5829 kvm_clear_interrupt_queue(vcpu
);
5831 case INTR_TYPE_HARD_EXCEPTION
:
5832 if (vmx
->idt_vectoring_info
&
5833 VECTORING_INFO_DELIVER_CODE_MASK
) {
5834 has_error_code
= true;
5836 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5839 case INTR_TYPE_SOFT_EXCEPTION
:
5840 kvm_clear_exception_queue(vcpu
);
5846 tss_selector
= exit_qualification
;
5848 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5849 type
!= INTR_TYPE_EXT_INTR
&&
5850 type
!= INTR_TYPE_NMI_INTR
))
5851 skip_emulated_instruction(vcpu
);
5853 if (kvm_task_switch(vcpu
, tss_selector
,
5854 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5855 has_error_code
, error_code
) == EMULATE_FAIL
) {
5856 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5857 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5858 vcpu
->run
->internal
.ndata
= 0;
5863 * TODO: What about debug traps on tss switch?
5864 * Are we supposed to inject them and update dr6?
5870 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5872 unsigned long exit_qualification
;
5877 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5879 gla_validity
= (exit_qualification
>> 7) & 0x3;
5880 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5881 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5882 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5883 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5884 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5885 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5886 (long unsigned int)exit_qualification
);
5887 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5888 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5893 * EPT violation happened while executing iret from NMI,
5894 * "blocked by NMI" bit has to be set before next VM entry.
5895 * There are errata that may cause this bit to not be set:
5898 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5899 cpu_has_virtual_nmis() &&
5900 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5901 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5903 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5904 trace_kvm_page_fault(gpa
, exit_qualification
);
5906 /* It is a write fault? */
5907 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5908 /* It is a fetch fault? */
5909 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5910 /* ept page table is present? */
5911 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5913 vcpu
->arch
.exit_qualification
= exit_qualification
;
5915 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5918 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5923 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5924 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5925 skip_emulated_instruction(vcpu
);
5926 trace_kvm_fast_mmio(gpa
);
5930 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
5931 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5932 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5935 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5936 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5938 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5941 /* It is the real ept misconfig */
5944 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5945 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5950 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5952 u32 cpu_based_vm_exec_control
;
5954 /* clear pending NMI */
5955 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5956 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5957 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5958 ++vcpu
->stat
.nmi_window_exits
;
5959 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5964 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5966 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5967 enum emulation_result err
= EMULATE_DONE
;
5970 bool intr_window_requested
;
5971 unsigned count
= 130;
5973 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5974 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5976 while (vmx
->emulation_required
&& count
-- != 0) {
5977 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5978 return handle_interrupt_window(&vmx
->vcpu
);
5980 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5983 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5985 if (err
== EMULATE_USER_EXIT
) {
5986 ++vcpu
->stat
.mmio_exits
;
5991 if (err
!= EMULATE_DONE
) {
5992 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5993 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5994 vcpu
->run
->internal
.ndata
= 0;
5998 if (vcpu
->arch
.halt_request
) {
5999 vcpu
->arch
.halt_request
= 0;
6000 ret
= kvm_vcpu_halt(vcpu
);
6004 if (signal_pending(current
))
6014 static int __grow_ple_window(int val
)
6016 if (ple_window_grow
< 1)
6019 val
= min(val
, ple_window_actual_max
);
6021 if (ple_window_grow
< ple_window
)
6022 val
*= ple_window_grow
;
6024 val
+= ple_window_grow
;
6029 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6034 if (modifier
< ple_window
)
6039 return max(val
, minimum
);
6042 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6044 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6045 int old
= vmx
->ple_window
;
6047 vmx
->ple_window
= __grow_ple_window(old
);
6049 if (vmx
->ple_window
!= old
)
6050 vmx
->ple_window_dirty
= true;
6052 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6055 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6057 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6058 int old
= vmx
->ple_window
;
6060 vmx
->ple_window
= __shrink_ple_window(old
,
6061 ple_window_shrink
, ple_window
);
6063 if (vmx
->ple_window
!= old
)
6064 vmx
->ple_window_dirty
= true;
6066 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6070 * ple_window_actual_max is computed to be one grow_ple_window() below
6071 * ple_window_max. (See __grow_ple_window for the reason.)
6072 * This prevents overflows, because ple_window_max is int.
6073 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6075 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6077 static void update_ple_window_actual_max(void)
6079 ple_window_actual_max
=
6080 __shrink_ple_window(max(ple_window_max
, ple_window
),
6081 ple_window_grow
, INT_MIN
);
6085 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6087 static void wakeup_handler(void)
6089 struct kvm_vcpu
*vcpu
;
6090 int cpu
= smp_processor_id();
6092 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6093 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6094 blocked_vcpu_list
) {
6095 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6097 if (pi_test_on(pi_desc
) == 1)
6098 kvm_vcpu_kick(vcpu
);
6100 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6103 static __init
int hardware_setup(void)
6105 int r
= -ENOMEM
, i
, msr
;
6107 rdmsrl_safe(MSR_EFER
, &host_efer
);
6109 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6110 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6112 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6113 if (!vmx_io_bitmap_a
)
6116 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6117 if (!vmx_io_bitmap_b
)
6120 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6121 if (!vmx_msr_bitmap_legacy
)
6124 vmx_msr_bitmap_legacy_x2apic
=
6125 (unsigned long *)__get_free_page(GFP_KERNEL
);
6126 if (!vmx_msr_bitmap_legacy_x2apic
)
6129 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6130 if (!vmx_msr_bitmap_longmode
)
6133 vmx_msr_bitmap_longmode_x2apic
=
6134 (unsigned long *)__get_free_page(GFP_KERNEL
);
6135 if (!vmx_msr_bitmap_longmode_x2apic
)
6139 vmx_msr_bitmap_nested
=
6140 (unsigned long *)__get_free_page(GFP_KERNEL
);
6141 if (!vmx_msr_bitmap_nested
)
6145 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6146 if (!vmx_vmread_bitmap
)
6149 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6150 if (!vmx_vmwrite_bitmap
)
6153 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6154 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6157 * Allow direct access to the PC debug port (it is often used for I/O
6158 * delays, but the vmexits simply slow things down).
6160 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6161 clear_bit(0x80, vmx_io_bitmap_a
);
6163 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6165 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6166 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6168 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6170 if (setup_vmcs_config(&vmcs_config
) < 0) {
6175 if (boot_cpu_has(X86_FEATURE_NX
))
6176 kvm_enable_efer_bits(EFER_NX
);
6178 if (!cpu_has_vmx_vpid())
6180 if (!cpu_has_vmx_shadow_vmcs())
6181 enable_shadow_vmcs
= 0;
6182 if (enable_shadow_vmcs
)
6183 init_vmcs_shadow_fields();
6185 if (!cpu_has_vmx_ept() ||
6186 !cpu_has_vmx_ept_4levels()) {
6188 enable_unrestricted_guest
= 0;
6189 enable_ept_ad_bits
= 0;
6192 if (!cpu_has_vmx_ept_ad_bits())
6193 enable_ept_ad_bits
= 0;
6195 if (!cpu_has_vmx_unrestricted_guest())
6196 enable_unrestricted_guest
= 0;
6198 if (!cpu_has_vmx_flexpriority())
6199 flexpriority_enabled
= 0;
6202 * set_apic_access_page_addr() is used to reload apic access
6203 * page upon invalidation. No need to do anything if not
6204 * using the APIC_ACCESS_ADDR VMCS field.
6206 if (!flexpriority_enabled
)
6207 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6209 if (!cpu_has_vmx_tpr_shadow())
6210 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6212 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6213 kvm_disable_largepages();
6215 if (!cpu_has_vmx_ple())
6218 if (!cpu_has_vmx_apicv())
6221 if (cpu_has_vmx_tsc_scaling()) {
6222 kvm_has_tsc_control
= true;
6223 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6224 kvm_tsc_scaling_ratio_frac_bits
= 48;
6228 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6230 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6231 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6232 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6233 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6236 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6237 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6238 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6239 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6240 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6241 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6242 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6244 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6245 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6246 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6247 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6249 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6252 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6253 vmx_disable_intercept_msr_read_x2apic(msr
);
6255 /* According SDM, in x2apic mode, the whole id reg is used.
6256 * But in KVM, it only use the highest eight bits. Need to
6258 vmx_enable_intercept_msr_read_x2apic(0x802);
6260 vmx_enable_intercept_msr_read_x2apic(0x839);
6262 vmx_disable_intercept_msr_write_x2apic(0x808);
6264 vmx_disable_intercept_msr_write_x2apic(0x80b);
6266 vmx_disable_intercept_msr_write_x2apic(0x83f);
6270 kvm_mmu_set_mask_ptes(0ull,
6271 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6272 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6273 0ull, VMX_EPT_EXECUTABLE_MASK
);
6274 ept_set_mmio_spte_mask();
6279 update_ple_window_actual_max();
6282 * Only enable PML when hardware supports PML feature, and both EPT
6283 * and EPT A/D bit features are enabled -- PML depends on them to work.
6285 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6289 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6290 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6291 kvm_x86_ops
->flush_log_dirty
= NULL
;
6292 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6295 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6297 return alloc_kvm_area();
6300 free_page((unsigned long)vmx_vmwrite_bitmap
);
6302 free_page((unsigned long)vmx_vmread_bitmap
);
6305 free_page((unsigned long)vmx_msr_bitmap_nested
);
6307 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6309 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6311 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6313 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6315 free_page((unsigned long)vmx_io_bitmap_b
);
6317 free_page((unsigned long)vmx_io_bitmap_a
);
6322 static __exit
void hardware_unsetup(void)
6324 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6325 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6326 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6327 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6328 free_page((unsigned long)vmx_io_bitmap_b
);
6329 free_page((unsigned long)vmx_io_bitmap_a
);
6330 free_page((unsigned long)vmx_vmwrite_bitmap
);
6331 free_page((unsigned long)vmx_vmread_bitmap
);
6333 free_page((unsigned long)vmx_msr_bitmap_nested
);
6339 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6340 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6342 static int handle_pause(struct kvm_vcpu
*vcpu
)
6345 grow_ple_window(vcpu
);
6347 skip_emulated_instruction(vcpu
);
6348 kvm_vcpu_on_spin(vcpu
);
6353 static int handle_nop(struct kvm_vcpu
*vcpu
)
6355 skip_emulated_instruction(vcpu
);
6359 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6361 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6362 return handle_nop(vcpu
);
6365 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6370 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6372 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6373 return handle_nop(vcpu
);
6377 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6378 * We could reuse a single VMCS for all the L2 guests, but we also want the
6379 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6380 * allows keeping them loaded on the processor, and in the future will allow
6381 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6382 * every entry if they never change.
6383 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6384 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6386 * The following functions allocate and free a vmcs02 in this pool.
6389 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6390 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6392 struct vmcs02_list
*item
;
6393 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6394 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6395 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6396 return &item
->vmcs02
;
6399 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6400 /* Recycle the least recently used VMCS. */
6401 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6402 struct vmcs02_list
, list
);
6403 item
->vmptr
= vmx
->nested
.current_vmptr
;
6404 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6405 return &item
->vmcs02
;
6408 /* Create a new VMCS */
6409 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6412 item
->vmcs02
.vmcs
= alloc_vmcs();
6413 if (!item
->vmcs02
.vmcs
) {
6417 loaded_vmcs_init(&item
->vmcs02
);
6418 item
->vmptr
= vmx
->nested
.current_vmptr
;
6419 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6420 vmx
->nested
.vmcs02_num
++;
6421 return &item
->vmcs02
;
6424 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6425 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6427 struct vmcs02_list
*item
;
6428 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6429 if (item
->vmptr
== vmptr
) {
6430 free_loaded_vmcs(&item
->vmcs02
);
6431 list_del(&item
->list
);
6433 vmx
->nested
.vmcs02_num
--;
6439 * Free all VMCSs saved for this vcpu, except the one pointed by
6440 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6441 * must be &vmx->vmcs01.
6443 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6445 struct vmcs02_list
*item
, *n
;
6447 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6448 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6450 * Something will leak if the above WARN triggers. Better than
6453 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6456 free_loaded_vmcs(&item
->vmcs02
);
6457 list_del(&item
->list
);
6459 vmx
->nested
.vmcs02_num
--;
6464 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6465 * set the success or error code of an emulated VMX instruction, as specified
6466 * by Vol 2B, VMX Instruction Reference, "Conventions".
6468 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6470 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6471 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6472 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6475 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6477 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6478 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6479 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6483 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6484 u32 vm_instruction_error
)
6486 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6488 * failValid writes the error number to the current VMCS, which
6489 * can't be done there isn't a current VMCS.
6491 nested_vmx_failInvalid(vcpu
);
6494 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6495 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6496 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6498 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6500 * We don't need to force a shadow sync because
6501 * VM_INSTRUCTION_ERROR is not shadowed
6505 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6507 /* TODO: not to reset guest simply here. */
6508 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6509 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6512 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6514 struct vcpu_vmx
*vmx
=
6515 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6517 vmx
->nested
.preemption_timer_expired
= true;
6518 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6519 kvm_vcpu_kick(&vmx
->vcpu
);
6521 return HRTIMER_NORESTART
;
6525 * Decode the memory-address operand of a vmx instruction, as recorded on an
6526 * exit caused by such an instruction (run by a guest hypervisor).
6527 * On success, returns 0. When the operand is invalid, returns 1 and throws
6530 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6531 unsigned long exit_qualification
,
6532 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6536 struct kvm_segment s
;
6539 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6540 * Execution", on an exit, vmx_instruction_info holds most of the
6541 * addressing components of the operand. Only the displacement part
6542 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6543 * For how an actual address is calculated from all these components,
6544 * refer to Vol. 1, "Operand Addressing".
6546 int scaling
= vmx_instruction_info
& 3;
6547 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6548 bool is_reg
= vmx_instruction_info
& (1u << 10);
6549 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6550 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6551 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6552 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6553 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6556 kvm_queue_exception(vcpu
, UD_VECTOR
);
6560 /* Addr = segment_base + offset */
6561 /* offset = base + [index * scale] + displacement */
6562 off
= exit_qualification
; /* holds the displacement */
6564 off
+= kvm_register_read(vcpu
, base_reg
);
6566 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6567 vmx_get_segment(vcpu
, &s
, seg_reg
);
6568 *ret
= s
.base
+ off
;
6570 if (addr_size
== 1) /* 32 bit */
6573 /* Checks for #GP/#SS exceptions. */
6575 if (is_protmode(vcpu
)) {
6576 /* Protected mode: apply checks for segment validity in the
6578 * - segment type check (#GP(0) may be thrown)
6579 * - usability check (#GP(0)/#SS(0))
6580 * - limit check (#GP(0)/#SS(0))
6583 /* #GP(0) if the destination operand is located in a
6584 * read-only data segment or any code segment.
6586 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6588 /* #GP(0) if the source operand is located in an
6589 * execute-only code segment
6591 exn
= ((s
.type
& 0xa) == 8);
6594 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6597 if (is_long_mode(vcpu
)) {
6598 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6599 * non-canonical form. This is an only check for long mode.
6601 exn
= is_noncanonical_address(*ret
);
6602 } else if (is_protmode(vcpu
)) {
6603 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6605 exn
= (s
.unusable
!= 0);
6606 /* Protected mode: #GP(0)/#SS(0) if the memory
6607 * operand is outside the segment limit.
6609 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6612 kvm_queue_exception_e(vcpu
,
6613 seg_reg
== VCPU_SREG_SS
?
6614 SS_VECTOR
: GP_VECTOR
,
6623 * This function performs the various checks including
6624 * - if it's 4KB aligned
6625 * - No bits beyond the physical address width are set
6626 * - Returns 0 on success or else 1
6627 * (Intel SDM Section 30.3)
6629 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6634 struct x86_exception e
;
6636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6637 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6639 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6640 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6643 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6644 sizeof(vmptr
), &e
)) {
6645 kvm_inject_page_fault(vcpu
, &e
);
6649 switch (exit_reason
) {
6650 case EXIT_REASON_VMON
:
6653 * The first 4 bytes of VMXON region contain the supported
6654 * VMCS revision identifier
6656 * Note - IA32_VMX_BASIC[48] will never be 1
6657 * for the nested case;
6658 * which replaces physical address width with 32
6661 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6662 nested_vmx_failInvalid(vcpu
);
6663 skip_emulated_instruction(vcpu
);
6667 page
= nested_get_page(vcpu
, vmptr
);
6669 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6670 nested_vmx_failInvalid(vcpu
);
6672 skip_emulated_instruction(vcpu
);
6676 vmx
->nested
.vmxon_ptr
= vmptr
;
6678 case EXIT_REASON_VMCLEAR
:
6679 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6680 nested_vmx_failValid(vcpu
,
6681 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6682 skip_emulated_instruction(vcpu
);
6686 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6687 nested_vmx_failValid(vcpu
,
6688 VMXERR_VMCLEAR_VMXON_POINTER
);
6689 skip_emulated_instruction(vcpu
);
6693 case EXIT_REASON_VMPTRLD
:
6694 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6695 nested_vmx_failValid(vcpu
,
6696 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6697 skip_emulated_instruction(vcpu
);
6701 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6702 nested_vmx_failValid(vcpu
,
6703 VMXERR_VMCLEAR_VMXON_POINTER
);
6704 skip_emulated_instruction(vcpu
);
6709 return 1; /* shouldn't happen */
6718 * Emulate the VMXON instruction.
6719 * Currently, we just remember that VMX is active, and do not save or even
6720 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6721 * do not currently need to store anything in that guest-allocated memory
6722 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6723 * argument is different from the VMXON pointer (which the spec says they do).
6725 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6727 struct kvm_segment cs
;
6728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6729 struct vmcs
*shadow_vmcs
;
6730 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6731 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6733 /* The Intel VMX Instruction Reference lists a bunch of bits that
6734 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6735 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6736 * Otherwise, we should fail with #UD. We test these now:
6738 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6739 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6740 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6741 kvm_queue_exception(vcpu
, UD_VECTOR
);
6745 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6746 if (is_long_mode(vcpu
) && !cs
.l
) {
6747 kvm_queue_exception(vcpu
, UD_VECTOR
);
6751 if (vmx_get_cpl(vcpu
)) {
6752 kvm_inject_gp(vcpu
, 0);
6756 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6759 if (vmx
->nested
.vmxon
) {
6760 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6761 skip_emulated_instruction(vcpu
);
6765 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6766 != VMXON_NEEDED_FEATURES
) {
6767 kvm_inject_gp(vcpu
, 0);
6771 if (enable_shadow_vmcs
) {
6772 shadow_vmcs
= alloc_vmcs();
6775 /* mark vmcs as shadow */
6776 shadow_vmcs
->revision_id
|= (1u << 31);
6777 /* init shadow vmcs */
6778 vmcs_clear(shadow_vmcs
);
6779 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6782 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6783 vmx
->nested
.vmcs02_num
= 0;
6785 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6787 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6789 vmx
->nested
.vmxon
= true;
6791 skip_emulated_instruction(vcpu
);
6792 nested_vmx_succeed(vcpu
);
6797 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6798 * for running VMX instructions (except VMXON, whose prerequisites are
6799 * slightly different). It also specifies what exception to inject otherwise.
6801 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6803 struct kvm_segment cs
;
6804 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6806 if (!vmx
->nested
.vmxon
) {
6807 kvm_queue_exception(vcpu
, UD_VECTOR
);
6811 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6812 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6813 (is_long_mode(vcpu
) && !cs
.l
)) {
6814 kvm_queue_exception(vcpu
, UD_VECTOR
);
6818 if (vmx_get_cpl(vcpu
)) {
6819 kvm_inject_gp(vcpu
, 0);
6826 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6828 if (vmx
->nested
.current_vmptr
== -1ull)
6831 /* current_vmptr and current_vmcs12 are always set/reset together */
6832 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6835 if (enable_shadow_vmcs
) {
6836 /* copy to memory all shadowed fields in case
6837 they were modified */
6838 copy_shadow_to_vmcs12(vmx
);
6839 vmx
->nested
.sync_shadow_vmcs
= false;
6840 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6841 SECONDARY_EXEC_SHADOW_VMCS
);
6842 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6844 vmx
->nested
.posted_intr_nv
= -1;
6845 kunmap(vmx
->nested
.current_vmcs12_page
);
6846 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6847 vmx
->nested
.current_vmptr
= -1ull;
6848 vmx
->nested
.current_vmcs12
= NULL
;
6852 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6853 * just stops using VMX.
6855 static void free_nested(struct vcpu_vmx
*vmx
)
6857 if (!vmx
->nested
.vmxon
)
6860 vmx
->nested
.vmxon
= false;
6861 free_vpid(vmx
->nested
.vpid02
);
6862 nested_release_vmcs12(vmx
);
6863 if (enable_shadow_vmcs
)
6864 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6865 /* Unpin physical memory we referred to in current vmcs02 */
6866 if (vmx
->nested
.apic_access_page
) {
6867 nested_release_page(vmx
->nested
.apic_access_page
);
6868 vmx
->nested
.apic_access_page
= NULL
;
6870 if (vmx
->nested
.virtual_apic_page
) {
6871 nested_release_page(vmx
->nested
.virtual_apic_page
);
6872 vmx
->nested
.virtual_apic_page
= NULL
;
6874 if (vmx
->nested
.pi_desc_page
) {
6875 kunmap(vmx
->nested
.pi_desc_page
);
6876 nested_release_page(vmx
->nested
.pi_desc_page
);
6877 vmx
->nested
.pi_desc_page
= NULL
;
6878 vmx
->nested
.pi_desc
= NULL
;
6881 nested_free_all_saved_vmcss(vmx
);
6884 /* Emulate the VMXOFF instruction */
6885 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6887 if (!nested_vmx_check_permission(vcpu
))
6889 free_nested(to_vmx(vcpu
));
6890 skip_emulated_instruction(vcpu
);
6891 nested_vmx_succeed(vcpu
);
6895 /* Emulate the VMCLEAR instruction */
6896 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6898 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6900 struct vmcs12
*vmcs12
;
6903 if (!nested_vmx_check_permission(vcpu
))
6906 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6909 if (vmptr
== vmx
->nested
.current_vmptr
)
6910 nested_release_vmcs12(vmx
);
6912 page
= nested_get_page(vcpu
, vmptr
);
6915 * For accurate processor emulation, VMCLEAR beyond available
6916 * physical memory should do nothing at all. However, it is
6917 * possible that a nested vmx bug, not a guest hypervisor bug,
6918 * resulted in this case, so let's shut down before doing any
6921 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6924 vmcs12
= kmap(page
);
6925 vmcs12
->launch_state
= 0;
6927 nested_release_page(page
);
6929 nested_free_vmcs02(vmx
, vmptr
);
6931 skip_emulated_instruction(vcpu
);
6932 nested_vmx_succeed(vcpu
);
6936 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6938 /* Emulate the VMLAUNCH instruction */
6939 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6941 return nested_vmx_run(vcpu
, true);
6944 /* Emulate the VMRESUME instruction */
6945 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6948 return nested_vmx_run(vcpu
, false);
6951 enum vmcs_field_type
{
6952 VMCS_FIELD_TYPE_U16
= 0,
6953 VMCS_FIELD_TYPE_U64
= 1,
6954 VMCS_FIELD_TYPE_U32
= 2,
6955 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6958 static inline int vmcs_field_type(unsigned long field
)
6960 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6961 return VMCS_FIELD_TYPE_U32
;
6962 return (field
>> 13) & 0x3 ;
6965 static inline int vmcs_field_readonly(unsigned long field
)
6967 return (((field
>> 10) & 0x3) == 1);
6971 * Read a vmcs12 field. Since these can have varying lengths and we return
6972 * one type, we chose the biggest type (u64) and zero-extend the return value
6973 * to that size. Note that the caller, handle_vmread, might need to use only
6974 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6975 * 64-bit fields are to be returned).
6977 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6978 unsigned long field
, u64
*ret
)
6980 short offset
= vmcs_field_to_offset(field
);
6986 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6988 switch (vmcs_field_type(field
)) {
6989 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6990 *ret
= *((natural_width
*)p
);
6992 case VMCS_FIELD_TYPE_U16
:
6995 case VMCS_FIELD_TYPE_U32
:
6998 case VMCS_FIELD_TYPE_U64
:
7008 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7009 unsigned long field
, u64 field_value
){
7010 short offset
= vmcs_field_to_offset(field
);
7011 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7015 switch (vmcs_field_type(field
)) {
7016 case VMCS_FIELD_TYPE_U16
:
7017 *(u16
*)p
= field_value
;
7019 case VMCS_FIELD_TYPE_U32
:
7020 *(u32
*)p
= field_value
;
7022 case VMCS_FIELD_TYPE_U64
:
7023 *(u64
*)p
= field_value
;
7025 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7026 *(natural_width
*)p
= field_value
;
7035 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7038 unsigned long field
;
7040 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7041 const unsigned long *fields
= shadow_read_write_fields
;
7042 const int num_fields
= max_shadow_read_write_fields
;
7046 vmcs_load(shadow_vmcs
);
7048 for (i
= 0; i
< num_fields
; i
++) {
7050 switch (vmcs_field_type(field
)) {
7051 case VMCS_FIELD_TYPE_U16
:
7052 field_value
= vmcs_read16(field
);
7054 case VMCS_FIELD_TYPE_U32
:
7055 field_value
= vmcs_read32(field
);
7057 case VMCS_FIELD_TYPE_U64
:
7058 field_value
= vmcs_read64(field
);
7060 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7061 field_value
= vmcs_readl(field
);
7067 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7070 vmcs_clear(shadow_vmcs
);
7071 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7076 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7078 const unsigned long *fields
[] = {
7079 shadow_read_write_fields
,
7080 shadow_read_only_fields
7082 const int max_fields
[] = {
7083 max_shadow_read_write_fields
,
7084 max_shadow_read_only_fields
7087 unsigned long field
;
7088 u64 field_value
= 0;
7089 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7091 vmcs_load(shadow_vmcs
);
7093 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7094 for (i
= 0; i
< max_fields
[q
]; i
++) {
7095 field
= fields
[q
][i
];
7096 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7098 switch (vmcs_field_type(field
)) {
7099 case VMCS_FIELD_TYPE_U16
:
7100 vmcs_write16(field
, (u16
)field_value
);
7102 case VMCS_FIELD_TYPE_U32
:
7103 vmcs_write32(field
, (u32
)field_value
);
7105 case VMCS_FIELD_TYPE_U64
:
7106 vmcs_write64(field
, (u64
)field_value
);
7108 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7109 vmcs_writel(field
, (long)field_value
);
7118 vmcs_clear(shadow_vmcs
);
7119 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7123 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7124 * used before) all generate the same failure when it is missing.
7126 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7129 if (vmx
->nested
.current_vmptr
== -1ull) {
7130 nested_vmx_failInvalid(vcpu
);
7131 skip_emulated_instruction(vcpu
);
7137 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7139 unsigned long field
;
7141 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7142 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7145 if (!nested_vmx_check_permission(vcpu
) ||
7146 !nested_vmx_check_vmcs12(vcpu
))
7149 /* Decode instruction info and find the field to read */
7150 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7151 /* Read the field, zero-extended to a u64 field_value */
7152 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7153 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7154 skip_emulated_instruction(vcpu
);
7158 * Now copy part of this value to register or memory, as requested.
7159 * Note that the number of bits actually copied is 32 or 64 depending
7160 * on the guest's mode (32 or 64 bit), not on the given field's length.
7162 if (vmx_instruction_info
& (1u << 10)) {
7163 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7166 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7167 vmx_instruction_info
, true, &gva
))
7169 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7170 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7171 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7174 nested_vmx_succeed(vcpu
);
7175 skip_emulated_instruction(vcpu
);
7180 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7182 unsigned long field
;
7184 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7185 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7186 /* The value to write might be 32 or 64 bits, depending on L1's long
7187 * mode, and eventually we need to write that into a field of several
7188 * possible lengths. The code below first zero-extends the value to 64
7189 * bit (field_value), and then copies only the approriate number of
7190 * bits into the vmcs12 field.
7192 u64 field_value
= 0;
7193 struct x86_exception e
;
7195 if (!nested_vmx_check_permission(vcpu
) ||
7196 !nested_vmx_check_vmcs12(vcpu
))
7199 if (vmx_instruction_info
& (1u << 10))
7200 field_value
= kvm_register_readl(vcpu
,
7201 (((vmx_instruction_info
) >> 3) & 0xf));
7203 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7204 vmx_instruction_info
, false, &gva
))
7206 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7207 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7208 kvm_inject_page_fault(vcpu
, &e
);
7214 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7215 if (vmcs_field_readonly(field
)) {
7216 nested_vmx_failValid(vcpu
,
7217 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7218 skip_emulated_instruction(vcpu
);
7222 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7223 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7224 skip_emulated_instruction(vcpu
);
7228 nested_vmx_succeed(vcpu
);
7229 skip_emulated_instruction(vcpu
);
7233 /* Emulate the VMPTRLD instruction */
7234 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7236 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7239 if (!nested_vmx_check_permission(vcpu
))
7242 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7245 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7246 struct vmcs12
*new_vmcs12
;
7248 page
= nested_get_page(vcpu
, vmptr
);
7250 nested_vmx_failInvalid(vcpu
);
7251 skip_emulated_instruction(vcpu
);
7254 new_vmcs12
= kmap(page
);
7255 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7257 nested_release_page_clean(page
);
7258 nested_vmx_failValid(vcpu
,
7259 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7260 skip_emulated_instruction(vcpu
);
7264 nested_release_vmcs12(vmx
);
7265 vmx
->nested
.current_vmptr
= vmptr
;
7266 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7267 vmx
->nested
.current_vmcs12_page
= page
;
7268 if (enable_shadow_vmcs
) {
7269 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7270 SECONDARY_EXEC_SHADOW_VMCS
);
7271 vmcs_write64(VMCS_LINK_POINTER
,
7272 __pa(vmx
->nested
.current_shadow_vmcs
));
7273 vmx
->nested
.sync_shadow_vmcs
= true;
7277 nested_vmx_succeed(vcpu
);
7278 skip_emulated_instruction(vcpu
);
7282 /* Emulate the VMPTRST instruction */
7283 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7285 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7286 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7288 struct x86_exception e
;
7290 if (!nested_vmx_check_permission(vcpu
))
7293 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7294 vmx_instruction_info
, true, &vmcs_gva
))
7296 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7297 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7298 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7300 kvm_inject_page_fault(vcpu
, &e
);
7303 nested_vmx_succeed(vcpu
);
7304 skip_emulated_instruction(vcpu
);
7308 /* Emulate the INVEPT instruction */
7309 static int handle_invept(struct kvm_vcpu
*vcpu
)
7311 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7312 u32 vmx_instruction_info
, types
;
7315 struct x86_exception e
;
7320 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7321 SECONDARY_EXEC_ENABLE_EPT
) ||
7322 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7323 kvm_queue_exception(vcpu
, UD_VECTOR
);
7327 if (!nested_vmx_check_permission(vcpu
))
7330 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7331 kvm_queue_exception(vcpu
, UD_VECTOR
);
7335 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7336 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7338 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7340 if (!(types
& (1UL << type
))) {
7341 nested_vmx_failValid(vcpu
,
7342 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7343 skip_emulated_instruction(vcpu
);
7347 /* According to the Intel VMX instruction reference, the memory
7348 * operand is read even if it isn't needed (e.g., for type==global)
7350 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7351 vmx_instruction_info
, false, &gva
))
7353 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7354 sizeof(operand
), &e
)) {
7355 kvm_inject_page_fault(vcpu
, &e
);
7360 case VMX_EPT_EXTENT_GLOBAL
:
7361 kvm_mmu_sync_roots(vcpu
);
7362 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7363 nested_vmx_succeed(vcpu
);
7366 /* Trap single context invalidation invept calls */
7371 skip_emulated_instruction(vcpu
);
7375 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7377 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7378 u32 vmx_instruction_info
;
7379 unsigned long type
, types
;
7381 struct x86_exception e
;
7384 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7385 SECONDARY_EXEC_ENABLE_VPID
) ||
7386 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7387 kvm_queue_exception(vcpu
, UD_VECTOR
);
7391 if (!nested_vmx_check_permission(vcpu
))
7394 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7395 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7397 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7399 if (!(types
& (1UL << type
))) {
7400 nested_vmx_failValid(vcpu
,
7401 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7405 /* according to the intel vmx instruction reference, the memory
7406 * operand is read even if it isn't needed (e.g., for type==global)
7408 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7409 vmx_instruction_info
, false, &gva
))
7411 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7413 kvm_inject_page_fault(vcpu
, &e
);
7418 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7419 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7420 nested_vmx_succeed(vcpu
);
7423 /* Trap single context invalidation invvpid calls */
7428 skip_emulated_instruction(vcpu
);
7432 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7434 unsigned long exit_qualification
;
7436 trace_kvm_pml_full(vcpu
->vcpu_id
);
7438 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7441 * PML buffer FULL happened while executing iret from NMI,
7442 * "blocked by NMI" bit has to be set before next VM entry.
7444 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7445 cpu_has_virtual_nmis() &&
7446 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7447 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7448 GUEST_INTR_STATE_NMI
);
7451 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7452 * here.., and there's no userspace involvement needed for PML.
7457 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7459 /* we never catch pcommit instruct for L1 guest. */
7465 * The exit handlers return 1 if the exit was handled fully and guest execution
7466 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7467 * to be done to userspace and return 0.
7469 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7470 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7471 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7472 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7473 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7474 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7475 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7476 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7477 [EXIT_REASON_CPUID
] = handle_cpuid
,
7478 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7479 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7480 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7481 [EXIT_REASON_HLT
] = handle_halt
,
7482 [EXIT_REASON_INVD
] = handle_invd
,
7483 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7484 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7485 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7486 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7487 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7488 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7489 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7490 [EXIT_REASON_VMREAD
] = handle_vmread
,
7491 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7492 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7493 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7494 [EXIT_REASON_VMON
] = handle_vmon
,
7495 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7496 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7497 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7498 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7499 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7500 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7501 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7502 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7503 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7504 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7505 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7506 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7507 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7508 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7509 [EXIT_REASON_INVEPT
] = handle_invept
,
7510 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7511 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7512 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7513 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7514 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7517 static const int kvm_vmx_max_exit_handlers
=
7518 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7520 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7521 struct vmcs12
*vmcs12
)
7523 unsigned long exit_qualification
;
7524 gpa_t bitmap
, last_bitmap
;
7529 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7530 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7532 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7534 port
= exit_qualification
>> 16;
7535 size
= (exit_qualification
& 7) + 1;
7537 last_bitmap
= (gpa_t
)-1;
7542 bitmap
= vmcs12
->io_bitmap_a
;
7543 else if (port
< 0x10000)
7544 bitmap
= vmcs12
->io_bitmap_b
;
7547 bitmap
+= (port
& 0x7fff) / 8;
7549 if (last_bitmap
!= bitmap
)
7550 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7552 if (b
& (1 << (port
& 7)))
7557 last_bitmap
= bitmap
;
7564 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7565 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7566 * disinterest in the current event (read or write a specific MSR) by using an
7567 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7569 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7570 struct vmcs12
*vmcs12
, u32 exit_reason
)
7572 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7575 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7579 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7580 * for the four combinations of read/write and low/high MSR numbers.
7581 * First we need to figure out which of the four to use:
7583 bitmap
= vmcs12
->msr_bitmap
;
7584 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7586 if (msr_index
>= 0xc0000000) {
7587 msr_index
-= 0xc0000000;
7591 /* Then read the msr_index'th bit from this bitmap: */
7592 if (msr_index
< 1024*8) {
7594 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7596 return 1 & (b
>> (msr_index
& 7));
7598 return true; /* let L1 handle the wrong parameter */
7602 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7603 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7604 * intercept (via guest_host_mask etc.) the current event.
7606 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7607 struct vmcs12
*vmcs12
)
7609 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7610 int cr
= exit_qualification
& 15;
7611 int reg
= (exit_qualification
>> 8) & 15;
7612 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7614 switch ((exit_qualification
>> 4) & 3) {
7615 case 0: /* mov to cr */
7618 if (vmcs12
->cr0_guest_host_mask
&
7619 (val
^ vmcs12
->cr0_read_shadow
))
7623 if ((vmcs12
->cr3_target_count
>= 1 &&
7624 vmcs12
->cr3_target_value0
== val
) ||
7625 (vmcs12
->cr3_target_count
>= 2 &&
7626 vmcs12
->cr3_target_value1
== val
) ||
7627 (vmcs12
->cr3_target_count
>= 3 &&
7628 vmcs12
->cr3_target_value2
== val
) ||
7629 (vmcs12
->cr3_target_count
>= 4 &&
7630 vmcs12
->cr3_target_value3
== val
))
7632 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7636 if (vmcs12
->cr4_guest_host_mask
&
7637 (vmcs12
->cr4_read_shadow
^ val
))
7641 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7647 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7648 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7651 case 1: /* mov from cr */
7654 if (vmcs12
->cpu_based_vm_exec_control
&
7655 CPU_BASED_CR3_STORE_EXITING
)
7659 if (vmcs12
->cpu_based_vm_exec_control
&
7660 CPU_BASED_CR8_STORE_EXITING
)
7667 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7668 * cr0. Other attempted changes are ignored, with no exit.
7670 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7671 (val
^ vmcs12
->cr0_read_shadow
))
7673 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7674 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7683 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7684 * should handle it ourselves in L0 (and then continue L2). Only call this
7685 * when in is_guest_mode (L2).
7687 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7689 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7690 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7691 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7692 u32 exit_reason
= vmx
->exit_reason
;
7694 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7695 vmcs_readl(EXIT_QUALIFICATION
),
7696 vmx
->idt_vectoring_info
,
7698 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7701 if (vmx
->nested
.nested_run_pending
)
7704 if (unlikely(vmx
->fail
)) {
7705 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7706 vmcs_read32(VM_INSTRUCTION_ERROR
));
7710 switch (exit_reason
) {
7711 case EXIT_REASON_EXCEPTION_NMI
:
7712 if (!is_exception(intr_info
))
7714 else if (is_page_fault(intr_info
))
7716 else if (is_no_device(intr_info
) &&
7717 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7719 return vmcs12
->exception_bitmap
&
7720 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7721 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7723 case EXIT_REASON_TRIPLE_FAULT
:
7725 case EXIT_REASON_PENDING_INTERRUPT
:
7726 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7727 case EXIT_REASON_NMI_WINDOW
:
7728 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7729 case EXIT_REASON_TASK_SWITCH
:
7731 case EXIT_REASON_CPUID
:
7732 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7735 case EXIT_REASON_HLT
:
7736 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7737 case EXIT_REASON_INVD
:
7739 case EXIT_REASON_INVLPG
:
7740 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7741 case EXIT_REASON_RDPMC
:
7742 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7743 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7744 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7745 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7746 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7747 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7748 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7749 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7750 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7752 * VMX instructions trap unconditionally. This allows L1 to
7753 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7756 case EXIT_REASON_CR_ACCESS
:
7757 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7758 case EXIT_REASON_DR_ACCESS
:
7759 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7760 case EXIT_REASON_IO_INSTRUCTION
:
7761 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7762 case EXIT_REASON_MSR_READ
:
7763 case EXIT_REASON_MSR_WRITE
:
7764 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7765 case EXIT_REASON_INVALID_STATE
:
7767 case EXIT_REASON_MWAIT_INSTRUCTION
:
7768 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7769 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7770 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7771 case EXIT_REASON_MONITOR_INSTRUCTION
:
7772 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7773 case EXIT_REASON_PAUSE_INSTRUCTION
:
7774 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7775 nested_cpu_has2(vmcs12
,
7776 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7777 case EXIT_REASON_MCE_DURING_VMENTRY
:
7779 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7780 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7781 case EXIT_REASON_APIC_ACCESS
:
7782 return nested_cpu_has2(vmcs12
,
7783 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7784 case EXIT_REASON_APIC_WRITE
:
7785 case EXIT_REASON_EOI_INDUCED
:
7786 /* apic_write and eoi_induced should exit unconditionally. */
7788 case EXIT_REASON_EPT_VIOLATION
:
7790 * L0 always deals with the EPT violation. If nested EPT is
7791 * used, and the nested mmu code discovers that the address is
7792 * missing in the guest EPT table (EPT12), the EPT violation
7793 * will be injected with nested_ept_inject_page_fault()
7796 case EXIT_REASON_EPT_MISCONFIG
:
7798 * L2 never uses directly L1's EPT, but rather L0's own EPT
7799 * table (shadow on EPT) or a merged EPT table that L0 built
7800 * (EPT on EPT). So any problems with the structure of the
7801 * table is L0's fault.
7804 case EXIT_REASON_WBINVD
:
7805 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7806 case EXIT_REASON_XSETBV
:
7808 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7810 * This should never happen, since it is not possible to
7811 * set XSS to a non-zero value---neither in L1 nor in L2.
7812 * If if it were, XSS would have to be checked against
7813 * the XSS exit bitmap in vmcs12.
7815 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7816 case EXIT_REASON_PCOMMIT
:
7817 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7823 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7825 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7826 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7829 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
7831 struct page
*pml_pg
;
7833 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7837 vmx
->pml_pg
= pml_pg
;
7839 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7840 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7845 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
7848 __free_page(vmx
->pml_pg
);
7853 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7855 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7859 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7861 /* Do nothing if PML buffer is empty */
7862 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7865 /* PML index always points to next available PML buffer entity */
7866 if (pml_idx
>= PML_ENTITY_NUM
)
7871 pml_buf
= page_address(vmx
->pml_pg
);
7872 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7875 gpa
= pml_buf
[pml_idx
];
7876 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7877 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7880 /* reset PML index */
7881 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7885 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7886 * Called before reporting dirty_bitmap to userspace.
7888 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7891 struct kvm_vcpu
*vcpu
;
7893 * We only need to kick vcpu out of guest mode here, as PML buffer
7894 * is flushed at beginning of all VMEXITs, and it's obvious that only
7895 * vcpus running in guest are possible to have unflushed GPAs in PML
7898 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7899 kvm_vcpu_kick(vcpu
);
7902 static void vmx_dump_sel(char *name
, uint32_t sel
)
7904 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7905 name
, vmcs_read32(sel
),
7906 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7907 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7908 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7911 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7913 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7914 name
, vmcs_read32(limit
),
7915 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7918 static void dump_vmcs(void)
7920 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7921 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7922 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7923 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7924 u32 secondary_exec_control
= 0;
7925 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7926 u64 efer
= vmcs_readl(GUEST_IA32_EFER
);
7929 if (cpu_has_secondary_exec_ctrls())
7930 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7932 pr_err("*** Guest State ***\n");
7933 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7934 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7935 vmcs_readl(CR0_GUEST_HOST_MASK
));
7936 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7937 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7938 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7939 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7940 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7942 pr_err("PDPTR0 = 0x%016lx PDPTR1 = 0x%016lx\n",
7943 vmcs_readl(GUEST_PDPTR0
), vmcs_readl(GUEST_PDPTR1
));
7944 pr_err("PDPTR2 = 0x%016lx PDPTR3 = 0x%016lx\n",
7945 vmcs_readl(GUEST_PDPTR2
), vmcs_readl(GUEST_PDPTR3
));
7947 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
7948 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
7949 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
7950 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
7951 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7952 vmcs_readl(GUEST_SYSENTER_ESP
),
7953 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
7954 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
7955 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
7956 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
7957 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
7958 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
7959 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
7960 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
7961 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
7962 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
7963 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
7964 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
7965 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
7966 pr_err("EFER = 0x%016llx PAT = 0x%016lx\n",
7967 efer
, vmcs_readl(GUEST_IA32_PAT
));
7968 pr_err("DebugCtl = 0x%016lx DebugExceptions = 0x%016lx\n",
7969 vmcs_readl(GUEST_IA32_DEBUGCTL
),
7970 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
7971 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
7972 pr_err("PerfGlobCtl = 0x%016lx\n",
7973 vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL
));
7974 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
7975 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS
));
7976 pr_err("Interruptibility = %08x ActivityState = %08x\n",
7977 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
7978 vmcs_read32(GUEST_ACTIVITY_STATE
));
7979 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
7980 pr_err("InterruptStatus = %04x\n",
7981 vmcs_read16(GUEST_INTR_STATUS
));
7983 pr_err("*** Host State ***\n");
7984 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
7985 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
7986 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
7987 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
7988 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
7989 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
7990 vmcs_read16(HOST_TR_SELECTOR
));
7991 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
7992 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
7993 vmcs_readl(HOST_TR_BASE
));
7994 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
7995 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
7996 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
7997 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
7998 vmcs_readl(HOST_CR4
));
7999 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8000 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8001 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8002 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8003 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8004 pr_err("EFER = 0x%016lx PAT = 0x%016lx\n",
8005 vmcs_readl(HOST_IA32_EFER
), vmcs_readl(HOST_IA32_PAT
));
8006 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8007 pr_err("PerfGlobCtl = 0x%016lx\n",
8008 vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL
));
8010 pr_err("*** Control State ***\n");
8011 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8012 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8013 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8014 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8015 vmcs_read32(EXCEPTION_BITMAP
),
8016 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8017 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8018 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8019 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8020 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8021 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8022 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8023 vmcs_read32(VM_EXIT_INTR_INFO
),
8024 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8025 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8026 pr_err(" reason=%08x qualification=%016lx\n",
8027 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8028 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8029 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8030 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8031 pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET
));
8032 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8033 pr_err("TSC Multiplier = 0x%016lx\n",
8034 vmcs_readl(TSC_MULTIPLIER
));
8035 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8036 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8037 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8038 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8039 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8040 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER
));
8041 n
= vmcs_read32(CR3_TARGET_COUNT
);
8042 for (i
= 0; i
+ 1 < n
; i
+= 4)
8043 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8044 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8045 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8047 pr_err("CR3 target%u=%016lx\n",
8048 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8049 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8050 pr_err("PLE Gap=%08x Window=%08x\n",
8051 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8052 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8053 pr_err("Virtual processor ID = 0x%04x\n",
8054 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8058 * The guest has exited. See if we can fix it or if we need userspace
8061 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8063 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8064 u32 exit_reason
= vmx
->exit_reason
;
8065 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8067 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8070 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8071 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8072 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8073 * mode as if vcpus is in root mode, the PML buffer must has been
8077 vmx_flush_pml_buffer(vcpu
);
8079 /* If guest state is invalid, start emulating */
8080 if (vmx
->emulation_required
)
8081 return handle_invalid_guest_state(vcpu
);
8083 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8084 nested_vmx_vmexit(vcpu
, exit_reason
,
8085 vmcs_read32(VM_EXIT_INTR_INFO
),
8086 vmcs_readl(EXIT_QUALIFICATION
));
8090 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8092 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8093 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8098 if (unlikely(vmx
->fail
)) {
8099 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8100 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8101 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8107 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8108 * delivery event since it indicates guest is accessing MMIO.
8109 * The vm-exit can be triggered again after return to guest that
8110 * will cause infinite loop.
8112 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8113 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8114 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8115 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8116 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8117 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8118 vcpu
->run
->internal
.ndata
= 2;
8119 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8120 vcpu
->run
->internal
.data
[1] = exit_reason
;
8124 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8125 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8126 get_vmcs12(vcpu
))))) {
8127 if (vmx_interrupt_allowed(vcpu
)) {
8128 vmx
->soft_vnmi_blocked
= 0;
8129 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8130 vcpu
->arch
.nmi_pending
) {
8132 * This CPU don't support us in finding the end of an
8133 * NMI-blocked window if the guest runs with IRQs
8134 * disabled. So we pull the trigger after 1 s of
8135 * futile waiting, but inform the user about this.
8137 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8138 "state on VCPU %d after 1 s timeout\n",
8139 __func__
, vcpu
->vcpu_id
);
8140 vmx
->soft_vnmi_blocked
= 0;
8144 if (exit_reason
< kvm_vmx_max_exit_handlers
8145 && kvm_vmx_exit_handlers
[exit_reason
])
8146 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8148 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8149 kvm_queue_exception(vcpu
, UD_VECTOR
);
8154 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8156 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8158 if (is_guest_mode(vcpu
) &&
8159 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8162 if (irr
== -1 || tpr
< irr
) {
8163 vmcs_write32(TPR_THRESHOLD
, 0);
8167 vmcs_write32(TPR_THRESHOLD
, irr
);
8170 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8172 u32 sec_exec_control
;
8175 * There is not point to enable virtualize x2apic without enable
8178 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8179 !vmx_cpu_uses_apicv(vcpu
))
8182 if (!cpu_need_tpr_shadow(vcpu
))
8185 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8188 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8189 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8191 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8192 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8194 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8196 vmx_set_msr_bitmap(vcpu
);
8199 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8201 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8204 * Currently we do not handle the nested case where L2 has an
8205 * APIC access page of its own; that page is still pinned.
8206 * Hence, we skip the case where the VCPU is in guest mode _and_
8207 * L1 prepared an APIC access page for L2.
8209 * For the case where L1 and L2 share the same APIC access page
8210 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8211 * in the vmcs12), this function will only update either the vmcs01
8212 * or the vmcs02. If the former, the vmcs02 will be updated by
8213 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8214 * the next L2->L1 exit.
8216 if (!is_guest_mode(vcpu
) ||
8217 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8218 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8219 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8222 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
8230 status
= vmcs_read16(GUEST_INTR_STATUS
);
8235 vmcs_write16(GUEST_INTR_STATUS
, status
);
8239 static void vmx_set_rvi(int vector
)
8247 status
= vmcs_read16(GUEST_INTR_STATUS
);
8248 old
= (u8
)status
& 0xff;
8249 if ((u8
)vector
!= old
) {
8251 status
|= (u8
)vector
;
8252 vmcs_write16(GUEST_INTR_STATUS
, status
);
8256 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8258 if (!is_guest_mode(vcpu
)) {
8259 vmx_set_rvi(max_irr
);
8267 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8270 if (nested_exit_on_intr(vcpu
))
8274 * Else, fall back to pre-APICv interrupt injection since L2
8275 * is run without virtual interrupt delivery.
8277 if (!kvm_event_needs_reinjection(vcpu
) &&
8278 vmx_interrupt_allowed(vcpu
)) {
8279 kvm_queue_interrupt(vcpu
, max_irr
, false);
8280 vmx_inject_irq(vcpu
);
8284 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
)
8286 u64
*eoi_exit_bitmap
= vcpu
->arch
.eoi_exit_bitmap
;
8287 if (!vmx_cpu_uses_apicv(vcpu
))
8290 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8291 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8292 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8293 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8296 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8300 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8301 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8304 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8305 exit_intr_info
= vmx
->exit_intr_info
;
8307 /* Handle machine checks before interrupts are enabled */
8308 if (is_machine_check(exit_intr_info
))
8309 kvm_machine_check();
8311 /* We need to handle NMIs before interrupts are enabled */
8312 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8313 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8314 kvm_before_handle_nmi(&vmx
->vcpu
);
8316 kvm_after_handle_nmi(&vmx
->vcpu
);
8320 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8322 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8325 * If external interrupt exists, IF bit is set in rflags/eflags on the
8326 * interrupt stack frame, and interrupt will be enabled on a return
8327 * from interrupt handler.
8329 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8330 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8331 unsigned int vector
;
8332 unsigned long entry
;
8334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8335 #ifdef CONFIG_X86_64
8339 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8340 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8341 entry
= gate_offset(*desc
);
8343 #ifdef CONFIG_X86_64
8344 "mov %%" _ASM_SP
", %[sp]\n\t"
8345 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8350 "orl $0x200, (%%" _ASM_SP
")\n\t"
8351 __ASM_SIZE(push
) " $%c[cs]\n\t"
8352 "call *%[entry]\n\t"
8354 #ifdef CONFIG_X86_64
8359 [ss
]"i"(__KERNEL_DS
),
8360 [cs
]"i"(__KERNEL_CS
)
8366 static bool vmx_has_high_real_mode_segbase(void)
8368 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8371 static bool vmx_mpx_supported(void)
8373 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8374 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8377 static bool vmx_xsaves_supported(void)
8379 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8380 SECONDARY_EXEC_XSAVES
;
8383 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8388 bool idtv_info_valid
;
8390 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8392 if (cpu_has_virtual_nmis()) {
8393 if (vmx
->nmi_known_unmasked
)
8396 * Can't use vmx->exit_intr_info since we're not sure what
8397 * the exit reason is.
8399 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8400 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8401 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8403 * SDM 3: 27.7.1.2 (September 2008)
8404 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8405 * a guest IRET fault.
8406 * SDM 3: 23.2.2 (September 2008)
8407 * Bit 12 is undefined in any of the following cases:
8408 * If the VM exit sets the valid bit in the IDT-vectoring
8409 * information field.
8410 * If the VM exit is due to a double fault.
8412 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8413 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8414 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8415 GUEST_INTR_STATE_NMI
);
8417 vmx
->nmi_known_unmasked
=
8418 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8419 & GUEST_INTR_STATE_NMI
);
8420 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8421 vmx
->vnmi_blocked_time
+=
8422 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8425 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8426 u32 idt_vectoring_info
,
8427 int instr_len_field
,
8428 int error_code_field
)
8432 bool idtv_info_valid
;
8434 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8436 vcpu
->arch
.nmi_injected
= false;
8437 kvm_clear_exception_queue(vcpu
);
8438 kvm_clear_interrupt_queue(vcpu
);
8440 if (!idtv_info_valid
)
8443 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8445 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8446 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8449 case INTR_TYPE_NMI_INTR
:
8450 vcpu
->arch
.nmi_injected
= true;
8452 * SDM 3: 27.7.1.2 (September 2008)
8453 * Clear bit "block by NMI" before VM entry if a NMI
8456 vmx_set_nmi_mask(vcpu
, false);
8458 case INTR_TYPE_SOFT_EXCEPTION
:
8459 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8461 case INTR_TYPE_HARD_EXCEPTION
:
8462 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8463 u32 err
= vmcs_read32(error_code_field
);
8464 kvm_requeue_exception_e(vcpu
, vector
, err
);
8466 kvm_requeue_exception(vcpu
, vector
);
8468 case INTR_TYPE_SOFT_INTR
:
8469 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8471 case INTR_TYPE_EXT_INTR
:
8472 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8479 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8481 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8482 VM_EXIT_INSTRUCTION_LEN
,
8483 IDT_VECTORING_ERROR_CODE
);
8486 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8488 __vmx_complete_interrupts(vcpu
,
8489 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8490 VM_ENTRY_INSTRUCTION_LEN
,
8491 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8493 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8496 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8499 struct perf_guest_switch_msr
*msrs
;
8501 msrs
= perf_guest_get_msrs(&nr_msrs
);
8506 for (i
= 0; i
< nr_msrs
; i
++)
8507 if (msrs
[i
].host
== msrs
[i
].guest
)
8508 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8510 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8514 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8517 unsigned long debugctlmsr
, cr4
;
8519 /* Record the guest's net vcpu time for enforced NMI injections. */
8520 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8521 vmx
->entry_time
= ktime_get();
8523 /* Don't enter VMX if guest state is invalid, let the exit handler
8524 start emulation until we arrive back to a valid state */
8525 if (vmx
->emulation_required
)
8528 if (vmx
->ple_window_dirty
) {
8529 vmx
->ple_window_dirty
= false;
8530 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8533 if (vmx
->nested
.sync_shadow_vmcs
) {
8534 copy_vmcs12_to_shadow(vmx
);
8535 vmx
->nested
.sync_shadow_vmcs
= false;
8538 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8539 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8540 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8541 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8543 cr4
= cr4_read_shadow();
8544 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8545 vmcs_writel(HOST_CR4
, cr4
);
8546 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8549 /* When single-stepping over STI and MOV SS, we must clear the
8550 * corresponding interruptibility bits in the guest state. Otherwise
8551 * vmentry fails as it then expects bit 14 (BS) in pending debug
8552 * exceptions being set, but that's not correct for the guest debugging
8554 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8555 vmx_set_interrupt_shadow(vcpu
, 0);
8557 atomic_switch_perf_msrs(vmx
);
8558 debugctlmsr
= get_debugctlmsr();
8560 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8562 /* Store host registers */
8563 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8564 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8565 "push %%" _ASM_CX
" \n\t"
8566 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8568 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8569 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8571 /* Reload cr2 if changed */
8572 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8573 "mov %%cr2, %%" _ASM_DX
" \n\t"
8574 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8576 "mov %%" _ASM_AX
", %%cr2 \n\t"
8578 /* Check if vmlaunch of vmresume is needed */
8579 "cmpl $0, %c[launched](%0) \n\t"
8580 /* Load guest registers. Don't clobber flags. */
8581 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8582 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8583 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8584 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8585 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8586 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8587 #ifdef CONFIG_X86_64
8588 "mov %c[r8](%0), %%r8 \n\t"
8589 "mov %c[r9](%0), %%r9 \n\t"
8590 "mov %c[r10](%0), %%r10 \n\t"
8591 "mov %c[r11](%0), %%r11 \n\t"
8592 "mov %c[r12](%0), %%r12 \n\t"
8593 "mov %c[r13](%0), %%r13 \n\t"
8594 "mov %c[r14](%0), %%r14 \n\t"
8595 "mov %c[r15](%0), %%r15 \n\t"
8597 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8599 /* Enter guest mode */
8601 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8603 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8605 /* Save guest registers, load host registers, keep flags */
8606 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8608 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8609 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8610 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8611 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8612 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8613 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8614 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8615 #ifdef CONFIG_X86_64
8616 "mov %%r8, %c[r8](%0) \n\t"
8617 "mov %%r9, %c[r9](%0) \n\t"
8618 "mov %%r10, %c[r10](%0) \n\t"
8619 "mov %%r11, %c[r11](%0) \n\t"
8620 "mov %%r12, %c[r12](%0) \n\t"
8621 "mov %%r13, %c[r13](%0) \n\t"
8622 "mov %%r14, %c[r14](%0) \n\t"
8623 "mov %%r15, %c[r15](%0) \n\t"
8625 "mov %%cr2, %%" _ASM_AX
" \n\t"
8626 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8628 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8629 "setbe %c[fail](%0) \n\t"
8630 ".pushsection .rodata \n\t"
8631 ".global vmx_return \n\t"
8632 "vmx_return: " _ASM_PTR
" 2b \n\t"
8634 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8635 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8636 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8637 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8638 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8639 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8640 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8641 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8642 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8643 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8644 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8645 #ifdef CONFIG_X86_64
8646 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8647 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8648 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8649 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8650 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8651 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8652 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8653 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8655 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8656 [wordsize
]"i"(sizeof(ulong
))
8658 #ifdef CONFIG_X86_64
8659 , "rax", "rbx", "rdi", "rsi"
8660 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8662 , "eax", "ebx", "edi", "esi"
8666 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8668 update_debugctlmsr(debugctlmsr
);
8670 #ifndef CONFIG_X86_64
8672 * The sysexit path does not restore ds/es, so we must set them to
8673 * a reasonable value ourselves.
8675 * We can't defer this to vmx_load_host_state() since that function
8676 * may be executed in interrupt context, which saves and restore segments
8677 * around it, nullifying its effect.
8679 loadsegment(ds
, __USER_DS
);
8680 loadsegment(es
, __USER_DS
);
8683 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8684 | (1 << VCPU_EXREG_RFLAGS
)
8685 | (1 << VCPU_EXREG_PDPTR
)
8686 | (1 << VCPU_EXREG_SEGMENTS
)
8687 | (1 << VCPU_EXREG_CR3
));
8688 vcpu
->arch
.regs_dirty
= 0;
8690 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8692 vmx
->loaded_vmcs
->launched
= 1;
8694 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8697 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8698 * we did not inject a still-pending event to L1 now because of
8699 * nested_run_pending, we need to re-enable this bit.
8701 if (vmx
->nested
.nested_run_pending
)
8702 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8704 vmx
->nested
.nested_run_pending
= 0;
8706 vmx_complete_atomic_exit(vmx
);
8707 vmx_recover_nmi_blocking(vmx
);
8708 vmx_complete_interrupts(vmx
);
8711 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8713 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8716 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8720 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8722 vmx_vcpu_load(vcpu
, cpu
);
8727 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8729 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8732 vmx_destroy_pml_buffer(vmx
);
8733 free_vpid(vmx
->vpid
);
8734 leave_guest_mode(vcpu
);
8735 vmx_load_vmcs01(vcpu
);
8737 free_loaded_vmcs(vmx
->loaded_vmcs
);
8738 kfree(vmx
->guest_msrs
);
8739 kvm_vcpu_uninit(vcpu
);
8740 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8743 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8746 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8750 return ERR_PTR(-ENOMEM
);
8752 vmx
->vpid
= allocate_vpid();
8754 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8758 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8759 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8763 if (!vmx
->guest_msrs
) {
8767 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8768 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8769 if (!vmx
->loaded_vmcs
->vmcs
)
8772 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8773 loaded_vmcs_init(vmx
->loaded_vmcs
);
8778 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8779 vmx
->vcpu
.cpu
= cpu
;
8780 err
= vmx_vcpu_setup(vmx
);
8781 vmx_vcpu_put(&vmx
->vcpu
);
8785 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8786 err
= alloc_apic_access_page(kvm
);
8792 if (!kvm
->arch
.ept_identity_map_addr
)
8793 kvm
->arch
.ept_identity_map_addr
=
8794 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8795 err
= init_rmode_identity_map(kvm
);
8801 nested_vmx_setup_ctls_msrs(vmx
);
8802 vmx
->nested
.vpid02
= allocate_vpid();
8805 vmx
->nested
.posted_intr_nv
= -1;
8806 vmx
->nested
.current_vmptr
= -1ull;
8807 vmx
->nested
.current_vmcs12
= NULL
;
8810 * If PML is turned on, failure on enabling PML just results in failure
8811 * of creating the vcpu, therefore we can simplify PML logic (by
8812 * avoiding dealing with cases, such as enabling PML partially on vcpus
8813 * for the guest, etc.
8816 err
= vmx_create_pml_buffer(vmx
);
8824 free_vpid(vmx
->nested
.vpid02
);
8825 free_loaded_vmcs(vmx
->loaded_vmcs
);
8827 kfree(vmx
->guest_msrs
);
8829 kvm_vcpu_uninit(&vmx
->vcpu
);
8831 free_vpid(vmx
->vpid
);
8832 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8833 return ERR_PTR(err
);
8836 static void __init
vmx_check_processor_compat(void *rtn
)
8838 struct vmcs_config vmcs_conf
;
8841 if (setup_vmcs_config(&vmcs_conf
) < 0)
8843 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8844 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8845 smp_processor_id());
8850 static int get_ept_level(void)
8852 return VMX_EPT_DEFAULT_GAW
+ 1;
8855 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8860 /* For VT-d and EPT combination
8861 * 1. MMIO: always map as UC
8863 * a. VT-d without snooping control feature: can't guarantee the
8864 * result, try to trust guest.
8865 * b. VT-d with snooping control feature: snooping control feature of
8866 * VT-d engine can guarantee the cache correctness. Just set it
8867 * to WB to keep consistent with host. So the same as item 3.
8868 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8869 * consistent with host MTRR
8872 cache
= MTRR_TYPE_UNCACHABLE
;
8876 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8877 ipat
= VMX_EPT_IPAT_BIT
;
8878 cache
= MTRR_TYPE_WRBACK
;
8882 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8883 ipat
= VMX_EPT_IPAT_BIT
;
8884 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8885 cache
= MTRR_TYPE_WRBACK
;
8887 cache
= MTRR_TYPE_UNCACHABLE
;
8891 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8894 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8897 static int vmx_get_lpage_level(void)
8899 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8900 return PT_DIRECTORY_LEVEL
;
8902 /* For shadow and EPT supported 1GB page */
8903 return PT_PDPE_LEVEL
;
8906 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
8909 * These bits in the secondary execution controls field
8910 * are dynamic, the others are mostly based on the hypervisor
8911 * architecture and the guest's CPUID. Do not touch the
8915 SECONDARY_EXEC_SHADOW_VMCS
|
8916 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
8917 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8919 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8921 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8922 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
8925 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8927 struct kvm_cpuid_entry2
*best
;
8928 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8929 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
8931 if (vmx_rdtscp_supported()) {
8932 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
8933 if (!rdtscp_enabled
)
8934 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
8938 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8939 SECONDARY_EXEC_RDTSCP
;
8941 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8942 ~SECONDARY_EXEC_RDTSCP
;
8946 /* Exposing INVPCID only when PCID is exposed */
8947 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8948 if (vmx_invpcid_supported() &&
8949 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
8950 !guest_cpuid_has_pcid(vcpu
))) {
8951 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8954 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8957 if (cpu_has_secondary_exec_ctrls())
8958 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
8960 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
8961 if (guest_cpuid_has_pcommit(vcpu
))
8962 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8963 SECONDARY_EXEC_PCOMMIT
;
8965 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8966 ~SECONDARY_EXEC_PCOMMIT
;
8970 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8972 if (func
== 1 && nested
)
8973 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8976 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8977 struct x86_exception
*fault
)
8979 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8982 if (fault
->error_code
& PFERR_RSVD_MASK
)
8983 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8985 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8986 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8987 vmcs12
->guest_physical_address
= fault
->address
;
8990 /* Callbacks for nested_ept_init_mmu_context: */
8992 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8994 /* return the page table to be shadowed - in our case, EPT12 */
8995 return get_vmcs12(vcpu
)->ept_pointer
;
8998 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9000 WARN_ON(mmu_is_nested(vcpu
));
9001 kvm_init_shadow_ept_mmu(vcpu
,
9002 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9003 VMX_EPT_EXECUTE_ONLY_BIT
);
9004 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9005 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9006 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9008 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9011 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9013 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9016 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9019 bool inequality
, bit
;
9021 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9023 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9024 vmcs12
->page_fault_error_code_match
;
9025 return inequality
^ bit
;
9028 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9029 struct x86_exception
*fault
)
9031 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9033 WARN_ON(!is_guest_mode(vcpu
));
9035 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9036 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9037 vmcs_read32(VM_EXIT_INTR_INFO
),
9038 vmcs_readl(EXIT_QUALIFICATION
));
9040 kvm_inject_page_fault(vcpu
, fault
);
9043 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9044 struct vmcs12
*vmcs12
)
9046 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9047 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9049 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9050 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9051 vmcs12
->apic_access_addr
>> maxphyaddr
)
9055 * Translate L1 physical address to host physical
9056 * address for vmcs02. Keep the page pinned, so this
9057 * physical address remains valid. We keep a reference
9058 * to it so we can release it later.
9060 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9061 nested_release_page(vmx
->nested
.apic_access_page
);
9062 vmx
->nested
.apic_access_page
=
9063 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9066 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9067 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9068 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9071 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9072 nested_release_page(vmx
->nested
.virtual_apic_page
);
9073 vmx
->nested
.virtual_apic_page
=
9074 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9077 * Failing the vm entry is _not_ what the processor does
9078 * but it's basically the only possibility we have.
9079 * We could still enter the guest if CR8 load exits are
9080 * enabled, CR8 store exits are enabled, and virtualize APIC
9081 * access is disabled; in this case the processor would never
9082 * use the TPR shadow and we could simply clear the bit from
9083 * the execution control. But such a configuration is useless,
9084 * so let's keep the code simple.
9086 if (!vmx
->nested
.virtual_apic_page
)
9090 if (nested_cpu_has_posted_intr(vmcs12
)) {
9091 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9092 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9095 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9096 kunmap(vmx
->nested
.pi_desc_page
);
9097 nested_release_page(vmx
->nested
.pi_desc_page
);
9099 vmx
->nested
.pi_desc_page
=
9100 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9101 if (!vmx
->nested
.pi_desc_page
)
9104 vmx
->nested
.pi_desc
=
9105 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9106 if (!vmx
->nested
.pi_desc
) {
9107 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9110 vmx
->nested
.pi_desc
=
9111 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9112 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9119 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9121 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9122 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9124 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9127 /* Make sure short timeouts reliably trigger an immediate vmexit.
9128 * hrtimer_start does not guarantee this. */
9129 if (preemption_timeout
<= 1) {
9130 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9134 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9135 preemption_timeout
*= 1000000;
9136 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9137 hrtimer_start(&vmx
->nested
.preemption_timer
,
9138 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9141 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9142 struct vmcs12
*vmcs12
)
9147 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9150 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9154 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9156 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9157 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9164 * Merge L0's and L1's MSR bitmap, return false to indicate that
9165 * we do not use the hardware.
9167 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9168 struct vmcs12
*vmcs12
)
9172 unsigned long *msr_bitmap
;
9174 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9177 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9182 msr_bitmap
= (unsigned long *)kmap(page
);
9184 nested_release_page_clean(page
);
9189 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9190 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9191 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9192 nested_vmx_disable_intercept_for_msr(
9194 vmx_msr_bitmap_nested
,
9196 /* TPR is allowed */
9197 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9198 vmx_msr_bitmap_nested
,
9199 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9200 MSR_TYPE_R
| MSR_TYPE_W
);
9201 if (nested_cpu_has_vid(vmcs12
)) {
9202 /* EOI and self-IPI are allowed */
9203 nested_vmx_disable_intercept_for_msr(
9205 vmx_msr_bitmap_nested
,
9206 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9208 nested_vmx_disable_intercept_for_msr(
9210 vmx_msr_bitmap_nested
,
9211 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9216 * Enable reading intercept of all the x2apic
9217 * MSRs. We should not rely on vmcs12 to do any
9218 * optimizations here, it may have been modified
9221 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9222 __vmx_enable_intercept_for_msr(
9223 vmx_msr_bitmap_nested
,
9227 __vmx_enable_intercept_for_msr(
9228 vmx_msr_bitmap_nested
,
9229 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9231 __vmx_enable_intercept_for_msr(
9232 vmx_msr_bitmap_nested
,
9233 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9235 __vmx_enable_intercept_for_msr(
9236 vmx_msr_bitmap_nested
,
9237 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9241 nested_release_page_clean(page
);
9246 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9247 struct vmcs12
*vmcs12
)
9249 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9250 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9251 !nested_cpu_has_vid(vmcs12
) &&
9252 !nested_cpu_has_posted_intr(vmcs12
))
9256 * If virtualize x2apic mode is enabled,
9257 * virtualize apic access must be disabled.
9259 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9260 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9264 * If virtual interrupt delivery is enabled,
9265 * we must exit on external interrupts.
9267 if (nested_cpu_has_vid(vmcs12
) &&
9268 !nested_exit_on_intr(vcpu
))
9272 * bits 15:8 should be zero in posted_intr_nv,
9273 * the descriptor address has been already checked
9274 * in nested_get_vmcs12_pages.
9276 if (nested_cpu_has_posted_intr(vmcs12
) &&
9277 (!nested_cpu_has_vid(vmcs12
) ||
9278 !nested_exit_intr_ack_set(vcpu
) ||
9279 vmcs12
->posted_intr_nv
& 0xff00))
9282 /* tpr shadow is needed by all apicv features. */
9283 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9289 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9290 unsigned long count_field
,
9291 unsigned long addr_field
)
9296 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9297 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9303 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9304 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9305 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9306 pr_warn_ratelimited(
9307 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9308 addr_field
, maxphyaddr
, count
, addr
);
9314 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9315 struct vmcs12
*vmcs12
)
9317 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9318 vmcs12
->vm_exit_msr_store_count
== 0 &&
9319 vmcs12
->vm_entry_msr_load_count
== 0)
9320 return 0; /* Fast path */
9321 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9322 VM_EXIT_MSR_LOAD_ADDR
) ||
9323 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9324 VM_EXIT_MSR_STORE_ADDR
) ||
9325 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9326 VM_ENTRY_MSR_LOAD_ADDR
))
9331 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9332 struct vmx_msr_entry
*e
)
9334 /* x2APIC MSR accesses are not allowed */
9335 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9337 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9338 e
->index
== MSR_IA32_UCODE_REV
)
9340 if (e
->reserved
!= 0)
9345 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9346 struct vmx_msr_entry
*e
)
9348 if (e
->index
== MSR_FS_BASE
||
9349 e
->index
== MSR_GS_BASE
||
9350 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9351 nested_vmx_msr_check_common(vcpu
, e
))
9356 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9357 struct vmx_msr_entry
*e
)
9359 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9360 nested_vmx_msr_check_common(vcpu
, e
))
9366 * Load guest's/host's msr at nested entry/exit.
9367 * return 0 for success, entry index for failure.
9369 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9372 struct vmx_msr_entry e
;
9373 struct msr_data msr
;
9375 msr
.host_initiated
= false;
9376 for (i
= 0; i
< count
; i
++) {
9377 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9379 pr_warn_ratelimited(
9380 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9381 __func__
, i
, gpa
+ i
* sizeof(e
));
9384 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9385 pr_warn_ratelimited(
9386 "%s check failed (%u, 0x%x, 0x%x)\n",
9387 __func__
, i
, e
.index
, e
.reserved
);
9390 msr
.index
= e
.index
;
9392 if (kvm_set_msr(vcpu
, &msr
)) {
9393 pr_warn_ratelimited(
9394 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9395 __func__
, i
, e
.index
, e
.value
);
9404 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9407 struct vmx_msr_entry e
;
9409 for (i
= 0; i
< count
; i
++) {
9410 struct msr_data msr_info
;
9411 if (kvm_vcpu_read_guest(vcpu
,
9412 gpa
+ i
* sizeof(e
),
9413 &e
, 2 * sizeof(u32
))) {
9414 pr_warn_ratelimited(
9415 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9416 __func__
, i
, gpa
+ i
* sizeof(e
));
9419 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9420 pr_warn_ratelimited(
9421 "%s check failed (%u, 0x%x, 0x%x)\n",
9422 __func__
, i
, e
.index
, e
.reserved
);
9425 msr_info
.host_initiated
= false;
9426 msr_info
.index
= e
.index
;
9427 if (kvm_get_msr(vcpu
, &msr_info
)) {
9428 pr_warn_ratelimited(
9429 "%s cannot read MSR (%u, 0x%x)\n",
9430 __func__
, i
, e
.index
);
9433 if (kvm_vcpu_write_guest(vcpu
,
9434 gpa
+ i
* sizeof(e
) +
9435 offsetof(struct vmx_msr_entry
, value
),
9436 &msr_info
.data
, sizeof(msr_info
.data
))) {
9437 pr_warn_ratelimited(
9438 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9439 __func__
, i
, e
.index
, msr_info
.data
);
9447 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9448 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9449 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9450 * guest in a way that will both be appropriate to L1's requests, and our
9451 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9452 * function also has additional necessary side-effects, like setting various
9453 * vcpu->arch fields.
9455 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9457 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9460 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9461 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9462 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9463 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9464 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9465 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9466 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9467 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9468 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9469 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9470 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9471 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9472 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9473 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9474 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9475 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9476 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9477 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9478 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9479 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9480 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9481 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9482 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9483 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9484 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9485 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9486 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9487 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9488 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9489 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9490 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9491 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9492 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9493 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9494 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9495 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9497 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9498 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9499 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9501 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9502 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9504 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9505 vmcs12
->vm_entry_intr_info_field
);
9506 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9507 vmcs12
->vm_entry_exception_error_code
);
9508 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9509 vmcs12
->vm_entry_instruction_len
);
9510 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9511 vmcs12
->guest_interruptibility_info
);
9512 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9513 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9514 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9515 vmcs12
->guest_pending_dbg_exceptions
);
9516 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9517 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9519 if (nested_cpu_has_xsaves(vmcs12
))
9520 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9521 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9523 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9524 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9525 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9527 if (nested_cpu_has_posted_intr(vmcs12
)) {
9529 * Note that we use L0's vector here and in
9530 * vmx_deliver_nested_posted_interrupt.
9532 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9533 vmx
->nested
.pi_pending
= false;
9534 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9535 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9536 page_to_phys(vmx
->nested
.pi_desc_page
) +
9537 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9540 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9542 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9544 vmx
->nested
.preemption_timer_expired
= false;
9545 if (nested_cpu_has_preemption_timer(vmcs12
))
9546 vmx_start_preemption_timer(vcpu
);
9549 * Whether page-faults are trapped is determined by a combination of
9550 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9551 * If enable_ept, L0 doesn't care about page faults and we should
9552 * set all of these to L1's desires. However, if !enable_ept, L0 does
9553 * care about (at least some) page faults, and because it is not easy
9554 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9555 * to exit on each and every L2 page fault. This is done by setting
9556 * MASK=MATCH=0 and (see below) EB.PF=1.
9557 * Note that below we don't need special code to set EB.PF beyond the
9558 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9559 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9560 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9562 * A problem with this approach (when !enable_ept) is that L1 may be
9563 * injected with more page faults than it asked for. This could have
9564 * caused problems, but in practice existing hypervisors don't care.
9565 * To fix this, we will need to emulate the PFEC checking (on the L1
9566 * page tables), using walk_addr(), when injecting PFs to L1.
9568 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9569 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9570 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9571 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9573 if (cpu_has_secondary_exec_ctrls()) {
9574 exec_control
= vmx_secondary_exec_control(vmx
);
9576 /* Take the following fields only from vmcs12 */
9577 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9578 SECONDARY_EXEC_RDTSCP
|
9579 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9580 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9581 SECONDARY_EXEC_PCOMMIT
);
9582 if (nested_cpu_has(vmcs12
,
9583 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9584 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9586 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9588 * If translation failed, no matter: This feature asks
9589 * to exit when accessing the given address, and if it
9590 * can never be accessed, this feature won't do
9593 if (!vmx
->nested
.apic_access_page
)
9595 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9597 vmcs_write64(APIC_ACCESS_ADDR
,
9598 page_to_phys(vmx
->nested
.apic_access_page
));
9599 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9600 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9602 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9603 kvm_vcpu_reload_apic_access_page(vcpu
);
9606 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9607 vmcs_write64(EOI_EXIT_BITMAP0
,
9608 vmcs12
->eoi_exit_bitmap0
);
9609 vmcs_write64(EOI_EXIT_BITMAP1
,
9610 vmcs12
->eoi_exit_bitmap1
);
9611 vmcs_write64(EOI_EXIT_BITMAP2
,
9612 vmcs12
->eoi_exit_bitmap2
);
9613 vmcs_write64(EOI_EXIT_BITMAP3
,
9614 vmcs12
->eoi_exit_bitmap3
);
9615 vmcs_write16(GUEST_INTR_STATUS
,
9616 vmcs12
->guest_intr_status
);
9619 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9624 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9625 * Some constant fields are set here by vmx_set_constant_host_state().
9626 * Other fields are different per CPU, and will be set later when
9627 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9629 vmx_set_constant_host_state(vmx
);
9632 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9633 * entry, but only if the current (host) sp changed from the value
9634 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9635 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9636 * here we just force the write to happen on entry.
9640 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9641 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9642 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9643 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9644 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9646 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9647 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9648 page_to_phys(vmx
->nested
.virtual_apic_page
));
9649 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9652 if (cpu_has_vmx_msr_bitmap() &&
9653 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9654 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9655 /* MSR_BITMAP will be set by following vmx_set_efer. */
9657 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9660 * Merging of IO bitmap not currently supported.
9661 * Rather, exit every time.
9663 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9664 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9666 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9668 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9669 * bitwise-or of what L1 wants to trap for L2, and what we want to
9670 * trap. Note that CR0.TS also needs updating - we do this later.
9672 update_exception_bitmap(vcpu
);
9673 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9674 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9676 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9677 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9678 * bits are further modified by vmx_set_efer() below.
9680 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9682 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9683 * emulated by vmx_set_efer(), below.
9685 vm_entry_controls_init(vmx
,
9686 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9687 ~VM_ENTRY_IA32E_MODE
) |
9688 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9690 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9691 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9692 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9693 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9694 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9697 set_cr4_guest_host_mask(vmx
);
9699 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9700 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9702 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9703 vmcs_write64(TSC_OFFSET
,
9704 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9706 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9710 * There is no direct mapping between vpid02 and vpid12, the
9711 * vpid02 is per-vCPU for L0 and reused while the value of
9712 * vpid12 is changed w/ one invvpid during nested vmentry.
9713 * The vpid12 is allocated by L1 for L2, so it will not
9714 * influence global bitmap(for vpid01 and vpid02 allocation)
9715 * even if spawn a lot of nested vCPUs.
9717 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9718 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9719 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9720 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9721 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9724 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9725 vmx_flush_tlb(vcpu
);
9730 if (nested_cpu_has_ept(vmcs12
)) {
9731 kvm_mmu_unload(vcpu
);
9732 nested_ept_init_mmu_context(vcpu
);
9735 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9736 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9737 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9738 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9740 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9741 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9742 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9745 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9746 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9747 * The CR0_READ_SHADOW is what L2 should have expected to read given
9748 * the specifications by L1; It's not enough to take
9749 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9750 * have more bits than L1 expected.
9752 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9753 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9755 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9756 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9758 /* shadow page tables on either EPT or shadow page tables */
9759 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9760 kvm_mmu_reset_context(vcpu
);
9763 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9766 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9769 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9770 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9771 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9772 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9775 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9776 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9780 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9781 * for running an L2 nested guest.
9783 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9785 struct vmcs12
*vmcs12
;
9786 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9788 struct loaded_vmcs
*vmcs02
;
9792 if (!nested_vmx_check_permission(vcpu
) ||
9793 !nested_vmx_check_vmcs12(vcpu
))
9796 skip_emulated_instruction(vcpu
);
9797 vmcs12
= get_vmcs12(vcpu
);
9799 if (enable_shadow_vmcs
)
9800 copy_shadow_to_vmcs12(vmx
);
9803 * The nested entry process starts with enforcing various prerequisites
9804 * on vmcs12 as required by the Intel SDM, and act appropriately when
9805 * they fail: As the SDM explains, some conditions should cause the
9806 * instruction to fail, while others will cause the instruction to seem
9807 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9808 * To speed up the normal (success) code path, we should avoid checking
9809 * for misconfigurations which will anyway be caught by the processor
9810 * when using the merged vmcs02.
9812 if (vmcs12
->launch_state
== launch
) {
9813 nested_vmx_failValid(vcpu
,
9814 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9815 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9819 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9820 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9821 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9825 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9826 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9830 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9831 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9835 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9836 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9840 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9841 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9845 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9846 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9847 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9848 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9849 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9850 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9851 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9852 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9853 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9854 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9855 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9856 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9857 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9858 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9859 vmx
->nested
.nested_vmx_entry_ctls_high
))
9861 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9865 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9866 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9867 nested_vmx_failValid(vcpu
,
9868 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9872 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9873 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9874 nested_vmx_entry_failure(vcpu
, vmcs12
,
9875 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9878 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9879 nested_vmx_entry_failure(vcpu
, vmcs12
,
9880 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9885 * If the load IA32_EFER VM-entry control is 1, the following checks
9886 * are performed on the field for the IA32_EFER MSR:
9887 * - Bits reserved in the IA32_EFER MSR must be 0.
9888 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9889 * the IA-32e mode guest VM-exit control. It must also be identical
9890 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9893 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9894 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9895 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9896 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9897 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9898 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9899 nested_vmx_entry_failure(vcpu
, vmcs12
,
9900 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9906 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9907 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9908 * the values of the LMA and LME bits in the field must each be that of
9909 * the host address-space size VM-exit control.
9911 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9912 ia32e
= (vmcs12
->vm_exit_controls
&
9913 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9914 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9915 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9916 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9917 nested_vmx_entry_failure(vcpu
, vmcs12
,
9918 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9924 * We're finally done with prerequisite checking, and can start with
9928 vmcs02
= nested_get_current_vmcs02(vmx
);
9932 enter_guest_mode(vcpu
);
9934 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9936 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9937 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9940 vmx
->loaded_vmcs
= vmcs02
;
9942 vmx_vcpu_load(vcpu
, cpu
);
9946 vmx_segment_cache_clear(vmx
);
9948 prepare_vmcs02(vcpu
, vmcs12
);
9950 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9951 vmcs12
->vm_entry_msr_load_addr
,
9952 vmcs12
->vm_entry_msr_load_count
);
9953 if (msr_entry_idx
) {
9954 leave_guest_mode(vcpu
);
9955 vmx_load_vmcs01(vcpu
);
9956 nested_vmx_entry_failure(vcpu
, vmcs12
,
9957 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9961 vmcs12
->launch_state
= 1;
9963 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9964 return kvm_vcpu_halt(vcpu
);
9966 vmx
->nested
.nested_run_pending
= 1;
9969 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9970 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9971 * returned as far as L1 is concerned. It will only return (and set
9972 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9978 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9979 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9980 * This function returns the new value we should put in vmcs12.guest_cr0.
9981 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9982 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9983 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9984 * didn't trap the bit, because if L1 did, so would L0).
9985 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9986 * been modified by L2, and L1 knows it. So just leave the old value of
9987 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9988 * isn't relevant, because if L0 traps this bit it can set it to anything.
9989 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9990 * changed these bits, and therefore they need to be updated, but L0
9991 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9992 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9994 static inline unsigned long
9995 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9998 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9999 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10000 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10001 vcpu
->arch
.cr0_guest_owned_bits
));
10004 static inline unsigned long
10005 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10008 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10009 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10010 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10011 vcpu
->arch
.cr4_guest_owned_bits
));
10014 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10015 struct vmcs12
*vmcs12
)
10020 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10021 nr
= vcpu
->arch
.exception
.nr
;
10022 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10024 if (kvm_exception_is_soft(nr
)) {
10025 vmcs12
->vm_exit_instruction_len
=
10026 vcpu
->arch
.event_exit_inst_len
;
10027 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10029 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10031 if (vcpu
->arch
.exception
.has_error_code
) {
10032 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10033 vmcs12
->idt_vectoring_error_code
=
10034 vcpu
->arch
.exception
.error_code
;
10037 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10038 } else if (vcpu
->arch
.nmi_injected
) {
10039 vmcs12
->idt_vectoring_info_field
=
10040 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10041 } else if (vcpu
->arch
.interrupt
.pending
) {
10042 nr
= vcpu
->arch
.interrupt
.nr
;
10043 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10045 if (vcpu
->arch
.interrupt
.soft
) {
10046 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10047 vmcs12
->vm_entry_instruction_len
=
10048 vcpu
->arch
.event_exit_inst_len
;
10050 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10052 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10056 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10058 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10060 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10061 vmx
->nested
.preemption_timer_expired
) {
10062 if (vmx
->nested
.nested_run_pending
)
10064 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10068 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10069 if (vmx
->nested
.nested_run_pending
||
10070 vcpu
->arch
.interrupt
.pending
)
10072 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10073 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10074 INTR_INFO_VALID_MASK
, 0);
10076 * The NMI-triggered VM exit counts as injection:
10077 * clear this one and block further NMIs.
10079 vcpu
->arch
.nmi_pending
= 0;
10080 vmx_set_nmi_mask(vcpu
, true);
10084 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10085 nested_exit_on_intr(vcpu
)) {
10086 if (vmx
->nested
.nested_run_pending
)
10088 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10092 return vmx_complete_nested_posted_interrupt(vcpu
);
10095 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10097 ktime_t remaining
=
10098 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10101 if (ktime_to_ns(remaining
) <= 0)
10104 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10105 do_div(value
, 1000000);
10106 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10110 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10111 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10112 * and this function updates it to reflect the changes to the guest state while
10113 * L2 was running (and perhaps made some exits which were handled directly by L0
10114 * without going back to L1), and to reflect the exit reason.
10115 * Note that we do not have to copy here all VMCS fields, just those that
10116 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10117 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10118 * which already writes to vmcs12 directly.
10120 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10121 u32 exit_reason
, u32 exit_intr_info
,
10122 unsigned long exit_qualification
)
10124 /* update guest state fields: */
10125 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10126 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10128 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10129 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10130 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10132 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10133 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10134 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10135 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10136 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10137 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10138 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10139 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10140 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10141 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10142 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10143 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10144 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10145 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10146 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10147 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10148 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10149 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10150 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10151 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10152 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10153 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10154 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10155 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10156 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10157 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10158 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10159 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10160 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10161 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10162 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10163 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10164 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10165 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10166 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10167 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10169 vmcs12
->guest_interruptibility_info
=
10170 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10171 vmcs12
->guest_pending_dbg_exceptions
=
10172 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10173 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10174 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10176 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10178 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10179 if (vmcs12
->vm_exit_controls
&
10180 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10181 vmcs12
->vmx_preemption_timer_value
=
10182 vmx_get_preemption_timer_value(vcpu
);
10183 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10187 * In some cases (usually, nested EPT), L2 is allowed to change its
10188 * own CR3 without exiting. If it has changed it, we must keep it.
10189 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10190 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10192 * Additionally, restore L2's PDPTR to vmcs12.
10195 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
10196 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10197 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10198 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10199 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10202 if (nested_cpu_has_vid(vmcs12
))
10203 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10205 vmcs12
->vm_entry_controls
=
10206 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10207 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10209 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10210 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10211 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10214 /* TODO: These cannot have changed unless we have MSR bitmaps and
10215 * the relevant bit asks not to trap the change */
10216 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10217 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10218 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10219 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10220 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10221 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10222 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10223 if (vmx_mpx_supported())
10224 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10225 if (nested_cpu_has_xsaves(vmcs12
))
10226 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10228 /* update exit information fields: */
10230 vmcs12
->vm_exit_reason
= exit_reason
;
10231 vmcs12
->exit_qualification
= exit_qualification
;
10233 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10234 if ((vmcs12
->vm_exit_intr_info
&
10235 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10236 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10237 vmcs12
->vm_exit_intr_error_code
=
10238 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10239 vmcs12
->idt_vectoring_info_field
= 0;
10240 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10241 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10243 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10244 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10245 * instead of reading the real value. */
10246 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10249 * Transfer the event that L0 or L1 may wanted to inject into
10250 * L2 to IDT_VECTORING_INFO_FIELD.
10252 vmcs12_save_pending_event(vcpu
, vmcs12
);
10256 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10257 * preserved above and would only end up incorrectly in L1.
10259 vcpu
->arch
.nmi_injected
= false;
10260 kvm_clear_exception_queue(vcpu
);
10261 kvm_clear_interrupt_queue(vcpu
);
10265 * A part of what we need to when the nested L2 guest exits and we want to
10266 * run its L1 parent, is to reset L1's guest state to the host state specified
10268 * This function is to be called not only on normal nested exit, but also on
10269 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10270 * Failures During or After Loading Guest State").
10271 * This function should be called when the active VMCS is L1's (vmcs01).
10273 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10274 struct vmcs12
*vmcs12
)
10276 struct kvm_segment seg
;
10278 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10279 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10280 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10281 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10283 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10284 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10286 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10287 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10288 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10290 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10291 * actually changed, because it depends on the current state of
10292 * fpu_active (which may have changed).
10293 * Note that vmx_set_cr0 refers to efer set above.
10295 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10297 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10298 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10299 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10301 update_exception_bitmap(vcpu
);
10302 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10303 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10306 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10307 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10309 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10310 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10312 nested_ept_uninit_mmu_context(vcpu
);
10314 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10315 kvm_mmu_reset_context(vcpu
);
10318 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10322 * Trivially support vpid by letting L2s share their parent
10323 * L1's vpid. TODO: move to a more elaborate solution, giving
10324 * each L2 its own vpid and exposing the vpid feature to L1.
10326 vmx_flush_tlb(vcpu
);
10330 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10331 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10332 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10333 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10334 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10336 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10337 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10338 vmcs_write64(GUEST_BNDCFGS
, 0);
10340 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10341 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10342 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10344 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10345 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10346 vmcs12
->host_ia32_perf_global_ctrl
);
10348 /* Set L1 segment info according to Intel SDM
10349 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10350 seg
= (struct kvm_segment
) {
10352 .limit
= 0xFFFFFFFF,
10353 .selector
= vmcs12
->host_cs_selector
,
10359 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10363 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10364 seg
= (struct kvm_segment
) {
10366 .limit
= 0xFFFFFFFF,
10373 seg
.selector
= vmcs12
->host_ds_selector
;
10374 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10375 seg
.selector
= vmcs12
->host_es_selector
;
10376 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10377 seg
.selector
= vmcs12
->host_ss_selector
;
10378 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10379 seg
.selector
= vmcs12
->host_fs_selector
;
10380 seg
.base
= vmcs12
->host_fs_base
;
10381 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10382 seg
.selector
= vmcs12
->host_gs_selector
;
10383 seg
.base
= vmcs12
->host_gs_base
;
10384 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10385 seg
= (struct kvm_segment
) {
10386 .base
= vmcs12
->host_tr_base
,
10388 .selector
= vmcs12
->host_tr_selector
,
10392 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10394 kvm_set_dr(vcpu
, 7, 0x400);
10395 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10397 if (cpu_has_vmx_msr_bitmap())
10398 vmx_set_msr_bitmap(vcpu
);
10400 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10401 vmcs12
->vm_exit_msr_load_count
))
10402 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10406 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10407 * and modify vmcs12 to make it see what it would expect to see there if
10408 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10410 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10411 u32 exit_intr_info
,
10412 unsigned long exit_qualification
)
10414 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10415 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10417 /* trying to cancel vmlaunch/vmresume is a bug */
10418 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10420 leave_guest_mode(vcpu
);
10421 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10422 exit_qualification
);
10424 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10425 vmcs12
->vm_exit_msr_store_count
))
10426 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10428 vmx_load_vmcs01(vcpu
);
10430 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10431 && nested_exit_intr_ack_set(vcpu
)) {
10432 int irq
= kvm_cpu_get_interrupt(vcpu
);
10434 vmcs12
->vm_exit_intr_info
= irq
|
10435 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10438 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10439 vmcs12
->exit_qualification
,
10440 vmcs12
->idt_vectoring_info_field
,
10441 vmcs12
->vm_exit_intr_info
,
10442 vmcs12
->vm_exit_intr_error_code
,
10445 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10446 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10447 vmx_segment_cache_clear(vmx
);
10449 /* if no vmcs02 cache requested, remove the one we used */
10450 if (VMCS02_POOL_SIZE
== 0)
10451 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10453 load_vmcs12_host_state(vcpu
, vmcs12
);
10455 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10456 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10458 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10461 /* Unpin physical memory we referred to in vmcs02 */
10462 if (vmx
->nested
.apic_access_page
) {
10463 nested_release_page(vmx
->nested
.apic_access_page
);
10464 vmx
->nested
.apic_access_page
= NULL
;
10466 if (vmx
->nested
.virtual_apic_page
) {
10467 nested_release_page(vmx
->nested
.virtual_apic_page
);
10468 vmx
->nested
.virtual_apic_page
= NULL
;
10470 if (vmx
->nested
.pi_desc_page
) {
10471 kunmap(vmx
->nested
.pi_desc_page
);
10472 nested_release_page(vmx
->nested
.pi_desc_page
);
10473 vmx
->nested
.pi_desc_page
= NULL
;
10474 vmx
->nested
.pi_desc
= NULL
;
10478 * We are now running in L2, mmu_notifier will force to reload the
10479 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10481 kvm_vcpu_reload_apic_access_page(vcpu
);
10484 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10485 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10486 * success or failure flag accordingly.
10488 if (unlikely(vmx
->fail
)) {
10490 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10492 nested_vmx_succeed(vcpu
);
10493 if (enable_shadow_vmcs
)
10494 vmx
->nested
.sync_shadow_vmcs
= true;
10496 /* in case we halted in L2 */
10497 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10501 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10503 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10505 if (is_guest_mode(vcpu
))
10506 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10507 free_nested(to_vmx(vcpu
));
10511 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10512 * 23.7 "VM-entry failures during or after loading guest state" (this also
10513 * lists the acceptable exit-reason and exit-qualification parameters).
10514 * It should only be called before L2 actually succeeded to run, and when
10515 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10517 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10518 struct vmcs12
*vmcs12
,
10519 u32 reason
, unsigned long qualification
)
10521 load_vmcs12_host_state(vcpu
, vmcs12
);
10522 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10523 vmcs12
->exit_qualification
= qualification
;
10524 nested_vmx_succeed(vcpu
);
10525 if (enable_shadow_vmcs
)
10526 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10529 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10530 struct x86_instruction_info
*info
,
10531 enum x86_intercept_stage stage
)
10533 return X86EMUL_CONTINUE
;
10536 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10539 shrink_ple_window(vcpu
);
10542 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10543 struct kvm_memory_slot
*slot
)
10545 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10546 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10549 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10550 struct kvm_memory_slot
*slot
)
10552 kvm_mmu_slot_set_dirty(kvm
, slot
);
10555 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10557 kvm_flush_pml_buffers(kvm
);
10560 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10561 struct kvm_memory_slot
*memslot
,
10562 gfn_t offset
, unsigned long mask
)
10564 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10568 * This routine does the following things for vCPU which is going
10569 * to be blocked if VT-d PI is enabled.
10570 * - Store the vCPU to the wakeup list, so when interrupts happen
10571 * we can find the right vCPU to wake up.
10572 * - Change the Posted-interrupt descriptor as below:
10573 * 'NDST' <-- vcpu->pre_pcpu
10574 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10575 * - If 'ON' is set during this process, which means at least one
10576 * interrupt is posted for this vCPU, we cannot block it, in
10577 * this case, return 1, otherwise, return 0.
10580 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10582 unsigned long flags
;
10584 struct pi_desc old
, new;
10585 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10587 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10588 !irq_remapping_cap(IRQ_POSTING_CAP
))
10591 vcpu
->pre_pcpu
= vcpu
->cpu
;
10592 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10593 vcpu
->pre_pcpu
), flags
);
10594 list_add_tail(&vcpu
->blocked_vcpu_list
,
10595 &per_cpu(blocked_vcpu_on_cpu
,
10597 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10598 vcpu
->pre_pcpu
), flags
);
10601 old
.control
= new.control
= pi_desc
->control
;
10604 * We should not block the vCPU if
10605 * an interrupt is posted for it.
10607 if (pi_test_on(pi_desc
) == 1) {
10608 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10609 vcpu
->pre_pcpu
), flags
);
10610 list_del(&vcpu
->blocked_vcpu_list
);
10611 spin_unlock_irqrestore(
10612 &per_cpu(blocked_vcpu_on_cpu_lock
,
10613 vcpu
->pre_pcpu
), flags
);
10614 vcpu
->pre_pcpu
= -1;
10619 WARN((pi_desc
->sn
== 1),
10620 "Warning: SN field of posted-interrupts "
10621 "is set before blocking\n");
10624 * Since vCPU can be preempted during this process,
10625 * vcpu->cpu could be different with pre_pcpu, we
10626 * need to set pre_pcpu as the destination of wakeup
10627 * notification event, then we can find the right vCPU
10628 * to wakeup in wakeup handler if interrupts happen
10629 * when the vCPU is in blocked state.
10631 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10633 if (x2apic_enabled())
10636 new.ndst
= (dest
<< 8) & 0xFF00;
10638 /* set 'NV' to 'wakeup vector' */
10639 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10640 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10641 new.control
) != old
.control
);
10646 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10648 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10649 struct pi_desc old
, new;
10651 unsigned long flags
;
10653 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10654 !irq_remapping_cap(IRQ_POSTING_CAP
))
10658 old
.control
= new.control
= pi_desc
->control
;
10660 dest
= cpu_physical_id(vcpu
->cpu
);
10662 if (x2apic_enabled())
10665 new.ndst
= (dest
<< 8) & 0xFF00;
10667 /* Allow posting non-urgent interrupts */
10670 /* set 'NV' to 'notification vector' */
10671 new.nv
= POSTED_INTR_VECTOR
;
10672 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10673 new.control
) != old
.control
);
10675 if(vcpu
->pre_pcpu
!= -1) {
10677 &per_cpu(blocked_vcpu_on_cpu_lock
,
10678 vcpu
->pre_pcpu
), flags
);
10679 list_del(&vcpu
->blocked_vcpu_list
);
10680 spin_unlock_irqrestore(
10681 &per_cpu(blocked_vcpu_on_cpu_lock
,
10682 vcpu
->pre_pcpu
), flags
);
10683 vcpu
->pre_pcpu
= -1;
10688 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10691 * @host_irq: host irq of the interrupt
10692 * @guest_irq: gsi of the interrupt
10693 * @set: set or unset PI
10694 * returns 0 on success, < 0 on failure
10696 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10697 uint32_t guest_irq
, bool set
)
10699 struct kvm_kernel_irq_routing_entry
*e
;
10700 struct kvm_irq_routing_table
*irq_rt
;
10701 struct kvm_lapic_irq irq
;
10702 struct kvm_vcpu
*vcpu
;
10703 struct vcpu_data vcpu_info
;
10704 int idx
, ret
= -EINVAL
;
10706 if (!kvm_arch_has_assigned_device(kvm
) ||
10707 !irq_remapping_cap(IRQ_POSTING_CAP
))
10710 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10711 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10712 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10714 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10715 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10718 * VT-d PI cannot support posting multicast/broadcast
10719 * interrupts to a vCPU, we still use interrupt remapping
10720 * for these kind of interrupts.
10722 * For lowest-priority interrupts, we only support
10723 * those with single CPU as the destination, e.g. user
10724 * configures the interrupts via /proc/irq or uses
10725 * irqbalance to make the interrupts single-CPU.
10727 * We will support full lowest-priority interrupt later.
10730 kvm_set_msi_irq(e
, &irq
);
10731 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
))
10734 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10735 vcpu_info
.vector
= irq
.vector
;
10737 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, e
->gsi
,
10738 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10741 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10743 /* suppress notification event before unposting */
10744 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10745 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10746 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10750 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10758 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10762 static struct kvm_x86_ops vmx_x86_ops
= {
10763 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10764 .disabled_by_bios
= vmx_disabled_by_bios
,
10765 .hardware_setup
= hardware_setup
,
10766 .hardware_unsetup
= hardware_unsetup
,
10767 .check_processor_compatibility
= vmx_check_processor_compat
,
10768 .hardware_enable
= hardware_enable
,
10769 .hardware_disable
= hardware_disable
,
10770 .cpu_has_accelerated_tpr
= report_flexpriority
,
10771 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10773 .vcpu_create
= vmx_create_vcpu
,
10774 .vcpu_free
= vmx_free_vcpu
,
10775 .vcpu_reset
= vmx_vcpu_reset
,
10777 .prepare_guest_switch
= vmx_save_host_state
,
10778 .vcpu_load
= vmx_vcpu_load
,
10779 .vcpu_put
= vmx_vcpu_put
,
10781 .update_bp_intercept
= update_exception_bitmap
,
10782 .get_msr
= vmx_get_msr
,
10783 .set_msr
= vmx_set_msr
,
10784 .get_segment_base
= vmx_get_segment_base
,
10785 .get_segment
= vmx_get_segment
,
10786 .set_segment
= vmx_set_segment
,
10787 .get_cpl
= vmx_get_cpl
,
10788 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10789 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10790 .decache_cr3
= vmx_decache_cr3
,
10791 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10792 .set_cr0
= vmx_set_cr0
,
10793 .set_cr3
= vmx_set_cr3
,
10794 .set_cr4
= vmx_set_cr4
,
10795 .set_efer
= vmx_set_efer
,
10796 .get_idt
= vmx_get_idt
,
10797 .set_idt
= vmx_set_idt
,
10798 .get_gdt
= vmx_get_gdt
,
10799 .set_gdt
= vmx_set_gdt
,
10800 .get_dr6
= vmx_get_dr6
,
10801 .set_dr6
= vmx_set_dr6
,
10802 .set_dr7
= vmx_set_dr7
,
10803 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10804 .cache_reg
= vmx_cache_reg
,
10805 .get_rflags
= vmx_get_rflags
,
10806 .set_rflags
= vmx_set_rflags
,
10807 .fpu_activate
= vmx_fpu_activate
,
10808 .fpu_deactivate
= vmx_fpu_deactivate
,
10810 .tlb_flush
= vmx_flush_tlb
,
10812 .run
= vmx_vcpu_run
,
10813 .handle_exit
= vmx_handle_exit
,
10814 .skip_emulated_instruction
= skip_emulated_instruction
,
10815 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10816 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10817 .patch_hypercall
= vmx_patch_hypercall
,
10818 .set_irq
= vmx_inject_irq
,
10819 .set_nmi
= vmx_inject_nmi
,
10820 .queue_exception
= vmx_queue_exception
,
10821 .cancel_injection
= vmx_cancel_injection
,
10822 .interrupt_allowed
= vmx_interrupt_allowed
,
10823 .nmi_allowed
= vmx_nmi_allowed
,
10824 .get_nmi_mask
= vmx_get_nmi_mask
,
10825 .set_nmi_mask
= vmx_set_nmi_mask
,
10826 .enable_nmi_window
= enable_nmi_window
,
10827 .enable_irq_window
= enable_irq_window
,
10828 .update_cr8_intercept
= update_cr8_intercept
,
10829 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10830 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10831 .cpu_uses_apicv
= vmx_cpu_uses_apicv
,
10832 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10833 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10834 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10835 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10836 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10838 .set_tss_addr
= vmx_set_tss_addr
,
10839 .get_tdp_level
= get_ept_level
,
10840 .get_mt_mask
= vmx_get_mt_mask
,
10842 .get_exit_info
= vmx_get_exit_info
,
10844 .get_lpage_level
= vmx_get_lpage_level
,
10846 .cpuid_update
= vmx_cpuid_update
,
10848 .rdtscp_supported
= vmx_rdtscp_supported
,
10849 .invpcid_supported
= vmx_invpcid_supported
,
10851 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10853 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10855 .read_tsc_offset
= vmx_read_tsc_offset
,
10856 .write_tsc_offset
= vmx_write_tsc_offset
,
10857 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
10858 .read_l1_tsc
= vmx_read_l1_tsc
,
10860 .set_tdp_cr3
= vmx_set_cr3
,
10862 .check_intercept
= vmx_check_intercept
,
10863 .handle_external_intr
= vmx_handle_external_intr
,
10864 .mpx_supported
= vmx_mpx_supported
,
10865 .xsaves_supported
= vmx_xsaves_supported
,
10867 .check_nested_events
= vmx_check_nested_events
,
10869 .sched_in
= vmx_sched_in
,
10871 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10872 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10873 .flush_log_dirty
= vmx_flush_log_dirty
,
10874 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10876 .pre_block
= vmx_pre_block
,
10877 .post_block
= vmx_post_block
,
10879 .pmu_ops
= &intel_pmu_ops
,
10881 .update_pi_irte
= vmx_update_pi_irte
,
10884 static int __init
vmx_init(void)
10886 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10887 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10891 #ifdef CONFIG_KEXEC_CORE
10892 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10893 crash_vmclear_local_loaded_vmcss
);
10899 static void __exit
vmx_exit(void)
10901 #ifdef CONFIG_KEXEC_CORE
10902 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10909 module_init(vmx_init
)
10910 module_exit(vmx_exit
)