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KVM: x86: fix CR8 handling
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42
43 #include "trace.h"
44
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
49
50 static int __read_mostly bypass_guest_pf = 1;
51 module_param(bypass_guest_pf, bool, S_IRUGO);
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
92 /*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
103 #define KVM_VMX_DEFAULT_PLE_GAP 41
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106 module_param(ple_gap, int, S_IRUGO);
107
108 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109 module_param(ple_window, int, S_IRUGO);
110
111 #define NR_AUTOLOAD_MSRS 1
112
113 struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117 };
118
119 struct shared_msr_entry {
120 unsigned index;
121 u64 data;
122 u64 mask;
123 };
124
125 struct vcpu_vmx {
126 struct kvm_vcpu vcpu;
127 struct list_head local_vcpus_link;
128 unsigned long host_rsp;
129 int launched;
130 u8 fail;
131 u32 exit_intr_info;
132 u32 idt_vectoring_info;
133 struct shared_msr_entry *guest_msrs;
134 int nmsrs;
135 int save_nmsrs;
136 #ifdef CONFIG_X86_64
137 u64 msr_host_kernel_gs_base;
138 u64 msr_guest_kernel_gs_base;
139 #endif
140 struct vmcs *vmcs;
141 struct msr_autoload {
142 unsigned nr;
143 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
144 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
145 } msr_autoload;
146 struct {
147 int loaded;
148 u16 fs_sel, gs_sel, ldt_sel;
149 int gs_ldt_reload_needed;
150 int fs_reload_needed;
151 } host_state;
152 struct {
153 int vm86_active;
154 ulong save_rflags;
155 struct kvm_save_segment {
156 u16 selector;
157 unsigned long base;
158 u32 limit;
159 u32 ar;
160 } tr, es, ds, fs, gs;
161 } rmode;
162 int vpid;
163 bool emulation_required;
164
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked;
167 ktime_t entry_time;
168 s64 vnmi_blocked_time;
169 u32 exit_reason;
170
171 bool rdtscp_enabled;
172 };
173
174 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
175 {
176 return container_of(vcpu, struct vcpu_vmx, vcpu);
177 }
178
179 static int init_rmode(struct kvm *kvm);
180 static u64 construct_eptp(unsigned long root_hpa);
181 static void kvm_cpu_vmxon(u64 addr);
182 static void kvm_cpu_vmxoff(void);
183
184 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
185 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
186 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
187 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
188
189 static unsigned long *vmx_io_bitmap_a;
190 static unsigned long *vmx_io_bitmap_b;
191 static unsigned long *vmx_msr_bitmap_legacy;
192 static unsigned long *vmx_msr_bitmap_longmode;
193
194 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
195 static DEFINE_SPINLOCK(vmx_vpid_lock);
196
197 static struct vmcs_config {
198 int size;
199 int order;
200 u32 revision_id;
201 u32 pin_based_exec_ctrl;
202 u32 cpu_based_exec_ctrl;
203 u32 cpu_based_2nd_exec_ctrl;
204 u32 vmexit_ctrl;
205 u32 vmentry_ctrl;
206 } vmcs_config;
207
208 static struct vmx_capability {
209 u32 ept;
210 u32 vpid;
211 } vmx_capability;
212
213 #define VMX_SEGMENT_FIELD(seg) \
214 [VCPU_SREG_##seg] = { \
215 .selector = GUEST_##seg##_SELECTOR, \
216 .base = GUEST_##seg##_BASE, \
217 .limit = GUEST_##seg##_LIMIT, \
218 .ar_bytes = GUEST_##seg##_AR_BYTES, \
219 }
220
221 static struct kvm_vmx_segment_field {
222 unsigned selector;
223 unsigned base;
224 unsigned limit;
225 unsigned ar_bytes;
226 } kvm_vmx_segment_fields[] = {
227 VMX_SEGMENT_FIELD(CS),
228 VMX_SEGMENT_FIELD(DS),
229 VMX_SEGMENT_FIELD(ES),
230 VMX_SEGMENT_FIELD(FS),
231 VMX_SEGMENT_FIELD(GS),
232 VMX_SEGMENT_FIELD(SS),
233 VMX_SEGMENT_FIELD(TR),
234 VMX_SEGMENT_FIELD(LDTR),
235 };
236
237 static u64 host_efer;
238
239 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
240
241 /*
242 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
243 * away by decrementing the array size.
244 */
245 static const u32 vmx_msr_index[] = {
246 #ifdef CONFIG_X86_64
247 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
248 #endif
249 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
250 };
251 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
252
253 static inline bool is_page_fault(u32 intr_info)
254 {
255 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
256 INTR_INFO_VALID_MASK)) ==
257 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
258 }
259
260 static inline bool is_no_device(u32 intr_info)
261 {
262 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
263 INTR_INFO_VALID_MASK)) ==
264 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
265 }
266
267 static inline bool is_invalid_opcode(u32 intr_info)
268 {
269 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
270 INTR_INFO_VALID_MASK)) ==
271 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
272 }
273
274 static inline bool is_external_interrupt(u32 intr_info)
275 {
276 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
277 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
278 }
279
280 static inline bool is_machine_check(u32 intr_info)
281 {
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
283 INTR_INFO_VALID_MASK)) ==
284 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
285 }
286
287 static inline bool cpu_has_vmx_msr_bitmap(void)
288 {
289 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
290 }
291
292 static inline bool cpu_has_vmx_tpr_shadow(void)
293 {
294 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
295 }
296
297 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
298 {
299 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
300 }
301
302 static inline bool cpu_has_secondary_exec_ctrls(void)
303 {
304 return vmcs_config.cpu_based_exec_ctrl &
305 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
306 }
307
308 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
309 {
310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
312 }
313
314 static inline bool cpu_has_vmx_flexpriority(void)
315 {
316 return cpu_has_vmx_tpr_shadow() &&
317 cpu_has_vmx_virtualize_apic_accesses();
318 }
319
320 static inline bool cpu_has_vmx_ept_execute_only(void)
321 {
322 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
323 }
324
325 static inline bool cpu_has_vmx_eptp_uncacheable(void)
326 {
327 return vmx_capability.ept & VMX_EPTP_UC_BIT;
328 }
329
330 static inline bool cpu_has_vmx_eptp_writeback(void)
331 {
332 return vmx_capability.ept & VMX_EPTP_WB_BIT;
333 }
334
335 static inline bool cpu_has_vmx_ept_2m_page(void)
336 {
337 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
338 }
339
340 static inline bool cpu_has_vmx_ept_1g_page(void)
341 {
342 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
343 }
344
345 static inline bool cpu_has_vmx_ept_4levels(void)
346 {
347 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
348 }
349
350 static inline bool cpu_has_vmx_invept_individual_addr(void)
351 {
352 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
353 }
354
355 static inline bool cpu_has_vmx_invept_context(void)
356 {
357 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
358 }
359
360 static inline bool cpu_has_vmx_invept_global(void)
361 {
362 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
363 }
364
365 static inline bool cpu_has_vmx_invvpid_single(void)
366 {
367 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
368 }
369
370 static inline bool cpu_has_vmx_invvpid_global(void)
371 {
372 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
373 }
374
375 static inline bool cpu_has_vmx_ept(void)
376 {
377 return vmcs_config.cpu_based_2nd_exec_ctrl &
378 SECONDARY_EXEC_ENABLE_EPT;
379 }
380
381 static inline bool cpu_has_vmx_unrestricted_guest(void)
382 {
383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_UNRESTRICTED_GUEST;
385 }
386
387 static inline bool cpu_has_vmx_ple(void)
388 {
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
391 }
392
393 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
394 {
395 return flexpriority_enabled && irqchip_in_kernel(kvm);
396 }
397
398 static inline bool cpu_has_vmx_vpid(void)
399 {
400 return vmcs_config.cpu_based_2nd_exec_ctrl &
401 SECONDARY_EXEC_ENABLE_VPID;
402 }
403
404 static inline bool cpu_has_vmx_rdtscp(void)
405 {
406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_RDTSCP;
408 }
409
410 static inline bool cpu_has_virtual_nmis(void)
411 {
412 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
413 }
414
415 static inline bool cpu_has_vmx_wbinvd_exit(void)
416 {
417 return vmcs_config.cpu_based_2nd_exec_ctrl &
418 SECONDARY_EXEC_WBINVD_EXITING;
419 }
420
421 static inline bool report_flexpriority(void)
422 {
423 return flexpriority_enabled;
424 }
425
426 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
427 {
428 int i;
429
430 for (i = 0; i < vmx->nmsrs; ++i)
431 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
432 return i;
433 return -1;
434 }
435
436 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
437 {
438 struct {
439 u64 vpid : 16;
440 u64 rsvd : 48;
441 u64 gva;
442 } operand = { vpid, 0, gva };
443
444 asm volatile (__ex(ASM_VMX_INVVPID)
445 /* CF==1 or ZF==1 --> rc = -1 */
446 "; ja 1f ; ud2 ; 1:"
447 : : "a"(&operand), "c"(ext) : "cc", "memory");
448 }
449
450 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
451 {
452 struct {
453 u64 eptp, gpa;
454 } operand = {eptp, gpa};
455
456 asm volatile (__ex(ASM_VMX_INVEPT)
457 /* CF==1 or ZF==1 --> rc = -1 */
458 "; ja 1f ; ud2 ; 1:\n"
459 : : "a" (&operand), "c" (ext) : "cc", "memory");
460 }
461
462 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
463 {
464 int i;
465
466 i = __find_msr_index(vmx, msr);
467 if (i >= 0)
468 return &vmx->guest_msrs[i];
469 return NULL;
470 }
471
472 static void vmcs_clear(struct vmcs *vmcs)
473 {
474 u64 phys_addr = __pa(vmcs);
475 u8 error;
476
477 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
478 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
479 : "cc", "memory");
480 if (error)
481 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
482 vmcs, phys_addr);
483 }
484
485 static void vmcs_load(struct vmcs *vmcs)
486 {
487 u64 phys_addr = __pa(vmcs);
488 u8 error;
489
490 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
491 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
492 : "cc", "memory");
493 if (error)
494 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
495 vmcs, phys_addr);
496 }
497
498 static void __vcpu_clear(void *arg)
499 {
500 struct vcpu_vmx *vmx = arg;
501 int cpu = raw_smp_processor_id();
502
503 if (vmx->vcpu.cpu == cpu)
504 vmcs_clear(vmx->vmcs);
505 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
506 per_cpu(current_vmcs, cpu) = NULL;
507 list_del(&vmx->local_vcpus_link);
508 vmx->vcpu.cpu = -1;
509 vmx->launched = 0;
510 }
511
512 static void vcpu_clear(struct vcpu_vmx *vmx)
513 {
514 if (vmx->vcpu.cpu == -1)
515 return;
516 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
517 }
518
519 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
520 {
521 if (vmx->vpid == 0)
522 return;
523
524 if (cpu_has_vmx_invvpid_single())
525 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
526 }
527
528 static inline void vpid_sync_vcpu_global(void)
529 {
530 if (cpu_has_vmx_invvpid_global())
531 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
532 }
533
534 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
535 {
536 if (cpu_has_vmx_invvpid_single())
537 vpid_sync_vcpu_single(vmx);
538 else
539 vpid_sync_vcpu_global();
540 }
541
542 static inline void ept_sync_global(void)
543 {
544 if (cpu_has_vmx_invept_global())
545 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
546 }
547
548 static inline void ept_sync_context(u64 eptp)
549 {
550 if (enable_ept) {
551 if (cpu_has_vmx_invept_context())
552 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
553 else
554 ept_sync_global();
555 }
556 }
557
558 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
559 {
560 if (enable_ept) {
561 if (cpu_has_vmx_invept_individual_addr())
562 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
563 eptp, gpa);
564 else
565 ept_sync_context(eptp);
566 }
567 }
568
569 static unsigned long vmcs_readl(unsigned long field)
570 {
571 unsigned long value = 0;
572
573 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
574 : "+a"(value) : "d"(field) : "cc");
575 return value;
576 }
577
578 static u16 vmcs_read16(unsigned long field)
579 {
580 return vmcs_readl(field);
581 }
582
583 static u32 vmcs_read32(unsigned long field)
584 {
585 return vmcs_readl(field);
586 }
587
588 static u64 vmcs_read64(unsigned long field)
589 {
590 #ifdef CONFIG_X86_64
591 return vmcs_readl(field);
592 #else
593 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
594 #endif
595 }
596
597 static noinline void vmwrite_error(unsigned long field, unsigned long value)
598 {
599 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
600 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
601 dump_stack();
602 }
603
604 static void vmcs_writel(unsigned long field, unsigned long value)
605 {
606 u8 error;
607
608 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
609 : "=q"(error) : "a"(value), "d"(field) : "cc");
610 if (unlikely(error))
611 vmwrite_error(field, value);
612 }
613
614 static void vmcs_write16(unsigned long field, u16 value)
615 {
616 vmcs_writel(field, value);
617 }
618
619 static void vmcs_write32(unsigned long field, u32 value)
620 {
621 vmcs_writel(field, value);
622 }
623
624 static void vmcs_write64(unsigned long field, u64 value)
625 {
626 vmcs_writel(field, value);
627 #ifndef CONFIG_X86_64
628 asm volatile ("");
629 vmcs_writel(field+1, value >> 32);
630 #endif
631 }
632
633 static void vmcs_clear_bits(unsigned long field, u32 mask)
634 {
635 vmcs_writel(field, vmcs_readl(field) & ~mask);
636 }
637
638 static void vmcs_set_bits(unsigned long field, u32 mask)
639 {
640 vmcs_writel(field, vmcs_readl(field) | mask);
641 }
642
643 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
644 {
645 u32 eb;
646
647 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
648 (1u << NM_VECTOR) | (1u << DB_VECTOR);
649 if ((vcpu->guest_debug &
650 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
651 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
652 eb |= 1u << BP_VECTOR;
653 if (to_vmx(vcpu)->rmode.vm86_active)
654 eb = ~0;
655 if (enable_ept)
656 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
657 if (vcpu->fpu_active)
658 eb &= ~(1u << NM_VECTOR);
659 vmcs_write32(EXCEPTION_BITMAP, eb);
660 }
661
662 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
663 {
664 unsigned i;
665 struct msr_autoload *m = &vmx->msr_autoload;
666
667 for (i = 0; i < m->nr; ++i)
668 if (m->guest[i].index == msr)
669 break;
670
671 if (i == m->nr)
672 return;
673 --m->nr;
674 m->guest[i] = m->guest[m->nr];
675 m->host[i] = m->host[m->nr];
676 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
677 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
678 }
679
680 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
681 u64 guest_val, u64 host_val)
682 {
683 unsigned i;
684 struct msr_autoload *m = &vmx->msr_autoload;
685
686 for (i = 0; i < m->nr; ++i)
687 if (m->guest[i].index == msr)
688 break;
689
690 if (i == m->nr) {
691 ++m->nr;
692 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
693 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
694 }
695
696 m->guest[i].index = msr;
697 m->guest[i].value = guest_val;
698 m->host[i].index = msr;
699 m->host[i].value = host_val;
700 }
701
702 static void reload_tss(void)
703 {
704 /*
705 * VT restores TR but not its size. Useless.
706 */
707 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
708 struct desc_struct *descs;
709
710 descs = (void *)gdt->address;
711 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
712 load_TR_desc();
713 }
714
715 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
716 {
717 u64 guest_efer;
718 u64 ignore_bits;
719
720 guest_efer = vmx->vcpu.arch.efer;
721
722 /*
723 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
724 * outside long mode
725 */
726 ignore_bits = EFER_NX | EFER_SCE;
727 #ifdef CONFIG_X86_64
728 ignore_bits |= EFER_LMA | EFER_LME;
729 /* SCE is meaningful only in long mode on Intel */
730 if (guest_efer & EFER_LMA)
731 ignore_bits &= ~(u64)EFER_SCE;
732 #endif
733 guest_efer &= ~ignore_bits;
734 guest_efer |= host_efer & ignore_bits;
735 vmx->guest_msrs[efer_offset].data = guest_efer;
736 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
737
738 clear_atomic_switch_msr(vmx, MSR_EFER);
739 /* On ept, can't emulate nx, and must switch nx atomically */
740 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
741 guest_efer = vmx->vcpu.arch.efer;
742 if (!(guest_efer & EFER_LMA))
743 guest_efer &= ~EFER_LME;
744 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
745 return false;
746 }
747
748 return true;
749 }
750
751 static unsigned long segment_base(u16 selector)
752 {
753 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
754 struct desc_struct *d;
755 unsigned long table_base;
756 unsigned long v;
757
758 if (!(selector & ~3))
759 return 0;
760
761 table_base = gdt->address;
762
763 if (selector & 4) { /* from ldt */
764 u16 ldt_selector = kvm_read_ldt();
765
766 if (!(ldt_selector & ~3))
767 return 0;
768
769 table_base = segment_base(ldt_selector);
770 }
771 d = (struct desc_struct *)(table_base + (selector & ~7));
772 v = get_desc_base(d);
773 #ifdef CONFIG_X86_64
774 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
775 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
776 #endif
777 return v;
778 }
779
780 static inline unsigned long kvm_read_tr_base(void)
781 {
782 u16 tr;
783 asm("str %0" : "=g"(tr));
784 return segment_base(tr);
785 }
786
787 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
788 {
789 struct vcpu_vmx *vmx = to_vmx(vcpu);
790 int i;
791
792 if (vmx->host_state.loaded)
793 return;
794
795 vmx->host_state.loaded = 1;
796 /*
797 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
798 * allow segment selectors with cpl > 0 or ti == 1.
799 */
800 vmx->host_state.ldt_sel = kvm_read_ldt();
801 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
802 savesegment(fs, vmx->host_state.fs_sel);
803 if (!(vmx->host_state.fs_sel & 7)) {
804 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
805 vmx->host_state.fs_reload_needed = 0;
806 } else {
807 vmcs_write16(HOST_FS_SELECTOR, 0);
808 vmx->host_state.fs_reload_needed = 1;
809 }
810 savesegment(gs, vmx->host_state.gs_sel);
811 if (!(vmx->host_state.gs_sel & 7))
812 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
813 else {
814 vmcs_write16(HOST_GS_SELECTOR, 0);
815 vmx->host_state.gs_ldt_reload_needed = 1;
816 }
817
818 #ifdef CONFIG_X86_64
819 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
820 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
821 #else
822 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
823 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
824 #endif
825
826 #ifdef CONFIG_X86_64
827 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
828 if (is_long_mode(&vmx->vcpu))
829 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
830 #endif
831 for (i = 0; i < vmx->save_nmsrs; ++i)
832 kvm_set_shared_msr(vmx->guest_msrs[i].index,
833 vmx->guest_msrs[i].data,
834 vmx->guest_msrs[i].mask);
835 }
836
837 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
838 {
839 if (!vmx->host_state.loaded)
840 return;
841
842 ++vmx->vcpu.stat.host_state_reload;
843 vmx->host_state.loaded = 0;
844 #ifdef CONFIG_X86_64
845 if (is_long_mode(&vmx->vcpu))
846 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
847 #endif
848 if (vmx->host_state.gs_ldt_reload_needed) {
849 kvm_load_ldt(vmx->host_state.ldt_sel);
850 #ifdef CONFIG_X86_64
851 load_gs_index(vmx->host_state.gs_sel);
852 #else
853 loadsegment(gs, vmx->host_state.gs_sel);
854 #endif
855 }
856 if (vmx->host_state.fs_reload_needed)
857 loadsegment(fs, vmx->host_state.fs_sel);
858 reload_tss();
859 #ifdef CONFIG_X86_64
860 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
861 #endif
862 if (current_thread_info()->status & TS_USEDFPU)
863 clts();
864 load_gdt(&__get_cpu_var(host_gdt));
865 }
866
867 static void vmx_load_host_state(struct vcpu_vmx *vmx)
868 {
869 preempt_disable();
870 __vmx_load_host_state(vmx);
871 preempt_enable();
872 }
873
874 /*
875 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
876 * vcpu mutex is already taken.
877 */
878 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
879 {
880 struct vcpu_vmx *vmx = to_vmx(vcpu);
881 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
882
883 if (!vmm_exclusive)
884 kvm_cpu_vmxon(phys_addr);
885 else if (vcpu->cpu != cpu)
886 vcpu_clear(vmx);
887
888 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
889 per_cpu(current_vmcs, cpu) = vmx->vmcs;
890 vmcs_load(vmx->vmcs);
891 }
892
893 if (vcpu->cpu != cpu) {
894 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
895 unsigned long sysenter_esp;
896
897 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
898 local_irq_disable();
899 list_add(&vmx->local_vcpus_link,
900 &per_cpu(vcpus_on_cpu, cpu));
901 local_irq_enable();
902
903 /*
904 * Linux uses per-cpu TSS and GDT, so set these when switching
905 * processors.
906 */
907 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
908 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
909
910 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
911 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
912 }
913 }
914
915 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
916 {
917 __vmx_load_host_state(to_vmx(vcpu));
918 if (!vmm_exclusive) {
919 __vcpu_clear(to_vmx(vcpu));
920 kvm_cpu_vmxoff();
921 }
922 }
923
924 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
925 {
926 ulong cr0;
927
928 if (vcpu->fpu_active)
929 return;
930 vcpu->fpu_active = 1;
931 cr0 = vmcs_readl(GUEST_CR0);
932 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
933 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
934 vmcs_writel(GUEST_CR0, cr0);
935 update_exception_bitmap(vcpu);
936 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
937 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
938 }
939
940 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
941
942 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
943 {
944 vmx_decache_cr0_guest_bits(vcpu);
945 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
946 update_exception_bitmap(vcpu);
947 vcpu->arch.cr0_guest_owned_bits = 0;
948 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
949 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
950 }
951
952 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
953 {
954 unsigned long rflags, save_rflags;
955
956 rflags = vmcs_readl(GUEST_RFLAGS);
957 if (to_vmx(vcpu)->rmode.vm86_active) {
958 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
959 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
960 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
961 }
962 return rflags;
963 }
964
965 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
966 {
967 if (to_vmx(vcpu)->rmode.vm86_active) {
968 to_vmx(vcpu)->rmode.save_rflags = rflags;
969 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
970 }
971 vmcs_writel(GUEST_RFLAGS, rflags);
972 }
973
974 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
975 {
976 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
977 int ret = 0;
978
979 if (interruptibility & GUEST_INTR_STATE_STI)
980 ret |= KVM_X86_SHADOW_INT_STI;
981 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
982 ret |= KVM_X86_SHADOW_INT_MOV_SS;
983
984 return ret & mask;
985 }
986
987 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
988 {
989 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
990 u32 interruptibility = interruptibility_old;
991
992 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
993
994 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
995 interruptibility |= GUEST_INTR_STATE_MOV_SS;
996 else if (mask & KVM_X86_SHADOW_INT_STI)
997 interruptibility |= GUEST_INTR_STATE_STI;
998
999 if ((interruptibility != interruptibility_old))
1000 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1001 }
1002
1003 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1004 {
1005 unsigned long rip;
1006
1007 rip = kvm_rip_read(vcpu);
1008 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1009 kvm_rip_write(vcpu, rip);
1010
1011 /* skipping an emulated instruction also counts */
1012 vmx_set_interrupt_shadow(vcpu, 0);
1013 }
1014
1015 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1016 {
1017 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1018 * explicitly skip the instruction because if the HLT state is set, then
1019 * the instruction is already executing and RIP has already been
1020 * advanced. */
1021 if (!yield_on_hlt &&
1022 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1023 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1024 }
1025
1026 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1027 bool has_error_code, u32 error_code,
1028 bool reinject)
1029 {
1030 struct vcpu_vmx *vmx = to_vmx(vcpu);
1031 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1032
1033 if (has_error_code) {
1034 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1035 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1036 }
1037
1038 if (vmx->rmode.vm86_active) {
1039 if (kvm_inject_realmode_interrupt(vcpu, nr) != EMULATE_DONE)
1040 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1041 return;
1042 }
1043
1044 if (kvm_exception_is_soft(nr)) {
1045 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1046 vmx->vcpu.arch.event_exit_inst_len);
1047 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1048 } else
1049 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1050
1051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1052 vmx_clear_hlt(vcpu);
1053 }
1054
1055 static bool vmx_rdtscp_supported(void)
1056 {
1057 return cpu_has_vmx_rdtscp();
1058 }
1059
1060 /*
1061 * Swap MSR entry in host/guest MSR entry array.
1062 */
1063 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1064 {
1065 struct shared_msr_entry tmp;
1066
1067 tmp = vmx->guest_msrs[to];
1068 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1069 vmx->guest_msrs[from] = tmp;
1070 }
1071
1072 /*
1073 * Set up the vmcs to automatically save and restore system
1074 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1075 * mode, as fiddling with msrs is very expensive.
1076 */
1077 static void setup_msrs(struct vcpu_vmx *vmx)
1078 {
1079 int save_nmsrs, index;
1080 unsigned long *msr_bitmap;
1081
1082 vmx_load_host_state(vmx);
1083 save_nmsrs = 0;
1084 #ifdef CONFIG_X86_64
1085 if (is_long_mode(&vmx->vcpu)) {
1086 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1087 if (index >= 0)
1088 move_msr_up(vmx, index, save_nmsrs++);
1089 index = __find_msr_index(vmx, MSR_LSTAR);
1090 if (index >= 0)
1091 move_msr_up(vmx, index, save_nmsrs++);
1092 index = __find_msr_index(vmx, MSR_CSTAR);
1093 if (index >= 0)
1094 move_msr_up(vmx, index, save_nmsrs++);
1095 index = __find_msr_index(vmx, MSR_TSC_AUX);
1096 if (index >= 0 && vmx->rdtscp_enabled)
1097 move_msr_up(vmx, index, save_nmsrs++);
1098 /*
1099 * MSR_STAR is only needed on long mode guests, and only
1100 * if efer.sce is enabled.
1101 */
1102 index = __find_msr_index(vmx, MSR_STAR);
1103 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1104 move_msr_up(vmx, index, save_nmsrs++);
1105 }
1106 #endif
1107 index = __find_msr_index(vmx, MSR_EFER);
1108 if (index >= 0 && update_transition_efer(vmx, index))
1109 move_msr_up(vmx, index, save_nmsrs++);
1110
1111 vmx->save_nmsrs = save_nmsrs;
1112
1113 if (cpu_has_vmx_msr_bitmap()) {
1114 if (is_long_mode(&vmx->vcpu))
1115 msr_bitmap = vmx_msr_bitmap_longmode;
1116 else
1117 msr_bitmap = vmx_msr_bitmap_legacy;
1118
1119 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1120 }
1121 }
1122
1123 /*
1124 * reads and returns guest's timestamp counter "register"
1125 * guest_tsc = host_tsc + tsc_offset -- 21.3
1126 */
1127 static u64 guest_read_tsc(void)
1128 {
1129 u64 host_tsc, tsc_offset;
1130
1131 rdtscll(host_tsc);
1132 tsc_offset = vmcs_read64(TSC_OFFSET);
1133 return host_tsc + tsc_offset;
1134 }
1135
1136 /*
1137 * writes 'offset' into guest's timestamp counter offset register
1138 */
1139 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1140 {
1141 vmcs_write64(TSC_OFFSET, offset);
1142 }
1143
1144 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1145 {
1146 u64 offset = vmcs_read64(TSC_OFFSET);
1147 vmcs_write64(TSC_OFFSET, offset + adjustment);
1148 }
1149
1150 /*
1151 * Reads an msr value (of 'msr_index') into 'pdata'.
1152 * Returns 0 on success, non-0 otherwise.
1153 * Assumes vcpu_load() was already called.
1154 */
1155 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1156 {
1157 u64 data;
1158 struct shared_msr_entry *msr;
1159
1160 if (!pdata) {
1161 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1162 return -EINVAL;
1163 }
1164
1165 switch (msr_index) {
1166 #ifdef CONFIG_X86_64
1167 case MSR_FS_BASE:
1168 data = vmcs_readl(GUEST_FS_BASE);
1169 break;
1170 case MSR_GS_BASE:
1171 data = vmcs_readl(GUEST_GS_BASE);
1172 break;
1173 case MSR_KERNEL_GS_BASE:
1174 vmx_load_host_state(to_vmx(vcpu));
1175 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1176 break;
1177 #endif
1178 case MSR_EFER:
1179 return kvm_get_msr_common(vcpu, msr_index, pdata);
1180 case MSR_IA32_TSC:
1181 data = guest_read_tsc();
1182 break;
1183 case MSR_IA32_SYSENTER_CS:
1184 data = vmcs_read32(GUEST_SYSENTER_CS);
1185 break;
1186 case MSR_IA32_SYSENTER_EIP:
1187 data = vmcs_readl(GUEST_SYSENTER_EIP);
1188 break;
1189 case MSR_IA32_SYSENTER_ESP:
1190 data = vmcs_readl(GUEST_SYSENTER_ESP);
1191 break;
1192 case MSR_TSC_AUX:
1193 if (!to_vmx(vcpu)->rdtscp_enabled)
1194 return 1;
1195 /* Otherwise falls through */
1196 default:
1197 vmx_load_host_state(to_vmx(vcpu));
1198 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1199 if (msr) {
1200 vmx_load_host_state(to_vmx(vcpu));
1201 data = msr->data;
1202 break;
1203 }
1204 return kvm_get_msr_common(vcpu, msr_index, pdata);
1205 }
1206
1207 *pdata = data;
1208 return 0;
1209 }
1210
1211 /*
1212 * Writes msr value into into the appropriate "register".
1213 * Returns 0 on success, non-0 otherwise.
1214 * Assumes vcpu_load() was already called.
1215 */
1216 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1217 {
1218 struct vcpu_vmx *vmx = to_vmx(vcpu);
1219 struct shared_msr_entry *msr;
1220 int ret = 0;
1221
1222 switch (msr_index) {
1223 case MSR_EFER:
1224 vmx_load_host_state(vmx);
1225 ret = kvm_set_msr_common(vcpu, msr_index, data);
1226 break;
1227 #ifdef CONFIG_X86_64
1228 case MSR_FS_BASE:
1229 vmcs_writel(GUEST_FS_BASE, data);
1230 break;
1231 case MSR_GS_BASE:
1232 vmcs_writel(GUEST_GS_BASE, data);
1233 break;
1234 case MSR_KERNEL_GS_BASE:
1235 vmx_load_host_state(vmx);
1236 vmx->msr_guest_kernel_gs_base = data;
1237 break;
1238 #endif
1239 case MSR_IA32_SYSENTER_CS:
1240 vmcs_write32(GUEST_SYSENTER_CS, data);
1241 break;
1242 case MSR_IA32_SYSENTER_EIP:
1243 vmcs_writel(GUEST_SYSENTER_EIP, data);
1244 break;
1245 case MSR_IA32_SYSENTER_ESP:
1246 vmcs_writel(GUEST_SYSENTER_ESP, data);
1247 break;
1248 case MSR_IA32_TSC:
1249 kvm_write_tsc(vcpu, data);
1250 break;
1251 case MSR_IA32_CR_PAT:
1252 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1253 vmcs_write64(GUEST_IA32_PAT, data);
1254 vcpu->arch.pat = data;
1255 break;
1256 }
1257 ret = kvm_set_msr_common(vcpu, msr_index, data);
1258 break;
1259 case MSR_TSC_AUX:
1260 if (!vmx->rdtscp_enabled)
1261 return 1;
1262 /* Check reserved bit, higher 32 bits should be zero */
1263 if ((data >> 32) != 0)
1264 return 1;
1265 /* Otherwise falls through */
1266 default:
1267 msr = find_msr_entry(vmx, msr_index);
1268 if (msr) {
1269 vmx_load_host_state(vmx);
1270 msr->data = data;
1271 break;
1272 }
1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
1274 }
1275
1276 return ret;
1277 }
1278
1279 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1280 {
1281 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1282 switch (reg) {
1283 case VCPU_REGS_RSP:
1284 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1285 break;
1286 case VCPU_REGS_RIP:
1287 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1288 break;
1289 case VCPU_EXREG_PDPTR:
1290 if (enable_ept)
1291 ept_save_pdptrs(vcpu);
1292 break;
1293 default:
1294 break;
1295 }
1296 }
1297
1298 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1299 {
1300 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1301 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1302 else
1303 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1304
1305 update_exception_bitmap(vcpu);
1306 }
1307
1308 static __init int cpu_has_kvm_support(void)
1309 {
1310 return cpu_has_vmx();
1311 }
1312
1313 static __init int vmx_disabled_by_bios(void)
1314 {
1315 u64 msr;
1316
1317 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1318 if (msr & FEATURE_CONTROL_LOCKED) {
1319 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1320 && tboot_enabled())
1321 return 1;
1322 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1323 && !tboot_enabled()) {
1324 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
1325 " activate TXT before enabling KVM\n");
1326 return 1;
1327 }
1328 }
1329
1330 return 0;
1331 /* locked but not enabled */
1332 }
1333
1334 static void kvm_cpu_vmxon(u64 addr)
1335 {
1336 asm volatile (ASM_VMX_VMXON_RAX
1337 : : "a"(&addr), "m"(addr)
1338 : "memory", "cc");
1339 }
1340
1341 static int hardware_enable(void *garbage)
1342 {
1343 int cpu = raw_smp_processor_id();
1344 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1345 u64 old, test_bits;
1346
1347 if (read_cr4() & X86_CR4_VMXE)
1348 return -EBUSY;
1349
1350 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1351 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1352
1353 test_bits = FEATURE_CONTROL_LOCKED;
1354 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1355 if (tboot_enabled())
1356 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1357
1358 if ((old & test_bits) != test_bits) {
1359 /* enable and lock */
1360 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1361 }
1362 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1363
1364 if (vmm_exclusive) {
1365 kvm_cpu_vmxon(phys_addr);
1366 ept_sync_global();
1367 }
1368
1369 store_gdt(&__get_cpu_var(host_gdt));
1370
1371 return 0;
1372 }
1373
1374 static void vmclear_local_vcpus(void)
1375 {
1376 int cpu = raw_smp_processor_id();
1377 struct vcpu_vmx *vmx, *n;
1378
1379 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1380 local_vcpus_link)
1381 __vcpu_clear(vmx);
1382 }
1383
1384
1385 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1386 * tricks.
1387 */
1388 static void kvm_cpu_vmxoff(void)
1389 {
1390 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1391 }
1392
1393 static void hardware_disable(void *garbage)
1394 {
1395 if (vmm_exclusive) {
1396 vmclear_local_vcpus();
1397 kvm_cpu_vmxoff();
1398 }
1399 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1400 }
1401
1402 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1403 u32 msr, u32 *result)
1404 {
1405 u32 vmx_msr_low, vmx_msr_high;
1406 u32 ctl = ctl_min | ctl_opt;
1407
1408 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1409
1410 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1411 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1412
1413 /* Ensure minimum (required) set of control bits are supported. */
1414 if (ctl_min & ~ctl)
1415 return -EIO;
1416
1417 *result = ctl;
1418 return 0;
1419 }
1420
1421 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1422 {
1423 u32 vmx_msr_low, vmx_msr_high;
1424 u32 min, opt, min2, opt2;
1425 u32 _pin_based_exec_control = 0;
1426 u32 _cpu_based_exec_control = 0;
1427 u32 _cpu_based_2nd_exec_control = 0;
1428 u32 _vmexit_control = 0;
1429 u32 _vmentry_control = 0;
1430
1431 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1432 opt = PIN_BASED_VIRTUAL_NMIS;
1433 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1434 &_pin_based_exec_control) < 0)
1435 return -EIO;
1436
1437 min =
1438 #ifdef CONFIG_X86_64
1439 CPU_BASED_CR8_LOAD_EXITING |
1440 CPU_BASED_CR8_STORE_EXITING |
1441 #endif
1442 CPU_BASED_CR3_LOAD_EXITING |
1443 CPU_BASED_CR3_STORE_EXITING |
1444 CPU_BASED_USE_IO_BITMAPS |
1445 CPU_BASED_MOV_DR_EXITING |
1446 CPU_BASED_USE_TSC_OFFSETING |
1447 CPU_BASED_MWAIT_EXITING |
1448 CPU_BASED_MONITOR_EXITING |
1449 CPU_BASED_INVLPG_EXITING;
1450
1451 if (yield_on_hlt)
1452 min |= CPU_BASED_HLT_EXITING;
1453
1454 opt = CPU_BASED_TPR_SHADOW |
1455 CPU_BASED_USE_MSR_BITMAPS |
1456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1457 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1458 &_cpu_based_exec_control) < 0)
1459 return -EIO;
1460 #ifdef CONFIG_X86_64
1461 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1462 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1463 ~CPU_BASED_CR8_STORE_EXITING;
1464 #endif
1465 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1466 min2 = 0;
1467 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1468 SECONDARY_EXEC_WBINVD_EXITING |
1469 SECONDARY_EXEC_ENABLE_VPID |
1470 SECONDARY_EXEC_ENABLE_EPT |
1471 SECONDARY_EXEC_UNRESTRICTED_GUEST |
1472 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1473 SECONDARY_EXEC_RDTSCP;
1474 if (adjust_vmx_controls(min2, opt2,
1475 MSR_IA32_VMX_PROCBASED_CTLS2,
1476 &_cpu_based_2nd_exec_control) < 0)
1477 return -EIO;
1478 }
1479 #ifndef CONFIG_X86_64
1480 if (!(_cpu_based_2nd_exec_control &
1481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1482 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1483 #endif
1484 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1486 enabled */
1487 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1488 CPU_BASED_CR3_STORE_EXITING |
1489 CPU_BASED_INVLPG_EXITING);
1490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1491 vmx_capability.ept, vmx_capability.vpid);
1492 }
1493
1494 min = 0;
1495 #ifdef CONFIG_X86_64
1496 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1497 #endif
1498 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1499 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1500 &_vmexit_control) < 0)
1501 return -EIO;
1502
1503 min = 0;
1504 opt = VM_ENTRY_LOAD_IA32_PAT;
1505 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1506 &_vmentry_control) < 0)
1507 return -EIO;
1508
1509 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1510
1511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1512 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1513 return -EIO;
1514
1515 #ifdef CONFIG_X86_64
1516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1517 if (vmx_msr_high & (1u<<16))
1518 return -EIO;
1519 #endif
1520
1521 /* Require Write-Back (WB) memory type for VMCS accesses. */
1522 if (((vmx_msr_high >> 18) & 15) != 6)
1523 return -EIO;
1524
1525 vmcs_conf->size = vmx_msr_high & 0x1fff;
1526 vmcs_conf->order = get_order(vmcs_config.size);
1527 vmcs_conf->revision_id = vmx_msr_low;
1528
1529 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1530 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1531 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1532 vmcs_conf->vmexit_ctrl = _vmexit_control;
1533 vmcs_conf->vmentry_ctrl = _vmentry_control;
1534
1535 return 0;
1536 }
1537
1538 static struct vmcs *alloc_vmcs_cpu(int cpu)
1539 {
1540 int node = cpu_to_node(cpu);
1541 struct page *pages;
1542 struct vmcs *vmcs;
1543
1544 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1545 if (!pages)
1546 return NULL;
1547 vmcs = page_address(pages);
1548 memset(vmcs, 0, vmcs_config.size);
1549 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1550 return vmcs;
1551 }
1552
1553 static struct vmcs *alloc_vmcs(void)
1554 {
1555 return alloc_vmcs_cpu(raw_smp_processor_id());
1556 }
1557
1558 static void free_vmcs(struct vmcs *vmcs)
1559 {
1560 free_pages((unsigned long)vmcs, vmcs_config.order);
1561 }
1562
1563 static void free_kvm_area(void)
1564 {
1565 int cpu;
1566
1567 for_each_possible_cpu(cpu) {
1568 free_vmcs(per_cpu(vmxarea, cpu));
1569 per_cpu(vmxarea, cpu) = NULL;
1570 }
1571 }
1572
1573 static __init int alloc_kvm_area(void)
1574 {
1575 int cpu;
1576
1577 for_each_possible_cpu(cpu) {
1578 struct vmcs *vmcs;
1579
1580 vmcs = alloc_vmcs_cpu(cpu);
1581 if (!vmcs) {
1582 free_kvm_area();
1583 return -ENOMEM;
1584 }
1585
1586 per_cpu(vmxarea, cpu) = vmcs;
1587 }
1588 return 0;
1589 }
1590
1591 static __init int hardware_setup(void)
1592 {
1593 if (setup_vmcs_config(&vmcs_config) < 0)
1594 return -EIO;
1595
1596 if (boot_cpu_has(X86_FEATURE_NX))
1597 kvm_enable_efer_bits(EFER_NX);
1598
1599 if (!cpu_has_vmx_vpid())
1600 enable_vpid = 0;
1601
1602 if (!cpu_has_vmx_ept() ||
1603 !cpu_has_vmx_ept_4levels()) {
1604 enable_ept = 0;
1605 enable_unrestricted_guest = 0;
1606 }
1607
1608 if (!cpu_has_vmx_unrestricted_guest())
1609 enable_unrestricted_guest = 0;
1610
1611 if (!cpu_has_vmx_flexpriority())
1612 flexpriority_enabled = 0;
1613
1614 if (!cpu_has_vmx_tpr_shadow())
1615 kvm_x86_ops->update_cr8_intercept = NULL;
1616
1617 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1618 kvm_disable_largepages();
1619
1620 if (!cpu_has_vmx_ple())
1621 ple_gap = 0;
1622
1623 return alloc_kvm_area();
1624 }
1625
1626 static __exit void hardware_unsetup(void)
1627 {
1628 free_kvm_area();
1629 }
1630
1631 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1632 {
1633 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1634
1635 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1636 vmcs_write16(sf->selector, save->selector);
1637 vmcs_writel(sf->base, save->base);
1638 vmcs_write32(sf->limit, save->limit);
1639 vmcs_write32(sf->ar_bytes, save->ar);
1640 } else {
1641 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1642 << AR_DPL_SHIFT;
1643 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1644 }
1645 }
1646
1647 static void enter_pmode(struct kvm_vcpu *vcpu)
1648 {
1649 unsigned long flags;
1650 struct vcpu_vmx *vmx = to_vmx(vcpu);
1651
1652 vmx->emulation_required = 1;
1653 vmx->rmode.vm86_active = 0;
1654
1655 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1656 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1657 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1658
1659 flags = vmcs_readl(GUEST_RFLAGS);
1660 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1661 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1662 vmcs_writel(GUEST_RFLAGS, flags);
1663
1664 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1665 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1666
1667 update_exception_bitmap(vcpu);
1668
1669 if (emulate_invalid_guest_state)
1670 return;
1671
1672 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1673 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1674 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1675 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1676
1677 vmcs_write16(GUEST_SS_SELECTOR, 0);
1678 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1679
1680 vmcs_write16(GUEST_CS_SELECTOR,
1681 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1682 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1683 }
1684
1685 static gva_t rmode_tss_base(struct kvm *kvm)
1686 {
1687 if (!kvm->arch.tss_addr) {
1688 struct kvm_memslots *slots;
1689 gfn_t base_gfn;
1690
1691 slots = kvm_memslots(kvm);
1692 base_gfn = slots->memslots[0].base_gfn +
1693 kvm->memslots->memslots[0].npages - 3;
1694 return base_gfn << PAGE_SHIFT;
1695 }
1696 return kvm->arch.tss_addr;
1697 }
1698
1699 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1700 {
1701 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1702
1703 save->selector = vmcs_read16(sf->selector);
1704 save->base = vmcs_readl(sf->base);
1705 save->limit = vmcs_read32(sf->limit);
1706 save->ar = vmcs_read32(sf->ar_bytes);
1707 vmcs_write16(sf->selector, save->base >> 4);
1708 vmcs_write32(sf->base, save->base & 0xfffff);
1709 vmcs_write32(sf->limit, 0xffff);
1710 vmcs_write32(sf->ar_bytes, 0xf3);
1711 }
1712
1713 static void enter_rmode(struct kvm_vcpu *vcpu)
1714 {
1715 unsigned long flags;
1716 struct vcpu_vmx *vmx = to_vmx(vcpu);
1717
1718 if (enable_unrestricted_guest)
1719 return;
1720
1721 vmx->emulation_required = 1;
1722 vmx->rmode.vm86_active = 1;
1723
1724 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1725 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1726
1727 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1728 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1729
1730 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1731 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1732
1733 flags = vmcs_readl(GUEST_RFLAGS);
1734 vmx->rmode.save_rflags = flags;
1735
1736 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1737
1738 vmcs_writel(GUEST_RFLAGS, flags);
1739 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1740 update_exception_bitmap(vcpu);
1741
1742 if (emulate_invalid_guest_state)
1743 goto continue_rmode;
1744
1745 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1746 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1747 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1748
1749 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1750 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1751 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1752 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1753 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1754
1755 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1756 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1757 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1758 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1759
1760 continue_rmode:
1761 kvm_mmu_reset_context(vcpu);
1762 init_rmode(vcpu->kvm);
1763 }
1764
1765 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1766 {
1767 struct vcpu_vmx *vmx = to_vmx(vcpu);
1768 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1769
1770 if (!msr)
1771 return;
1772
1773 /*
1774 * Force kernel_gs_base reloading before EFER changes, as control
1775 * of this msr depends on is_long_mode().
1776 */
1777 vmx_load_host_state(to_vmx(vcpu));
1778 vcpu->arch.efer = efer;
1779 if (efer & EFER_LMA) {
1780 vmcs_write32(VM_ENTRY_CONTROLS,
1781 vmcs_read32(VM_ENTRY_CONTROLS) |
1782 VM_ENTRY_IA32E_MODE);
1783 msr->data = efer;
1784 } else {
1785 vmcs_write32(VM_ENTRY_CONTROLS,
1786 vmcs_read32(VM_ENTRY_CONTROLS) &
1787 ~VM_ENTRY_IA32E_MODE);
1788
1789 msr->data = efer & ~EFER_LME;
1790 }
1791 setup_msrs(vmx);
1792 }
1793
1794 #ifdef CONFIG_X86_64
1795
1796 static void enter_lmode(struct kvm_vcpu *vcpu)
1797 {
1798 u32 guest_tr_ar;
1799
1800 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1801 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1802 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1803 __func__);
1804 vmcs_write32(GUEST_TR_AR_BYTES,
1805 (guest_tr_ar & ~AR_TYPE_MASK)
1806 | AR_TYPE_BUSY_64_TSS);
1807 }
1808 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
1809 }
1810
1811 static void exit_lmode(struct kvm_vcpu *vcpu)
1812 {
1813 vmcs_write32(VM_ENTRY_CONTROLS,
1814 vmcs_read32(VM_ENTRY_CONTROLS)
1815 & ~VM_ENTRY_IA32E_MODE);
1816 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
1817 }
1818
1819 #endif
1820
1821 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1822 {
1823 vpid_sync_context(to_vmx(vcpu));
1824 if (enable_ept) {
1825 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1826 return;
1827 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1828 }
1829 }
1830
1831 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1832 {
1833 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1834
1835 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1836 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1837 }
1838
1839 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1840 {
1841 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1842
1843 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1844 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1845 }
1846
1847 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1848 {
1849 if (!test_bit(VCPU_EXREG_PDPTR,
1850 (unsigned long *)&vcpu->arch.regs_dirty))
1851 return;
1852
1853 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1854 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1855 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1856 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1857 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1858 }
1859 }
1860
1861 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1862 {
1863 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1864 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1865 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1866 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1867 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1868 }
1869
1870 __set_bit(VCPU_EXREG_PDPTR,
1871 (unsigned long *)&vcpu->arch.regs_avail);
1872 __set_bit(VCPU_EXREG_PDPTR,
1873 (unsigned long *)&vcpu->arch.regs_dirty);
1874 }
1875
1876 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1877
1878 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1879 unsigned long cr0,
1880 struct kvm_vcpu *vcpu)
1881 {
1882 if (!(cr0 & X86_CR0_PG)) {
1883 /* From paging/starting to nonpaging */
1884 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1885 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1886 (CPU_BASED_CR3_LOAD_EXITING |
1887 CPU_BASED_CR3_STORE_EXITING));
1888 vcpu->arch.cr0 = cr0;
1889 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1890 } else if (!is_paging(vcpu)) {
1891 /* From nonpaging to paging */
1892 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1893 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1894 ~(CPU_BASED_CR3_LOAD_EXITING |
1895 CPU_BASED_CR3_STORE_EXITING));
1896 vcpu->arch.cr0 = cr0;
1897 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1898 }
1899
1900 if (!(cr0 & X86_CR0_WP))
1901 *hw_cr0 &= ~X86_CR0_WP;
1902 }
1903
1904 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1905 {
1906 struct vcpu_vmx *vmx = to_vmx(vcpu);
1907 unsigned long hw_cr0;
1908
1909 if (enable_unrestricted_guest)
1910 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1911 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1912 else
1913 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1914
1915 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1916 enter_pmode(vcpu);
1917
1918 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1919 enter_rmode(vcpu);
1920
1921 #ifdef CONFIG_X86_64
1922 if (vcpu->arch.efer & EFER_LME) {
1923 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1924 enter_lmode(vcpu);
1925 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1926 exit_lmode(vcpu);
1927 }
1928 #endif
1929
1930 if (enable_ept)
1931 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1932
1933 if (!vcpu->fpu_active)
1934 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1935
1936 vmcs_writel(CR0_READ_SHADOW, cr0);
1937 vmcs_writel(GUEST_CR0, hw_cr0);
1938 vcpu->arch.cr0 = cr0;
1939 }
1940
1941 static u64 construct_eptp(unsigned long root_hpa)
1942 {
1943 u64 eptp;
1944
1945 /* TODO write the value reading from MSR */
1946 eptp = VMX_EPT_DEFAULT_MT |
1947 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1948 eptp |= (root_hpa & PAGE_MASK);
1949
1950 return eptp;
1951 }
1952
1953 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1954 {
1955 unsigned long guest_cr3;
1956 u64 eptp;
1957
1958 guest_cr3 = cr3;
1959 if (enable_ept) {
1960 eptp = construct_eptp(cr3);
1961 vmcs_write64(EPT_POINTER, eptp);
1962 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1963 vcpu->kvm->arch.ept_identity_map_addr;
1964 ept_load_pdptrs(vcpu);
1965 }
1966
1967 vmx_flush_tlb(vcpu);
1968 vmcs_writel(GUEST_CR3, guest_cr3);
1969 }
1970
1971 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1972 {
1973 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1974 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1975
1976 vcpu->arch.cr4 = cr4;
1977 if (enable_ept) {
1978 if (!is_paging(vcpu)) {
1979 hw_cr4 &= ~X86_CR4_PAE;
1980 hw_cr4 |= X86_CR4_PSE;
1981 } else if (!(cr4 & X86_CR4_PAE)) {
1982 hw_cr4 &= ~X86_CR4_PAE;
1983 }
1984 }
1985
1986 vmcs_writel(CR4_READ_SHADOW, cr4);
1987 vmcs_writel(GUEST_CR4, hw_cr4);
1988 }
1989
1990 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1991 {
1992 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1993
1994 return vmcs_readl(sf->base);
1995 }
1996
1997 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1998 struct kvm_segment *var, int seg)
1999 {
2000 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2001 u32 ar;
2002
2003 var->base = vmcs_readl(sf->base);
2004 var->limit = vmcs_read32(sf->limit);
2005 var->selector = vmcs_read16(sf->selector);
2006 ar = vmcs_read32(sf->ar_bytes);
2007 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
2008 ar = 0;
2009 var->type = ar & 15;
2010 var->s = (ar >> 4) & 1;
2011 var->dpl = (ar >> 5) & 3;
2012 var->present = (ar >> 7) & 1;
2013 var->avl = (ar >> 12) & 1;
2014 var->l = (ar >> 13) & 1;
2015 var->db = (ar >> 14) & 1;
2016 var->g = (ar >> 15) & 1;
2017 var->unusable = (ar >> 16) & 1;
2018 }
2019
2020 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2021 {
2022 if (!is_protmode(vcpu))
2023 return 0;
2024
2025 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2026 return 3;
2027
2028 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2029 }
2030
2031 static u32 vmx_segment_access_rights(struct kvm_segment *var)
2032 {
2033 u32 ar;
2034
2035 if (var->unusable)
2036 ar = 1 << 16;
2037 else {
2038 ar = var->type & 15;
2039 ar |= (var->s & 1) << 4;
2040 ar |= (var->dpl & 3) << 5;
2041 ar |= (var->present & 1) << 7;
2042 ar |= (var->avl & 1) << 12;
2043 ar |= (var->l & 1) << 13;
2044 ar |= (var->db & 1) << 14;
2045 ar |= (var->g & 1) << 15;
2046 }
2047 if (ar == 0) /* a 0 value means unusable */
2048 ar = AR_UNUSABLE_MASK;
2049
2050 return ar;
2051 }
2052
2053 static void vmx_set_segment(struct kvm_vcpu *vcpu,
2054 struct kvm_segment *var, int seg)
2055 {
2056 struct vcpu_vmx *vmx = to_vmx(vcpu);
2057 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2058 u32 ar;
2059
2060 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2061 vmx->rmode.tr.selector = var->selector;
2062 vmx->rmode.tr.base = var->base;
2063 vmx->rmode.tr.limit = var->limit;
2064 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2065 return;
2066 }
2067 vmcs_writel(sf->base, var->base);
2068 vmcs_write32(sf->limit, var->limit);
2069 vmcs_write16(sf->selector, var->selector);
2070 if (vmx->rmode.vm86_active && var->s) {
2071 /*
2072 * Hack real-mode segments into vm86 compatibility.
2073 */
2074 if (var->base == 0xffff0000 && var->selector == 0xf000)
2075 vmcs_writel(sf->base, 0xf0000);
2076 ar = 0xf3;
2077 } else
2078 ar = vmx_segment_access_rights(var);
2079
2080 /*
2081 * Fix the "Accessed" bit in AR field of segment registers for older
2082 * qemu binaries.
2083 * IA32 arch specifies that at the time of processor reset the
2084 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2085 * is setting it to 0 in the usedland code. This causes invalid guest
2086 * state vmexit when "unrestricted guest" mode is turned on.
2087 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2088 * tree. Newer qemu binaries with that qemu fix would not need this
2089 * kvm hack.
2090 */
2091 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2092 ar |= 0x1; /* Accessed */
2093
2094 vmcs_write32(sf->ar_bytes, ar);
2095 }
2096
2097 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2098 {
2099 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2100
2101 *db = (ar >> 14) & 1;
2102 *l = (ar >> 13) & 1;
2103 }
2104
2105 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2106 {
2107 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2108 dt->address = vmcs_readl(GUEST_IDTR_BASE);
2109 }
2110
2111 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2112 {
2113 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2114 vmcs_writel(GUEST_IDTR_BASE, dt->address);
2115 }
2116
2117 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2118 {
2119 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2120 dt->address = vmcs_readl(GUEST_GDTR_BASE);
2121 }
2122
2123 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2124 {
2125 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2126 vmcs_writel(GUEST_GDTR_BASE, dt->address);
2127 }
2128
2129 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2130 {
2131 struct kvm_segment var;
2132 u32 ar;
2133
2134 vmx_get_segment(vcpu, &var, seg);
2135 ar = vmx_segment_access_rights(&var);
2136
2137 if (var.base != (var.selector << 4))
2138 return false;
2139 if (var.limit != 0xffff)
2140 return false;
2141 if (ar != 0xf3)
2142 return false;
2143
2144 return true;
2145 }
2146
2147 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2148 {
2149 struct kvm_segment cs;
2150 unsigned int cs_rpl;
2151
2152 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2153 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2154
2155 if (cs.unusable)
2156 return false;
2157 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2158 return false;
2159 if (!cs.s)
2160 return false;
2161 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2162 if (cs.dpl > cs_rpl)
2163 return false;
2164 } else {
2165 if (cs.dpl != cs_rpl)
2166 return false;
2167 }
2168 if (!cs.present)
2169 return false;
2170
2171 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2172 return true;
2173 }
2174
2175 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2176 {
2177 struct kvm_segment ss;
2178 unsigned int ss_rpl;
2179
2180 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2181 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2182
2183 if (ss.unusable)
2184 return true;
2185 if (ss.type != 3 && ss.type != 7)
2186 return false;
2187 if (!ss.s)
2188 return false;
2189 if (ss.dpl != ss_rpl) /* DPL != RPL */
2190 return false;
2191 if (!ss.present)
2192 return false;
2193
2194 return true;
2195 }
2196
2197 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2198 {
2199 struct kvm_segment var;
2200 unsigned int rpl;
2201
2202 vmx_get_segment(vcpu, &var, seg);
2203 rpl = var.selector & SELECTOR_RPL_MASK;
2204
2205 if (var.unusable)
2206 return true;
2207 if (!var.s)
2208 return false;
2209 if (!var.present)
2210 return false;
2211 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2212 if (var.dpl < rpl) /* DPL < RPL */
2213 return false;
2214 }
2215
2216 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2217 * rights flags
2218 */
2219 return true;
2220 }
2221
2222 static bool tr_valid(struct kvm_vcpu *vcpu)
2223 {
2224 struct kvm_segment tr;
2225
2226 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2227
2228 if (tr.unusable)
2229 return false;
2230 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2231 return false;
2232 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2233 return false;
2234 if (!tr.present)
2235 return false;
2236
2237 return true;
2238 }
2239
2240 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2241 {
2242 struct kvm_segment ldtr;
2243
2244 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2245
2246 if (ldtr.unusable)
2247 return true;
2248 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2249 return false;
2250 if (ldtr.type != 2)
2251 return false;
2252 if (!ldtr.present)
2253 return false;
2254
2255 return true;
2256 }
2257
2258 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2259 {
2260 struct kvm_segment cs, ss;
2261
2262 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2263 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2264
2265 return ((cs.selector & SELECTOR_RPL_MASK) ==
2266 (ss.selector & SELECTOR_RPL_MASK));
2267 }
2268
2269 /*
2270 * Check if guest state is valid. Returns true if valid, false if
2271 * not.
2272 * We assume that registers are always usable
2273 */
2274 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2275 {
2276 /* real mode guest state checks */
2277 if (!is_protmode(vcpu)) {
2278 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2279 return false;
2280 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2281 return false;
2282 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2283 return false;
2284 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2285 return false;
2286 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2287 return false;
2288 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2289 return false;
2290 } else {
2291 /* protected mode guest state checks */
2292 if (!cs_ss_rpl_check(vcpu))
2293 return false;
2294 if (!code_segment_valid(vcpu))
2295 return false;
2296 if (!stack_segment_valid(vcpu))
2297 return false;
2298 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2299 return false;
2300 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2301 return false;
2302 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2303 return false;
2304 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2305 return false;
2306 if (!tr_valid(vcpu))
2307 return false;
2308 if (!ldtr_valid(vcpu))
2309 return false;
2310 }
2311 /* TODO:
2312 * - Add checks on RIP
2313 * - Add checks on RFLAGS
2314 */
2315
2316 return true;
2317 }
2318
2319 static int init_rmode_tss(struct kvm *kvm)
2320 {
2321 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2322 u16 data = 0;
2323 int ret = 0;
2324 int r;
2325
2326 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2327 if (r < 0)
2328 goto out;
2329 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2330 r = kvm_write_guest_page(kvm, fn++, &data,
2331 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2332 if (r < 0)
2333 goto out;
2334 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2335 if (r < 0)
2336 goto out;
2337 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2338 if (r < 0)
2339 goto out;
2340 data = ~0;
2341 r = kvm_write_guest_page(kvm, fn, &data,
2342 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2343 sizeof(u8));
2344 if (r < 0)
2345 goto out;
2346
2347 ret = 1;
2348 out:
2349 return ret;
2350 }
2351
2352 static int init_rmode_identity_map(struct kvm *kvm)
2353 {
2354 int i, r, ret;
2355 pfn_t identity_map_pfn;
2356 u32 tmp;
2357
2358 if (!enable_ept)
2359 return 1;
2360 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2361 printk(KERN_ERR "EPT: identity-mapping pagetable "
2362 "haven't been allocated!\n");
2363 return 0;
2364 }
2365 if (likely(kvm->arch.ept_identity_pagetable_done))
2366 return 1;
2367 ret = 0;
2368 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2369 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2370 if (r < 0)
2371 goto out;
2372 /* Set up identity-mapping pagetable for EPT in real mode */
2373 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2374 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2375 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2376 r = kvm_write_guest_page(kvm, identity_map_pfn,
2377 &tmp, i * sizeof(tmp), sizeof(tmp));
2378 if (r < 0)
2379 goto out;
2380 }
2381 kvm->arch.ept_identity_pagetable_done = true;
2382 ret = 1;
2383 out:
2384 return ret;
2385 }
2386
2387 static void seg_setup(int seg)
2388 {
2389 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2390 unsigned int ar;
2391
2392 vmcs_write16(sf->selector, 0);
2393 vmcs_writel(sf->base, 0);
2394 vmcs_write32(sf->limit, 0xffff);
2395 if (enable_unrestricted_guest) {
2396 ar = 0x93;
2397 if (seg == VCPU_SREG_CS)
2398 ar |= 0x08; /* code segment */
2399 } else
2400 ar = 0xf3;
2401
2402 vmcs_write32(sf->ar_bytes, ar);
2403 }
2404
2405 static int alloc_apic_access_page(struct kvm *kvm)
2406 {
2407 struct kvm_userspace_memory_region kvm_userspace_mem;
2408 int r = 0;
2409
2410 mutex_lock(&kvm->slots_lock);
2411 if (kvm->arch.apic_access_page)
2412 goto out;
2413 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2414 kvm_userspace_mem.flags = 0;
2415 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2416 kvm_userspace_mem.memory_size = PAGE_SIZE;
2417 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2418 if (r)
2419 goto out;
2420
2421 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2422 out:
2423 mutex_unlock(&kvm->slots_lock);
2424 return r;
2425 }
2426
2427 static int alloc_identity_pagetable(struct kvm *kvm)
2428 {
2429 struct kvm_userspace_memory_region kvm_userspace_mem;
2430 int r = 0;
2431
2432 mutex_lock(&kvm->slots_lock);
2433 if (kvm->arch.ept_identity_pagetable)
2434 goto out;
2435 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2436 kvm_userspace_mem.flags = 0;
2437 kvm_userspace_mem.guest_phys_addr =
2438 kvm->arch.ept_identity_map_addr;
2439 kvm_userspace_mem.memory_size = PAGE_SIZE;
2440 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2441 if (r)
2442 goto out;
2443
2444 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2445 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2446 out:
2447 mutex_unlock(&kvm->slots_lock);
2448 return r;
2449 }
2450
2451 static void allocate_vpid(struct vcpu_vmx *vmx)
2452 {
2453 int vpid;
2454
2455 vmx->vpid = 0;
2456 if (!enable_vpid)
2457 return;
2458 spin_lock(&vmx_vpid_lock);
2459 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2460 if (vpid < VMX_NR_VPIDS) {
2461 vmx->vpid = vpid;
2462 __set_bit(vpid, vmx_vpid_bitmap);
2463 }
2464 spin_unlock(&vmx_vpid_lock);
2465 }
2466
2467 static void free_vpid(struct vcpu_vmx *vmx)
2468 {
2469 if (!enable_vpid)
2470 return;
2471 spin_lock(&vmx_vpid_lock);
2472 if (vmx->vpid != 0)
2473 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2474 spin_unlock(&vmx_vpid_lock);
2475 }
2476
2477 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2478 {
2479 int f = sizeof(unsigned long);
2480
2481 if (!cpu_has_vmx_msr_bitmap())
2482 return;
2483
2484 /*
2485 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2486 * have the write-low and read-high bitmap offsets the wrong way round.
2487 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2488 */
2489 if (msr <= 0x1fff) {
2490 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2491 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2492 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2493 msr &= 0x1fff;
2494 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2495 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2496 }
2497 }
2498
2499 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2500 {
2501 if (!longmode_only)
2502 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2503 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2504 }
2505
2506 /*
2507 * Sets up the vmcs for emulated real mode.
2508 */
2509 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2510 {
2511 u32 host_sysenter_cs, msr_low, msr_high;
2512 u32 junk;
2513 u64 host_pat;
2514 unsigned long a;
2515 struct desc_ptr dt;
2516 int i;
2517 unsigned long kvm_vmx_return;
2518 u32 exec_control;
2519
2520 /* I/O */
2521 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2522 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2523
2524 if (cpu_has_vmx_msr_bitmap())
2525 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2526
2527 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2528
2529 /* Control */
2530 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2531 vmcs_config.pin_based_exec_ctrl);
2532
2533 exec_control = vmcs_config.cpu_based_exec_ctrl;
2534 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2535 exec_control &= ~CPU_BASED_TPR_SHADOW;
2536 #ifdef CONFIG_X86_64
2537 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2538 CPU_BASED_CR8_LOAD_EXITING;
2539 #endif
2540 }
2541 if (!enable_ept)
2542 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2543 CPU_BASED_CR3_LOAD_EXITING |
2544 CPU_BASED_INVLPG_EXITING;
2545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2546
2547 if (cpu_has_secondary_exec_ctrls()) {
2548 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2549 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2550 exec_control &=
2551 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2552 if (vmx->vpid == 0)
2553 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2554 if (!enable_ept) {
2555 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2556 enable_unrestricted_guest = 0;
2557 }
2558 if (!enable_unrestricted_guest)
2559 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2560 if (!ple_gap)
2561 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2562 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2563 }
2564
2565 if (ple_gap) {
2566 vmcs_write32(PLE_GAP, ple_gap);
2567 vmcs_write32(PLE_WINDOW, ple_window);
2568 }
2569
2570 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2571 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2572 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2573
2574 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
2575 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2576 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2577
2578 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2579 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2580 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2581 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2582 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
2583 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2584 #ifdef CONFIG_X86_64
2585 rdmsrl(MSR_FS_BASE, a);
2586 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2587 rdmsrl(MSR_GS_BASE, a);
2588 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2589 #else
2590 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2591 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2592 #endif
2593
2594 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2595
2596 native_store_idt(&dt);
2597 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
2598
2599 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2600 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2601 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2602 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2603 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2604 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2605 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2606
2607 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2608 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2609 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2610 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2611 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2612 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2613
2614 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2615 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2616 host_pat = msr_low | ((u64) msr_high << 32);
2617 vmcs_write64(HOST_IA32_PAT, host_pat);
2618 }
2619 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2620 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2621 host_pat = msr_low | ((u64) msr_high << 32);
2622 /* Write the default value follow host pat */
2623 vmcs_write64(GUEST_IA32_PAT, host_pat);
2624 /* Keep arch.pat sync with GUEST_IA32_PAT */
2625 vmx->vcpu.arch.pat = host_pat;
2626 }
2627
2628 for (i = 0; i < NR_VMX_MSR; ++i) {
2629 u32 index = vmx_msr_index[i];
2630 u32 data_low, data_high;
2631 int j = vmx->nmsrs;
2632
2633 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2634 continue;
2635 if (wrmsr_safe(index, data_low, data_high) < 0)
2636 continue;
2637 vmx->guest_msrs[j].index = i;
2638 vmx->guest_msrs[j].data = 0;
2639 vmx->guest_msrs[j].mask = -1ull;
2640 ++vmx->nmsrs;
2641 }
2642
2643 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2644
2645 /* 22.2.1, 20.8.1 */
2646 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2647
2648 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2649 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2650 if (enable_ept)
2651 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2652 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2653
2654 kvm_write_tsc(&vmx->vcpu, 0);
2655
2656 return 0;
2657 }
2658
2659 static int init_rmode(struct kvm *kvm)
2660 {
2661 int idx, ret = 0;
2662
2663 idx = srcu_read_lock(&kvm->srcu);
2664 if (!init_rmode_tss(kvm))
2665 goto exit;
2666 if (!init_rmode_identity_map(kvm))
2667 goto exit;
2668
2669 ret = 1;
2670 exit:
2671 srcu_read_unlock(&kvm->srcu, idx);
2672 return ret;
2673 }
2674
2675 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2676 {
2677 struct vcpu_vmx *vmx = to_vmx(vcpu);
2678 u64 msr;
2679 int ret;
2680
2681 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2682 if (!init_rmode(vmx->vcpu.kvm)) {
2683 ret = -ENOMEM;
2684 goto out;
2685 }
2686
2687 vmx->rmode.vm86_active = 0;
2688
2689 vmx->soft_vnmi_blocked = 0;
2690
2691 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2692 kvm_set_cr8(&vmx->vcpu, 0);
2693 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2694 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2695 msr |= MSR_IA32_APICBASE_BSP;
2696 kvm_set_apic_base(&vmx->vcpu, msr);
2697
2698 ret = fx_init(&vmx->vcpu);
2699 if (ret != 0)
2700 goto out;
2701
2702 seg_setup(VCPU_SREG_CS);
2703 /*
2704 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2705 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2706 */
2707 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2708 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2709 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2710 } else {
2711 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2712 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2713 }
2714
2715 seg_setup(VCPU_SREG_DS);
2716 seg_setup(VCPU_SREG_ES);
2717 seg_setup(VCPU_SREG_FS);
2718 seg_setup(VCPU_SREG_GS);
2719 seg_setup(VCPU_SREG_SS);
2720
2721 vmcs_write16(GUEST_TR_SELECTOR, 0);
2722 vmcs_writel(GUEST_TR_BASE, 0);
2723 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2724 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2725
2726 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2727 vmcs_writel(GUEST_LDTR_BASE, 0);
2728 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2729 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2730
2731 vmcs_write32(GUEST_SYSENTER_CS, 0);
2732 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2733 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2734
2735 vmcs_writel(GUEST_RFLAGS, 0x02);
2736 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2737 kvm_rip_write(vcpu, 0xfff0);
2738 else
2739 kvm_rip_write(vcpu, 0);
2740 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2741
2742 vmcs_writel(GUEST_DR7, 0x400);
2743
2744 vmcs_writel(GUEST_GDTR_BASE, 0);
2745 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2746
2747 vmcs_writel(GUEST_IDTR_BASE, 0);
2748 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2749
2750 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
2751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2752 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2753
2754 /* Special registers */
2755 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2756
2757 setup_msrs(vmx);
2758
2759 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2760
2761 if (cpu_has_vmx_tpr_shadow()) {
2762 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2763 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2764 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2765 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2766 vmcs_write32(TPR_THRESHOLD, 0);
2767 }
2768
2769 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2770 vmcs_write64(APIC_ACCESS_ADDR,
2771 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2772
2773 if (vmx->vpid != 0)
2774 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2775
2776 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2777 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2778 vmx_set_cr4(&vmx->vcpu, 0);
2779 vmx_set_efer(&vmx->vcpu, 0);
2780 vmx_fpu_activate(&vmx->vcpu);
2781 update_exception_bitmap(&vmx->vcpu);
2782
2783 vpid_sync_context(vmx);
2784
2785 ret = 0;
2786
2787 /* HACK: Don't enable emulation on guest boot/reset */
2788 vmx->emulation_required = 0;
2789
2790 out:
2791 return ret;
2792 }
2793
2794 static void enable_irq_window(struct kvm_vcpu *vcpu)
2795 {
2796 u32 cpu_based_vm_exec_control;
2797
2798 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2799 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2800 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2801 }
2802
2803 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2804 {
2805 u32 cpu_based_vm_exec_control;
2806
2807 if (!cpu_has_virtual_nmis()) {
2808 enable_irq_window(vcpu);
2809 return;
2810 }
2811
2812 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2813 enable_irq_window(vcpu);
2814 return;
2815 }
2816 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2817 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2818 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2819 }
2820
2821 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2822 {
2823 struct vcpu_vmx *vmx = to_vmx(vcpu);
2824 uint32_t intr;
2825 int irq = vcpu->arch.interrupt.nr;
2826
2827 trace_kvm_inj_virq(irq);
2828
2829 ++vcpu->stat.irq_injections;
2830 if (vmx->rmode.vm86_active) {
2831 if (kvm_inject_realmode_interrupt(vcpu, irq) != EMULATE_DONE)
2832 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2833 return;
2834 }
2835 intr = irq | INTR_INFO_VALID_MASK;
2836 if (vcpu->arch.interrupt.soft) {
2837 intr |= INTR_TYPE_SOFT_INTR;
2838 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2839 vmx->vcpu.arch.event_exit_inst_len);
2840 } else
2841 intr |= INTR_TYPE_EXT_INTR;
2842 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2843 vmx_clear_hlt(vcpu);
2844 }
2845
2846 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2847 {
2848 struct vcpu_vmx *vmx = to_vmx(vcpu);
2849
2850 if (!cpu_has_virtual_nmis()) {
2851 /*
2852 * Tracking the NMI-blocked state in software is built upon
2853 * finding the next open IRQ window. This, in turn, depends on
2854 * well-behaving guests: They have to keep IRQs disabled at
2855 * least as long as the NMI handler runs. Otherwise we may
2856 * cause NMI nesting, maybe breaking the guest. But as this is
2857 * highly unlikely, we can live with the residual risk.
2858 */
2859 vmx->soft_vnmi_blocked = 1;
2860 vmx->vnmi_blocked_time = 0;
2861 }
2862
2863 ++vcpu->stat.nmi_injections;
2864 if (vmx->rmode.vm86_active) {
2865 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR) != EMULATE_DONE)
2866 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2867 return;
2868 }
2869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2870 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2871 vmx_clear_hlt(vcpu);
2872 }
2873
2874 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2875 {
2876 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2877 return 0;
2878
2879 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2880 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
2881 | GUEST_INTR_STATE_NMI));
2882 }
2883
2884 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2885 {
2886 if (!cpu_has_virtual_nmis())
2887 return to_vmx(vcpu)->soft_vnmi_blocked;
2888 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
2889 }
2890
2891 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2892 {
2893 struct vcpu_vmx *vmx = to_vmx(vcpu);
2894
2895 if (!cpu_has_virtual_nmis()) {
2896 if (vmx->soft_vnmi_blocked != masked) {
2897 vmx->soft_vnmi_blocked = masked;
2898 vmx->vnmi_blocked_time = 0;
2899 }
2900 } else {
2901 if (masked)
2902 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2903 GUEST_INTR_STATE_NMI);
2904 else
2905 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2906 GUEST_INTR_STATE_NMI);
2907 }
2908 }
2909
2910 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2911 {
2912 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2913 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2914 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2915 }
2916
2917 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2918 {
2919 int ret;
2920 struct kvm_userspace_memory_region tss_mem = {
2921 .slot = TSS_PRIVATE_MEMSLOT,
2922 .guest_phys_addr = addr,
2923 .memory_size = PAGE_SIZE * 3,
2924 .flags = 0,
2925 };
2926
2927 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2928 if (ret)
2929 return ret;
2930 kvm->arch.tss_addr = addr;
2931 return 0;
2932 }
2933
2934 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2935 int vec, u32 err_code)
2936 {
2937 /*
2938 * Instruction with address size override prefix opcode 0x67
2939 * Cause the #SS fault with 0 error code in VM86 mode.
2940 */
2941 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2942 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2943 return 1;
2944 /*
2945 * Forward all other exceptions that are valid in real mode.
2946 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2947 * the required debugging infrastructure rework.
2948 */
2949 switch (vec) {
2950 case DB_VECTOR:
2951 if (vcpu->guest_debug &
2952 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2953 return 0;
2954 kvm_queue_exception(vcpu, vec);
2955 return 1;
2956 case BP_VECTOR:
2957 /*
2958 * Update instruction length as we may reinject the exception
2959 * from user space while in guest debugging mode.
2960 */
2961 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2962 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2963 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2964 return 0;
2965 /* fall through */
2966 case DE_VECTOR:
2967 case OF_VECTOR:
2968 case BR_VECTOR:
2969 case UD_VECTOR:
2970 case DF_VECTOR:
2971 case SS_VECTOR:
2972 case GP_VECTOR:
2973 case MF_VECTOR:
2974 kvm_queue_exception(vcpu, vec);
2975 return 1;
2976 }
2977 return 0;
2978 }
2979
2980 /*
2981 * Trigger machine check on the host. We assume all the MSRs are already set up
2982 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2983 * We pass a fake environment to the machine check handler because we want
2984 * the guest to be always treated like user space, no matter what context
2985 * it used internally.
2986 */
2987 static void kvm_machine_check(void)
2988 {
2989 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2990 struct pt_regs regs = {
2991 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2992 .flags = X86_EFLAGS_IF,
2993 };
2994
2995 do_machine_check(&regs, 0);
2996 #endif
2997 }
2998
2999 static int handle_machine_check(struct kvm_vcpu *vcpu)
3000 {
3001 /* already handled by vcpu_run */
3002 return 1;
3003 }
3004
3005 static int handle_exception(struct kvm_vcpu *vcpu)
3006 {
3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
3008 struct kvm_run *kvm_run = vcpu->run;
3009 u32 intr_info, ex_no, error_code;
3010 unsigned long cr2, rip, dr6;
3011 u32 vect_info;
3012 enum emulation_result er;
3013
3014 vect_info = vmx->idt_vectoring_info;
3015 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3016
3017 if (is_machine_check(intr_info))
3018 return handle_machine_check(vcpu);
3019
3020 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
3021 !is_page_fault(intr_info)) {
3022 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3023 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3024 vcpu->run->internal.ndata = 2;
3025 vcpu->run->internal.data[0] = vect_info;
3026 vcpu->run->internal.data[1] = intr_info;
3027 return 0;
3028 }
3029
3030 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
3031 return 1; /* already handled by vmx_vcpu_run() */
3032
3033 if (is_no_device(intr_info)) {
3034 vmx_fpu_activate(vcpu);
3035 return 1;
3036 }
3037
3038 if (is_invalid_opcode(intr_info)) {
3039 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
3040 if (er != EMULATE_DONE)
3041 kvm_queue_exception(vcpu, UD_VECTOR);
3042 return 1;
3043 }
3044
3045 error_code = 0;
3046 rip = kvm_rip_read(vcpu);
3047 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
3048 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3049 if (is_page_fault(intr_info)) {
3050 /* EPT won't cause page fault directly */
3051 if (enable_ept)
3052 BUG();
3053 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3054 trace_kvm_page_fault(cr2, error_code);
3055
3056 if (kvm_event_needs_reinjection(vcpu))
3057 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3058 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3059 }
3060
3061 if (vmx->rmode.vm86_active &&
3062 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3063 error_code)) {
3064 if (vcpu->arch.halt_request) {
3065 vcpu->arch.halt_request = 0;
3066 return kvm_emulate_halt(vcpu);
3067 }
3068 return 1;
3069 }
3070
3071 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3072 switch (ex_no) {
3073 case DB_VECTOR:
3074 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3075 if (!(vcpu->guest_debug &
3076 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3077 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3078 kvm_queue_exception(vcpu, DB_VECTOR);
3079 return 1;
3080 }
3081 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3082 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3083 /* fall through */
3084 case BP_VECTOR:
3085 /*
3086 * Update instruction length as we may reinject #BP from
3087 * user space while in guest debugging mode. Reading it for
3088 * #DB as well causes no harm, it is not used in that case.
3089 */
3090 vmx->vcpu.arch.event_exit_inst_len =
3091 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3092 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3093 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3094 kvm_run->debug.arch.exception = ex_no;
3095 break;
3096 default:
3097 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3098 kvm_run->ex.exception = ex_no;
3099 kvm_run->ex.error_code = error_code;
3100 break;
3101 }
3102 return 0;
3103 }
3104
3105 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3106 {
3107 ++vcpu->stat.irq_exits;
3108 return 1;
3109 }
3110
3111 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3112 {
3113 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3114 return 0;
3115 }
3116
3117 static int handle_io(struct kvm_vcpu *vcpu)
3118 {
3119 unsigned long exit_qualification;
3120 int size, in, string;
3121 unsigned port;
3122
3123 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3124 string = (exit_qualification & 16) != 0;
3125 in = (exit_qualification & 8) != 0;
3126
3127 ++vcpu->stat.io_exits;
3128
3129 if (string || in)
3130 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3131
3132 port = exit_qualification >> 16;
3133 size = (exit_qualification & 7) + 1;
3134 skip_emulated_instruction(vcpu);
3135
3136 return kvm_fast_pio_out(vcpu, size, port);
3137 }
3138
3139 static void
3140 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3141 {
3142 /*
3143 * Patch in the VMCALL instruction:
3144 */
3145 hypercall[0] = 0x0f;
3146 hypercall[1] = 0x01;
3147 hypercall[2] = 0xc1;
3148 }
3149
3150 static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3151 {
3152 if (err)
3153 kvm_inject_gp(vcpu, 0);
3154 else
3155 skip_emulated_instruction(vcpu);
3156 }
3157
3158 static int handle_cr(struct kvm_vcpu *vcpu)
3159 {
3160 unsigned long exit_qualification, val;
3161 int cr;
3162 int reg;
3163 int err;
3164
3165 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3166 cr = exit_qualification & 15;
3167 reg = (exit_qualification >> 8) & 15;
3168 switch ((exit_qualification >> 4) & 3) {
3169 case 0: /* mov to cr */
3170 val = kvm_register_read(vcpu, reg);
3171 trace_kvm_cr_write(cr, val);
3172 switch (cr) {
3173 case 0:
3174 err = kvm_set_cr0(vcpu, val);
3175 complete_insn_gp(vcpu, err);
3176 return 1;
3177 case 3:
3178 err = kvm_set_cr3(vcpu, val);
3179 complete_insn_gp(vcpu, err);
3180 return 1;
3181 case 4:
3182 err = kvm_set_cr4(vcpu, val);
3183 complete_insn_gp(vcpu, err);
3184 return 1;
3185 case 8: {
3186 u8 cr8_prev = kvm_get_cr8(vcpu);
3187 u8 cr8 = kvm_register_read(vcpu, reg);
3188 err = kvm_set_cr8(vcpu, cr8);
3189 complete_insn_gp(vcpu, err);
3190 if (irqchip_in_kernel(vcpu->kvm))
3191 return 1;
3192 if (cr8_prev <= cr8)
3193 return 1;
3194 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3195 return 0;
3196 }
3197 };
3198 break;
3199 case 2: /* clts */
3200 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3201 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3202 skip_emulated_instruction(vcpu);
3203 vmx_fpu_activate(vcpu);
3204 return 1;
3205 case 1: /*mov from cr*/
3206 switch (cr) {
3207 case 3:
3208 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3209 trace_kvm_cr_read(cr, vcpu->arch.cr3);
3210 skip_emulated_instruction(vcpu);
3211 return 1;
3212 case 8:
3213 val = kvm_get_cr8(vcpu);
3214 kvm_register_write(vcpu, reg, val);
3215 trace_kvm_cr_read(cr, val);
3216 skip_emulated_instruction(vcpu);
3217 return 1;
3218 }
3219 break;
3220 case 3: /* lmsw */
3221 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3222 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3223 kvm_lmsw(vcpu, val);
3224
3225 skip_emulated_instruction(vcpu);
3226 return 1;
3227 default:
3228 break;
3229 }
3230 vcpu->run->exit_reason = 0;
3231 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3232 (int)(exit_qualification >> 4) & 3, cr);
3233 return 0;
3234 }
3235
3236 static int handle_dr(struct kvm_vcpu *vcpu)
3237 {
3238 unsigned long exit_qualification;
3239 int dr, reg;
3240
3241 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3242 if (!kvm_require_cpl(vcpu, 0))
3243 return 1;
3244 dr = vmcs_readl(GUEST_DR7);
3245 if (dr & DR7_GD) {
3246 /*
3247 * As the vm-exit takes precedence over the debug trap, we
3248 * need to emulate the latter, either for the host or the
3249 * guest debugging itself.
3250 */
3251 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3252 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3253 vcpu->run->debug.arch.dr7 = dr;
3254 vcpu->run->debug.arch.pc =
3255 vmcs_readl(GUEST_CS_BASE) +
3256 vmcs_readl(GUEST_RIP);
3257 vcpu->run->debug.arch.exception = DB_VECTOR;
3258 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3259 return 0;
3260 } else {
3261 vcpu->arch.dr7 &= ~DR7_GD;
3262 vcpu->arch.dr6 |= DR6_BD;
3263 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3264 kvm_queue_exception(vcpu, DB_VECTOR);
3265 return 1;
3266 }
3267 }
3268
3269 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3270 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3271 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3272 if (exit_qualification & TYPE_MOV_FROM_DR) {
3273 unsigned long val;
3274 if (!kvm_get_dr(vcpu, dr, &val))
3275 kvm_register_write(vcpu, reg, val);
3276 } else
3277 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3278 skip_emulated_instruction(vcpu);
3279 return 1;
3280 }
3281
3282 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3283 {
3284 vmcs_writel(GUEST_DR7, val);
3285 }
3286
3287 static int handle_cpuid(struct kvm_vcpu *vcpu)
3288 {
3289 kvm_emulate_cpuid(vcpu);
3290 return 1;
3291 }
3292
3293 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3294 {
3295 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3296 u64 data;
3297
3298 if (vmx_get_msr(vcpu, ecx, &data)) {
3299 trace_kvm_msr_read_ex(ecx);
3300 kvm_inject_gp(vcpu, 0);
3301 return 1;
3302 }
3303
3304 trace_kvm_msr_read(ecx, data);
3305
3306 /* FIXME: handling of bits 32:63 of rax, rdx */
3307 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3308 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3309 skip_emulated_instruction(vcpu);
3310 return 1;
3311 }
3312
3313 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3314 {
3315 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3316 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3317 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3318
3319 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3320 trace_kvm_msr_write_ex(ecx, data);
3321 kvm_inject_gp(vcpu, 0);
3322 return 1;
3323 }
3324
3325 trace_kvm_msr_write(ecx, data);
3326 skip_emulated_instruction(vcpu);
3327 return 1;
3328 }
3329
3330 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3331 {
3332 kvm_make_request(KVM_REQ_EVENT, vcpu);
3333 return 1;
3334 }
3335
3336 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3337 {
3338 u32 cpu_based_vm_exec_control;
3339
3340 /* clear pending irq */
3341 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3342 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3344
3345 kvm_make_request(KVM_REQ_EVENT, vcpu);
3346
3347 ++vcpu->stat.irq_window_exits;
3348
3349 /*
3350 * If the user space waits to inject interrupts, exit as soon as
3351 * possible
3352 */
3353 if (!irqchip_in_kernel(vcpu->kvm) &&
3354 vcpu->run->request_interrupt_window &&
3355 !kvm_cpu_has_interrupt(vcpu)) {
3356 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3357 return 0;
3358 }
3359 return 1;
3360 }
3361
3362 static int handle_halt(struct kvm_vcpu *vcpu)
3363 {
3364 skip_emulated_instruction(vcpu);
3365 return kvm_emulate_halt(vcpu);
3366 }
3367
3368 static int handle_vmcall(struct kvm_vcpu *vcpu)
3369 {
3370 skip_emulated_instruction(vcpu);
3371 kvm_emulate_hypercall(vcpu);
3372 return 1;
3373 }
3374
3375 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3376 {
3377 kvm_queue_exception(vcpu, UD_VECTOR);
3378 return 1;
3379 }
3380
3381 static int handle_invd(struct kvm_vcpu *vcpu)
3382 {
3383 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3384 }
3385
3386 static int handle_invlpg(struct kvm_vcpu *vcpu)
3387 {
3388 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3389
3390 kvm_mmu_invlpg(vcpu, exit_qualification);
3391 skip_emulated_instruction(vcpu);
3392 return 1;
3393 }
3394
3395 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3396 {
3397 skip_emulated_instruction(vcpu);
3398 kvm_emulate_wbinvd(vcpu);
3399 return 1;
3400 }
3401
3402 static int handle_xsetbv(struct kvm_vcpu *vcpu)
3403 {
3404 u64 new_bv = kvm_read_edx_eax(vcpu);
3405 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3406
3407 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3408 skip_emulated_instruction(vcpu);
3409 return 1;
3410 }
3411
3412 static int handle_apic_access(struct kvm_vcpu *vcpu)
3413 {
3414 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
3415 }
3416
3417 static int handle_task_switch(struct kvm_vcpu *vcpu)
3418 {
3419 struct vcpu_vmx *vmx = to_vmx(vcpu);
3420 unsigned long exit_qualification;
3421 bool has_error_code = false;
3422 u32 error_code = 0;
3423 u16 tss_selector;
3424 int reason, type, idt_v;
3425
3426 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3427 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3428
3429 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3430
3431 reason = (u32)exit_qualification >> 30;
3432 if (reason == TASK_SWITCH_GATE && idt_v) {
3433 switch (type) {
3434 case INTR_TYPE_NMI_INTR:
3435 vcpu->arch.nmi_injected = false;
3436 if (cpu_has_virtual_nmis())
3437 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3438 GUEST_INTR_STATE_NMI);
3439 break;
3440 case INTR_TYPE_EXT_INTR:
3441 case INTR_TYPE_SOFT_INTR:
3442 kvm_clear_interrupt_queue(vcpu);
3443 break;
3444 case INTR_TYPE_HARD_EXCEPTION:
3445 if (vmx->idt_vectoring_info &
3446 VECTORING_INFO_DELIVER_CODE_MASK) {
3447 has_error_code = true;
3448 error_code =
3449 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3450 }
3451 /* fall through */
3452 case INTR_TYPE_SOFT_EXCEPTION:
3453 kvm_clear_exception_queue(vcpu);
3454 break;
3455 default:
3456 break;
3457 }
3458 }
3459 tss_selector = exit_qualification;
3460
3461 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3462 type != INTR_TYPE_EXT_INTR &&
3463 type != INTR_TYPE_NMI_INTR))
3464 skip_emulated_instruction(vcpu);
3465
3466 if (kvm_task_switch(vcpu, tss_selector, reason,
3467 has_error_code, error_code) == EMULATE_FAIL) {
3468 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3469 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3470 vcpu->run->internal.ndata = 0;
3471 return 0;
3472 }
3473
3474 /* clear all local breakpoint enable flags */
3475 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3476
3477 /*
3478 * TODO: What about debug traps on tss switch?
3479 * Are we supposed to inject them and update dr6?
3480 */
3481
3482 return 1;
3483 }
3484
3485 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3486 {
3487 unsigned long exit_qualification;
3488 gpa_t gpa;
3489 int gla_validity;
3490
3491 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3492
3493 if (exit_qualification & (1 << 6)) {
3494 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3495 return -EINVAL;
3496 }
3497
3498 gla_validity = (exit_qualification >> 7) & 0x3;
3499 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3500 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3501 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3502 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3503 vmcs_readl(GUEST_LINEAR_ADDRESS));
3504 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3505 (long unsigned int)exit_qualification);
3506 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3507 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3508 return 0;
3509 }
3510
3511 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3512 trace_kvm_page_fault(gpa, exit_qualification);
3513 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3);
3514 }
3515
3516 static u64 ept_rsvd_mask(u64 spte, int level)
3517 {
3518 int i;
3519 u64 mask = 0;
3520
3521 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3522 mask |= (1ULL << i);
3523
3524 if (level > 2)
3525 /* bits 7:3 reserved */
3526 mask |= 0xf8;
3527 else if (level == 2) {
3528 if (spte & (1ULL << 7))
3529 /* 2MB ref, bits 20:12 reserved */
3530 mask |= 0x1ff000;
3531 else
3532 /* bits 6:3 reserved */
3533 mask |= 0x78;
3534 }
3535
3536 return mask;
3537 }
3538
3539 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3540 int level)
3541 {
3542 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3543
3544 /* 010b (write-only) */
3545 WARN_ON((spte & 0x7) == 0x2);
3546
3547 /* 110b (write/execute) */
3548 WARN_ON((spte & 0x7) == 0x6);
3549
3550 /* 100b (execute-only) and value not supported by logical processor */
3551 if (!cpu_has_vmx_ept_execute_only())
3552 WARN_ON((spte & 0x7) == 0x4);
3553
3554 /* not 000b */
3555 if ((spte & 0x7)) {
3556 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3557
3558 if (rsvd_bits != 0) {
3559 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3560 __func__, rsvd_bits);
3561 WARN_ON(1);
3562 }
3563
3564 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3565 u64 ept_mem_type = (spte & 0x38) >> 3;
3566
3567 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3568 ept_mem_type == 7) {
3569 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3570 __func__, ept_mem_type);
3571 WARN_ON(1);
3572 }
3573 }
3574 }
3575 }
3576
3577 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3578 {
3579 u64 sptes[4];
3580 int nr_sptes, i;
3581 gpa_t gpa;
3582
3583 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3584
3585 printk(KERN_ERR "EPT: Misconfiguration.\n");
3586 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3587
3588 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3589
3590 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3591 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3592
3593 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3594 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3595
3596 return 0;
3597 }
3598
3599 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3600 {
3601 u32 cpu_based_vm_exec_control;
3602
3603 /* clear pending NMI */
3604 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3605 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3606 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3607 ++vcpu->stat.nmi_window_exits;
3608 kvm_make_request(KVM_REQ_EVENT, vcpu);
3609
3610 return 1;
3611 }
3612
3613 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3614 {
3615 struct vcpu_vmx *vmx = to_vmx(vcpu);
3616 enum emulation_result err = EMULATE_DONE;
3617 int ret = 1;
3618 u32 cpu_exec_ctrl;
3619 bool intr_window_requested;
3620
3621 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3622 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
3623
3624 while (!guest_state_valid(vcpu)) {
3625 if (intr_window_requested
3626 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3627 return handle_interrupt_window(&vmx->vcpu);
3628
3629 err = emulate_instruction(vcpu, 0, 0, 0);
3630
3631 if (err == EMULATE_DO_MMIO) {
3632 ret = 0;
3633 goto out;
3634 }
3635
3636 if (err != EMULATE_DONE)
3637 return 0;
3638
3639 if (signal_pending(current))
3640 goto out;
3641 if (need_resched())
3642 schedule();
3643 }
3644
3645 vmx->emulation_required = 0;
3646 out:
3647 return ret;
3648 }
3649
3650 /*
3651 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3652 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3653 */
3654 static int handle_pause(struct kvm_vcpu *vcpu)
3655 {
3656 skip_emulated_instruction(vcpu);
3657 kvm_vcpu_on_spin(vcpu);
3658
3659 return 1;
3660 }
3661
3662 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3663 {
3664 kvm_queue_exception(vcpu, UD_VECTOR);
3665 return 1;
3666 }
3667
3668 /*
3669 * The exit handlers return 1 if the exit was handled fully and guest execution
3670 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3671 * to be done to userspace and return 0.
3672 */
3673 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3674 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3675 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3676 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3677 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3678 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3679 [EXIT_REASON_CR_ACCESS] = handle_cr,
3680 [EXIT_REASON_DR_ACCESS] = handle_dr,
3681 [EXIT_REASON_CPUID] = handle_cpuid,
3682 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3683 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3684 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3685 [EXIT_REASON_HLT] = handle_halt,
3686 [EXIT_REASON_INVD] = handle_invd,
3687 [EXIT_REASON_INVLPG] = handle_invlpg,
3688 [EXIT_REASON_VMCALL] = handle_vmcall,
3689 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3690 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3691 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3692 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3693 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3694 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3695 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3696 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3697 [EXIT_REASON_VMON] = handle_vmx_insn,
3698 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3699 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3700 [EXIT_REASON_WBINVD] = handle_wbinvd,
3701 [EXIT_REASON_XSETBV] = handle_xsetbv,
3702 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3703 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3704 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3705 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3706 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
3707 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3708 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
3709 };
3710
3711 static const int kvm_vmx_max_exit_handlers =
3712 ARRAY_SIZE(kvm_vmx_exit_handlers);
3713
3714 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3715 {
3716 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3717 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3718 }
3719
3720 /*
3721 * The guest has exited. See if we can fix it or if we need userspace
3722 * assistance.
3723 */
3724 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3725 {
3726 struct vcpu_vmx *vmx = to_vmx(vcpu);
3727 u32 exit_reason = vmx->exit_reason;
3728 u32 vectoring_info = vmx->idt_vectoring_info;
3729
3730 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
3731
3732 /* If guest state is invalid, start emulating */
3733 if (vmx->emulation_required && emulate_invalid_guest_state)
3734 return handle_invalid_guest_state(vcpu);
3735
3736 /* Access CR3 don't cause VMExit in paging mode, so we need
3737 * to sync with guest real CR3. */
3738 if (enable_ept && is_paging(vcpu))
3739 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3740
3741 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3742 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3743 vcpu->run->fail_entry.hardware_entry_failure_reason
3744 = exit_reason;
3745 return 0;
3746 }
3747
3748 if (unlikely(vmx->fail)) {
3749 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3750 vcpu->run->fail_entry.hardware_entry_failure_reason
3751 = vmcs_read32(VM_INSTRUCTION_ERROR);
3752 return 0;
3753 }
3754
3755 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3756 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3757 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3758 exit_reason != EXIT_REASON_TASK_SWITCH))
3759 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3760 "(0x%x) and exit reason is 0x%x\n",
3761 __func__, vectoring_info, exit_reason);
3762
3763 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3764 if (vmx_interrupt_allowed(vcpu)) {
3765 vmx->soft_vnmi_blocked = 0;
3766 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3767 vcpu->arch.nmi_pending) {
3768 /*
3769 * This CPU don't support us in finding the end of an
3770 * NMI-blocked window if the guest runs with IRQs
3771 * disabled. So we pull the trigger after 1 s of
3772 * futile waiting, but inform the user about this.
3773 */
3774 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3775 "state on VCPU %d after 1 s timeout\n",
3776 __func__, vcpu->vcpu_id);
3777 vmx->soft_vnmi_blocked = 0;
3778 }
3779 }
3780
3781 if (exit_reason < kvm_vmx_max_exit_handlers
3782 && kvm_vmx_exit_handlers[exit_reason])
3783 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3784 else {
3785 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3786 vcpu->run->hw.hardware_exit_reason = exit_reason;
3787 }
3788 return 0;
3789 }
3790
3791 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3792 {
3793 if (irr == -1 || tpr < irr) {
3794 vmcs_write32(TPR_THRESHOLD, 0);
3795 return;
3796 }
3797
3798 vmcs_write32(TPR_THRESHOLD, irr);
3799 }
3800
3801 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
3802 {
3803 u32 exit_intr_info = vmx->exit_intr_info;
3804
3805 /* Handle machine checks before interrupts are enabled */
3806 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3807 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3808 && is_machine_check(exit_intr_info)))
3809 kvm_machine_check();
3810
3811 /* We need to handle NMIs before interrupts are enabled */
3812 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3813 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3814 kvm_before_handle_nmi(&vmx->vcpu);
3815 asm("int $2");
3816 kvm_after_handle_nmi(&vmx->vcpu);
3817 }
3818 }
3819
3820 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3821 {
3822 u32 exit_intr_info = vmx->exit_intr_info;
3823 bool unblock_nmi;
3824 u8 vector;
3825 bool idtv_info_valid;
3826
3827 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3828
3829 if (cpu_has_virtual_nmis()) {
3830 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3831 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3832 /*
3833 * SDM 3: 27.7.1.2 (September 2008)
3834 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3835 * a guest IRET fault.
3836 * SDM 3: 23.2.2 (September 2008)
3837 * Bit 12 is undefined in any of the following cases:
3838 * If the VM exit sets the valid bit in the IDT-vectoring
3839 * information field.
3840 * If the VM exit is due to a double fault.
3841 */
3842 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3843 vector != DF_VECTOR && !idtv_info_valid)
3844 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3845 GUEST_INTR_STATE_NMI);
3846 } else if (unlikely(vmx->soft_vnmi_blocked))
3847 vmx->vnmi_blocked_time +=
3848 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3849 }
3850
3851 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3852 u32 idt_vectoring_info,
3853 int instr_len_field,
3854 int error_code_field)
3855 {
3856 u8 vector;
3857 int type;
3858 bool idtv_info_valid;
3859
3860 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3861
3862 vmx->vcpu.arch.nmi_injected = false;
3863 kvm_clear_exception_queue(&vmx->vcpu);
3864 kvm_clear_interrupt_queue(&vmx->vcpu);
3865
3866 if (!idtv_info_valid)
3867 return;
3868
3869 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3870
3871 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3872 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3873
3874 switch (type) {
3875 case INTR_TYPE_NMI_INTR:
3876 vmx->vcpu.arch.nmi_injected = true;
3877 /*
3878 * SDM 3: 27.7.1.2 (September 2008)
3879 * Clear bit "block by NMI" before VM entry if a NMI
3880 * delivery faulted.
3881 */
3882 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3883 GUEST_INTR_STATE_NMI);
3884 break;
3885 case INTR_TYPE_SOFT_EXCEPTION:
3886 vmx->vcpu.arch.event_exit_inst_len =
3887 vmcs_read32(instr_len_field);
3888 /* fall through */
3889 case INTR_TYPE_HARD_EXCEPTION:
3890 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3891 u32 err = vmcs_read32(error_code_field);
3892 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3893 } else
3894 kvm_queue_exception(&vmx->vcpu, vector);
3895 break;
3896 case INTR_TYPE_SOFT_INTR:
3897 vmx->vcpu.arch.event_exit_inst_len =
3898 vmcs_read32(instr_len_field);
3899 /* fall through */
3900 case INTR_TYPE_EXT_INTR:
3901 kvm_queue_interrupt(&vmx->vcpu, vector,
3902 type == INTR_TYPE_SOFT_INTR);
3903 break;
3904 default:
3905 break;
3906 }
3907 }
3908
3909 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3910 {
3911 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
3912 VM_EXIT_INSTRUCTION_LEN,
3913 IDT_VECTORING_ERROR_CODE);
3914 }
3915
3916 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
3917 {
3918 __vmx_complete_interrupts(to_vmx(vcpu),
3919 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
3920 VM_ENTRY_INSTRUCTION_LEN,
3921 VM_ENTRY_EXCEPTION_ERROR_CODE);
3922
3923 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
3924 }
3925
3926 #ifdef CONFIG_X86_64
3927 #define R "r"
3928 #define Q "q"
3929 #else
3930 #define R "e"
3931 #define Q "l"
3932 #endif
3933
3934 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3935 {
3936 struct vcpu_vmx *vmx = to_vmx(vcpu);
3937
3938 /* Record the guest's net vcpu time for enforced NMI injections. */
3939 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3940 vmx->entry_time = ktime_get();
3941
3942 /* Don't enter VMX if guest state is invalid, let the exit handler
3943 start emulation until we arrive back to a valid state */
3944 if (vmx->emulation_required && emulate_invalid_guest_state)
3945 return;
3946
3947 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3948 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3949 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3950 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3951
3952 /* When single-stepping over STI and MOV SS, we must clear the
3953 * corresponding interruptibility bits in the guest state. Otherwise
3954 * vmentry fails as it then expects bit 14 (BS) in pending debug
3955 * exceptions being set, but that's not correct for the guest debugging
3956 * case. */
3957 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3958 vmx_set_interrupt_shadow(vcpu, 0);
3959
3960 asm(
3961 /* Store host registers */
3962 "push %%"R"dx; push %%"R"bp;"
3963 "push %%"R"cx \n\t"
3964 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3965 "je 1f \n\t"
3966 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3967 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3968 "1: \n\t"
3969 /* Reload cr2 if changed */
3970 "mov %c[cr2](%0), %%"R"ax \n\t"
3971 "mov %%cr2, %%"R"dx \n\t"
3972 "cmp %%"R"ax, %%"R"dx \n\t"
3973 "je 2f \n\t"
3974 "mov %%"R"ax, %%cr2 \n\t"
3975 "2: \n\t"
3976 /* Check if vmlaunch of vmresume is needed */
3977 "cmpl $0, %c[launched](%0) \n\t"
3978 /* Load guest registers. Don't clobber flags. */
3979 "mov %c[rax](%0), %%"R"ax \n\t"
3980 "mov %c[rbx](%0), %%"R"bx \n\t"
3981 "mov %c[rdx](%0), %%"R"dx \n\t"
3982 "mov %c[rsi](%0), %%"R"si \n\t"
3983 "mov %c[rdi](%0), %%"R"di \n\t"
3984 "mov %c[rbp](%0), %%"R"bp \n\t"
3985 #ifdef CONFIG_X86_64
3986 "mov %c[r8](%0), %%r8 \n\t"
3987 "mov %c[r9](%0), %%r9 \n\t"
3988 "mov %c[r10](%0), %%r10 \n\t"
3989 "mov %c[r11](%0), %%r11 \n\t"
3990 "mov %c[r12](%0), %%r12 \n\t"
3991 "mov %c[r13](%0), %%r13 \n\t"
3992 "mov %c[r14](%0), %%r14 \n\t"
3993 "mov %c[r15](%0), %%r15 \n\t"
3994 #endif
3995 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3996
3997 /* Enter guest mode */
3998 "jne .Llaunched \n\t"
3999 __ex(ASM_VMX_VMLAUNCH) "\n\t"
4000 "jmp .Lkvm_vmx_return \n\t"
4001 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
4002 ".Lkvm_vmx_return: "
4003 /* Save guest registers, load host registers, keep flags */
4004 "xchg %0, (%%"R"sp) \n\t"
4005 "mov %%"R"ax, %c[rax](%0) \n\t"
4006 "mov %%"R"bx, %c[rbx](%0) \n\t"
4007 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
4008 "mov %%"R"dx, %c[rdx](%0) \n\t"
4009 "mov %%"R"si, %c[rsi](%0) \n\t"
4010 "mov %%"R"di, %c[rdi](%0) \n\t"
4011 "mov %%"R"bp, %c[rbp](%0) \n\t"
4012 #ifdef CONFIG_X86_64
4013 "mov %%r8, %c[r8](%0) \n\t"
4014 "mov %%r9, %c[r9](%0) \n\t"
4015 "mov %%r10, %c[r10](%0) \n\t"
4016 "mov %%r11, %c[r11](%0) \n\t"
4017 "mov %%r12, %c[r12](%0) \n\t"
4018 "mov %%r13, %c[r13](%0) \n\t"
4019 "mov %%r14, %c[r14](%0) \n\t"
4020 "mov %%r15, %c[r15](%0) \n\t"
4021 #endif
4022 "mov %%cr2, %%"R"ax \n\t"
4023 "mov %%"R"ax, %c[cr2](%0) \n\t"
4024
4025 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
4026 "setbe %c[fail](%0) \n\t"
4027 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4028 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4029 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
4030 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
4031 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4032 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4033 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4034 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4035 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4036 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4037 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
4038 #ifdef CONFIG_X86_64
4039 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4040 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4041 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4042 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4043 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4044 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4045 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4046 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
4047 #endif
4048 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
4049 : "cc", "memory"
4050 , R"ax", R"bx", R"di", R"si"
4051 #ifdef CONFIG_X86_64
4052 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4053 #endif
4054 );
4055
4056 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4057 | (1 << VCPU_EXREG_PDPTR));
4058 vcpu->arch.regs_dirty = 0;
4059
4060 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4061
4062 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
4063 vmx->launched = 1;
4064
4065 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4066 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4067
4068 vmx_complete_atomic_exit(vmx);
4069 vmx_recover_nmi_blocking(vmx);
4070 vmx_complete_interrupts(vmx);
4071 }
4072
4073 #undef R
4074 #undef Q
4075
4076 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4077 {
4078 struct vcpu_vmx *vmx = to_vmx(vcpu);
4079
4080 if (vmx->vmcs) {
4081 vcpu_clear(vmx);
4082 free_vmcs(vmx->vmcs);
4083 vmx->vmcs = NULL;
4084 }
4085 }
4086
4087 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4088 {
4089 struct vcpu_vmx *vmx = to_vmx(vcpu);
4090
4091 free_vpid(vmx);
4092 vmx_free_vmcs(vcpu);
4093 kfree(vmx->guest_msrs);
4094 kvm_vcpu_uninit(vcpu);
4095 kmem_cache_free(kvm_vcpu_cache, vmx);
4096 }
4097
4098 static inline void vmcs_init(struct vmcs *vmcs)
4099 {
4100 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4101
4102 if (!vmm_exclusive)
4103 kvm_cpu_vmxon(phys_addr);
4104
4105 vmcs_clear(vmcs);
4106
4107 if (!vmm_exclusive)
4108 kvm_cpu_vmxoff();
4109 }
4110
4111 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4112 {
4113 int err;
4114 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4115 int cpu;
4116
4117 if (!vmx)
4118 return ERR_PTR(-ENOMEM);
4119
4120 allocate_vpid(vmx);
4121
4122 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4123 if (err)
4124 goto free_vcpu;
4125
4126 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4127 if (!vmx->guest_msrs) {
4128 err = -ENOMEM;
4129 goto uninit_vcpu;
4130 }
4131
4132 vmx->vmcs = alloc_vmcs();
4133 if (!vmx->vmcs)
4134 goto free_msrs;
4135
4136 vmcs_init(vmx->vmcs);
4137
4138 cpu = get_cpu();
4139 vmx_vcpu_load(&vmx->vcpu, cpu);
4140 vmx->vcpu.cpu = cpu;
4141 err = vmx_vcpu_setup(vmx);
4142 vmx_vcpu_put(&vmx->vcpu);
4143 put_cpu();
4144 if (err)
4145 goto free_vmcs;
4146 if (vm_need_virtualize_apic_accesses(kvm))
4147 if (alloc_apic_access_page(kvm) != 0)
4148 goto free_vmcs;
4149
4150 if (enable_ept) {
4151 if (!kvm->arch.ept_identity_map_addr)
4152 kvm->arch.ept_identity_map_addr =
4153 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4154 if (alloc_identity_pagetable(kvm) != 0)
4155 goto free_vmcs;
4156 }
4157
4158 return &vmx->vcpu;
4159
4160 free_vmcs:
4161 free_vmcs(vmx->vmcs);
4162 free_msrs:
4163 kfree(vmx->guest_msrs);
4164 uninit_vcpu:
4165 kvm_vcpu_uninit(&vmx->vcpu);
4166 free_vcpu:
4167 free_vpid(vmx);
4168 kmem_cache_free(kvm_vcpu_cache, vmx);
4169 return ERR_PTR(err);
4170 }
4171
4172 static void __init vmx_check_processor_compat(void *rtn)
4173 {
4174 struct vmcs_config vmcs_conf;
4175
4176 *(int *)rtn = 0;
4177 if (setup_vmcs_config(&vmcs_conf) < 0)
4178 *(int *)rtn = -EIO;
4179 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4180 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4181 smp_processor_id());
4182 *(int *)rtn = -EIO;
4183 }
4184 }
4185
4186 static int get_ept_level(void)
4187 {
4188 return VMX_EPT_DEFAULT_GAW + 1;
4189 }
4190
4191 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4192 {
4193 u64 ret;
4194
4195 /* For VT-d and EPT combination
4196 * 1. MMIO: always map as UC
4197 * 2. EPT with VT-d:
4198 * a. VT-d without snooping control feature: can't guarantee the
4199 * result, try to trust guest.
4200 * b. VT-d with snooping control feature: snooping control feature of
4201 * VT-d engine can guarantee the cache correctness. Just set it
4202 * to WB to keep consistent with host. So the same as item 3.
4203 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4204 * consistent with host MTRR
4205 */
4206 if (is_mmio)
4207 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4208 else if (vcpu->kvm->arch.iommu_domain &&
4209 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4210 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4211 VMX_EPT_MT_EPTE_SHIFT;
4212 else
4213 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4214 | VMX_EPT_IPAT_BIT;
4215
4216 return ret;
4217 }
4218
4219 #define _ER(x) { EXIT_REASON_##x, #x }
4220
4221 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4222 _ER(EXCEPTION_NMI),
4223 _ER(EXTERNAL_INTERRUPT),
4224 _ER(TRIPLE_FAULT),
4225 _ER(PENDING_INTERRUPT),
4226 _ER(NMI_WINDOW),
4227 _ER(TASK_SWITCH),
4228 _ER(CPUID),
4229 _ER(HLT),
4230 _ER(INVLPG),
4231 _ER(RDPMC),
4232 _ER(RDTSC),
4233 _ER(VMCALL),
4234 _ER(VMCLEAR),
4235 _ER(VMLAUNCH),
4236 _ER(VMPTRLD),
4237 _ER(VMPTRST),
4238 _ER(VMREAD),
4239 _ER(VMRESUME),
4240 _ER(VMWRITE),
4241 _ER(VMOFF),
4242 _ER(VMON),
4243 _ER(CR_ACCESS),
4244 _ER(DR_ACCESS),
4245 _ER(IO_INSTRUCTION),
4246 _ER(MSR_READ),
4247 _ER(MSR_WRITE),
4248 _ER(MWAIT_INSTRUCTION),
4249 _ER(MONITOR_INSTRUCTION),
4250 _ER(PAUSE_INSTRUCTION),
4251 _ER(MCE_DURING_VMENTRY),
4252 _ER(TPR_BELOW_THRESHOLD),
4253 _ER(APIC_ACCESS),
4254 _ER(EPT_VIOLATION),
4255 _ER(EPT_MISCONFIG),
4256 _ER(WBINVD),
4257 { -1, NULL }
4258 };
4259
4260 #undef _ER
4261
4262 static int vmx_get_lpage_level(void)
4263 {
4264 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4265 return PT_DIRECTORY_LEVEL;
4266 else
4267 /* For shadow and EPT supported 1GB page */
4268 return PT_PDPE_LEVEL;
4269 }
4270
4271 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4272 {
4273 struct kvm_cpuid_entry2 *best;
4274 struct vcpu_vmx *vmx = to_vmx(vcpu);
4275 u32 exec_control;
4276
4277 vmx->rdtscp_enabled = false;
4278 if (vmx_rdtscp_supported()) {
4279 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4280 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4281 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4282 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4283 vmx->rdtscp_enabled = true;
4284 else {
4285 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4286 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4287 exec_control);
4288 }
4289 }
4290 }
4291 }
4292
4293 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4294 {
4295 }
4296
4297 static struct kvm_x86_ops vmx_x86_ops = {
4298 .cpu_has_kvm_support = cpu_has_kvm_support,
4299 .disabled_by_bios = vmx_disabled_by_bios,
4300 .hardware_setup = hardware_setup,
4301 .hardware_unsetup = hardware_unsetup,
4302 .check_processor_compatibility = vmx_check_processor_compat,
4303 .hardware_enable = hardware_enable,
4304 .hardware_disable = hardware_disable,
4305 .cpu_has_accelerated_tpr = report_flexpriority,
4306
4307 .vcpu_create = vmx_create_vcpu,
4308 .vcpu_free = vmx_free_vcpu,
4309 .vcpu_reset = vmx_vcpu_reset,
4310
4311 .prepare_guest_switch = vmx_save_host_state,
4312 .vcpu_load = vmx_vcpu_load,
4313 .vcpu_put = vmx_vcpu_put,
4314
4315 .set_guest_debug = set_guest_debug,
4316 .get_msr = vmx_get_msr,
4317 .set_msr = vmx_set_msr,
4318 .get_segment_base = vmx_get_segment_base,
4319 .get_segment = vmx_get_segment,
4320 .set_segment = vmx_set_segment,
4321 .get_cpl = vmx_get_cpl,
4322 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4323 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4324 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4325 .set_cr0 = vmx_set_cr0,
4326 .set_cr3 = vmx_set_cr3,
4327 .set_cr4 = vmx_set_cr4,
4328 .set_efer = vmx_set_efer,
4329 .get_idt = vmx_get_idt,
4330 .set_idt = vmx_set_idt,
4331 .get_gdt = vmx_get_gdt,
4332 .set_gdt = vmx_set_gdt,
4333 .set_dr7 = vmx_set_dr7,
4334 .cache_reg = vmx_cache_reg,
4335 .get_rflags = vmx_get_rflags,
4336 .set_rflags = vmx_set_rflags,
4337 .fpu_activate = vmx_fpu_activate,
4338 .fpu_deactivate = vmx_fpu_deactivate,
4339
4340 .tlb_flush = vmx_flush_tlb,
4341
4342 .run = vmx_vcpu_run,
4343 .handle_exit = vmx_handle_exit,
4344 .skip_emulated_instruction = skip_emulated_instruction,
4345 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4346 .get_interrupt_shadow = vmx_get_interrupt_shadow,
4347 .patch_hypercall = vmx_patch_hypercall,
4348 .set_irq = vmx_inject_irq,
4349 .set_nmi = vmx_inject_nmi,
4350 .queue_exception = vmx_queue_exception,
4351 .cancel_injection = vmx_cancel_injection,
4352 .interrupt_allowed = vmx_interrupt_allowed,
4353 .nmi_allowed = vmx_nmi_allowed,
4354 .get_nmi_mask = vmx_get_nmi_mask,
4355 .set_nmi_mask = vmx_set_nmi_mask,
4356 .enable_nmi_window = enable_nmi_window,
4357 .enable_irq_window = enable_irq_window,
4358 .update_cr8_intercept = update_cr8_intercept,
4359
4360 .set_tss_addr = vmx_set_tss_addr,
4361 .get_tdp_level = get_ept_level,
4362 .get_mt_mask = vmx_get_mt_mask,
4363
4364 .get_exit_info = vmx_get_exit_info,
4365 .exit_reasons_str = vmx_exit_reasons_str,
4366
4367 .get_lpage_level = vmx_get_lpage_level,
4368
4369 .cpuid_update = vmx_cpuid_update,
4370
4371 .rdtscp_supported = vmx_rdtscp_supported,
4372
4373 .set_supported_cpuid = vmx_set_supported_cpuid,
4374
4375 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
4376
4377 .write_tsc_offset = vmx_write_tsc_offset,
4378 .adjust_tsc_offset = vmx_adjust_tsc_offset,
4379
4380 .set_tdp_cr3 = vmx_set_cr3,
4381 };
4382
4383 static int __init vmx_init(void)
4384 {
4385 int r, i;
4386
4387 rdmsrl_safe(MSR_EFER, &host_efer);
4388
4389 for (i = 0; i < NR_VMX_MSR; ++i)
4390 kvm_define_shared_msr(i, vmx_msr_index[i]);
4391
4392 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4393 if (!vmx_io_bitmap_a)
4394 return -ENOMEM;
4395
4396 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4397 if (!vmx_io_bitmap_b) {
4398 r = -ENOMEM;
4399 goto out;
4400 }
4401
4402 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4403 if (!vmx_msr_bitmap_legacy) {
4404 r = -ENOMEM;
4405 goto out1;
4406 }
4407
4408 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4409 if (!vmx_msr_bitmap_longmode) {
4410 r = -ENOMEM;
4411 goto out2;
4412 }
4413
4414 /*
4415 * Allow direct access to the PC debug port (it is often used for I/O
4416 * delays, but the vmexits simply slow things down).
4417 */
4418 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4419 clear_bit(0x80, vmx_io_bitmap_a);
4420
4421 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4422
4423 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4424 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4425
4426 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4427
4428 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4429 __alignof__(struct vcpu_vmx), THIS_MODULE);
4430 if (r)
4431 goto out3;
4432
4433 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4434 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4435 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4436 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4437 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4438 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4439
4440 if (enable_ept) {
4441 bypass_guest_pf = 0;
4442 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4443 VMX_EPT_EXECUTABLE_MASK);
4444 kvm_enable_tdp();
4445 } else
4446 kvm_disable_tdp();
4447
4448 if (bypass_guest_pf)
4449 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4450
4451 return 0;
4452
4453 out3:
4454 free_page((unsigned long)vmx_msr_bitmap_longmode);
4455 out2:
4456 free_page((unsigned long)vmx_msr_bitmap_legacy);
4457 out1:
4458 free_page((unsigned long)vmx_io_bitmap_b);
4459 out:
4460 free_page((unsigned long)vmx_io_bitmap_a);
4461 return r;
4462 }
4463
4464 static void __exit vmx_exit(void)
4465 {
4466 free_page((unsigned long)vmx_msr_bitmap_legacy);
4467 free_page((unsigned long)vmx_msr_bitmap_longmode);
4468 free_page((unsigned long)vmx_io_bitmap_b);
4469 free_page((unsigned long)vmx_io_bitmap_a);
4470
4471 kvm_exit();
4472 }
4473
4474 module_init(vmx_init)
4475 module_exit(vmx_exit)
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