2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
50 static int __read_mostly bypass_guest_pf
= 1;
51 module_param(bypass_guest_pf
, bool, S_IRUGO
);
53 static int __read_mostly enable_vpid
= 1;
54 module_param_named(vpid
, enable_vpid
, bool, 0444);
56 static int __read_mostly flexpriority_enabled
= 1;
57 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
59 static int __read_mostly enable_ept
= 1;
60 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
62 static int __read_mostly enable_unrestricted_guest
= 1;
63 module_param_named(unrestricted_guest
,
64 enable_unrestricted_guest
, bool, S_IRUGO
);
66 static int __read_mostly emulate_invalid_guest_state
= 0;
67 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
69 static int __read_mostly vmm_exclusive
= 1;
70 module_param(vmm_exclusive
, bool, S_IRUGO
);
72 static int __read_mostly yield_on_hlt
= 1;
73 module_param(yield_on_hlt
, bool, S_IRUGO
);
75 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77 #define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
80 (X86_CR0_WP | X86_CR0_NE)
81 #define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
83 #define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
87 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
90 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
96 * According to test, this time is usually small than 41 cycles.
97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
103 #define KVM_VMX_DEFAULT_PLE_GAP 41
104 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
106 module_param(ple_gap
, int, S_IRUGO
);
108 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
109 module_param(ple_window
, int, S_IRUGO
);
111 #define NR_AUTOLOAD_MSRS 1
119 struct shared_msr_entry
{
126 struct kvm_vcpu vcpu
;
127 struct list_head local_vcpus_link
;
128 unsigned long host_rsp
;
132 u32 idt_vectoring_info
;
133 struct shared_msr_entry
*guest_msrs
;
137 u64 msr_host_kernel_gs_base
;
138 u64 msr_guest_kernel_gs_base
;
141 struct msr_autoload
{
143 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
144 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
148 u16 fs_sel
, gs_sel
, ldt_sel
;
149 int gs_ldt_reload_needed
;
150 int fs_reload_needed
;
155 struct kvm_save_segment
{
160 } tr
, es
, ds
, fs
, gs
;
163 bool emulation_required
;
165 /* Support for vnmi-less CPUs */
166 int soft_vnmi_blocked
;
168 s64 vnmi_blocked_time
;
174 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
176 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
179 static int init_rmode(struct kvm
*kvm
);
180 static u64
construct_eptp(unsigned long root_hpa
);
181 static void kvm_cpu_vmxon(u64 addr
);
182 static void kvm_cpu_vmxoff(void);
184 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
185 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
186 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
187 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
189 static unsigned long *vmx_io_bitmap_a
;
190 static unsigned long *vmx_io_bitmap_b
;
191 static unsigned long *vmx_msr_bitmap_legacy
;
192 static unsigned long *vmx_msr_bitmap_longmode
;
194 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
195 static DEFINE_SPINLOCK(vmx_vpid_lock
);
197 static struct vmcs_config
{
201 u32 pin_based_exec_ctrl
;
202 u32 cpu_based_exec_ctrl
;
203 u32 cpu_based_2nd_exec_ctrl
;
208 static struct vmx_capability
{
213 #define VMX_SEGMENT_FIELD(seg) \
214 [VCPU_SREG_##seg] = { \
215 .selector = GUEST_##seg##_SELECTOR, \
216 .base = GUEST_##seg##_BASE, \
217 .limit = GUEST_##seg##_LIMIT, \
218 .ar_bytes = GUEST_##seg##_AR_BYTES, \
221 static struct kvm_vmx_segment_field
{
226 } kvm_vmx_segment_fields
[] = {
227 VMX_SEGMENT_FIELD(CS
),
228 VMX_SEGMENT_FIELD(DS
),
229 VMX_SEGMENT_FIELD(ES
),
230 VMX_SEGMENT_FIELD(FS
),
231 VMX_SEGMENT_FIELD(GS
),
232 VMX_SEGMENT_FIELD(SS
),
233 VMX_SEGMENT_FIELD(TR
),
234 VMX_SEGMENT_FIELD(LDTR
),
237 static u64 host_efer
;
239 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
242 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
243 * away by decrementing the array size.
245 static const u32 vmx_msr_index
[] = {
247 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
249 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
251 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
253 static inline bool is_page_fault(u32 intr_info
)
255 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
256 INTR_INFO_VALID_MASK
)) ==
257 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
260 static inline bool is_no_device(u32 intr_info
)
262 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
263 INTR_INFO_VALID_MASK
)) ==
264 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
267 static inline bool is_invalid_opcode(u32 intr_info
)
269 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
270 INTR_INFO_VALID_MASK
)) ==
271 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
274 static inline bool is_external_interrupt(u32 intr_info
)
276 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
277 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
280 static inline bool is_machine_check(u32 intr_info
)
282 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
283 INTR_INFO_VALID_MASK
)) ==
284 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
287 static inline bool cpu_has_vmx_msr_bitmap(void)
289 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
292 static inline bool cpu_has_vmx_tpr_shadow(void)
294 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
297 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
299 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
302 static inline bool cpu_has_secondary_exec_ctrls(void)
304 return vmcs_config
.cpu_based_exec_ctrl
&
305 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
308 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
310 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
311 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
314 static inline bool cpu_has_vmx_flexpriority(void)
316 return cpu_has_vmx_tpr_shadow() &&
317 cpu_has_vmx_virtualize_apic_accesses();
320 static inline bool cpu_has_vmx_ept_execute_only(void)
322 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
325 static inline bool cpu_has_vmx_eptp_uncacheable(void)
327 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
330 static inline bool cpu_has_vmx_eptp_writeback(void)
332 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
335 static inline bool cpu_has_vmx_ept_2m_page(void)
337 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
340 static inline bool cpu_has_vmx_ept_1g_page(void)
342 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
345 static inline bool cpu_has_vmx_ept_4levels(void)
347 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
350 static inline bool cpu_has_vmx_invept_individual_addr(void)
352 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
355 static inline bool cpu_has_vmx_invept_context(void)
357 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
360 static inline bool cpu_has_vmx_invept_global(void)
362 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
365 static inline bool cpu_has_vmx_invvpid_single(void)
367 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
370 static inline bool cpu_has_vmx_invvpid_global(void)
372 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
375 static inline bool cpu_has_vmx_ept(void)
377 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
378 SECONDARY_EXEC_ENABLE_EPT
;
381 static inline bool cpu_has_vmx_unrestricted_guest(void)
383 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
384 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
387 static inline bool cpu_has_vmx_ple(void)
389 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
390 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
393 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
395 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
398 static inline bool cpu_has_vmx_vpid(void)
400 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
401 SECONDARY_EXEC_ENABLE_VPID
;
404 static inline bool cpu_has_vmx_rdtscp(void)
406 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
407 SECONDARY_EXEC_RDTSCP
;
410 static inline bool cpu_has_virtual_nmis(void)
412 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
415 static inline bool cpu_has_vmx_wbinvd_exit(void)
417 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
418 SECONDARY_EXEC_WBINVD_EXITING
;
421 static inline bool report_flexpriority(void)
423 return flexpriority_enabled
;
426 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
430 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
431 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
436 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
442 } operand
= { vpid
, 0, gva
};
444 asm volatile (__ex(ASM_VMX_INVVPID
)
445 /* CF==1 or ZF==1 --> rc = -1 */
447 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
450 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
454 } operand
= {eptp
, gpa
};
456 asm volatile (__ex(ASM_VMX_INVEPT
)
457 /* CF==1 or ZF==1 --> rc = -1 */
458 "; ja 1f ; ud2 ; 1:\n"
459 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
462 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
466 i
= __find_msr_index(vmx
, msr
);
468 return &vmx
->guest_msrs
[i
];
472 static void vmcs_clear(struct vmcs
*vmcs
)
474 u64 phys_addr
= __pa(vmcs
);
477 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
478 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
481 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
485 static void vmcs_load(struct vmcs
*vmcs
)
487 u64 phys_addr
= __pa(vmcs
);
490 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
491 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
494 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
498 static void __vcpu_clear(void *arg
)
500 struct vcpu_vmx
*vmx
= arg
;
501 int cpu
= raw_smp_processor_id();
503 if (vmx
->vcpu
.cpu
== cpu
)
504 vmcs_clear(vmx
->vmcs
);
505 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
506 per_cpu(current_vmcs
, cpu
) = NULL
;
507 list_del(&vmx
->local_vcpus_link
);
512 static void vcpu_clear(struct vcpu_vmx
*vmx
)
514 if (vmx
->vcpu
.cpu
== -1)
516 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
519 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
524 if (cpu_has_vmx_invvpid_single())
525 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
528 static inline void vpid_sync_vcpu_global(void)
530 if (cpu_has_vmx_invvpid_global())
531 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
534 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
536 if (cpu_has_vmx_invvpid_single())
537 vpid_sync_vcpu_single(vmx
);
539 vpid_sync_vcpu_global();
542 static inline void ept_sync_global(void)
544 if (cpu_has_vmx_invept_global())
545 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
548 static inline void ept_sync_context(u64 eptp
)
551 if (cpu_has_vmx_invept_context())
552 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
558 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
561 if (cpu_has_vmx_invept_individual_addr())
562 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
565 ept_sync_context(eptp
);
569 static unsigned long vmcs_readl(unsigned long field
)
571 unsigned long value
= 0;
573 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
574 : "+a"(value
) : "d"(field
) : "cc");
578 static u16
vmcs_read16(unsigned long field
)
580 return vmcs_readl(field
);
583 static u32
vmcs_read32(unsigned long field
)
585 return vmcs_readl(field
);
588 static u64
vmcs_read64(unsigned long field
)
591 return vmcs_readl(field
);
593 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
597 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
599 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
600 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
604 static void vmcs_writel(unsigned long field
, unsigned long value
)
608 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
609 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
611 vmwrite_error(field
, value
);
614 static void vmcs_write16(unsigned long field
, u16 value
)
616 vmcs_writel(field
, value
);
619 static void vmcs_write32(unsigned long field
, u32 value
)
621 vmcs_writel(field
, value
);
624 static void vmcs_write64(unsigned long field
, u64 value
)
626 vmcs_writel(field
, value
);
627 #ifndef CONFIG_X86_64
629 vmcs_writel(field
+1, value
>> 32);
633 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
635 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
638 static void vmcs_set_bits(unsigned long field
, u32 mask
)
640 vmcs_writel(field
, vmcs_readl(field
) | mask
);
643 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
647 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
648 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
649 if ((vcpu
->guest_debug
&
650 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
651 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
652 eb
|= 1u << BP_VECTOR
;
653 if (to_vmx(vcpu
)->rmode
.vm86_active
)
656 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
657 if (vcpu
->fpu_active
)
658 eb
&= ~(1u << NM_VECTOR
);
659 vmcs_write32(EXCEPTION_BITMAP
, eb
);
662 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
665 struct msr_autoload
*m
= &vmx
->msr_autoload
;
667 for (i
= 0; i
< m
->nr
; ++i
)
668 if (m
->guest
[i
].index
== msr
)
674 m
->guest
[i
] = m
->guest
[m
->nr
];
675 m
->host
[i
] = m
->host
[m
->nr
];
676 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
677 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
680 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
681 u64 guest_val
, u64 host_val
)
684 struct msr_autoload
*m
= &vmx
->msr_autoload
;
686 for (i
= 0; i
< m
->nr
; ++i
)
687 if (m
->guest
[i
].index
== msr
)
692 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
693 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
696 m
->guest
[i
].index
= msr
;
697 m
->guest
[i
].value
= guest_val
;
698 m
->host
[i
].index
= msr
;
699 m
->host
[i
].value
= host_val
;
702 static void reload_tss(void)
705 * VT restores TR but not its size. Useless.
707 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
708 struct desc_struct
*descs
;
710 descs
= (void *)gdt
->address
;
711 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
715 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
720 guest_efer
= vmx
->vcpu
.arch
.efer
;
723 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
726 ignore_bits
= EFER_NX
| EFER_SCE
;
728 ignore_bits
|= EFER_LMA
| EFER_LME
;
729 /* SCE is meaningful only in long mode on Intel */
730 if (guest_efer
& EFER_LMA
)
731 ignore_bits
&= ~(u64
)EFER_SCE
;
733 guest_efer
&= ~ignore_bits
;
734 guest_efer
|= host_efer
& ignore_bits
;
735 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
736 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
738 clear_atomic_switch_msr(vmx
, MSR_EFER
);
739 /* On ept, can't emulate nx, and must switch nx atomically */
740 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
741 guest_efer
= vmx
->vcpu
.arch
.efer
;
742 if (!(guest_efer
& EFER_LMA
))
743 guest_efer
&= ~EFER_LME
;
744 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
751 static unsigned long segment_base(u16 selector
)
753 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
754 struct desc_struct
*d
;
755 unsigned long table_base
;
758 if (!(selector
& ~3))
761 table_base
= gdt
->address
;
763 if (selector
& 4) { /* from ldt */
764 u16 ldt_selector
= kvm_read_ldt();
766 if (!(ldt_selector
& ~3))
769 table_base
= segment_base(ldt_selector
);
771 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
772 v
= get_desc_base(d
);
774 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
775 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
780 static inline unsigned long kvm_read_tr_base(void)
783 asm("str %0" : "=g"(tr
));
784 return segment_base(tr
);
787 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
789 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
792 if (vmx
->host_state
.loaded
)
795 vmx
->host_state
.loaded
= 1;
797 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
798 * allow segment selectors with cpl > 0 or ti == 1.
800 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
801 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
802 savesegment(fs
, vmx
->host_state
.fs_sel
);
803 if (!(vmx
->host_state
.fs_sel
& 7)) {
804 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
805 vmx
->host_state
.fs_reload_needed
= 0;
807 vmcs_write16(HOST_FS_SELECTOR
, 0);
808 vmx
->host_state
.fs_reload_needed
= 1;
810 savesegment(gs
, vmx
->host_state
.gs_sel
);
811 if (!(vmx
->host_state
.gs_sel
& 7))
812 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
814 vmcs_write16(HOST_GS_SELECTOR
, 0);
815 vmx
->host_state
.gs_ldt_reload_needed
= 1;
819 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
820 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
822 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
823 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
827 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
828 if (is_long_mode(&vmx
->vcpu
))
829 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
831 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
832 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
833 vmx
->guest_msrs
[i
].data
,
834 vmx
->guest_msrs
[i
].mask
);
837 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
839 if (!vmx
->host_state
.loaded
)
842 ++vmx
->vcpu
.stat
.host_state_reload
;
843 vmx
->host_state
.loaded
= 0;
845 if (is_long_mode(&vmx
->vcpu
))
846 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
848 if (vmx
->host_state
.gs_ldt_reload_needed
) {
849 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
851 load_gs_index(vmx
->host_state
.gs_sel
);
853 loadsegment(gs
, vmx
->host_state
.gs_sel
);
856 if (vmx
->host_state
.fs_reload_needed
)
857 loadsegment(fs
, vmx
->host_state
.fs_sel
);
860 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
862 if (current_thread_info()->status
& TS_USEDFPU
)
864 load_gdt(&__get_cpu_var(host_gdt
));
867 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
870 __vmx_load_host_state(vmx
);
875 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
876 * vcpu mutex is already taken.
878 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
880 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
881 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
884 kvm_cpu_vmxon(phys_addr
);
885 else if (vcpu
->cpu
!= cpu
)
888 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
889 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
890 vmcs_load(vmx
->vmcs
);
893 if (vcpu
->cpu
!= cpu
) {
894 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
895 unsigned long sysenter_esp
;
897 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
899 list_add(&vmx
->local_vcpus_link
,
900 &per_cpu(vcpus_on_cpu
, cpu
));
904 * Linux uses per-cpu TSS and GDT, so set these when switching
907 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
908 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
910 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
911 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
915 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
917 __vmx_load_host_state(to_vmx(vcpu
));
918 if (!vmm_exclusive
) {
919 __vcpu_clear(to_vmx(vcpu
));
924 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
928 if (vcpu
->fpu_active
)
930 vcpu
->fpu_active
= 1;
931 cr0
= vmcs_readl(GUEST_CR0
);
932 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
933 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
934 vmcs_writel(GUEST_CR0
, cr0
);
935 update_exception_bitmap(vcpu
);
936 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
937 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
940 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
942 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
944 vmx_decache_cr0_guest_bits(vcpu
);
945 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
946 update_exception_bitmap(vcpu
);
947 vcpu
->arch
.cr0_guest_owned_bits
= 0;
948 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
949 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
952 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
954 unsigned long rflags
, save_rflags
;
956 rflags
= vmcs_readl(GUEST_RFLAGS
);
957 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
958 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
959 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
960 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
965 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
967 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
968 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
969 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
971 vmcs_writel(GUEST_RFLAGS
, rflags
);
974 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
976 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
979 if (interruptibility
& GUEST_INTR_STATE_STI
)
980 ret
|= KVM_X86_SHADOW_INT_STI
;
981 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
982 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
987 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
989 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
990 u32 interruptibility
= interruptibility_old
;
992 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
994 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
995 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
996 else if (mask
& KVM_X86_SHADOW_INT_STI
)
997 interruptibility
|= GUEST_INTR_STATE_STI
;
999 if ((interruptibility
!= interruptibility_old
))
1000 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1003 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1007 rip
= kvm_rip_read(vcpu
);
1008 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1009 kvm_rip_write(vcpu
, rip
);
1011 /* skipping an emulated instruction also counts */
1012 vmx_set_interrupt_shadow(vcpu
, 0);
1015 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1017 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1018 * explicitly skip the instruction because if the HLT state is set, then
1019 * the instruction is already executing and RIP has already been
1021 if (!yield_on_hlt
&&
1022 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1023 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1026 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1027 bool has_error_code
, u32 error_code
,
1030 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1031 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1033 if (has_error_code
) {
1034 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1035 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1038 if (vmx
->rmode
.vm86_active
) {
1039 if (kvm_inject_realmode_interrupt(vcpu
, nr
) != EMULATE_DONE
)
1040 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1044 if (kvm_exception_is_soft(nr
)) {
1045 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1046 vmx
->vcpu
.arch
.event_exit_inst_len
);
1047 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1049 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1052 vmx_clear_hlt(vcpu
);
1055 static bool vmx_rdtscp_supported(void)
1057 return cpu_has_vmx_rdtscp();
1061 * Swap MSR entry in host/guest MSR entry array.
1063 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1065 struct shared_msr_entry tmp
;
1067 tmp
= vmx
->guest_msrs
[to
];
1068 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1069 vmx
->guest_msrs
[from
] = tmp
;
1073 * Set up the vmcs to automatically save and restore system
1074 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1075 * mode, as fiddling with msrs is very expensive.
1077 static void setup_msrs(struct vcpu_vmx
*vmx
)
1079 int save_nmsrs
, index
;
1080 unsigned long *msr_bitmap
;
1082 vmx_load_host_state(vmx
);
1084 #ifdef CONFIG_X86_64
1085 if (is_long_mode(&vmx
->vcpu
)) {
1086 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1088 move_msr_up(vmx
, index
, save_nmsrs
++);
1089 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1091 move_msr_up(vmx
, index
, save_nmsrs
++);
1092 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1094 move_msr_up(vmx
, index
, save_nmsrs
++);
1095 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1096 if (index
>= 0 && vmx
->rdtscp_enabled
)
1097 move_msr_up(vmx
, index
, save_nmsrs
++);
1099 * MSR_STAR is only needed on long mode guests, and only
1100 * if efer.sce is enabled.
1102 index
= __find_msr_index(vmx
, MSR_STAR
);
1103 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1104 move_msr_up(vmx
, index
, save_nmsrs
++);
1107 index
= __find_msr_index(vmx
, MSR_EFER
);
1108 if (index
>= 0 && update_transition_efer(vmx
, index
))
1109 move_msr_up(vmx
, index
, save_nmsrs
++);
1111 vmx
->save_nmsrs
= save_nmsrs
;
1113 if (cpu_has_vmx_msr_bitmap()) {
1114 if (is_long_mode(&vmx
->vcpu
))
1115 msr_bitmap
= vmx_msr_bitmap_longmode
;
1117 msr_bitmap
= vmx_msr_bitmap_legacy
;
1119 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1124 * reads and returns guest's timestamp counter "register"
1125 * guest_tsc = host_tsc + tsc_offset -- 21.3
1127 static u64
guest_read_tsc(void)
1129 u64 host_tsc
, tsc_offset
;
1132 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1133 return host_tsc
+ tsc_offset
;
1137 * writes 'offset' into guest's timestamp counter offset register
1139 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1141 vmcs_write64(TSC_OFFSET
, offset
);
1144 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1146 u64 offset
= vmcs_read64(TSC_OFFSET
);
1147 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1151 * Reads an msr value (of 'msr_index') into 'pdata'.
1152 * Returns 0 on success, non-0 otherwise.
1153 * Assumes vcpu_load() was already called.
1155 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1158 struct shared_msr_entry
*msr
;
1161 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1165 switch (msr_index
) {
1166 #ifdef CONFIG_X86_64
1168 data
= vmcs_readl(GUEST_FS_BASE
);
1171 data
= vmcs_readl(GUEST_GS_BASE
);
1173 case MSR_KERNEL_GS_BASE
:
1174 vmx_load_host_state(to_vmx(vcpu
));
1175 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1179 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1181 data
= guest_read_tsc();
1183 case MSR_IA32_SYSENTER_CS
:
1184 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1186 case MSR_IA32_SYSENTER_EIP
:
1187 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1189 case MSR_IA32_SYSENTER_ESP
:
1190 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1193 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1195 /* Otherwise falls through */
1197 vmx_load_host_state(to_vmx(vcpu
));
1198 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1200 vmx_load_host_state(to_vmx(vcpu
));
1204 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1212 * Writes msr value into into the appropriate "register".
1213 * Returns 0 on success, non-0 otherwise.
1214 * Assumes vcpu_load() was already called.
1216 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1218 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1219 struct shared_msr_entry
*msr
;
1222 switch (msr_index
) {
1224 vmx_load_host_state(vmx
);
1225 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1227 #ifdef CONFIG_X86_64
1229 vmcs_writel(GUEST_FS_BASE
, data
);
1232 vmcs_writel(GUEST_GS_BASE
, data
);
1234 case MSR_KERNEL_GS_BASE
:
1235 vmx_load_host_state(vmx
);
1236 vmx
->msr_guest_kernel_gs_base
= data
;
1239 case MSR_IA32_SYSENTER_CS
:
1240 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1242 case MSR_IA32_SYSENTER_EIP
:
1243 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1245 case MSR_IA32_SYSENTER_ESP
:
1246 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1249 kvm_write_tsc(vcpu
, data
);
1251 case MSR_IA32_CR_PAT
:
1252 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1253 vmcs_write64(GUEST_IA32_PAT
, data
);
1254 vcpu
->arch
.pat
= data
;
1257 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1260 if (!vmx
->rdtscp_enabled
)
1262 /* Check reserved bit, higher 32 bits should be zero */
1263 if ((data
>> 32) != 0)
1265 /* Otherwise falls through */
1267 msr
= find_msr_entry(vmx
, msr_index
);
1269 vmx_load_host_state(vmx
);
1273 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1279 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1281 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1284 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1287 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1289 case VCPU_EXREG_PDPTR
:
1291 ept_save_pdptrs(vcpu
);
1298 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1300 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1301 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1303 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1305 update_exception_bitmap(vcpu
);
1308 static __init
int cpu_has_kvm_support(void)
1310 return cpu_has_vmx();
1313 static __init
int vmx_disabled_by_bios(void)
1317 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1318 if (msr
& FEATURE_CONTROL_LOCKED
) {
1319 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1322 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1323 && !tboot_enabled()) {
1324 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
1325 " activate TXT before enabling KVM\n");
1331 /* locked but not enabled */
1334 static void kvm_cpu_vmxon(u64 addr
)
1336 asm volatile (ASM_VMX_VMXON_RAX
1337 : : "a"(&addr
), "m"(addr
)
1341 static int hardware_enable(void *garbage
)
1343 int cpu
= raw_smp_processor_id();
1344 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1347 if (read_cr4() & X86_CR4_VMXE
)
1350 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1351 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1353 test_bits
= FEATURE_CONTROL_LOCKED
;
1354 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1355 if (tboot_enabled())
1356 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
1358 if ((old
& test_bits
) != test_bits
) {
1359 /* enable and lock */
1360 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
1362 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1364 if (vmm_exclusive
) {
1365 kvm_cpu_vmxon(phys_addr
);
1369 store_gdt(&__get_cpu_var(host_gdt
));
1374 static void vmclear_local_vcpus(void)
1376 int cpu
= raw_smp_processor_id();
1377 struct vcpu_vmx
*vmx
, *n
;
1379 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1385 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1388 static void kvm_cpu_vmxoff(void)
1390 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1393 static void hardware_disable(void *garbage
)
1395 if (vmm_exclusive
) {
1396 vmclear_local_vcpus();
1399 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1402 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1403 u32 msr
, u32
*result
)
1405 u32 vmx_msr_low
, vmx_msr_high
;
1406 u32 ctl
= ctl_min
| ctl_opt
;
1408 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1410 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1411 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1413 /* Ensure minimum (required) set of control bits are supported. */
1421 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1423 u32 vmx_msr_low
, vmx_msr_high
;
1424 u32 min
, opt
, min2
, opt2
;
1425 u32 _pin_based_exec_control
= 0;
1426 u32 _cpu_based_exec_control
= 0;
1427 u32 _cpu_based_2nd_exec_control
= 0;
1428 u32 _vmexit_control
= 0;
1429 u32 _vmentry_control
= 0;
1431 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1432 opt
= PIN_BASED_VIRTUAL_NMIS
;
1433 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1434 &_pin_based_exec_control
) < 0)
1438 #ifdef CONFIG_X86_64
1439 CPU_BASED_CR8_LOAD_EXITING
|
1440 CPU_BASED_CR8_STORE_EXITING
|
1442 CPU_BASED_CR3_LOAD_EXITING
|
1443 CPU_BASED_CR3_STORE_EXITING
|
1444 CPU_BASED_USE_IO_BITMAPS
|
1445 CPU_BASED_MOV_DR_EXITING
|
1446 CPU_BASED_USE_TSC_OFFSETING
|
1447 CPU_BASED_MWAIT_EXITING
|
1448 CPU_BASED_MONITOR_EXITING
|
1449 CPU_BASED_INVLPG_EXITING
;
1452 min
|= CPU_BASED_HLT_EXITING
;
1454 opt
= CPU_BASED_TPR_SHADOW
|
1455 CPU_BASED_USE_MSR_BITMAPS
|
1456 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1457 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1458 &_cpu_based_exec_control
) < 0)
1460 #ifdef CONFIG_X86_64
1461 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1462 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1463 ~CPU_BASED_CR8_STORE_EXITING
;
1465 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1467 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1468 SECONDARY_EXEC_WBINVD_EXITING
|
1469 SECONDARY_EXEC_ENABLE_VPID
|
1470 SECONDARY_EXEC_ENABLE_EPT
|
1471 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1472 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1473 SECONDARY_EXEC_RDTSCP
;
1474 if (adjust_vmx_controls(min2
, opt2
,
1475 MSR_IA32_VMX_PROCBASED_CTLS2
,
1476 &_cpu_based_2nd_exec_control
) < 0)
1479 #ifndef CONFIG_X86_64
1480 if (!(_cpu_based_2nd_exec_control
&
1481 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1482 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1484 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1485 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1487 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1488 CPU_BASED_CR3_STORE_EXITING
|
1489 CPU_BASED_INVLPG_EXITING
);
1490 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1491 vmx_capability
.ept
, vmx_capability
.vpid
);
1495 #ifdef CONFIG_X86_64
1496 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1498 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1499 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1500 &_vmexit_control
) < 0)
1504 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1505 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1506 &_vmentry_control
) < 0)
1509 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1511 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1512 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1515 #ifdef CONFIG_X86_64
1516 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1517 if (vmx_msr_high
& (1u<<16))
1521 /* Require Write-Back (WB) memory type for VMCS accesses. */
1522 if (((vmx_msr_high
>> 18) & 15) != 6)
1525 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1526 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1527 vmcs_conf
->revision_id
= vmx_msr_low
;
1529 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1530 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1531 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1532 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1533 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1538 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1540 int node
= cpu_to_node(cpu
);
1544 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1547 vmcs
= page_address(pages
);
1548 memset(vmcs
, 0, vmcs_config
.size
);
1549 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1553 static struct vmcs
*alloc_vmcs(void)
1555 return alloc_vmcs_cpu(raw_smp_processor_id());
1558 static void free_vmcs(struct vmcs
*vmcs
)
1560 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1563 static void free_kvm_area(void)
1567 for_each_possible_cpu(cpu
) {
1568 free_vmcs(per_cpu(vmxarea
, cpu
));
1569 per_cpu(vmxarea
, cpu
) = NULL
;
1573 static __init
int alloc_kvm_area(void)
1577 for_each_possible_cpu(cpu
) {
1580 vmcs
= alloc_vmcs_cpu(cpu
);
1586 per_cpu(vmxarea
, cpu
) = vmcs
;
1591 static __init
int hardware_setup(void)
1593 if (setup_vmcs_config(&vmcs_config
) < 0)
1596 if (boot_cpu_has(X86_FEATURE_NX
))
1597 kvm_enable_efer_bits(EFER_NX
);
1599 if (!cpu_has_vmx_vpid())
1602 if (!cpu_has_vmx_ept() ||
1603 !cpu_has_vmx_ept_4levels()) {
1605 enable_unrestricted_guest
= 0;
1608 if (!cpu_has_vmx_unrestricted_guest())
1609 enable_unrestricted_guest
= 0;
1611 if (!cpu_has_vmx_flexpriority())
1612 flexpriority_enabled
= 0;
1614 if (!cpu_has_vmx_tpr_shadow())
1615 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1617 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
1618 kvm_disable_largepages();
1620 if (!cpu_has_vmx_ple())
1623 return alloc_kvm_area();
1626 static __exit
void hardware_unsetup(void)
1631 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1633 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1635 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1636 vmcs_write16(sf
->selector
, save
->selector
);
1637 vmcs_writel(sf
->base
, save
->base
);
1638 vmcs_write32(sf
->limit
, save
->limit
);
1639 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1641 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1643 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1647 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1649 unsigned long flags
;
1650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1652 vmx
->emulation_required
= 1;
1653 vmx
->rmode
.vm86_active
= 0;
1655 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
1656 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
1657 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
1659 flags
= vmcs_readl(GUEST_RFLAGS
);
1660 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1661 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1662 vmcs_writel(GUEST_RFLAGS
, flags
);
1664 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1665 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1667 update_exception_bitmap(vcpu
);
1669 if (emulate_invalid_guest_state
)
1672 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1673 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1674 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1675 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1677 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1678 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1680 vmcs_write16(GUEST_CS_SELECTOR
,
1681 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1682 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1685 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1687 if (!kvm
->arch
.tss_addr
) {
1688 struct kvm_memslots
*slots
;
1691 slots
= kvm_memslots(kvm
);
1692 base_gfn
= slots
->memslots
[0].base_gfn
+
1693 kvm
->memslots
->memslots
[0].npages
- 3;
1694 return base_gfn
<< PAGE_SHIFT
;
1696 return kvm
->arch
.tss_addr
;
1699 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1701 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1703 save
->selector
= vmcs_read16(sf
->selector
);
1704 save
->base
= vmcs_readl(sf
->base
);
1705 save
->limit
= vmcs_read32(sf
->limit
);
1706 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1707 vmcs_write16(sf
->selector
, save
->base
>> 4);
1708 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1709 vmcs_write32(sf
->limit
, 0xffff);
1710 vmcs_write32(sf
->ar_bytes
, 0xf3);
1713 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1715 unsigned long flags
;
1716 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1718 if (enable_unrestricted_guest
)
1721 vmx
->emulation_required
= 1;
1722 vmx
->rmode
.vm86_active
= 1;
1724 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1725 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1727 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1728 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1730 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1731 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1733 flags
= vmcs_readl(GUEST_RFLAGS
);
1734 vmx
->rmode
.save_rflags
= flags
;
1736 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1738 vmcs_writel(GUEST_RFLAGS
, flags
);
1739 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1740 update_exception_bitmap(vcpu
);
1742 if (emulate_invalid_guest_state
)
1743 goto continue_rmode
;
1745 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1746 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1747 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1749 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1750 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1751 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1752 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1753 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1755 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
1756 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
1757 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
1758 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
1761 kvm_mmu_reset_context(vcpu
);
1762 init_rmode(vcpu
->kvm
);
1765 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1767 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1768 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1774 * Force kernel_gs_base reloading before EFER changes, as control
1775 * of this msr depends on is_long_mode().
1777 vmx_load_host_state(to_vmx(vcpu
));
1778 vcpu
->arch
.efer
= efer
;
1779 if (efer
& EFER_LMA
) {
1780 vmcs_write32(VM_ENTRY_CONTROLS
,
1781 vmcs_read32(VM_ENTRY_CONTROLS
) |
1782 VM_ENTRY_IA32E_MODE
);
1785 vmcs_write32(VM_ENTRY_CONTROLS
,
1786 vmcs_read32(VM_ENTRY_CONTROLS
) &
1787 ~VM_ENTRY_IA32E_MODE
);
1789 msr
->data
= efer
& ~EFER_LME
;
1794 #ifdef CONFIG_X86_64
1796 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1800 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1801 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1802 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1804 vmcs_write32(GUEST_TR_AR_BYTES
,
1805 (guest_tr_ar
& ~AR_TYPE_MASK
)
1806 | AR_TYPE_BUSY_64_TSS
);
1808 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
1811 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1813 vmcs_write32(VM_ENTRY_CONTROLS
,
1814 vmcs_read32(VM_ENTRY_CONTROLS
)
1815 & ~VM_ENTRY_IA32E_MODE
);
1816 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
1821 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1823 vpid_sync_context(to_vmx(vcpu
));
1825 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
1827 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1831 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
1833 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
1835 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
1836 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
1839 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1841 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
1843 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
1844 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
1847 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1849 if (!test_bit(VCPU_EXREG_PDPTR
,
1850 (unsigned long *)&vcpu
->arch
.regs_dirty
))
1853 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1854 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
1855 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
1856 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
1857 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
1861 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
1863 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1864 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
1865 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
1866 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
1867 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
1870 __set_bit(VCPU_EXREG_PDPTR
,
1871 (unsigned long *)&vcpu
->arch
.regs_avail
);
1872 __set_bit(VCPU_EXREG_PDPTR
,
1873 (unsigned long *)&vcpu
->arch
.regs_dirty
);
1876 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1878 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1880 struct kvm_vcpu
*vcpu
)
1882 if (!(cr0
& X86_CR0_PG
)) {
1883 /* From paging/starting to nonpaging */
1884 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1885 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1886 (CPU_BASED_CR3_LOAD_EXITING
|
1887 CPU_BASED_CR3_STORE_EXITING
));
1888 vcpu
->arch
.cr0
= cr0
;
1889 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1890 } else if (!is_paging(vcpu
)) {
1891 /* From nonpaging to paging */
1892 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1893 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1894 ~(CPU_BASED_CR3_LOAD_EXITING
|
1895 CPU_BASED_CR3_STORE_EXITING
));
1896 vcpu
->arch
.cr0
= cr0
;
1897 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
1900 if (!(cr0
& X86_CR0_WP
))
1901 *hw_cr0
&= ~X86_CR0_WP
;
1904 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1907 unsigned long hw_cr0
;
1909 if (enable_unrestricted_guest
)
1910 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
1911 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
1913 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
1915 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
1918 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
1921 #ifdef CONFIG_X86_64
1922 if (vcpu
->arch
.efer
& EFER_LME
) {
1923 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1925 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1931 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1933 if (!vcpu
->fpu_active
)
1934 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
1936 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1937 vmcs_writel(GUEST_CR0
, hw_cr0
);
1938 vcpu
->arch
.cr0
= cr0
;
1941 static u64
construct_eptp(unsigned long root_hpa
)
1945 /* TODO write the value reading from MSR */
1946 eptp
= VMX_EPT_DEFAULT_MT
|
1947 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1948 eptp
|= (root_hpa
& PAGE_MASK
);
1953 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1955 unsigned long guest_cr3
;
1960 eptp
= construct_eptp(cr3
);
1961 vmcs_write64(EPT_POINTER
, eptp
);
1962 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1963 vcpu
->kvm
->arch
.ept_identity_map_addr
;
1964 ept_load_pdptrs(vcpu
);
1967 vmx_flush_tlb(vcpu
);
1968 vmcs_writel(GUEST_CR3
, guest_cr3
);
1971 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1973 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
1974 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1976 vcpu
->arch
.cr4
= cr4
;
1978 if (!is_paging(vcpu
)) {
1979 hw_cr4
&= ~X86_CR4_PAE
;
1980 hw_cr4
|= X86_CR4_PSE
;
1981 } else if (!(cr4
& X86_CR4_PAE
)) {
1982 hw_cr4
&= ~X86_CR4_PAE
;
1986 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1987 vmcs_writel(GUEST_CR4
, hw_cr4
);
1990 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1992 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1994 return vmcs_readl(sf
->base
);
1997 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1998 struct kvm_segment
*var
, int seg
)
2000 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2003 var
->base
= vmcs_readl(sf
->base
);
2004 var
->limit
= vmcs_read32(sf
->limit
);
2005 var
->selector
= vmcs_read16(sf
->selector
);
2006 ar
= vmcs_read32(sf
->ar_bytes
);
2007 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2009 var
->type
= ar
& 15;
2010 var
->s
= (ar
>> 4) & 1;
2011 var
->dpl
= (ar
>> 5) & 3;
2012 var
->present
= (ar
>> 7) & 1;
2013 var
->avl
= (ar
>> 12) & 1;
2014 var
->l
= (ar
>> 13) & 1;
2015 var
->db
= (ar
>> 14) & 1;
2016 var
->g
= (ar
>> 15) & 1;
2017 var
->unusable
= (ar
>> 16) & 1;
2020 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2022 if (!is_protmode(vcpu
))
2025 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
2028 return vmcs_read16(GUEST_CS_SELECTOR
) & 3;
2031 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
2038 ar
= var
->type
& 15;
2039 ar
|= (var
->s
& 1) << 4;
2040 ar
|= (var
->dpl
& 3) << 5;
2041 ar
|= (var
->present
& 1) << 7;
2042 ar
|= (var
->avl
& 1) << 12;
2043 ar
|= (var
->l
& 1) << 13;
2044 ar
|= (var
->db
& 1) << 14;
2045 ar
|= (var
->g
& 1) << 15;
2047 if (ar
== 0) /* a 0 value means unusable */
2048 ar
= AR_UNUSABLE_MASK
;
2053 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
2054 struct kvm_segment
*var
, int seg
)
2056 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2057 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2060 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2061 vmx
->rmode
.tr
.selector
= var
->selector
;
2062 vmx
->rmode
.tr
.base
= var
->base
;
2063 vmx
->rmode
.tr
.limit
= var
->limit
;
2064 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2067 vmcs_writel(sf
->base
, var
->base
);
2068 vmcs_write32(sf
->limit
, var
->limit
);
2069 vmcs_write16(sf
->selector
, var
->selector
);
2070 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2072 * Hack real-mode segments into vm86 compatibility.
2074 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2075 vmcs_writel(sf
->base
, 0xf0000);
2078 ar
= vmx_segment_access_rights(var
);
2081 * Fix the "Accessed" bit in AR field of segment registers for older
2083 * IA32 arch specifies that at the time of processor reset the
2084 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2085 * is setting it to 0 in the usedland code. This causes invalid guest
2086 * state vmexit when "unrestricted guest" mode is turned on.
2087 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2088 * tree. Newer qemu binaries with that qemu fix would not need this
2091 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2092 ar
|= 0x1; /* Accessed */
2094 vmcs_write32(sf
->ar_bytes
, ar
);
2097 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2099 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
2101 *db
= (ar
>> 14) & 1;
2102 *l
= (ar
>> 13) & 1;
2105 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2107 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2108 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2111 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2113 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
2114 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
2117 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2119 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
2120 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
2123 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2125 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
2126 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
2129 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2131 struct kvm_segment var
;
2134 vmx_get_segment(vcpu
, &var
, seg
);
2135 ar
= vmx_segment_access_rights(&var
);
2137 if (var
.base
!= (var
.selector
<< 4))
2139 if (var
.limit
!= 0xffff)
2147 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
2149 struct kvm_segment cs
;
2150 unsigned int cs_rpl
;
2152 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2153 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
2157 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
2161 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
2162 if (cs
.dpl
> cs_rpl
)
2165 if (cs
.dpl
!= cs_rpl
)
2171 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2175 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2177 struct kvm_segment ss
;
2178 unsigned int ss_rpl
;
2180 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2181 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2185 if (ss
.type
!= 3 && ss
.type
!= 7)
2189 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2197 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2199 struct kvm_segment var
;
2202 vmx_get_segment(vcpu
, &var
, seg
);
2203 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2211 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2212 if (var
.dpl
< rpl
) /* DPL < RPL */
2216 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2222 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2224 struct kvm_segment tr
;
2226 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2230 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2232 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2240 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2242 struct kvm_segment ldtr
;
2244 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2248 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2258 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2260 struct kvm_segment cs
, ss
;
2262 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2263 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2265 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2266 (ss
.selector
& SELECTOR_RPL_MASK
));
2270 * Check if guest state is valid. Returns true if valid, false if
2272 * We assume that registers are always usable
2274 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2276 /* real mode guest state checks */
2277 if (!is_protmode(vcpu
)) {
2278 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2280 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2282 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2284 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2286 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2288 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2291 /* protected mode guest state checks */
2292 if (!cs_ss_rpl_check(vcpu
))
2294 if (!code_segment_valid(vcpu
))
2296 if (!stack_segment_valid(vcpu
))
2298 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2300 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2302 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2304 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2306 if (!tr_valid(vcpu
))
2308 if (!ldtr_valid(vcpu
))
2312 * - Add checks on RIP
2313 * - Add checks on RFLAGS
2319 static int init_rmode_tss(struct kvm
*kvm
)
2321 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2326 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2329 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2330 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2331 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2334 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2337 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2341 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2342 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2352 static int init_rmode_identity_map(struct kvm
*kvm
)
2355 pfn_t identity_map_pfn
;
2360 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2361 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2362 "haven't been allocated!\n");
2365 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2368 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2369 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2372 /* Set up identity-mapping pagetable for EPT in real mode */
2373 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2374 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2375 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2376 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2377 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2381 kvm
->arch
.ept_identity_pagetable_done
= true;
2387 static void seg_setup(int seg
)
2389 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2392 vmcs_write16(sf
->selector
, 0);
2393 vmcs_writel(sf
->base
, 0);
2394 vmcs_write32(sf
->limit
, 0xffff);
2395 if (enable_unrestricted_guest
) {
2397 if (seg
== VCPU_SREG_CS
)
2398 ar
|= 0x08; /* code segment */
2402 vmcs_write32(sf
->ar_bytes
, ar
);
2405 static int alloc_apic_access_page(struct kvm
*kvm
)
2407 struct kvm_userspace_memory_region kvm_userspace_mem
;
2410 mutex_lock(&kvm
->slots_lock
);
2411 if (kvm
->arch
.apic_access_page
)
2413 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2414 kvm_userspace_mem
.flags
= 0;
2415 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2416 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2417 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2421 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2423 mutex_unlock(&kvm
->slots_lock
);
2427 static int alloc_identity_pagetable(struct kvm
*kvm
)
2429 struct kvm_userspace_memory_region kvm_userspace_mem
;
2432 mutex_lock(&kvm
->slots_lock
);
2433 if (kvm
->arch
.ept_identity_pagetable
)
2435 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2436 kvm_userspace_mem
.flags
= 0;
2437 kvm_userspace_mem
.guest_phys_addr
=
2438 kvm
->arch
.ept_identity_map_addr
;
2439 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2440 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2444 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2445 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
2447 mutex_unlock(&kvm
->slots_lock
);
2451 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2458 spin_lock(&vmx_vpid_lock
);
2459 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2460 if (vpid
< VMX_NR_VPIDS
) {
2462 __set_bit(vpid
, vmx_vpid_bitmap
);
2464 spin_unlock(&vmx_vpid_lock
);
2467 static void free_vpid(struct vcpu_vmx
*vmx
)
2471 spin_lock(&vmx_vpid_lock
);
2473 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
2474 spin_unlock(&vmx_vpid_lock
);
2477 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2479 int f
= sizeof(unsigned long);
2481 if (!cpu_has_vmx_msr_bitmap())
2485 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2486 * have the write-low and read-high bitmap offsets the wrong way round.
2487 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2489 if (msr
<= 0x1fff) {
2490 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2491 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2492 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2494 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2495 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2499 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2502 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2503 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2507 * Sets up the vmcs for emulated real mode.
2509 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2511 u32 host_sysenter_cs
, msr_low
, msr_high
;
2517 unsigned long kvm_vmx_return
;
2521 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2522 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2524 if (cpu_has_vmx_msr_bitmap())
2525 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2527 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2530 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2531 vmcs_config
.pin_based_exec_ctrl
);
2533 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2534 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2535 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2536 #ifdef CONFIG_X86_64
2537 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2538 CPU_BASED_CR8_LOAD_EXITING
;
2542 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2543 CPU_BASED_CR3_LOAD_EXITING
|
2544 CPU_BASED_INVLPG_EXITING
;
2545 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2547 if (cpu_has_secondary_exec_ctrls()) {
2548 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2549 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2551 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2553 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2555 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2556 enable_unrestricted_guest
= 0;
2558 if (!enable_unrestricted_guest
)
2559 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2561 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
2562 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2566 vmcs_write32(PLE_GAP
, ple_gap
);
2567 vmcs_write32(PLE_WINDOW
, ple_window
);
2570 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2571 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2572 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2574 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
2575 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2576 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2578 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2579 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2580 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2581 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
2582 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
2583 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2584 #ifdef CONFIG_X86_64
2585 rdmsrl(MSR_FS_BASE
, a
);
2586 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2587 rdmsrl(MSR_GS_BASE
, a
);
2588 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2590 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2591 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2594 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2596 native_store_idt(&dt
);
2597 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
2599 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2600 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2601 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2602 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2603 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
2604 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2605 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
2607 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2608 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2609 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2610 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2611 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2612 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2614 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2615 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2616 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2617 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2619 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2620 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2621 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2622 /* Write the default value follow host pat */
2623 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2624 /* Keep arch.pat sync with GUEST_IA32_PAT */
2625 vmx
->vcpu
.arch
.pat
= host_pat
;
2628 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2629 u32 index
= vmx_msr_index
[i
];
2630 u32 data_low
, data_high
;
2633 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2635 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2637 vmx
->guest_msrs
[j
].index
= i
;
2638 vmx
->guest_msrs
[j
].data
= 0;
2639 vmx
->guest_msrs
[j
].mask
= -1ull;
2643 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2645 /* 22.2.1, 20.8.1 */
2646 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2648 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2649 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
2651 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
2652 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
2654 kvm_write_tsc(&vmx
->vcpu
, 0);
2659 static int init_rmode(struct kvm
*kvm
)
2663 idx
= srcu_read_lock(&kvm
->srcu
);
2664 if (!init_rmode_tss(kvm
))
2666 if (!init_rmode_identity_map(kvm
))
2671 srcu_read_unlock(&kvm
->srcu
, idx
);
2675 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2681 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2682 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2687 vmx
->rmode
.vm86_active
= 0;
2689 vmx
->soft_vnmi_blocked
= 0;
2691 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2692 kvm_set_cr8(&vmx
->vcpu
, 0);
2693 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2694 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2695 msr
|= MSR_IA32_APICBASE_BSP
;
2696 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2698 ret
= fx_init(&vmx
->vcpu
);
2702 seg_setup(VCPU_SREG_CS
);
2704 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2705 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2707 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
2708 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2709 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2711 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2712 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2715 seg_setup(VCPU_SREG_DS
);
2716 seg_setup(VCPU_SREG_ES
);
2717 seg_setup(VCPU_SREG_FS
);
2718 seg_setup(VCPU_SREG_GS
);
2719 seg_setup(VCPU_SREG_SS
);
2721 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2722 vmcs_writel(GUEST_TR_BASE
, 0);
2723 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2724 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2726 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2727 vmcs_writel(GUEST_LDTR_BASE
, 0);
2728 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2729 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2731 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2732 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2733 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2735 vmcs_writel(GUEST_RFLAGS
, 0x02);
2736 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
2737 kvm_rip_write(vcpu
, 0xfff0);
2739 kvm_rip_write(vcpu
, 0);
2740 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2742 vmcs_writel(GUEST_DR7
, 0x400);
2744 vmcs_writel(GUEST_GDTR_BASE
, 0);
2745 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2747 vmcs_writel(GUEST_IDTR_BASE
, 0);
2748 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2750 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
2751 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2752 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2754 /* Special registers */
2755 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2759 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2761 if (cpu_has_vmx_tpr_shadow()) {
2762 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2763 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2764 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2765 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2766 vmcs_write32(TPR_THRESHOLD
, 0);
2769 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2770 vmcs_write64(APIC_ACCESS_ADDR
,
2771 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2774 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2776 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
2777 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
2778 vmx_set_cr4(&vmx
->vcpu
, 0);
2779 vmx_set_efer(&vmx
->vcpu
, 0);
2780 vmx_fpu_activate(&vmx
->vcpu
);
2781 update_exception_bitmap(&vmx
->vcpu
);
2783 vpid_sync_context(vmx
);
2787 /* HACK: Don't enable emulation on guest boot/reset */
2788 vmx
->emulation_required
= 0;
2794 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2796 u32 cpu_based_vm_exec_control
;
2798 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2799 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2800 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2803 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2805 u32 cpu_based_vm_exec_control
;
2807 if (!cpu_has_virtual_nmis()) {
2808 enable_irq_window(vcpu
);
2812 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
2813 enable_irq_window(vcpu
);
2816 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2817 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2818 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2821 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2823 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2825 int irq
= vcpu
->arch
.interrupt
.nr
;
2827 trace_kvm_inj_virq(irq
);
2829 ++vcpu
->stat
.irq_injections
;
2830 if (vmx
->rmode
.vm86_active
) {
2831 if (kvm_inject_realmode_interrupt(vcpu
, irq
) != EMULATE_DONE
)
2832 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2835 intr
= irq
| INTR_INFO_VALID_MASK
;
2836 if (vcpu
->arch
.interrupt
.soft
) {
2837 intr
|= INTR_TYPE_SOFT_INTR
;
2838 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2839 vmx
->vcpu
.arch
.event_exit_inst_len
);
2841 intr
|= INTR_TYPE_EXT_INTR
;
2842 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2843 vmx_clear_hlt(vcpu
);
2846 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2848 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2850 if (!cpu_has_virtual_nmis()) {
2852 * Tracking the NMI-blocked state in software is built upon
2853 * finding the next open IRQ window. This, in turn, depends on
2854 * well-behaving guests: They have to keep IRQs disabled at
2855 * least as long as the NMI handler runs. Otherwise we may
2856 * cause NMI nesting, maybe breaking the guest. But as this is
2857 * highly unlikely, we can live with the residual risk.
2859 vmx
->soft_vnmi_blocked
= 1;
2860 vmx
->vnmi_blocked_time
= 0;
2863 ++vcpu
->stat
.nmi_injections
;
2864 if (vmx
->rmode
.vm86_active
) {
2865 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
) != EMULATE_DONE
)
2866 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2870 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2871 vmx_clear_hlt(vcpu
);
2874 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2876 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2879 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2880 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
2881 | GUEST_INTR_STATE_NMI
));
2884 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
2886 if (!cpu_has_virtual_nmis())
2887 return to_vmx(vcpu
)->soft_vnmi_blocked
;
2888 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
2891 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
2893 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2895 if (!cpu_has_virtual_nmis()) {
2896 if (vmx
->soft_vnmi_blocked
!= masked
) {
2897 vmx
->soft_vnmi_blocked
= masked
;
2898 vmx
->vnmi_blocked_time
= 0;
2902 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
2903 GUEST_INTR_STATE_NMI
);
2905 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
2906 GUEST_INTR_STATE_NMI
);
2910 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2912 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2913 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2914 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2917 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2920 struct kvm_userspace_memory_region tss_mem
= {
2921 .slot
= TSS_PRIVATE_MEMSLOT
,
2922 .guest_phys_addr
= addr
,
2923 .memory_size
= PAGE_SIZE
* 3,
2927 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2930 kvm
->arch
.tss_addr
= addr
;
2934 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2935 int vec
, u32 err_code
)
2938 * Instruction with address size override prefix opcode 0x67
2939 * Cause the #SS fault with 0 error code in VM86 mode.
2941 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2942 if (emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
)
2945 * Forward all other exceptions that are valid in real mode.
2946 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2947 * the required debugging infrastructure rework.
2951 if (vcpu
->guest_debug
&
2952 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2954 kvm_queue_exception(vcpu
, vec
);
2958 * Update instruction length as we may reinject the exception
2959 * from user space while in guest debugging mode.
2961 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
2962 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2963 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2974 kvm_queue_exception(vcpu
, vec
);
2981 * Trigger machine check on the host. We assume all the MSRs are already set up
2982 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2983 * We pass a fake environment to the machine check handler because we want
2984 * the guest to be always treated like user space, no matter what context
2985 * it used internally.
2987 static void kvm_machine_check(void)
2989 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2990 struct pt_regs regs
= {
2991 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
2992 .flags
= X86_EFLAGS_IF
,
2995 do_machine_check(®s
, 0);
2999 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
3001 /* already handled by vcpu_run */
3005 static int handle_exception(struct kvm_vcpu
*vcpu
)
3007 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3008 struct kvm_run
*kvm_run
= vcpu
->run
;
3009 u32 intr_info
, ex_no
, error_code
;
3010 unsigned long cr2
, rip
, dr6
;
3012 enum emulation_result er
;
3014 vect_info
= vmx
->idt_vectoring_info
;
3015 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3017 if (is_machine_check(intr_info
))
3018 return handle_machine_check(vcpu
);
3020 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
3021 !is_page_fault(intr_info
)) {
3022 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3023 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
3024 vcpu
->run
->internal
.ndata
= 2;
3025 vcpu
->run
->internal
.data
[0] = vect_info
;
3026 vcpu
->run
->internal
.data
[1] = intr_info
;
3030 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
3031 return 1; /* already handled by vmx_vcpu_run() */
3033 if (is_no_device(intr_info
)) {
3034 vmx_fpu_activate(vcpu
);
3038 if (is_invalid_opcode(intr_info
)) {
3039 er
= emulate_instruction(vcpu
, 0, 0, EMULTYPE_TRAP_UD
);
3040 if (er
!= EMULATE_DONE
)
3041 kvm_queue_exception(vcpu
, UD_VECTOR
);
3046 rip
= kvm_rip_read(vcpu
);
3047 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
3048 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
3049 if (is_page_fault(intr_info
)) {
3050 /* EPT won't cause page fault directly */
3053 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3054 trace_kvm_page_fault(cr2
, error_code
);
3056 if (kvm_event_needs_reinjection(vcpu
))
3057 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3058 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
3061 if (vmx
->rmode
.vm86_active
&&
3062 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3064 if (vcpu
->arch
.halt_request
) {
3065 vcpu
->arch
.halt_request
= 0;
3066 return kvm_emulate_halt(vcpu
);
3071 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3074 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3075 if (!(vcpu
->guest_debug
&
3076 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3077 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3078 kvm_queue_exception(vcpu
, DB_VECTOR
);
3081 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3082 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3086 * Update instruction length as we may reinject #BP from
3087 * user space while in guest debugging mode. Reading it for
3088 * #DB as well causes no harm, it is not used in that case.
3090 vmx
->vcpu
.arch
.event_exit_inst_len
=
3091 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3092 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3093 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3094 kvm_run
->debug
.arch
.exception
= ex_no
;
3097 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3098 kvm_run
->ex
.exception
= ex_no
;
3099 kvm_run
->ex
.error_code
= error_code
;
3105 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3107 ++vcpu
->stat
.irq_exits
;
3111 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3113 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
3117 static int handle_io(struct kvm_vcpu
*vcpu
)
3119 unsigned long exit_qualification
;
3120 int size
, in
, string
;
3123 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3124 string
= (exit_qualification
& 16) != 0;
3125 in
= (exit_qualification
& 8) != 0;
3127 ++vcpu
->stat
.io_exits
;
3130 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
3132 port
= exit_qualification
>> 16;
3133 size
= (exit_qualification
& 7) + 1;
3134 skip_emulated_instruction(vcpu
);
3136 return kvm_fast_pio_out(vcpu
, size
, port
);
3140 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3143 * Patch in the VMCALL instruction:
3145 hypercall
[0] = 0x0f;
3146 hypercall
[1] = 0x01;
3147 hypercall
[2] = 0xc1;
3150 static void complete_insn_gp(struct kvm_vcpu
*vcpu
, int err
)
3153 kvm_inject_gp(vcpu
, 0);
3155 skip_emulated_instruction(vcpu
);
3158 static int handle_cr(struct kvm_vcpu
*vcpu
)
3160 unsigned long exit_qualification
, val
;
3165 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3166 cr
= exit_qualification
& 15;
3167 reg
= (exit_qualification
>> 8) & 15;
3168 switch ((exit_qualification
>> 4) & 3) {
3169 case 0: /* mov to cr */
3170 val
= kvm_register_read(vcpu
, reg
);
3171 trace_kvm_cr_write(cr
, val
);
3174 err
= kvm_set_cr0(vcpu
, val
);
3175 complete_insn_gp(vcpu
, err
);
3178 err
= kvm_set_cr3(vcpu
, val
);
3179 complete_insn_gp(vcpu
, err
);
3182 err
= kvm_set_cr4(vcpu
, val
);
3183 complete_insn_gp(vcpu
, err
);
3186 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3187 u8 cr8
= kvm_register_read(vcpu
, reg
);
3188 err
= kvm_set_cr8(vcpu
, cr8
);
3189 complete_insn_gp(vcpu
, err
);
3190 if (irqchip_in_kernel(vcpu
->kvm
))
3192 if (cr8_prev
<= cr8
)
3194 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3200 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3201 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3202 skip_emulated_instruction(vcpu
);
3203 vmx_fpu_activate(vcpu
);
3205 case 1: /*mov from cr*/
3208 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
3209 trace_kvm_cr_read(cr
, vcpu
->arch
.cr3
);
3210 skip_emulated_instruction(vcpu
);
3213 val
= kvm_get_cr8(vcpu
);
3214 kvm_register_write(vcpu
, reg
, val
);
3215 trace_kvm_cr_read(cr
, val
);
3216 skip_emulated_instruction(vcpu
);
3221 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3222 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3223 kvm_lmsw(vcpu
, val
);
3225 skip_emulated_instruction(vcpu
);
3230 vcpu
->run
->exit_reason
= 0;
3231 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3232 (int)(exit_qualification
>> 4) & 3, cr
);
3236 static int handle_dr(struct kvm_vcpu
*vcpu
)
3238 unsigned long exit_qualification
;
3241 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3242 if (!kvm_require_cpl(vcpu
, 0))
3244 dr
= vmcs_readl(GUEST_DR7
);
3247 * As the vm-exit takes precedence over the debug trap, we
3248 * need to emulate the latter, either for the host or the
3249 * guest debugging itself.
3251 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3252 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3253 vcpu
->run
->debug
.arch
.dr7
= dr
;
3254 vcpu
->run
->debug
.arch
.pc
=
3255 vmcs_readl(GUEST_CS_BASE
) +
3256 vmcs_readl(GUEST_RIP
);
3257 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3258 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3261 vcpu
->arch
.dr7
&= ~DR7_GD
;
3262 vcpu
->arch
.dr6
|= DR6_BD
;
3263 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3264 kvm_queue_exception(vcpu
, DB_VECTOR
);
3269 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3270 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3271 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3272 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3274 if (!kvm_get_dr(vcpu
, dr
, &val
))
3275 kvm_register_write(vcpu
, reg
, val
);
3277 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
3278 skip_emulated_instruction(vcpu
);
3282 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
3284 vmcs_writel(GUEST_DR7
, val
);
3287 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3289 kvm_emulate_cpuid(vcpu
);
3293 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3295 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3298 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3299 trace_kvm_msr_read_ex(ecx
);
3300 kvm_inject_gp(vcpu
, 0);
3304 trace_kvm_msr_read(ecx
, data
);
3306 /* FIXME: handling of bits 32:63 of rax, rdx */
3307 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3308 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3309 skip_emulated_instruction(vcpu
);
3313 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3315 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3316 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3317 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3319 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3320 trace_kvm_msr_write_ex(ecx
, data
);
3321 kvm_inject_gp(vcpu
, 0);
3325 trace_kvm_msr_write(ecx
, data
);
3326 skip_emulated_instruction(vcpu
);
3330 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3332 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3336 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3338 u32 cpu_based_vm_exec_control
;
3340 /* clear pending irq */
3341 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3342 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3345 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3347 ++vcpu
->stat
.irq_window_exits
;
3350 * If the user space waits to inject interrupts, exit as soon as
3353 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3354 vcpu
->run
->request_interrupt_window
&&
3355 !kvm_cpu_has_interrupt(vcpu
)) {
3356 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3362 static int handle_halt(struct kvm_vcpu
*vcpu
)
3364 skip_emulated_instruction(vcpu
);
3365 return kvm_emulate_halt(vcpu
);
3368 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3370 skip_emulated_instruction(vcpu
);
3371 kvm_emulate_hypercall(vcpu
);
3375 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3377 kvm_queue_exception(vcpu
, UD_VECTOR
);
3381 static int handle_invd(struct kvm_vcpu
*vcpu
)
3383 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
3386 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3388 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3390 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3391 skip_emulated_instruction(vcpu
);
3395 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3397 skip_emulated_instruction(vcpu
);
3398 kvm_emulate_wbinvd(vcpu
);
3402 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
3404 u64 new_bv
= kvm_read_edx_eax(vcpu
);
3405 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
3407 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
3408 skip_emulated_instruction(vcpu
);
3412 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3414 return emulate_instruction(vcpu
, 0, 0, 0) == EMULATE_DONE
;
3417 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3419 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3420 unsigned long exit_qualification
;
3421 bool has_error_code
= false;
3424 int reason
, type
, idt_v
;
3426 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3427 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3429 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3431 reason
= (u32
)exit_qualification
>> 30;
3432 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3434 case INTR_TYPE_NMI_INTR
:
3435 vcpu
->arch
.nmi_injected
= false;
3436 if (cpu_has_virtual_nmis())
3437 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3438 GUEST_INTR_STATE_NMI
);
3440 case INTR_TYPE_EXT_INTR
:
3441 case INTR_TYPE_SOFT_INTR
:
3442 kvm_clear_interrupt_queue(vcpu
);
3444 case INTR_TYPE_HARD_EXCEPTION
:
3445 if (vmx
->idt_vectoring_info
&
3446 VECTORING_INFO_DELIVER_CODE_MASK
) {
3447 has_error_code
= true;
3449 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3452 case INTR_TYPE_SOFT_EXCEPTION
:
3453 kvm_clear_exception_queue(vcpu
);
3459 tss_selector
= exit_qualification
;
3461 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3462 type
!= INTR_TYPE_EXT_INTR
&&
3463 type
!= INTR_TYPE_NMI_INTR
))
3464 skip_emulated_instruction(vcpu
);
3466 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
3467 has_error_code
, error_code
) == EMULATE_FAIL
) {
3468 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3469 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
3470 vcpu
->run
->internal
.ndata
= 0;
3474 /* clear all local breakpoint enable flags */
3475 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3478 * TODO: What about debug traps on tss switch?
3479 * Are we supposed to inject them and update dr6?
3485 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
3487 unsigned long exit_qualification
;
3491 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3493 if (exit_qualification
& (1 << 6)) {
3494 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3498 gla_validity
= (exit_qualification
>> 7) & 0x3;
3499 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3500 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3501 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3502 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3503 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3504 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3505 (long unsigned int)exit_qualification
);
3506 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3507 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
3511 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3512 trace_kvm_page_fault(gpa
, exit_qualification
);
3513 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3);
3516 static u64
ept_rsvd_mask(u64 spte
, int level
)
3521 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
3522 mask
|= (1ULL << i
);
3525 /* bits 7:3 reserved */
3527 else if (level
== 2) {
3528 if (spte
& (1ULL << 7))
3529 /* 2MB ref, bits 20:12 reserved */
3532 /* bits 6:3 reserved */
3539 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
3542 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
3544 /* 010b (write-only) */
3545 WARN_ON((spte
& 0x7) == 0x2);
3547 /* 110b (write/execute) */
3548 WARN_ON((spte
& 0x7) == 0x6);
3550 /* 100b (execute-only) and value not supported by logical processor */
3551 if (!cpu_has_vmx_ept_execute_only())
3552 WARN_ON((spte
& 0x7) == 0x4);
3556 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
3558 if (rsvd_bits
!= 0) {
3559 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
3560 __func__
, rsvd_bits
);
3564 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
3565 u64 ept_mem_type
= (spte
& 0x38) >> 3;
3567 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
3568 ept_mem_type
== 7) {
3569 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
3570 __func__
, ept_mem_type
);
3577 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
3583 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3585 printk(KERN_ERR
"EPT: Misconfiguration.\n");
3586 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
3588 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
3590 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
3591 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
3593 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3594 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
3599 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
3601 u32 cpu_based_vm_exec_control
;
3603 /* clear pending NMI */
3604 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3605 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3606 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3607 ++vcpu
->stat
.nmi_window_exits
;
3608 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3613 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
3615 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3616 enum emulation_result err
= EMULATE_DONE
;
3619 bool intr_window_requested
;
3621 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3622 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
3624 while (!guest_state_valid(vcpu
)) {
3625 if (intr_window_requested
3626 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
3627 return handle_interrupt_window(&vmx
->vcpu
);
3629 err
= emulate_instruction(vcpu
, 0, 0, 0);
3631 if (err
== EMULATE_DO_MMIO
) {
3636 if (err
!= EMULATE_DONE
)
3639 if (signal_pending(current
))
3645 vmx
->emulation_required
= 0;
3651 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3652 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3654 static int handle_pause(struct kvm_vcpu
*vcpu
)
3656 skip_emulated_instruction(vcpu
);
3657 kvm_vcpu_on_spin(vcpu
);
3662 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
3664 kvm_queue_exception(vcpu
, UD_VECTOR
);
3669 * The exit handlers return 1 if the exit was handled fully and guest execution
3670 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3671 * to be done to userspace and return 0.
3673 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
3674 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3675 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3676 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3677 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3678 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3679 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3680 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3681 [EXIT_REASON_CPUID
] = handle_cpuid
,
3682 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3683 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3684 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3685 [EXIT_REASON_HLT
] = handle_halt
,
3686 [EXIT_REASON_INVD
] = handle_invd
,
3687 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3688 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3689 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
3690 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
3691 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
3692 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
3693 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
3694 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
3695 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
3696 [EXIT_REASON_VMOFF
] = handle_vmx_insn
,
3697 [EXIT_REASON_VMON
] = handle_vmx_insn
,
3698 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3699 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3700 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3701 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
3702 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3703 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
3704 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3705 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
3706 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
3707 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
3708 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
3711 static const int kvm_vmx_max_exit_handlers
=
3712 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3714 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
3716 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
3717 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
3721 * The guest has exited. See if we can fix it or if we need userspace
3724 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
3726 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3727 u32 exit_reason
= vmx
->exit_reason
;
3728 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3730 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
3732 /* If guest state is invalid, start emulating */
3733 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3734 return handle_invalid_guest_state(vcpu
);
3736 /* Access CR3 don't cause VMExit in paging mode, so we need
3737 * to sync with guest real CR3. */
3738 if (enable_ept
&& is_paging(vcpu
))
3739 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3741 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
3742 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3743 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3748 if (unlikely(vmx
->fail
)) {
3749 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3750 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
3751 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3755 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3756 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3757 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3758 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3759 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3760 "(0x%x) and exit reason is 0x%x\n",
3761 __func__
, vectoring_info
, exit_reason
);
3763 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3764 if (vmx_interrupt_allowed(vcpu
)) {
3765 vmx
->soft_vnmi_blocked
= 0;
3766 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3767 vcpu
->arch
.nmi_pending
) {
3769 * This CPU don't support us in finding the end of an
3770 * NMI-blocked window if the guest runs with IRQs
3771 * disabled. So we pull the trigger after 1 s of
3772 * futile waiting, but inform the user about this.
3774 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3775 "state on VCPU %d after 1 s timeout\n",
3776 __func__
, vcpu
->vcpu_id
);
3777 vmx
->soft_vnmi_blocked
= 0;
3781 if (exit_reason
< kvm_vmx_max_exit_handlers
3782 && kvm_vmx_exit_handlers
[exit_reason
])
3783 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
3785 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3786 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
3791 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3793 if (irr
== -1 || tpr
< irr
) {
3794 vmcs_write32(TPR_THRESHOLD
, 0);
3798 vmcs_write32(TPR_THRESHOLD
, irr
);
3801 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
3803 u32 exit_intr_info
= vmx
->exit_intr_info
;
3805 /* Handle machine checks before interrupts are enabled */
3806 if ((vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
)
3807 || (vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
3808 && is_machine_check(exit_intr_info
)))
3809 kvm_machine_check();
3811 /* We need to handle NMIs before interrupts are enabled */
3812 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3813 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
3814 kvm_before_handle_nmi(&vmx
->vcpu
);
3816 kvm_after_handle_nmi(&vmx
->vcpu
);
3820 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
3822 u32 exit_intr_info
= vmx
->exit_intr_info
;
3825 bool idtv_info_valid
;
3827 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3829 if (cpu_has_virtual_nmis()) {
3830 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3831 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3833 * SDM 3: 27.7.1.2 (September 2008)
3834 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3835 * a guest IRET fault.
3836 * SDM 3: 23.2.2 (September 2008)
3837 * Bit 12 is undefined in any of the following cases:
3838 * If the VM exit sets the valid bit in the IDT-vectoring
3839 * information field.
3840 * If the VM exit is due to a double fault.
3842 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3843 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3844 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3845 GUEST_INTR_STATE_NMI
);
3846 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3847 vmx
->vnmi_blocked_time
+=
3848 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3851 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
3852 u32 idt_vectoring_info
,
3853 int instr_len_field
,
3854 int error_code_field
)
3858 bool idtv_info_valid
;
3860 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3862 vmx
->vcpu
.arch
.nmi_injected
= false;
3863 kvm_clear_exception_queue(&vmx
->vcpu
);
3864 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3866 if (!idtv_info_valid
)
3869 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
3871 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3872 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3875 case INTR_TYPE_NMI_INTR
:
3876 vmx
->vcpu
.arch
.nmi_injected
= true;
3878 * SDM 3: 27.7.1.2 (September 2008)
3879 * Clear bit "block by NMI" before VM entry if a NMI
3882 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3883 GUEST_INTR_STATE_NMI
);
3885 case INTR_TYPE_SOFT_EXCEPTION
:
3886 vmx
->vcpu
.arch
.event_exit_inst_len
=
3887 vmcs_read32(instr_len_field
);
3889 case INTR_TYPE_HARD_EXCEPTION
:
3890 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3891 u32 err
= vmcs_read32(error_code_field
);
3892 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3894 kvm_queue_exception(&vmx
->vcpu
, vector
);
3896 case INTR_TYPE_SOFT_INTR
:
3897 vmx
->vcpu
.arch
.event_exit_inst_len
=
3898 vmcs_read32(instr_len_field
);
3900 case INTR_TYPE_EXT_INTR
:
3901 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3902 type
== INTR_TYPE_SOFT_INTR
);
3909 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3911 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
3912 VM_EXIT_INSTRUCTION_LEN
,
3913 IDT_VECTORING_ERROR_CODE
);
3916 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
3918 __vmx_complete_interrupts(to_vmx(vcpu
),
3919 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
3920 VM_ENTRY_INSTRUCTION_LEN
,
3921 VM_ENTRY_EXCEPTION_ERROR_CODE
);
3923 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
3926 #ifdef CONFIG_X86_64
3934 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
3936 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3938 /* Record the guest's net vcpu time for enforced NMI injections. */
3939 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3940 vmx
->entry_time
= ktime_get();
3942 /* Don't enter VMX if guest state is invalid, let the exit handler
3943 start emulation until we arrive back to a valid state */
3944 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
3947 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3948 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3949 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3950 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3952 /* When single-stepping over STI and MOV SS, we must clear the
3953 * corresponding interruptibility bits in the guest state. Otherwise
3954 * vmentry fails as it then expects bit 14 (BS) in pending debug
3955 * exceptions being set, but that's not correct for the guest debugging
3957 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
3958 vmx_set_interrupt_shadow(vcpu
, 0);
3961 /* Store host registers */
3962 "push %%"R
"dx; push %%"R
"bp;"
3964 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3966 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3967 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3969 /* Reload cr2 if changed */
3970 "mov %c[cr2](%0), %%"R
"ax \n\t"
3971 "mov %%cr2, %%"R
"dx \n\t"
3972 "cmp %%"R
"ax, %%"R
"dx \n\t"
3974 "mov %%"R
"ax, %%cr2 \n\t"
3976 /* Check if vmlaunch of vmresume is needed */
3977 "cmpl $0, %c[launched](%0) \n\t"
3978 /* Load guest registers. Don't clobber flags. */
3979 "mov %c[rax](%0), %%"R
"ax \n\t"
3980 "mov %c[rbx](%0), %%"R
"bx \n\t"
3981 "mov %c[rdx](%0), %%"R
"dx \n\t"
3982 "mov %c[rsi](%0), %%"R
"si \n\t"
3983 "mov %c[rdi](%0), %%"R
"di \n\t"
3984 "mov %c[rbp](%0), %%"R
"bp \n\t"
3985 #ifdef CONFIG_X86_64
3986 "mov %c[r8](%0), %%r8 \n\t"
3987 "mov %c[r9](%0), %%r9 \n\t"
3988 "mov %c[r10](%0), %%r10 \n\t"
3989 "mov %c[r11](%0), %%r11 \n\t"
3990 "mov %c[r12](%0), %%r12 \n\t"
3991 "mov %c[r13](%0), %%r13 \n\t"
3992 "mov %c[r14](%0), %%r14 \n\t"
3993 "mov %c[r15](%0), %%r15 \n\t"
3995 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3997 /* Enter guest mode */
3998 "jne .Llaunched \n\t"
3999 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
4000 "jmp .Lkvm_vmx_return \n\t"
4001 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
4002 ".Lkvm_vmx_return: "
4003 /* Save guest registers, load host registers, keep flags */
4004 "xchg %0, (%%"R
"sp) \n\t"
4005 "mov %%"R
"ax, %c[rax](%0) \n\t"
4006 "mov %%"R
"bx, %c[rbx](%0) \n\t"
4007 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
4008 "mov %%"R
"dx, %c[rdx](%0) \n\t"
4009 "mov %%"R
"si, %c[rsi](%0) \n\t"
4010 "mov %%"R
"di, %c[rdi](%0) \n\t"
4011 "mov %%"R
"bp, %c[rbp](%0) \n\t"
4012 #ifdef CONFIG_X86_64
4013 "mov %%r8, %c[r8](%0) \n\t"
4014 "mov %%r9, %c[r9](%0) \n\t"
4015 "mov %%r10, %c[r10](%0) \n\t"
4016 "mov %%r11, %c[r11](%0) \n\t"
4017 "mov %%r12, %c[r12](%0) \n\t"
4018 "mov %%r13, %c[r13](%0) \n\t"
4019 "mov %%r14, %c[r14](%0) \n\t"
4020 "mov %%r15, %c[r15](%0) \n\t"
4022 "mov %%cr2, %%"R
"ax \n\t"
4023 "mov %%"R
"ax, %c[cr2](%0) \n\t"
4025 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
4026 "setbe %c[fail](%0) \n\t"
4027 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
4028 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
4029 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
4030 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
4031 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
4032 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4033 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4034 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4035 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4036 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4037 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
4038 #ifdef CONFIG_X86_64
4039 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4040 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4041 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4042 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4043 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4044 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4045 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4046 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
4048 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
4050 , R
"ax", R
"bx", R
"di", R
"si"
4051 #ifdef CONFIG_X86_64
4052 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4056 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
4057 | (1 << VCPU_EXREG_PDPTR
));
4058 vcpu
->arch
.regs_dirty
= 0;
4060 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
4062 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
4065 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
4066 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
4068 vmx_complete_atomic_exit(vmx
);
4069 vmx_recover_nmi_blocking(vmx
);
4070 vmx_complete_interrupts(vmx
);
4076 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
4078 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4082 free_vmcs(vmx
->vmcs
);
4087 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
4089 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4092 vmx_free_vmcs(vcpu
);
4093 kfree(vmx
->guest_msrs
);
4094 kvm_vcpu_uninit(vcpu
);
4095 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4098 static inline void vmcs_init(struct vmcs
*vmcs
)
4100 u64 phys_addr
= __pa(per_cpu(vmxarea
, raw_smp_processor_id()));
4103 kvm_cpu_vmxon(phys_addr
);
4111 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
4114 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
4118 return ERR_PTR(-ENOMEM
);
4122 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
4126 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
4127 if (!vmx
->guest_msrs
) {
4132 vmx
->vmcs
= alloc_vmcs();
4136 vmcs_init(vmx
->vmcs
);
4139 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
4140 vmx
->vcpu
.cpu
= cpu
;
4141 err
= vmx_vcpu_setup(vmx
);
4142 vmx_vcpu_put(&vmx
->vcpu
);
4146 if (vm_need_virtualize_apic_accesses(kvm
))
4147 if (alloc_apic_access_page(kvm
) != 0)
4151 if (!kvm
->arch
.ept_identity_map_addr
)
4152 kvm
->arch
.ept_identity_map_addr
=
4153 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4154 if (alloc_identity_pagetable(kvm
) != 0)
4161 free_vmcs(vmx
->vmcs
);
4163 kfree(vmx
->guest_msrs
);
4165 kvm_vcpu_uninit(&vmx
->vcpu
);
4168 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4169 return ERR_PTR(err
);
4172 static void __init
vmx_check_processor_compat(void *rtn
)
4174 struct vmcs_config vmcs_conf
;
4177 if (setup_vmcs_config(&vmcs_conf
) < 0)
4179 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
4180 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
4181 smp_processor_id());
4186 static int get_ept_level(void)
4188 return VMX_EPT_DEFAULT_GAW
+ 1;
4191 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4195 /* For VT-d and EPT combination
4196 * 1. MMIO: always map as UC
4198 * a. VT-d without snooping control feature: can't guarantee the
4199 * result, try to trust guest.
4200 * b. VT-d with snooping control feature: snooping control feature of
4201 * VT-d engine can guarantee the cache correctness. Just set it
4202 * to WB to keep consistent with host. So the same as item 3.
4203 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4204 * consistent with host MTRR
4207 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4208 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4209 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4210 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4211 VMX_EPT_MT_EPTE_SHIFT
;
4213 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4219 #define _ER(x) { EXIT_REASON_##x, #x }
4221 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4223 _ER(EXTERNAL_INTERRUPT
),
4225 _ER(PENDING_INTERRUPT
),
4245 _ER(IO_INSTRUCTION
),
4248 _ER(MWAIT_INSTRUCTION
),
4249 _ER(MONITOR_INSTRUCTION
),
4250 _ER(PAUSE_INSTRUCTION
),
4251 _ER(MCE_DURING_VMENTRY
),
4252 _ER(TPR_BELOW_THRESHOLD
),
4262 static int vmx_get_lpage_level(void)
4264 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
4265 return PT_DIRECTORY_LEVEL
;
4267 /* For shadow and EPT supported 1GB page */
4268 return PT_PDPE_LEVEL
;
4271 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
4273 struct kvm_cpuid_entry2
*best
;
4274 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4277 vmx
->rdtscp_enabled
= false;
4278 if (vmx_rdtscp_supported()) {
4279 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
4280 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
4281 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
4282 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
4283 vmx
->rdtscp_enabled
= true;
4285 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
4286 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4293 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
4297 static struct kvm_x86_ops vmx_x86_ops
= {
4298 .cpu_has_kvm_support
= cpu_has_kvm_support
,
4299 .disabled_by_bios
= vmx_disabled_by_bios
,
4300 .hardware_setup
= hardware_setup
,
4301 .hardware_unsetup
= hardware_unsetup
,
4302 .check_processor_compatibility
= vmx_check_processor_compat
,
4303 .hardware_enable
= hardware_enable
,
4304 .hardware_disable
= hardware_disable
,
4305 .cpu_has_accelerated_tpr
= report_flexpriority
,
4307 .vcpu_create
= vmx_create_vcpu
,
4308 .vcpu_free
= vmx_free_vcpu
,
4309 .vcpu_reset
= vmx_vcpu_reset
,
4311 .prepare_guest_switch
= vmx_save_host_state
,
4312 .vcpu_load
= vmx_vcpu_load
,
4313 .vcpu_put
= vmx_vcpu_put
,
4315 .set_guest_debug
= set_guest_debug
,
4316 .get_msr
= vmx_get_msr
,
4317 .set_msr
= vmx_set_msr
,
4318 .get_segment_base
= vmx_get_segment_base
,
4319 .get_segment
= vmx_get_segment
,
4320 .set_segment
= vmx_set_segment
,
4321 .get_cpl
= vmx_get_cpl
,
4322 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
4323 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
4324 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
4325 .set_cr0
= vmx_set_cr0
,
4326 .set_cr3
= vmx_set_cr3
,
4327 .set_cr4
= vmx_set_cr4
,
4328 .set_efer
= vmx_set_efer
,
4329 .get_idt
= vmx_get_idt
,
4330 .set_idt
= vmx_set_idt
,
4331 .get_gdt
= vmx_get_gdt
,
4332 .set_gdt
= vmx_set_gdt
,
4333 .set_dr7
= vmx_set_dr7
,
4334 .cache_reg
= vmx_cache_reg
,
4335 .get_rflags
= vmx_get_rflags
,
4336 .set_rflags
= vmx_set_rflags
,
4337 .fpu_activate
= vmx_fpu_activate
,
4338 .fpu_deactivate
= vmx_fpu_deactivate
,
4340 .tlb_flush
= vmx_flush_tlb
,
4342 .run
= vmx_vcpu_run
,
4343 .handle_exit
= vmx_handle_exit
,
4344 .skip_emulated_instruction
= skip_emulated_instruction
,
4345 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
4346 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
4347 .patch_hypercall
= vmx_patch_hypercall
,
4348 .set_irq
= vmx_inject_irq
,
4349 .set_nmi
= vmx_inject_nmi
,
4350 .queue_exception
= vmx_queue_exception
,
4351 .cancel_injection
= vmx_cancel_injection
,
4352 .interrupt_allowed
= vmx_interrupt_allowed
,
4353 .nmi_allowed
= vmx_nmi_allowed
,
4354 .get_nmi_mask
= vmx_get_nmi_mask
,
4355 .set_nmi_mask
= vmx_set_nmi_mask
,
4356 .enable_nmi_window
= enable_nmi_window
,
4357 .enable_irq_window
= enable_irq_window
,
4358 .update_cr8_intercept
= update_cr8_intercept
,
4360 .set_tss_addr
= vmx_set_tss_addr
,
4361 .get_tdp_level
= get_ept_level
,
4362 .get_mt_mask
= vmx_get_mt_mask
,
4364 .get_exit_info
= vmx_get_exit_info
,
4365 .exit_reasons_str
= vmx_exit_reasons_str
,
4367 .get_lpage_level
= vmx_get_lpage_level
,
4369 .cpuid_update
= vmx_cpuid_update
,
4371 .rdtscp_supported
= vmx_rdtscp_supported
,
4373 .set_supported_cpuid
= vmx_set_supported_cpuid
,
4375 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
4377 .write_tsc_offset
= vmx_write_tsc_offset
,
4378 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
4380 .set_tdp_cr3
= vmx_set_cr3
,
4383 static int __init
vmx_init(void)
4387 rdmsrl_safe(MSR_EFER
, &host_efer
);
4389 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
4390 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
4392 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4393 if (!vmx_io_bitmap_a
)
4396 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4397 if (!vmx_io_bitmap_b
) {
4402 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4403 if (!vmx_msr_bitmap_legacy
) {
4408 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
4409 if (!vmx_msr_bitmap_longmode
) {
4415 * Allow direct access to the PC debug port (it is often used for I/O
4416 * delays, but the vmexits simply slow things down).
4418 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
4419 clear_bit(0x80, vmx_io_bitmap_a
);
4421 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
4423 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
4424 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
4426 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
4428 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
4429 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
4433 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
4434 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
4435 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
4436 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
4437 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
4438 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
4441 bypass_guest_pf
= 0;
4442 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4443 VMX_EPT_EXECUTABLE_MASK
);
4448 if (bypass_guest_pf
)
4449 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
4454 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4456 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4458 free_page((unsigned long)vmx_io_bitmap_b
);
4460 free_page((unsigned long)vmx_io_bitmap_a
);
4464 static void __exit
vmx_exit(void)
4466 free_page((unsigned long)vmx_msr_bitmap_legacy
);
4467 free_page((unsigned long)vmx_msr_bitmap_longmode
);
4468 free_page((unsigned long)vmx_io_bitmap_b
);
4469 free_page((unsigned long)vmx_io_bitmap_a
);
4474 module_init(vmx_init
)
4475 module_exit(vmx_exit
)