2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/microcode.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 #define __ex_clear(x, reg) \
60 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62 MODULE_AUTHOR("Qumranet");
63 MODULE_LICENSE("GPL");
65 static const struct x86_cpu_id vmx_cpu_id
[] = {
66 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
69 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
71 static bool __read_mostly enable_vpid
= 1;
72 module_param_named(vpid
, enable_vpid
, bool, 0444);
74 static bool __read_mostly flexpriority_enabled
= 1;
75 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept
= 1;
78 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
80 static bool __read_mostly enable_unrestricted_guest
= 1;
81 module_param_named(unrestricted_guest
,
82 enable_unrestricted_guest
, bool, S_IRUGO
);
84 static bool __read_mostly enable_ept_ad_bits
= 1;
85 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
87 static bool __read_mostly emulate_invalid_guest_state
= true;
88 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
139 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
149 * According to test, this time is usually smaller than 128 cycles.
150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
156 #define KVM_VMX_DEFAULT_PLE_GAP 128
157 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
163 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
164 module_param(ple_gap
, int, S_IRUGO
);
166 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
167 module_param(ple_window
, int, S_IRUGO
);
169 /* Default doubles per-vcpu window every exit. */
170 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
171 module_param(ple_window_grow
, int, S_IRUGO
);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
175 module_param(ple_window_shrink
, int, S_IRUGO
);
177 /* Default is to compute the maximum so we can never overflow. */
178 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
180 module_param(ple_window_max
, int, S_IRUGO
);
182 extern const ulong vmx_return
;
184 #define NR_AUTOLOAD_MSRS 8
185 #define VMCS02_POOL_SIZE 1
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
200 struct vmcs
*shadow_vmcs
;
203 bool nmi_known_unmasked
;
204 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
205 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
206 struct list_head loaded_vmcss_on_cpu_link
;
209 struct shared_msr_entry
{
216 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
217 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
218 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
219 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
220 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
221 * More than one of these structures may exist, if L1 runs multiple L2 guests.
222 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
223 * underlying hardware which will be used to run L2.
224 * This structure is packed to ensure that its layout is identical across
225 * machines (necessary for live migration).
226 * If there are changes in this struct, VMCS12_REVISION must be changed.
228 typedef u64 natural_width
;
229 struct __packed vmcs12
{
230 /* According to the Intel spec, a VMCS region must start with the
231 * following two fields. Then follow implementation-specific data.
236 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
237 u32 padding
[7]; /* room for future expansion */
242 u64 vm_exit_msr_store_addr
;
243 u64 vm_exit_msr_load_addr
;
244 u64 vm_entry_msr_load_addr
;
246 u64 virtual_apic_page_addr
;
247 u64 apic_access_addr
;
248 u64 posted_intr_desc_addr
;
250 u64 eoi_exit_bitmap0
;
251 u64 eoi_exit_bitmap1
;
252 u64 eoi_exit_bitmap2
;
253 u64 eoi_exit_bitmap3
;
255 u64 guest_physical_address
;
256 u64 vmcs_link_pointer
;
258 u64 guest_ia32_debugctl
;
261 u64 guest_ia32_perf_global_ctrl
;
269 u64 host_ia32_perf_global_ctrl
;
270 u64 padding64
[8]; /* room for future expansion */
272 * To allow migration of L1 (complete with its L2 guests) between
273 * machines of different natural widths (32 or 64 bit), we cannot have
274 * unsigned long fields with no explict size. We use u64 (aliased
275 * natural_width) instead. Luckily, x86 is little-endian.
277 natural_width cr0_guest_host_mask
;
278 natural_width cr4_guest_host_mask
;
279 natural_width cr0_read_shadow
;
280 natural_width cr4_read_shadow
;
281 natural_width cr3_target_value0
;
282 natural_width cr3_target_value1
;
283 natural_width cr3_target_value2
;
284 natural_width cr3_target_value3
;
285 natural_width exit_qualification
;
286 natural_width guest_linear_address
;
287 natural_width guest_cr0
;
288 natural_width guest_cr3
;
289 natural_width guest_cr4
;
290 natural_width guest_es_base
;
291 natural_width guest_cs_base
;
292 natural_width guest_ss_base
;
293 natural_width guest_ds_base
;
294 natural_width guest_fs_base
;
295 natural_width guest_gs_base
;
296 natural_width guest_ldtr_base
;
297 natural_width guest_tr_base
;
298 natural_width guest_gdtr_base
;
299 natural_width guest_idtr_base
;
300 natural_width guest_dr7
;
301 natural_width guest_rsp
;
302 natural_width guest_rip
;
303 natural_width guest_rflags
;
304 natural_width guest_pending_dbg_exceptions
;
305 natural_width guest_sysenter_esp
;
306 natural_width guest_sysenter_eip
;
307 natural_width host_cr0
;
308 natural_width host_cr3
;
309 natural_width host_cr4
;
310 natural_width host_fs_base
;
311 natural_width host_gs_base
;
312 natural_width host_tr_base
;
313 natural_width host_gdtr_base
;
314 natural_width host_idtr_base
;
315 natural_width host_ia32_sysenter_esp
;
316 natural_width host_ia32_sysenter_eip
;
317 natural_width host_rsp
;
318 natural_width host_rip
;
319 natural_width paddingl
[8]; /* room for future expansion */
320 u32 pin_based_vm_exec_control
;
321 u32 cpu_based_vm_exec_control
;
322 u32 exception_bitmap
;
323 u32 page_fault_error_code_mask
;
324 u32 page_fault_error_code_match
;
325 u32 cr3_target_count
;
326 u32 vm_exit_controls
;
327 u32 vm_exit_msr_store_count
;
328 u32 vm_exit_msr_load_count
;
329 u32 vm_entry_controls
;
330 u32 vm_entry_msr_load_count
;
331 u32 vm_entry_intr_info_field
;
332 u32 vm_entry_exception_error_code
;
333 u32 vm_entry_instruction_len
;
335 u32 secondary_vm_exec_control
;
336 u32 vm_instruction_error
;
338 u32 vm_exit_intr_info
;
339 u32 vm_exit_intr_error_code
;
340 u32 idt_vectoring_info_field
;
341 u32 idt_vectoring_error_code
;
342 u32 vm_exit_instruction_len
;
343 u32 vmx_instruction_info
;
350 u32 guest_ldtr_limit
;
352 u32 guest_gdtr_limit
;
353 u32 guest_idtr_limit
;
354 u32 guest_es_ar_bytes
;
355 u32 guest_cs_ar_bytes
;
356 u32 guest_ss_ar_bytes
;
357 u32 guest_ds_ar_bytes
;
358 u32 guest_fs_ar_bytes
;
359 u32 guest_gs_ar_bytes
;
360 u32 guest_ldtr_ar_bytes
;
361 u32 guest_tr_ar_bytes
;
362 u32 guest_interruptibility_info
;
363 u32 guest_activity_state
;
364 u32 guest_sysenter_cs
;
365 u32 host_ia32_sysenter_cs
;
366 u32 vmx_preemption_timer_value
;
367 u32 padding32
[7]; /* room for future expansion */
368 u16 virtual_processor_id
;
370 u16 guest_es_selector
;
371 u16 guest_cs_selector
;
372 u16 guest_ss_selector
;
373 u16 guest_ds_selector
;
374 u16 guest_fs_selector
;
375 u16 guest_gs_selector
;
376 u16 guest_ldtr_selector
;
377 u16 guest_tr_selector
;
378 u16 guest_intr_status
;
380 u16 host_es_selector
;
381 u16 host_cs_selector
;
382 u16 host_ss_selector
;
383 u16 host_ds_selector
;
384 u16 host_fs_selector
;
385 u16 host_gs_selector
;
386 u16 host_tr_selector
;
390 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
391 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
392 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
394 #define VMCS12_REVISION 0x11e57ed0
397 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
398 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
399 * current implementation, 4K are reserved to avoid future complications.
401 #define VMCS12_SIZE 0x1000
403 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
405 struct list_head list
;
407 struct loaded_vmcs vmcs02
;
411 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
412 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
415 /* Has the level1 guest done vmxon? */
420 /* The guest-physical address of the current VMCS L1 keeps for L2 */
423 * Cache of the guest's VMCS, existing outside of guest memory.
424 * Loaded from guest memory during VMPTRLD. Flushed to guest
425 * memory during VMCLEAR and VMPTRLD.
427 struct vmcs12
*cached_vmcs12
;
429 * Indicates if the shadow vmcs must be updated with the
430 * data hold by vmcs12
432 bool sync_shadow_vmcs
;
434 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
435 struct list_head vmcs02_pool
;
437 bool change_vmcs01_virtual_x2apic_mode
;
438 /* L2 must run next, and mustn't decide to exit to L1. */
439 bool nested_run_pending
;
441 * Guest pages referred to in vmcs02 with host-physical pointers, so
442 * we must keep them pinned while L2 runs.
444 struct page
*apic_access_page
;
445 struct page
*virtual_apic_page
;
446 struct page
*pi_desc_page
;
447 struct pi_desc
*pi_desc
;
451 unsigned long *msr_bitmap
;
453 struct hrtimer preemption_timer
;
454 bool preemption_timer_expired
;
456 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
463 * We only store the "true" versions of the VMX capability MSRs. We
464 * generate the "non-true" versions by setting the must-be-1 bits
465 * according to the SDM.
467 u32 nested_vmx_procbased_ctls_low
;
468 u32 nested_vmx_procbased_ctls_high
;
469 u32 nested_vmx_secondary_ctls_low
;
470 u32 nested_vmx_secondary_ctls_high
;
471 u32 nested_vmx_pinbased_ctls_low
;
472 u32 nested_vmx_pinbased_ctls_high
;
473 u32 nested_vmx_exit_ctls_low
;
474 u32 nested_vmx_exit_ctls_high
;
475 u32 nested_vmx_entry_ctls_low
;
476 u32 nested_vmx_entry_ctls_high
;
477 u32 nested_vmx_misc_low
;
478 u32 nested_vmx_misc_high
;
479 u32 nested_vmx_ept_caps
;
480 u32 nested_vmx_vpid_caps
;
481 u64 nested_vmx_basic
;
482 u64 nested_vmx_cr0_fixed0
;
483 u64 nested_vmx_cr0_fixed1
;
484 u64 nested_vmx_cr4_fixed0
;
485 u64 nested_vmx_cr4_fixed1
;
486 u64 nested_vmx_vmcs_enum
;
489 #define POSTED_INTR_ON 0
490 #define POSTED_INTR_SN 1
492 /* Posted-Interrupt Descriptor */
494 u32 pir
[8]; /* Posted interrupt requested */
497 /* bit 256 - Outstanding Notification */
499 /* bit 257 - Suppress Notification */
501 /* bit 271:258 - Reserved */
503 /* bit 279:272 - Notification Vector */
505 /* bit 287:280 - Reserved */
507 /* bit 319:288 - Notification Destination */
515 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
517 return test_and_set_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
523 return test_and_clear_bit(POSTED_INTR_ON
,
524 (unsigned long *)&pi_desc
->control
);
527 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
529 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
532 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
534 return clear_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
540 return set_bit(POSTED_INTR_SN
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
546 clear_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_on(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_ON
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
558 return test_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
563 struct kvm_vcpu vcpu
;
564 unsigned long host_rsp
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
584 struct loaded_vmcs vmcs01
;
585 struct loaded_vmcs
*loaded_vmcs
;
586 bool __launched
; /* temporary, used in vmx_vcpu_run */
587 struct msr_autoload
{
589 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
590 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
594 u16 fs_sel
, gs_sel
, ldt_sel
;
598 int gs_ldt_reload_needed
;
599 int fs_reload_needed
;
600 u64 msr_host_bndcfgs
;
605 struct kvm_segment segs
[8];
608 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
609 struct kvm_save_segment
{
617 bool emulation_required
;
621 /* Posted interrupt descriptor */
622 struct pi_desc pi_desc
;
624 /* Support for a guest hypervisor (nested VMX) */
625 struct nested_vmx nested
;
627 /* Dynamic PLE window. */
629 bool ple_window_dirty
;
631 /* Support for PML */
632 #define PML_ENTITY_NUM 512
635 /* apic deadline value in host tsc */
638 u64 current_tsc_ratio
;
643 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
644 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
645 * in msr_ia32_feature_control_valid_bits.
647 u64 msr_ia32_feature_control
;
648 u64 msr_ia32_feature_control_valid_bits
;
651 enum segment_cache_field
{
660 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
662 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
665 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
667 return &(to_vmx(vcpu
)->pi_desc
);
670 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
671 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
672 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
673 [number##_HIGH] = VMCS12_OFFSET(name)+4
676 static unsigned long shadow_read_only_fields
[] = {
678 * We do NOT shadow fields that are modified when L0
679 * traps and emulates any vmx instruction (e.g. VMPTRLD,
680 * VMXON...) executed by L1.
681 * For example, VM_INSTRUCTION_ERROR is read
682 * by L1 if a vmx instruction fails (part of the error path).
683 * Note the code assumes this logic. If for some reason
684 * we start shadowing these fields then we need to
685 * force a shadow sync when L0 emulates vmx instructions
686 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
687 * by nested_vmx_failValid)
691 VM_EXIT_INSTRUCTION_LEN
,
692 IDT_VECTORING_INFO_FIELD
,
693 IDT_VECTORING_ERROR_CODE
,
694 VM_EXIT_INTR_ERROR_CODE
,
696 GUEST_LINEAR_ADDRESS
,
697 GUEST_PHYSICAL_ADDRESS
699 static int max_shadow_read_only_fields
=
700 ARRAY_SIZE(shadow_read_only_fields
);
702 static unsigned long shadow_read_write_fields
[] = {
709 GUEST_INTERRUPTIBILITY_INFO
,
722 CPU_BASED_VM_EXEC_CONTROL
,
723 VM_ENTRY_EXCEPTION_ERROR_CODE
,
724 VM_ENTRY_INTR_INFO_FIELD
,
725 VM_ENTRY_INSTRUCTION_LEN
,
726 VM_ENTRY_EXCEPTION_ERROR_CODE
,
732 static int max_shadow_read_write_fields
=
733 ARRAY_SIZE(shadow_read_write_fields
);
735 static const unsigned short vmcs_field_to_offset_table
[] = {
736 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
737 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
738 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
739 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
740 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
741 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
742 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
743 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
744 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
745 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
746 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
747 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
748 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
749 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
750 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
751 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
752 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
753 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
754 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
755 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
756 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
757 FIELD64(MSR_BITMAP
, msr_bitmap
),
758 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
759 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
760 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
761 FIELD64(TSC_OFFSET
, tsc_offset
),
762 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
763 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
764 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
765 FIELD64(EPT_POINTER
, ept_pointer
),
766 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
767 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
768 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
769 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
770 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
771 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
772 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
773 FIELD64(PML_ADDRESS
, pml_address
),
774 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
775 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
776 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
777 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
778 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
779 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
780 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
781 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
782 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
783 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
784 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
785 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
786 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
787 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
788 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
789 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
790 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
791 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
792 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
793 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
794 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
795 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
796 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
797 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
798 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
799 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
800 FIELD(TPR_THRESHOLD
, tpr_threshold
),
801 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
802 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
803 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
804 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
805 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
806 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
807 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
808 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
809 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
810 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
811 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
812 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
813 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
814 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
815 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
816 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
817 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
818 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
819 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
820 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
821 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
822 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
823 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
824 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
825 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
826 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
827 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
828 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
829 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
830 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
831 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
832 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
833 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
834 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
835 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
836 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
837 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
838 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
839 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
840 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
841 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
842 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
843 FIELD(GUEST_CR0
, guest_cr0
),
844 FIELD(GUEST_CR3
, guest_cr3
),
845 FIELD(GUEST_CR4
, guest_cr4
),
846 FIELD(GUEST_ES_BASE
, guest_es_base
),
847 FIELD(GUEST_CS_BASE
, guest_cs_base
),
848 FIELD(GUEST_SS_BASE
, guest_ss_base
),
849 FIELD(GUEST_DS_BASE
, guest_ds_base
),
850 FIELD(GUEST_FS_BASE
, guest_fs_base
),
851 FIELD(GUEST_GS_BASE
, guest_gs_base
),
852 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
853 FIELD(GUEST_TR_BASE
, guest_tr_base
),
854 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
855 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
856 FIELD(GUEST_DR7
, guest_dr7
),
857 FIELD(GUEST_RSP
, guest_rsp
),
858 FIELD(GUEST_RIP
, guest_rip
),
859 FIELD(GUEST_RFLAGS
, guest_rflags
),
860 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
861 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
862 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
863 FIELD(HOST_CR0
, host_cr0
),
864 FIELD(HOST_CR3
, host_cr3
),
865 FIELD(HOST_CR4
, host_cr4
),
866 FIELD(HOST_FS_BASE
, host_fs_base
),
867 FIELD(HOST_GS_BASE
, host_gs_base
),
868 FIELD(HOST_TR_BASE
, host_tr_base
),
869 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
870 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
871 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
872 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
873 FIELD(HOST_RSP
, host_rsp
),
874 FIELD(HOST_RIP
, host_rip
),
877 static inline short vmcs_field_to_offset(unsigned long field
)
879 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
881 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
882 vmcs_field_to_offset_table
[field
] == 0)
885 return vmcs_field_to_offset_table
[field
];
888 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
890 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
893 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
895 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
896 if (is_error_page(page
))
902 static void nested_release_page(struct page
*page
)
904 kvm_release_page_dirty(page
);
907 static void nested_release_page_clean(struct page
*page
)
909 kvm_release_page_clean(page
);
912 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
913 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
914 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
915 static bool vmx_xsaves_supported(void);
916 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
917 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
918 struct kvm_segment
*var
, int seg
);
919 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
920 struct kvm_segment
*var
, int seg
);
921 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
922 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
923 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
924 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
925 static int alloc_identity_pagetable(struct kvm
*kvm
);
926 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
927 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
928 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
931 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
932 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
943 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
944 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
949 VMX_MSR_BITMAP_LEGACY
,
950 VMX_MSR_BITMAP_LONGMODE
,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LEGACY_X2APIC
,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
960 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
962 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
973 static bool cpu_has_load_ia32_efer
;
974 static bool cpu_has_load_perf_global_ctrl
;
976 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
977 static DEFINE_SPINLOCK(vmx_vpid_lock
);
979 static struct vmcs_config
{
984 u32 pin_based_exec_ctrl
;
985 u32 cpu_based_exec_ctrl
;
986 u32 cpu_based_2nd_exec_ctrl
;
991 static struct vmx_capability
{
996 #define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1004 static const struct kvm_vmx_segment_field
{
1009 } kvm_vmx_segment_fields
[] = {
1010 VMX_SEGMENT_FIELD(CS
),
1011 VMX_SEGMENT_FIELD(DS
),
1012 VMX_SEGMENT_FIELD(ES
),
1013 VMX_SEGMENT_FIELD(FS
),
1014 VMX_SEGMENT_FIELD(GS
),
1015 VMX_SEGMENT_FIELD(SS
),
1016 VMX_SEGMENT_FIELD(TR
),
1017 VMX_SEGMENT_FIELD(LDTR
),
1020 static u64 host_efer
;
1022 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026 * away by decrementing the array size.
1028 static const u32 vmx_msr_index
[] = {
1029 #ifdef CONFIG_X86_64
1030 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1032 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1035 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1037 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1038 INTR_INFO_VALID_MASK
)) ==
1039 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1042 static inline bool is_debug(u32 intr_info
)
1044 return is_exception_n(intr_info
, DB_VECTOR
);
1047 static inline bool is_breakpoint(u32 intr_info
)
1049 return is_exception_n(intr_info
, BP_VECTOR
);
1052 static inline bool is_page_fault(u32 intr_info
)
1054 return is_exception_n(intr_info
, PF_VECTOR
);
1057 static inline bool is_no_device(u32 intr_info
)
1059 return is_exception_n(intr_info
, NM_VECTOR
);
1062 static inline bool is_invalid_opcode(u32 intr_info
)
1064 return is_exception_n(intr_info
, UD_VECTOR
);
1067 static inline bool is_external_interrupt(u32 intr_info
)
1069 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1070 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1073 static inline bool is_machine_check(u32 intr_info
)
1075 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1076 INTR_INFO_VALID_MASK
)) ==
1077 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 return vmcs_config
.cpu_based_exec_ctrl
&
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1126 * Comment's format: document - errata name - stepping - processor name.
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130 static u32 vmx_preemption_cpu_tfms
[] = {
1131 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1133 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 u32 eax
= cpuid_eax(0x00000001), i
;
1162 /* Clear the reserved bits */
1163 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1164 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1165 if (eax
== vmx_preemption_cpu_tfms
[i
])
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1173 return vmcs_config
.pin_based_exec_ctrl
&
1174 PIN_BASED_VMX_PREEMPTION_TIMER
;
1177 static inline bool cpu_has_vmx_posted_intr(void)
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1180 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1183 static inline bool cpu_has_vmx_apicv(void)
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1190 static inline bool cpu_has_vmx_flexpriority(void)
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1213 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1221 static inline bool cpu_has_vmx_invept_context(void)
1223 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1226 static inline bool cpu_has_vmx_invept_global(void)
1228 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1233 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1238 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1241 static inline bool cpu_has_vmx_invvpid(void)
1243 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1246 static inline bool cpu_has_vmx_ept(void)
1248 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1249 SECONDARY_EXEC_ENABLE_EPT
;
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1258 static inline bool cpu_has_vmx_ple(void)
1260 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1264 static inline bool cpu_has_vmx_basic_inout(void)
1266 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1271 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1274 static inline bool cpu_has_vmx_vpid(void)
1276 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1277 SECONDARY_EXEC_ENABLE_VPID
;
1280 static inline bool cpu_has_vmx_rdtscp(void)
1282 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1283 SECONDARY_EXEC_RDTSCP
;
1286 static inline bool cpu_has_vmx_invpcid(void)
1288 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1289 SECONDARY_EXEC_ENABLE_INVPCID
;
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1295 SECONDARY_EXEC_WBINVD_EXITING
;
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1301 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1306 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1307 SECONDARY_EXEC_SHADOW_VMCS
;
1310 static inline bool cpu_has_vmx_pml(void)
1312 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1318 SECONDARY_EXEC_TSC_SCALING
;
1321 static inline bool report_flexpriority(void)
1323 return flexpriority_enabled
;
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1328 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1331 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1333 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1336 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1338 return (vmcs12
->cpu_based_vm_exec_control
&
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1340 (vmcs12
->secondary_vm_exec_control
& bit
);
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1345 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1350 return vmcs12
->pin_based_vm_exec_control
&
1351 PIN_BASED_VMX_PREEMPTION_TIMER
;
1354 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1356 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1361 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1362 vmx_xsaves_supported();
1365 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1367 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1372 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1375 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1377 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1382 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1385 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1387 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1392 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1395 static inline bool is_nmi(u32 intr_info
)
1397 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1398 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1401 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1403 unsigned long exit_qualification
);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1405 struct vmcs12
*vmcs12
,
1406 u32 reason
, unsigned long qualification
);
1408 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1412 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1413 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1418 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1424 } operand
= { vpid
, 0, gva
};
1426 asm volatile (__ex(ASM_VMX_INVVPID
)
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1432 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1436 } operand
= {eptp
, gpa
};
1438 asm volatile (__ex(ASM_VMX_INVEPT
)
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1444 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1448 i
= __find_msr_index(vmx
, msr
);
1450 return &vmx
->guest_msrs
[i
];
1454 static void vmcs_clear(struct vmcs
*vmcs
)
1456 u64 phys_addr
= __pa(vmcs
);
1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1460 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1463 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1467 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1469 vmcs_clear(loaded_vmcs
->vmcs
);
1470 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1471 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1472 loaded_vmcs
->cpu
= -1;
1473 loaded_vmcs
->launched
= 0;
1476 static void vmcs_load(struct vmcs
*vmcs
)
1478 u64 phys_addr
= __pa(vmcs
);
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1482 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1485 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1489 #ifdef CONFIG_KEXEC_CORE
1491 * This bitmap is used to indicate whether the vmclear
1492 * operation is enabled on all cpus. All disabled by
1495 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1497 static inline void crash_enable_local_vmclear(int cpu
)
1499 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1502 static inline void crash_disable_local_vmclear(int cpu
)
1504 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1507 static inline int crash_local_vmclear_enabled(int cpu
)
1509 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1512 static void crash_vmclear_local_loaded_vmcss(void)
1514 int cpu
= raw_smp_processor_id();
1515 struct loaded_vmcs
*v
;
1517 if (!crash_local_vmclear_enabled(cpu
))
1520 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1521 loaded_vmcss_on_cpu_link
)
1522 vmcs_clear(v
->vmcs
);
1525 static inline void crash_enable_local_vmclear(int cpu
) { }
1526 static inline void crash_disable_local_vmclear(int cpu
) { }
1527 #endif /* CONFIG_KEXEC_CORE */
1529 static void __loaded_vmcs_clear(void *arg
)
1531 struct loaded_vmcs
*loaded_vmcs
= arg
;
1532 int cpu
= raw_smp_processor_id();
1534 if (loaded_vmcs
->cpu
!= cpu
)
1535 return; /* vcpu migration can race with cpu offline */
1536 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1537 per_cpu(current_vmcs
, cpu
) = NULL
;
1538 crash_disable_local_vmclear(cpu
);
1539 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1542 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1543 * is before setting loaded_vmcs->vcpu to -1 which is done in
1544 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1545 * then adds the vmcs into percpu list before it is deleted.
1549 loaded_vmcs_init(loaded_vmcs
);
1550 crash_enable_local_vmclear(cpu
);
1553 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1555 int cpu
= loaded_vmcs
->cpu
;
1558 smp_call_function_single(cpu
,
1559 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1562 static inline void vpid_sync_vcpu_single(int vpid
)
1567 if (cpu_has_vmx_invvpid_single())
1568 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1571 static inline void vpid_sync_vcpu_global(void)
1573 if (cpu_has_vmx_invvpid_global())
1574 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1577 static inline void vpid_sync_context(int vpid
)
1579 if (cpu_has_vmx_invvpid_single())
1580 vpid_sync_vcpu_single(vpid
);
1582 vpid_sync_vcpu_global();
1585 static inline void ept_sync_global(void)
1587 if (cpu_has_vmx_invept_global())
1588 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1591 static inline void ept_sync_context(u64 eptp
)
1594 if (cpu_has_vmx_invept_context())
1595 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1601 static __always_inline
void vmcs_check16(unsigned long field
)
1603 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1604 "16-bit accessor invalid for 64-bit field");
1605 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1606 "16-bit accessor invalid for 64-bit high field");
1607 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1608 "16-bit accessor invalid for 32-bit high field");
1609 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1610 "16-bit accessor invalid for natural width field");
1613 static __always_inline
void vmcs_check32(unsigned long field
)
1615 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1616 "32-bit accessor invalid for 16-bit field");
1617 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1618 "32-bit accessor invalid for natural width field");
1621 static __always_inline
void vmcs_check64(unsigned long field
)
1623 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1624 "64-bit accessor invalid for 16-bit field");
1625 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1626 "64-bit accessor invalid for 64-bit high field");
1627 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1628 "64-bit accessor invalid for 32-bit field");
1629 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1630 "64-bit accessor invalid for natural width field");
1633 static __always_inline
void vmcs_checkl(unsigned long field
)
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1636 "Natural width accessor invalid for 16-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1638 "Natural width accessor invalid for 64-bit field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1640 "Natural width accessor invalid for 64-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1642 "Natural width accessor invalid for 32-bit field");
1645 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1647 unsigned long value
;
1649 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1650 : "=a"(value
) : "d"(field
) : "cc");
1654 static __always_inline u16
vmcs_read16(unsigned long field
)
1656 vmcs_check16(field
);
1657 return __vmcs_readl(field
);
1660 static __always_inline u32
vmcs_read32(unsigned long field
)
1662 vmcs_check32(field
);
1663 return __vmcs_readl(field
);
1666 static __always_inline u64
vmcs_read64(unsigned long field
)
1668 vmcs_check64(field
);
1669 #ifdef CONFIG_X86_64
1670 return __vmcs_readl(field
);
1672 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1676 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1679 return __vmcs_readl(field
);
1682 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1684 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1685 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1689 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1693 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1694 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1695 if (unlikely(error
))
1696 vmwrite_error(field
, value
);
1699 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1701 vmcs_check16(field
);
1702 __vmcs_writel(field
, value
);
1705 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1707 vmcs_check32(field
);
1708 __vmcs_writel(field
, value
);
1711 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1713 vmcs_check64(field
);
1714 __vmcs_writel(field
, value
);
1715 #ifndef CONFIG_X86_64
1717 __vmcs_writel(field
+1, value
>> 32);
1721 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1724 __vmcs_writel(field
, value
);
1727 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1729 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1730 "vmcs_clear_bits does not support 64-bit fields");
1731 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1734 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1736 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1737 "vmcs_set_bits does not support 64-bit fields");
1738 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1741 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1743 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1746 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1748 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1749 vmx
->vm_entry_controls_shadow
= val
;
1752 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1754 if (vmx
->vm_entry_controls_shadow
!= val
)
1755 vm_entry_controls_init(vmx
, val
);
1758 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1760 return vmx
->vm_entry_controls_shadow
;
1764 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1766 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1769 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1771 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1774 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1776 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1779 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1781 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1782 vmx
->vm_exit_controls_shadow
= val
;
1785 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1787 if (vmx
->vm_exit_controls_shadow
!= val
)
1788 vm_exit_controls_init(vmx
, val
);
1791 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1793 return vmx
->vm_exit_controls_shadow
;
1797 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1799 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1802 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1804 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1807 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1809 vmx
->segment_cache
.bitmask
= 0;
1812 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1816 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1818 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1819 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1820 vmx
->segment_cache
.bitmask
= 0;
1822 ret
= vmx
->segment_cache
.bitmask
& mask
;
1823 vmx
->segment_cache
.bitmask
|= mask
;
1827 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1829 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1831 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1832 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1836 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1838 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1840 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1841 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1845 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1847 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1849 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1850 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1854 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1856 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1858 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1859 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1863 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1867 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1868 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1869 if ((vcpu
->guest_debug
&
1870 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1871 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1872 eb
|= 1u << BP_VECTOR
;
1873 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1876 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1878 /* When we are running a nested L2 guest and L1 specified for it a
1879 * certain exception bitmap, we must trap the same exceptions and pass
1880 * them to L1. When running L2, we will only handle the exceptions
1881 * specified above if L1 did not want them.
1883 if (is_guest_mode(vcpu
))
1884 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1886 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1889 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1890 unsigned long entry
, unsigned long exit
)
1892 vm_entry_controls_clearbit(vmx
, entry
);
1893 vm_exit_controls_clearbit(vmx
, exit
);
1896 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1899 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1903 if (cpu_has_load_ia32_efer
) {
1904 clear_atomic_switch_msr_special(vmx
,
1905 VM_ENTRY_LOAD_IA32_EFER
,
1906 VM_EXIT_LOAD_IA32_EFER
);
1910 case MSR_CORE_PERF_GLOBAL_CTRL
:
1911 if (cpu_has_load_perf_global_ctrl
) {
1912 clear_atomic_switch_msr_special(vmx
,
1913 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1914 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1920 for (i
= 0; i
< m
->nr
; ++i
)
1921 if (m
->guest
[i
].index
== msr
)
1927 m
->guest
[i
] = m
->guest
[m
->nr
];
1928 m
->host
[i
] = m
->host
[m
->nr
];
1929 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1930 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1933 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1934 unsigned long entry
, unsigned long exit
,
1935 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1936 u64 guest_val
, u64 host_val
)
1938 vmcs_write64(guest_val_vmcs
, guest_val
);
1939 vmcs_write64(host_val_vmcs
, host_val
);
1940 vm_entry_controls_setbit(vmx
, entry
);
1941 vm_exit_controls_setbit(vmx
, exit
);
1944 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1945 u64 guest_val
, u64 host_val
)
1948 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1952 if (cpu_has_load_ia32_efer
) {
1953 add_atomic_switch_msr_special(vmx
,
1954 VM_ENTRY_LOAD_IA32_EFER
,
1955 VM_EXIT_LOAD_IA32_EFER
,
1958 guest_val
, host_val
);
1962 case MSR_CORE_PERF_GLOBAL_CTRL
:
1963 if (cpu_has_load_perf_global_ctrl
) {
1964 add_atomic_switch_msr_special(vmx
,
1965 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1966 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1967 GUEST_IA32_PERF_GLOBAL_CTRL
,
1968 HOST_IA32_PERF_GLOBAL_CTRL
,
1969 guest_val
, host_val
);
1973 case MSR_IA32_PEBS_ENABLE
:
1974 /* PEBS needs a quiescent period after being disabled (to write
1975 * a record). Disabling PEBS through VMX MSR swapping doesn't
1976 * provide that period, so a CPU could write host's record into
1979 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1982 for (i
= 0; i
< m
->nr
; ++i
)
1983 if (m
->guest
[i
].index
== msr
)
1986 if (i
== NR_AUTOLOAD_MSRS
) {
1987 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1988 "Can't add msr %x\n", msr
);
1990 } else if (i
== m
->nr
) {
1992 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1993 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1996 m
->guest
[i
].index
= msr
;
1997 m
->guest
[i
].value
= guest_val
;
1998 m
->host
[i
].index
= msr
;
1999 m
->host
[i
].value
= host_val
;
2002 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2004 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2005 u64 ignore_bits
= 0;
2009 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2010 * host CPUID is more efficient than testing guest CPUID
2011 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2013 if (boot_cpu_has(X86_FEATURE_SMEP
))
2014 guest_efer
|= EFER_NX
;
2015 else if (!(guest_efer
& EFER_NX
))
2016 ignore_bits
|= EFER_NX
;
2020 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2022 ignore_bits
|= EFER_SCE
;
2023 #ifdef CONFIG_X86_64
2024 ignore_bits
|= EFER_LMA
| EFER_LME
;
2025 /* SCE is meaningful only in long mode on Intel */
2026 if (guest_efer
& EFER_LMA
)
2027 ignore_bits
&= ~(u64
)EFER_SCE
;
2030 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2033 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2034 * On CPUs that support "load IA32_EFER", always switch EFER
2035 * atomically, since it's faster than switching it manually.
2037 if (cpu_has_load_ia32_efer
||
2038 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2039 if (!(guest_efer
& EFER_LMA
))
2040 guest_efer
&= ~EFER_LME
;
2041 if (guest_efer
!= host_efer
)
2042 add_atomic_switch_msr(vmx
, MSR_EFER
,
2043 guest_efer
, host_efer
);
2046 guest_efer
&= ~ignore_bits
;
2047 guest_efer
|= host_efer
& ignore_bits
;
2049 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2050 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2056 #ifdef CONFIG_X86_32
2058 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2059 * VMCS rather than the segment table. KVM uses this helper to figure
2060 * out the current bases to poke them into the VMCS before entry.
2062 static unsigned long segment_base(u16 selector
)
2064 struct desc_struct
*table
;
2067 if (!(selector
& ~SEGMENT_RPL_MASK
))
2070 table
= get_current_gdt_ro();
2072 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2073 u16 ldt_selector
= kvm_read_ldt();
2075 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2078 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2080 v
= get_desc_base(&table
[selector
>> 3]);
2085 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2087 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2090 if (vmx
->host_state
.loaded
)
2093 vmx
->host_state
.loaded
= 1;
2095 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2096 * allow segment selectors with cpl > 0 or ti == 1.
2098 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2099 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2100 savesegment(fs
, vmx
->host_state
.fs_sel
);
2101 if (!(vmx
->host_state
.fs_sel
& 7)) {
2102 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2103 vmx
->host_state
.fs_reload_needed
= 0;
2105 vmcs_write16(HOST_FS_SELECTOR
, 0);
2106 vmx
->host_state
.fs_reload_needed
= 1;
2108 savesegment(gs
, vmx
->host_state
.gs_sel
);
2109 if (!(vmx
->host_state
.gs_sel
& 7))
2110 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2112 vmcs_write16(HOST_GS_SELECTOR
, 0);
2113 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2116 #ifdef CONFIG_X86_64
2117 savesegment(ds
, vmx
->host_state
.ds_sel
);
2118 savesegment(es
, vmx
->host_state
.es_sel
);
2121 #ifdef CONFIG_X86_64
2122 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2123 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2125 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2126 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2129 #ifdef CONFIG_X86_64
2130 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2131 if (is_long_mode(&vmx
->vcpu
))
2132 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2134 if (boot_cpu_has(X86_FEATURE_MPX
))
2135 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2136 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2137 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2138 vmx
->guest_msrs
[i
].data
,
2139 vmx
->guest_msrs
[i
].mask
);
2142 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2144 if (!vmx
->host_state
.loaded
)
2147 ++vmx
->vcpu
.stat
.host_state_reload
;
2148 vmx
->host_state
.loaded
= 0;
2149 #ifdef CONFIG_X86_64
2150 if (is_long_mode(&vmx
->vcpu
))
2151 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2153 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2154 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2155 #ifdef CONFIG_X86_64
2156 load_gs_index(vmx
->host_state
.gs_sel
);
2158 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2161 if (vmx
->host_state
.fs_reload_needed
)
2162 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2163 #ifdef CONFIG_X86_64
2164 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2165 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2166 loadsegment(es
, vmx
->host_state
.es_sel
);
2169 invalidate_tss_limit();
2170 #ifdef CONFIG_X86_64
2171 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2173 if (vmx
->host_state
.msr_host_bndcfgs
)
2174 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2175 load_fixmap_gdt(raw_smp_processor_id());
2178 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2181 __vmx_load_host_state(vmx
);
2185 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2187 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2188 struct pi_desc old
, new;
2192 * In case of hot-plug or hot-unplug, we may have to undo
2193 * vmx_vcpu_pi_put even if there is no assigned device. And we
2194 * always keep PI.NDST up to date for simplicity: it makes the
2195 * code easier, and CPU migration is not a fast path.
2197 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2201 * First handle the simple case where no cmpxchg is necessary; just
2202 * allow posting non-urgent interrupts.
2204 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2205 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2206 * expects the VCPU to be on the blocked_vcpu_list that matches
2209 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2211 pi_clear_sn(pi_desc
);
2215 /* The full case. */
2217 old
.control
= new.control
= pi_desc
->control
;
2219 dest
= cpu_physical_id(cpu
);
2221 if (x2apic_enabled())
2224 new.ndst
= (dest
<< 8) & 0xFF00;
2227 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2228 new.control
) != old
.control
);
2231 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2233 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2234 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2238 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2239 * vcpu mutex is already taken.
2241 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2243 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2244 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2246 if (!already_loaded
) {
2247 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2248 local_irq_disable();
2249 crash_disable_local_vmclear(cpu
);
2252 * Read loaded_vmcs->cpu should be before fetching
2253 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2254 * See the comments in __loaded_vmcs_clear().
2258 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2259 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2260 crash_enable_local_vmclear(cpu
);
2264 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2265 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2266 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2269 if (!already_loaded
) {
2270 void *gdt
= get_current_gdt_ro();
2271 unsigned long sysenter_esp
;
2273 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2276 * Linux uses per-cpu TSS and GDT, so set these when switching
2277 * processors. See 22.2.4.
2279 vmcs_writel(HOST_TR_BASE
,
2280 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2281 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2284 * VM exits change the host TR limit to 0x67 after a VM
2285 * exit. This is okay, since 0x67 covers everything except
2286 * the IO bitmap and have have code to handle the IO bitmap
2287 * being lost after a VM exit.
2289 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2291 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2292 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2294 vmx
->loaded_vmcs
->cpu
= cpu
;
2297 /* Setup TSC multiplier */
2298 if (kvm_has_tsc_control
&&
2299 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2300 decache_tsc_multiplier(vmx
);
2302 vmx_vcpu_pi_load(vcpu
, cpu
);
2303 vmx
->host_pkru
= read_pkru();
2306 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2308 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2310 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2311 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2312 !kvm_vcpu_apicv_active(vcpu
))
2315 /* Set SN when the vCPU is preempted */
2316 if (vcpu
->preempted
)
2320 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2322 vmx_vcpu_pi_put(vcpu
);
2324 __vmx_load_host_state(to_vmx(vcpu
));
2327 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2329 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2332 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2335 * Return the cr0 value that a nested guest would read. This is a combination
2336 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2337 * its hypervisor (cr0_read_shadow).
2339 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2341 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2342 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2344 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2346 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2347 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2350 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2352 unsigned long rflags
, save_rflags
;
2354 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2355 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2356 rflags
= vmcs_readl(GUEST_RFLAGS
);
2357 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2358 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2359 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2360 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2362 to_vmx(vcpu
)->rflags
= rflags
;
2364 return to_vmx(vcpu
)->rflags
;
2367 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2369 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2371 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2372 to_vmx(vcpu
)->rflags
= rflags
;
2373 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2374 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2375 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2377 vmcs_writel(GUEST_RFLAGS
, rflags
);
2379 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2380 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2383 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2385 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2388 if (interruptibility
& GUEST_INTR_STATE_STI
)
2389 ret
|= KVM_X86_SHADOW_INT_STI
;
2390 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2391 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2396 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2398 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2399 u32 interruptibility
= interruptibility_old
;
2401 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2403 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2404 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2405 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2406 interruptibility
|= GUEST_INTR_STATE_STI
;
2408 if ((interruptibility
!= interruptibility_old
))
2409 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2412 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2416 rip
= kvm_rip_read(vcpu
);
2417 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2418 kvm_rip_write(vcpu
, rip
);
2420 /* skipping an emulated instruction also counts */
2421 vmx_set_interrupt_shadow(vcpu
, 0);
2424 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2425 unsigned long exit_qual
)
2427 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2428 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2429 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2431 if (vcpu
->arch
.exception
.has_error_code
) {
2432 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2433 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2436 if (kvm_exception_is_soft(nr
))
2437 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2439 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2441 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2442 vmx_get_nmi_mask(vcpu
))
2443 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2445 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2449 * KVM wants to inject page-faults which it got to the guest. This function
2450 * checks whether in a nested guest, we need to inject them to L1 or L2.
2452 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2454 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2455 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2457 if (nr
== PF_VECTOR
) {
2458 if (vcpu
->arch
.exception
.nested_apf
) {
2459 nested_vmx_inject_exception_vmexit(vcpu
,
2460 vcpu
->arch
.apf
.nested_apf_token
);
2464 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2465 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2466 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2467 * can be written only when inject_pending_event runs. This should be
2468 * conditional on a new capability---if the capability is disabled,
2469 * kvm_multiple_exception would write the ancillary information to
2470 * CR2 or DR6, for backwards ABI-compatibility.
2472 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2473 vcpu
->arch
.exception
.error_code
)) {
2474 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2478 unsigned long exit_qual
= 0;
2479 if (nr
== DB_VECTOR
)
2480 exit_qual
= vcpu
->arch
.dr6
;
2482 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2483 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2491 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2493 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2494 unsigned nr
= vcpu
->arch
.exception
.nr
;
2495 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2496 bool reinject
= vcpu
->arch
.exception
.reinject
;
2497 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2498 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2500 if (!reinject
&& is_guest_mode(vcpu
) &&
2501 nested_vmx_check_exception(vcpu
))
2504 if (has_error_code
) {
2505 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2506 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2509 if (vmx
->rmode
.vm86_active
) {
2511 if (kvm_exception_is_soft(nr
))
2512 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2513 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2514 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2518 if (kvm_exception_is_soft(nr
)) {
2519 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2520 vmx
->vcpu
.arch
.event_exit_inst_len
);
2521 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2523 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2525 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2528 static bool vmx_rdtscp_supported(void)
2530 return cpu_has_vmx_rdtscp();
2533 static bool vmx_invpcid_supported(void)
2535 return cpu_has_vmx_invpcid() && enable_ept
;
2539 * Swap MSR entry in host/guest MSR entry array.
2541 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2543 struct shared_msr_entry tmp
;
2545 tmp
= vmx
->guest_msrs
[to
];
2546 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2547 vmx
->guest_msrs
[from
] = tmp
;
2550 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2552 unsigned long *msr_bitmap
;
2554 if (is_guest_mode(vcpu
))
2555 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2556 else if (cpu_has_secondary_exec_ctrls() &&
2557 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2558 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2559 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2560 if (is_long_mode(vcpu
))
2561 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2563 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2565 if (is_long_mode(vcpu
))
2566 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2568 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2571 if (is_long_mode(vcpu
))
2572 msr_bitmap
= vmx_msr_bitmap_longmode
;
2574 msr_bitmap
= vmx_msr_bitmap_legacy
;
2577 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2581 * Set up the vmcs to automatically save and restore system
2582 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2583 * mode, as fiddling with msrs is very expensive.
2585 static void setup_msrs(struct vcpu_vmx
*vmx
)
2587 int save_nmsrs
, index
;
2590 #ifdef CONFIG_X86_64
2591 if (is_long_mode(&vmx
->vcpu
)) {
2592 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2594 move_msr_up(vmx
, index
, save_nmsrs
++);
2595 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2597 move_msr_up(vmx
, index
, save_nmsrs
++);
2598 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2600 move_msr_up(vmx
, index
, save_nmsrs
++);
2601 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2602 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2603 move_msr_up(vmx
, index
, save_nmsrs
++);
2605 * MSR_STAR is only needed on long mode guests, and only
2606 * if efer.sce is enabled.
2608 index
= __find_msr_index(vmx
, MSR_STAR
);
2609 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2610 move_msr_up(vmx
, index
, save_nmsrs
++);
2613 index
= __find_msr_index(vmx
, MSR_EFER
);
2614 if (index
>= 0 && update_transition_efer(vmx
, index
))
2615 move_msr_up(vmx
, index
, save_nmsrs
++);
2617 vmx
->save_nmsrs
= save_nmsrs
;
2619 if (cpu_has_vmx_msr_bitmap())
2620 vmx_set_msr_bitmap(&vmx
->vcpu
);
2624 * reads and returns guest's timestamp counter "register"
2625 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2626 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2628 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2630 u64 host_tsc
, tsc_offset
;
2633 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2634 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2638 * writes 'offset' into guest's timestamp counter offset register
2640 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2642 if (is_guest_mode(vcpu
)) {
2644 * We're here if L1 chose not to trap WRMSR to TSC. According
2645 * to the spec, this should set L1's TSC; The offset that L1
2646 * set for L2 remains unchanged, and still needs to be added
2647 * to the newly set TSC to get L2's TSC.
2649 struct vmcs12
*vmcs12
;
2650 /* recalculate vmcs02.TSC_OFFSET: */
2651 vmcs12
= get_vmcs12(vcpu
);
2652 vmcs_write64(TSC_OFFSET
, offset
+
2653 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2654 vmcs12
->tsc_offset
: 0));
2656 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2657 vmcs_read64(TSC_OFFSET
), offset
);
2658 vmcs_write64(TSC_OFFSET
, offset
);
2662 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2664 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2665 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2669 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2670 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2671 * all guests if the "nested" module option is off, and can also be disabled
2672 * for a single guest by disabling its VMX cpuid bit.
2674 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2676 return nested
&& guest_cpuid_has_vmx(vcpu
);
2680 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2681 * returned for the various VMX controls MSRs when nested VMX is enabled.
2682 * The same values should also be used to verify that vmcs12 control fields are
2683 * valid during nested entry from L1 to L2.
2684 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2685 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2686 * bit in the high half is on if the corresponding bit in the control field
2687 * may be on. See also vmx_control_verify().
2689 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2692 * Note that as a general rule, the high half of the MSRs (bits in
2693 * the control fields which may be 1) should be initialized by the
2694 * intersection of the underlying hardware's MSR (i.e., features which
2695 * can be supported) and the list of features we want to expose -
2696 * because they are known to be properly supported in our code.
2697 * Also, usually, the low half of the MSRs (bits which must be 1) can
2698 * be set to 0, meaning that L1 may turn off any of these bits. The
2699 * reason is that if one of these bits is necessary, it will appear
2700 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2701 * fields of vmcs01 and vmcs02, will turn these bits off - and
2702 * nested_vmx_exit_reflected() will not pass related exits to L1.
2703 * These rules have exceptions below.
2706 /* pin-based controls */
2707 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2708 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2709 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2710 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2711 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2712 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2713 PIN_BASED_EXT_INTR_MASK
|
2714 PIN_BASED_NMI_EXITING
|
2715 PIN_BASED_VIRTUAL_NMIS
;
2716 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2717 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2718 PIN_BASED_VMX_PREEMPTION_TIMER
;
2719 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2720 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2721 PIN_BASED_POSTED_INTR
;
2724 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2725 vmx
->nested
.nested_vmx_exit_ctls_low
,
2726 vmx
->nested
.nested_vmx_exit_ctls_high
);
2727 vmx
->nested
.nested_vmx_exit_ctls_low
=
2728 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2730 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2731 #ifdef CONFIG_X86_64
2732 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2734 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2735 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2736 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2737 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2738 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2740 if (kvm_mpx_supported())
2741 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2743 /* We support free control of debug control saving. */
2744 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2746 /* entry controls */
2747 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2748 vmx
->nested
.nested_vmx_entry_ctls_low
,
2749 vmx
->nested
.nested_vmx_entry_ctls_high
);
2750 vmx
->nested
.nested_vmx_entry_ctls_low
=
2751 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2752 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2753 #ifdef CONFIG_X86_64
2754 VM_ENTRY_IA32E_MODE
|
2756 VM_ENTRY_LOAD_IA32_PAT
;
2757 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2758 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2759 if (kvm_mpx_supported())
2760 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2762 /* We support free control of debug control loading. */
2763 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2765 /* cpu-based controls */
2766 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2767 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2768 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2769 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2770 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2772 CPU_BASED_VIRTUAL_INTR_PENDING
|
2773 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2774 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2775 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2776 CPU_BASED_CR3_STORE_EXITING
|
2777 #ifdef CONFIG_X86_64
2778 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2780 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2781 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2782 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2783 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2784 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2786 * We can allow some features even when not supported by the
2787 * hardware. For example, L1 can specify an MSR bitmap - and we
2788 * can use it to avoid exits to L1 - even when L0 runs L2
2789 * without MSR bitmaps.
2791 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2792 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2793 CPU_BASED_USE_MSR_BITMAPS
;
2795 /* We support free control of CR3 access interception. */
2796 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2797 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2799 /* secondary cpu-based controls */
2800 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2801 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2802 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2803 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2804 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2805 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2806 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2807 SECONDARY_EXEC_RDTSCP
|
2808 SECONDARY_EXEC_DESC
|
2809 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2810 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2811 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2812 SECONDARY_EXEC_WBINVD_EXITING
|
2813 SECONDARY_EXEC_XSAVES
;
2816 /* nested EPT: emulate EPT also to L1 */
2817 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2818 SECONDARY_EXEC_ENABLE_EPT
;
2819 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2820 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2821 if (cpu_has_vmx_ept_execute_only())
2822 vmx
->nested
.nested_vmx_ept_caps
|=
2823 VMX_EPT_EXECUTE_ONLY_BIT
;
2824 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2825 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2826 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2827 VMX_EPT_1GB_PAGE_BIT
;
2828 if (enable_ept_ad_bits
) {
2829 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2830 SECONDARY_EXEC_ENABLE_PML
;
2831 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2834 vmx
->nested
.nested_vmx_ept_caps
= 0;
2837 * Old versions of KVM use the single-context version without
2838 * checking for support, so declare that it is supported even
2839 * though it is treated as global context. The alternative is
2840 * not failing the single-context invvpid, and it is worse.
2843 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2844 SECONDARY_EXEC_ENABLE_VPID
;
2845 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2846 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2848 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2850 if (enable_unrestricted_guest
)
2851 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2852 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2854 /* miscellaneous data */
2855 rdmsr(MSR_IA32_VMX_MISC
,
2856 vmx
->nested
.nested_vmx_misc_low
,
2857 vmx
->nested
.nested_vmx_misc_high
);
2858 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2859 vmx
->nested
.nested_vmx_misc_low
|=
2860 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2861 VMX_MISC_ACTIVITY_HLT
;
2862 vmx
->nested
.nested_vmx_misc_high
= 0;
2865 * This MSR reports some information about VMX support. We
2866 * should return information about the VMX we emulate for the
2867 * guest, and the VMCS structure we give it - not about the
2868 * VMX support of the underlying hardware.
2870 vmx
->nested
.nested_vmx_basic
=
2872 VMX_BASIC_TRUE_CTLS
|
2873 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2874 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2876 if (cpu_has_vmx_basic_inout())
2877 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2880 * These MSRs specify bits which the guest must keep fixed on
2881 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2882 * We picked the standard core2 setting.
2884 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2885 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2886 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2887 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2889 /* These MSRs specify bits which the guest must keep fixed off. */
2890 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2891 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2893 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2894 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2898 * if fixed0[i] == 1: val[i] must be 1
2899 * if fixed1[i] == 0: val[i] must be 0
2901 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2903 return ((val
& fixed1
) | fixed0
) == val
;
2906 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2908 return fixed_bits_valid(control
, low
, high
);
2911 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2913 return low
| ((u64
)high
<< 32);
2916 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2921 return (superset
| subset
) == superset
;
2924 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2926 const u64 feature_and_reserved
=
2927 /* feature (except bit 48; see below) */
2928 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2930 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2931 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2933 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2937 * KVM does not emulate a version of VMX that constrains physical
2938 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2940 if (data
& BIT_ULL(48))
2943 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2944 vmx_basic_vmcs_revision_id(data
))
2947 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2950 vmx
->nested
.nested_vmx_basic
= data
;
2955 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2960 switch (msr_index
) {
2961 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2962 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2963 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2965 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2966 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2967 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2969 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2970 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2971 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2973 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2974 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2975 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2977 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2978 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2979 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2985 supported
= vmx_control_msr(*lowp
, *highp
);
2987 /* Check must-be-1 bits are still 1. */
2988 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2991 /* Check must-be-0 bits are still 0. */
2992 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2996 *highp
= data
>> 32;
3000 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3002 const u64 feature_and_reserved_bits
=
3004 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3005 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3007 GENMASK_ULL(13, 9) | BIT_ULL(31);
3010 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3011 vmx
->nested
.nested_vmx_misc_high
);
3013 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3016 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3017 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3018 vmx_misc_preemption_timer_rate(data
) !=
3019 vmx_misc_preemption_timer_rate(vmx_misc
))
3022 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3025 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3028 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3031 vmx
->nested
.nested_vmx_misc_low
= data
;
3032 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3036 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3038 u64 vmx_ept_vpid_cap
;
3040 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3041 vmx
->nested
.nested_vmx_vpid_caps
);
3043 /* Every bit is either reserved or a feature bit. */
3044 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3047 vmx
->nested
.nested_vmx_ept_caps
= data
;
3048 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3052 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3056 switch (msr_index
) {
3057 case MSR_IA32_VMX_CR0_FIXED0
:
3058 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3060 case MSR_IA32_VMX_CR4_FIXED0
:
3061 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3068 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3069 * must be 1 in the restored value.
3071 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3079 * Called when userspace is restoring VMX MSRs.
3081 * Returns 0 on success, non-0 otherwise.
3083 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3085 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3087 switch (msr_index
) {
3088 case MSR_IA32_VMX_BASIC
:
3089 return vmx_restore_vmx_basic(vmx
, data
);
3090 case MSR_IA32_VMX_PINBASED_CTLS
:
3091 case MSR_IA32_VMX_PROCBASED_CTLS
:
3092 case MSR_IA32_VMX_EXIT_CTLS
:
3093 case MSR_IA32_VMX_ENTRY_CTLS
:
3095 * The "non-true" VMX capability MSRs are generated from the
3096 * "true" MSRs, so we do not support restoring them directly.
3098 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3099 * should restore the "true" MSRs with the must-be-1 bits
3100 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3101 * DEFAULT SETTINGS".
3104 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3105 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3106 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3107 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3108 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3109 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3110 case MSR_IA32_VMX_MISC
:
3111 return vmx_restore_vmx_misc(vmx
, data
);
3112 case MSR_IA32_VMX_CR0_FIXED0
:
3113 case MSR_IA32_VMX_CR4_FIXED0
:
3114 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3115 case MSR_IA32_VMX_CR0_FIXED1
:
3116 case MSR_IA32_VMX_CR4_FIXED1
:
3118 * These MSRs are generated based on the vCPU's CPUID, so we
3119 * do not support restoring them directly.
3122 case MSR_IA32_VMX_EPT_VPID_CAP
:
3123 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3124 case MSR_IA32_VMX_VMCS_ENUM
:
3125 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3129 * The rest of the VMX capability MSRs do not support restore.
3135 /* Returns 0 on success, non-0 otherwise. */
3136 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3138 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3140 switch (msr_index
) {
3141 case MSR_IA32_VMX_BASIC
:
3142 *pdata
= vmx
->nested
.nested_vmx_basic
;
3144 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3145 case MSR_IA32_VMX_PINBASED_CTLS
:
3146 *pdata
= vmx_control_msr(
3147 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3148 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3149 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3150 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3152 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3153 case MSR_IA32_VMX_PROCBASED_CTLS
:
3154 *pdata
= vmx_control_msr(
3155 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3156 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3157 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3158 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3160 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3161 case MSR_IA32_VMX_EXIT_CTLS
:
3162 *pdata
= vmx_control_msr(
3163 vmx
->nested
.nested_vmx_exit_ctls_low
,
3164 vmx
->nested
.nested_vmx_exit_ctls_high
);
3165 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3166 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3168 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3169 case MSR_IA32_VMX_ENTRY_CTLS
:
3170 *pdata
= vmx_control_msr(
3171 vmx
->nested
.nested_vmx_entry_ctls_low
,
3172 vmx
->nested
.nested_vmx_entry_ctls_high
);
3173 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3174 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3176 case MSR_IA32_VMX_MISC
:
3177 *pdata
= vmx_control_msr(
3178 vmx
->nested
.nested_vmx_misc_low
,
3179 vmx
->nested
.nested_vmx_misc_high
);
3181 case MSR_IA32_VMX_CR0_FIXED0
:
3182 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3184 case MSR_IA32_VMX_CR0_FIXED1
:
3185 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3187 case MSR_IA32_VMX_CR4_FIXED0
:
3188 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3190 case MSR_IA32_VMX_CR4_FIXED1
:
3191 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3193 case MSR_IA32_VMX_VMCS_ENUM
:
3194 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3196 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3197 *pdata
= vmx_control_msr(
3198 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3199 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3201 case MSR_IA32_VMX_EPT_VPID_CAP
:
3202 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3203 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3212 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3215 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3217 return !(val
& ~valid_bits
);
3221 * Reads an msr value (of 'msr_index') into 'pdata'.
3222 * Returns 0 on success, non-0 otherwise.
3223 * Assumes vcpu_load() was already called.
3225 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3227 struct shared_msr_entry
*msr
;
3229 switch (msr_info
->index
) {
3230 #ifdef CONFIG_X86_64
3232 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3235 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3237 case MSR_KERNEL_GS_BASE
:
3238 vmx_load_host_state(to_vmx(vcpu
));
3239 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3243 return kvm_get_msr_common(vcpu
, msr_info
);
3245 msr_info
->data
= guest_read_tsc(vcpu
);
3247 case MSR_IA32_SPEC_CTRL
:
3248 msr_info
->data
= vcpu
->arch
.spec_ctrl
;
3250 case MSR_IA32_SYSENTER_CS
:
3251 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3253 case MSR_IA32_SYSENTER_EIP
:
3254 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3256 case MSR_IA32_SYSENTER_ESP
:
3257 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3259 case MSR_IA32_BNDCFGS
:
3260 if (!kvm_mpx_supported() ||
3261 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3263 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3265 case MSR_IA32_MCG_EXT_CTL
:
3266 if (!msr_info
->host_initiated
&&
3267 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3268 FEATURE_CONTROL_LMCE
))
3270 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3272 case MSR_IA32_FEATURE_CONTROL
:
3273 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3275 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3276 if (!nested_vmx_allowed(vcpu
))
3278 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3280 if (!vmx_xsaves_supported())
3282 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3285 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3287 /* Otherwise falls through */
3289 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3291 msr_info
->data
= msr
->data
;
3294 return kvm_get_msr_common(vcpu
, msr_info
);
3300 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3303 * Writes msr value into into the appropriate "register".
3304 * Returns 0 on success, non-0 otherwise.
3305 * Assumes vcpu_load() was already called.
3307 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3309 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3310 struct shared_msr_entry
*msr
;
3312 u32 msr_index
= msr_info
->index
;
3313 u64 data
= msr_info
->data
;
3315 switch (msr_index
) {
3317 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3319 #ifdef CONFIG_X86_64
3321 vmx_segment_cache_clear(vmx
);
3322 vmcs_writel(GUEST_FS_BASE
, data
);
3325 vmx_segment_cache_clear(vmx
);
3326 vmcs_writel(GUEST_GS_BASE
, data
);
3328 case MSR_KERNEL_GS_BASE
:
3329 vmx_load_host_state(vmx
);
3330 vmx
->msr_guest_kernel_gs_base
= data
;
3333 case MSR_IA32_SYSENTER_CS
:
3334 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3336 case MSR_IA32_SYSENTER_EIP
:
3337 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3339 case MSR_IA32_SYSENTER_ESP
:
3340 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3342 case MSR_IA32_BNDCFGS
:
3343 if (!kvm_mpx_supported() ||
3344 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3346 if (is_noncanonical_address(data
& PAGE_MASK
) ||
3347 (data
& MSR_IA32_BNDCFGS_RSVD
))
3349 vmcs_write64(GUEST_BNDCFGS
, data
);
3352 kvm_write_tsc(vcpu
, msr_info
);
3354 case MSR_IA32_SPEC_CTRL
:
3355 vcpu
->arch
.spec_ctrl
= msr_info
->data
;
3357 case MSR_IA32_CR_PAT
:
3358 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3359 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3361 vmcs_write64(GUEST_IA32_PAT
, data
);
3362 vcpu
->arch
.pat
= data
;
3365 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3367 case MSR_IA32_TSC_ADJUST
:
3368 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3370 case MSR_IA32_MCG_EXT_CTL
:
3371 if ((!msr_info
->host_initiated
&&
3372 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3373 FEATURE_CONTROL_LMCE
)) ||
3374 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3376 vcpu
->arch
.mcg_ext_ctl
= data
;
3378 case MSR_IA32_FEATURE_CONTROL
:
3379 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3380 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3381 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3383 vmx
->msr_ia32_feature_control
= data
;
3384 if (msr_info
->host_initiated
&& data
== 0)
3385 vmx_leave_nested(vcpu
);
3387 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3388 if (!msr_info
->host_initiated
)
3389 return 1; /* they are read-only */
3390 if (!nested_vmx_allowed(vcpu
))
3392 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3394 if (!vmx_xsaves_supported())
3397 * The only supported bit as of Skylake is bit 8, but
3398 * it is not supported on KVM.
3402 vcpu
->arch
.ia32_xss
= data
;
3403 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3404 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3405 vcpu
->arch
.ia32_xss
, host_xss
);
3407 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3410 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3412 /* Check reserved bit, higher 32 bits should be zero */
3413 if ((data
>> 32) != 0)
3415 /* Otherwise falls through */
3417 msr
= find_msr_entry(vmx
, msr_index
);
3419 u64 old_msr_data
= msr
->data
;
3421 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3423 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3427 msr
->data
= old_msr_data
;
3431 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3437 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3439 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3442 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3445 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3447 case VCPU_EXREG_PDPTR
:
3449 ept_save_pdptrs(vcpu
);
3456 static __init
int cpu_has_kvm_support(void)
3458 return cpu_has_vmx();
3461 static __init
int vmx_disabled_by_bios(void)
3465 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3466 if (msr
& FEATURE_CONTROL_LOCKED
) {
3467 /* launched w/ TXT and VMX disabled */
3468 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3471 /* launched w/o TXT and VMX only enabled w/ TXT */
3472 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3473 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3474 && !tboot_enabled()) {
3475 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3476 "activate TXT before enabling KVM\n");
3479 /* launched w/o TXT and VMX disabled */
3480 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3481 && !tboot_enabled())
3488 static void kvm_cpu_vmxon(u64 addr
)
3490 cr4_set_bits(X86_CR4_VMXE
);
3491 intel_pt_handle_vmx(1);
3493 asm volatile (ASM_VMX_VMXON_RAX
3494 : : "a"(&addr
), "m"(addr
)
3498 static int hardware_enable(void)
3500 int cpu
= raw_smp_processor_id();
3501 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3504 if (cr4_read_shadow() & X86_CR4_VMXE
)
3507 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3508 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3509 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3512 * Now we can enable the vmclear operation in kdump
3513 * since the loaded_vmcss_on_cpu list on this cpu
3514 * has been initialized.
3516 * Though the cpu is not in VMX operation now, there
3517 * is no problem to enable the vmclear operation
3518 * for the loaded_vmcss_on_cpu list is empty!
3520 crash_enable_local_vmclear(cpu
);
3522 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3524 test_bits
= FEATURE_CONTROL_LOCKED
;
3525 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3526 if (tboot_enabled())
3527 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3529 if ((old
& test_bits
) != test_bits
) {
3530 /* enable and lock */
3531 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3533 kvm_cpu_vmxon(phys_addr
);
3539 static void vmclear_local_loaded_vmcss(void)
3541 int cpu
= raw_smp_processor_id();
3542 struct loaded_vmcs
*v
, *n
;
3544 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3545 loaded_vmcss_on_cpu_link
)
3546 __loaded_vmcs_clear(v
);
3550 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3553 static void kvm_cpu_vmxoff(void)
3555 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3557 intel_pt_handle_vmx(0);
3558 cr4_clear_bits(X86_CR4_VMXE
);
3561 static void hardware_disable(void)
3563 vmclear_local_loaded_vmcss();
3567 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3568 u32 msr
, u32
*result
)
3570 u32 vmx_msr_low
, vmx_msr_high
;
3571 u32 ctl
= ctl_min
| ctl_opt
;
3573 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3575 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3576 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3578 /* Ensure minimum (required) set of control bits are supported. */
3586 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3588 u32 vmx_msr_low
, vmx_msr_high
;
3590 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3591 return vmx_msr_high
& ctl
;
3594 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3596 u32 vmx_msr_low
, vmx_msr_high
;
3597 u32 min
, opt
, min2
, opt2
;
3598 u32 _pin_based_exec_control
= 0;
3599 u32 _cpu_based_exec_control
= 0;
3600 u32 _cpu_based_2nd_exec_control
= 0;
3601 u32 _vmexit_control
= 0;
3602 u32 _vmentry_control
= 0;
3604 min
= CPU_BASED_HLT_EXITING
|
3605 #ifdef CONFIG_X86_64
3606 CPU_BASED_CR8_LOAD_EXITING
|
3607 CPU_BASED_CR8_STORE_EXITING
|
3609 CPU_BASED_CR3_LOAD_EXITING
|
3610 CPU_BASED_CR3_STORE_EXITING
|
3611 CPU_BASED_USE_IO_BITMAPS
|
3612 CPU_BASED_MOV_DR_EXITING
|
3613 CPU_BASED_USE_TSC_OFFSETING
|
3614 CPU_BASED_INVLPG_EXITING
|
3615 CPU_BASED_RDPMC_EXITING
;
3617 if (!kvm_mwait_in_guest())
3618 min
|= CPU_BASED_MWAIT_EXITING
|
3619 CPU_BASED_MONITOR_EXITING
;
3621 opt
= CPU_BASED_TPR_SHADOW
|
3622 CPU_BASED_USE_MSR_BITMAPS
|
3623 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3624 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3625 &_cpu_based_exec_control
) < 0)
3627 #ifdef CONFIG_X86_64
3628 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3629 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3630 ~CPU_BASED_CR8_STORE_EXITING
;
3632 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3634 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3635 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3636 SECONDARY_EXEC_WBINVD_EXITING
|
3637 SECONDARY_EXEC_ENABLE_VPID
|
3638 SECONDARY_EXEC_ENABLE_EPT
|
3639 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3640 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3641 SECONDARY_EXEC_RDTSCP
|
3642 SECONDARY_EXEC_ENABLE_INVPCID
|
3643 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3644 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3645 SECONDARY_EXEC_SHADOW_VMCS
|
3646 SECONDARY_EXEC_XSAVES
|
3647 SECONDARY_EXEC_ENABLE_PML
|
3648 SECONDARY_EXEC_TSC_SCALING
;
3649 if (adjust_vmx_controls(min2
, opt2
,
3650 MSR_IA32_VMX_PROCBASED_CTLS2
,
3651 &_cpu_based_2nd_exec_control
) < 0)
3654 #ifndef CONFIG_X86_64
3655 if (!(_cpu_based_2nd_exec_control
&
3656 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3657 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3660 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3661 _cpu_based_2nd_exec_control
&= ~(
3662 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3663 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3664 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3666 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3667 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3669 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3670 CPU_BASED_CR3_STORE_EXITING
|
3671 CPU_BASED_INVLPG_EXITING
);
3672 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3673 vmx_capability
.ept
, vmx_capability
.vpid
);
3676 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3677 #ifdef CONFIG_X86_64
3678 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3680 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3681 VM_EXIT_CLEAR_BNDCFGS
;
3682 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3683 &_vmexit_control
) < 0)
3686 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3687 PIN_BASED_VIRTUAL_NMIS
;
3688 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3689 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3690 &_pin_based_exec_control
) < 0)
3693 if (cpu_has_broken_vmx_preemption_timer())
3694 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3695 if (!(_cpu_based_2nd_exec_control
&
3696 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3697 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3699 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3700 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3701 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3702 &_vmentry_control
) < 0)
3705 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3707 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3708 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3711 #ifdef CONFIG_X86_64
3712 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3713 if (vmx_msr_high
& (1u<<16))
3717 /* Require Write-Back (WB) memory type for VMCS accesses. */
3718 if (((vmx_msr_high
>> 18) & 15) != 6)
3721 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3722 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3723 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3724 vmcs_conf
->revision_id
= vmx_msr_low
;
3726 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3727 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3728 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3729 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3730 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3732 cpu_has_load_ia32_efer
=
3733 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3734 VM_ENTRY_LOAD_IA32_EFER
)
3735 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3736 VM_EXIT_LOAD_IA32_EFER
);
3738 cpu_has_load_perf_global_ctrl
=
3739 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3740 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3741 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3742 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3745 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3746 * but due to errata below it can't be used. Workaround is to use
3747 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3749 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3754 * BC86,AAY89,BD102 (model 44)
3758 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3759 switch (boot_cpu_data
.x86_model
) {
3765 cpu_has_load_perf_global_ctrl
= false;
3766 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3767 "does not work properly. Using workaround\n");
3774 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3775 rdmsrl(MSR_IA32_XSS
, host_xss
);
3780 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3782 int node
= cpu_to_node(cpu
);
3786 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3789 vmcs
= page_address(pages
);
3790 memset(vmcs
, 0, vmcs_config
.size
);
3791 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3795 static struct vmcs
*alloc_vmcs(void)
3797 return alloc_vmcs_cpu(raw_smp_processor_id());
3800 static void free_vmcs(struct vmcs
*vmcs
)
3802 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3806 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3808 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3810 if (!loaded_vmcs
->vmcs
)
3812 loaded_vmcs_clear(loaded_vmcs
);
3813 free_vmcs(loaded_vmcs
->vmcs
);
3814 loaded_vmcs
->vmcs
= NULL
;
3815 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3818 static void free_kvm_area(void)
3822 for_each_possible_cpu(cpu
) {
3823 free_vmcs(per_cpu(vmxarea
, cpu
));
3824 per_cpu(vmxarea
, cpu
) = NULL
;
3828 enum vmcs_field_type
{
3829 VMCS_FIELD_TYPE_U16
= 0,
3830 VMCS_FIELD_TYPE_U64
= 1,
3831 VMCS_FIELD_TYPE_U32
= 2,
3832 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3835 static inline int vmcs_field_type(unsigned long field
)
3837 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3838 return VMCS_FIELD_TYPE_U32
;
3839 return (field
>> 13) & 0x3 ;
3842 static inline int vmcs_field_readonly(unsigned long field
)
3844 return (((field
>> 10) & 0x3) == 1);
3847 static void init_vmcs_shadow_fields(void)
3851 /* No checks for read only fields yet */
3853 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3854 switch (shadow_read_write_fields
[i
]) {
3856 if (!kvm_mpx_supported())
3864 shadow_read_write_fields
[j
] =
3865 shadow_read_write_fields
[i
];
3868 max_shadow_read_write_fields
= j
;
3870 /* shadowed fields guest access without vmexit */
3871 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3872 unsigned long field
= shadow_read_write_fields
[i
];
3874 clear_bit(field
, vmx_vmwrite_bitmap
);
3875 clear_bit(field
, vmx_vmread_bitmap
);
3876 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3877 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3878 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3881 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3882 unsigned long field
= shadow_read_only_fields
[i
];
3884 clear_bit(field
, vmx_vmread_bitmap
);
3885 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3886 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3890 static __init
int alloc_kvm_area(void)
3894 for_each_possible_cpu(cpu
) {
3897 vmcs
= alloc_vmcs_cpu(cpu
);
3903 per_cpu(vmxarea
, cpu
) = vmcs
;
3908 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3909 struct kvm_segment
*save
)
3911 if (!emulate_invalid_guest_state
) {
3913 * CS and SS RPL should be equal during guest entry according
3914 * to VMX spec, but in reality it is not always so. Since vcpu
3915 * is in the middle of the transition from real mode to
3916 * protected mode it is safe to assume that RPL 0 is a good
3919 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3920 save
->selector
&= ~SEGMENT_RPL_MASK
;
3921 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3924 vmx_set_segment(vcpu
, save
, seg
);
3927 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3929 unsigned long flags
;
3930 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3933 * Update real mode segment cache. It may be not up-to-date if sement
3934 * register was written while vcpu was in a guest mode.
3936 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3937 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3938 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3939 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3940 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3941 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3943 vmx
->rmode
.vm86_active
= 0;
3945 vmx_segment_cache_clear(vmx
);
3947 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3949 flags
= vmcs_readl(GUEST_RFLAGS
);
3950 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3951 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3952 vmcs_writel(GUEST_RFLAGS
, flags
);
3954 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3955 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3957 update_exception_bitmap(vcpu
);
3959 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3960 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3961 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3962 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3963 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3964 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3967 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3969 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3970 struct kvm_segment var
= *save
;
3973 if (seg
== VCPU_SREG_CS
)
3976 if (!emulate_invalid_guest_state
) {
3977 var
.selector
= var
.base
>> 4;
3978 var
.base
= var
.base
& 0xffff0;
3988 if (save
->base
& 0xf)
3989 printk_once(KERN_WARNING
"kvm: segment base is not "
3990 "paragraph aligned when entering "
3991 "protected mode (seg=%d)", seg
);
3994 vmcs_write16(sf
->selector
, var
.selector
);
3995 vmcs_writel(sf
->base
, var
.base
);
3996 vmcs_write32(sf
->limit
, var
.limit
);
3997 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4000 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4002 unsigned long flags
;
4003 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4005 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4006 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4007 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4008 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4009 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4010 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4011 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4013 vmx
->rmode
.vm86_active
= 1;
4016 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4017 * vcpu. Warn the user that an update is overdue.
4019 if (!vcpu
->kvm
->arch
.tss_addr
)
4020 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4021 "called before entering vcpu\n");
4023 vmx_segment_cache_clear(vmx
);
4025 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4026 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4027 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4029 flags
= vmcs_readl(GUEST_RFLAGS
);
4030 vmx
->rmode
.save_rflags
= flags
;
4032 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4034 vmcs_writel(GUEST_RFLAGS
, flags
);
4035 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4036 update_exception_bitmap(vcpu
);
4038 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4039 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4040 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4041 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4042 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4043 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4045 kvm_mmu_reset_context(vcpu
);
4048 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4050 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4051 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4057 * Force kernel_gs_base reloading before EFER changes, as control
4058 * of this msr depends on is_long_mode().
4060 vmx_load_host_state(to_vmx(vcpu
));
4061 vcpu
->arch
.efer
= efer
;
4062 if (efer
& EFER_LMA
) {
4063 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4066 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4068 msr
->data
= efer
& ~EFER_LME
;
4073 #ifdef CONFIG_X86_64
4075 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4079 vmx_segment_cache_clear(to_vmx(vcpu
));
4081 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4082 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4083 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4085 vmcs_write32(GUEST_TR_AR_BYTES
,
4086 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4087 | VMX_AR_TYPE_BUSY_64_TSS
);
4089 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4092 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4094 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4095 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4100 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4103 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4105 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4107 vpid_sync_context(vpid
);
4111 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4113 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4116 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4119 vmx_flush_tlb(vcpu
);
4122 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4124 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4126 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4127 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4130 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4132 if (enable_ept
&& is_paging(vcpu
))
4133 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4134 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4137 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4139 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4141 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4142 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4145 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4147 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4149 if (!test_bit(VCPU_EXREG_PDPTR
,
4150 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4153 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4154 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4155 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4156 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4157 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4161 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4163 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4165 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4166 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4167 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4168 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4169 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4172 __set_bit(VCPU_EXREG_PDPTR
,
4173 (unsigned long *)&vcpu
->arch
.regs_avail
);
4174 __set_bit(VCPU_EXREG_PDPTR
,
4175 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4178 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4180 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4181 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4182 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4184 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4185 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4186 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4187 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4189 return fixed_bits_valid(val
, fixed0
, fixed1
);
4192 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4194 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4195 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4197 return fixed_bits_valid(val
, fixed0
, fixed1
);
4200 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4202 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4203 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4205 return fixed_bits_valid(val
, fixed0
, fixed1
);
4208 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4209 #define nested_guest_cr4_valid nested_cr4_valid
4210 #define nested_host_cr4_valid nested_cr4_valid
4212 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4214 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4216 struct kvm_vcpu
*vcpu
)
4218 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4219 vmx_decache_cr3(vcpu
);
4220 if (!(cr0
& X86_CR0_PG
)) {
4221 /* From paging/starting to nonpaging */
4222 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4223 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4224 (CPU_BASED_CR3_LOAD_EXITING
|
4225 CPU_BASED_CR3_STORE_EXITING
));
4226 vcpu
->arch
.cr0
= cr0
;
4227 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4228 } else if (!is_paging(vcpu
)) {
4229 /* From nonpaging to paging */
4230 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4231 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4232 ~(CPU_BASED_CR3_LOAD_EXITING
|
4233 CPU_BASED_CR3_STORE_EXITING
));
4234 vcpu
->arch
.cr0
= cr0
;
4235 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4238 if (!(cr0
& X86_CR0_WP
))
4239 *hw_cr0
&= ~X86_CR0_WP
;
4242 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4245 unsigned long hw_cr0
;
4247 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4248 if (enable_unrestricted_guest
)
4249 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4251 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4253 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4256 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4260 #ifdef CONFIG_X86_64
4261 if (vcpu
->arch
.efer
& EFER_LME
) {
4262 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4264 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4270 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4272 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4273 vmcs_writel(GUEST_CR0
, hw_cr0
);
4274 vcpu
->arch
.cr0
= cr0
;
4276 /* depends on vcpu->arch.cr0 to be set to a new value */
4277 vmx
->emulation_required
= emulation_required(vcpu
);
4280 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4284 /* TODO write the value reading from MSR */
4285 eptp
= VMX_EPT_DEFAULT_MT
|
4286 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4287 if (enable_ept_ad_bits
&&
4288 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4289 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4290 eptp
|= (root_hpa
& PAGE_MASK
);
4295 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4297 unsigned long guest_cr3
;
4302 eptp
= construct_eptp(vcpu
, cr3
);
4303 vmcs_write64(EPT_POINTER
, eptp
);
4304 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4305 guest_cr3
= kvm_read_cr3(vcpu
);
4307 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4308 ept_load_pdptrs(vcpu
);
4311 vmx_flush_tlb(vcpu
);
4312 vmcs_writel(GUEST_CR3
, guest_cr3
);
4315 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4318 * Pass through host's Machine Check Enable value to hw_cr4, which
4319 * is in force while we are in guest mode. Do not let guests control
4320 * this bit, even if host CR4.MCE == 0.
4322 unsigned long hw_cr4
=
4323 (cr4_read_shadow() & X86_CR4_MCE
) |
4324 (cr4
& ~X86_CR4_MCE
) |
4325 (to_vmx(vcpu
)->rmode
.vm86_active
?
4326 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4328 if (cr4
& X86_CR4_VMXE
) {
4330 * To use VMXON (and later other VMX instructions), a guest
4331 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4332 * So basically the check on whether to allow nested VMX
4335 if (!nested_vmx_allowed(vcpu
))
4339 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4342 vcpu
->arch
.cr4
= cr4
;
4344 if (!is_paging(vcpu
)) {
4345 hw_cr4
&= ~X86_CR4_PAE
;
4346 hw_cr4
|= X86_CR4_PSE
;
4347 } else if (!(cr4
& X86_CR4_PAE
)) {
4348 hw_cr4
&= ~X86_CR4_PAE
;
4352 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4354 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4355 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4356 * to be manually disabled when guest switches to non-paging
4359 * If !enable_unrestricted_guest, the CPU is always running
4360 * with CR0.PG=1 and CR4 needs to be modified.
4361 * If enable_unrestricted_guest, the CPU automatically
4362 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4364 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4366 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4367 vmcs_writel(GUEST_CR4
, hw_cr4
);
4371 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4372 struct kvm_segment
*var
, int seg
)
4374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4377 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4378 *var
= vmx
->rmode
.segs
[seg
];
4379 if (seg
== VCPU_SREG_TR
4380 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4382 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4383 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4386 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4387 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4388 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4389 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4390 var
->unusable
= (ar
>> 16) & 1;
4391 var
->type
= ar
& 15;
4392 var
->s
= (ar
>> 4) & 1;
4393 var
->dpl
= (ar
>> 5) & 3;
4395 * Some userspaces do not preserve unusable property. Since usable
4396 * segment has to be present according to VMX spec we can use present
4397 * property to amend userspace bug by making unusable segment always
4398 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4399 * segment as unusable.
4401 var
->present
= !var
->unusable
;
4402 var
->avl
= (ar
>> 12) & 1;
4403 var
->l
= (ar
>> 13) & 1;
4404 var
->db
= (ar
>> 14) & 1;
4405 var
->g
= (ar
>> 15) & 1;
4408 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4410 struct kvm_segment s
;
4412 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4413 vmx_get_segment(vcpu
, &s
, seg
);
4416 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4419 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4421 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4423 if (unlikely(vmx
->rmode
.vm86_active
))
4426 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4427 return VMX_AR_DPL(ar
);
4431 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4435 if (var
->unusable
|| !var
->present
)
4438 ar
= var
->type
& 15;
4439 ar
|= (var
->s
& 1) << 4;
4440 ar
|= (var
->dpl
& 3) << 5;
4441 ar
|= (var
->present
& 1) << 7;
4442 ar
|= (var
->avl
& 1) << 12;
4443 ar
|= (var
->l
& 1) << 13;
4444 ar
|= (var
->db
& 1) << 14;
4445 ar
|= (var
->g
& 1) << 15;
4451 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4452 struct kvm_segment
*var
, int seg
)
4454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4455 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4457 vmx_segment_cache_clear(vmx
);
4459 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4460 vmx
->rmode
.segs
[seg
] = *var
;
4461 if (seg
== VCPU_SREG_TR
)
4462 vmcs_write16(sf
->selector
, var
->selector
);
4464 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4468 vmcs_writel(sf
->base
, var
->base
);
4469 vmcs_write32(sf
->limit
, var
->limit
);
4470 vmcs_write16(sf
->selector
, var
->selector
);
4473 * Fix the "Accessed" bit in AR field of segment registers for older
4475 * IA32 arch specifies that at the time of processor reset the
4476 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4477 * is setting it to 0 in the userland code. This causes invalid guest
4478 * state vmexit when "unrestricted guest" mode is turned on.
4479 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4480 * tree. Newer qemu binaries with that qemu fix would not need this
4483 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4484 var
->type
|= 0x1; /* Accessed */
4486 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4489 vmx
->emulation_required
= emulation_required(vcpu
);
4492 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4494 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4496 *db
= (ar
>> 14) & 1;
4497 *l
= (ar
>> 13) & 1;
4500 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4502 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4503 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4506 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4508 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4509 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4512 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4514 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4515 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4518 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4520 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4521 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4524 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4526 struct kvm_segment var
;
4529 vmx_get_segment(vcpu
, &var
, seg
);
4531 if (seg
== VCPU_SREG_CS
)
4533 ar
= vmx_segment_access_rights(&var
);
4535 if (var
.base
!= (var
.selector
<< 4))
4537 if (var
.limit
!= 0xffff)
4545 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4547 struct kvm_segment cs
;
4548 unsigned int cs_rpl
;
4550 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4551 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4555 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4559 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4560 if (cs
.dpl
> cs_rpl
)
4563 if (cs
.dpl
!= cs_rpl
)
4569 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4573 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4575 struct kvm_segment ss
;
4576 unsigned int ss_rpl
;
4578 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4579 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4583 if (ss
.type
!= 3 && ss
.type
!= 7)
4587 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4595 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4597 struct kvm_segment var
;
4600 vmx_get_segment(vcpu
, &var
, seg
);
4601 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4609 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4610 if (var
.dpl
< rpl
) /* DPL < RPL */
4614 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4620 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4622 struct kvm_segment tr
;
4624 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4628 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4630 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4638 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4640 struct kvm_segment ldtr
;
4642 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4646 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4656 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4658 struct kvm_segment cs
, ss
;
4660 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4661 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4663 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4664 (ss
.selector
& SEGMENT_RPL_MASK
));
4668 * Check if guest state is valid. Returns true if valid, false if
4670 * We assume that registers are always usable
4672 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4674 if (enable_unrestricted_guest
)
4677 /* real mode guest state checks */
4678 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4679 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4681 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4683 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4685 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4687 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4689 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4692 /* protected mode guest state checks */
4693 if (!cs_ss_rpl_check(vcpu
))
4695 if (!code_segment_valid(vcpu
))
4697 if (!stack_segment_valid(vcpu
))
4699 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4701 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4703 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4705 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4707 if (!tr_valid(vcpu
))
4709 if (!ldtr_valid(vcpu
))
4713 * - Add checks on RIP
4714 * - Add checks on RFLAGS
4720 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4722 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4725 static int init_rmode_tss(struct kvm
*kvm
)
4731 idx
= srcu_read_lock(&kvm
->srcu
);
4732 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4733 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4736 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4737 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4738 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4741 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4744 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4748 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4749 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4752 srcu_read_unlock(&kvm
->srcu
, idx
);
4756 static int init_rmode_identity_map(struct kvm
*kvm
)
4759 kvm_pfn_t identity_map_pfn
;
4765 /* Protect kvm->arch.ept_identity_pagetable_done. */
4766 mutex_lock(&kvm
->slots_lock
);
4768 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4771 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4773 r
= alloc_identity_pagetable(kvm
);
4777 idx
= srcu_read_lock(&kvm
->srcu
);
4778 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4781 /* Set up identity-mapping pagetable for EPT in real mode */
4782 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4783 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4784 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4785 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4786 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4790 kvm
->arch
.ept_identity_pagetable_done
= true;
4793 srcu_read_unlock(&kvm
->srcu
, idx
);
4796 mutex_unlock(&kvm
->slots_lock
);
4800 static void seg_setup(int seg
)
4802 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4805 vmcs_write16(sf
->selector
, 0);
4806 vmcs_writel(sf
->base
, 0);
4807 vmcs_write32(sf
->limit
, 0xffff);
4809 if (seg
== VCPU_SREG_CS
)
4810 ar
|= 0x08; /* code segment */
4812 vmcs_write32(sf
->ar_bytes
, ar
);
4815 static int alloc_apic_access_page(struct kvm
*kvm
)
4820 mutex_lock(&kvm
->slots_lock
);
4821 if (kvm
->arch
.apic_access_page_done
)
4823 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4824 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4828 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4829 if (is_error_page(page
)) {
4835 * Do not pin the page in memory, so that memory hot-unplug
4836 * is able to migrate it.
4839 kvm
->arch
.apic_access_page_done
= true;
4841 mutex_unlock(&kvm
->slots_lock
);
4845 static int alloc_identity_pagetable(struct kvm
*kvm
)
4847 /* Called with kvm->slots_lock held. */
4851 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4853 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4854 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4859 static int allocate_vpid(void)
4865 spin_lock(&vmx_vpid_lock
);
4866 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4867 if (vpid
< VMX_NR_VPIDS
)
4868 __set_bit(vpid
, vmx_vpid_bitmap
);
4871 spin_unlock(&vmx_vpid_lock
);
4875 static void free_vpid(int vpid
)
4877 if (!enable_vpid
|| vpid
== 0)
4879 spin_lock(&vmx_vpid_lock
);
4880 __clear_bit(vpid
, vmx_vpid_bitmap
);
4881 spin_unlock(&vmx_vpid_lock
);
4884 #define MSR_TYPE_R 1
4885 #define MSR_TYPE_W 2
4886 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4889 int f
= sizeof(unsigned long);
4891 if (!cpu_has_vmx_msr_bitmap())
4895 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4896 * have the write-low and read-high bitmap offsets the wrong way round.
4897 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4899 if (msr
<= 0x1fff) {
4900 if (type
& MSR_TYPE_R
)
4902 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4904 if (type
& MSR_TYPE_W
)
4906 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4908 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4910 if (type
& MSR_TYPE_R
)
4912 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4914 if (type
& MSR_TYPE_W
)
4916 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4922 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4923 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4925 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4926 unsigned long *msr_bitmap_nested
,
4929 int f
= sizeof(unsigned long);
4931 if (!cpu_has_vmx_msr_bitmap()) {
4937 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4938 * have the write-low and read-high bitmap offsets the wrong way round.
4939 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4941 if (msr
<= 0x1fff) {
4942 if (type
& MSR_TYPE_R
&&
4943 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4945 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4947 if (type
& MSR_TYPE_W
&&
4948 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4950 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4952 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4954 if (type
& MSR_TYPE_R
&&
4955 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4957 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4959 if (type
& MSR_TYPE_W
&&
4960 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4962 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4967 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4970 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4971 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4972 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4973 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4976 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4979 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4981 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4984 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4986 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4991 static bool vmx_get_enable_apicv(void)
4993 return enable_apicv
;
4996 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
4998 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5002 * Don't need to mark the APIC access page dirty; it is never
5003 * written to by the CPU during APIC virtualization.
5006 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5007 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5008 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5011 if (nested_cpu_has_posted_intr(vmcs12
)) {
5012 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5013 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5018 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5020 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5025 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5028 vmx
->nested
.pi_pending
= false;
5029 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5032 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5033 if (max_irr
!= 256) {
5034 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5035 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5036 kunmap(vmx
->nested
.virtual_apic_page
);
5038 status
= vmcs_read16(GUEST_INTR_STATUS
);
5039 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5041 status
|= (u8
)max_irr
;
5042 vmcs_write16(GUEST_INTR_STATUS
, status
);
5046 nested_mark_vmcs12_pages_dirty(vcpu
);
5049 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5053 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5055 if (vcpu
->mode
== IN_GUEST_MODE
) {
5057 * The vector of interrupt to be delivered to vcpu had
5058 * been set in PIR before this function.
5060 * Following cases will be reached in this block, and
5061 * we always send a notification event in all cases as
5064 * Case 1: vcpu keeps in non-root mode. Sending a
5065 * notification event posts the interrupt to vcpu.
5067 * Case 2: vcpu exits to root mode and is still
5068 * runnable. PIR will be synced to vIRR before the
5069 * next vcpu entry. Sending a notification event in
5070 * this case has no effect, as vcpu is not in root
5073 * Case 3: vcpu exits to root mode and is blocked.
5074 * vcpu_block() has already synced PIR to vIRR and
5075 * never blocks vcpu if vIRR is not cleared. Therefore,
5076 * a blocked vcpu here does not wait for any requested
5077 * interrupts in PIR, and sending a notification event
5078 * which has no effect is safe here.
5081 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5088 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5091 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5093 if (is_guest_mode(vcpu
) &&
5094 vector
== vmx
->nested
.posted_intr_nv
) {
5095 /* the PIR and ON have been set by L1. */
5096 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5098 * If a posted intr is not recognized by hardware,
5099 * we will accomplish it in the next vmentry.
5101 vmx
->nested
.pi_pending
= true;
5102 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5108 * Send interrupt to vcpu via posted interrupt way.
5109 * 1. If target vcpu is running(non-root mode), send posted interrupt
5110 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5111 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5112 * interrupt from PIR in next vmentry.
5114 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5116 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5119 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5123 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5126 /* If a previous notification has sent the IPI, nothing to do. */
5127 if (pi_test_and_set_on(&vmx
->pi_desc
))
5130 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5131 kvm_vcpu_kick(vcpu
);
5135 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5136 * will not change in the lifetime of the guest.
5137 * Note that host-state that does change is set elsewhere. E.g., host-state
5138 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5140 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5145 unsigned long cr0
, cr3
, cr4
;
5148 WARN_ON(cr0
& X86_CR0_TS
);
5149 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5152 * Save the most likely value for this task's CR3 in the VMCS.
5153 * We can't use __get_current_cr3_fast() because we're not atomic.
5156 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5157 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5159 /* Save the most likely value for this task's CR4 in the VMCS. */
5160 cr4
= cr4_read_shadow();
5161 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5162 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5164 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5165 #ifdef CONFIG_X86_64
5167 * Load null selectors, so we can avoid reloading them in
5168 * __vmx_load_host_state(), in case userspace uses the null selectors
5169 * too (the expected case).
5171 vmcs_write16(HOST_DS_SELECTOR
, 0);
5172 vmcs_write16(HOST_ES_SELECTOR
, 0);
5174 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5175 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5177 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5178 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5181 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5182 vmx
->host_idt_base
= dt
.address
;
5184 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5186 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5187 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5188 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5189 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5191 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5192 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5193 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5197 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5199 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5201 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5202 if (is_guest_mode(&vmx
->vcpu
))
5203 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5204 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5205 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5208 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5210 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5212 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5213 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5214 /* Enable the preemption timer dynamically */
5215 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5216 return pin_based_exec_ctrl
;
5219 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5221 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5223 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5224 if (cpu_has_secondary_exec_ctrls()) {
5225 if (kvm_vcpu_apicv_active(vcpu
))
5226 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5227 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5228 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5230 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5231 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5232 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5235 if (cpu_has_vmx_msr_bitmap())
5236 vmx_set_msr_bitmap(vcpu
);
5239 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5241 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5243 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5244 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5246 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5247 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5248 #ifdef CONFIG_X86_64
5249 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5250 CPU_BASED_CR8_LOAD_EXITING
;
5254 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5255 CPU_BASED_CR3_LOAD_EXITING
|
5256 CPU_BASED_INVLPG_EXITING
;
5257 return exec_control
;
5260 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5262 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5263 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5264 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5266 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5268 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5269 enable_unrestricted_guest
= 0;
5270 /* Enable INVPCID for non-ept guests may cause performance regression. */
5271 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5273 if (!enable_unrestricted_guest
)
5274 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5276 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5277 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5278 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5279 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5280 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5281 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5283 We can NOT enable shadow_vmcs here because we don't have yet
5286 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5289 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5291 return exec_control
;
5294 static void ept_set_mmio_spte_mask(void)
5297 * EPT Misconfigurations can be generated if the value of bits 2:0
5298 * of an EPT paging-structure entry is 110b (write/execute).
5300 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5301 VMX_EPT_MISCONFIG_WX_VALUE
);
5304 #define VMX_XSS_EXIT_BITMAP 0
5306 * Sets up the vmcs for emulated real mode.
5308 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5310 #ifdef CONFIG_X86_64
5316 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5317 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5319 if (enable_shadow_vmcs
) {
5320 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5321 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5323 if (cpu_has_vmx_msr_bitmap())
5324 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5326 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5329 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5330 vmx
->hv_deadline_tsc
= -1;
5332 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5334 if (cpu_has_secondary_exec_ctrls()) {
5335 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5336 vmx_secondary_exec_control(vmx
));
5339 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5340 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5341 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5342 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5343 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5345 vmcs_write16(GUEST_INTR_STATUS
, 0);
5347 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5348 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5352 vmcs_write32(PLE_GAP
, ple_gap
);
5353 vmx
->ple_window
= ple_window
;
5354 vmx
->ple_window_dirty
= true;
5357 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5358 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5359 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5361 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5362 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5363 vmx_set_constant_host_state(vmx
);
5364 #ifdef CONFIG_X86_64
5365 rdmsrl(MSR_FS_BASE
, a
);
5366 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5367 rdmsrl(MSR_GS_BASE
, a
);
5368 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5370 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5371 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5374 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5375 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5376 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5377 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5378 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5380 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5381 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5383 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5384 u32 index
= vmx_msr_index
[i
];
5385 u32 data_low
, data_high
;
5388 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5390 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5392 vmx
->guest_msrs
[j
].index
= i
;
5393 vmx
->guest_msrs
[j
].data
= 0;
5394 vmx
->guest_msrs
[j
].mask
= -1ull;
5399 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5401 /* 22.2.1, 20.8.1 */
5402 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5404 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5405 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5407 set_cr4_guest_host_mask(vmx
);
5409 if (vmx_xsaves_supported())
5410 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5413 ASSERT(vmx
->pml_pg
);
5414 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5415 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5421 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5424 struct msr_data apic_base_msr
;
5427 vmx
->rmode
.vm86_active
= 0;
5429 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5430 kvm_set_cr8(vcpu
, 0);
5433 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5434 MSR_IA32_APICBASE_ENABLE
;
5435 if (kvm_vcpu_is_reset_bsp(vcpu
))
5436 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5437 apic_base_msr
.host_initiated
= true;
5438 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5441 vmx_segment_cache_clear(vmx
);
5443 seg_setup(VCPU_SREG_CS
);
5444 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5445 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5447 seg_setup(VCPU_SREG_DS
);
5448 seg_setup(VCPU_SREG_ES
);
5449 seg_setup(VCPU_SREG_FS
);
5450 seg_setup(VCPU_SREG_GS
);
5451 seg_setup(VCPU_SREG_SS
);
5453 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5454 vmcs_writel(GUEST_TR_BASE
, 0);
5455 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5456 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5458 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5459 vmcs_writel(GUEST_LDTR_BASE
, 0);
5460 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5461 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5464 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5465 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5466 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5467 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5470 vmcs_writel(GUEST_RFLAGS
, 0x02);
5471 kvm_rip_write(vcpu
, 0xfff0);
5473 vmcs_writel(GUEST_GDTR_BASE
, 0);
5474 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5476 vmcs_writel(GUEST_IDTR_BASE
, 0);
5477 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5479 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5480 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5481 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5487 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5488 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5489 if (cpu_need_tpr_shadow(vcpu
))
5490 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5491 __pa(vcpu
->arch
.apic
->regs
));
5492 vmcs_write32(TPR_THRESHOLD
, 0);
5495 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5497 if (kvm_vcpu_apicv_active(vcpu
))
5498 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5501 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5503 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5504 vmx
->vcpu
.arch
.cr0
= cr0
;
5505 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5506 vmx_set_cr4(vcpu
, 0);
5507 vmx_set_efer(vcpu
, 0);
5509 update_exception_bitmap(vcpu
);
5511 vpid_sync_context(vmx
->vpid
);
5515 * In nested virtualization, check if L1 asked to exit on external interrupts.
5516 * For most existing hypervisors, this will always return true.
5518 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5520 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5521 PIN_BASED_EXT_INTR_MASK
;
5525 * In nested virtualization, check if L1 has set
5526 * VM_EXIT_ACK_INTR_ON_EXIT
5528 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5530 return get_vmcs12(vcpu
)->vm_exit_controls
&
5531 VM_EXIT_ACK_INTR_ON_EXIT
;
5534 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5536 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5537 PIN_BASED_NMI_EXITING
;
5540 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5542 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5543 CPU_BASED_VIRTUAL_INTR_PENDING
);
5546 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5548 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5549 enable_irq_window(vcpu
);
5553 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5554 CPU_BASED_VIRTUAL_NMI_PENDING
);
5557 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5559 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5561 int irq
= vcpu
->arch
.interrupt
.nr
;
5563 trace_kvm_inj_virq(irq
);
5565 ++vcpu
->stat
.irq_injections
;
5566 if (vmx
->rmode
.vm86_active
) {
5568 if (vcpu
->arch
.interrupt
.soft
)
5569 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5570 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5571 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5574 intr
= irq
| INTR_INFO_VALID_MASK
;
5575 if (vcpu
->arch
.interrupt
.soft
) {
5576 intr
|= INTR_TYPE_SOFT_INTR
;
5577 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5578 vmx
->vcpu
.arch
.event_exit_inst_len
);
5580 intr
|= INTR_TYPE_EXT_INTR
;
5581 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5584 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5586 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5588 ++vcpu
->stat
.nmi_injections
;
5589 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5591 if (vmx
->rmode
.vm86_active
) {
5592 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5593 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5597 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5598 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5601 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5603 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5606 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5608 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5609 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5613 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5615 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5617 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5619 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5620 GUEST_INTR_STATE_NMI
);
5622 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5623 GUEST_INTR_STATE_NMI
);
5626 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5628 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5631 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5632 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5633 | GUEST_INTR_STATE_NMI
));
5636 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5638 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5639 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5640 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5641 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5644 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5648 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5652 kvm
->arch
.tss_addr
= addr
;
5653 return init_rmode_tss(kvm
);
5656 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5661 * Update instruction length as we may reinject the exception
5662 * from user space while in guest debugging mode.
5664 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5665 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5666 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5670 if (vcpu
->guest_debug
&
5671 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5688 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5689 int vec
, u32 err_code
)
5692 * Instruction with address size override prefix opcode 0x67
5693 * Cause the #SS fault with 0 error code in VM86 mode.
5695 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5696 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5697 if (vcpu
->arch
.halt_request
) {
5698 vcpu
->arch
.halt_request
= 0;
5699 return kvm_vcpu_halt(vcpu
);
5707 * Forward all other exceptions that are valid in real mode.
5708 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5709 * the required debugging infrastructure rework.
5711 kvm_queue_exception(vcpu
, vec
);
5716 * Trigger machine check on the host. We assume all the MSRs are already set up
5717 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5718 * We pass a fake environment to the machine check handler because we want
5719 * the guest to be always treated like user space, no matter what context
5720 * it used internally.
5722 static void kvm_machine_check(void)
5724 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5725 struct pt_regs regs
= {
5726 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5727 .flags
= X86_EFLAGS_IF
,
5730 do_machine_check(®s
, 0);
5734 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5736 /* already handled by vcpu_run */
5740 static int handle_exception(struct kvm_vcpu
*vcpu
)
5742 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5743 struct kvm_run
*kvm_run
= vcpu
->run
;
5744 u32 intr_info
, ex_no
, error_code
;
5745 unsigned long cr2
, rip
, dr6
;
5747 enum emulation_result er
;
5749 vect_info
= vmx
->idt_vectoring_info
;
5750 intr_info
= vmx
->exit_intr_info
;
5752 if (is_machine_check(intr_info
))
5753 return handle_machine_check(vcpu
);
5755 if (is_nmi(intr_info
))
5756 return 1; /* already handled by vmx_vcpu_run() */
5758 if (is_invalid_opcode(intr_info
)) {
5759 if (is_guest_mode(vcpu
)) {
5760 kvm_queue_exception(vcpu
, UD_VECTOR
);
5763 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5764 if (er
!= EMULATE_DONE
)
5765 kvm_queue_exception(vcpu
, UD_VECTOR
);
5770 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5771 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5774 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5775 * MMIO, it is better to report an internal error.
5776 * See the comments in vmx_handle_exit.
5778 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5779 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5780 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5781 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5782 vcpu
->run
->internal
.ndata
= 3;
5783 vcpu
->run
->internal
.data
[0] = vect_info
;
5784 vcpu
->run
->internal
.data
[1] = intr_info
;
5785 vcpu
->run
->internal
.data
[2] = error_code
;
5789 if (is_page_fault(intr_info
)) {
5790 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5791 /* EPT won't cause page fault directly */
5792 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5793 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5797 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5799 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5800 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5804 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5807 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5808 if (!(vcpu
->guest_debug
&
5809 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5810 vcpu
->arch
.dr6
&= ~15;
5811 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5812 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5813 skip_emulated_instruction(vcpu
);
5815 kvm_queue_exception(vcpu
, DB_VECTOR
);
5818 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5819 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5823 * Update instruction length as we may reinject #BP from
5824 * user space while in guest debugging mode. Reading it for
5825 * #DB as well causes no harm, it is not used in that case.
5827 vmx
->vcpu
.arch
.event_exit_inst_len
=
5828 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5829 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5830 rip
= kvm_rip_read(vcpu
);
5831 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5832 kvm_run
->debug
.arch
.exception
= ex_no
;
5835 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5836 kvm_run
->ex
.exception
= ex_no
;
5837 kvm_run
->ex
.error_code
= error_code
;
5843 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5845 ++vcpu
->stat
.irq_exits
;
5849 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5851 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5855 static int handle_io(struct kvm_vcpu
*vcpu
)
5857 unsigned long exit_qualification
;
5858 int size
, in
, string
, ret
;
5861 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5862 string
= (exit_qualification
& 16) != 0;
5863 in
= (exit_qualification
& 8) != 0;
5865 ++vcpu
->stat
.io_exits
;
5868 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5870 port
= exit_qualification
>> 16;
5871 size
= (exit_qualification
& 7) + 1;
5873 ret
= kvm_skip_emulated_instruction(vcpu
);
5876 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5877 * KVM_EXIT_DEBUG here.
5879 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5883 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5886 * Patch in the VMCALL instruction:
5888 hypercall
[0] = 0x0f;
5889 hypercall
[1] = 0x01;
5890 hypercall
[2] = 0xc1;
5893 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5894 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5896 if (is_guest_mode(vcpu
)) {
5897 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5898 unsigned long orig_val
= val
;
5901 * We get here when L2 changed cr0 in a way that did not change
5902 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5903 * but did change L0 shadowed bits. So we first calculate the
5904 * effective cr0 value that L1 would like to write into the
5905 * hardware. It consists of the L2-owned bits from the new
5906 * value combined with the L1-owned bits from L1's guest_cr0.
5908 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5909 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5911 if (!nested_guest_cr0_valid(vcpu
, val
))
5914 if (kvm_set_cr0(vcpu
, val
))
5916 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5919 if (to_vmx(vcpu
)->nested
.vmxon
&&
5920 !nested_host_cr0_valid(vcpu
, val
))
5923 return kvm_set_cr0(vcpu
, val
);
5927 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5929 if (is_guest_mode(vcpu
)) {
5930 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5931 unsigned long orig_val
= val
;
5933 /* analogously to handle_set_cr0 */
5934 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5935 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5936 if (kvm_set_cr4(vcpu
, val
))
5938 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5941 return kvm_set_cr4(vcpu
, val
);
5944 static int handle_cr(struct kvm_vcpu
*vcpu
)
5946 unsigned long exit_qualification
, val
;
5952 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5953 cr
= exit_qualification
& 15;
5954 reg
= (exit_qualification
>> 8) & 15;
5955 switch ((exit_qualification
>> 4) & 3) {
5956 case 0: /* mov to cr */
5957 val
= kvm_register_readl(vcpu
, reg
);
5958 trace_kvm_cr_write(cr
, val
);
5961 err
= handle_set_cr0(vcpu
, val
);
5962 return kvm_complete_insn_gp(vcpu
, err
);
5964 err
= kvm_set_cr3(vcpu
, val
);
5965 return kvm_complete_insn_gp(vcpu
, err
);
5967 err
= handle_set_cr4(vcpu
, val
);
5968 return kvm_complete_insn_gp(vcpu
, err
);
5970 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5972 err
= kvm_set_cr8(vcpu
, cr8
);
5973 ret
= kvm_complete_insn_gp(vcpu
, err
);
5974 if (lapic_in_kernel(vcpu
))
5976 if (cr8_prev
<= cr8
)
5979 * TODO: we might be squashing a
5980 * KVM_GUESTDBG_SINGLESTEP-triggered
5981 * KVM_EXIT_DEBUG here.
5983 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5989 WARN_ONCE(1, "Guest should always own CR0.TS");
5990 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5991 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5992 return kvm_skip_emulated_instruction(vcpu
);
5993 case 1: /*mov from cr*/
5996 val
= kvm_read_cr3(vcpu
);
5997 kvm_register_write(vcpu
, reg
, val
);
5998 trace_kvm_cr_read(cr
, val
);
5999 return kvm_skip_emulated_instruction(vcpu
);
6001 val
= kvm_get_cr8(vcpu
);
6002 kvm_register_write(vcpu
, reg
, val
);
6003 trace_kvm_cr_read(cr
, val
);
6004 return kvm_skip_emulated_instruction(vcpu
);
6008 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6009 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6010 kvm_lmsw(vcpu
, val
);
6012 return kvm_skip_emulated_instruction(vcpu
);
6016 vcpu
->run
->exit_reason
= 0;
6017 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6018 (int)(exit_qualification
>> 4) & 3, cr
);
6022 static int handle_dr(struct kvm_vcpu
*vcpu
)
6024 unsigned long exit_qualification
;
6027 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6028 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6030 /* First, if DR does not exist, trigger UD */
6031 if (!kvm_require_dr(vcpu
, dr
))
6034 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6035 if (!kvm_require_cpl(vcpu
, 0))
6037 dr7
= vmcs_readl(GUEST_DR7
);
6040 * As the vm-exit takes precedence over the debug trap, we
6041 * need to emulate the latter, either for the host or the
6042 * guest debugging itself.
6044 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6045 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6046 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6047 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6048 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6049 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6052 vcpu
->arch
.dr6
&= ~15;
6053 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6054 kvm_queue_exception(vcpu
, DB_VECTOR
);
6059 if (vcpu
->guest_debug
== 0) {
6060 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6061 CPU_BASED_MOV_DR_EXITING
);
6064 * No more DR vmexits; force a reload of the debug registers
6065 * and reenter on this instruction. The next vmexit will
6066 * retrieve the full state of the debug registers.
6068 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6072 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6073 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6076 if (kvm_get_dr(vcpu
, dr
, &val
))
6078 kvm_register_write(vcpu
, reg
, val
);
6080 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6083 return kvm_skip_emulated_instruction(vcpu
);
6086 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6088 return vcpu
->arch
.dr6
;
6091 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6095 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6097 get_debugreg(vcpu
->arch
.db
[0], 0);
6098 get_debugreg(vcpu
->arch
.db
[1], 1);
6099 get_debugreg(vcpu
->arch
.db
[2], 2);
6100 get_debugreg(vcpu
->arch
.db
[3], 3);
6101 get_debugreg(vcpu
->arch
.dr6
, 6);
6102 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6104 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6105 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6108 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6110 vmcs_writel(GUEST_DR7
, val
);
6113 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6115 return kvm_emulate_cpuid(vcpu
);
6118 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6120 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6121 struct msr_data msr_info
;
6123 msr_info
.index
= ecx
;
6124 msr_info
.host_initiated
= false;
6126 if (vmx_get_msr(vcpu
, &msr_info
)) {
6127 trace_kvm_msr_read_ex(ecx
);
6128 kvm_inject_gp(vcpu
, 0);
6132 trace_kvm_msr_read(ecx
, msr_info
.data
);
6134 /* FIXME: handling of bits 32:63 of rax, rdx */
6135 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6136 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6137 return kvm_skip_emulated_instruction(vcpu
);
6140 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6142 struct msr_data msr
;
6143 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6144 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6145 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6149 msr
.host_initiated
= false;
6150 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6151 trace_kvm_msr_write_ex(ecx
, data
);
6152 kvm_inject_gp(vcpu
, 0);
6156 trace_kvm_msr_write(ecx
, data
);
6157 return kvm_skip_emulated_instruction(vcpu
);
6160 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6162 kvm_apic_update_ppr(vcpu
);
6166 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6168 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6169 CPU_BASED_VIRTUAL_INTR_PENDING
);
6171 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6173 ++vcpu
->stat
.irq_window_exits
;
6177 static int handle_halt(struct kvm_vcpu
*vcpu
)
6179 return kvm_emulate_halt(vcpu
);
6182 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6184 return kvm_emulate_hypercall(vcpu
);
6187 static int handle_invd(struct kvm_vcpu
*vcpu
)
6189 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6192 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6194 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6196 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6197 return kvm_skip_emulated_instruction(vcpu
);
6200 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6204 err
= kvm_rdpmc(vcpu
);
6205 return kvm_complete_insn_gp(vcpu
, err
);
6208 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6210 return kvm_emulate_wbinvd(vcpu
);
6213 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6215 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6216 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6218 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6219 return kvm_skip_emulated_instruction(vcpu
);
6223 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6225 kvm_skip_emulated_instruction(vcpu
);
6226 WARN(1, "this should never happen\n");
6230 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6232 kvm_skip_emulated_instruction(vcpu
);
6233 WARN(1, "this should never happen\n");
6237 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6239 if (likely(fasteoi
)) {
6240 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6241 int access_type
, offset
;
6243 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6244 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6246 * Sane guest uses MOV to write EOI, with written value
6247 * not cared. So make a short-circuit here by avoiding
6248 * heavy instruction emulation.
6250 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6251 (offset
== APIC_EOI
)) {
6252 kvm_lapic_set_eoi(vcpu
);
6253 return kvm_skip_emulated_instruction(vcpu
);
6256 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6259 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6261 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6262 int vector
= exit_qualification
& 0xff;
6264 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6265 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6269 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6271 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6272 u32 offset
= exit_qualification
& 0xfff;
6274 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6275 kvm_apic_write_nodecode(vcpu
, offset
);
6279 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6281 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6282 unsigned long exit_qualification
;
6283 bool has_error_code
= false;
6286 int reason
, type
, idt_v
, idt_index
;
6288 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6289 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6290 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6292 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6294 reason
= (u32
)exit_qualification
>> 30;
6295 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6297 case INTR_TYPE_NMI_INTR
:
6298 vcpu
->arch
.nmi_injected
= false;
6299 vmx_set_nmi_mask(vcpu
, true);
6301 case INTR_TYPE_EXT_INTR
:
6302 case INTR_TYPE_SOFT_INTR
:
6303 kvm_clear_interrupt_queue(vcpu
);
6305 case INTR_TYPE_HARD_EXCEPTION
:
6306 if (vmx
->idt_vectoring_info
&
6307 VECTORING_INFO_DELIVER_CODE_MASK
) {
6308 has_error_code
= true;
6310 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6313 case INTR_TYPE_SOFT_EXCEPTION
:
6314 kvm_clear_exception_queue(vcpu
);
6320 tss_selector
= exit_qualification
;
6322 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6323 type
!= INTR_TYPE_EXT_INTR
&&
6324 type
!= INTR_TYPE_NMI_INTR
))
6325 skip_emulated_instruction(vcpu
);
6327 if (kvm_task_switch(vcpu
, tss_selector
,
6328 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6329 has_error_code
, error_code
) == EMULATE_FAIL
) {
6330 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6331 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6332 vcpu
->run
->internal
.ndata
= 0;
6337 * TODO: What about debug traps on tss switch?
6338 * Are we supposed to inject them and update dr6?
6344 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6346 unsigned long exit_qualification
;
6350 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6353 * EPT violation happened while executing iret from NMI,
6354 * "blocked by NMI" bit has to be set before next VM entry.
6355 * There are errata that may cause this bit to not be set:
6358 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6359 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6360 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6362 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6363 trace_kvm_page_fault(gpa
, exit_qualification
);
6365 /* Is it a read fault? */
6366 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6367 ? PFERR_USER_MASK
: 0;
6368 /* Is it a write fault? */
6369 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6370 ? PFERR_WRITE_MASK
: 0;
6371 /* Is it a fetch fault? */
6372 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6373 ? PFERR_FETCH_MASK
: 0;
6374 /* ept page table entry is present? */
6375 error_code
|= (exit_qualification
&
6376 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6377 EPT_VIOLATION_EXECUTABLE
))
6378 ? PFERR_PRESENT_MASK
: 0;
6380 vcpu
->arch
.gpa_available
= true;
6381 vcpu
->arch
.exit_qualification
= exit_qualification
;
6383 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6386 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6391 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6392 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6393 trace_kvm_fast_mmio(gpa
);
6394 return kvm_skip_emulated_instruction(vcpu
);
6397 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6398 vcpu
->arch
.gpa_available
= true;
6399 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6400 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6403 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6404 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6406 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6409 /* It is the real ept misconfig */
6412 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6413 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6418 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6420 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6421 CPU_BASED_VIRTUAL_NMI_PENDING
);
6422 ++vcpu
->stat
.nmi_window_exits
;
6423 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6428 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6430 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6431 enum emulation_result err
= EMULATE_DONE
;
6434 bool intr_window_requested
;
6435 unsigned count
= 130;
6437 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6438 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6440 while (vmx
->emulation_required
&& count
-- != 0) {
6441 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6442 return handle_interrupt_window(&vmx
->vcpu
);
6444 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6447 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6449 if (err
== EMULATE_USER_EXIT
) {
6450 ++vcpu
->stat
.mmio_exits
;
6455 if (err
!= EMULATE_DONE
) {
6456 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6457 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6458 vcpu
->run
->internal
.ndata
= 0;
6462 if (vcpu
->arch
.halt_request
) {
6463 vcpu
->arch
.halt_request
= 0;
6464 ret
= kvm_vcpu_halt(vcpu
);
6468 if (signal_pending(current
))
6478 static int __grow_ple_window(int val
)
6480 if (ple_window_grow
< 1)
6483 val
= min(val
, ple_window_actual_max
);
6485 if (ple_window_grow
< ple_window
)
6486 val
*= ple_window_grow
;
6488 val
+= ple_window_grow
;
6493 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6498 if (modifier
< ple_window
)
6503 return max(val
, minimum
);
6506 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6508 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6509 int old
= vmx
->ple_window
;
6511 vmx
->ple_window
= __grow_ple_window(old
);
6513 if (vmx
->ple_window
!= old
)
6514 vmx
->ple_window_dirty
= true;
6516 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6519 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6521 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6522 int old
= vmx
->ple_window
;
6524 vmx
->ple_window
= __shrink_ple_window(old
,
6525 ple_window_shrink
, ple_window
);
6527 if (vmx
->ple_window
!= old
)
6528 vmx
->ple_window_dirty
= true;
6530 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6534 * ple_window_actual_max is computed to be one grow_ple_window() below
6535 * ple_window_max. (See __grow_ple_window for the reason.)
6536 * This prevents overflows, because ple_window_max is int.
6537 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6539 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6541 static void update_ple_window_actual_max(void)
6543 ple_window_actual_max
=
6544 __shrink_ple_window(max(ple_window_max
, ple_window
),
6545 ple_window_grow
, INT_MIN
);
6549 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6551 static void wakeup_handler(void)
6553 struct kvm_vcpu
*vcpu
;
6554 int cpu
= smp_processor_id();
6556 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6557 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6558 blocked_vcpu_list
) {
6559 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6561 if (pi_test_on(pi_desc
) == 1)
6562 kvm_vcpu_kick(vcpu
);
6564 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6567 void vmx_enable_tdp(void)
6569 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6570 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6571 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6572 0ull, VMX_EPT_EXECUTABLE_MASK
,
6573 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6576 ept_set_mmio_spte_mask();
6580 static __init
int hardware_setup(void)
6582 int r
= -ENOMEM
, i
, msr
;
6584 rdmsrl_safe(MSR_EFER
, &host_efer
);
6586 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6587 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6589 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6590 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6595 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6596 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6597 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6600 * Allow direct access to the PC debug port (it is often used for I/O
6601 * delays, but the vmexits simply slow things down).
6603 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6604 clear_bit(0x80, vmx_io_bitmap_a
);
6606 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6608 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6609 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6611 if (setup_vmcs_config(&vmcs_config
) < 0) {
6616 if (boot_cpu_has(X86_FEATURE_NX
))
6617 kvm_enable_efer_bits(EFER_NX
);
6619 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6620 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6623 if (!cpu_has_vmx_shadow_vmcs())
6624 enable_shadow_vmcs
= 0;
6625 if (enable_shadow_vmcs
)
6626 init_vmcs_shadow_fields();
6628 if (!cpu_has_vmx_ept() ||
6629 !cpu_has_vmx_ept_4levels()) {
6631 enable_unrestricted_guest
= 0;
6632 enable_ept_ad_bits
= 0;
6635 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6636 enable_ept_ad_bits
= 0;
6638 if (!cpu_has_vmx_unrestricted_guest())
6639 enable_unrestricted_guest
= 0;
6641 if (!cpu_has_vmx_flexpriority())
6642 flexpriority_enabled
= 0;
6645 * set_apic_access_page_addr() is used to reload apic access
6646 * page upon invalidation. No need to do anything if not
6647 * using the APIC_ACCESS_ADDR VMCS field.
6649 if (!flexpriority_enabled
)
6650 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6652 if (!cpu_has_vmx_tpr_shadow())
6653 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6655 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6656 kvm_disable_largepages();
6658 if (!cpu_has_vmx_ple())
6661 if (!cpu_has_vmx_apicv()) {
6663 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6666 if (cpu_has_vmx_tsc_scaling()) {
6667 kvm_has_tsc_control
= true;
6668 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6669 kvm_tsc_scaling_ratio_frac_bits
= 48;
6672 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6673 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6674 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6675 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6676 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6677 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6678 vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL
, false);
6679 vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD
, false);
6681 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6682 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6683 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6684 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6685 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6686 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6687 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6688 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6690 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6692 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6693 if (msr
== 0x839 /* TMCCT */)
6695 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6699 * TPR reads and writes can be virtualized even if virtual interrupt
6700 * delivery is not in use.
6702 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6703 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6706 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6708 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6715 update_ple_window_actual_max();
6718 * Only enable PML when hardware supports PML feature, and both EPT
6719 * and EPT A/D bit features are enabled -- PML depends on them to work.
6721 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6725 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6726 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6727 kvm_x86_ops
->flush_log_dirty
= NULL
;
6728 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6731 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6734 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6735 cpu_preemption_timer_multi
=
6736 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6738 kvm_x86_ops
->set_hv_timer
= NULL
;
6739 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6742 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6744 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6746 return alloc_kvm_area();
6749 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6750 free_page((unsigned long)vmx_bitmap
[i
]);
6755 static __exit
void hardware_unsetup(void)
6759 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6760 free_page((unsigned long)vmx_bitmap
[i
]);
6766 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6767 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6769 static int handle_pause(struct kvm_vcpu
*vcpu
)
6772 grow_ple_window(vcpu
);
6774 kvm_vcpu_on_spin(vcpu
);
6775 return kvm_skip_emulated_instruction(vcpu
);
6778 static int handle_nop(struct kvm_vcpu
*vcpu
)
6780 return kvm_skip_emulated_instruction(vcpu
);
6783 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6785 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6786 return handle_nop(vcpu
);
6789 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6794 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6796 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6797 return handle_nop(vcpu
);
6801 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6802 * We could reuse a single VMCS for all the L2 guests, but we also want the
6803 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6804 * allows keeping them loaded on the processor, and in the future will allow
6805 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6806 * every entry if they never change.
6807 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6808 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6810 * The following functions allocate and free a vmcs02 in this pool.
6813 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6814 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6816 struct vmcs02_list
*item
;
6817 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6818 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6819 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6820 return &item
->vmcs02
;
6823 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6824 /* Recycle the least recently used VMCS. */
6825 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6826 struct vmcs02_list
, list
);
6827 item
->vmptr
= vmx
->nested
.current_vmptr
;
6828 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6829 return &item
->vmcs02
;
6832 /* Create a new VMCS */
6833 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6836 item
->vmcs02
.vmcs
= alloc_vmcs();
6837 item
->vmcs02
.shadow_vmcs
= NULL
;
6838 if (!item
->vmcs02
.vmcs
) {
6842 loaded_vmcs_init(&item
->vmcs02
);
6843 item
->vmptr
= vmx
->nested
.current_vmptr
;
6844 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6845 vmx
->nested
.vmcs02_num
++;
6846 return &item
->vmcs02
;
6849 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6850 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6852 struct vmcs02_list
*item
;
6853 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6854 if (item
->vmptr
== vmptr
) {
6855 free_loaded_vmcs(&item
->vmcs02
);
6856 list_del(&item
->list
);
6858 vmx
->nested
.vmcs02_num
--;
6864 * Free all VMCSs saved for this vcpu, except the one pointed by
6865 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6866 * must be &vmx->vmcs01.
6868 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6870 struct vmcs02_list
*item
, *n
;
6872 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6873 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6875 * Something will leak if the above WARN triggers. Better than
6878 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6881 free_loaded_vmcs(&item
->vmcs02
);
6882 list_del(&item
->list
);
6884 vmx
->nested
.vmcs02_num
--;
6889 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6890 * set the success or error code of an emulated VMX instruction, as specified
6891 * by Vol 2B, VMX Instruction Reference, "Conventions".
6893 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6895 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6896 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6897 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6900 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6902 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6903 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6904 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6908 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6909 u32 vm_instruction_error
)
6911 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6913 * failValid writes the error number to the current VMCS, which
6914 * can't be done there isn't a current VMCS.
6916 nested_vmx_failInvalid(vcpu
);
6919 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6920 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6921 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6923 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6925 * We don't need to force a shadow sync because
6926 * VM_INSTRUCTION_ERROR is not shadowed
6930 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6932 /* TODO: not to reset guest simply here. */
6933 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6934 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6937 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6939 struct vcpu_vmx
*vmx
=
6940 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6942 vmx
->nested
.preemption_timer_expired
= true;
6943 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6944 kvm_vcpu_kick(&vmx
->vcpu
);
6946 return HRTIMER_NORESTART
;
6950 * Decode the memory-address operand of a vmx instruction, as recorded on an
6951 * exit caused by such an instruction (run by a guest hypervisor).
6952 * On success, returns 0. When the operand is invalid, returns 1 and throws
6955 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6956 unsigned long exit_qualification
,
6957 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6961 struct kvm_segment s
;
6964 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6965 * Execution", on an exit, vmx_instruction_info holds most of the
6966 * addressing components of the operand. Only the displacement part
6967 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6968 * For how an actual address is calculated from all these components,
6969 * refer to Vol. 1, "Operand Addressing".
6971 int scaling
= vmx_instruction_info
& 3;
6972 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6973 bool is_reg
= vmx_instruction_info
& (1u << 10);
6974 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6975 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6976 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6977 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6978 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6981 kvm_queue_exception(vcpu
, UD_VECTOR
);
6985 /* Addr = segment_base + offset */
6986 /* offset = base + [index * scale] + displacement */
6987 off
= exit_qualification
; /* holds the displacement */
6989 off
+= kvm_register_read(vcpu
, base_reg
);
6991 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6992 vmx_get_segment(vcpu
, &s
, seg_reg
);
6993 *ret
= s
.base
+ off
;
6995 if (addr_size
== 1) /* 32 bit */
6998 /* Checks for #GP/#SS exceptions. */
7000 if (is_long_mode(vcpu
)) {
7001 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7002 * non-canonical form. This is the only check on the memory
7003 * destination for long mode!
7005 exn
= is_noncanonical_address(*ret
);
7006 } else if (is_protmode(vcpu
)) {
7007 /* Protected mode: apply checks for segment validity in the
7009 * - segment type check (#GP(0) may be thrown)
7010 * - usability check (#GP(0)/#SS(0))
7011 * - limit check (#GP(0)/#SS(0))
7014 /* #GP(0) if the destination operand is located in a
7015 * read-only data segment or any code segment.
7017 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7019 /* #GP(0) if the source operand is located in an
7020 * execute-only code segment
7022 exn
= ((s
.type
& 0xa) == 8);
7024 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7027 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7029 exn
= (s
.unusable
!= 0);
7030 /* Protected mode: #GP(0)/#SS(0) if the memory
7031 * operand is outside the segment limit.
7033 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7036 kvm_queue_exception_e(vcpu
,
7037 seg_reg
== VCPU_SREG_SS
?
7038 SS_VECTOR
: GP_VECTOR
,
7046 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7049 struct x86_exception e
;
7051 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7052 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7055 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7056 sizeof(*vmpointer
), &e
)) {
7057 kvm_inject_page_fault(vcpu
, &e
);
7064 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7066 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7067 struct vmcs
*shadow_vmcs
;
7069 if (cpu_has_vmx_msr_bitmap()) {
7070 vmx
->nested
.msr_bitmap
=
7071 (unsigned long *)__get_free_page(GFP_KERNEL
);
7072 if (!vmx
->nested
.msr_bitmap
)
7073 goto out_msr_bitmap
;
7076 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7077 if (!vmx
->nested
.cached_vmcs12
)
7078 goto out_cached_vmcs12
;
7080 if (enable_shadow_vmcs
) {
7081 shadow_vmcs
= alloc_vmcs();
7083 goto out_shadow_vmcs
;
7084 /* mark vmcs as shadow */
7085 shadow_vmcs
->revision_id
|= (1u << 31);
7086 /* init shadow vmcs */
7087 vmcs_clear(shadow_vmcs
);
7088 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7091 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7092 vmx
->nested
.vmcs02_num
= 0;
7094 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7095 HRTIMER_MODE_REL_PINNED
);
7096 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7098 vmx
->nested
.vmxon
= true;
7102 kfree(vmx
->nested
.cached_vmcs12
);
7105 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7112 * Emulate the VMXON instruction.
7113 * Currently, we just remember that VMX is active, and do not save or even
7114 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7115 * do not currently need to store anything in that guest-allocated memory
7116 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7117 * argument is different from the VMXON pointer (which the spec says they do).
7119 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7124 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7125 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7126 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7129 * The Intel VMX Instruction Reference lists a bunch of bits that are
7130 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7131 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7132 * Otherwise, we should fail with #UD. But most faulting conditions
7133 * have already been checked by hardware, prior to the VM-exit for
7134 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7135 * that bit set to 1 in non-root mode.
7137 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7138 kvm_queue_exception(vcpu
, UD_VECTOR
);
7142 if (vmx
->nested
.vmxon
) {
7143 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7144 return kvm_skip_emulated_instruction(vcpu
);
7147 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7148 != VMXON_NEEDED_FEATURES
) {
7149 kvm_inject_gp(vcpu
, 0);
7153 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7158 * The first 4 bytes of VMXON region contain the supported
7159 * VMCS revision identifier
7161 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7162 * which replaces physical address width with 32
7164 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7165 nested_vmx_failInvalid(vcpu
);
7166 return kvm_skip_emulated_instruction(vcpu
);
7169 page
= nested_get_page(vcpu
, vmptr
);
7171 nested_vmx_failInvalid(vcpu
);
7172 return kvm_skip_emulated_instruction(vcpu
);
7174 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7176 nested_release_page_clean(page
);
7177 nested_vmx_failInvalid(vcpu
);
7178 return kvm_skip_emulated_instruction(vcpu
);
7181 nested_release_page_clean(page
);
7183 vmx
->nested
.vmxon_ptr
= vmptr
;
7184 ret
= enter_vmx_operation(vcpu
);
7188 nested_vmx_succeed(vcpu
);
7189 return kvm_skip_emulated_instruction(vcpu
);
7193 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7194 * for running VMX instructions (except VMXON, whose prerequisites are
7195 * slightly different). It also specifies what exception to inject otherwise.
7196 * Note that many of these exceptions have priority over VM exits, so they
7197 * don't have to be checked again here.
7199 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7201 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7202 kvm_queue_exception(vcpu
, UD_VECTOR
);
7208 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7210 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7211 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7214 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7216 if (vmx
->nested
.current_vmptr
== -1ull)
7219 if (enable_shadow_vmcs
) {
7220 /* copy to memory all shadowed fields in case
7221 they were modified */
7222 copy_shadow_to_vmcs12(vmx
);
7223 vmx
->nested
.sync_shadow_vmcs
= false;
7224 vmx_disable_shadow_vmcs(vmx
);
7226 vmx
->nested
.posted_intr_nv
= -1;
7228 /* Flush VMCS12 to guest memory */
7229 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7230 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7231 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7233 vmx
->nested
.current_vmptr
= -1ull;
7237 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7238 * just stops using VMX.
7240 static void free_nested(struct vcpu_vmx
*vmx
)
7242 if (!vmx
->nested
.vmxon
)
7245 vmx
->nested
.vmxon
= false;
7246 free_vpid(vmx
->nested
.vpid02
);
7247 vmx
->nested
.posted_intr_nv
= -1;
7248 vmx
->nested
.current_vmptr
= -1ull;
7249 if (vmx
->nested
.msr_bitmap
) {
7250 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7251 vmx
->nested
.msr_bitmap
= NULL
;
7253 if (enable_shadow_vmcs
) {
7254 vmx_disable_shadow_vmcs(vmx
);
7255 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7256 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7257 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7259 kfree(vmx
->nested
.cached_vmcs12
);
7260 /* Unpin physical memory we referred to in current vmcs02 */
7261 if (vmx
->nested
.apic_access_page
) {
7262 nested_release_page(vmx
->nested
.apic_access_page
);
7263 vmx
->nested
.apic_access_page
= NULL
;
7265 if (vmx
->nested
.virtual_apic_page
) {
7266 nested_release_page(vmx
->nested
.virtual_apic_page
);
7267 vmx
->nested
.virtual_apic_page
= NULL
;
7269 if (vmx
->nested
.pi_desc_page
) {
7270 kunmap(vmx
->nested
.pi_desc_page
);
7271 nested_release_page(vmx
->nested
.pi_desc_page
);
7272 vmx
->nested
.pi_desc_page
= NULL
;
7273 vmx
->nested
.pi_desc
= NULL
;
7276 nested_free_all_saved_vmcss(vmx
);
7279 /* Emulate the VMXOFF instruction */
7280 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7282 if (!nested_vmx_check_permission(vcpu
))
7284 free_nested(to_vmx(vcpu
));
7285 nested_vmx_succeed(vcpu
);
7286 return kvm_skip_emulated_instruction(vcpu
);
7289 /* Emulate the VMCLEAR instruction */
7290 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7292 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7296 if (!nested_vmx_check_permission(vcpu
))
7299 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7302 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7303 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7304 return kvm_skip_emulated_instruction(vcpu
);
7307 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7308 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7309 return kvm_skip_emulated_instruction(vcpu
);
7312 if (vmptr
== vmx
->nested
.current_vmptr
)
7313 nested_release_vmcs12(vmx
);
7315 kvm_vcpu_write_guest(vcpu
,
7316 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7317 &zero
, sizeof(zero
));
7319 nested_free_vmcs02(vmx
, vmptr
);
7321 nested_vmx_succeed(vcpu
);
7322 return kvm_skip_emulated_instruction(vcpu
);
7325 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7327 /* Emulate the VMLAUNCH instruction */
7328 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7330 return nested_vmx_run(vcpu
, true);
7333 /* Emulate the VMRESUME instruction */
7334 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7337 return nested_vmx_run(vcpu
, false);
7341 * Read a vmcs12 field. Since these can have varying lengths and we return
7342 * one type, we chose the biggest type (u64) and zero-extend the return value
7343 * to that size. Note that the caller, handle_vmread, might need to use only
7344 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7345 * 64-bit fields are to be returned).
7347 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7348 unsigned long field
, u64
*ret
)
7350 short offset
= vmcs_field_to_offset(field
);
7356 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7358 switch (vmcs_field_type(field
)) {
7359 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7360 *ret
= *((natural_width
*)p
);
7362 case VMCS_FIELD_TYPE_U16
:
7365 case VMCS_FIELD_TYPE_U32
:
7368 case VMCS_FIELD_TYPE_U64
:
7378 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7379 unsigned long field
, u64 field_value
){
7380 short offset
= vmcs_field_to_offset(field
);
7381 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7385 switch (vmcs_field_type(field
)) {
7386 case VMCS_FIELD_TYPE_U16
:
7387 *(u16
*)p
= field_value
;
7389 case VMCS_FIELD_TYPE_U32
:
7390 *(u32
*)p
= field_value
;
7392 case VMCS_FIELD_TYPE_U64
:
7393 *(u64
*)p
= field_value
;
7395 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7396 *(natural_width
*)p
= field_value
;
7405 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7408 unsigned long field
;
7410 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7411 const unsigned long *fields
= shadow_read_write_fields
;
7412 const int num_fields
= max_shadow_read_write_fields
;
7416 vmcs_load(shadow_vmcs
);
7418 for (i
= 0; i
< num_fields
; i
++) {
7420 switch (vmcs_field_type(field
)) {
7421 case VMCS_FIELD_TYPE_U16
:
7422 field_value
= vmcs_read16(field
);
7424 case VMCS_FIELD_TYPE_U32
:
7425 field_value
= vmcs_read32(field
);
7427 case VMCS_FIELD_TYPE_U64
:
7428 field_value
= vmcs_read64(field
);
7430 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7431 field_value
= vmcs_readl(field
);
7437 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7440 vmcs_clear(shadow_vmcs
);
7441 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7446 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7448 const unsigned long *fields
[] = {
7449 shadow_read_write_fields
,
7450 shadow_read_only_fields
7452 const int max_fields
[] = {
7453 max_shadow_read_write_fields
,
7454 max_shadow_read_only_fields
7457 unsigned long field
;
7458 u64 field_value
= 0;
7459 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7461 vmcs_load(shadow_vmcs
);
7463 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7464 for (i
= 0; i
< max_fields
[q
]; i
++) {
7465 field
= fields
[q
][i
];
7466 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7468 switch (vmcs_field_type(field
)) {
7469 case VMCS_FIELD_TYPE_U16
:
7470 vmcs_write16(field
, (u16
)field_value
);
7472 case VMCS_FIELD_TYPE_U32
:
7473 vmcs_write32(field
, (u32
)field_value
);
7475 case VMCS_FIELD_TYPE_U64
:
7476 vmcs_write64(field
, (u64
)field_value
);
7478 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7479 vmcs_writel(field
, (long)field_value
);
7488 vmcs_clear(shadow_vmcs
);
7489 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7493 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7494 * used before) all generate the same failure when it is missing.
7496 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7498 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7499 if (vmx
->nested
.current_vmptr
== -1ull) {
7500 nested_vmx_failInvalid(vcpu
);
7506 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7508 unsigned long field
;
7510 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7511 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7514 if (!nested_vmx_check_permission(vcpu
))
7517 if (!nested_vmx_check_vmcs12(vcpu
))
7518 return kvm_skip_emulated_instruction(vcpu
);
7520 /* Decode instruction info and find the field to read */
7521 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7522 /* Read the field, zero-extended to a u64 field_value */
7523 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7524 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7525 return kvm_skip_emulated_instruction(vcpu
);
7528 * Now copy part of this value to register or memory, as requested.
7529 * Note that the number of bits actually copied is 32 or 64 depending
7530 * on the guest's mode (32 or 64 bit), not on the given field's length.
7532 if (vmx_instruction_info
& (1u << 10)) {
7533 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7536 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7537 vmx_instruction_info
, true, &gva
))
7539 /* _system ok, as hardware has verified cpl=0 */
7540 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7541 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7544 nested_vmx_succeed(vcpu
);
7545 return kvm_skip_emulated_instruction(vcpu
);
7549 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7551 unsigned long field
;
7553 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7554 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7555 /* The value to write might be 32 or 64 bits, depending on L1's long
7556 * mode, and eventually we need to write that into a field of several
7557 * possible lengths. The code below first zero-extends the value to 64
7558 * bit (field_value), and then copies only the appropriate number of
7559 * bits into the vmcs12 field.
7561 u64 field_value
= 0;
7562 struct x86_exception e
;
7564 if (!nested_vmx_check_permission(vcpu
))
7567 if (!nested_vmx_check_vmcs12(vcpu
))
7568 return kvm_skip_emulated_instruction(vcpu
);
7570 if (vmx_instruction_info
& (1u << 10))
7571 field_value
= kvm_register_readl(vcpu
,
7572 (((vmx_instruction_info
) >> 3) & 0xf));
7574 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7575 vmx_instruction_info
, false, &gva
))
7577 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7578 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7579 kvm_inject_page_fault(vcpu
, &e
);
7585 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7586 if (vmcs_field_readonly(field
)) {
7587 nested_vmx_failValid(vcpu
,
7588 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7589 return kvm_skip_emulated_instruction(vcpu
);
7592 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7593 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7594 return kvm_skip_emulated_instruction(vcpu
);
7597 nested_vmx_succeed(vcpu
);
7598 return kvm_skip_emulated_instruction(vcpu
);
7601 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7603 vmx
->nested
.current_vmptr
= vmptr
;
7604 if (enable_shadow_vmcs
) {
7605 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7606 SECONDARY_EXEC_SHADOW_VMCS
);
7607 vmcs_write64(VMCS_LINK_POINTER
,
7608 __pa(vmx
->vmcs01
.shadow_vmcs
));
7609 vmx
->nested
.sync_shadow_vmcs
= true;
7613 /* Emulate the VMPTRLD instruction */
7614 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7616 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7619 if (!nested_vmx_check_permission(vcpu
))
7622 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7625 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7626 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7627 return kvm_skip_emulated_instruction(vcpu
);
7630 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7631 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7632 return kvm_skip_emulated_instruction(vcpu
);
7635 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7636 struct vmcs12
*new_vmcs12
;
7638 page
= nested_get_page(vcpu
, vmptr
);
7640 nested_vmx_failInvalid(vcpu
);
7641 return kvm_skip_emulated_instruction(vcpu
);
7643 new_vmcs12
= kmap(page
);
7644 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7646 nested_release_page_clean(page
);
7647 nested_vmx_failValid(vcpu
,
7648 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7649 return kvm_skip_emulated_instruction(vcpu
);
7652 nested_release_vmcs12(vmx
);
7654 * Load VMCS12 from guest memory since it is not already
7657 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7659 nested_release_page_clean(page
);
7661 set_current_vmptr(vmx
, vmptr
);
7664 nested_vmx_succeed(vcpu
);
7665 return kvm_skip_emulated_instruction(vcpu
);
7668 /* Emulate the VMPTRST instruction */
7669 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7671 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7672 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7674 struct x86_exception e
;
7676 if (!nested_vmx_check_permission(vcpu
))
7679 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7680 vmx_instruction_info
, true, &vmcs_gva
))
7682 /* ok to use *_system, as hardware has verified cpl=0 */
7683 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7684 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7686 kvm_inject_page_fault(vcpu
, &e
);
7689 nested_vmx_succeed(vcpu
);
7690 return kvm_skip_emulated_instruction(vcpu
);
7693 /* Emulate the INVEPT instruction */
7694 static int handle_invept(struct kvm_vcpu
*vcpu
)
7696 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7697 u32 vmx_instruction_info
, types
;
7700 struct x86_exception e
;
7705 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7706 SECONDARY_EXEC_ENABLE_EPT
) ||
7707 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7708 kvm_queue_exception(vcpu
, UD_VECTOR
);
7712 if (!nested_vmx_check_permission(vcpu
))
7715 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7716 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7718 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7720 if (type
>= 32 || !(types
& (1 << type
))) {
7721 nested_vmx_failValid(vcpu
,
7722 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7723 return kvm_skip_emulated_instruction(vcpu
);
7726 /* According to the Intel VMX instruction reference, the memory
7727 * operand is read even if it isn't needed (e.g., for type==global)
7729 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7730 vmx_instruction_info
, false, &gva
))
7732 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7733 sizeof(operand
), &e
)) {
7734 kvm_inject_page_fault(vcpu
, &e
);
7739 case VMX_EPT_EXTENT_GLOBAL
:
7741 * TODO: track mappings and invalidate
7742 * single context requests appropriately
7744 case VMX_EPT_EXTENT_CONTEXT
:
7745 kvm_mmu_sync_roots(vcpu
);
7746 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7747 nested_vmx_succeed(vcpu
);
7754 return kvm_skip_emulated_instruction(vcpu
);
7757 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7759 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7760 u32 vmx_instruction_info
;
7761 unsigned long type
, types
;
7763 struct x86_exception e
;
7769 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7770 SECONDARY_EXEC_ENABLE_VPID
) ||
7771 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7772 kvm_queue_exception(vcpu
, UD_VECTOR
);
7776 if (!nested_vmx_check_permission(vcpu
))
7779 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7780 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7782 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7783 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7785 if (type
>= 32 || !(types
& (1 << type
))) {
7786 nested_vmx_failValid(vcpu
,
7787 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7788 return kvm_skip_emulated_instruction(vcpu
);
7791 /* according to the intel vmx instruction reference, the memory
7792 * operand is read even if it isn't needed (e.g., for type==global)
7794 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7795 vmx_instruction_info
, false, &gva
))
7797 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7798 sizeof(operand
), &e
)) {
7799 kvm_inject_page_fault(vcpu
, &e
);
7802 if (operand
.vpid
>> 16) {
7803 nested_vmx_failValid(vcpu
,
7804 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7805 return kvm_skip_emulated_instruction(vcpu
);
7809 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7810 if (is_noncanonical_address(operand
.gla
)) {
7811 nested_vmx_failValid(vcpu
,
7812 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7813 return kvm_skip_emulated_instruction(vcpu
);
7816 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7817 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7818 if (!operand
.vpid
) {
7819 nested_vmx_failValid(vcpu
,
7820 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7821 return kvm_skip_emulated_instruction(vcpu
);
7824 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7828 return kvm_skip_emulated_instruction(vcpu
);
7831 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7832 nested_vmx_succeed(vcpu
);
7834 return kvm_skip_emulated_instruction(vcpu
);
7837 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7839 unsigned long exit_qualification
;
7841 trace_kvm_pml_full(vcpu
->vcpu_id
);
7843 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7846 * PML buffer FULL happened while executing iret from NMI,
7847 * "blocked by NMI" bit has to be set before next VM entry.
7849 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7850 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7851 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7852 GUEST_INTR_STATE_NMI
);
7855 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7856 * here.., and there's no userspace involvement needed for PML.
7861 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7863 kvm_lapic_expired_hv_timer(vcpu
);
7868 * The exit handlers return 1 if the exit was handled fully and guest execution
7869 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7870 * to be done to userspace and return 0.
7872 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7873 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7874 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7875 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7876 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7877 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7878 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7879 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7880 [EXIT_REASON_CPUID
] = handle_cpuid
,
7881 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7882 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7883 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7884 [EXIT_REASON_HLT
] = handle_halt
,
7885 [EXIT_REASON_INVD
] = handle_invd
,
7886 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7887 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7888 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7889 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7890 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7891 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7892 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7893 [EXIT_REASON_VMREAD
] = handle_vmread
,
7894 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7895 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7896 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7897 [EXIT_REASON_VMON
] = handle_vmon
,
7898 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7899 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7900 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7901 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7902 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7903 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7904 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7905 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7906 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7907 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7908 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7909 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7910 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7911 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7912 [EXIT_REASON_INVEPT
] = handle_invept
,
7913 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7914 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7915 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7916 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7917 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7920 static const int kvm_vmx_max_exit_handlers
=
7921 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7923 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7924 struct vmcs12
*vmcs12
)
7926 unsigned long exit_qualification
;
7927 gpa_t bitmap
, last_bitmap
;
7932 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7933 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7935 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7937 port
= exit_qualification
>> 16;
7938 size
= (exit_qualification
& 7) + 1;
7940 last_bitmap
= (gpa_t
)-1;
7945 bitmap
= vmcs12
->io_bitmap_a
;
7946 else if (port
< 0x10000)
7947 bitmap
= vmcs12
->io_bitmap_b
;
7950 bitmap
+= (port
& 0x7fff) / 8;
7952 if (last_bitmap
!= bitmap
)
7953 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7955 if (b
& (1 << (port
& 7)))
7960 last_bitmap
= bitmap
;
7967 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7968 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7969 * disinterest in the current event (read or write a specific MSR) by using an
7970 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7972 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7973 struct vmcs12
*vmcs12
, u32 exit_reason
)
7975 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7978 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7982 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7983 * for the four combinations of read/write and low/high MSR numbers.
7984 * First we need to figure out which of the four to use:
7986 bitmap
= vmcs12
->msr_bitmap
;
7987 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7989 if (msr_index
>= 0xc0000000) {
7990 msr_index
-= 0xc0000000;
7994 /* Then read the msr_index'th bit from this bitmap: */
7995 if (msr_index
< 1024*8) {
7997 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7999 return 1 & (b
>> (msr_index
& 7));
8001 return true; /* let L1 handle the wrong parameter */
8005 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8006 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8007 * intercept (via guest_host_mask etc.) the current event.
8009 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8010 struct vmcs12
*vmcs12
)
8012 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8013 int cr
= exit_qualification
& 15;
8017 switch ((exit_qualification
>> 4) & 3) {
8018 case 0: /* mov to cr */
8019 reg
= (exit_qualification
>> 8) & 15;
8020 val
= kvm_register_readl(vcpu
, reg
);
8023 if (vmcs12
->cr0_guest_host_mask
&
8024 (val
^ vmcs12
->cr0_read_shadow
))
8028 if ((vmcs12
->cr3_target_count
>= 1 &&
8029 vmcs12
->cr3_target_value0
== val
) ||
8030 (vmcs12
->cr3_target_count
>= 2 &&
8031 vmcs12
->cr3_target_value1
== val
) ||
8032 (vmcs12
->cr3_target_count
>= 3 &&
8033 vmcs12
->cr3_target_value2
== val
) ||
8034 (vmcs12
->cr3_target_count
>= 4 &&
8035 vmcs12
->cr3_target_value3
== val
))
8037 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8041 if (vmcs12
->cr4_guest_host_mask
&
8042 (vmcs12
->cr4_read_shadow
^ val
))
8046 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8052 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8053 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8056 case 1: /* mov from cr */
8059 if (vmcs12
->cpu_based_vm_exec_control
&
8060 CPU_BASED_CR3_STORE_EXITING
)
8064 if (vmcs12
->cpu_based_vm_exec_control
&
8065 CPU_BASED_CR8_STORE_EXITING
)
8072 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8073 * cr0. Other attempted changes are ignored, with no exit.
8075 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8076 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8077 (val
^ vmcs12
->cr0_read_shadow
))
8079 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8080 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8089 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8090 * should handle it ourselves in L0 (and then continue L2). Only call this
8091 * when in is_guest_mode (L2).
8093 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8095 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8096 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8097 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8099 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8100 vmcs_readl(EXIT_QUALIFICATION
),
8101 vmx
->idt_vectoring_info
,
8103 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8107 * The host physical addresses of some pages of guest memory
8108 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8109 * may write to these pages via their host physical address while
8110 * L2 is running, bypassing any address-translation-based dirty
8111 * tracking (e.g. EPT write protection).
8113 * Mark them dirty on every exit from L2 to prevent them from
8114 * getting out of sync with dirty tracking.
8116 nested_mark_vmcs12_pages_dirty(vcpu
);
8118 if (vmx
->nested
.nested_run_pending
)
8121 if (unlikely(vmx
->fail
)) {
8122 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8123 vmcs_read32(VM_INSTRUCTION_ERROR
));
8127 switch (exit_reason
) {
8128 case EXIT_REASON_EXCEPTION_NMI
:
8129 if (is_nmi(intr_info
))
8131 else if (is_page_fault(intr_info
))
8132 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8133 else if (is_no_device(intr_info
) &&
8134 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8136 else if (is_debug(intr_info
) &&
8138 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8140 else if (is_breakpoint(intr_info
) &&
8141 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8143 return vmcs12
->exception_bitmap
&
8144 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8145 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8147 case EXIT_REASON_TRIPLE_FAULT
:
8149 case EXIT_REASON_PENDING_INTERRUPT
:
8150 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8151 case EXIT_REASON_NMI_WINDOW
:
8152 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8153 case EXIT_REASON_TASK_SWITCH
:
8155 case EXIT_REASON_CPUID
:
8157 case EXIT_REASON_HLT
:
8158 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8159 case EXIT_REASON_INVD
:
8161 case EXIT_REASON_INVLPG
:
8162 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8163 case EXIT_REASON_RDPMC
:
8164 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8165 case EXIT_REASON_RDRAND
:
8166 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8167 case EXIT_REASON_RDSEED
:
8168 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8169 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8170 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8171 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8172 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8173 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8174 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8175 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8176 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8178 * VMX instructions trap unconditionally. This allows L1 to
8179 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8182 case EXIT_REASON_CR_ACCESS
:
8183 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8184 case EXIT_REASON_DR_ACCESS
:
8185 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8186 case EXIT_REASON_IO_INSTRUCTION
:
8187 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8188 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8189 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8190 case EXIT_REASON_MSR_READ
:
8191 case EXIT_REASON_MSR_WRITE
:
8192 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8193 case EXIT_REASON_INVALID_STATE
:
8195 case EXIT_REASON_MWAIT_INSTRUCTION
:
8196 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8197 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8198 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8199 case EXIT_REASON_MONITOR_INSTRUCTION
:
8200 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8201 case EXIT_REASON_PAUSE_INSTRUCTION
:
8202 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8203 nested_cpu_has2(vmcs12
,
8204 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8205 case EXIT_REASON_MCE_DURING_VMENTRY
:
8207 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8208 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8209 case EXIT_REASON_APIC_ACCESS
:
8210 return nested_cpu_has2(vmcs12
,
8211 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8212 case EXIT_REASON_APIC_WRITE
:
8213 case EXIT_REASON_EOI_INDUCED
:
8214 /* apic_write and eoi_induced should exit unconditionally. */
8216 case EXIT_REASON_EPT_VIOLATION
:
8218 * L0 always deals with the EPT violation. If nested EPT is
8219 * used, and the nested mmu code discovers that the address is
8220 * missing in the guest EPT table (EPT12), the EPT violation
8221 * will be injected with nested_ept_inject_page_fault()
8224 case EXIT_REASON_EPT_MISCONFIG
:
8226 * L2 never uses directly L1's EPT, but rather L0's own EPT
8227 * table (shadow on EPT) or a merged EPT table that L0 built
8228 * (EPT on EPT). So any problems with the structure of the
8229 * table is L0's fault.
8232 case EXIT_REASON_WBINVD
:
8233 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8234 case EXIT_REASON_XSETBV
:
8236 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8238 * This should never happen, since it is not possible to
8239 * set XSS to a non-zero value---neither in L1 nor in L2.
8240 * If if it were, XSS would have to be checked against
8241 * the XSS exit bitmap in vmcs12.
8243 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8244 case EXIT_REASON_PREEMPTION_TIMER
:
8246 case EXIT_REASON_PML_FULL
:
8247 /* We emulate PML support to L1. */
8254 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8256 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8259 * At this point, the exit interruption info in exit_intr_info
8260 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8261 * we need to query the in-kernel LAPIC.
8263 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8264 if ((exit_intr_info
&
8265 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8266 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8267 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8268 vmcs12
->vm_exit_intr_error_code
=
8269 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8272 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8273 vmcs_readl(EXIT_QUALIFICATION
));
8277 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8279 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8280 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8283 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8286 __free_page(vmx
->pml_pg
);
8291 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8293 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8297 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8299 /* Do nothing if PML buffer is empty */
8300 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8303 /* PML index always points to next available PML buffer entity */
8304 if (pml_idx
>= PML_ENTITY_NUM
)
8309 pml_buf
= page_address(vmx
->pml_pg
);
8310 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8313 gpa
= pml_buf
[pml_idx
];
8314 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8315 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8318 /* reset PML index */
8319 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8323 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8324 * Called before reporting dirty_bitmap to userspace.
8326 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8329 struct kvm_vcpu
*vcpu
;
8331 * We only need to kick vcpu out of guest mode here, as PML buffer
8332 * is flushed at beginning of all VMEXITs, and it's obvious that only
8333 * vcpus running in guest are possible to have unflushed GPAs in PML
8336 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8337 kvm_vcpu_kick(vcpu
);
8340 static void vmx_dump_sel(char *name
, uint32_t sel
)
8342 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8343 name
, vmcs_read16(sel
),
8344 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8345 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8346 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8349 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8351 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8352 name
, vmcs_read32(limit
),
8353 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8356 static void dump_vmcs(void)
8358 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8359 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8360 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8361 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8362 u32 secondary_exec_control
= 0;
8363 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8364 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8367 if (cpu_has_secondary_exec_ctrls())
8368 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8370 pr_err("*** Guest State ***\n");
8371 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8372 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8373 vmcs_readl(CR0_GUEST_HOST_MASK
));
8374 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8375 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8376 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8377 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8378 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8380 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8381 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8382 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8383 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8385 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8386 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8387 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8388 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8389 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8390 vmcs_readl(GUEST_SYSENTER_ESP
),
8391 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8392 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8393 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8394 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8395 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8396 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8397 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8398 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8399 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8400 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8401 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8402 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8403 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8404 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8405 efer
, vmcs_read64(GUEST_IA32_PAT
));
8406 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8407 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8408 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8409 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8410 pr_err("PerfGlobCtl = 0x%016llx\n",
8411 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8412 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8413 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8414 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8415 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8416 vmcs_read32(GUEST_ACTIVITY_STATE
));
8417 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8418 pr_err("InterruptStatus = %04x\n",
8419 vmcs_read16(GUEST_INTR_STATUS
));
8421 pr_err("*** Host State ***\n");
8422 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8423 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8424 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8425 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8426 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8427 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8428 vmcs_read16(HOST_TR_SELECTOR
));
8429 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8430 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8431 vmcs_readl(HOST_TR_BASE
));
8432 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8433 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8434 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8435 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8436 vmcs_readl(HOST_CR4
));
8437 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8438 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8439 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8440 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8441 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8442 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8443 vmcs_read64(HOST_IA32_EFER
),
8444 vmcs_read64(HOST_IA32_PAT
));
8445 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8446 pr_err("PerfGlobCtl = 0x%016llx\n",
8447 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8449 pr_err("*** Control State ***\n");
8450 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8451 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8452 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8453 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8454 vmcs_read32(EXCEPTION_BITMAP
),
8455 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8456 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8457 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8458 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8459 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8460 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8461 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8462 vmcs_read32(VM_EXIT_INTR_INFO
),
8463 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8464 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8465 pr_err(" reason=%08x qualification=%016lx\n",
8466 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8467 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8468 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8469 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8470 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8471 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8472 pr_err("TSC Multiplier = 0x%016llx\n",
8473 vmcs_read64(TSC_MULTIPLIER
));
8474 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8475 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8476 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8477 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8478 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8479 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8480 n
= vmcs_read32(CR3_TARGET_COUNT
);
8481 for (i
= 0; i
+ 1 < n
; i
+= 4)
8482 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8483 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8484 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8486 pr_err("CR3 target%u=%016lx\n",
8487 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8488 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8489 pr_err("PLE Gap=%08x Window=%08x\n",
8490 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8491 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8492 pr_err("Virtual processor ID = 0x%04x\n",
8493 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8497 * The guest has exited. See if we can fix it or if we need userspace
8500 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8502 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8503 u32 exit_reason
= vmx
->exit_reason
;
8504 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8506 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8507 vcpu
->arch
.gpa_available
= false;
8510 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8511 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8512 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8513 * mode as if vcpus is in root mode, the PML buffer must has been
8517 vmx_flush_pml_buffer(vcpu
);
8519 /* If guest state is invalid, start emulating */
8520 if (vmx
->emulation_required
)
8521 return handle_invalid_guest_state(vcpu
);
8523 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8524 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8526 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8528 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8529 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8534 if (unlikely(vmx
->fail
)) {
8535 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8536 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8537 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8543 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8544 * delivery event since it indicates guest is accessing MMIO.
8545 * The vm-exit can be triggered again after return to guest that
8546 * will cause infinite loop.
8548 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8549 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8550 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8551 exit_reason
!= EXIT_REASON_PML_FULL
&&
8552 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8553 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8554 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8555 vcpu
->run
->internal
.ndata
= 3;
8556 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8557 vcpu
->run
->internal
.data
[1] = exit_reason
;
8558 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8559 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8560 vcpu
->run
->internal
.ndata
++;
8561 vcpu
->run
->internal
.data
[3] =
8562 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8567 if (exit_reason
< kvm_vmx_max_exit_handlers
8568 && kvm_vmx_exit_handlers
[exit_reason
])
8569 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8571 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8573 kvm_queue_exception(vcpu
, UD_VECTOR
);
8578 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8580 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8582 if (is_guest_mode(vcpu
) &&
8583 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8586 if (irr
== -1 || tpr
< irr
) {
8587 vmcs_write32(TPR_THRESHOLD
, 0);
8591 vmcs_write32(TPR_THRESHOLD
, irr
);
8594 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8596 u32 sec_exec_control
;
8598 /* Postpone execution until vmcs01 is the current VMCS. */
8599 if (is_guest_mode(vcpu
)) {
8600 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8604 if (!cpu_has_vmx_virtualize_x2apic_mode())
8607 if (!cpu_need_tpr_shadow(vcpu
))
8610 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8613 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8614 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8616 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8617 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8618 vmx_flush_tlb_ept_only(vcpu
);
8620 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8622 vmx_set_msr_bitmap(vcpu
);
8625 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8627 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8630 * Currently we do not handle the nested case where L2 has an
8631 * APIC access page of its own; that page is still pinned.
8632 * Hence, we skip the case where the VCPU is in guest mode _and_
8633 * L1 prepared an APIC access page for L2.
8635 * For the case where L1 and L2 share the same APIC access page
8636 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8637 * in the vmcs12), this function will only update either the vmcs01
8638 * or the vmcs02. If the former, the vmcs02 will be updated by
8639 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8640 * the next L2->L1 exit.
8642 if (!is_guest_mode(vcpu
) ||
8643 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8644 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8645 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8646 vmx_flush_tlb_ept_only(vcpu
);
8650 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8658 status
= vmcs_read16(GUEST_INTR_STATUS
);
8660 if (max_isr
!= old
) {
8662 status
|= max_isr
<< 8;
8663 vmcs_write16(GUEST_INTR_STATUS
, status
);
8667 static void vmx_set_rvi(int vector
)
8675 status
= vmcs_read16(GUEST_INTR_STATUS
);
8676 old
= (u8
)status
& 0xff;
8677 if ((u8
)vector
!= old
) {
8679 status
|= (u8
)vector
;
8680 vmcs_write16(GUEST_INTR_STATUS
, status
);
8684 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8686 if (!is_guest_mode(vcpu
)) {
8687 vmx_set_rvi(max_irr
);
8695 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8698 if (nested_exit_on_intr(vcpu
))
8702 * Else, fall back to pre-APICv interrupt injection since L2
8703 * is run without virtual interrupt delivery.
8705 if (!kvm_event_needs_reinjection(vcpu
) &&
8706 vmx_interrupt_allowed(vcpu
)) {
8707 kvm_queue_interrupt(vcpu
, max_irr
, false);
8708 vmx_inject_irq(vcpu
);
8712 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8714 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8717 WARN_ON(!vcpu
->arch
.apicv_active
);
8718 if (pi_test_on(&vmx
->pi_desc
)) {
8719 pi_clear_on(&vmx
->pi_desc
);
8721 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8722 * But on x86 this is just a compiler barrier anyway.
8724 smp_mb__after_atomic();
8725 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8727 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8729 vmx_hwapic_irr_update(vcpu
, max_irr
);
8733 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8735 if (!kvm_vcpu_apicv_active(vcpu
))
8738 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8739 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8740 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8741 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8744 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8746 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8748 pi_clear_on(&vmx
->pi_desc
);
8749 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8752 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8754 u32 exit_intr_info
= 0;
8755 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8757 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8758 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8761 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8762 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8763 vmx
->exit_intr_info
= exit_intr_info
;
8765 /* if exit due to PF check for async PF */
8766 if (is_page_fault(exit_intr_info
))
8767 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8769 /* Handle machine checks before interrupts are enabled */
8770 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8771 is_machine_check(exit_intr_info
))
8772 kvm_machine_check();
8774 /* We need to handle NMIs before interrupts are enabled */
8775 if (is_nmi(exit_intr_info
)) {
8776 kvm_before_handle_nmi(&vmx
->vcpu
);
8778 kvm_after_handle_nmi(&vmx
->vcpu
);
8782 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8784 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8785 register void *__sp
asm(_ASM_SP
);
8787 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8788 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8789 unsigned int vector
;
8790 unsigned long entry
;
8792 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8793 #ifdef CONFIG_X86_64
8797 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8798 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8799 entry
= gate_offset(desc
);
8801 #ifdef CONFIG_X86_64
8802 "mov %%" _ASM_SP
", %[sp]\n\t"
8803 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8808 __ASM_SIZE(push
) " $%c[cs]\n\t"
8809 "call *%[entry]\n\t"
8811 #ifdef CONFIG_X86_64
8817 [ss
]"i"(__KERNEL_DS
),
8818 [cs
]"i"(__KERNEL_CS
)
8822 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8824 static bool vmx_has_high_real_mode_segbase(void)
8826 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8829 static bool vmx_mpx_supported(void)
8831 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8832 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8835 static bool vmx_xsaves_supported(void)
8837 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8838 SECONDARY_EXEC_XSAVES
;
8841 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8846 bool idtv_info_valid
;
8848 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8850 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
8853 * Can't use vmx->exit_intr_info since we're not sure what
8854 * the exit reason is.
8856 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8857 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8858 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8860 * SDM 3: 27.7.1.2 (September 2008)
8861 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8862 * a guest IRET fault.
8863 * SDM 3: 23.2.2 (September 2008)
8864 * Bit 12 is undefined in any of the following cases:
8865 * If the VM exit sets the valid bit in the IDT-vectoring
8866 * information field.
8867 * If the VM exit is due to a double fault.
8869 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8870 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8871 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8872 GUEST_INTR_STATE_NMI
);
8874 vmx
->loaded_vmcs
->nmi_known_unmasked
=
8875 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8876 & GUEST_INTR_STATE_NMI
);
8879 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8880 u32 idt_vectoring_info
,
8881 int instr_len_field
,
8882 int error_code_field
)
8886 bool idtv_info_valid
;
8888 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8890 vcpu
->arch
.nmi_injected
= false;
8891 kvm_clear_exception_queue(vcpu
);
8892 kvm_clear_interrupt_queue(vcpu
);
8894 if (!idtv_info_valid
)
8897 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8899 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8900 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8903 case INTR_TYPE_NMI_INTR
:
8904 vcpu
->arch
.nmi_injected
= true;
8906 * SDM 3: 27.7.1.2 (September 2008)
8907 * Clear bit "block by NMI" before VM entry if a NMI
8910 vmx_set_nmi_mask(vcpu
, false);
8912 case INTR_TYPE_SOFT_EXCEPTION
:
8913 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8915 case INTR_TYPE_HARD_EXCEPTION
:
8916 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8917 u32 err
= vmcs_read32(error_code_field
);
8918 kvm_requeue_exception_e(vcpu
, vector
, err
);
8920 kvm_requeue_exception(vcpu
, vector
);
8922 case INTR_TYPE_SOFT_INTR
:
8923 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8925 case INTR_TYPE_EXT_INTR
:
8926 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8933 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8935 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8936 VM_EXIT_INSTRUCTION_LEN
,
8937 IDT_VECTORING_ERROR_CODE
);
8940 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8942 __vmx_complete_interrupts(vcpu
,
8943 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8944 VM_ENTRY_INSTRUCTION_LEN
,
8945 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8947 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8950 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8953 struct perf_guest_switch_msr
*msrs
;
8955 msrs
= perf_guest_get_msrs(&nr_msrs
);
8960 for (i
= 0; i
< nr_msrs
; i
++)
8961 if (msrs
[i
].host
== msrs
[i
].guest
)
8962 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8964 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8968 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8970 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8974 if (vmx
->hv_deadline_tsc
== -1)
8978 if (vmx
->hv_deadline_tsc
> tscl
)
8979 /* sure to be 32 bit only because checked on set_hv_timer */
8980 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8981 cpu_preemption_timer_multi
);
8985 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8988 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8990 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8991 unsigned long debugctlmsr
, cr3
, cr4
;
8993 /* Don't enter VMX if guest state is invalid, let the exit handler
8994 start emulation until we arrive back to a valid state */
8995 if (vmx
->emulation_required
)
8998 if (vmx
->ple_window_dirty
) {
8999 vmx
->ple_window_dirty
= false;
9000 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9003 if (vmx
->nested
.sync_shadow_vmcs
) {
9004 copy_vmcs12_to_shadow(vmx
);
9005 vmx
->nested
.sync_shadow_vmcs
= false;
9008 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9009 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9010 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9011 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9013 cr3
= __get_current_cr3_fast();
9014 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9015 vmcs_writel(HOST_CR3
, cr3
);
9016 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9019 cr4
= cr4_read_shadow();
9020 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9021 vmcs_writel(HOST_CR4
, cr4
);
9022 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9025 /* When single-stepping over STI and MOV SS, we must clear the
9026 * corresponding interruptibility bits in the guest state. Otherwise
9027 * vmentry fails as it then expects bit 14 (BS) in pending debug
9028 * exceptions being set, but that's not correct for the guest debugging
9030 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9031 vmx_set_interrupt_shadow(vcpu
, 0);
9033 if (static_cpu_has(X86_FEATURE_PKU
) &&
9034 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9035 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9036 __write_pkru(vcpu
->arch
.pkru
);
9038 atomic_switch_perf_msrs(vmx
);
9039 debugctlmsr
= get_debugctlmsr();
9041 vmx_arm_hv_timer(vcpu
);
9043 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9045 /* Store host registers */
9046 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9047 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9048 "push %%" _ASM_CX
" \n\t"
9049 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9051 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9052 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9054 /* Reload cr2 if changed */
9055 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9056 "mov %%cr2, %%" _ASM_DX
" \n\t"
9057 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9059 "mov %%" _ASM_AX
", %%cr2 \n\t"
9061 /* Check if vmlaunch of vmresume is needed */
9062 "cmpl $0, %c[launched](%0) \n\t"
9063 /* Load guest registers. Don't clobber flags. */
9064 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9065 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9066 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9067 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9068 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9069 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9070 #ifdef CONFIG_X86_64
9071 "mov %c[r8](%0), %%r8 \n\t"
9072 "mov %c[r9](%0), %%r9 \n\t"
9073 "mov %c[r10](%0), %%r10 \n\t"
9074 "mov %c[r11](%0), %%r11 \n\t"
9075 "mov %c[r12](%0), %%r12 \n\t"
9076 "mov %c[r13](%0), %%r13 \n\t"
9077 "mov %c[r14](%0), %%r14 \n\t"
9078 "mov %c[r15](%0), %%r15 \n\t"
9080 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9082 /* Enter guest mode */
9084 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9086 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9088 /* Save guest registers, load host registers, keep flags */
9089 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9091 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9092 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9093 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9094 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9095 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9096 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9097 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9098 #ifdef CONFIG_X86_64
9099 "mov %%r8, %c[r8](%0) \n\t"
9100 "mov %%r9, %c[r9](%0) \n\t"
9101 "mov %%r10, %c[r10](%0) \n\t"
9102 "mov %%r11, %c[r11](%0) \n\t"
9103 "mov %%r12, %c[r12](%0) \n\t"
9104 "mov %%r13, %c[r13](%0) \n\t"
9105 "mov %%r14, %c[r14](%0) \n\t"
9106 "mov %%r15, %c[r15](%0) \n\t"
9108 "mov %%cr2, %%" _ASM_AX
" \n\t"
9109 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9111 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9112 "setbe %c[fail](%0) \n\t"
9113 ".pushsection .rodata \n\t"
9114 ".global vmx_return \n\t"
9115 "vmx_return: " _ASM_PTR
" 2b \n\t"
9117 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9118 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9119 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9120 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9121 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9122 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9123 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9124 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9125 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9126 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9127 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9128 #ifdef CONFIG_X86_64
9129 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9130 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9131 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9132 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9133 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9134 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9135 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9136 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9138 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9139 [wordsize
]"i"(sizeof(ulong
))
9141 #ifdef CONFIG_X86_64
9142 , "rax", "rbx", "rdi", "rsi"
9143 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9145 , "eax", "ebx", "edi", "esi"
9149 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9151 update_debugctlmsr(debugctlmsr
);
9153 #ifndef CONFIG_X86_64
9155 * The sysexit path does not restore ds/es, so we must set them to
9156 * a reasonable value ourselves.
9158 * We can't defer this to vmx_load_host_state() since that function
9159 * may be executed in interrupt context, which saves and restore segments
9160 * around it, nullifying its effect.
9162 loadsegment(ds
, __USER_DS
);
9163 loadsegment(es
, __USER_DS
);
9166 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9167 | (1 << VCPU_EXREG_RFLAGS
)
9168 | (1 << VCPU_EXREG_PDPTR
)
9169 | (1 << VCPU_EXREG_SEGMENTS
)
9170 | (1 << VCPU_EXREG_CR3
));
9171 vcpu
->arch
.regs_dirty
= 0;
9173 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9175 vmx
->loaded_vmcs
->launched
= 1;
9177 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9180 * eager fpu is enabled if PKEY is supported and CR4 is switched
9181 * back on host, so it is safe to read guest PKRU from current
9184 if (static_cpu_has(X86_FEATURE_PKU
) &&
9185 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9186 vcpu
->arch
.pkru
= __read_pkru();
9187 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9188 __write_pkru(vmx
->host_pkru
);
9192 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9193 * we did not inject a still-pending event to L1 now because of
9194 * nested_run_pending, we need to re-enable this bit.
9196 if (vmx
->nested
.nested_run_pending
)
9197 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9199 vmx
->nested
.nested_run_pending
= 0;
9201 vmx_complete_atomic_exit(vmx
);
9202 vmx_recover_nmi_blocking(vmx
);
9203 vmx_complete_interrupts(vmx
);
9205 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9207 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9209 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9212 if (vmx
->loaded_vmcs
== vmcs
)
9216 vmx
->loaded_vmcs
= vmcs
;
9218 vmx_vcpu_load(vcpu
, cpu
);
9224 * Ensure that the current vmcs of the logical processor is the
9225 * vmcs01 of the vcpu before calling free_nested().
9227 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9229 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9232 r
= vcpu_load(vcpu
);
9234 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9239 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9241 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9244 vmx_destroy_pml_buffer(vmx
);
9245 free_vpid(vmx
->vpid
);
9246 leave_guest_mode(vcpu
);
9247 vmx_free_vcpu_nested(vcpu
);
9248 free_loaded_vmcs(vmx
->loaded_vmcs
);
9249 kfree(vmx
->guest_msrs
);
9250 kvm_vcpu_uninit(vcpu
);
9251 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9254 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9257 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9261 return ERR_PTR(-ENOMEM
);
9263 vmx
->vpid
= allocate_vpid();
9265 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9272 * If PML is turned on, failure on enabling PML just results in failure
9273 * of creating the vcpu, therefore we can simplify PML logic (by
9274 * avoiding dealing with cases, such as enabling PML partially on vcpus
9275 * for the guest, etc.
9278 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9283 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9284 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9287 if (!vmx
->guest_msrs
)
9290 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9291 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9292 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9293 if (!vmx
->loaded_vmcs
->vmcs
)
9295 loaded_vmcs_init(vmx
->loaded_vmcs
);
9298 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9299 vmx
->vcpu
.cpu
= cpu
;
9300 err
= vmx_vcpu_setup(vmx
);
9301 vmx_vcpu_put(&vmx
->vcpu
);
9305 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9306 err
= alloc_apic_access_page(kvm
);
9312 if (!kvm
->arch
.ept_identity_map_addr
)
9313 kvm
->arch
.ept_identity_map_addr
=
9314 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9315 err
= init_rmode_identity_map(kvm
);
9321 nested_vmx_setup_ctls_msrs(vmx
);
9322 vmx
->nested
.vpid02
= allocate_vpid();
9325 vmx
->nested
.posted_intr_nv
= -1;
9326 vmx
->nested
.current_vmptr
= -1ull;
9328 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9331 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9332 * or POSTED_INTR_WAKEUP_VECTOR.
9334 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9335 vmx
->pi_desc
.sn
= 1;
9340 free_vpid(vmx
->nested
.vpid02
);
9341 free_loaded_vmcs(vmx
->loaded_vmcs
);
9343 kfree(vmx
->guest_msrs
);
9345 vmx_destroy_pml_buffer(vmx
);
9347 kvm_vcpu_uninit(&vmx
->vcpu
);
9349 free_vpid(vmx
->vpid
);
9350 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9351 return ERR_PTR(err
);
9354 static void __init
vmx_check_processor_compat(void *rtn
)
9356 struct vmcs_config vmcs_conf
;
9359 if (setup_vmcs_config(&vmcs_conf
) < 0)
9361 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9362 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9363 smp_processor_id());
9368 static int get_ept_level(void)
9370 return VMX_EPT_DEFAULT_GAW
+ 1;
9373 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9378 /* For VT-d and EPT combination
9379 * 1. MMIO: always map as UC
9381 * a. VT-d without snooping control feature: can't guarantee the
9382 * result, try to trust guest.
9383 * b. VT-d with snooping control feature: snooping control feature of
9384 * VT-d engine can guarantee the cache correctness. Just set it
9385 * to WB to keep consistent with host. So the same as item 3.
9386 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9387 * consistent with host MTRR
9390 cache
= MTRR_TYPE_UNCACHABLE
;
9394 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9395 ipat
= VMX_EPT_IPAT_BIT
;
9396 cache
= MTRR_TYPE_WRBACK
;
9400 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9401 ipat
= VMX_EPT_IPAT_BIT
;
9402 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9403 cache
= MTRR_TYPE_WRBACK
;
9405 cache
= MTRR_TYPE_UNCACHABLE
;
9409 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9412 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9415 static int vmx_get_lpage_level(void)
9417 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9418 return PT_DIRECTORY_LEVEL
;
9420 /* For shadow and EPT supported 1GB page */
9421 return PT_PDPE_LEVEL
;
9424 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9427 * These bits in the secondary execution controls field
9428 * are dynamic, the others are mostly based on the hypervisor
9429 * architecture and the guest's CPUID. Do not touch the
9433 SECONDARY_EXEC_SHADOW_VMCS
|
9434 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9435 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9437 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9439 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9440 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9444 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9445 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9447 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9449 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9450 struct kvm_cpuid_entry2
*entry
;
9452 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9453 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9455 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9456 if (entry && (entry->_reg & (_cpuid_mask))) \
9457 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9460 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9461 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9462 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9463 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9464 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9465 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9466 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9467 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9468 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9469 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9470 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9471 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9472 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9473 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9474 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9476 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9477 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9478 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9479 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9480 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9481 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9482 cr4_fixed1_update(bit(11), ecx
, bit(2));
9484 #undef cr4_fixed1_update
9487 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9489 struct kvm_cpuid_entry2
*best
;
9490 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9491 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9493 if (vmx_rdtscp_supported()) {
9494 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9495 if (!rdtscp_enabled
)
9496 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9500 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9501 SECONDARY_EXEC_RDTSCP
;
9503 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9504 ~SECONDARY_EXEC_RDTSCP
;
9508 /* Exposing INVPCID only when PCID is exposed */
9509 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9510 if (vmx_invpcid_supported() &&
9511 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9512 !guest_cpuid_has_pcid(vcpu
))) {
9513 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9516 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9519 if (cpu_has_secondary_exec_ctrls())
9520 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9522 if (nested_vmx_allowed(vcpu
))
9523 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9524 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9526 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9527 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9529 if (nested_vmx_allowed(vcpu
))
9530 nested_vmx_cr_fixed1_bits_update(vcpu
);
9533 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9535 if (func
== 1 && nested
)
9536 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9539 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9540 struct x86_exception
*fault
)
9542 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9543 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9545 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9547 if (vmx
->nested
.pml_full
) {
9548 exit_reason
= EXIT_REASON_PML_FULL
;
9549 vmx
->nested
.pml_full
= false;
9550 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9551 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9552 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9554 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9556 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9557 vmcs12
->guest_physical_address
= fault
->address
;
9560 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9562 return nested_ept_get_cr3(vcpu
) & VMX_EPT_AD_ENABLE_BIT
;
9565 /* Callbacks for nested_ept_init_mmu_context: */
9567 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9569 /* return the page table to be shadowed - in our case, EPT12 */
9570 return get_vmcs12(vcpu
)->ept_pointer
;
9573 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9577 WARN_ON(mmu_is_nested(vcpu
));
9578 wants_ad
= nested_ept_ad_enabled(vcpu
);
9579 if (wants_ad
&& !enable_ept_ad_bits
)
9582 kvm_mmu_unload(vcpu
);
9583 kvm_init_shadow_ept_mmu(vcpu
,
9584 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9585 VMX_EPT_EXECUTE_ONLY_BIT
,
9587 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9588 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9589 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9591 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9595 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9597 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9600 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9603 bool inequality
, bit
;
9605 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9607 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9608 vmcs12
->page_fault_error_code_match
;
9609 return inequality
^ bit
;
9612 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9613 struct x86_exception
*fault
)
9615 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9617 WARN_ON(!is_guest_mode(vcpu
));
9619 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9620 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9621 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9622 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9623 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9626 kvm_inject_page_fault(vcpu
, fault
);
9630 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9631 struct vmcs12
*vmcs12
);
9633 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9634 struct vmcs12
*vmcs12
)
9636 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9639 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9641 * Translate L1 physical address to host physical
9642 * address for vmcs02. Keep the page pinned, so this
9643 * physical address remains valid. We keep a reference
9644 * to it so we can release it later.
9646 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9647 nested_release_page(vmx
->nested
.apic_access_page
);
9648 vmx
->nested
.apic_access_page
=
9649 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9651 * If translation failed, no matter: This feature asks
9652 * to exit when accessing the given address, and if it
9653 * can never be accessed, this feature won't do
9656 if (vmx
->nested
.apic_access_page
) {
9657 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9658 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9660 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9661 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9663 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9664 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9665 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9666 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9667 kvm_vcpu_reload_apic_access_page(vcpu
);
9670 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9671 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9672 nested_release_page(vmx
->nested
.virtual_apic_page
);
9673 vmx
->nested
.virtual_apic_page
=
9674 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9677 * If translation failed, VM entry will fail because
9678 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9679 * Failing the vm entry is _not_ what the processor
9680 * does but it's basically the only possibility we
9681 * have. We could still enter the guest if CR8 load
9682 * exits are enabled, CR8 store exits are enabled, and
9683 * virtualize APIC access is disabled; in this case
9684 * the processor would never use the TPR shadow and we
9685 * could simply clear the bit from the execution
9686 * control. But such a configuration is useless, so
9687 * let's keep the code simple.
9689 if (vmx
->nested
.virtual_apic_page
) {
9690 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9691 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9695 if (nested_cpu_has_posted_intr(vmcs12
)) {
9696 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9697 kunmap(vmx
->nested
.pi_desc_page
);
9698 nested_release_page(vmx
->nested
.pi_desc_page
);
9700 vmx
->nested
.pi_desc_page
=
9701 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9702 vmx
->nested
.pi_desc
=
9703 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9704 if (!vmx
->nested
.pi_desc
) {
9705 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9708 vmx
->nested
.pi_desc
=
9709 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9710 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9712 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9713 page_to_phys(vmx
->nested
.pi_desc_page
) +
9714 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9717 if (cpu_has_vmx_msr_bitmap() &&
9718 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9719 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9722 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9723 CPU_BASED_USE_MSR_BITMAPS
);
9726 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9728 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9729 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9731 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9734 /* Make sure short timeouts reliably trigger an immediate vmexit.
9735 * hrtimer_start does not guarantee this. */
9736 if (preemption_timeout
<= 1) {
9737 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9741 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9742 preemption_timeout
*= 1000000;
9743 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9744 hrtimer_start(&vmx
->nested
.preemption_timer
,
9745 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9748 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9749 struct vmcs12
*vmcs12
)
9751 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9754 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9755 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9761 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9762 struct vmcs12
*vmcs12
)
9764 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9767 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9774 * Merge L0's and L1's MSR bitmap, return false to indicate that
9775 * we do not use the hardware.
9777 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9778 struct vmcs12
*vmcs12
)
9782 unsigned long *msr_bitmap_l1
;
9783 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9785 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9786 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9789 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9792 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9794 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9796 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9797 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9798 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9799 nested_vmx_disable_intercept_for_msr(
9800 msr_bitmap_l1
, msr_bitmap_l0
,
9803 nested_vmx_disable_intercept_for_msr(
9804 msr_bitmap_l1
, msr_bitmap_l0
,
9805 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9806 MSR_TYPE_R
| MSR_TYPE_W
);
9808 if (nested_cpu_has_vid(vmcs12
)) {
9809 nested_vmx_disable_intercept_for_msr(
9810 msr_bitmap_l1
, msr_bitmap_l0
,
9811 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9813 nested_vmx_disable_intercept_for_msr(
9814 msr_bitmap_l1
, msr_bitmap_l0
,
9815 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9820 nested_release_page_clean(page
);
9825 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9826 struct vmcs12
*vmcs12
)
9828 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9829 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9830 !nested_cpu_has_vid(vmcs12
) &&
9831 !nested_cpu_has_posted_intr(vmcs12
))
9835 * If virtualize x2apic mode is enabled,
9836 * virtualize apic access must be disabled.
9838 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9839 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9843 * If virtual interrupt delivery is enabled,
9844 * we must exit on external interrupts.
9846 if (nested_cpu_has_vid(vmcs12
) &&
9847 !nested_exit_on_intr(vcpu
))
9851 * bits 15:8 should be zero in posted_intr_nv,
9852 * the descriptor address has been already checked
9853 * in nested_get_vmcs12_pages.
9855 if (nested_cpu_has_posted_intr(vmcs12
) &&
9856 (!nested_cpu_has_vid(vmcs12
) ||
9857 !nested_exit_intr_ack_set(vcpu
) ||
9858 vmcs12
->posted_intr_nv
& 0xff00))
9861 /* tpr shadow is needed by all apicv features. */
9862 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9868 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9869 unsigned long count_field
,
9870 unsigned long addr_field
)
9875 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9876 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9882 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9883 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9884 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9885 pr_debug_ratelimited(
9886 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9887 addr_field
, maxphyaddr
, count
, addr
);
9893 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9894 struct vmcs12
*vmcs12
)
9896 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9897 vmcs12
->vm_exit_msr_store_count
== 0 &&
9898 vmcs12
->vm_entry_msr_load_count
== 0)
9899 return 0; /* Fast path */
9900 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9901 VM_EXIT_MSR_LOAD_ADDR
) ||
9902 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9903 VM_EXIT_MSR_STORE_ADDR
) ||
9904 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9905 VM_ENTRY_MSR_LOAD_ADDR
))
9910 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9911 struct vmcs12
*vmcs12
)
9913 u64 address
= vmcs12
->pml_address
;
9914 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9916 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9917 if (!nested_cpu_has_ept(vmcs12
) ||
9918 !IS_ALIGNED(address
, 4096) ||
9919 address
>> maxphyaddr
)
9926 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9927 struct vmx_msr_entry
*e
)
9929 /* x2APIC MSR accesses are not allowed */
9930 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9932 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9933 e
->index
== MSR_IA32_UCODE_REV
)
9935 if (e
->reserved
!= 0)
9940 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9941 struct vmx_msr_entry
*e
)
9943 if (e
->index
== MSR_FS_BASE
||
9944 e
->index
== MSR_GS_BASE
||
9945 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9946 nested_vmx_msr_check_common(vcpu
, e
))
9951 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9952 struct vmx_msr_entry
*e
)
9954 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9955 nested_vmx_msr_check_common(vcpu
, e
))
9961 * Load guest's/host's msr at nested entry/exit.
9962 * return 0 for success, entry index for failure.
9964 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9967 struct vmx_msr_entry e
;
9968 struct msr_data msr
;
9970 msr
.host_initiated
= false;
9971 for (i
= 0; i
< count
; i
++) {
9972 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9974 pr_debug_ratelimited(
9975 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9976 __func__
, i
, gpa
+ i
* sizeof(e
));
9979 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9980 pr_debug_ratelimited(
9981 "%s check failed (%u, 0x%x, 0x%x)\n",
9982 __func__
, i
, e
.index
, e
.reserved
);
9985 msr
.index
= e
.index
;
9987 if (kvm_set_msr(vcpu
, &msr
)) {
9988 pr_debug_ratelimited(
9989 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9990 __func__
, i
, e
.index
, e
.value
);
9999 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10002 struct vmx_msr_entry e
;
10004 for (i
= 0; i
< count
; i
++) {
10005 struct msr_data msr_info
;
10006 if (kvm_vcpu_read_guest(vcpu
,
10007 gpa
+ i
* sizeof(e
),
10008 &e
, 2 * sizeof(u32
))) {
10009 pr_debug_ratelimited(
10010 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10011 __func__
, i
, gpa
+ i
* sizeof(e
));
10014 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10015 pr_debug_ratelimited(
10016 "%s check failed (%u, 0x%x, 0x%x)\n",
10017 __func__
, i
, e
.index
, e
.reserved
);
10020 msr_info
.host_initiated
= false;
10021 msr_info
.index
= e
.index
;
10022 if (kvm_get_msr(vcpu
, &msr_info
)) {
10023 pr_debug_ratelimited(
10024 "%s cannot read MSR (%u, 0x%x)\n",
10025 __func__
, i
, e
.index
);
10028 if (kvm_vcpu_write_guest(vcpu
,
10029 gpa
+ i
* sizeof(e
) +
10030 offsetof(struct vmx_msr_entry
, value
),
10031 &msr_info
.data
, sizeof(msr_info
.data
))) {
10032 pr_debug_ratelimited(
10033 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10034 __func__
, i
, e
.index
, msr_info
.data
);
10041 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10043 unsigned long invalid_mask
;
10045 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10046 return (val
& invalid_mask
) == 0;
10050 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10051 * emulating VM entry into a guest with EPT enabled.
10052 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10053 * is assigned to entry_failure_code on failure.
10055 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10056 u32
*entry_failure_code
)
10058 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10059 if (!nested_cr3_valid(vcpu
, cr3
)) {
10060 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10065 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10066 * must not be dereferenced.
10068 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10070 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10071 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10076 vcpu
->arch
.cr3
= cr3
;
10077 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10080 kvm_mmu_reset_context(vcpu
);
10085 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10086 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10087 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10088 * guest in a way that will both be appropriate to L1's requests, and our
10089 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10090 * function also has additional necessary side-effects, like setting various
10091 * vcpu->arch fields.
10092 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10093 * is assigned to entry_failure_code on failure.
10095 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10096 bool from_vmentry
, u32
*entry_failure_code
)
10098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10099 u32 exec_control
, vmcs12_exec_ctrl
;
10101 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10102 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10103 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10104 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10105 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10106 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10107 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10108 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10109 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10110 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10111 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10112 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10113 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10114 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10115 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10116 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10117 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10118 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10119 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10120 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10121 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10122 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10123 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10124 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10125 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10126 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10127 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10128 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10129 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10130 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10131 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10132 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10133 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10134 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10135 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10136 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10138 if (from_vmentry
&&
10139 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10140 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10141 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10143 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10144 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10146 if (from_vmentry
) {
10147 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10148 vmcs12
->vm_entry_intr_info_field
);
10149 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10150 vmcs12
->vm_entry_exception_error_code
);
10151 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10152 vmcs12
->vm_entry_instruction_len
);
10153 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10154 vmcs12
->guest_interruptibility_info
);
10155 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10156 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10158 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10160 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10161 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10162 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10163 vmcs12
->guest_pending_dbg_exceptions
);
10164 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10165 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10167 if (nested_cpu_has_xsaves(vmcs12
))
10168 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10169 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10171 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10173 /* Preemption timer setting is only taken from vmcs01. */
10174 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10175 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10176 if (vmx
->hv_deadline_tsc
== -1)
10177 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10179 /* Posted interrupts setting is only taken from vmcs12. */
10180 if (nested_cpu_has_posted_intr(vmcs12
)) {
10181 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10182 vmx
->nested
.pi_pending
= false;
10183 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10185 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10188 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10190 vmx
->nested
.preemption_timer_expired
= false;
10191 if (nested_cpu_has_preemption_timer(vmcs12
))
10192 vmx_start_preemption_timer(vcpu
);
10195 * Whether page-faults are trapped is determined by a combination of
10196 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10197 * If enable_ept, L0 doesn't care about page faults and we should
10198 * set all of these to L1's desires. However, if !enable_ept, L0 does
10199 * care about (at least some) page faults, and because it is not easy
10200 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10201 * to exit on each and every L2 page fault. This is done by setting
10202 * MASK=MATCH=0 and (see below) EB.PF=1.
10203 * Note that below we don't need special code to set EB.PF beyond the
10204 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10205 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10206 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10208 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10209 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10210 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10211 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10213 if (cpu_has_secondary_exec_ctrls()) {
10214 exec_control
= vmx_secondary_exec_control(vmx
);
10216 /* Take the following fields only from vmcs12 */
10217 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10218 SECONDARY_EXEC_RDTSCP
|
10219 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10220 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10221 if (nested_cpu_has(vmcs12
,
10222 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10223 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10224 ~SECONDARY_EXEC_ENABLE_PML
;
10225 exec_control
|= vmcs12_exec_ctrl
;
10228 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10229 vmcs_write64(EOI_EXIT_BITMAP0
,
10230 vmcs12
->eoi_exit_bitmap0
);
10231 vmcs_write64(EOI_EXIT_BITMAP1
,
10232 vmcs12
->eoi_exit_bitmap1
);
10233 vmcs_write64(EOI_EXIT_BITMAP2
,
10234 vmcs12
->eoi_exit_bitmap2
);
10235 vmcs_write64(EOI_EXIT_BITMAP3
,
10236 vmcs12
->eoi_exit_bitmap3
);
10237 vmcs_write16(GUEST_INTR_STATUS
,
10238 vmcs12
->guest_intr_status
);
10242 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10243 * nested_get_vmcs12_pages will either fix it up or
10244 * remove the VM execution control.
10246 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10247 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10249 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10254 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10255 * Some constant fields are set here by vmx_set_constant_host_state().
10256 * Other fields are different per CPU, and will be set later when
10257 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10259 vmx_set_constant_host_state(vmx
);
10262 * Set the MSR load/store lists to match L0's settings.
10264 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10265 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10266 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10267 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10268 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10271 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10272 * entry, but only if the current (host) sp changed from the value
10273 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10274 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10275 * here we just force the write to happen on entry.
10279 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10280 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10281 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10282 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10283 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10286 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10287 * nested_get_vmcs12_pages can't fix it up, the illegal value
10288 * will result in a VM entry failure.
10290 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10291 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10292 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10294 #ifdef CONFIG_X86_64
10295 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10296 CPU_BASED_CR8_STORE_EXITING
;
10301 * Merging of IO bitmap not currently supported.
10302 * Rather, exit every time.
10304 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10305 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10307 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10309 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10310 * bitwise-or of what L1 wants to trap for L2, and what we want to
10311 * trap. Note that CR0.TS also needs updating - we do this later.
10313 update_exception_bitmap(vcpu
);
10314 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10315 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10317 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10318 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10319 * bits are further modified by vmx_set_efer() below.
10321 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10323 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10324 * emulated by vmx_set_efer(), below.
10326 vm_entry_controls_init(vmx
,
10327 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10328 ~VM_ENTRY_IA32E_MODE
) |
10329 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10331 if (from_vmentry
&&
10332 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10333 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10334 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10335 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10336 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10339 set_cr4_guest_host_mask(vmx
);
10341 if (from_vmentry
&&
10342 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10343 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10345 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10346 vmcs_write64(TSC_OFFSET
,
10347 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10349 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10350 if (kvm_has_tsc_control
)
10351 decache_tsc_multiplier(vmx
);
10355 * There is no direct mapping between vpid02 and vpid12, the
10356 * vpid02 is per-vCPU for L0 and reused while the value of
10357 * vpid12 is changed w/ one invvpid during nested vmentry.
10358 * The vpid12 is allocated by L1 for L2, so it will not
10359 * influence global bitmap(for vpid01 and vpid02 allocation)
10360 * even if spawn a lot of nested vCPUs.
10362 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10363 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10364 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10365 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10366 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10369 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10370 vmx_flush_tlb(vcpu
);
10377 * Conceptually we want to copy the PML address and index from
10378 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10379 * since we always flush the log on each vmexit, this happens
10380 * to be equivalent to simply resetting the fields in vmcs02.
10382 ASSERT(vmx
->pml_pg
);
10383 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10384 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10387 if (nested_cpu_has_ept(vmcs12
)) {
10388 if (nested_ept_init_mmu_context(vcpu
)) {
10389 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10392 } else if (nested_cpu_has2(vmcs12
,
10393 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10394 vmx_flush_tlb_ept_only(vcpu
);
10398 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10399 * bits which we consider mandatory enabled.
10400 * The CR0_READ_SHADOW is what L2 should have expected to read given
10401 * the specifications by L1; It's not enough to take
10402 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10403 * have more bits than L1 expected.
10405 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10406 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10408 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10409 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10411 if (from_vmentry
&&
10412 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10413 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10414 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10415 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10417 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10418 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10419 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10421 /* Shadow page tables on either EPT or shadow page tables. */
10422 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10423 entry_failure_code
))
10427 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10430 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10433 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10434 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10435 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10436 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10439 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10440 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10444 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10448 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10449 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10450 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10452 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10453 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10455 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10456 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10458 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10459 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10461 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10462 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10464 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10465 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10467 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10468 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10469 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10470 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10471 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10472 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10473 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10474 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10475 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10476 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10477 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10478 vmx
->nested
.nested_vmx_exit_ctls_low
,
10479 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10480 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10481 vmx
->nested
.nested_vmx_entry_ctls_low
,
10482 vmx
->nested
.nested_vmx_entry_ctls_high
))
10483 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10485 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10486 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10488 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10489 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10490 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10491 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10496 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10501 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10503 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10504 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10507 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10508 vmcs12
->vmcs_link_pointer
!= -1ull) {
10509 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10514 * If the load IA32_EFER VM-entry control is 1, the following checks
10515 * are performed on the field for the IA32_EFER MSR:
10516 * - Bits reserved in the IA32_EFER MSR must be 0.
10517 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10518 * the IA-32e mode guest VM-exit control. It must also be identical
10519 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10522 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10523 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10524 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10525 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10526 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10527 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10528 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10533 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10534 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10535 * the values of the LMA and LME bits in the field must each be that of
10536 * the host address-space size VM-exit control.
10538 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10539 ia32e
= (vmcs12
->vm_exit_controls
&
10540 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10541 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10542 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10543 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10550 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10552 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10553 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10554 struct loaded_vmcs
*vmcs02
;
10558 vmcs02
= nested_get_current_vmcs02(vmx
);
10562 enter_guest_mode(vcpu
);
10564 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10565 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10567 vmx_switch_vmcs(vcpu
, vmcs02
);
10568 vmx_segment_cache_clear(vmx
);
10570 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10571 leave_guest_mode(vcpu
);
10572 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10573 nested_vmx_entry_failure(vcpu
, vmcs12
,
10574 EXIT_REASON_INVALID_STATE
, exit_qual
);
10578 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10580 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10581 vmcs12
->vm_entry_msr_load_addr
,
10582 vmcs12
->vm_entry_msr_load_count
);
10583 if (msr_entry_idx
) {
10584 leave_guest_mode(vcpu
);
10585 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10586 nested_vmx_entry_failure(vcpu
, vmcs12
,
10587 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10592 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10593 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10594 * returned as far as L1 is concerned. It will only return (and set
10595 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10601 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10602 * for running an L2 nested guest.
10604 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10606 struct vmcs12
*vmcs12
;
10607 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10608 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10612 if (!nested_vmx_check_permission(vcpu
))
10615 if (!nested_vmx_check_vmcs12(vcpu
))
10618 vmcs12
= get_vmcs12(vcpu
);
10620 if (enable_shadow_vmcs
)
10621 copy_shadow_to_vmcs12(vmx
);
10624 * The nested entry process starts with enforcing various prerequisites
10625 * on vmcs12 as required by the Intel SDM, and act appropriately when
10626 * they fail: As the SDM explains, some conditions should cause the
10627 * instruction to fail, while others will cause the instruction to seem
10628 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10629 * To speed up the normal (success) code path, we should avoid checking
10630 * for misconfigurations which will anyway be caught by the processor
10631 * when using the merged vmcs02.
10633 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10634 nested_vmx_failValid(vcpu
,
10635 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10639 if (vmcs12
->launch_state
== launch
) {
10640 nested_vmx_failValid(vcpu
,
10641 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10642 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10646 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10648 nested_vmx_failValid(vcpu
, ret
);
10653 * After this point, the trap flag no longer triggers a singlestep trap
10654 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10655 * This is not 100% correct; for performance reasons, we delegate most
10656 * of the checks on host state to the processor. If those fail,
10657 * the singlestep trap is missed.
10659 skip_emulated_instruction(vcpu
);
10661 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10663 nested_vmx_entry_failure(vcpu
, vmcs12
,
10664 EXIT_REASON_INVALID_STATE
, exit_qual
);
10669 * We're finally done with prerequisite checking, and can start with
10670 * the nested entry.
10673 ret
= enter_vmx_non_root_mode(vcpu
, true);
10677 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10678 return kvm_vcpu_halt(vcpu
);
10680 vmx
->nested
.nested_run_pending
= 1;
10685 return kvm_skip_emulated_instruction(vcpu
);
10689 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10690 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10691 * This function returns the new value we should put in vmcs12.guest_cr0.
10692 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10693 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10694 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10695 * didn't trap the bit, because if L1 did, so would L0).
10696 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10697 * been modified by L2, and L1 knows it. So just leave the old value of
10698 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10699 * isn't relevant, because if L0 traps this bit it can set it to anything.
10700 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10701 * changed these bits, and therefore they need to be updated, but L0
10702 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10703 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10705 static inline unsigned long
10706 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10709 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10710 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10711 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10712 vcpu
->arch
.cr0_guest_owned_bits
));
10715 static inline unsigned long
10716 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10719 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10720 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10721 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10722 vcpu
->arch
.cr4_guest_owned_bits
));
10725 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10726 struct vmcs12
*vmcs12
)
10731 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10732 nr
= vcpu
->arch
.exception
.nr
;
10733 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10735 if (kvm_exception_is_soft(nr
)) {
10736 vmcs12
->vm_exit_instruction_len
=
10737 vcpu
->arch
.event_exit_inst_len
;
10738 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10740 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10742 if (vcpu
->arch
.exception
.has_error_code
) {
10743 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10744 vmcs12
->idt_vectoring_error_code
=
10745 vcpu
->arch
.exception
.error_code
;
10748 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10749 } else if (vcpu
->arch
.nmi_injected
) {
10750 vmcs12
->idt_vectoring_info_field
=
10751 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10752 } else if (vcpu
->arch
.interrupt
.pending
) {
10753 nr
= vcpu
->arch
.interrupt
.nr
;
10754 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10756 if (vcpu
->arch
.interrupt
.soft
) {
10757 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10758 vmcs12
->vm_entry_instruction_len
=
10759 vcpu
->arch
.event_exit_inst_len
;
10761 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10763 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10767 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10769 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10771 if (vcpu
->arch
.exception
.pending
||
10772 vcpu
->arch
.nmi_injected
||
10773 vcpu
->arch
.interrupt
.pending
)
10776 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10777 vmx
->nested
.preemption_timer_expired
) {
10778 if (vmx
->nested
.nested_run_pending
)
10780 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10784 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10785 if (vmx
->nested
.nested_run_pending
)
10787 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10788 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10789 INTR_INFO_VALID_MASK
, 0);
10791 * The NMI-triggered VM exit counts as injection:
10792 * clear this one and block further NMIs.
10794 vcpu
->arch
.nmi_pending
= 0;
10795 vmx_set_nmi_mask(vcpu
, true);
10799 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10800 nested_exit_on_intr(vcpu
)) {
10801 if (vmx
->nested
.nested_run_pending
)
10803 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10807 vmx_complete_nested_posted_interrupt(vcpu
);
10811 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10813 ktime_t remaining
=
10814 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10817 if (ktime_to_ns(remaining
) <= 0)
10820 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10821 do_div(value
, 1000000);
10822 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10826 * Update the guest state fields of vmcs12 to reflect changes that
10827 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10828 * VM-entry controls is also updated, since this is really a guest
10831 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10833 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10834 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10836 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10837 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10838 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10840 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10841 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10842 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10843 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10844 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10845 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10846 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10847 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10848 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10849 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10850 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10851 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10852 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10853 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10854 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10855 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10856 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10857 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10858 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10859 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10860 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10861 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10862 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10863 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10864 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10865 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10866 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10867 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10868 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10869 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10870 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10871 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10872 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10873 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10874 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10875 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10877 vmcs12
->guest_interruptibility_info
=
10878 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10879 vmcs12
->guest_pending_dbg_exceptions
=
10880 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10881 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10882 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10884 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10886 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10887 if (vmcs12
->vm_exit_controls
&
10888 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10889 vmcs12
->vmx_preemption_timer_value
=
10890 vmx_get_preemption_timer_value(vcpu
);
10891 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10895 * In some cases (usually, nested EPT), L2 is allowed to change its
10896 * own CR3 without exiting. If it has changed it, we must keep it.
10897 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10898 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10900 * Additionally, restore L2's PDPTR to vmcs12.
10903 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10904 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10905 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10906 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10907 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10910 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10912 if (nested_cpu_has_vid(vmcs12
))
10913 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10915 vmcs12
->vm_entry_controls
=
10916 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10917 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10919 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10920 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10921 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10924 /* TODO: These cannot have changed unless we have MSR bitmaps and
10925 * the relevant bit asks not to trap the change */
10926 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10927 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10928 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10929 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10930 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10931 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10932 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10933 if (kvm_mpx_supported())
10934 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10938 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10939 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10940 * and this function updates it to reflect the changes to the guest state while
10941 * L2 was running (and perhaps made some exits which were handled directly by L0
10942 * without going back to L1), and to reflect the exit reason.
10943 * Note that we do not have to copy here all VMCS fields, just those that
10944 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10945 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10946 * which already writes to vmcs12 directly.
10948 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10949 u32 exit_reason
, u32 exit_intr_info
,
10950 unsigned long exit_qualification
)
10952 /* update guest state fields: */
10953 sync_vmcs12(vcpu
, vmcs12
);
10955 /* update exit information fields: */
10957 vmcs12
->vm_exit_reason
= exit_reason
;
10958 vmcs12
->exit_qualification
= exit_qualification
;
10959 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10961 vmcs12
->idt_vectoring_info_field
= 0;
10962 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10963 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10965 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10966 vmcs12
->launch_state
= 1;
10968 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10969 * instead of reading the real value. */
10970 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10973 * Transfer the event that L0 or L1 may wanted to inject into
10974 * L2 to IDT_VECTORING_INFO_FIELD.
10976 vmcs12_save_pending_event(vcpu
, vmcs12
);
10980 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10981 * preserved above and would only end up incorrectly in L1.
10983 vcpu
->arch
.nmi_injected
= false;
10984 kvm_clear_exception_queue(vcpu
);
10985 kvm_clear_interrupt_queue(vcpu
);
10989 * A part of what we need to when the nested L2 guest exits and we want to
10990 * run its L1 parent, is to reset L1's guest state to the host state specified
10992 * This function is to be called not only on normal nested exit, but also on
10993 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10994 * Failures During or After Loading Guest State").
10995 * This function should be called when the active VMCS is L1's (vmcs01).
10997 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10998 struct vmcs12
*vmcs12
)
11000 struct kvm_segment seg
;
11001 u32 entry_failure_code
;
11003 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11004 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11005 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11006 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11008 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11009 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11011 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11012 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11013 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11015 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11016 * actually changed, because vmx_set_cr0 refers to efer set above.
11018 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11019 * (KVM doesn't change it);
11021 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11022 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11024 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11025 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11026 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11028 nested_ept_uninit_mmu_context(vcpu
);
11031 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11032 * couldn't have changed.
11034 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11035 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11038 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11042 * Trivially support vpid by letting L2s share their parent
11043 * L1's vpid. TODO: move to a more elaborate solution, giving
11044 * each L2 its own vpid and exposing the vpid feature to L1.
11046 vmx_flush_tlb(vcpu
);
11048 /* Restore posted intr vector. */
11049 if (nested_cpu_has_posted_intr(vmcs12
))
11050 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11052 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11053 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11054 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11055 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11056 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11058 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11059 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11060 vmcs_write64(GUEST_BNDCFGS
, 0);
11062 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11063 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11064 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11066 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11067 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11068 vmcs12
->host_ia32_perf_global_ctrl
);
11070 /* Set L1 segment info according to Intel SDM
11071 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11072 seg
= (struct kvm_segment
) {
11074 .limit
= 0xFFFFFFFF,
11075 .selector
= vmcs12
->host_cs_selector
,
11081 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11085 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11086 seg
= (struct kvm_segment
) {
11088 .limit
= 0xFFFFFFFF,
11095 seg
.selector
= vmcs12
->host_ds_selector
;
11096 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11097 seg
.selector
= vmcs12
->host_es_selector
;
11098 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11099 seg
.selector
= vmcs12
->host_ss_selector
;
11100 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11101 seg
.selector
= vmcs12
->host_fs_selector
;
11102 seg
.base
= vmcs12
->host_fs_base
;
11103 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11104 seg
.selector
= vmcs12
->host_gs_selector
;
11105 seg
.base
= vmcs12
->host_gs_base
;
11106 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11107 seg
= (struct kvm_segment
) {
11108 .base
= vmcs12
->host_tr_base
,
11110 .selector
= vmcs12
->host_tr_selector
,
11114 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11116 kvm_set_dr(vcpu
, 7, 0x400);
11117 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11119 if (cpu_has_vmx_msr_bitmap())
11120 vmx_set_msr_bitmap(vcpu
);
11122 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11123 vmcs12
->vm_exit_msr_load_count
))
11124 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11128 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11129 * and modify vmcs12 to make it see what it would expect to see there if
11130 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11132 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11133 u32 exit_intr_info
,
11134 unsigned long exit_qualification
)
11136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11137 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11138 u32 vm_inst_error
= 0;
11140 /* trying to cancel vmlaunch/vmresume is a bug */
11141 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11143 leave_guest_mode(vcpu
);
11144 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11145 exit_qualification
);
11147 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11148 vmcs12
->vm_exit_msr_store_count
))
11149 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11151 if (unlikely(vmx
->fail
))
11152 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11154 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11157 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11158 * the VM-exit interrupt information (valid interrupt) is always set to
11159 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11160 * kvm_cpu_has_interrupt(). See the commit message for details.
11162 if (nested_exit_intr_ack_set(vcpu
) &&
11163 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11164 kvm_cpu_has_interrupt(vcpu
)) {
11165 int irq
= kvm_cpu_get_interrupt(vcpu
);
11167 vmcs12
->vm_exit_intr_info
= irq
|
11168 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11171 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11172 vmcs12
->exit_qualification
,
11173 vmcs12
->idt_vectoring_info_field
,
11174 vmcs12
->vm_exit_intr_info
,
11175 vmcs12
->vm_exit_intr_error_code
,
11178 vm_entry_controls_reset_shadow(vmx
);
11179 vm_exit_controls_reset_shadow(vmx
);
11180 vmx_segment_cache_clear(vmx
);
11182 /* if no vmcs02 cache requested, remove the one we used */
11183 if (VMCS02_POOL_SIZE
== 0)
11184 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11186 load_vmcs12_host_state(vcpu
, vmcs12
);
11188 /* Update any VMCS fields that might have changed while L2 ran */
11189 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11190 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11191 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11192 if (vmx
->hv_deadline_tsc
== -1)
11193 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11194 PIN_BASED_VMX_PREEMPTION_TIMER
);
11196 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11197 PIN_BASED_VMX_PREEMPTION_TIMER
);
11198 if (kvm_has_tsc_control
)
11199 decache_tsc_multiplier(vmx
);
11201 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11202 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11203 vmx_set_virtual_x2apic_mode(vcpu
,
11204 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11205 } else if (!nested_cpu_has_ept(vmcs12
) &&
11206 nested_cpu_has2(vmcs12
,
11207 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11208 vmx_flush_tlb_ept_only(vcpu
);
11211 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11214 /* Unpin physical memory we referred to in vmcs02 */
11215 if (vmx
->nested
.apic_access_page
) {
11216 nested_release_page(vmx
->nested
.apic_access_page
);
11217 vmx
->nested
.apic_access_page
= NULL
;
11219 if (vmx
->nested
.virtual_apic_page
) {
11220 nested_release_page(vmx
->nested
.virtual_apic_page
);
11221 vmx
->nested
.virtual_apic_page
= NULL
;
11223 if (vmx
->nested
.pi_desc_page
) {
11224 kunmap(vmx
->nested
.pi_desc_page
);
11225 nested_release_page(vmx
->nested
.pi_desc_page
);
11226 vmx
->nested
.pi_desc_page
= NULL
;
11227 vmx
->nested
.pi_desc
= NULL
;
11231 * We are now running in L2, mmu_notifier will force to reload the
11232 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11234 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11237 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11238 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11239 * success or failure flag accordingly.
11241 if (unlikely(vmx
->fail
)) {
11243 nested_vmx_failValid(vcpu
, vm_inst_error
);
11245 nested_vmx_succeed(vcpu
);
11246 if (enable_shadow_vmcs
)
11247 vmx
->nested
.sync_shadow_vmcs
= true;
11249 /* in case we halted in L2 */
11250 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11254 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11256 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11258 if (is_guest_mode(vcpu
)) {
11259 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11260 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11262 free_nested(to_vmx(vcpu
));
11266 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11267 * 23.7 "VM-entry failures during or after loading guest state" (this also
11268 * lists the acceptable exit-reason and exit-qualification parameters).
11269 * It should only be called before L2 actually succeeded to run, and when
11270 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11272 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11273 struct vmcs12
*vmcs12
,
11274 u32 reason
, unsigned long qualification
)
11276 load_vmcs12_host_state(vcpu
, vmcs12
);
11277 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11278 vmcs12
->exit_qualification
= qualification
;
11279 nested_vmx_succeed(vcpu
);
11280 if (enable_shadow_vmcs
)
11281 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11284 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11285 struct x86_instruction_info
*info
,
11286 enum x86_intercept_stage stage
)
11288 return X86EMUL_CONTINUE
;
11291 #ifdef CONFIG_X86_64
11292 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11293 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11294 u64 divisor
, u64
*result
)
11296 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11298 /* To avoid the overflow on divq */
11299 if (high
>= divisor
)
11302 /* Low hold the result, high hold rem which is discarded */
11303 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11304 "rm" (divisor
), "0" (low
), "1" (high
));
11310 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11312 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11313 u64 tscl
= rdtsc();
11314 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11315 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11317 /* Convert to host delta tsc if tsc scaling is enabled */
11318 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11319 u64_shl_div_u64(delta_tsc
,
11320 kvm_tsc_scaling_ratio_frac_bits
,
11321 vcpu
->arch
.tsc_scaling_ratio
,
11326 * If the delta tsc can't fit in the 32 bit after the multi shift,
11327 * we can't use the preemption timer.
11328 * It's possible that it fits on later vmentries, but checking
11329 * on every vmentry is costly so we just use an hrtimer.
11331 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11334 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11335 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11336 PIN_BASED_VMX_PREEMPTION_TIMER
);
11338 return delta_tsc
== 0;
11341 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11343 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11344 vmx
->hv_deadline_tsc
= -1;
11345 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11346 PIN_BASED_VMX_PREEMPTION_TIMER
);
11350 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11353 shrink_ple_window(vcpu
);
11356 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11357 struct kvm_memory_slot
*slot
)
11359 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11360 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11363 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11364 struct kvm_memory_slot
*slot
)
11366 kvm_mmu_slot_set_dirty(kvm
, slot
);
11369 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11371 kvm_flush_pml_buffers(kvm
);
11374 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11376 struct vmcs12
*vmcs12
;
11377 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11379 struct page
*page
= NULL
;
11382 if (is_guest_mode(vcpu
)) {
11383 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11386 * Check if PML is enabled for the nested guest.
11387 * Whether eptp bit 6 is set is already checked
11388 * as part of A/D emulation.
11390 vmcs12
= get_vmcs12(vcpu
);
11391 if (!nested_cpu_has_pml(vmcs12
))
11394 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11395 vmx
->nested
.pml_full
= true;
11399 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11401 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11405 pml_address
= kmap(page
);
11406 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11408 nested_release_page_clean(page
);
11414 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11415 struct kvm_memory_slot
*memslot
,
11416 gfn_t offset
, unsigned long mask
)
11418 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11421 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11423 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11424 struct pi_desc old
, new;
11428 old
.control
= new.control
= pi_desc
->control
;
11429 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11430 "Wakeup handler not enabled while the VCPU is blocked\n");
11432 dest
= cpu_physical_id(vcpu
->cpu
);
11434 if (x2apic_enabled())
11437 new.ndst
= (dest
<< 8) & 0xFF00;
11439 /* set 'NV' to 'notification vector' */
11440 new.nv
= POSTED_INTR_VECTOR
;
11441 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11442 new.control
) != old
.control
);
11444 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11445 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11446 list_del(&vcpu
->blocked_vcpu_list
);
11447 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11448 vcpu
->pre_pcpu
= -1;
11453 * This routine does the following things for vCPU which is going
11454 * to be blocked if VT-d PI is enabled.
11455 * - Store the vCPU to the wakeup list, so when interrupts happen
11456 * we can find the right vCPU to wake up.
11457 * - Change the Posted-interrupt descriptor as below:
11458 * 'NDST' <-- vcpu->pre_pcpu
11459 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11460 * - If 'ON' is set during this process, which means at least one
11461 * interrupt is posted for this vCPU, we cannot block it, in
11462 * this case, return 1, otherwise, return 0.
11465 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11468 struct pi_desc old
, new;
11469 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11471 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11472 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11473 !kvm_vcpu_apicv_active(vcpu
))
11476 WARN_ON(irqs_disabled());
11477 local_irq_disable();
11478 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11479 vcpu
->pre_pcpu
= vcpu
->cpu
;
11480 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11481 list_add_tail(&vcpu
->blocked_vcpu_list
,
11482 &per_cpu(blocked_vcpu_on_cpu
,
11484 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11488 old
.control
= new.control
= pi_desc
->control
;
11490 WARN((pi_desc
->sn
== 1),
11491 "Warning: SN field of posted-interrupts "
11492 "is set before blocking\n");
11495 * Since vCPU can be preempted during this process,
11496 * vcpu->cpu could be different with pre_pcpu, we
11497 * need to set pre_pcpu as the destination of wakeup
11498 * notification event, then we can find the right vCPU
11499 * to wakeup in wakeup handler if interrupts happen
11500 * when the vCPU is in blocked state.
11502 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11504 if (x2apic_enabled())
11507 new.ndst
= (dest
<< 8) & 0xFF00;
11509 /* set 'NV' to 'wakeup vector' */
11510 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11511 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11512 new.control
) != old
.control
);
11514 /* We should not block the vCPU if an interrupt is posted for it. */
11515 if (pi_test_on(pi_desc
) == 1)
11516 __pi_post_block(vcpu
);
11518 local_irq_enable();
11519 return (vcpu
->pre_pcpu
== -1);
11522 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11524 if (pi_pre_block(vcpu
))
11527 if (kvm_lapic_hv_timer_in_use(vcpu
))
11528 kvm_lapic_switch_to_sw_timer(vcpu
);
11533 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11535 if (vcpu
->pre_pcpu
== -1)
11538 WARN_ON(irqs_disabled());
11539 local_irq_disable();
11540 __pi_post_block(vcpu
);
11541 local_irq_enable();
11544 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11546 if (kvm_x86_ops
->set_hv_timer
)
11547 kvm_lapic_switch_to_hv_timer(vcpu
);
11549 pi_post_block(vcpu
);
11553 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11556 * @host_irq: host irq of the interrupt
11557 * @guest_irq: gsi of the interrupt
11558 * @set: set or unset PI
11559 * returns 0 on success, < 0 on failure
11561 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11562 uint32_t guest_irq
, bool set
)
11564 struct kvm_kernel_irq_routing_entry
*e
;
11565 struct kvm_irq_routing_table
*irq_rt
;
11566 struct kvm_lapic_irq irq
;
11567 struct kvm_vcpu
*vcpu
;
11568 struct vcpu_data vcpu_info
;
11571 if (!kvm_arch_has_assigned_device(kvm
) ||
11572 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11573 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11576 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11577 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11578 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11579 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11580 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11581 guest_irq
, irq_rt
->nr_rt_entries
);
11585 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11586 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11589 * VT-d PI cannot support posting multicast/broadcast
11590 * interrupts to a vCPU, we still use interrupt remapping
11591 * for these kind of interrupts.
11593 * For lowest-priority interrupts, we only support
11594 * those with single CPU as the destination, e.g. user
11595 * configures the interrupts via /proc/irq or uses
11596 * irqbalance to make the interrupts single-CPU.
11598 * We will support full lowest-priority interrupt later.
11601 kvm_set_msi_irq(kvm
, e
, &irq
);
11602 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11604 * Make sure the IRTE is in remapped mode if
11605 * we don't handle it in posted mode.
11607 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11610 "failed to back to remapped mode, irq: %u\n",
11618 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11619 vcpu_info
.vector
= irq
.vector
;
11621 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11622 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11625 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11627 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11630 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11638 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11642 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11644 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11645 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11646 FEATURE_CONTROL_LMCE
;
11648 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11649 ~FEATURE_CONTROL_LMCE
;
11652 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11653 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11654 .disabled_by_bios
= vmx_disabled_by_bios
,
11655 .hardware_setup
= hardware_setup
,
11656 .hardware_unsetup
= hardware_unsetup
,
11657 .check_processor_compatibility
= vmx_check_processor_compat
,
11658 .hardware_enable
= hardware_enable
,
11659 .hardware_disable
= hardware_disable
,
11660 .cpu_has_accelerated_tpr
= report_flexpriority
,
11661 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11663 .vcpu_create
= vmx_create_vcpu
,
11664 .vcpu_free
= vmx_free_vcpu
,
11665 .vcpu_reset
= vmx_vcpu_reset
,
11667 .prepare_guest_switch
= vmx_save_host_state
,
11668 .vcpu_load
= vmx_vcpu_load
,
11669 .vcpu_put
= vmx_vcpu_put
,
11671 .update_bp_intercept
= update_exception_bitmap
,
11672 .get_msr
= vmx_get_msr
,
11673 .set_msr
= vmx_set_msr
,
11674 .get_segment_base
= vmx_get_segment_base
,
11675 .get_segment
= vmx_get_segment
,
11676 .set_segment
= vmx_set_segment
,
11677 .get_cpl
= vmx_get_cpl
,
11678 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11679 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11680 .decache_cr3
= vmx_decache_cr3
,
11681 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11682 .set_cr0
= vmx_set_cr0
,
11683 .set_cr3
= vmx_set_cr3
,
11684 .set_cr4
= vmx_set_cr4
,
11685 .set_efer
= vmx_set_efer
,
11686 .get_idt
= vmx_get_idt
,
11687 .set_idt
= vmx_set_idt
,
11688 .get_gdt
= vmx_get_gdt
,
11689 .set_gdt
= vmx_set_gdt
,
11690 .get_dr6
= vmx_get_dr6
,
11691 .set_dr6
= vmx_set_dr6
,
11692 .set_dr7
= vmx_set_dr7
,
11693 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11694 .cache_reg
= vmx_cache_reg
,
11695 .get_rflags
= vmx_get_rflags
,
11696 .set_rflags
= vmx_set_rflags
,
11698 .tlb_flush
= vmx_flush_tlb
,
11700 .run
= vmx_vcpu_run
,
11701 .handle_exit
= vmx_handle_exit
,
11702 .skip_emulated_instruction
= skip_emulated_instruction
,
11703 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11704 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11705 .patch_hypercall
= vmx_patch_hypercall
,
11706 .set_irq
= vmx_inject_irq
,
11707 .set_nmi
= vmx_inject_nmi
,
11708 .queue_exception
= vmx_queue_exception
,
11709 .cancel_injection
= vmx_cancel_injection
,
11710 .interrupt_allowed
= vmx_interrupt_allowed
,
11711 .nmi_allowed
= vmx_nmi_allowed
,
11712 .get_nmi_mask
= vmx_get_nmi_mask
,
11713 .set_nmi_mask
= vmx_set_nmi_mask
,
11714 .enable_nmi_window
= enable_nmi_window
,
11715 .enable_irq_window
= enable_irq_window
,
11716 .update_cr8_intercept
= update_cr8_intercept
,
11717 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11718 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11719 .get_enable_apicv
= vmx_get_enable_apicv
,
11720 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11721 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11722 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11723 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11724 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11725 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11726 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11728 .set_tss_addr
= vmx_set_tss_addr
,
11729 .get_tdp_level
= get_ept_level
,
11730 .get_mt_mask
= vmx_get_mt_mask
,
11732 .get_exit_info
= vmx_get_exit_info
,
11734 .get_lpage_level
= vmx_get_lpage_level
,
11736 .cpuid_update
= vmx_cpuid_update
,
11738 .rdtscp_supported
= vmx_rdtscp_supported
,
11739 .invpcid_supported
= vmx_invpcid_supported
,
11741 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11743 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11745 .write_tsc_offset
= vmx_write_tsc_offset
,
11747 .set_tdp_cr3
= vmx_set_cr3
,
11749 .check_intercept
= vmx_check_intercept
,
11750 .handle_external_intr
= vmx_handle_external_intr
,
11751 .mpx_supported
= vmx_mpx_supported
,
11752 .xsaves_supported
= vmx_xsaves_supported
,
11754 .check_nested_events
= vmx_check_nested_events
,
11756 .sched_in
= vmx_sched_in
,
11758 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11759 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11760 .flush_log_dirty
= vmx_flush_log_dirty
,
11761 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11762 .write_log_dirty
= vmx_write_pml_buffer
,
11764 .pre_block
= vmx_pre_block
,
11765 .post_block
= vmx_post_block
,
11767 .pmu_ops
= &intel_pmu_ops
,
11769 .update_pi_irte
= vmx_update_pi_irte
,
11771 #ifdef CONFIG_X86_64
11772 .set_hv_timer
= vmx_set_hv_timer
,
11773 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11776 .setup_mce
= vmx_setup_mce
,
11779 static int __init
vmx_init(void)
11781 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11782 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11786 #ifdef CONFIG_KEXEC_CORE
11787 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11788 crash_vmclear_local_loaded_vmcss
);
11794 static void __exit
vmx_exit(void)
11796 #ifdef CONFIG_KEXEC_CORE
11797 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11804 module_init(vmx_init
)
11805 module_exit(vmx_exit
)