2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/nospec-branch.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 #define __ex_clear(x, reg) \
60 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62 MODULE_AUTHOR("Qumranet");
63 MODULE_LICENSE("GPL");
65 static const struct x86_cpu_id vmx_cpu_id
[] = {
66 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
69 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
71 static bool __read_mostly enable_vpid
= 1;
72 module_param_named(vpid
, enable_vpid
, bool, 0444);
74 static bool __read_mostly enable_vnmi
= 1;
75 module_param_named(vnmi
, enable_vnmi
, bool, S_IRUGO
);
77 static bool __read_mostly flexpriority_enabled
= 1;
78 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
80 static bool __read_mostly enable_ept
= 1;
81 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
83 static bool __read_mostly enable_unrestricted_guest
= 1;
84 module_param_named(unrestricted_guest
,
85 enable_unrestricted_guest
, bool, S_IRUGO
);
87 static bool __read_mostly enable_ept_ad_bits
= 1;
88 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
90 static bool __read_mostly emulate_invalid_guest_state
= true;
91 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
93 static bool __read_mostly fasteoi
= 1;
94 module_param(fasteoi
, bool, S_IRUGO
);
96 static bool __read_mostly enable_apicv
= 1;
97 module_param(enable_apicv
, bool, S_IRUGO
);
99 static bool __read_mostly enable_shadow_vmcs
= 1;
100 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
102 * If nested=1, nested virtualization is supported, i.e., guests may use
103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
104 * use VMX instructions.
106 static bool __read_mostly nested
= 0;
107 module_param(nested
, bool, S_IRUGO
);
109 static u64 __read_mostly host_xss
;
111 static bool __read_mostly enable_pml
= 1;
112 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
114 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
116 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
117 static int __read_mostly cpu_preemption_timer_multi
;
118 static bool __read_mostly enable_preemption_timer
= 1;
120 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
123 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
124 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
125 #define KVM_VM_CR0_ALWAYS_ON \
126 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
127 #define KVM_CR4_GUEST_OWNED_BITS \
128 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
129 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
131 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
132 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
134 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
136 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
139 * Hyper-V requires all of these, so mark them as supported even though
140 * they are just treated the same as all-context.
142 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
143 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
144 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
145 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
146 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
149 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
150 * ple_gap: upper bound on the amount of time between two successive
151 * executions of PAUSE in a loop. Also indicate if ple enabled.
152 * According to test, this time is usually smaller than 128 cycles.
153 * ple_window: upper bound on the amount of time a guest is allowed to execute
154 * in a PAUSE loop. Tests indicate that most spinlocks are held for
155 * less than 2^12 cycles
156 * Time is measured based on a counter that runs at the same rate as the TSC,
157 * refer SDM volume 3b section 21.6.13 & 22.1.3.
159 #define KVM_VMX_DEFAULT_PLE_GAP 128
160 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
161 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
162 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
163 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
164 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
166 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
167 module_param(ple_gap
, int, S_IRUGO
);
169 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
170 module_param(ple_window
, int, S_IRUGO
);
172 /* Default doubles per-vcpu window every exit. */
173 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
174 module_param(ple_window_grow
, int, S_IRUGO
);
176 /* Default resets per-vcpu window every exit to ple_window. */
177 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
178 module_param(ple_window_shrink
, int, S_IRUGO
);
180 /* Default is to compute the maximum so we can never overflow. */
181 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
182 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
183 module_param(ple_window_max
, int, S_IRUGO
);
185 extern const ulong vmx_return
;
187 #define NR_AUTOLOAD_MSRS 8
188 #define VMCS02_POOL_SIZE 1
197 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
198 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
199 * loaded on this CPU (so we can clear them if the CPU goes down).
203 struct vmcs
*shadow_vmcs
;
206 bool nmi_known_unmasked
;
207 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
208 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
209 /* Support for vnmi-less CPUs */
210 int soft_vnmi_blocked
;
212 s64 vnmi_blocked_time
;
213 struct list_head loaded_vmcss_on_cpu_link
;
216 struct shared_msr_entry
{
223 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
224 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
225 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
226 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
227 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
228 * More than one of these structures may exist, if L1 runs multiple L2 guests.
229 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
230 * underlying hardware which will be used to run L2.
231 * This structure is packed to ensure that its layout is identical across
232 * machines (necessary for live migration).
233 * If there are changes in this struct, VMCS12_REVISION must be changed.
235 typedef u64 natural_width
;
236 struct __packed vmcs12
{
237 /* According to the Intel spec, a VMCS region must start with the
238 * following two fields. Then follow implementation-specific data.
243 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
244 u32 padding
[7]; /* room for future expansion */
249 u64 vm_exit_msr_store_addr
;
250 u64 vm_exit_msr_load_addr
;
251 u64 vm_entry_msr_load_addr
;
253 u64 virtual_apic_page_addr
;
254 u64 apic_access_addr
;
255 u64 posted_intr_desc_addr
;
256 u64 vm_function_control
;
258 u64 eoi_exit_bitmap0
;
259 u64 eoi_exit_bitmap1
;
260 u64 eoi_exit_bitmap2
;
261 u64 eoi_exit_bitmap3
;
262 u64 eptp_list_address
;
264 u64 guest_physical_address
;
265 u64 vmcs_link_pointer
;
267 u64 guest_ia32_debugctl
;
270 u64 guest_ia32_perf_global_ctrl
;
278 u64 host_ia32_perf_global_ctrl
;
279 u64 padding64
[8]; /* room for future expansion */
281 * To allow migration of L1 (complete with its L2 guests) between
282 * machines of different natural widths (32 or 64 bit), we cannot have
283 * unsigned long fields with no explict size. We use u64 (aliased
284 * natural_width) instead. Luckily, x86 is little-endian.
286 natural_width cr0_guest_host_mask
;
287 natural_width cr4_guest_host_mask
;
288 natural_width cr0_read_shadow
;
289 natural_width cr4_read_shadow
;
290 natural_width cr3_target_value0
;
291 natural_width cr3_target_value1
;
292 natural_width cr3_target_value2
;
293 natural_width cr3_target_value3
;
294 natural_width exit_qualification
;
295 natural_width guest_linear_address
;
296 natural_width guest_cr0
;
297 natural_width guest_cr3
;
298 natural_width guest_cr4
;
299 natural_width guest_es_base
;
300 natural_width guest_cs_base
;
301 natural_width guest_ss_base
;
302 natural_width guest_ds_base
;
303 natural_width guest_fs_base
;
304 natural_width guest_gs_base
;
305 natural_width guest_ldtr_base
;
306 natural_width guest_tr_base
;
307 natural_width guest_gdtr_base
;
308 natural_width guest_idtr_base
;
309 natural_width guest_dr7
;
310 natural_width guest_rsp
;
311 natural_width guest_rip
;
312 natural_width guest_rflags
;
313 natural_width guest_pending_dbg_exceptions
;
314 natural_width guest_sysenter_esp
;
315 natural_width guest_sysenter_eip
;
316 natural_width host_cr0
;
317 natural_width host_cr3
;
318 natural_width host_cr4
;
319 natural_width host_fs_base
;
320 natural_width host_gs_base
;
321 natural_width host_tr_base
;
322 natural_width host_gdtr_base
;
323 natural_width host_idtr_base
;
324 natural_width host_ia32_sysenter_esp
;
325 natural_width host_ia32_sysenter_eip
;
326 natural_width host_rsp
;
327 natural_width host_rip
;
328 natural_width paddingl
[8]; /* room for future expansion */
329 u32 pin_based_vm_exec_control
;
330 u32 cpu_based_vm_exec_control
;
331 u32 exception_bitmap
;
332 u32 page_fault_error_code_mask
;
333 u32 page_fault_error_code_match
;
334 u32 cr3_target_count
;
335 u32 vm_exit_controls
;
336 u32 vm_exit_msr_store_count
;
337 u32 vm_exit_msr_load_count
;
338 u32 vm_entry_controls
;
339 u32 vm_entry_msr_load_count
;
340 u32 vm_entry_intr_info_field
;
341 u32 vm_entry_exception_error_code
;
342 u32 vm_entry_instruction_len
;
344 u32 secondary_vm_exec_control
;
345 u32 vm_instruction_error
;
347 u32 vm_exit_intr_info
;
348 u32 vm_exit_intr_error_code
;
349 u32 idt_vectoring_info_field
;
350 u32 idt_vectoring_error_code
;
351 u32 vm_exit_instruction_len
;
352 u32 vmx_instruction_info
;
359 u32 guest_ldtr_limit
;
361 u32 guest_gdtr_limit
;
362 u32 guest_idtr_limit
;
363 u32 guest_es_ar_bytes
;
364 u32 guest_cs_ar_bytes
;
365 u32 guest_ss_ar_bytes
;
366 u32 guest_ds_ar_bytes
;
367 u32 guest_fs_ar_bytes
;
368 u32 guest_gs_ar_bytes
;
369 u32 guest_ldtr_ar_bytes
;
370 u32 guest_tr_ar_bytes
;
371 u32 guest_interruptibility_info
;
372 u32 guest_activity_state
;
373 u32 guest_sysenter_cs
;
374 u32 host_ia32_sysenter_cs
;
375 u32 vmx_preemption_timer_value
;
376 u32 padding32
[7]; /* room for future expansion */
377 u16 virtual_processor_id
;
379 u16 guest_es_selector
;
380 u16 guest_cs_selector
;
381 u16 guest_ss_selector
;
382 u16 guest_ds_selector
;
383 u16 guest_fs_selector
;
384 u16 guest_gs_selector
;
385 u16 guest_ldtr_selector
;
386 u16 guest_tr_selector
;
387 u16 guest_intr_status
;
389 u16 host_es_selector
;
390 u16 host_cs_selector
;
391 u16 host_ss_selector
;
392 u16 host_ds_selector
;
393 u16 host_fs_selector
;
394 u16 host_gs_selector
;
395 u16 host_tr_selector
;
399 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
400 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
401 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
403 #define VMCS12_REVISION 0x11e57ed0
406 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
407 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
408 * current implementation, 4K are reserved to avoid future complications.
410 #define VMCS12_SIZE 0x1000
412 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
414 struct list_head list
;
416 struct loaded_vmcs vmcs02
;
420 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
421 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
424 /* Has the level1 guest done vmxon? */
429 /* The guest-physical address of the current VMCS L1 keeps for L2 */
432 * Cache of the guest's VMCS, existing outside of guest memory.
433 * Loaded from guest memory during VMPTRLD. Flushed to guest
434 * memory during VMCLEAR and VMPTRLD.
436 struct vmcs12
*cached_vmcs12
;
438 * Indicates if the shadow vmcs must be updated with the
439 * data hold by vmcs12
441 bool sync_shadow_vmcs
;
443 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
444 struct list_head vmcs02_pool
;
446 bool change_vmcs01_virtual_x2apic_mode
;
447 /* L2 must run next, and mustn't decide to exit to L1. */
448 bool nested_run_pending
;
450 * Guest pages referred to in vmcs02 with host-physical pointers, so
451 * we must keep them pinned while L2 runs.
453 struct page
*apic_access_page
;
454 struct page
*virtual_apic_page
;
455 struct page
*pi_desc_page
;
456 struct pi_desc
*pi_desc
;
460 unsigned long *msr_bitmap
;
462 struct hrtimer preemption_timer
;
463 bool preemption_timer_expired
;
465 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
472 * We only store the "true" versions of the VMX capability MSRs. We
473 * generate the "non-true" versions by setting the must-be-1 bits
474 * according to the SDM.
476 u32 nested_vmx_procbased_ctls_low
;
477 u32 nested_vmx_procbased_ctls_high
;
478 u32 nested_vmx_secondary_ctls_low
;
479 u32 nested_vmx_secondary_ctls_high
;
480 u32 nested_vmx_pinbased_ctls_low
;
481 u32 nested_vmx_pinbased_ctls_high
;
482 u32 nested_vmx_exit_ctls_low
;
483 u32 nested_vmx_exit_ctls_high
;
484 u32 nested_vmx_entry_ctls_low
;
485 u32 nested_vmx_entry_ctls_high
;
486 u32 nested_vmx_misc_low
;
487 u32 nested_vmx_misc_high
;
488 u32 nested_vmx_ept_caps
;
489 u32 nested_vmx_vpid_caps
;
490 u64 nested_vmx_basic
;
491 u64 nested_vmx_cr0_fixed0
;
492 u64 nested_vmx_cr0_fixed1
;
493 u64 nested_vmx_cr4_fixed0
;
494 u64 nested_vmx_cr4_fixed1
;
495 u64 nested_vmx_vmcs_enum
;
496 u64 nested_vmx_vmfunc_controls
;
498 /* SMM related state */
500 /* in VMX operation on SMM entry? */
502 /* in guest mode on SMM entry? */
507 #define POSTED_INTR_ON 0
508 #define POSTED_INTR_SN 1
510 /* Posted-Interrupt Descriptor */
512 u32 pir
[8]; /* Posted interrupt requested */
515 /* bit 256 - Outstanding Notification */
517 /* bit 257 - Suppress Notification */
519 /* bit 271:258 - Reserved */
521 /* bit 279:272 - Notification Vector */
523 /* bit 287:280 - Reserved */
525 /* bit 319:288 - Notification Destination */
533 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
535 return test_and_set_bit(POSTED_INTR_ON
,
536 (unsigned long *)&pi_desc
->control
);
539 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
541 return test_and_clear_bit(POSTED_INTR_ON
,
542 (unsigned long *)&pi_desc
->control
);
545 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
547 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
550 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
552 return clear_bit(POSTED_INTR_SN
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
558 return set_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
562 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
564 clear_bit(POSTED_INTR_ON
,
565 (unsigned long *)&pi_desc
->control
);
568 static inline int pi_test_on(struct pi_desc
*pi_desc
)
570 return test_bit(POSTED_INTR_ON
,
571 (unsigned long *)&pi_desc
->control
);
574 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
576 return test_bit(POSTED_INTR_SN
,
577 (unsigned long *)&pi_desc
->control
);
581 struct kvm_vcpu vcpu
;
582 unsigned long host_rsp
;
585 u32 idt_vectoring_info
;
587 struct shared_msr_entry
*guest_msrs
;
590 unsigned long host_idt_base
;
592 u64 msr_host_kernel_gs_base
;
593 u64 msr_guest_kernel_gs_base
;
595 u32 vm_entry_controls_shadow
;
596 u32 vm_exit_controls_shadow
;
597 u32 secondary_exec_control
;
600 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
601 * non-nested (L1) guest, it always points to vmcs01. For a nested
602 * guest (L2), it points to a different VMCS.
604 struct loaded_vmcs vmcs01
;
605 struct loaded_vmcs
*loaded_vmcs
;
606 bool __launched
; /* temporary, used in vmx_vcpu_run */
607 struct msr_autoload
{
609 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
610 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
614 u16 fs_sel
, gs_sel
, ldt_sel
;
618 int gs_ldt_reload_needed
;
619 int fs_reload_needed
;
620 u64 msr_host_bndcfgs
;
625 struct kvm_segment segs
[8];
628 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
629 struct kvm_save_segment
{
637 bool emulation_required
;
641 /* Posted interrupt descriptor */
642 struct pi_desc pi_desc
;
644 /* Support for a guest hypervisor (nested VMX) */
645 struct nested_vmx nested
;
647 /* Dynamic PLE window. */
649 bool ple_window_dirty
;
651 /* Support for PML */
652 #define PML_ENTITY_NUM 512
655 /* apic deadline value in host tsc */
658 u64 current_tsc_ratio
;
663 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
664 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
665 * in msr_ia32_feature_control_valid_bits.
667 u64 msr_ia32_feature_control
;
668 u64 msr_ia32_feature_control_valid_bits
;
671 enum segment_cache_field
{
680 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
682 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
685 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
687 return &(to_vmx(vcpu
)->pi_desc
);
690 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
691 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
692 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
693 [number##_HIGH] = VMCS12_OFFSET(name)+4
696 static unsigned long shadow_read_only_fields
[] = {
698 * We do NOT shadow fields that are modified when L0
699 * traps and emulates any vmx instruction (e.g. VMPTRLD,
700 * VMXON...) executed by L1.
701 * For example, VM_INSTRUCTION_ERROR is read
702 * by L1 if a vmx instruction fails (part of the error path).
703 * Note the code assumes this logic. If for some reason
704 * we start shadowing these fields then we need to
705 * force a shadow sync when L0 emulates vmx instructions
706 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
707 * by nested_vmx_failValid)
711 VM_EXIT_INSTRUCTION_LEN
,
712 IDT_VECTORING_INFO_FIELD
,
713 IDT_VECTORING_ERROR_CODE
,
714 VM_EXIT_INTR_ERROR_CODE
,
716 GUEST_LINEAR_ADDRESS
,
717 GUEST_PHYSICAL_ADDRESS
719 static int max_shadow_read_only_fields
=
720 ARRAY_SIZE(shadow_read_only_fields
);
722 static unsigned long shadow_read_write_fields
[] = {
729 GUEST_INTERRUPTIBILITY_INFO
,
742 CPU_BASED_VM_EXEC_CONTROL
,
743 VM_ENTRY_EXCEPTION_ERROR_CODE
,
744 VM_ENTRY_INTR_INFO_FIELD
,
745 VM_ENTRY_INSTRUCTION_LEN
,
746 VM_ENTRY_EXCEPTION_ERROR_CODE
,
752 static int max_shadow_read_write_fields
=
753 ARRAY_SIZE(shadow_read_write_fields
);
755 static const unsigned short vmcs_field_to_offset_table
[] = {
756 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
757 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
758 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
759 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
760 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
761 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
762 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
763 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
764 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
765 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
766 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
767 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
768 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
769 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
770 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
771 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
772 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
773 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
774 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
775 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
776 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
777 FIELD64(MSR_BITMAP
, msr_bitmap
),
778 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
779 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
780 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
781 FIELD64(TSC_OFFSET
, tsc_offset
),
782 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
783 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
784 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
785 FIELD64(VM_FUNCTION_CONTROL
, vm_function_control
),
786 FIELD64(EPT_POINTER
, ept_pointer
),
787 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
788 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
789 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
790 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
791 FIELD64(EPTP_LIST_ADDRESS
, eptp_list_address
),
792 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
793 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
794 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
795 FIELD64(PML_ADDRESS
, pml_address
),
796 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
797 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
798 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
799 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
800 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
801 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
802 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
803 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
804 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
805 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
806 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
807 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
808 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
809 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
810 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
811 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
812 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
813 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
814 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
815 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
816 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
817 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
818 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
819 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
820 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
821 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
822 FIELD(TPR_THRESHOLD
, tpr_threshold
),
823 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
824 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
825 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
826 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
827 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
828 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
829 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
830 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
831 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
832 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
833 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
834 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
835 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
836 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
837 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
838 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
839 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
840 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
841 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
842 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
843 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
844 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
845 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
846 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
847 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
848 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
849 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
850 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
851 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
852 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
853 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
854 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
855 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
856 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
857 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
858 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
859 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
860 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
861 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
862 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
863 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
864 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
865 FIELD(GUEST_CR0
, guest_cr0
),
866 FIELD(GUEST_CR3
, guest_cr3
),
867 FIELD(GUEST_CR4
, guest_cr4
),
868 FIELD(GUEST_ES_BASE
, guest_es_base
),
869 FIELD(GUEST_CS_BASE
, guest_cs_base
),
870 FIELD(GUEST_SS_BASE
, guest_ss_base
),
871 FIELD(GUEST_DS_BASE
, guest_ds_base
),
872 FIELD(GUEST_FS_BASE
, guest_fs_base
),
873 FIELD(GUEST_GS_BASE
, guest_gs_base
),
874 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
875 FIELD(GUEST_TR_BASE
, guest_tr_base
),
876 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
877 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
878 FIELD(GUEST_DR7
, guest_dr7
),
879 FIELD(GUEST_RSP
, guest_rsp
),
880 FIELD(GUEST_RIP
, guest_rip
),
881 FIELD(GUEST_RFLAGS
, guest_rflags
),
882 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
883 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
884 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
885 FIELD(HOST_CR0
, host_cr0
),
886 FIELD(HOST_CR3
, host_cr3
),
887 FIELD(HOST_CR4
, host_cr4
),
888 FIELD(HOST_FS_BASE
, host_fs_base
),
889 FIELD(HOST_GS_BASE
, host_gs_base
),
890 FIELD(HOST_TR_BASE
, host_tr_base
),
891 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
892 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
893 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
894 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
895 FIELD(HOST_RSP
, host_rsp
),
896 FIELD(HOST_RIP
, host_rip
),
899 static inline short vmcs_field_to_offset(unsigned long field
)
901 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
903 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
))
907 * FIXME: Mitigation for CVE-2017-5753. To be replaced with a
912 if (vmcs_field_to_offset_table
[field
] == 0)
915 return vmcs_field_to_offset_table
[field
];
918 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
920 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
923 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
924 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
925 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
926 static bool vmx_xsaves_supported(void);
927 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
928 struct kvm_segment
*var
, int seg
);
929 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
930 struct kvm_segment
*var
, int seg
);
931 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
932 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
933 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
934 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
935 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
936 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
939 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
940 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
942 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
943 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
945 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
948 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
949 * can find which vCPU should be waken up.
951 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
952 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
957 VMX_MSR_BITMAP_LEGACY
,
958 VMX_MSR_BITMAP_LONGMODE
,
959 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
960 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
961 VMX_MSR_BITMAP_LEGACY_X2APIC
,
962 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
968 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
970 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
971 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
972 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
973 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
974 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
975 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
976 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
977 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
978 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
979 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
981 static bool cpu_has_load_ia32_efer
;
982 static bool cpu_has_load_perf_global_ctrl
;
984 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
985 static DEFINE_SPINLOCK(vmx_vpid_lock
);
987 static struct vmcs_config
{
992 u32 pin_based_exec_ctrl
;
993 u32 cpu_based_exec_ctrl
;
994 u32 cpu_based_2nd_exec_ctrl
;
999 static struct vmx_capability
{
1004 #define VMX_SEGMENT_FIELD(seg) \
1005 [VCPU_SREG_##seg] = { \
1006 .selector = GUEST_##seg##_SELECTOR, \
1007 .base = GUEST_##seg##_BASE, \
1008 .limit = GUEST_##seg##_LIMIT, \
1009 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1012 static const struct kvm_vmx_segment_field
{
1017 } kvm_vmx_segment_fields
[] = {
1018 VMX_SEGMENT_FIELD(CS
),
1019 VMX_SEGMENT_FIELD(DS
),
1020 VMX_SEGMENT_FIELD(ES
),
1021 VMX_SEGMENT_FIELD(FS
),
1022 VMX_SEGMENT_FIELD(GS
),
1023 VMX_SEGMENT_FIELD(SS
),
1024 VMX_SEGMENT_FIELD(TR
),
1025 VMX_SEGMENT_FIELD(LDTR
),
1028 static u64 host_efer
;
1030 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1033 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1034 * away by decrementing the array size.
1036 static const u32 vmx_msr_index
[] = {
1037 #ifdef CONFIG_X86_64
1038 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1040 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1043 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1045 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1046 INTR_INFO_VALID_MASK
)) ==
1047 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1050 static inline bool is_debug(u32 intr_info
)
1052 return is_exception_n(intr_info
, DB_VECTOR
);
1055 static inline bool is_breakpoint(u32 intr_info
)
1057 return is_exception_n(intr_info
, BP_VECTOR
);
1060 static inline bool is_page_fault(u32 intr_info
)
1062 return is_exception_n(intr_info
, PF_VECTOR
);
1065 static inline bool is_no_device(u32 intr_info
)
1067 return is_exception_n(intr_info
, NM_VECTOR
);
1070 static inline bool is_invalid_opcode(u32 intr_info
)
1072 return is_exception_n(intr_info
, UD_VECTOR
);
1075 static inline bool is_external_interrupt(u32 intr_info
)
1077 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1078 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1081 static inline bool is_machine_check(u32 intr_info
)
1083 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1084 INTR_INFO_VALID_MASK
)) ==
1085 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1088 static inline bool cpu_has_vmx_msr_bitmap(void)
1090 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1093 static inline bool cpu_has_vmx_tpr_shadow(void)
1095 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1098 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1100 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1103 static inline bool cpu_has_secondary_exec_ctrls(void)
1105 return vmcs_config
.cpu_based_exec_ctrl
&
1106 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1109 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1111 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1112 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1115 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1117 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1118 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1121 static inline bool cpu_has_vmx_apic_register_virt(void)
1123 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1124 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1127 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1129 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1130 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1134 * Comment's format: document - errata name - stepping - processor name.
1136 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1138 static u32 vmx_preemption_cpu_tfms
[] = {
1139 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1141 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1142 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1143 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1145 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1147 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1148 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1150 * 320767.pdf - AAP86 - B1 -
1151 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1154 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1156 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1158 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1160 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1161 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1162 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1166 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1168 u32 eax
= cpuid_eax(0x00000001), i
;
1170 /* Clear the reserved bits */
1171 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1172 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1173 if (eax
== vmx_preemption_cpu_tfms
[i
])
1179 static inline bool cpu_has_vmx_preemption_timer(void)
1181 return vmcs_config
.pin_based_exec_ctrl
&
1182 PIN_BASED_VMX_PREEMPTION_TIMER
;
1185 static inline bool cpu_has_vmx_posted_intr(void)
1187 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1188 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1191 static inline bool cpu_has_vmx_apicv(void)
1193 return cpu_has_vmx_apic_register_virt() &&
1194 cpu_has_vmx_virtual_intr_delivery() &&
1195 cpu_has_vmx_posted_intr();
1198 static inline bool cpu_has_vmx_flexpriority(void)
1200 return cpu_has_vmx_tpr_shadow() &&
1201 cpu_has_vmx_virtualize_apic_accesses();
1204 static inline bool cpu_has_vmx_ept_execute_only(void)
1206 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1209 static inline bool cpu_has_vmx_ept_2m_page(void)
1211 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1214 static inline bool cpu_has_vmx_ept_1g_page(void)
1216 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1219 static inline bool cpu_has_vmx_ept_4levels(void)
1221 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1224 static inline bool cpu_has_vmx_ept_mt_wb(void)
1226 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
1229 static inline bool cpu_has_vmx_ept_5levels(void)
1231 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_5_BIT
;
1234 static inline bool cpu_has_vmx_ept_ad_bits(void)
1236 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1239 static inline bool cpu_has_vmx_invept_context(void)
1241 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1244 static inline bool cpu_has_vmx_invept_global(void)
1246 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1249 static inline bool cpu_has_vmx_invvpid_single(void)
1251 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1254 static inline bool cpu_has_vmx_invvpid_global(void)
1256 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1259 static inline bool cpu_has_vmx_invvpid(void)
1261 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1264 static inline bool cpu_has_vmx_ept(void)
1266 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1267 SECONDARY_EXEC_ENABLE_EPT
;
1270 static inline bool cpu_has_vmx_unrestricted_guest(void)
1272 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1273 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1276 static inline bool cpu_has_vmx_ple(void)
1278 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1279 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1282 static inline bool cpu_has_vmx_basic_inout(void)
1284 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1287 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1289 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1292 static inline bool cpu_has_vmx_vpid(void)
1294 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1295 SECONDARY_EXEC_ENABLE_VPID
;
1298 static inline bool cpu_has_vmx_rdtscp(void)
1300 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1301 SECONDARY_EXEC_RDTSCP
;
1304 static inline bool cpu_has_vmx_invpcid(void)
1306 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1307 SECONDARY_EXEC_ENABLE_INVPCID
;
1310 static inline bool cpu_has_virtual_nmis(void)
1312 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1315 static inline bool cpu_has_vmx_wbinvd_exit(void)
1317 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1318 SECONDARY_EXEC_WBINVD_EXITING
;
1321 static inline bool cpu_has_vmx_shadow_vmcs(void)
1324 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1325 /* check if the cpu supports writing r/o exit information fields */
1326 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1329 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1330 SECONDARY_EXEC_SHADOW_VMCS
;
1333 static inline bool cpu_has_vmx_pml(void)
1335 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1338 static inline bool cpu_has_vmx_tsc_scaling(void)
1340 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1341 SECONDARY_EXEC_TSC_SCALING
;
1344 static inline bool cpu_has_vmx_vmfunc(void)
1346 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1347 SECONDARY_EXEC_ENABLE_VMFUNC
;
1350 static inline bool report_flexpriority(void)
1352 return flexpriority_enabled
;
1355 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1357 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1360 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1362 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1365 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1367 return (vmcs12
->cpu_based_vm_exec_control
&
1368 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1369 (vmcs12
->secondary_vm_exec_control
& bit
);
1372 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1374 return vmcs12
->pin_based_vm_exec_control
&
1375 PIN_BASED_VMX_PREEMPTION_TIMER
;
1378 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1380 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1383 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1385 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
1388 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1390 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1393 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1395 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1398 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1400 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1403 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1405 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1408 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1410 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1413 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1415 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1418 static inline bool nested_cpu_has_vmfunc(struct vmcs12
*vmcs12
)
1420 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VMFUNC
);
1423 static inline bool nested_cpu_has_eptp_switching(struct vmcs12
*vmcs12
)
1425 return nested_cpu_has_vmfunc(vmcs12
) &&
1426 (vmcs12
->vm_function_control
&
1427 VMX_VMFUNC_EPTP_SWITCHING
);
1430 static inline bool is_nmi(u32 intr_info
)
1432 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1433 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1436 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1438 unsigned long exit_qualification
);
1439 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1440 struct vmcs12
*vmcs12
,
1441 u32 reason
, unsigned long qualification
);
1443 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1447 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1448 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1453 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1459 } operand
= { vpid
, 0, gva
};
1461 asm volatile (__ex(ASM_VMX_INVVPID
)
1462 /* CF==1 or ZF==1 --> rc = -1 */
1463 "; ja 1f ; ud2 ; 1:"
1464 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1467 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1471 } operand
= {eptp
, gpa
};
1473 asm volatile (__ex(ASM_VMX_INVEPT
)
1474 /* CF==1 or ZF==1 --> rc = -1 */
1475 "; ja 1f ; ud2 ; 1:\n"
1476 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1479 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1483 i
= __find_msr_index(vmx
, msr
);
1485 return &vmx
->guest_msrs
[i
];
1489 static void vmcs_clear(struct vmcs
*vmcs
)
1491 u64 phys_addr
= __pa(vmcs
);
1494 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1495 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1498 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1502 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1504 vmcs_clear(loaded_vmcs
->vmcs
);
1505 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1506 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1507 loaded_vmcs
->cpu
= -1;
1508 loaded_vmcs
->launched
= 0;
1511 static void vmcs_load(struct vmcs
*vmcs
)
1513 u64 phys_addr
= __pa(vmcs
);
1516 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1517 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1520 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1524 #ifdef CONFIG_KEXEC_CORE
1526 * This bitmap is used to indicate whether the vmclear
1527 * operation is enabled on all cpus. All disabled by
1530 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1532 static inline void crash_enable_local_vmclear(int cpu
)
1534 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1537 static inline void crash_disable_local_vmclear(int cpu
)
1539 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1542 static inline int crash_local_vmclear_enabled(int cpu
)
1544 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1547 static void crash_vmclear_local_loaded_vmcss(void)
1549 int cpu
= raw_smp_processor_id();
1550 struct loaded_vmcs
*v
;
1552 if (!crash_local_vmclear_enabled(cpu
))
1555 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1556 loaded_vmcss_on_cpu_link
)
1557 vmcs_clear(v
->vmcs
);
1560 static inline void crash_enable_local_vmclear(int cpu
) { }
1561 static inline void crash_disable_local_vmclear(int cpu
) { }
1562 #endif /* CONFIG_KEXEC_CORE */
1564 static void __loaded_vmcs_clear(void *arg
)
1566 struct loaded_vmcs
*loaded_vmcs
= arg
;
1567 int cpu
= raw_smp_processor_id();
1569 if (loaded_vmcs
->cpu
!= cpu
)
1570 return; /* vcpu migration can race with cpu offline */
1571 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1572 per_cpu(current_vmcs
, cpu
) = NULL
;
1573 crash_disable_local_vmclear(cpu
);
1574 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1577 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1578 * is before setting loaded_vmcs->vcpu to -1 which is done in
1579 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1580 * then adds the vmcs into percpu list before it is deleted.
1584 loaded_vmcs_init(loaded_vmcs
);
1585 crash_enable_local_vmclear(cpu
);
1588 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1590 int cpu
= loaded_vmcs
->cpu
;
1593 smp_call_function_single(cpu
,
1594 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1597 static inline void vpid_sync_vcpu_single(int vpid
)
1602 if (cpu_has_vmx_invvpid_single())
1603 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1606 static inline void vpid_sync_vcpu_global(void)
1608 if (cpu_has_vmx_invvpid_global())
1609 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1612 static inline void vpid_sync_context(int vpid
)
1614 if (cpu_has_vmx_invvpid_single())
1615 vpid_sync_vcpu_single(vpid
);
1617 vpid_sync_vcpu_global();
1620 static inline void ept_sync_global(void)
1622 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1625 static inline void ept_sync_context(u64 eptp
)
1627 if (cpu_has_vmx_invept_context())
1628 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1633 static __always_inline
void vmcs_check16(unsigned long field
)
1635 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1636 "16-bit accessor invalid for 64-bit field");
1637 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1638 "16-bit accessor invalid for 64-bit high field");
1639 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1640 "16-bit accessor invalid for 32-bit high field");
1641 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1642 "16-bit accessor invalid for natural width field");
1645 static __always_inline
void vmcs_check32(unsigned long field
)
1647 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1648 "32-bit accessor invalid for 16-bit field");
1649 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1650 "32-bit accessor invalid for natural width field");
1653 static __always_inline
void vmcs_check64(unsigned long field
)
1655 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1656 "64-bit accessor invalid for 16-bit field");
1657 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1658 "64-bit accessor invalid for 64-bit high field");
1659 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1660 "64-bit accessor invalid for 32-bit field");
1661 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1662 "64-bit accessor invalid for natural width field");
1665 static __always_inline
void vmcs_checkl(unsigned long field
)
1667 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1668 "Natural width accessor invalid for 16-bit field");
1669 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1670 "Natural width accessor invalid for 64-bit field");
1671 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1672 "Natural width accessor invalid for 64-bit high field");
1673 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1674 "Natural width accessor invalid for 32-bit field");
1677 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1679 unsigned long value
;
1681 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1682 : "=a"(value
) : "d"(field
) : "cc");
1686 static __always_inline u16
vmcs_read16(unsigned long field
)
1688 vmcs_check16(field
);
1689 return __vmcs_readl(field
);
1692 static __always_inline u32
vmcs_read32(unsigned long field
)
1694 vmcs_check32(field
);
1695 return __vmcs_readl(field
);
1698 static __always_inline u64
vmcs_read64(unsigned long field
)
1700 vmcs_check64(field
);
1701 #ifdef CONFIG_X86_64
1702 return __vmcs_readl(field
);
1704 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1708 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1711 return __vmcs_readl(field
);
1714 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1716 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1717 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1721 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1725 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1726 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1727 if (unlikely(error
))
1728 vmwrite_error(field
, value
);
1731 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1733 vmcs_check16(field
);
1734 __vmcs_writel(field
, value
);
1737 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1739 vmcs_check32(field
);
1740 __vmcs_writel(field
, value
);
1743 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1745 vmcs_check64(field
);
1746 __vmcs_writel(field
, value
);
1747 #ifndef CONFIG_X86_64
1749 __vmcs_writel(field
+1, value
>> 32);
1753 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1756 __vmcs_writel(field
, value
);
1759 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1761 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1762 "vmcs_clear_bits does not support 64-bit fields");
1763 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1766 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1768 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1769 "vmcs_set_bits does not support 64-bit fields");
1770 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1773 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1775 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1778 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1780 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1781 vmx
->vm_entry_controls_shadow
= val
;
1784 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1786 if (vmx
->vm_entry_controls_shadow
!= val
)
1787 vm_entry_controls_init(vmx
, val
);
1790 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1792 return vmx
->vm_entry_controls_shadow
;
1796 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1798 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1801 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1803 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1806 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1808 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1811 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1813 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1814 vmx
->vm_exit_controls_shadow
= val
;
1817 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1819 if (vmx
->vm_exit_controls_shadow
!= val
)
1820 vm_exit_controls_init(vmx
, val
);
1823 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1825 return vmx
->vm_exit_controls_shadow
;
1829 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1831 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1834 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1836 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1839 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1841 vmx
->segment_cache
.bitmask
= 0;
1844 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1848 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1850 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1851 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1852 vmx
->segment_cache
.bitmask
= 0;
1854 ret
= vmx
->segment_cache
.bitmask
& mask
;
1855 vmx
->segment_cache
.bitmask
|= mask
;
1859 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1861 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1863 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1864 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1868 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1870 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1872 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1873 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1877 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1879 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1881 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1882 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1886 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1888 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1890 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1891 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1895 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1899 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1900 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1901 if ((vcpu
->guest_debug
&
1902 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1903 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1904 eb
|= 1u << BP_VECTOR
;
1905 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1908 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1910 /* When we are running a nested L2 guest and L1 specified for it a
1911 * certain exception bitmap, we must trap the same exceptions and pass
1912 * them to L1. When running L2, we will only handle the exceptions
1913 * specified above if L1 did not want them.
1915 if (is_guest_mode(vcpu
))
1916 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1918 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1921 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1922 unsigned long entry
, unsigned long exit
)
1924 vm_entry_controls_clearbit(vmx
, entry
);
1925 vm_exit_controls_clearbit(vmx
, exit
);
1928 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1931 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1935 if (cpu_has_load_ia32_efer
) {
1936 clear_atomic_switch_msr_special(vmx
,
1937 VM_ENTRY_LOAD_IA32_EFER
,
1938 VM_EXIT_LOAD_IA32_EFER
);
1942 case MSR_CORE_PERF_GLOBAL_CTRL
:
1943 if (cpu_has_load_perf_global_ctrl
) {
1944 clear_atomic_switch_msr_special(vmx
,
1945 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1946 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1952 for (i
= 0; i
< m
->nr
; ++i
)
1953 if (m
->guest
[i
].index
== msr
)
1959 m
->guest
[i
] = m
->guest
[m
->nr
];
1960 m
->host
[i
] = m
->host
[m
->nr
];
1961 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1962 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1965 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1966 unsigned long entry
, unsigned long exit
,
1967 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1968 u64 guest_val
, u64 host_val
)
1970 vmcs_write64(guest_val_vmcs
, guest_val
);
1971 vmcs_write64(host_val_vmcs
, host_val
);
1972 vm_entry_controls_setbit(vmx
, entry
);
1973 vm_exit_controls_setbit(vmx
, exit
);
1976 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1977 u64 guest_val
, u64 host_val
)
1980 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1984 if (cpu_has_load_ia32_efer
) {
1985 add_atomic_switch_msr_special(vmx
,
1986 VM_ENTRY_LOAD_IA32_EFER
,
1987 VM_EXIT_LOAD_IA32_EFER
,
1990 guest_val
, host_val
);
1994 case MSR_CORE_PERF_GLOBAL_CTRL
:
1995 if (cpu_has_load_perf_global_ctrl
) {
1996 add_atomic_switch_msr_special(vmx
,
1997 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1998 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1999 GUEST_IA32_PERF_GLOBAL_CTRL
,
2000 HOST_IA32_PERF_GLOBAL_CTRL
,
2001 guest_val
, host_val
);
2005 case MSR_IA32_PEBS_ENABLE
:
2006 /* PEBS needs a quiescent period after being disabled (to write
2007 * a record). Disabling PEBS through VMX MSR swapping doesn't
2008 * provide that period, so a CPU could write host's record into
2011 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
2014 for (i
= 0; i
< m
->nr
; ++i
)
2015 if (m
->guest
[i
].index
== msr
)
2018 if (i
== NR_AUTOLOAD_MSRS
) {
2019 printk_once(KERN_WARNING
"Not enough msr switch entries. "
2020 "Can't add msr %x\n", msr
);
2022 } else if (i
== m
->nr
) {
2024 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
2025 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
2028 m
->guest
[i
].index
= msr
;
2029 m
->guest
[i
].value
= guest_val
;
2030 m
->host
[i
].index
= msr
;
2031 m
->host
[i
].value
= host_val
;
2034 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2036 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2037 u64 ignore_bits
= 0;
2041 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2042 * host CPUID is more efficient than testing guest CPUID
2043 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2045 if (boot_cpu_has(X86_FEATURE_SMEP
))
2046 guest_efer
|= EFER_NX
;
2047 else if (!(guest_efer
& EFER_NX
))
2048 ignore_bits
|= EFER_NX
;
2052 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2054 ignore_bits
|= EFER_SCE
;
2055 #ifdef CONFIG_X86_64
2056 ignore_bits
|= EFER_LMA
| EFER_LME
;
2057 /* SCE is meaningful only in long mode on Intel */
2058 if (guest_efer
& EFER_LMA
)
2059 ignore_bits
&= ~(u64
)EFER_SCE
;
2062 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2065 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2066 * On CPUs that support "load IA32_EFER", always switch EFER
2067 * atomically, since it's faster than switching it manually.
2069 if (cpu_has_load_ia32_efer
||
2070 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2071 if (!(guest_efer
& EFER_LMA
))
2072 guest_efer
&= ~EFER_LME
;
2073 if (guest_efer
!= host_efer
)
2074 add_atomic_switch_msr(vmx
, MSR_EFER
,
2075 guest_efer
, host_efer
);
2078 guest_efer
&= ~ignore_bits
;
2079 guest_efer
|= host_efer
& ignore_bits
;
2081 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2082 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2088 #ifdef CONFIG_X86_32
2090 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2091 * VMCS rather than the segment table. KVM uses this helper to figure
2092 * out the current bases to poke them into the VMCS before entry.
2094 static unsigned long segment_base(u16 selector
)
2096 struct desc_struct
*table
;
2099 if (!(selector
& ~SEGMENT_RPL_MASK
))
2102 table
= get_current_gdt_ro();
2104 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2105 u16 ldt_selector
= kvm_read_ldt();
2107 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2110 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2112 v
= get_desc_base(&table
[selector
>> 3]);
2117 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2119 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2122 if (vmx
->host_state
.loaded
)
2125 vmx
->host_state
.loaded
= 1;
2127 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2128 * allow segment selectors with cpl > 0 or ti == 1.
2130 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2131 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2132 savesegment(fs
, vmx
->host_state
.fs_sel
);
2133 if (!(vmx
->host_state
.fs_sel
& 7)) {
2134 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2135 vmx
->host_state
.fs_reload_needed
= 0;
2137 vmcs_write16(HOST_FS_SELECTOR
, 0);
2138 vmx
->host_state
.fs_reload_needed
= 1;
2140 savesegment(gs
, vmx
->host_state
.gs_sel
);
2141 if (!(vmx
->host_state
.gs_sel
& 7))
2142 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2144 vmcs_write16(HOST_GS_SELECTOR
, 0);
2145 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2148 #ifdef CONFIG_X86_64
2149 savesegment(ds
, vmx
->host_state
.ds_sel
);
2150 savesegment(es
, vmx
->host_state
.es_sel
);
2153 #ifdef CONFIG_X86_64
2154 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2155 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2157 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2158 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2161 #ifdef CONFIG_X86_64
2162 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2163 if (is_long_mode(&vmx
->vcpu
))
2164 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2166 if (boot_cpu_has(X86_FEATURE_MPX
))
2167 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2168 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2169 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2170 vmx
->guest_msrs
[i
].data
,
2171 vmx
->guest_msrs
[i
].mask
);
2174 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2176 if (!vmx
->host_state
.loaded
)
2179 ++vmx
->vcpu
.stat
.host_state_reload
;
2180 vmx
->host_state
.loaded
= 0;
2181 #ifdef CONFIG_X86_64
2182 if (is_long_mode(&vmx
->vcpu
))
2183 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2185 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2186 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2187 #ifdef CONFIG_X86_64
2188 load_gs_index(vmx
->host_state
.gs_sel
);
2190 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2193 if (vmx
->host_state
.fs_reload_needed
)
2194 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2195 #ifdef CONFIG_X86_64
2196 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2197 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2198 loadsegment(es
, vmx
->host_state
.es_sel
);
2201 invalidate_tss_limit();
2202 #ifdef CONFIG_X86_64
2203 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2205 if (vmx
->host_state
.msr_host_bndcfgs
)
2206 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2207 load_fixmap_gdt(raw_smp_processor_id());
2210 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2213 __vmx_load_host_state(vmx
);
2217 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2219 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2220 struct pi_desc old
, new;
2224 * In case of hot-plug or hot-unplug, we may have to undo
2225 * vmx_vcpu_pi_put even if there is no assigned device. And we
2226 * always keep PI.NDST up to date for simplicity: it makes the
2227 * code easier, and CPU migration is not a fast path.
2229 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2233 * First handle the simple case where no cmpxchg is necessary; just
2234 * allow posting non-urgent interrupts.
2236 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2237 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2238 * expects the VCPU to be on the blocked_vcpu_list that matches
2241 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2243 pi_clear_sn(pi_desc
);
2247 /* The full case. */
2249 old
.control
= new.control
= pi_desc
->control
;
2251 dest
= cpu_physical_id(cpu
);
2253 if (x2apic_enabled())
2256 new.ndst
= (dest
<< 8) & 0xFF00;
2259 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2260 new.control
) != old
.control
);
2263 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2265 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2266 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2270 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2271 * vcpu mutex is already taken.
2273 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2275 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2276 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2278 if (!already_loaded
) {
2279 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2280 local_irq_disable();
2281 crash_disable_local_vmclear(cpu
);
2284 * Read loaded_vmcs->cpu should be before fetching
2285 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2286 * See the comments in __loaded_vmcs_clear().
2290 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2291 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2292 crash_enable_local_vmclear(cpu
);
2296 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2297 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2298 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2301 if (!already_loaded
) {
2302 void *gdt
= get_current_gdt_ro();
2303 unsigned long sysenter_esp
;
2305 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2308 * Linux uses per-cpu TSS and GDT, so set these when switching
2309 * processors. See 22.2.4.
2311 vmcs_writel(HOST_TR_BASE
,
2312 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2313 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2316 * VM exits change the host TR limit to 0x67 after a VM
2317 * exit. This is okay, since 0x67 covers everything except
2318 * the IO bitmap and have have code to handle the IO bitmap
2319 * being lost after a VM exit.
2321 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2323 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2324 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2326 vmx
->loaded_vmcs
->cpu
= cpu
;
2329 /* Setup TSC multiplier */
2330 if (kvm_has_tsc_control
&&
2331 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2332 decache_tsc_multiplier(vmx
);
2334 vmx_vcpu_pi_load(vcpu
, cpu
);
2335 vmx
->host_pkru
= read_pkru();
2338 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2340 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2342 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2343 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2344 !kvm_vcpu_apicv_active(vcpu
))
2347 /* Set SN when the vCPU is preempted */
2348 if (vcpu
->preempted
)
2352 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2354 vmx_vcpu_pi_put(vcpu
);
2356 __vmx_load_host_state(to_vmx(vcpu
));
2359 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2361 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2364 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2367 * Return the cr0 value that a nested guest would read. This is a combination
2368 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2369 * its hypervisor (cr0_read_shadow).
2371 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2373 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2374 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2376 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2378 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2379 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2382 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2384 unsigned long rflags
, save_rflags
;
2386 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2387 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2388 rflags
= vmcs_readl(GUEST_RFLAGS
);
2389 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2390 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2391 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2392 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2394 to_vmx(vcpu
)->rflags
= rflags
;
2396 return to_vmx(vcpu
)->rflags
;
2399 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2401 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2403 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2404 to_vmx(vcpu
)->rflags
= rflags
;
2405 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2406 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2407 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2409 vmcs_writel(GUEST_RFLAGS
, rflags
);
2411 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2412 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2415 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2417 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2420 if (interruptibility
& GUEST_INTR_STATE_STI
)
2421 ret
|= KVM_X86_SHADOW_INT_STI
;
2422 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2423 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2428 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2430 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2431 u32 interruptibility
= interruptibility_old
;
2433 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2435 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2436 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2437 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2438 interruptibility
|= GUEST_INTR_STATE_STI
;
2440 if ((interruptibility
!= interruptibility_old
))
2441 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2444 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2448 rip
= kvm_rip_read(vcpu
);
2449 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2450 kvm_rip_write(vcpu
, rip
);
2452 /* skipping an emulated instruction also counts */
2453 vmx_set_interrupt_shadow(vcpu
, 0);
2456 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2457 unsigned long exit_qual
)
2459 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2460 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2461 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2463 if (vcpu
->arch
.exception
.has_error_code
) {
2464 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2465 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2468 if (kvm_exception_is_soft(nr
))
2469 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2471 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2473 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2474 vmx_get_nmi_mask(vcpu
))
2475 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2477 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2481 * KVM wants to inject page-faults which it got to the guest. This function
2482 * checks whether in a nested guest, we need to inject them to L1 or L2.
2484 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned long *exit_qual
)
2486 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2487 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2489 if (nr
== PF_VECTOR
) {
2490 if (vcpu
->arch
.exception
.nested_apf
) {
2491 *exit_qual
= vcpu
->arch
.apf
.nested_apf_token
;
2495 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2496 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2497 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2498 * can be written only when inject_pending_event runs. This should be
2499 * conditional on a new capability---if the capability is disabled,
2500 * kvm_multiple_exception would write the ancillary information to
2501 * CR2 or DR6, for backwards ABI-compatibility.
2503 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2504 vcpu
->arch
.exception
.error_code
)) {
2505 *exit_qual
= vcpu
->arch
.cr2
;
2509 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2510 if (nr
== DB_VECTOR
)
2511 *exit_qual
= vcpu
->arch
.dr6
;
2521 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2523 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2524 unsigned nr
= vcpu
->arch
.exception
.nr
;
2525 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2526 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2527 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2529 if (has_error_code
) {
2530 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2531 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2534 if (vmx
->rmode
.vm86_active
) {
2536 if (kvm_exception_is_soft(nr
))
2537 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2538 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2539 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2543 if (kvm_exception_is_soft(nr
)) {
2544 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2545 vmx
->vcpu
.arch
.event_exit_inst_len
);
2546 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2548 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2550 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2553 static bool vmx_rdtscp_supported(void)
2555 return cpu_has_vmx_rdtscp();
2558 static bool vmx_invpcid_supported(void)
2560 return cpu_has_vmx_invpcid() && enable_ept
;
2564 * Swap MSR entry in host/guest MSR entry array.
2566 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2568 struct shared_msr_entry tmp
;
2570 tmp
= vmx
->guest_msrs
[to
];
2571 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2572 vmx
->guest_msrs
[from
] = tmp
;
2575 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2577 unsigned long *msr_bitmap
;
2579 if (is_guest_mode(vcpu
))
2580 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2581 else if (cpu_has_secondary_exec_ctrls() &&
2582 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2583 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2584 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2585 if (is_long_mode(vcpu
))
2586 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2588 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2590 if (is_long_mode(vcpu
))
2591 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2593 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2596 if (is_long_mode(vcpu
))
2597 msr_bitmap
= vmx_msr_bitmap_longmode
;
2599 msr_bitmap
= vmx_msr_bitmap_legacy
;
2602 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2606 * Set up the vmcs to automatically save and restore system
2607 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2608 * mode, as fiddling with msrs is very expensive.
2610 static void setup_msrs(struct vcpu_vmx
*vmx
)
2612 int save_nmsrs
, index
;
2615 #ifdef CONFIG_X86_64
2616 if (is_long_mode(&vmx
->vcpu
)) {
2617 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2619 move_msr_up(vmx
, index
, save_nmsrs
++);
2620 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2622 move_msr_up(vmx
, index
, save_nmsrs
++);
2623 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2625 move_msr_up(vmx
, index
, save_nmsrs
++);
2626 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2627 if (index
>= 0 && guest_cpuid_has(&vmx
->vcpu
, X86_FEATURE_RDTSCP
))
2628 move_msr_up(vmx
, index
, save_nmsrs
++);
2630 * MSR_STAR is only needed on long mode guests, and only
2631 * if efer.sce is enabled.
2633 index
= __find_msr_index(vmx
, MSR_STAR
);
2634 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2635 move_msr_up(vmx
, index
, save_nmsrs
++);
2638 index
= __find_msr_index(vmx
, MSR_EFER
);
2639 if (index
>= 0 && update_transition_efer(vmx
, index
))
2640 move_msr_up(vmx
, index
, save_nmsrs
++);
2642 vmx
->save_nmsrs
= save_nmsrs
;
2644 if (cpu_has_vmx_msr_bitmap())
2645 vmx_set_msr_bitmap(&vmx
->vcpu
);
2649 * reads and returns guest's timestamp counter "register"
2650 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2651 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2653 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2655 u64 host_tsc
, tsc_offset
;
2658 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2659 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2663 * writes 'offset' into guest's timestamp counter offset register
2665 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2667 if (is_guest_mode(vcpu
)) {
2669 * We're here if L1 chose not to trap WRMSR to TSC. According
2670 * to the spec, this should set L1's TSC; The offset that L1
2671 * set for L2 remains unchanged, and still needs to be added
2672 * to the newly set TSC to get L2's TSC.
2674 struct vmcs12
*vmcs12
;
2675 /* recalculate vmcs02.TSC_OFFSET: */
2676 vmcs12
= get_vmcs12(vcpu
);
2677 vmcs_write64(TSC_OFFSET
, offset
+
2678 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2679 vmcs12
->tsc_offset
: 0));
2681 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2682 vmcs_read64(TSC_OFFSET
), offset
);
2683 vmcs_write64(TSC_OFFSET
, offset
);
2688 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2689 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2690 * all guests if the "nested" module option is off, and can also be disabled
2691 * for a single guest by disabling its VMX cpuid bit.
2693 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2695 return nested
&& guest_cpuid_has(vcpu
, X86_FEATURE_VMX
);
2699 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2700 * returned for the various VMX controls MSRs when nested VMX is enabled.
2701 * The same values should also be used to verify that vmcs12 control fields are
2702 * valid during nested entry from L1 to L2.
2703 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2704 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2705 * bit in the high half is on if the corresponding bit in the control field
2706 * may be on. See also vmx_control_verify().
2708 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2711 * Note that as a general rule, the high half of the MSRs (bits in
2712 * the control fields which may be 1) should be initialized by the
2713 * intersection of the underlying hardware's MSR (i.e., features which
2714 * can be supported) and the list of features we want to expose -
2715 * because they are known to be properly supported in our code.
2716 * Also, usually, the low half of the MSRs (bits which must be 1) can
2717 * be set to 0, meaning that L1 may turn off any of these bits. The
2718 * reason is that if one of these bits is necessary, it will appear
2719 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2720 * fields of vmcs01 and vmcs02, will turn these bits off - and
2721 * nested_vmx_exit_reflected() will not pass related exits to L1.
2722 * These rules have exceptions below.
2725 /* pin-based controls */
2726 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2727 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2728 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2729 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2730 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2731 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2732 PIN_BASED_EXT_INTR_MASK
|
2733 PIN_BASED_NMI_EXITING
|
2734 PIN_BASED_VIRTUAL_NMIS
;
2735 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2736 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2737 PIN_BASED_VMX_PREEMPTION_TIMER
;
2738 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2739 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2740 PIN_BASED_POSTED_INTR
;
2743 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2744 vmx
->nested
.nested_vmx_exit_ctls_low
,
2745 vmx
->nested
.nested_vmx_exit_ctls_high
);
2746 vmx
->nested
.nested_vmx_exit_ctls_low
=
2747 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2749 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2750 #ifdef CONFIG_X86_64
2751 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2753 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2754 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2755 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2756 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2757 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2759 if (kvm_mpx_supported())
2760 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2762 /* We support free control of debug control saving. */
2763 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2765 /* entry controls */
2766 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2767 vmx
->nested
.nested_vmx_entry_ctls_low
,
2768 vmx
->nested
.nested_vmx_entry_ctls_high
);
2769 vmx
->nested
.nested_vmx_entry_ctls_low
=
2770 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2771 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2772 #ifdef CONFIG_X86_64
2773 VM_ENTRY_IA32E_MODE
|
2775 VM_ENTRY_LOAD_IA32_PAT
;
2776 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2777 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2778 if (kvm_mpx_supported())
2779 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2781 /* We support free control of debug control loading. */
2782 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2784 /* cpu-based controls */
2785 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2786 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2787 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2788 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2789 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2790 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2791 CPU_BASED_VIRTUAL_INTR_PENDING
|
2792 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2793 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2794 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2795 CPU_BASED_CR3_STORE_EXITING
|
2796 #ifdef CONFIG_X86_64
2797 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2799 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2800 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2801 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2802 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2803 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2805 * We can allow some features even when not supported by the
2806 * hardware. For example, L1 can specify an MSR bitmap - and we
2807 * can use it to avoid exits to L1 - even when L0 runs L2
2808 * without MSR bitmaps.
2810 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2811 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2812 CPU_BASED_USE_MSR_BITMAPS
;
2814 /* We support free control of CR3 access interception. */
2815 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2816 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2819 * secondary cpu-based controls. Do not include those that
2820 * depend on CPUID bits, they are added later by vmx_cpuid_update.
2822 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2823 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2824 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2825 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2826 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2827 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2828 SECONDARY_EXEC_DESC
|
2829 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2830 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2831 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2832 SECONDARY_EXEC_WBINVD_EXITING
;
2835 /* nested EPT: emulate EPT also to L1 */
2836 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2837 SECONDARY_EXEC_ENABLE_EPT
;
2838 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2839 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2840 if (cpu_has_vmx_ept_execute_only())
2841 vmx
->nested
.nested_vmx_ept_caps
|=
2842 VMX_EPT_EXECUTE_ONLY_BIT
;
2843 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2844 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2845 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2846 VMX_EPT_1GB_PAGE_BIT
;
2847 if (enable_ept_ad_bits
) {
2848 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2849 SECONDARY_EXEC_ENABLE_PML
;
2850 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2854 if (cpu_has_vmx_vmfunc()) {
2855 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2856 SECONDARY_EXEC_ENABLE_VMFUNC
;
2858 * Advertise EPTP switching unconditionally
2859 * since we emulate it
2862 vmx
->nested
.nested_vmx_vmfunc_controls
=
2863 VMX_VMFUNC_EPTP_SWITCHING
;
2867 * Old versions of KVM use the single-context version without
2868 * checking for support, so declare that it is supported even
2869 * though it is treated as global context. The alternative is
2870 * not failing the single-context invvpid, and it is worse.
2873 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2874 SECONDARY_EXEC_ENABLE_VPID
;
2875 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2876 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2879 if (enable_unrestricted_guest
)
2880 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2881 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2883 /* miscellaneous data */
2884 rdmsr(MSR_IA32_VMX_MISC
,
2885 vmx
->nested
.nested_vmx_misc_low
,
2886 vmx
->nested
.nested_vmx_misc_high
);
2887 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2888 vmx
->nested
.nested_vmx_misc_low
|=
2889 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2890 VMX_MISC_ACTIVITY_HLT
;
2891 vmx
->nested
.nested_vmx_misc_high
= 0;
2894 * This MSR reports some information about VMX support. We
2895 * should return information about the VMX we emulate for the
2896 * guest, and the VMCS structure we give it - not about the
2897 * VMX support of the underlying hardware.
2899 vmx
->nested
.nested_vmx_basic
=
2901 VMX_BASIC_TRUE_CTLS
|
2902 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2903 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2905 if (cpu_has_vmx_basic_inout())
2906 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2909 * These MSRs specify bits which the guest must keep fixed on
2910 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2911 * We picked the standard core2 setting.
2913 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2914 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2915 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2916 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2918 /* These MSRs specify bits which the guest must keep fixed off. */
2919 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2920 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2922 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2923 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2927 * if fixed0[i] == 1: val[i] must be 1
2928 * if fixed1[i] == 0: val[i] must be 0
2930 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2932 return ((val
& fixed1
) | fixed0
) == val
;
2935 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2937 return fixed_bits_valid(control
, low
, high
);
2940 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2942 return low
| ((u64
)high
<< 32);
2945 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2950 return (superset
| subset
) == superset
;
2953 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2955 const u64 feature_and_reserved
=
2956 /* feature (except bit 48; see below) */
2957 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2959 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2960 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2962 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2966 * KVM does not emulate a version of VMX that constrains physical
2967 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2969 if (data
& BIT_ULL(48))
2972 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2973 vmx_basic_vmcs_revision_id(data
))
2976 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2979 vmx
->nested
.nested_vmx_basic
= data
;
2984 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2989 switch (msr_index
) {
2990 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2991 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2992 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2994 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2995 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2996 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2998 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2999 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
3000 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
3002 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3003 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
3004 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
3006 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3007 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
3008 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
3014 supported
= vmx_control_msr(*lowp
, *highp
);
3016 /* Check must-be-1 bits are still 1. */
3017 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
3020 /* Check must-be-0 bits are still 0. */
3021 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
3025 *highp
= data
>> 32;
3029 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3031 const u64 feature_and_reserved_bits
=
3033 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3034 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3036 GENMASK_ULL(13, 9) | BIT_ULL(31);
3039 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3040 vmx
->nested
.nested_vmx_misc_high
);
3042 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3045 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3046 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3047 vmx_misc_preemption_timer_rate(data
) !=
3048 vmx_misc_preemption_timer_rate(vmx_misc
))
3051 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3054 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3057 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3060 vmx
->nested
.nested_vmx_misc_low
= data
;
3061 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3065 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3067 u64 vmx_ept_vpid_cap
;
3069 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3070 vmx
->nested
.nested_vmx_vpid_caps
);
3072 /* Every bit is either reserved or a feature bit. */
3073 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3076 vmx
->nested
.nested_vmx_ept_caps
= data
;
3077 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3081 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3085 switch (msr_index
) {
3086 case MSR_IA32_VMX_CR0_FIXED0
:
3087 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3089 case MSR_IA32_VMX_CR4_FIXED0
:
3090 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3097 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3098 * must be 1 in the restored value.
3100 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3108 * Called when userspace is restoring VMX MSRs.
3110 * Returns 0 on success, non-0 otherwise.
3112 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3114 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3116 switch (msr_index
) {
3117 case MSR_IA32_VMX_BASIC
:
3118 return vmx_restore_vmx_basic(vmx
, data
);
3119 case MSR_IA32_VMX_PINBASED_CTLS
:
3120 case MSR_IA32_VMX_PROCBASED_CTLS
:
3121 case MSR_IA32_VMX_EXIT_CTLS
:
3122 case MSR_IA32_VMX_ENTRY_CTLS
:
3124 * The "non-true" VMX capability MSRs are generated from the
3125 * "true" MSRs, so we do not support restoring them directly.
3127 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3128 * should restore the "true" MSRs with the must-be-1 bits
3129 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3130 * DEFAULT SETTINGS".
3133 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3134 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3135 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3136 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3137 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3138 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3139 case MSR_IA32_VMX_MISC
:
3140 return vmx_restore_vmx_misc(vmx
, data
);
3141 case MSR_IA32_VMX_CR0_FIXED0
:
3142 case MSR_IA32_VMX_CR4_FIXED0
:
3143 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3144 case MSR_IA32_VMX_CR0_FIXED1
:
3145 case MSR_IA32_VMX_CR4_FIXED1
:
3147 * These MSRs are generated based on the vCPU's CPUID, so we
3148 * do not support restoring them directly.
3151 case MSR_IA32_VMX_EPT_VPID_CAP
:
3152 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3153 case MSR_IA32_VMX_VMCS_ENUM
:
3154 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3158 * The rest of the VMX capability MSRs do not support restore.
3164 /* Returns 0 on success, non-0 otherwise. */
3165 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3167 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3169 switch (msr_index
) {
3170 case MSR_IA32_VMX_BASIC
:
3171 *pdata
= vmx
->nested
.nested_vmx_basic
;
3173 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3174 case MSR_IA32_VMX_PINBASED_CTLS
:
3175 *pdata
= vmx_control_msr(
3176 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3177 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3178 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3179 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3181 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3182 case MSR_IA32_VMX_PROCBASED_CTLS
:
3183 *pdata
= vmx_control_msr(
3184 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3185 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3186 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3187 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3189 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3190 case MSR_IA32_VMX_EXIT_CTLS
:
3191 *pdata
= vmx_control_msr(
3192 vmx
->nested
.nested_vmx_exit_ctls_low
,
3193 vmx
->nested
.nested_vmx_exit_ctls_high
);
3194 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3195 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3197 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3198 case MSR_IA32_VMX_ENTRY_CTLS
:
3199 *pdata
= vmx_control_msr(
3200 vmx
->nested
.nested_vmx_entry_ctls_low
,
3201 vmx
->nested
.nested_vmx_entry_ctls_high
);
3202 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3203 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3205 case MSR_IA32_VMX_MISC
:
3206 *pdata
= vmx_control_msr(
3207 vmx
->nested
.nested_vmx_misc_low
,
3208 vmx
->nested
.nested_vmx_misc_high
);
3210 case MSR_IA32_VMX_CR0_FIXED0
:
3211 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3213 case MSR_IA32_VMX_CR0_FIXED1
:
3214 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3216 case MSR_IA32_VMX_CR4_FIXED0
:
3217 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3219 case MSR_IA32_VMX_CR4_FIXED1
:
3220 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3222 case MSR_IA32_VMX_VMCS_ENUM
:
3223 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3225 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3226 *pdata
= vmx_control_msr(
3227 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3228 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3230 case MSR_IA32_VMX_EPT_VPID_CAP
:
3231 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3232 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3234 case MSR_IA32_VMX_VMFUNC
:
3235 *pdata
= vmx
->nested
.nested_vmx_vmfunc_controls
;
3244 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3247 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3249 return !(val
& ~valid_bits
);
3253 * Reads an msr value (of 'msr_index') into 'pdata'.
3254 * Returns 0 on success, non-0 otherwise.
3255 * Assumes vcpu_load() was already called.
3257 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3259 struct shared_msr_entry
*msr
;
3261 switch (msr_info
->index
) {
3262 #ifdef CONFIG_X86_64
3264 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3267 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3269 case MSR_KERNEL_GS_BASE
:
3270 vmx_load_host_state(to_vmx(vcpu
));
3271 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3275 return kvm_get_msr_common(vcpu
, msr_info
);
3277 msr_info
->data
= guest_read_tsc(vcpu
);
3279 case MSR_IA32_SYSENTER_CS
:
3280 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3282 case MSR_IA32_SYSENTER_EIP
:
3283 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3285 case MSR_IA32_SYSENTER_ESP
:
3286 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3288 case MSR_IA32_BNDCFGS
:
3289 if (!kvm_mpx_supported() ||
3290 (!msr_info
->host_initiated
&&
3291 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3293 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3295 case MSR_IA32_MCG_EXT_CTL
:
3296 if (!msr_info
->host_initiated
&&
3297 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3298 FEATURE_CONTROL_LMCE
))
3300 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3302 case MSR_IA32_FEATURE_CONTROL
:
3303 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3305 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3306 if (!nested_vmx_allowed(vcpu
))
3308 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3310 if (!vmx_xsaves_supported())
3312 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3315 if (!msr_info
->host_initiated
&&
3316 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3318 /* Otherwise falls through */
3320 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3322 msr_info
->data
= msr
->data
;
3325 return kvm_get_msr_common(vcpu
, msr_info
);
3331 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3334 * Writes msr value into into the appropriate "register".
3335 * Returns 0 on success, non-0 otherwise.
3336 * Assumes vcpu_load() was already called.
3338 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3340 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3341 struct shared_msr_entry
*msr
;
3343 u32 msr_index
= msr_info
->index
;
3344 u64 data
= msr_info
->data
;
3346 switch (msr_index
) {
3348 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3350 #ifdef CONFIG_X86_64
3352 vmx_segment_cache_clear(vmx
);
3353 vmcs_writel(GUEST_FS_BASE
, data
);
3356 vmx_segment_cache_clear(vmx
);
3357 vmcs_writel(GUEST_GS_BASE
, data
);
3359 case MSR_KERNEL_GS_BASE
:
3360 vmx_load_host_state(vmx
);
3361 vmx
->msr_guest_kernel_gs_base
= data
;
3364 case MSR_IA32_SYSENTER_CS
:
3365 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3367 case MSR_IA32_SYSENTER_EIP
:
3368 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3370 case MSR_IA32_SYSENTER_ESP
:
3371 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3373 case MSR_IA32_BNDCFGS
:
3374 if (!kvm_mpx_supported() ||
3375 (!msr_info
->host_initiated
&&
3376 !guest_cpuid_has(vcpu
, X86_FEATURE_MPX
)))
3378 if (is_noncanonical_address(data
& PAGE_MASK
, vcpu
) ||
3379 (data
& MSR_IA32_BNDCFGS_RSVD
))
3381 vmcs_write64(GUEST_BNDCFGS
, data
);
3384 kvm_write_tsc(vcpu
, msr_info
);
3386 case MSR_IA32_CR_PAT
:
3387 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3388 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3390 vmcs_write64(GUEST_IA32_PAT
, data
);
3391 vcpu
->arch
.pat
= data
;
3394 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3396 case MSR_IA32_TSC_ADJUST
:
3397 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3399 case MSR_IA32_MCG_EXT_CTL
:
3400 if ((!msr_info
->host_initiated
&&
3401 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3402 FEATURE_CONTROL_LMCE
)) ||
3403 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3405 vcpu
->arch
.mcg_ext_ctl
= data
;
3407 case MSR_IA32_FEATURE_CONTROL
:
3408 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3409 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3410 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3412 vmx
->msr_ia32_feature_control
= data
;
3413 if (msr_info
->host_initiated
&& data
== 0)
3414 vmx_leave_nested(vcpu
);
3416 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3417 if (!msr_info
->host_initiated
)
3418 return 1; /* they are read-only */
3419 if (!nested_vmx_allowed(vcpu
))
3421 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3423 if (!vmx_xsaves_supported())
3426 * The only supported bit as of Skylake is bit 8, but
3427 * it is not supported on KVM.
3431 vcpu
->arch
.ia32_xss
= data
;
3432 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3433 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3434 vcpu
->arch
.ia32_xss
, host_xss
);
3436 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3439 if (!msr_info
->host_initiated
&&
3440 !guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
))
3442 /* Check reserved bit, higher 32 bits should be zero */
3443 if ((data
>> 32) != 0)
3445 /* Otherwise falls through */
3447 msr
= find_msr_entry(vmx
, msr_index
);
3449 u64 old_msr_data
= msr
->data
;
3451 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3453 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3457 msr
->data
= old_msr_data
;
3461 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3467 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3469 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3472 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3475 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3477 case VCPU_EXREG_PDPTR
:
3479 ept_save_pdptrs(vcpu
);
3486 static __init
int cpu_has_kvm_support(void)
3488 return cpu_has_vmx();
3491 static __init
int vmx_disabled_by_bios(void)
3495 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3496 if (msr
& FEATURE_CONTROL_LOCKED
) {
3497 /* launched w/ TXT and VMX disabled */
3498 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3501 /* launched w/o TXT and VMX only enabled w/ TXT */
3502 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3503 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3504 && !tboot_enabled()) {
3505 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3506 "activate TXT before enabling KVM\n");
3509 /* launched w/o TXT and VMX disabled */
3510 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3511 && !tboot_enabled())
3518 static void kvm_cpu_vmxon(u64 addr
)
3520 cr4_set_bits(X86_CR4_VMXE
);
3521 intel_pt_handle_vmx(1);
3523 asm volatile (ASM_VMX_VMXON_RAX
3524 : : "a"(&addr
), "m"(addr
)
3528 static int hardware_enable(void)
3530 int cpu
= raw_smp_processor_id();
3531 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3534 if (cr4_read_shadow() & X86_CR4_VMXE
)
3537 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3538 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3539 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3542 * Now we can enable the vmclear operation in kdump
3543 * since the loaded_vmcss_on_cpu list on this cpu
3544 * has been initialized.
3546 * Though the cpu is not in VMX operation now, there
3547 * is no problem to enable the vmclear operation
3548 * for the loaded_vmcss_on_cpu list is empty!
3550 crash_enable_local_vmclear(cpu
);
3552 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3554 test_bits
= FEATURE_CONTROL_LOCKED
;
3555 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3556 if (tboot_enabled())
3557 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3559 if ((old
& test_bits
) != test_bits
) {
3560 /* enable and lock */
3561 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3563 kvm_cpu_vmxon(phys_addr
);
3570 static void vmclear_local_loaded_vmcss(void)
3572 int cpu
= raw_smp_processor_id();
3573 struct loaded_vmcs
*v
, *n
;
3575 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3576 loaded_vmcss_on_cpu_link
)
3577 __loaded_vmcs_clear(v
);
3581 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3584 static void kvm_cpu_vmxoff(void)
3586 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3588 intel_pt_handle_vmx(0);
3589 cr4_clear_bits(X86_CR4_VMXE
);
3592 static void hardware_disable(void)
3594 vmclear_local_loaded_vmcss();
3598 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3599 u32 msr
, u32
*result
)
3601 u32 vmx_msr_low
, vmx_msr_high
;
3602 u32 ctl
= ctl_min
| ctl_opt
;
3604 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3606 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3607 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3609 /* Ensure minimum (required) set of control bits are supported. */
3617 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3619 u32 vmx_msr_low
, vmx_msr_high
;
3621 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3622 return vmx_msr_high
& ctl
;
3625 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3627 u32 vmx_msr_low
, vmx_msr_high
;
3628 u32 min
, opt
, min2
, opt2
;
3629 u32 _pin_based_exec_control
= 0;
3630 u32 _cpu_based_exec_control
= 0;
3631 u32 _cpu_based_2nd_exec_control
= 0;
3632 u32 _vmexit_control
= 0;
3633 u32 _vmentry_control
= 0;
3635 min
= CPU_BASED_HLT_EXITING
|
3636 #ifdef CONFIG_X86_64
3637 CPU_BASED_CR8_LOAD_EXITING
|
3638 CPU_BASED_CR8_STORE_EXITING
|
3640 CPU_BASED_CR3_LOAD_EXITING
|
3641 CPU_BASED_CR3_STORE_EXITING
|
3642 CPU_BASED_USE_IO_BITMAPS
|
3643 CPU_BASED_MOV_DR_EXITING
|
3644 CPU_BASED_USE_TSC_OFFSETING
|
3645 CPU_BASED_INVLPG_EXITING
|
3646 CPU_BASED_RDPMC_EXITING
;
3648 if (!kvm_mwait_in_guest())
3649 min
|= CPU_BASED_MWAIT_EXITING
|
3650 CPU_BASED_MONITOR_EXITING
;
3652 opt
= CPU_BASED_TPR_SHADOW
|
3653 CPU_BASED_USE_MSR_BITMAPS
|
3654 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3655 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3656 &_cpu_based_exec_control
) < 0)
3658 #ifdef CONFIG_X86_64
3659 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3660 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3661 ~CPU_BASED_CR8_STORE_EXITING
;
3663 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3665 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3666 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3667 SECONDARY_EXEC_WBINVD_EXITING
|
3668 SECONDARY_EXEC_ENABLE_VPID
|
3669 SECONDARY_EXEC_ENABLE_EPT
|
3670 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3671 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3672 SECONDARY_EXEC_RDTSCP
|
3673 SECONDARY_EXEC_ENABLE_INVPCID
|
3674 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3675 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3676 SECONDARY_EXEC_SHADOW_VMCS
|
3677 SECONDARY_EXEC_XSAVES
|
3678 SECONDARY_EXEC_RDSEED_EXITING
|
3679 SECONDARY_EXEC_RDRAND_EXITING
|
3680 SECONDARY_EXEC_ENABLE_PML
|
3681 SECONDARY_EXEC_TSC_SCALING
|
3682 SECONDARY_EXEC_ENABLE_VMFUNC
;
3683 if (adjust_vmx_controls(min2
, opt2
,
3684 MSR_IA32_VMX_PROCBASED_CTLS2
,
3685 &_cpu_based_2nd_exec_control
) < 0)
3688 #ifndef CONFIG_X86_64
3689 if (!(_cpu_based_2nd_exec_control
&
3690 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3691 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3694 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3695 _cpu_based_2nd_exec_control
&= ~(
3696 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3697 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3698 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3700 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP
,
3701 &vmx_capability
.ept
, &vmx_capability
.vpid
);
3703 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3704 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3706 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3707 CPU_BASED_CR3_STORE_EXITING
|
3708 CPU_BASED_INVLPG_EXITING
);
3709 } else if (vmx_capability
.ept
) {
3710 vmx_capability
.ept
= 0;
3711 pr_warn_once("EPT CAP should not exist if not support "
3712 "1-setting enable EPT VM-execution control\n");
3714 if (!(_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_VPID
) &&
3715 vmx_capability
.vpid
) {
3716 vmx_capability
.vpid
= 0;
3717 pr_warn_once("VPID CAP should not exist if not support "
3718 "1-setting enable VPID VM-execution control\n");
3721 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3722 #ifdef CONFIG_X86_64
3723 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3725 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3726 VM_EXIT_CLEAR_BNDCFGS
;
3727 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3728 &_vmexit_control
) < 0)
3731 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3732 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
|
3733 PIN_BASED_VMX_PREEMPTION_TIMER
;
3734 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3735 &_pin_based_exec_control
) < 0)
3738 if (cpu_has_broken_vmx_preemption_timer())
3739 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3740 if (!(_cpu_based_2nd_exec_control
&
3741 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3742 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3744 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3745 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3746 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3747 &_vmentry_control
) < 0)
3750 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3752 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3753 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3756 #ifdef CONFIG_X86_64
3757 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3758 if (vmx_msr_high
& (1u<<16))
3762 /* Require Write-Back (WB) memory type for VMCS accesses. */
3763 if (((vmx_msr_high
>> 18) & 15) != 6)
3766 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3767 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3768 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3769 vmcs_conf
->revision_id
= vmx_msr_low
;
3771 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3772 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3773 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3774 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3775 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3777 cpu_has_load_ia32_efer
=
3778 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3779 VM_ENTRY_LOAD_IA32_EFER
)
3780 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3781 VM_EXIT_LOAD_IA32_EFER
);
3783 cpu_has_load_perf_global_ctrl
=
3784 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3785 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3786 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3787 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3790 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3791 * but due to errata below it can't be used. Workaround is to use
3792 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3794 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3799 * BC86,AAY89,BD102 (model 44)
3803 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3804 switch (boot_cpu_data
.x86_model
) {
3810 cpu_has_load_perf_global_ctrl
= false;
3811 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3812 "does not work properly. Using workaround\n");
3819 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3820 rdmsrl(MSR_IA32_XSS
, host_xss
);
3825 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3827 int node
= cpu_to_node(cpu
);
3831 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3834 vmcs
= page_address(pages
);
3835 memset(vmcs
, 0, vmcs_config
.size
);
3836 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3840 static struct vmcs
*alloc_vmcs(void)
3842 return alloc_vmcs_cpu(raw_smp_processor_id());
3845 static void free_vmcs(struct vmcs
*vmcs
)
3847 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3851 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3853 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3855 if (!loaded_vmcs
->vmcs
)
3857 loaded_vmcs_clear(loaded_vmcs
);
3858 free_vmcs(loaded_vmcs
->vmcs
);
3859 loaded_vmcs
->vmcs
= NULL
;
3860 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3863 static void free_kvm_area(void)
3867 for_each_possible_cpu(cpu
) {
3868 free_vmcs(per_cpu(vmxarea
, cpu
));
3869 per_cpu(vmxarea
, cpu
) = NULL
;
3873 enum vmcs_field_type
{
3874 VMCS_FIELD_TYPE_U16
= 0,
3875 VMCS_FIELD_TYPE_U64
= 1,
3876 VMCS_FIELD_TYPE_U32
= 2,
3877 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3880 static inline int vmcs_field_type(unsigned long field
)
3882 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3883 return VMCS_FIELD_TYPE_U32
;
3884 return (field
>> 13) & 0x3 ;
3887 static inline int vmcs_field_readonly(unsigned long field
)
3889 return (((field
>> 10) & 0x3) == 1);
3892 static void init_vmcs_shadow_fields(void)
3896 /* No checks for read only fields yet */
3898 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3899 switch (shadow_read_write_fields
[i
]) {
3901 if (!kvm_mpx_supported())
3909 shadow_read_write_fields
[j
] =
3910 shadow_read_write_fields
[i
];
3913 max_shadow_read_write_fields
= j
;
3915 /* shadowed fields guest access without vmexit */
3916 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3917 unsigned long field
= shadow_read_write_fields
[i
];
3919 clear_bit(field
, vmx_vmwrite_bitmap
);
3920 clear_bit(field
, vmx_vmread_bitmap
);
3921 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3922 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3923 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3926 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3927 unsigned long field
= shadow_read_only_fields
[i
];
3929 clear_bit(field
, vmx_vmread_bitmap
);
3930 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3931 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3935 static __init
int alloc_kvm_area(void)
3939 for_each_possible_cpu(cpu
) {
3942 vmcs
= alloc_vmcs_cpu(cpu
);
3948 per_cpu(vmxarea
, cpu
) = vmcs
;
3953 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3954 struct kvm_segment
*save
)
3956 if (!emulate_invalid_guest_state
) {
3958 * CS and SS RPL should be equal during guest entry according
3959 * to VMX spec, but in reality it is not always so. Since vcpu
3960 * is in the middle of the transition from real mode to
3961 * protected mode it is safe to assume that RPL 0 is a good
3964 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3965 save
->selector
&= ~SEGMENT_RPL_MASK
;
3966 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3969 vmx_set_segment(vcpu
, save
, seg
);
3972 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3974 unsigned long flags
;
3975 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3978 * Update real mode segment cache. It may be not up-to-date if sement
3979 * register was written while vcpu was in a guest mode.
3981 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3982 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3983 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3984 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3985 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3986 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3988 vmx
->rmode
.vm86_active
= 0;
3990 vmx_segment_cache_clear(vmx
);
3992 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3994 flags
= vmcs_readl(GUEST_RFLAGS
);
3995 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3996 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3997 vmcs_writel(GUEST_RFLAGS
, flags
);
3999 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
4000 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
4002 update_exception_bitmap(vcpu
);
4004 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4005 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4006 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4007 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4008 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4009 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4012 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
4014 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4015 struct kvm_segment var
= *save
;
4018 if (seg
== VCPU_SREG_CS
)
4021 if (!emulate_invalid_guest_state
) {
4022 var
.selector
= var
.base
>> 4;
4023 var
.base
= var
.base
& 0xffff0;
4033 if (save
->base
& 0xf)
4034 printk_once(KERN_WARNING
"kvm: segment base is not "
4035 "paragraph aligned when entering "
4036 "protected mode (seg=%d)", seg
);
4039 vmcs_write16(sf
->selector
, var
.selector
);
4040 vmcs_writel(sf
->base
, var
.base
);
4041 vmcs_write32(sf
->limit
, var
.limit
);
4042 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4045 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4047 unsigned long flags
;
4048 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4050 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4051 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4052 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4053 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4054 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4055 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4056 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4058 vmx
->rmode
.vm86_active
= 1;
4061 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4062 * vcpu. Warn the user that an update is overdue.
4064 if (!vcpu
->kvm
->arch
.tss_addr
)
4065 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4066 "called before entering vcpu\n");
4068 vmx_segment_cache_clear(vmx
);
4070 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4071 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4072 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4074 flags
= vmcs_readl(GUEST_RFLAGS
);
4075 vmx
->rmode
.save_rflags
= flags
;
4077 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4079 vmcs_writel(GUEST_RFLAGS
, flags
);
4080 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4081 update_exception_bitmap(vcpu
);
4083 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4084 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4085 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4086 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4087 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4088 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4090 kvm_mmu_reset_context(vcpu
);
4093 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4095 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4096 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4102 * Force kernel_gs_base reloading before EFER changes, as control
4103 * of this msr depends on is_long_mode().
4105 vmx_load_host_state(to_vmx(vcpu
));
4106 vcpu
->arch
.efer
= efer
;
4107 if (efer
& EFER_LMA
) {
4108 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4111 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4113 msr
->data
= efer
& ~EFER_LME
;
4118 #ifdef CONFIG_X86_64
4120 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4124 vmx_segment_cache_clear(to_vmx(vcpu
));
4126 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4127 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4128 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4130 vmcs_write32(GUEST_TR_AR_BYTES
,
4131 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4132 | VMX_AR_TYPE_BUSY_64_TSS
);
4134 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4137 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4139 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4140 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4145 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4148 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4150 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4152 vpid_sync_context(vpid
);
4156 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4158 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4161 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4164 vmx_flush_tlb(vcpu
);
4167 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4169 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4171 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4172 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4175 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4177 if (enable_ept
&& is_paging(vcpu
))
4178 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4179 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4182 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4184 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4186 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4187 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4190 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4192 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4194 if (!test_bit(VCPU_EXREG_PDPTR
,
4195 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4198 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4199 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4200 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4201 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4202 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4206 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4208 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4210 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4211 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4212 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4213 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4214 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4217 __set_bit(VCPU_EXREG_PDPTR
,
4218 (unsigned long *)&vcpu
->arch
.regs_avail
);
4219 __set_bit(VCPU_EXREG_PDPTR
,
4220 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4223 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4225 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4226 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4227 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4229 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4230 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4231 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4232 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4234 return fixed_bits_valid(val
, fixed0
, fixed1
);
4237 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4239 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4240 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4242 return fixed_bits_valid(val
, fixed0
, fixed1
);
4245 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4247 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4248 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4250 return fixed_bits_valid(val
, fixed0
, fixed1
);
4253 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4254 #define nested_guest_cr4_valid nested_cr4_valid
4255 #define nested_host_cr4_valid nested_cr4_valid
4257 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4259 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4261 struct kvm_vcpu
*vcpu
)
4263 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4264 vmx_decache_cr3(vcpu
);
4265 if (!(cr0
& X86_CR0_PG
)) {
4266 /* From paging/starting to nonpaging */
4267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4268 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4269 (CPU_BASED_CR3_LOAD_EXITING
|
4270 CPU_BASED_CR3_STORE_EXITING
));
4271 vcpu
->arch
.cr0
= cr0
;
4272 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4273 } else if (!is_paging(vcpu
)) {
4274 /* From nonpaging to paging */
4275 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4276 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4277 ~(CPU_BASED_CR3_LOAD_EXITING
|
4278 CPU_BASED_CR3_STORE_EXITING
));
4279 vcpu
->arch
.cr0
= cr0
;
4280 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4283 if (!(cr0
& X86_CR0_WP
))
4284 *hw_cr0
&= ~X86_CR0_WP
;
4287 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4289 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4290 unsigned long hw_cr0
;
4292 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4293 if (enable_unrestricted_guest
)
4294 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4296 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4298 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4301 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4305 #ifdef CONFIG_X86_64
4306 if (vcpu
->arch
.efer
& EFER_LME
) {
4307 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4309 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4315 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4317 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4318 vmcs_writel(GUEST_CR0
, hw_cr0
);
4319 vcpu
->arch
.cr0
= cr0
;
4321 /* depends on vcpu->arch.cr0 to be set to a new value */
4322 vmx
->emulation_required
= emulation_required(vcpu
);
4325 static int get_ept_level(struct kvm_vcpu
*vcpu
)
4327 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu
) > 48))
4332 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4334 u64 eptp
= VMX_EPTP_MT_WB
;
4336 eptp
|= (get_ept_level(vcpu
) == 5) ? VMX_EPTP_PWL_5
: VMX_EPTP_PWL_4
;
4338 if (enable_ept_ad_bits
&&
4339 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4340 eptp
|= VMX_EPTP_AD_ENABLE_BIT
;
4341 eptp
|= (root_hpa
& PAGE_MASK
);
4346 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4348 unsigned long guest_cr3
;
4353 eptp
= construct_eptp(vcpu
, cr3
);
4354 vmcs_write64(EPT_POINTER
, eptp
);
4355 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4356 guest_cr3
= kvm_read_cr3(vcpu
);
4358 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4359 ept_load_pdptrs(vcpu
);
4362 vmx_flush_tlb(vcpu
);
4363 vmcs_writel(GUEST_CR3
, guest_cr3
);
4366 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4369 * Pass through host's Machine Check Enable value to hw_cr4, which
4370 * is in force while we are in guest mode. Do not let guests control
4371 * this bit, even if host CR4.MCE == 0.
4373 unsigned long hw_cr4
=
4374 (cr4_read_shadow() & X86_CR4_MCE
) |
4375 (cr4
& ~X86_CR4_MCE
) |
4376 (to_vmx(vcpu
)->rmode
.vm86_active
?
4377 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4379 if (cr4
& X86_CR4_VMXE
) {
4381 * To use VMXON (and later other VMX instructions), a guest
4382 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4383 * So basically the check on whether to allow nested VMX
4386 if (!nested_vmx_allowed(vcpu
))
4390 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4393 vcpu
->arch
.cr4
= cr4
;
4395 if (!is_paging(vcpu
)) {
4396 hw_cr4
&= ~X86_CR4_PAE
;
4397 hw_cr4
|= X86_CR4_PSE
;
4398 } else if (!(cr4
& X86_CR4_PAE
)) {
4399 hw_cr4
&= ~X86_CR4_PAE
;
4403 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4405 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4406 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4407 * to be manually disabled when guest switches to non-paging
4410 * If !enable_unrestricted_guest, the CPU is always running
4411 * with CR0.PG=1 and CR4 needs to be modified.
4412 * If enable_unrestricted_guest, the CPU automatically
4413 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4415 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4417 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4418 vmcs_writel(GUEST_CR4
, hw_cr4
);
4422 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4423 struct kvm_segment
*var
, int seg
)
4425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4428 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4429 *var
= vmx
->rmode
.segs
[seg
];
4430 if (seg
== VCPU_SREG_TR
4431 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4433 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4434 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4437 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4438 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4439 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4440 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4441 var
->unusable
= (ar
>> 16) & 1;
4442 var
->type
= ar
& 15;
4443 var
->s
= (ar
>> 4) & 1;
4444 var
->dpl
= (ar
>> 5) & 3;
4446 * Some userspaces do not preserve unusable property. Since usable
4447 * segment has to be present according to VMX spec we can use present
4448 * property to amend userspace bug by making unusable segment always
4449 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4450 * segment as unusable.
4452 var
->present
= !var
->unusable
;
4453 var
->avl
= (ar
>> 12) & 1;
4454 var
->l
= (ar
>> 13) & 1;
4455 var
->db
= (ar
>> 14) & 1;
4456 var
->g
= (ar
>> 15) & 1;
4459 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4461 struct kvm_segment s
;
4463 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4464 vmx_get_segment(vcpu
, &s
, seg
);
4467 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4470 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4474 if (unlikely(vmx
->rmode
.vm86_active
))
4477 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4478 return VMX_AR_DPL(ar
);
4482 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4486 if (var
->unusable
|| !var
->present
)
4489 ar
= var
->type
& 15;
4490 ar
|= (var
->s
& 1) << 4;
4491 ar
|= (var
->dpl
& 3) << 5;
4492 ar
|= (var
->present
& 1) << 7;
4493 ar
|= (var
->avl
& 1) << 12;
4494 ar
|= (var
->l
& 1) << 13;
4495 ar
|= (var
->db
& 1) << 14;
4496 ar
|= (var
->g
& 1) << 15;
4502 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4503 struct kvm_segment
*var
, int seg
)
4505 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4506 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4508 vmx_segment_cache_clear(vmx
);
4510 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4511 vmx
->rmode
.segs
[seg
] = *var
;
4512 if (seg
== VCPU_SREG_TR
)
4513 vmcs_write16(sf
->selector
, var
->selector
);
4515 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4519 vmcs_writel(sf
->base
, var
->base
);
4520 vmcs_write32(sf
->limit
, var
->limit
);
4521 vmcs_write16(sf
->selector
, var
->selector
);
4524 * Fix the "Accessed" bit in AR field of segment registers for older
4526 * IA32 arch specifies that at the time of processor reset the
4527 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4528 * is setting it to 0 in the userland code. This causes invalid guest
4529 * state vmexit when "unrestricted guest" mode is turned on.
4530 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4531 * tree. Newer qemu binaries with that qemu fix would not need this
4534 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4535 var
->type
|= 0x1; /* Accessed */
4537 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4540 vmx
->emulation_required
= emulation_required(vcpu
);
4543 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4545 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4547 *db
= (ar
>> 14) & 1;
4548 *l
= (ar
>> 13) & 1;
4551 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4553 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4554 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4557 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4559 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4560 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4563 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4565 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4566 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4569 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4571 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4572 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4575 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4577 struct kvm_segment var
;
4580 vmx_get_segment(vcpu
, &var
, seg
);
4582 if (seg
== VCPU_SREG_CS
)
4584 ar
= vmx_segment_access_rights(&var
);
4586 if (var
.base
!= (var
.selector
<< 4))
4588 if (var
.limit
!= 0xffff)
4596 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4598 struct kvm_segment cs
;
4599 unsigned int cs_rpl
;
4601 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4602 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4606 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4610 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4611 if (cs
.dpl
> cs_rpl
)
4614 if (cs
.dpl
!= cs_rpl
)
4620 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4624 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4626 struct kvm_segment ss
;
4627 unsigned int ss_rpl
;
4629 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4630 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4634 if (ss
.type
!= 3 && ss
.type
!= 7)
4638 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4646 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4648 struct kvm_segment var
;
4651 vmx_get_segment(vcpu
, &var
, seg
);
4652 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4660 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4661 if (var
.dpl
< rpl
) /* DPL < RPL */
4665 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4671 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4673 struct kvm_segment tr
;
4675 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4679 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4681 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4689 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4691 struct kvm_segment ldtr
;
4693 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4697 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4707 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4709 struct kvm_segment cs
, ss
;
4711 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4712 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4714 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4715 (ss
.selector
& SEGMENT_RPL_MASK
));
4719 * Check if guest state is valid. Returns true if valid, false if
4721 * We assume that registers are always usable
4723 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4725 if (enable_unrestricted_guest
)
4728 /* real mode guest state checks */
4729 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4730 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4732 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4734 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4736 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4738 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4740 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4743 /* protected mode guest state checks */
4744 if (!cs_ss_rpl_check(vcpu
))
4746 if (!code_segment_valid(vcpu
))
4748 if (!stack_segment_valid(vcpu
))
4750 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4752 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4754 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4756 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4758 if (!tr_valid(vcpu
))
4760 if (!ldtr_valid(vcpu
))
4764 * - Add checks on RIP
4765 * - Add checks on RFLAGS
4771 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4773 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4776 static int init_rmode_tss(struct kvm
*kvm
)
4782 idx
= srcu_read_lock(&kvm
->srcu
);
4783 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4784 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4787 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4788 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4789 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4792 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4795 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4799 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4800 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4803 srcu_read_unlock(&kvm
->srcu
, idx
);
4807 static int init_rmode_identity_map(struct kvm
*kvm
)
4810 kvm_pfn_t identity_map_pfn
;
4813 /* Protect kvm->arch.ept_identity_pagetable_done. */
4814 mutex_lock(&kvm
->slots_lock
);
4816 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4819 if (!kvm
->arch
.ept_identity_map_addr
)
4820 kvm
->arch
.ept_identity_map_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4821 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4823 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4824 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4828 idx
= srcu_read_lock(&kvm
->srcu
);
4829 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4832 /* Set up identity-mapping pagetable for EPT in real mode */
4833 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4834 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4835 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4836 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4837 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4841 kvm
->arch
.ept_identity_pagetable_done
= true;
4844 srcu_read_unlock(&kvm
->srcu
, idx
);
4847 mutex_unlock(&kvm
->slots_lock
);
4851 static void seg_setup(int seg
)
4853 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4856 vmcs_write16(sf
->selector
, 0);
4857 vmcs_writel(sf
->base
, 0);
4858 vmcs_write32(sf
->limit
, 0xffff);
4860 if (seg
== VCPU_SREG_CS
)
4861 ar
|= 0x08; /* code segment */
4863 vmcs_write32(sf
->ar_bytes
, ar
);
4866 static int alloc_apic_access_page(struct kvm
*kvm
)
4871 mutex_lock(&kvm
->slots_lock
);
4872 if (kvm
->arch
.apic_access_page_done
)
4874 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4875 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4879 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4880 if (is_error_page(page
)) {
4886 * Do not pin the page in memory, so that memory hot-unplug
4887 * is able to migrate it.
4890 kvm
->arch
.apic_access_page_done
= true;
4892 mutex_unlock(&kvm
->slots_lock
);
4896 static int allocate_vpid(void)
4902 spin_lock(&vmx_vpid_lock
);
4903 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4904 if (vpid
< VMX_NR_VPIDS
)
4905 __set_bit(vpid
, vmx_vpid_bitmap
);
4908 spin_unlock(&vmx_vpid_lock
);
4912 static void free_vpid(int vpid
)
4914 if (!enable_vpid
|| vpid
== 0)
4916 spin_lock(&vmx_vpid_lock
);
4917 __clear_bit(vpid
, vmx_vpid_bitmap
);
4918 spin_unlock(&vmx_vpid_lock
);
4921 #define MSR_TYPE_R 1
4922 #define MSR_TYPE_W 2
4923 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4926 int f
= sizeof(unsigned long);
4928 if (!cpu_has_vmx_msr_bitmap())
4932 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4933 * have the write-low and read-high bitmap offsets the wrong way round.
4934 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4936 if (msr
<= 0x1fff) {
4937 if (type
& MSR_TYPE_R
)
4939 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4941 if (type
& MSR_TYPE_W
)
4943 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4945 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4947 if (type
& MSR_TYPE_R
)
4949 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4951 if (type
& MSR_TYPE_W
)
4953 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4959 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4960 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4962 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4963 unsigned long *msr_bitmap_nested
,
4966 int f
= sizeof(unsigned long);
4968 if (!cpu_has_vmx_msr_bitmap()) {
4974 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4975 * have the write-low and read-high bitmap offsets the wrong way round.
4976 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4978 if (msr
<= 0x1fff) {
4979 if (type
& MSR_TYPE_R
&&
4980 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4982 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4984 if (type
& MSR_TYPE_W
&&
4985 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4987 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4989 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4991 if (type
& MSR_TYPE_R
&&
4992 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4994 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4996 if (type
& MSR_TYPE_W
&&
4997 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4999 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
5004 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
5007 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
5008 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5009 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
5010 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
5013 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
5016 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
5018 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
5021 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
5023 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
5028 static bool vmx_get_enable_apicv(struct kvm_vcpu
*vcpu
)
5030 return enable_apicv
;
5033 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5035 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5039 * Don't need to mark the APIC access page dirty; it is never
5040 * written to by the CPU during APIC virtualization.
5043 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5044 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5045 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5048 if (nested_cpu_has_posted_intr(vmcs12
)) {
5049 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5050 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5055 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5057 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5062 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5065 vmx
->nested
.pi_pending
= false;
5066 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5069 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5070 if (max_irr
!= 256) {
5071 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5072 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5073 kunmap(vmx
->nested
.virtual_apic_page
);
5075 status
= vmcs_read16(GUEST_INTR_STATUS
);
5076 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5078 status
|= (u8
)max_irr
;
5079 vmcs_write16(GUEST_INTR_STATUS
, status
);
5083 nested_mark_vmcs12_pages_dirty(vcpu
);
5086 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5090 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5092 if (vcpu
->mode
== IN_GUEST_MODE
) {
5094 * The vector of interrupt to be delivered to vcpu had
5095 * been set in PIR before this function.
5097 * Following cases will be reached in this block, and
5098 * we always send a notification event in all cases as
5101 * Case 1: vcpu keeps in non-root mode. Sending a
5102 * notification event posts the interrupt to vcpu.
5104 * Case 2: vcpu exits to root mode and is still
5105 * runnable. PIR will be synced to vIRR before the
5106 * next vcpu entry. Sending a notification event in
5107 * this case has no effect, as vcpu is not in root
5110 * Case 3: vcpu exits to root mode and is blocked.
5111 * vcpu_block() has already synced PIR to vIRR and
5112 * never blocks vcpu if vIRR is not cleared. Therefore,
5113 * a blocked vcpu here does not wait for any requested
5114 * interrupts in PIR, and sending a notification event
5115 * which has no effect is safe here.
5118 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5125 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5130 if (is_guest_mode(vcpu
) &&
5131 vector
== vmx
->nested
.posted_intr_nv
) {
5132 /* the PIR and ON have been set by L1. */
5133 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5135 * If a posted intr is not recognized by hardware,
5136 * we will accomplish it in the next vmentry.
5138 vmx
->nested
.pi_pending
= true;
5139 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5145 * Send interrupt to vcpu via posted interrupt way.
5146 * 1. If target vcpu is running(non-root mode), send posted interrupt
5147 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5148 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5149 * interrupt from PIR in next vmentry.
5151 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5153 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5156 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5160 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5163 /* If a previous notification has sent the IPI, nothing to do. */
5164 if (pi_test_and_set_on(&vmx
->pi_desc
))
5167 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5168 kvm_vcpu_kick(vcpu
);
5172 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5173 * will not change in the lifetime of the guest.
5174 * Note that host-state that does change is set elsewhere. E.g., host-state
5175 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5177 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5182 unsigned long cr0
, cr3
, cr4
;
5185 WARN_ON(cr0
& X86_CR0_TS
);
5186 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5189 * Save the most likely value for this task's CR3 in the VMCS.
5190 * We can't use __get_current_cr3_fast() because we're not atomic.
5193 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5194 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5196 /* Save the most likely value for this task's CR4 in the VMCS. */
5197 cr4
= cr4_read_shadow();
5198 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5199 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5201 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5202 #ifdef CONFIG_X86_64
5204 * Load null selectors, so we can avoid reloading them in
5205 * __vmx_load_host_state(), in case userspace uses the null selectors
5206 * too (the expected case).
5208 vmcs_write16(HOST_DS_SELECTOR
, 0);
5209 vmcs_write16(HOST_ES_SELECTOR
, 0);
5211 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5212 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5214 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5215 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5218 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5219 vmx
->host_idt_base
= dt
.address
;
5221 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5223 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5224 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5225 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5226 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5228 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5229 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5230 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5234 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5236 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5238 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5239 if (is_guest_mode(&vmx
->vcpu
))
5240 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5241 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5242 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5245 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5247 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5249 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5250 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5253 pin_based_exec_ctrl
&= ~PIN_BASED_VIRTUAL_NMIS
;
5255 /* Enable the preemption timer dynamically */
5256 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5257 return pin_based_exec_ctrl
;
5260 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5262 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5264 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5265 if (cpu_has_secondary_exec_ctrls()) {
5266 if (kvm_vcpu_apicv_active(vcpu
))
5267 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5268 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5269 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5271 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5272 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5273 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5276 if (cpu_has_vmx_msr_bitmap())
5277 vmx_set_msr_bitmap(vcpu
);
5280 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5282 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5284 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5285 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5287 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5288 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5289 #ifdef CONFIG_X86_64
5290 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5291 CPU_BASED_CR8_LOAD_EXITING
;
5295 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5296 CPU_BASED_CR3_LOAD_EXITING
|
5297 CPU_BASED_INVLPG_EXITING
;
5298 return exec_control
;
5301 static bool vmx_rdrand_supported(void)
5303 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5304 SECONDARY_EXEC_RDRAND_EXITING
;
5307 static bool vmx_rdseed_supported(void)
5309 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
5310 SECONDARY_EXEC_RDSEED_EXITING
;
5313 static void vmx_compute_secondary_exec_control(struct vcpu_vmx
*vmx
)
5315 struct kvm_vcpu
*vcpu
= &vmx
->vcpu
;
5317 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5318 if (!cpu_need_virtualize_apic_accesses(vcpu
))
5319 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5321 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5323 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5324 enable_unrestricted_guest
= 0;
5325 /* Enable INVPCID for non-ept guests may cause performance regression. */
5326 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5328 if (!enable_unrestricted_guest
)
5329 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5331 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5332 if (!kvm_vcpu_apicv_active(vcpu
))
5333 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5334 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5335 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5336 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5338 We can NOT enable shadow_vmcs here because we don't have yet
5341 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5344 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5346 if (vmx_xsaves_supported()) {
5347 /* Exposing XSAVES only when XSAVE is exposed */
5348 bool xsaves_enabled
=
5349 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVE
) &&
5350 guest_cpuid_has(vcpu
, X86_FEATURE_XSAVES
);
5352 if (!xsaves_enabled
)
5353 exec_control
&= ~SECONDARY_EXEC_XSAVES
;
5357 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5358 SECONDARY_EXEC_XSAVES
;
5360 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5361 ~SECONDARY_EXEC_XSAVES
;
5365 if (vmx_rdtscp_supported()) {
5366 bool rdtscp_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDTSCP
);
5367 if (!rdtscp_enabled
)
5368 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5372 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5373 SECONDARY_EXEC_RDTSCP
;
5375 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5376 ~SECONDARY_EXEC_RDTSCP
;
5380 if (vmx_invpcid_supported()) {
5381 /* Exposing INVPCID only when PCID is exposed */
5382 bool invpcid_enabled
=
5383 guest_cpuid_has(vcpu
, X86_FEATURE_INVPCID
) &&
5384 guest_cpuid_has(vcpu
, X86_FEATURE_PCID
);
5386 if (!invpcid_enabled
) {
5387 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5388 guest_cpuid_clear(vcpu
, X86_FEATURE_INVPCID
);
5392 if (invpcid_enabled
)
5393 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5394 SECONDARY_EXEC_ENABLE_INVPCID
;
5396 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5397 ~SECONDARY_EXEC_ENABLE_INVPCID
;
5401 if (vmx_rdrand_supported()) {
5402 bool rdrand_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDRAND
);
5404 exec_control
&= ~SECONDARY_EXEC_RDRAND_EXITING
;
5408 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5409 SECONDARY_EXEC_RDRAND_EXITING
;
5411 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5412 ~SECONDARY_EXEC_RDRAND_EXITING
;
5416 if (vmx_rdseed_supported()) {
5417 bool rdseed_enabled
= guest_cpuid_has(vcpu
, X86_FEATURE_RDSEED
);
5419 exec_control
&= ~SECONDARY_EXEC_RDSEED_EXITING
;
5423 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
5424 SECONDARY_EXEC_RDSEED_EXITING
;
5426 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
5427 ~SECONDARY_EXEC_RDSEED_EXITING
;
5431 vmx
->secondary_exec_control
= exec_control
;
5434 static void ept_set_mmio_spte_mask(void)
5437 * EPT Misconfigurations can be generated if the value of bits 2:0
5438 * of an EPT paging-structure entry is 110b (write/execute).
5440 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5441 VMX_EPT_MISCONFIG_WX_VALUE
);
5444 #define VMX_XSS_EXIT_BITMAP 0
5446 * Sets up the vmcs for emulated real mode.
5448 static void vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5450 #ifdef CONFIG_X86_64
5456 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5457 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5459 if (enable_shadow_vmcs
) {
5460 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5461 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5463 if (cpu_has_vmx_msr_bitmap())
5464 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5466 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5469 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5470 vmx
->hv_deadline_tsc
= -1;
5472 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5474 if (cpu_has_secondary_exec_ctrls()) {
5475 vmx_compute_secondary_exec_control(vmx
);
5476 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5477 vmx
->secondary_exec_control
);
5480 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5481 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5482 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5483 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5484 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5486 vmcs_write16(GUEST_INTR_STATUS
, 0);
5488 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5489 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5493 vmcs_write32(PLE_GAP
, ple_gap
);
5494 vmx
->ple_window
= ple_window
;
5495 vmx
->ple_window_dirty
= true;
5498 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5499 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5500 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5502 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5503 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5504 vmx_set_constant_host_state(vmx
);
5505 #ifdef CONFIG_X86_64
5506 rdmsrl(MSR_FS_BASE
, a
);
5507 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5508 rdmsrl(MSR_GS_BASE
, a
);
5509 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5511 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5512 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5515 if (cpu_has_vmx_vmfunc())
5516 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
5518 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5519 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5520 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5521 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5522 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5524 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5525 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5527 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5528 u32 index
= vmx_msr_index
[i
];
5529 u32 data_low
, data_high
;
5532 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5534 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5536 vmx
->guest_msrs
[j
].index
= i
;
5537 vmx
->guest_msrs
[j
].data
= 0;
5538 vmx
->guest_msrs
[j
].mask
= -1ull;
5543 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5545 /* 22.2.1, 20.8.1 */
5546 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5548 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5549 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5551 set_cr4_guest_host_mask(vmx
);
5553 if (vmx_xsaves_supported())
5554 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5557 ASSERT(vmx
->pml_pg
);
5558 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5559 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5563 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5565 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5566 struct msr_data apic_base_msr
;
5569 vmx
->rmode
.vm86_active
= 0;
5571 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5572 kvm_set_cr8(vcpu
, 0);
5575 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5576 MSR_IA32_APICBASE_ENABLE
;
5577 if (kvm_vcpu_is_reset_bsp(vcpu
))
5578 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5579 apic_base_msr
.host_initiated
= true;
5580 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5583 vmx_segment_cache_clear(vmx
);
5585 seg_setup(VCPU_SREG_CS
);
5586 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5587 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5589 seg_setup(VCPU_SREG_DS
);
5590 seg_setup(VCPU_SREG_ES
);
5591 seg_setup(VCPU_SREG_FS
);
5592 seg_setup(VCPU_SREG_GS
);
5593 seg_setup(VCPU_SREG_SS
);
5595 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5596 vmcs_writel(GUEST_TR_BASE
, 0);
5597 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5598 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5600 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5601 vmcs_writel(GUEST_LDTR_BASE
, 0);
5602 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5603 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5606 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5607 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5608 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5609 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5612 kvm_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
5613 kvm_rip_write(vcpu
, 0xfff0);
5615 vmcs_writel(GUEST_GDTR_BASE
, 0);
5616 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5618 vmcs_writel(GUEST_IDTR_BASE
, 0);
5619 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5621 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5622 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5623 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5624 if (kvm_mpx_supported())
5625 vmcs_write64(GUEST_BNDCFGS
, 0);
5629 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5631 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5632 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5633 if (cpu_need_tpr_shadow(vcpu
))
5634 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5635 __pa(vcpu
->arch
.apic
->regs
));
5636 vmcs_write32(TPR_THRESHOLD
, 0);
5639 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5642 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5644 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5645 vmx
->vcpu
.arch
.cr0
= cr0
;
5646 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5647 vmx_set_cr4(vcpu
, 0);
5648 vmx_set_efer(vcpu
, 0);
5650 update_exception_bitmap(vcpu
);
5652 vpid_sync_context(vmx
->vpid
);
5656 * In nested virtualization, check if L1 asked to exit on external interrupts.
5657 * For most existing hypervisors, this will always return true.
5659 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5661 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5662 PIN_BASED_EXT_INTR_MASK
;
5666 * In nested virtualization, check if L1 has set
5667 * VM_EXIT_ACK_INTR_ON_EXIT
5669 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5671 return get_vmcs12(vcpu
)->vm_exit_controls
&
5672 VM_EXIT_ACK_INTR_ON_EXIT
;
5675 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5677 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5678 PIN_BASED_NMI_EXITING
;
5681 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5683 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5684 CPU_BASED_VIRTUAL_INTR_PENDING
);
5687 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5690 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5691 enable_irq_window(vcpu
);
5695 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5696 CPU_BASED_VIRTUAL_NMI_PENDING
);
5699 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5701 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5703 int irq
= vcpu
->arch
.interrupt
.nr
;
5705 trace_kvm_inj_virq(irq
);
5707 ++vcpu
->stat
.irq_injections
;
5708 if (vmx
->rmode
.vm86_active
) {
5710 if (vcpu
->arch
.interrupt
.soft
)
5711 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5712 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5713 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5716 intr
= irq
| INTR_INFO_VALID_MASK
;
5717 if (vcpu
->arch
.interrupt
.soft
) {
5718 intr
|= INTR_TYPE_SOFT_INTR
;
5719 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5720 vmx
->vcpu
.arch
.event_exit_inst_len
);
5722 intr
|= INTR_TYPE_EXT_INTR
;
5723 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5726 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5728 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5732 * Tracking the NMI-blocked state in software is built upon
5733 * finding the next open IRQ window. This, in turn, depends on
5734 * well-behaving guests: They have to keep IRQs disabled at
5735 * least as long as the NMI handler runs. Otherwise we may
5736 * cause NMI nesting, maybe breaking the guest. But as this is
5737 * highly unlikely, we can live with the residual risk.
5739 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 1;
5740 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5743 ++vcpu
->stat
.nmi_injections
;
5744 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5746 if (vmx
->rmode
.vm86_active
) {
5747 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5748 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5753 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5756 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5758 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5762 return vmx
->loaded_vmcs
->soft_vnmi_blocked
;
5763 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5765 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5766 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5770 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5772 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5775 if (vmx
->loaded_vmcs
->soft_vnmi_blocked
!= masked
) {
5776 vmx
->loaded_vmcs
->soft_vnmi_blocked
= masked
;
5777 vmx
->loaded_vmcs
->vnmi_blocked_time
= 0;
5780 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5782 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5783 GUEST_INTR_STATE_NMI
);
5785 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5786 GUEST_INTR_STATE_NMI
);
5790 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5792 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5796 to_vmx(vcpu
)->loaded_vmcs
->soft_vnmi_blocked
)
5799 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5800 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5801 | GUEST_INTR_STATE_NMI
));
5804 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5806 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5807 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5808 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5809 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5812 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5816 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5820 kvm
->arch
.tss_addr
= addr
;
5821 return init_rmode_tss(kvm
);
5824 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5829 * Update instruction length as we may reinject the exception
5830 * from user space while in guest debugging mode.
5832 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5833 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5834 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5838 if (vcpu
->guest_debug
&
5839 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5856 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5857 int vec
, u32 err_code
)
5860 * Instruction with address size override prefix opcode 0x67
5861 * Cause the #SS fault with 0 error code in VM86 mode.
5863 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5864 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5865 if (vcpu
->arch
.halt_request
) {
5866 vcpu
->arch
.halt_request
= 0;
5867 return kvm_vcpu_halt(vcpu
);
5875 * Forward all other exceptions that are valid in real mode.
5876 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5877 * the required debugging infrastructure rework.
5879 kvm_queue_exception(vcpu
, vec
);
5884 * Trigger machine check on the host. We assume all the MSRs are already set up
5885 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5886 * We pass a fake environment to the machine check handler because we want
5887 * the guest to be always treated like user space, no matter what context
5888 * it used internally.
5890 static void kvm_machine_check(void)
5892 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5893 struct pt_regs regs
= {
5894 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5895 .flags
= X86_EFLAGS_IF
,
5898 do_machine_check(®s
, 0);
5902 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5904 /* already handled by vcpu_run */
5908 static int handle_exception(struct kvm_vcpu
*vcpu
)
5910 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5911 struct kvm_run
*kvm_run
= vcpu
->run
;
5912 u32 intr_info
, ex_no
, error_code
;
5913 unsigned long cr2
, rip
, dr6
;
5915 enum emulation_result er
;
5917 vect_info
= vmx
->idt_vectoring_info
;
5918 intr_info
= vmx
->exit_intr_info
;
5920 if (is_machine_check(intr_info
))
5921 return handle_machine_check(vcpu
);
5923 if (is_nmi(intr_info
))
5924 return 1; /* already handled by vmx_vcpu_run() */
5926 if (is_invalid_opcode(intr_info
)) {
5927 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5928 if (er
== EMULATE_USER_EXIT
)
5930 if (er
!= EMULATE_DONE
)
5931 kvm_queue_exception(vcpu
, UD_VECTOR
);
5936 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5937 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5940 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5941 * MMIO, it is better to report an internal error.
5942 * See the comments in vmx_handle_exit.
5944 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5945 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5946 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5947 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5948 vcpu
->run
->internal
.ndata
= 3;
5949 vcpu
->run
->internal
.data
[0] = vect_info
;
5950 vcpu
->run
->internal
.data
[1] = intr_info
;
5951 vcpu
->run
->internal
.data
[2] = error_code
;
5955 if (is_page_fault(intr_info
)) {
5956 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5957 /* EPT won't cause page fault directly */
5958 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5959 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0);
5962 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5964 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5965 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5969 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5972 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5973 if (!(vcpu
->guest_debug
&
5974 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5975 vcpu
->arch
.dr6
&= ~15;
5976 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5977 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5978 skip_emulated_instruction(vcpu
);
5980 kvm_queue_exception(vcpu
, DB_VECTOR
);
5983 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5984 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5988 * Update instruction length as we may reinject #BP from
5989 * user space while in guest debugging mode. Reading it for
5990 * #DB as well causes no harm, it is not used in that case.
5992 vmx
->vcpu
.arch
.event_exit_inst_len
=
5993 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5994 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5995 rip
= kvm_rip_read(vcpu
);
5996 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5997 kvm_run
->debug
.arch
.exception
= ex_no
;
6000 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
6001 kvm_run
->ex
.exception
= ex_no
;
6002 kvm_run
->ex
.error_code
= error_code
;
6008 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
6010 ++vcpu
->stat
.irq_exits
;
6014 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
6016 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
6017 vcpu
->mmio_needed
= 0;
6021 static int handle_io(struct kvm_vcpu
*vcpu
)
6023 unsigned long exit_qualification
;
6024 int size
, in
, string
, ret
;
6027 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6028 string
= (exit_qualification
& 16) != 0;
6029 in
= (exit_qualification
& 8) != 0;
6031 ++vcpu
->stat
.io_exits
;
6034 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6036 port
= exit_qualification
>> 16;
6037 size
= (exit_qualification
& 7) + 1;
6039 ret
= kvm_skip_emulated_instruction(vcpu
);
6042 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
6043 * KVM_EXIT_DEBUG here.
6045 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
6049 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
6052 * Patch in the VMCALL instruction:
6054 hypercall
[0] = 0x0f;
6055 hypercall
[1] = 0x01;
6056 hypercall
[2] = 0xc1;
6059 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
6060 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
6062 if (is_guest_mode(vcpu
)) {
6063 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6064 unsigned long orig_val
= val
;
6067 * We get here when L2 changed cr0 in a way that did not change
6068 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
6069 * but did change L0 shadowed bits. So we first calculate the
6070 * effective cr0 value that L1 would like to write into the
6071 * hardware. It consists of the L2-owned bits from the new
6072 * value combined with the L1-owned bits from L1's guest_cr0.
6074 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
6075 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
6077 if (!nested_guest_cr0_valid(vcpu
, val
))
6080 if (kvm_set_cr0(vcpu
, val
))
6082 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
6085 if (to_vmx(vcpu
)->nested
.vmxon
&&
6086 !nested_host_cr0_valid(vcpu
, val
))
6089 return kvm_set_cr0(vcpu
, val
);
6093 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
6095 if (is_guest_mode(vcpu
)) {
6096 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6097 unsigned long orig_val
= val
;
6099 /* analogously to handle_set_cr0 */
6100 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
6101 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
6102 if (kvm_set_cr4(vcpu
, val
))
6104 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
6107 return kvm_set_cr4(vcpu
, val
);
6110 static int handle_cr(struct kvm_vcpu
*vcpu
)
6112 unsigned long exit_qualification
, val
;
6118 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6119 cr
= exit_qualification
& 15;
6120 reg
= (exit_qualification
>> 8) & 15;
6121 switch ((exit_qualification
>> 4) & 3) {
6122 case 0: /* mov to cr */
6123 val
= kvm_register_readl(vcpu
, reg
);
6124 trace_kvm_cr_write(cr
, val
);
6127 err
= handle_set_cr0(vcpu
, val
);
6128 return kvm_complete_insn_gp(vcpu
, err
);
6130 err
= kvm_set_cr3(vcpu
, val
);
6131 return kvm_complete_insn_gp(vcpu
, err
);
6133 err
= handle_set_cr4(vcpu
, val
);
6134 return kvm_complete_insn_gp(vcpu
, err
);
6136 u8 cr8_prev
= kvm_get_cr8(vcpu
);
6138 err
= kvm_set_cr8(vcpu
, cr8
);
6139 ret
= kvm_complete_insn_gp(vcpu
, err
);
6140 if (lapic_in_kernel(vcpu
))
6142 if (cr8_prev
<= cr8
)
6145 * TODO: we might be squashing a
6146 * KVM_GUESTDBG_SINGLESTEP-triggered
6147 * KVM_EXIT_DEBUG here.
6149 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
6155 WARN_ONCE(1, "Guest should always own CR0.TS");
6156 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
6157 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
6158 return kvm_skip_emulated_instruction(vcpu
);
6159 case 1: /*mov from cr*/
6162 val
= kvm_read_cr3(vcpu
);
6163 kvm_register_write(vcpu
, reg
, val
);
6164 trace_kvm_cr_read(cr
, val
);
6165 return kvm_skip_emulated_instruction(vcpu
);
6167 val
= kvm_get_cr8(vcpu
);
6168 kvm_register_write(vcpu
, reg
, val
);
6169 trace_kvm_cr_read(cr
, val
);
6170 return kvm_skip_emulated_instruction(vcpu
);
6174 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6175 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6176 kvm_lmsw(vcpu
, val
);
6178 return kvm_skip_emulated_instruction(vcpu
);
6182 vcpu
->run
->exit_reason
= 0;
6183 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6184 (int)(exit_qualification
>> 4) & 3, cr
);
6188 static int handle_dr(struct kvm_vcpu
*vcpu
)
6190 unsigned long exit_qualification
;
6193 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6194 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6196 /* First, if DR does not exist, trigger UD */
6197 if (!kvm_require_dr(vcpu
, dr
))
6200 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6201 if (!kvm_require_cpl(vcpu
, 0))
6203 dr7
= vmcs_readl(GUEST_DR7
);
6206 * As the vm-exit takes precedence over the debug trap, we
6207 * need to emulate the latter, either for the host or the
6208 * guest debugging itself.
6210 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6211 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6212 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6213 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6214 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6215 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6218 vcpu
->arch
.dr6
&= ~15;
6219 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6220 kvm_queue_exception(vcpu
, DB_VECTOR
);
6225 if (vcpu
->guest_debug
== 0) {
6226 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6227 CPU_BASED_MOV_DR_EXITING
);
6230 * No more DR vmexits; force a reload of the debug registers
6231 * and reenter on this instruction. The next vmexit will
6232 * retrieve the full state of the debug registers.
6234 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6238 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6239 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6242 if (kvm_get_dr(vcpu
, dr
, &val
))
6244 kvm_register_write(vcpu
, reg
, val
);
6246 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6249 return kvm_skip_emulated_instruction(vcpu
);
6252 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6254 return vcpu
->arch
.dr6
;
6257 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6261 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6263 get_debugreg(vcpu
->arch
.db
[0], 0);
6264 get_debugreg(vcpu
->arch
.db
[1], 1);
6265 get_debugreg(vcpu
->arch
.db
[2], 2);
6266 get_debugreg(vcpu
->arch
.db
[3], 3);
6267 get_debugreg(vcpu
->arch
.dr6
, 6);
6268 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6270 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6271 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6274 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6276 vmcs_writel(GUEST_DR7
, val
);
6279 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6281 return kvm_emulate_cpuid(vcpu
);
6284 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6286 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6287 struct msr_data msr_info
;
6289 msr_info
.index
= ecx
;
6290 msr_info
.host_initiated
= false;
6291 if (vmx_get_msr(vcpu
, &msr_info
)) {
6292 trace_kvm_msr_read_ex(ecx
);
6293 kvm_inject_gp(vcpu
, 0);
6297 trace_kvm_msr_read(ecx
, msr_info
.data
);
6299 /* FIXME: handling of bits 32:63 of rax, rdx */
6300 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6301 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6302 return kvm_skip_emulated_instruction(vcpu
);
6305 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6307 struct msr_data msr
;
6308 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6309 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6310 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6314 msr
.host_initiated
= false;
6315 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6316 trace_kvm_msr_write_ex(ecx
, data
);
6317 kvm_inject_gp(vcpu
, 0);
6321 trace_kvm_msr_write(ecx
, data
);
6322 return kvm_skip_emulated_instruction(vcpu
);
6325 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6327 kvm_apic_update_ppr(vcpu
);
6331 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6333 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6334 CPU_BASED_VIRTUAL_INTR_PENDING
);
6336 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6338 ++vcpu
->stat
.irq_window_exits
;
6342 static int handle_halt(struct kvm_vcpu
*vcpu
)
6344 return kvm_emulate_halt(vcpu
);
6347 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6349 return kvm_emulate_hypercall(vcpu
);
6352 static int handle_invd(struct kvm_vcpu
*vcpu
)
6354 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6357 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6359 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6361 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6362 return kvm_skip_emulated_instruction(vcpu
);
6365 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6369 err
= kvm_rdpmc(vcpu
);
6370 return kvm_complete_insn_gp(vcpu
, err
);
6373 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6375 return kvm_emulate_wbinvd(vcpu
);
6378 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6380 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6381 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6383 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6384 return kvm_skip_emulated_instruction(vcpu
);
6388 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6390 kvm_skip_emulated_instruction(vcpu
);
6391 WARN(1, "this should never happen\n");
6395 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6397 kvm_skip_emulated_instruction(vcpu
);
6398 WARN(1, "this should never happen\n");
6402 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6404 if (likely(fasteoi
)) {
6405 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6406 int access_type
, offset
;
6408 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6409 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6411 * Sane guest uses MOV to write EOI, with written value
6412 * not cared. So make a short-circuit here by avoiding
6413 * heavy instruction emulation.
6415 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6416 (offset
== APIC_EOI
)) {
6417 kvm_lapic_set_eoi(vcpu
);
6418 return kvm_skip_emulated_instruction(vcpu
);
6421 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6424 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6426 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6427 int vector
= exit_qualification
& 0xff;
6429 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6430 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6434 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6436 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6437 u32 offset
= exit_qualification
& 0xfff;
6439 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6440 kvm_apic_write_nodecode(vcpu
, offset
);
6444 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6446 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6447 unsigned long exit_qualification
;
6448 bool has_error_code
= false;
6451 int reason
, type
, idt_v
, idt_index
;
6453 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6454 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6455 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6457 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6459 reason
= (u32
)exit_qualification
>> 30;
6460 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6462 case INTR_TYPE_NMI_INTR
:
6463 vcpu
->arch
.nmi_injected
= false;
6464 vmx_set_nmi_mask(vcpu
, true);
6466 case INTR_TYPE_EXT_INTR
:
6467 case INTR_TYPE_SOFT_INTR
:
6468 kvm_clear_interrupt_queue(vcpu
);
6470 case INTR_TYPE_HARD_EXCEPTION
:
6471 if (vmx
->idt_vectoring_info
&
6472 VECTORING_INFO_DELIVER_CODE_MASK
) {
6473 has_error_code
= true;
6475 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6478 case INTR_TYPE_SOFT_EXCEPTION
:
6479 kvm_clear_exception_queue(vcpu
);
6485 tss_selector
= exit_qualification
;
6487 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6488 type
!= INTR_TYPE_EXT_INTR
&&
6489 type
!= INTR_TYPE_NMI_INTR
))
6490 skip_emulated_instruction(vcpu
);
6492 if (kvm_task_switch(vcpu
, tss_selector
,
6493 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6494 has_error_code
, error_code
) == EMULATE_FAIL
) {
6495 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6496 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6497 vcpu
->run
->internal
.ndata
= 0;
6502 * TODO: What about debug traps on tss switch?
6503 * Are we supposed to inject them and update dr6?
6509 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6511 unsigned long exit_qualification
;
6515 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6518 * EPT violation happened while executing iret from NMI,
6519 * "blocked by NMI" bit has to be set before next VM entry.
6520 * There are errata that may cause this bit to not be set:
6523 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6525 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6526 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6528 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6529 trace_kvm_page_fault(gpa
, exit_qualification
);
6531 /* Is it a read fault? */
6532 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6533 ? PFERR_USER_MASK
: 0;
6534 /* Is it a write fault? */
6535 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6536 ? PFERR_WRITE_MASK
: 0;
6537 /* Is it a fetch fault? */
6538 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6539 ? PFERR_FETCH_MASK
: 0;
6540 /* ept page table entry is present? */
6541 error_code
|= (exit_qualification
&
6542 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6543 EPT_VIOLATION_EXECUTABLE
))
6544 ? PFERR_PRESENT_MASK
: 0;
6546 error_code
|= (exit_qualification
& 0x100) != 0 ?
6547 PFERR_GUEST_FINAL_MASK
: PFERR_GUEST_PAGE_MASK
;
6549 vcpu
->arch
.exit_qualification
= exit_qualification
;
6550 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6553 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6559 * A nested guest cannot optimize MMIO vmexits, because we have an
6560 * nGPA here instead of the required GPA.
6562 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6563 if (!is_guest_mode(vcpu
) &&
6564 !kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6565 trace_kvm_fast_mmio(gpa
);
6566 return kvm_skip_emulated_instruction(vcpu
);
6569 ret
= kvm_mmu_page_fault(vcpu
, gpa
, PFERR_RSVD_MASK
, NULL
, 0);
6573 /* It is the real ept misconfig */
6576 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6577 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6582 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6584 WARN_ON_ONCE(!enable_vnmi
);
6585 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6586 CPU_BASED_VIRTUAL_NMI_PENDING
);
6587 ++vcpu
->stat
.nmi_window_exits
;
6588 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6593 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6595 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6596 enum emulation_result err
= EMULATE_DONE
;
6599 bool intr_window_requested
;
6600 unsigned count
= 130;
6602 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6603 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6605 while (vmx
->emulation_required
&& count
-- != 0) {
6606 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6607 return handle_interrupt_window(&vmx
->vcpu
);
6609 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6612 err
= emulate_instruction(vcpu
, 0);
6614 if (err
== EMULATE_USER_EXIT
) {
6615 ++vcpu
->stat
.mmio_exits
;
6620 if (err
!= EMULATE_DONE
) {
6621 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6622 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6623 vcpu
->run
->internal
.ndata
= 0;
6627 if (vcpu
->arch
.halt_request
) {
6628 vcpu
->arch
.halt_request
= 0;
6629 ret
= kvm_vcpu_halt(vcpu
);
6633 if (signal_pending(current
))
6643 static int __grow_ple_window(int val
)
6645 if (ple_window_grow
< 1)
6648 val
= min(val
, ple_window_actual_max
);
6650 if (ple_window_grow
< ple_window
)
6651 val
*= ple_window_grow
;
6653 val
+= ple_window_grow
;
6658 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6663 if (modifier
< ple_window
)
6668 return max(val
, minimum
);
6671 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6673 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6674 int old
= vmx
->ple_window
;
6676 vmx
->ple_window
= __grow_ple_window(old
);
6678 if (vmx
->ple_window
!= old
)
6679 vmx
->ple_window_dirty
= true;
6681 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6684 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6686 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6687 int old
= vmx
->ple_window
;
6689 vmx
->ple_window
= __shrink_ple_window(old
,
6690 ple_window_shrink
, ple_window
);
6692 if (vmx
->ple_window
!= old
)
6693 vmx
->ple_window_dirty
= true;
6695 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6699 * ple_window_actual_max is computed to be one grow_ple_window() below
6700 * ple_window_max. (See __grow_ple_window for the reason.)
6701 * This prevents overflows, because ple_window_max is int.
6702 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6704 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6706 static void update_ple_window_actual_max(void)
6708 ple_window_actual_max
=
6709 __shrink_ple_window(max(ple_window_max
, ple_window
),
6710 ple_window_grow
, INT_MIN
);
6714 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6716 static void wakeup_handler(void)
6718 struct kvm_vcpu
*vcpu
;
6719 int cpu
= smp_processor_id();
6721 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6722 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6723 blocked_vcpu_list
) {
6724 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6726 if (pi_test_on(pi_desc
) == 1)
6727 kvm_vcpu_kick(vcpu
);
6729 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6732 void vmx_enable_tdp(void)
6734 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6735 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6736 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6737 0ull, VMX_EPT_EXECUTABLE_MASK
,
6738 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6739 VMX_EPT_RWX_MASK
, 0ull);
6741 ept_set_mmio_spte_mask();
6745 static __init
int hardware_setup(void)
6747 int r
= -ENOMEM
, i
, msr
;
6749 rdmsrl_safe(MSR_EFER
, &host_efer
);
6751 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6752 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6754 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6755 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6760 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6761 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6763 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6765 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6767 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6768 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6770 if (setup_vmcs_config(&vmcs_config
) < 0) {
6775 if (boot_cpu_has(X86_FEATURE_NX
))
6776 kvm_enable_efer_bits(EFER_NX
);
6778 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6779 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6782 if (!cpu_has_vmx_shadow_vmcs())
6783 enable_shadow_vmcs
= 0;
6784 if (enable_shadow_vmcs
)
6785 init_vmcs_shadow_fields();
6787 if (!cpu_has_vmx_ept() ||
6788 !cpu_has_vmx_ept_4levels() ||
6789 !cpu_has_vmx_ept_mt_wb() ||
6790 !cpu_has_vmx_invept_global())
6793 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6794 enable_ept_ad_bits
= 0;
6796 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept
)
6797 enable_unrestricted_guest
= 0;
6799 if (!cpu_has_vmx_flexpriority())
6800 flexpriority_enabled
= 0;
6802 if (!cpu_has_virtual_nmis())
6806 * set_apic_access_page_addr() is used to reload apic access
6807 * page upon invalidation. No need to do anything if not
6808 * using the APIC_ACCESS_ADDR VMCS field.
6810 if (!flexpriority_enabled
)
6811 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6813 if (!cpu_has_vmx_tpr_shadow())
6814 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6816 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6817 kvm_disable_largepages();
6819 if (!cpu_has_vmx_ple()) {
6822 ple_window_grow
= 0;
6824 ple_window_shrink
= 0;
6827 if (!cpu_has_vmx_apicv()) {
6829 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6832 if (cpu_has_vmx_tsc_scaling()) {
6833 kvm_has_tsc_control
= true;
6834 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6835 kvm_tsc_scaling_ratio_frac_bits
= 48;
6838 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6839 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6840 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6841 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6842 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6843 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6845 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6846 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6847 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6848 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6849 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6850 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6851 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6852 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6854 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6856 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6857 if (msr
== 0x839 /* TMCCT */)
6859 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6863 * TPR reads and writes can be virtualized even if virtual interrupt
6864 * delivery is not in use.
6866 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6867 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6870 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6872 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6879 update_ple_window_actual_max();
6882 * Only enable PML when hardware supports PML feature, and both EPT
6883 * and EPT A/D bit features are enabled -- PML depends on them to work.
6885 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6889 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6890 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6891 kvm_x86_ops
->flush_log_dirty
= NULL
;
6892 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6895 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6898 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6899 cpu_preemption_timer_multi
=
6900 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6902 kvm_x86_ops
->set_hv_timer
= NULL
;
6903 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6906 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6908 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6910 return alloc_kvm_area();
6913 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6914 free_page((unsigned long)vmx_bitmap
[i
]);
6919 static __exit
void hardware_unsetup(void)
6923 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6924 free_page((unsigned long)vmx_bitmap
[i
]);
6930 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6931 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6933 static int handle_pause(struct kvm_vcpu
*vcpu
)
6936 grow_ple_window(vcpu
);
6939 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
6940 * VM-execution control is ignored if CPL > 0. OTOH, KVM
6941 * never set PAUSE_EXITING and just set PLE if supported,
6942 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
6944 kvm_vcpu_on_spin(vcpu
, true);
6945 return kvm_skip_emulated_instruction(vcpu
);
6948 static int handle_nop(struct kvm_vcpu
*vcpu
)
6950 return kvm_skip_emulated_instruction(vcpu
);
6953 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6955 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6956 return handle_nop(vcpu
);
6959 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
6961 kvm_queue_exception(vcpu
, UD_VECTOR
);
6965 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6970 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6972 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6973 return handle_nop(vcpu
);
6977 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6978 * We could reuse a single VMCS for all the L2 guests, but we also want the
6979 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6980 * allows keeping them loaded on the processor, and in the future will allow
6981 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6982 * every entry if they never change.
6983 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6984 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6986 * The following functions allocate and free a vmcs02 in this pool.
6989 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6990 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6992 struct vmcs02_list
*item
;
6993 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6994 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6995 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6996 return &item
->vmcs02
;
6999 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
7000 /* Recycle the least recently used VMCS. */
7001 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
7002 struct vmcs02_list
, list
);
7003 item
->vmptr
= vmx
->nested
.current_vmptr
;
7004 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
7005 return &item
->vmcs02
;
7008 /* Create a new VMCS */
7009 item
= kzalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
7012 item
->vmcs02
.vmcs
= alloc_vmcs();
7013 item
->vmcs02
.shadow_vmcs
= NULL
;
7014 if (!item
->vmcs02
.vmcs
) {
7018 loaded_vmcs_init(&item
->vmcs02
);
7019 item
->vmptr
= vmx
->nested
.current_vmptr
;
7020 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
7021 vmx
->nested
.vmcs02_num
++;
7022 return &item
->vmcs02
;
7025 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
7026 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7028 struct vmcs02_list
*item
;
7029 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
7030 if (item
->vmptr
== vmptr
) {
7031 free_loaded_vmcs(&item
->vmcs02
);
7032 list_del(&item
->list
);
7034 vmx
->nested
.vmcs02_num
--;
7040 * Free all VMCSs saved for this vcpu, except the one pointed by
7041 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
7042 * must be &vmx->vmcs01.
7044 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
7046 struct vmcs02_list
*item
, *n
;
7048 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
7049 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
7051 * Something will leak if the above WARN triggers. Better than
7054 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
7057 free_loaded_vmcs(&item
->vmcs02
);
7058 list_del(&item
->list
);
7060 vmx
->nested
.vmcs02_num
--;
7065 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
7066 * set the success or error code of an emulated VMX instruction, as specified
7067 * by Vol 2B, VMX Instruction Reference, "Conventions".
7069 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
7071 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
7072 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7073 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
7076 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
7078 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7079 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
7080 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7084 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
7085 u32 vm_instruction_error
)
7087 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
7089 * failValid writes the error number to the current VMCS, which
7090 * can't be done there isn't a current VMCS.
7092 nested_vmx_failInvalid(vcpu
);
7095 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
7096 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
7097 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
7099 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
7101 * We don't need to force a shadow sync because
7102 * VM_INSTRUCTION_ERROR is not shadowed
7106 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
7108 /* TODO: not to reset guest simply here. */
7109 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
7110 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
7113 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
7115 struct vcpu_vmx
*vmx
=
7116 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
7118 vmx
->nested
.preemption_timer_expired
= true;
7119 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
7120 kvm_vcpu_kick(&vmx
->vcpu
);
7122 return HRTIMER_NORESTART
;
7126 * Decode the memory-address operand of a vmx instruction, as recorded on an
7127 * exit caused by such an instruction (run by a guest hypervisor).
7128 * On success, returns 0. When the operand is invalid, returns 1 and throws
7131 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
7132 unsigned long exit_qualification
,
7133 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
7137 struct kvm_segment s
;
7140 * According to Vol. 3B, "Information for VM Exits Due to Instruction
7141 * Execution", on an exit, vmx_instruction_info holds most of the
7142 * addressing components of the operand. Only the displacement part
7143 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
7144 * For how an actual address is calculated from all these components,
7145 * refer to Vol. 1, "Operand Addressing".
7147 int scaling
= vmx_instruction_info
& 3;
7148 int addr_size
= (vmx_instruction_info
>> 7) & 7;
7149 bool is_reg
= vmx_instruction_info
& (1u << 10);
7150 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
7151 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
7152 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
7153 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
7154 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
7157 kvm_queue_exception(vcpu
, UD_VECTOR
);
7161 /* Addr = segment_base + offset */
7162 /* offset = base + [index * scale] + displacement */
7163 off
= exit_qualification
; /* holds the displacement */
7165 off
+= kvm_register_read(vcpu
, base_reg
);
7167 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
7168 vmx_get_segment(vcpu
, &s
, seg_reg
);
7169 *ret
= s
.base
+ off
;
7171 if (addr_size
== 1) /* 32 bit */
7174 /* Checks for #GP/#SS exceptions. */
7176 if (is_long_mode(vcpu
)) {
7177 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7178 * non-canonical form. This is the only check on the memory
7179 * destination for long mode!
7181 exn
= is_noncanonical_address(*ret
, vcpu
);
7182 } else if (is_protmode(vcpu
)) {
7183 /* Protected mode: apply checks for segment validity in the
7185 * - segment type check (#GP(0) may be thrown)
7186 * - usability check (#GP(0)/#SS(0))
7187 * - limit check (#GP(0)/#SS(0))
7190 /* #GP(0) if the destination operand is located in a
7191 * read-only data segment or any code segment.
7193 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7195 /* #GP(0) if the source operand is located in an
7196 * execute-only code segment
7198 exn
= ((s
.type
& 0xa) == 8);
7200 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7203 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7205 exn
= (s
.unusable
!= 0);
7206 /* Protected mode: #GP(0)/#SS(0) if the memory
7207 * operand is outside the segment limit.
7209 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7212 kvm_queue_exception_e(vcpu
,
7213 seg_reg
== VCPU_SREG_SS
?
7214 SS_VECTOR
: GP_VECTOR
,
7222 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7225 struct x86_exception e
;
7227 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7228 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7231 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7232 sizeof(*vmpointer
), &e
)) {
7233 kvm_inject_page_fault(vcpu
, &e
);
7240 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7242 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7243 struct vmcs
*shadow_vmcs
;
7245 if (cpu_has_vmx_msr_bitmap()) {
7246 vmx
->nested
.msr_bitmap
=
7247 (unsigned long *)__get_free_page(GFP_KERNEL
);
7248 if (!vmx
->nested
.msr_bitmap
)
7249 goto out_msr_bitmap
;
7252 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7253 if (!vmx
->nested
.cached_vmcs12
)
7254 goto out_cached_vmcs12
;
7256 if (enable_shadow_vmcs
) {
7257 shadow_vmcs
= alloc_vmcs();
7259 goto out_shadow_vmcs
;
7260 /* mark vmcs as shadow */
7261 shadow_vmcs
->revision_id
|= (1u << 31);
7262 /* init shadow vmcs */
7263 vmcs_clear(shadow_vmcs
);
7264 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7267 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7268 vmx
->nested
.vmcs02_num
= 0;
7270 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7271 HRTIMER_MODE_REL_PINNED
);
7272 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7274 vmx
->nested
.vmxon
= true;
7278 kfree(vmx
->nested
.cached_vmcs12
);
7281 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7288 * Emulate the VMXON instruction.
7289 * Currently, we just remember that VMX is active, and do not save or even
7290 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7291 * do not currently need to store anything in that guest-allocated memory
7292 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7293 * argument is different from the VMXON pointer (which the spec says they do).
7295 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7300 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7301 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7302 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7305 * The Intel VMX Instruction Reference lists a bunch of bits that are
7306 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7307 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7308 * Otherwise, we should fail with #UD. But most faulting conditions
7309 * have already been checked by hardware, prior to the VM-exit for
7310 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7311 * that bit set to 1 in non-root mode.
7313 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7314 kvm_queue_exception(vcpu
, UD_VECTOR
);
7318 if (vmx
->nested
.vmxon
) {
7319 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7320 return kvm_skip_emulated_instruction(vcpu
);
7323 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7324 != VMXON_NEEDED_FEATURES
) {
7325 kvm_inject_gp(vcpu
, 0);
7329 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7334 * The first 4 bytes of VMXON region contain the supported
7335 * VMCS revision identifier
7337 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7338 * which replaces physical address width with 32
7340 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7341 nested_vmx_failInvalid(vcpu
);
7342 return kvm_skip_emulated_instruction(vcpu
);
7345 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7346 if (is_error_page(page
)) {
7347 nested_vmx_failInvalid(vcpu
);
7348 return kvm_skip_emulated_instruction(vcpu
);
7350 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7352 kvm_release_page_clean(page
);
7353 nested_vmx_failInvalid(vcpu
);
7354 return kvm_skip_emulated_instruction(vcpu
);
7357 kvm_release_page_clean(page
);
7359 vmx
->nested
.vmxon_ptr
= vmptr
;
7360 ret
= enter_vmx_operation(vcpu
);
7364 nested_vmx_succeed(vcpu
);
7365 return kvm_skip_emulated_instruction(vcpu
);
7369 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7370 * for running VMX instructions (except VMXON, whose prerequisites are
7371 * slightly different). It also specifies what exception to inject otherwise.
7372 * Note that many of these exceptions have priority over VM exits, so they
7373 * don't have to be checked again here.
7375 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7377 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7378 kvm_queue_exception(vcpu
, UD_VECTOR
);
7384 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7386 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7387 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7390 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7392 if (vmx
->nested
.current_vmptr
== -1ull)
7395 if (enable_shadow_vmcs
) {
7396 /* copy to memory all shadowed fields in case
7397 they were modified */
7398 copy_shadow_to_vmcs12(vmx
);
7399 vmx
->nested
.sync_shadow_vmcs
= false;
7400 vmx_disable_shadow_vmcs(vmx
);
7402 vmx
->nested
.posted_intr_nv
= -1;
7404 /* Flush VMCS12 to guest memory */
7405 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7406 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7407 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7409 vmx
->nested
.current_vmptr
= -1ull;
7413 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7414 * just stops using VMX.
7416 static void free_nested(struct vcpu_vmx
*vmx
)
7418 if (!vmx
->nested
.vmxon
&& !vmx
->nested
.smm
.vmxon
)
7421 vmx
->nested
.vmxon
= false;
7422 vmx
->nested
.smm
.vmxon
= false;
7423 free_vpid(vmx
->nested
.vpid02
);
7424 vmx
->nested
.posted_intr_nv
= -1;
7425 vmx
->nested
.current_vmptr
= -1ull;
7426 if (vmx
->nested
.msr_bitmap
) {
7427 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7428 vmx
->nested
.msr_bitmap
= NULL
;
7430 if (enable_shadow_vmcs
) {
7431 vmx_disable_shadow_vmcs(vmx
);
7432 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7433 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7434 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7436 kfree(vmx
->nested
.cached_vmcs12
);
7437 /* Unpin physical memory we referred to in current vmcs02 */
7438 if (vmx
->nested
.apic_access_page
) {
7439 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
7440 vmx
->nested
.apic_access_page
= NULL
;
7442 if (vmx
->nested
.virtual_apic_page
) {
7443 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
7444 vmx
->nested
.virtual_apic_page
= NULL
;
7446 if (vmx
->nested
.pi_desc_page
) {
7447 kunmap(vmx
->nested
.pi_desc_page
);
7448 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
7449 vmx
->nested
.pi_desc_page
= NULL
;
7450 vmx
->nested
.pi_desc
= NULL
;
7453 nested_free_all_saved_vmcss(vmx
);
7456 /* Emulate the VMXOFF instruction */
7457 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7459 if (!nested_vmx_check_permission(vcpu
))
7461 free_nested(to_vmx(vcpu
));
7462 nested_vmx_succeed(vcpu
);
7463 return kvm_skip_emulated_instruction(vcpu
);
7466 /* Emulate the VMCLEAR instruction */
7467 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7469 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7473 if (!nested_vmx_check_permission(vcpu
))
7476 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7479 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7480 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7481 return kvm_skip_emulated_instruction(vcpu
);
7484 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7485 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7486 return kvm_skip_emulated_instruction(vcpu
);
7489 if (vmptr
== vmx
->nested
.current_vmptr
)
7490 nested_release_vmcs12(vmx
);
7492 kvm_vcpu_write_guest(vcpu
,
7493 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7494 &zero
, sizeof(zero
));
7496 nested_free_vmcs02(vmx
, vmptr
);
7498 nested_vmx_succeed(vcpu
);
7499 return kvm_skip_emulated_instruction(vcpu
);
7502 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7504 /* Emulate the VMLAUNCH instruction */
7505 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7507 return nested_vmx_run(vcpu
, true);
7510 /* Emulate the VMRESUME instruction */
7511 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7514 return nested_vmx_run(vcpu
, false);
7518 * Read a vmcs12 field. Since these can have varying lengths and we return
7519 * one type, we chose the biggest type (u64) and zero-extend the return value
7520 * to that size. Note that the caller, handle_vmread, might need to use only
7521 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7522 * 64-bit fields are to be returned).
7524 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7525 unsigned long field
, u64
*ret
)
7527 short offset
= vmcs_field_to_offset(field
);
7533 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7535 switch (vmcs_field_type(field
)) {
7536 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7537 *ret
= *((natural_width
*)p
);
7539 case VMCS_FIELD_TYPE_U16
:
7542 case VMCS_FIELD_TYPE_U32
:
7545 case VMCS_FIELD_TYPE_U64
:
7555 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7556 unsigned long field
, u64 field_value
){
7557 short offset
= vmcs_field_to_offset(field
);
7558 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7562 switch (vmcs_field_type(field
)) {
7563 case VMCS_FIELD_TYPE_U16
:
7564 *(u16
*)p
= field_value
;
7566 case VMCS_FIELD_TYPE_U32
:
7567 *(u32
*)p
= field_value
;
7569 case VMCS_FIELD_TYPE_U64
:
7570 *(u64
*)p
= field_value
;
7572 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7573 *(natural_width
*)p
= field_value
;
7582 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7585 unsigned long field
;
7587 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7588 const unsigned long *fields
= shadow_read_write_fields
;
7589 const int num_fields
= max_shadow_read_write_fields
;
7593 vmcs_load(shadow_vmcs
);
7595 for (i
= 0; i
< num_fields
; i
++) {
7597 switch (vmcs_field_type(field
)) {
7598 case VMCS_FIELD_TYPE_U16
:
7599 field_value
= vmcs_read16(field
);
7601 case VMCS_FIELD_TYPE_U32
:
7602 field_value
= vmcs_read32(field
);
7604 case VMCS_FIELD_TYPE_U64
:
7605 field_value
= vmcs_read64(field
);
7607 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7608 field_value
= vmcs_readl(field
);
7614 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7617 vmcs_clear(shadow_vmcs
);
7618 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7623 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7625 const unsigned long *fields
[] = {
7626 shadow_read_write_fields
,
7627 shadow_read_only_fields
7629 const int max_fields
[] = {
7630 max_shadow_read_write_fields
,
7631 max_shadow_read_only_fields
7634 unsigned long field
;
7635 u64 field_value
= 0;
7636 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7638 vmcs_load(shadow_vmcs
);
7640 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7641 for (i
= 0; i
< max_fields
[q
]; i
++) {
7642 field
= fields
[q
][i
];
7643 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7645 switch (vmcs_field_type(field
)) {
7646 case VMCS_FIELD_TYPE_U16
:
7647 vmcs_write16(field
, (u16
)field_value
);
7649 case VMCS_FIELD_TYPE_U32
:
7650 vmcs_write32(field
, (u32
)field_value
);
7652 case VMCS_FIELD_TYPE_U64
:
7653 vmcs_write64(field
, (u64
)field_value
);
7655 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7656 vmcs_writel(field
, (long)field_value
);
7665 vmcs_clear(shadow_vmcs
);
7666 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7670 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7671 * used before) all generate the same failure when it is missing.
7673 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7675 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7676 if (vmx
->nested
.current_vmptr
== -1ull) {
7677 nested_vmx_failInvalid(vcpu
);
7683 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7685 unsigned long field
;
7687 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7688 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7691 if (!nested_vmx_check_permission(vcpu
))
7694 if (!nested_vmx_check_vmcs12(vcpu
))
7695 return kvm_skip_emulated_instruction(vcpu
);
7697 /* Decode instruction info and find the field to read */
7698 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7699 /* Read the field, zero-extended to a u64 field_value */
7700 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7701 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7702 return kvm_skip_emulated_instruction(vcpu
);
7705 * Now copy part of this value to register or memory, as requested.
7706 * Note that the number of bits actually copied is 32 or 64 depending
7707 * on the guest's mode (32 or 64 bit), not on the given field's length.
7709 if (vmx_instruction_info
& (1u << 10)) {
7710 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7713 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7714 vmx_instruction_info
, true, &gva
))
7716 /* _system ok, as hardware has verified cpl=0 */
7717 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7718 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7721 nested_vmx_succeed(vcpu
);
7722 return kvm_skip_emulated_instruction(vcpu
);
7726 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7728 unsigned long field
;
7730 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7731 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7732 /* The value to write might be 32 or 64 bits, depending on L1's long
7733 * mode, and eventually we need to write that into a field of several
7734 * possible lengths. The code below first zero-extends the value to 64
7735 * bit (field_value), and then copies only the appropriate number of
7736 * bits into the vmcs12 field.
7738 u64 field_value
= 0;
7739 struct x86_exception e
;
7741 if (!nested_vmx_check_permission(vcpu
))
7744 if (!nested_vmx_check_vmcs12(vcpu
))
7745 return kvm_skip_emulated_instruction(vcpu
);
7747 if (vmx_instruction_info
& (1u << 10))
7748 field_value
= kvm_register_readl(vcpu
,
7749 (((vmx_instruction_info
) >> 3) & 0xf));
7751 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7752 vmx_instruction_info
, false, &gva
))
7754 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7755 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7756 kvm_inject_page_fault(vcpu
, &e
);
7762 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7763 if (vmcs_field_readonly(field
)) {
7764 nested_vmx_failValid(vcpu
,
7765 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7766 return kvm_skip_emulated_instruction(vcpu
);
7769 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7770 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7771 return kvm_skip_emulated_instruction(vcpu
);
7774 nested_vmx_succeed(vcpu
);
7775 return kvm_skip_emulated_instruction(vcpu
);
7778 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7780 vmx
->nested
.current_vmptr
= vmptr
;
7781 if (enable_shadow_vmcs
) {
7782 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7783 SECONDARY_EXEC_SHADOW_VMCS
);
7784 vmcs_write64(VMCS_LINK_POINTER
,
7785 __pa(vmx
->vmcs01
.shadow_vmcs
));
7786 vmx
->nested
.sync_shadow_vmcs
= true;
7790 /* Emulate the VMPTRLD instruction */
7791 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7793 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7796 if (!nested_vmx_check_permission(vcpu
))
7799 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7802 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7803 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7804 return kvm_skip_emulated_instruction(vcpu
);
7807 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7808 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7809 return kvm_skip_emulated_instruction(vcpu
);
7812 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7813 struct vmcs12
*new_vmcs12
;
7815 page
= kvm_vcpu_gpa_to_page(vcpu
, vmptr
);
7816 if (is_error_page(page
)) {
7817 nested_vmx_failInvalid(vcpu
);
7818 return kvm_skip_emulated_instruction(vcpu
);
7820 new_vmcs12
= kmap(page
);
7821 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7823 kvm_release_page_clean(page
);
7824 nested_vmx_failValid(vcpu
,
7825 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7826 return kvm_skip_emulated_instruction(vcpu
);
7829 nested_release_vmcs12(vmx
);
7831 * Load VMCS12 from guest memory since it is not already
7834 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7836 kvm_release_page_clean(page
);
7838 set_current_vmptr(vmx
, vmptr
);
7841 nested_vmx_succeed(vcpu
);
7842 return kvm_skip_emulated_instruction(vcpu
);
7845 /* Emulate the VMPTRST instruction */
7846 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7848 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7849 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7851 struct x86_exception e
;
7853 if (!nested_vmx_check_permission(vcpu
))
7856 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7857 vmx_instruction_info
, true, &vmcs_gva
))
7859 /* ok to use *_system, as hardware has verified cpl=0 */
7860 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7861 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7863 kvm_inject_page_fault(vcpu
, &e
);
7866 nested_vmx_succeed(vcpu
);
7867 return kvm_skip_emulated_instruction(vcpu
);
7870 /* Emulate the INVEPT instruction */
7871 static int handle_invept(struct kvm_vcpu
*vcpu
)
7873 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7874 u32 vmx_instruction_info
, types
;
7877 struct x86_exception e
;
7882 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7883 SECONDARY_EXEC_ENABLE_EPT
) ||
7884 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7885 kvm_queue_exception(vcpu
, UD_VECTOR
);
7889 if (!nested_vmx_check_permission(vcpu
))
7892 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7893 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7895 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7897 if (type
>= 32 || !(types
& (1 << type
))) {
7898 nested_vmx_failValid(vcpu
,
7899 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7900 return kvm_skip_emulated_instruction(vcpu
);
7903 /* According to the Intel VMX instruction reference, the memory
7904 * operand is read even if it isn't needed (e.g., for type==global)
7906 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7907 vmx_instruction_info
, false, &gva
))
7909 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7910 sizeof(operand
), &e
)) {
7911 kvm_inject_page_fault(vcpu
, &e
);
7916 case VMX_EPT_EXTENT_GLOBAL
:
7918 * TODO: track mappings and invalidate
7919 * single context requests appropriately
7921 case VMX_EPT_EXTENT_CONTEXT
:
7922 kvm_mmu_sync_roots(vcpu
);
7923 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7924 nested_vmx_succeed(vcpu
);
7931 return kvm_skip_emulated_instruction(vcpu
);
7934 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7936 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7937 u32 vmx_instruction_info
;
7938 unsigned long type
, types
;
7940 struct x86_exception e
;
7946 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7947 SECONDARY_EXEC_ENABLE_VPID
) ||
7948 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7949 kvm_queue_exception(vcpu
, UD_VECTOR
);
7953 if (!nested_vmx_check_permission(vcpu
))
7956 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7957 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7959 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7960 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7962 if (type
>= 32 || !(types
& (1 << type
))) {
7963 nested_vmx_failValid(vcpu
,
7964 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7965 return kvm_skip_emulated_instruction(vcpu
);
7968 /* according to the intel vmx instruction reference, the memory
7969 * operand is read even if it isn't needed (e.g., for type==global)
7971 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7972 vmx_instruction_info
, false, &gva
))
7974 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7975 sizeof(operand
), &e
)) {
7976 kvm_inject_page_fault(vcpu
, &e
);
7979 if (operand
.vpid
>> 16) {
7980 nested_vmx_failValid(vcpu
,
7981 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7982 return kvm_skip_emulated_instruction(vcpu
);
7986 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7987 if (is_noncanonical_address(operand
.gla
, vcpu
)) {
7988 nested_vmx_failValid(vcpu
,
7989 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7990 return kvm_skip_emulated_instruction(vcpu
);
7993 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7994 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7995 if (!operand
.vpid
) {
7996 nested_vmx_failValid(vcpu
,
7997 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7998 return kvm_skip_emulated_instruction(vcpu
);
8001 case VMX_VPID_EXTENT_ALL_CONTEXT
:
8005 return kvm_skip_emulated_instruction(vcpu
);
8008 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
8009 nested_vmx_succeed(vcpu
);
8011 return kvm_skip_emulated_instruction(vcpu
);
8014 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
8016 unsigned long exit_qualification
;
8018 trace_kvm_pml_full(vcpu
->vcpu_id
);
8020 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8023 * PML buffer FULL happened while executing iret from NMI,
8024 * "blocked by NMI" bit has to be set before next VM entry.
8026 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8028 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
8029 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8030 GUEST_INTR_STATE_NMI
);
8033 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
8034 * here.., and there's no userspace involvement needed for PML.
8039 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
8041 kvm_lapic_expired_hv_timer(vcpu
);
8045 static bool valid_ept_address(struct kvm_vcpu
*vcpu
, u64 address
)
8047 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8048 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8050 /* Check for memory type validity */
8051 switch (address
& VMX_EPTP_MT_MASK
) {
8052 case VMX_EPTP_MT_UC
:
8053 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_UC_BIT
))
8056 case VMX_EPTP_MT_WB
:
8057 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPTP_WB_BIT
))
8064 /* only 4 levels page-walk length are valid */
8065 if ((address
& VMX_EPTP_PWL_MASK
) != VMX_EPTP_PWL_4
)
8068 /* Reserved bits should not be set */
8069 if (address
>> maxphyaddr
|| ((address
>> 7) & 0x1f))
8072 /* AD, if set, should be supported */
8073 if (address
& VMX_EPTP_AD_ENABLE_BIT
) {
8074 if (!(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_AD_BIT
))
8081 static int nested_vmx_eptp_switching(struct kvm_vcpu
*vcpu
,
8082 struct vmcs12
*vmcs12
)
8084 u32 index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8086 bool accessed_dirty
;
8087 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
8089 if (!nested_cpu_has_eptp_switching(vmcs12
) ||
8090 !nested_cpu_has_ept(vmcs12
))
8093 if (index
>= VMFUNC_EPTP_ENTRIES
)
8097 if (kvm_vcpu_read_guest_page(vcpu
, vmcs12
->eptp_list_address
>> PAGE_SHIFT
,
8098 &address
, index
* 8, 8))
8101 accessed_dirty
= !!(address
& VMX_EPTP_AD_ENABLE_BIT
);
8104 * If the (L2) guest does a vmfunc to the currently
8105 * active ept pointer, we don't have to do anything else
8107 if (vmcs12
->ept_pointer
!= address
) {
8108 if (!valid_ept_address(vcpu
, address
))
8111 kvm_mmu_unload(vcpu
);
8112 mmu
->ept_ad
= accessed_dirty
;
8113 mmu
->base_role
.ad_disabled
= !accessed_dirty
;
8114 vmcs12
->ept_pointer
= address
;
8116 * TODO: Check what's the correct approach in case
8117 * mmu reload fails. Currently, we just let the next
8118 * reload potentially fail
8120 kvm_mmu_reload(vcpu
);
8126 static int handle_vmfunc(struct kvm_vcpu
*vcpu
)
8128 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8129 struct vmcs12
*vmcs12
;
8130 u32 function
= vcpu
->arch
.regs
[VCPU_REGS_RAX
];
8133 * VMFUNC is only supported for nested guests, but we always enable the
8134 * secondary control for simplicity; for non-nested mode, fake that we
8135 * didn't by injecting #UD.
8137 if (!is_guest_mode(vcpu
)) {
8138 kvm_queue_exception(vcpu
, UD_VECTOR
);
8142 vmcs12
= get_vmcs12(vcpu
);
8143 if ((vmcs12
->vm_function_control
& (1 << function
)) == 0)
8148 if (nested_vmx_eptp_switching(vcpu
, vmcs12
))
8154 return kvm_skip_emulated_instruction(vcpu
);
8157 nested_vmx_vmexit(vcpu
, vmx
->exit_reason
,
8158 vmcs_read32(VM_EXIT_INTR_INFO
),
8159 vmcs_readl(EXIT_QUALIFICATION
));
8164 * The exit handlers return 1 if the exit was handled fully and guest execution
8165 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
8166 * to be done to userspace and return 0.
8168 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
8169 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
8170 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
8171 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
8172 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
8173 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
8174 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
8175 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
8176 [EXIT_REASON_CPUID
] = handle_cpuid
,
8177 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
8178 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
8179 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
8180 [EXIT_REASON_HLT
] = handle_halt
,
8181 [EXIT_REASON_INVD
] = handle_invd
,
8182 [EXIT_REASON_INVLPG
] = handle_invlpg
,
8183 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
8184 [EXIT_REASON_VMCALL
] = handle_vmcall
,
8185 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
8186 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
8187 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
8188 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
8189 [EXIT_REASON_VMREAD
] = handle_vmread
,
8190 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
8191 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
8192 [EXIT_REASON_VMOFF
] = handle_vmoff
,
8193 [EXIT_REASON_VMON
] = handle_vmon
,
8194 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
8195 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
8196 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
8197 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
8198 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
8199 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
8200 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
8201 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
8202 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
8203 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
8204 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
8205 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
8206 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
8207 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
8208 [EXIT_REASON_INVEPT
] = handle_invept
,
8209 [EXIT_REASON_INVVPID
] = handle_invvpid
,
8210 [EXIT_REASON_RDRAND
] = handle_invalid_op
,
8211 [EXIT_REASON_RDSEED
] = handle_invalid_op
,
8212 [EXIT_REASON_XSAVES
] = handle_xsaves
,
8213 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
8214 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
8215 [EXIT_REASON_VMFUNC
] = handle_vmfunc
,
8216 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
8219 static const int kvm_vmx_max_exit_handlers
=
8220 ARRAY_SIZE(kvm_vmx_exit_handlers
);
8222 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
8223 struct vmcs12
*vmcs12
)
8225 unsigned long exit_qualification
;
8226 gpa_t bitmap
, last_bitmap
;
8231 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
8232 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
8234 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8236 port
= exit_qualification
>> 16;
8237 size
= (exit_qualification
& 7) + 1;
8239 last_bitmap
= (gpa_t
)-1;
8244 bitmap
= vmcs12
->io_bitmap_a
;
8245 else if (port
< 0x10000)
8246 bitmap
= vmcs12
->io_bitmap_b
;
8249 bitmap
+= (port
& 0x7fff) / 8;
8251 if (last_bitmap
!= bitmap
)
8252 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
8254 if (b
& (1 << (port
& 7)))
8259 last_bitmap
= bitmap
;
8266 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
8267 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
8268 * disinterest in the current event (read or write a specific MSR) by using an
8269 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
8271 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
8272 struct vmcs12
*vmcs12
, u32 exit_reason
)
8274 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
8277 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8281 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
8282 * for the four combinations of read/write and low/high MSR numbers.
8283 * First we need to figure out which of the four to use:
8285 bitmap
= vmcs12
->msr_bitmap
;
8286 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
8288 if (msr_index
>= 0xc0000000) {
8289 msr_index
-= 0xc0000000;
8293 /* Then read the msr_index'th bit from this bitmap: */
8294 if (msr_index
< 1024*8) {
8296 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8298 return 1 & (b
>> (msr_index
& 7));
8300 return true; /* let L1 handle the wrong parameter */
8304 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8305 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8306 * intercept (via guest_host_mask etc.) the current event.
8308 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8309 struct vmcs12
*vmcs12
)
8311 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8312 int cr
= exit_qualification
& 15;
8316 switch ((exit_qualification
>> 4) & 3) {
8317 case 0: /* mov to cr */
8318 reg
= (exit_qualification
>> 8) & 15;
8319 val
= kvm_register_readl(vcpu
, reg
);
8322 if (vmcs12
->cr0_guest_host_mask
&
8323 (val
^ vmcs12
->cr0_read_shadow
))
8327 if ((vmcs12
->cr3_target_count
>= 1 &&
8328 vmcs12
->cr3_target_value0
== val
) ||
8329 (vmcs12
->cr3_target_count
>= 2 &&
8330 vmcs12
->cr3_target_value1
== val
) ||
8331 (vmcs12
->cr3_target_count
>= 3 &&
8332 vmcs12
->cr3_target_value2
== val
) ||
8333 (vmcs12
->cr3_target_count
>= 4 &&
8334 vmcs12
->cr3_target_value3
== val
))
8336 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8340 if (vmcs12
->cr4_guest_host_mask
&
8341 (vmcs12
->cr4_read_shadow
^ val
))
8345 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8351 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8352 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8355 case 1: /* mov from cr */
8358 if (vmcs12
->cpu_based_vm_exec_control
&
8359 CPU_BASED_CR3_STORE_EXITING
)
8363 if (vmcs12
->cpu_based_vm_exec_control
&
8364 CPU_BASED_CR8_STORE_EXITING
)
8371 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8372 * cr0. Other attempted changes are ignored, with no exit.
8374 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8375 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8376 (val
^ vmcs12
->cr0_read_shadow
))
8378 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8379 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8388 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8389 * should handle it ourselves in L0 (and then continue L2). Only call this
8390 * when in is_guest_mode (L2).
8392 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8394 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8395 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8396 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8398 if (vmx
->nested
.nested_run_pending
)
8401 if (unlikely(vmx
->fail
)) {
8402 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8403 vmcs_read32(VM_INSTRUCTION_ERROR
));
8408 * The host physical addresses of some pages of guest memory
8409 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8410 * may write to these pages via their host physical address while
8411 * L2 is running, bypassing any address-translation-based dirty
8412 * tracking (e.g. EPT write protection).
8414 * Mark them dirty on every exit from L2 to prevent them from
8415 * getting out of sync with dirty tracking.
8417 nested_mark_vmcs12_pages_dirty(vcpu
);
8419 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8420 vmcs_readl(EXIT_QUALIFICATION
),
8421 vmx
->idt_vectoring_info
,
8423 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8426 switch (exit_reason
) {
8427 case EXIT_REASON_EXCEPTION_NMI
:
8428 if (is_nmi(intr_info
))
8430 else if (is_page_fault(intr_info
))
8431 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8432 else if (is_no_device(intr_info
) &&
8433 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8435 else if (is_debug(intr_info
) &&
8437 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8439 else if (is_breakpoint(intr_info
) &&
8440 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8442 return vmcs12
->exception_bitmap
&
8443 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8444 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8446 case EXIT_REASON_TRIPLE_FAULT
:
8448 case EXIT_REASON_PENDING_INTERRUPT
:
8449 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8450 case EXIT_REASON_NMI_WINDOW
:
8451 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8452 case EXIT_REASON_TASK_SWITCH
:
8454 case EXIT_REASON_CPUID
:
8456 case EXIT_REASON_HLT
:
8457 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8458 case EXIT_REASON_INVD
:
8460 case EXIT_REASON_INVLPG
:
8461 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8462 case EXIT_REASON_RDPMC
:
8463 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8464 case EXIT_REASON_RDRAND
:
8465 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND_EXITING
);
8466 case EXIT_REASON_RDSEED
:
8467 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED_EXITING
);
8468 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8469 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8470 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8471 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8472 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8473 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8474 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8475 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8477 * VMX instructions trap unconditionally. This allows L1 to
8478 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8481 case EXIT_REASON_CR_ACCESS
:
8482 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8483 case EXIT_REASON_DR_ACCESS
:
8484 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8485 case EXIT_REASON_IO_INSTRUCTION
:
8486 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8487 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8488 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8489 case EXIT_REASON_MSR_READ
:
8490 case EXIT_REASON_MSR_WRITE
:
8491 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8492 case EXIT_REASON_INVALID_STATE
:
8494 case EXIT_REASON_MWAIT_INSTRUCTION
:
8495 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8496 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8497 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8498 case EXIT_REASON_MONITOR_INSTRUCTION
:
8499 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8500 case EXIT_REASON_PAUSE_INSTRUCTION
:
8501 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8502 nested_cpu_has2(vmcs12
,
8503 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8504 case EXIT_REASON_MCE_DURING_VMENTRY
:
8506 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8507 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8508 case EXIT_REASON_APIC_ACCESS
:
8509 return nested_cpu_has2(vmcs12
,
8510 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8511 case EXIT_REASON_APIC_WRITE
:
8512 case EXIT_REASON_EOI_INDUCED
:
8513 /* apic_write and eoi_induced should exit unconditionally. */
8515 case EXIT_REASON_EPT_VIOLATION
:
8517 * L0 always deals with the EPT violation. If nested EPT is
8518 * used, and the nested mmu code discovers that the address is
8519 * missing in the guest EPT table (EPT12), the EPT violation
8520 * will be injected with nested_ept_inject_page_fault()
8523 case EXIT_REASON_EPT_MISCONFIG
:
8525 * L2 never uses directly L1's EPT, but rather L0's own EPT
8526 * table (shadow on EPT) or a merged EPT table that L0 built
8527 * (EPT on EPT). So any problems with the structure of the
8528 * table is L0's fault.
8531 case EXIT_REASON_INVPCID
:
8533 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_INVPCID
) &&
8534 nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8535 case EXIT_REASON_WBINVD
:
8536 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8537 case EXIT_REASON_XSETBV
:
8539 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8541 * This should never happen, since it is not possible to
8542 * set XSS to a non-zero value---neither in L1 nor in L2.
8543 * If if it were, XSS would have to be checked against
8544 * the XSS exit bitmap in vmcs12.
8546 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8547 case EXIT_REASON_PREEMPTION_TIMER
:
8549 case EXIT_REASON_PML_FULL
:
8550 /* We emulate PML support to L1. */
8552 case EXIT_REASON_VMFUNC
:
8553 /* VM functions are emulated through L2->L0 vmexits. */
8560 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8562 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8565 * At this point, the exit interruption info in exit_intr_info
8566 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8567 * we need to query the in-kernel LAPIC.
8569 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8570 if ((exit_intr_info
&
8571 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8572 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8573 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8574 vmcs12
->vm_exit_intr_error_code
=
8575 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8578 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8579 vmcs_readl(EXIT_QUALIFICATION
));
8583 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8585 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8586 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8589 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8592 __free_page(vmx
->pml_pg
);
8597 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8599 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8603 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8605 /* Do nothing if PML buffer is empty */
8606 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8609 /* PML index always points to next available PML buffer entity */
8610 if (pml_idx
>= PML_ENTITY_NUM
)
8615 pml_buf
= page_address(vmx
->pml_pg
);
8616 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8619 gpa
= pml_buf
[pml_idx
];
8620 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8621 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8624 /* reset PML index */
8625 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8629 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8630 * Called before reporting dirty_bitmap to userspace.
8632 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8635 struct kvm_vcpu
*vcpu
;
8637 * We only need to kick vcpu out of guest mode here, as PML buffer
8638 * is flushed at beginning of all VMEXITs, and it's obvious that only
8639 * vcpus running in guest are possible to have unflushed GPAs in PML
8642 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8643 kvm_vcpu_kick(vcpu
);
8646 static void vmx_dump_sel(char *name
, uint32_t sel
)
8648 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8649 name
, vmcs_read16(sel
),
8650 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8651 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8652 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8655 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8657 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8658 name
, vmcs_read32(limit
),
8659 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8662 static void dump_vmcs(void)
8664 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8665 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8666 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8667 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8668 u32 secondary_exec_control
= 0;
8669 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8670 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8673 if (cpu_has_secondary_exec_ctrls())
8674 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8676 pr_err("*** Guest State ***\n");
8677 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8678 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8679 vmcs_readl(CR0_GUEST_HOST_MASK
));
8680 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8681 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8682 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8683 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8684 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8686 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8687 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8688 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8689 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8691 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8692 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8693 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8694 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8695 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8696 vmcs_readl(GUEST_SYSENTER_ESP
),
8697 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8698 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8699 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8700 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8701 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8702 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8703 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8704 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8705 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8706 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8707 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8708 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8709 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8710 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8711 efer
, vmcs_read64(GUEST_IA32_PAT
));
8712 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8713 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8714 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8715 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8716 pr_err("PerfGlobCtl = 0x%016llx\n",
8717 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8718 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8719 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8720 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8721 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8722 vmcs_read32(GUEST_ACTIVITY_STATE
));
8723 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8724 pr_err("InterruptStatus = %04x\n",
8725 vmcs_read16(GUEST_INTR_STATUS
));
8727 pr_err("*** Host State ***\n");
8728 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8729 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8730 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8731 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8732 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8733 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8734 vmcs_read16(HOST_TR_SELECTOR
));
8735 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8736 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8737 vmcs_readl(HOST_TR_BASE
));
8738 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8739 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8740 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8741 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8742 vmcs_readl(HOST_CR4
));
8743 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8744 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8745 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8746 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8747 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8748 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8749 vmcs_read64(HOST_IA32_EFER
),
8750 vmcs_read64(HOST_IA32_PAT
));
8751 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8752 pr_err("PerfGlobCtl = 0x%016llx\n",
8753 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8755 pr_err("*** Control State ***\n");
8756 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8757 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8758 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8759 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8760 vmcs_read32(EXCEPTION_BITMAP
),
8761 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8762 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8763 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8764 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8765 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8766 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8767 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8768 vmcs_read32(VM_EXIT_INTR_INFO
),
8769 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8770 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8771 pr_err(" reason=%08x qualification=%016lx\n",
8772 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8773 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8774 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8775 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8776 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8777 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8778 pr_err("TSC Multiplier = 0x%016llx\n",
8779 vmcs_read64(TSC_MULTIPLIER
));
8780 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8781 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8782 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8783 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8784 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8785 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8786 n
= vmcs_read32(CR3_TARGET_COUNT
);
8787 for (i
= 0; i
+ 1 < n
; i
+= 4)
8788 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8789 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8790 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8792 pr_err("CR3 target%u=%016lx\n",
8793 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8794 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8795 pr_err("PLE Gap=%08x Window=%08x\n",
8796 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8797 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8798 pr_err("Virtual processor ID = 0x%04x\n",
8799 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8803 * The guest has exited. See if we can fix it or if we need userspace
8806 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8808 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8809 u32 exit_reason
= vmx
->exit_reason
;
8810 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8812 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8815 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8816 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8817 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8818 * mode as if vcpus is in root mode, the PML buffer must has been
8822 vmx_flush_pml_buffer(vcpu
);
8824 /* If guest state is invalid, start emulating */
8825 if (vmx
->emulation_required
)
8826 return handle_invalid_guest_state(vcpu
);
8828 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8829 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8831 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8833 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8834 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8839 if (unlikely(vmx
->fail
)) {
8840 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8841 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8842 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8848 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8849 * delivery event since it indicates guest is accessing MMIO.
8850 * The vm-exit can be triggered again after return to guest that
8851 * will cause infinite loop.
8853 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8854 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8855 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8856 exit_reason
!= EXIT_REASON_PML_FULL
&&
8857 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8858 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8859 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8860 vcpu
->run
->internal
.ndata
= 3;
8861 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8862 vcpu
->run
->internal
.data
[1] = exit_reason
;
8863 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8864 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8865 vcpu
->run
->internal
.ndata
++;
8866 vcpu
->run
->internal
.data
[3] =
8867 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8872 if (unlikely(!enable_vnmi
&&
8873 vmx
->loaded_vmcs
->soft_vnmi_blocked
)) {
8874 if (vmx_interrupt_allowed(vcpu
)) {
8875 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8876 } else if (vmx
->loaded_vmcs
->vnmi_blocked_time
> 1000000000LL &&
8877 vcpu
->arch
.nmi_pending
) {
8879 * This CPU don't support us in finding the end of an
8880 * NMI-blocked window if the guest runs with IRQs
8881 * disabled. So we pull the trigger after 1 s of
8882 * futile waiting, but inform the user about this.
8884 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8885 "state on VCPU %d after 1 s timeout\n",
8886 __func__
, vcpu
->vcpu_id
);
8887 vmx
->loaded_vmcs
->soft_vnmi_blocked
= 0;
8891 if (exit_reason
< kvm_vmx_max_exit_handlers
8892 && kvm_vmx_exit_handlers
[exit_reason
])
8893 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8895 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8897 kvm_queue_exception(vcpu
, UD_VECTOR
);
8902 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8904 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8906 if (is_guest_mode(vcpu
) &&
8907 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8910 if (irr
== -1 || tpr
< irr
) {
8911 vmcs_write32(TPR_THRESHOLD
, 0);
8915 vmcs_write32(TPR_THRESHOLD
, irr
);
8918 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8920 u32 sec_exec_control
;
8922 /* Postpone execution until vmcs01 is the current VMCS. */
8923 if (is_guest_mode(vcpu
)) {
8924 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8928 if (!cpu_has_vmx_virtualize_x2apic_mode())
8931 if (!cpu_need_tpr_shadow(vcpu
))
8934 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8937 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8938 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8940 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8941 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8942 vmx_flush_tlb_ept_only(vcpu
);
8944 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8946 vmx_set_msr_bitmap(vcpu
);
8949 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8951 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8954 * Currently we do not handle the nested case where L2 has an
8955 * APIC access page of its own; that page is still pinned.
8956 * Hence, we skip the case where the VCPU is in guest mode _and_
8957 * L1 prepared an APIC access page for L2.
8959 * For the case where L1 and L2 share the same APIC access page
8960 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8961 * in the vmcs12), this function will only update either the vmcs01
8962 * or the vmcs02. If the former, the vmcs02 will be updated by
8963 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8964 * the next L2->L1 exit.
8966 if (!is_guest_mode(vcpu
) ||
8967 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8968 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8969 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8970 vmx_flush_tlb_ept_only(vcpu
);
8974 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8982 status
= vmcs_read16(GUEST_INTR_STATUS
);
8984 if (max_isr
!= old
) {
8986 status
|= max_isr
<< 8;
8987 vmcs_write16(GUEST_INTR_STATUS
, status
);
8991 static void vmx_set_rvi(int vector
)
8999 status
= vmcs_read16(GUEST_INTR_STATUS
);
9000 old
= (u8
)status
& 0xff;
9001 if ((u8
)vector
!= old
) {
9003 status
|= (u8
)vector
;
9004 vmcs_write16(GUEST_INTR_STATUS
, status
);
9008 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
9010 if (!is_guest_mode(vcpu
)) {
9011 vmx_set_rvi(max_irr
);
9019 * In guest mode. If a vmexit is needed, vmx_check_nested_events
9022 if (nested_exit_on_intr(vcpu
))
9026 * Else, fall back to pre-APICv interrupt injection since L2
9027 * is run without virtual interrupt delivery.
9029 if (!kvm_event_needs_reinjection(vcpu
) &&
9030 vmx_interrupt_allowed(vcpu
)) {
9031 kvm_queue_interrupt(vcpu
, max_irr
, false);
9032 vmx_inject_irq(vcpu
);
9036 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
9038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9041 WARN_ON(!vcpu
->arch
.apicv_active
);
9042 if (pi_test_on(&vmx
->pi_desc
)) {
9043 pi_clear_on(&vmx
->pi_desc
);
9045 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
9046 * But on x86 this is just a compiler barrier anyway.
9048 smp_mb__after_atomic();
9049 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
9051 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
9053 vmx_hwapic_irr_update(vcpu
, max_irr
);
9057 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
9059 if (!kvm_vcpu_apicv_active(vcpu
))
9062 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
9063 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
9064 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
9065 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
9068 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
9070 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9072 pi_clear_on(&vmx
->pi_desc
);
9073 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
9076 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
9078 u32 exit_intr_info
= 0;
9079 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
9081 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
9082 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
9085 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9086 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9087 vmx
->exit_intr_info
= exit_intr_info
;
9089 /* if exit due to PF check for async PF */
9090 if (is_page_fault(exit_intr_info
))
9091 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
9093 /* Handle machine checks before interrupts are enabled */
9094 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
9095 is_machine_check(exit_intr_info
))
9096 kvm_machine_check();
9098 /* We need to handle NMIs before interrupts are enabled */
9099 if (is_nmi(exit_intr_info
)) {
9100 kvm_before_handle_nmi(&vmx
->vcpu
);
9102 kvm_after_handle_nmi(&vmx
->vcpu
);
9106 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
9108 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9110 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
9111 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
9112 unsigned int vector
;
9113 unsigned long entry
;
9115 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9116 #ifdef CONFIG_X86_64
9120 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9121 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
9122 entry
= gate_offset(desc
);
9124 #ifdef CONFIG_X86_64
9125 "mov %%" _ASM_SP
", %[sp]\n\t"
9126 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
9131 __ASM_SIZE(push
) " $%c[cs]\n\t"
9134 #ifdef CONFIG_X86_64
9139 THUNK_TARGET(entry
),
9140 [ss
]"i"(__KERNEL_DS
),
9141 [cs
]"i"(__KERNEL_CS
)
9145 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
9147 static bool vmx_has_high_real_mode_segbase(void)
9149 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
9152 static bool vmx_mpx_supported(void)
9154 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
9155 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
9158 static bool vmx_xsaves_supported(void)
9160 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
9161 SECONDARY_EXEC_XSAVES
;
9164 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
9169 bool idtv_info_valid
;
9171 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9174 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
9177 * Can't use vmx->exit_intr_info since we're not sure what
9178 * the exit reason is.
9180 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
9181 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
9182 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
9184 * SDM 3: 27.7.1.2 (September 2008)
9185 * Re-set bit "block by NMI" before VM entry if vmexit caused by
9186 * a guest IRET fault.
9187 * SDM 3: 23.2.2 (September 2008)
9188 * Bit 12 is undefined in any of the following cases:
9189 * If the VM exit sets the valid bit in the IDT-vectoring
9190 * information field.
9191 * If the VM exit is due to a double fault.
9193 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
9194 vector
!= DF_VECTOR
&& !idtv_info_valid
)
9195 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
9196 GUEST_INTR_STATE_NMI
);
9198 vmx
->loaded_vmcs
->nmi_known_unmasked
=
9199 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
9200 & GUEST_INTR_STATE_NMI
);
9201 } else if (unlikely(vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9202 vmx
->loaded_vmcs
->vnmi_blocked_time
+=
9203 ktime_to_ns(ktime_sub(ktime_get(),
9204 vmx
->loaded_vmcs
->entry_time
));
9207 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
9208 u32 idt_vectoring_info
,
9209 int instr_len_field
,
9210 int error_code_field
)
9214 bool idtv_info_valid
;
9216 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
9218 vcpu
->arch
.nmi_injected
= false;
9219 kvm_clear_exception_queue(vcpu
);
9220 kvm_clear_interrupt_queue(vcpu
);
9222 if (!idtv_info_valid
)
9225 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9227 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
9228 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
9231 case INTR_TYPE_NMI_INTR
:
9232 vcpu
->arch
.nmi_injected
= true;
9234 * SDM 3: 27.7.1.2 (September 2008)
9235 * Clear bit "block by NMI" before VM entry if a NMI
9238 vmx_set_nmi_mask(vcpu
, false);
9240 case INTR_TYPE_SOFT_EXCEPTION
:
9241 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9243 case INTR_TYPE_HARD_EXCEPTION
:
9244 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
9245 u32 err
= vmcs_read32(error_code_field
);
9246 kvm_requeue_exception_e(vcpu
, vector
, err
);
9248 kvm_requeue_exception(vcpu
, vector
);
9250 case INTR_TYPE_SOFT_INTR
:
9251 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
9253 case INTR_TYPE_EXT_INTR
:
9254 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
9261 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
9263 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
9264 VM_EXIT_INSTRUCTION_LEN
,
9265 IDT_VECTORING_ERROR_CODE
);
9268 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
9270 __vmx_complete_interrupts(vcpu
,
9271 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
9272 VM_ENTRY_INSTRUCTION_LEN
,
9273 VM_ENTRY_EXCEPTION_ERROR_CODE
);
9275 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
9278 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
9281 struct perf_guest_switch_msr
*msrs
;
9283 msrs
= perf_guest_get_msrs(&nr_msrs
);
9288 for (i
= 0; i
< nr_msrs
; i
++)
9289 if (msrs
[i
].host
== msrs
[i
].guest
)
9290 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
9292 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
9296 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
9298 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9302 if (vmx
->hv_deadline_tsc
== -1)
9306 if (vmx
->hv_deadline_tsc
> tscl
)
9307 /* sure to be 32 bit only because checked on set_hv_timer */
9308 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
9309 cpu_preemption_timer_multi
);
9313 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
9316 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
9318 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9319 unsigned long debugctlmsr
, cr3
, cr4
;
9321 /* Record the guest's net vcpu time for enforced NMI injections. */
9322 if (unlikely(!enable_vnmi
&&
9323 vmx
->loaded_vmcs
->soft_vnmi_blocked
))
9324 vmx
->loaded_vmcs
->entry_time
= ktime_get();
9326 /* Don't enter VMX if guest state is invalid, let the exit handler
9327 start emulation until we arrive back to a valid state */
9328 if (vmx
->emulation_required
)
9331 if (vmx
->ple_window_dirty
) {
9332 vmx
->ple_window_dirty
= false;
9333 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9336 if (vmx
->nested
.sync_shadow_vmcs
) {
9337 copy_vmcs12_to_shadow(vmx
);
9338 vmx
->nested
.sync_shadow_vmcs
= false;
9341 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9342 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9343 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9344 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9346 cr3
= __get_current_cr3_fast();
9347 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9348 vmcs_writel(HOST_CR3
, cr3
);
9349 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9352 cr4
= cr4_read_shadow();
9353 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9354 vmcs_writel(HOST_CR4
, cr4
);
9355 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9358 /* When single-stepping over STI and MOV SS, we must clear the
9359 * corresponding interruptibility bits in the guest state. Otherwise
9360 * vmentry fails as it then expects bit 14 (BS) in pending debug
9361 * exceptions being set, but that's not correct for the guest debugging
9363 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9364 vmx_set_interrupt_shadow(vcpu
, 0);
9366 if (static_cpu_has(X86_FEATURE_PKU
) &&
9367 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9368 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9369 __write_pkru(vcpu
->arch
.pkru
);
9371 atomic_switch_perf_msrs(vmx
);
9372 debugctlmsr
= get_debugctlmsr();
9374 vmx_arm_hv_timer(vcpu
);
9376 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9378 /* Store host registers */
9379 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9380 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9381 "push %%" _ASM_CX
" \n\t"
9382 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9384 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9385 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9387 /* Reload cr2 if changed */
9388 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9389 "mov %%cr2, %%" _ASM_DX
" \n\t"
9390 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9392 "mov %%" _ASM_AX
", %%cr2 \n\t"
9394 /* Check if vmlaunch of vmresume is needed */
9395 "cmpl $0, %c[launched](%0) \n\t"
9396 /* Load guest registers. Don't clobber flags. */
9397 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9398 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9399 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9400 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9401 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9402 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9403 #ifdef CONFIG_X86_64
9404 "mov %c[r8](%0), %%r8 \n\t"
9405 "mov %c[r9](%0), %%r9 \n\t"
9406 "mov %c[r10](%0), %%r10 \n\t"
9407 "mov %c[r11](%0), %%r11 \n\t"
9408 "mov %c[r12](%0), %%r12 \n\t"
9409 "mov %c[r13](%0), %%r13 \n\t"
9410 "mov %c[r14](%0), %%r14 \n\t"
9411 "mov %c[r15](%0), %%r15 \n\t"
9413 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9415 /* Enter guest mode */
9417 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9419 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9421 /* Save guest registers, load host registers, keep flags */
9422 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9424 "setbe %c[fail](%0)\n\t"
9425 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9426 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9427 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9428 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9429 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9430 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9431 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9432 #ifdef CONFIG_X86_64
9433 "mov %%r8, %c[r8](%0) \n\t"
9434 "mov %%r9, %c[r9](%0) \n\t"
9435 "mov %%r10, %c[r10](%0) \n\t"
9436 "mov %%r11, %c[r11](%0) \n\t"
9437 "mov %%r12, %c[r12](%0) \n\t"
9438 "mov %%r13, %c[r13](%0) \n\t"
9439 "mov %%r14, %c[r14](%0) \n\t"
9440 "mov %%r15, %c[r15](%0) \n\t"
9441 "xor %%r8d, %%r8d \n\t"
9442 "xor %%r9d, %%r9d \n\t"
9443 "xor %%r10d, %%r10d \n\t"
9444 "xor %%r11d, %%r11d \n\t"
9445 "xor %%r12d, %%r12d \n\t"
9446 "xor %%r13d, %%r13d \n\t"
9447 "xor %%r14d, %%r14d \n\t"
9448 "xor %%r15d, %%r15d \n\t"
9450 "mov %%cr2, %%" _ASM_AX
" \n\t"
9451 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9453 "xor %%eax, %%eax \n\t"
9454 "xor %%ebx, %%ebx \n\t"
9455 "xor %%esi, %%esi \n\t"
9456 "xor %%edi, %%edi \n\t"
9457 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9458 ".pushsection .rodata \n\t"
9459 ".global vmx_return \n\t"
9460 "vmx_return: " _ASM_PTR
" 2b \n\t"
9462 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9463 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9464 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9465 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9466 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9467 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9468 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9469 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9470 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9471 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9472 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9473 #ifdef CONFIG_X86_64
9474 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9475 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9476 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9477 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9478 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9479 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9480 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9481 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9483 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9484 [wordsize
]"i"(sizeof(ulong
))
9486 #ifdef CONFIG_X86_64
9487 , "rax", "rbx", "rdi", "rsi"
9488 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9490 , "eax", "ebx", "edi", "esi"
9494 /* Eliminate branch target predictions from guest mode */
9497 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9499 update_debugctlmsr(debugctlmsr
);
9501 #ifndef CONFIG_X86_64
9503 * The sysexit path does not restore ds/es, so we must set them to
9504 * a reasonable value ourselves.
9506 * We can't defer this to vmx_load_host_state() since that function
9507 * may be executed in interrupt context, which saves and restore segments
9508 * around it, nullifying its effect.
9510 loadsegment(ds
, __USER_DS
);
9511 loadsegment(es
, __USER_DS
);
9514 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9515 | (1 << VCPU_EXREG_RFLAGS
)
9516 | (1 << VCPU_EXREG_PDPTR
)
9517 | (1 << VCPU_EXREG_SEGMENTS
)
9518 | (1 << VCPU_EXREG_CR3
));
9519 vcpu
->arch
.regs_dirty
= 0;
9522 * eager fpu is enabled if PKEY is supported and CR4 is switched
9523 * back on host, so it is safe to read guest PKRU from current
9526 if (static_cpu_has(X86_FEATURE_PKU
) &&
9527 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9528 vcpu
->arch
.pkru
= __read_pkru();
9529 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9530 __write_pkru(vmx
->host_pkru
);
9534 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9535 * we did not inject a still-pending event to L1 now because of
9536 * nested_run_pending, we need to re-enable this bit.
9538 if (vmx
->nested
.nested_run_pending
)
9539 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9541 vmx
->nested
.nested_run_pending
= 0;
9542 vmx
->idt_vectoring_info
= 0;
9544 vmx
->exit_reason
= vmx
->fail
? 0xdead : vmcs_read32(VM_EXIT_REASON
);
9545 if (vmx
->fail
|| (vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
9548 vmx
->loaded_vmcs
->launched
= 1;
9549 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9551 vmx_complete_atomic_exit(vmx
);
9552 vmx_recover_nmi_blocking(vmx
);
9553 vmx_complete_interrupts(vmx
);
9555 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9557 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9559 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9562 if (vmx
->loaded_vmcs
== vmcs
)
9566 vmx
->loaded_vmcs
= vmcs
;
9568 vmx_vcpu_load(vcpu
, cpu
);
9573 * Ensure that the current vmcs of the logical processor is the
9574 * vmcs01 of the vcpu before calling free_nested().
9576 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9578 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9581 r
= vcpu_load(vcpu
);
9583 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9588 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9590 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9593 vmx_destroy_pml_buffer(vmx
);
9594 free_vpid(vmx
->vpid
);
9595 leave_guest_mode(vcpu
);
9596 vmx_free_vcpu_nested(vcpu
);
9597 free_loaded_vmcs(vmx
->loaded_vmcs
);
9598 kfree(vmx
->guest_msrs
);
9599 kvm_vcpu_uninit(vcpu
);
9600 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9603 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9606 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9610 return ERR_PTR(-ENOMEM
);
9612 vmx
->vpid
= allocate_vpid();
9614 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9621 * If PML is turned on, failure on enabling PML just results in failure
9622 * of creating the vcpu, therefore we can simplify PML logic (by
9623 * avoiding dealing with cases, such as enabling PML partially on vcpus
9624 * for the guest, etc.
9627 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9632 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9633 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9636 if (!vmx
->guest_msrs
)
9639 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9640 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9641 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9642 if (!vmx
->loaded_vmcs
->vmcs
)
9644 loaded_vmcs_init(vmx
->loaded_vmcs
);
9647 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9648 vmx
->vcpu
.cpu
= cpu
;
9649 vmx_vcpu_setup(vmx
);
9650 vmx_vcpu_put(&vmx
->vcpu
);
9652 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9653 err
= alloc_apic_access_page(kvm
);
9659 err
= init_rmode_identity_map(kvm
);
9665 nested_vmx_setup_ctls_msrs(vmx
);
9666 vmx
->nested
.vpid02
= allocate_vpid();
9669 vmx
->nested
.posted_intr_nv
= -1;
9670 vmx
->nested
.current_vmptr
= -1ull;
9672 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9675 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9676 * or POSTED_INTR_WAKEUP_VECTOR.
9678 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9679 vmx
->pi_desc
.sn
= 1;
9684 free_vpid(vmx
->nested
.vpid02
);
9685 free_loaded_vmcs(vmx
->loaded_vmcs
);
9687 kfree(vmx
->guest_msrs
);
9689 vmx_destroy_pml_buffer(vmx
);
9691 kvm_vcpu_uninit(&vmx
->vcpu
);
9693 free_vpid(vmx
->vpid
);
9694 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9695 return ERR_PTR(err
);
9698 static void __init
vmx_check_processor_compat(void *rtn
)
9700 struct vmcs_config vmcs_conf
;
9703 if (setup_vmcs_config(&vmcs_conf
) < 0)
9705 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9706 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9707 smp_processor_id());
9712 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9717 /* For VT-d and EPT combination
9718 * 1. MMIO: always map as UC
9720 * a. VT-d without snooping control feature: can't guarantee the
9721 * result, try to trust guest.
9722 * b. VT-d with snooping control feature: snooping control feature of
9723 * VT-d engine can guarantee the cache correctness. Just set it
9724 * to WB to keep consistent with host. So the same as item 3.
9725 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9726 * consistent with host MTRR
9729 cache
= MTRR_TYPE_UNCACHABLE
;
9733 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9734 ipat
= VMX_EPT_IPAT_BIT
;
9735 cache
= MTRR_TYPE_WRBACK
;
9739 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9740 ipat
= VMX_EPT_IPAT_BIT
;
9741 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9742 cache
= MTRR_TYPE_WRBACK
;
9744 cache
= MTRR_TYPE_UNCACHABLE
;
9748 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9751 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9754 static int vmx_get_lpage_level(void)
9756 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9757 return PT_DIRECTORY_LEVEL
;
9759 /* For shadow and EPT supported 1GB page */
9760 return PT_PDPE_LEVEL
;
9763 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9766 * These bits in the secondary execution controls field
9767 * are dynamic, the others are mostly based on the hypervisor
9768 * architecture and the guest's CPUID. Do not touch the
9772 SECONDARY_EXEC_SHADOW_VMCS
|
9773 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9774 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9776 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9778 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9779 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9783 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9784 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9786 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9788 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9789 struct kvm_cpuid_entry2
*entry
;
9791 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9792 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9794 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9795 if (entry && (entry->_reg & (_cpuid_mask))) \
9796 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9799 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9800 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9801 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9802 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9803 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9804 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9805 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9806 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9807 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9808 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9809 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9810 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9811 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9812 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9813 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9815 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9816 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9817 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9818 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9819 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9820 cr4_fixed1_update(X86_CR4_UMIP
, ecx
, bit(X86_FEATURE_UMIP
));
9822 #undef cr4_fixed1_update
9825 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9827 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9829 if (cpu_has_secondary_exec_ctrls()) {
9830 vmx_compute_secondary_exec_control(vmx
);
9831 vmcs_set_secondary_exec_control(vmx
->secondary_exec_control
);
9834 if (nested_vmx_allowed(vcpu
))
9835 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9836 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9838 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9839 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9841 if (nested_vmx_allowed(vcpu
))
9842 nested_vmx_cr_fixed1_bits_update(vcpu
);
9845 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9847 if (func
== 1 && nested
)
9848 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9851 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9852 struct x86_exception
*fault
)
9854 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9855 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9857 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9859 if (vmx
->nested
.pml_full
) {
9860 exit_reason
= EXIT_REASON_PML_FULL
;
9861 vmx
->nested
.pml_full
= false;
9862 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9863 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9864 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9866 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9868 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9869 vmcs12
->guest_physical_address
= fault
->address
;
9872 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9874 return nested_ept_get_cr3(vcpu
) & VMX_EPTP_AD_ENABLE_BIT
;
9877 /* Callbacks for nested_ept_init_mmu_context: */
9879 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9881 /* return the page table to be shadowed - in our case, EPT12 */
9882 return get_vmcs12(vcpu
)->ept_pointer
;
9885 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9887 WARN_ON(mmu_is_nested(vcpu
));
9888 if (!valid_ept_address(vcpu
, nested_ept_get_cr3(vcpu
)))
9891 kvm_mmu_unload(vcpu
);
9892 kvm_init_shadow_ept_mmu(vcpu
,
9893 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9894 VMX_EPT_EXECUTE_ONLY_BIT
,
9895 nested_ept_ad_enabled(vcpu
));
9896 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9897 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9898 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9900 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9904 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9906 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9909 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9912 bool inequality
, bit
;
9914 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9916 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9917 vmcs12
->page_fault_error_code_match
;
9918 return inequality
^ bit
;
9921 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9922 struct x86_exception
*fault
)
9924 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9926 WARN_ON(!is_guest_mode(vcpu
));
9928 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
) &&
9929 !to_vmx(vcpu
)->nested
.nested_run_pending
) {
9930 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9931 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9932 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9933 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9936 kvm_inject_page_fault(vcpu
, fault
);
9940 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9941 struct vmcs12
*vmcs12
);
9943 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9944 struct vmcs12
*vmcs12
)
9946 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9950 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9952 * Translate L1 physical address to host physical
9953 * address for vmcs02. Keep the page pinned, so this
9954 * physical address remains valid. We keep a reference
9955 * to it so we can release it later.
9957 if (vmx
->nested
.apic_access_page
) { /* shouldn't happen */
9958 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
9959 vmx
->nested
.apic_access_page
= NULL
;
9961 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->apic_access_addr
);
9963 * If translation failed, no matter: This feature asks
9964 * to exit when accessing the given address, and if it
9965 * can never be accessed, this feature won't do
9968 if (!is_error_page(page
)) {
9969 vmx
->nested
.apic_access_page
= page
;
9970 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9971 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9973 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9974 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9976 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9977 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9978 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9979 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9980 kvm_vcpu_reload_apic_access_page(vcpu
);
9983 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9984 if (vmx
->nested
.virtual_apic_page
) { /* shouldn't happen */
9985 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
9986 vmx
->nested
.virtual_apic_page
= NULL
;
9988 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9991 * If translation failed, VM entry will fail because
9992 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9993 * Failing the vm entry is _not_ what the processor
9994 * does but it's basically the only possibility we
9995 * have. We could still enter the guest if CR8 load
9996 * exits are enabled, CR8 store exits are enabled, and
9997 * virtualize APIC access is disabled; in this case
9998 * the processor would never use the TPR shadow and we
9999 * could simply clear the bit from the execution
10000 * control. But such a configuration is useless, so
10001 * let's keep the code simple.
10003 if (!is_error_page(page
)) {
10004 vmx
->nested
.virtual_apic_page
= page
;
10005 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
10006 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
10010 if (nested_cpu_has_posted_intr(vmcs12
)) {
10011 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
10012 kunmap(vmx
->nested
.pi_desc_page
);
10013 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
10014 vmx
->nested
.pi_desc_page
= NULL
;
10016 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
10017 if (is_error_page(page
))
10019 vmx
->nested
.pi_desc_page
= page
;
10020 vmx
->nested
.pi_desc
= kmap(vmx
->nested
.pi_desc_page
);
10021 vmx
->nested
.pi_desc
=
10022 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
10023 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10025 vmcs_write64(POSTED_INTR_DESC_ADDR
,
10026 page_to_phys(vmx
->nested
.pi_desc_page
) +
10027 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
10030 if (cpu_has_vmx_msr_bitmap() &&
10031 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
10032 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
10035 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
10036 CPU_BASED_USE_MSR_BITMAPS
);
10039 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
10041 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
10042 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10044 if (vcpu
->arch
.virtual_tsc_khz
== 0)
10047 /* Make sure short timeouts reliably trigger an immediate vmexit.
10048 * hrtimer_start does not guarantee this. */
10049 if (preemption_timeout
<= 1) {
10050 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
10054 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10055 preemption_timeout
*= 1000000;
10056 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
10057 hrtimer_start(&vmx
->nested
.preemption_timer
,
10058 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
10061 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
10062 struct vmcs12
*vmcs12
)
10064 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
10067 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
10068 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
10074 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
10075 struct vmcs12
*vmcs12
)
10077 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
10080 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
10086 static int nested_vmx_check_tpr_shadow_controls(struct kvm_vcpu
*vcpu
,
10087 struct vmcs12
*vmcs12
)
10089 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10092 if (!page_address_valid(vcpu
, vmcs12
->virtual_apic_page_addr
))
10099 * Merge L0's and L1's MSR bitmap, return false to indicate that
10100 * we do not use the hardware.
10102 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
10103 struct vmcs12
*vmcs12
)
10107 unsigned long *msr_bitmap_l1
;
10108 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
10110 /* This shortcut is ok because we support only x2APIC MSRs so far. */
10111 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
10114 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->msr_bitmap
);
10115 if (is_error_page(page
))
10117 msr_bitmap_l1
= (unsigned long *)kmap(page
);
10119 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
10121 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
10122 if (nested_cpu_has_apic_reg_virt(vmcs12
))
10123 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
10124 nested_vmx_disable_intercept_for_msr(
10125 msr_bitmap_l1
, msr_bitmap_l0
,
10128 nested_vmx_disable_intercept_for_msr(
10129 msr_bitmap_l1
, msr_bitmap_l0
,
10130 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
10131 MSR_TYPE_R
| MSR_TYPE_W
);
10133 if (nested_cpu_has_vid(vmcs12
)) {
10134 nested_vmx_disable_intercept_for_msr(
10135 msr_bitmap_l1
, msr_bitmap_l0
,
10136 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
10138 nested_vmx_disable_intercept_for_msr(
10139 msr_bitmap_l1
, msr_bitmap_l0
,
10140 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
10145 kvm_release_page_clean(page
);
10150 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
10151 struct vmcs12
*vmcs12
)
10153 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10154 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
10155 !nested_cpu_has_vid(vmcs12
) &&
10156 !nested_cpu_has_posted_intr(vmcs12
))
10160 * If virtualize x2apic mode is enabled,
10161 * virtualize apic access must be disabled.
10163 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
10164 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
10168 * If virtual interrupt delivery is enabled,
10169 * we must exit on external interrupts.
10171 if (nested_cpu_has_vid(vmcs12
) &&
10172 !nested_exit_on_intr(vcpu
))
10176 * bits 15:8 should be zero in posted_intr_nv,
10177 * the descriptor address has been already checked
10178 * in nested_get_vmcs12_pages.
10180 if (nested_cpu_has_posted_intr(vmcs12
) &&
10181 (!nested_cpu_has_vid(vmcs12
) ||
10182 !nested_exit_intr_ack_set(vcpu
) ||
10183 vmcs12
->posted_intr_nv
& 0xff00))
10186 /* tpr shadow is needed by all apicv features. */
10187 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
10193 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
10194 unsigned long count_field
,
10195 unsigned long addr_field
)
10200 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
10201 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
10207 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10208 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
10209 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
10210 pr_debug_ratelimited(
10211 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
10212 addr_field
, maxphyaddr
, count
, addr
);
10218 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
10219 struct vmcs12
*vmcs12
)
10221 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
10222 vmcs12
->vm_exit_msr_store_count
== 0 &&
10223 vmcs12
->vm_entry_msr_load_count
== 0)
10224 return 0; /* Fast path */
10225 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
10226 VM_EXIT_MSR_LOAD_ADDR
) ||
10227 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
10228 VM_EXIT_MSR_STORE_ADDR
) ||
10229 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
10230 VM_ENTRY_MSR_LOAD_ADDR
))
10235 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
10236 struct vmcs12
*vmcs12
)
10238 u64 address
= vmcs12
->pml_address
;
10239 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
10241 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
10242 if (!nested_cpu_has_ept(vmcs12
) ||
10243 !IS_ALIGNED(address
, 4096) ||
10244 address
>> maxphyaddr
)
10251 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
10252 struct vmx_msr_entry
*e
)
10254 /* x2APIC MSR accesses are not allowed */
10255 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
10257 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
10258 e
->index
== MSR_IA32_UCODE_REV
)
10260 if (e
->reserved
!= 0)
10265 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
10266 struct vmx_msr_entry
*e
)
10268 if (e
->index
== MSR_FS_BASE
||
10269 e
->index
== MSR_GS_BASE
||
10270 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
10271 nested_vmx_msr_check_common(vcpu
, e
))
10276 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
10277 struct vmx_msr_entry
*e
)
10279 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
10280 nested_vmx_msr_check_common(vcpu
, e
))
10286 * Load guest's/host's msr at nested entry/exit.
10287 * return 0 for success, entry index for failure.
10289 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10292 struct vmx_msr_entry e
;
10293 struct msr_data msr
;
10295 msr
.host_initiated
= false;
10296 for (i
= 0; i
< count
; i
++) {
10297 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
10299 pr_debug_ratelimited(
10300 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10301 __func__
, i
, gpa
+ i
* sizeof(e
));
10304 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
10305 pr_debug_ratelimited(
10306 "%s check failed (%u, 0x%x, 0x%x)\n",
10307 __func__
, i
, e
.index
, e
.reserved
);
10310 msr
.index
= e
.index
;
10311 msr
.data
= e
.value
;
10312 if (kvm_set_msr(vcpu
, &msr
)) {
10313 pr_debug_ratelimited(
10314 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10315 __func__
, i
, e
.index
, e
.value
);
10324 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10327 struct vmx_msr_entry e
;
10329 for (i
= 0; i
< count
; i
++) {
10330 struct msr_data msr_info
;
10331 if (kvm_vcpu_read_guest(vcpu
,
10332 gpa
+ i
* sizeof(e
),
10333 &e
, 2 * sizeof(u32
))) {
10334 pr_debug_ratelimited(
10335 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10336 __func__
, i
, gpa
+ i
* sizeof(e
));
10339 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10340 pr_debug_ratelimited(
10341 "%s check failed (%u, 0x%x, 0x%x)\n",
10342 __func__
, i
, e
.index
, e
.reserved
);
10345 msr_info
.host_initiated
= false;
10346 msr_info
.index
= e
.index
;
10347 if (kvm_get_msr(vcpu
, &msr_info
)) {
10348 pr_debug_ratelimited(
10349 "%s cannot read MSR (%u, 0x%x)\n",
10350 __func__
, i
, e
.index
);
10353 if (kvm_vcpu_write_guest(vcpu
,
10354 gpa
+ i
* sizeof(e
) +
10355 offsetof(struct vmx_msr_entry
, value
),
10356 &msr_info
.data
, sizeof(msr_info
.data
))) {
10357 pr_debug_ratelimited(
10358 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10359 __func__
, i
, e
.index
, msr_info
.data
);
10366 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10368 unsigned long invalid_mask
;
10370 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10371 return (val
& invalid_mask
) == 0;
10375 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10376 * emulating VM entry into a guest with EPT enabled.
10377 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10378 * is assigned to entry_failure_code on failure.
10380 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10381 u32
*entry_failure_code
)
10383 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10384 if (!nested_cr3_valid(vcpu
, cr3
)) {
10385 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10390 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10391 * must not be dereferenced.
10393 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10395 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10396 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10401 vcpu
->arch
.cr3
= cr3
;
10402 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10405 kvm_mmu_reset_context(vcpu
);
10410 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10411 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10412 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10413 * guest in a way that will both be appropriate to L1's requests, and our
10414 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10415 * function also has additional necessary side-effects, like setting various
10416 * vcpu->arch fields.
10417 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10418 * is assigned to entry_failure_code on failure.
10420 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10421 bool from_vmentry
, u32
*entry_failure_code
)
10423 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10424 u32 exec_control
, vmcs12_exec_ctrl
;
10426 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10427 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10428 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10429 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10430 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10431 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10432 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10433 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10434 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10435 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10436 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10437 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10438 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10439 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10440 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10441 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10442 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10443 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10444 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10445 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10446 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10447 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10448 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10449 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10450 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10451 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10452 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10453 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10454 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10455 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10456 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10457 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10458 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10459 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10460 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10461 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10463 if (from_vmentry
&&
10464 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10465 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10466 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10468 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10469 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10471 if (from_vmentry
) {
10472 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10473 vmcs12
->vm_entry_intr_info_field
);
10474 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10475 vmcs12
->vm_entry_exception_error_code
);
10476 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10477 vmcs12
->vm_entry_instruction_len
);
10478 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10479 vmcs12
->guest_interruptibility_info
);
10480 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10481 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10483 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10485 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10486 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10487 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10488 vmcs12
->guest_pending_dbg_exceptions
);
10489 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10490 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10492 if (nested_cpu_has_xsaves(vmcs12
))
10493 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10494 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10496 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10498 /* Preemption timer setting is only taken from vmcs01. */
10499 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10500 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10501 if (vmx
->hv_deadline_tsc
== -1)
10502 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10504 /* Posted interrupts setting is only taken from vmcs12. */
10505 if (nested_cpu_has_posted_intr(vmcs12
)) {
10506 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10507 vmx
->nested
.pi_pending
= false;
10508 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10510 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10513 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10515 vmx
->nested
.preemption_timer_expired
= false;
10516 if (nested_cpu_has_preemption_timer(vmcs12
))
10517 vmx_start_preemption_timer(vcpu
);
10520 * Whether page-faults are trapped is determined by a combination of
10521 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10522 * If enable_ept, L0 doesn't care about page faults and we should
10523 * set all of these to L1's desires. However, if !enable_ept, L0 does
10524 * care about (at least some) page faults, and because it is not easy
10525 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10526 * to exit on each and every L2 page fault. This is done by setting
10527 * MASK=MATCH=0 and (see below) EB.PF=1.
10528 * Note that below we don't need special code to set EB.PF beyond the
10529 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10530 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10531 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10533 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10534 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10535 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10536 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10538 if (cpu_has_secondary_exec_ctrls()) {
10539 exec_control
= vmx
->secondary_exec_control
;
10541 /* Take the following fields only from vmcs12 */
10542 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10543 SECONDARY_EXEC_ENABLE_INVPCID
|
10544 SECONDARY_EXEC_RDTSCP
|
10545 SECONDARY_EXEC_XSAVES
|
10546 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10547 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
10548 SECONDARY_EXEC_ENABLE_VMFUNC
);
10549 if (nested_cpu_has(vmcs12
,
10550 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10551 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10552 ~SECONDARY_EXEC_ENABLE_PML
;
10553 exec_control
|= vmcs12_exec_ctrl
;
10556 /* All VMFUNCs are currently emulated through L0 vmexits. */
10557 if (exec_control
& SECONDARY_EXEC_ENABLE_VMFUNC
)
10558 vmcs_write64(VM_FUNCTION_CONTROL
, 0);
10560 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10561 vmcs_write64(EOI_EXIT_BITMAP0
,
10562 vmcs12
->eoi_exit_bitmap0
);
10563 vmcs_write64(EOI_EXIT_BITMAP1
,
10564 vmcs12
->eoi_exit_bitmap1
);
10565 vmcs_write64(EOI_EXIT_BITMAP2
,
10566 vmcs12
->eoi_exit_bitmap2
);
10567 vmcs_write64(EOI_EXIT_BITMAP3
,
10568 vmcs12
->eoi_exit_bitmap3
);
10569 vmcs_write16(GUEST_INTR_STATUS
,
10570 vmcs12
->guest_intr_status
);
10574 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10575 * nested_get_vmcs12_pages will either fix it up or
10576 * remove the VM execution control.
10578 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10579 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10581 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10586 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10587 * Some constant fields are set here by vmx_set_constant_host_state().
10588 * Other fields are different per CPU, and will be set later when
10589 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10591 vmx_set_constant_host_state(vmx
);
10594 * Set the MSR load/store lists to match L0's settings.
10596 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10597 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10598 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10599 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10600 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10603 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10604 * entry, but only if the current (host) sp changed from the value
10605 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10606 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10607 * here we just force the write to happen on entry.
10611 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10612 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10613 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10614 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10615 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10618 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10619 * nested_get_vmcs12_pages can't fix it up, the illegal value
10620 * will result in a VM entry failure.
10622 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10623 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10624 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10626 #ifdef CONFIG_X86_64
10627 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10628 CPU_BASED_CR8_STORE_EXITING
;
10633 * Merging of IO bitmap not currently supported.
10634 * Rather, exit every time.
10636 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10637 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10639 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10641 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10642 * bitwise-or of what L1 wants to trap for L2, and what we want to
10643 * trap. Note that CR0.TS also needs updating - we do this later.
10645 update_exception_bitmap(vcpu
);
10646 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10647 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10649 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10650 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10651 * bits are further modified by vmx_set_efer() below.
10653 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10655 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10656 * emulated by vmx_set_efer(), below.
10658 vm_entry_controls_init(vmx
,
10659 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10660 ~VM_ENTRY_IA32E_MODE
) |
10661 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10663 if (from_vmentry
&&
10664 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10665 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10666 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10667 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10668 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10671 set_cr4_guest_host_mask(vmx
);
10673 if (from_vmentry
&&
10674 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10675 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10677 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10678 vmcs_write64(TSC_OFFSET
,
10679 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10681 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10682 if (kvm_has_tsc_control
)
10683 decache_tsc_multiplier(vmx
);
10687 * There is no direct mapping between vpid02 and vpid12, the
10688 * vpid02 is per-vCPU for L0 and reused while the value of
10689 * vpid12 is changed w/ one invvpid during nested vmentry.
10690 * The vpid12 is allocated by L1 for L2, so it will not
10691 * influence global bitmap(for vpid01 and vpid02 allocation)
10692 * even if spawn a lot of nested vCPUs.
10694 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10695 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10696 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10697 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10698 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10701 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10702 vmx_flush_tlb(vcpu
);
10709 * Conceptually we want to copy the PML address and index from
10710 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10711 * since we always flush the log on each vmexit, this happens
10712 * to be equivalent to simply resetting the fields in vmcs02.
10714 ASSERT(vmx
->pml_pg
);
10715 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10716 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10719 if (nested_cpu_has_ept(vmcs12
)) {
10720 if (nested_ept_init_mmu_context(vcpu
)) {
10721 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10724 } else if (nested_cpu_has2(vmcs12
,
10725 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10726 vmx_flush_tlb_ept_only(vcpu
);
10730 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10731 * bits which we consider mandatory enabled.
10732 * The CR0_READ_SHADOW is what L2 should have expected to read given
10733 * the specifications by L1; It's not enough to take
10734 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10735 * have more bits than L1 expected.
10737 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10738 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10740 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10741 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10743 if (from_vmentry
&&
10744 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10745 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10746 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10747 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10749 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10750 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10751 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10753 /* Shadow page tables on either EPT or shadow page tables. */
10754 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10755 entry_failure_code
))
10759 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10762 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10765 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10766 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10767 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10768 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10771 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10772 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10776 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10778 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10780 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10781 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10782 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10784 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10785 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10787 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10788 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10790 if (nested_vmx_check_tpr_shadow_controls(vcpu
, vmcs12
))
10791 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10793 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10794 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10796 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10797 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10799 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10800 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10802 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10803 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10804 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10805 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10806 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10807 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10808 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10809 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10810 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10811 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10812 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10813 vmx
->nested
.nested_vmx_exit_ctls_low
,
10814 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10815 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10816 vmx
->nested
.nested_vmx_entry_ctls_low
,
10817 vmx
->nested
.nested_vmx_entry_ctls_high
))
10818 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10820 if (nested_cpu_has_vmfunc(vmcs12
)) {
10821 if (vmcs12
->vm_function_control
&
10822 ~vmx
->nested
.nested_vmx_vmfunc_controls
)
10823 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10825 if (nested_cpu_has_eptp_switching(vmcs12
)) {
10826 if (!nested_cpu_has_ept(vmcs12
) ||
10827 !page_address_valid(vcpu
, vmcs12
->eptp_list_address
))
10828 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10832 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10833 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10835 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10836 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10837 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10838 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10843 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10848 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10850 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10851 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10854 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10855 vmcs12
->vmcs_link_pointer
!= -1ull) {
10856 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10861 * If the load IA32_EFER VM-entry control is 1, the following checks
10862 * are performed on the field for the IA32_EFER MSR:
10863 * - Bits reserved in the IA32_EFER MSR must be 0.
10864 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10865 * the IA-32e mode guest VM-exit control. It must also be identical
10866 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10869 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10870 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10871 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10872 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10873 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10874 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10875 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10880 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10881 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10882 * the values of the LMA and LME bits in the field must each be that of
10883 * the host address-space size VM-exit control.
10885 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10886 ia32e
= (vmcs12
->vm_exit_controls
&
10887 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10888 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10889 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10890 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10894 if ((vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
) &&
10895 (is_noncanonical_address(vmcs12
->guest_bndcfgs
& PAGE_MASK
, vcpu
) ||
10896 (vmcs12
->guest_bndcfgs
& MSR_IA32_BNDCFGS_RSVD
)))
10902 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10905 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10906 struct loaded_vmcs
*vmcs02
;
10910 vmcs02
= nested_get_current_vmcs02(vmx
);
10914 enter_guest_mode(vcpu
);
10916 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10917 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10919 vmx_switch_vmcs(vcpu
, vmcs02
);
10920 vmx_segment_cache_clear(vmx
);
10922 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10923 leave_guest_mode(vcpu
);
10924 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10925 nested_vmx_entry_failure(vcpu
, vmcs12
,
10926 EXIT_REASON_INVALID_STATE
, exit_qual
);
10930 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10932 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10933 vmcs12
->vm_entry_msr_load_addr
,
10934 vmcs12
->vm_entry_msr_load_count
);
10935 if (msr_entry_idx
) {
10936 leave_guest_mode(vcpu
);
10937 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10938 nested_vmx_entry_failure(vcpu
, vmcs12
,
10939 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10944 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10945 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10946 * returned as far as L1 is concerned. It will only return (and set
10947 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10953 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10954 * for running an L2 nested guest.
10956 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10958 struct vmcs12
*vmcs12
;
10959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10960 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10964 if (!nested_vmx_check_permission(vcpu
))
10967 if (!nested_vmx_check_vmcs12(vcpu
))
10970 vmcs12
= get_vmcs12(vcpu
);
10972 if (enable_shadow_vmcs
)
10973 copy_shadow_to_vmcs12(vmx
);
10976 * The nested entry process starts with enforcing various prerequisites
10977 * on vmcs12 as required by the Intel SDM, and act appropriately when
10978 * they fail: As the SDM explains, some conditions should cause the
10979 * instruction to fail, while others will cause the instruction to seem
10980 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10981 * To speed up the normal (success) code path, we should avoid checking
10982 * for misconfigurations which will anyway be caught by the processor
10983 * when using the merged vmcs02.
10985 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10986 nested_vmx_failValid(vcpu
,
10987 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10991 if (vmcs12
->launch_state
== launch
) {
10992 nested_vmx_failValid(vcpu
,
10993 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10994 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10998 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
11000 nested_vmx_failValid(vcpu
, ret
);
11005 * After this point, the trap flag no longer triggers a singlestep trap
11006 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
11007 * This is not 100% correct; for performance reasons, we delegate most
11008 * of the checks on host state to the processor. If those fail,
11009 * the singlestep trap is missed.
11011 skip_emulated_instruction(vcpu
);
11013 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
11015 nested_vmx_entry_failure(vcpu
, vmcs12
,
11016 EXIT_REASON_INVALID_STATE
, exit_qual
);
11021 * We're finally done with prerequisite checking, and can start with
11022 * the nested entry.
11025 ret
= enter_vmx_non_root_mode(vcpu
, true);
11029 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
11030 return kvm_vcpu_halt(vcpu
);
11032 vmx
->nested
.nested_run_pending
= 1;
11037 return kvm_skip_emulated_instruction(vcpu
);
11041 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
11042 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
11043 * This function returns the new value we should put in vmcs12.guest_cr0.
11044 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
11045 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
11046 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
11047 * didn't trap the bit, because if L1 did, so would L0).
11048 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
11049 * been modified by L2, and L1 knows it. So just leave the old value of
11050 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
11051 * isn't relevant, because if L0 traps this bit it can set it to anything.
11052 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
11053 * changed these bits, and therefore they need to be updated, but L0
11054 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
11055 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
11057 static inline unsigned long
11058 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11061 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
11062 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
11063 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
11064 vcpu
->arch
.cr0_guest_owned_bits
));
11067 static inline unsigned long
11068 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11071 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
11072 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
11073 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
11074 vcpu
->arch
.cr4_guest_owned_bits
));
11077 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
11078 struct vmcs12
*vmcs12
)
11083 if (vcpu
->arch
.exception
.injected
) {
11084 nr
= vcpu
->arch
.exception
.nr
;
11085 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11087 if (kvm_exception_is_soft(nr
)) {
11088 vmcs12
->vm_exit_instruction_len
=
11089 vcpu
->arch
.event_exit_inst_len
;
11090 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
11092 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
11094 if (vcpu
->arch
.exception
.has_error_code
) {
11095 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
11096 vmcs12
->idt_vectoring_error_code
=
11097 vcpu
->arch
.exception
.error_code
;
11100 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11101 } else if (vcpu
->arch
.nmi_injected
) {
11102 vmcs12
->idt_vectoring_info_field
=
11103 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
11104 } else if (vcpu
->arch
.interrupt
.pending
) {
11105 nr
= vcpu
->arch
.interrupt
.nr
;
11106 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
11108 if (vcpu
->arch
.interrupt
.soft
) {
11109 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
11110 vmcs12
->vm_entry_instruction_len
=
11111 vcpu
->arch
.event_exit_inst_len
;
11113 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
11115 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
11119 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
11121 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11122 unsigned long exit_qual
;
11123 bool block_nested_events
=
11124 vmx
->nested
.nested_run_pending
|| kvm_event_needs_reinjection(vcpu
);
11126 if (vcpu
->arch
.exception
.pending
&&
11127 nested_vmx_check_exception(vcpu
, &exit_qual
)) {
11128 if (block_nested_events
)
11130 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
11131 vcpu
->arch
.exception
.pending
= false;
11135 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
11136 vmx
->nested
.preemption_timer_expired
) {
11137 if (block_nested_events
)
11139 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
11143 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
11144 if (block_nested_events
)
11146 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
11147 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
11148 INTR_INFO_VALID_MASK
, 0);
11150 * The NMI-triggered VM exit counts as injection:
11151 * clear this one and block further NMIs.
11153 vcpu
->arch
.nmi_pending
= 0;
11154 vmx_set_nmi_mask(vcpu
, true);
11158 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
11159 nested_exit_on_intr(vcpu
)) {
11160 if (block_nested_events
)
11162 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
11166 vmx_complete_nested_posted_interrupt(vcpu
);
11170 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
11172 ktime_t remaining
=
11173 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
11176 if (ktime_to_ns(remaining
) <= 0)
11179 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
11180 do_div(value
, 1000000);
11181 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
11185 * Update the guest state fields of vmcs12 to reflect changes that
11186 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
11187 * VM-entry controls is also updated, since this is really a guest
11190 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
11192 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
11193 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
11195 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
11196 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
11197 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
11199 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
11200 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
11201 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
11202 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
11203 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
11204 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
11205 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
11206 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
11207 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
11208 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
11209 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
11210 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
11211 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
11212 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
11213 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
11214 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
11215 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
11216 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
11217 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
11218 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
11219 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
11220 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
11221 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
11222 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
11223 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
11224 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
11225 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
11226 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
11227 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
11228 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
11229 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
11230 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
11231 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
11232 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
11233 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
11234 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
11236 vmcs12
->guest_interruptibility_info
=
11237 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
11238 vmcs12
->guest_pending_dbg_exceptions
=
11239 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
11240 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
11241 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
11243 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
11245 if (nested_cpu_has_preemption_timer(vmcs12
)) {
11246 if (vmcs12
->vm_exit_controls
&
11247 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
11248 vmcs12
->vmx_preemption_timer_value
=
11249 vmx_get_preemption_timer_value(vcpu
);
11250 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
11254 * In some cases (usually, nested EPT), L2 is allowed to change its
11255 * own CR3 without exiting. If it has changed it, we must keep it.
11256 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
11257 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
11259 * Additionally, restore L2's PDPTR to vmcs12.
11262 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
11263 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
11264 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
11265 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
11266 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
11269 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
11271 if (nested_cpu_has_vid(vmcs12
))
11272 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
11274 vmcs12
->vm_entry_controls
=
11275 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
11276 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
11278 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
11279 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
11280 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
11283 /* TODO: These cannot have changed unless we have MSR bitmaps and
11284 * the relevant bit asks not to trap the change */
11285 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
11286 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
11287 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
11288 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
11289 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
11290 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
11291 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
11292 if (kvm_mpx_supported())
11293 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
11297 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
11298 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
11299 * and this function updates it to reflect the changes to the guest state while
11300 * L2 was running (and perhaps made some exits which were handled directly by L0
11301 * without going back to L1), and to reflect the exit reason.
11302 * Note that we do not have to copy here all VMCS fields, just those that
11303 * could have changed by the L2 guest or the exit - i.e., the guest-state and
11304 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
11305 * which already writes to vmcs12 directly.
11307 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
11308 u32 exit_reason
, u32 exit_intr_info
,
11309 unsigned long exit_qualification
)
11311 /* update guest state fields: */
11312 sync_vmcs12(vcpu
, vmcs12
);
11314 /* update exit information fields: */
11316 vmcs12
->vm_exit_reason
= exit_reason
;
11317 vmcs12
->exit_qualification
= exit_qualification
;
11318 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
11320 vmcs12
->idt_vectoring_info_field
= 0;
11321 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
11322 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
11324 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
11325 vmcs12
->launch_state
= 1;
11327 /* vm_entry_intr_info_field is cleared on exit. Emulate this
11328 * instead of reading the real value. */
11329 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
11332 * Transfer the event that L0 or L1 may wanted to inject into
11333 * L2 to IDT_VECTORING_INFO_FIELD.
11335 vmcs12_save_pending_event(vcpu
, vmcs12
);
11339 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
11340 * preserved above and would only end up incorrectly in L1.
11342 vcpu
->arch
.nmi_injected
= false;
11343 kvm_clear_exception_queue(vcpu
);
11344 kvm_clear_interrupt_queue(vcpu
);
11347 static void load_vmcs12_mmu_host_state(struct kvm_vcpu
*vcpu
,
11348 struct vmcs12
*vmcs12
)
11350 u32 entry_failure_code
;
11352 nested_ept_uninit_mmu_context(vcpu
);
11355 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11356 * couldn't have changed.
11358 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11359 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11362 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11366 * A part of what we need to when the nested L2 guest exits and we want to
11367 * run its L1 parent, is to reset L1's guest state to the host state specified
11369 * This function is to be called not only on normal nested exit, but also on
11370 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11371 * Failures During or After Loading Guest State").
11372 * This function should be called when the active VMCS is L1's (vmcs01).
11374 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11375 struct vmcs12
*vmcs12
)
11377 struct kvm_segment seg
;
11379 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11380 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11381 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11382 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11384 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11385 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11387 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11388 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11389 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11391 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11392 * actually changed, because vmx_set_cr0 refers to efer set above.
11394 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11395 * (KVM doesn't change it);
11397 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11398 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11400 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11401 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11402 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11404 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11408 * Trivially support vpid by letting L2s share their parent
11409 * L1's vpid. TODO: move to a more elaborate solution, giving
11410 * each L2 its own vpid and exposing the vpid feature to L1.
11412 vmx_flush_tlb(vcpu
);
11414 /* Restore posted intr vector. */
11415 if (nested_cpu_has_posted_intr(vmcs12
))
11416 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11418 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11419 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11420 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11421 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11422 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11423 vmcs_write32(GUEST_IDTR_LIMIT
, 0xFFFF);
11424 vmcs_write32(GUEST_GDTR_LIMIT
, 0xFFFF);
11426 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11427 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11428 vmcs_write64(GUEST_BNDCFGS
, 0);
11430 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11431 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11432 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11434 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11435 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11436 vmcs12
->host_ia32_perf_global_ctrl
);
11438 /* Set L1 segment info according to Intel SDM
11439 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11440 seg
= (struct kvm_segment
) {
11442 .limit
= 0xFFFFFFFF,
11443 .selector
= vmcs12
->host_cs_selector
,
11449 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11453 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11454 seg
= (struct kvm_segment
) {
11456 .limit
= 0xFFFFFFFF,
11463 seg
.selector
= vmcs12
->host_ds_selector
;
11464 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11465 seg
.selector
= vmcs12
->host_es_selector
;
11466 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11467 seg
.selector
= vmcs12
->host_ss_selector
;
11468 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11469 seg
.selector
= vmcs12
->host_fs_selector
;
11470 seg
.base
= vmcs12
->host_fs_base
;
11471 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11472 seg
.selector
= vmcs12
->host_gs_selector
;
11473 seg
.base
= vmcs12
->host_gs_base
;
11474 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11475 seg
= (struct kvm_segment
) {
11476 .base
= vmcs12
->host_tr_base
,
11478 .selector
= vmcs12
->host_tr_selector
,
11482 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11484 kvm_set_dr(vcpu
, 7, 0x400);
11485 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11487 if (cpu_has_vmx_msr_bitmap())
11488 vmx_set_msr_bitmap(vcpu
);
11490 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11491 vmcs12
->vm_exit_msr_load_count
))
11492 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11496 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11497 * and modify vmcs12 to make it see what it would expect to see there if
11498 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11500 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11501 u32 exit_intr_info
,
11502 unsigned long exit_qualification
)
11504 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11505 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11507 /* trying to cancel vmlaunch/vmresume is a bug */
11508 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11511 * The only expected VM-instruction error is "VM entry with
11512 * invalid control field(s)." Anything else indicates a
11515 WARN_ON_ONCE(vmx
->fail
&& (vmcs_read32(VM_INSTRUCTION_ERROR
) !=
11516 VMXERR_ENTRY_INVALID_CONTROL_FIELD
));
11518 leave_guest_mode(vcpu
);
11520 if (likely(!vmx
->fail
)) {
11521 if (exit_reason
== -1)
11522 sync_vmcs12(vcpu
, vmcs12
);
11524 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11525 exit_qualification
);
11527 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11528 vmcs12
->vm_exit_msr_store_count
))
11529 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11532 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11533 vm_entry_controls_reset_shadow(vmx
);
11534 vm_exit_controls_reset_shadow(vmx
);
11535 vmx_segment_cache_clear(vmx
);
11537 /* if no vmcs02 cache requested, remove the one we used */
11538 if (VMCS02_POOL_SIZE
== 0)
11539 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11541 /* Update any VMCS fields that might have changed while L2 ran */
11542 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11543 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11544 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11545 if (vmx
->hv_deadline_tsc
== -1)
11546 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11547 PIN_BASED_VMX_PREEMPTION_TIMER
);
11549 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11550 PIN_BASED_VMX_PREEMPTION_TIMER
);
11551 if (kvm_has_tsc_control
)
11552 decache_tsc_multiplier(vmx
);
11554 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11555 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11556 vmx_set_virtual_x2apic_mode(vcpu
,
11557 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11558 } else if (!nested_cpu_has_ept(vmcs12
) &&
11559 nested_cpu_has2(vmcs12
,
11560 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11561 vmx_flush_tlb_ept_only(vcpu
);
11564 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11567 /* Unpin physical memory we referred to in vmcs02 */
11568 if (vmx
->nested
.apic_access_page
) {
11569 kvm_release_page_dirty(vmx
->nested
.apic_access_page
);
11570 vmx
->nested
.apic_access_page
= NULL
;
11572 if (vmx
->nested
.virtual_apic_page
) {
11573 kvm_release_page_dirty(vmx
->nested
.virtual_apic_page
);
11574 vmx
->nested
.virtual_apic_page
= NULL
;
11576 if (vmx
->nested
.pi_desc_page
) {
11577 kunmap(vmx
->nested
.pi_desc_page
);
11578 kvm_release_page_dirty(vmx
->nested
.pi_desc_page
);
11579 vmx
->nested
.pi_desc_page
= NULL
;
11580 vmx
->nested
.pi_desc
= NULL
;
11584 * We are now running in L2, mmu_notifier will force to reload the
11585 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11587 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11589 if (enable_shadow_vmcs
&& exit_reason
!= -1)
11590 vmx
->nested
.sync_shadow_vmcs
= true;
11592 /* in case we halted in L2 */
11593 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11595 if (likely(!vmx
->fail
)) {
11597 * TODO: SDM says that with acknowledge interrupt on
11598 * exit, bit 31 of the VM-exit interrupt information
11599 * (valid interrupt) is always set to 1 on
11600 * EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't
11601 * need kvm_cpu_has_interrupt(). See the commit
11602 * message for details.
11604 if (nested_exit_intr_ack_set(vcpu
) &&
11605 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11606 kvm_cpu_has_interrupt(vcpu
)) {
11607 int irq
= kvm_cpu_get_interrupt(vcpu
);
11609 vmcs12
->vm_exit_intr_info
= irq
|
11610 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11613 if (exit_reason
!= -1)
11614 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11615 vmcs12
->exit_qualification
,
11616 vmcs12
->idt_vectoring_info_field
,
11617 vmcs12
->vm_exit_intr_info
,
11618 vmcs12
->vm_exit_intr_error_code
,
11621 load_vmcs12_host_state(vcpu
, vmcs12
);
11627 * After an early L2 VM-entry failure, we're now back
11628 * in L1 which thinks it just finished a VMLAUNCH or
11629 * VMRESUME instruction, so we need to set the failure
11630 * flag and the VM-instruction error field of the VMCS
11633 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
11635 load_vmcs12_mmu_host_state(vcpu
, vmcs12
);
11638 * The emulated instruction was already skipped in
11639 * nested_vmx_run, but the updated RIP was never
11640 * written back to the vmcs01.
11642 skip_emulated_instruction(vcpu
);
11647 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11649 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11651 if (is_guest_mode(vcpu
)) {
11652 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11653 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11655 free_nested(to_vmx(vcpu
));
11659 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11660 * 23.7 "VM-entry failures during or after loading guest state" (this also
11661 * lists the acceptable exit-reason and exit-qualification parameters).
11662 * It should only be called before L2 actually succeeded to run, and when
11663 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11665 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11666 struct vmcs12
*vmcs12
,
11667 u32 reason
, unsigned long qualification
)
11669 load_vmcs12_host_state(vcpu
, vmcs12
);
11670 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11671 vmcs12
->exit_qualification
= qualification
;
11672 nested_vmx_succeed(vcpu
);
11673 if (enable_shadow_vmcs
)
11674 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11677 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11678 struct x86_instruction_info
*info
,
11679 enum x86_intercept_stage stage
)
11681 return X86EMUL_CONTINUE
;
11684 #ifdef CONFIG_X86_64
11685 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11686 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11687 u64 divisor
, u64
*result
)
11689 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11691 /* To avoid the overflow on divq */
11692 if (high
>= divisor
)
11695 /* Low hold the result, high hold rem which is discarded */
11696 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11697 "rm" (divisor
), "0" (low
), "1" (high
));
11703 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11706 u64 tscl
= rdtsc();
11707 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11708 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11710 /* Convert to host delta tsc if tsc scaling is enabled */
11711 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11712 u64_shl_div_u64(delta_tsc
,
11713 kvm_tsc_scaling_ratio_frac_bits
,
11714 vcpu
->arch
.tsc_scaling_ratio
,
11719 * If the delta tsc can't fit in the 32 bit after the multi shift,
11720 * we can't use the preemption timer.
11721 * It's possible that it fits on later vmentries, but checking
11722 * on every vmentry is costly so we just use an hrtimer.
11724 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11727 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11728 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11729 PIN_BASED_VMX_PREEMPTION_TIMER
);
11731 return delta_tsc
== 0;
11734 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11736 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11737 vmx
->hv_deadline_tsc
= -1;
11738 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11739 PIN_BASED_VMX_PREEMPTION_TIMER
);
11743 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11746 shrink_ple_window(vcpu
);
11749 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11750 struct kvm_memory_slot
*slot
)
11752 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11753 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11756 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11757 struct kvm_memory_slot
*slot
)
11759 kvm_mmu_slot_set_dirty(kvm
, slot
);
11762 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11764 kvm_flush_pml_buffers(kvm
);
11767 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11769 struct vmcs12
*vmcs12
;
11770 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11772 struct page
*page
= NULL
;
11775 if (is_guest_mode(vcpu
)) {
11776 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11779 * Check if PML is enabled for the nested guest.
11780 * Whether eptp bit 6 is set is already checked
11781 * as part of A/D emulation.
11783 vmcs12
= get_vmcs12(vcpu
);
11784 if (!nested_cpu_has_pml(vmcs12
))
11787 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11788 vmx
->nested
.pml_full
= true;
11792 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11794 page
= kvm_vcpu_gpa_to_page(vcpu
, vmcs12
->pml_address
);
11795 if (is_error_page(page
))
11798 pml_address
= kmap(page
);
11799 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11801 kvm_release_page_clean(page
);
11807 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11808 struct kvm_memory_slot
*memslot
,
11809 gfn_t offset
, unsigned long mask
)
11811 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11814 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11816 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11817 struct pi_desc old
, new;
11821 old
.control
= new.control
= pi_desc
->control
;
11822 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11823 "Wakeup handler not enabled while the VCPU is blocked\n");
11825 dest
= cpu_physical_id(vcpu
->cpu
);
11827 if (x2apic_enabled())
11830 new.ndst
= (dest
<< 8) & 0xFF00;
11832 /* set 'NV' to 'notification vector' */
11833 new.nv
= POSTED_INTR_VECTOR
;
11834 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11835 new.control
) != old
.control
);
11837 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11838 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11839 list_del(&vcpu
->blocked_vcpu_list
);
11840 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11841 vcpu
->pre_pcpu
= -1;
11846 * This routine does the following things for vCPU which is going
11847 * to be blocked if VT-d PI is enabled.
11848 * - Store the vCPU to the wakeup list, so when interrupts happen
11849 * we can find the right vCPU to wake up.
11850 * - Change the Posted-interrupt descriptor as below:
11851 * 'NDST' <-- vcpu->pre_pcpu
11852 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11853 * - If 'ON' is set during this process, which means at least one
11854 * interrupt is posted for this vCPU, we cannot block it, in
11855 * this case, return 1, otherwise, return 0.
11858 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11861 struct pi_desc old
, new;
11862 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11864 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11865 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11866 !kvm_vcpu_apicv_active(vcpu
))
11869 WARN_ON(irqs_disabled());
11870 local_irq_disable();
11871 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11872 vcpu
->pre_pcpu
= vcpu
->cpu
;
11873 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11874 list_add_tail(&vcpu
->blocked_vcpu_list
,
11875 &per_cpu(blocked_vcpu_on_cpu
,
11877 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11881 old
.control
= new.control
= pi_desc
->control
;
11883 WARN((pi_desc
->sn
== 1),
11884 "Warning: SN field of posted-interrupts "
11885 "is set before blocking\n");
11888 * Since vCPU can be preempted during this process,
11889 * vcpu->cpu could be different with pre_pcpu, we
11890 * need to set pre_pcpu as the destination of wakeup
11891 * notification event, then we can find the right vCPU
11892 * to wakeup in wakeup handler if interrupts happen
11893 * when the vCPU is in blocked state.
11895 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11897 if (x2apic_enabled())
11900 new.ndst
= (dest
<< 8) & 0xFF00;
11902 /* set 'NV' to 'wakeup vector' */
11903 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11904 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11905 new.control
) != old
.control
);
11907 /* We should not block the vCPU if an interrupt is posted for it. */
11908 if (pi_test_on(pi_desc
) == 1)
11909 __pi_post_block(vcpu
);
11911 local_irq_enable();
11912 return (vcpu
->pre_pcpu
== -1);
11915 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11917 if (pi_pre_block(vcpu
))
11920 if (kvm_lapic_hv_timer_in_use(vcpu
))
11921 kvm_lapic_switch_to_sw_timer(vcpu
);
11926 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11928 if (vcpu
->pre_pcpu
== -1)
11931 WARN_ON(irqs_disabled());
11932 local_irq_disable();
11933 __pi_post_block(vcpu
);
11934 local_irq_enable();
11937 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11939 if (kvm_x86_ops
->set_hv_timer
)
11940 kvm_lapic_switch_to_hv_timer(vcpu
);
11942 pi_post_block(vcpu
);
11946 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11949 * @host_irq: host irq of the interrupt
11950 * @guest_irq: gsi of the interrupt
11951 * @set: set or unset PI
11952 * returns 0 on success, < 0 on failure
11954 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11955 uint32_t guest_irq
, bool set
)
11957 struct kvm_kernel_irq_routing_entry
*e
;
11958 struct kvm_irq_routing_table
*irq_rt
;
11959 struct kvm_lapic_irq irq
;
11960 struct kvm_vcpu
*vcpu
;
11961 struct vcpu_data vcpu_info
;
11964 if (!kvm_arch_has_assigned_device(kvm
) ||
11965 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11966 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11969 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11970 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11971 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11972 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11973 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11974 guest_irq
, irq_rt
->nr_rt_entries
);
11978 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11979 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11982 * VT-d PI cannot support posting multicast/broadcast
11983 * interrupts to a vCPU, we still use interrupt remapping
11984 * for these kind of interrupts.
11986 * For lowest-priority interrupts, we only support
11987 * those with single CPU as the destination, e.g. user
11988 * configures the interrupts via /proc/irq or uses
11989 * irqbalance to make the interrupts single-CPU.
11991 * We will support full lowest-priority interrupt later.
11994 kvm_set_msi_irq(kvm
, e
, &irq
);
11995 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11997 * Make sure the IRTE is in remapped mode if
11998 * we don't handle it in posted mode.
12000 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12003 "failed to back to remapped mode, irq: %u\n",
12011 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
12012 vcpu_info
.vector
= irq
.vector
;
12014 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
12015 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
12018 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
12020 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
12023 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
12031 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
12035 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
12037 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
12038 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
12039 FEATURE_CONTROL_LMCE
;
12041 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
12042 ~FEATURE_CONTROL_LMCE
;
12045 static int vmx_smi_allowed(struct kvm_vcpu
*vcpu
)
12047 /* we need a nested vmexit to enter SMM, postpone if run is pending */
12048 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
12053 static int vmx_pre_enter_smm(struct kvm_vcpu
*vcpu
, char *smstate
)
12055 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12057 vmx
->nested
.smm
.guest_mode
= is_guest_mode(vcpu
);
12058 if (vmx
->nested
.smm
.guest_mode
)
12059 nested_vmx_vmexit(vcpu
, -1, 0, 0);
12061 vmx
->nested
.smm
.vmxon
= vmx
->nested
.vmxon
;
12062 vmx
->nested
.vmxon
= false;
12066 static int vmx_pre_leave_smm(struct kvm_vcpu
*vcpu
, u64 smbase
)
12068 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
12071 if (vmx
->nested
.smm
.vmxon
) {
12072 vmx
->nested
.vmxon
= true;
12073 vmx
->nested
.smm
.vmxon
= false;
12076 if (vmx
->nested
.smm
.guest_mode
) {
12077 vcpu
->arch
.hflags
&= ~HF_SMM_MASK
;
12078 ret
= enter_vmx_non_root_mode(vcpu
, false);
12079 vcpu
->arch
.hflags
|= HF_SMM_MASK
;
12083 vmx
->nested
.smm
.guest_mode
= false;
12088 static int enable_smi_window(struct kvm_vcpu
*vcpu
)
12093 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
12094 .cpu_has_kvm_support
= cpu_has_kvm_support
,
12095 .disabled_by_bios
= vmx_disabled_by_bios
,
12096 .hardware_setup
= hardware_setup
,
12097 .hardware_unsetup
= hardware_unsetup
,
12098 .check_processor_compatibility
= vmx_check_processor_compat
,
12099 .hardware_enable
= hardware_enable
,
12100 .hardware_disable
= hardware_disable
,
12101 .cpu_has_accelerated_tpr
= report_flexpriority
,
12102 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
12104 .vcpu_create
= vmx_create_vcpu
,
12105 .vcpu_free
= vmx_free_vcpu
,
12106 .vcpu_reset
= vmx_vcpu_reset
,
12108 .prepare_guest_switch
= vmx_save_host_state
,
12109 .vcpu_load
= vmx_vcpu_load
,
12110 .vcpu_put
= vmx_vcpu_put
,
12112 .update_bp_intercept
= update_exception_bitmap
,
12113 .get_msr
= vmx_get_msr
,
12114 .set_msr
= vmx_set_msr
,
12115 .get_segment_base
= vmx_get_segment_base
,
12116 .get_segment
= vmx_get_segment
,
12117 .set_segment
= vmx_set_segment
,
12118 .get_cpl
= vmx_get_cpl
,
12119 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
12120 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
12121 .decache_cr3
= vmx_decache_cr3
,
12122 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
12123 .set_cr0
= vmx_set_cr0
,
12124 .set_cr3
= vmx_set_cr3
,
12125 .set_cr4
= vmx_set_cr4
,
12126 .set_efer
= vmx_set_efer
,
12127 .get_idt
= vmx_get_idt
,
12128 .set_idt
= vmx_set_idt
,
12129 .get_gdt
= vmx_get_gdt
,
12130 .set_gdt
= vmx_set_gdt
,
12131 .get_dr6
= vmx_get_dr6
,
12132 .set_dr6
= vmx_set_dr6
,
12133 .set_dr7
= vmx_set_dr7
,
12134 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
12135 .cache_reg
= vmx_cache_reg
,
12136 .get_rflags
= vmx_get_rflags
,
12137 .set_rflags
= vmx_set_rflags
,
12139 .tlb_flush
= vmx_flush_tlb
,
12141 .run
= vmx_vcpu_run
,
12142 .handle_exit
= vmx_handle_exit
,
12143 .skip_emulated_instruction
= skip_emulated_instruction
,
12144 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
12145 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
12146 .patch_hypercall
= vmx_patch_hypercall
,
12147 .set_irq
= vmx_inject_irq
,
12148 .set_nmi
= vmx_inject_nmi
,
12149 .queue_exception
= vmx_queue_exception
,
12150 .cancel_injection
= vmx_cancel_injection
,
12151 .interrupt_allowed
= vmx_interrupt_allowed
,
12152 .nmi_allowed
= vmx_nmi_allowed
,
12153 .get_nmi_mask
= vmx_get_nmi_mask
,
12154 .set_nmi_mask
= vmx_set_nmi_mask
,
12155 .enable_nmi_window
= enable_nmi_window
,
12156 .enable_irq_window
= enable_irq_window
,
12157 .update_cr8_intercept
= update_cr8_intercept
,
12158 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
12159 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
12160 .get_enable_apicv
= vmx_get_enable_apicv
,
12161 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
12162 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
12163 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
12164 .hwapic_irr_update
= vmx_hwapic_irr_update
,
12165 .hwapic_isr_update
= vmx_hwapic_isr_update
,
12166 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
12167 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
12169 .set_tss_addr
= vmx_set_tss_addr
,
12170 .get_tdp_level
= get_ept_level
,
12171 .get_mt_mask
= vmx_get_mt_mask
,
12173 .get_exit_info
= vmx_get_exit_info
,
12175 .get_lpage_level
= vmx_get_lpage_level
,
12177 .cpuid_update
= vmx_cpuid_update
,
12179 .rdtscp_supported
= vmx_rdtscp_supported
,
12180 .invpcid_supported
= vmx_invpcid_supported
,
12182 .set_supported_cpuid
= vmx_set_supported_cpuid
,
12184 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
12186 .write_tsc_offset
= vmx_write_tsc_offset
,
12188 .set_tdp_cr3
= vmx_set_cr3
,
12190 .check_intercept
= vmx_check_intercept
,
12191 .handle_external_intr
= vmx_handle_external_intr
,
12192 .mpx_supported
= vmx_mpx_supported
,
12193 .xsaves_supported
= vmx_xsaves_supported
,
12195 .check_nested_events
= vmx_check_nested_events
,
12197 .sched_in
= vmx_sched_in
,
12199 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
12200 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
12201 .flush_log_dirty
= vmx_flush_log_dirty
,
12202 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
12203 .write_log_dirty
= vmx_write_pml_buffer
,
12205 .pre_block
= vmx_pre_block
,
12206 .post_block
= vmx_post_block
,
12208 .pmu_ops
= &intel_pmu_ops
,
12210 .update_pi_irte
= vmx_update_pi_irte
,
12212 #ifdef CONFIG_X86_64
12213 .set_hv_timer
= vmx_set_hv_timer
,
12214 .cancel_hv_timer
= vmx_cancel_hv_timer
,
12217 .setup_mce
= vmx_setup_mce
,
12219 .smi_allowed
= vmx_smi_allowed
,
12220 .pre_enter_smm
= vmx_pre_enter_smm
,
12221 .pre_leave_smm
= vmx_pre_leave_smm
,
12222 .enable_smi_window
= enable_smi_window
,
12225 static int __init
vmx_init(void)
12227 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
12228 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
12232 #ifdef CONFIG_KEXEC_CORE
12233 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
12234 crash_vmclear_local_loaded_vmcss
);
12240 static void __exit
vmx_exit(void)
12242 #ifdef CONFIG_KEXEC_CORE
12243 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
12250 module_init(vmx_init
)
12251 module_exit(vmx_exit
)