2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf
= 1;
53 module_param(bypass_guest_pf
, bool, S_IRUGO
);
55 static int __read_mostly enable_vpid
= 1;
56 module_param_named(vpid
, enable_vpid
, bool, 0444);
58 static int __read_mostly flexpriority_enabled
= 1;
59 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
61 static int __read_mostly enable_ept
= 1;
62 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
64 static int __read_mostly enable_unrestricted_guest
= 1;
65 module_param_named(unrestricted_guest
,
66 enable_unrestricted_guest
, bool, S_IRUGO
);
68 static int __read_mostly emulate_invalid_guest_state
= 0;
69 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
71 static int __read_mostly vmm_exclusive
= 1;
72 module_param(vmm_exclusive
, bool, S_IRUGO
);
74 static int __read_mostly yield_on_hlt
= 1;
75 module_param(yield_on_hlt
, bool, S_IRUGO
);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested
= 0;
83 module_param(nested
, bool, S_IRUGO
);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
116 module_param(ple_gap
, int, S_IRUGO
);
118 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
119 module_param(ple_window
, int, S_IRUGO
);
121 #define NR_AUTOLOAD_MSRS 1
122 #define VMCS02_POOL_SIZE 1
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
139 struct list_head loaded_vmcss_on_cpu_link
;
142 struct shared_msr_entry
{
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 typedef u64 natural_width
;
162 struct __packed vmcs12
{
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
169 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding
[7]; /* room for future expansion */
175 u64 vm_exit_msr_store_addr
;
176 u64 vm_exit_msr_load_addr
;
177 u64 vm_entry_msr_load_addr
;
179 u64 virtual_apic_page_addr
;
180 u64 apic_access_addr
;
182 u64 guest_physical_address
;
183 u64 vmcs_link_pointer
;
184 u64 guest_ia32_debugctl
;
187 u64 guest_ia32_perf_global_ctrl
;
194 u64 host_ia32_perf_global_ctrl
;
195 u64 padding64
[8]; /* room for future expansion */
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
202 natural_width cr0_guest_host_mask
;
203 natural_width cr4_guest_host_mask
;
204 natural_width cr0_read_shadow
;
205 natural_width cr4_read_shadow
;
206 natural_width cr3_target_value0
;
207 natural_width cr3_target_value1
;
208 natural_width cr3_target_value2
;
209 natural_width cr3_target_value3
;
210 natural_width exit_qualification
;
211 natural_width guest_linear_address
;
212 natural_width guest_cr0
;
213 natural_width guest_cr3
;
214 natural_width guest_cr4
;
215 natural_width guest_es_base
;
216 natural_width guest_cs_base
;
217 natural_width guest_ss_base
;
218 natural_width guest_ds_base
;
219 natural_width guest_fs_base
;
220 natural_width guest_gs_base
;
221 natural_width guest_ldtr_base
;
222 natural_width guest_tr_base
;
223 natural_width guest_gdtr_base
;
224 natural_width guest_idtr_base
;
225 natural_width guest_dr7
;
226 natural_width guest_rsp
;
227 natural_width guest_rip
;
228 natural_width guest_rflags
;
229 natural_width guest_pending_dbg_exceptions
;
230 natural_width guest_sysenter_esp
;
231 natural_width guest_sysenter_eip
;
232 natural_width host_cr0
;
233 natural_width host_cr3
;
234 natural_width host_cr4
;
235 natural_width host_fs_base
;
236 natural_width host_gs_base
;
237 natural_width host_tr_base
;
238 natural_width host_gdtr_base
;
239 natural_width host_idtr_base
;
240 natural_width host_ia32_sysenter_esp
;
241 natural_width host_ia32_sysenter_eip
;
242 natural_width host_rsp
;
243 natural_width host_rip
;
244 natural_width paddingl
[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control
;
246 u32 cpu_based_vm_exec_control
;
247 u32 exception_bitmap
;
248 u32 page_fault_error_code_mask
;
249 u32 page_fault_error_code_match
;
250 u32 cr3_target_count
;
251 u32 vm_exit_controls
;
252 u32 vm_exit_msr_store_count
;
253 u32 vm_exit_msr_load_count
;
254 u32 vm_entry_controls
;
255 u32 vm_entry_msr_load_count
;
256 u32 vm_entry_intr_info_field
;
257 u32 vm_entry_exception_error_code
;
258 u32 vm_entry_instruction_len
;
260 u32 secondary_vm_exec_control
;
261 u32 vm_instruction_error
;
263 u32 vm_exit_intr_info
;
264 u32 vm_exit_intr_error_code
;
265 u32 idt_vectoring_info_field
;
266 u32 idt_vectoring_error_code
;
267 u32 vm_exit_instruction_len
;
268 u32 vmx_instruction_info
;
275 u32 guest_ldtr_limit
;
277 u32 guest_gdtr_limit
;
278 u32 guest_idtr_limit
;
279 u32 guest_es_ar_bytes
;
280 u32 guest_cs_ar_bytes
;
281 u32 guest_ss_ar_bytes
;
282 u32 guest_ds_ar_bytes
;
283 u32 guest_fs_ar_bytes
;
284 u32 guest_gs_ar_bytes
;
285 u32 guest_ldtr_ar_bytes
;
286 u32 guest_tr_ar_bytes
;
287 u32 guest_interruptibility_info
;
288 u32 guest_activity_state
;
289 u32 guest_sysenter_cs
;
290 u32 host_ia32_sysenter_cs
;
291 u32 padding32
[8]; /* room for future expansion */
292 u16 virtual_processor_id
;
293 u16 guest_es_selector
;
294 u16 guest_cs_selector
;
295 u16 guest_ss_selector
;
296 u16 guest_ds_selector
;
297 u16 guest_fs_selector
;
298 u16 guest_gs_selector
;
299 u16 guest_ldtr_selector
;
300 u16 guest_tr_selector
;
301 u16 host_es_selector
;
302 u16 host_cs_selector
;
303 u16 host_ss_selector
;
304 u16 host_ds_selector
;
305 u16 host_fs_selector
;
306 u16 host_gs_selector
;
307 u16 host_tr_selector
;
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 #define VMCS12_REVISION 0x11e57ed0
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
322 #define VMCS12_SIZE 0x1000
324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct list_head list
;
328 struct loaded_vmcs vmcs02
;
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
336 /* Has the level1 guest done vmxon? */
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 /* The host-usable pointer to the above */
342 struct page
*current_vmcs12_page
;
343 struct vmcs12
*current_vmcs12
;
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool
;
348 u64 vmcs01_tsc_offset
;
349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending
;
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
355 struct page
*apic_access_page
;
359 struct kvm_vcpu vcpu
;
360 unsigned long host_rsp
;
363 bool nmi_known_unmasked
;
365 u32 idt_vectoring_info
;
367 struct shared_msr_entry
*guest_msrs
;
371 u64 msr_host_kernel_gs_base
;
372 u64 msr_guest_kernel_gs_base
;
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
379 struct loaded_vmcs vmcs01
;
380 struct loaded_vmcs
*loaded_vmcs
;
381 bool __launched
; /* temporary, used in vmx_vcpu_run */
382 struct msr_autoload
{
384 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
385 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
389 u16 fs_sel
, gs_sel
, ldt_sel
;
390 int gs_ldt_reload_needed
;
391 int fs_reload_needed
;
396 struct kvm_save_segment
{
401 } tr
, es
, ds
, fs
, gs
;
404 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg
[8];
408 bool emulation_required
;
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked
;
413 s64 vnmi_blocked_time
;
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested
;
422 enum segment_cache_field
{
431 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
433 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
441 static unsigned short vmcs_field_to_offset_table
[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
443 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
444 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
445 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
446 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
447 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
448 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
449 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
450 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
451 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
452 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
453 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
454 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
455 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
456 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
457 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
458 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
459 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
460 FIELD64(MSR_BITMAP
, msr_bitmap
),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
464 FIELD64(TSC_OFFSET
, tsc_offset
),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
466 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
467 FIELD64(EPT_POINTER
, ept_pointer
),
468 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
469 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
470 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
471 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
472 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
474 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
475 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
476 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
477 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
478 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
479 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
483 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
486 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
487 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
488 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
490 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
495 FIELD(TPR_THRESHOLD
, tpr_threshold
),
496 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
497 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
498 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
499 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
500 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
501 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
502 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
503 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
504 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
505 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
506 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
507 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
508 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
509 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
510 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
511 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
512 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
513 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
514 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
515 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
516 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
517 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
518 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
519 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
520 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
521 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
522 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
524 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
525 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
526 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
527 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
528 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
529 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
530 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
531 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
532 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
533 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
534 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
535 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
536 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
537 FIELD(GUEST_CR0
, guest_cr0
),
538 FIELD(GUEST_CR3
, guest_cr3
),
539 FIELD(GUEST_CR4
, guest_cr4
),
540 FIELD(GUEST_ES_BASE
, guest_es_base
),
541 FIELD(GUEST_CS_BASE
, guest_cs_base
),
542 FIELD(GUEST_SS_BASE
, guest_ss_base
),
543 FIELD(GUEST_DS_BASE
, guest_ds_base
),
544 FIELD(GUEST_FS_BASE
, guest_fs_base
),
545 FIELD(GUEST_GS_BASE
, guest_gs_base
),
546 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
547 FIELD(GUEST_TR_BASE
, guest_tr_base
),
548 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
549 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
550 FIELD(GUEST_DR7
, guest_dr7
),
551 FIELD(GUEST_RSP
, guest_rsp
),
552 FIELD(GUEST_RIP
, guest_rip
),
553 FIELD(GUEST_RFLAGS
, guest_rflags
),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
555 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
556 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
557 FIELD(HOST_CR0
, host_cr0
),
558 FIELD(HOST_CR3
, host_cr3
),
559 FIELD(HOST_CR4
, host_cr4
),
560 FIELD(HOST_FS_BASE
, host_fs_base
),
561 FIELD(HOST_GS_BASE
, host_gs_base
),
562 FIELD(HOST_TR_BASE
, host_tr_base
),
563 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
564 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
565 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
566 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
567 FIELD(HOST_RSP
, host_rsp
),
568 FIELD(HOST_RIP
, host_rip
),
570 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
572 static inline short vmcs_field_to_offset(unsigned long field
)
574 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
576 return vmcs_field_to_offset_table
[field
];
579 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
581 return to_vmx(vcpu
)->nested
.current_vmcs12
;
584 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
586 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
587 if (is_error_page(page
)) {
588 kvm_release_page_clean(page
);
594 static void nested_release_page(struct page
*page
)
596 kvm_release_page_dirty(page
);
599 static void nested_release_page_clean(struct page
*page
)
601 kvm_release_page_clean(page
);
604 static u64
construct_eptp(unsigned long root_hpa
);
605 static void kvm_cpu_vmxon(u64 addr
);
606 static void kvm_cpu_vmxoff(void);
607 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
608 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
610 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
611 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
617 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
619 static unsigned long *vmx_io_bitmap_a
;
620 static unsigned long *vmx_io_bitmap_b
;
621 static unsigned long *vmx_msr_bitmap_legacy
;
622 static unsigned long *vmx_msr_bitmap_longmode
;
624 static bool cpu_has_load_ia32_efer
;
626 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
627 static DEFINE_SPINLOCK(vmx_vpid_lock
);
629 static struct vmcs_config
{
633 u32 pin_based_exec_ctrl
;
634 u32 cpu_based_exec_ctrl
;
635 u32 cpu_based_2nd_exec_ctrl
;
640 static struct vmx_capability
{
645 #define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 static struct kvm_vmx_segment_field
{
658 } kvm_vmx_segment_fields
[] = {
659 VMX_SEGMENT_FIELD(CS
),
660 VMX_SEGMENT_FIELD(DS
),
661 VMX_SEGMENT_FIELD(ES
),
662 VMX_SEGMENT_FIELD(FS
),
663 VMX_SEGMENT_FIELD(GS
),
664 VMX_SEGMENT_FIELD(SS
),
665 VMX_SEGMENT_FIELD(TR
),
666 VMX_SEGMENT_FIELD(LDTR
),
669 static u64 host_efer
;
671 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
675 * away by decrementing the array size.
677 static const u32 vmx_msr_index
[] = {
679 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
681 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
685 static inline bool is_page_fault(u32 intr_info
)
687 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
688 INTR_INFO_VALID_MASK
)) ==
689 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
692 static inline bool is_no_device(u32 intr_info
)
694 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
695 INTR_INFO_VALID_MASK
)) ==
696 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
699 static inline bool is_invalid_opcode(u32 intr_info
)
701 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
702 INTR_INFO_VALID_MASK
)) ==
703 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
706 static inline bool is_external_interrupt(u32 intr_info
)
708 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
709 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
712 static inline bool is_machine_check(u32 intr_info
)
714 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
715 INTR_INFO_VALID_MASK
)) ==
716 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
719 static inline bool cpu_has_vmx_msr_bitmap(void)
721 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
724 static inline bool cpu_has_vmx_tpr_shadow(void)
726 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
729 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
734 static inline bool cpu_has_secondary_exec_ctrls(void)
736 return vmcs_config
.cpu_based_exec_ctrl
&
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
742 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
746 static inline bool cpu_has_vmx_flexpriority(void)
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
752 static inline bool cpu_has_vmx_ept_execute_only(void)
754 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
759 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
762 static inline bool cpu_has_vmx_eptp_writeback(void)
764 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
767 static inline bool cpu_has_vmx_ept_2m_page(void)
769 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
772 static inline bool cpu_has_vmx_ept_1g_page(void)
774 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
777 static inline bool cpu_has_vmx_ept_4levels(void)
779 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
782 static inline bool cpu_has_vmx_invept_individual_addr(void)
784 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
787 static inline bool cpu_has_vmx_invept_context(void)
789 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
792 static inline bool cpu_has_vmx_invept_global(void)
794 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
797 static inline bool cpu_has_vmx_invvpid_single(void)
799 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
802 static inline bool cpu_has_vmx_invvpid_global(void)
804 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
807 static inline bool cpu_has_vmx_ept(void)
809 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
810 SECONDARY_EXEC_ENABLE_EPT
;
813 static inline bool cpu_has_vmx_unrestricted_guest(void)
815 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
816 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
819 static inline bool cpu_has_vmx_ple(void)
821 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
825 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
827 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
830 static inline bool cpu_has_vmx_vpid(void)
832 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
833 SECONDARY_EXEC_ENABLE_VPID
;
836 static inline bool cpu_has_vmx_rdtscp(void)
838 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
839 SECONDARY_EXEC_RDTSCP
;
842 static inline bool cpu_has_virtual_nmis(void)
844 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
847 static inline bool cpu_has_vmx_wbinvd_exit(void)
849 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
850 SECONDARY_EXEC_WBINVD_EXITING
;
853 static inline bool report_flexpriority(void)
855 return flexpriority_enabled
;
858 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
860 return vmcs12
->cpu_based_vm_exec_control
& bit
;
863 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
865 return (vmcs12
->cpu_based_vm_exec_control
&
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
867 (vmcs12
->secondary_vm_exec_control
& bit
);
870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
,
871 struct kvm_vcpu
*vcpu
)
873 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
876 static inline bool is_exception(u32 intr_info
)
878 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
879 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
882 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
);
883 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
884 struct vmcs12
*vmcs12
,
885 u32 reason
, unsigned long qualification
);
887 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
891 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
892 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
897 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
903 } operand
= { vpid
, 0, gva
};
905 asm volatile (__ex(ASM_VMX_INVVPID
)
906 /* CF==1 or ZF==1 --> rc = -1 */
908 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
911 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
915 } operand
= {eptp
, gpa
};
917 asm volatile (__ex(ASM_VMX_INVEPT
)
918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
923 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
927 i
= __find_msr_index(vmx
, msr
);
929 return &vmx
->guest_msrs
[i
];
933 static void vmcs_clear(struct vmcs
*vmcs
)
935 u64 phys_addr
= __pa(vmcs
);
938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
939 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
942 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
946 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
948 vmcs_clear(loaded_vmcs
->vmcs
);
949 loaded_vmcs
->cpu
= -1;
950 loaded_vmcs
->launched
= 0;
953 static void vmcs_load(struct vmcs
*vmcs
)
955 u64 phys_addr
= __pa(vmcs
);
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
959 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
962 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
966 static void __loaded_vmcs_clear(void *arg
)
968 struct loaded_vmcs
*loaded_vmcs
= arg
;
969 int cpu
= raw_smp_processor_id();
971 if (loaded_vmcs
->cpu
!= cpu
)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
974 per_cpu(current_vmcs
, cpu
) = NULL
;
975 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
976 loaded_vmcs_init(loaded_vmcs
);
979 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
981 if (loaded_vmcs
->cpu
!= -1)
982 smp_call_function_single(
983 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
995 static inline void vpid_sync_vcpu_global(void)
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1001 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1003 if (cpu_has_vmx_invvpid_single())
1004 vpid_sync_vcpu_single(vmx
);
1006 vpid_sync_vcpu_global();
1009 static inline void ept_sync_global(void)
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1015 static inline void ept_sync_context(u64 eptp
)
1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1025 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
1032 ept_sync_context(eptp
);
1036 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1038 unsigned long value
;
1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1041 : "=a"(value
) : "d"(field
) : "cc");
1045 static __always_inline u16
vmcs_read16(unsigned long field
)
1047 return vmcs_readl(field
);
1050 static __always_inline u32
vmcs_read32(unsigned long field
)
1052 return vmcs_readl(field
);
1055 static __always_inline u64
vmcs_read64(unsigned long field
)
1057 #ifdef CONFIG_X86_64
1058 return vmcs_readl(field
);
1060 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1064 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1066 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1067 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1071 static void vmcs_writel(unsigned long field
, unsigned long value
)
1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1076 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1077 if (unlikely(error
))
1078 vmwrite_error(field
, value
);
1081 static void vmcs_write16(unsigned long field
, u16 value
)
1083 vmcs_writel(field
, value
);
1086 static void vmcs_write32(unsigned long field
, u32 value
)
1088 vmcs_writel(field
, value
);
1091 static void vmcs_write64(unsigned long field
, u64 value
)
1093 vmcs_writel(field
, value
);
1094 #ifndef CONFIG_X86_64
1096 vmcs_writel(field
+1, value
>> 32);
1100 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1102 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1105 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1107 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1110 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1112 vmx
->segment_cache
.bitmask
= 0;
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1119 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1121 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1122 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1123 vmx
->segment_cache
.bitmask
= 0;
1125 ret
= vmx
->segment_cache
.bitmask
& mask
;
1126 vmx
->segment_cache
.bitmask
|= mask
;
1130 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1132 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1134 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1135 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1139 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1141 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1143 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1144 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1148 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1150 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1152 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1153 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1157 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1159 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1161 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1162 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1166 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1170 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1171 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1172 if ((vcpu
->guest_debug
&
1173 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1174 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1175 eb
|= 1u << BP_VECTOR
;
1176 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1179 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1180 if (vcpu
->fpu_active
)
1181 eb
&= ~(1u << NM_VECTOR
);
1183 /* When we are running a nested L2 guest and L1 specified for it a
1184 * certain exception bitmap, we must trap the same exceptions and pass
1185 * them to L1. When running L2, we will only handle the exceptions
1186 * specified above if L1 did not want them.
1188 if (is_guest_mode(vcpu
))
1189 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1191 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1194 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1197 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1199 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1200 vmcs_clear_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1201 vmcs_clear_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1205 for (i
= 0; i
< m
->nr
; ++i
)
1206 if (m
->guest
[i
].index
== msr
)
1212 m
->guest
[i
] = m
->guest
[m
->nr
];
1213 m
->host
[i
] = m
->host
[m
->nr
];
1214 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1215 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1218 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1219 u64 guest_val
, u64 host_val
)
1222 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1224 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
1225 vmcs_write64(GUEST_IA32_EFER
, guest_val
);
1226 vmcs_write64(HOST_IA32_EFER
, host_val
);
1227 vmcs_set_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
1228 vmcs_set_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
1232 for (i
= 0; i
< m
->nr
; ++i
)
1233 if (m
->guest
[i
].index
== msr
)
1238 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1239 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1242 m
->guest
[i
].index
= msr
;
1243 m
->guest
[i
].value
= guest_val
;
1244 m
->host
[i
].index
= msr
;
1245 m
->host
[i
].value
= host_val
;
1248 static void reload_tss(void)
1251 * VT restores TR but not its size. Useless.
1253 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1254 struct desc_struct
*descs
;
1256 descs
= (void *)gdt
->address
;
1257 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1261 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1266 guest_efer
= vmx
->vcpu
.arch
.efer
;
1269 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1272 ignore_bits
= EFER_NX
| EFER_SCE
;
1273 #ifdef CONFIG_X86_64
1274 ignore_bits
|= EFER_LMA
| EFER_LME
;
1275 /* SCE is meaningful only in long mode on Intel */
1276 if (guest_efer
& EFER_LMA
)
1277 ignore_bits
&= ~(u64
)EFER_SCE
;
1279 guest_efer
&= ~ignore_bits
;
1280 guest_efer
|= host_efer
& ignore_bits
;
1281 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1282 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1284 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1285 /* On ept, can't emulate nx, and must switch nx atomically */
1286 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1287 guest_efer
= vmx
->vcpu
.arch
.efer
;
1288 if (!(guest_efer
& EFER_LMA
))
1289 guest_efer
&= ~EFER_LME
;
1290 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1297 static unsigned long segment_base(u16 selector
)
1299 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1300 struct desc_struct
*d
;
1301 unsigned long table_base
;
1304 if (!(selector
& ~3))
1307 table_base
= gdt
->address
;
1309 if (selector
& 4) { /* from ldt */
1310 u16 ldt_selector
= kvm_read_ldt();
1312 if (!(ldt_selector
& ~3))
1315 table_base
= segment_base(ldt_selector
);
1317 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1318 v
= get_desc_base(d
);
1319 #ifdef CONFIG_X86_64
1320 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1321 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1326 static inline unsigned long kvm_read_tr_base(void)
1329 asm("str %0" : "=g"(tr
));
1330 return segment_base(tr
);
1333 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1335 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1338 if (vmx
->host_state
.loaded
)
1341 vmx
->host_state
.loaded
= 1;
1343 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1344 * allow segment selectors with cpl > 0 or ti == 1.
1346 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1347 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1348 savesegment(fs
, vmx
->host_state
.fs_sel
);
1349 if (!(vmx
->host_state
.fs_sel
& 7)) {
1350 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1351 vmx
->host_state
.fs_reload_needed
= 0;
1353 vmcs_write16(HOST_FS_SELECTOR
, 0);
1354 vmx
->host_state
.fs_reload_needed
= 1;
1356 savesegment(gs
, vmx
->host_state
.gs_sel
);
1357 if (!(vmx
->host_state
.gs_sel
& 7))
1358 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1360 vmcs_write16(HOST_GS_SELECTOR
, 0);
1361 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1364 #ifdef CONFIG_X86_64
1365 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1366 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1368 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1369 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1372 #ifdef CONFIG_X86_64
1373 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1374 if (is_long_mode(&vmx
->vcpu
))
1375 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1377 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1378 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1379 vmx
->guest_msrs
[i
].data
,
1380 vmx
->guest_msrs
[i
].mask
);
1383 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1385 if (!vmx
->host_state
.loaded
)
1388 ++vmx
->vcpu
.stat
.host_state_reload
;
1389 vmx
->host_state
.loaded
= 0;
1390 #ifdef CONFIG_X86_64
1391 if (is_long_mode(&vmx
->vcpu
))
1392 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1394 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1395 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1396 #ifdef CONFIG_X86_64
1397 load_gs_index(vmx
->host_state
.gs_sel
);
1399 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1402 if (vmx
->host_state
.fs_reload_needed
)
1403 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1405 #ifdef CONFIG_X86_64
1406 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1408 if (current_thread_info()->status
& TS_USEDFPU
)
1410 load_gdt(&__get_cpu_var(host_gdt
));
1413 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1416 __vmx_load_host_state(vmx
);
1421 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422 * vcpu mutex is already taken.
1424 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1426 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1427 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1430 kvm_cpu_vmxon(phys_addr
);
1431 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1432 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1434 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1435 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1436 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1439 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1440 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1441 unsigned long sysenter_esp
;
1443 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1444 local_irq_disable();
1445 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1446 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1450 * Linux uses per-cpu TSS and GDT, so set these when switching
1453 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1454 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1456 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1457 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1458 vmx
->loaded_vmcs
->cpu
= cpu
;
1462 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1464 __vmx_load_host_state(to_vmx(vcpu
));
1465 if (!vmm_exclusive
) {
1466 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1472 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1476 if (vcpu
->fpu_active
)
1478 vcpu
->fpu_active
= 1;
1479 cr0
= vmcs_readl(GUEST_CR0
);
1480 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1481 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1482 vmcs_writel(GUEST_CR0
, cr0
);
1483 update_exception_bitmap(vcpu
);
1484 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1485 if (is_guest_mode(vcpu
))
1486 vcpu
->arch
.cr0_guest_owned_bits
&=
1487 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1488 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1491 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1494 * Return the cr0 value that a nested guest would read. This is a combination
1495 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496 * its hypervisor (cr0_read_shadow).
1498 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1500 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1501 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1503 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1505 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1506 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1509 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1511 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512 * set this *before* calling this function.
1514 vmx_decache_cr0_guest_bits(vcpu
);
1515 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1516 update_exception_bitmap(vcpu
);
1517 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1518 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1519 if (is_guest_mode(vcpu
)) {
1521 * L1's specified read shadow might not contain the TS bit,
1522 * so now that we turned on shadowing of this bit, we need to
1523 * set this bit of the shadow. Like in nested_vmx_run we need
1524 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525 * up-to-date here because we just decached cr0.TS (and we'll
1526 * only update vmcs12->guest_cr0 on nested exit).
1528 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1529 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1530 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1531 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1533 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1536 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1538 unsigned long rflags
, save_rflags
;
1540 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1541 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1542 rflags
= vmcs_readl(GUEST_RFLAGS
);
1543 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1544 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1545 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1546 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1548 to_vmx(vcpu
)->rflags
= rflags
;
1550 return to_vmx(vcpu
)->rflags
;
1553 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1555 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1556 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1557 to_vmx(vcpu
)->rflags
= rflags
;
1558 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1559 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1560 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1562 vmcs_writel(GUEST_RFLAGS
, rflags
);
1565 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1567 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1570 if (interruptibility
& GUEST_INTR_STATE_STI
)
1571 ret
|= KVM_X86_SHADOW_INT_STI
;
1572 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1573 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1578 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1580 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1581 u32 interruptibility
= interruptibility_old
;
1583 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1585 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1586 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1587 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1588 interruptibility
|= GUEST_INTR_STATE_STI
;
1590 if ((interruptibility
!= interruptibility_old
))
1591 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1594 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1598 rip
= kvm_rip_read(vcpu
);
1599 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1600 kvm_rip_write(vcpu
, rip
);
1602 /* skipping an emulated instruction also counts */
1603 vmx_set_interrupt_shadow(vcpu
, 0);
1606 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1608 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1609 * explicitly skip the instruction because if the HLT state is set, then
1610 * the instruction is already executing and RIP has already been
1612 if (!yield_on_hlt
&&
1613 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1614 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1618 * KVM wants to inject page-faults which it got to the guest. This function
1619 * checks whether in a nested guest, we need to inject them to L1 or L2.
1620 * This function assumes it is called with the exit reason in vmcs02 being
1621 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1624 static int nested_pf_handled(struct kvm_vcpu
*vcpu
)
1626 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1628 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629 if (!(vmcs12
->exception_bitmap
& PF_VECTOR
))
1632 nested_vmx_vmexit(vcpu
);
1636 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1637 bool has_error_code
, u32 error_code
,
1640 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1641 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1643 if (nr
== PF_VECTOR
&& is_guest_mode(vcpu
) &&
1644 nested_pf_handled(vcpu
))
1647 if (has_error_code
) {
1648 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1649 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1652 if (vmx
->rmode
.vm86_active
) {
1654 if (kvm_exception_is_soft(nr
))
1655 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1656 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1657 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1661 if (kvm_exception_is_soft(nr
)) {
1662 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1663 vmx
->vcpu
.arch
.event_exit_inst_len
);
1664 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1666 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1668 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1669 vmx_clear_hlt(vcpu
);
1672 static bool vmx_rdtscp_supported(void)
1674 return cpu_has_vmx_rdtscp();
1678 * Swap MSR entry in host/guest MSR entry array.
1680 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1682 struct shared_msr_entry tmp
;
1684 tmp
= vmx
->guest_msrs
[to
];
1685 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1686 vmx
->guest_msrs
[from
] = tmp
;
1690 * Set up the vmcs to automatically save and restore system
1691 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1692 * mode, as fiddling with msrs is very expensive.
1694 static void setup_msrs(struct vcpu_vmx
*vmx
)
1696 int save_nmsrs
, index
;
1697 unsigned long *msr_bitmap
;
1699 vmx_load_host_state(vmx
);
1701 #ifdef CONFIG_X86_64
1702 if (is_long_mode(&vmx
->vcpu
)) {
1703 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1705 move_msr_up(vmx
, index
, save_nmsrs
++);
1706 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1708 move_msr_up(vmx
, index
, save_nmsrs
++);
1709 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1711 move_msr_up(vmx
, index
, save_nmsrs
++);
1712 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1713 if (index
>= 0 && vmx
->rdtscp_enabled
)
1714 move_msr_up(vmx
, index
, save_nmsrs
++);
1716 * MSR_STAR is only needed on long mode guests, and only
1717 * if efer.sce is enabled.
1719 index
= __find_msr_index(vmx
, MSR_STAR
);
1720 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1721 move_msr_up(vmx
, index
, save_nmsrs
++);
1724 index
= __find_msr_index(vmx
, MSR_EFER
);
1725 if (index
>= 0 && update_transition_efer(vmx
, index
))
1726 move_msr_up(vmx
, index
, save_nmsrs
++);
1728 vmx
->save_nmsrs
= save_nmsrs
;
1730 if (cpu_has_vmx_msr_bitmap()) {
1731 if (is_long_mode(&vmx
->vcpu
))
1732 msr_bitmap
= vmx_msr_bitmap_longmode
;
1734 msr_bitmap
= vmx_msr_bitmap_legacy
;
1736 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1741 * reads and returns guest's timestamp counter "register"
1742 * guest_tsc = host_tsc + tsc_offset -- 21.3
1744 static u64
guest_read_tsc(void)
1746 u64 host_tsc
, tsc_offset
;
1749 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1750 return host_tsc
+ tsc_offset
;
1754 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1755 * ioctl. In this case the call-back should update internal vmx state to make
1756 * the changes effective.
1758 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
)
1760 /* Nothing to do here */
1764 * writes 'offset' into guest's timestamp counter offset register
1766 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1768 vmcs_write64(TSC_OFFSET
, offset
);
1769 if (is_guest_mode(vcpu
))
1771 * We're here if L1 chose not to trap the TSC MSR. Since
1772 * prepare_vmcs12() does not copy tsc_offset, we need to also
1773 * set the vmcs12 field here.
1775 get_vmcs12(vcpu
)->tsc_offset
= offset
-
1776 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
;
1779 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1781 u64 offset
= vmcs_read64(TSC_OFFSET
);
1782 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1783 if (is_guest_mode(vcpu
)) {
1784 /* Even when running L2, the adjustment needs to apply to L1 */
1785 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
1789 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1791 return target_tsc
- native_read_tsc();
1794 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1796 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1797 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1801 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1802 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1803 * all guests if the "nested" module option is off, and can also be disabled
1804 * for a single guest by disabling its VMX cpuid bit.
1806 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1808 return nested
&& guest_cpuid_has_vmx(vcpu
);
1812 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1813 * returned for the various VMX controls MSRs when nested VMX is enabled.
1814 * The same values should also be used to verify that vmcs12 control fields are
1815 * valid during nested entry from L1 to L2.
1816 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1817 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1818 * bit in the high half is on if the corresponding bit in the control field
1819 * may be on. See also vmx_control_verify().
1820 * TODO: allow these variables to be modified (downgraded) by module options
1823 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1824 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1825 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1826 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1827 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1828 static __init
void nested_vmx_setup_ctls_msrs(void)
1831 * Note that as a general rule, the high half of the MSRs (bits in
1832 * the control fields which may be 1) should be initialized by the
1833 * intersection of the underlying hardware's MSR (i.e., features which
1834 * can be supported) and the list of features we want to expose -
1835 * because they are known to be properly supported in our code.
1836 * Also, usually, the low half of the MSRs (bits which must be 1) can
1837 * be set to 0, meaning that L1 may turn off any of these bits. The
1838 * reason is that if one of these bits is necessary, it will appear
1839 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1840 * fields of vmcs01 and vmcs02, will turn these bits off - and
1841 * nested_vmx_exit_handled() will not pass related exits to L1.
1842 * These rules have exceptions below.
1845 /* pin-based controls */
1847 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1848 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1850 nested_vmx_pinbased_ctls_low
= 0x16 ;
1851 nested_vmx_pinbased_ctls_high
= 0x16 |
1852 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1853 PIN_BASED_VIRTUAL_NMIS
;
1856 nested_vmx_exit_ctls_low
= 0;
1857 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1858 #ifdef CONFIG_X86_64
1859 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1861 nested_vmx_exit_ctls_high
= 0;
1864 /* entry controls */
1865 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1866 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1867 nested_vmx_entry_ctls_low
= 0;
1868 nested_vmx_entry_ctls_high
&=
1869 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1871 /* cpu-based controls */
1872 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1873 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1874 nested_vmx_procbased_ctls_low
= 0;
1875 nested_vmx_procbased_ctls_high
&=
1876 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1877 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1878 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1879 CPU_BASED_CR3_STORE_EXITING
|
1880 #ifdef CONFIG_X86_64
1881 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1883 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1884 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1885 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1887 * We can allow some features even when not supported by the
1888 * hardware. For example, L1 can specify an MSR bitmap - and we
1889 * can use it to avoid exits to L1 - even when L0 runs L2
1890 * without MSR bitmaps.
1892 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
1894 /* secondary cpu-based controls */
1895 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1896 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
1897 nested_vmx_secondary_ctls_low
= 0;
1898 nested_vmx_secondary_ctls_high
&=
1899 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1902 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
1905 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1907 return ((control
& high
) | low
) == control
;
1910 static inline u64
vmx_control_msr(u32 low
, u32 high
)
1912 return low
| ((u64
)high
<< 32);
1916 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1917 * also let it use VMX-specific MSRs.
1918 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1919 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1920 * like all other MSRs).
1922 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1924 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
1925 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
1927 * According to the spec, processors which do not support VMX
1928 * should throw a #GP(0) when VMX capability MSRs are read.
1930 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
1934 switch (msr_index
) {
1935 case MSR_IA32_FEATURE_CONTROL
:
1938 case MSR_IA32_VMX_BASIC
:
1940 * This MSR reports some information about VMX support. We
1941 * should return information about the VMX we emulate for the
1942 * guest, and the VMCS structure we give it - not about the
1943 * VMX support of the underlying hardware.
1945 *pdata
= VMCS12_REVISION
|
1946 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
1947 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
1949 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
1950 case MSR_IA32_VMX_PINBASED_CTLS
:
1951 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
1952 nested_vmx_pinbased_ctls_high
);
1954 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
1955 case MSR_IA32_VMX_PROCBASED_CTLS
:
1956 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
1957 nested_vmx_procbased_ctls_high
);
1959 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
1960 case MSR_IA32_VMX_EXIT_CTLS
:
1961 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
1962 nested_vmx_exit_ctls_high
);
1964 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
1965 case MSR_IA32_VMX_ENTRY_CTLS
:
1966 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
1967 nested_vmx_entry_ctls_high
);
1969 case MSR_IA32_VMX_MISC
:
1973 * These MSRs specify bits which the guest must keep fixed (on or off)
1974 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1975 * We picked the standard core2 setting.
1977 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1978 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1979 case MSR_IA32_VMX_CR0_FIXED0
:
1980 *pdata
= VMXON_CR0_ALWAYSON
;
1982 case MSR_IA32_VMX_CR0_FIXED1
:
1985 case MSR_IA32_VMX_CR4_FIXED0
:
1986 *pdata
= VMXON_CR4_ALWAYSON
;
1988 case MSR_IA32_VMX_CR4_FIXED1
:
1991 case MSR_IA32_VMX_VMCS_ENUM
:
1994 case MSR_IA32_VMX_PROCBASED_CTLS2
:
1995 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
1996 nested_vmx_secondary_ctls_high
);
1998 case MSR_IA32_VMX_EPT_VPID_CAP
:
1999 /* Currently, no nested ept or nested vpid */
2009 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2011 if (!nested_vmx_allowed(vcpu
))
2014 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
2015 /* TODO: the right thing. */
2018 * No need to treat VMX capability MSRs specially: If we don't handle
2019 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2025 * Reads an msr value (of 'msr_index') into 'pdata'.
2026 * Returns 0 on success, non-0 otherwise.
2027 * Assumes vcpu_load() was already called.
2029 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2032 struct shared_msr_entry
*msr
;
2035 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2039 switch (msr_index
) {
2040 #ifdef CONFIG_X86_64
2042 data
= vmcs_readl(GUEST_FS_BASE
);
2045 data
= vmcs_readl(GUEST_GS_BASE
);
2047 case MSR_KERNEL_GS_BASE
:
2048 vmx_load_host_state(to_vmx(vcpu
));
2049 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2053 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2055 data
= guest_read_tsc();
2057 case MSR_IA32_SYSENTER_CS
:
2058 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2060 case MSR_IA32_SYSENTER_EIP
:
2061 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2063 case MSR_IA32_SYSENTER_ESP
:
2064 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2067 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2069 /* Otherwise falls through */
2071 vmx_load_host_state(to_vmx(vcpu
));
2072 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
2074 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2076 vmx_load_host_state(to_vmx(vcpu
));
2080 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2088 * Writes msr value into into the appropriate "register".
2089 * Returns 0 on success, non-0 otherwise.
2090 * Assumes vcpu_load() was already called.
2092 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
2094 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2095 struct shared_msr_entry
*msr
;
2098 switch (msr_index
) {
2100 vmx_load_host_state(vmx
);
2101 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2103 #ifdef CONFIG_X86_64
2105 vmx_segment_cache_clear(vmx
);
2106 vmcs_writel(GUEST_FS_BASE
, data
);
2109 vmx_segment_cache_clear(vmx
);
2110 vmcs_writel(GUEST_GS_BASE
, data
);
2112 case MSR_KERNEL_GS_BASE
:
2113 vmx_load_host_state(vmx
);
2114 vmx
->msr_guest_kernel_gs_base
= data
;
2117 case MSR_IA32_SYSENTER_CS
:
2118 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2120 case MSR_IA32_SYSENTER_EIP
:
2121 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2123 case MSR_IA32_SYSENTER_ESP
:
2124 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2127 kvm_write_tsc(vcpu
, data
);
2129 case MSR_IA32_CR_PAT
:
2130 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2131 vmcs_write64(GUEST_IA32_PAT
, data
);
2132 vcpu
->arch
.pat
= data
;
2135 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2138 if (!vmx
->rdtscp_enabled
)
2140 /* Check reserved bit, higher 32 bits should be zero */
2141 if ((data
>> 32) != 0)
2143 /* Otherwise falls through */
2145 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
2147 msr
= find_msr_entry(vmx
, msr_index
);
2149 vmx_load_host_state(vmx
);
2153 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
2159 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2161 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2164 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2167 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2169 case VCPU_EXREG_PDPTR
:
2171 ept_save_pdptrs(vcpu
);
2178 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
2180 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
2181 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
2183 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2185 update_exception_bitmap(vcpu
);
2188 static __init
int cpu_has_kvm_support(void)
2190 return cpu_has_vmx();
2193 static __init
int vmx_disabled_by_bios(void)
2197 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2198 if (msr
& FEATURE_CONTROL_LOCKED
) {
2199 /* launched w/ TXT and VMX disabled */
2200 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2203 /* launched w/o TXT and VMX only enabled w/ TXT */
2204 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2205 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2206 && !tboot_enabled()) {
2207 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2208 "activate TXT before enabling KVM\n");
2211 /* launched w/o TXT and VMX disabled */
2212 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2213 && !tboot_enabled())
2220 static void kvm_cpu_vmxon(u64 addr
)
2222 asm volatile (ASM_VMX_VMXON_RAX
2223 : : "a"(&addr
), "m"(addr
)
2227 static int hardware_enable(void *garbage
)
2229 int cpu
= raw_smp_processor_id();
2230 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2233 if (read_cr4() & X86_CR4_VMXE
)
2236 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2237 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2239 test_bits
= FEATURE_CONTROL_LOCKED
;
2240 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2241 if (tboot_enabled())
2242 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2244 if ((old
& test_bits
) != test_bits
) {
2245 /* enable and lock */
2246 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2248 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2250 if (vmm_exclusive
) {
2251 kvm_cpu_vmxon(phys_addr
);
2255 store_gdt(&__get_cpu_var(host_gdt
));
2260 static void vmclear_local_loaded_vmcss(void)
2262 int cpu
= raw_smp_processor_id();
2263 struct loaded_vmcs
*v
, *n
;
2265 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2266 loaded_vmcss_on_cpu_link
)
2267 __loaded_vmcs_clear(v
);
2271 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2274 static void kvm_cpu_vmxoff(void)
2276 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2279 static void hardware_disable(void *garbage
)
2281 if (vmm_exclusive
) {
2282 vmclear_local_loaded_vmcss();
2285 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2288 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2289 u32 msr
, u32
*result
)
2291 u32 vmx_msr_low
, vmx_msr_high
;
2292 u32 ctl
= ctl_min
| ctl_opt
;
2294 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2296 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2297 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2299 /* Ensure minimum (required) set of control bits are supported. */
2307 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2309 u32 vmx_msr_low
, vmx_msr_high
;
2311 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2312 return vmx_msr_high
& ctl
;
2315 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2317 u32 vmx_msr_low
, vmx_msr_high
;
2318 u32 min
, opt
, min2
, opt2
;
2319 u32 _pin_based_exec_control
= 0;
2320 u32 _cpu_based_exec_control
= 0;
2321 u32 _cpu_based_2nd_exec_control
= 0;
2322 u32 _vmexit_control
= 0;
2323 u32 _vmentry_control
= 0;
2325 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2326 opt
= PIN_BASED_VIRTUAL_NMIS
;
2327 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2328 &_pin_based_exec_control
) < 0)
2332 #ifdef CONFIG_X86_64
2333 CPU_BASED_CR8_LOAD_EXITING
|
2334 CPU_BASED_CR8_STORE_EXITING
|
2336 CPU_BASED_CR3_LOAD_EXITING
|
2337 CPU_BASED_CR3_STORE_EXITING
|
2338 CPU_BASED_USE_IO_BITMAPS
|
2339 CPU_BASED_MOV_DR_EXITING
|
2340 CPU_BASED_USE_TSC_OFFSETING
|
2341 CPU_BASED_MWAIT_EXITING
|
2342 CPU_BASED_MONITOR_EXITING
|
2343 CPU_BASED_INVLPG_EXITING
;
2346 min
|= CPU_BASED_HLT_EXITING
;
2348 opt
= CPU_BASED_TPR_SHADOW
|
2349 CPU_BASED_USE_MSR_BITMAPS
|
2350 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2351 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2352 &_cpu_based_exec_control
) < 0)
2354 #ifdef CONFIG_X86_64
2355 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2356 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2357 ~CPU_BASED_CR8_STORE_EXITING
;
2359 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2361 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2362 SECONDARY_EXEC_WBINVD_EXITING
|
2363 SECONDARY_EXEC_ENABLE_VPID
|
2364 SECONDARY_EXEC_ENABLE_EPT
|
2365 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2366 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2367 SECONDARY_EXEC_RDTSCP
;
2368 if (adjust_vmx_controls(min2
, opt2
,
2369 MSR_IA32_VMX_PROCBASED_CTLS2
,
2370 &_cpu_based_2nd_exec_control
) < 0)
2373 #ifndef CONFIG_X86_64
2374 if (!(_cpu_based_2nd_exec_control
&
2375 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2376 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2378 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2379 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2381 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2382 CPU_BASED_CR3_STORE_EXITING
|
2383 CPU_BASED_INVLPG_EXITING
);
2384 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2385 vmx_capability
.ept
, vmx_capability
.vpid
);
2389 #ifdef CONFIG_X86_64
2390 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2392 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
2393 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2394 &_vmexit_control
) < 0)
2398 opt
= VM_ENTRY_LOAD_IA32_PAT
;
2399 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2400 &_vmentry_control
) < 0)
2403 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2405 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2406 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2409 #ifdef CONFIG_X86_64
2410 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2411 if (vmx_msr_high
& (1u<<16))
2415 /* Require Write-Back (WB) memory type for VMCS accesses. */
2416 if (((vmx_msr_high
>> 18) & 15) != 6)
2419 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2420 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2421 vmcs_conf
->revision_id
= vmx_msr_low
;
2423 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2424 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2425 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2426 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2427 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2429 cpu_has_load_ia32_efer
=
2430 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2431 VM_ENTRY_LOAD_IA32_EFER
)
2432 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2433 VM_EXIT_LOAD_IA32_EFER
);
2438 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2440 int node
= cpu_to_node(cpu
);
2444 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2447 vmcs
= page_address(pages
);
2448 memset(vmcs
, 0, vmcs_config
.size
);
2449 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2453 static struct vmcs
*alloc_vmcs(void)
2455 return alloc_vmcs_cpu(raw_smp_processor_id());
2458 static void free_vmcs(struct vmcs
*vmcs
)
2460 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2464 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2466 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2468 if (!loaded_vmcs
->vmcs
)
2470 loaded_vmcs_clear(loaded_vmcs
);
2471 free_vmcs(loaded_vmcs
->vmcs
);
2472 loaded_vmcs
->vmcs
= NULL
;
2475 static void free_kvm_area(void)
2479 for_each_possible_cpu(cpu
) {
2480 free_vmcs(per_cpu(vmxarea
, cpu
));
2481 per_cpu(vmxarea
, cpu
) = NULL
;
2485 static __init
int alloc_kvm_area(void)
2489 for_each_possible_cpu(cpu
) {
2492 vmcs
= alloc_vmcs_cpu(cpu
);
2498 per_cpu(vmxarea
, cpu
) = vmcs
;
2503 static __init
int hardware_setup(void)
2505 if (setup_vmcs_config(&vmcs_config
) < 0)
2508 if (boot_cpu_has(X86_FEATURE_NX
))
2509 kvm_enable_efer_bits(EFER_NX
);
2511 if (!cpu_has_vmx_vpid())
2514 if (!cpu_has_vmx_ept() ||
2515 !cpu_has_vmx_ept_4levels()) {
2517 enable_unrestricted_guest
= 0;
2520 if (!cpu_has_vmx_unrestricted_guest())
2521 enable_unrestricted_guest
= 0;
2523 if (!cpu_has_vmx_flexpriority())
2524 flexpriority_enabled
= 0;
2526 if (!cpu_has_vmx_tpr_shadow())
2527 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2529 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2530 kvm_disable_largepages();
2532 if (!cpu_has_vmx_ple())
2536 nested_vmx_setup_ctls_msrs();
2538 return alloc_kvm_area();
2541 static __exit
void hardware_unsetup(void)
2546 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2548 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2550 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2551 vmcs_write16(sf
->selector
, save
->selector
);
2552 vmcs_writel(sf
->base
, save
->base
);
2553 vmcs_write32(sf
->limit
, save
->limit
);
2554 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2556 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2558 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2562 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2564 unsigned long flags
;
2565 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2567 vmx
->emulation_required
= 1;
2568 vmx
->rmode
.vm86_active
= 0;
2570 vmx_segment_cache_clear(vmx
);
2572 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2573 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2574 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2575 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2577 flags
= vmcs_readl(GUEST_RFLAGS
);
2578 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2579 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2580 vmcs_writel(GUEST_RFLAGS
, flags
);
2582 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2583 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2585 update_exception_bitmap(vcpu
);
2587 if (emulate_invalid_guest_state
)
2590 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2591 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2592 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2593 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2595 vmx_segment_cache_clear(vmx
);
2597 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2598 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2600 vmcs_write16(GUEST_CS_SELECTOR
,
2601 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2602 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2605 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2607 if (!kvm
->arch
.tss_addr
) {
2608 struct kvm_memslots
*slots
;
2611 slots
= kvm_memslots(kvm
);
2612 base_gfn
= slots
->memslots
[0].base_gfn
+
2613 kvm
->memslots
->memslots
[0].npages
- 3;
2614 return base_gfn
<< PAGE_SHIFT
;
2616 return kvm
->arch
.tss_addr
;
2619 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2621 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2623 save
->selector
= vmcs_read16(sf
->selector
);
2624 save
->base
= vmcs_readl(sf
->base
);
2625 save
->limit
= vmcs_read32(sf
->limit
);
2626 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2627 vmcs_write16(sf
->selector
, save
->base
>> 4);
2628 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2629 vmcs_write32(sf
->limit
, 0xffff);
2630 vmcs_write32(sf
->ar_bytes
, 0xf3);
2631 if (save
->base
& 0xf)
2632 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2633 " aligned when entering protected mode (seg=%d)",
2637 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2639 unsigned long flags
;
2640 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2642 if (enable_unrestricted_guest
)
2645 vmx
->emulation_required
= 1;
2646 vmx
->rmode
.vm86_active
= 1;
2649 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2650 * vcpu. Call it here with phys address pointing 16M below 4G.
2652 if (!vcpu
->kvm
->arch
.tss_addr
) {
2653 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2654 "called before entering vcpu\n");
2655 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2656 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2657 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2660 vmx_segment_cache_clear(vmx
);
2662 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2663 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2664 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2666 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2667 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2669 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2670 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2672 flags
= vmcs_readl(GUEST_RFLAGS
);
2673 vmx
->rmode
.save_rflags
= flags
;
2675 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2677 vmcs_writel(GUEST_RFLAGS
, flags
);
2678 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2679 update_exception_bitmap(vcpu
);
2681 if (emulate_invalid_guest_state
)
2682 goto continue_rmode
;
2684 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
2685 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
2686 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
2688 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
2689 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
2690 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
2691 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
2692 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
2694 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2695 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2696 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2697 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2700 kvm_mmu_reset_context(vcpu
);
2703 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2706 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2712 * Force kernel_gs_base reloading before EFER changes, as control
2713 * of this msr depends on is_long_mode().
2715 vmx_load_host_state(to_vmx(vcpu
));
2716 vcpu
->arch
.efer
= efer
;
2717 if (efer
& EFER_LMA
) {
2718 vmcs_write32(VM_ENTRY_CONTROLS
,
2719 vmcs_read32(VM_ENTRY_CONTROLS
) |
2720 VM_ENTRY_IA32E_MODE
);
2723 vmcs_write32(VM_ENTRY_CONTROLS
,
2724 vmcs_read32(VM_ENTRY_CONTROLS
) &
2725 ~VM_ENTRY_IA32E_MODE
);
2727 msr
->data
= efer
& ~EFER_LME
;
2732 #ifdef CONFIG_X86_64
2734 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2738 vmx_segment_cache_clear(to_vmx(vcpu
));
2740 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2741 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2742 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
2744 vmcs_write32(GUEST_TR_AR_BYTES
,
2745 (guest_tr_ar
& ~AR_TYPE_MASK
)
2746 | AR_TYPE_BUSY_64_TSS
);
2748 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2751 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2753 vmcs_write32(VM_ENTRY_CONTROLS
,
2754 vmcs_read32(VM_ENTRY_CONTROLS
)
2755 & ~VM_ENTRY_IA32E_MODE
);
2756 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2761 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2763 vpid_sync_context(to_vmx(vcpu
));
2765 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2767 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2771 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2773 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2775 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2776 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2779 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2781 if (enable_ept
&& is_paging(vcpu
))
2782 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2783 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2786 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2788 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2790 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2791 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2794 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2796 if (!test_bit(VCPU_EXREG_PDPTR
,
2797 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2800 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2801 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2802 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2803 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2804 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2808 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2810 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2811 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2812 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2813 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2814 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2817 __set_bit(VCPU_EXREG_PDPTR
,
2818 (unsigned long *)&vcpu
->arch
.regs_avail
);
2819 __set_bit(VCPU_EXREG_PDPTR
,
2820 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2823 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2825 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2827 struct kvm_vcpu
*vcpu
)
2829 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2830 vmx_decache_cr3(vcpu
);
2831 if (!(cr0
& X86_CR0_PG
)) {
2832 /* From paging/starting to nonpaging */
2833 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2834 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2835 (CPU_BASED_CR3_LOAD_EXITING
|
2836 CPU_BASED_CR3_STORE_EXITING
));
2837 vcpu
->arch
.cr0
= cr0
;
2838 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2839 } else if (!is_paging(vcpu
)) {
2840 /* From nonpaging to paging */
2841 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2842 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
2843 ~(CPU_BASED_CR3_LOAD_EXITING
|
2844 CPU_BASED_CR3_STORE_EXITING
));
2845 vcpu
->arch
.cr0
= cr0
;
2846 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2849 if (!(cr0
& X86_CR0_WP
))
2850 *hw_cr0
&= ~X86_CR0_WP
;
2853 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2855 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2856 unsigned long hw_cr0
;
2858 if (enable_unrestricted_guest
)
2859 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
2860 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
2862 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
2864 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
2867 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
2870 #ifdef CONFIG_X86_64
2871 if (vcpu
->arch
.efer
& EFER_LME
) {
2872 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
2874 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
2880 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
2882 if (!vcpu
->fpu_active
)
2883 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
2885 vmcs_writel(CR0_READ_SHADOW
, cr0
);
2886 vmcs_writel(GUEST_CR0
, hw_cr0
);
2887 vcpu
->arch
.cr0
= cr0
;
2888 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2891 static u64
construct_eptp(unsigned long root_hpa
)
2895 /* TODO write the value reading from MSR */
2896 eptp
= VMX_EPT_DEFAULT_MT
|
2897 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
2898 eptp
|= (root_hpa
& PAGE_MASK
);
2903 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
2905 unsigned long guest_cr3
;
2910 eptp
= construct_eptp(cr3
);
2911 vmcs_write64(EPT_POINTER
, eptp
);
2912 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
2913 vcpu
->kvm
->arch
.ept_identity_map_addr
;
2914 ept_load_pdptrs(vcpu
);
2917 vmx_flush_tlb(vcpu
);
2918 vmcs_writel(GUEST_CR3
, guest_cr3
);
2921 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2923 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
2924 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
2926 if (cr4
& X86_CR4_VMXE
) {
2928 * To use VMXON (and later other VMX instructions), a guest
2929 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2930 * So basically the check on whether to allow nested VMX
2933 if (!nested_vmx_allowed(vcpu
))
2935 } else if (to_vmx(vcpu
)->nested
.vmxon
)
2938 vcpu
->arch
.cr4
= cr4
;
2940 if (!is_paging(vcpu
)) {
2941 hw_cr4
&= ~X86_CR4_PAE
;
2942 hw_cr4
|= X86_CR4_PSE
;
2943 } else if (!(cr4
& X86_CR4_PAE
)) {
2944 hw_cr4
&= ~X86_CR4_PAE
;
2948 vmcs_writel(CR4_READ_SHADOW
, cr4
);
2949 vmcs_writel(GUEST_CR4
, hw_cr4
);
2953 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2954 struct kvm_segment
*var
, int seg
)
2956 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2957 struct kvm_save_segment
*save
;
2960 if (vmx
->rmode
.vm86_active
2961 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
2962 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
2963 || seg
== VCPU_SREG_GS
)
2964 && !emulate_invalid_guest_state
) {
2966 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
2967 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
2968 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
2969 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
2970 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
2973 var
->selector
= save
->selector
;
2974 var
->base
= save
->base
;
2975 var
->limit
= save
->limit
;
2977 if (seg
== VCPU_SREG_TR
2978 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
2979 goto use_saved_rmode_seg
;
2981 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
2982 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
2983 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
2984 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
2985 use_saved_rmode_seg
:
2986 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2988 var
->type
= ar
& 15;
2989 var
->s
= (ar
>> 4) & 1;
2990 var
->dpl
= (ar
>> 5) & 3;
2991 var
->present
= (ar
>> 7) & 1;
2992 var
->avl
= (ar
>> 12) & 1;
2993 var
->l
= (ar
>> 13) & 1;
2994 var
->db
= (ar
>> 14) & 1;
2995 var
->g
= (ar
>> 15) & 1;
2996 var
->unusable
= (ar
>> 16) & 1;
2999 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3001 struct kvm_segment s
;
3003 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3004 vmx_get_segment(vcpu
, &s
, seg
);
3007 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3010 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3012 if (!is_protmode(vcpu
))
3015 if (!is_long_mode(vcpu
)
3016 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
3019 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
3022 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3024 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
3025 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3026 to_vmx(vcpu
)->cpl
= __vmx_get_cpl(vcpu
);
3028 return to_vmx(vcpu
)->cpl
;
3032 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3039 ar
= var
->type
& 15;
3040 ar
|= (var
->s
& 1) << 4;
3041 ar
|= (var
->dpl
& 3) << 5;
3042 ar
|= (var
->present
& 1) << 7;
3043 ar
|= (var
->avl
& 1) << 12;
3044 ar
|= (var
->l
& 1) << 13;
3045 ar
|= (var
->db
& 1) << 14;
3046 ar
|= (var
->g
& 1) << 15;
3048 if (ar
== 0) /* a 0 value means unusable */
3049 ar
= AR_UNUSABLE_MASK
;
3054 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3055 struct kvm_segment
*var
, int seg
)
3057 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3058 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3061 vmx_segment_cache_clear(vmx
);
3063 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
3064 vmcs_write16(sf
->selector
, var
->selector
);
3065 vmx
->rmode
.tr
.selector
= var
->selector
;
3066 vmx
->rmode
.tr
.base
= var
->base
;
3067 vmx
->rmode
.tr
.limit
= var
->limit
;
3068 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
3071 vmcs_writel(sf
->base
, var
->base
);
3072 vmcs_write32(sf
->limit
, var
->limit
);
3073 vmcs_write16(sf
->selector
, var
->selector
);
3074 if (vmx
->rmode
.vm86_active
&& var
->s
) {
3076 * Hack real-mode segments into vm86 compatibility.
3078 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
3079 vmcs_writel(sf
->base
, 0xf0000);
3082 ar
= vmx_segment_access_rights(var
);
3085 * Fix the "Accessed" bit in AR field of segment registers for older
3087 * IA32 arch specifies that at the time of processor reset the
3088 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3089 * is setting it to 0 in the usedland code. This causes invalid guest
3090 * state vmexit when "unrestricted guest" mode is turned on.
3091 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3092 * tree. Newer qemu binaries with that qemu fix would not need this
3095 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3096 ar
|= 0x1; /* Accessed */
3098 vmcs_write32(sf
->ar_bytes
, ar
);
3099 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
3102 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3104 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3106 *db
= (ar
>> 14) & 1;
3107 *l
= (ar
>> 13) & 1;
3110 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3112 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3113 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3116 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3118 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3119 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3122 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3124 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3125 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3128 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3130 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3131 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3134 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3136 struct kvm_segment var
;
3139 vmx_get_segment(vcpu
, &var
, seg
);
3140 ar
= vmx_segment_access_rights(&var
);
3142 if (var
.base
!= (var
.selector
<< 4))
3144 if (var
.limit
!= 0xffff)
3152 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3154 struct kvm_segment cs
;
3155 unsigned int cs_rpl
;
3157 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3158 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3162 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3166 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3167 if (cs
.dpl
> cs_rpl
)
3170 if (cs
.dpl
!= cs_rpl
)
3176 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3180 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3182 struct kvm_segment ss
;
3183 unsigned int ss_rpl
;
3185 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3186 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3190 if (ss
.type
!= 3 && ss
.type
!= 7)
3194 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3202 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3204 struct kvm_segment var
;
3207 vmx_get_segment(vcpu
, &var
, seg
);
3208 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3216 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3217 if (var
.dpl
< rpl
) /* DPL < RPL */
3221 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3227 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3229 struct kvm_segment tr
;
3231 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3235 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3237 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3245 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3247 struct kvm_segment ldtr
;
3249 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3253 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3263 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3265 struct kvm_segment cs
, ss
;
3267 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3268 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3270 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3271 (ss
.selector
& SELECTOR_RPL_MASK
));
3275 * Check if guest state is valid. Returns true if valid, false if
3277 * We assume that registers are always usable
3279 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3281 /* real mode guest state checks */
3282 if (!is_protmode(vcpu
)) {
3283 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3285 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3287 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3289 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3291 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3293 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3296 /* protected mode guest state checks */
3297 if (!cs_ss_rpl_check(vcpu
))
3299 if (!code_segment_valid(vcpu
))
3301 if (!stack_segment_valid(vcpu
))
3303 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3305 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3307 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3309 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3311 if (!tr_valid(vcpu
))
3313 if (!ldtr_valid(vcpu
))
3317 * - Add checks on RIP
3318 * - Add checks on RFLAGS
3324 static int init_rmode_tss(struct kvm
*kvm
)
3328 int r
, idx
, ret
= 0;
3330 idx
= srcu_read_lock(&kvm
->srcu
);
3331 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
3332 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3335 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3336 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3337 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3340 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3343 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3347 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3348 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3355 srcu_read_unlock(&kvm
->srcu
, idx
);
3359 static int init_rmode_identity_map(struct kvm
*kvm
)
3362 pfn_t identity_map_pfn
;
3367 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3368 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3369 "haven't been allocated!\n");
3372 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3375 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3376 idx
= srcu_read_lock(&kvm
->srcu
);
3377 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3380 /* Set up identity-mapping pagetable for EPT in real mode */
3381 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3382 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3383 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3384 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3385 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3389 kvm
->arch
.ept_identity_pagetable_done
= true;
3392 srcu_read_unlock(&kvm
->srcu
, idx
);
3396 static void seg_setup(int seg
)
3398 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3401 vmcs_write16(sf
->selector
, 0);
3402 vmcs_writel(sf
->base
, 0);
3403 vmcs_write32(sf
->limit
, 0xffff);
3404 if (enable_unrestricted_guest
) {
3406 if (seg
== VCPU_SREG_CS
)
3407 ar
|= 0x08; /* code segment */
3411 vmcs_write32(sf
->ar_bytes
, ar
);
3414 static int alloc_apic_access_page(struct kvm
*kvm
)
3416 struct kvm_userspace_memory_region kvm_userspace_mem
;
3419 mutex_lock(&kvm
->slots_lock
);
3420 if (kvm
->arch
.apic_access_page
)
3422 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3423 kvm_userspace_mem
.flags
= 0;
3424 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3425 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3426 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3430 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3432 mutex_unlock(&kvm
->slots_lock
);
3436 static int alloc_identity_pagetable(struct kvm
*kvm
)
3438 struct kvm_userspace_memory_region kvm_userspace_mem
;
3441 mutex_lock(&kvm
->slots_lock
);
3442 if (kvm
->arch
.ept_identity_pagetable
)
3444 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3445 kvm_userspace_mem
.flags
= 0;
3446 kvm_userspace_mem
.guest_phys_addr
=
3447 kvm
->arch
.ept_identity_map_addr
;
3448 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3449 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3453 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3454 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3456 mutex_unlock(&kvm
->slots_lock
);
3460 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3467 spin_lock(&vmx_vpid_lock
);
3468 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3469 if (vpid
< VMX_NR_VPIDS
) {
3471 __set_bit(vpid
, vmx_vpid_bitmap
);
3473 spin_unlock(&vmx_vpid_lock
);
3476 static void free_vpid(struct vcpu_vmx
*vmx
)
3480 spin_lock(&vmx_vpid_lock
);
3482 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3483 spin_unlock(&vmx_vpid_lock
);
3486 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3488 int f
= sizeof(unsigned long);
3490 if (!cpu_has_vmx_msr_bitmap())
3494 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3495 * have the write-low and read-high bitmap offsets the wrong way round.
3496 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3498 if (msr
<= 0x1fff) {
3499 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3500 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3501 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3503 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3504 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3508 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3511 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3512 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3516 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3517 * will not change in the lifetime of the guest.
3518 * Note that host-state that does change is set elsewhere. E.g., host-state
3519 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3521 static void vmx_set_constant_host_state(void)
3527 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3528 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3529 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3531 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3532 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3533 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3534 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3535 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3537 native_store_idt(&dt
);
3538 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3540 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl
));
3541 vmcs_writel(HOST_RIP
, tmpl
); /* 22.2.5 */
3543 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
3544 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
3545 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
3546 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
3548 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3549 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
3550 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
3554 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
3556 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3558 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3559 if (is_guest_mode(&vmx
->vcpu
))
3560 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
3561 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
3562 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3565 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
3567 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3568 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3569 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3570 #ifdef CONFIG_X86_64
3571 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3572 CPU_BASED_CR8_LOAD_EXITING
;
3576 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3577 CPU_BASED_CR3_LOAD_EXITING
|
3578 CPU_BASED_INVLPG_EXITING
;
3579 return exec_control
;
3582 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
3584 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3585 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3586 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3588 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3590 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3591 enable_unrestricted_guest
= 0;
3593 if (!enable_unrestricted_guest
)
3594 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3596 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3597 return exec_control
;
3601 * Sets up the vmcs for emulated real mode.
3603 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3609 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3610 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3612 if (cpu_has_vmx_msr_bitmap())
3613 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3615 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3618 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3619 vmcs_config
.pin_based_exec_ctrl
);
3621 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
3623 if (cpu_has_secondary_exec_ctrls()) {
3624 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
3625 vmx_secondary_exec_control(vmx
));
3629 vmcs_write32(PLE_GAP
, ple_gap
);
3630 vmcs_write32(PLE_WINDOW
, ple_window
);
3633 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
3634 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
3635 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3637 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3638 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3639 vmx_set_constant_host_state();
3640 #ifdef CONFIG_X86_64
3641 rdmsrl(MSR_FS_BASE
, a
);
3642 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3643 rdmsrl(MSR_GS_BASE
, a
);
3644 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3646 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3647 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3650 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3651 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3652 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3653 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3654 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3656 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3657 u32 msr_low
, msr_high
;
3659 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3660 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3661 /* Write the default value follow host pat */
3662 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3663 /* Keep arch.pat sync with GUEST_IA32_PAT */
3664 vmx
->vcpu
.arch
.pat
= host_pat
;
3667 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3668 u32 index
= vmx_msr_index
[i
];
3669 u32 data_low
, data_high
;
3672 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3674 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3676 vmx
->guest_msrs
[j
].index
= i
;
3677 vmx
->guest_msrs
[j
].data
= 0;
3678 vmx
->guest_msrs
[j
].mask
= -1ull;
3682 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3684 /* 22.2.1, 20.8.1 */
3685 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3687 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3688 set_cr4_guest_host_mask(vmx
);
3690 kvm_write_tsc(&vmx
->vcpu
, 0);
3695 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3697 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3701 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3703 vmx
->rmode
.vm86_active
= 0;
3705 vmx
->soft_vnmi_blocked
= 0;
3707 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3708 kvm_set_cr8(&vmx
->vcpu
, 0);
3709 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3710 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3711 msr
|= MSR_IA32_APICBASE_BSP
;
3712 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3714 ret
= fx_init(&vmx
->vcpu
);
3718 vmx_segment_cache_clear(vmx
);
3720 seg_setup(VCPU_SREG_CS
);
3722 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3723 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3725 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3726 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3727 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3729 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3730 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3733 seg_setup(VCPU_SREG_DS
);
3734 seg_setup(VCPU_SREG_ES
);
3735 seg_setup(VCPU_SREG_FS
);
3736 seg_setup(VCPU_SREG_GS
);
3737 seg_setup(VCPU_SREG_SS
);
3739 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3740 vmcs_writel(GUEST_TR_BASE
, 0);
3741 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3742 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3744 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3745 vmcs_writel(GUEST_LDTR_BASE
, 0);
3746 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3747 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3749 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3750 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3751 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3753 vmcs_writel(GUEST_RFLAGS
, 0x02);
3754 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3755 kvm_rip_write(vcpu
, 0xfff0);
3757 kvm_rip_write(vcpu
, 0);
3758 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3760 vmcs_writel(GUEST_DR7
, 0x400);
3762 vmcs_writel(GUEST_GDTR_BASE
, 0);
3763 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3765 vmcs_writel(GUEST_IDTR_BASE
, 0);
3766 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3768 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3769 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3770 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3772 /* Special registers */
3773 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
3777 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
3779 if (cpu_has_vmx_tpr_shadow()) {
3780 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
3781 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
3782 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
3783 __pa(vmx
->vcpu
.arch
.apic
->regs
));
3784 vmcs_write32(TPR_THRESHOLD
, 0);
3787 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3788 vmcs_write64(APIC_ACCESS_ADDR
,
3789 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
3792 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
3794 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
3795 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
3796 vmx_set_cr4(&vmx
->vcpu
, 0);
3797 vmx_set_efer(&vmx
->vcpu
, 0);
3798 vmx_fpu_activate(&vmx
->vcpu
);
3799 update_exception_bitmap(&vmx
->vcpu
);
3801 vpid_sync_context(vmx
);
3805 /* HACK: Don't enable emulation on guest boot/reset */
3806 vmx
->emulation_required
= 0;
3813 * In nested virtualization, check if L1 asked to exit on external interrupts.
3814 * For most existing hypervisors, this will always return true.
3816 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
3818 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
3819 PIN_BASED_EXT_INTR_MASK
;
3822 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3824 u32 cpu_based_vm_exec_control
;
3825 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
))
3826 /* We can get here when nested_run_pending caused
3827 * vmx_interrupt_allowed() to return false. In this case, do
3828 * nothing - the interrupt will be injected later.
3832 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3833 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
3834 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3837 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3839 u32 cpu_based_vm_exec_control
;
3841 if (!cpu_has_virtual_nmis()) {
3842 enable_irq_window(vcpu
);
3846 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
3847 enable_irq_window(vcpu
);
3850 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3851 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
3852 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3855 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
3857 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3859 int irq
= vcpu
->arch
.interrupt
.nr
;
3861 trace_kvm_inj_virq(irq
);
3863 ++vcpu
->stat
.irq_injections
;
3864 if (vmx
->rmode
.vm86_active
) {
3866 if (vcpu
->arch
.interrupt
.soft
)
3867 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
3868 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
3869 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3872 intr
= irq
| INTR_INFO_VALID_MASK
;
3873 if (vcpu
->arch
.interrupt
.soft
) {
3874 intr
|= INTR_TYPE_SOFT_INTR
;
3875 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
3876 vmx
->vcpu
.arch
.event_exit_inst_len
);
3878 intr
|= INTR_TYPE_EXT_INTR
;
3879 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
3880 vmx_clear_hlt(vcpu
);
3883 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
3885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3887 if (is_guest_mode(vcpu
))
3890 if (!cpu_has_virtual_nmis()) {
3892 * Tracking the NMI-blocked state in software is built upon
3893 * finding the next open IRQ window. This, in turn, depends on
3894 * well-behaving guests: They have to keep IRQs disabled at
3895 * least as long as the NMI handler runs. Otherwise we may
3896 * cause NMI nesting, maybe breaking the guest. But as this is
3897 * highly unlikely, we can live with the residual risk.
3899 vmx
->soft_vnmi_blocked
= 1;
3900 vmx
->vnmi_blocked_time
= 0;
3903 ++vcpu
->stat
.nmi_injections
;
3904 vmx
->nmi_known_unmasked
= false;
3905 if (vmx
->rmode
.vm86_active
) {
3906 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
3907 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3910 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
3911 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
3912 vmx_clear_hlt(vcpu
);
3915 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
3917 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
3920 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3921 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
3922 | GUEST_INTR_STATE_NMI
));
3925 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3927 if (!cpu_has_virtual_nmis())
3928 return to_vmx(vcpu
)->soft_vnmi_blocked
;
3929 if (to_vmx(vcpu
)->nmi_known_unmasked
)
3931 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
3934 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3936 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3938 if (!cpu_has_virtual_nmis()) {
3939 if (vmx
->soft_vnmi_blocked
!= masked
) {
3940 vmx
->soft_vnmi_blocked
= masked
;
3941 vmx
->vnmi_blocked_time
= 0;
3944 vmx
->nmi_known_unmasked
= !masked
;
3946 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3947 GUEST_INTR_STATE_NMI
);
3949 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3950 GUEST_INTR_STATE_NMI
);
3954 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3956 if (is_guest_mode(vcpu
) && nested_exit_on_intr(vcpu
)) {
3957 struct vmcs12
*vmcs12
;
3958 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
3960 nested_vmx_vmexit(vcpu
);
3961 vmcs12
= get_vmcs12(vcpu
);
3962 vmcs12
->vm_exit_reason
= EXIT_REASON_EXTERNAL_INTERRUPT
;
3963 vmcs12
->vm_exit_intr_info
= 0;
3964 /* fall through to normal code, but now in L1, not L2 */
3967 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
3968 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3969 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
3972 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3975 struct kvm_userspace_memory_region tss_mem
= {
3976 .slot
= TSS_PRIVATE_MEMSLOT
,
3977 .guest_phys_addr
= addr
,
3978 .memory_size
= PAGE_SIZE
* 3,
3982 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
3985 kvm
->arch
.tss_addr
= addr
;
3986 if (!init_rmode_tss(kvm
))
3992 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
3993 int vec
, u32 err_code
)
3996 * Instruction with address size override prefix opcode 0x67
3997 * Cause the #SS fault with 0 error code in VM86 mode.
3999 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
4000 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
4003 * Forward all other exceptions that are valid in real mode.
4004 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4005 * the required debugging infrastructure rework.
4009 if (vcpu
->guest_debug
&
4010 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4012 kvm_queue_exception(vcpu
, vec
);
4016 * Update instruction length as we may reinject the exception
4017 * from user space while in guest debugging mode.
4019 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4020 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4021 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4032 kvm_queue_exception(vcpu
, vec
);
4039 * Trigger machine check on the host. We assume all the MSRs are already set up
4040 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4041 * We pass a fake environment to the machine check handler because we want
4042 * the guest to be always treated like user space, no matter what context
4043 * it used internally.
4045 static void kvm_machine_check(void)
4047 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4048 struct pt_regs regs
= {
4049 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4050 .flags
= X86_EFLAGS_IF
,
4053 do_machine_check(®s
, 0);
4057 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4059 /* already handled by vcpu_run */
4063 static int handle_exception(struct kvm_vcpu
*vcpu
)
4065 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4066 struct kvm_run
*kvm_run
= vcpu
->run
;
4067 u32 intr_info
, ex_no
, error_code
;
4068 unsigned long cr2
, rip
, dr6
;
4070 enum emulation_result er
;
4072 vect_info
= vmx
->idt_vectoring_info
;
4073 intr_info
= vmx
->exit_intr_info
;
4075 if (is_machine_check(intr_info
))
4076 return handle_machine_check(vcpu
);
4078 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4079 !is_page_fault(intr_info
)) {
4080 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4081 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4082 vcpu
->run
->internal
.ndata
= 2;
4083 vcpu
->run
->internal
.data
[0] = vect_info
;
4084 vcpu
->run
->internal
.data
[1] = intr_info
;
4088 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4089 return 1; /* already handled by vmx_vcpu_run() */
4091 if (is_no_device(intr_info
)) {
4092 vmx_fpu_activate(vcpu
);
4096 if (is_invalid_opcode(intr_info
)) {
4097 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4098 if (er
!= EMULATE_DONE
)
4099 kvm_queue_exception(vcpu
, UD_VECTOR
);
4104 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4105 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4106 if (is_page_fault(intr_info
)) {
4107 /* EPT won't cause page fault directly */
4110 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4111 trace_kvm_page_fault(cr2
, error_code
);
4113 if (kvm_event_needs_reinjection(vcpu
))
4114 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4115 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4118 if (vmx
->rmode
.vm86_active
&&
4119 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
4121 if (vcpu
->arch
.halt_request
) {
4122 vcpu
->arch
.halt_request
= 0;
4123 return kvm_emulate_halt(vcpu
);
4128 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4131 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4132 if (!(vcpu
->guest_debug
&
4133 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4134 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
4135 kvm_queue_exception(vcpu
, DB_VECTOR
);
4138 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4139 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4143 * Update instruction length as we may reinject #BP from
4144 * user space while in guest debugging mode. Reading it for
4145 * #DB as well causes no harm, it is not used in that case.
4147 vmx
->vcpu
.arch
.event_exit_inst_len
=
4148 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4149 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4150 rip
= kvm_rip_read(vcpu
);
4151 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4152 kvm_run
->debug
.arch
.exception
= ex_no
;
4155 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4156 kvm_run
->ex
.exception
= ex_no
;
4157 kvm_run
->ex
.error_code
= error_code
;
4163 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4165 ++vcpu
->stat
.irq_exits
;
4169 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4171 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4175 static int handle_io(struct kvm_vcpu
*vcpu
)
4177 unsigned long exit_qualification
;
4178 int size
, in
, string
;
4181 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4182 string
= (exit_qualification
& 16) != 0;
4183 in
= (exit_qualification
& 8) != 0;
4185 ++vcpu
->stat
.io_exits
;
4188 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4190 port
= exit_qualification
>> 16;
4191 size
= (exit_qualification
& 7) + 1;
4192 skip_emulated_instruction(vcpu
);
4194 return kvm_fast_pio_out(vcpu
, size
, port
);
4198 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4201 * Patch in the VMCALL instruction:
4203 hypercall
[0] = 0x0f;
4204 hypercall
[1] = 0x01;
4205 hypercall
[2] = 0xc1;
4208 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4209 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4211 if (to_vmx(vcpu
)->nested
.vmxon
&&
4212 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4215 if (is_guest_mode(vcpu
)) {
4217 * We get here when L2 changed cr0 in a way that did not change
4218 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4219 * but did change L0 shadowed bits. This can currently happen
4220 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4221 * loading) while pretending to allow the guest to change it.
4223 if (kvm_set_cr0(vcpu
, (val
& vcpu
->arch
.cr0_guest_owned_bits
) |
4224 (vcpu
->arch
.cr0
& ~vcpu
->arch
.cr0_guest_owned_bits
)))
4226 vmcs_writel(CR0_READ_SHADOW
, val
);
4229 return kvm_set_cr0(vcpu
, val
);
4232 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4234 if (is_guest_mode(vcpu
)) {
4235 if (kvm_set_cr4(vcpu
, (val
& vcpu
->arch
.cr4_guest_owned_bits
) |
4236 (vcpu
->arch
.cr4
& ~vcpu
->arch
.cr4_guest_owned_bits
)))
4238 vmcs_writel(CR4_READ_SHADOW
, val
);
4241 return kvm_set_cr4(vcpu
, val
);
4244 /* called to set cr0 as approriate for clts instruction exit. */
4245 static void handle_clts(struct kvm_vcpu
*vcpu
)
4247 if (is_guest_mode(vcpu
)) {
4249 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4250 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4251 * just pretend it's off (also in arch.cr0 for fpu_activate).
4253 vmcs_writel(CR0_READ_SHADOW
,
4254 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
4255 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
4257 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
4260 static int handle_cr(struct kvm_vcpu
*vcpu
)
4262 unsigned long exit_qualification
, val
;
4267 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4268 cr
= exit_qualification
& 15;
4269 reg
= (exit_qualification
>> 8) & 15;
4270 switch ((exit_qualification
>> 4) & 3) {
4271 case 0: /* mov to cr */
4272 val
= kvm_register_read(vcpu
, reg
);
4273 trace_kvm_cr_write(cr
, val
);
4276 err
= handle_set_cr0(vcpu
, val
);
4277 kvm_complete_insn_gp(vcpu
, err
);
4280 err
= kvm_set_cr3(vcpu
, val
);
4281 kvm_complete_insn_gp(vcpu
, err
);
4284 err
= handle_set_cr4(vcpu
, val
);
4285 kvm_complete_insn_gp(vcpu
, err
);
4288 u8 cr8_prev
= kvm_get_cr8(vcpu
);
4289 u8 cr8
= kvm_register_read(vcpu
, reg
);
4290 err
= kvm_set_cr8(vcpu
, cr8
);
4291 kvm_complete_insn_gp(vcpu
, err
);
4292 if (irqchip_in_kernel(vcpu
->kvm
))
4294 if (cr8_prev
<= cr8
)
4296 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
4303 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
4304 skip_emulated_instruction(vcpu
);
4305 vmx_fpu_activate(vcpu
);
4307 case 1: /*mov from cr*/
4310 val
= kvm_read_cr3(vcpu
);
4311 kvm_register_write(vcpu
, reg
, val
);
4312 trace_kvm_cr_read(cr
, val
);
4313 skip_emulated_instruction(vcpu
);
4316 val
= kvm_get_cr8(vcpu
);
4317 kvm_register_write(vcpu
, reg
, val
);
4318 trace_kvm_cr_read(cr
, val
);
4319 skip_emulated_instruction(vcpu
);
4324 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
4325 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
4326 kvm_lmsw(vcpu
, val
);
4328 skip_emulated_instruction(vcpu
);
4333 vcpu
->run
->exit_reason
= 0;
4334 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
4335 (int)(exit_qualification
>> 4) & 3, cr
);
4339 static int handle_dr(struct kvm_vcpu
*vcpu
)
4341 unsigned long exit_qualification
;
4344 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4345 if (!kvm_require_cpl(vcpu
, 0))
4347 dr
= vmcs_readl(GUEST_DR7
);
4350 * As the vm-exit takes precedence over the debug trap, we
4351 * need to emulate the latter, either for the host or the
4352 * guest debugging itself.
4354 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
4355 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
4356 vcpu
->run
->debug
.arch
.dr7
= dr
;
4357 vcpu
->run
->debug
.arch
.pc
=
4358 vmcs_readl(GUEST_CS_BASE
) +
4359 vmcs_readl(GUEST_RIP
);
4360 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
4361 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
4364 vcpu
->arch
.dr7
&= ~DR7_GD
;
4365 vcpu
->arch
.dr6
|= DR6_BD
;
4366 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
4367 kvm_queue_exception(vcpu
, DB_VECTOR
);
4372 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4373 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
4374 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
4375 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
4377 if (!kvm_get_dr(vcpu
, dr
, &val
))
4378 kvm_register_write(vcpu
, reg
, val
);
4380 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
4381 skip_emulated_instruction(vcpu
);
4385 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
4387 vmcs_writel(GUEST_DR7
, val
);
4390 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
4392 kvm_emulate_cpuid(vcpu
);
4396 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
4398 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4401 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
4402 trace_kvm_msr_read_ex(ecx
);
4403 kvm_inject_gp(vcpu
, 0);
4407 trace_kvm_msr_read(ecx
, data
);
4409 /* FIXME: handling of bits 32:63 of rax, rdx */
4410 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
4411 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
4412 skip_emulated_instruction(vcpu
);
4416 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
4418 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
4419 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
4420 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
4422 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
4423 trace_kvm_msr_write_ex(ecx
, data
);
4424 kvm_inject_gp(vcpu
, 0);
4428 trace_kvm_msr_write(ecx
, data
);
4429 skip_emulated_instruction(vcpu
);
4433 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
4435 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4439 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
4441 u32 cpu_based_vm_exec_control
;
4443 /* clear pending irq */
4444 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4445 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
4446 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4448 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4450 ++vcpu
->stat
.irq_window_exits
;
4453 * If the user space waits to inject interrupts, exit as soon as
4456 if (!irqchip_in_kernel(vcpu
->kvm
) &&
4457 vcpu
->run
->request_interrupt_window
&&
4458 !kvm_cpu_has_interrupt(vcpu
)) {
4459 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
4465 static int handle_halt(struct kvm_vcpu
*vcpu
)
4467 skip_emulated_instruction(vcpu
);
4468 return kvm_emulate_halt(vcpu
);
4471 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
4473 skip_emulated_instruction(vcpu
);
4474 kvm_emulate_hypercall(vcpu
);
4478 static int handle_invd(struct kvm_vcpu
*vcpu
)
4480 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4483 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
4485 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4487 kvm_mmu_invlpg(vcpu
, exit_qualification
);
4488 skip_emulated_instruction(vcpu
);
4492 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
4494 skip_emulated_instruction(vcpu
);
4495 kvm_emulate_wbinvd(vcpu
);
4499 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
4501 u64 new_bv
= kvm_read_edx_eax(vcpu
);
4502 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
4504 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
4505 skip_emulated_instruction(vcpu
);
4509 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
4511 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4514 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
4516 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4517 unsigned long exit_qualification
;
4518 bool has_error_code
= false;
4521 int reason
, type
, idt_v
;
4523 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4524 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4526 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4528 reason
= (u32
)exit_qualification
>> 30;
4529 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4531 case INTR_TYPE_NMI_INTR
:
4532 vcpu
->arch
.nmi_injected
= false;
4533 vmx_set_nmi_mask(vcpu
, true);
4535 case INTR_TYPE_EXT_INTR
:
4536 case INTR_TYPE_SOFT_INTR
:
4537 kvm_clear_interrupt_queue(vcpu
);
4539 case INTR_TYPE_HARD_EXCEPTION
:
4540 if (vmx
->idt_vectoring_info
&
4541 VECTORING_INFO_DELIVER_CODE_MASK
) {
4542 has_error_code
= true;
4544 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4547 case INTR_TYPE_SOFT_EXCEPTION
:
4548 kvm_clear_exception_queue(vcpu
);
4554 tss_selector
= exit_qualification
;
4556 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4557 type
!= INTR_TYPE_EXT_INTR
&&
4558 type
!= INTR_TYPE_NMI_INTR
))
4559 skip_emulated_instruction(vcpu
);
4561 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
4562 has_error_code
, error_code
) == EMULATE_FAIL
) {
4563 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4564 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4565 vcpu
->run
->internal
.ndata
= 0;
4569 /* clear all local breakpoint enable flags */
4570 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4573 * TODO: What about debug traps on tss switch?
4574 * Are we supposed to inject them and update dr6?
4580 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4582 unsigned long exit_qualification
;
4586 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4588 if (exit_qualification
& (1 << 6)) {
4589 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4593 gla_validity
= (exit_qualification
>> 7) & 0x3;
4594 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4595 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4596 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4597 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4598 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4599 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4600 (long unsigned int)exit_qualification
);
4601 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4602 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4606 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4607 trace_kvm_page_fault(gpa
, exit_qualification
);
4608 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
4611 static u64
ept_rsvd_mask(u64 spte
, int level
)
4616 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4617 mask
|= (1ULL << i
);
4620 /* bits 7:3 reserved */
4622 else if (level
== 2) {
4623 if (spte
& (1ULL << 7))
4624 /* 2MB ref, bits 20:12 reserved */
4627 /* bits 6:3 reserved */
4634 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4637 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4639 /* 010b (write-only) */
4640 WARN_ON((spte
& 0x7) == 0x2);
4642 /* 110b (write/execute) */
4643 WARN_ON((spte
& 0x7) == 0x6);
4645 /* 100b (execute-only) and value not supported by logical processor */
4646 if (!cpu_has_vmx_ept_execute_only())
4647 WARN_ON((spte
& 0x7) == 0x4);
4651 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4653 if (rsvd_bits
!= 0) {
4654 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4655 __func__
, rsvd_bits
);
4659 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4660 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4662 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4663 ept_mem_type
== 7) {
4664 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4665 __func__
, ept_mem_type
);
4672 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4678 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4680 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4681 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4683 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4685 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4686 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4688 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4689 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4694 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4696 u32 cpu_based_vm_exec_control
;
4698 /* clear pending NMI */
4699 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4700 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4701 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4702 ++vcpu
->stat
.nmi_window_exits
;
4703 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4708 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4710 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4711 enum emulation_result err
= EMULATE_DONE
;
4714 bool intr_window_requested
;
4716 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4717 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4719 while (!guest_state_valid(vcpu
)) {
4720 if (intr_window_requested
4721 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
4722 return handle_interrupt_window(&vmx
->vcpu
);
4724 err
= emulate_instruction(vcpu
, 0);
4726 if (err
== EMULATE_DO_MMIO
) {
4731 if (err
!= EMULATE_DONE
)
4734 if (signal_pending(current
))
4740 vmx
->emulation_required
= 0;
4746 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4747 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4749 static int handle_pause(struct kvm_vcpu
*vcpu
)
4751 skip_emulated_instruction(vcpu
);
4752 kvm_vcpu_on_spin(vcpu
);
4757 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
4759 kvm_queue_exception(vcpu
, UD_VECTOR
);
4764 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4765 * We could reuse a single VMCS for all the L2 guests, but we also want the
4766 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4767 * allows keeping them loaded on the processor, and in the future will allow
4768 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4769 * every entry if they never change.
4770 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4771 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4773 * The following functions allocate and free a vmcs02 in this pool.
4776 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4777 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
4779 struct vmcs02_list
*item
;
4780 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4781 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
4782 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4783 return &item
->vmcs02
;
4786 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
4787 /* Recycle the least recently used VMCS. */
4788 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
4789 struct vmcs02_list
, list
);
4790 item
->vmptr
= vmx
->nested
.current_vmptr
;
4791 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
4792 return &item
->vmcs02
;
4795 /* Create a new VMCS */
4796 item
= (struct vmcs02_list
*)
4797 kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
4800 item
->vmcs02
.vmcs
= alloc_vmcs();
4801 if (!item
->vmcs02
.vmcs
) {
4805 loaded_vmcs_init(&item
->vmcs02
);
4806 item
->vmptr
= vmx
->nested
.current_vmptr
;
4807 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
4808 vmx
->nested
.vmcs02_num
++;
4809 return &item
->vmcs02
;
4812 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4813 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
4815 struct vmcs02_list
*item
;
4816 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
4817 if (item
->vmptr
== vmptr
) {
4818 free_loaded_vmcs(&item
->vmcs02
);
4819 list_del(&item
->list
);
4821 vmx
->nested
.vmcs02_num
--;
4827 * Free all VMCSs saved for this vcpu, except the one pointed by
4828 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4829 * currently used, if running L2), and vmcs01 when running L2.
4831 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
4833 struct vmcs02_list
*item
, *n
;
4834 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
4835 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
4836 free_loaded_vmcs(&item
->vmcs02
);
4837 list_del(&item
->list
);
4840 vmx
->nested
.vmcs02_num
= 0;
4842 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
4843 free_loaded_vmcs(&vmx
->vmcs01
);
4847 * Emulate the VMXON instruction.
4848 * Currently, we just remember that VMX is active, and do not save or even
4849 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4850 * do not currently need to store anything in that guest-allocated memory
4851 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4852 * argument is different from the VMXON pointer (which the spec says they do).
4854 static int handle_vmon(struct kvm_vcpu
*vcpu
)
4856 struct kvm_segment cs
;
4857 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4859 /* The Intel VMX Instruction Reference lists a bunch of bits that
4860 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4861 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4862 * Otherwise, we should fail with #UD. We test these now:
4864 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
4865 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
4866 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4867 kvm_queue_exception(vcpu
, UD_VECTOR
);
4871 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4872 if (is_long_mode(vcpu
) && !cs
.l
) {
4873 kvm_queue_exception(vcpu
, UD_VECTOR
);
4877 if (vmx_get_cpl(vcpu
)) {
4878 kvm_inject_gp(vcpu
, 0);
4882 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
4883 vmx
->nested
.vmcs02_num
= 0;
4885 vmx
->nested
.vmxon
= true;
4887 skip_emulated_instruction(vcpu
);
4892 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4893 * for running VMX instructions (except VMXON, whose prerequisites are
4894 * slightly different). It also specifies what exception to inject otherwise.
4896 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
4898 struct kvm_segment cs
;
4899 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4901 if (!vmx
->nested
.vmxon
) {
4902 kvm_queue_exception(vcpu
, UD_VECTOR
);
4906 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4907 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
4908 (is_long_mode(vcpu
) && !cs
.l
)) {
4909 kvm_queue_exception(vcpu
, UD_VECTOR
);
4913 if (vmx_get_cpl(vcpu
)) {
4914 kvm_inject_gp(vcpu
, 0);
4922 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4923 * just stops using VMX.
4925 static void free_nested(struct vcpu_vmx
*vmx
)
4927 if (!vmx
->nested
.vmxon
)
4929 vmx
->nested
.vmxon
= false;
4930 if (vmx
->nested
.current_vmptr
!= -1ull) {
4931 kunmap(vmx
->nested
.current_vmcs12_page
);
4932 nested_release_page(vmx
->nested
.current_vmcs12_page
);
4933 vmx
->nested
.current_vmptr
= -1ull;
4934 vmx
->nested
.current_vmcs12
= NULL
;
4936 /* Unpin physical memory we referred to in current vmcs02 */
4937 if (vmx
->nested
.apic_access_page
) {
4938 nested_release_page(vmx
->nested
.apic_access_page
);
4939 vmx
->nested
.apic_access_page
= 0;
4942 nested_free_all_saved_vmcss(vmx
);
4945 /* Emulate the VMXOFF instruction */
4946 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
4948 if (!nested_vmx_check_permission(vcpu
))
4950 free_nested(to_vmx(vcpu
));
4951 skip_emulated_instruction(vcpu
);
4956 * Decode the memory-address operand of a vmx instruction, as recorded on an
4957 * exit caused by such an instruction (run by a guest hypervisor).
4958 * On success, returns 0. When the operand is invalid, returns 1 and throws
4961 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
4962 unsigned long exit_qualification
,
4963 u32 vmx_instruction_info
, gva_t
*ret
)
4966 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4967 * Execution", on an exit, vmx_instruction_info holds most of the
4968 * addressing components of the operand. Only the displacement part
4969 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4970 * For how an actual address is calculated from all these components,
4971 * refer to Vol. 1, "Operand Addressing".
4973 int scaling
= vmx_instruction_info
& 3;
4974 int addr_size
= (vmx_instruction_info
>> 7) & 7;
4975 bool is_reg
= vmx_instruction_info
& (1u << 10);
4976 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
4977 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
4978 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
4979 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
4980 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
4983 kvm_queue_exception(vcpu
, UD_VECTOR
);
4987 /* Addr = segment_base + offset */
4988 /* offset = base + [index * scale] + displacement */
4989 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
4991 *ret
+= kvm_register_read(vcpu
, base_reg
);
4993 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
4994 *ret
+= exit_qualification
; /* holds the displacement */
4996 if (addr_size
== 1) /* 32 bit */
5000 * TODO: throw #GP (and return 1) in various cases that the VM*
5001 * instructions require it - e.g., offset beyond segment limit,
5002 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5003 * address, and so on. Currently these are not checked.
5009 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5010 * set the success or error code of an emulated VMX instruction, as specified
5011 * by Vol 2B, VMX Instruction Reference, "Conventions".
5013 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5015 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5016 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5017 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5020 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5022 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5023 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5024 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5028 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5029 u32 vm_instruction_error
)
5031 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5033 * failValid writes the error number to the current VMCS, which
5034 * can't be done there isn't a current VMCS.
5036 nested_vmx_failInvalid(vcpu
);
5039 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5040 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5041 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5043 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5046 /* Emulate the VMCLEAR instruction */
5047 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
5049 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5052 struct vmcs12
*vmcs12
;
5054 struct x86_exception e
;
5056 if (!nested_vmx_check_permission(vcpu
))
5059 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5060 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5063 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5064 sizeof(vmptr
), &e
)) {
5065 kvm_inject_page_fault(vcpu
, &e
);
5069 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5070 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
5071 skip_emulated_instruction(vcpu
);
5075 if (vmptr
== vmx
->nested
.current_vmptr
) {
5076 kunmap(vmx
->nested
.current_vmcs12_page
);
5077 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5078 vmx
->nested
.current_vmptr
= -1ull;
5079 vmx
->nested
.current_vmcs12
= NULL
;
5082 page
= nested_get_page(vcpu
, vmptr
);
5085 * For accurate processor emulation, VMCLEAR beyond available
5086 * physical memory should do nothing at all. However, it is
5087 * possible that a nested vmx bug, not a guest hypervisor bug,
5088 * resulted in this case, so let's shut down before doing any
5091 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5094 vmcs12
= kmap(page
);
5095 vmcs12
->launch_state
= 0;
5097 nested_release_page(page
);
5099 nested_free_vmcs02(vmx
, vmptr
);
5101 skip_emulated_instruction(vcpu
);
5102 nested_vmx_succeed(vcpu
);
5106 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
5108 /* Emulate the VMLAUNCH instruction */
5109 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
5111 return nested_vmx_run(vcpu
, true);
5114 /* Emulate the VMRESUME instruction */
5115 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
5118 return nested_vmx_run(vcpu
, false);
5121 enum vmcs_field_type
{
5122 VMCS_FIELD_TYPE_U16
= 0,
5123 VMCS_FIELD_TYPE_U64
= 1,
5124 VMCS_FIELD_TYPE_U32
= 2,
5125 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
5128 static inline int vmcs_field_type(unsigned long field
)
5130 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
5131 return VMCS_FIELD_TYPE_U32
;
5132 return (field
>> 13) & 0x3 ;
5135 static inline int vmcs_field_readonly(unsigned long field
)
5137 return (((field
>> 10) & 0x3) == 1);
5141 * Read a vmcs12 field. Since these can have varying lengths and we return
5142 * one type, we chose the biggest type (u64) and zero-extend the return value
5143 * to that size. Note that the caller, handle_vmread, might need to use only
5144 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5145 * 64-bit fields are to be returned).
5147 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
5148 unsigned long field
, u64
*ret
)
5150 short offset
= vmcs_field_to_offset(field
);
5156 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
5158 switch (vmcs_field_type(field
)) {
5159 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5160 *ret
= *((natural_width
*)p
);
5162 case VMCS_FIELD_TYPE_U16
:
5165 case VMCS_FIELD_TYPE_U32
:
5168 case VMCS_FIELD_TYPE_U64
:
5172 return 0; /* can never happen. */
5177 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5178 * used before) all generate the same failure when it is missing.
5180 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
5182 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5183 if (vmx
->nested
.current_vmptr
== -1ull) {
5184 nested_vmx_failInvalid(vcpu
);
5185 skip_emulated_instruction(vcpu
);
5191 static int handle_vmread(struct kvm_vcpu
*vcpu
)
5193 unsigned long field
;
5195 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5196 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5199 if (!nested_vmx_check_permission(vcpu
) ||
5200 !nested_vmx_check_vmcs12(vcpu
))
5203 /* Decode instruction info and find the field to read */
5204 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5205 /* Read the field, zero-extended to a u64 field_value */
5206 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
5207 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5208 skip_emulated_instruction(vcpu
);
5212 * Now copy part of this value to register or memory, as requested.
5213 * Note that the number of bits actually copied is 32 or 64 depending
5214 * on the guest's mode (32 or 64 bit), not on the given field's length.
5216 if (vmx_instruction_info
& (1u << 10)) {
5217 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
5220 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5221 vmx_instruction_info
, &gva
))
5223 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5224 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
5225 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
5228 nested_vmx_succeed(vcpu
);
5229 skip_emulated_instruction(vcpu
);
5234 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
5236 unsigned long field
;
5238 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5239 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5242 /* The value to write might be 32 or 64 bits, depending on L1's long
5243 * mode, and eventually we need to write that into a field of several
5244 * possible lengths. The code below first zero-extends the value to 64
5245 * bit (field_value), and then copies only the approriate number of
5246 * bits into the vmcs12 field.
5248 u64 field_value
= 0;
5249 struct x86_exception e
;
5251 if (!nested_vmx_check_permission(vcpu
) ||
5252 !nested_vmx_check_vmcs12(vcpu
))
5255 if (vmx_instruction_info
& (1u << 10))
5256 field_value
= kvm_register_read(vcpu
,
5257 (((vmx_instruction_info
) >> 3) & 0xf));
5259 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5260 vmx_instruction_info
, &gva
))
5262 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
5263 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
5264 kvm_inject_page_fault(vcpu
, &e
);
5270 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
5271 if (vmcs_field_readonly(field
)) {
5272 nested_vmx_failValid(vcpu
,
5273 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
5274 skip_emulated_instruction(vcpu
);
5278 offset
= vmcs_field_to_offset(field
);
5280 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5281 skip_emulated_instruction(vcpu
);
5284 p
= ((char *) get_vmcs12(vcpu
)) + offset
;
5286 switch (vmcs_field_type(field
)) {
5287 case VMCS_FIELD_TYPE_U16
:
5288 *(u16
*)p
= field_value
;
5290 case VMCS_FIELD_TYPE_U32
:
5291 *(u32
*)p
= field_value
;
5293 case VMCS_FIELD_TYPE_U64
:
5294 *(u64
*)p
= field_value
;
5296 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
5297 *(natural_width
*)p
= field_value
;
5300 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
5301 skip_emulated_instruction(vcpu
);
5305 nested_vmx_succeed(vcpu
);
5306 skip_emulated_instruction(vcpu
);
5310 /* Emulate the VMPTRLD instruction */
5311 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
5313 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5316 struct x86_exception e
;
5318 if (!nested_vmx_check_permission(vcpu
))
5321 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5322 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5325 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5326 sizeof(vmptr
), &e
)) {
5327 kvm_inject_page_fault(vcpu
, &e
);
5331 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
)) {
5332 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
5333 skip_emulated_instruction(vcpu
);
5337 if (vmx
->nested
.current_vmptr
!= vmptr
) {
5338 struct vmcs12
*new_vmcs12
;
5340 page
= nested_get_page(vcpu
, vmptr
);
5342 nested_vmx_failInvalid(vcpu
);
5343 skip_emulated_instruction(vcpu
);
5346 new_vmcs12
= kmap(page
);
5347 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
5349 nested_release_page_clean(page
);
5350 nested_vmx_failValid(vcpu
,
5351 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
5352 skip_emulated_instruction(vcpu
);
5355 if (vmx
->nested
.current_vmptr
!= -1ull) {
5356 kunmap(vmx
->nested
.current_vmcs12_page
);
5357 nested_release_page(vmx
->nested
.current_vmcs12_page
);
5360 vmx
->nested
.current_vmptr
= vmptr
;
5361 vmx
->nested
.current_vmcs12
= new_vmcs12
;
5362 vmx
->nested
.current_vmcs12_page
= page
;
5365 nested_vmx_succeed(vcpu
);
5366 skip_emulated_instruction(vcpu
);
5370 /* Emulate the VMPTRST instruction */
5371 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
5373 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5374 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
5376 struct x86_exception e
;
5378 if (!nested_vmx_check_permission(vcpu
))
5381 if (get_vmx_mem_address(vcpu
, exit_qualification
,
5382 vmx_instruction_info
, &vmcs_gva
))
5384 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5385 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
5386 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
5388 kvm_inject_page_fault(vcpu
, &e
);
5391 nested_vmx_succeed(vcpu
);
5392 skip_emulated_instruction(vcpu
);
5397 * The exit handlers return 1 if the exit was handled fully and guest execution
5398 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5399 * to be done to userspace and return 0.
5401 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
5402 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
5403 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
5404 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
5405 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
5406 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
5407 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
5408 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
5409 [EXIT_REASON_CPUID
] = handle_cpuid
,
5410 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
5411 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
5412 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
5413 [EXIT_REASON_HLT
] = handle_halt
,
5414 [EXIT_REASON_INVD
] = handle_invd
,
5415 [EXIT_REASON_INVLPG
] = handle_invlpg
,
5416 [EXIT_REASON_VMCALL
] = handle_vmcall
,
5417 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
5418 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
5419 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
5420 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
5421 [EXIT_REASON_VMREAD
] = handle_vmread
,
5422 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
5423 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
5424 [EXIT_REASON_VMOFF
] = handle_vmoff
,
5425 [EXIT_REASON_VMON
] = handle_vmon
,
5426 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
5427 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
5428 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
5429 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
5430 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
5431 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
5432 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
5433 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
5434 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
5435 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
5436 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
5439 static const int kvm_vmx_max_exit_handlers
=
5440 ARRAY_SIZE(kvm_vmx_exit_handlers
);
5443 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5444 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5445 * disinterest in the current event (read or write a specific MSR) by using an
5446 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5448 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
5449 struct vmcs12
*vmcs12
, u32 exit_reason
)
5451 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5454 if (!nested_cpu_has(get_vmcs12(vcpu
), CPU_BASED_USE_MSR_BITMAPS
))
5458 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5459 * for the four combinations of read/write and low/high MSR numbers.
5460 * First we need to figure out which of the four to use:
5462 bitmap
= vmcs12
->msr_bitmap
;
5463 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
5465 if (msr_index
>= 0xc0000000) {
5466 msr_index
-= 0xc0000000;
5470 /* Then read the msr_index'th bit from this bitmap: */
5471 if (msr_index
< 1024*8) {
5473 kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1);
5474 return 1 & (b
>> (msr_index
& 7));
5476 return 1; /* let L1 handle the wrong parameter */
5480 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5481 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5482 * intercept (via guest_host_mask etc.) the current event.
5484 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
5485 struct vmcs12
*vmcs12
)
5487 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5488 int cr
= exit_qualification
& 15;
5489 int reg
= (exit_qualification
>> 8) & 15;
5490 unsigned long val
= kvm_register_read(vcpu
, reg
);
5492 switch ((exit_qualification
>> 4) & 3) {
5493 case 0: /* mov to cr */
5496 if (vmcs12
->cr0_guest_host_mask
&
5497 (val
^ vmcs12
->cr0_read_shadow
))
5501 if ((vmcs12
->cr3_target_count
>= 1 &&
5502 vmcs12
->cr3_target_value0
== val
) ||
5503 (vmcs12
->cr3_target_count
>= 2 &&
5504 vmcs12
->cr3_target_value1
== val
) ||
5505 (vmcs12
->cr3_target_count
>= 3 &&
5506 vmcs12
->cr3_target_value2
== val
) ||
5507 (vmcs12
->cr3_target_count
>= 4 &&
5508 vmcs12
->cr3_target_value3
== val
))
5510 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
5514 if (vmcs12
->cr4_guest_host_mask
&
5515 (vmcs12
->cr4_read_shadow
^ val
))
5519 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
5525 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
5526 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
5529 case 1: /* mov from cr */
5532 if (vmcs12
->cpu_based_vm_exec_control
&
5533 CPU_BASED_CR3_STORE_EXITING
)
5537 if (vmcs12
->cpu_based_vm_exec_control
&
5538 CPU_BASED_CR8_STORE_EXITING
)
5545 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5546 * cr0. Other attempted changes are ignored, with no exit.
5548 if (vmcs12
->cr0_guest_host_mask
& 0xe &
5549 (val
^ vmcs12
->cr0_read_shadow
))
5551 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
5552 !(vmcs12
->cr0_read_shadow
& 0x1) &&
5561 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5562 * should handle it ourselves in L0 (and then continue L2). Only call this
5563 * when in is_guest_mode (L2).
5565 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
5567 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
5568 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5569 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5570 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5572 if (vmx
->nested
.nested_run_pending
)
5575 if (unlikely(vmx
->fail
)) {
5576 printk(KERN_INFO
"%s failed vm entry %x\n",
5577 __func__
, vmcs_read32(VM_INSTRUCTION_ERROR
));
5581 switch (exit_reason
) {
5582 case EXIT_REASON_EXCEPTION_NMI
:
5583 if (!is_exception(intr_info
))
5585 else if (is_page_fault(intr_info
))
5587 return vmcs12
->exception_bitmap
&
5588 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
5589 case EXIT_REASON_EXTERNAL_INTERRUPT
:
5591 case EXIT_REASON_TRIPLE_FAULT
:
5593 case EXIT_REASON_PENDING_INTERRUPT
:
5594 case EXIT_REASON_NMI_WINDOW
:
5596 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5597 * (aka Interrupt Window Exiting) only when L1 turned it on,
5598 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5599 * Same for NMI Window Exiting.
5602 case EXIT_REASON_TASK_SWITCH
:
5604 case EXIT_REASON_CPUID
:
5606 case EXIT_REASON_HLT
:
5607 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
5608 case EXIT_REASON_INVD
:
5610 case EXIT_REASON_INVLPG
:
5611 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
5612 case EXIT_REASON_RDPMC
:
5613 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
5614 case EXIT_REASON_RDTSC
:
5615 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
5616 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
5617 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
5618 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
5619 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
5620 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
5622 * VMX instructions trap unconditionally. This allows L1 to
5623 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5626 case EXIT_REASON_CR_ACCESS
:
5627 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
5628 case EXIT_REASON_DR_ACCESS
:
5629 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
5630 case EXIT_REASON_IO_INSTRUCTION
:
5631 /* TODO: support IO bitmaps */
5633 case EXIT_REASON_MSR_READ
:
5634 case EXIT_REASON_MSR_WRITE
:
5635 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
5636 case EXIT_REASON_INVALID_STATE
:
5638 case EXIT_REASON_MWAIT_INSTRUCTION
:
5639 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
5640 case EXIT_REASON_MONITOR_INSTRUCTION
:
5641 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
5642 case EXIT_REASON_PAUSE_INSTRUCTION
:
5643 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
5644 nested_cpu_has2(vmcs12
,
5645 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
5646 case EXIT_REASON_MCE_DURING_VMENTRY
:
5648 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
5650 case EXIT_REASON_APIC_ACCESS
:
5651 return nested_cpu_has2(vmcs12
,
5652 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
5653 case EXIT_REASON_EPT_VIOLATION
:
5654 case EXIT_REASON_EPT_MISCONFIG
:
5656 case EXIT_REASON_WBINVD
:
5657 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
5658 case EXIT_REASON_XSETBV
:
5665 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
5667 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
5668 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
5672 * The guest has exited. See if we can fix it or if we need userspace
5675 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
5677 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5678 u32 exit_reason
= vmx
->exit_reason
;
5679 u32 vectoring_info
= vmx
->idt_vectoring_info
;
5681 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
5683 /* If guest state is invalid, start emulating */
5684 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5685 return handle_invalid_guest_state(vcpu
);
5688 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5689 * we did not inject a still-pending event to L1 now because of
5690 * nested_run_pending, we need to re-enable this bit.
5692 if (vmx
->nested
.nested_run_pending
)
5693 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5695 if (exit_reason
== EXIT_REASON_VMLAUNCH
||
5696 exit_reason
== EXIT_REASON_VMRESUME
)
5697 vmx
->nested
.nested_run_pending
= 1;
5699 vmx
->nested
.nested_run_pending
= 0;
5701 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
5702 nested_vmx_vmexit(vcpu
);
5706 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
5707 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5708 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5713 if (unlikely(vmx
->fail
)) {
5714 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
5715 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
5716 = vmcs_read32(VM_INSTRUCTION_ERROR
);
5720 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5721 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
5722 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
5723 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
5724 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
5725 "(0x%x) and exit reason is 0x%x\n",
5726 __func__
, vectoring_info
, exit_reason
);
5728 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
5729 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
5730 get_vmcs12(vcpu
), vcpu
)))) {
5731 if (vmx_interrupt_allowed(vcpu
)) {
5732 vmx
->soft_vnmi_blocked
= 0;
5733 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
5734 vcpu
->arch
.nmi_pending
) {
5736 * This CPU don't support us in finding the end of an
5737 * NMI-blocked window if the guest runs with IRQs
5738 * disabled. So we pull the trigger after 1 s of
5739 * futile waiting, but inform the user about this.
5741 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
5742 "state on VCPU %d after 1 s timeout\n",
5743 __func__
, vcpu
->vcpu_id
);
5744 vmx
->soft_vnmi_blocked
= 0;
5748 if (exit_reason
< kvm_vmx_max_exit_handlers
5749 && kvm_vmx_exit_handlers
[exit_reason
])
5750 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
5752 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5753 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
5758 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
5760 if (irr
== -1 || tpr
< irr
) {
5761 vmcs_write32(TPR_THRESHOLD
, 0);
5765 vmcs_write32(TPR_THRESHOLD
, irr
);
5768 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
5772 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
5773 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
5776 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5777 exit_intr_info
= vmx
->exit_intr_info
;
5779 /* Handle machine checks before interrupts are enabled */
5780 if (is_machine_check(exit_intr_info
))
5781 kvm_machine_check();
5783 /* We need to handle NMIs before interrupts are enabled */
5784 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
5785 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
5786 kvm_before_handle_nmi(&vmx
->vcpu
);
5788 kvm_after_handle_nmi(&vmx
->vcpu
);
5792 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
5797 bool idtv_info_valid
;
5799 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5801 if (cpu_has_virtual_nmis()) {
5802 if (vmx
->nmi_known_unmasked
)
5805 * Can't use vmx->exit_intr_info since we're not sure what
5806 * the exit reason is.
5808 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
5809 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
5810 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
5812 * SDM 3: 27.7.1.2 (September 2008)
5813 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5814 * a guest IRET fault.
5815 * SDM 3: 23.2.2 (September 2008)
5816 * Bit 12 is undefined in any of the following cases:
5817 * If the VM exit sets the valid bit in the IDT-vectoring
5818 * information field.
5819 * If the VM exit is due to a double fault.
5821 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
5822 vector
!= DF_VECTOR
&& !idtv_info_valid
)
5823 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5824 GUEST_INTR_STATE_NMI
);
5826 vmx
->nmi_known_unmasked
=
5827 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
5828 & GUEST_INTR_STATE_NMI
);
5829 } else if (unlikely(vmx
->soft_vnmi_blocked
))
5830 vmx
->vnmi_blocked_time
+=
5831 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
5834 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
5835 u32 idt_vectoring_info
,
5836 int instr_len_field
,
5837 int error_code_field
)
5841 bool idtv_info_valid
;
5843 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
5845 vmx
->vcpu
.arch
.nmi_injected
= false;
5846 kvm_clear_exception_queue(&vmx
->vcpu
);
5847 kvm_clear_interrupt_queue(&vmx
->vcpu
);
5849 if (!idtv_info_valid
)
5852 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5854 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
5855 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
5858 case INTR_TYPE_NMI_INTR
:
5859 vmx
->vcpu
.arch
.nmi_injected
= true;
5861 * SDM 3: 27.7.1.2 (September 2008)
5862 * Clear bit "block by NMI" before VM entry if a NMI
5865 vmx_set_nmi_mask(&vmx
->vcpu
, false);
5867 case INTR_TYPE_SOFT_EXCEPTION
:
5868 vmx
->vcpu
.arch
.event_exit_inst_len
=
5869 vmcs_read32(instr_len_field
);
5871 case INTR_TYPE_HARD_EXCEPTION
:
5872 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
5873 u32 err
= vmcs_read32(error_code_field
);
5874 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
5876 kvm_queue_exception(&vmx
->vcpu
, vector
);
5878 case INTR_TYPE_SOFT_INTR
:
5879 vmx
->vcpu
.arch
.event_exit_inst_len
=
5880 vmcs_read32(instr_len_field
);
5882 case INTR_TYPE_EXT_INTR
:
5883 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
5884 type
== INTR_TYPE_SOFT_INTR
);
5891 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
5893 if (is_guest_mode(&vmx
->vcpu
))
5895 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
5896 VM_EXIT_INSTRUCTION_LEN
,
5897 IDT_VECTORING_ERROR_CODE
);
5900 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
5902 if (is_guest_mode(vcpu
))
5904 __vmx_complete_interrupts(to_vmx(vcpu
),
5905 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
5906 VM_ENTRY_INSTRUCTION_LEN
,
5907 VM_ENTRY_EXCEPTION_ERROR_CODE
);
5909 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
5912 #ifdef CONFIG_X86_64
5920 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
5922 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5924 if (is_guest_mode(vcpu
) && !vmx
->nested
.nested_run_pending
) {
5925 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5926 if (vmcs12
->idt_vectoring_info_field
&
5927 VECTORING_INFO_VALID_MASK
) {
5928 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5929 vmcs12
->idt_vectoring_info_field
);
5930 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5931 vmcs12
->vm_exit_instruction_len
);
5932 if (vmcs12
->idt_vectoring_info_field
&
5933 VECTORING_INFO_DELIVER_CODE_MASK
)
5934 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
5935 vmcs12
->idt_vectoring_error_code
);
5939 /* Record the guest's net vcpu time for enforced NMI injections. */
5940 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
5941 vmx
->entry_time
= ktime_get();
5943 /* Don't enter VMX if guest state is invalid, let the exit handler
5944 start emulation until we arrive back to a valid state */
5945 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
5948 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
5949 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
5950 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
5951 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
5953 /* When single-stepping over STI and MOV SS, we must clear the
5954 * corresponding interruptibility bits in the guest state. Otherwise
5955 * vmentry fails as it then expects bit 14 (BS) in pending debug
5956 * exceptions being set, but that's not correct for the guest debugging
5958 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
5959 vmx_set_interrupt_shadow(vcpu
, 0);
5961 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
5963 /* Store host registers */
5964 "push %%"R
"dx; push %%"R
"bp;"
5965 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
5967 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
5969 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
5970 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
5972 /* Reload cr2 if changed */
5973 "mov %c[cr2](%0), %%"R
"ax \n\t"
5974 "mov %%cr2, %%"R
"dx \n\t"
5975 "cmp %%"R
"ax, %%"R
"dx \n\t"
5977 "mov %%"R
"ax, %%cr2 \n\t"
5979 /* Check if vmlaunch of vmresume is needed */
5980 "cmpl $0, %c[launched](%0) \n\t"
5981 /* Load guest registers. Don't clobber flags. */
5982 "mov %c[rax](%0), %%"R
"ax \n\t"
5983 "mov %c[rbx](%0), %%"R
"bx \n\t"
5984 "mov %c[rdx](%0), %%"R
"dx \n\t"
5985 "mov %c[rsi](%0), %%"R
"si \n\t"
5986 "mov %c[rdi](%0), %%"R
"di \n\t"
5987 "mov %c[rbp](%0), %%"R
"bp \n\t"
5988 #ifdef CONFIG_X86_64
5989 "mov %c[r8](%0), %%r8 \n\t"
5990 "mov %c[r9](%0), %%r9 \n\t"
5991 "mov %c[r10](%0), %%r10 \n\t"
5992 "mov %c[r11](%0), %%r11 \n\t"
5993 "mov %c[r12](%0), %%r12 \n\t"
5994 "mov %c[r13](%0), %%r13 \n\t"
5995 "mov %c[r14](%0), %%r14 \n\t"
5996 "mov %c[r15](%0), %%r15 \n\t"
5998 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
6000 /* Enter guest mode */
6001 "jne .Llaunched \n\t"
6002 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
6003 "jmp .Lkvm_vmx_return \n\t"
6004 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
6005 ".Lkvm_vmx_return: "
6006 /* Save guest registers, load host registers, keep flags */
6007 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
6009 "mov %%"R
"ax, %c[rax](%0) \n\t"
6010 "mov %%"R
"bx, %c[rbx](%0) \n\t"
6011 "pop"Q
" %c[rcx](%0) \n\t"
6012 "mov %%"R
"dx, %c[rdx](%0) \n\t"
6013 "mov %%"R
"si, %c[rsi](%0) \n\t"
6014 "mov %%"R
"di, %c[rdi](%0) \n\t"
6015 "mov %%"R
"bp, %c[rbp](%0) \n\t"
6016 #ifdef CONFIG_X86_64
6017 "mov %%r8, %c[r8](%0) \n\t"
6018 "mov %%r9, %c[r9](%0) \n\t"
6019 "mov %%r10, %c[r10](%0) \n\t"
6020 "mov %%r11, %c[r11](%0) \n\t"
6021 "mov %%r12, %c[r12](%0) \n\t"
6022 "mov %%r13, %c[r13](%0) \n\t"
6023 "mov %%r14, %c[r14](%0) \n\t"
6024 "mov %%r15, %c[r15](%0) \n\t"
6026 "mov %%cr2, %%"R
"ax \n\t"
6027 "mov %%"R
"ax, %c[cr2](%0) \n\t"
6029 "pop %%"R
"bp; pop %%"R
"dx \n\t"
6030 "setbe %c[fail](%0) \n\t"
6031 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
6032 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
6033 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
6034 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
6035 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
6036 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
6037 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
6038 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
6039 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
6040 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
6041 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
6042 #ifdef CONFIG_X86_64
6043 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
6044 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
6045 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
6046 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
6047 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
6048 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
6049 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
6050 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
6052 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
6053 [wordsize
]"i"(sizeof(ulong
))
6055 , R
"ax", R
"bx", R
"di", R
"si"
6056 #ifdef CONFIG_X86_64
6057 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6061 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
6062 | (1 << VCPU_EXREG_RFLAGS
)
6063 | (1 << VCPU_EXREG_CPL
)
6064 | (1 << VCPU_EXREG_PDPTR
)
6065 | (1 << VCPU_EXREG_SEGMENTS
)
6066 | (1 << VCPU_EXREG_CR3
));
6067 vcpu
->arch
.regs_dirty
= 0;
6069 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6071 if (is_guest_mode(vcpu
)) {
6072 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6073 vmcs12
->idt_vectoring_info_field
= vmx
->idt_vectoring_info
;
6074 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
6075 vmcs12
->idt_vectoring_error_code
=
6076 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6077 vmcs12
->vm_exit_instruction_len
=
6078 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6082 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
6083 vmx
->loaded_vmcs
->launched
= 1;
6085 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6087 vmx_complete_atomic_exit(vmx
);
6088 vmx_recover_nmi_blocking(vmx
);
6089 vmx_complete_interrupts(vmx
);
6095 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
6097 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6101 free_loaded_vmcs(vmx
->loaded_vmcs
);
6102 kfree(vmx
->guest_msrs
);
6103 kvm_vcpu_uninit(vcpu
);
6104 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6107 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
6110 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
6114 return ERR_PTR(-ENOMEM
);
6118 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
6122 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
6124 if (!vmx
->guest_msrs
) {
6128 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6129 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
6130 if (!vmx
->loaded_vmcs
->vmcs
)
6133 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
6134 loaded_vmcs_init(vmx
->loaded_vmcs
);
6139 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
6140 vmx
->vcpu
.cpu
= cpu
;
6141 err
= vmx_vcpu_setup(vmx
);
6142 vmx_vcpu_put(&vmx
->vcpu
);
6146 if (vm_need_virtualize_apic_accesses(kvm
))
6147 err
= alloc_apic_access_page(kvm
);
6152 if (!kvm
->arch
.ept_identity_map_addr
)
6153 kvm
->arch
.ept_identity_map_addr
=
6154 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
6156 if (alloc_identity_pagetable(kvm
) != 0)
6158 if (!init_rmode_identity_map(kvm
))
6162 vmx
->nested
.current_vmptr
= -1ull;
6163 vmx
->nested
.current_vmcs12
= NULL
;
6168 free_vmcs(vmx
->loaded_vmcs
->vmcs
);
6170 kfree(vmx
->guest_msrs
);
6172 kvm_vcpu_uninit(&vmx
->vcpu
);
6175 kmem_cache_free(kvm_vcpu_cache
, vmx
);
6176 return ERR_PTR(err
);
6179 static void __init
vmx_check_processor_compat(void *rtn
)
6181 struct vmcs_config vmcs_conf
;
6184 if (setup_vmcs_config(&vmcs_conf
) < 0)
6186 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
6187 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
6188 smp_processor_id());
6193 static int get_ept_level(void)
6195 return VMX_EPT_DEFAULT_GAW
+ 1;
6198 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
6202 /* For VT-d and EPT combination
6203 * 1. MMIO: always map as UC
6205 * a. VT-d without snooping control feature: can't guarantee the
6206 * result, try to trust guest.
6207 * b. VT-d with snooping control feature: snooping control feature of
6208 * VT-d engine can guarantee the cache correctness. Just set it
6209 * to WB to keep consistent with host. So the same as item 3.
6210 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6211 * consistent with host MTRR
6214 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
6215 else if (vcpu
->kvm
->arch
.iommu_domain
&&
6216 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
6217 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
6218 VMX_EPT_MT_EPTE_SHIFT
;
6220 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
6226 #define _ER(x) { EXIT_REASON_##x, #x }
6228 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
6230 _ER(EXTERNAL_INTERRUPT
),
6232 _ER(PENDING_INTERRUPT
),
6252 _ER(IO_INSTRUCTION
),
6255 _ER(MWAIT_INSTRUCTION
),
6256 _ER(MONITOR_INSTRUCTION
),
6257 _ER(PAUSE_INSTRUCTION
),
6258 _ER(MCE_DURING_VMENTRY
),
6259 _ER(TPR_BELOW_THRESHOLD
),
6269 static int vmx_get_lpage_level(void)
6271 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
6272 return PT_DIRECTORY_LEVEL
;
6274 /* For shadow and EPT supported 1GB page */
6275 return PT_PDPE_LEVEL
;
6278 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
6280 struct kvm_cpuid_entry2
*best
;
6281 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6284 vmx
->rdtscp_enabled
= false;
6285 if (vmx_rdtscp_supported()) {
6286 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6287 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
6288 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
6289 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
6290 vmx
->rdtscp_enabled
= true;
6292 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6293 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
6300 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
6305 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6306 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6307 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6308 * guest in a way that will both be appropriate to L1's requests, and our
6309 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6310 * function also has additional necessary side-effects, like setting various
6311 * vcpu->arch fields.
6313 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6315 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6318 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
6319 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
6320 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
6321 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
6322 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
6323 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
6324 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
6325 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
6326 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
6327 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
6328 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
6329 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
6330 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
6331 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
6332 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
6333 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
6334 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
6335 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
6336 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
6337 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
6338 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
6339 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
6340 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
6341 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
6342 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
6343 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
6344 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
6345 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
6346 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
6347 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
6348 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
6349 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
6350 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
6351 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
6352 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
6353 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
6355 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
6356 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
6357 vmcs12
->vm_entry_intr_info_field
);
6358 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
6359 vmcs12
->vm_entry_exception_error_code
);
6360 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
6361 vmcs12
->vm_entry_instruction_len
);
6362 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
6363 vmcs12
->guest_interruptibility_info
);
6364 vmcs_write32(GUEST_ACTIVITY_STATE
, vmcs12
->guest_activity_state
);
6365 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
6366 vmcs_writel(GUEST_DR7
, vmcs12
->guest_dr7
);
6367 vmcs_writel(GUEST_RFLAGS
, vmcs12
->guest_rflags
);
6368 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
6369 vmcs12
->guest_pending_dbg_exceptions
);
6370 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
6371 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
6373 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6375 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
6376 (vmcs_config
.pin_based_exec_ctrl
|
6377 vmcs12
->pin_based_vm_exec_control
));
6380 * Whether page-faults are trapped is determined by a combination of
6381 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6382 * If enable_ept, L0 doesn't care about page faults and we should
6383 * set all of these to L1's desires. However, if !enable_ept, L0 does
6384 * care about (at least some) page faults, and because it is not easy
6385 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6386 * to exit on each and every L2 page fault. This is done by setting
6387 * MASK=MATCH=0 and (see below) EB.PF=1.
6388 * Note that below we don't need special code to set EB.PF beyond the
6389 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6390 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6391 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6393 * A problem with this approach (when !enable_ept) is that L1 may be
6394 * injected with more page faults than it asked for. This could have
6395 * caused problems, but in practice existing hypervisors don't care.
6396 * To fix this, we will need to emulate the PFEC checking (on the L1
6397 * page tables), using walk_addr(), when injecting PFs to L1.
6399 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
6400 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
6401 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
6402 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
6404 if (cpu_has_secondary_exec_ctrls()) {
6405 u32 exec_control
= vmx_secondary_exec_control(vmx
);
6406 if (!vmx
->rdtscp_enabled
)
6407 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
6408 /* Take the following fields only from vmcs12 */
6409 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6410 if (nested_cpu_has(vmcs12
,
6411 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
6412 exec_control
|= vmcs12
->secondary_vm_exec_control
;
6414 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
6416 * Translate L1 physical address to host physical
6417 * address for vmcs02. Keep the page pinned, so this
6418 * physical address remains valid. We keep a reference
6419 * to it so we can release it later.
6421 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
6422 nested_release_page(vmx
->nested
.apic_access_page
);
6423 vmx
->nested
.apic_access_page
=
6424 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
6426 * If translation failed, no matter: This feature asks
6427 * to exit when accessing the given address, and if it
6428 * can never be accessed, this feature won't do
6431 if (!vmx
->nested
.apic_access_page
)
6433 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
6435 vmcs_write64(APIC_ACCESS_ADDR
,
6436 page_to_phys(vmx
->nested
.apic_access_page
));
6439 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6444 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6445 * Some constant fields are set here by vmx_set_constant_host_state().
6446 * Other fields are different per CPU, and will be set later when
6447 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6449 vmx_set_constant_host_state();
6452 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6453 * entry, but only if the current (host) sp changed from the value
6454 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6455 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6456 * here we just force the write to happen on entry.
6460 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
6461 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
6462 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6463 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
6464 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
6466 * Merging of IO and MSR bitmaps not currently supported.
6467 * Rather, exit every time.
6469 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
6470 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
6471 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
6473 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
6475 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6476 * bitwise-or of what L1 wants to trap for L2, and what we want to
6477 * trap. Note that CR0.TS also needs updating - we do this later.
6479 update_exception_bitmap(vcpu
);
6480 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
6481 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6483 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6484 vmcs_write32(VM_EXIT_CONTROLS
,
6485 vmcs12
->vm_exit_controls
| vmcs_config
.vmexit_ctrl
);
6486 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs12
->vm_entry_controls
|
6487 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
6489 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)
6490 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
6491 else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
6492 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
6495 set_cr4_guest_host_mask(vmx
);
6497 vmcs_write64(TSC_OFFSET
,
6498 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
6502 * Trivially support vpid by letting L2s share their parent
6503 * L1's vpid. TODO: move to a more elaborate solution, giving
6504 * each L2 its own vpid and exposing the vpid feature to L1.
6506 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
6507 vmx_flush_tlb(vcpu
);
6510 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
6511 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
6512 if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
6513 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6515 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6516 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6517 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6520 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6521 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6522 * The CR0_READ_SHADOW is what L2 should have expected to read given
6523 * the specifications by L1; It's not enough to take
6524 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6525 * have more bits than L1 expected.
6527 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
6528 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
6530 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
6531 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
6533 /* shadow page tables on either EPT or shadow page tables */
6534 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
6535 kvm_mmu_reset_context(vcpu
);
6537 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
6538 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
6542 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6543 * for running an L2 nested guest.
6545 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
6547 struct vmcs12
*vmcs12
;
6548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6550 struct loaded_vmcs
*vmcs02
;
6552 if (!nested_vmx_check_permission(vcpu
) ||
6553 !nested_vmx_check_vmcs12(vcpu
))
6556 skip_emulated_instruction(vcpu
);
6557 vmcs12
= get_vmcs12(vcpu
);
6560 * The nested entry process starts with enforcing various prerequisites
6561 * on vmcs12 as required by the Intel SDM, and act appropriately when
6562 * they fail: As the SDM explains, some conditions should cause the
6563 * instruction to fail, while others will cause the instruction to seem
6564 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6565 * To speed up the normal (success) code path, we should avoid checking
6566 * for misconfigurations which will anyway be caught by the processor
6567 * when using the merged vmcs02.
6569 if (vmcs12
->launch_state
== launch
) {
6570 nested_vmx_failValid(vcpu
,
6571 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6572 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
6576 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
6577 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
6578 /*TODO: Also verify bits beyond physical address width are 0*/
6579 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6583 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
6584 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
6585 /*TODO: Also verify bits beyond physical address width are 0*/
6586 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6590 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
6591 vmcs12
->vm_exit_msr_load_count
> 0 ||
6592 vmcs12
->vm_exit_msr_store_count
> 0) {
6593 if (printk_ratelimit())
6595 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__
);
6596 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6600 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
6601 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
6602 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
6603 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
6604 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
6605 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
6606 !vmx_control_verify(vmcs12
->vm_exit_controls
,
6607 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
6608 !vmx_control_verify(vmcs12
->vm_entry_controls
,
6609 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
6611 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
6615 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6616 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6617 nested_vmx_failValid(vcpu
,
6618 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
6622 if (((vmcs12
->guest_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
6623 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
6624 nested_vmx_entry_failure(vcpu
, vmcs12
,
6625 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
6628 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
6629 nested_vmx_entry_failure(vcpu
, vmcs12
,
6630 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
6635 * We're finally done with prerequisite checking, and can start with
6639 vmcs02
= nested_get_current_vmcs02(vmx
);
6643 enter_guest_mode(vcpu
);
6645 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
6648 vmx
->loaded_vmcs
= vmcs02
;
6650 vmx_vcpu_load(vcpu
, cpu
);
6654 vmcs12
->launch_state
= 1;
6656 prepare_vmcs02(vcpu
, vmcs12
);
6659 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6660 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6661 * returned as far as L1 is concerned. It will only return (and set
6662 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6668 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6669 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6670 * This function returns the new value we should put in vmcs12.guest_cr0.
6671 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6672 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6673 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6674 * didn't trap the bit, because if L1 did, so would L0).
6675 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6676 * been modified by L2, and L1 knows it. So just leave the old value of
6677 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6678 * isn't relevant, because if L0 traps this bit it can set it to anything.
6679 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6680 * changed these bits, and therefore they need to be updated, but L0
6681 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6682 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6684 static inline unsigned long
6685 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6688 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
6689 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
6690 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
6691 vcpu
->arch
.cr0_guest_owned_bits
));
6694 static inline unsigned long
6695 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6698 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
6699 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
6700 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
6701 vcpu
->arch
.cr4_guest_owned_bits
));
6705 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6706 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6707 * and this function updates it to reflect the changes to the guest state while
6708 * L2 was running (and perhaps made some exits which were handled directly by L0
6709 * without going back to L1), and to reflect the exit reason.
6710 * Note that we do not have to copy here all VMCS fields, just those that
6711 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6712 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6713 * which already writes to vmcs12 directly.
6715 void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6717 /* update guest state fields: */
6718 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
6719 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
6721 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
6722 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
6723 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
6724 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
6726 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
6727 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
6728 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
6729 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
6730 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
6731 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
6732 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
6733 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
6734 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
6735 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
6736 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
6737 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
6738 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
6739 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
6740 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
6741 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
6742 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
6743 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
6744 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
6745 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
6746 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
6747 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
6748 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
6749 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
6750 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
6751 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
6752 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
6753 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
6754 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
6755 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
6756 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
6757 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
6758 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
6759 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
6760 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
6761 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
6763 vmcs12
->guest_activity_state
= vmcs_read32(GUEST_ACTIVITY_STATE
);
6764 vmcs12
->guest_interruptibility_info
=
6765 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
6766 vmcs12
->guest_pending_dbg_exceptions
=
6767 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
6769 /* TODO: These cannot have changed unless we have MSR bitmaps and
6770 * the relevant bit asks not to trap the change */
6771 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
6772 if (vmcs12
->vm_entry_controls
& VM_EXIT_SAVE_IA32_PAT
)
6773 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
6774 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
6775 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
6776 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
6778 /* update exit information fields: */
6780 vmcs12
->vm_exit_reason
= vmcs_read32(VM_EXIT_REASON
);
6781 vmcs12
->exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6783 vmcs12
->vm_exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6784 vmcs12
->vm_exit_intr_error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
6785 vmcs12
->idt_vectoring_info_field
=
6786 vmcs_read32(IDT_VECTORING_INFO_FIELD
);
6787 vmcs12
->idt_vectoring_error_code
=
6788 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6789 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
6790 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6792 /* clear vm-entry fields which are to be cleared on exit */
6793 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
6794 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
6798 * A part of what we need to when the nested L2 guest exits and we want to
6799 * run its L1 parent, is to reset L1's guest state to the host state specified
6801 * This function is to be called not only on normal nested exit, but also on
6802 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6803 * Failures During or After Loading Guest State").
6804 * This function should be called when the active VMCS is L1's (vmcs01).
6806 void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
6808 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
6809 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
6810 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
6811 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
6813 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
6814 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
6816 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
6817 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
6819 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6820 * actually changed, because it depends on the current state of
6821 * fpu_active (which may have changed).
6822 * Note that vmx_set_cr0 refers to efer set above.
6824 kvm_set_cr0(vcpu
, vmcs12
->host_cr0
);
6826 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6827 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6828 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6830 update_exception_bitmap(vcpu
);
6831 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
6832 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
6835 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6836 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6838 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
6839 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
6841 /* shadow page tables on either EPT or shadow page tables */
6842 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
6843 kvm_mmu_reset_context(vcpu
);
6847 * Trivially support vpid by letting L2s share their parent
6848 * L1's vpid. TODO: move to a more elaborate solution, giving
6849 * each L2 its own vpid and exposing the vpid feature to L1.
6851 vmx_flush_tlb(vcpu
);
6855 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
6856 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
6857 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
6858 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
6859 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
6860 vmcs_writel(GUEST_TR_BASE
, vmcs12
->host_tr_base
);
6861 vmcs_writel(GUEST_GS_BASE
, vmcs12
->host_gs_base
);
6862 vmcs_writel(GUEST_FS_BASE
, vmcs12
->host_fs_base
);
6863 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->host_es_selector
);
6864 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->host_cs_selector
);
6865 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->host_ss_selector
);
6866 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->host_ds_selector
);
6867 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->host_fs_selector
);
6868 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->host_gs_selector
);
6869 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->host_tr_selector
);
6871 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
)
6872 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
6873 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
6874 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
6875 vmcs12
->host_ia32_perf_global_ctrl
);
6879 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6880 * and modify vmcs12 to make it see what it would expect to see there if
6881 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6883 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
)
6885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6887 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6889 leave_guest_mode(vcpu
);
6890 prepare_vmcs12(vcpu
, vmcs12
);
6893 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
6895 vmx_vcpu_load(vcpu
, cpu
);
6899 /* if no vmcs02 cache requested, remove the one we used */
6900 if (VMCS02_POOL_SIZE
== 0)
6901 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
6903 load_vmcs12_host_state(vcpu
, vmcs12
);
6905 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6906 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
6908 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6911 /* Unpin physical memory we referred to in vmcs02 */
6912 if (vmx
->nested
.apic_access_page
) {
6913 nested_release_page(vmx
->nested
.apic_access_page
);
6914 vmx
->nested
.apic_access_page
= 0;
6918 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6919 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6920 * success or failure flag accordingly.
6922 if (unlikely(vmx
->fail
)) {
6924 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
6926 nested_vmx_succeed(vcpu
);
6930 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6931 * 23.7 "VM-entry failures during or after loading guest state" (this also
6932 * lists the acceptable exit-reason and exit-qualification parameters).
6933 * It should only be called before L2 actually succeeded to run, and when
6934 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6936 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
6937 struct vmcs12
*vmcs12
,
6938 u32 reason
, unsigned long qualification
)
6940 load_vmcs12_host_state(vcpu
, vmcs12
);
6941 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
6942 vmcs12
->exit_qualification
= qualification
;
6943 nested_vmx_succeed(vcpu
);
6946 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
6947 struct x86_instruction_info
*info
,
6948 enum x86_intercept_stage stage
)
6950 return X86EMUL_CONTINUE
;
6953 static struct kvm_x86_ops vmx_x86_ops
= {
6954 .cpu_has_kvm_support
= cpu_has_kvm_support
,
6955 .disabled_by_bios
= vmx_disabled_by_bios
,
6956 .hardware_setup
= hardware_setup
,
6957 .hardware_unsetup
= hardware_unsetup
,
6958 .check_processor_compatibility
= vmx_check_processor_compat
,
6959 .hardware_enable
= hardware_enable
,
6960 .hardware_disable
= hardware_disable
,
6961 .cpu_has_accelerated_tpr
= report_flexpriority
,
6963 .vcpu_create
= vmx_create_vcpu
,
6964 .vcpu_free
= vmx_free_vcpu
,
6965 .vcpu_reset
= vmx_vcpu_reset
,
6967 .prepare_guest_switch
= vmx_save_host_state
,
6968 .vcpu_load
= vmx_vcpu_load
,
6969 .vcpu_put
= vmx_vcpu_put
,
6971 .set_guest_debug
= set_guest_debug
,
6972 .get_msr
= vmx_get_msr
,
6973 .set_msr
= vmx_set_msr
,
6974 .get_segment_base
= vmx_get_segment_base
,
6975 .get_segment
= vmx_get_segment
,
6976 .set_segment
= vmx_set_segment
,
6977 .get_cpl
= vmx_get_cpl
,
6978 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
6979 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
6980 .decache_cr3
= vmx_decache_cr3
,
6981 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
6982 .set_cr0
= vmx_set_cr0
,
6983 .set_cr3
= vmx_set_cr3
,
6984 .set_cr4
= vmx_set_cr4
,
6985 .set_efer
= vmx_set_efer
,
6986 .get_idt
= vmx_get_idt
,
6987 .set_idt
= vmx_set_idt
,
6988 .get_gdt
= vmx_get_gdt
,
6989 .set_gdt
= vmx_set_gdt
,
6990 .set_dr7
= vmx_set_dr7
,
6991 .cache_reg
= vmx_cache_reg
,
6992 .get_rflags
= vmx_get_rflags
,
6993 .set_rflags
= vmx_set_rflags
,
6994 .fpu_activate
= vmx_fpu_activate
,
6995 .fpu_deactivate
= vmx_fpu_deactivate
,
6997 .tlb_flush
= vmx_flush_tlb
,
6999 .run
= vmx_vcpu_run
,
7000 .handle_exit
= vmx_handle_exit
,
7001 .skip_emulated_instruction
= skip_emulated_instruction
,
7002 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
7003 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
7004 .patch_hypercall
= vmx_patch_hypercall
,
7005 .set_irq
= vmx_inject_irq
,
7006 .set_nmi
= vmx_inject_nmi
,
7007 .queue_exception
= vmx_queue_exception
,
7008 .cancel_injection
= vmx_cancel_injection
,
7009 .interrupt_allowed
= vmx_interrupt_allowed
,
7010 .nmi_allowed
= vmx_nmi_allowed
,
7011 .get_nmi_mask
= vmx_get_nmi_mask
,
7012 .set_nmi_mask
= vmx_set_nmi_mask
,
7013 .enable_nmi_window
= enable_nmi_window
,
7014 .enable_irq_window
= enable_irq_window
,
7015 .update_cr8_intercept
= update_cr8_intercept
,
7017 .set_tss_addr
= vmx_set_tss_addr
,
7018 .get_tdp_level
= get_ept_level
,
7019 .get_mt_mask
= vmx_get_mt_mask
,
7021 .get_exit_info
= vmx_get_exit_info
,
7022 .exit_reasons_str
= vmx_exit_reasons_str
,
7024 .get_lpage_level
= vmx_get_lpage_level
,
7026 .cpuid_update
= vmx_cpuid_update
,
7028 .rdtscp_supported
= vmx_rdtscp_supported
,
7030 .set_supported_cpuid
= vmx_set_supported_cpuid
,
7032 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
7034 .set_tsc_khz
= vmx_set_tsc_khz
,
7035 .write_tsc_offset
= vmx_write_tsc_offset
,
7036 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
7037 .compute_tsc_offset
= vmx_compute_tsc_offset
,
7039 .set_tdp_cr3
= vmx_set_cr3
,
7041 .check_intercept
= vmx_check_intercept
,
7044 static int __init
vmx_init(void)
7048 rdmsrl_safe(MSR_EFER
, &host_efer
);
7050 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
7051 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
7053 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7054 if (!vmx_io_bitmap_a
)
7057 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7058 if (!vmx_io_bitmap_b
) {
7063 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7064 if (!vmx_msr_bitmap_legacy
) {
7069 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
7070 if (!vmx_msr_bitmap_longmode
) {
7076 * Allow direct access to the PC debug port (it is often used for I/O
7077 * delays, but the vmexits simply slow things down).
7079 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
7080 clear_bit(0x80, vmx_io_bitmap_a
);
7082 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
7084 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
7085 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
7087 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
7089 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
7090 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
7094 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
7095 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
7096 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
7097 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
7098 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
7099 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
7102 bypass_guest_pf
= 0;
7103 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7104 VMX_EPT_EXECUTABLE_MASK
);
7109 if (bypass_guest_pf
)
7110 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
7115 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7117 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7119 free_page((unsigned long)vmx_io_bitmap_b
);
7121 free_page((unsigned long)vmx_io_bitmap_a
);
7125 static void __exit
vmx_exit(void)
7127 free_page((unsigned long)vmx_msr_bitmap_legacy
);
7128 free_page((unsigned long)vmx_msr_bitmap_longmode
);
7129 free_page((unsigned long)vmx_io_bitmap_b
);
7130 free_page((unsigned long)vmx_io_bitmap_a
);
7135 module_init(vmx_init
)
7136 module_exit(vmx_exit
)