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kvm: remove unnecessary bit checking for ept violation
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "cpuid.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include "kvm_cache_regs.h"
35 #include "x86.h"
36
37 #include <asm/io.h>
38 #include <asm/desc.h>
39 #include <asm/vmx.h>
40 #include <asm/virtext.h>
41 #include <asm/mce.h>
42 #include <asm/i387.h>
43 #include <asm/xcr.h>
44 #include <asm/perf_event.h>
45
46 #include "trace.h"
47
48 #define __ex(x) __kvm_handle_fault_on_reboot(x)
49 #define __ex_clear(x, reg) \
50 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
51
52 MODULE_AUTHOR("Qumranet");
53 MODULE_LICENSE("GPL");
54
55 static const struct x86_cpu_id vmx_cpu_id[] = {
56 X86_FEATURE_MATCH(X86_FEATURE_VMX),
57 {}
58 };
59 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
60
61 static bool __read_mostly enable_vpid = 1;
62 module_param_named(vpid, enable_vpid, bool, 0444);
63
64 static bool __read_mostly flexpriority_enabled = 1;
65 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
66
67 static bool __read_mostly enable_ept = 1;
68 module_param_named(ept, enable_ept, bool, S_IRUGO);
69
70 static bool __read_mostly enable_unrestricted_guest = 1;
71 module_param_named(unrestricted_guest,
72 enable_unrestricted_guest, bool, S_IRUGO);
73
74 static bool __read_mostly enable_ept_ad_bits = 1;
75 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
76
77 static bool __read_mostly emulate_invalid_guest_state = true;
78 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
79
80 static bool __read_mostly vmm_exclusive = 1;
81 module_param(vmm_exclusive, bool, S_IRUGO);
82
83 static bool __read_mostly fasteoi = 1;
84 module_param(fasteoi, bool, S_IRUGO);
85
86 /*
87 * If nested=1, nested virtualization is supported, i.e., guests may use
88 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
89 * use VMX instructions.
90 */
91 static bool __read_mostly nested = 0;
92 module_param(nested, bool, S_IRUGO);
93
94 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
95 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
96 #define KVM_GUEST_CR0_MASK \
97 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
98 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
99 (X86_CR0_WP | X86_CR0_NE)
100 #define KVM_VM_CR0_ALWAYS_ON \
101 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
102 #define KVM_CR4_GUEST_OWNED_BITS \
103 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
104 | X86_CR4_OSXMMEXCPT)
105
106 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
107 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
108
109 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
110
111 /*
112 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
113 * ple_gap: upper bound on the amount of time between two successive
114 * executions of PAUSE in a loop. Also indicate if ple enabled.
115 * According to test, this time is usually smaller than 128 cycles.
116 * ple_window: upper bound on the amount of time a guest is allowed to execute
117 * in a PAUSE loop. Tests indicate that most spinlocks are held for
118 * less than 2^12 cycles
119 * Time is measured based on a counter that runs at the same rate as the TSC,
120 * refer SDM volume 3b section 21.6.13 & 22.1.3.
121 */
122 #define KVM_VMX_DEFAULT_PLE_GAP 128
123 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
124 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
125 module_param(ple_gap, int, S_IRUGO);
126
127 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
128 module_param(ple_window, int, S_IRUGO);
129
130 extern const ulong vmx_return;
131
132 #define NR_AUTOLOAD_MSRS 8
133 #define VMCS02_POOL_SIZE 1
134
135 struct vmcs {
136 u32 revision_id;
137 u32 abort;
138 char data[0];
139 };
140
141 /*
142 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
143 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
144 * loaded on this CPU (so we can clear them if the CPU goes down).
145 */
146 struct loaded_vmcs {
147 struct vmcs *vmcs;
148 int cpu;
149 int launched;
150 struct list_head loaded_vmcss_on_cpu_link;
151 };
152
153 struct shared_msr_entry {
154 unsigned index;
155 u64 data;
156 u64 mask;
157 };
158
159 /*
160 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
161 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
162 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
163 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
164 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
165 * More than one of these structures may exist, if L1 runs multiple L2 guests.
166 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
167 * underlying hardware which will be used to run L2.
168 * This structure is packed to ensure that its layout is identical across
169 * machines (necessary for live migration).
170 * If there are changes in this struct, VMCS12_REVISION must be changed.
171 */
172 typedef u64 natural_width;
173 struct __packed vmcs12 {
174 /* According to the Intel spec, a VMCS region must start with the
175 * following two fields. Then follow implementation-specific data.
176 */
177 u32 revision_id;
178 u32 abort;
179
180 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
181 u32 padding[7]; /* room for future expansion */
182
183 u64 io_bitmap_a;
184 u64 io_bitmap_b;
185 u64 msr_bitmap;
186 u64 vm_exit_msr_store_addr;
187 u64 vm_exit_msr_load_addr;
188 u64 vm_entry_msr_load_addr;
189 u64 tsc_offset;
190 u64 virtual_apic_page_addr;
191 u64 apic_access_addr;
192 u64 ept_pointer;
193 u64 guest_physical_address;
194 u64 vmcs_link_pointer;
195 u64 guest_ia32_debugctl;
196 u64 guest_ia32_pat;
197 u64 guest_ia32_efer;
198 u64 guest_ia32_perf_global_ctrl;
199 u64 guest_pdptr0;
200 u64 guest_pdptr1;
201 u64 guest_pdptr2;
202 u64 guest_pdptr3;
203 u64 host_ia32_pat;
204 u64 host_ia32_efer;
205 u64 host_ia32_perf_global_ctrl;
206 u64 padding64[8]; /* room for future expansion */
207 /*
208 * To allow migration of L1 (complete with its L2 guests) between
209 * machines of different natural widths (32 or 64 bit), we cannot have
210 * unsigned long fields with no explict size. We use u64 (aliased
211 * natural_width) instead. Luckily, x86 is little-endian.
212 */
213 natural_width cr0_guest_host_mask;
214 natural_width cr4_guest_host_mask;
215 natural_width cr0_read_shadow;
216 natural_width cr4_read_shadow;
217 natural_width cr3_target_value0;
218 natural_width cr3_target_value1;
219 natural_width cr3_target_value2;
220 natural_width cr3_target_value3;
221 natural_width exit_qualification;
222 natural_width guest_linear_address;
223 natural_width guest_cr0;
224 natural_width guest_cr3;
225 natural_width guest_cr4;
226 natural_width guest_es_base;
227 natural_width guest_cs_base;
228 natural_width guest_ss_base;
229 natural_width guest_ds_base;
230 natural_width guest_fs_base;
231 natural_width guest_gs_base;
232 natural_width guest_ldtr_base;
233 natural_width guest_tr_base;
234 natural_width guest_gdtr_base;
235 natural_width guest_idtr_base;
236 natural_width guest_dr7;
237 natural_width guest_rsp;
238 natural_width guest_rip;
239 natural_width guest_rflags;
240 natural_width guest_pending_dbg_exceptions;
241 natural_width guest_sysenter_esp;
242 natural_width guest_sysenter_eip;
243 natural_width host_cr0;
244 natural_width host_cr3;
245 natural_width host_cr4;
246 natural_width host_fs_base;
247 natural_width host_gs_base;
248 natural_width host_tr_base;
249 natural_width host_gdtr_base;
250 natural_width host_idtr_base;
251 natural_width host_ia32_sysenter_esp;
252 natural_width host_ia32_sysenter_eip;
253 natural_width host_rsp;
254 natural_width host_rip;
255 natural_width paddingl[8]; /* room for future expansion */
256 u32 pin_based_vm_exec_control;
257 u32 cpu_based_vm_exec_control;
258 u32 exception_bitmap;
259 u32 page_fault_error_code_mask;
260 u32 page_fault_error_code_match;
261 u32 cr3_target_count;
262 u32 vm_exit_controls;
263 u32 vm_exit_msr_store_count;
264 u32 vm_exit_msr_load_count;
265 u32 vm_entry_controls;
266 u32 vm_entry_msr_load_count;
267 u32 vm_entry_intr_info_field;
268 u32 vm_entry_exception_error_code;
269 u32 vm_entry_instruction_len;
270 u32 tpr_threshold;
271 u32 secondary_vm_exec_control;
272 u32 vm_instruction_error;
273 u32 vm_exit_reason;
274 u32 vm_exit_intr_info;
275 u32 vm_exit_intr_error_code;
276 u32 idt_vectoring_info_field;
277 u32 idt_vectoring_error_code;
278 u32 vm_exit_instruction_len;
279 u32 vmx_instruction_info;
280 u32 guest_es_limit;
281 u32 guest_cs_limit;
282 u32 guest_ss_limit;
283 u32 guest_ds_limit;
284 u32 guest_fs_limit;
285 u32 guest_gs_limit;
286 u32 guest_ldtr_limit;
287 u32 guest_tr_limit;
288 u32 guest_gdtr_limit;
289 u32 guest_idtr_limit;
290 u32 guest_es_ar_bytes;
291 u32 guest_cs_ar_bytes;
292 u32 guest_ss_ar_bytes;
293 u32 guest_ds_ar_bytes;
294 u32 guest_fs_ar_bytes;
295 u32 guest_gs_ar_bytes;
296 u32 guest_ldtr_ar_bytes;
297 u32 guest_tr_ar_bytes;
298 u32 guest_interruptibility_info;
299 u32 guest_activity_state;
300 u32 guest_sysenter_cs;
301 u32 host_ia32_sysenter_cs;
302 u32 padding32[8]; /* room for future expansion */
303 u16 virtual_processor_id;
304 u16 guest_es_selector;
305 u16 guest_cs_selector;
306 u16 guest_ss_selector;
307 u16 guest_ds_selector;
308 u16 guest_fs_selector;
309 u16 guest_gs_selector;
310 u16 guest_ldtr_selector;
311 u16 guest_tr_selector;
312 u16 host_es_selector;
313 u16 host_cs_selector;
314 u16 host_ss_selector;
315 u16 host_ds_selector;
316 u16 host_fs_selector;
317 u16 host_gs_selector;
318 u16 host_tr_selector;
319 };
320
321 /*
322 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
323 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
324 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
325 */
326 #define VMCS12_REVISION 0x11e57ed0
327
328 /*
329 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
330 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
331 * current implementation, 4K are reserved to avoid future complications.
332 */
333 #define VMCS12_SIZE 0x1000
334
335 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
336 struct vmcs02_list {
337 struct list_head list;
338 gpa_t vmptr;
339 struct loaded_vmcs vmcs02;
340 };
341
342 /*
343 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
344 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
345 */
346 struct nested_vmx {
347 /* Has the level1 guest done vmxon? */
348 bool vmxon;
349
350 /* The guest-physical address of the current VMCS L1 keeps for L2 */
351 gpa_t current_vmptr;
352 /* The host-usable pointer to the above */
353 struct page *current_vmcs12_page;
354 struct vmcs12 *current_vmcs12;
355
356 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
357 struct list_head vmcs02_pool;
358 int vmcs02_num;
359 u64 vmcs01_tsc_offset;
360 /* L2 must run next, and mustn't decide to exit to L1. */
361 bool nested_run_pending;
362 /*
363 * Guest pages referred to in vmcs02 with host-physical pointers, so
364 * we must keep them pinned while L2 runs.
365 */
366 struct page *apic_access_page;
367 };
368
369 struct vcpu_vmx {
370 struct kvm_vcpu vcpu;
371 unsigned long host_rsp;
372 u8 fail;
373 u8 cpl;
374 bool nmi_known_unmasked;
375 u32 exit_intr_info;
376 u32 idt_vectoring_info;
377 ulong rflags;
378 struct shared_msr_entry *guest_msrs;
379 int nmsrs;
380 int save_nmsrs;
381 #ifdef CONFIG_X86_64
382 u64 msr_host_kernel_gs_base;
383 u64 msr_guest_kernel_gs_base;
384 #endif
385 /*
386 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
387 * non-nested (L1) guest, it always points to vmcs01. For a nested
388 * guest (L2), it points to a different VMCS.
389 */
390 struct loaded_vmcs vmcs01;
391 struct loaded_vmcs *loaded_vmcs;
392 bool __launched; /* temporary, used in vmx_vcpu_run */
393 struct msr_autoload {
394 unsigned nr;
395 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
396 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
397 } msr_autoload;
398 struct {
399 int loaded;
400 u16 fs_sel, gs_sel, ldt_sel;
401 #ifdef CONFIG_X86_64
402 u16 ds_sel, es_sel;
403 #endif
404 int gs_ldt_reload_needed;
405 int fs_reload_needed;
406 } host_state;
407 struct {
408 int vm86_active;
409 ulong save_rflags;
410 struct kvm_segment segs[8];
411 } rmode;
412 struct {
413 u32 bitmask; /* 4 bits per segment (1 bit per field) */
414 struct kvm_save_segment {
415 u16 selector;
416 unsigned long base;
417 u32 limit;
418 u32 ar;
419 } seg[8];
420 } segment_cache;
421 int vpid;
422 bool emulation_required;
423
424 /* Support for vnmi-less CPUs */
425 int soft_vnmi_blocked;
426 ktime_t entry_time;
427 s64 vnmi_blocked_time;
428 u32 exit_reason;
429
430 bool rdtscp_enabled;
431
432 /* Support for a guest hypervisor (nested VMX) */
433 struct nested_vmx nested;
434 };
435
436 enum segment_cache_field {
437 SEG_FIELD_SEL = 0,
438 SEG_FIELD_BASE = 1,
439 SEG_FIELD_LIMIT = 2,
440 SEG_FIELD_AR = 3,
441
442 SEG_FIELD_NR = 4
443 };
444
445 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
446 {
447 return container_of(vcpu, struct vcpu_vmx, vcpu);
448 }
449
450 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
451 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
452 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
453 [number##_HIGH] = VMCS12_OFFSET(name)+4
454
455 static const unsigned short vmcs_field_to_offset_table[] = {
456 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
457 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
458 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
459 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
460 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
461 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
462 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
463 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
464 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
465 FIELD(HOST_ES_SELECTOR, host_es_selector),
466 FIELD(HOST_CS_SELECTOR, host_cs_selector),
467 FIELD(HOST_SS_SELECTOR, host_ss_selector),
468 FIELD(HOST_DS_SELECTOR, host_ds_selector),
469 FIELD(HOST_FS_SELECTOR, host_fs_selector),
470 FIELD(HOST_GS_SELECTOR, host_gs_selector),
471 FIELD(HOST_TR_SELECTOR, host_tr_selector),
472 FIELD64(IO_BITMAP_A, io_bitmap_a),
473 FIELD64(IO_BITMAP_B, io_bitmap_b),
474 FIELD64(MSR_BITMAP, msr_bitmap),
475 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
476 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
477 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
478 FIELD64(TSC_OFFSET, tsc_offset),
479 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
480 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
481 FIELD64(EPT_POINTER, ept_pointer),
482 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
483 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
484 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
485 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
486 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
487 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
488 FIELD64(GUEST_PDPTR0, guest_pdptr0),
489 FIELD64(GUEST_PDPTR1, guest_pdptr1),
490 FIELD64(GUEST_PDPTR2, guest_pdptr2),
491 FIELD64(GUEST_PDPTR3, guest_pdptr3),
492 FIELD64(HOST_IA32_PAT, host_ia32_pat),
493 FIELD64(HOST_IA32_EFER, host_ia32_efer),
494 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
495 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
496 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
497 FIELD(EXCEPTION_BITMAP, exception_bitmap),
498 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
499 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
500 FIELD(CR3_TARGET_COUNT, cr3_target_count),
501 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
502 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
503 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
504 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
505 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
506 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
507 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
508 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
509 FIELD(TPR_THRESHOLD, tpr_threshold),
510 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
511 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
512 FIELD(VM_EXIT_REASON, vm_exit_reason),
513 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
514 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
515 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
516 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
517 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
518 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
519 FIELD(GUEST_ES_LIMIT, guest_es_limit),
520 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
521 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
522 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
523 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
524 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
525 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
526 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
527 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
528 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
529 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
530 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
531 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
532 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
533 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
534 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
535 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
536 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
537 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
538 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
539 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
540 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
541 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
542 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
543 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
544 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
545 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
546 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
547 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
548 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
549 FIELD(EXIT_QUALIFICATION, exit_qualification),
550 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
551 FIELD(GUEST_CR0, guest_cr0),
552 FIELD(GUEST_CR3, guest_cr3),
553 FIELD(GUEST_CR4, guest_cr4),
554 FIELD(GUEST_ES_BASE, guest_es_base),
555 FIELD(GUEST_CS_BASE, guest_cs_base),
556 FIELD(GUEST_SS_BASE, guest_ss_base),
557 FIELD(GUEST_DS_BASE, guest_ds_base),
558 FIELD(GUEST_FS_BASE, guest_fs_base),
559 FIELD(GUEST_GS_BASE, guest_gs_base),
560 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
561 FIELD(GUEST_TR_BASE, guest_tr_base),
562 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
563 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
564 FIELD(GUEST_DR7, guest_dr7),
565 FIELD(GUEST_RSP, guest_rsp),
566 FIELD(GUEST_RIP, guest_rip),
567 FIELD(GUEST_RFLAGS, guest_rflags),
568 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
569 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
570 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
571 FIELD(HOST_CR0, host_cr0),
572 FIELD(HOST_CR3, host_cr3),
573 FIELD(HOST_CR4, host_cr4),
574 FIELD(HOST_FS_BASE, host_fs_base),
575 FIELD(HOST_GS_BASE, host_gs_base),
576 FIELD(HOST_TR_BASE, host_tr_base),
577 FIELD(HOST_GDTR_BASE, host_gdtr_base),
578 FIELD(HOST_IDTR_BASE, host_idtr_base),
579 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
580 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
581 FIELD(HOST_RSP, host_rsp),
582 FIELD(HOST_RIP, host_rip),
583 };
584 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
585
586 static inline short vmcs_field_to_offset(unsigned long field)
587 {
588 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
589 return -1;
590 return vmcs_field_to_offset_table[field];
591 }
592
593 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
594 {
595 return to_vmx(vcpu)->nested.current_vmcs12;
596 }
597
598 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
599 {
600 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
601 if (is_error_page(page))
602 return NULL;
603
604 return page;
605 }
606
607 static void nested_release_page(struct page *page)
608 {
609 kvm_release_page_dirty(page);
610 }
611
612 static void nested_release_page_clean(struct page *page)
613 {
614 kvm_release_page_clean(page);
615 }
616
617 static u64 construct_eptp(unsigned long root_hpa);
618 static void kvm_cpu_vmxon(u64 addr);
619 static void kvm_cpu_vmxoff(void);
620 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
621 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
622 static void vmx_set_segment(struct kvm_vcpu *vcpu,
623 struct kvm_segment *var, int seg);
624 static void vmx_get_segment(struct kvm_vcpu *vcpu,
625 struct kvm_segment *var, int seg);
626
627 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
628 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
629 /*
630 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
631 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
632 */
633 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
634 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
635
636 static unsigned long *vmx_io_bitmap_a;
637 static unsigned long *vmx_io_bitmap_b;
638 static unsigned long *vmx_msr_bitmap_legacy;
639 static unsigned long *vmx_msr_bitmap_longmode;
640
641 static bool cpu_has_load_ia32_efer;
642 static bool cpu_has_load_perf_global_ctrl;
643
644 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
645 static DEFINE_SPINLOCK(vmx_vpid_lock);
646
647 static struct vmcs_config {
648 int size;
649 int order;
650 u32 revision_id;
651 u32 pin_based_exec_ctrl;
652 u32 cpu_based_exec_ctrl;
653 u32 cpu_based_2nd_exec_ctrl;
654 u32 vmexit_ctrl;
655 u32 vmentry_ctrl;
656 } vmcs_config;
657
658 static struct vmx_capability {
659 u32 ept;
660 u32 vpid;
661 } vmx_capability;
662
663 #define VMX_SEGMENT_FIELD(seg) \
664 [VCPU_SREG_##seg] = { \
665 .selector = GUEST_##seg##_SELECTOR, \
666 .base = GUEST_##seg##_BASE, \
667 .limit = GUEST_##seg##_LIMIT, \
668 .ar_bytes = GUEST_##seg##_AR_BYTES, \
669 }
670
671 static const struct kvm_vmx_segment_field {
672 unsigned selector;
673 unsigned base;
674 unsigned limit;
675 unsigned ar_bytes;
676 } kvm_vmx_segment_fields[] = {
677 VMX_SEGMENT_FIELD(CS),
678 VMX_SEGMENT_FIELD(DS),
679 VMX_SEGMENT_FIELD(ES),
680 VMX_SEGMENT_FIELD(FS),
681 VMX_SEGMENT_FIELD(GS),
682 VMX_SEGMENT_FIELD(SS),
683 VMX_SEGMENT_FIELD(TR),
684 VMX_SEGMENT_FIELD(LDTR),
685 };
686
687 static u64 host_efer;
688
689 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
690
691 /*
692 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
693 * away by decrementing the array size.
694 */
695 static const u32 vmx_msr_index[] = {
696 #ifdef CONFIG_X86_64
697 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
698 #endif
699 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
700 };
701 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
702
703 static inline bool is_page_fault(u32 intr_info)
704 {
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
706 INTR_INFO_VALID_MASK)) ==
707 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
708 }
709
710 static inline bool is_no_device(u32 intr_info)
711 {
712 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
713 INTR_INFO_VALID_MASK)) ==
714 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
715 }
716
717 static inline bool is_invalid_opcode(u32 intr_info)
718 {
719 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
720 INTR_INFO_VALID_MASK)) ==
721 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
722 }
723
724 static inline bool is_external_interrupt(u32 intr_info)
725 {
726 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
727 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
728 }
729
730 static inline bool is_machine_check(u32 intr_info)
731 {
732 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
733 INTR_INFO_VALID_MASK)) ==
734 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
735 }
736
737 static inline bool cpu_has_vmx_msr_bitmap(void)
738 {
739 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
740 }
741
742 static inline bool cpu_has_vmx_tpr_shadow(void)
743 {
744 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
745 }
746
747 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
748 {
749 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
750 }
751
752 static inline bool cpu_has_secondary_exec_ctrls(void)
753 {
754 return vmcs_config.cpu_based_exec_ctrl &
755 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
756 }
757
758 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
759 {
760 return vmcs_config.cpu_based_2nd_exec_ctrl &
761 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
762 }
763
764 static inline bool cpu_has_vmx_flexpriority(void)
765 {
766 return cpu_has_vmx_tpr_shadow() &&
767 cpu_has_vmx_virtualize_apic_accesses();
768 }
769
770 static inline bool cpu_has_vmx_ept_execute_only(void)
771 {
772 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
773 }
774
775 static inline bool cpu_has_vmx_eptp_uncacheable(void)
776 {
777 return vmx_capability.ept & VMX_EPTP_UC_BIT;
778 }
779
780 static inline bool cpu_has_vmx_eptp_writeback(void)
781 {
782 return vmx_capability.ept & VMX_EPTP_WB_BIT;
783 }
784
785 static inline bool cpu_has_vmx_ept_2m_page(void)
786 {
787 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
788 }
789
790 static inline bool cpu_has_vmx_ept_1g_page(void)
791 {
792 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
793 }
794
795 static inline bool cpu_has_vmx_ept_4levels(void)
796 {
797 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
798 }
799
800 static inline bool cpu_has_vmx_ept_ad_bits(void)
801 {
802 return vmx_capability.ept & VMX_EPT_AD_BIT;
803 }
804
805 static inline bool cpu_has_vmx_invept_individual_addr(void)
806 {
807 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
808 }
809
810 static inline bool cpu_has_vmx_invept_context(void)
811 {
812 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
813 }
814
815 static inline bool cpu_has_vmx_invept_global(void)
816 {
817 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
818 }
819
820 static inline bool cpu_has_vmx_invvpid_single(void)
821 {
822 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
823 }
824
825 static inline bool cpu_has_vmx_invvpid_global(void)
826 {
827 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
828 }
829
830 static inline bool cpu_has_vmx_ept(void)
831 {
832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_EPT;
834 }
835
836 static inline bool cpu_has_vmx_unrestricted_guest(void)
837 {
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_UNRESTRICTED_GUEST;
840 }
841
842 static inline bool cpu_has_vmx_ple(void)
843 {
844 return vmcs_config.cpu_based_2nd_exec_ctrl &
845 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
846 }
847
848 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
849 {
850 return flexpriority_enabled && irqchip_in_kernel(kvm);
851 }
852
853 static inline bool cpu_has_vmx_vpid(void)
854 {
855 return vmcs_config.cpu_based_2nd_exec_ctrl &
856 SECONDARY_EXEC_ENABLE_VPID;
857 }
858
859 static inline bool cpu_has_vmx_rdtscp(void)
860 {
861 return vmcs_config.cpu_based_2nd_exec_ctrl &
862 SECONDARY_EXEC_RDTSCP;
863 }
864
865 static inline bool cpu_has_vmx_invpcid(void)
866 {
867 return vmcs_config.cpu_based_2nd_exec_ctrl &
868 SECONDARY_EXEC_ENABLE_INVPCID;
869 }
870
871 static inline bool cpu_has_virtual_nmis(void)
872 {
873 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
874 }
875
876 static inline bool cpu_has_vmx_wbinvd_exit(void)
877 {
878 return vmcs_config.cpu_based_2nd_exec_ctrl &
879 SECONDARY_EXEC_WBINVD_EXITING;
880 }
881
882 static inline bool report_flexpriority(void)
883 {
884 return flexpriority_enabled;
885 }
886
887 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
888 {
889 return vmcs12->cpu_based_vm_exec_control & bit;
890 }
891
892 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
893 {
894 return (vmcs12->cpu_based_vm_exec_control &
895 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
896 (vmcs12->secondary_vm_exec_control & bit);
897 }
898
899 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
900 struct kvm_vcpu *vcpu)
901 {
902 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
903 }
904
905 static inline bool is_exception(u32 intr_info)
906 {
907 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
908 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
909 }
910
911 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
912 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
913 struct vmcs12 *vmcs12,
914 u32 reason, unsigned long qualification);
915
916 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
917 {
918 int i;
919
920 for (i = 0; i < vmx->nmsrs; ++i)
921 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
922 return i;
923 return -1;
924 }
925
926 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
927 {
928 struct {
929 u64 vpid : 16;
930 u64 rsvd : 48;
931 u64 gva;
932 } operand = { vpid, 0, gva };
933
934 asm volatile (__ex(ASM_VMX_INVVPID)
935 /* CF==1 or ZF==1 --> rc = -1 */
936 "; ja 1f ; ud2 ; 1:"
937 : : "a"(&operand), "c"(ext) : "cc", "memory");
938 }
939
940 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
941 {
942 struct {
943 u64 eptp, gpa;
944 } operand = {eptp, gpa};
945
946 asm volatile (__ex(ASM_VMX_INVEPT)
947 /* CF==1 or ZF==1 --> rc = -1 */
948 "; ja 1f ; ud2 ; 1:\n"
949 : : "a" (&operand), "c" (ext) : "cc", "memory");
950 }
951
952 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
953 {
954 int i;
955
956 i = __find_msr_index(vmx, msr);
957 if (i >= 0)
958 return &vmx->guest_msrs[i];
959 return NULL;
960 }
961
962 static void vmcs_clear(struct vmcs *vmcs)
963 {
964 u64 phys_addr = __pa(vmcs);
965 u8 error;
966
967 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
968 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
969 : "cc", "memory");
970 if (error)
971 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
972 vmcs, phys_addr);
973 }
974
975 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
976 {
977 vmcs_clear(loaded_vmcs->vmcs);
978 loaded_vmcs->cpu = -1;
979 loaded_vmcs->launched = 0;
980 }
981
982 static void vmcs_load(struct vmcs *vmcs)
983 {
984 u64 phys_addr = __pa(vmcs);
985 u8 error;
986
987 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
988 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
989 : "cc", "memory");
990 if (error)
991 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
992 vmcs, phys_addr);
993 }
994
995 static void __loaded_vmcs_clear(void *arg)
996 {
997 struct loaded_vmcs *loaded_vmcs = arg;
998 int cpu = raw_smp_processor_id();
999
1000 if (loaded_vmcs->cpu != cpu)
1001 return; /* vcpu migration can race with cpu offline */
1002 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1003 per_cpu(current_vmcs, cpu) = NULL;
1004 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1005
1006 /*
1007 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1008 * is before setting loaded_vmcs->vcpu to -1 which is done in
1009 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1010 * then adds the vmcs into percpu list before it is deleted.
1011 */
1012 smp_wmb();
1013
1014 loaded_vmcs_init(loaded_vmcs);
1015 }
1016
1017 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1018 {
1019 int cpu = loaded_vmcs->cpu;
1020
1021 if (cpu != -1)
1022 smp_call_function_single(cpu,
1023 __loaded_vmcs_clear, loaded_vmcs, 1);
1024 }
1025
1026 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
1027 {
1028 if (vmx->vpid == 0)
1029 return;
1030
1031 if (cpu_has_vmx_invvpid_single())
1032 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
1033 }
1034
1035 static inline void vpid_sync_vcpu_global(void)
1036 {
1037 if (cpu_has_vmx_invvpid_global())
1038 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1039 }
1040
1041 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1042 {
1043 if (cpu_has_vmx_invvpid_single())
1044 vpid_sync_vcpu_single(vmx);
1045 else
1046 vpid_sync_vcpu_global();
1047 }
1048
1049 static inline void ept_sync_global(void)
1050 {
1051 if (cpu_has_vmx_invept_global())
1052 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1053 }
1054
1055 static inline void ept_sync_context(u64 eptp)
1056 {
1057 if (enable_ept) {
1058 if (cpu_has_vmx_invept_context())
1059 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1060 else
1061 ept_sync_global();
1062 }
1063 }
1064
1065 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1066 {
1067 if (enable_ept) {
1068 if (cpu_has_vmx_invept_individual_addr())
1069 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1070 eptp, gpa);
1071 else
1072 ept_sync_context(eptp);
1073 }
1074 }
1075
1076 static __always_inline unsigned long vmcs_readl(unsigned long field)
1077 {
1078 unsigned long value;
1079
1080 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1081 : "=a"(value) : "d"(field) : "cc");
1082 return value;
1083 }
1084
1085 static __always_inline u16 vmcs_read16(unsigned long field)
1086 {
1087 return vmcs_readl(field);
1088 }
1089
1090 static __always_inline u32 vmcs_read32(unsigned long field)
1091 {
1092 return vmcs_readl(field);
1093 }
1094
1095 static __always_inline u64 vmcs_read64(unsigned long field)
1096 {
1097 #ifdef CONFIG_X86_64
1098 return vmcs_readl(field);
1099 #else
1100 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1101 #endif
1102 }
1103
1104 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1105 {
1106 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1107 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1108 dump_stack();
1109 }
1110
1111 static void vmcs_writel(unsigned long field, unsigned long value)
1112 {
1113 u8 error;
1114
1115 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1116 : "=q"(error) : "a"(value), "d"(field) : "cc");
1117 if (unlikely(error))
1118 vmwrite_error(field, value);
1119 }
1120
1121 static void vmcs_write16(unsigned long field, u16 value)
1122 {
1123 vmcs_writel(field, value);
1124 }
1125
1126 static void vmcs_write32(unsigned long field, u32 value)
1127 {
1128 vmcs_writel(field, value);
1129 }
1130
1131 static void vmcs_write64(unsigned long field, u64 value)
1132 {
1133 vmcs_writel(field, value);
1134 #ifndef CONFIG_X86_64
1135 asm volatile ("");
1136 vmcs_writel(field+1, value >> 32);
1137 #endif
1138 }
1139
1140 static void vmcs_clear_bits(unsigned long field, u32 mask)
1141 {
1142 vmcs_writel(field, vmcs_readl(field) & ~mask);
1143 }
1144
1145 static void vmcs_set_bits(unsigned long field, u32 mask)
1146 {
1147 vmcs_writel(field, vmcs_readl(field) | mask);
1148 }
1149
1150 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1151 {
1152 vmx->segment_cache.bitmask = 0;
1153 }
1154
1155 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1156 unsigned field)
1157 {
1158 bool ret;
1159 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1160
1161 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1162 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1163 vmx->segment_cache.bitmask = 0;
1164 }
1165 ret = vmx->segment_cache.bitmask & mask;
1166 vmx->segment_cache.bitmask |= mask;
1167 return ret;
1168 }
1169
1170 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1171 {
1172 u16 *p = &vmx->segment_cache.seg[seg].selector;
1173
1174 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1175 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1176 return *p;
1177 }
1178
1179 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1180 {
1181 ulong *p = &vmx->segment_cache.seg[seg].base;
1182
1183 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1184 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1185 return *p;
1186 }
1187
1188 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1189 {
1190 u32 *p = &vmx->segment_cache.seg[seg].limit;
1191
1192 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1193 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1194 return *p;
1195 }
1196
1197 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1198 {
1199 u32 *p = &vmx->segment_cache.seg[seg].ar;
1200
1201 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1202 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1203 return *p;
1204 }
1205
1206 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1207 {
1208 u32 eb;
1209
1210 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1211 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1212 if ((vcpu->guest_debug &
1213 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1214 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1215 eb |= 1u << BP_VECTOR;
1216 if (to_vmx(vcpu)->rmode.vm86_active)
1217 eb = ~0;
1218 if (enable_ept)
1219 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1220 if (vcpu->fpu_active)
1221 eb &= ~(1u << NM_VECTOR);
1222
1223 /* When we are running a nested L2 guest and L1 specified for it a
1224 * certain exception bitmap, we must trap the same exceptions and pass
1225 * them to L1. When running L2, we will only handle the exceptions
1226 * specified above if L1 did not want them.
1227 */
1228 if (is_guest_mode(vcpu))
1229 eb |= get_vmcs12(vcpu)->exception_bitmap;
1230
1231 vmcs_write32(EXCEPTION_BITMAP, eb);
1232 }
1233
1234 static void clear_atomic_switch_msr_special(unsigned long entry,
1235 unsigned long exit)
1236 {
1237 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1238 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1239 }
1240
1241 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1242 {
1243 unsigned i;
1244 struct msr_autoload *m = &vmx->msr_autoload;
1245
1246 switch (msr) {
1247 case MSR_EFER:
1248 if (cpu_has_load_ia32_efer) {
1249 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1250 VM_EXIT_LOAD_IA32_EFER);
1251 return;
1252 }
1253 break;
1254 case MSR_CORE_PERF_GLOBAL_CTRL:
1255 if (cpu_has_load_perf_global_ctrl) {
1256 clear_atomic_switch_msr_special(
1257 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1258 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1259 return;
1260 }
1261 break;
1262 }
1263
1264 for (i = 0; i < m->nr; ++i)
1265 if (m->guest[i].index == msr)
1266 break;
1267
1268 if (i == m->nr)
1269 return;
1270 --m->nr;
1271 m->guest[i] = m->guest[m->nr];
1272 m->host[i] = m->host[m->nr];
1273 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1274 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1275 }
1276
1277 static void add_atomic_switch_msr_special(unsigned long entry,
1278 unsigned long exit, unsigned long guest_val_vmcs,
1279 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1280 {
1281 vmcs_write64(guest_val_vmcs, guest_val);
1282 vmcs_write64(host_val_vmcs, host_val);
1283 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1284 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1285 }
1286
1287 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1288 u64 guest_val, u64 host_val)
1289 {
1290 unsigned i;
1291 struct msr_autoload *m = &vmx->msr_autoload;
1292
1293 switch (msr) {
1294 case MSR_EFER:
1295 if (cpu_has_load_ia32_efer) {
1296 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1297 VM_EXIT_LOAD_IA32_EFER,
1298 GUEST_IA32_EFER,
1299 HOST_IA32_EFER,
1300 guest_val, host_val);
1301 return;
1302 }
1303 break;
1304 case MSR_CORE_PERF_GLOBAL_CTRL:
1305 if (cpu_has_load_perf_global_ctrl) {
1306 add_atomic_switch_msr_special(
1307 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1308 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1309 GUEST_IA32_PERF_GLOBAL_CTRL,
1310 HOST_IA32_PERF_GLOBAL_CTRL,
1311 guest_val, host_val);
1312 return;
1313 }
1314 break;
1315 }
1316
1317 for (i = 0; i < m->nr; ++i)
1318 if (m->guest[i].index == msr)
1319 break;
1320
1321 if (i == NR_AUTOLOAD_MSRS) {
1322 printk_once(KERN_WARNING"Not enough mst switch entries. "
1323 "Can't add msr %x\n", msr);
1324 return;
1325 } else if (i == m->nr) {
1326 ++m->nr;
1327 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1328 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1329 }
1330
1331 m->guest[i].index = msr;
1332 m->guest[i].value = guest_val;
1333 m->host[i].index = msr;
1334 m->host[i].value = host_val;
1335 }
1336
1337 static void reload_tss(void)
1338 {
1339 /*
1340 * VT restores TR but not its size. Useless.
1341 */
1342 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1343 struct desc_struct *descs;
1344
1345 descs = (void *)gdt->address;
1346 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1347 load_TR_desc();
1348 }
1349
1350 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1351 {
1352 u64 guest_efer;
1353 u64 ignore_bits;
1354
1355 guest_efer = vmx->vcpu.arch.efer;
1356
1357 /*
1358 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1359 * outside long mode
1360 */
1361 ignore_bits = EFER_NX | EFER_SCE;
1362 #ifdef CONFIG_X86_64
1363 ignore_bits |= EFER_LMA | EFER_LME;
1364 /* SCE is meaningful only in long mode on Intel */
1365 if (guest_efer & EFER_LMA)
1366 ignore_bits &= ~(u64)EFER_SCE;
1367 #endif
1368 guest_efer &= ~ignore_bits;
1369 guest_efer |= host_efer & ignore_bits;
1370 vmx->guest_msrs[efer_offset].data = guest_efer;
1371 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1372
1373 clear_atomic_switch_msr(vmx, MSR_EFER);
1374 /* On ept, can't emulate nx, and must switch nx atomically */
1375 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1376 guest_efer = vmx->vcpu.arch.efer;
1377 if (!(guest_efer & EFER_LMA))
1378 guest_efer &= ~EFER_LME;
1379 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1380 return false;
1381 }
1382
1383 return true;
1384 }
1385
1386 static unsigned long segment_base(u16 selector)
1387 {
1388 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1389 struct desc_struct *d;
1390 unsigned long table_base;
1391 unsigned long v;
1392
1393 if (!(selector & ~3))
1394 return 0;
1395
1396 table_base = gdt->address;
1397
1398 if (selector & 4) { /* from ldt */
1399 u16 ldt_selector = kvm_read_ldt();
1400
1401 if (!(ldt_selector & ~3))
1402 return 0;
1403
1404 table_base = segment_base(ldt_selector);
1405 }
1406 d = (struct desc_struct *)(table_base + (selector & ~7));
1407 v = get_desc_base(d);
1408 #ifdef CONFIG_X86_64
1409 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1410 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1411 #endif
1412 return v;
1413 }
1414
1415 static inline unsigned long kvm_read_tr_base(void)
1416 {
1417 u16 tr;
1418 asm("str %0" : "=g"(tr));
1419 return segment_base(tr);
1420 }
1421
1422 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1423 {
1424 struct vcpu_vmx *vmx = to_vmx(vcpu);
1425 int i;
1426
1427 if (vmx->host_state.loaded)
1428 return;
1429
1430 vmx->host_state.loaded = 1;
1431 /*
1432 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1433 * allow segment selectors with cpl > 0 or ti == 1.
1434 */
1435 vmx->host_state.ldt_sel = kvm_read_ldt();
1436 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1437 savesegment(fs, vmx->host_state.fs_sel);
1438 if (!(vmx->host_state.fs_sel & 7)) {
1439 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1440 vmx->host_state.fs_reload_needed = 0;
1441 } else {
1442 vmcs_write16(HOST_FS_SELECTOR, 0);
1443 vmx->host_state.fs_reload_needed = 1;
1444 }
1445 savesegment(gs, vmx->host_state.gs_sel);
1446 if (!(vmx->host_state.gs_sel & 7))
1447 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1448 else {
1449 vmcs_write16(HOST_GS_SELECTOR, 0);
1450 vmx->host_state.gs_ldt_reload_needed = 1;
1451 }
1452
1453 #ifdef CONFIG_X86_64
1454 savesegment(ds, vmx->host_state.ds_sel);
1455 savesegment(es, vmx->host_state.es_sel);
1456 #endif
1457
1458 #ifdef CONFIG_X86_64
1459 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1460 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1461 #else
1462 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1463 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1464 #endif
1465
1466 #ifdef CONFIG_X86_64
1467 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1468 if (is_long_mode(&vmx->vcpu))
1469 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1470 #endif
1471 for (i = 0; i < vmx->save_nmsrs; ++i)
1472 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1473 vmx->guest_msrs[i].data,
1474 vmx->guest_msrs[i].mask);
1475 }
1476
1477 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1478 {
1479 if (!vmx->host_state.loaded)
1480 return;
1481
1482 ++vmx->vcpu.stat.host_state_reload;
1483 vmx->host_state.loaded = 0;
1484 #ifdef CONFIG_X86_64
1485 if (is_long_mode(&vmx->vcpu))
1486 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1487 #endif
1488 if (vmx->host_state.gs_ldt_reload_needed) {
1489 kvm_load_ldt(vmx->host_state.ldt_sel);
1490 #ifdef CONFIG_X86_64
1491 load_gs_index(vmx->host_state.gs_sel);
1492 #else
1493 loadsegment(gs, vmx->host_state.gs_sel);
1494 #endif
1495 }
1496 if (vmx->host_state.fs_reload_needed)
1497 loadsegment(fs, vmx->host_state.fs_sel);
1498 #ifdef CONFIG_X86_64
1499 if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1500 loadsegment(ds, vmx->host_state.ds_sel);
1501 loadsegment(es, vmx->host_state.es_sel);
1502 }
1503 #endif
1504 reload_tss();
1505 #ifdef CONFIG_X86_64
1506 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1507 #endif
1508 /*
1509 * If the FPU is not active (through the host task or
1510 * the guest vcpu), then restore the cr0.TS bit.
1511 */
1512 if (!user_has_fpu() && !vmx->vcpu.guest_fpu_loaded)
1513 stts();
1514 load_gdt(&__get_cpu_var(host_gdt));
1515 }
1516
1517 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1518 {
1519 preempt_disable();
1520 __vmx_load_host_state(vmx);
1521 preempt_enable();
1522 }
1523
1524 /*
1525 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1526 * vcpu mutex is already taken.
1527 */
1528 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1529 {
1530 struct vcpu_vmx *vmx = to_vmx(vcpu);
1531 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1532
1533 if (!vmm_exclusive)
1534 kvm_cpu_vmxon(phys_addr);
1535 else if (vmx->loaded_vmcs->cpu != cpu)
1536 loaded_vmcs_clear(vmx->loaded_vmcs);
1537
1538 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1539 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1540 vmcs_load(vmx->loaded_vmcs->vmcs);
1541 }
1542
1543 if (vmx->loaded_vmcs->cpu != cpu) {
1544 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1545 unsigned long sysenter_esp;
1546
1547 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1548 local_irq_disable();
1549
1550 /*
1551 * Read loaded_vmcs->cpu should be before fetching
1552 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1553 * See the comments in __loaded_vmcs_clear().
1554 */
1555 smp_rmb();
1556
1557 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1558 &per_cpu(loaded_vmcss_on_cpu, cpu));
1559 local_irq_enable();
1560
1561 /*
1562 * Linux uses per-cpu TSS and GDT, so set these when switching
1563 * processors.
1564 */
1565 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1566 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1567
1568 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1569 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1570 vmx->loaded_vmcs->cpu = cpu;
1571 }
1572 }
1573
1574 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1575 {
1576 __vmx_load_host_state(to_vmx(vcpu));
1577 if (!vmm_exclusive) {
1578 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1579 vcpu->cpu = -1;
1580 kvm_cpu_vmxoff();
1581 }
1582 }
1583
1584 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1585 {
1586 ulong cr0;
1587
1588 if (vcpu->fpu_active)
1589 return;
1590 vcpu->fpu_active = 1;
1591 cr0 = vmcs_readl(GUEST_CR0);
1592 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1593 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1594 vmcs_writel(GUEST_CR0, cr0);
1595 update_exception_bitmap(vcpu);
1596 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1597 if (is_guest_mode(vcpu))
1598 vcpu->arch.cr0_guest_owned_bits &=
1599 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1600 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1601 }
1602
1603 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1604
1605 /*
1606 * Return the cr0 value that a nested guest would read. This is a combination
1607 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1608 * its hypervisor (cr0_read_shadow).
1609 */
1610 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1611 {
1612 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1613 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1614 }
1615 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1616 {
1617 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1618 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1619 }
1620
1621 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1622 {
1623 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1624 * set this *before* calling this function.
1625 */
1626 vmx_decache_cr0_guest_bits(vcpu);
1627 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1628 update_exception_bitmap(vcpu);
1629 vcpu->arch.cr0_guest_owned_bits = 0;
1630 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1631 if (is_guest_mode(vcpu)) {
1632 /*
1633 * L1's specified read shadow might not contain the TS bit,
1634 * so now that we turned on shadowing of this bit, we need to
1635 * set this bit of the shadow. Like in nested_vmx_run we need
1636 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1637 * up-to-date here because we just decached cr0.TS (and we'll
1638 * only update vmcs12->guest_cr0 on nested exit).
1639 */
1640 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1641 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1642 (vcpu->arch.cr0 & X86_CR0_TS);
1643 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1644 } else
1645 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1646 }
1647
1648 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1649 {
1650 unsigned long rflags, save_rflags;
1651
1652 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1653 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1654 rflags = vmcs_readl(GUEST_RFLAGS);
1655 if (to_vmx(vcpu)->rmode.vm86_active) {
1656 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1657 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1658 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1659 }
1660 to_vmx(vcpu)->rflags = rflags;
1661 }
1662 return to_vmx(vcpu)->rflags;
1663 }
1664
1665 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1666 {
1667 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1668 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1669 to_vmx(vcpu)->rflags = rflags;
1670 if (to_vmx(vcpu)->rmode.vm86_active) {
1671 to_vmx(vcpu)->rmode.save_rflags = rflags;
1672 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1673 }
1674 vmcs_writel(GUEST_RFLAGS, rflags);
1675 }
1676
1677 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1678 {
1679 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1680 int ret = 0;
1681
1682 if (interruptibility & GUEST_INTR_STATE_STI)
1683 ret |= KVM_X86_SHADOW_INT_STI;
1684 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1685 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1686
1687 return ret & mask;
1688 }
1689
1690 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1691 {
1692 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1693 u32 interruptibility = interruptibility_old;
1694
1695 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1696
1697 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1698 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1699 else if (mask & KVM_X86_SHADOW_INT_STI)
1700 interruptibility |= GUEST_INTR_STATE_STI;
1701
1702 if ((interruptibility != interruptibility_old))
1703 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1704 }
1705
1706 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1707 {
1708 unsigned long rip;
1709
1710 rip = kvm_rip_read(vcpu);
1711 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1712 kvm_rip_write(vcpu, rip);
1713
1714 /* skipping an emulated instruction also counts */
1715 vmx_set_interrupt_shadow(vcpu, 0);
1716 }
1717
1718 /*
1719 * KVM wants to inject page-faults which it got to the guest. This function
1720 * checks whether in a nested guest, we need to inject them to L1 or L2.
1721 * This function assumes it is called with the exit reason in vmcs02 being
1722 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1723 * is running).
1724 */
1725 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1726 {
1727 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1728
1729 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1730 if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1731 return 0;
1732
1733 nested_vmx_vmexit(vcpu);
1734 return 1;
1735 }
1736
1737 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1738 bool has_error_code, u32 error_code,
1739 bool reinject)
1740 {
1741 struct vcpu_vmx *vmx = to_vmx(vcpu);
1742 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1743
1744 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1745 nested_pf_handled(vcpu))
1746 return;
1747
1748 if (has_error_code) {
1749 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1750 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1751 }
1752
1753 if (vmx->rmode.vm86_active) {
1754 int inc_eip = 0;
1755 if (kvm_exception_is_soft(nr))
1756 inc_eip = vcpu->arch.event_exit_inst_len;
1757 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1758 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1759 return;
1760 }
1761
1762 if (kvm_exception_is_soft(nr)) {
1763 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1764 vmx->vcpu.arch.event_exit_inst_len);
1765 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1766 } else
1767 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1768
1769 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1770 }
1771
1772 static bool vmx_rdtscp_supported(void)
1773 {
1774 return cpu_has_vmx_rdtscp();
1775 }
1776
1777 static bool vmx_invpcid_supported(void)
1778 {
1779 return cpu_has_vmx_invpcid() && enable_ept;
1780 }
1781
1782 /*
1783 * Swap MSR entry in host/guest MSR entry array.
1784 */
1785 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1786 {
1787 struct shared_msr_entry tmp;
1788
1789 tmp = vmx->guest_msrs[to];
1790 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1791 vmx->guest_msrs[from] = tmp;
1792 }
1793
1794 /*
1795 * Set up the vmcs to automatically save and restore system
1796 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1797 * mode, as fiddling with msrs is very expensive.
1798 */
1799 static void setup_msrs(struct vcpu_vmx *vmx)
1800 {
1801 int save_nmsrs, index;
1802 unsigned long *msr_bitmap;
1803
1804 save_nmsrs = 0;
1805 #ifdef CONFIG_X86_64
1806 if (is_long_mode(&vmx->vcpu)) {
1807 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1808 if (index >= 0)
1809 move_msr_up(vmx, index, save_nmsrs++);
1810 index = __find_msr_index(vmx, MSR_LSTAR);
1811 if (index >= 0)
1812 move_msr_up(vmx, index, save_nmsrs++);
1813 index = __find_msr_index(vmx, MSR_CSTAR);
1814 if (index >= 0)
1815 move_msr_up(vmx, index, save_nmsrs++);
1816 index = __find_msr_index(vmx, MSR_TSC_AUX);
1817 if (index >= 0 && vmx->rdtscp_enabled)
1818 move_msr_up(vmx, index, save_nmsrs++);
1819 /*
1820 * MSR_STAR is only needed on long mode guests, and only
1821 * if efer.sce is enabled.
1822 */
1823 index = __find_msr_index(vmx, MSR_STAR);
1824 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1825 move_msr_up(vmx, index, save_nmsrs++);
1826 }
1827 #endif
1828 index = __find_msr_index(vmx, MSR_EFER);
1829 if (index >= 0 && update_transition_efer(vmx, index))
1830 move_msr_up(vmx, index, save_nmsrs++);
1831
1832 vmx->save_nmsrs = save_nmsrs;
1833
1834 if (cpu_has_vmx_msr_bitmap()) {
1835 if (is_long_mode(&vmx->vcpu))
1836 msr_bitmap = vmx_msr_bitmap_longmode;
1837 else
1838 msr_bitmap = vmx_msr_bitmap_legacy;
1839
1840 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1841 }
1842 }
1843
1844 /*
1845 * reads and returns guest's timestamp counter "register"
1846 * guest_tsc = host_tsc + tsc_offset -- 21.3
1847 */
1848 static u64 guest_read_tsc(void)
1849 {
1850 u64 host_tsc, tsc_offset;
1851
1852 rdtscll(host_tsc);
1853 tsc_offset = vmcs_read64(TSC_OFFSET);
1854 return host_tsc + tsc_offset;
1855 }
1856
1857 /*
1858 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1859 * counter, even if a nested guest (L2) is currently running.
1860 */
1861 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
1862 {
1863 u64 tsc_offset;
1864
1865 tsc_offset = is_guest_mode(vcpu) ?
1866 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1867 vmcs_read64(TSC_OFFSET);
1868 return host_tsc + tsc_offset;
1869 }
1870
1871 /*
1872 * Engage any workarounds for mis-matched TSC rates. Currently limited to
1873 * software catchup for faster rates on slower CPUs.
1874 */
1875 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
1876 {
1877 if (!scale)
1878 return;
1879
1880 if (user_tsc_khz > tsc_khz) {
1881 vcpu->arch.tsc_catchup = 1;
1882 vcpu->arch.tsc_always_catchup = 1;
1883 } else
1884 WARN(1, "user requested TSC rate below hardware speed\n");
1885 }
1886
1887 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
1888 {
1889 return vmcs_read64(TSC_OFFSET);
1890 }
1891
1892 /*
1893 * writes 'offset' into guest's timestamp counter offset register
1894 */
1895 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1896 {
1897 if (is_guest_mode(vcpu)) {
1898 /*
1899 * We're here if L1 chose not to trap WRMSR to TSC. According
1900 * to the spec, this should set L1's TSC; The offset that L1
1901 * set for L2 remains unchanged, and still needs to be added
1902 * to the newly set TSC to get L2's TSC.
1903 */
1904 struct vmcs12 *vmcs12;
1905 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1906 /* recalculate vmcs02.TSC_OFFSET: */
1907 vmcs12 = get_vmcs12(vcpu);
1908 vmcs_write64(TSC_OFFSET, offset +
1909 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1910 vmcs12->tsc_offset : 0));
1911 } else {
1912 vmcs_write64(TSC_OFFSET, offset);
1913 }
1914 }
1915
1916 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
1917 {
1918 u64 offset = vmcs_read64(TSC_OFFSET);
1919 vmcs_write64(TSC_OFFSET, offset + adjustment);
1920 if (is_guest_mode(vcpu)) {
1921 /* Even when running L2, the adjustment needs to apply to L1 */
1922 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1923 }
1924 }
1925
1926 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1927 {
1928 return target_tsc - native_read_tsc();
1929 }
1930
1931 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1932 {
1933 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1934 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1935 }
1936
1937 /*
1938 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1939 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1940 * all guests if the "nested" module option is off, and can also be disabled
1941 * for a single guest by disabling its VMX cpuid bit.
1942 */
1943 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1944 {
1945 return nested && guest_cpuid_has_vmx(vcpu);
1946 }
1947
1948 /*
1949 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1950 * returned for the various VMX controls MSRs when nested VMX is enabled.
1951 * The same values should also be used to verify that vmcs12 control fields are
1952 * valid during nested entry from L1 to L2.
1953 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1954 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1955 * bit in the high half is on if the corresponding bit in the control field
1956 * may be on. See also vmx_control_verify().
1957 * TODO: allow these variables to be modified (downgraded) by module options
1958 * or other means.
1959 */
1960 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1961 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1962 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1963 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1964 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1965 static __init void nested_vmx_setup_ctls_msrs(void)
1966 {
1967 /*
1968 * Note that as a general rule, the high half of the MSRs (bits in
1969 * the control fields which may be 1) should be initialized by the
1970 * intersection of the underlying hardware's MSR (i.e., features which
1971 * can be supported) and the list of features we want to expose -
1972 * because they are known to be properly supported in our code.
1973 * Also, usually, the low half of the MSRs (bits which must be 1) can
1974 * be set to 0, meaning that L1 may turn off any of these bits. The
1975 * reason is that if one of these bits is necessary, it will appear
1976 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1977 * fields of vmcs01 and vmcs02, will turn these bits off - and
1978 * nested_vmx_exit_handled() will not pass related exits to L1.
1979 * These rules have exceptions below.
1980 */
1981
1982 /* pin-based controls */
1983 /*
1984 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1985 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1986 */
1987 nested_vmx_pinbased_ctls_low = 0x16 ;
1988 nested_vmx_pinbased_ctls_high = 0x16 |
1989 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1990 PIN_BASED_VIRTUAL_NMIS;
1991
1992 /* exit controls */
1993 nested_vmx_exit_ctls_low = 0;
1994 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1995 #ifdef CONFIG_X86_64
1996 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1997 #else
1998 nested_vmx_exit_ctls_high = 0;
1999 #endif
2000
2001 /* entry controls */
2002 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2003 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
2004 nested_vmx_entry_ctls_low = 0;
2005 nested_vmx_entry_ctls_high &=
2006 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
2007
2008 /* cpu-based controls */
2009 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2010 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
2011 nested_vmx_procbased_ctls_low = 0;
2012 nested_vmx_procbased_ctls_high &=
2013 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2014 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2015 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2016 CPU_BASED_CR3_STORE_EXITING |
2017 #ifdef CONFIG_X86_64
2018 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2019 #endif
2020 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2021 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
2022 CPU_BASED_RDPMC_EXITING | CPU_BASED_RDTSC_EXITING |
2023 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2024 /*
2025 * We can allow some features even when not supported by the
2026 * hardware. For example, L1 can specify an MSR bitmap - and we
2027 * can use it to avoid exits to L1 - even when L0 runs L2
2028 * without MSR bitmaps.
2029 */
2030 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
2031
2032 /* secondary cpu-based controls */
2033 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2034 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
2035 nested_vmx_secondary_ctls_low = 0;
2036 nested_vmx_secondary_ctls_high &=
2037 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2038 }
2039
2040 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2041 {
2042 /*
2043 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2044 */
2045 return ((control & high) | low) == control;
2046 }
2047
2048 static inline u64 vmx_control_msr(u32 low, u32 high)
2049 {
2050 return low | ((u64)high << 32);
2051 }
2052
2053 /*
2054 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
2055 * also let it use VMX-specific MSRs.
2056 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
2057 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
2058 * like all other MSRs).
2059 */
2060 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2061 {
2062 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
2063 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2064 /*
2065 * According to the spec, processors which do not support VMX
2066 * should throw a #GP(0) when VMX capability MSRs are read.
2067 */
2068 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2069 return 1;
2070 }
2071
2072 switch (msr_index) {
2073 case MSR_IA32_FEATURE_CONTROL:
2074 *pdata = 0;
2075 break;
2076 case MSR_IA32_VMX_BASIC:
2077 /*
2078 * This MSR reports some information about VMX support. We
2079 * should return information about the VMX we emulate for the
2080 * guest, and the VMCS structure we give it - not about the
2081 * VMX support of the underlying hardware.
2082 */
2083 *pdata = VMCS12_REVISION |
2084 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2085 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2086 break;
2087 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2088 case MSR_IA32_VMX_PINBASED_CTLS:
2089 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2090 nested_vmx_pinbased_ctls_high);
2091 break;
2092 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2093 case MSR_IA32_VMX_PROCBASED_CTLS:
2094 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2095 nested_vmx_procbased_ctls_high);
2096 break;
2097 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2098 case MSR_IA32_VMX_EXIT_CTLS:
2099 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2100 nested_vmx_exit_ctls_high);
2101 break;
2102 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2103 case MSR_IA32_VMX_ENTRY_CTLS:
2104 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2105 nested_vmx_entry_ctls_high);
2106 break;
2107 case MSR_IA32_VMX_MISC:
2108 *pdata = 0;
2109 break;
2110 /*
2111 * These MSRs specify bits which the guest must keep fixed (on or off)
2112 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2113 * We picked the standard core2 setting.
2114 */
2115 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2116 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2117 case MSR_IA32_VMX_CR0_FIXED0:
2118 *pdata = VMXON_CR0_ALWAYSON;
2119 break;
2120 case MSR_IA32_VMX_CR0_FIXED1:
2121 *pdata = -1ULL;
2122 break;
2123 case MSR_IA32_VMX_CR4_FIXED0:
2124 *pdata = VMXON_CR4_ALWAYSON;
2125 break;
2126 case MSR_IA32_VMX_CR4_FIXED1:
2127 *pdata = -1ULL;
2128 break;
2129 case MSR_IA32_VMX_VMCS_ENUM:
2130 *pdata = 0x1f;
2131 break;
2132 case MSR_IA32_VMX_PROCBASED_CTLS2:
2133 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2134 nested_vmx_secondary_ctls_high);
2135 break;
2136 case MSR_IA32_VMX_EPT_VPID_CAP:
2137 /* Currently, no nested ept or nested vpid */
2138 *pdata = 0;
2139 break;
2140 default:
2141 return 0;
2142 }
2143
2144 return 1;
2145 }
2146
2147 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2148 {
2149 if (!nested_vmx_allowed(vcpu))
2150 return 0;
2151
2152 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2153 /* TODO: the right thing. */
2154 return 1;
2155 /*
2156 * No need to treat VMX capability MSRs specially: If we don't handle
2157 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2158 */
2159 return 0;
2160 }
2161
2162 /*
2163 * Reads an msr value (of 'msr_index') into 'pdata'.
2164 * Returns 0 on success, non-0 otherwise.
2165 * Assumes vcpu_load() was already called.
2166 */
2167 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2168 {
2169 u64 data;
2170 struct shared_msr_entry *msr;
2171
2172 if (!pdata) {
2173 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2174 return -EINVAL;
2175 }
2176
2177 switch (msr_index) {
2178 #ifdef CONFIG_X86_64
2179 case MSR_FS_BASE:
2180 data = vmcs_readl(GUEST_FS_BASE);
2181 break;
2182 case MSR_GS_BASE:
2183 data = vmcs_readl(GUEST_GS_BASE);
2184 break;
2185 case MSR_KERNEL_GS_BASE:
2186 vmx_load_host_state(to_vmx(vcpu));
2187 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2188 break;
2189 #endif
2190 case MSR_EFER:
2191 return kvm_get_msr_common(vcpu, msr_index, pdata);
2192 case MSR_IA32_TSC:
2193 data = guest_read_tsc();
2194 break;
2195 case MSR_IA32_SYSENTER_CS:
2196 data = vmcs_read32(GUEST_SYSENTER_CS);
2197 break;
2198 case MSR_IA32_SYSENTER_EIP:
2199 data = vmcs_readl(GUEST_SYSENTER_EIP);
2200 break;
2201 case MSR_IA32_SYSENTER_ESP:
2202 data = vmcs_readl(GUEST_SYSENTER_ESP);
2203 break;
2204 case MSR_TSC_AUX:
2205 if (!to_vmx(vcpu)->rdtscp_enabled)
2206 return 1;
2207 /* Otherwise falls through */
2208 default:
2209 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2210 return 0;
2211 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2212 if (msr) {
2213 data = msr->data;
2214 break;
2215 }
2216 return kvm_get_msr_common(vcpu, msr_index, pdata);
2217 }
2218
2219 *pdata = data;
2220 return 0;
2221 }
2222
2223 /*
2224 * Writes msr value into into the appropriate "register".
2225 * Returns 0 on success, non-0 otherwise.
2226 * Assumes vcpu_load() was already called.
2227 */
2228 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2229 {
2230 struct vcpu_vmx *vmx = to_vmx(vcpu);
2231 struct shared_msr_entry *msr;
2232 int ret = 0;
2233 u32 msr_index = msr_info->index;
2234 u64 data = msr_info->data;
2235
2236 switch (msr_index) {
2237 case MSR_EFER:
2238 ret = kvm_set_msr_common(vcpu, msr_info);
2239 break;
2240 #ifdef CONFIG_X86_64
2241 case MSR_FS_BASE:
2242 vmx_segment_cache_clear(vmx);
2243 vmcs_writel(GUEST_FS_BASE, data);
2244 break;
2245 case MSR_GS_BASE:
2246 vmx_segment_cache_clear(vmx);
2247 vmcs_writel(GUEST_GS_BASE, data);
2248 break;
2249 case MSR_KERNEL_GS_BASE:
2250 vmx_load_host_state(vmx);
2251 vmx->msr_guest_kernel_gs_base = data;
2252 break;
2253 #endif
2254 case MSR_IA32_SYSENTER_CS:
2255 vmcs_write32(GUEST_SYSENTER_CS, data);
2256 break;
2257 case MSR_IA32_SYSENTER_EIP:
2258 vmcs_writel(GUEST_SYSENTER_EIP, data);
2259 break;
2260 case MSR_IA32_SYSENTER_ESP:
2261 vmcs_writel(GUEST_SYSENTER_ESP, data);
2262 break;
2263 case MSR_IA32_TSC:
2264 kvm_write_tsc(vcpu, msr_info);
2265 break;
2266 case MSR_IA32_CR_PAT:
2267 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2268 vmcs_write64(GUEST_IA32_PAT, data);
2269 vcpu->arch.pat = data;
2270 break;
2271 }
2272 ret = kvm_set_msr_common(vcpu, msr_info);
2273 break;
2274 case MSR_IA32_TSC_ADJUST:
2275 ret = kvm_set_msr_common(vcpu, msr_info);
2276 break;
2277 case MSR_TSC_AUX:
2278 if (!vmx->rdtscp_enabled)
2279 return 1;
2280 /* Check reserved bit, higher 32 bits should be zero */
2281 if ((data >> 32) != 0)
2282 return 1;
2283 /* Otherwise falls through */
2284 default:
2285 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2286 break;
2287 msr = find_msr_entry(vmx, msr_index);
2288 if (msr) {
2289 msr->data = data;
2290 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2291 preempt_disable();
2292 kvm_set_shared_msr(msr->index, msr->data,
2293 msr->mask);
2294 preempt_enable();
2295 }
2296 break;
2297 }
2298 ret = kvm_set_msr_common(vcpu, msr_info);
2299 }
2300
2301 return ret;
2302 }
2303
2304 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2305 {
2306 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2307 switch (reg) {
2308 case VCPU_REGS_RSP:
2309 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2310 break;
2311 case VCPU_REGS_RIP:
2312 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2313 break;
2314 case VCPU_EXREG_PDPTR:
2315 if (enable_ept)
2316 ept_save_pdptrs(vcpu);
2317 break;
2318 default:
2319 break;
2320 }
2321 }
2322
2323 static __init int cpu_has_kvm_support(void)
2324 {
2325 return cpu_has_vmx();
2326 }
2327
2328 static __init int vmx_disabled_by_bios(void)
2329 {
2330 u64 msr;
2331
2332 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2333 if (msr & FEATURE_CONTROL_LOCKED) {
2334 /* launched w/ TXT and VMX disabled */
2335 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2336 && tboot_enabled())
2337 return 1;
2338 /* launched w/o TXT and VMX only enabled w/ TXT */
2339 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2340 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2341 && !tboot_enabled()) {
2342 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2343 "activate TXT before enabling KVM\n");
2344 return 1;
2345 }
2346 /* launched w/o TXT and VMX disabled */
2347 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2348 && !tboot_enabled())
2349 return 1;
2350 }
2351
2352 return 0;
2353 }
2354
2355 static void kvm_cpu_vmxon(u64 addr)
2356 {
2357 asm volatile (ASM_VMX_VMXON_RAX
2358 : : "a"(&addr), "m"(addr)
2359 : "memory", "cc");
2360 }
2361
2362 static int hardware_enable(void *garbage)
2363 {
2364 int cpu = raw_smp_processor_id();
2365 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2366 u64 old, test_bits;
2367
2368 if (read_cr4() & X86_CR4_VMXE)
2369 return -EBUSY;
2370
2371 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2372 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2373
2374 test_bits = FEATURE_CONTROL_LOCKED;
2375 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2376 if (tboot_enabled())
2377 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2378
2379 if ((old & test_bits) != test_bits) {
2380 /* enable and lock */
2381 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2382 }
2383 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2384
2385 if (vmm_exclusive) {
2386 kvm_cpu_vmxon(phys_addr);
2387 ept_sync_global();
2388 }
2389
2390 store_gdt(&__get_cpu_var(host_gdt));
2391
2392 return 0;
2393 }
2394
2395 static void vmclear_local_loaded_vmcss(void)
2396 {
2397 int cpu = raw_smp_processor_id();
2398 struct loaded_vmcs *v, *n;
2399
2400 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2401 loaded_vmcss_on_cpu_link)
2402 __loaded_vmcs_clear(v);
2403 }
2404
2405
2406 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2407 * tricks.
2408 */
2409 static void kvm_cpu_vmxoff(void)
2410 {
2411 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2412 }
2413
2414 static void hardware_disable(void *garbage)
2415 {
2416 if (vmm_exclusive) {
2417 vmclear_local_loaded_vmcss();
2418 kvm_cpu_vmxoff();
2419 }
2420 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2421 }
2422
2423 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2424 u32 msr, u32 *result)
2425 {
2426 u32 vmx_msr_low, vmx_msr_high;
2427 u32 ctl = ctl_min | ctl_opt;
2428
2429 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2430
2431 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2432 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2433
2434 /* Ensure minimum (required) set of control bits are supported. */
2435 if (ctl_min & ~ctl)
2436 return -EIO;
2437
2438 *result = ctl;
2439 return 0;
2440 }
2441
2442 static __init bool allow_1_setting(u32 msr, u32 ctl)
2443 {
2444 u32 vmx_msr_low, vmx_msr_high;
2445
2446 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2447 return vmx_msr_high & ctl;
2448 }
2449
2450 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2451 {
2452 u32 vmx_msr_low, vmx_msr_high;
2453 u32 min, opt, min2, opt2;
2454 u32 _pin_based_exec_control = 0;
2455 u32 _cpu_based_exec_control = 0;
2456 u32 _cpu_based_2nd_exec_control = 0;
2457 u32 _vmexit_control = 0;
2458 u32 _vmentry_control = 0;
2459
2460 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2461 opt = PIN_BASED_VIRTUAL_NMIS;
2462 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2463 &_pin_based_exec_control) < 0)
2464 return -EIO;
2465
2466 min = CPU_BASED_HLT_EXITING |
2467 #ifdef CONFIG_X86_64
2468 CPU_BASED_CR8_LOAD_EXITING |
2469 CPU_BASED_CR8_STORE_EXITING |
2470 #endif
2471 CPU_BASED_CR3_LOAD_EXITING |
2472 CPU_BASED_CR3_STORE_EXITING |
2473 CPU_BASED_USE_IO_BITMAPS |
2474 CPU_BASED_MOV_DR_EXITING |
2475 CPU_BASED_USE_TSC_OFFSETING |
2476 CPU_BASED_MWAIT_EXITING |
2477 CPU_BASED_MONITOR_EXITING |
2478 CPU_BASED_INVLPG_EXITING |
2479 CPU_BASED_RDPMC_EXITING;
2480
2481 opt = CPU_BASED_TPR_SHADOW |
2482 CPU_BASED_USE_MSR_BITMAPS |
2483 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2484 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2485 &_cpu_based_exec_control) < 0)
2486 return -EIO;
2487 #ifdef CONFIG_X86_64
2488 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2489 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2490 ~CPU_BASED_CR8_STORE_EXITING;
2491 #endif
2492 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2493 min2 = 0;
2494 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2495 SECONDARY_EXEC_WBINVD_EXITING |
2496 SECONDARY_EXEC_ENABLE_VPID |
2497 SECONDARY_EXEC_ENABLE_EPT |
2498 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2499 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2500 SECONDARY_EXEC_RDTSCP |
2501 SECONDARY_EXEC_ENABLE_INVPCID;
2502 if (adjust_vmx_controls(min2, opt2,
2503 MSR_IA32_VMX_PROCBASED_CTLS2,
2504 &_cpu_based_2nd_exec_control) < 0)
2505 return -EIO;
2506 }
2507 #ifndef CONFIG_X86_64
2508 if (!(_cpu_based_2nd_exec_control &
2509 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2510 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2511 #endif
2512 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2513 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2514 enabled */
2515 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2516 CPU_BASED_CR3_STORE_EXITING |
2517 CPU_BASED_INVLPG_EXITING);
2518 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2519 vmx_capability.ept, vmx_capability.vpid);
2520 }
2521
2522 min = 0;
2523 #ifdef CONFIG_X86_64
2524 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2525 #endif
2526 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2527 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2528 &_vmexit_control) < 0)
2529 return -EIO;
2530
2531 min = 0;
2532 opt = VM_ENTRY_LOAD_IA32_PAT;
2533 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2534 &_vmentry_control) < 0)
2535 return -EIO;
2536
2537 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2538
2539 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2540 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2541 return -EIO;
2542
2543 #ifdef CONFIG_X86_64
2544 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2545 if (vmx_msr_high & (1u<<16))
2546 return -EIO;
2547 #endif
2548
2549 /* Require Write-Back (WB) memory type for VMCS accesses. */
2550 if (((vmx_msr_high >> 18) & 15) != 6)
2551 return -EIO;
2552
2553 vmcs_conf->size = vmx_msr_high & 0x1fff;
2554 vmcs_conf->order = get_order(vmcs_config.size);
2555 vmcs_conf->revision_id = vmx_msr_low;
2556
2557 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2558 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2559 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2560 vmcs_conf->vmexit_ctrl = _vmexit_control;
2561 vmcs_conf->vmentry_ctrl = _vmentry_control;
2562
2563 cpu_has_load_ia32_efer =
2564 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2565 VM_ENTRY_LOAD_IA32_EFER)
2566 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2567 VM_EXIT_LOAD_IA32_EFER);
2568
2569 cpu_has_load_perf_global_ctrl =
2570 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2571 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2572 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2573 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2574
2575 /*
2576 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2577 * but due to arrata below it can't be used. Workaround is to use
2578 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2579 *
2580 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2581 *
2582 * AAK155 (model 26)
2583 * AAP115 (model 30)
2584 * AAT100 (model 37)
2585 * BC86,AAY89,BD102 (model 44)
2586 * BA97 (model 46)
2587 *
2588 */
2589 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2590 switch (boot_cpu_data.x86_model) {
2591 case 26:
2592 case 30:
2593 case 37:
2594 case 44:
2595 case 46:
2596 cpu_has_load_perf_global_ctrl = false;
2597 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2598 "does not work properly. Using workaround\n");
2599 break;
2600 default:
2601 break;
2602 }
2603 }
2604
2605 return 0;
2606 }
2607
2608 static struct vmcs *alloc_vmcs_cpu(int cpu)
2609 {
2610 int node = cpu_to_node(cpu);
2611 struct page *pages;
2612 struct vmcs *vmcs;
2613
2614 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2615 if (!pages)
2616 return NULL;
2617 vmcs = page_address(pages);
2618 memset(vmcs, 0, vmcs_config.size);
2619 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2620 return vmcs;
2621 }
2622
2623 static struct vmcs *alloc_vmcs(void)
2624 {
2625 return alloc_vmcs_cpu(raw_smp_processor_id());
2626 }
2627
2628 static void free_vmcs(struct vmcs *vmcs)
2629 {
2630 free_pages((unsigned long)vmcs, vmcs_config.order);
2631 }
2632
2633 /*
2634 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2635 */
2636 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2637 {
2638 if (!loaded_vmcs->vmcs)
2639 return;
2640 loaded_vmcs_clear(loaded_vmcs);
2641 free_vmcs(loaded_vmcs->vmcs);
2642 loaded_vmcs->vmcs = NULL;
2643 }
2644
2645 static void free_kvm_area(void)
2646 {
2647 int cpu;
2648
2649 for_each_possible_cpu(cpu) {
2650 free_vmcs(per_cpu(vmxarea, cpu));
2651 per_cpu(vmxarea, cpu) = NULL;
2652 }
2653 }
2654
2655 static __init int alloc_kvm_area(void)
2656 {
2657 int cpu;
2658
2659 for_each_possible_cpu(cpu) {
2660 struct vmcs *vmcs;
2661
2662 vmcs = alloc_vmcs_cpu(cpu);
2663 if (!vmcs) {
2664 free_kvm_area();
2665 return -ENOMEM;
2666 }
2667
2668 per_cpu(vmxarea, cpu) = vmcs;
2669 }
2670 return 0;
2671 }
2672
2673 static __init int hardware_setup(void)
2674 {
2675 if (setup_vmcs_config(&vmcs_config) < 0)
2676 return -EIO;
2677
2678 if (boot_cpu_has(X86_FEATURE_NX))
2679 kvm_enable_efer_bits(EFER_NX);
2680
2681 if (!cpu_has_vmx_vpid())
2682 enable_vpid = 0;
2683
2684 if (!cpu_has_vmx_ept() ||
2685 !cpu_has_vmx_ept_4levels()) {
2686 enable_ept = 0;
2687 enable_unrestricted_guest = 0;
2688 enable_ept_ad_bits = 0;
2689 }
2690
2691 if (!cpu_has_vmx_ept_ad_bits())
2692 enable_ept_ad_bits = 0;
2693
2694 if (!cpu_has_vmx_unrestricted_guest())
2695 enable_unrestricted_guest = 0;
2696
2697 if (!cpu_has_vmx_flexpriority())
2698 flexpriority_enabled = 0;
2699
2700 if (!cpu_has_vmx_tpr_shadow())
2701 kvm_x86_ops->update_cr8_intercept = NULL;
2702
2703 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2704 kvm_disable_largepages();
2705
2706 if (!cpu_has_vmx_ple())
2707 ple_gap = 0;
2708
2709 if (nested)
2710 nested_vmx_setup_ctls_msrs();
2711
2712 return alloc_kvm_area();
2713 }
2714
2715 static __exit void hardware_unsetup(void)
2716 {
2717 free_kvm_area();
2718 }
2719
2720 static void fix_pmode_dataseg(struct kvm_vcpu *vcpu, int seg, struct kvm_segment *save)
2721 {
2722 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2723 struct kvm_segment tmp = *save;
2724
2725 if (!(vmcs_readl(sf->base) == tmp.base && tmp.s)) {
2726 tmp.base = vmcs_readl(sf->base);
2727 tmp.selector = vmcs_read16(sf->selector);
2728 tmp.s = 1;
2729 }
2730 vmx_set_segment(vcpu, &tmp, seg);
2731 }
2732
2733 static void enter_pmode(struct kvm_vcpu *vcpu)
2734 {
2735 unsigned long flags;
2736 struct vcpu_vmx *vmx = to_vmx(vcpu);
2737
2738 vmx->emulation_required = 1;
2739 vmx->rmode.vm86_active = 0;
2740
2741 vmx_segment_cache_clear(vmx);
2742
2743 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2744
2745 flags = vmcs_readl(GUEST_RFLAGS);
2746 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2747 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2748 vmcs_writel(GUEST_RFLAGS, flags);
2749
2750 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2751 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2752
2753 update_exception_bitmap(vcpu);
2754
2755 if (emulate_invalid_guest_state)
2756 return;
2757
2758 fix_pmode_dataseg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2759 fix_pmode_dataseg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2760 fix_pmode_dataseg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2761 fix_pmode_dataseg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2762
2763 vmx_segment_cache_clear(vmx);
2764
2765 vmcs_write16(GUEST_SS_SELECTOR, 0);
2766 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2767
2768 vmcs_write16(GUEST_CS_SELECTOR,
2769 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2770 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2771 }
2772
2773 static gva_t rmode_tss_base(struct kvm *kvm)
2774 {
2775 if (!kvm->arch.tss_addr) {
2776 struct kvm_memslots *slots;
2777 struct kvm_memory_slot *slot;
2778 gfn_t base_gfn;
2779
2780 slots = kvm_memslots(kvm);
2781 slot = id_to_memslot(slots, 0);
2782 base_gfn = slot->base_gfn + slot->npages - 3;
2783
2784 return base_gfn << PAGE_SHIFT;
2785 }
2786 return kvm->arch.tss_addr;
2787 }
2788
2789 static void fix_rmode_seg(int seg, struct kvm_segment *save)
2790 {
2791 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2792
2793 vmcs_write16(sf->selector, save->base >> 4);
2794 vmcs_write32(sf->base, save->base & 0xffff0);
2795 vmcs_write32(sf->limit, 0xffff);
2796 vmcs_write32(sf->ar_bytes, 0xf3);
2797 if (save->base & 0xf)
2798 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2799 " aligned when entering protected mode (seg=%d)",
2800 seg);
2801 }
2802
2803 static void enter_rmode(struct kvm_vcpu *vcpu)
2804 {
2805 unsigned long flags;
2806 struct vcpu_vmx *vmx = to_vmx(vcpu);
2807 struct kvm_segment var;
2808
2809 if (enable_unrestricted_guest)
2810 return;
2811
2812 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2813 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2814 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2815 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2816 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2817
2818 vmx->emulation_required = 1;
2819 vmx->rmode.vm86_active = 1;
2820
2821
2822 /*
2823 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2824 * vcpu. Call it here with phys address pointing 16M below 4G.
2825 */
2826 if (!vcpu->kvm->arch.tss_addr) {
2827 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2828 "called before entering vcpu\n");
2829 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2830 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2831 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2832 }
2833
2834 vmx_segment_cache_clear(vmx);
2835
2836 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2837 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2838 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2839
2840 flags = vmcs_readl(GUEST_RFLAGS);
2841 vmx->rmode.save_rflags = flags;
2842
2843 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2844
2845 vmcs_writel(GUEST_RFLAGS, flags);
2846 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2847 update_exception_bitmap(vcpu);
2848
2849 if (emulate_invalid_guest_state)
2850 goto continue_rmode;
2851
2852 vmx_get_segment(vcpu, &var, VCPU_SREG_SS);
2853 vmx_set_segment(vcpu, &var, VCPU_SREG_SS);
2854
2855 vmx_get_segment(vcpu, &var, VCPU_SREG_CS);
2856 vmx_set_segment(vcpu, &var, VCPU_SREG_CS);
2857
2858 vmx_get_segment(vcpu, &var, VCPU_SREG_ES);
2859 vmx_set_segment(vcpu, &var, VCPU_SREG_ES);
2860
2861 vmx_get_segment(vcpu, &var, VCPU_SREG_DS);
2862 vmx_set_segment(vcpu, &var, VCPU_SREG_DS);
2863
2864 vmx_get_segment(vcpu, &var, VCPU_SREG_GS);
2865 vmx_set_segment(vcpu, &var, VCPU_SREG_GS);
2866
2867 vmx_get_segment(vcpu, &var, VCPU_SREG_FS);
2868 vmx_set_segment(vcpu, &var, VCPU_SREG_FS);
2869
2870 continue_rmode:
2871 kvm_mmu_reset_context(vcpu);
2872 }
2873
2874 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2875 {
2876 struct vcpu_vmx *vmx = to_vmx(vcpu);
2877 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2878
2879 if (!msr)
2880 return;
2881
2882 /*
2883 * Force kernel_gs_base reloading before EFER changes, as control
2884 * of this msr depends on is_long_mode().
2885 */
2886 vmx_load_host_state(to_vmx(vcpu));
2887 vcpu->arch.efer = efer;
2888 if (efer & EFER_LMA) {
2889 vmcs_write32(VM_ENTRY_CONTROLS,
2890 vmcs_read32(VM_ENTRY_CONTROLS) |
2891 VM_ENTRY_IA32E_MODE);
2892 msr->data = efer;
2893 } else {
2894 vmcs_write32(VM_ENTRY_CONTROLS,
2895 vmcs_read32(VM_ENTRY_CONTROLS) &
2896 ~VM_ENTRY_IA32E_MODE);
2897
2898 msr->data = efer & ~EFER_LME;
2899 }
2900 setup_msrs(vmx);
2901 }
2902
2903 #ifdef CONFIG_X86_64
2904
2905 static void enter_lmode(struct kvm_vcpu *vcpu)
2906 {
2907 u32 guest_tr_ar;
2908
2909 vmx_segment_cache_clear(to_vmx(vcpu));
2910
2911 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2912 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2913 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2914 __func__);
2915 vmcs_write32(GUEST_TR_AR_BYTES,
2916 (guest_tr_ar & ~AR_TYPE_MASK)
2917 | AR_TYPE_BUSY_64_TSS);
2918 }
2919 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2920 }
2921
2922 static void exit_lmode(struct kvm_vcpu *vcpu)
2923 {
2924 vmcs_write32(VM_ENTRY_CONTROLS,
2925 vmcs_read32(VM_ENTRY_CONTROLS)
2926 & ~VM_ENTRY_IA32E_MODE);
2927 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2928 }
2929
2930 #endif
2931
2932 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2933 {
2934 vpid_sync_context(to_vmx(vcpu));
2935 if (enable_ept) {
2936 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2937 return;
2938 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2939 }
2940 }
2941
2942 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2943 {
2944 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2945
2946 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2947 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2948 }
2949
2950 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2951 {
2952 if (enable_ept && is_paging(vcpu))
2953 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2954 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2955 }
2956
2957 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2958 {
2959 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2960
2961 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2962 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2963 }
2964
2965 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2966 {
2967 if (!test_bit(VCPU_EXREG_PDPTR,
2968 (unsigned long *)&vcpu->arch.regs_dirty))
2969 return;
2970
2971 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2972 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2973 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2974 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2975 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2976 }
2977 }
2978
2979 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2980 {
2981 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2982 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2983 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2984 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2985 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2986 }
2987
2988 __set_bit(VCPU_EXREG_PDPTR,
2989 (unsigned long *)&vcpu->arch.regs_avail);
2990 __set_bit(VCPU_EXREG_PDPTR,
2991 (unsigned long *)&vcpu->arch.regs_dirty);
2992 }
2993
2994 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2995
2996 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2997 unsigned long cr0,
2998 struct kvm_vcpu *vcpu)
2999 {
3000 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3001 vmx_decache_cr3(vcpu);
3002 if (!(cr0 & X86_CR0_PG)) {
3003 /* From paging/starting to nonpaging */
3004 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3005 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3006 (CPU_BASED_CR3_LOAD_EXITING |
3007 CPU_BASED_CR3_STORE_EXITING));
3008 vcpu->arch.cr0 = cr0;
3009 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3010 } else if (!is_paging(vcpu)) {
3011 /* From nonpaging to paging */
3012 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3013 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3014 ~(CPU_BASED_CR3_LOAD_EXITING |
3015 CPU_BASED_CR3_STORE_EXITING));
3016 vcpu->arch.cr0 = cr0;
3017 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3018 }
3019
3020 if (!(cr0 & X86_CR0_WP))
3021 *hw_cr0 &= ~X86_CR0_WP;
3022 }
3023
3024 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3025 {
3026 struct vcpu_vmx *vmx = to_vmx(vcpu);
3027 unsigned long hw_cr0;
3028
3029 if (enable_unrestricted_guest)
3030 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
3031 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3032 else
3033 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
3034
3035 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3036 enter_pmode(vcpu);
3037
3038 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3039 enter_rmode(vcpu);
3040
3041 #ifdef CONFIG_X86_64
3042 if (vcpu->arch.efer & EFER_LME) {
3043 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3044 enter_lmode(vcpu);
3045 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3046 exit_lmode(vcpu);
3047 }
3048 #endif
3049
3050 if (enable_ept)
3051 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3052
3053 if (!vcpu->fpu_active)
3054 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3055
3056 vmcs_writel(CR0_READ_SHADOW, cr0);
3057 vmcs_writel(GUEST_CR0, hw_cr0);
3058 vcpu->arch.cr0 = cr0;
3059 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3060 }
3061
3062 static u64 construct_eptp(unsigned long root_hpa)
3063 {
3064 u64 eptp;
3065
3066 /* TODO write the value reading from MSR */
3067 eptp = VMX_EPT_DEFAULT_MT |
3068 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3069 if (enable_ept_ad_bits)
3070 eptp |= VMX_EPT_AD_ENABLE_BIT;
3071 eptp |= (root_hpa & PAGE_MASK);
3072
3073 return eptp;
3074 }
3075
3076 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3077 {
3078 unsigned long guest_cr3;
3079 u64 eptp;
3080
3081 guest_cr3 = cr3;
3082 if (enable_ept) {
3083 eptp = construct_eptp(cr3);
3084 vmcs_write64(EPT_POINTER, eptp);
3085 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3086 vcpu->kvm->arch.ept_identity_map_addr;
3087 ept_load_pdptrs(vcpu);
3088 }
3089
3090 vmx_flush_tlb(vcpu);
3091 vmcs_writel(GUEST_CR3, guest_cr3);
3092 }
3093
3094 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3095 {
3096 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3097 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3098
3099 if (cr4 & X86_CR4_VMXE) {
3100 /*
3101 * To use VMXON (and later other VMX instructions), a guest
3102 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3103 * So basically the check on whether to allow nested VMX
3104 * is here.
3105 */
3106 if (!nested_vmx_allowed(vcpu))
3107 return 1;
3108 } else if (to_vmx(vcpu)->nested.vmxon)
3109 return 1;
3110
3111 vcpu->arch.cr4 = cr4;
3112 if (enable_ept) {
3113 if (!is_paging(vcpu)) {
3114 hw_cr4 &= ~X86_CR4_PAE;
3115 hw_cr4 |= X86_CR4_PSE;
3116 } else if (!(cr4 & X86_CR4_PAE)) {
3117 hw_cr4 &= ~X86_CR4_PAE;
3118 }
3119 }
3120
3121 vmcs_writel(CR4_READ_SHADOW, cr4);
3122 vmcs_writel(GUEST_CR4, hw_cr4);
3123 return 0;
3124 }
3125
3126 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3127 struct kvm_segment *var, int seg)
3128 {
3129 struct vcpu_vmx *vmx = to_vmx(vcpu);
3130 u32 ar;
3131
3132 if (vmx->rmode.vm86_active
3133 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3134 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3135 || seg == VCPU_SREG_GS)) {
3136 *var = vmx->rmode.segs[seg];
3137 if (seg == VCPU_SREG_TR
3138 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3139 return;
3140 var->base = vmx_read_guest_seg_base(vmx, seg);
3141 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3142 return;
3143 }
3144 var->base = vmx_read_guest_seg_base(vmx, seg);
3145 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3146 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3147 ar = vmx_read_guest_seg_ar(vmx, seg);
3148 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3149 ar = 0;
3150 var->type = ar & 15;
3151 var->s = (ar >> 4) & 1;
3152 var->dpl = (ar >> 5) & 3;
3153 var->present = (ar >> 7) & 1;
3154 var->avl = (ar >> 12) & 1;
3155 var->l = (ar >> 13) & 1;
3156 var->db = (ar >> 14) & 1;
3157 var->g = (ar >> 15) & 1;
3158 var->unusable = (ar >> 16) & 1;
3159 }
3160
3161 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3162 {
3163 struct kvm_segment s;
3164
3165 if (to_vmx(vcpu)->rmode.vm86_active) {
3166 vmx_get_segment(vcpu, &s, seg);
3167 return s.base;
3168 }
3169 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3170 }
3171
3172 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3173 {
3174 if (!is_protmode(vcpu))
3175 return 0;
3176
3177 if (!is_long_mode(vcpu)
3178 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3179 return 3;
3180
3181 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3182 }
3183
3184 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3185 {
3186 struct vcpu_vmx *vmx = to_vmx(vcpu);
3187
3188 /*
3189 * If we enter real mode with cs.sel & 3 != 0, the normal CPL calculations
3190 * fail; use the cache instead.
3191 */
3192 if (unlikely(vmx->emulation_required && emulate_invalid_guest_state)) {
3193 return vmx->cpl;
3194 }
3195
3196 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3197 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3198 vmx->cpl = __vmx_get_cpl(vcpu);
3199 }
3200
3201 return vmx->cpl;
3202 }
3203
3204
3205 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3206 {
3207 u32 ar;
3208
3209 if (var->unusable || !var->present)
3210 ar = 1 << 16;
3211 else {
3212 ar = var->type & 15;
3213 ar |= (var->s & 1) << 4;
3214 ar |= (var->dpl & 3) << 5;
3215 ar |= (var->present & 1) << 7;
3216 ar |= (var->avl & 1) << 12;
3217 ar |= (var->l & 1) << 13;
3218 ar |= (var->db & 1) << 14;
3219 ar |= (var->g & 1) << 15;
3220 }
3221
3222 return ar;
3223 }
3224
3225 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3226 struct kvm_segment *var, int seg)
3227 {
3228 struct vcpu_vmx *vmx = to_vmx(vcpu);
3229 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3230 u32 ar;
3231
3232 vmx_segment_cache_clear(vmx);
3233
3234 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3235 vmcs_write16(sf->selector, var->selector);
3236 vmx->rmode.segs[VCPU_SREG_TR] = *var;
3237 return;
3238 }
3239 vmcs_writel(sf->base, var->base);
3240 vmcs_write32(sf->limit, var->limit);
3241 vmcs_write16(sf->selector, var->selector);
3242 if (vmx->rmode.vm86_active && var->s) {
3243 vmx->rmode.segs[seg] = *var;
3244 /*
3245 * Hack real-mode segments into vm86 compatibility.
3246 */
3247 if (var->base == 0xffff0000 && var->selector == 0xf000)
3248 vmcs_writel(sf->base, 0xf0000);
3249 ar = 0xf3;
3250 } else
3251 ar = vmx_segment_access_rights(var);
3252
3253 /*
3254 * Fix the "Accessed" bit in AR field of segment registers for older
3255 * qemu binaries.
3256 * IA32 arch specifies that at the time of processor reset the
3257 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3258 * is setting it to 0 in the userland code. This causes invalid guest
3259 * state vmexit when "unrestricted guest" mode is turned on.
3260 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3261 * tree. Newer qemu binaries with that qemu fix would not need this
3262 * kvm hack.
3263 */
3264 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3265 ar |= 0x1; /* Accessed */
3266
3267 vmcs_write32(sf->ar_bytes, ar);
3268 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3269
3270 /*
3271 * Fix segments for real mode guest in hosts that don't have
3272 * "unrestricted_mode" or it was disabled.
3273 * This is done to allow migration of the guests from hosts with
3274 * unrestricted guest like Westmere to older host that don't have
3275 * unrestricted guest like Nehelem.
3276 */
3277 if (!enable_unrestricted_guest && vmx->rmode.vm86_active) {
3278 switch (seg) {
3279 case VCPU_SREG_CS:
3280 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
3281 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
3282 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
3283 vmcs_writel(GUEST_CS_BASE, 0xf0000);
3284 vmcs_write16(GUEST_CS_SELECTOR,
3285 vmcs_readl(GUEST_CS_BASE) >> 4);
3286 break;
3287 case VCPU_SREG_ES:
3288 case VCPU_SREG_DS:
3289 case VCPU_SREG_GS:
3290 case VCPU_SREG_FS:
3291 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3292 break;
3293 case VCPU_SREG_SS:
3294 vmcs_write16(GUEST_SS_SELECTOR,
3295 vmcs_readl(GUEST_SS_BASE) >> 4);
3296 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
3297 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
3298 break;
3299 }
3300 }
3301 }
3302
3303 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3304 {
3305 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3306
3307 *db = (ar >> 14) & 1;
3308 *l = (ar >> 13) & 1;
3309 }
3310
3311 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3312 {
3313 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3314 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3315 }
3316
3317 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3318 {
3319 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3320 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3321 }
3322
3323 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3324 {
3325 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3326 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3327 }
3328
3329 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3330 {
3331 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3332 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3333 }
3334
3335 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3336 {
3337 struct kvm_segment var;
3338 u32 ar;
3339
3340 vmx_get_segment(vcpu, &var, seg);
3341 ar = vmx_segment_access_rights(&var);
3342
3343 if (var.base != (var.selector << 4))
3344 return false;
3345 if (var.limit < 0xffff)
3346 return false;
3347 if (((ar | (3 << AR_DPL_SHIFT)) & ~(AR_G_MASK | AR_DB_MASK)) != 0xf3)
3348 return false;
3349
3350 return true;
3351 }
3352
3353 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3354 {
3355 struct kvm_segment cs;
3356 unsigned int cs_rpl;
3357
3358 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3359 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3360
3361 if (cs.unusable)
3362 return false;
3363 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3364 return false;
3365 if (!cs.s)
3366 return false;
3367 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3368 if (cs.dpl > cs_rpl)
3369 return false;
3370 } else {
3371 if (cs.dpl != cs_rpl)
3372 return false;
3373 }
3374 if (!cs.present)
3375 return false;
3376
3377 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3378 return true;
3379 }
3380
3381 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3382 {
3383 struct kvm_segment ss;
3384 unsigned int ss_rpl;
3385
3386 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3387 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3388
3389 if (ss.unusable)
3390 return true;
3391 if (ss.type != 3 && ss.type != 7)
3392 return false;
3393 if (!ss.s)
3394 return false;
3395 if (ss.dpl != ss_rpl) /* DPL != RPL */
3396 return false;
3397 if (!ss.present)
3398 return false;
3399
3400 return true;
3401 }
3402
3403 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3404 {
3405 struct kvm_segment var;
3406 unsigned int rpl;
3407
3408 vmx_get_segment(vcpu, &var, seg);
3409 rpl = var.selector & SELECTOR_RPL_MASK;
3410
3411 if (var.unusable)
3412 return true;
3413 if (!var.s)
3414 return false;
3415 if (!var.present)
3416 return false;
3417 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3418 if (var.dpl < rpl) /* DPL < RPL */
3419 return false;
3420 }
3421
3422 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3423 * rights flags
3424 */
3425 return true;
3426 }
3427
3428 static bool tr_valid(struct kvm_vcpu *vcpu)
3429 {
3430 struct kvm_segment tr;
3431
3432 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3433
3434 if (tr.unusable)
3435 return false;
3436 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3437 return false;
3438 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3439 return false;
3440 if (!tr.present)
3441 return false;
3442
3443 return true;
3444 }
3445
3446 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3447 {
3448 struct kvm_segment ldtr;
3449
3450 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3451
3452 if (ldtr.unusable)
3453 return true;
3454 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3455 return false;
3456 if (ldtr.type != 2)
3457 return false;
3458 if (!ldtr.present)
3459 return false;
3460
3461 return true;
3462 }
3463
3464 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3465 {
3466 struct kvm_segment cs, ss;
3467
3468 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3469 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3470
3471 return ((cs.selector & SELECTOR_RPL_MASK) ==
3472 (ss.selector & SELECTOR_RPL_MASK));
3473 }
3474
3475 /*
3476 * Check if guest state is valid. Returns true if valid, false if
3477 * not.
3478 * We assume that registers are always usable
3479 */
3480 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3481 {
3482 /* real mode guest state checks */
3483 if (!is_protmode(vcpu)) {
3484 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3485 return false;
3486 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3487 return false;
3488 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3489 return false;
3490 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3491 return false;
3492 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3493 return false;
3494 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3495 return false;
3496 } else {
3497 /* protected mode guest state checks */
3498 if (!cs_ss_rpl_check(vcpu))
3499 return false;
3500 if (!code_segment_valid(vcpu))
3501 return false;
3502 if (!stack_segment_valid(vcpu))
3503 return false;
3504 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3505 return false;
3506 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3507 return false;
3508 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3509 return false;
3510 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3511 return false;
3512 if (!tr_valid(vcpu))
3513 return false;
3514 if (!ldtr_valid(vcpu))
3515 return false;
3516 }
3517 /* TODO:
3518 * - Add checks on RIP
3519 * - Add checks on RFLAGS
3520 */
3521
3522 return true;
3523 }
3524
3525 static int init_rmode_tss(struct kvm *kvm)
3526 {
3527 gfn_t fn;
3528 u16 data = 0;
3529 int r, idx, ret = 0;
3530
3531 idx = srcu_read_lock(&kvm->srcu);
3532 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3533 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3534 if (r < 0)
3535 goto out;
3536 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3537 r = kvm_write_guest_page(kvm, fn++, &data,
3538 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3539 if (r < 0)
3540 goto out;
3541 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3542 if (r < 0)
3543 goto out;
3544 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3545 if (r < 0)
3546 goto out;
3547 data = ~0;
3548 r = kvm_write_guest_page(kvm, fn, &data,
3549 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3550 sizeof(u8));
3551 if (r < 0)
3552 goto out;
3553
3554 ret = 1;
3555 out:
3556 srcu_read_unlock(&kvm->srcu, idx);
3557 return ret;
3558 }
3559
3560 static int init_rmode_identity_map(struct kvm *kvm)
3561 {
3562 int i, idx, r, ret;
3563 pfn_t identity_map_pfn;
3564 u32 tmp;
3565
3566 if (!enable_ept)
3567 return 1;
3568 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3569 printk(KERN_ERR "EPT: identity-mapping pagetable "
3570 "haven't been allocated!\n");
3571 return 0;
3572 }
3573 if (likely(kvm->arch.ept_identity_pagetable_done))
3574 return 1;
3575 ret = 0;
3576 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3577 idx = srcu_read_lock(&kvm->srcu);
3578 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3579 if (r < 0)
3580 goto out;
3581 /* Set up identity-mapping pagetable for EPT in real mode */
3582 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3583 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3584 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3585 r = kvm_write_guest_page(kvm, identity_map_pfn,
3586 &tmp, i * sizeof(tmp), sizeof(tmp));
3587 if (r < 0)
3588 goto out;
3589 }
3590 kvm->arch.ept_identity_pagetable_done = true;
3591 ret = 1;
3592 out:
3593 srcu_read_unlock(&kvm->srcu, idx);
3594 return ret;
3595 }
3596
3597 static void seg_setup(int seg)
3598 {
3599 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3600 unsigned int ar;
3601
3602 vmcs_write16(sf->selector, 0);
3603 vmcs_writel(sf->base, 0);
3604 vmcs_write32(sf->limit, 0xffff);
3605 if (enable_unrestricted_guest) {
3606 ar = 0x93;
3607 if (seg == VCPU_SREG_CS)
3608 ar |= 0x08; /* code segment */
3609 } else
3610 ar = 0xf3;
3611
3612 vmcs_write32(sf->ar_bytes, ar);
3613 }
3614
3615 static int alloc_apic_access_page(struct kvm *kvm)
3616 {
3617 struct page *page;
3618 struct kvm_userspace_memory_region kvm_userspace_mem;
3619 int r = 0;
3620
3621 mutex_lock(&kvm->slots_lock);
3622 if (kvm->arch.apic_access_page)
3623 goto out;
3624 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3625 kvm_userspace_mem.flags = 0;
3626 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3627 kvm_userspace_mem.memory_size = PAGE_SIZE;
3628 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3629 if (r)
3630 goto out;
3631
3632 page = gfn_to_page(kvm, 0xfee00);
3633 if (is_error_page(page)) {
3634 r = -EFAULT;
3635 goto out;
3636 }
3637
3638 kvm->arch.apic_access_page = page;
3639 out:
3640 mutex_unlock(&kvm->slots_lock);
3641 return r;
3642 }
3643
3644 static int alloc_identity_pagetable(struct kvm *kvm)
3645 {
3646 struct page *page;
3647 struct kvm_userspace_memory_region kvm_userspace_mem;
3648 int r = 0;
3649
3650 mutex_lock(&kvm->slots_lock);
3651 if (kvm->arch.ept_identity_pagetable)
3652 goto out;
3653 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3654 kvm_userspace_mem.flags = 0;
3655 kvm_userspace_mem.guest_phys_addr =
3656 kvm->arch.ept_identity_map_addr;
3657 kvm_userspace_mem.memory_size = PAGE_SIZE;
3658 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3659 if (r)
3660 goto out;
3661
3662 page = gfn_to_page(kvm, kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3663 if (is_error_page(page)) {
3664 r = -EFAULT;
3665 goto out;
3666 }
3667
3668 kvm->arch.ept_identity_pagetable = page;
3669 out:
3670 mutex_unlock(&kvm->slots_lock);
3671 return r;
3672 }
3673
3674 static void allocate_vpid(struct vcpu_vmx *vmx)
3675 {
3676 int vpid;
3677
3678 vmx->vpid = 0;
3679 if (!enable_vpid)
3680 return;
3681 spin_lock(&vmx_vpid_lock);
3682 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3683 if (vpid < VMX_NR_VPIDS) {
3684 vmx->vpid = vpid;
3685 __set_bit(vpid, vmx_vpid_bitmap);
3686 }
3687 spin_unlock(&vmx_vpid_lock);
3688 }
3689
3690 static void free_vpid(struct vcpu_vmx *vmx)
3691 {
3692 if (!enable_vpid)
3693 return;
3694 spin_lock(&vmx_vpid_lock);
3695 if (vmx->vpid != 0)
3696 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3697 spin_unlock(&vmx_vpid_lock);
3698 }
3699
3700 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3701 {
3702 int f = sizeof(unsigned long);
3703
3704 if (!cpu_has_vmx_msr_bitmap())
3705 return;
3706
3707 /*
3708 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3709 * have the write-low and read-high bitmap offsets the wrong way round.
3710 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3711 */
3712 if (msr <= 0x1fff) {
3713 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3714 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3715 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3716 msr &= 0x1fff;
3717 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3718 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3719 }
3720 }
3721
3722 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3723 {
3724 if (!longmode_only)
3725 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3726 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3727 }
3728
3729 /*
3730 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3731 * will not change in the lifetime of the guest.
3732 * Note that host-state that does change is set elsewhere. E.g., host-state
3733 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3734 */
3735 static void vmx_set_constant_host_state(void)
3736 {
3737 u32 low32, high32;
3738 unsigned long tmpl;
3739 struct desc_ptr dt;
3740
3741 vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS); /* 22.2.3 */
3742 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3743 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3744
3745 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3746 #ifdef CONFIG_X86_64
3747 /*
3748 * Load null selectors, so we can avoid reloading them in
3749 * __vmx_load_host_state(), in case userspace uses the null selectors
3750 * too (the expected case).
3751 */
3752 vmcs_write16(HOST_DS_SELECTOR, 0);
3753 vmcs_write16(HOST_ES_SELECTOR, 0);
3754 #else
3755 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3756 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3757 #endif
3758 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3759 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3760
3761 native_store_idt(&dt);
3762 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3763
3764 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
3765
3766 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3767 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3768 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3769 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3770
3771 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3772 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3773 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3774 }
3775 }
3776
3777 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3778 {
3779 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3780 if (enable_ept)
3781 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3782 if (is_guest_mode(&vmx->vcpu))
3783 vmx->vcpu.arch.cr4_guest_owned_bits &=
3784 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3785 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3786 }
3787
3788 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3789 {
3790 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3791 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3792 exec_control &= ~CPU_BASED_TPR_SHADOW;
3793 #ifdef CONFIG_X86_64
3794 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3795 CPU_BASED_CR8_LOAD_EXITING;
3796 #endif
3797 }
3798 if (!enable_ept)
3799 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3800 CPU_BASED_CR3_LOAD_EXITING |
3801 CPU_BASED_INVLPG_EXITING;
3802 return exec_control;
3803 }
3804
3805 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3806 {
3807 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3808 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3809 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3810 if (vmx->vpid == 0)
3811 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3812 if (!enable_ept) {
3813 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3814 enable_unrestricted_guest = 0;
3815 /* Enable INVPCID for non-ept guests may cause performance regression. */
3816 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3817 }
3818 if (!enable_unrestricted_guest)
3819 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3820 if (!ple_gap)
3821 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3822 return exec_control;
3823 }
3824
3825 static void ept_set_mmio_spte_mask(void)
3826 {
3827 /*
3828 * EPT Misconfigurations can be generated if the value of bits 2:0
3829 * of an EPT paging-structure entry is 110b (write/execute).
3830 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3831 * spte.
3832 */
3833 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3834 }
3835
3836 /*
3837 * Sets up the vmcs for emulated real mode.
3838 */
3839 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3840 {
3841 #ifdef CONFIG_X86_64
3842 unsigned long a;
3843 #endif
3844 int i;
3845
3846 /* I/O */
3847 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3848 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3849
3850 if (cpu_has_vmx_msr_bitmap())
3851 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3852
3853 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3854
3855 /* Control */
3856 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3857 vmcs_config.pin_based_exec_ctrl);
3858
3859 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3860
3861 if (cpu_has_secondary_exec_ctrls()) {
3862 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3863 vmx_secondary_exec_control(vmx));
3864 }
3865
3866 if (ple_gap) {
3867 vmcs_write32(PLE_GAP, ple_gap);
3868 vmcs_write32(PLE_WINDOW, ple_window);
3869 }
3870
3871 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3872 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3873 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3874
3875 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3876 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3877 vmx_set_constant_host_state();
3878 #ifdef CONFIG_X86_64
3879 rdmsrl(MSR_FS_BASE, a);
3880 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3881 rdmsrl(MSR_GS_BASE, a);
3882 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3883 #else
3884 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3885 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3886 #endif
3887
3888 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3889 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3890 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3891 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3892 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3893
3894 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3895 u32 msr_low, msr_high;
3896 u64 host_pat;
3897 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3898 host_pat = msr_low | ((u64) msr_high << 32);
3899 /* Write the default value follow host pat */
3900 vmcs_write64(GUEST_IA32_PAT, host_pat);
3901 /* Keep arch.pat sync with GUEST_IA32_PAT */
3902 vmx->vcpu.arch.pat = host_pat;
3903 }
3904
3905 for (i = 0; i < NR_VMX_MSR; ++i) {
3906 u32 index = vmx_msr_index[i];
3907 u32 data_low, data_high;
3908 int j = vmx->nmsrs;
3909
3910 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3911 continue;
3912 if (wrmsr_safe(index, data_low, data_high) < 0)
3913 continue;
3914 vmx->guest_msrs[j].index = i;
3915 vmx->guest_msrs[j].data = 0;
3916 vmx->guest_msrs[j].mask = -1ull;
3917 ++vmx->nmsrs;
3918 }
3919
3920 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3921
3922 /* 22.2.1, 20.8.1 */
3923 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3924
3925 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3926 set_cr4_guest_host_mask(vmx);
3927
3928 return 0;
3929 }
3930
3931 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3932 {
3933 struct vcpu_vmx *vmx = to_vmx(vcpu);
3934 u64 msr;
3935 int ret;
3936
3937 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3938
3939 vmx->rmode.vm86_active = 0;
3940
3941 vmx->soft_vnmi_blocked = 0;
3942
3943 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3944 kvm_set_cr8(&vmx->vcpu, 0);
3945 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3946 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3947 msr |= MSR_IA32_APICBASE_BSP;
3948 kvm_set_apic_base(&vmx->vcpu, msr);
3949
3950 ret = fx_init(&vmx->vcpu);
3951 if (ret != 0)
3952 goto out;
3953
3954 vmx_segment_cache_clear(vmx);
3955
3956 seg_setup(VCPU_SREG_CS);
3957 /*
3958 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3959 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3960 */
3961 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3962 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3963 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3964 } else {
3965 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3966 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3967 }
3968
3969 seg_setup(VCPU_SREG_DS);
3970 seg_setup(VCPU_SREG_ES);
3971 seg_setup(VCPU_SREG_FS);
3972 seg_setup(VCPU_SREG_GS);
3973 seg_setup(VCPU_SREG_SS);
3974
3975 vmcs_write16(GUEST_TR_SELECTOR, 0);
3976 vmcs_writel(GUEST_TR_BASE, 0);
3977 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3978 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3979
3980 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3981 vmcs_writel(GUEST_LDTR_BASE, 0);
3982 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3983 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3984
3985 vmcs_write32(GUEST_SYSENTER_CS, 0);
3986 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3987 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3988
3989 vmcs_writel(GUEST_RFLAGS, 0x02);
3990 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3991 kvm_rip_write(vcpu, 0xfff0);
3992 else
3993 kvm_rip_write(vcpu, 0);
3994 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3995
3996 vmcs_writel(GUEST_GDTR_BASE, 0);
3997 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3998
3999 vmcs_writel(GUEST_IDTR_BASE, 0);
4000 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4001
4002 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4003 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4004 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4005
4006 /* Special registers */
4007 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4008
4009 setup_msrs(vmx);
4010
4011 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
4012
4013 if (cpu_has_vmx_tpr_shadow()) {
4014 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4015 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
4016 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4017 __pa(vmx->vcpu.arch.apic->regs));
4018 vmcs_write32(TPR_THRESHOLD, 0);
4019 }
4020
4021 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
4022 vmcs_write64(APIC_ACCESS_ADDR,
4023 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
4024
4025 if (vmx->vpid != 0)
4026 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4027
4028 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4029 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
4030 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
4031 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
4032 vmx_set_cr4(&vmx->vcpu, 0);
4033 vmx_set_efer(&vmx->vcpu, 0);
4034 vmx_fpu_activate(&vmx->vcpu);
4035 update_exception_bitmap(&vmx->vcpu);
4036
4037 vpid_sync_context(vmx);
4038
4039 ret = 0;
4040
4041 /* HACK: Don't enable emulation on guest boot/reset */
4042 vmx->emulation_required = 0;
4043
4044 out:
4045 return ret;
4046 }
4047
4048 /*
4049 * In nested virtualization, check if L1 asked to exit on external interrupts.
4050 * For most existing hypervisors, this will always return true.
4051 */
4052 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4053 {
4054 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4055 PIN_BASED_EXT_INTR_MASK;
4056 }
4057
4058 static void enable_irq_window(struct kvm_vcpu *vcpu)
4059 {
4060 u32 cpu_based_vm_exec_control;
4061 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4062 /*
4063 * We get here if vmx_interrupt_allowed() said we can't
4064 * inject to L1 now because L2 must run. Ask L2 to exit
4065 * right after entry, so we can inject to L1 more promptly.
4066 */
4067 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
4068 return;
4069 }
4070
4071 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4072 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4073 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4074 }
4075
4076 static void enable_nmi_window(struct kvm_vcpu *vcpu)
4077 {
4078 u32 cpu_based_vm_exec_control;
4079
4080 if (!cpu_has_virtual_nmis()) {
4081 enable_irq_window(vcpu);
4082 return;
4083 }
4084
4085 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
4086 enable_irq_window(vcpu);
4087 return;
4088 }
4089 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4090 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
4091 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4092 }
4093
4094 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
4095 {
4096 struct vcpu_vmx *vmx = to_vmx(vcpu);
4097 uint32_t intr;
4098 int irq = vcpu->arch.interrupt.nr;
4099
4100 trace_kvm_inj_virq(irq);
4101
4102 ++vcpu->stat.irq_injections;
4103 if (vmx->rmode.vm86_active) {
4104 int inc_eip = 0;
4105 if (vcpu->arch.interrupt.soft)
4106 inc_eip = vcpu->arch.event_exit_inst_len;
4107 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
4108 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4109 return;
4110 }
4111 intr = irq | INTR_INFO_VALID_MASK;
4112 if (vcpu->arch.interrupt.soft) {
4113 intr |= INTR_TYPE_SOFT_INTR;
4114 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4115 vmx->vcpu.arch.event_exit_inst_len);
4116 } else
4117 intr |= INTR_TYPE_EXT_INTR;
4118 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4119 }
4120
4121 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4122 {
4123 struct vcpu_vmx *vmx = to_vmx(vcpu);
4124
4125 if (is_guest_mode(vcpu))
4126 return;
4127
4128 if (!cpu_has_virtual_nmis()) {
4129 /*
4130 * Tracking the NMI-blocked state in software is built upon
4131 * finding the next open IRQ window. This, in turn, depends on
4132 * well-behaving guests: They have to keep IRQs disabled at
4133 * least as long as the NMI handler runs. Otherwise we may
4134 * cause NMI nesting, maybe breaking the guest. But as this is
4135 * highly unlikely, we can live with the residual risk.
4136 */
4137 vmx->soft_vnmi_blocked = 1;
4138 vmx->vnmi_blocked_time = 0;
4139 }
4140
4141 ++vcpu->stat.nmi_injections;
4142 vmx->nmi_known_unmasked = false;
4143 if (vmx->rmode.vm86_active) {
4144 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4145 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4146 return;
4147 }
4148 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4149 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4150 }
4151
4152 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4153 {
4154 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4155 return 0;
4156
4157 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4158 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4159 | GUEST_INTR_STATE_NMI));
4160 }
4161
4162 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4163 {
4164 if (!cpu_has_virtual_nmis())
4165 return to_vmx(vcpu)->soft_vnmi_blocked;
4166 if (to_vmx(vcpu)->nmi_known_unmasked)
4167 return false;
4168 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4169 }
4170
4171 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4172 {
4173 struct vcpu_vmx *vmx = to_vmx(vcpu);
4174
4175 if (!cpu_has_virtual_nmis()) {
4176 if (vmx->soft_vnmi_blocked != masked) {
4177 vmx->soft_vnmi_blocked = masked;
4178 vmx->vnmi_blocked_time = 0;
4179 }
4180 } else {
4181 vmx->nmi_known_unmasked = !masked;
4182 if (masked)
4183 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4184 GUEST_INTR_STATE_NMI);
4185 else
4186 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4187 GUEST_INTR_STATE_NMI);
4188 }
4189 }
4190
4191 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4192 {
4193 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4194 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4195 if (to_vmx(vcpu)->nested.nested_run_pending ||
4196 (vmcs12->idt_vectoring_info_field &
4197 VECTORING_INFO_VALID_MASK))
4198 return 0;
4199 nested_vmx_vmexit(vcpu);
4200 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4201 vmcs12->vm_exit_intr_info = 0;
4202 /* fall through to normal code, but now in L1, not L2 */
4203 }
4204
4205 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4206 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4207 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4208 }
4209
4210 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4211 {
4212 int ret;
4213 struct kvm_userspace_memory_region tss_mem = {
4214 .slot = TSS_PRIVATE_MEMSLOT,
4215 .guest_phys_addr = addr,
4216 .memory_size = PAGE_SIZE * 3,
4217 .flags = 0,
4218 };
4219
4220 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4221 if (ret)
4222 return ret;
4223 kvm->arch.tss_addr = addr;
4224 if (!init_rmode_tss(kvm))
4225 return -ENOMEM;
4226
4227 return 0;
4228 }
4229
4230 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4231 int vec, u32 err_code)
4232 {
4233 /*
4234 * Instruction with address size override prefix opcode 0x67
4235 * Cause the #SS fault with 0 error code in VM86 mode.
4236 */
4237 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4238 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4239 return 1;
4240 /*
4241 * Forward all other exceptions that are valid in real mode.
4242 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4243 * the required debugging infrastructure rework.
4244 */
4245 switch (vec) {
4246 case DB_VECTOR:
4247 if (vcpu->guest_debug &
4248 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4249 return 0;
4250 kvm_queue_exception(vcpu, vec);
4251 return 1;
4252 case BP_VECTOR:
4253 /*
4254 * Update instruction length as we may reinject the exception
4255 * from user space while in guest debugging mode.
4256 */
4257 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4258 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4259 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4260 return 0;
4261 /* fall through */
4262 case DE_VECTOR:
4263 case OF_VECTOR:
4264 case BR_VECTOR:
4265 case UD_VECTOR:
4266 case DF_VECTOR:
4267 case SS_VECTOR:
4268 case GP_VECTOR:
4269 case MF_VECTOR:
4270 kvm_queue_exception(vcpu, vec);
4271 return 1;
4272 }
4273 return 0;
4274 }
4275
4276 /*
4277 * Trigger machine check on the host. We assume all the MSRs are already set up
4278 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4279 * We pass a fake environment to the machine check handler because we want
4280 * the guest to be always treated like user space, no matter what context
4281 * it used internally.
4282 */
4283 static void kvm_machine_check(void)
4284 {
4285 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4286 struct pt_regs regs = {
4287 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4288 .flags = X86_EFLAGS_IF,
4289 };
4290
4291 do_machine_check(&regs, 0);
4292 #endif
4293 }
4294
4295 static int handle_machine_check(struct kvm_vcpu *vcpu)
4296 {
4297 /* already handled by vcpu_run */
4298 return 1;
4299 }
4300
4301 static int handle_exception(struct kvm_vcpu *vcpu)
4302 {
4303 struct vcpu_vmx *vmx = to_vmx(vcpu);
4304 struct kvm_run *kvm_run = vcpu->run;
4305 u32 intr_info, ex_no, error_code;
4306 unsigned long cr2, rip, dr6;
4307 u32 vect_info;
4308 enum emulation_result er;
4309
4310 vect_info = vmx->idt_vectoring_info;
4311 intr_info = vmx->exit_intr_info;
4312
4313 if (is_machine_check(intr_info))
4314 return handle_machine_check(vcpu);
4315
4316 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4317 return 1; /* already handled by vmx_vcpu_run() */
4318
4319 if (is_no_device(intr_info)) {
4320 vmx_fpu_activate(vcpu);
4321 return 1;
4322 }
4323
4324 if (is_invalid_opcode(intr_info)) {
4325 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4326 if (er != EMULATE_DONE)
4327 kvm_queue_exception(vcpu, UD_VECTOR);
4328 return 1;
4329 }
4330
4331 error_code = 0;
4332 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4333 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4334
4335 /*
4336 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4337 * MMIO, it is better to report an internal error.
4338 * See the comments in vmx_handle_exit.
4339 */
4340 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4341 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4342 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4343 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4344 vcpu->run->internal.ndata = 2;
4345 vcpu->run->internal.data[0] = vect_info;
4346 vcpu->run->internal.data[1] = intr_info;
4347 return 0;
4348 }
4349
4350 if (is_page_fault(intr_info)) {
4351 /* EPT won't cause page fault directly */
4352 BUG_ON(enable_ept);
4353 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4354 trace_kvm_page_fault(cr2, error_code);
4355
4356 if (kvm_event_needs_reinjection(vcpu))
4357 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4358 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4359 }
4360
4361 if (vmx->rmode.vm86_active &&
4362 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4363 error_code)) {
4364 if (vcpu->arch.halt_request) {
4365 vcpu->arch.halt_request = 0;
4366 return kvm_emulate_halt(vcpu);
4367 }
4368 return 1;
4369 }
4370
4371 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4372 switch (ex_no) {
4373 case DB_VECTOR:
4374 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4375 if (!(vcpu->guest_debug &
4376 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4377 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4378 kvm_queue_exception(vcpu, DB_VECTOR);
4379 return 1;
4380 }
4381 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4382 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4383 /* fall through */
4384 case BP_VECTOR:
4385 /*
4386 * Update instruction length as we may reinject #BP from
4387 * user space while in guest debugging mode. Reading it for
4388 * #DB as well causes no harm, it is not used in that case.
4389 */
4390 vmx->vcpu.arch.event_exit_inst_len =
4391 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4392 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4393 rip = kvm_rip_read(vcpu);
4394 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4395 kvm_run->debug.arch.exception = ex_no;
4396 break;
4397 default:
4398 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4399 kvm_run->ex.exception = ex_no;
4400 kvm_run->ex.error_code = error_code;
4401 break;
4402 }
4403 return 0;
4404 }
4405
4406 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4407 {
4408 ++vcpu->stat.irq_exits;
4409 return 1;
4410 }
4411
4412 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4413 {
4414 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4415 return 0;
4416 }
4417
4418 static int handle_io(struct kvm_vcpu *vcpu)
4419 {
4420 unsigned long exit_qualification;
4421 int size, in, string;
4422 unsigned port;
4423
4424 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4425 string = (exit_qualification & 16) != 0;
4426 in = (exit_qualification & 8) != 0;
4427
4428 ++vcpu->stat.io_exits;
4429
4430 if (string || in)
4431 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4432
4433 port = exit_qualification >> 16;
4434 size = (exit_qualification & 7) + 1;
4435 skip_emulated_instruction(vcpu);
4436
4437 return kvm_fast_pio_out(vcpu, size, port);
4438 }
4439
4440 static void
4441 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4442 {
4443 /*
4444 * Patch in the VMCALL instruction:
4445 */
4446 hypercall[0] = 0x0f;
4447 hypercall[1] = 0x01;
4448 hypercall[2] = 0xc1;
4449 }
4450
4451 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4452 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4453 {
4454 if (to_vmx(vcpu)->nested.vmxon &&
4455 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4456 return 1;
4457
4458 if (is_guest_mode(vcpu)) {
4459 /*
4460 * We get here when L2 changed cr0 in a way that did not change
4461 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4462 * but did change L0 shadowed bits. This can currently happen
4463 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4464 * loading) while pretending to allow the guest to change it.
4465 */
4466 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4467 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4468 return 1;
4469 vmcs_writel(CR0_READ_SHADOW, val);
4470 return 0;
4471 } else
4472 return kvm_set_cr0(vcpu, val);
4473 }
4474
4475 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4476 {
4477 if (is_guest_mode(vcpu)) {
4478 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4479 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4480 return 1;
4481 vmcs_writel(CR4_READ_SHADOW, val);
4482 return 0;
4483 } else
4484 return kvm_set_cr4(vcpu, val);
4485 }
4486
4487 /* called to set cr0 as approriate for clts instruction exit. */
4488 static void handle_clts(struct kvm_vcpu *vcpu)
4489 {
4490 if (is_guest_mode(vcpu)) {
4491 /*
4492 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4493 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4494 * just pretend it's off (also in arch.cr0 for fpu_activate).
4495 */
4496 vmcs_writel(CR0_READ_SHADOW,
4497 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4498 vcpu->arch.cr0 &= ~X86_CR0_TS;
4499 } else
4500 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4501 }
4502
4503 static int handle_cr(struct kvm_vcpu *vcpu)
4504 {
4505 unsigned long exit_qualification, val;
4506 int cr;
4507 int reg;
4508 int err;
4509
4510 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4511 cr = exit_qualification & 15;
4512 reg = (exit_qualification >> 8) & 15;
4513 switch ((exit_qualification >> 4) & 3) {
4514 case 0: /* mov to cr */
4515 val = kvm_register_read(vcpu, reg);
4516 trace_kvm_cr_write(cr, val);
4517 switch (cr) {
4518 case 0:
4519 err = handle_set_cr0(vcpu, val);
4520 kvm_complete_insn_gp(vcpu, err);
4521 return 1;
4522 case 3:
4523 err = kvm_set_cr3(vcpu, val);
4524 kvm_complete_insn_gp(vcpu, err);
4525 return 1;
4526 case 4:
4527 err = handle_set_cr4(vcpu, val);
4528 kvm_complete_insn_gp(vcpu, err);
4529 return 1;
4530 case 8: {
4531 u8 cr8_prev = kvm_get_cr8(vcpu);
4532 u8 cr8 = kvm_register_read(vcpu, reg);
4533 err = kvm_set_cr8(vcpu, cr8);
4534 kvm_complete_insn_gp(vcpu, err);
4535 if (irqchip_in_kernel(vcpu->kvm))
4536 return 1;
4537 if (cr8_prev <= cr8)
4538 return 1;
4539 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4540 return 0;
4541 }
4542 }
4543 break;
4544 case 2: /* clts */
4545 handle_clts(vcpu);
4546 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4547 skip_emulated_instruction(vcpu);
4548 vmx_fpu_activate(vcpu);
4549 return 1;
4550 case 1: /*mov from cr*/
4551 switch (cr) {
4552 case 3:
4553 val = kvm_read_cr3(vcpu);
4554 kvm_register_write(vcpu, reg, val);
4555 trace_kvm_cr_read(cr, val);
4556 skip_emulated_instruction(vcpu);
4557 return 1;
4558 case 8:
4559 val = kvm_get_cr8(vcpu);
4560 kvm_register_write(vcpu, reg, val);
4561 trace_kvm_cr_read(cr, val);
4562 skip_emulated_instruction(vcpu);
4563 return 1;
4564 }
4565 break;
4566 case 3: /* lmsw */
4567 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4568 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4569 kvm_lmsw(vcpu, val);
4570
4571 skip_emulated_instruction(vcpu);
4572 return 1;
4573 default:
4574 break;
4575 }
4576 vcpu->run->exit_reason = 0;
4577 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4578 (int)(exit_qualification >> 4) & 3, cr);
4579 return 0;
4580 }
4581
4582 static int handle_dr(struct kvm_vcpu *vcpu)
4583 {
4584 unsigned long exit_qualification;
4585 int dr, reg;
4586
4587 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4588 if (!kvm_require_cpl(vcpu, 0))
4589 return 1;
4590 dr = vmcs_readl(GUEST_DR7);
4591 if (dr & DR7_GD) {
4592 /*
4593 * As the vm-exit takes precedence over the debug trap, we
4594 * need to emulate the latter, either for the host or the
4595 * guest debugging itself.
4596 */
4597 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4598 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4599 vcpu->run->debug.arch.dr7 = dr;
4600 vcpu->run->debug.arch.pc =
4601 vmcs_readl(GUEST_CS_BASE) +
4602 vmcs_readl(GUEST_RIP);
4603 vcpu->run->debug.arch.exception = DB_VECTOR;
4604 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4605 return 0;
4606 } else {
4607 vcpu->arch.dr7 &= ~DR7_GD;
4608 vcpu->arch.dr6 |= DR6_BD;
4609 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4610 kvm_queue_exception(vcpu, DB_VECTOR);
4611 return 1;
4612 }
4613 }
4614
4615 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4616 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4617 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4618 if (exit_qualification & TYPE_MOV_FROM_DR) {
4619 unsigned long val;
4620 if (!kvm_get_dr(vcpu, dr, &val))
4621 kvm_register_write(vcpu, reg, val);
4622 } else
4623 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4624 skip_emulated_instruction(vcpu);
4625 return 1;
4626 }
4627
4628 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4629 {
4630 vmcs_writel(GUEST_DR7, val);
4631 }
4632
4633 static int handle_cpuid(struct kvm_vcpu *vcpu)
4634 {
4635 kvm_emulate_cpuid(vcpu);
4636 return 1;
4637 }
4638
4639 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4640 {
4641 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4642 u64 data;
4643
4644 if (vmx_get_msr(vcpu, ecx, &data)) {
4645 trace_kvm_msr_read_ex(ecx);
4646 kvm_inject_gp(vcpu, 0);
4647 return 1;
4648 }
4649
4650 trace_kvm_msr_read(ecx, data);
4651
4652 /* FIXME: handling of bits 32:63 of rax, rdx */
4653 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4654 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4655 skip_emulated_instruction(vcpu);
4656 return 1;
4657 }
4658
4659 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4660 {
4661 struct msr_data msr;
4662 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4663 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4664 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4665
4666 msr.data = data;
4667 msr.index = ecx;
4668 msr.host_initiated = false;
4669 if (vmx_set_msr(vcpu, &msr) != 0) {
4670 trace_kvm_msr_write_ex(ecx, data);
4671 kvm_inject_gp(vcpu, 0);
4672 return 1;
4673 }
4674
4675 trace_kvm_msr_write(ecx, data);
4676 skip_emulated_instruction(vcpu);
4677 return 1;
4678 }
4679
4680 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4681 {
4682 kvm_make_request(KVM_REQ_EVENT, vcpu);
4683 return 1;
4684 }
4685
4686 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4687 {
4688 u32 cpu_based_vm_exec_control;
4689
4690 /* clear pending irq */
4691 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4692 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4693 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4694
4695 kvm_make_request(KVM_REQ_EVENT, vcpu);
4696
4697 ++vcpu->stat.irq_window_exits;
4698
4699 /*
4700 * If the user space waits to inject interrupts, exit as soon as
4701 * possible
4702 */
4703 if (!irqchip_in_kernel(vcpu->kvm) &&
4704 vcpu->run->request_interrupt_window &&
4705 !kvm_cpu_has_interrupt(vcpu)) {
4706 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4707 return 0;
4708 }
4709 return 1;
4710 }
4711
4712 static int handle_halt(struct kvm_vcpu *vcpu)
4713 {
4714 skip_emulated_instruction(vcpu);
4715 return kvm_emulate_halt(vcpu);
4716 }
4717
4718 static int handle_vmcall(struct kvm_vcpu *vcpu)
4719 {
4720 skip_emulated_instruction(vcpu);
4721 kvm_emulate_hypercall(vcpu);
4722 return 1;
4723 }
4724
4725 static int handle_invd(struct kvm_vcpu *vcpu)
4726 {
4727 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4728 }
4729
4730 static int handle_invlpg(struct kvm_vcpu *vcpu)
4731 {
4732 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4733
4734 kvm_mmu_invlpg(vcpu, exit_qualification);
4735 skip_emulated_instruction(vcpu);
4736 return 1;
4737 }
4738
4739 static int handle_rdpmc(struct kvm_vcpu *vcpu)
4740 {
4741 int err;
4742
4743 err = kvm_rdpmc(vcpu);
4744 kvm_complete_insn_gp(vcpu, err);
4745
4746 return 1;
4747 }
4748
4749 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4750 {
4751 skip_emulated_instruction(vcpu);
4752 kvm_emulate_wbinvd(vcpu);
4753 return 1;
4754 }
4755
4756 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4757 {
4758 u64 new_bv = kvm_read_edx_eax(vcpu);
4759 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4760
4761 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4762 skip_emulated_instruction(vcpu);
4763 return 1;
4764 }
4765
4766 static int handle_apic_access(struct kvm_vcpu *vcpu)
4767 {
4768 if (likely(fasteoi)) {
4769 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4770 int access_type, offset;
4771
4772 access_type = exit_qualification & APIC_ACCESS_TYPE;
4773 offset = exit_qualification & APIC_ACCESS_OFFSET;
4774 /*
4775 * Sane guest uses MOV to write EOI, with written value
4776 * not cared. So make a short-circuit here by avoiding
4777 * heavy instruction emulation.
4778 */
4779 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4780 (offset == APIC_EOI)) {
4781 kvm_lapic_set_eoi(vcpu);
4782 skip_emulated_instruction(vcpu);
4783 return 1;
4784 }
4785 }
4786 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4787 }
4788
4789 static int handle_task_switch(struct kvm_vcpu *vcpu)
4790 {
4791 struct vcpu_vmx *vmx = to_vmx(vcpu);
4792 unsigned long exit_qualification;
4793 bool has_error_code = false;
4794 u32 error_code = 0;
4795 u16 tss_selector;
4796 int reason, type, idt_v, idt_index;
4797
4798 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4799 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
4800 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4801
4802 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4803
4804 reason = (u32)exit_qualification >> 30;
4805 if (reason == TASK_SWITCH_GATE && idt_v) {
4806 switch (type) {
4807 case INTR_TYPE_NMI_INTR:
4808 vcpu->arch.nmi_injected = false;
4809 vmx_set_nmi_mask(vcpu, true);
4810 break;
4811 case INTR_TYPE_EXT_INTR:
4812 case INTR_TYPE_SOFT_INTR:
4813 kvm_clear_interrupt_queue(vcpu);
4814 break;
4815 case INTR_TYPE_HARD_EXCEPTION:
4816 if (vmx->idt_vectoring_info &
4817 VECTORING_INFO_DELIVER_CODE_MASK) {
4818 has_error_code = true;
4819 error_code =
4820 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4821 }
4822 /* fall through */
4823 case INTR_TYPE_SOFT_EXCEPTION:
4824 kvm_clear_exception_queue(vcpu);
4825 break;
4826 default:
4827 break;
4828 }
4829 }
4830 tss_selector = exit_qualification;
4831
4832 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4833 type != INTR_TYPE_EXT_INTR &&
4834 type != INTR_TYPE_NMI_INTR))
4835 skip_emulated_instruction(vcpu);
4836
4837 if (kvm_task_switch(vcpu, tss_selector,
4838 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4839 has_error_code, error_code) == EMULATE_FAIL) {
4840 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4841 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4842 vcpu->run->internal.ndata = 0;
4843 return 0;
4844 }
4845
4846 /* clear all local breakpoint enable flags */
4847 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4848
4849 /*
4850 * TODO: What about debug traps on tss switch?
4851 * Are we supposed to inject them and update dr6?
4852 */
4853
4854 return 1;
4855 }
4856
4857 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4858 {
4859 unsigned long exit_qualification;
4860 gpa_t gpa;
4861 u32 error_code;
4862 int gla_validity;
4863
4864 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4865
4866 gla_validity = (exit_qualification >> 7) & 0x3;
4867 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4868 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4869 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4870 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4871 vmcs_readl(GUEST_LINEAR_ADDRESS));
4872 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4873 (long unsigned int)exit_qualification);
4874 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4875 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4876 return 0;
4877 }
4878
4879 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4880 trace_kvm_page_fault(gpa, exit_qualification);
4881
4882 /* It is a write fault? */
4883 error_code = exit_qualification & (1U << 1);
4884 /* ept page table is present? */
4885 error_code |= (exit_qualification >> 3) & 0x1;
4886
4887 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
4888 }
4889
4890 static u64 ept_rsvd_mask(u64 spte, int level)
4891 {
4892 int i;
4893 u64 mask = 0;
4894
4895 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4896 mask |= (1ULL << i);
4897
4898 if (level > 2)
4899 /* bits 7:3 reserved */
4900 mask |= 0xf8;
4901 else if (level == 2) {
4902 if (spte & (1ULL << 7))
4903 /* 2MB ref, bits 20:12 reserved */
4904 mask |= 0x1ff000;
4905 else
4906 /* bits 6:3 reserved */
4907 mask |= 0x78;
4908 }
4909
4910 return mask;
4911 }
4912
4913 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4914 int level)
4915 {
4916 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4917
4918 /* 010b (write-only) */
4919 WARN_ON((spte & 0x7) == 0x2);
4920
4921 /* 110b (write/execute) */
4922 WARN_ON((spte & 0x7) == 0x6);
4923
4924 /* 100b (execute-only) and value not supported by logical processor */
4925 if (!cpu_has_vmx_ept_execute_only())
4926 WARN_ON((spte & 0x7) == 0x4);
4927
4928 /* not 000b */
4929 if ((spte & 0x7)) {
4930 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4931
4932 if (rsvd_bits != 0) {
4933 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4934 __func__, rsvd_bits);
4935 WARN_ON(1);
4936 }
4937
4938 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4939 u64 ept_mem_type = (spte & 0x38) >> 3;
4940
4941 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4942 ept_mem_type == 7) {
4943 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4944 __func__, ept_mem_type);
4945 WARN_ON(1);
4946 }
4947 }
4948 }
4949 }
4950
4951 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4952 {
4953 u64 sptes[4];
4954 int nr_sptes, i, ret;
4955 gpa_t gpa;
4956
4957 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4958
4959 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4960 if (likely(ret == 1))
4961 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4962 EMULATE_DONE;
4963 if (unlikely(!ret))
4964 return 1;
4965
4966 /* It is the real ept misconfig */
4967 printk(KERN_ERR "EPT: Misconfiguration.\n");
4968 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4969
4970 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4971
4972 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4973 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4974
4975 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4976 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4977
4978 return 0;
4979 }
4980
4981 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4982 {
4983 u32 cpu_based_vm_exec_control;
4984
4985 /* clear pending NMI */
4986 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4987 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4988 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4989 ++vcpu->stat.nmi_window_exits;
4990 kvm_make_request(KVM_REQ_EVENT, vcpu);
4991
4992 return 1;
4993 }
4994
4995 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4996 {
4997 struct vcpu_vmx *vmx = to_vmx(vcpu);
4998 enum emulation_result err = EMULATE_DONE;
4999 int ret = 1;
5000 u32 cpu_exec_ctrl;
5001 bool intr_window_requested;
5002 unsigned count = 130;
5003
5004 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5005 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5006
5007 while (!guest_state_valid(vcpu) && count-- != 0) {
5008 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5009 return handle_interrupt_window(&vmx->vcpu);
5010
5011 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5012 return 1;
5013
5014 err = emulate_instruction(vcpu, 0);
5015
5016 if (err == EMULATE_DO_MMIO) {
5017 ret = 0;
5018 goto out;
5019 }
5020
5021 if (err != EMULATE_DONE) {
5022 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5023 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5024 vcpu->run->internal.ndata = 0;
5025 return 0;
5026 }
5027
5028 if (signal_pending(current))
5029 goto out;
5030 if (need_resched())
5031 schedule();
5032 }
5033
5034 vmx->emulation_required = !guest_state_valid(vcpu);
5035 out:
5036 return ret;
5037 }
5038
5039 /*
5040 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5041 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5042 */
5043 static int handle_pause(struct kvm_vcpu *vcpu)
5044 {
5045 skip_emulated_instruction(vcpu);
5046 kvm_vcpu_on_spin(vcpu);
5047
5048 return 1;
5049 }
5050
5051 static int handle_invalid_op(struct kvm_vcpu *vcpu)
5052 {
5053 kvm_queue_exception(vcpu, UD_VECTOR);
5054 return 1;
5055 }
5056
5057 /*
5058 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5059 * We could reuse a single VMCS for all the L2 guests, but we also want the
5060 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5061 * allows keeping them loaded on the processor, and in the future will allow
5062 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5063 * every entry if they never change.
5064 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5065 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5066 *
5067 * The following functions allocate and free a vmcs02 in this pool.
5068 */
5069
5070 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5071 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
5072 {
5073 struct vmcs02_list *item;
5074 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5075 if (item->vmptr == vmx->nested.current_vmptr) {
5076 list_move(&item->list, &vmx->nested.vmcs02_pool);
5077 return &item->vmcs02;
5078 }
5079
5080 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
5081 /* Recycle the least recently used VMCS. */
5082 item = list_entry(vmx->nested.vmcs02_pool.prev,
5083 struct vmcs02_list, list);
5084 item->vmptr = vmx->nested.current_vmptr;
5085 list_move(&item->list, &vmx->nested.vmcs02_pool);
5086 return &item->vmcs02;
5087 }
5088
5089 /* Create a new VMCS */
5090 item = (struct vmcs02_list *)
5091 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
5092 if (!item)
5093 return NULL;
5094 item->vmcs02.vmcs = alloc_vmcs();
5095 if (!item->vmcs02.vmcs) {
5096 kfree(item);
5097 return NULL;
5098 }
5099 loaded_vmcs_init(&item->vmcs02);
5100 item->vmptr = vmx->nested.current_vmptr;
5101 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
5102 vmx->nested.vmcs02_num++;
5103 return &item->vmcs02;
5104 }
5105
5106 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5107 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
5108 {
5109 struct vmcs02_list *item;
5110 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
5111 if (item->vmptr == vmptr) {
5112 free_loaded_vmcs(&item->vmcs02);
5113 list_del(&item->list);
5114 kfree(item);
5115 vmx->nested.vmcs02_num--;
5116 return;
5117 }
5118 }
5119
5120 /*
5121 * Free all VMCSs saved for this vcpu, except the one pointed by
5122 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5123 * currently used, if running L2), and vmcs01 when running L2.
5124 */
5125 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
5126 {
5127 struct vmcs02_list *item, *n;
5128 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
5129 if (vmx->loaded_vmcs != &item->vmcs02)
5130 free_loaded_vmcs(&item->vmcs02);
5131 list_del(&item->list);
5132 kfree(item);
5133 }
5134 vmx->nested.vmcs02_num = 0;
5135
5136 if (vmx->loaded_vmcs != &vmx->vmcs01)
5137 free_loaded_vmcs(&vmx->vmcs01);
5138 }
5139
5140 /*
5141 * Emulate the VMXON instruction.
5142 * Currently, we just remember that VMX is active, and do not save or even
5143 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5144 * do not currently need to store anything in that guest-allocated memory
5145 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5146 * argument is different from the VMXON pointer (which the spec says they do).
5147 */
5148 static int handle_vmon(struct kvm_vcpu *vcpu)
5149 {
5150 struct kvm_segment cs;
5151 struct vcpu_vmx *vmx = to_vmx(vcpu);
5152
5153 /* The Intel VMX Instruction Reference lists a bunch of bits that
5154 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5155 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5156 * Otherwise, we should fail with #UD. We test these now:
5157 */
5158 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5159 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5160 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5161 kvm_queue_exception(vcpu, UD_VECTOR);
5162 return 1;
5163 }
5164
5165 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5166 if (is_long_mode(vcpu) && !cs.l) {
5167 kvm_queue_exception(vcpu, UD_VECTOR);
5168 return 1;
5169 }
5170
5171 if (vmx_get_cpl(vcpu)) {
5172 kvm_inject_gp(vcpu, 0);
5173 return 1;
5174 }
5175
5176 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5177 vmx->nested.vmcs02_num = 0;
5178
5179 vmx->nested.vmxon = true;
5180
5181 skip_emulated_instruction(vcpu);
5182 return 1;
5183 }
5184
5185 /*
5186 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5187 * for running VMX instructions (except VMXON, whose prerequisites are
5188 * slightly different). It also specifies what exception to inject otherwise.
5189 */
5190 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5191 {
5192 struct kvm_segment cs;
5193 struct vcpu_vmx *vmx = to_vmx(vcpu);
5194
5195 if (!vmx->nested.vmxon) {
5196 kvm_queue_exception(vcpu, UD_VECTOR);
5197 return 0;
5198 }
5199
5200 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5201 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5202 (is_long_mode(vcpu) && !cs.l)) {
5203 kvm_queue_exception(vcpu, UD_VECTOR);
5204 return 0;
5205 }
5206
5207 if (vmx_get_cpl(vcpu)) {
5208 kvm_inject_gp(vcpu, 0);
5209 return 0;
5210 }
5211
5212 return 1;
5213 }
5214
5215 /*
5216 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5217 * just stops using VMX.
5218 */
5219 static void free_nested(struct vcpu_vmx *vmx)
5220 {
5221 if (!vmx->nested.vmxon)
5222 return;
5223 vmx->nested.vmxon = false;
5224 if (vmx->nested.current_vmptr != -1ull) {
5225 kunmap(vmx->nested.current_vmcs12_page);
5226 nested_release_page(vmx->nested.current_vmcs12_page);
5227 vmx->nested.current_vmptr = -1ull;
5228 vmx->nested.current_vmcs12 = NULL;
5229 }
5230 /* Unpin physical memory we referred to in current vmcs02 */
5231 if (vmx->nested.apic_access_page) {
5232 nested_release_page(vmx->nested.apic_access_page);
5233 vmx->nested.apic_access_page = 0;
5234 }
5235
5236 nested_free_all_saved_vmcss(vmx);
5237 }
5238
5239 /* Emulate the VMXOFF instruction */
5240 static int handle_vmoff(struct kvm_vcpu *vcpu)
5241 {
5242 if (!nested_vmx_check_permission(vcpu))
5243 return 1;
5244 free_nested(to_vmx(vcpu));
5245 skip_emulated_instruction(vcpu);
5246 return 1;
5247 }
5248
5249 /*
5250 * Decode the memory-address operand of a vmx instruction, as recorded on an
5251 * exit caused by such an instruction (run by a guest hypervisor).
5252 * On success, returns 0. When the operand is invalid, returns 1 and throws
5253 * #UD or #GP.
5254 */
5255 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5256 unsigned long exit_qualification,
5257 u32 vmx_instruction_info, gva_t *ret)
5258 {
5259 /*
5260 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5261 * Execution", on an exit, vmx_instruction_info holds most of the
5262 * addressing components of the operand. Only the displacement part
5263 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5264 * For how an actual address is calculated from all these components,
5265 * refer to Vol. 1, "Operand Addressing".
5266 */
5267 int scaling = vmx_instruction_info & 3;
5268 int addr_size = (vmx_instruction_info >> 7) & 7;
5269 bool is_reg = vmx_instruction_info & (1u << 10);
5270 int seg_reg = (vmx_instruction_info >> 15) & 7;
5271 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5272 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5273 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5274 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5275
5276 if (is_reg) {
5277 kvm_queue_exception(vcpu, UD_VECTOR);
5278 return 1;
5279 }
5280
5281 /* Addr = segment_base + offset */
5282 /* offset = base + [index * scale] + displacement */
5283 *ret = vmx_get_segment_base(vcpu, seg_reg);
5284 if (base_is_valid)
5285 *ret += kvm_register_read(vcpu, base_reg);
5286 if (index_is_valid)
5287 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5288 *ret += exit_qualification; /* holds the displacement */
5289
5290 if (addr_size == 1) /* 32 bit */
5291 *ret &= 0xffffffff;
5292
5293 /*
5294 * TODO: throw #GP (and return 1) in various cases that the VM*
5295 * instructions require it - e.g., offset beyond segment limit,
5296 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5297 * address, and so on. Currently these are not checked.
5298 */
5299 return 0;
5300 }
5301
5302 /*
5303 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5304 * set the success or error code of an emulated VMX instruction, as specified
5305 * by Vol 2B, VMX Instruction Reference, "Conventions".
5306 */
5307 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5308 {
5309 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5310 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5311 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5312 }
5313
5314 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5315 {
5316 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5317 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5318 X86_EFLAGS_SF | X86_EFLAGS_OF))
5319 | X86_EFLAGS_CF);
5320 }
5321
5322 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5323 u32 vm_instruction_error)
5324 {
5325 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5326 /*
5327 * failValid writes the error number to the current VMCS, which
5328 * can't be done there isn't a current VMCS.
5329 */
5330 nested_vmx_failInvalid(vcpu);
5331 return;
5332 }
5333 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5334 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5335 X86_EFLAGS_SF | X86_EFLAGS_OF))
5336 | X86_EFLAGS_ZF);
5337 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5338 }
5339
5340 /* Emulate the VMCLEAR instruction */
5341 static int handle_vmclear(struct kvm_vcpu *vcpu)
5342 {
5343 struct vcpu_vmx *vmx = to_vmx(vcpu);
5344 gva_t gva;
5345 gpa_t vmptr;
5346 struct vmcs12 *vmcs12;
5347 struct page *page;
5348 struct x86_exception e;
5349
5350 if (!nested_vmx_check_permission(vcpu))
5351 return 1;
5352
5353 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5354 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5355 return 1;
5356
5357 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5358 sizeof(vmptr), &e)) {
5359 kvm_inject_page_fault(vcpu, &e);
5360 return 1;
5361 }
5362
5363 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5364 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5365 skip_emulated_instruction(vcpu);
5366 return 1;
5367 }
5368
5369 if (vmptr == vmx->nested.current_vmptr) {
5370 kunmap(vmx->nested.current_vmcs12_page);
5371 nested_release_page(vmx->nested.current_vmcs12_page);
5372 vmx->nested.current_vmptr = -1ull;
5373 vmx->nested.current_vmcs12 = NULL;
5374 }
5375
5376 page = nested_get_page(vcpu, vmptr);
5377 if (page == NULL) {
5378 /*
5379 * For accurate processor emulation, VMCLEAR beyond available
5380 * physical memory should do nothing at all. However, it is
5381 * possible that a nested vmx bug, not a guest hypervisor bug,
5382 * resulted in this case, so let's shut down before doing any
5383 * more damage:
5384 */
5385 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5386 return 1;
5387 }
5388 vmcs12 = kmap(page);
5389 vmcs12->launch_state = 0;
5390 kunmap(page);
5391 nested_release_page(page);
5392
5393 nested_free_vmcs02(vmx, vmptr);
5394
5395 skip_emulated_instruction(vcpu);
5396 nested_vmx_succeed(vcpu);
5397 return 1;
5398 }
5399
5400 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5401
5402 /* Emulate the VMLAUNCH instruction */
5403 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5404 {
5405 return nested_vmx_run(vcpu, true);
5406 }
5407
5408 /* Emulate the VMRESUME instruction */
5409 static int handle_vmresume(struct kvm_vcpu *vcpu)
5410 {
5411
5412 return nested_vmx_run(vcpu, false);
5413 }
5414
5415 enum vmcs_field_type {
5416 VMCS_FIELD_TYPE_U16 = 0,
5417 VMCS_FIELD_TYPE_U64 = 1,
5418 VMCS_FIELD_TYPE_U32 = 2,
5419 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5420 };
5421
5422 static inline int vmcs_field_type(unsigned long field)
5423 {
5424 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5425 return VMCS_FIELD_TYPE_U32;
5426 return (field >> 13) & 0x3 ;
5427 }
5428
5429 static inline int vmcs_field_readonly(unsigned long field)
5430 {
5431 return (((field >> 10) & 0x3) == 1);
5432 }
5433
5434 /*
5435 * Read a vmcs12 field. Since these can have varying lengths and we return
5436 * one type, we chose the biggest type (u64) and zero-extend the return value
5437 * to that size. Note that the caller, handle_vmread, might need to use only
5438 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5439 * 64-bit fields are to be returned).
5440 */
5441 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5442 unsigned long field, u64 *ret)
5443 {
5444 short offset = vmcs_field_to_offset(field);
5445 char *p;
5446
5447 if (offset < 0)
5448 return 0;
5449
5450 p = ((char *)(get_vmcs12(vcpu))) + offset;
5451
5452 switch (vmcs_field_type(field)) {
5453 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5454 *ret = *((natural_width *)p);
5455 return 1;
5456 case VMCS_FIELD_TYPE_U16:
5457 *ret = *((u16 *)p);
5458 return 1;
5459 case VMCS_FIELD_TYPE_U32:
5460 *ret = *((u32 *)p);
5461 return 1;
5462 case VMCS_FIELD_TYPE_U64:
5463 *ret = *((u64 *)p);
5464 return 1;
5465 default:
5466 return 0; /* can never happen. */
5467 }
5468 }
5469
5470 /*
5471 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5472 * used before) all generate the same failure when it is missing.
5473 */
5474 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5475 {
5476 struct vcpu_vmx *vmx = to_vmx(vcpu);
5477 if (vmx->nested.current_vmptr == -1ull) {
5478 nested_vmx_failInvalid(vcpu);
5479 skip_emulated_instruction(vcpu);
5480 return 0;
5481 }
5482 return 1;
5483 }
5484
5485 static int handle_vmread(struct kvm_vcpu *vcpu)
5486 {
5487 unsigned long field;
5488 u64 field_value;
5489 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5490 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5491 gva_t gva = 0;
5492
5493 if (!nested_vmx_check_permission(vcpu) ||
5494 !nested_vmx_check_vmcs12(vcpu))
5495 return 1;
5496
5497 /* Decode instruction info and find the field to read */
5498 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5499 /* Read the field, zero-extended to a u64 field_value */
5500 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5501 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5502 skip_emulated_instruction(vcpu);
5503 return 1;
5504 }
5505 /*
5506 * Now copy part of this value to register or memory, as requested.
5507 * Note that the number of bits actually copied is 32 or 64 depending
5508 * on the guest's mode (32 or 64 bit), not on the given field's length.
5509 */
5510 if (vmx_instruction_info & (1u << 10)) {
5511 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5512 field_value);
5513 } else {
5514 if (get_vmx_mem_address(vcpu, exit_qualification,
5515 vmx_instruction_info, &gva))
5516 return 1;
5517 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5518 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5519 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5520 }
5521
5522 nested_vmx_succeed(vcpu);
5523 skip_emulated_instruction(vcpu);
5524 return 1;
5525 }
5526
5527
5528 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5529 {
5530 unsigned long field;
5531 gva_t gva;
5532 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5533 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5534 char *p;
5535 short offset;
5536 /* The value to write might be 32 or 64 bits, depending on L1's long
5537 * mode, and eventually we need to write that into a field of several
5538 * possible lengths. The code below first zero-extends the value to 64
5539 * bit (field_value), and then copies only the approriate number of
5540 * bits into the vmcs12 field.
5541 */
5542 u64 field_value = 0;
5543 struct x86_exception e;
5544
5545 if (!nested_vmx_check_permission(vcpu) ||
5546 !nested_vmx_check_vmcs12(vcpu))
5547 return 1;
5548
5549 if (vmx_instruction_info & (1u << 10))
5550 field_value = kvm_register_read(vcpu,
5551 (((vmx_instruction_info) >> 3) & 0xf));
5552 else {
5553 if (get_vmx_mem_address(vcpu, exit_qualification,
5554 vmx_instruction_info, &gva))
5555 return 1;
5556 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5557 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5558 kvm_inject_page_fault(vcpu, &e);
5559 return 1;
5560 }
5561 }
5562
5563
5564 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5565 if (vmcs_field_readonly(field)) {
5566 nested_vmx_failValid(vcpu,
5567 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5568 skip_emulated_instruction(vcpu);
5569 return 1;
5570 }
5571
5572 offset = vmcs_field_to_offset(field);
5573 if (offset < 0) {
5574 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5575 skip_emulated_instruction(vcpu);
5576 return 1;
5577 }
5578 p = ((char *) get_vmcs12(vcpu)) + offset;
5579
5580 switch (vmcs_field_type(field)) {
5581 case VMCS_FIELD_TYPE_U16:
5582 *(u16 *)p = field_value;
5583 break;
5584 case VMCS_FIELD_TYPE_U32:
5585 *(u32 *)p = field_value;
5586 break;
5587 case VMCS_FIELD_TYPE_U64:
5588 *(u64 *)p = field_value;
5589 break;
5590 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5591 *(natural_width *)p = field_value;
5592 break;
5593 default:
5594 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5595 skip_emulated_instruction(vcpu);
5596 return 1;
5597 }
5598
5599 nested_vmx_succeed(vcpu);
5600 skip_emulated_instruction(vcpu);
5601 return 1;
5602 }
5603
5604 /* Emulate the VMPTRLD instruction */
5605 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5606 {
5607 struct vcpu_vmx *vmx = to_vmx(vcpu);
5608 gva_t gva;
5609 gpa_t vmptr;
5610 struct x86_exception e;
5611
5612 if (!nested_vmx_check_permission(vcpu))
5613 return 1;
5614
5615 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5616 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5617 return 1;
5618
5619 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5620 sizeof(vmptr), &e)) {
5621 kvm_inject_page_fault(vcpu, &e);
5622 return 1;
5623 }
5624
5625 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5626 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5627 skip_emulated_instruction(vcpu);
5628 return 1;
5629 }
5630
5631 if (vmx->nested.current_vmptr != vmptr) {
5632 struct vmcs12 *new_vmcs12;
5633 struct page *page;
5634 page = nested_get_page(vcpu, vmptr);
5635 if (page == NULL) {
5636 nested_vmx_failInvalid(vcpu);
5637 skip_emulated_instruction(vcpu);
5638 return 1;
5639 }
5640 new_vmcs12 = kmap(page);
5641 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5642 kunmap(page);
5643 nested_release_page_clean(page);
5644 nested_vmx_failValid(vcpu,
5645 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5646 skip_emulated_instruction(vcpu);
5647 return 1;
5648 }
5649 if (vmx->nested.current_vmptr != -1ull) {
5650 kunmap(vmx->nested.current_vmcs12_page);
5651 nested_release_page(vmx->nested.current_vmcs12_page);
5652 }
5653
5654 vmx->nested.current_vmptr = vmptr;
5655 vmx->nested.current_vmcs12 = new_vmcs12;
5656 vmx->nested.current_vmcs12_page = page;
5657 }
5658
5659 nested_vmx_succeed(vcpu);
5660 skip_emulated_instruction(vcpu);
5661 return 1;
5662 }
5663
5664 /* Emulate the VMPTRST instruction */
5665 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5666 {
5667 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5668 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5669 gva_t vmcs_gva;
5670 struct x86_exception e;
5671
5672 if (!nested_vmx_check_permission(vcpu))
5673 return 1;
5674
5675 if (get_vmx_mem_address(vcpu, exit_qualification,
5676 vmx_instruction_info, &vmcs_gva))
5677 return 1;
5678 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5679 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5680 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5681 sizeof(u64), &e)) {
5682 kvm_inject_page_fault(vcpu, &e);
5683 return 1;
5684 }
5685 nested_vmx_succeed(vcpu);
5686 skip_emulated_instruction(vcpu);
5687 return 1;
5688 }
5689
5690 /*
5691 * The exit handlers return 1 if the exit was handled fully and guest execution
5692 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5693 * to be done to userspace and return 0.
5694 */
5695 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5696 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5697 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5698 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5699 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5700 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5701 [EXIT_REASON_CR_ACCESS] = handle_cr,
5702 [EXIT_REASON_DR_ACCESS] = handle_dr,
5703 [EXIT_REASON_CPUID] = handle_cpuid,
5704 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5705 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5706 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5707 [EXIT_REASON_HLT] = handle_halt,
5708 [EXIT_REASON_INVD] = handle_invd,
5709 [EXIT_REASON_INVLPG] = handle_invlpg,
5710 [EXIT_REASON_RDPMC] = handle_rdpmc,
5711 [EXIT_REASON_VMCALL] = handle_vmcall,
5712 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5713 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5714 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5715 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5716 [EXIT_REASON_VMREAD] = handle_vmread,
5717 [EXIT_REASON_VMRESUME] = handle_vmresume,
5718 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5719 [EXIT_REASON_VMOFF] = handle_vmoff,
5720 [EXIT_REASON_VMON] = handle_vmon,
5721 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5722 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5723 [EXIT_REASON_WBINVD] = handle_wbinvd,
5724 [EXIT_REASON_XSETBV] = handle_xsetbv,
5725 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5726 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5727 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5728 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5729 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5730 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5731 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5732 };
5733
5734 static const int kvm_vmx_max_exit_handlers =
5735 ARRAY_SIZE(kvm_vmx_exit_handlers);
5736
5737 /*
5738 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5739 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5740 * disinterest in the current event (read or write a specific MSR) by using an
5741 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5742 */
5743 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5744 struct vmcs12 *vmcs12, u32 exit_reason)
5745 {
5746 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5747 gpa_t bitmap;
5748
5749 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5750 return 1;
5751
5752 /*
5753 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5754 * for the four combinations of read/write and low/high MSR numbers.
5755 * First we need to figure out which of the four to use:
5756 */
5757 bitmap = vmcs12->msr_bitmap;
5758 if (exit_reason == EXIT_REASON_MSR_WRITE)
5759 bitmap += 2048;
5760 if (msr_index >= 0xc0000000) {
5761 msr_index -= 0xc0000000;
5762 bitmap += 1024;
5763 }
5764
5765 /* Then read the msr_index'th bit from this bitmap: */
5766 if (msr_index < 1024*8) {
5767 unsigned char b;
5768 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5769 return 1 & (b >> (msr_index & 7));
5770 } else
5771 return 1; /* let L1 handle the wrong parameter */
5772 }
5773
5774 /*
5775 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5776 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5777 * intercept (via guest_host_mask etc.) the current event.
5778 */
5779 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5780 struct vmcs12 *vmcs12)
5781 {
5782 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5783 int cr = exit_qualification & 15;
5784 int reg = (exit_qualification >> 8) & 15;
5785 unsigned long val = kvm_register_read(vcpu, reg);
5786
5787 switch ((exit_qualification >> 4) & 3) {
5788 case 0: /* mov to cr */
5789 switch (cr) {
5790 case 0:
5791 if (vmcs12->cr0_guest_host_mask &
5792 (val ^ vmcs12->cr0_read_shadow))
5793 return 1;
5794 break;
5795 case 3:
5796 if ((vmcs12->cr3_target_count >= 1 &&
5797 vmcs12->cr3_target_value0 == val) ||
5798 (vmcs12->cr3_target_count >= 2 &&
5799 vmcs12->cr3_target_value1 == val) ||
5800 (vmcs12->cr3_target_count >= 3 &&
5801 vmcs12->cr3_target_value2 == val) ||
5802 (vmcs12->cr3_target_count >= 4 &&
5803 vmcs12->cr3_target_value3 == val))
5804 return 0;
5805 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5806 return 1;
5807 break;
5808 case 4:
5809 if (vmcs12->cr4_guest_host_mask &
5810 (vmcs12->cr4_read_shadow ^ val))
5811 return 1;
5812 break;
5813 case 8:
5814 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5815 return 1;
5816 break;
5817 }
5818 break;
5819 case 2: /* clts */
5820 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5821 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5822 return 1;
5823 break;
5824 case 1: /* mov from cr */
5825 switch (cr) {
5826 case 3:
5827 if (vmcs12->cpu_based_vm_exec_control &
5828 CPU_BASED_CR3_STORE_EXITING)
5829 return 1;
5830 break;
5831 case 8:
5832 if (vmcs12->cpu_based_vm_exec_control &
5833 CPU_BASED_CR8_STORE_EXITING)
5834 return 1;
5835 break;
5836 }
5837 break;
5838 case 3: /* lmsw */
5839 /*
5840 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5841 * cr0. Other attempted changes are ignored, with no exit.
5842 */
5843 if (vmcs12->cr0_guest_host_mask & 0xe &
5844 (val ^ vmcs12->cr0_read_shadow))
5845 return 1;
5846 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5847 !(vmcs12->cr0_read_shadow & 0x1) &&
5848 (val & 0x1))
5849 return 1;
5850 break;
5851 }
5852 return 0;
5853 }
5854
5855 /*
5856 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5857 * should handle it ourselves in L0 (and then continue L2). Only call this
5858 * when in is_guest_mode (L2).
5859 */
5860 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5861 {
5862 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5863 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5864 struct vcpu_vmx *vmx = to_vmx(vcpu);
5865 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5866
5867 if (vmx->nested.nested_run_pending)
5868 return 0;
5869
5870 if (unlikely(vmx->fail)) {
5871 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5872 vmcs_read32(VM_INSTRUCTION_ERROR));
5873 return 1;
5874 }
5875
5876 switch (exit_reason) {
5877 case EXIT_REASON_EXCEPTION_NMI:
5878 if (!is_exception(intr_info))
5879 return 0;
5880 else if (is_page_fault(intr_info))
5881 return enable_ept;
5882 return vmcs12->exception_bitmap &
5883 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5884 case EXIT_REASON_EXTERNAL_INTERRUPT:
5885 return 0;
5886 case EXIT_REASON_TRIPLE_FAULT:
5887 return 1;
5888 case EXIT_REASON_PENDING_INTERRUPT:
5889 case EXIT_REASON_NMI_WINDOW:
5890 /*
5891 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5892 * (aka Interrupt Window Exiting) only when L1 turned it on,
5893 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5894 * Same for NMI Window Exiting.
5895 */
5896 return 1;
5897 case EXIT_REASON_TASK_SWITCH:
5898 return 1;
5899 case EXIT_REASON_CPUID:
5900 return 1;
5901 case EXIT_REASON_HLT:
5902 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5903 case EXIT_REASON_INVD:
5904 return 1;
5905 case EXIT_REASON_INVLPG:
5906 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5907 case EXIT_REASON_RDPMC:
5908 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5909 case EXIT_REASON_RDTSC:
5910 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5911 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5912 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5913 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5914 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5915 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5916 /*
5917 * VMX instructions trap unconditionally. This allows L1 to
5918 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5919 */
5920 return 1;
5921 case EXIT_REASON_CR_ACCESS:
5922 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5923 case EXIT_REASON_DR_ACCESS:
5924 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5925 case EXIT_REASON_IO_INSTRUCTION:
5926 /* TODO: support IO bitmaps */
5927 return 1;
5928 case EXIT_REASON_MSR_READ:
5929 case EXIT_REASON_MSR_WRITE:
5930 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5931 case EXIT_REASON_INVALID_STATE:
5932 return 1;
5933 case EXIT_REASON_MWAIT_INSTRUCTION:
5934 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5935 case EXIT_REASON_MONITOR_INSTRUCTION:
5936 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5937 case EXIT_REASON_PAUSE_INSTRUCTION:
5938 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5939 nested_cpu_has2(vmcs12,
5940 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5941 case EXIT_REASON_MCE_DURING_VMENTRY:
5942 return 0;
5943 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5944 return 1;
5945 case EXIT_REASON_APIC_ACCESS:
5946 return nested_cpu_has2(vmcs12,
5947 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5948 case EXIT_REASON_EPT_VIOLATION:
5949 case EXIT_REASON_EPT_MISCONFIG:
5950 return 0;
5951 case EXIT_REASON_WBINVD:
5952 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5953 case EXIT_REASON_XSETBV:
5954 return 1;
5955 default:
5956 return 1;
5957 }
5958 }
5959
5960 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5961 {
5962 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5963 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5964 }
5965
5966 /*
5967 * The guest has exited. See if we can fix it or if we need userspace
5968 * assistance.
5969 */
5970 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5971 {
5972 struct vcpu_vmx *vmx = to_vmx(vcpu);
5973 u32 exit_reason = vmx->exit_reason;
5974 u32 vectoring_info = vmx->idt_vectoring_info;
5975
5976 /* If guest state is invalid, start emulating */
5977 if (vmx->emulation_required && emulate_invalid_guest_state)
5978 return handle_invalid_guest_state(vcpu);
5979
5980 /*
5981 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5982 * we did not inject a still-pending event to L1 now because of
5983 * nested_run_pending, we need to re-enable this bit.
5984 */
5985 if (vmx->nested.nested_run_pending)
5986 kvm_make_request(KVM_REQ_EVENT, vcpu);
5987
5988 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5989 exit_reason == EXIT_REASON_VMRESUME))
5990 vmx->nested.nested_run_pending = 1;
5991 else
5992 vmx->nested.nested_run_pending = 0;
5993
5994 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5995 nested_vmx_vmexit(vcpu);
5996 return 1;
5997 }
5998
5999 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
6000 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6001 vcpu->run->fail_entry.hardware_entry_failure_reason
6002 = exit_reason;
6003 return 0;
6004 }
6005
6006 if (unlikely(vmx->fail)) {
6007 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
6008 vcpu->run->fail_entry.hardware_entry_failure_reason
6009 = vmcs_read32(VM_INSTRUCTION_ERROR);
6010 return 0;
6011 }
6012
6013 /*
6014 * Note:
6015 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6016 * delivery event since it indicates guest is accessing MMIO.
6017 * The vm-exit can be triggered again after return to guest that
6018 * will cause infinite loop.
6019 */
6020 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
6021 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
6022 exit_reason != EXIT_REASON_EPT_VIOLATION &&
6023 exit_reason != EXIT_REASON_TASK_SWITCH)) {
6024 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6025 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
6026 vcpu->run->internal.ndata = 2;
6027 vcpu->run->internal.data[0] = vectoring_info;
6028 vcpu->run->internal.data[1] = exit_reason;
6029 return 0;
6030 }
6031
6032 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
6033 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
6034 get_vmcs12(vcpu), vcpu)))) {
6035 if (vmx_interrupt_allowed(vcpu)) {
6036 vmx->soft_vnmi_blocked = 0;
6037 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
6038 vcpu->arch.nmi_pending) {
6039 /*
6040 * This CPU don't support us in finding the end of an
6041 * NMI-blocked window if the guest runs with IRQs
6042 * disabled. So we pull the trigger after 1 s of
6043 * futile waiting, but inform the user about this.
6044 */
6045 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
6046 "state on VCPU %d after 1 s timeout\n",
6047 __func__, vcpu->vcpu_id);
6048 vmx->soft_vnmi_blocked = 0;
6049 }
6050 }
6051
6052 if (exit_reason < kvm_vmx_max_exit_handlers
6053 && kvm_vmx_exit_handlers[exit_reason])
6054 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6055 else {
6056 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6057 vcpu->run->hw.hardware_exit_reason = exit_reason;
6058 }
6059 return 0;
6060 }
6061
6062 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6063 {
6064 if (irr == -1 || tpr < irr) {
6065 vmcs_write32(TPR_THRESHOLD, 0);
6066 return;
6067 }
6068
6069 vmcs_write32(TPR_THRESHOLD, irr);
6070 }
6071
6072 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
6073 {
6074 u32 exit_intr_info;
6075
6076 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
6077 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
6078 return;
6079
6080 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6081 exit_intr_info = vmx->exit_intr_info;
6082
6083 /* Handle machine checks before interrupts are enabled */
6084 if (is_machine_check(exit_intr_info))
6085 kvm_machine_check();
6086
6087 /* We need to handle NMIs before interrupts are enabled */
6088 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
6089 (exit_intr_info & INTR_INFO_VALID_MASK)) {
6090 kvm_before_handle_nmi(&vmx->vcpu);
6091 asm("int $2");
6092 kvm_after_handle_nmi(&vmx->vcpu);
6093 }
6094 }
6095
6096 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
6097 {
6098 u32 exit_intr_info;
6099 bool unblock_nmi;
6100 u8 vector;
6101 bool idtv_info_valid;
6102
6103 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6104
6105 if (cpu_has_virtual_nmis()) {
6106 if (vmx->nmi_known_unmasked)
6107 return;
6108 /*
6109 * Can't use vmx->exit_intr_info since we're not sure what
6110 * the exit reason is.
6111 */
6112 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6113 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
6114 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
6115 /*
6116 * SDM 3: 27.7.1.2 (September 2008)
6117 * Re-set bit "block by NMI" before VM entry if vmexit caused by
6118 * a guest IRET fault.
6119 * SDM 3: 23.2.2 (September 2008)
6120 * Bit 12 is undefined in any of the following cases:
6121 * If the VM exit sets the valid bit in the IDT-vectoring
6122 * information field.
6123 * If the VM exit is due to a double fault.
6124 */
6125 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
6126 vector != DF_VECTOR && !idtv_info_valid)
6127 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
6128 GUEST_INTR_STATE_NMI);
6129 else
6130 vmx->nmi_known_unmasked =
6131 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
6132 & GUEST_INTR_STATE_NMI);
6133 } else if (unlikely(vmx->soft_vnmi_blocked))
6134 vmx->vnmi_blocked_time +=
6135 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
6136 }
6137
6138 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
6139 u32 idt_vectoring_info,
6140 int instr_len_field,
6141 int error_code_field)
6142 {
6143 u8 vector;
6144 int type;
6145 bool idtv_info_valid;
6146
6147 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
6148
6149 vmx->vcpu.arch.nmi_injected = false;
6150 kvm_clear_exception_queue(&vmx->vcpu);
6151 kvm_clear_interrupt_queue(&vmx->vcpu);
6152
6153 if (!idtv_info_valid)
6154 return;
6155
6156 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6157
6158 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6159 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6160
6161 switch (type) {
6162 case INTR_TYPE_NMI_INTR:
6163 vmx->vcpu.arch.nmi_injected = true;
6164 /*
6165 * SDM 3: 27.7.1.2 (September 2008)
6166 * Clear bit "block by NMI" before VM entry if a NMI
6167 * delivery faulted.
6168 */
6169 vmx_set_nmi_mask(&vmx->vcpu, false);
6170 break;
6171 case INTR_TYPE_SOFT_EXCEPTION:
6172 vmx->vcpu.arch.event_exit_inst_len =
6173 vmcs_read32(instr_len_field);
6174 /* fall through */
6175 case INTR_TYPE_HARD_EXCEPTION:
6176 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6177 u32 err = vmcs_read32(error_code_field);
6178 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6179 } else
6180 kvm_queue_exception(&vmx->vcpu, vector);
6181 break;
6182 case INTR_TYPE_SOFT_INTR:
6183 vmx->vcpu.arch.event_exit_inst_len =
6184 vmcs_read32(instr_len_field);
6185 /* fall through */
6186 case INTR_TYPE_EXT_INTR:
6187 kvm_queue_interrupt(&vmx->vcpu, vector,
6188 type == INTR_TYPE_SOFT_INTR);
6189 break;
6190 default:
6191 break;
6192 }
6193 }
6194
6195 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6196 {
6197 if (is_guest_mode(&vmx->vcpu))
6198 return;
6199 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6200 VM_EXIT_INSTRUCTION_LEN,
6201 IDT_VECTORING_ERROR_CODE);
6202 }
6203
6204 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6205 {
6206 if (is_guest_mode(vcpu))
6207 return;
6208 __vmx_complete_interrupts(to_vmx(vcpu),
6209 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6210 VM_ENTRY_INSTRUCTION_LEN,
6211 VM_ENTRY_EXCEPTION_ERROR_CODE);
6212
6213 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6214 }
6215
6216 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6217 {
6218 int i, nr_msrs;
6219 struct perf_guest_switch_msr *msrs;
6220
6221 msrs = perf_guest_get_msrs(&nr_msrs);
6222
6223 if (!msrs)
6224 return;
6225
6226 for (i = 0; i < nr_msrs; i++)
6227 if (msrs[i].host == msrs[i].guest)
6228 clear_atomic_switch_msr(vmx, msrs[i].msr);
6229 else
6230 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6231 msrs[i].host);
6232 }
6233
6234 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6235 {
6236 struct vcpu_vmx *vmx = to_vmx(vcpu);
6237 unsigned long debugctlmsr;
6238
6239 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6240 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6241 if (vmcs12->idt_vectoring_info_field &
6242 VECTORING_INFO_VALID_MASK) {
6243 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6244 vmcs12->idt_vectoring_info_field);
6245 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6246 vmcs12->vm_exit_instruction_len);
6247 if (vmcs12->idt_vectoring_info_field &
6248 VECTORING_INFO_DELIVER_CODE_MASK)
6249 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6250 vmcs12->idt_vectoring_error_code);
6251 }
6252 }
6253
6254 /* Record the guest's net vcpu time for enforced NMI injections. */
6255 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6256 vmx->entry_time = ktime_get();
6257
6258 /* Don't enter VMX if guest state is invalid, let the exit handler
6259 start emulation until we arrive back to a valid state */
6260 if (vmx->emulation_required && emulate_invalid_guest_state)
6261 return;
6262
6263 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6264 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6265 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6266 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6267
6268 /* When single-stepping over STI and MOV SS, we must clear the
6269 * corresponding interruptibility bits in the guest state. Otherwise
6270 * vmentry fails as it then expects bit 14 (BS) in pending debug
6271 * exceptions being set, but that's not correct for the guest debugging
6272 * case. */
6273 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6274 vmx_set_interrupt_shadow(vcpu, 0);
6275
6276 atomic_switch_perf_msrs(vmx);
6277 debugctlmsr = get_debugctlmsr();
6278
6279 vmx->__launched = vmx->loaded_vmcs->launched;
6280 asm(
6281 /* Store host registers */
6282 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6283 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6284 "push %%" _ASM_CX " \n\t"
6285 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6286 "je 1f \n\t"
6287 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6288 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6289 "1: \n\t"
6290 /* Reload cr2 if changed */
6291 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6292 "mov %%cr2, %%" _ASM_DX " \n\t"
6293 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6294 "je 2f \n\t"
6295 "mov %%" _ASM_AX", %%cr2 \n\t"
6296 "2: \n\t"
6297 /* Check if vmlaunch of vmresume is needed */
6298 "cmpl $0, %c[launched](%0) \n\t"
6299 /* Load guest registers. Don't clobber flags. */
6300 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6301 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6302 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6303 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6304 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6305 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6306 #ifdef CONFIG_X86_64
6307 "mov %c[r8](%0), %%r8 \n\t"
6308 "mov %c[r9](%0), %%r9 \n\t"
6309 "mov %c[r10](%0), %%r10 \n\t"
6310 "mov %c[r11](%0), %%r11 \n\t"
6311 "mov %c[r12](%0), %%r12 \n\t"
6312 "mov %c[r13](%0), %%r13 \n\t"
6313 "mov %c[r14](%0), %%r14 \n\t"
6314 "mov %c[r15](%0), %%r15 \n\t"
6315 #endif
6316 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
6317
6318 /* Enter guest mode */
6319 "jne 1f \n\t"
6320 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6321 "jmp 2f \n\t"
6322 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
6323 "2: "
6324 /* Save guest registers, load host registers, keep flags */
6325 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6326 "pop %0 \n\t"
6327 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6328 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6329 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6330 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6331 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6332 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6333 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6334 #ifdef CONFIG_X86_64
6335 "mov %%r8, %c[r8](%0) \n\t"
6336 "mov %%r9, %c[r9](%0) \n\t"
6337 "mov %%r10, %c[r10](%0) \n\t"
6338 "mov %%r11, %c[r11](%0) \n\t"
6339 "mov %%r12, %c[r12](%0) \n\t"
6340 "mov %%r13, %c[r13](%0) \n\t"
6341 "mov %%r14, %c[r14](%0) \n\t"
6342 "mov %%r15, %c[r15](%0) \n\t"
6343 #endif
6344 "mov %%cr2, %%" _ASM_AX " \n\t"
6345 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
6346
6347 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6348 "setbe %c[fail](%0) \n\t"
6349 ".pushsection .rodata \n\t"
6350 ".global vmx_return \n\t"
6351 "vmx_return: " _ASM_PTR " 2b \n\t"
6352 ".popsection"
6353 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6354 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6355 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6356 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6357 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6358 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6359 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6360 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6361 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6362 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6363 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6364 #ifdef CONFIG_X86_64
6365 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6366 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6367 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6368 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6369 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6370 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6371 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6372 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6373 #endif
6374 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6375 [wordsize]"i"(sizeof(ulong))
6376 : "cc", "memory"
6377 #ifdef CONFIG_X86_64
6378 , "rax", "rbx", "rdi", "rsi"
6379 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6380 #else
6381 , "eax", "ebx", "edi", "esi"
6382 #endif
6383 );
6384
6385 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6386 if (debugctlmsr)
6387 update_debugctlmsr(debugctlmsr);
6388
6389 #ifndef CONFIG_X86_64
6390 /*
6391 * The sysexit path does not restore ds/es, so we must set them to
6392 * a reasonable value ourselves.
6393 *
6394 * We can't defer this to vmx_load_host_state() since that function
6395 * may be executed in interrupt context, which saves and restore segments
6396 * around it, nullifying its effect.
6397 */
6398 loadsegment(ds, __USER_DS);
6399 loadsegment(es, __USER_DS);
6400 #endif
6401
6402 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6403 | (1 << VCPU_EXREG_RFLAGS)
6404 | (1 << VCPU_EXREG_CPL)
6405 | (1 << VCPU_EXREG_PDPTR)
6406 | (1 << VCPU_EXREG_SEGMENTS)
6407 | (1 << VCPU_EXREG_CR3));
6408 vcpu->arch.regs_dirty = 0;
6409
6410 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6411
6412 if (is_guest_mode(vcpu)) {
6413 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6414 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6415 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6416 vmcs12->idt_vectoring_error_code =
6417 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6418 vmcs12->vm_exit_instruction_len =
6419 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6420 }
6421 }
6422
6423 vmx->loaded_vmcs->launched = 1;
6424
6425 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6426 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6427
6428 vmx_complete_atomic_exit(vmx);
6429 vmx_recover_nmi_blocking(vmx);
6430 vmx_complete_interrupts(vmx);
6431 }
6432
6433 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6434 {
6435 struct vcpu_vmx *vmx = to_vmx(vcpu);
6436
6437 free_vpid(vmx);
6438 free_nested(vmx);
6439 free_loaded_vmcs(vmx->loaded_vmcs);
6440 kfree(vmx->guest_msrs);
6441 kvm_vcpu_uninit(vcpu);
6442 kmem_cache_free(kvm_vcpu_cache, vmx);
6443 }
6444
6445 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6446 {
6447 int err;
6448 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6449 int cpu;
6450
6451 if (!vmx)
6452 return ERR_PTR(-ENOMEM);
6453
6454 allocate_vpid(vmx);
6455
6456 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6457 if (err)
6458 goto free_vcpu;
6459
6460 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6461 err = -ENOMEM;
6462 if (!vmx->guest_msrs) {
6463 goto uninit_vcpu;
6464 }
6465
6466 vmx->loaded_vmcs = &vmx->vmcs01;
6467 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6468 if (!vmx->loaded_vmcs->vmcs)
6469 goto free_msrs;
6470 if (!vmm_exclusive)
6471 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6472 loaded_vmcs_init(vmx->loaded_vmcs);
6473 if (!vmm_exclusive)
6474 kvm_cpu_vmxoff();
6475
6476 cpu = get_cpu();
6477 vmx_vcpu_load(&vmx->vcpu, cpu);
6478 vmx->vcpu.cpu = cpu;
6479 err = vmx_vcpu_setup(vmx);
6480 vmx_vcpu_put(&vmx->vcpu);
6481 put_cpu();
6482 if (err)
6483 goto free_vmcs;
6484 if (vm_need_virtualize_apic_accesses(kvm))
6485 err = alloc_apic_access_page(kvm);
6486 if (err)
6487 goto free_vmcs;
6488
6489 if (enable_ept) {
6490 if (!kvm->arch.ept_identity_map_addr)
6491 kvm->arch.ept_identity_map_addr =
6492 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6493 err = -ENOMEM;
6494 if (alloc_identity_pagetable(kvm) != 0)
6495 goto free_vmcs;
6496 if (!init_rmode_identity_map(kvm))
6497 goto free_vmcs;
6498 }
6499
6500 vmx->nested.current_vmptr = -1ull;
6501 vmx->nested.current_vmcs12 = NULL;
6502
6503 return &vmx->vcpu;
6504
6505 free_vmcs:
6506 free_loaded_vmcs(vmx->loaded_vmcs);
6507 free_msrs:
6508 kfree(vmx->guest_msrs);
6509 uninit_vcpu:
6510 kvm_vcpu_uninit(&vmx->vcpu);
6511 free_vcpu:
6512 free_vpid(vmx);
6513 kmem_cache_free(kvm_vcpu_cache, vmx);
6514 return ERR_PTR(err);
6515 }
6516
6517 static void __init vmx_check_processor_compat(void *rtn)
6518 {
6519 struct vmcs_config vmcs_conf;
6520
6521 *(int *)rtn = 0;
6522 if (setup_vmcs_config(&vmcs_conf) < 0)
6523 *(int *)rtn = -EIO;
6524 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6525 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6526 smp_processor_id());
6527 *(int *)rtn = -EIO;
6528 }
6529 }
6530
6531 static int get_ept_level(void)
6532 {
6533 return VMX_EPT_DEFAULT_GAW + 1;
6534 }
6535
6536 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6537 {
6538 u64 ret;
6539
6540 /* For VT-d and EPT combination
6541 * 1. MMIO: always map as UC
6542 * 2. EPT with VT-d:
6543 * a. VT-d without snooping control feature: can't guarantee the
6544 * result, try to trust guest.
6545 * b. VT-d with snooping control feature: snooping control feature of
6546 * VT-d engine can guarantee the cache correctness. Just set it
6547 * to WB to keep consistent with host. So the same as item 3.
6548 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6549 * consistent with host MTRR
6550 */
6551 if (is_mmio)
6552 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6553 else if (vcpu->kvm->arch.iommu_domain &&
6554 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6555 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6556 VMX_EPT_MT_EPTE_SHIFT;
6557 else
6558 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6559 | VMX_EPT_IPAT_BIT;
6560
6561 return ret;
6562 }
6563
6564 static int vmx_get_lpage_level(void)
6565 {
6566 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6567 return PT_DIRECTORY_LEVEL;
6568 else
6569 /* For shadow and EPT supported 1GB page */
6570 return PT_PDPE_LEVEL;
6571 }
6572
6573 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6574 {
6575 struct kvm_cpuid_entry2 *best;
6576 struct vcpu_vmx *vmx = to_vmx(vcpu);
6577 u32 exec_control;
6578
6579 vmx->rdtscp_enabled = false;
6580 if (vmx_rdtscp_supported()) {
6581 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6582 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6583 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6584 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6585 vmx->rdtscp_enabled = true;
6586 else {
6587 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6588 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6589 exec_control);
6590 }
6591 }
6592 }
6593
6594 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6595 /* Exposing INVPCID only when PCID is exposed */
6596 best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6597 if (vmx_invpcid_supported() &&
6598 best && (best->ebx & bit(X86_FEATURE_INVPCID)) &&
6599 guest_cpuid_has_pcid(vcpu)) {
6600 exec_control |= SECONDARY_EXEC_ENABLE_INVPCID;
6601 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6602 exec_control);
6603 } else {
6604 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
6605 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6606 exec_control);
6607 if (best)
6608 best->ebx &= ~bit(X86_FEATURE_INVPCID);
6609 }
6610 }
6611
6612 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6613 {
6614 if (func == 1 && nested)
6615 entry->ecx |= bit(X86_FEATURE_VMX);
6616 }
6617
6618 /*
6619 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6620 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6621 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6622 * guest in a way that will both be appropriate to L1's requests, and our
6623 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6624 * function also has additional necessary side-effects, like setting various
6625 * vcpu->arch fields.
6626 */
6627 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6628 {
6629 struct vcpu_vmx *vmx = to_vmx(vcpu);
6630 u32 exec_control;
6631
6632 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6633 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6634 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6635 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6636 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6637 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6638 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6639 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6640 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6641 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6642 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6643 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6644 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6645 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6646 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6647 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6648 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6649 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6650 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6651 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6652 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6653 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6654 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6655 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6656 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6657 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6658 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6659 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6660 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6661 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6662 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6663 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6664 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6665 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6666 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6667 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6668
6669 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6670 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6671 vmcs12->vm_entry_intr_info_field);
6672 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6673 vmcs12->vm_entry_exception_error_code);
6674 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6675 vmcs12->vm_entry_instruction_len);
6676 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6677 vmcs12->guest_interruptibility_info);
6678 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6679 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6680 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6681 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6682 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6683 vmcs12->guest_pending_dbg_exceptions);
6684 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6685 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6686
6687 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6688
6689 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6690 (vmcs_config.pin_based_exec_ctrl |
6691 vmcs12->pin_based_vm_exec_control));
6692
6693 /*
6694 * Whether page-faults are trapped is determined by a combination of
6695 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6696 * If enable_ept, L0 doesn't care about page faults and we should
6697 * set all of these to L1's desires. However, if !enable_ept, L0 does
6698 * care about (at least some) page faults, and because it is not easy
6699 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6700 * to exit on each and every L2 page fault. This is done by setting
6701 * MASK=MATCH=0 and (see below) EB.PF=1.
6702 * Note that below we don't need special code to set EB.PF beyond the
6703 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6704 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6705 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6706 *
6707 * A problem with this approach (when !enable_ept) is that L1 may be
6708 * injected with more page faults than it asked for. This could have
6709 * caused problems, but in practice existing hypervisors don't care.
6710 * To fix this, we will need to emulate the PFEC checking (on the L1
6711 * page tables), using walk_addr(), when injecting PFs to L1.
6712 */
6713 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6714 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6715 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6716 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6717
6718 if (cpu_has_secondary_exec_ctrls()) {
6719 u32 exec_control = vmx_secondary_exec_control(vmx);
6720 if (!vmx->rdtscp_enabled)
6721 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6722 /* Take the following fields only from vmcs12 */
6723 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6724 if (nested_cpu_has(vmcs12,
6725 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6726 exec_control |= vmcs12->secondary_vm_exec_control;
6727
6728 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6729 /*
6730 * Translate L1 physical address to host physical
6731 * address for vmcs02. Keep the page pinned, so this
6732 * physical address remains valid. We keep a reference
6733 * to it so we can release it later.
6734 */
6735 if (vmx->nested.apic_access_page) /* shouldn't happen */
6736 nested_release_page(vmx->nested.apic_access_page);
6737 vmx->nested.apic_access_page =
6738 nested_get_page(vcpu, vmcs12->apic_access_addr);
6739 /*
6740 * If translation failed, no matter: This feature asks
6741 * to exit when accessing the given address, and if it
6742 * can never be accessed, this feature won't do
6743 * anything anyway.
6744 */
6745 if (!vmx->nested.apic_access_page)
6746 exec_control &=
6747 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6748 else
6749 vmcs_write64(APIC_ACCESS_ADDR,
6750 page_to_phys(vmx->nested.apic_access_page));
6751 }
6752
6753 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6754 }
6755
6756
6757 /*
6758 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6759 * Some constant fields are set here by vmx_set_constant_host_state().
6760 * Other fields are different per CPU, and will be set later when
6761 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6762 */
6763 vmx_set_constant_host_state();
6764
6765 /*
6766 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6767 * entry, but only if the current (host) sp changed from the value
6768 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6769 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6770 * here we just force the write to happen on entry.
6771 */
6772 vmx->host_rsp = 0;
6773
6774 exec_control = vmx_exec_control(vmx); /* L0's desires */
6775 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6776 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6777 exec_control &= ~CPU_BASED_TPR_SHADOW;
6778 exec_control |= vmcs12->cpu_based_vm_exec_control;
6779 /*
6780 * Merging of IO and MSR bitmaps not currently supported.
6781 * Rather, exit every time.
6782 */
6783 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6784 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6785 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6786
6787 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6788
6789 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6790 * bitwise-or of what L1 wants to trap for L2, and what we want to
6791 * trap. Note that CR0.TS also needs updating - we do this later.
6792 */
6793 update_exception_bitmap(vcpu);
6794 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6795 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6796
6797 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6798 vmcs_write32(VM_EXIT_CONTROLS,
6799 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6800 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6801 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6802
6803 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6804 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6805 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6806 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6807
6808
6809 set_cr4_guest_host_mask(vmx);
6810
6811 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6812 vmcs_write64(TSC_OFFSET,
6813 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6814 else
6815 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6816
6817 if (enable_vpid) {
6818 /*
6819 * Trivially support vpid by letting L2s share their parent
6820 * L1's vpid. TODO: move to a more elaborate solution, giving
6821 * each L2 its own vpid and exposing the vpid feature to L1.
6822 */
6823 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6824 vmx_flush_tlb(vcpu);
6825 }
6826
6827 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6828 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6829 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6830 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6831 else
6832 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6833 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6834 vmx_set_efer(vcpu, vcpu->arch.efer);
6835
6836 /*
6837 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6838 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6839 * The CR0_READ_SHADOW is what L2 should have expected to read given
6840 * the specifications by L1; It's not enough to take
6841 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6842 * have more bits than L1 expected.
6843 */
6844 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6845 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6846
6847 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6848 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6849
6850 /* shadow page tables on either EPT or shadow page tables */
6851 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6852 kvm_mmu_reset_context(vcpu);
6853
6854 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6855 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6856 }
6857
6858 /*
6859 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6860 * for running an L2 nested guest.
6861 */
6862 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6863 {
6864 struct vmcs12 *vmcs12;
6865 struct vcpu_vmx *vmx = to_vmx(vcpu);
6866 int cpu;
6867 struct loaded_vmcs *vmcs02;
6868
6869 if (!nested_vmx_check_permission(vcpu) ||
6870 !nested_vmx_check_vmcs12(vcpu))
6871 return 1;
6872
6873 skip_emulated_instruction(vcpu);
6874 vmcs12 = get_vmcs12(vcpu);
6875
6876 /*
6877 * The nested entry process starts with enforcing various prerequisites
6878 * on vmcs12 as required by the Intel SDM, and act appropriately when
6879 * they fail: As the SDM explains, some conditions should cause the
6880 * instruction to fail, while others will cause the instruction to seem
6881 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6882 * To speed up the normal (success) code path, we should avoid checking
6883 * for misconfigurations which will anyway be caught by the processor
6884 * when using the merged vmcs02.
6885 */
6886 if (vmcs12->launch_state == launch) {
6887 nested_vmx_failValid(vcpu,
6888 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6889 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6890 return 1;
6891 }
6892
6893 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6894 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6895 /*TODO: Also verify bits beyond physical address width are 0*/
6896 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6897 return 1;
6898 }
6899
6900 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6901 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6902 /*TODO: Also verify bits beyond physical address width are 0*/
6903 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6904 return 1;
6905 }
6906
6907 if (vmcs12->vm_entry_msr_load_count > 0 ||
6908 vmcs12->vm_exit_msr_load_count > 0 ||
6909 vmcs12->vm_exit_msr_store_count > 0) {
6910 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6911 __func__);
6912 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6913 return 1;
6914 }
6915
6916 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6917 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6918 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6919 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6920 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6921 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6922 !vmx_control_verify(vmcs12->vm_exit_controls,
6923 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6924 !vmx_control_verify(vmcs12->vm_entry_controls,
6925 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6926 {
6927 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6928 return 1;
6929 }
6930
6931 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6932 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6933 nested_vmx_failValid(vcpu,
6934 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6935 return 1;
6936 }
6937
6938 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6939 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6940 nested_vmx_entry_failure(vcpu, vmcs12,
6941 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6942 return 1;
6943 }
6944 if (vmcs12->vmcs_link_pointer != -1ull) {
6945 nested_vmx_entry_failure(vcpu, vmcs12,
6946 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6947 return 1;
6948 }
6949
6950 /*
6951 * We're finally done with prerequisite checking, and can start with
6952 * the nested entry.
6953 */
6954
6955 vmcs02 = nested_get_current_vmcs02(vmx);
6956 if (!vmcs02)
6957 return -ENOMEM;
6958
6959 enter_guest_mode(vcpu);
6960
6961 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6962
6963 cpu = get_cpu();
6964 vmx->loaded_vmcs = vmcs02;
6965 vmx_vcpu_put(vcpu);
6966 vmx_vcpu_load(vcpu, cpu);
6967 vcpu->cpu = cpu;
6968 put_cpu();
6969
6970 vmcs12->launch_state = 1;
6971
6972 prepare_vmcs02(vcpu, vmcs12);
6973
6974 /*
6975 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6976 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6977 * returned as far as L1 is concerned. It will only return (and set
6978 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6979 */
6980 return 1;
6981 }
6982
6983 /*
6984 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6985 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6986 * This function returns the new value we should put in vmcs12.guest_cr0.
6987 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6988 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6989 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6990 * didn't trap the bit, because if L1 did, so would L0).
6991 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6992 * been modified by L2, and L1 knows it. So just leave the old value of
6993 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6994 * isn't relevant, because if L0 traps this bit it can set it to anything.
6995 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6996 * changed these bits, and therefore they need to be updated, but L0
6997 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6998 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6999 */
7000 static inline unsigned long
7001 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7002 {
7003 return
7004 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
7005 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
7006 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
7007 vcpu->arch.cr0_guest_owned_bits));
7008 }
7009
7010 static inline unsigned long
7011 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7012 {
7013 return
7014 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
7015 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
7016 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
7017 vcpu->arch.cr4_guest_owned_bits));
7018 }
7019
7020 /*
7021 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
7022 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
7023 * and this function updates it to reflect the changes to the guest state while
7024 * L2 was running (and perhaps made some exits which were handled directly by L0
7025 * without going back to L1), and to reflect the exit reason.
7026 * Note that we do not have to copy here all VMCS fields, just those that
7027 * could have changed by the L2 guest or the exit - i.e., the guest-state and
7028 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
7029 * which already writes to vmcs12 directly.
7030 */
7031 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7032 {
7033 /* update guest state fields: */
7034 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
7035 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
7036
7037 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
7038 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
7039 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
7040 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
7041
7042 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
7043 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
7044 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
7045 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
7046 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
7047 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
7048 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
7049 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
7050 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
7051 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
7052 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
7053 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
7054 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
7055 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
7056 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
7057 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
7058 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
7059 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
7060 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
7061 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
7062 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
7063 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
7064 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
7065 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
7066 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
7067 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
7068 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
7069 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
7070 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
7071 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
7072 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
7073 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
7074 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
7075 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
7076 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
7077 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
7078
7079 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
7080 vmcs12->guest_interruptibility_info =
7081 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
7082 vmcs12->guest_pending_dbg_exceptions =
7083 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
7084
7085 /* TODO: These cannot have changed unless we have MSR bitmaps and
7086 * the relevant bit asks not to trap the change */
7087 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
7088 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
7089 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
7090 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
7091 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
7092 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
7093
7094 /* update exit information fields: */
7095
7096 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
7097 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7098
7099 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7100 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
7101 vmcs12->idt_vectoring_info_field =
7102 vmcs_read32(IDT_VECTORING_INFO_FIELD);
7103 vmcs12->idt_vectoring_error_code =
7104 vmcs_read32(IDT_VECTORING_ERROR_CODE);
7105 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
7106 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7107
7108 /* clear vm-entry fields which are to be cleared on exit */
7109 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
7110 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
7111 }
7112
7113 /*
7114 * A part of what we need to when the nested L2 guest exits and we want to
7115 * run its L1 parent, is to reset L1's guest state to the host state specified
7116 * in vmcs12.
7117 * This function is to be called not only on normal nested exit, but also on
7118 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
7119 * Failures During or After Loading Guest State").
7120 * This function should be called when the active VMCS is L1's (vmcs01).
7121 */
7122 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
7123 {
7124 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
7125 vcpu->arch.efer = vmcs12->host_ia32_efer;
7126 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
7127 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
7128 else
7129 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
7130 vmx_set_efer(vcpu, vcpu->arch.efer);
7131
7132 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
7133 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
7134 /*
7135 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
7136 * actually changed, because it depends on the current state of
7137 * fpu_active (which may have changed).
7138 * Note that vmx_set_cr0 refers to efer set above.
7139 */
7140 kvm_set_cr0(vcpu, vmcs12->host_cr0);
7141 /*
7142 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
7143 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
7144 * but we also need to update cr0_guest_host_mask and exception_bitmap.
7145 */
7146 update_exception_bitmap(vcpu);
7147 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
7148 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
7149
7150 /*
7151 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
7152 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
7153 */
7154 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
7155 kvm_set_cr4(vcpu, vmcs12->host_cr4);
7156
7157 /* shadow page tables on either EPT or shadow page tables */
7158 kvm_set_cr3(vcpu, vmcs12->host_cr3);
7159 kvm_mmu_reset_context(vcpu);
7160
7161 if (enable_vpid) {
7162 /*
7163 * Trivially support vpid by letting L2s share their parent
7164 * L1's vpid. TODO: move to a more elaborate solution, giving
7165 * each L2 its own vpid and exposing the vpid feature to L1.
7166 */
7167 vmx_flush_tlb(vcpu);
7168 }
7169
7170
7171 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
7172 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
7173 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
7174 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
7175 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
7176 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
7177 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
7178 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
7179 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
7180 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
7181 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
7182 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
7183 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
7184 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
7185 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7186
7187 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7188 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7189 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7190 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7191 vmcs12->host_ia32_perf_global_ctrl);
7192 }
7193
7194 /*
7195 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7196 * and modify vmcs12 to make it see what it would expect to see there if
7197 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7198 */
7199 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7200 {
7201 struct vcpu_vmx *vmx = to_vmx(vcpu);
7202 int cpu;
7203 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7204
7205 leave_guest_mode(vcpu);
7206 prepare_vmcs12(vcpu, vmcs12);
7207
7208 cpu = get_cpu();
7209 vmx->loaded_vmcs = &vmx->vmcs01;
7210 vmx_vcpu_put(vcpu);
7211 vmx_vcpu_load(vcpu, cpu);
7212 vcpu->cpu = cpu;
7213 put_cpu();
7214
7215 /* if no vmcs02 cache requested, remove the one we used */
7216 if (VMCS02_POOL_SIZE == 0)
7217 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7218
7219 load_vmcs12_host_state(vcpu, vmcs12);
7220
7221 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7222 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7223
7224 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7225 vmx->host_rsp = 0;
7226
7227 /* Unpin physical memory we referred to in vmcs02 */
7228 if (vmx->nested.apic_access_page) {
7229 nested_release_page(vmx->nested.apic_access_page);
7230 vmx->nested.apic_access_page = 0;
7231 }
7232
7233 /*
7234 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7235 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7236 * success or failure flag accordingly.
7237 */
7238 if (unlikely(vmx->fail)) {
7239 vmx->fail = 0;
7240 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7241 } else
7242 nested_vmx_succeed(vcpu);
7243 }
7244
7245 /*
7246 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7247 * 23.7 "VM-entry failures during or after loading guest state" (this also
7248 * lists the acceptable exit-reason and exit-qualification parameters).
7249 * It should only be called before L2 actually succeeded to run, and when
7250 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7251 */
7252 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7253 struct vmcs12 *vmcs12,
7254 u32 reason, unsigned long qualification)
7255 {
7256 load_vmcs12_host_state(vcpu, vmcs12);
7257 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7258 vmcs12->exit_qualification = qualification;
7259 nested_vmx_succeed(vcpu);
7260 }
7261
7262 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7263 struct x86_instruction_info *info,
7264 enum x86_intercept_stage stage)
7265 {
7266 return X86EMUL_CONTINUE;
7267 }
7268
7269 static struct kvm_x86_ops vmx_x86_ops = {
7270 .cpu_has_kvm_support = cpu_has_kvm_support,
7271 .disabled_by_bios = vmx_disabled_by_bios,
7272 .hardware_setup = hardware_setup,
7273 .hardware_unsetup = hardware_unsetup,
7274 .check_processor_compatibility = vmx_check_processor_compat,
7275 .hardware_enable = hardware_enable,
7276 .hardware_disable = hardware_disable,
7277 .cpu_has_accelerated_tpr = report_flexpriority,
7278
7279 .vcpu_create = vmx_create_vcpu,
7280 .vcpu_free = vmx_free_vcpu,
7281 .vcpu_reset = vmx_vcpu_reset,
7282
7283 .prepare_guest_switch = vmx_save_host_state,
7284 .vcpu_load = vmx_vcpu_load,
7285 .vcpu_put = vmx_vcpu_put,
7286
7287 .update_db_bp_intercept = update_exception_bitmap,
7288 .get_msr = vmx_get_msr,
7289 .set_msr = vmx_set_msr,
7290 .get_segment_base = vmx_get_segment_base,
7291 .get_segment = vmx_get_segment,
7292 .set_segment = vmx_set_segment,
7293 .get_cpl = vmx_get_cpl,
7294 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7295 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7296 .decache_cr3 = vmx_decache_cr3,
7297 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7298 .set_cr0 = vmx_set_cr0,
7299 .set_cr3 = vmx_set_cr3,
7300 .set_cr4 = vmx_set_cr4,
7301 .set_efer = vmx_set_efer,
7302 .get_idt = vmx_get_idt,
7303 .set_idt = vmx_set_idt,
7304 .get_gdt = vmx_get_gdt,
7305 .set_gdt = vmx_set_gdt,
7306 .set_dr7 = vmx_set_dr7,
7307 .cache_reg = vmx_cache_reg,
7308 .get_rflags = vmx_get_rflags,
7309 .set_rflags = vmx_set_rflags,
7310 .fpu_activate = vmx_fpu_activate,
7311 .fpu_deactivate = vmx_fpu_deactivate,
7312
7313 .tlb_flush = vmx_flush_tlb,
7314
7315 .run = vmx_vcpu_run,
7316 .handle_exit = vmx_handle_exit,
7317 .skip_emulated_instruction = skip_emulated_instruction,
7318 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7319 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7320 .patch_hypercall = vmx_patch_hypercall,
7321 .set_irq = vmx_inject_irq,
7322 .set_nmi = vmx_inject_nmi,
7323 .queue_exception = vmx_queue_exception,
7324 .cancel_injection = vmx_cancel_injection,
7325 .interrupt_allowed = vmx_interrupt_allowed,
7326 .nmi_allowed = vmx_nmi_allowed,
7327 .get_nmi_mask = vmx_get_nmi_mask,
7328 .set_nmi_mask = vmx_set_nmi_mask,
7329 .enable_nmi_window = enable_nmi_window,
7330 .enable_irq_window = enable_irq_window,
7331 .update_cr8_intercept = update_cr8_intercept,
7332
7333 .set_tss_addr = vmx_set_tss_addr,
7334 .get_tdp_level = get_ept_level,
7335 .get_mt_mask = vmx_get_mt_mask,
7336
7337 .get_exit_info = vmx_get_exit_info,
7338
7339 .get_lpage_level = vmx_get_lpage_level,
7340
7341 .cpuid_update = vmx_cpuid_update,
7342
7343 .rdtscp_supported = vmx_rdtscp_supported,
7344 .invpcid_supported = vmx_invpcid_supported,
7345
7346 .set_supported_cpuid = vmx_set_supported_cpuid,
7347
7348 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7349
7350 .set_tsc_khz = vmx_set_tsc_khz,
7351 .read_tsc_offset = vmx_read_tsc_offset,
7352 .write_tsc_offset = vmx_write_tsc_offset,
7353 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7354 .compute_tsc_offset = vmx_compute_tsc_offset,
7355 .read_l1_tsc = vmx_read_l1_tsc,
7356
7357 .set_tdp_cr3 = vmx_set_cr3,
7358
7359 .check_intercept = vmx_check_intercept,
7360 };
7361
7362 static int __init vmx_init(void)
7363 {
7364 int r, i;
7365
7366 rdmsrl_safe(MSR_EFER, &host_efer);
7367
7368 for (i = 0; i < NR_VMX_MSR; ++i)
7369 kvm_define_shared_msr(i, vmx_msr_index[i]);
7370
7371 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7372 if (!vmx_io_bitmap_a)
7373 return -ENOMEM;
7374
7375 r = -ENOMEM;
7376
7377 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7378 if (!vmx_io_bitmap_b)
7379 goto out;
7380
7381 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7382 if (!vmx_msr_bitmap_legacy)
7383 goto out1;
7384
7385
7386 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7387 if (!vmx_msr_bitmap_longmode)
7388 goto out2;
7389
7390
7391 /*
7392 * Allow direct access to the PC debug port (it is often used for I/O
7393 * delays, but the vmexits simply slow things down).
7394 */
7395 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7396 clear_bit(0x80, vmx_io_bitmap_a);
7397
7398 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7399
7400 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7401 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7402
7403 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7404
7405 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7406 __alignof__(struct vcpu_vmx), THIS_MODULE);
7407 if (r)
7408 goto out3;
7409
7410 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7411 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7412 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7413 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7414 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7415 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7416
7417 if (enable_ept) {
7418 kvm_mmu_set_mask_ptes(0ull,
7419 (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
7420 (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
7421 0ull, VMX_EPT_EXECUTABLE_MASK);
7422 ept_set_mmio_spte_mask();
7423 kvm_enable_tdp();
7424 } else
7425 kvm_disable_tdp();
7426
7427 return 0;
7428
7429 out3:
7430 free_page((unsigned long)vmx_msr_bitmap_longmode);
7431 out2:
7432 free_page((unsigned long)vmx_msr_bitmap_legacy);
7433 out1:
7434 free_page((unsigned long)vmx_io_bitmap_b);
7435 out:
7436 free_page((unsigned long)vmx_io_bitmap_a);
7437 return r;
7438 }
7439
7440 static void __exit vmx_exit(void)
7441 {
7442 free_page((unsigned long)vmx_msr_bitmap_legacy);
7443 free_page((unsigned long)vmx_msr_bitmap_longmode);
7444 free_page((unsigned long)vmx_io_bitmap_b);
7445 free_page((unsigned long)vmx_io_bitmap_a);
7446
7447 kvm_exit();
7448 }
7449
7450 module_init(vmx_init)
7451 module_exit(vmx_exit)
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