2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include <linux/frame.h>
37 #include "kvm_cache_regs.h"
44 #include <asm/virtext.h>
46 #include <asm/fpu/internal.h>
47 #include <asm/perf_event.h>
48 #include <asm/debugreg.h>
49 #include <asm/kexec.h>
51 #include <asm/irq_remapping.h>
52 #include <asm/mmu_context.h>
53 #include <asm/microcode.h>
58 #define __ex(x) __kvm_handle_fault_on_reboot(x)
59 #define __ex_clear(x, reg) \
60 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
62 MODULE_AUTHOR("Qumranet");
63 MODULE_LICENSE("GPL");
65 static const struct x86_cpu_id vmx_cpu_id
[] = {
66 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
69 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
71 static bool __read_mostly enable_vpid
= 1;
72 module_param_named(vpid
, enable_vpid
, bool, 0444);
74 static bool __read_mostly flexpriority_enabled
= 1;
75 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept
= 1;
78 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
80 static bool __read_mostly enable_unrestricted_guest
= 1;
81 module_param_named(unrestricted_guest
,
82 enable_unrestricted_guest
, bool, S_IRUGO
);
84 static bool __read_mostly enable_ept_ad_bits
= 1;
85 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
87 static bool __read_mostly emulate_invalid_guest_state
= true;
88 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */
114 static int __read_mostly cpu_preemption_timer_multi
;
115 static bool __read_mostly enable_preemption_timer
= 1;
117 module_param_named(preemption_timer
, enable_preemption_timer
, bool, S_IRUGO
);
120 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
121 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
122 #define KVM_VM_CR0_ALWAYS_ON \
123 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
124 #define KVM_CR4_GUEST_OWNED_BITS \
125 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
126 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
128 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
129 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
131 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
133 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
136 * Hyper-V requires all of these, so mark them as supported even though
137 * they are just treated the same as all-context.
139 #define VMX_VPID_EXTENT_SUPPORTED_MASK \
140 (VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT | \
141 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT | \
142 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT | \
143 VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT)
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * ple_gap: upper bound on the amount of time between two successive
148 * executions of PAUSE in a loop. Also indicate if ple enabled.
149 * According to test, this time is usually smaller than 128 cycles.
150 * ple_window: upper bound on the amount of time a guest is allowed to execute
151 * in a PAUSE loop. Tests indicate that most spinlocks are held for
152 * less than 2^12 cycles
153 * Time is measured based on a counter that runs at the same rate as the TSC,
154 * refer SDM volume 3b section 21.6.13 & 22.1.3.
156 #define KVM_VMX_DEFAULT_PLE_GAP 128
157 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
158 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
159 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
160 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
161 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
163 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
164 module_param(ple_gap
, int, S_IRUGO
);
166 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
167 module_param(ple_window
, int, S_IRUGO
);
169 /* Default doubles per-vcpu window every exit. */
170 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
171 module_param(ple_window_grow
, int, S_IRUGO
);
173 /* Default resets per-vcpu window every exit to ple_window. */
174 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
175 module_param(ple_window_shrink
, int, S_IRUGO
);
177 /* Default is to compute the maximum so we can never overflow. */
178 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
179 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
180 module_param(ple_window_max
, int, S_IRUGO
);
182 extern const ulong vmx_return
;
184 #define NR_AUTOLOAD_MSRS 8
185 #define VMCS02_POOL_SIZE 1
194 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
195 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
196 * loaded on this CPU (so we can clear them if the CPU goes down).
200 struct vmcs
*shadow_vmcs
;
203 bool nmi_known_unmasked
;
204 unsigned long vmcs_host_cr3
; /* May not match real cr3 */
205 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
206 struct list_head loaded_vmcss_on_cpu_link
;
209 struct shared_msr_entry
{
216 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
217 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
218 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
219 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
220 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
221 * More than one of these structures may exist, if L1 runs multiple L2 guests.
222 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
223 * underlying hardware which will be used to run L2.
224 * This structure is packed to ensure that its layout is identical across
225 * machines (necessary for live migration).
226 * If there are changes in this struct, VMCS12_REVISION must be changed.
228 typedef u64 natural_width
;
229 struct __packed vmcs12
{
230 /* According to the Intel spec, a VMCS region must start with the
231 * following two fields. Then follow implementation-specific data.
236 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
237 u32 padding
[7]; /* room for future expansion */
242 u64 vm_exit_msr_store_addr
;
243 u64 vm_exit_msr_load_addr
;
244 u64 vm_entry_msr_load_addr
;
246 u64 virtual_apic_page_addr
;
247 u64 apic_access_addr
;
248 u64 posted_intr_desc_addr
;
250 u64 eoi_exit_bitmap0
;
251 u64 eoi_exit_bitmap1
;
252 u64 eoi_exit_bitmap2
;
253 u64 eoi_exit_bitmap3
;
255 u64 guest_physical_address
;
256 u64 vmcs_link_pointer
;
258 u64 guest_ia32_debugctl
;
261 u64 guest_ia32_perf_global_ctrl
;
269 u64 host_ia32_perf_global_ctrl
;
270 u64 padding64
[8]; /* room for future expansion */
272 * To allow migration of L1 (complete with its L2 guests) between
273 * machines of different natural widths (32 or 64 bit), we cannot have
274 * unsigned long fields with no explict size. We use u64 (aliased
275 * natural_width) instead. Luckily, x86 is little-endian.
277 natural_width cr0_guest_host_mask
;
278 natural_width cr4_guest_host_mask
;
279 natural_width cr0_read_shadow
;
280 natural_width cr4_read_shadow
;
281 natural_width cr3_target_value0
;
282 natural_width cr3_target_value1
;
283 natural_width cr3_target_value2
;
284 natural_width cr3_target_value3
;
285 natural_width exit_qualification
;
286 natural_width guest_linear_address
;
287 natural_width guest_cr0
;
288 natural_width guest_cr3
;
289 natural_width guest_cr4
;
290 natural_width guest_es_base
;
291 natural_width guest_cs_base
;
292 natural_width guest_ss_base
;
293 natural_width guest_ds_base
;
294 natural_width guest_fs_base
;
295 natural_width guest_gs_base
;
296 natural_width guest_ldtr_base
;
297 natural_width guest_tr_base
;
298 natural_width guest_gdtr_base
;
299 natural_width guest_idtr_base
;
300 natural_width guest_dr7
;
301 natural_width guest_rsp
;
302 natural_width guest_rip
;
303 natural_width guest_rflags
;
304 natural_width guest_pending_dbg_exceptions
;
305 natural_width guest_sysenter_esp
;
306 natural_width guest_sysenter_eip
;
307 natural_width host_cr0
;
308 natural_width host_cr3
;
309 natural_width host_cr4
;
310 natural_width host_fs_base
;
311 natural_width host_gs_base
;
312 natural_width host_tr_base
;
313 natural_width host_gdtr_base
;
314 natural_width host_idtr_base
;
315 natural_width host_ia32_sysenter_esp
;
316 natural_width host_ia32_sysenter_eip
;
317 natural_width host_rsp
;
318 natural_width host_rip
;
319 natural_width paddingl
[8]; /* room for future expansion */
320 u32 pin_based_vm_exec_control
;
321 u32 cpu_based_vm_exec_control
;
322 u32 exception_bitmap
;
323 u32 page_fault_error_code_mask
;
324 u32 page_fault_error_code_match
;
325 u32 cr3_target_count
;
326 u32 vm_exit_controls
;
327 u32 vm_exit_msr_store_count
;
328 u32 vm_exit_msr_load_count
;
329 u32 vm_entry_controls
;
330 u32 vm_entry_msr_load_count
;
331 u32 vm_entry_intr_info_field
;
332 u32 vm_entry_exception_error_code
;
333 u32 vm_entry_instruction_len
;
335 u32 secondary_vm_exec_control
;
336 u32 vm_instruction_error
;
338 u32 vm_exit_intr_info
;
339 u32 vm_exit_intr_error_code
;
340 u32 idt_vectoring_info_field
;
341 u32 idt_vectoring_error_code
;
342 u32 vm_exit_instruction_len
;
343 u32 vmx_instruction_info
;
350 u32 guest_ldtr_limit
;
352 u32 guest_gdtr_limit
;
353 u32 guest_idtr_limit
;
354 u32 guest_es_ar_bytes
;
355 u32 guest_cs_ar_bytes
;
356 u32 guest_ss_ar_bytes
;
357 u32 guest_ds_ar_bytes
;
358 u32 guest_fs_ar_bytes
;
359 u32 guest_gs_ar_bytes
;
360 u32 guest_ldtr_ar_bytes
;
361 u32 guest_tr_ar_bytes
;
362 u32 guest_interruptibility_info
;
363 u32 guest_activity_state
;
364 u32 guest_sysenter_cs
;
365 u32 host_ia32_sysenter_cs
;
366 u32 vmx_preemption_timer_value
;
367 u32 padding32
[7]; /* room for future expansion */
368 u16 virtual_processor_id
;
370 u16 guest_es_selector
;
371 u16 guest_cs_selector
;
372 u16 guest_ss_selector
;
373 u16 guest_ds_selector
;
374 u16 guest_fs_selector
;
375 u16 guest_gs_selector
;
376 u16 guest_ldtr_selector
;
377 u16 guest_tr_selector
;
378 u16 guest_intr_status
;
380 u16 host_es_selector
;
381 u16 host_cs_selector
;
382 u16 host_ss_selector
;
383 u16 host_ds_selector
;
384 u16 host_fs_selector
;
385 u16 host_gs_selector
;
386 u16 host_tr_selector
;
390 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
391 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
392 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
394 #define VMCS12_REVISION 0x11e57ed0
397 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
398 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
399 * current implementation, 4K are reserved to avoid future complications.
401 #define VMCS12_SIZE 0x1000
403 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
405 struct list_head list
;
407 struct loaded_vmcs vmcs02
;
411 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
412 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
415 /* Has the level1 guest done vmxon? */
420 /* The guest-physical address of the current VMCS L1 keeps for L2 */
423 * Cache of the guest's VMCS, existing outside of guest memory.
424 * Loaded from guest memory during VMPTRLD. Flushed to guest
425 * memory during VMCLEAR and VMPTRLD.
427 struct vmcs12
*cached_vmcs12
;
429 * Indicates if the shadow vmcs must be updated with the
430 * data hold by vmcs12
432 bool sync_shadow_vmcs
;
434 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
435 struct list_head vmcs02_pool
;
437 bool change_vmcs01_virtual_x2apic_mode
;
438 /* L2 must run next, and mustn't decide to exit to L1. */
439 bool nested_run_pending
;
441 * Guest pages referred to in vmcs02 with host-physical pointers, so
442 * we must keep them pinned while L2 runs.
444 struct page
*apic_access_page
;
445 struct page
*virtual_apic_page
;
446 struct page
*pi_desc_page
;
447 struct pi_desc
*pi_desc
;
451 unsigned long *msr_bitmap
;
453 struct hrtimer preemption_timer
;
454 bool preemption_timer_expired
;
456 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
463 * We only store the "true" versions of the VMX capability MSRs. We
464 * generate the "non-true" versions by setting the must-be-1 bits
465 * according to the SDM.
467 u32 nested_vmx_procbased_ctls_low
;
468 u32 nested_vmx_procbased_ctls_high
;
469 u32 nested_vmx_secondary_ctls_low
;
470 u32 nested_vmx_secondary_ctls_high
;
471 u32 nested_vmx_pinbased_ctls_low
;
472 u32 nested_vmx_pinbased_ctls_high
;
473 u32 nested_vmx_exit_ctls_low
;
474 u32 nested_vmx_exit_ctls_high
;
475 u32 nested_vmx_entry_ctls_low
;
476 u32 nested_vmx_entry_ctls_high
;
477 u32 nested_vmx_misc_low
;
478 u32 nested_vmx_misc_high
;
479 u32 nested_vmx_ept_caps
;
480 u32 nested_vmx_vpid_caps
;
481 u64 nested_vmx_basic
;
482 u64 nested_vmx_cr0_fixed0
;
483 u64 nested_vmx_cr0_fixed1
;
484 u64 nested_vmx_cr4_fixed0
;
485 u64 nested_vmx_cr4_fixed1
;
486 u64 nested_vmx_vmcs_enum
;
489 #define POSTED_INTR_ON 0
490 #define POSTED_INTR_SN 1
492 /* Posted-Interrupt Descriptor */
494 u32 pir
[8]; /* Posted interrupt requested */
497 /* bit 256 - Outstanding Notification */
499 /* bit 257 - Suppress Notification */
501 /* bit 271:258 - Reserved */
503 /* bit 279:272 - Notification Vector */
505 /* bit 287:280 - Reserved */
507 /* bit 319:288 - Notification Destination */
515 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
517 return test_and_set_bit(POSTED_INTR_ON
,
518 (unsigned long *)&pi_desc
->control
);
521 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
523 return test_and_clear_bit(POSTED_INTR_ON
,
524 (unsigned long *)&pi_desc
->control
);
527 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
529 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
532 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
534 return clear_bit(POSTED_INTR_SN
,
535 (unsigned long *)&pi_desc
->control
);
538 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
540 return set_bit(POSTED_INTR_SN
,
541 (unsigned long *)&pi_desc
->control
);
544 static inline void pi_clear_on(struct pi_desc
*pi_desc
)
546 clear_bit(POSTED_INTR_ON
,
547 (unsigned long *)&pi_desc
->control
);
550 static inline int pi_test_on(struct pi_desc
*pi_desc
)
552 return test_bit(POSTED_INTR_ON
,
553 (unsigned long *)&pi_desc
->control
);
556 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
558 return test_bit(POSTED_INTR_SN
,
559 (unsigned long *)&pi_desc
->control
);
563 struct kvm_vcpu vcpu
;
564 unsigned long host_rsp
;
567 u32 idt_vectoring_info
;
569 struct shared_msr_entry
*guest_msrs
;
572 unsigned long host_idt_base
;
574 u64 msr_host_kernel_gs_base
;
575 u64 msr_guest_kernel_gs_base
;
577 u32 vm_entry_controls_shadow
;
578 u32 vm_exit_controls_shadow
;
580 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
581 * non-nested (L1) guest, it always points to vmcs01. For a nested
582 * guest (L2), it points to a different VMCS.
584 struct loaded_vmcs vmcs01
;
585 struct loaded_vmcs
*loaded_vmcs
;
586 bool __launched
; /* temporary, used in vmx_vcpu_run */
587 struct msr_autoload
{
589 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
590 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
594 u16 fs_sel
, gs_sel
, ldt_sel
;
598 int gs_ldt_reload_needed
;
599 int fs_reload_needed
;
600 u64 msr_host_bndcfgs
;
605 struct kvm_segment segs
[8];
608 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
609 struct kvm_save_segment
{
617 bool emulation_required
;
621 /* Posted interrupt descriptor */
622 struct pi_desc pi_desc
;
624 /* Support for a guest hypervisor (nested VMX) */
625 struct nested_vmx nested
;
627 /* Dynamic PLE window. */
629 bool ple_window_dirty
;
631 /* Support for PML */
632 #define PML_ENTITY_NUM 512
635 /* apic deadline value in host tsc */
638 u64 current_tsc_ratio
;
643 * Only bits masked by msr_ia32_feature_control_valid_bits can be set in
644 * msr_ia32_feature_control. FEATURE_CONTROL_LOCKED is always included
645 * in msr_ia32_feature_control_valid_bits.
647 u64 msr_ia32_feature_control
;
648 u64 msr_ia32_feature_control_valid_bits
;
651 enum segment_cache_field
{
660 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
662 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
665 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
667 return &(to_vmx(vcpu
)->pi_desc
);
670 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
671 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
672 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
673 [number##_HIGH] = VMCS12_OFFSET(name)+4
676 static unsigned long shadow_read_only_fields
[] = {
678 * We do NOT shadow fields that are modified when L0
679 * traps and emulates any vmx instruction (e.g. VMPTRLD,
680 * VMXON...) executed by L1.
681 * For example, VM_INSTRUCTION_ERROR is read
682 * by L1 if a vmx instruction fails (part of the error path).
683 * Note the code assumes this logic. If for some reason
684 * we start shadowing these fields then we need to
685 * force a shadow sync when L0 emulates vmx instructions
686 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
687 * by nested_vmx_failValid)
691 VM_EXIT_INSTRUCTION_LEN
,
692 IDT_VECTORING_INFO_FIELD
,
693 IDT_VECTORING_ERROR_CODE
,
694 VM_EXIT_INTR_ERROR_CODE
,
696 GUEST_LINEAR_ADDRESS
,
697 GUEST_PHYSICAL_ADDRESS
699 static int max_shadow_read_only_fields
=
700 ARRAY_SIZE(shadow_read_only_fields
);
702 static unsigned long shadow_read_write_fields
[] = {
709 GUEST_INTERRUPTIBILITY_INFO
,
722 CPU_BASED_VM_EXEC_CONTROL
,
723 VM_ENTRY_EXCEPTION_ERROR_CODE
,
724 VM_ENTRY_INTR_INFO_FIELD
,
725 VM_ENTRY_INSTRUCTION_LEN
,
726 VM_ENTRY_EXCEPTION_ERROR_CODE
,
732 static int max_shadow_read_write_fields
=
733 ARRAY_SIZE(shadow_read_write_fields
);
735 static const unsigned short vmcs_field_to_offset_table
[] = {
736 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
737 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
738 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
739 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
740 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
741 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
742 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
743 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
744 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
745 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
746 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
747 FIELD(GUEST_PML_INDEX
, guest_pml_index
),
748 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
749 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
750 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
751 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
752 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
753 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
754 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
755 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
756 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
757 FIELD64(MSR_BITMAP
, msr_bitmap
),
758 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
759 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
760 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
761 FIELD64(TSC_OFFSET
, tsc_offset
),
762 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
763 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
764 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
765 FIELD64(EPT_POINTER
, ept_pointer
),
766 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
767 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
768 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
769 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
770 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
771 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
772 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
773 FIELD64(PML_ADDRESS
, pml_address
),
774 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
775 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
776 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
777 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
778 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
779 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
780 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
781 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
782 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
783 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
784 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
785 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
786 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
787 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
788 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
789 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
790 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
791 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
792 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
793 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
794 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
795 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
796 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
797 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
798 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
799 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
800 FIELD(TPR_THRESHOLD
, tpr_threshold
),
801 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
802 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
803 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
804 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
805 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
806 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
807 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
808 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
809 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
810 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
811 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
812 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
813 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
814 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
815 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
816 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
817 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
818 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
819 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
820 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
821 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
822 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
823 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
824 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
825 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
826 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
827 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
828 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
829 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
830 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
831 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
832 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
833 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
834 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
835 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
836 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
837 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
838 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
839 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
840 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
841 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
842 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
843 FIELD(GUEST_CR0
, guest_cr0
),
844 FIELD(GUEST_CR3
, guest_cr3
),
845 FIELD(GUEST_CR4
, guest_cr4
),
846 FIELD(GUEST_ES_BASE
, guest_es_base
),
847 FIELD(GUEST_CS_BASE
, guest_cs_base
),
848 FIELD(GUEST_SS_BASE
, guest_ss_base
),
849 FIELD(GUEST_DS_BASE
, guest_ds_base
),
850 FIELD(GUEST_FS_BASE
, guest_fs_base
),
851 FIELD(GUEST_GS_BASE
, guest_gs_base
),
852 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
853 FIELD(GUEST_TR_BASE
, guest_tr_base
),
854 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
855 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
856 FIELD(GUEST_DR7
, guest_dr7
),
857 FIELD(GUEST_RSP
, guest_rsp
),
858 FIELD(GUEST_RIP
, guest_rip
),
859 FIELD(GUEST_RFLAGS
, guest_rflags
),
860 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
861 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
862 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
863 FIELD(HOST_CR0
, host_cr0
),
864 FIELD(HOST_CR3
, host_cr3
),
865 FIELD(HOST_CR4
, host_cr4
),
866 FIELD(HOST_FS_BASE
, host_fs_base
),
867 FIELD(HOST_GS_BASE
, host_gs_base
),
868 FIELD(HOST_TR_BASE
, host_tr_base
),
869 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
870 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
871 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
872 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
873 FIELD(HOST_RSP
, host_rsp
),
874 FIELD(HOST_RIP
, host_rip
),
877 static inline short vmcs_field_to_offset(unsigned long field
)
879 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
881 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
882 vmcs_field_to_offset_table
[field
] == 0)
885 return vmcs_field_to_offset_table
[field
];
888 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
890 return to_vmx(vcpu
)->nested
.cached_vmcs12
;
893 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
895 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
896 if (is_error_page(page
))
902 static void nested_release_page(struct page
*page
)
904 kvm_release_page_dirty(page
);
907 static void nested_release_page_clean(struct page
*page
)
909 kvm_release_page_clean(page
);
912 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
);
913 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
914 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
);
915 static bool vmx_xsaves_supported(void);
916 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
917 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
918 struct kvm_segment
*var
, int seg
);
919 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
920 struct kvm_segment
*var
, int seg
);
921 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
922 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
923 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
924 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
925 static int alloc_identity_pagetable(struct kvm
*kvm
);
926 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
);
927 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
);
928 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
931 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
932 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
934 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
935 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
937 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
940 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
941 * can find which vCPU should be waken up.
943 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
944 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
949 VMX_MSR_BITMAP_LEGACY
,
950 VMX_MSR_BITMAP_LONGMODE
,
951 VMX_MSR_BITMAP_LEGACY_X2APIC_APICV
,
952 VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV
,
953 VMX_MSR_BITMAP_LEGACY_X2APIC
,
954 VMX_MSR_BITMAP_LONGMODE_X2APIC
,
960 static unsigned long *vmx_bitmap
[VMX_BITMAP_NR
];
962 #define vmx_io_bitmap_a (vmx_bitmap[VMX_IO_BITMAP_A])
963 #define vmx_io_bitmap_b (vmx_bitmap[VMX_IO_BITMAP_B])
964 #define vmx_msr_bitmap_legacy (vmx_bitmap[VMX_MSR_BITMAP_LEGACY])
965 #define vmx_msr_bitmap_longmode (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE])
966 #define vmx_msr_bitmap_legacy_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC_APICV])
967 #define vmx_msr_bitmap_longmode_x2apic_apicv (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC_APICV])
968 #define vmx_msr_bitmap_legacy_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LEGACY_X2APIC])
969 #define vmx_msr_bitmap_longmode_x2apic (vmx_bitmap[VMX_MSR_BITMAP_LONGMODE_X2APIC])
970 #define vmx_vmread_bitmap (vmx_bitmap[VMX_VMREAD_BITMAP])
971 #define vmx_vmwrite_bitmap (vmx_bitmap[VMX_VMWRITE_BITMAP])
973 static bool cpu_has_load_ia32_efer
;
974 static bool cpu_has_load_perf_global_ctrl
;
976 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
977 static DEFINE_SPINLOCK(vmx_vpid_lock
);
979 static struct vmcs_config
{
984 u32 pin_based_exec_ctrl
;
985 u32 cpu_based_exec_ctrl
;
986 u32 cpu_based_2nd_exec_ctrl
;
991 static struct vmx_capability
{
996 #define VMX_SEGMENT_FIELD(seg) \
997 [VCPU_SREG_##seg] = { \
998 .selector = GUEST_##seg##_SELECTOR, \
999 .base = GUEST_##seg##_BASE, \
1000 .limit = GUEST_##seg##_LIMIT, \
1001 .ar_bytes = GUEST_##seg##_AR_BYTES, \
1004 static const struct kvm_vmx_segment_field
{
1009 } kvm_vmx_segment_fields
[] = {
1010 VMX_SEGMENT_FIELD(CS
),
1011 VMX_SEGMENT_FIELD(DS
),
1012 VMX_SEGMENT_FIELD(ES
),
1013 VMX_SEGMENT_FIELD(FS
),
1014 VMX_SEGMENT_FIELD(GS
),
1015 VMX_SEGMENT_FIELD(SS
),
1016 VMX_SEGMENT_FIELD(TR
),
1017 VMX_SEGMENT_FIELD(LDTR
),
1020 static u64 host_efer
;
1022 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
1025 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
1026 * away by decrementing the array size.
1028 static const u32 vmx_msr_index
[] = {
1029 #ifdef CONFIG_X86_64
1030 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
1032 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
1035 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
1037 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1038 INTR_INFO_VALID_MASK
)) ==
1039 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
1042 static inline bool is_debug(u32 intr_info
)
1044 return is_exception_n(intr_info
, DB_VECTOR
);
1047 static inline bool is_breakpoint(u32 intr_info
)
1049 return is_exception_n(intr_info
, BP_VECTOR
);
1052 static inline bool is_page_fault(u32 intr_info
)
1054 return is_exception_n(intr_info
, PF_VECTOR
);
1057 static inline bool is_no_device(u32 intr_info
)
1059 return is_exception_n(intr_info
, NM_VECTOR
);
1062 static inline bool is_invalid_opcode(u32 intr_info
)
1064 return is_exception_n(intr_info
, UD_VECTOR
);
1067 static inline bool is_external_interrupt(u32 intr_info
)
1069 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1070 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1073 static inline bool is_machine_check(u32 intr_info
)
1075 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1076 INTR_INFO_VALID_MASK
)) ==
1077 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1080 static inline bool cpu_has_vmx_msr_bitmap(void)
1082 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1085 static inline bool cpu_has_vmx_tpr_shadow(void)
1087 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1090 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1092 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1095 static inline bool cpu_has_secondary_exec_ctrls(void)
1097 return vmcs_config
.cpu_based_exec_ctrl
&
1098 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1101 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1103 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1104 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1107 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1109 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1110 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1113 static inline bool cpu_has_vmx_apic_register_virt(void)
1115 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1116 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1119 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1121 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1122 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1126 * Comment's format: document - errata name - stepping - processor name.
1128 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
1130 static u32 vmx_preemption_cpu_tfms
[] = {
1131 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
1133 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */
1134 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
1135 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
1137 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
1139 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
1140 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
1142 * 320767.pdf - AAP86 - B1 -
1143 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
1146 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */
1148 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */
1150 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
1152 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
1153 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
1154 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
1158 static inline bool cpu_has_broken_vmx_preemption_timer(void)
1160 u32 eax
= cpuid_eax(0x00000001), i
;
1162 /* Clear the reserved bits */
1163 eax
&= ~(0x3U
<< 14 | 0xfU
<< 28);
1164 for (i
= 0; i
< ARRAY_SIZE(vmx_preemption_cpu_tfms
); i
++)
1165 if (eax
== vmx_preemption_cpu_tfms
[i
])
1171 static inline bool cpu_has_vmx_preemption_timer(void)
1173 return vmcs_config
.pin_based_exec_ctrl
&
1174 PIN_BASED_VMX_PREEMPTION_TIMER
;
1177 static inline bool cpu_has_vmx_posted_intr(void)
1179 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1180 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1183 static inline bool cpu_has_vmx_apicv(void)
1185 return cpu_has_vmx_apic_register_virt() &&
1186 cpu_has_vmx_virtual_intr_delivery() &&
1187 cpu_has_vmx_posted_intr();
1190 static inline bool cpu_has_vmx_flexpriority(void)
1192 return cpu_has_vmx_tpr_shadow() &&
1193 cpu_has_vmx_virtualize_apic_accesses();
1196 static inline bool cpu_has_vmx_ept_execute_only(void)
1198 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1201 static inline bool cpu_has_vmx_ept_2m_page(void)
1203 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1206 static inline bool cpu_has_vmx_ept_1g_page(void)
1208 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1211 static inline bool cpu_has_vmx_ept_4levels(void)
1213 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1216 static inline bool cpu_has_vmx_ept_ad_bits(void)
1218 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1221 static inline bool cpu_has_vmx_invept_context(void)
1223 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1226 static inline bool cpu_has_vmx_invept_global(void)
1228 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1231 static inline bool cpu_has_vmx_invvpid_single(void)
1233 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1236 static inline bool cpu_has_vmx_invvpid_global(void)
1238 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1241 static inline bool cpu_has_vmx_invvpid(void)
1243 return vmx_capability
.vpid
& VMX_VPID_INVVPID_BIT
;
1246 static inline bool cpu_has_vmx_ept(void)
1248 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1249 SECONDARY_EXEC_ENABLE_EPT
;
1252 static inline bool cpu_has_vmx_unrestricted_guest(void)
1254 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1255 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1258 static inline bool cpu_has_vmx_ple(void)
1260 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1261 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1264 static inline bool cpu_has_vmx_basic_inout(void)
1266 return (((u64
)vmcs_config
.basic_cap
<< 32) & VMX_BASIC_INOUT
);
1269 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1271 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1274 static inline bool cpu_has_vmx_vpid(void)
1276 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1277 SECONDARY_EXEC_ENABLE_VPID
;
1280 static inline bool cpu_has_vmx_rdtscp(void)
1282 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1283 SECONDARY_EXEC_RDTSCP
;
1286 static inline bool cpu_has_vmx_invpcid(void)
1288 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1289 SECONDARY_EXEC_ENABLE_INVPCID
;
1292 static inline bool cpu_has_vmx_wbinvd_exit(void)
1294 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1295 SECONDARY_EXEC_WBINVD_EXITING
;
1298 static inline bool cpu_has_vmx_shadow_vmcs(void)
1301 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1302 /* check if the cpu supports writing r/o exit information fields */
1303 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1306 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1307 SECONDARY_EXEC_SHADOW_VMCS
;
1310 static inline bool cpu_has_vmx_pml(void)
1312 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1315 static inline bool cpu_has_vmx_tsc_scaling(void)
1317 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1318 SECONDARY_EXEC_TSC_SCALING
;
1321 static inline bool report_flexpriority(void)
1323 return flexpriority_enabled
;
1326 static inline unsigned nested_cpu_vmx_misc_cr3_count(struct kvm_vcpu
*vcpu
)
1328 return vmx_misc_cr3_count(to_vmx(vcpu
)->nested
.nested_vmx_misc_low
);
1331 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1333 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1336 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1338 return (vmcs12
->cpu_based_vm_exec_control
&
1339 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1340 (vmcs12
->secondary_vm_exec_control
& bit
);
1343 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1345 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1348 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1350 return vmcs12
->pin_based_vm_exec_control
&
1351 PIN_BASED_VMX_PREEMPTION_TIMER
;
1354 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1356 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1359 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1361 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1362 vmx_xsaves_supported();
1365 static inline bool nested_cpu_has_pml(struct vmcs12
*vmcs12
)
1367 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
);
1370 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1372 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1375 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1377 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1380 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1382 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1385 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1387 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1390 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1392 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1395 static inline bool is_nmi(u32 intr_info
)
1397 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1398 == (INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
);
1401 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1403 unsigned long exit_qualification
);
1404 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1405 struct vmcs12
*vmcs12
,
1406 u32 reason
, unsigned long qualification
);
1408 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1412 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1413 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1418 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1424 } operand
= { vpid
, 0, gva
};
1426 asm volatile (__ex(ASM_VMX_INVVPID
)
1427 /* CF==1 or ZF==1 --> rc = -1 */
1428 "; ja 1f ; ud2 ; 1:"
1429 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1432 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1436 } operand
= {eptp
, gpa
};
1438 asm volatile (__ex(ASM_VMX_INVEPT
)
1439 /* CF==1 or ZF==1 --> rc = -1 */
1440 "; ja 1f ; ud2 ; 1:\n"
1441 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1444 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1448 i
= __find_msr_index(vmx
, msr
);
1450 return &vmx
->guest_msrs
[i
];
1454 static void vmcs_clear(struct vmcs
*vmcs
)
1456 u64 phys_addr
= __pa(vmcs
);
1459 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1460 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1463 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1467 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1469 vmcs_clear(loaded_vmcs
->vmcs
);
1470 if (loaded_vmcs
->shadow_vmcs
&& loaded_vmcs
->launched
)
1471 vmcs_clear(loaded_vmcs
->shadow_vmcs
);
1472 loaded_vmcs
->cpu
= -1;
1473 loaded_vmcs
->launched
= 0;
1476 static void vmcs_load(struct vmcs
*vmcs
)
1478 u64 phys_addr
= __pa(vmcs
);
1481 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1482 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1485 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1490 #ifdef CONFIG_KEXEC_CORE
1492 * This bitmap is used to indicate whether the vmclear
1493 * operation is enabled on all cpus. All disabled by
1496 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1498 static inline void crash_enable_local_vmclear(int cpu
)
1500 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1503 static inline void crash_disable_local_vmclear(int cpu
)
1505 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1508 static inline int crash_local_vmclear_enabled(int cpu
)
1510 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1513 static void crash_vmclear_local_loaded_vmcss(void)
1515 int cpu
= raw_smp_processor_id();
1516 struct loaded_vmcs
*v
;
1518 if (!crash_local_vmclear_enabled(cpu
))
1521 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1522 loaded_vmcss_on_cpu_link
)
1523 vmcs_clear(v
->vmcs
);
1526 static inline void crash_enable_local_vmclear(int cpu
) { }
1527 static inline void crash_disable_local_vmclear(int cpu
) { }
1528 #endif /* CONFIG_KEXEC_CORE */
1530 static void __loaded_vmcs_clear(void *arg
)
1532 struct loaded_vmcs
*loaded_vmcs
= arg
;
1533 int cpu
= raw_smp_processor_id();
1535 if (loaded_vmcs
->cpu
!= cpu
)
1536 return; /* vcpu migration can race with cpu offline */
1537 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1538 per_cpu(current_vmcs
, cpu
) = NULL
;
1539 crash_disable_local_vmclear(cpu
);
1540 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1543 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1544 * is before setting loaded_vmcs->vcpu to -1 which is done in
1545 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1546 * then adds the vmcs into percpu list before it is deleted.
1550 loaded_vmcs_init(loaded_vmcs
);
1551 crash_enable_local_vmclear(cpu
);
1554 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1556 int cpu
= loaded_vmcs
->cpu
;
1559 smp_call_function_single(cpu
,
1560 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1563 static inline void vpid_sync_vcpu_single(int vpid
)
1568 if (cpu_has_vmx_invvpid_single())
1569 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1572 static inline void vpid_sync_vcpu_global(void)
1574 if (cpu_has_vmx_invvpid_global())
1575 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1578 static inline void vpid_sync_context(int vpid
)
1580 if (cpu_has_vmx_invvpid_single())
1581 vpid_sync_vcpu_single(vpid
);
1583 vpid_sync_vcpu_global();
1586 static inline void ept_sync_global(void)
1588 if (cpu_has_vmx_invept_global())
1589 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1592 static inline void ept_sync_context(u64 eptp
)
1595 if (cpu_has_vmx_invept_context())
1596 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1602 static __always_inline
void vmcs_check16(unsigned long field
)
1604 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1605 "16-bit accessor invalid for 64-bit field");
1606 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1607 "16-bit accessor invalid for 64-bit high field");
1608 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1609 "16-bit accessor invalid for 32-bit high field");
1610 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1611 "16-bit accessor invalid for natural width field");
1614 static __always_inline
void vmcs_check32(unsigned long field
)
1616 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1617 "32-bit accessor invalid for 16-bit field");
1618 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1619 "32-bit accessor invalid for natural width field");
1622 static __always_inline
void vmcs_check64(unsigned long field
)
1624 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1625 "64-bit accessor invalid for 16-bit field");
1626 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1627 "64-bit accessor invalid for 64-bit high field");
1628 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1629 "64-bit accessor invalid for 32-bit field");
1630 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1631 "64-bit accessor invalid for natural width field");
1634 static __always_inline
void vmcs_checkl(unsigned long field
)
1636 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1637 "Natural width accessor invalid for 16-bit field");
1638 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1639 "Natural width accessor invalid for 64-bit field");
1640 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1641 "Natural width accessor invalid for 64-bit high field");
1642 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1643 "Natural width accessor invalid for 32-bit field");
1646 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1648 unsigned long value
;
1650 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1651 : "=a"(value
) : "d"(field
) : "cc");
1655 static __always_inline u16
vmcs_read16(unsigned long field
)
1657 vmcs_check16(field
);
1658 return __vmcs_readl(field
);
1661 static __always_inline u32
vmcs_read32(unsigned long field
)
1663 vmcs_check32(field
);
1664 return __vmcs_readl(field
);
1667 static __always_inline u64
vmcs_read64(unsigned long field
)
1669 vmcs_check64(field
);
1670 #ifdef CONFIG_X86_64
1671 return __vmcs_readl(field
);
1673 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1677 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1680 return __vmcs_readl(field
);
1683 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1685 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1686 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1690 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1694 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1695 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1696 if (unlikely(error
))
1697 vmwrite_error(field
, value
);
1700 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1702 vmcs_check16(field
);
1703 __vmcs_writel(field
, value
);
1706 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1708 vmcs_check32(field
);
1709 __vmcs_writel(field
, value
);
1712 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1714 vmcs_check64(field
);
1715 __vmcs_writel(field
, value
);
1716 #ifndef CONFIG_X86_64
1718 __vmcs_writel(field
+1, value
>> 32);
1722 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1725 __vmcs_writel(field
, value
);
1728 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1730 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1731 "vmcs_clear_bits does not support 64-bit fields");
1732 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1735 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1737 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1738 "vmcs_set_bits does not support 64-bit fields");
1739 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1742 static inline void vm_entry_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1744 vmx
->vm_entry_controls_shadow
= vmcs_read32(VM_ENTRY_CONTROLS
);
1747 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1749 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1750 vmx
->vm_entry_controls_shadow
= val
;
1753 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1755 if (vmx
->vm_entry_controls_shadow
!= val
)
1756 vm_entry_controls_init(vmx
, val
);
1759 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1761 return vmx
->vm_entry_controls_shadow
;
1765 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1767 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1770 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1772 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1775 static inline void vm_exit_controls_reset_shadow(struct vcpu_vmx
*vmx
)
1777 vmx
->vm_exit_controls_shadow
= vmcs_read32(VM_EXIT_CONTROLS
);
1780 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1782 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1783 vmx
->vm_exit_controls_shadow
= val
;
1786 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1788 if (vmx
->vm_exit_controls_shadow
!= val
)
1789 vm_exit_controls_init(vmx
, val
);
1792 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1794 return vmx
->vm_exit_controls_shadow
;
1798 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1800 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1803 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1805 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1808 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1810 vmx
->segment_cache
.bitmask
= 0;
1813 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1817 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1819 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1820 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1821 vmx
->segment_cache
.bitmask
= 0;
1823 ret
= vmx
->segment_cache
.bitmask
& mask
;
1824 vmx
->segment_cache
.bitmask
|= mask
;
1828 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1830 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1832 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1833 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1837 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1839 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1841 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1842 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1846 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1848 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1850 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1851 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1855 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1857 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1859 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1860 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1864 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1868 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1869 (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1870 if ((vcpu
->guest_debug
&
1871 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1872 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1873 eb
|= 1u << BP_VECTOR
;
1874 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1877 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1879 /* When we are running a nested L2 guest and L1 specified for it a
1880 * certain exception bitmap, we must trap the same exceptions and pass
1881 * them to L1. When running L2, we will only handle the exceptions
1882 * specified above if L1 did not want them.
1884 if (is_guest_mode(vcpu
))
1885 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1887 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1890 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1891 unsigned long entry
, unsigned long exit
)
1893 vm_entry_controls_clearbit(vmx
, entry
);
1894 vm_exit_controls_clearbit(vmx
, exit
);
1897 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1900 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1904 if (cpu_has_load_ia32_efer
) {
1905 clear_atomic_switch_msr_special(vmx
,
1906 VM_ENTRY_LOAD_IA32_EFER
,
1907 VM_EXIT_LOAD_IA32_EFER
);
1911 case MSR_CORE_PERF_GLOBAL_CTRL
:
1912 if (cpu_has_load_perf_global_ctrl
) {
1913 clear_atomic_switch_msr_special(vmx
,
1914 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1915 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1921 for (i
= 0; i
< m
->nr
; ++i
)
1922 if (m
->guest
[i
].index
== msr
)
1928 m
->guest
[i
] = m
->guest
[m
->nr
];
1929 m
->host
[i
] = m
->host
[m
->nr
];
1930 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1931 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1934 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1935 unsigned long entry
, unsigned long exit
,
1936 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1937 u64 guest_val
, u64 host_val
)
1939 vmcs_write64(guest_val_vmcs
, guest_val
);
1940 vmcs_write64(host_val_vmcs
, host_val
);
1941 vm_entry_controls_setbit(vmx
, entry
);
1942 vm_exit_controls_setbit(vmx
, exit
);
1945 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1946 u64 guest_val
, u64 host_val
)
1949 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1953 if (cpu_has_load_ia32_efer
) {
1954 add_atomic_switch_msr_special(vmx
,
1955 VM_ENTRY_LOAD_IA32_EFER
,
1956 VM_EXIT_LOAD_IA32_EFER
,
1959 guest_val
, host_val
);
1963 case MSR_CORE_PERF_GLOBAL_CTRL
:
1964 if (cpu_has_load_perf_global_ctrl
) {
1965 add_atomic_switch_msr_special(vmx
,
1966 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1967 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1968 GUEST_IA32_PERF_GLOBAL_CTRL
,
1969 HOST_IA32_PERF_GLOBAL_CTRL
,
1970 guest_val
, host_val
);
1974 case MSR_IA32_PEBS_ENABLE
:
1975 /* PEBS needs a quiescent period after being disabled (to write
1976 * a record). Disabling PEBS through VMX MSR swapping doesn't
1977 * provide that period, so a CPU could write host's record into
1980 wrmsrl(MSR_IA32_PEBS_ENABLE
, 0);
1983 for (i
= 0; i
< m
->nr
; ++i
)
1984 if (m
->guest
[i
].index
== msr
)
1987 if (i
== NR_AUTOLOAD_MSRS
) {
1988 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1989 "Can't add msr %x\n", msr
);
1991 } else if (i
== m
->nr
) {
1993 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1994 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1997 m
->guest
[i
].index
= msr
;
1998 m
->guest
[i
].value
= guest_val
;
1999 m
->host
[i
].index
= msr
;
2000 m
->host
[i
].value
= host_val
;
2003 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
2005 u64 guest_efer
= vmx
->vcpu
.arch
.efer
;
2006 u64 ignore_bits
= 0;
2010 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
2011 * host CPUID is more efficient than testing guest CPUID
2012 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
2014 if (boot_cpu_has(X86_FEATURE_SMEP
))
2015 guest_efer
|= EFER_NX
;
2016 else if (!(guest_efer
& EFER_NX
))
2017 ignore_bits
|= EFER_NX
;
2021 * LMA and LME handled by hardware; SCE meaningless outside long mode.
2023 ignore_bits
|= EFER_SCE
;
2024 #ifdef CONFIG_X86_64
2025 ignore_bits
|= EFER_LMA
| EFER_LME
;
2026 /* SCE is meaningful only in long mode on Intel */
2027 if (guest_efer
& EFER_LMA
)
2028 ignore_bits
&= ~(u64
)EFER_SCE
;
2031 clear_atomic_switch_msr(vmx
, MSR_EFER
);
2034 * On EPT, we can't emulate NX, so we must switch EFER atomically.
2035 * On CPUs that support "load IA32_EFER", always switch EFER
2036 * atomically, since it's faster than switching it manually.
2038 if (cpu_has_load_ia32_efer
||
2039 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
2040 if (!(guest_efer
& EFER_LMA
))
2041 guest_efer
&= ~EFER_LME
;
2042 if (guest_efer
!= host_efer
)
2043 add_atomic_switch_msr(vmx
, MSR_EFER
,
2044 guest_efer
, host_efer
);
2047 guest_efer
&= ~ignore_bits
;
2048 guest_efer
|= host_efer
& ignore_bits
;
2050 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
2051 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
2057 #ifdef CONFIG_X86_32
2059 * On 32-bit kernels, VM exits still load the FS and GS bases from the
2060 * VMCS rather than the segment table. KVM uses this helper to figure
2061 * out the current bases to poke them into the VMCS before entry.
2063 static unsigned long segment_base(u16 selector
)
2065 struct desc_struct
*table
;
2068 if (!(selector
& ~SEGMENT_RPL_MASK
))
2071 table
= get_current_gdt_ro();
2073 if ((selector
& SEGMENT_TI_MASK
) == SEGMENT_LDT
) {
2074 u16 ldt_selector
= kvm_read_ldt();
2076 if (!(ldt_selector
& ~SEGMENT_RPL_MASK
))
2079 table
= (struct desc_struct
*)segment_base(ldt_selector
);
2081 v
= get_desc_base(&table
[selector
>> 3]);
2086 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
2088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2091 if (vmx
->host_state
.loaded
)
2094 vmx
->host_state
.loaded
= 1;
2096 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
2097 * allow segment selectors with cpl > 0 or ti == 1.
2099 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
2100 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
2101 savesegment(fs
, vmx
->host_state
.fs_sel
);
2102 if (!(vmx
->host_state
.fs_sel
& 7)) {
2103 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
2104 vmx
->host_state
.fs_reload_needed
= 0;
2106 vmcs_write16(HOST_FS_SELECTOR
, 0);
2107 vmx
->host_state
.fs_reload_needed
= 1;
2109 savesegment(gs
, vmx
->host_state
.gs_sel
);
2110 if (!(vmx
->host_state
.gs_sel
& 7))
2111 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
2113 vmcs_write16(HOST_GS_SELECTOR
, 0);
2114 vmx
->host_state
.gs_ldt_reload_needed
= 1;
2117 #ifdef CONFIG_X86_64
2118 savesegment(ds
, vmx
->host_state
.ds_sel
);
2119 savesegment(es
, vmx
->host_state
.es_sel
);
2122 #ifdef CONFIG_X86_64
2123 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
2124 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
2126 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
2127 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
2130 #ifdef CONFIG_X86_64
2131 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2132 if (is_long_mode(&vmx
->vcpu
))
2133 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2135 if (boot_cpu_has(X86_FEATURE_MPX
))
2136 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2137 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
2138 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
2139 vmx
->guest_msrs
[i
].data
,
2140 vmx
->guest_msrs
[i
].mask
);
2143 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
2145 if (!vmx
->host_state
.loaded
)
2148 ++vmx
->vcpu
.stat
.host_state_reload
;
2149 vmx
->host_state
.loaded
= 0;
2150 #ifdef CONFIG_X86_64
2151 if (is_long_mode(&vmx
->vcpu
))
2152 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2154 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2155 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2156 #ifdef CONFIG_X86_64
2157 load_gs_index(vmx
->host_state
.gs_sel
);
2159 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2162 if (vmx
->host_state
.fs_reload_needed
)
2163 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2164 #ifdef CONFIG_X86_64
2165 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2166 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2167 loadsegment(es
, vmx
->host_state
.es_sel
);
2170 invalidate_tss_limit();
2171 #ifdef CONFIG_X86_64
2172 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2174 if (vmx
->host_state
.msr_host_bndcfgs
)
2175 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2176 load_fixmap_gdt(raw_smp_processor_id());
2179 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2182 __vmx_load_host_state(vmx
);
2186 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2188 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2189 struct pi_desc old
, new;
2193 * In case of hot-plug or hot-unplug, we may have to undo
2194 * vmx_vcpu_pi_put even if there is no assigned device. And we
2195 * always keep PI.NDST up to date for simplicity: it makes the
2196 * code easier, and CPU migration is not a fast path.
2198 if (!pi_test_sn(pi_desc
) && vcpu
->cpu
== cpu
)
2202 * First handle the simple case where no cmpxchg is necessary; just
2203 * allow posting non-urgent interrupts.
2205 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
2206 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
2207 * expects the VCPU to be on the blocked_vcpu_list that matches
2210 if (pi_desc
->nv
== POSTED_INTR_WAKEUP_VECTOR
||
2212 pi_clear_sn(pi_desc
);
2216 /* The full case. */
2218 old
.control
= new.control
= pi_desc
->control
;
2220 dest
= cpu_physical_id(cpu
);
2222 if (x2apic_enabled())
2225 new.ndst
= (dest
<< 8) & 0xFF00;
2228 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
2229 new.control
) != old
.control
);
2232 static void decache_tsc_multiplier(struct vcpu_vmx
*vmx
)
2234 vmx
->current_tsc_ratio
= vmx
->vcpu
.arch
.tsc_scaling_ratio
;
2235 vmcs_write64(TSC_MULTIPLIER
, vmx
->current_tsc_ratio
);
2239 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2240 * vcpu mutex is already taken.
2242 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2244 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2245 bool already_loaded
= vmx
->loaded_vmcs
->cpu
== cpu
;
2247 if (!already_loaded
) {
2248 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2249 local_irq_disable();
2250 crash_disable_local_vmclear(cpu
);
2253 * Read loaded_vmcs->cpu should be before fetching
2254 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2255 * See the comments in __loaded_vmcs_clear().
2259 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2260 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2261 crash_enable_local_vmclear(cpu
);
2265 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2266 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2267 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2268 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
2269 native_wrmsrl(MSR_IA32_PRED_CMD
, FEATURE_SET_IBPB
);
2272 if (!already_loaded
) {
2273 void *gdt
= get_current_gdt_ro();
2274 unsigned long sysenter_esp
;
2276 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2279 * Linux uses per-cpu TSS and GDT, so set these when switching
2280 * processors. See 22.2.4.
2282 vmcs_writel(HOST_TR_BASE
,
2283 (unsigned long)&get_cpu_entry_area(cpu
)->tss
.x86_tss
);
2284 vmcs_writel(HOST_GDTR_BASE
, (unsigned long)gdt
); /* 22.2.4 */
2287 * VM exits change the host TR limit to 0x67 after a VM
2288 * exit. This is okay, since 0x67 covers everything except
2289 * the IO bitmap and have have code to handle the IO bitmap
2290 * being lost after a VM exit.
2292 BUILD_BUG_ON(IO_BITMAP_OFFSET
- 1 != 0x67);
2294 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2295 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2297 vmx
->loaded_vmcs
->cpu
= cpu
;
2300 /* Setup TSC multiplier */
2301 if (kvm_has_tsc_control
&&
2302 vmx
->current_tsc_ratio
!= vcpu
->arch
.tsc_scaling_ratio
)
2303 decache_tsc_multiplier(vmx
);
2305 vmx_vcpu_pi_load(vcpu
, cpu
);
2306 vmx
->host_pkru
= read_pkru();
2309 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2311 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2313 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2314 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
2315 !kvm_vcpu_apicv_active(vcpu
))
2318 /* Set SN when the vCPU is preempted */
2319 if (vcpu
->preempted
)
2323 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2325 vmx_vcpu_pi_put(vcpu
);
2327 __vmx_load_host_state(to_vmx(vcpu
));
2330 static bool emulation_required(struct kvm_vcpu
*vcpu
)
2332 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
2335 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2338 * Return the cr0 value that a nested guest would read. This is a combination
2339 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2340 * its hypervisor (cr0_read_shadow).
2342 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2344 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2345 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2347 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2349 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2350 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2353 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2355 unsigned long rflags
, save_rflags
;
2357 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2358 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2359 rflags
= vmcs_readl(GUEST_RFLAGS
);
2360 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2361 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2362 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2363 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2365 to_vmx(vcpu
)->rflags
= rflags
;
2367 return to_vmx(vcpu
)->rflags
;
2370 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2372 unsigned long old_rflags
= vmx_get_rflags(vcpu
);
2374 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2375 to_vmx(vcpu
)->rflags
= rflags
;
2376 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2377 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2378 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2380 vmcs_writel(GUEST_RFLAGS
, rflags
);
2382 if ((old_rflags
^ to_vmx(vcpu
)->rflags
) & X86_EFLAGS_VM
)
2383 to_vmx(vcpu
)->emulation_required
= emulation_required(vcpu
);
2386 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2388 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2391 if (interruptibility
& GUEST_INTR_STATE_STI
)
2392 ret
|= KVM_X86_SHADOW_INT_STI
;
2393 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2394 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2399 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2401 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2402 u32 interruptibility
= interruptibility_old
;
2404 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2406 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2407 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2408 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2409 interruptibility
|= GUEST_INTR_STATE_STI
;
2411 if ((interruptibility
!= interruptibility_old
))
2412 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2415 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2419 rip
= kvm_rip_read(vcpu
);
2420 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2421 kvm_rip_write(vcpu
, rip
);
2423 /* skipping an emulated instruction also counts */
2424 vmx_set_interrupt_shadow(vcpu
, 0);
2427 static void nested_vmx_inject_exception_vmexit(struct kvm_vcpu
*vcpu
,
2428 unsigned long exit_qual
)
2430 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2431 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2432 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2434 if (vcpu
->arch
.exception
.has_error_code
) {
2435 vmcs12
->vm_exit_intr_error_code
= vcpu
->arch
.exception
.error_code
;
2436 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2439 if (kvm_exception_is_soft(nr
))
2440 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2442 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2444 if (!(vmcs12
->idt_vectoring_info_field
& VECTORING_INFO_VALID_MASK
) &&
2445 vmx_get_nmi_mask(vcpu
))
2446 intr_info
|= INTR_INFO_UNBLOCK_NMI
;
2448 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
, intr_info
, exit_qual
);
2452 * KVM wants to inject page-faults which it got to the guest. This function
2453 * checks whether in a nested guest, we need to inject them to L1 or L2.
2455 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
)
2457 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2458 unsigned int nr
= vcpu
->arch
.exception
.nr
;
2460 if (nr
== PF_VECTOR
) {
2461 if (vcpu
->arch
.exception
.nested_apf
) {
2462 nested_vmx_inject_exception_vmexit(vcpu
,
2463 vcpu
->arch
.apf
.nested_apf_token
);
2467 * FIXME: we must not write CR2 when L1 intercepts an L2 #PF exception.
2468 * The fix is to add the ancillary datum (CR2 or DR6) to structs
2469 * kvm_queued_exception and kvm_vcpu_events, so that CR2 and DR6
2470 * can be written only when inject_pending_event runs. This should be
2471 * conditional on a new capability---if the capability is disabled,
2472 * kvm_multiple_exception would write the ancillary information to
2473 * CR2 or DR6, for backwards ABI-compatibility.
2475 if (nested_vmx_is_page_fault_vmexit(vmcs12
,
2476 vcpu
->arch
.exception
.error_code
)) {
2477 nested_vmx_inject_exception_vmexit(vcpu
, vcpu
->arch
.cr2
);
2481 unsigned long exit_qual
= 0;
2482 if (nr
== DB_VECTOR
)
2483 exit_qual
= vcpu
->arch
.dr6
;
2485 if (vmcs12
->exception_bitmap
& (1u << nr
)) {
2486 nested_vmx_inject_exception_vmexit(vcpu
, exit_qual
);
2494 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
)
2496 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2497 unsigned nr
= vcpu
->arch
.exception
.nr
;
2498 bool has_error_code
= vcpu
->arch
.exception
.has_error_code
;
2499 bool reinject
= vcpu
->arch
.exception
.reinject
;
2500 u32 error_code
= vcpu
->arch
.exception
.error_code
;
2501 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2503 if (!reinject
&& is_guest_mode(vcpu
) &&
2504 nested_vmx_check_exception(vcpu
))
2507 if (has_error_code
) {
2508 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2509 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2512 if (vmx
->rmode
.vm86_active
) {
2514 if (kvm_exception_is_soft(nr
))
2515 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2516 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2517 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2521 if (kvm_exception_is_soft(nr
)) {
2522 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2523 vmx
->vcpu
.arch
.event_exit_inst_len
);
2524 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2526 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2528 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2531 static bool vmx_rdtscp_supported(void)
2533 return cpu_has_vmx_rdtscp();
2536 static bool vmx_invpcid_supported(void)
2538 return cpu_has_vmx_invpcid() && enable_ept
;
2542 * Swap MSR entry in host/guest MSR entry array.
2544 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2546 struct shared_msr_entry tmp
;
2548 tmp
= vmx
->guest_msrs
[to
];
2549 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2550 vmx
->guest_msrs
[from
] = tmp
;
2553 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2555 unsigned long *msr_bitmap
;
2557 if (is_guest_mode(vcpu
))
2558 msr_bitmap
= to_vmx(vcpu
)->nested
.msr_bitmap
;
2559 else if (cpu_has_secondary_exec_ctrls() &&
2560 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL
) &
2561 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
)) {
2562 if (enable_apicv
&& kvm_vcpu_apicv_active(vcpu
)) {
2563 if (is_long_mode(vcpu
))
2564 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic_apicv
;
2566 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic_apicv
;
2568 if (is_long_mode(vcpu
))
2569 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2571 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2574 if (is_long_mode(vcpu
))
2575 msr_bitmap
= vmx_msr_bitmap_longmode
;
2577 msr_bitmap
= vmx_msr_bitmap_legacy
;
2580 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2584 * Set up the vmcs to automatically save and restore system
2585 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2586 * mode, as fiddling with msrs is very expensive.
2588 static void setup_msrs(struct vcpu_vmx
*vmx
)
2590 int save_nmsrs
, index
;
2593 #ifdef CONFIG_X86_64
2594 if (is_long_mode(&vmx
->vcpu
)) {
2595 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2597 move_msr_up(vmx
, index
, save_nmsrs
++);
2598 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2600 move_msr_up(vmx
, index
, save_nmsrs
++);
2601 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2603 move_msr_up(vmx
, index
, save_nmsrs
++);
2604 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2605 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2606 move_msr_up(vmx
, index
, save_nmsrs
++);
2608 * MSR_STAR is only needed on long mode guests, and only
2609 * if efer.sce is enabled.
2611 index
= __find_msr_index(vmx
, MSR_STAR
);
2612 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2613 move_msr_up(vmx
, index
, save_nmsrs
++);
2616 index
= __find_msr_index(vmx
, MSR_EFER
);
2617 if (index
>= 0 && update_transition_efer(vmx
, index
))
2618 move_msr_up(vmx
, index
, save_nmsrs
++);
2620 vmx
->save_nmsrs
= save_nmsrs
;
2622 if (cpu_has_vmx_msr_bitmap())
2623 vmx_set_msr_bitmap(&vmx
->vcpu
);
2627 * reads and returns guest's timestamp counter "register"
2628 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2629 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2631 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2633 u64 host_tsc
, tsc_offset
;
2636 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2637 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2641 * writes 'offset' into guest's timestamp counter offset register
2643 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2645 if (is_guest_mode(vcpu
)) {
2647 * We're here if L1 chose not to trap WRMSR to TSC. According
2648 * to the spec, this should set L1's TSC; The offset that L1
2649 * set for L2 remains unchanged, and still needs to be added
2650 * to the newly set TSC to get L2's TSC.
2652 struct vmcs12
*vmcs12
;
2653 /* recalculate vmcs02.TSC_OFFSET: */
2654 vmcs12
= get_vmcs12(vcpu
);
2655 vmcs_write64(TSC_OFFSET
, offset
+
2656 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2657 vmcs12
->tsc_offset
: 0));
2659 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2660 vmcs_read64(TSC_OFFSET
), offset
);
2661 vmcs_write64(TSC_OFFSET
, offset
);
2665 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2667 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2668 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2672 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2673 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2674 * all guests if the "nested" module option is off, and can also be disabled
2675 * for a single guest by disabling its VMX cpuid bit.
2677 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2679 return nested
&& guest_cpuid_has_vmx(vcpu
);
2683 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2684 * returned for the various VMX controls MSRs when nested VMX is enabled.
2685 * The same values should also be used to verify that vmcs12 control fields are
2686 * valid during nested entry from L1 to L2.
2687 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2688 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2689 * bit in the high half is on if the corresponding bit in the control field
2690 * may be on. See also vmx_control_verify().
2692 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2695 * Note that as a general rule, the high half of the MSRs (bits in
2696 * the control fields which may be 1) should be initialized by the
2697 * intersection of the underlying hardware's MSR (i.e., features which
2698 * can be supported) and the list of features we want to expose -
2699 * because they are known to be properly supported in our code.
2700 * Also, usually, the low half of the MSRs (bits which must be 1) can
2701 * be set to 0, meaning that L1 may turn off any of these bits. The
2702 * reason is that if one of these bits is necessary, it will appear
2703 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2704 * fields of vmcs01 and vmcs02, will turn these bits off - and
2705 * nested_vmx_exit_reflected() will not pass related exits to L1.
2706 * These rules have exceptions below.
2709 /* pin-based controls */
2710 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2711 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2712 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2713 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2714 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2715 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2716 PIN_BASED_EXT_INTR_MASK
|
2717 PIN_BASED_NMI_EXITING
|
2718 PIN_BASED_VIRTUAL_NMIS
;
2719 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2720 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2721 PIN_BASED_VMX_PREEMPTION_TIMER
;
2722 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2723 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2724 PIN_BASED_POSTED_INTR
;
2727 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2728 vmx
->nested
.nested_vmx_exit_ctls_low
,
2729 vmx
->nested
.nested_vmx_exit_ctls_high
);
2730 vmx
->nested
.nested_vmx_exit_ctls_low
=
2731 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2733 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2734 #ifdef CONFIG_X86_64
2735 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2737 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2738 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2739 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2740 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2741 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2743 if (kvm_mpx_supported())
2744 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2746 /* We support free control of debug control saving. */
2747 vmx
->nested
.nested_vmx_exit_ctls_low
&= ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2749 /* entry controls */
2750 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2751 vmx
->nested
.nested_vmx_entry_ctls_low
,
2752 vmx
->nested
.nested_vmx_entry_ctls_high
);
2753 vmx
->nested
.nested_vmx_entry_ctls_low
=
2754 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2755 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2756 #ifdef CONFIG_X86_64
2757 VM_ENTRY_IA32E_MODE
|
2759 VM_ENTRY_LOAD_IA32_PAT
;
2760 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2761 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2762 if (kvm_mpx_supported())
2763 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2765 /* We support free control of debug control loading. */
2766 vmx
->nested
.nested_vmx_entry_ctls_low
&= ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2768 /* cpu-based controls */
2769 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2770 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2771 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2772 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2773 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2774 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2775 CPU_BASED_VIRTUAL_INTR_PENDING
|
2776 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2777 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2778 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2779 CPU_BASED_CR3_STORE_EXITING
|
2780 #ifdef CONFIG_X86_64
2781 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2783 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2784 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2785 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2786 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2787 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2789 * We can allow some features even when not supported by the
2790 * hardware. For example, L1 can specify an MSR bitmap - and we
2791 * can use it to avoid exits to L1 - even when L0 runs L2
2792 * without MSR bitmaps.
2794 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2795 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2796 CPU_BASED_USE_MSR_BITMAPS
;
2798 /* We support free control of CR3 access interception. */
2799 vmx
->nested
.nested_vmx_procbased_ctls_low
&=
2800 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2802 /* secondary cpu-based controls */
2803 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2804 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2805 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2806 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2807 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2808 SECONDARY_EXEC_RDRAND
| SECONDARY_EXEC_RDSEED
|
2809 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2810 SECONDARY_EXEC_RDTSCP
|
2811 SECONDARY_EXEC_DESC
|
2812 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2813 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2814 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2815 SECONDARY_EXEC_WBINVD_EXITING
|
2816 SECONDARY_EXEC_XSAVES
;
2819 /* nested EPT: emulate EPT also to L1 */
2820 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2821 SECONDARY_EXEC_ENABLE_EPT
;
2822 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2823 VMX_EPTP_WB_BIT
| VMX_EPT_INVEPT_BIT
;
2824 if (cpu_has_vmx_ept_execute_only())
2825 vmx
->nested
.nested_vmx_ept_caps
|=
2826 VMX_EPT_EXECUTE_ONLY_BIT
;
2827 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2828 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
|
2829 VMX_EPT_EXTENT_CONTEXT_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2830 VMX_EPT_1GB_PAGE_BIT
;
2831 if (enable_ept_ad_bits
) {
2832 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2833 SECONDARY_EXEC_ENABLE_PML
;
2834 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_AD_BIT
;
2837 vmx
->nested
.nested_vmx_ept_caps
= 0;
2840 * Old versions of KVM use the single-context version without
2841 * checking for support, so declare that it is supported even
2842 * though it is treated as global context. The alternative is
2843 * not failing the single-context invvpid, and it is worse.
2846 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2847 SECONDARY_EXEC_ENABLE_VPID
;
2848 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2849 VMX_VPID_EXTENT_SUPPORTED_MASK
;
2851 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2853 if (enable_unrestricted_guest
)
2854 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2855 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2857 /* miscellaneous data */
2858 rdmsr(MSR_IA32_VMX_MISC
,
2859 vmx
->nested
.nested_vmx_misc_low
,
2860 vmx
->nested
.nested_vmx_misc_high
);
2861 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2862 vmx
->nested
.nested_vmx_misc_low
|=
2863 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2864 VMX_MISC_ACTIVITY_HLT
;
2865 vmx
->nested
.nested_vmx_misc_high
= 0;
2868 * This MSR reports some information about VMX support. We
2869 * should return information about the VMX we emulate for the
2870 * guest, and the VMCS structure we give it - not about the
2871 * VMX support of the underlying hardware.
2873 vmx
->nested
.nested_vmx_basic
=
2875 VMX_BASIC_TRUE_CTLS
|
2876 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2877 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2879 if (cpu_has_vmx_basic_inout())
2880 vmx
->nested
.nested_vmx_basic
|= VMX_BASIC_INOUT
;
2883 * These MSRs specify bits which the guest must keep fixed on
2884 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2885 * We picked the standard core2 setting.
2887 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2888 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2889 vmx
->nested
.nested_vmx_cr0_fixed0
= VMXON_CR0_ALWAYSON
;
2890 vmx
->nested
.nested_vmx_cr4_fixed0
= VMXON_CR4_ALWAYSON
;
2892 /* These MSRs specify bits which the guest must keep fixed off. */
2893 rdmsrl(MSR_IA32_VMX_CR0_FIXED1
, vmx
->nested
.nested_vmx_cr0_fixed1
);
2894 rdmsrl(MSR_IA32_VMX_CR4_FIXED1
, vmx
->nested
.nested_vmx_cr4_fixed1
);
2896 /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2897 vmx
->nested
.nested_vmx_vmcs_enum
= 0x2e;
2901 * if fixed0[i] == 1: val[i] must be 1
2902 * if fixed1[i] == 0: val[i] must be 0
2904 static inline bool fixed_bits_valid(u64 val
, u64 fixed0
, u64 fixed1
)
2906 return ((val
& fixed1
) | fixed0
) == val
;
2909 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2911 return fixed_bits_valid(control
, low
, high
);
2914 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2916 return low
| ((u64
)high
<< 32);
2919 static bool is_bitwise_subset(u64 superset
, u64 subset
, u64 mask
)
2924 return (superset
| subset
) == superset
;
2927 static int vmx_restore_vmx_basic(struct vcpu_vmx
*vmx
, u64 data
)
2929 const u64 feature_and_reserved
=
2930 /* feature (except bit 48; see below) */
2931 BIT_ULL(49) | BIT_ULL(54) | BIT_ULL(55) |
2933 BIT_ULL(31) | GENMASK_ULL(47, 45) | GENMASK_ULL(63, 56);
2934 u64 vmx_basic
= vmx
->nested
.nested_vmx_basic
;
2936 if (!is_bitwise_subset(vmx_basic
, data
, feature_and_reserved
))
2940 * KVM does not emulate a version of VMX that constrains physical
2941 * addresses of VMX structures (e.g. VMCS) to 32-bits.
2943 if (data
& BIT_ULL(48))
2946 if (vmx_basic_vmcs_revision_id(vmx_basic
) !=
2947 vmx_basic_vmcs_revision_id(data
))
2950 if (vmx_basic_vmcs_size(vmx_basic
) > vmx_basic_vmcs_size(data
))
2953 vmx
->nested
.nested_vmx_basic
= data
;
2958 vmx_restore_control_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
2963 switch (msr_index
) {
2964 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2965 lowp
= &vmx
->nested
.nested_vmx_pinbased_ctls_low
;
2966 highp
= &vmx
->nested
.nested_vmx_pinbased_ctls_high
;
2968 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2969 lowp
= &vmx
->nested
.nested_vmx_procbased_ctls_low
;
2970 highp
= &vmx
->nested
.nested_vmx_procbased_ctls_high
;
2972 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2973 lowp
= &vmx
->nested
.nested_vmx_exit_ctls_low
;
2974 highp
= &vmx
->nested
.nested_vmx_exit_ctls_high
;
2976 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2977 lowp
= &vmx
->nested
.nested_vmx_entry_ctls_low
;
2978 highp
= &vmx
->nested
.nested_vmx_entry_ctls_high
;
2980 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2981 lowp
= &vmx
->nested
.nested_vmx_secondary_ctls_low
;
2982 highp
= &vmx
->nested
.nested_vmx_secondary_ctls_high
;
2988 supported
= vmx_control_msr(*lowp
, *highp
);
2990 /* Check must-be-1 bits are still 1. */
2991 if (!is_bitwise_subset(data
, supported
, GENMASK_ULL(31, 0)))
2994 /* Check must-be-0 bits are still 0. */
2995 if (!is_bitwise_subset(supported
, data
, GENMASK_ULL(63, 32)))
2999 *highp
= data
>> 32;
3003 static int vmx_restore_vmx_misc(struct vcpu_vmx
*vmx
, u64 data
)
3005 const u64 feature_and_reserved_bits
=
3007 BIT_ULL(5) | GENMASK_ULL(8, 6) | BIT_ULL(14) | BIT_ULL(15) |
3008 BIT_ULL(28) | BIT_ULL(29) | BIT_ULL(30) |
3010 GENMASK_ULL(13, 9) | BIT_ULL(31);
3013 vmx_misc
= vmx_control_msr(vmx
->nested
.nested_vmx_misc_low
,
3014 vmx
->nested
.nested_vmx_misc_high
);
3016 if (!is_bitwise_subset(vmx_misc
, data
, feature_and_reserved_bits
))
3019 if ((vmx
->nested
.nested_vmx_pinbased_ctls_high
&
3020 PIN_BASED_VMX_PREEMPTION_TIMER
) &&
3021 vmx_misc_preemption_timer_rate(data
) !=
3022 vmx_misc_preemption_timer_rate(vmx_misc
))
3025 if (vmx_misc_cr3_count(data
) > vmx_misc_cr3_count(vmx_misc
))
3028 if (vmx_misc_max_msr(data
) > vmx_misc_max_msr(vmx_misc
))
3031 if (vmx_misc_mseg_revid(data
) != vmx_misc_mseg_revid(vmx_misc
))
3034 vmx
->nested
.nested_vmx_misc_low
= data
;
3035 vmx
->nested
.nested_vmx_misc_high
= data
>> 32;
3039 static int vmx_restore_vmx_ept_vpid_cap(struct vcpu_vmx
*vmx
, u64 data
)
3041 u64 vmx_ept_vpid_cap
;
3043 vmx_ept_vpid_cap
= vmx_control_msr(vmx
->nested
.nested_vmx_ept_caps
,
3044 vmx
->nested
.nested_vmx_vpid_caps
);
3046 /* Every bit is either reserved or a feature bit. */
3047 if (!is_bitwise_subset(vmx_ept_vpid_cap
, data
, -1ULL))
3050 vmx
->nested
.nested_vmx_ept_caps
= data
;
3051 vmx
->nested
.nested_vmx_vpid_caps
= data
>> 32;
3055 static int vmx_restore_fixed0_msr(struct vcpu_vmx
*vmx
, u32 msr_index
, u64 data
)
3059 switch (msr_index
) {
3060 case MSR_IA32_VMX_CR0_FIXED0
:
3061 msr
= &vmx
->nested
.nested_vmx_cr0_fixed0
;
3063 case MSR_IA32_VMX_CR4_FIXED0
:
3064 msr
= &vmx
->nested
.nested_vmx_cr4_fixed0
;
3071 * 1 bits (which indicates bits which "must-be-1" during VMX operation)
3072 * must be 1 in the restored value.
3074 if (!is_bitwise_subset(data
, *msr
, -1ULL))
3082 * Called when userspace is restoring VMX MSRs.
3084 * Returns 0 on success, non-0 otherwise.
3086 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
3088 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3090 switch (msr_index
) {
3091 case MSR_IA32_VMX_BASIC
:
3092 return vmx_restore_vmx_basic(vmx
, data
);
3093 case MSR_IA32_VMX_PINBASED_CTLS
:
3094 case MSR_IA32_VMX_PROCBASED_CTLS
:
3095 case MSR_IA32_VMX_EXIT_CTLS
:
3096 case MSR_IA32_VMX_ENTRY_CTLS
:
3098 * The "non-true" VMX capability MSRs are generated from the
3099 * "true" MSRs, so we do not support restoring them directly.
3101 * If userspace wants to emulate VMX_BASIC[55]=0, userspace
3102 * should restore the "true" MSRs with the must-be-1 bits
3103 * set according to the SDM Vol 3. A.2 "RESERVED CONTROLS AND
3104 * DEFAULT SETTINGS".
3107 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3108 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3109 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3110 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3111 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3112 return vmx_restore_control_msr(vmx
, msr_index
, data
);
3113 case MSR_IA32_VMX_MISC
:
3114 return vmx_restore_vmx_misc(vmx
, data
);
3115 case MSR_IA32_VMX_CR0_FIXED0
:
3116 case MSR_IA32_VMX_CR4_FIXED0
:
3117 return vmx_restore_fixed0_msr(vmx
, msr_index
, data
);
3118 case MSR_IA32_VMX_CR0_FIXED1
:
3119 case MSR_IA32_VMX_CR4_FIXED1
:
3121 * These MSRs are generated based on the vCPU's CPUID, so we
3122 * do not support restoring them directly.
3125 case MSR_IA32_VMX_EPT_VPID_CAP
:
3126 return vmx_restore_vmx_ept_vpid_cap(vmx
, data
);
3127 case MSR_IA32_VMX_VMCS_ENUM
:
3128 vmx
->nested
.nested_vmx_vmcs_enum
= data
;
3132 * The rest of the VMX capability MSRs do not support restore.
3138 /* Returns 0 on success, non-0 otherwise. */
3139 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
3141 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3143 switch (msr_index
) {
3144 case MSR_IA32_VMX_BASIC
:
3145 *pdata
= vmx
->nested
.nested_vmx_basic
;
3147 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
3148 case MSR_IA32_VMX_PINBASED_CTLS
:
3149 *pdata
= vmx_control_msr(
3150 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
3151 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
3152 if (msr_index
== MSR_IA32_VMX_PINBASED_CTLS
)
3153 *pdata
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3155 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
3156 case MSR_IA32_VMX_PROCBASED_CTLS
:
3157 *pdata
= vmx_control_msr(
3158 vmx
->nested
.nested_vmx_procbased_ctls_low
,
3159 vmx
->nested
.nested_vmx_procbased_ctls_high
);
3160 if (msr_index
== MSR_IA32_VMX_PROCBASED_CTLS
)
3161 *pdata
|= CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
3163 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
3164 case MSR_IA32_VMX_EXIT_CTLS
:
3165 *pdata
= vmx_control_msr(
3166 vmx
->nested
.nested_vmx_exit_ctls_low
,
3167 vmx
->nested
.nested_vmx_exit_ctls_high
);
3168 if (msr_index
== MSR_IA32_VMX_EXIT_CTLS
)
3169 *pdata
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
3171 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
3172 case MSR_IA32_VMX_ENTRY_CTLS
:
3173 *pdata
= vmx_control_msr(
3174 vmx
->nested
.nested_vmx_entry_ctls_low
,
3175 vmx
->nested
.nested_vmx_entry_ctls_high
);
3176 if (msr_index
== MSR_IA32_VMX_ENTRY_CTLS
)
3177 *pdata
|= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
3179 case MSR_IA32_VMX_MISC
:
3180 *pdata
= vmx_control_msr(
3181 vmx
->nested
.nested_vmx_misc_low
,
3182 vmx
->nested
.nested_vmx_misc_high
);
3184 case MSR_IA32_VMX_CR0_FIXED0
:
3185 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed0
;
3187 case MSR_IA32_VMX_CR0_FIXED1
:
3188 *pdata
= vmx
->nested
.nested_vmx_cr0_fixed1
;
3190 case MSR_IA32_VMX_CR4_FIXED0
:
3191 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed0
;
3193 case MSR_IA32_VMX_CR4_FIXED1
:
3194 *pdata
= vmx
->nested
.nested_vmx_cr4_fixed1
;
3196 case MSR_IA32_VMX_VMCS_ENUM
:
3197 *pdata
= vmx
->nested
.nested_vmx_vmcs_enum
;
3199 case MSR_IA32_VMX_PROCBASED_CTLS2
:
3200 *pdata
= vmx_control_msr(
3201 vmx
->nested
.nested_vmx_secondary_ctls_low
,
3202 vmx
->nested
.nested_vmx_secondary_ctls_high
);
3204 case MSR_IA32_VMX_EPT_VPID_CAP
:
3205 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
3206 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
3215 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu
*vcpu
,
3218 uint64_t valid_bits
= to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
;
3220 return !(val
& ~valid_bits
);
3224 * Reads an msr value (of 'msr_index') into 'pdata'.
3225 * Returns 0 on success, non-0 otherwise.
3226 * Assumes vcpu_load() was already called.
3228 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3230 struct shared_msr_entry
*msr
;
3232 switch (msr_info
->index
) {
3233 #ifdef CONFIG_X86_64
3235 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
3238 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
3240 case MSR_KERNEL_GS_BASE
:
3241 vmx_load_host_state(to_vmx(vcpu
));
3242 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
3246 return kvm_get_msr_common(vcpu
, msr_info
);
3248 msr_info
->data
= guest_read_tsc(vcpu
);
3250 case MSR_IA32_SPEC_CTRL
:
3251 msr_info
->data
= vcpu
->arch
.spec_ctrl
;
3253 case MSR_IA32_SYSENTER_CS
:
3254 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
3256 case MSR_IA32_SYSENTER_EIP
:
3257 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
3259 case MSR_IA32_SYSENTER_ESP
:
3260 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
3262 case MSR_IA32_BNDCFGS
:
3263 if (!kvm_mpx_supported() ||
3264 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3266 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
3268 case MSR_IA32_MCG_EXT_CTL
:
3269 if (!msr_info
->host_initiated
&&
3270 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3271 FEATURE_CONTROL_LMCE
))
3273 msr_info
->data
= vcpu
->arch
.mcg_ext_ctl
;
3275 case MSR_IA32_FEATURE_CONTROL
:
3276 msr_info
->data
= to_vmx(vcpu
)->msr_ia32_feature_control
;
3278 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3279 if (!nested_vmx_allowed(vcpu
))
3281 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
3283 if (!vmx_xsaves_supported())
3285 msr_info
->data
= vcpu
->arch
.ia32_xss
;
3288 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3290 /* Otherwise falls through */
3292 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
3294 msr_info
->data
= msr
->data
;
3297 return kvm_get_msr_common(vcpu
, msr_info
);
3303 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
3306 * Writes msr value into into the appropriate "register".
3307 * Returns 0 on success, non-0 otherwise.
3308 * Assumes vcpu_load() was already called.
3310 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
3312 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3313 struct shared_msr_entry
*msr
;
3315 u32 msr_index
= msr_info
->index
;
3316 u64 data
= msr_info
->data
;
3318 switch (msr_index
) {
3320 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3322 #ifdef CONFIG_X86_64
3324 vmx_segment_cache_clear(vmx
);
3325 vmcs_writel(GUEST_FS_BASE
, data
);
3328 vmx_segment_cache_clear(vmx
);
3329 vmcs_writel(GUEST_GS_BASE
, data
);
3331 case MSR_KERNEL_GS_BASE
:
3332 vmx_load_host_state(vmx
);
3333 vmx
->msr_guest_kernel_gs_base
= data
;
3336 case MSR_IA32_SYSENTER_CS
:
3337 vmcs_write32(GUEST_SYSENTER_CS
, data
);
3339 case MSR_IA32_SYSENTER_EIP
:
3340 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
3342 case MSR_IA32_SYSENTER_ESP
:
3343 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
3345 case MSR_IA32_BNDCFGS
:
3346 if (!kvm_mpx_supported() ||
3347 (!msr_info
->host_initiated
&& !guest_cpuid_has_mpx(vcpu
)))
3349 if (is_noncanonical_address(data
& PAGE_MASK
) ||
3350 (data
& MSR_IA32_BNDCFGS_RSVD
))
3352 vmcs_write64(GUEST_BNDCFGS
, data
);
3355 kvm_write_tsc(vcpu
, msr_info
);
3357 case MSR_IA32_SPEC_CTRL
:
3358 vcpu
->arch
.spec_ctrl
= msr_info
->data
;
3360 case MSR_IA32_CR_PAT
:
3361 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3362 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
3364 vmcs_write64(GUEST_IA32_PAT
, data
);
3365 vcpu
->arch
.pat
= data
;
3368 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3370 case MSR_IA32_TSC_ADJUST
:
3371 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3373 case MSR_IA32_MCG_EXT_CTL
:
3374 if ((!msr_info
->host_initiated
&&
3375 !(to_vmx(vcpu
)->msr_ia32_feature_control
&
3376 FEATURE_CONTROL_LMCE
)) ||
3377 (data
& ~MCG_EXT_CTL_LMCE_EN
))
3379 vcpu
->arch
.mcg_ext_ctl
= data
;
3381 case MSR_IA32_FEATURE_CONTROL
:
3382 if (!vmx_feature_control_msr_valid(vcpu
, data
) ||
3383 (to_vmx(vcpu
)->msr_ia32_feature_control
&
3384 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
3386 vmx
->msr_ia32_feature_control
= data
;
3387 if (msr_info
->host_initiated
&& data
== 0)
3388 vmx_leave_nested(vcpu
);
3390 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
3391 if (!msr_info
->host_initiated
)
3392 return 1; /* they are read-only */
3393 if (!nested_vmx_allowed(vcpu
))
3395 return vmx_set_vmx_msr(vcpu
, msr_index
, data
);
3397 if (!vmx_xsaves_supported())
3400 * The only supported bit as of Skylake is bit 8, but
3401 * it is not supported on KVM.
3405 vcpu
->arch
.ia32_xss
= data
;
3406 if (vcpu
->arch
.ia32_xss
!= host_xss
)
3407 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
3408 vcpu
->arch
.ia32_xss
, host_xss
);
3410 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
3413 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
3415 /* Check reserved bit, higher 32 bits should be zero */
3416 if ((data
>> 32) != 0)
3418 /* Otherwise falls through */
3420 msr
= find_msr_entry(vmx
, msr_index
);
3422 u64 old_msr_data
= msr
->data
;
3424 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3426 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3430 msr
->data
= old_msr_data
;
3434 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3440 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3442 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3445 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3448 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3450 case VCPU_EXREG_PDPTR
:
3452 ept_save_pdptrs(vcpu
);
3459 static __init
int cpu_has_kvm_support(void)
3461 return cpu_has_vmx();
3464 static __init
int vmx_disabled_by_bios(void)
3468 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3469 if (msr
& FEATURE_CONTROL_LOCKED
) {
3470 /* launched w/ TXT and VMX disabled */
3471 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3474 /* launched w/o TXT and VMX only enabled w/ TXT */
3475 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3476 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3477 && !tboot_enabled()) {
3478 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3479 "activate TXT before enabling KVM\n");
3482 /* launched w/o TXT and VMX disabled */
3483 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3484 && !tboot_enabled())
3491 static void kvm_cpu_vmxon(u64 addr
)
3493 cr4_set_bits(X86_CR4_VMXE
);
3494 intel_pt_handle_vmx(1);
3496 asm volatile (ASM_VMX_VMXON_RAX
3497 : : "a"(&addr
), "m"(addr
)
3501 static int hardware_enable(void)
3503 int cpu
= raw_smp_processor_id();
3504 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3507 if (cr4_read_shadow() & X86_CR4_VMXE
)
3510 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3511 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3512 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3515 * Now we can enable the vmclear operation in kdump
3516 * since the loaded_vmcss_on_cpu list on this cpu
3517 * has been initialized.
3519 * Though the cpu is not in VMX operation now, there
3520 * is no problem to enable the vmclear operation
3521 * for the loaded_vmcss_on_cpu list is empty!
3523 crash_enable_local_vmclear(cpu
);
3525 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3527 test_bits
= FEATURE_CONTROL_LOCKED
;
3528 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3529 if (tboot_enabled())
3530 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3532 if ((old
& test_bits
) != test_bits
) {
3533 /* enable and lock */
3534 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3536 kvm_cpu_vmxon(phys_addr
);
3542 static void vmclear_local_loaded_vmcss(void)
3544 int cpu
= raw_smp_processor_id();
3545 struct loaded_vmcs
*v
, *n
;
3547 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3548 loaded_vmcss_on_cpu_link
)
3549 __loaded_vmcs_clear(v
);
3553 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3556 static void kvm_cpu_vmxoff(void)
3558 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3560 intel_pt_handle_vmx(0);
3561 cr4_clear_bits(X86_CR4_VMXE
);
3564 static void hardware_disable(void)
3566 vmclear_local_loaded_vmcss();
3570 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3571 u32 msr
, u32
*result
)
3573 u32 vmx_msr_low
, vmx_msr_high
;
3574 u32 ctl
= ctl_min
| ctl_opt
;
3576 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3578 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3579 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3581 /* Ensure minimum (required) set of control bits are supported. */
3589 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3591 u32 vmx_msr_low
, vmx_msr_high
;
3593 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3594 return vmx_msr_high
& ctl
;
3597 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3599 u32 vmx_msr_low
, vmx_msr_high
;
3600 u32 min
, opt
, min2
, opt2
;
3601 u32 _pin_based_exec_control
= 0;
3602 u32 _cpu_based_exec_control
= 0;
3603 u32 _cpu_based_2nd_exec_control
= 0;
3604 u32 _vmexit_control
= 0;
3605 u32 _vmentry_control
= 0;
3607 min
= CPU_BASED_HLT_EXITING
|
3608 #ifdef CONFIG_X86_64
3609 CPU_BASED_CR8_LOAD_EXITING
|
3610 CPU_BASED_CR8_STORE_EXITING
|
3612 CPU_BASED_CR3_LOAD_EXITING
|
3613 CPU_BASED_CR3_STORE_EXITING
|
3614 CPU_BASED_USE_IO_BITMAPS
|
3615 CPU_BASED_MOV_DR_EXITING
|
3616 CPU_BASED_USE_TSC_OFFSETING
|
3617 CPU_BASED_INVLPG_EXITING
|
3618 CPU_BASED_RDPMC_EXITING
;
3620 if (!kvm_mwait_in_guest())
3621 min
|= CPU_BASED_MWAIT_EXITING
|
3622 CPU_BASED_MONITOR_EXITING
;
3624 opt
= CPU_BASED_TPR_SHADOW
|
3625 CPU_BASED_USE_MSR_BITMAPS
|
3626 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3627 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3628 &_cpu_based_exec_control
) < 0)
3630 #ifdef CONFIG_X86_64
3631 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3632 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3633 ~CPU_BASED_CR8_STORE_EXITING
;
3635 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3637 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3638 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3639 SECONDARY_EXEC_WBINVD_EXITING
|
3640 SECONDARY_EXEC_ENABLE_VPID
|
3641 SECONDARY_EXEC_ENABLE_EPT
|
3642 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3643 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3644 SECONDARY_EXEC_RDTSCP
|
3645 SECONDARY_EXEC_ENABLE_INVPCID
|
3646 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3647 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3648 SECONDARY_EXEC_SHADOW_VMCS
|
3649 SECONDARY_EXEC_XSAVES
|
3650 SECONDARY_EXEC_ENABLE_PML
|
3651 SECONDARY_EXEC_TSC_SCALING
;
3652 if (adjust_vmx_controls(min2
, opt2
,
3653 MSR_IA32_VMX_PROCBASED_CTLS2
,
3654 &_cpu_based_2nd_exec_control
) < 0)
3657 #ifndef CONFIG_X86_64
3658 if (!(_cpu_based_2nd_exec_control
&
3659 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3660 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3663 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3664 _cpu_based_2nd_exec_control
&= ~(
3665 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3666 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3667 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3669 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3670 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3672 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3673 CPU_BASED_CR3_STORE_EXITING
|
3674 CPU_BASED_INVLPG_EXITING
);
3675 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3676 vmx_capability
.ept
, vmx_capability
.vpid
);
3679 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
| VM_EXIT_ACK_INTR_ON_EXIT
;
3680 #ifdef CONFIG_X86_64
3681 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3683 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3684 VM_EXIT_CLEAR_BNDCFGS
;
3685 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3686 &_vmexit_control
) < 0)
3689 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
3690 PIN_BASED_VIRTUAL_NMIS
;
3691 opt
= PIN_BASED_POSTED_INTR
| PIN_BASED_VMX_PREEMPTION_TIMER
;
3692 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3693 &_pin_based_exec_control
) < 0)
3696 if (cpu_has_broken_vmx_preemption_timer())
3697 _pin_based_exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
3698 if (!(_cpu_based_2nd_exec_control
&
3699 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
))
3700 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3702 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3703 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3704 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3705 &_vmentry_control
) < 0)
3708 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3710 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3711 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3714 #ifdef CONFIG_X86_64
3715 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3716 if (vmx_msr_high
& (1u<<16))
3720 /* Require Write-Back (WB) memory type for VMCS accesses. */
3721 if (((vmx_msr_high
>> 18) & 15) != 6)
3724 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3725 vmcs_conf
->order
= get_order(vmcs_conf
->size
);
3726 vmcs_conf
->basic_cap
= vmx_msr_high
& ~0x1fff;
3727 vmcs_conf
->revision_id
= vmx_msr_low
;
3729 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3730 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3731 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3732 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3733 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3735 cpu_has_load_ia32_efer
=
3736 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3737 VM_ENTRY_LOAD_IA32_EFER
)
3738 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3739 VM_EXIT_LOAD_IA32_EFER
);
3741 cpu_has_load_perf_global_ctrl
=
3742 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3743 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3744 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3745 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3748 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3749 * but due to errata below it can't be used. Workaround is to use
3750 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3752 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3757 * BC86,AAY89,BD102 (model 44)
3761 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3762 switch (boot_cpu_data
.x86_model
) {
3768 cpu_has_load_perf_global_ctrl
= false;
3769 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3770 "does not work properly. Using workaround\n");
3777 if (boot_cpu_has(X86_FEATURE_XSAVES
))
3778 rdmsrl(MSR_IA32_XSS
, host_xss
);
3783 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3785 int node
= cpu_to_node(cpu
);
3789 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3792 vmcs
= page_address(pages
);
3793 memset(vmcs
, 0, vmcs_config
.size
);
3794 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3798 static struct vmcs
*alloc_vmcs(void)
3800 return alloc_vmcs_cpu(raw_smp_processor_id());
3803 static void free_vmcs(struct vmcs
*vmcs
)
3805 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3809 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3811 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3813 if (!loaded_vmcs
->vmcs
)
3815 loaded_vmcs_clear(loaded_vmcs
);
3816 free_vmcs(loaded_vmcs
->vmcs
);
3817 loaded_vmcs
->vmcs
= NULL
;
3818 WARN_ON(loaded_vmcs
->shadow_vmcs
!= NULL
);
3821 static void free_kvm_area(void)
3825 for_each_possible_cpu(cpu
) {
3826 free_vmcs(per_cpu(vmxarea
, cpu
));
3827 per_cpu(vmxarea
, cpu
) = NULL
;
3831 enum vmcs_field_type
{
3832 VMCS_FIELD_TYPE_U16
= 0,
3833 VMCS_FIELD_TYPE_U64
= 1,
3834 VMCS_FIELD_TYPE_U32
= 2,
3835 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
3838 static inline int vmcs_field_type(unsigned long field
)
3840 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
3841 return VMCS_FIELD_TYPE_U32
;
3842 return (field
>> 13) & 0x3 ;
3845 static inline int vmcs_field_readonly(unsigned long field
)
3847 return (((field
>> 10) & 0x3) == 1);
3850 static void init_vmcs_shadow_fields(void)
3854 /* No checks for read only fields yet */
3856 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3857 switch (shadow_read_write_fields
[i
]) {
3859 if (!kvm_mpx_supported())
3867 shadow_read_write_fields
[j
] =
3868 shadow_read_write_fields
[i
];
3871 max_shadow_read_write_fields
= j
;
3873 /* shadowed fields guest access without vmexit */
3874 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3875 unsigned long field
= shadow_read_write_fields
[i
];
3877 clear_bit(field
, vmx_vmwrite_bitmap
);
3878 clear_bit(field
, vmx_vmread_bitmap
);
3879 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
) {
3880 clear_bit(field
+ 1, vmx_vmwrite_bitmap
);
3881 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3884 for (i
= 0; i
< max_shadow_read_only_fields
; i
++) {
3885 unsigned long field
= shadow_read_only_fields
[i
];
3887 clear_bit(field
, vmx_vmread_bitmap
);
3888 if (vmcs_field_type(field
) == VMCS_FIELD_TYPE_U64
)
3889 clear_bit(field
+ 1, vmx_vmread_bitmap
);
3893 static __init
int alloc_kvm_area(void)
3897 for_each_possible_cpu(cpu
) {
3900 vmcs
= alloc_vmcs_cpu(cpu
);
3906 per_cpu(vmxarea
, cpu
) = vmcs
;
3911 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3912 struct kvm_segment
*save
)
3914 if (!emulate_invalid_guest_state
) {
3916 * CS and SS RPL should be equal during guest entry according
3917 * to VMX spec, but in reality it is not always so. Since vcpu
3918 * is in the middle of the transition from real mode to
3919 * protected mode it is safe to assume that RPL 0 is a good
3922 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3923 save
->selector
&= ~SEGMENT_RPL_MASK
;
3924 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3927 vmx_set_segment(vcpu
, save
, seg
);
3930 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3932 unsigned long flags
;
3933 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3936 * Update real mode segment cache. It may be not up-to-date if sement
3937 * register was written while vcpu was in a guest mode.
3939 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3940 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3941 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3942 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3943 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3944 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3946 vmx
->rmode
.vm86_active
= 0;
3948 vmx_segment_cache_clear(vmx
);
3950 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3952 flags
= vmcs_readl(GUEST_RFLAGS
);
3953 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3954 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3955 vmcs_writel(GUEST_RFLAGS
, flags
);
3957 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3958 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3960 update_exception_bitmap(vcpu
);
3962 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3963 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3964 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3965 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3966 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3967 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3970 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3972 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3973 struct kvm_segment var
= *save
;
3976 if (seg
== VCPU_SREG_CS
)
3979 if (!emulate_invalid_guest_state
) {
3980 var
.selector
= var
.base
>> 4;
3981 var
.base
= var
.base
& 0xffff0;
3991 if (save
->base
& 0xf)
3992 printk_once(KERN_WARNING
"kvm: segment base is not "
3993 "paragraph aligned when entering "
3994 "protected mode (seg=%d)", seg
);
3997 vmcs_write16(sf
->selector
, var
.selector
);
3998 vmcs_writel(sf
->base
, var
.base
);
3999 vmcs_write32(sf
->limit
, var
.limit
);
4000 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
4003 static void enter_rmode(struct kvm_vcpu
*vcpu
)
4005 unsigned long flags
;
4006 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4008 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
4009 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
4010 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
4011 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
4012 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
4013 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
4014 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
4016 vmx
->rmode
.vm86_active
= 1;
4019 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4020 * vcpu. Warn the user that an update is overdue.
4022 if (!vcpu
->kvm
->arch
.tss_addr
)
4023 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
4024 "called before entering vcpu\n");
4026 vmx_segment_cache_clear(vmx
);
4028 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
4029 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
4030 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4032 flags
= vmcs_readl(GUEST_RFLAGS
);
4033 vmx
->rmode
.save_rflags
= flags
;
4035 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
4037 vmcs_writel(GUEST_RFLAGS
, flags
);
4038 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
4039 update_exception_bitmap(vcpu
);
4041 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
4042 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
4043 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
4044 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
4045 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
4046 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
4048 kvm_mmu_reset_context(vcpu
);
4051 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
4053 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4054 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
4060 * Force kernel_gs_base reloading before EFER changes, as control
4061 * of this msr depends on is_long_mode().
4063 vmx_load_host_state(to_vmx(vcpu
));
4064 vcpu
->arch
.efer
= efer
;
4065 if (efer
& EFER_LMA
) {
4066 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4069 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4071 msr
->data
= efer
& ~EFER_LME
;
4076 #ifdef CONFIG_X86_64
4078 static void enter_lmode(struct kvm_vcpu
*vcpu
)
4082 vmx_segment_cache_clear(to_vmx(vcpu
));
4084 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
4085 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
4086 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
4088 vmcs_write32(GUEST_TR_AR_BYTES
,
4089 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
4090 | VMX_AR_TYPE_BUSY_64_TSS
);
4092 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
4095 static void exit_lmode(struct kvm_vcpu
*vcpu
)
4097 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
4098 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
4103 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
4106 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
4108 ept_sync_context(construct_eptp(vcpu
, vcpu
->arch
.mmu
.root_hpa
));
4110 vpid_sync_context(vpid
);
4114 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
4116 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
4119 static void vmx_flush_tlb_ept_only(struct kvm_vcpu
*vcpu
)
4122 vmx_flush_tlb(vcpu
);
4125 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
4127 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
4129 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
4130 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
4133 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
4135 if (enable_ept
&& is_paging(vcpu
))
4136 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
4137 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
4140 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
4142 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
4144 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
4145 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
4148 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
4150 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4152 if (!test_bit(VCPU_EXREG_PDPTR
,
4153 (unsigned long *)&vcpu
->arch
.regs_dirty
))
4156 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4157 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
4158 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
4159 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
4160 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
4164 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
4166 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
4168 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
4169 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
4170 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
4171 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
4172 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
4175 __set_bit(VCPU_EXREG_PDPTR
,
4176 (unsigned long *)&vcpu
->arch
.regs_avail
);
4177 __set_bit(VCPU_EXREG_PDPTR
,
4178 (unsigned long *)&vcpu
->arch
.regs_dirty
);
4181 static bool nested_guest_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4183 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4184 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4185 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4187 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
4188 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4189 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4190 fixed0
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4192 return fixed_bits_valid(val
, fixed0
, fixed1
);
4195 static bool nested_host_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4197 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed0
;
4198 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr0_fixed1
;
4200 return fixed_bits_valid(val
, fixed0
, fixed1
);
4203 static bool nested_cr4_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
4205 u64 fixed0
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed0
;
4206 u64 fixed1
= to_vmx(vcpu
)->nested
.nested_vmx_cr4_fixed1
;
4208 return fixed_bits_valid(val
, fixed0
, fixed1
);
4211 /* No difference in the restrictions on guest and host CR4 in VMX operation. */
4212 #define nested_guest_cr4_valid nested_cr4_valid
4213 #define nested_host_cr4_valid nested_cr4_valid
4215 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
4217 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
4219 struct kvm_vcpu
*vcpu
)
4221 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
4222 vmx_decache_cr3(vcpu
);
4223 if (!(cr0
& X86_CR0_PG
)) {
4224 /* From paging/starting to nonpaging */
4225 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4226 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
4227 (CPU_BASED_CR3_LOAD_EXITING
|
4228 CPU_BASED_CR3_STORE_EXITING
));
4229 vcpu
->arch
.cr0
= cr0
;
4230 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4231 } else if (!is_paging(vcpu
)) {
4232 /* From nonpaging to paging */
4233 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
4234 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
4235 ~(CPU_BASED_CR3_LOAD_EXITING
|
4236 CPU_BASED_CR3_STORE_EXITING
));
4237 vcpu
->arch
.cr0
= cr0
;
4238 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
4241 if (!(cr0
& X86_CR0_WP
))
4242 *hw_cr0
&= ~X86_CR0_WP
;
4245 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
4247 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4248 unsigned long hw_cr0
;
4250 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
4251 if (enable_unrestricted_guest
)
4252 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
4254 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
4256 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
4259 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
4263 #ifdef CONFIG_X86_64
4264 if (vcpu
->arch
.efer
& EFER_LME
) {
4265 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
4267 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
4273 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
4275 vmcs_writel(CR0_READ_SHADOW
, cr0
);
4276 vmcs_writel(GUEST_CR0
, hw_cr0
);
4277 vcpu
->arch
.cr0
= cr0
;
4279 /* depends on vcpu->arch.cr0 to be set to a new value */
4280 vmx
->emulation_required
= emulation_required(vcpu
);
4283 static u64
construct_eptp(struct kvm_vcpu
*vcpu
, unsigned long root_hpa
)
4287 /* TODO write the value reading from MSR */
4288 eptp
= VMX_EPT_DEFAULT_MT
|
4289 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
4290 if (enable_ept_ad_bits
&&
4291 (!is_guest_mode(vcpu
) || nested_ept_ad_enabled(vcpu
)))
4292 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
4293 eptp
|= (root_hpa
& PAGE_MASK
);
4298 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
4300 unsigned long guest_cr3
;
4305 eptp
= construct_eptp(vcpu
, cr3
);
4306 vmcs_write64(EPT_POINTER
, eptp
);
4307 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
4308 guest_cr3
= kvm_read_cr3(vcpu
);
4310 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
4311 ept_load_pdptrs(vcpu
);
4314 vmx_flush_tlb(vcpu
);
4315 vmcs_writel(GUEST_CR3
, guest_cr3
);
4318 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
4321 * Pass through host's Machine Check Enable value to hw_cr4, which
4322 * is in force while we are in guest mode. Do not let guests control
4323 * this bit, even if host CR4.MCE == 0.
4325 unsigned long hw_cr4
=
4326 (cr4_read_shadow() & X86_CR4_MCE
) |
4327 (cr4
& ~X86_CR4_MCE
) |
4328 (to_vmx(vcpu
)->rmode
.vm86_active
?
4329 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
4331 if (cr4
& X86_CR4_VMXE
) {
4333 * To use VMXON (and later other VMX instructions), a guest
4334 * must first be able to turn on cr4.VMXE (see handle_vmon()).
4335 * So basically the check on whether to allow nested VMX
4338 if (!nested_vmx_allowed(vcpu
))
4342 if (to_vmx(vcpu
)->nested
.vmxon
&& !nested_cr4_valid(vcpu
, cr4
))
4345 vcpu
->arch
.cr4
= cr4
;
4347 if (!is_paging(vcpu
)) {
4348 hw_cr4
&= ~X86_CR4_PAE
;
4349 hw_cr4
|= X86_CR4_PSE
;
4350 } else if (!(cr4
& X86_CR4_PAE
)) {
4351 hw_cr4
&= ~X86_CR4_PAE
;
4355 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
4357 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
4358 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
4359 * to be manually disabled when guest switches to non-paging
4362 * If !enable_unrestricted_guest, the CPU is always running
4363 * with CR0.PG=1 and CR4 needs to be modified.
4364 * If enable_unrestricted_guest, the CPU automatically
4365 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
4367 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
| X86_CR4_PKE
);
4369 vmcs_writel(CR4_READ_SHADOW
, cr4
);
4370 vmcs_writel(GUEST_CR4
, hw_cr4
);
4374 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
4375 struct kvm_segment
*var
, int seg
)
4377 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4380 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4381 *var
= vmx
->rmode
.segs
[seg
];
4382 if (seg
== VCPU_SREG_TR
4383 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
4385 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4386 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4389 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
4390 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
4391 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
4392 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
4393 var
->unusable
= (ar
>> 16) & 1;
4394 var
->type
= ar
& 15;
4395 var
->s
= (ar
>> 4) & 1;
4396 var
->dpl
= (ar
>> 5) & 3;
4398 * Some userspaces do not preserve unusable property. Since usable
4399 * segment has to be present according to VMX spec we can use present
4400 * property to amend userspace bug by making unusable segment always
4401 * nonpresent. vmx_segment_access_rights() already marks nonpresent
4402 * segment as unusable.
4404 var
->present
= !var
->unusable
;
4405 var
->avl
= (ar
>> 12) & 1;
4406 var
->l
= (ar
>> 13) & 1;
4407 var
->db
= (ar
>> 14) & 1;
4408 var
->g
= (ar
>> 15) & 1;
4411 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
4413 struct kvm_segment s
;
4415 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
4416 vmx_get_segment(vcpu
, &s
, seg
);
4419 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
4422 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
4424 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4426 if (unlikely(vmx
->rmode
.vm86_active
))
4429 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
4430 return VMX_AR_DPL(ar
);
4434 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
4438 if (var
->unusable
|| !var
->present
)
4441 ar
= var
->type
& 15;
4442 ar
|= (var
->s
& 1) << 4;
4443 ar
|= (var
->dpl
& 3) << 5;
4444 ar
|= (var
->present
& 1) << 7;
4445 ar
|= (var
->avl
& 1) << 12;
4446 ar
|= (var
->l
& 1) << 13;
4447 ar
|= (var
->db
& 1) << 14;
4448 ar
|= (var
->g
& 1) << 15;
4454 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
4455 struct kvm_segment
*var
, int seg
)
4457 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4458 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4460 vmx_segment_cache_clear(vmx
);
4462 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
4463 vmx
->rmode
.segs
[seg
] = *var
;
4464 if (seg
== VCPU_SREG_TR
)
4465 vmcs_write16(sf
->selector
, var
->selector
);
4467 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
4471 vmcs_writel(sf
->base
, var
->base
);
4472 vmcs_write32(sf
->limit
, var
->limit
);
4473 vmcs_write16(sf
->selector
, var
->selector
);
4476 * Fix the "Accessed" bit in AR field of segment registers for older
4478 * IA32 arch specifies that at the time of processor reset the
4479 * "Accessed" bit in the AR field of segment registers is 1. And qemu
4480 * is setting it to 0 in the userland code. This causes invalid guest
4481 * state vmexit when "unrestricted guest" mode is turned on.
4482 * Fix for this setup issue in cpu_reset is being pushed in the qemu
4483 * tree. Newer qemu binaries with that qemu fix would not need this
4486 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
4487 var
->type
|= 0x1; /* Accessed */
4489 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4492 vmx
->emulation_required
= emulation_required(vcpu
);
4495 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4497 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4499 *db
= (ar
>> 14) & 1;
4500 *l
= (ar
>> 13) & 1;
4503 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4505 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4506 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4509 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4511 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4512 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4515 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4517 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4518 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4521 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4523 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4524 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4527 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4529 struct kvm_segment var
;
4532 vmx_get_segment(vcpu
, &var
, seg
);
4534 if (seg
== VCPU_SREG_CS
)
4536 ar
= vmx_segment_access_rights(&var
);
4538 if (var
.base
!= (var
.selector
<< 4))
4540 if (var
.limit
!= 0xffff)
4548 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4550 struct kvm_segment cs
;
4551 unsigned int cs_rpl
;
4553 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4554 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4558 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4562 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4563 if (cs
.dpl
> cs_rpl
)
4566 if (cs
.dpl
!= cs_rpl
)
4572 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4576 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4578 struct kvm_segment ss
;
4579 unsigned int ss_rpl
;
4581 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4582 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4586 if (ss
.type
!= 3 && ss
.type
!= 7)
4590 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4598 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4600 struct kvm_segment var
;
4603 vmx_get_segment(vcpu
, &var
, seg
);
4604 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4612 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4613 if (var
.dpl
< rpl
) /* DPL < RPL */
4617 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4623 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4625 struct kvm_segment tr
;
4627 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4631 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4633 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4641 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4643 struct kvm_segment ldtr
;
4645 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4649 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4659 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4661 struct kvm_segment cs
, ss
;
4663 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4664 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4666 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4667 (ss
.selector
& SEGMENT_RPL_MASK
));
4671 * Check if guest state is valid. Returns true if valid, false if
4673 * We assume that registers are always usable
4675 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4677 if (enable_unrestricted_guest
)
4680 /* real mode guest state checks */
4681 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4682 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4684 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4686 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4688 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4690 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4692 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4695 /* protected mode guest state checks */
4696 if (!cs_ss_rpl_check(vcpu
))
4698 if (!code_segment_valid(vcpu
))
4700 if (!stack_segment_valid(vcpu
))
4702 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4704 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4706 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4708 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4710 if (!tr_valid(vcpu
))
4712 if (!ldtr_valid(vcpu
))
4716 * - Add checks on RIP
4717 * - Add checks on RFLAGS
4723 static bool page_address_valid(struct kvm_vcpu
*vcpu
, gpa_t gpa
)
4725 return PAGE_ALIGNED(gpa
) && !(gpa
>> cpuid_maxphyaddr(vcpu
));
4728 static int init_rmode_tss(struct kvm
*kvm
)
4734 idx
= srcu_read_lock(&kvm
->srcu
);
4735 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4736 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4739 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4740 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4741 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4744 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4747 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4751 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4752 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4755 srcu_read_unlock(&kvm
->srcu
, idx
);
4759 static int init_rmode_identity_map(struct kvm
*kvm
)
4762 kvm_pfn_t identity_map_pfn
;
4768 /* Protect kvm->arch.ept_identity_pagetable_done. */
4769 mutex_lock(&kvm
->slots_lock
);
4771 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4774 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4776 r
= alloc_identity_pagetable(kvm
);
4780 idx
= srcu_read_lock(&kvm
->srcu
);
4781 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4784 /* Set up identity-mapping pagetable for EPT in real mode */
4785 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4786 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4787 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4788 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4789 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4793 kvm
->arch
.ept_identity_pagetable_done
= true;
4796 srcu_read_unlock(&kvm
->srcu
, idx
);
4799 mutex_unlock(&kvm
->slots_lock
);
4803 static void seg_setup(int seg
)
4805 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4808 vmcs_write16(sf
->selector
, 0);
4809 vmcs_writel(sf
->base
, 0);
4810 vmcs_write32(sf
->limit
, 0xffff);
4812 if (seg
== VCPU_SREG_CS
)
4813 ar
|= 0x08; /* code segment */
4815 vmcs_write32(sf
->ar_bytes
, ar
);
4818 static int alloc_apic_access_page(struct kvm
*kvm
)
4823 mutex_lock(&kvm
->slots_lock
);
4824 if (kvm
->arch
.apic_access_page_done
)
4826 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4827 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4831 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4832 if (is_error_page(page
)) {
4838 * Do not pin the page in memory, so that memory hot-unplug
4839 * is able to migrate it.
4842 kvm
->arch
.apic_access_page_done
= true;
4844 mutex_unlock(&kvm
->slots_lock
);
4848 static int alloc_identity_pagetable(struct kvm
*kvm
)
4850 /* Called with kvm->slots_lock held. */
4854 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4856 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4857 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4862 static int allocate_vpid(void)
4868 spin_lock(&vmx_vpid_lock
);
4869 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4870 if (vpid
< VMX_NR_VPIDS
)
4871 __set_bit(vpid
, vmx_vpid_bitmap
);
4874 spin_unlock(&vmx_vpid_lock
);
4878 static void free_vpid(int vpid
)
4880 if (!enable_vpid
|| vpid
== 0)
4882 spin_lock(&vmx_vpid_lock
);
4883 __clear_bit(vpid
, vmx_vpid_bitmap
);
4884 spin_unlock(&vmx_vpid_lock
);
4887 #define MSR_TYPE_R 1
4888 #define MSR_TYPE_W 2
4889 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4892 int f
= sizeof(unsigned long);
4894 if (!cpu_has_vmx_msr_bitmap())
4898 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4899 * have the write-low and read-high bitmap offsets the wrong way round.
4900 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4902 if (msr
<= 0x1fff) {
4903 if (type
& MSR_TYPE_R
)
4905 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4907 if (type
& MSR_TYPE_W
)
4909 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4911 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4913 if (type
& MSR_TYPE_R
)
4915 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4917 if (type
& MSR_TYPE_W
)
4919 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4925 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4926 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4928 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4929 unsigned long *msr_bitmap_nested
,
4932 int f
= sizeof(unsigned long);
4934 if (!cpu_has_vmx_msr_bitmap()) {
4940 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4941 * have the write-low and read-high bitmap offsets the wrong way round.
4942 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4944 if (msr
<= 0x1fff) {
4945 if (type
& MSR_TYPE_R
&&
4946 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4948 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4950 if (type
& MSR_TYPE_W
&&
4951 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4953 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4955 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4957 if (type
& MSR_TYPE_R
&&
4958 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4960 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4962 if (type
& MSR_TYPE_W
&&
4963 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4965 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4970 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4973 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4974 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4975 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4976 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4979 static void vmx_disable_intercept_msr_x2apic(u32 msr
, int type
, bool apicv_active
)
4982 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic_apicv
,
4984 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic_apicv
,
4987 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4989 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4994 static bool vmx_get_enable_apicv(void)
4996 return enable_apicv
;
4999 static void nested_mark_vmcs12_pages_dirty(struct kvm_vcpu
*vcpu
)
5001 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5005 * Don't need to mark the APIC access page dirty; it is never
5006 * written to by the CPU during APIC virtualization.
5009 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
5010 gfn
= vmcs12
->virtual_apic_page_addr
>> PAGE_SHIFT
;
5011 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5014 if (nested_cpu_has_posted_intr(vmcs12
)) {
5015 gfn
= vmcs12
->posted_intr_desc_addr
>> PAGE_SHIFT
;
5016 kvm_vcpu_mark_page_dirty(vcpu
, gfn
);
5021 static void vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
5023 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5028 if (!vmx
->nested
.pi_desc
|| !vmx
->nested
.pi_pending
)
5031 vmx
->nested
.pi_pending
= false;
5032 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
5035 max_irr
= find_last_bit((unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
5036 if (max_irr
!= 256) {
5037 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
5038 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
5039 kunmap(vmx
->nested
.virtual_apic_page
);
5041 status
= vmcs_read16(GUEST_INTR_STATUS
);
5042 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
5044 status
|= (u8
)max_irr
;
5045 vmcs_write16(GUEST_INTR_STATUS
, status
);
5049 nested_mark_vmcs12_pages_dirty(vcpu
);
5052 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
,
5056 int pi_vec
= nested
? POSTED_INTR_NESTED_VECTOR
: POSTED_INTR_VECTOR
;
5058 if (vcpu
->mode
== IN_GUEST_MODE
) {
5060 * The vector of interrupt to be delivered to vcpu had
5061 * been set in PIR before this function.
5063 * Following cases will be reached in this block, and
5064 * we always send a notification event in all cases as
5067 * Case 1: vcpu keeps in non-root mode. Sending a
5068 * notification event posts the interrupt to vcpu.
5070 * Case 2: vcpu exits to root mode and is still
5071 * runnable. PIR will be synced to vIRR before the
5072 * next vcpu entry. Sending a notification event in
5073 * this case has no effect, as vcpu is not in root
5076 * Case 3: vcpu exits to root mode and is blocked.
5077 * vcpu_block() has already synced PIR to vIRR and
5078 * never blocks vcpu if vIRR is not cleared. Therefore,
5079 * a blocked vcpu here does not wait for any requested
5080 * interrupts in PIR, and sending a notification event
5081 * which has no effect is safe here.
5084 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
), pi_vec
);
5091 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
5094 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5096 if (is_guest_mode(vcpu
) &&
5097 vector
== vmx
->nested
.posted_intr_nv
) {
5098 /* the PIR and ON have been set by L1. */
5099 kvm_vcpu_trigger_posted_interrupt(vcpu
, true);
5101 * If a posted intr is not recognized by hardware,
5102 * we will accomplish it in the next vmentry.
5104 vmx
->nested
.pi_pending
= true;
5105 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5111 * Send interrupt to vcpu via posted interrupt way.
5112 * 1. If target vcpu is running(non-root mode), send posted interrupt
5113 * notification to vcpu and hardware will sync PIR to vIRR atomically.
5114 * 2. If target vcpu isn't running(root mode), kick it to pick up the
5115 * interrupt from PIR in next vmentry.
5117 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
5119 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5122 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
5126 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
5129 /* If a previous notification has sent the IPI, nothing to do. */
5130 if (pi_test_and_set_on(&vmx
->pi_desc
))
5133 if (!kvm_vcpu_trigger_posted_interrupt(vcpu
, false))
5134 kvm_vcpu_kick(vcpu
);
5138 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
5139 * will not change in the lifetime of the guest.
5140 * Note that host-state that does change is set elsewhere. E.g., host-state
5141 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
5143 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
5148 unsigned long cr0
, cr3
, cr4
;
5151 WARN_ON(cr0
& X86_CR0_TS
);
5152 vmcs_writel(HOST_CR0
, cr0
); /* 22.2.3 */
5155 * Save the most likely value for this task's CR3 in the VMCS.
5156 * We can't use __get_current_cr3_fast() because we're not atomic.
5159 vmcs_writel(HOST_CR3
, cr3
); /* 22.2.3 FIXME: shadow tables */
5160 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
5162 /* Save the most likely value for this task's CR4 in the VMCS. */
5163 cr4
= cr4_read_shadow();
5164 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
5165 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
5167 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
5168 #ifdef CONFIG_X86_64
5170 * Load null selectors, so we can avoid reloading them in
5171 * __vmx_load_host_state(), in case userspace uses the null selectors
5172 * too (the expected case).
5174 vmcs_write16(HOST_DS_SELECTOR
, 0);
5175 vmcs_write16(HOST_ES_SELECTOR
, 0);
5177 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5178 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5180 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
5181 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
5184 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
5185 vmx
->host_idt_base
= dt
.address
;
5187 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
5189 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
5190 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
5191 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
5192 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
5194 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
5195 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
5196 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
5200 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
5202 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
5204 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
5205 if (is_guest_mode(&vmx
->vcpu
))
5206 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
5207 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
5208 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
5211 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
5213 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
5215 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5216 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
5217 /* Enable the preemption timer dynamically */
5218 pin_based_exec_ctrl
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
5219 return pin_based_exec_ctrl
;
5222 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
5224 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5226 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5227 if (cpu_has_secondary_exec_ctrls()) {
5228 if (kvm_vcpu_apicv_active(vcpu
))
5229 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
5230 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5231 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5233 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
5234 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5235 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5238 if (cpu_has_vmx_msr_bitmap())
5239 vmx_set_msr_bitmap(vcpu
);
5242 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
5244 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
5246 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
5247 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5249 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
5250 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
5251 #ifdef CONFIG_X86_64
5252 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
5253 CPU_BASED_CR8_LOAD_EXITING
;
5257 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
5258 CPU_BASED_CR3_LOAD_EXITING
|
5259 CPU_BASED_INVLPG_EXITING
;
5260 return exec_control
;
5263 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
5265 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
5266 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
5267 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
5269 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
5271 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
5272 enable_unrestricted_guest
= 0;
5273 /* Enable INVPCID for non-ept guests may cause performance regression. */
5274 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
5276 if (!enable_unrestricted_guest
)
5277 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
5279 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
5280 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
5281 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
5282 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
5283 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
5284 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
5286 We can NOT enable shadow_vmcs here because we don't have yet
5289 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
5292 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
5294 return exec_control
;
5297 static void ept_set_mmio_spte_mask(void)
5300 * EPT Misconfigurations can be generated if the value of bits 2:0
5301 * of an EPT paging-structure entry is 110b (write/execute).
5303 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK
,
5304 VMX_EPT_MISCONFIG_WX_VALUE
);
5307 #define VMX_XSS_EXIT_BITMAP 0
5309 * Sets up the vmcs for emulated real mode.
5311 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
5313 #ifdef CONFIG_X86_64
5319 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
5320 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
5322 if (enable_shadow_vmcs
) {
5323 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
5324 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
5326 if (cpu_has_vmx_msr_bitmap())
5327 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
5329 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
5332 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
5333 vmx
->hv_deadline_tsc
= -1;
5335 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
5337 if (cpu_has_secondary_exec_ctrls()) {
5338 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5339 vmx_secondary_exec_control(vmx
));
5342 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
5343 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
5344 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
5345 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
5346 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
5348 vmcs_write16(GUEST_INTR_STATUS
, 0);
5350 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
5351 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
5355 vmcs_write32(PLE_GAP
, ple_gap
);
5356 vmx
->ple_window
= ple_window
;
5357 vmx
->ple_window_dirty
= true;
5360 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
5361 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
5362 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
5364 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
5365 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
5366 vmx_set_constant_host_state(vmx
);
5367 #ifdef CONFIG_X86_64
5368 rdmsrl(MSR_FS_BASE
, a
);
5369 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
5370 rdmsrl(MSR_GS_BASE
, a
);
5371 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
5373 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
5374 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
5377 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
5378 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
5379 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
5380 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
5381 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
5383 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
5384 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
5386 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
5387 u32 index
= vmx_msr_index
[i
];
5388 u32 data_low
, data_high
;
5391 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
5393 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
5395 vmx
->guest_msrs
[j
].index
= i
;
5396 vmx
->guest_msrs
[j
].data
= 0;
5397 vmx
->guest_msrs
[j
].mask
= -1ull;
5402 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
5404 /* 22.2.1, 20.8.1 */
5405 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
5407 vmx
->vcpu
.arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
5408 vmcs_writel(CR0_GUEST_HOST_MASK
, ~X86_CR0_TS
);
5410 set_cr4_guest_host_mask(vmx
);
5412 if (vmx_xsaves_supported())
5413 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
5416 ASSERT(vmx
->pml_pg
);
5417 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
5418 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
5424 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
5426 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5427 struct msr_data apic_base_msr
;
5430 vmx
->rmode
.vm86_active
= 0;
5432 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
5433 kvm_set_cr8(vcpu
, 0);
5436 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
5437 MSR_IA32_APICBASE_ENABLE
;
5438 if (kvm_vcpu_is_reset_bsp(vcpu
))
5439 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
5440 apic_base_msr
.host_initiated
= true;
5441 kvm_set_apic_base(vcpu
, &apic_base_msr
);
5444 vmx_segment_cache_clear(vmx
);
5446 seg_setup(VCPU_SREG_CS
);
5447 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
5448 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
5450 seg_setup(VCPU_SREG_DS
);
5451 seg_setup(VCPU_SREG_ES
);
5452 seg_setup(VCPU_SREG_FS
);
5453 seg_setup(VCPU_SREG_GS
);
5454 seg_setup(VCPU_SREG_SS
);
5456 vmcs_write16(GUEST_TR_SELECTOR
, 0);
5457 vmcs_writel(GUEST_TR_BASE
, 0);
5458 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
5459 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
5461 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
5462 vmcs_writel(GUEST_LDTR_BASE
, 0);
5463 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
5464 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
5467 vmcs_write32(GUEST_SYSENTER_CS
, 0);
5468 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
5469 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
5470 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
5473 vmcs_writel(GUEST_RFLAGS
, 0x02);
5474 kvm_rip_write(vcpu
, 0xfff0);
5476 vmcs_writel(GUEST_GDTR_BASE
, 0);
5477 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
5479 vmcs_writel(GUEST_IDTR_BASE
, 0);
5480 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
5482 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
5483 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
5484 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
5488 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
5490 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
5491 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
5492 if (cpu_need_tpr_shadow(vcpu
))
5493 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
5494 __pa(vcpu
->arch
.apic
->regs
));
5495 vmcs_write32(TPR_THRESHOLD
, 0);
5498 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5500 if (kvm_vcpu_apicv_active(vcpu
))
5501 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5504 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5506 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5507 vmx
->vcpu
.arch
.cr0
= cr0
;
5508 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5509 vmx_set_cr4(vcpu
, 0);
5510 vmx_set_efer(vcpu
, 0);
5512 update_exception_bitmap(vcpu
);
5514 vpid_sync_context(vmx
->vpid
);
5518 * In nested virtualization, check if L1 asked to exit on external interrupts.
5519 * For most existing hypervisors, this will always return true.
5521 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5523 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5524 PIN_BASED_EXT_INTR_MASK
;
5528 * In nested virtualization, check if L1 has set
5529 * VM_EXIT_ACK_INTR_ON_EXIT
5531 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5533 return get_vmcs12(vcpu
)->vm_exit_controls
&
5534 VM_EXIT_ACK_INTR_ON_EXIT
;
5537 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5539 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5540 PIN_BASED_NMI_EXITING
;
5543 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5545 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5546 CPU_BASED_VIRTUAL_INTR_PENDING
);
5549 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5551 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5552 enable_irq_window(vcpu
);
5556 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
,
5557 CPU_BASED_VIRTUAL_NMI_PENDING
);
5560 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5562 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5564 int irq
= vcpu
->arch
.interrupt
.nr
;
5566 trace_kvm_inj_virq(irq
);
5568 ++vcpu
->stat
.irq_injections
;
5569 if (vmx
->rmode
.vm86_active
) {
5571 if (vcpu
->arch
.interrupt
.soft
)
5572 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5573 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5574 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5577 intr
= irq
| INTR_INFO_VALID_MASK
;
5578 if (vcpu
->arch
.interrupt
.soft
) {
5579 intr
|= INTR_TYPE_SOFT_INTR
;
5580 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5581 vmx
->vcpu
.arch
.event_exit_inst_len
);
5583 intr
|= INTR_TYPE_EXT_INTR
;
5584 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5587 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5589 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5591 ++vcpu
->stat
.nmi_injections
;
5592 vmx
->loaded_vmcs
->nmi_known_unmasked
= false;
5594 if (vmx
->rmode
.vm86_active
) {
5595 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5596 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5600 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5601 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5604 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5606 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5609 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
5611 masked
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5612 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5616 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5618 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5620 vmx
->loaded_vmcs
->nmi_known_unmasked
= !masked
;
5622 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5623 GUEST_INTR_STATE_NMI
);
5625 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5626 GUEST_INTR_STATE_NMI
);
5629 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5631 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5634 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5635 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5636 | GUEST_INTR_STATE_NMI
));
5639 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5641 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5642 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5643 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5644 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5647 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5651 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5655 kvm
->arch
.tss_addr
= addr
;
5656 return init_rmode_tss(kvm
);
5659 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5664 * Update instruction length as we may reinject the exception
5665 * from user space while in guest debugging mode.
5667 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5668 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5669 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5673 if (vcpu
->guest_debug
&
5674 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5691 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5692 int vec
, u32 err_code
)
5695 * Instruction with address size override prefix opcode 0x67
5696 * Cause the #SS fault with 0 error code in VM86 mode.
5698 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5699 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5700 if (vcpu
->arch
.halt_request
) {
5701 vcpu
->arch
.halt_request
= 0;
5702 return kvm_vcpu_halt(vcpu
);
5710 * Forward all other exceptions that are valid in real mode.
5711 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5712 * the required debugging infrastructure rework.
5714 kvm_queue_exception(vcpu
, vec
);
5719 * Trigger machine check on the host. We assume all the MSRs are already set up
5720 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5721 * We pass a fake environment to the machine check handler because we want
5722 * the guest to be always treated like user space, no matter what context
5723 * it used internally.
5725 static void kvm_machine_check(void)
5727 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5728 struct pt_regs regs
= {
5729 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5730 .flags
= X86_EFLAGS_IF
,
5733 do_machine_check(®s
, 0);
5737 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5739 /* already handled by vcpu_run */
5743 static int handle_exception(struct kvm_vcpu
*vcpu
)
5745 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5746 struct kvm_run
*kvm_run
= vcpu
->run
;
5747 u32 intr_info
, ex_no
, error_code
;
5748 unsigned long cr2
, rip
, dr6
;
5750 enum emulation_result er
;
5752 vect_info
= vmx
->idt_vectoring_info
;
5753 intr_info
= vmx
->exit_intr_info
;
5755 if (is_machine_check(intr_info
))
5756 return handle_machine_check(vcpu
);
5758 if (is_nmi(intr_info
))
5759 return 1; /* already handled by vmx_vcpu_run() */
5761 if (is_invalid_opcode(intr_info
)) {
5762 if (is_guest_mode(vcpu
)) {
5763 kvm_queue_exception(vcpu
, UD_VECTOR
);
5766 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5767 if (er
!= EMULATE_DONE
)
5768 kvm_queue_exception(vcpu
, UD_VECTOR
);
5773 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5774 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5777 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5778 * MMIO, it is better to report an internal error.
5779 * See the comments in vmx_handle_exit.
5781 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5782 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5783 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5784 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5785 vcpu
->run
->internal
.ndata
= 3;
5786 vcpu
->run
->internal
.data
[0] = vect_info
;
5787 vcpu
->run
->internal
.data
[1] = intr_info
;
5788 vcpu
->run
->internal
.data
[2] = error_code
;
5792 if (is_page_fault(intr_info
)) {
5793 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5794 /* EPT won't cause page fault directly */
5795 WARN_ON_ONCE(!vcpu
->arch
.apf
.host_apf_reason
&& enable_ept
);
5796 return kvm_handle_page_fault(vcpu
, error_code
, cr2
, NULL
, 0,
5800 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5802 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5803 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5807 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5810 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5811 if (!(vcpu
->guest_debug
&
5812 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5813 vcpu
->arch
.dr6
&= ~15;
5814 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5815 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5816 skip_emulated_instruction(vcpu
);
5818 kvm_queue_exception(vcpu
, DB_VECTOR
);
5821 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5822 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5826 * Update instruction length as we may reinject #BP from
5827 * user space while in guest debugging mode. Reading it for
5828 * #DB as well causes no harm, it is not used in that case.
5830 vmx
->vcpu
.arch
.event_exit_inst_len
=
5831 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5832 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5833 rip
= kvm_rip_read(vcpu
);
5834 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5835 kvm_run
->debug
.arch
.exception
= ex_no
;
5838 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5839 kvm_run
->ex
.exception
= ex_no
;
5840 kvm_run
->ex
.error_code
= error_code
;
5846 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5848 ++vcpu
->stat
.irq_exits
;
5852 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5854 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5858 static int handle_io(struct kvm_vcpu
*vcpu
)
5860 unsigned long exit_qualification
;
5861 int size
, in
, string
, ret
;
5864 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5865 string
= (exit_qualification
& 16) != 0;
5866 in
= (exit_qualification
& 8) != 0;
5868 ++vcpu
->stat
.io_exits
;
5871 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5873 port
= exit_qualification
>> 16;
5874 size
= (exit_qualification
& 7) + 1;
5876 ret
= kvm_skip_emulated_instruction(vcpu
);
5879 * TODO: we might be squashing a KVM_GUESTDBG_SINGLESTEP-triggered
5880 * KVM_EXIT_DEBUG here.
5882 return kvm_fast_pio_out(vcpu
, size
, port
) && ret
;
5886 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5889 * Patch in the VMCALL instruction:
5891 hypercall
[0] = 0x0f;
5892 hypercall
[1] = 0x01;
5893 hypercall
[2] = 0xc1;
5896 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5897 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5899 if (is_guest_mode(vcpu
)) {
5900 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5901 unsigned long orig_val
= val
;
5904 * We get here when L2 changed cr0 in a way that did not change
5905 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5906 * but did change L0 shadowed bits. So we first calculate the
5907 * effective cr0 value that L1 would like to write into the
5908 * hardware. It consists of the L2-owned bits from the new
5909 * value combined with the L1-owned bits from L1's guest_cr0.
5911 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5912 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5914 if (!nested_guest_cr0_valid(vcpu
, val
))
5917 if (kvm_set_cr0(vcpu
, val
))
5919 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5922 if (to_vmx(vcpu
)->nested
.vmxon
&&
5923 !nested_host_cr0_valid(vcpu
, val
))
5926 return kvm_set_cr0(vcpu
, val
);
5930 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5932 if (is_guest_mode(vcpu
)) {
5933 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5934 unsigned long orig_val
= val
;
5936 /* analogously to handle_set_cr0 */
5937 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5938 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5939 if (kvm_set_cr4(vcpu
, val
))
5941 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5944 return kvm_set_cr4(vcpu
, val
);
5947 static int handle_cr(struct kvm_vcpu
*vcpu
)
5949 unsigned long exit_qualification
, val
;
5955 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5956 cr
= exit_qualification
& 15;
5957 reg
= (exit_qualification
>> 8) & 15;
5958 switch ((exit_qualification
>> 4) & 3) {
5959 case 0: /* mov to cr */
5960 val
= kvm_register_readl(vcpu
, reg
);
5961 trace_kvm_cr_write(cr
, val
);
5964 err
= handle_set_cr0(vcpu
, val
);
5965 return kvm_complete_insn_gp(vcpu
, err
);
5967 err
= kvm_set_cr3(vcpu
, val
);
5968 return kvm_complete_insn_gp(vcpu
, err
);
5970 err
= handle_set_cr4(vcpu
, val
);
5971 return kvm_complete_insn_gp(vcpu
, err
);
5973 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5975 err
= kvm_set_cr8(vcpu
, cr8
);
5976 ret
= kvm_complete_insn_gp(vcpu
, err
);
5977 if (lapic_in_kernel(vcpu
))
5979 if (cr8_prev
<= cr8
)
5982 * TODO: we might be squashing a
5983 * KVM_GUESTDBG_SINGLESTEP-triggered
5984 * KVM_EXIT_DEBUG here.
5986 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5992 WARN_ONCE(1, "Guest should always own CR0.TS");
5993 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5994 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5995 return kvm_skip_emulated_instruction(vcpu
);
5996 case 1: /*mov from cr*/
5999 val
= kvm_read_cr3(vcpu
);
6000 kvm_register_write(vcpu
, reg
, val
);
6001 trace_kvm_cr_read(cr
, val
);
6002 return kvm_skip_emulated_instruction(vcpu
);
6004 val
= kvm_get_cr8(vcpu
);
6005 kvm_register_write(vcpu
, reg
, val
);
6006 trace_kvm_cr_read(cr
, val
);
6007 return kvm_skip_emulated_instruction(vcpu
);
6011 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
6012 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
6013 kvm_lmsw(vcpu
, val
);
6015 return kvm_skip_emulated_instruction(vcpu
);
6019 vcpu
->run
->exit_reason
= 0;
6020 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
6021 (int)(exit_qualification
>> 4) & 3, cr
);
6025 static int handle_dr(struct kvm_vcpu
*vcpu
)
6027 unsigned long exit_qualification
;
6030 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6031 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
6033 /* First, if DR does not exist, trigger UD */
6034 if (!kvm_require_dr(vcpu
, dr
))
6037 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
6038 if (!kvm_require_cpl(vcpu
, 0))
6040 dr7
= vmcs_readl(GUEST_DR7
);
6043 * As the vm-exit takes precedence over the debug trap, we
6044 * need to emulate the latter, either for the host or the
6045 * guest debugging itself.
6047 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
6048 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
6049 vcpu
->run
->debug
.arch
.dr7
= dr7
;
6050 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
6051 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
6052 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
6055 vcpu
->arch
.dr6
&= ~15;
6056 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
6057 kvm_queue_exception(vcpu
, DB_VECTOR
);
6062 if (vcpu
->guest_debug
== 0) {
6063 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6064 CPU_BASED_MOV_DR_EXITING
);
6067 * No more DR vmexits; force a reload of the debug registers
6068 * and reenter on this instruction. The next vmexit will
6069 * retrieve the full state of the debug registers.
6071 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
6075 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
6076 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
6079 if (kvm_get_dr(vcpu
, dr
, &val
))
6081 kvm_register_write(vcpu
, reg
, val
);
6083 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
6086 return kvm_skip_emulated_instruction(vcpu
);
6089 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
6091 return vcpu
->arch
.dr6
;
6094 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
6098 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
6100 get_debugreg(vcpu
->arch
.db
[0], 0);
6101 get_debugreg(vcpu
->arch
.db
[1], 1);
6102 get_debugreg(vcpu
->arch
.db
[2], 2);
6103 get_debugreg(vcpu
->arch
.db
[3], 3);
6104 get_debugreg(vcpu
->arch
.dr6
, 6);
6105 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
6107 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
6108 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL
, CPU_BASED_MOV_DR_EXITING
);
6111 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
6113 vmcs_writel(GUEST_DR7
, val
);
6116 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
6118 return kvm_emulate_cpuid(vcpu
);
6121 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
6123 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6124 struct msr_data msr_info
;
6126 msr_info
.index
= ecx
;
6127 msr_info
.host_initiated
= false;
6129 if (vmx_get_msr(vcpu
, &msr_info
)) {
6130 trace_kvm_msr_read_ex(ecx
);
6131 kvm_inject_gp(vcpu
, 0);
6135 trace_kvm_msr_read(ecx
, msr_info
.data
);
6137 /* FIXME: handling of bits 32:63 of rax, rdx */
6138 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
6139 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
6140 return kvm_skip_emulated_instruction(vcpu
);
6143 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
6145 struct msr_data msr
;
6146 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6147 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
6148 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
6152 msr
.host_initiated
= false;
6153 if (kvm_set_msr(vcpu
, &msr
) != 0) {
6154 trace_kvm_msr_write_ex(ecx
, data
);
6155 kvm_inject_gp(vcpu
, 0);
6159 trace_kvm_msr_write(ecx
, data
);
6160 return kvm_skip_emulated_instruction(vcpu
);
6163 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
6165 kvm_apic_update_ppr(vcpu
);
6169 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
6171 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6172 CPU_BASED_VIRTUAL_INTR_PENDING
);
6174 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6176 ++vcpu
->stat
.irq_window_exits
;
6180 static int handle_halt(struct kvm_vcpu
*vcpu
)
6182 return kvm_emulate_halt(vcpu
);
6185 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
6187 return kvm_emulate_hypercall(vcpu
);
6190 static int handle_invd(struct kvm_vcpu
*vcpu
)
6192 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6195 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
6197 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6199 kvm_mmu_invlpg(vcpu
, exit_qualification
);
6200 return kvm_skip_emulated_instruction(vcpu
);
6203 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
6207 err
= kvm_rdpmc(vcpu
);
6208 return kvm_complete_insn_gp(vcpu
, err
);
6211 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
6213 return kvm_emulate_wbinvd(vcpu
);
6216 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
6218 u64 new_bv
= kvm_read_edx_eax(vcpu
);
6219 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
6221 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
6222 return kvm_skip_emulated_instruction(vcpu
);
6226 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
6228 kvm_skip_emulated_instruction(vcpu
);
6229 WARN(1, "this should never happen\n");
6233 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
6235 kvm_skip_emulated_instruction(vcpu
);
6236 WARN(1, "this should never happen\n");
6240 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
6242 if (likely(fasteoi
)) {
6243 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6244 int access_type
, offset
;
6246 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
6247 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
6249 * Sane guest uses MOV to write EOI, with written value
6250 * not cared. So make a short-circuit here by avoiding
6251 * heavy instruction emulation.
6253 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
6254 (offset
== APIC_EOI
)) {
6255 kvm_lapic_set_eoi(vcpu
);
6256 return kvm_skip_emulated_instruction(vcpu
);
6259 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
6262 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
6264 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6265 int vector
= exit_qualification
& 0xff;
6267 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
6268 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
6272 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
6274 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6275 u32 offset
= exit_qualification
& 0xfff;
6277 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
6278 kvm_apic_write_nodecode(vcpu
, offset
);
6282 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
6284 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6285 unsigned long exit_qualification
;
6286 bool has_error_code
= false;
6289 int reason
, type
, idt_v
, idt_index
;
6291 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
6292 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
6293 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
6295 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6297 reason
= (u32
)exit_qualification
>> 30;
6298 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
6300 case INTR_TYPE_NMI_INTR
:
6301 vcpu
->arch
.nmi_injected
= false;
6302 vmx_set_nmi_mask(vcpu
, true);
6304 case INTR_TYPE_EXT_INTR
:
6305 case INTR_TYPE_SOFT_INTR
:
6306 kvm_clear_interrupt_queue(vcpu
);
6308 case INTR_TYPE_HARD_EXCEPTION
:
6309 if (vmx
->idt_vectoring_info
&
6310 VECTORING_INFO_DELIVER_CODE_MASK
) {
6311 has_error_code
= true;
6313 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
6316 case INTR_TYPE_SOFT_EXCEPTION
:
6317 kvm_clear_exception_queue(vcpu
);
6323 tss_selector
= exit_qualification
;
6325 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
6326 type
!= INTR_TYPE_EXT_INTR
&&
6327 type
!= INTR_TYPE_NMI_INTR
))
6328 skip_emulated_instruction(vcpu
);
6330 if (kvm_task_switch(vcpu
, tss_selector
,
6331 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
6332 has_error_code
, error_code
) == EMULATE_FAIL
) {
6333 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6334 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6335 vcpu
->run
->internal
.ndata
= 0;
6340 * TODO: What about debug traps on tss switch?
6341 * Are we supposed to inject them and update dr6?
6347 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
6349 unsigned long exit_qualification
;
6353 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6356 * EPT violation happened while executing iret from NMI,
6357 * "blocked by NMI" bit has to be set before next VM entry.
6358 * There are errata that may cause this bit to not be set:
6361 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6362 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
6363 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
6365 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6366 trace_kvm_page_fault(gpa
, exit_qualification
);
6368 /* Is it a read fault? */
6369 error_code
= (exit_qualification
& EPT_VIOLATION_ACC_READ
)
6370 ? PFERR_USER_MASK
: 0;
6371 /* Is it a write fault? */
6372 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_WRITE
)
6373 ? PFERR_WRITE_MASK
: 0;
6374 /* Is it a fetch fault? */
6375 error_code
|= (exit_qualification
& EPT_VIOLATION_ACC_INSTR
)
6376 ? PFERR_FETCH_MASK
: 0;
6377 /* ept page table entry is present? */
6378 error_code
|= (exit_qualification
&
6379 (EPT_VIOLATION_READABLE
| EPT_VIOLATION_WRITABLE
|
6380 EPT_VIOLATION_EXECUTABLE
))
6381 ? PFERR_PRESENT_MASK
: 0;
6383 vcpu
->arch
.gpa_available
= true;
6384 vcpu
->arch
.exit_qualification
= exit_qualification
;
6386 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
6389 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
6394 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
6395 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
6396 trace_kvm_fast_mmio(gpa
);
6397 return kvm_skip_emulated_instruction(vcpu
);
6400 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
6401 vcpu
->arch
.gpa_available
= true;
6402 if (likely(ret
== RET_MMIO_PF_EMULATE
))
6403 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
6406 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
6407 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
6409 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
6412 /* It is the real ept misconfig */
6415 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6416 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6421 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6423 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
6424 CPU_BASED_VIRTUAL_NMI_PENDING
);
6425 ++vcpu
->stat
.nmi_window_exits
;
6426 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6431 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6433 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6434 enum emulation_result err
= EMULATE_DONE
;
6437 bool intr_window_requested
;
6438 unsigned count
= 130;
6440 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6441 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6443 while (vmx
->emulation_required
&& count
-- != 0) {
6444 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6445 return handle_interrupt_window(&vmx
->vcpu
);
6447 if (kvm_test_request(KVM_REQ_EVENT
, vcpu
))
6450 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6452 if (err
== EMULATE_USER_EXIT
) {
6453 ++vcpu
->stat
.mmio_exits
;
6458 if (err
!= EMULATE_DONE
) {
6459 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6460 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6461 vcpu
->run
->internal
.ndata
= 0;
6465 if (vcpu
->arch
.halt_request
) {
6466 vcpu
->arch
.halt_request
= 0;
6467 ret
= kvm_vcpu_halt(vcpu
);
6471 if (signal_pending(current
))
6481 static int __grow_ple_window(int val
)
6483 if (ple_window_grow
< 1)
6486 val
= min(val
, ple_window_actual_max
);
6488 if (ple_window_grow
< ple_window
)
6489 val
*= ple_window_grow
;
6491 val
+= ple_window_grow
;
6496 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6501 if (modifier
< ple_window
)
6506 return max(val
, minimum
);
6509 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6511 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6512 int old
= vmx
->ple_window
;
6514 vmx
->ple_window
= __grow_ple_window(old
);
6516 if (vmx
->ple_window
!= old
)
6517 vmx
->ple_window_dirty
= true;
6519 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6522 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6524 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6525 int old
= vmx
->ple_window
;
6527 vmx
->ple_window
= __shrink_ple_window(old
,
6528 ple_window_shrink
, ple_window
);
6530 if (vmx
->ple_window
!= old
)
6531 vmx
->ple_window_dirty
= true;
6533 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6537 * ple_window_actual_max is computed to be one grow_ple_window() below
6538 * ple_window_max. (See __grow_ple_window for the reason.)
6539 * This prevents overflows, because ple_window_max is int.
6540 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6542 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6544 static void update_ple_window_actual_max(void)
6546 ple_window_actual_max
=
6547 __shrink_ple_window(max(ple_window_max
, ple_window
),
6548 ple_window_grow
, INT_MIN
);
6552 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6554 static void wakeup_handler(void)
6556 struct kvm_vcpu
*vcpu
;
6557 int cpu
= smp_processor_id();
6559 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6560 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6561 blocked_vcpu_list
) {
6562 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6564 if (pi_test_on(pi_desc
) == 1)
6565 kvm_vcpu_kick(vcpu
);
6567 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6570 void vmx_enable_tdp(void)
6572 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK
,
6573 enable_ept_ad_bits
? VMX_EPT_ACCESS_BIT
: 0ull,
6574 enable_ept_ad_bits
? VMX_EPT_DIRTY_BIT
: 0ull,
6575 0ull, VMX_EPT_EXECUTABLE_MASK
,
6576 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK
,
6579 ept_set_mmio_spte_mask();
6583 static __init
int hardware_setup(void)
6585 int r
= -ENOMEM
, i
, msr
;
6587 rdmsrl_safe(MSR_EFER
, &host_efer
);
6589 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6590 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6592 for (i
= 0; i
< VMX_BITMAP_NR
; i
++) {
6593 vmx_bitmap
[i
] = (unsigned long *)__get_free_page(GFP_KERNEL
);
6598 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6599 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6600 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6603 * Allow direct access to the PC debug port (it is often used for I/O
6604 * delays, but the vmexits simply slow things down).
6606 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6607 clear_bit(0x80, vmx_io_bitmap_a
);
6609 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6611 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6612 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6614 if (setup_vmcs_config(&vmcs_config
) < 0) {
6619 if (boot_cpu_has(X86_FEATURE_NX
))
6620 kvm_enable_efer_bits(EFER_NX
);
6622 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
6623 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
6626 if (!cpu_has_vmx_shadow_vmcs())
6627 enable_shadow_vmcs
= 0;
6628 if (enable_shadow_vmcs
)
6629 init_vmcs_shadow_fields();
6631 if (!cpu_has_vmx_ept() ||
6632 !cpu_has_vmx_ept_4levels()) {
6634 enable_unrestricted_guest
= 0;
6635 enable_ept_ad_bits
= 0;
6638 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept
)
6639 enable_ept_ad_bits
= 0;
6641 if (!cpu_has_vmx_unrestricted_guest())
6642 enable_unrestricted_guest
= 0;
6644 if (!cpu_has_vmx_flexpriority())
6645 flexpriority_enabled
= 0;
6648 * set_apic_access_page_addr() is used to reload apic access
6649 * page upon invalidation. No need to do anything if not
6650 * using the APIC_ACCESS_ADDR VMCS field.
6652 if (!flexpriority_enabled
)
6653 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6655 if (!cpu_has_vmx_tpr_shadow())
6656 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6658 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6659 kvm_disable_largepages();
6661 if (!cpu_has_vmx_ple())
6664 if (!cpu_has_vmx_apicv()) {
6666 kvm_x86_ops
->sync_pir_to_irr
= NULL
;
6669 if (cpu_has_vmx_tsc_scaling()) {
6670 kvm_has_tsc_control
= true;
6671 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6672 kvm_tsc_scaling_ratio_frac_bits
= 48;
6675 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6676 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6677 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6678 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6679 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6680 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6681 vmx_disable_intercept_for_msr(MSR_IA32_SPEC_CTRL
, false);
6682 vmx_disable_intercept_for_msr(MSR_IA32_PRED_CMD
, false);
6684 memcpy(vmx_msr_bitmap_legacy_x2apic_apicv
,
6685 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6686 memcpy(vmx_msr_bitmap_longmode_x2apic_apicv
,
6687 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6688 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6689 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6690 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6691 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6693 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6695 for (msr
= 0x800; msr
<= 0x8ff; msr
++) {
6696 if (msr
== 0x839 /* TMCCT */)
6698 vmx_disable_intercept_msr_x2apic(msr
, MSR_TYPE_R
, true);
6702 * TPR reads and writes can be virtualized even if virtual interrupt
6703 * delivery is not in use.
6705 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_W
, true);
6706 vmx_disable_intercept_msr_x2apic(0x808, MSR_TYPE_R
| MSR_TYPE_W
, false);
6709 vmx_disable_intercept_msr_x2apic(0x80b, MSR_TYPE_W
, true);
6711 vmx_disable_intercept_msr_x2apic(0x83f, MSR_TYPE_W
, true);
6718 update_ple_window_actual_max();
6721 * Only enable PML when hardware supports PML feature, and both EPT
6722 * and EPT A/D bit features are enabled -- PML depends on them to work.
6724 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6728 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6729 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6730 kvm_x86_ops
->flush_log_dirty
= NULL
;
6731 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6734 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer
) {
6737 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
6738 cpu_preemption_timer_multi
=
6739 vmx_msr
& VMX_MISC_PREEMPTION_TIMER_RATE_MASK
;
6741 kvm_x86_ops
->set_hv_timer
= NULL
;
6742 kvm_x86_ops
->cancel_hv_timer
= NULL
;
6745 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6747 kvm_mce_cap_supported
|= MCG_LMCE_P
;
6749 return alloc_kvm_area();
6752 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6753 free_page((unsigned long)vmx_bitmap
[i
]);
6758 static __exit
void hardware_unsetup(void)
6762 for (i
= 0; i
< VMX_BITMAP_NR
; i
++)
6763 free_page((unsigned long)vmx_bitmap
[i
]);
6769 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6770 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6772 static int handle_pause(struct kvm_vcpu
*vcpu
)
6775 grow_ple_window(vcpu
);
6777 kvm_vcpu_on_spin(vcpu
);
6778 return kvm_skip_emulated_instruction(vcpu
);
6781 static int handle_nop(struct kvm_vcpu
*vcpu
)
6783 return kvm_skip_emulated_instruction(vcpu
);
6786 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6788 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6789 return handle_nop(vcpu
);
6792 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6797 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6799 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6800 return handle_nop(vcpu
);
6804 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6805 * We could reuse a single VMCS for all the L2 guests, but we also want the
6806 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6807 * allows keeping them loaded on the processor, and in the future will allow
6808 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6809 * every entry if they never change.
6810 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6811 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6813 * The following functions allocate and free a vmcs02 in this pool.
6816 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6817 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6819 struct vmcs02_list
*item
;
6820 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6821 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6822 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6823 return &item
->vmcs02
;
6826 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6827 /* Recycle the least recently used VMCS. */
6828 item
= list_last_entry(&vmx
->nested
.vmcs02_pool
,
6829 struct vmcs02_list
, list
);
6830 item
->vmptr
= vmx
->nested
.current_vmptr
;
6831 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6832 return &item
->vmcs02
;
6835 /* Create a new VMCS */
6836 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6839 item
->vmcs02
.vmcs
= alloc_vmcs();
6840 item
->vmcs02
.shadow_vmcs
= NULL
;
6841 if (!item
->vmcs02
.vmcs
) {
6845 loaded_vmcs_init(&item
->vmcs02
);
6846 item
->vmptr
= vmx
->nested
.current_vmptr
;
6847 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6848 vmx
->nested
.vmcs02_num
++;
6849 return &item
->vmcs02
;
6852 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6853 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6855 struct vmcs02_list
*item
;
6856 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6857 if (item
->vmptr
== vmptr
) {
6858 free_loaded_vmcs(&item
->vmcs02
);
6859 list_del(&item
->list
);
6861 vmx
->nested
.vmcs02_num
--;
6867 * Free all VMCSs saved for this vcpu, except the one pointed by
6868 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6869 * must be &vmx->vmcs01.
6871 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6873 struct vmcs02_list
*item
, *n
;
6875 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6876 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6878 * Something will leak if the above WARN triggers. Better than
6881 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6884 free_loaded_vmcs(&item
->vmcs02
);
6885 list_del(&item
->list
);
6887 vmx
->nested
.vmcs02_num
--;
6892 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6893 * set the success or error code of an emulated VMX instruction, as specified
6894 * by Vol 2B, VMX Instruction Reference, "Conventions".
6896 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6898 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6899 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6900 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6903 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6905 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6906 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6907 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6911 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6912 u32 vm_instruction_error
)
6914 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6916 * failValid writes the error number to the current VMCS, which
6917 * can't be done there isn't a current VMCS.
6919 nested_vmx_failInvalid(vcpu
);
6922 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6923 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6924 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6926 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6928 * We don't need to force a shadow sync because
6929 * VM_INSTRUCTION_ERROR is not shadowed
6933 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6935 /* TODO: not to reset guest simply here. */
6936 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6937 pr_debug_ratelimited("kvm: nested vmx abort, indicator %d\n", indicator
);
6940 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6942 struct vcpu_vmx
*vmx
=
6943 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6945 vmx
->nested
.preemption_timer_expired
= true;
6946 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6947 kvm_vcpu_kick(&vmx
->vcpu
);
6949 return HRTIMER_NORESTART
;
6953 * Decode the memory-address operand of a vmx instruction, as recorded on an
6954 * exit caused by such an instruction (run by a guest hypervisor).
6955 * On success, returns 0. When the operand is invalid, returns 1 and throws
6958 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6959 unsigned long exit_qualification
,
6960 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6964 struct kvm_segment s
;
6967 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6968 * Execution", on an exit, vmx_instruction_info holds most of the
6969 * addressing components of the operand. Only the displacement part
6970 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6971 * For how an actual address is calculated from all these components,
6972 * refer to Vol. 1, "Operand Addressing".
6974 int scaling
= vmx_instruction_info
& 3;
6975 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6976 bool is_reg
= vmx_instruction_info
& (1u << 10);
6977 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6978 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6979 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6980 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6981 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6984 kvm_queue_exception(vcpu
, UD_VECTOR
);
6988 /* Addr = segment_base + offset */
6989 /* offset = base + [index * scale] + displacement */
6990 off
= exit_qualification
; /* holds the displacement */
6992 off
+= kvm_register_read(vcpu
, base_reg
);
6994 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6995 vmx_get_segment(vcpu
, &s
, seg_reg
);
6996 *ret
= s
.base
+ off
;
6998 if (addr_size
== 1) /* 32 bit */
7001 /* Checks for #GP/#SS exceptions. */
7003 if (is_long_mode(vcpu
)) {
7004 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
7005 * non-canonical form. This is the only check on the memory
7006 * destination for long mode!
7008 exn
= is_noncanonical_address(*ret
);
7009 } else if (is_protmode(vcpu
)) {
7010 /* Protected mode: apply checks for segment validity in the
7012 * - segment type check (#GP(0) may be thrown)
7013 * - usability check (#GP(0)/#SS(0))
7014 * - limit check (#GP(0)/#SS(0))
7017 /* #GP(0) if the destination operand is located in a
7018 * read-only data segment or any code segment.
7020 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
7022 /* #GP(0) if the source operand is located in an
7023 * execute-only code segment
7025 exn
= ((s
.type
& 0xa) == 8);
7027 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
7030 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
7032 exn
= (s
.unusable
!= 0);
7033 /* Protected mode: #GP(0)/#SS(0) if the memory
7034 * operand is outside the segment limit.
7036 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
7039 kvm_queue_exception_e(vcpu
,
7040 seg_reg
== VCPU_SREG_SS
?
7041 SS_VECTOR
: GP_VECTOR
,
7049 static int nested_vmx_get_vmptr(struct kvm_vcpu
*vcpu
, gpa_t
*vmpointer
)
7052 struct x86_exception e
;
7054 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7055 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
7058 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, vmpointer
,
7059 sizeof(*vmpointer
), &e
)) {
7060 kvm_inject_page_fault(vcpu
, &e
);
7067 static int enter_vmx_operation(struct kvm_vcpu
*vcpu
)
7069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7070 struct vmcs
*shadow_vmcs
;
7072 if (cpu_has_vmx_msr_bitmap()) {
7073 vmx
->nested
.msr_bitmap
=
7074 (unsigned long *)__get_free_page(GFP_KERNEL
);
7075 if (!vmx
->nested
.msr_bitmap
)
7076 goto out_msr_bitmap
;
7079 vmx
->nested
.cached_vmcs12
= kmalloc(VMCS12_SIZE
, GFP_KERNEL
);
7080 if (!vmx
->nested
.cached_vmcs12
)
7081 goto out_cached_vmcs12
;
7083 if (enable_shadow_vmcs
) {
7084 shadow_vmcs
= alloc_vmcs();
7086 goto out_shadow_vmcs
;
7087 /* mark vmcs as shadow */
7088 shadow_vmcs
->revision_id
|= (1u << 31);
7089 /* init shadow vmcs */
7090 vmcs_clear(shadow_vmcs
);
7091 vmx
->vmcs01
.shadow_vmcs
= shadow_vmcs
;
7094 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
7095 vmx
->nested
.vmcs02_num
= 0;
7097 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
7098 HRTIMER_MODE_REL_PINNED
);
7099 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
7101 vmx
->nested
.vmxon
= true;
7105 kfree(vmx
->nested
.cached_vmcs12
);
7108 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7115 * Emulate the VMXON instruction.
7116 * Currently, we just remember that VMX is active, and do not save or even
7117 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
7118 * do not currently need to store anything in that guest-allocated memory
7119 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
7120 * argument is different from the VMXON pointer (which the spec says they do).
7122 static int handle_vmon(struct kvm_vcpu
*vcpu
)
7127 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7128 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
7129 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
7132 * The Intel VMX Instruction Reference lists a bunch of bits that are
7133 * prerequisite to running VMXON, most notably cr4.VMXE must be set to
7134 * 1 (see vmx_set_cr4() for when we allow the guest to set this).
7135 * Otherwise, we should fail with #UD. But most faulting conditions
7136 * have already been checked by hardware, prior to the VM-exit for
7137 * VMXON. We do test guest cr4.VMXE because processor CR4 always has
7138 * that bit set to 1 in non-root mode.
7140 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
)) {
7141 kvm_queue_exception(vcpu
, UD_VECTOR
);
7145 if (vmx
->nested
.vmxon
) {
7146 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
7147 return kvm_skip_emulated_instruction(vcpu
);
7150 if ((vmx
->msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
7151 != VMXON_NEEDED_FEATURES
) {
7152 kvm_inject_gp(vcpu
, 0);
7156 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7161 * The first 4 bytes of VMXON region contain the supported
7162 * VMCS revision identifier
7164 * Note - IA32_VMX_BASIC[48] will never be 1 for the nested case;
7165 * which replaces physical address width with 32
7167 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7168 nested_vmx_failInvalid(vcpu
);
7169 return kvm_skip_emulated_instruction(vcpu
);
7172 page
= nested_get_page(vcpu
, vmptr
);
7174 nested_vmx_failInvalid(vcpu
);
7175 return kvm_skip_emulated_instruction(vcpu
);
7177 if (*(u32
*)kmap(page
) != VMCS12_REVISION
) {
7179 nested_release_page_clean(page
);
7180 nested_vmx_failInvalid(vcpu
);
7181 return kvm_skip_emulated_instruction(vcpu
);
7184 nested_release_page_clean(page
);
7186 vmx
->nested
.vmxon_ptr
= vmptr
;
7187 ret
= enter_vmx_operation(vcpu
);
7191 nested_vmx_succeed(vcpu
);
7192 return kvm_skip_emulated_instruction(vcpu
);
7196 * Intel's VMX Instruction Reference specifies a common set of prerequisites
7197 * for running VMX instructions (except VMXON, whose prerequisites are
7198 * slightly different). It also specifies what exception to inject otherwise.
7199 * Note that many of these exceptions have priority over VM exits, so they
7200 * don't have to be checked again here.
7202 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
7204 if (!to_vmx(vcpu
)->nested
.vmxon
) {
7205 kvm_queue_exception(vcpu
, UD_VECTOR
);
7211 static void vmx_disable_shadow_vmcs(struct vcpu_vmx
*vmx
)
7213 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
, SECONDARY_EXEC_SHADOW_VMCS
);
7214 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7217 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
7219 if (vmx
->nested
.current_vmptr
== -1ull)
7222 if (enable_shadow_vmcs
) {
7223 /* copy to memory all shadowed fields in case
7224 they were modified */
7225 copy_shadow_to_vmcs12(vmx
);
7226 vmx
->nested
.sync_shadow_vmcs
= false;
7227 vmx_disable_shadow_vmcs(vmx
);
7229 vmx
->nested
.posted_intr_nv
= -1;
7231 /* Flush VMCS12 to guest memory */
7232 kvm_vcpu_write_guest_page(&vmx
->vcpu
,
7233 vmx
->nested
.current_vmptr
>> PAGE_SHIFT
,
7234 vmx
->nested
.cached_vmcs12
, 0, VMCS12_SIZE
);
7236 vmx
->nested
.current_vmptr
= -1ull;
7240 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
7241 * just stops using VMX.
7243 static void free_nested(struct vcpu_vmx
*vmx
)
7245 if (!vmx
->nested
.vmxon
)
7248 vmx
->nested
.vmxon
= false;
7249 free_vpid(vmx
->nested
.vpid02
);
7250 vmx
->nested
.posted_intr_nv
= -1;
7251 vmx
->nested
.current_vmptr
= -1ull;
7252 if (vmx
->nested
.msr_bitmap
) {
7253 free_page((unsigned long)vmx
->nested
.msr_bitmap
);
7254 vmx
->nested
.msr_bitmap
= NULL
;
7256 if (enable_shadow_vmcs
) {
7257 vmx_disable_shadow_vmcs(vmx
);
7258 vmcs_clear(vmx
->vmcs01
.shadow_vmcs
);
7259 free_vmcs(vmx
->vmcs01
.shadow_vmcs
);
7260 vmx
->vmcs01
.shadow_vmcs
= NULL
;
7262 kfree(vmx
->nested
.cached_vmcs12
);
7263 /* Unpin physical memory we referred to in current vmcs02 */
7264 if (vmx
->nested
.apic_access_page
) {
7265 nested_release_page(vmx
->nested
.apic_access_page
);
7266 vmx
->nested
.apic_access_page
= NULL
;
7268 if (vmx
->nested
.virtual_apic_page
) {
7269 nested_release_page(vmx
->nested
.virtual_apic_page
);
7270 vmx
->nested
.virtual_apic_page
= NULL
;
7272 if (vmx
->nested
.pi_desc_page
) {
7273 kunmap(vmx
->nested
.pi_desc_page
);
7274 nested_release_page(vmx
->nested
.pi_desc_page
);
7275 vmx
->nested
.pi_desc_page
= NULL
;
7276 vmx
->nested
.pi_desc
= NULL
;
7279 nested_free_all_saved_vmcss(vmx
);
7282 /* Emulate the VMXOFF instruction */
7283 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
7285 if (!nested_vmx_check_permission(vcpu
))
7287 free_nested(to_vmx(vcpu
));
7288 nested_vmx_succeed(vcpu
);
7289 return kvm_skip_emulated_instruction(vcpu
);
7292 /* Emulate the VMCLEAR instruction */
7293 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
7295 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7299 if (!nested_vmx_check_permission(vcpu
))
7302 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7305 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7306 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_INVALID_ADDRESS
);
7307 return kvm_skip_emulated_instruction(vcpu
);
7310 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7311 nested_vmx_failValid(vcpu
, VMXERR_VMCLEAR_VMXON_POINTER
);
7312 return kvm_skip_emulated_instruction(vcpu
);
7315 if (vmptr
== vmx
->nested
.current_vmptr
)
7316 nested_release_vmcs12(vmx
);
7318 kvm_vcpu_write_guest(vcpu
,
7319 vmptr
+ offsetof(struct vmcs12
, launch_state
),
7320 &zero
, sizeof(zero
));
7322 nested_free_vmcs02(vmx
, vmptr
);
7324 nested_vmx_succeed(vcpu
);
7325 return kvm_skip_emulated_instruction(vcpu
);
7328 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
7330 /* Emulate the VMLAUNCH instruction */
7331 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
7333 return nested_vmx_run(vcpu
, true);
7336 /* Emulate the VMRESUME instruction */
7337 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
7340 return nested_vmx_run(vcpu
, false);
7344 * Read a vmcs12 field. Since these can have varying lengths and we return
7345 * one type, we chose the biggest type (u64) and zero-extend the return value
7346 * to that size. Note that the caller, handle_vmread, might need to use only
7347 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7348 * 64-bit fields are to be returned).
7350 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7351 unsigned long field
, u64
*ret
)
7353 short offset
= vmcs_field_to_offset(field
);
7359 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7361 switch (vmcs_field_type(field
)) {
7362 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7363 *ret
= *((natural_width
*)p
);
7365 case VMCS_FIELD_TYPE_U16
:
7368 case VMCS_FIELD_TYPE_U32
:
7371 case VMCS_FIELD_TYPE_U64
:
7381 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7382 unsigned long field
, u64 field_value
){
7383 short offset
= vmcs_field_to_offset(field
);
7384 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7388 switch (vmcs_field_type(field
)) {
7389 case VMCS_FIELD_TYPE_U16
:
7390 *(u16
*)p
= field_value
;
7392 case VMCS_FIELD_TYPE_U32
:
7393 *(u32
*)p
= field_value
;
7395 case VMCS_FIELD_TYPE_U64
:
7396 *(u64
*)p
= field_value
;
7398 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7399 *(natural_width
*)p
= field_value
;
7408 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7411 unsigned long field
;
7413 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7414 const unsigned long *fields
= shadow_read_write_fields
;
7415 const int num_fields
= max_shadow_read_write_fields
;
7419 vmcs_load(shadow_vmcs
);
7421 for (i
= 0; i
< num_fields
; i
++) {
7423 switch (vmcs_field_type(field
)) {
7424 case VMCS_FIELD_TYPE_U16
:
7425 field_value
= vmcs_read16(field
);
7427 case VMCS_FIELD_TYPE_U32
:
7428 field_value
= vmcs_read32(field
);
7430 case VMCS_FIELD_TYPE_U64
:
7431 field_value
= vmcs_read64(field
);
7433 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7434 field_value
= vmcs_readl(field
);
7440 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7443 vmcs_clear(shadow_vmcs
);
7444 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7449 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7451 const unsigned long *fields
[] = {
7452 shadow_read_write_fields
,
7453 shadow_read_only_fields
7455 const int max_fields
[] = {
7456 max_shadow_read_write_fields
,
7457 max_shadow_read_only_fields
7460 unsigned long field
;
7461 u64 field_value
= 0;
7462 struct vmcs
*shadow_vmcs
= vmx
->vmcs01
.shadow_vmcs
;
7464 vmcs_load(shadow_vmcs
);
7466 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7467 for (i
= 0; i
< max_fields
[q
]; i
++) {
7468 field
= fields
[q
][i
];
7469 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7471 switch (vmcs_field_type(field
)) {
7472 case VMCS_FIELD_TYPE_U16
:
7473 vmcs_write16(field
, (u16
)field_value
);
7475 case VMCS_FIELD_TYPE_U32
:
7476 vmcs_write32(field
, (u32
)field_value
);
7478 case VMCS_FIELD_TYPE_U64
:
7479 vmcs_write64(field
, (u64
)field_value
);
7481 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7482 vmcs_writel(field
, (long)field_value
);
7491 vmcs_clear(shadow_vmcs
);
7492 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7496 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7497 * used before) all generate the same failure when it is missing.
7499 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7501 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7502 if (vmx
->nested
.current_vmptr
== -1ull) {
7503 nested_vmx_failInvalid(vcpu
);
7509 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7511 unsigned long field
;
7513 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7514 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7517 if (!nested_vmx_check_permission(vcpu
))
7520 if (!nested_vmx_check_vmcs12(vcpu
))
7521 return kvm_skip_emulated_instruction(vcpu
);
7523 /* Decode instruction info and find the field to read */
7524 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7525 /* Read the field, zero-extended to a u64 field_value */
7526 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7527 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7528 return kvm_skip_emulated_instruction(vcpu
);
7531 * Now copy part of this value to register or memory, as requested.
7532 * Note that the number of bits actually copied is 32 or 64 depending
7533 * on the guest's mode (32 or 64 bit), not on the given field's length.
7535 if (vmx_instruction_info
& (1u << 10)) {
7536 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7539 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7540 vmx_instruction_info
, true, &gva
))
7542 /* _system ok, as hardware has verified cpl=0 */
7543 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7544 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7547 nested_vmx_succeed(vcpu
);
7548 return kvm_skip_emulated_instruction(vcpu
);
7552 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7554 unsigned long field
;
7556 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7557 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7558 /* The value to write might be 32 or 64 bits, depending on L1's long
7559 * mode, and eventually we need to write that into a field of several
7560 * possible lengths. The code below first zero-extends the value to 64
7561 * bit (field_value), and then copies only the appropriate number of
7562 * bits into the vmcs12 field.
7564 u64 field_value
= 0;
7565 struct x86_exception e
;
7567 if (!nested_vmx_check_permission(vcpu
))
7570 if (!nested_vmx_check_vmcs12(vcpu
))
7571 return kvm_skip_emulated_instruction(vcpu
);
7573 if (vmx_instruction_info
& (1u << 10))
7574 field_value
= kvm_register_readl(vcpu
,
7575 (((vmx_instruction_info
) >> 3) & 0xf));
7577 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7578 vmx_instruction_info
, false, &gva
))
7580 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7581 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7582 kvm_inject_page_fault(vcpu
, &e
);
7588 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7589 if (vmcs_field_readonly(field
)) {
7590 nested_vmx_failValid(vcpu
,
7591 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7592 return kvm_skip_emulated_instruction(vcpu
);
7595 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7596 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7597 return kvm_skip_emulated_instruction(vcpu
);
7600 nested_vmx_succeed(vcpu
);
7601 return kvm_skip_emulated_instruction(vcpu
);
7604 static void set_current_vmptr(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
7606 vmx
->nested
.current_vmptr
= vmptr
;
7607 if (enable_shadow_vmcs
) {
7608 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7609 SECONDARY_EXEC_SHADOW_VMCS
);
7610 vmcs_write64(VMCS_LINK_POINTER
,
7611 __pa(vmx
->vmcs01
.shadow_vmcs
));
7612 vmx
->nested
.sync_shadow_vmcs
= true;
7616 /* Emulate the VMPTRLD instruction */
7617 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7619 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7622 if (!nested_vmx_check_permission(vcpu
))
7625 if (nested_vmx_get_vmptr(vcpu
, &vmptr
))
7628 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> cpuid_maxphyaddr(vcpu
))) {
7629 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_INVALID_ADDRESS
);
7630 return kvm_skip_emulated_instruction(vcpu
);
7633 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
7634 nested_vmx_failValid(vcpu
, VMXERR_VMPTRLD_VMXON_POINTER
);
7635 return kvm_skip_emulated_instruction(vcpu
);
7638 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7639 struct vmcs12
*new_vmcs12
;
7641 page
= nested_get_page(vcpu
, vmptr
);
7643 nested_vmx_failInvalid(vcpu
);
7644 return kvm_skip_emulated_instruction(vcpu
);
7646 new_vmcs12
= kmap(page
);
7647 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7649 nested_release_page_clean(page
);
7650 nested_vmx_failValid(vcpu
,
7651 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7652 return kvm_skip_emulated_instruction(vcpu
);
7655 nested_release_vmcs12(vmx
);
7657 * Load VMCS12 from guest memory since it is not already
7660 memcpy(vmx
->nested
.cached_vmcs12
, new_vmcs12
, VMCS12_SIZE
);
7662 nested_release_page_clean(page
);
7664 set_current_vmptr(vmx
, vmptr
);
7667 nested_vmx_succeed(vcpu
);
7668 return kvm_skip_emulated_instruction(vcpu
);
7671 /* Emulate the VMPTRST instruction */
7672 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7674 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7675 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7677 struct x86_exception e
;
7679 if (!nested_vmx_check_permission(vcpu
))
7682 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7683 vmx_instruction_info
, true, &vmcs_gva
))
7685 /* ok to use *_system, as hardware has verified cpl=0 */
7686 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7687 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7689 kvm_inject_page_fault(vcpu
, &e
);
7692 nested_vmx_succeed(vcpu
);
7693 return kvm_skip_emulated_instruction(vcpu
);
7696 /* Emulate the INVEPT instruction */
7697 static int handle_invept(struct kvm_vcpu
*vcpu
)
7699 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7700 u32 vmx_instruction_info
, types
;
7703 struct x86_exception e
;
7708 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7709 SECONDARY_EXEC_ENABLE_EPT
) ||
7710 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7711 kvm_queue_exception(vcpu
, UD_VECTOR
);
7715 if (!nested_vmx_check_permission(vcpu
))
7718 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7719 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7721 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7723 if (type
>= 32 || !(types
& (1 << type
))) {
7724 nested_vmx_failValid(vcpu
,
7725 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7726 return kvm_skip_emulated_instruction(vcpu
);
7729 /* According to the Intel VMX instruction reference, the memory
7730 * operand is read even if it isn't needed (e.g., for type==global)
7732 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7733 vmx_instruction_info
, false, &gva
))
7735 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7736 sizeof(operand
), &e
)) {
7737 kvm_inject_page_fault(vcpu
, &e
);
7742 case VMX_EPT_EXTENT_GLOBAL
:
7744 * TODO: track mappings and invalidate
7745 * single context requests appropriately
7747 case VMX_EPT_EXTENT_CONTEXT
:
7748 kvm_mmu_sync_roots(vcpu
);
7749 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7750 nested_vmx_succeed(vcpu
);
7757 return kvm_skip_emulated_instruction(vcpu
);
7760 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7762 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7763 u32 vmx_instruction_info
;
7764 unsigned long type
, types
;
7766 struct x86_exception e
;
7772 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7773 SECONDARY_EXEC_ENABLE_VPID
) ||
7774 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7775 kvm_queue_exception(vcpu
, UD_VECTOR
);
7779 if (!nested_vmx_check_permission(vcpu
))
7782 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7783 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7785 types
= (vmx
->nested
.nested_vmx_vpid_caps
&
7786 VMX_VPID_EXTENT_SUPPORTED_MASK
) >> 8;
7788 if (type
>= 32 || !(types
& (1 << type
))) {
7789 nested_vmx_failValid(vcpu
,
7790 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7791 return kvm_skip_emulated_instruction(vcpu
);
7794 /* according to the intel vmx instruction reference, the memory
7795 * operand is read even if it isn't needed (e.g., for type==global)
7797 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7798 vmx_instruction_info
, false, &gva
))
7800 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7801 sizeof(operand
), &e
)) {
7802 kvm_inject_page_fault(vcpu
, &e
);
7805 if (operand
.vpid
>> 16) {
7806 nested_vmx_failValid(vcpu
,
7807 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7808 return kvm_skip_emulated_instruction(vcpu
);
7812 case VMX_VPID_EXTENT_INDIVIDUAL_ADDR
:
7813 if (is_noncanonical_address(operand
.gla
)) {
7814 nested_vmx_failValid(vcpu
,
7815 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7816 return kvm_skip_emulated_instruction(vcpu
);
7819 case VMX_VPID_EXTENT_SINGLE_CONTEXT
:
7820 case VMX_VPID_EXTENT_SINGLE_NON_GLOBAL
:
7821 if (!operand
.vpid
) {
7822 nested_vmx_failValid(vcpu
,
7823 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7824 return kvm_skip_emulated_instruction(vcpu
);
7827 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7831 return kvm_skip_emulated_instruction(vcpu
);
7834 __vmx_flush_tlb(vcpu
, vmx
->nested
.vpid02
);
7835 nested_vmx_succeed(vcpu
);
7837 return kvm_skip_emulated_instruction(vcpu
);
7840 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7842 unsigned long exit_qualification
;
7844 trace_kvm_pml_full(vcpu
->vcpu_id
);
7846 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7849 * PML buffer FULL happened while executing iret from NMI,
7850 * "blocked by NMI" bit has to be set before next VM entry.
7852 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7853 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7854 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7855 GUEST_INTR_STATE_NMI
);
7858 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7859 * here.., and there's no userspace involvement needed for PML.
7864 static int handle_preemption_timer(struct kvm_vcpu
*vcpu
)
7866 kvm_lapic_expired_hv_timer(vcpu
);
7871 * The exit handlers return 1 if the exit was handled fully and guest execution
7872 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7873 * to be done to userspace and return 0.
7875 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7876 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7877 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7878 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7879 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7880 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7881 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7882 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7883 [EXIT_REASON_CPUID
] = handle_cpuid
,
7884 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7885 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7886 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7887 [EXIT_REASON_HLT
] = handle_halt
,
7888 [EXIT_REASON_INVD
] = handle_invd
,
7889 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7890 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7891 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7892 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7893 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7894 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7895 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7896 [EXIT_REASON_VMREAD
] = handle_vmread
,
7897 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7898 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7899 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7900 [EXIT_REASON_VMON
] = handle_vmon
,
7901 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7902 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7903 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7904 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7905 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7906 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7907 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7908 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7909 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7910 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7911 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7912 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7913 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7914 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7915 [EXIT_REASON_INVEPT
] = handle_invept
,
7916 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7917 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7918 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7919 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7920 [EXIT_REASON_PREEMPTION_TIMER
] = handle_preemption_timer
,
7923 static const int kvm_vmx_max_exit_handlers
=
7924 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7926 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7927 struct vmcs12
*vmcs12
)
7929 unsigned long exit_qualification
;
7930 gpa_t bitmap
, last_bitmap
;
7935 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7936 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7938 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7940 port
= exit_qualification
>> 16;
7941 size
= (exit_qualification
& 7) + 1;
7943 last_bitmap
= (gpa_t
)-1;
7948 bitmap
= vmcs12
->io_bitmap_a
;
7949 else if (port
< 0x10000)
7950 bitmap
= vmcs12
->io_bitmap_b
;
7953 bitmap
+= (port
& 0x7fff) / 8;
7955 if (last_bitmap
!= bitmap
)
7956 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7958 if (b
& (1 << (port
& 7)))
7963 last_bitmap
= bitmap
;
7970 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7971 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7972 * disinterest in the current event (read or write a specific MSR) by using an
7973 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7975 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7976 struct vmcs12
*vmcs12
, u32 exit_reason
)
7978 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7981 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7985 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7986 * for the four combinations of read/write and low/high MSR numbers.
7987 * First we need to figure out which of the four to use:
7989 bitmap
= vmcs12
->msr_bitmap
;
7990 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7992 if (msr_index
>= 0xc0000000) {
7993 msr_index
-= 0xc0000000;
7997 /* Then read the msr_index'th bit from this bitmap: */
7998 if (msr_index
< 1024*8) {
8000 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
8002 return 1 & (b
>> (msr_index
& 7));
8004 return true; /* let L1 handle the wrong parameter */
8008 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
8009 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
8010 * intercept (via guest_host_mask etc.) the current event.
8012 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
8013 struct vmcs12
*vmcs12
)
8015 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
8016 int cr
= exit_qualification
& 15;
8020 switch ((exit_qualification
>> 4) & 3) {
8021 case 0: /* mov to cr */
8022 reg
= (exit_qualification
>> 8) & 15;
8023 val
= kvm_register_readl(vcpu
, reg
);
8026 if (vmcs12
->cr0_guest_host_mask
&
8027 (val
^ vmcs12
->cr0_read_shadow
))
8031 if ((vmcs12
->cr3_target_count
>= 1 &&
8032 vmcs12
->cr3_target_value0
== val
) ||
8033 (vmcs12
->cr3_target_count
>= 2 &&
8034 vmcs12
->cr3_target_value1
== val
) ||
8035 (vmcs12
->cr3_target_count
>= 3 &&
8036 vmcs12
->cr3_target_value2
== val
) ||
8037 (vmcs12
->cr3_target_count
>= 4 &&
8038 vmcs12
->cr3_target_value3
== val
))
8040 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
8044 if (vmcs12
->cr4_guest_host_mask
&
8045 (vmcs12
->cr4_read_shadow
^ val
))
8049 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
8055 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
8056 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
8059 case 1: /* mov from cr */
8062 if (vmcs12
->cpu_based_vm_exec_control
&
8063 CPU_BASED_CR3_STORE_EXITING
)
8067 if (vmcs12
->cpu_based_vm_exec_control
&
8068 CPU_BASED_CR8_STORE_EXITING
)
8075 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
8076 * cr0. Other attempted changes are ignored, with no exit.
8078 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
8079 if (vmcs12
->cr0_guest_host_mask
& 0xe &
8080 (val
^ vmcs12
->cr0_read_shadow
))
8082 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
8083 !(vmcs12
->cr0_read_shadow
& 0x1) &&
8092 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
8093 * should handle it ourselves in L0 (and then continue L2). Only call this
8094 * when in is_guest_mode (L2).
8096 static bool nested_vmx_exit_reflected(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8098 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8099 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8100 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8102 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
8103 vmcs_readl(EXIT_QUALIFICATION
),
8104 vmx
->idt_vectoring_info
,
8106 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8110 * The host physical addresses of some pages of guest memory
8111 * are loaded into VMCS02 (e.g. L1's Virtual APIC Page). The CPU
8112 * may write to these pages via their host physical address while
8113 * L2 is running, bypassing any address-translation-based dirty
8114 * tracking (e.g. EPT write protection).
8116 * Mark them dirty on every exit from L2 to prevent them from
8117 * getting out of sync with dirty tracking.
8119 nested_mark_vmcs12_pages_dirty(vcpu
);
8121 if (vmx
->nested
.nested_run_pending
)
8124 if (unlikely(vmx
->fail
)) {
8125 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
8126 vmcs_read32(VM_INSTRUCTION_ERROR
));
8130 switch (exit_reason
) {
8131 case EXIT_REASON_EXCEPTION_NMI
:
8132 if (is_nmi(intr_info
))
8134 else if (is_page_fault(intr_info
))
8135 return !vmx
->vcpu
.arch
.apf
.host_apf_reason
&& enable_ept
;
8136 else if (is_no_device(intr_info
) &&
8137 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
8139 else if (is_debug(intr_info
) &&
8141 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
8143 else if (is_breakpoint(intr_info
) &&
8144 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
8146 return vmcs12
->exception_bitmap
&
8147 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
8148 case EXIT_REASON_EXTERNAL_INTERRUPT
:
8150 case EXIT_REASON_TRIPLE_FAULT
:
8152 case EXIT_REASON_PENDING_INTERRUPT
:
8153 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
8154 case EXIT_REASON_NMI_WINDOW
:
8155 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
8156 case EXIT_REASON_TASK_SWITCH
:
8158 case EXIT_REASON_CPUID
:
8160 case EXIT_REASON_HLT
:
8161 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
8162 case EXIT_REASON_INVD
:
8164 case EXIT_REASON_INVLPG
:
8165 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
8166 case EXIT_REASON_RDPMC
:
8167 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
8168 case EXIT_REASON_RDRAND
:
8169 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDRAND
);
8170 case EXIT_REASON_RDSEED
:
8171 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_RDSEED
);
8172 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
8173 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
8174 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
8175 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
8176 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
8177 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
8178 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
8179 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
8181 * VMX instructions trap unconditionally. This allows L1 to
8182 * emulate them for its L2 guest, i.e., allows 3-level nesting!
8185 case EXIT_REASON_CR_ACCESS
:
8186 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
8187 case EXIT_REASON_DR_ACCESS
:
8188 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
8189 case EXIT_REASON_IO_INSTRUCTION
:
8190 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
8191 case EXIT_REASON_GDTR_IDTR
: case EXIT_REASON_LDTR_TR
:
8192 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_DESC
);
8193 case EXIT_REASON_MSR_READ
:
8194 case EXIT_REASON_MSR_WRITE
:
8195 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
8196 case EXIT_REASON_INVALID_STATE
:
8198 case EXIT_REASON_MWAIT_INSTRUCTION
:
8199 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
8200 case EXIT_REASON_MONITOR_TRAP_FLAG
:
8201 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
8202 case EXIT_REASON_MONITOR_INSTRUCTION
:
8203 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
8204 case EXIT_REASON_PAUSE_INSTRUCTION
:
8205 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
8206 nested_cpu_has2(vmcs12
,
8207 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
8208 case EXIT_REASON_MCE_DURING_VMENTRY
:
8210 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
8211 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
8212 case EXIT_REASON_APIC_ACCESS
:
8213 return nested_cpu_has2(vmcs12
,
8214 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
8215 case EXIT_REASON_APIC_WRITE
:
8216 case EXIT_REASON_EOI_INDUCED
:
8217 /* apic_write and eoi_induced should exit unconditionally. */
8219 case EXIT_REASON_EPT_VIOLATION
:
8221 * L0 always deals with the EPT violation. If nested EPT is
8222 * used, and the nested mmu code discovers that the address is
8223 * missing in the guest EPT table (EPT12), the EPT violation
8224 * will be injected with nested_ept_inject_page_fault()
8227 case EXIT_REASON_EPT_MISCONFIG
:
8229 * L2 never uses directly L1's EPT, but rather L0's own EPT
8230 * table (shadow on EPT) or a merged EPT table that L0 built
8231 * (EPT on EPT). So any problems with the structure of the
8232 * table is L0's fault.
8235 case EXIT_REASON_WBINVD
:
8236 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
8237 case EXIT_REASON_XSETBV
:
8239 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
8241 * This should never happen, since it is not possible to
8242 * set XSS to a non-zero value---neither in L1 nor in L2.
8243 * If if it were, XSS would have to be checked against
8244 * the XSS exit bitmap in vmcs12.
8246 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
8247 case EXIT_REASON_PREEMPTION_TIMER
:
8249 case EXIT_REASON_PML_FULL
:
8250 /* We emulate PML support to L1. */
8257 static int nested_vmx_reflect_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
)
8259 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8262 * At this point, the exit interruption info in exit_intr_info
8263 * is only valid for EXCEPTION_NMI exits. For EXTERNAL_INTERRUPT
8264 * we need to query the in-kernel LAPIC.
8266 WARN_ON(exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
);
8267 if ((exit_intr_info
&
8268 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8269 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) {
8270 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8271 vmcs12
->vm_exit_intr_error_code
=
8272 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8275 nested_vmx_vmexit(vcpu
, exit_reason
, exit_intr_info
,
8276 vmcs_readl(EXIT_QUALIFICATION
));
8280 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
8282 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
8283 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
8286 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
8289 __free_page(vmx
->pml_pg
);
8294 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
8296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8300 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
8302 /* Do nothing if PML buffer is empty */
8303 if (pml_idx
== (PML_ENTITY_NUM
- 1))
8306 /* PML index always points to next available PML buffer entity */
8307 if (pml_idx
>= PML_ENTITY_NUM
)
8312 pml_buf
= page_address(vmx
->pml_pg
);
8313 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
8316 gpa
= pml_buf
[pml_idx
];
8317 WARN_ON(gpa
& (PAGE_SIZE
- 1));
8318 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
8321 /* reset PML index */
8322 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
8326 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
8327 * Called before reporting dirty_bitmap to userspace.
8329 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
8332 struct kvm_vcpu
*vcpu
;
8334 * We only need to kick vcpu out of guest mode here, as PML buffer
8335 * is flushed at beginning of all VMEXITs, and it's obvious that only
8336 * vcpus running in guest are possible to have unflushed GPAs in PML
8339 kvm_for_each_vcpu(i
, vcpu
, kvm
)
8340 kvm_vcpu_kick(vcpu
);
8343 static void vmx_dump_sel(char *name
, uint32_t sel
)
8345 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
8346 name
, vmcs_read16(sel
),
8347 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
8348 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
8349 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
8352 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
8354 pr_err("%s limit=0x%08x, base=0x%016lx\n",
8355 name
, vmcs_read32(limit
),
8356 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
8359 static void dump_vmcs(void)
8361 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
8362 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
8363 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
8364 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
8365 u32 secondary_exec_control
= 0;
8366 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
8367 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
8370 if (cpu_has_secondary_exec_ctrls())
8371 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8373 pr_err("*** Guest State ***\n");
8374 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8375 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
8376 vmcs_readl(CR0_GUEST_HOST_MASK
));
8377 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8378 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
8379 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
8380 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
8381 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
8383 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
8384 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
8385 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
8386 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8388 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8389 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8390 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8391 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8392 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8393 vmcs_readl(GUEST_SYSENTER_ESP
),
8394 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8395 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8396 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8397 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8398 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8399 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8400 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8401 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8402 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8403 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8404 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8405 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8406 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8407 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8408 efer
, vmcs_read64(GUEST_IA32_PAT
));
8409 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8410 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8411 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8412 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8413 pr_err("PerfGlobCtl = 0x%016llx\n",
8414 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8415 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8416 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8417 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8418 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8419 vmcs_read32(GUEST_ACTIVITY_STATE
));
8420 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8421 pr_err("InterruptStatus = %04x\n",
8422 vmcs_read16(GUEST_INTR_STATUS
));
8424 pr_err("*** Host State ***\n");
8425 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8426 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8427 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8428 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8429 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8430 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8431 vmcs_read16(HOST_TR_SELECTOR
));
8432 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8433 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8434 vmcs_readl(HOST_TR_BASE
));
8435 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8436 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8437 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8438 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8439 vmcs_readl(HOST_CR4
));
8440 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8441 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8442 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8443 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8444 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8445 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8446 vmcs_read64(HOST_IA32_EFER
),
8447 vmcs_read64(HOST_IA32_PAT
));
8448 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8449 pr_err("PerfGlobCtl = 0x%016llx\n",
8450 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8452 pr_err("*** Control State ***\n");
8453 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8454 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8455 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8456 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8457 vmcs_read32(EXCEPTION_BITMAP
),
8458 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8459 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8460 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8461 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8462 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8463 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8464 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8465 vmcs_read32(VM_EXIT_INTR_INFO
),
8466 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8467 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8468 pr_err(" reason=%08x qualification=%016lx\n",
8469 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8470 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8471 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8472 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8473 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8474 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8475 pr_err("TSC Multiplier = 0x%016llx\n",
8476 vmcs_read64(TSC_MULTIPLIER
));
8477 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8478 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8479 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8480 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8481 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8482 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8483 n
= vmcs_read32(CR3_TARGET_COUNT
);
8484 for (i
= 0; i
+ 1 < n
; i
+= 4)
8485 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8486 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8487 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8489 pr_err("CR3 target%u=%016lx\n",
8490 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8491 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8492 pr_err("PLE Gap=%08x Window=%08x\n",
8493 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8494 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8495 pr_err("Virtual processor ID = 0x%04x\n",
8496 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8500 * The guest has exited. See if we can fix it or if we need userspace
8503 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8505 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8506 u32 exit_reason
= vmx
->exit_reason
;
8507 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8509 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8510 vcpu
->arch
.gpa_available
= false;
8513 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8514 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8515 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8516 * mode as if vcpus is in root mode, the PML buffer must has been
8520 vmx_flush_pml_buffer(vcpu
);
8522 /* If guest state is invalid, start emulating */
8523 if (vmx
->emulation_required
)
8524 return handle_invalid_guest_state(vcpu
);
8526 if (is_guest_mode(vcpu
) && nested_vmx_exit_reflected(vcpu
, exit_reason
))
8527 return nested_vmx_reflect_vmexit(vcpu
, exit_reason
);
8529 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8531 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8532 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8537 if (unlikely(vmx
->fail
)) {
8538 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8539 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8540 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8546 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8547 * delivery event since it indicates guest is accessing MMIO.
8548 * The vm-exit can be triggered again after return to guest that
8549 * will cause infinite loop.
8551 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8552 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8553 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8554 exit_reason
!= EXIT_REASON_PML_FULL
&&
8555 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8556 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8557 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8558 vcpu
->run
->internal
.ndata
= 3;
8559 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8560 vcpu
->run
->internal
.data
[1] = exit_reason
;
8561 vcpu
->run
->internal
.data
[2] = vcpu
->arch
.exit_qualification
;
8562 if (exit_reason
== EXIT_REASON_EPT_MISCONFIG
) {
8563 vcpu
->run
->internal
.ndata
++;
8564 vcpu
->run
->internal
.data
[3] =
8565 vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
8570 if (exit_reason
< kvm_vmx_max_exit_handlers
8571 && kvm_vmx_exit_handlers
[exit_reason
])
8572 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8574 vcpu_unimpl(vcpu
, "vmx: unexpected exit reason 0x%x\n",
8576 kvm_queue_exception(vcpu
, UD_VECTOR
);
8581 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8583 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8585 if (is_guest_mode(vcpu
) &&
8586 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8589 if (irr
== -1 || tpr
< irr
) {
8590 vmcs_write32(TPR_THRESHOLD
, 0);
8594 vmcs_write32(TPR_THRESHOLD
, irr
);
8597 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8599 u32 sec_exec_control
;
8601 /* Postpone execution until vmcs01 is the current VMCS. */
8602 if (is_guest_mode(vcpu
)) {
8603 to_vmx(vcpu
)->nested
.change_vmcs01_virtual_x2apic_mode
= true;
8607 if (!cpu_has_vmx_virtualize_x2apic_mode())
8610 if (!cpu_need_tpr_shadow(vcpu
))
8613 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8616 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8617 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8619 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8620 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8621 vmx_flush_tlb_ept_only(vcpu
);
8623 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8625 vmx_set_msr_bitmap(vcpu
);
8628 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8633 * Currently we do not handle the nested case where L2 has an
8634 * APIC access page of its own; that page is still pinned.
8635 * Hence, we skip the case where the VCPU is in guest mode _and_
8636 * L1 prepared an APIC access page for L2.
8638 * For the case where L1 and L2 share the same APIC access page
8639 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8640 * in the vmcs12), this function will only update either the vmcs01
8641 * or the vmcs02. If the former, the vmcs02 will be updated by
8642 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8643 * the next L2->L1 exit.
8645 if (!is_guest_mode(vcpu
) ||
8646 !nested_cpu_has2(get_vmcs12(&vmx
->vcpu
),
8647 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8648 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8649 vmx_flush_tlb_ept_only(vcpu
);
8653 static void vmx_hwapic_isr_update(struct kvm_vcpu
*vcpu
, int max_isr
)
8661 status
= vmcs_read16(GUEST_INTR_STATUS
);
8663 if (max_isr
!= old
) {
8665 status
|= max_isr
<< 8;
8666 vmcs_write16(GUEST_INTR_STATUS
, status
);
8670 static void vmx_set_rvi(int vector
)
8678 status
= vmcs_read16(GUEST_INTR_STATUS
);
8679 old
= (u8
)status
& 0xff;
8680 if ((u8
)vector
!= old
) {
8682 status
|= (u8
)vector
;
8683 vmcs_write16(GUEST_INTR_STATUS
, status
);
8687 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8689 if (!is_guest_mode(vcpu
)) {
8690 vmx_set_rvi(max_irr
);
8698 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8701 if (nested_exit_on_intr(vcpu
))
8705 * Else, fall back to pre-APICv interrupt injection since L2
8706 * is run without virtual interrupt delivery.
8708 if (!kvm_event_needs_reinjection(vcpu
) &&
8709 vmx_interrupt_allowed(vcpu
)) {
8710 kvm_queue_interrupt(vcpu
, max_irr
, false);
8711 vmx_inject_irq(vcpu
);
8715 static int vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
8717 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8720 WARN_ON(!vcpu
->arch
.apicv_active
);
8721 if (pi_test_on(&vmx
->pi_desc
)) {
8722 pi_clear_on(&vmx
->pi_desc
);
8724 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
8725 * But on x86 this is just a compiler barrier anyway.
8727 smp_mb__after_atomic();
8728 max_irr
= kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
8730 max_irr
= kvm_lapic_find_highest_irr(vcpu
);
8732 vmx_hwapic_irr_update(vcpu
, max_irr
);
8736 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8738 if (!kvm_vcpu_apicv_active(vcpu
))
8741 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8742 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8743 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8744 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8747 static void vmx_apicv_post_state_restore(struct kvm_vcpu
*vcpu
)
8749 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8751 pi_clear_on(&vmx
->pi_desc
);
8752 memset(vmx
->pi_desc
.pir
, 0, sizeof(vmx
->pi_desc
.pir
));
8755 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8757 u32 exit_intr_info
= 0;
8758 u16 basic_exit_reason
= (u16
)vmx
->exit_reason
;
8760 if (!(basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8761 || basic_exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8764 if (!(vmx
->exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
))
8765 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8766 vmx
->exit_intr_info
= exit_intr_info
;
8768 /* if exit due to PF check for async PF */
8769 if (is_page_fault(exit_intr_info
))
8770 vmx
->vcpu
.arch
.apf
.host_apf_reason
= kvm_read_and_reset_pf_reason();
8772 /* Handle machine checks before interrupts are enabled */
8773 if (basic_exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
||
8774 is_machine_check(exit_intr_info
))
8775 kvm_machine_check();
8777 /* We need to handle NMIs before interrupts are enabled */
8778 if (is_nmi(exit_intr_info
)) {
8779 kvm_before_handle_nmi(&vmx
->vcpu
);
8781 kvm_after_handle_nmi(&vmx
->vcpu
);
8785 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8787 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8788 register void *__sp
asm(_ASM_SP
);
8790 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8791 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8792 unsigned int vector
;
8793 unsigned long entry
;
8795 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8796 #ifdef CONFIG_X86_64
8800 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8801 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8802 entry
= gate_offset(desc
);
8804 #ifdef CONFIG_X86_64
8805 "mov %%" _ASM_SP
", %[sp]\n\t"
8806 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8811 __ASM_SIZE(push
) " $%c[cs]\n\t"
8812 "call *%[entry]\n\t"
8814 #ifdef CONFIG_X86_64
8820 [ss
]"i"(__KERNEL_DS
),
8821 [cs
]"i"(__KERNEL_CS
)
8825 STACK_FRAME_NON_STANDARD(vmx_handle_external_intr
);
8827 static bool vmx_has_high_real_mode_segbase(void)
8829 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8832 static bool vmx_mpx_supported(void)
8834 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8835 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8838 static bool vmx_xsaves_supported(void)
8840 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8841 SECONDARY_EXEC_XSAVES
;
8844 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8849 bool idtv_info_valid
;
8851 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8853 if (vmx
->loaded_vmcs
->nmi_known_unmasked
)
8856 * Can't use vmx->exit_intr_info since we're not sure what
8857 * the exit reason is.
8859 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8860 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8861 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8863 * SDM 3: 27.7.1.2 (September 2008)
8864 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8865 * a guest IRET fault.
8866 * SDM 3: 23.2.2 (September 2008)
8867 * Bit 12 is undefined in any of the following cases:
8868 * If the VM exit sets the valid bit in the IDT-vectoring
8869 * information field.
8870 * If the VM exit is due to a double fault.
8872 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8873 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8874 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8875 GUEST_INTR_STATE_NMI
);
8877 vmx
->loaded_vmcs
->nmi_known_unmasked
=
8878 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8879 & GUEST_INTR_STATE_NMI
);
8882 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8883 u32 idt_vectoring_info
,
8884 int instr_len_field
,
8885 int error_code_field
)
8889 bool idtv_info_valid
;
8891 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8893 vcpu
->arch
.nmi_injected
= false;
8894 kvm_clear_exception_queue(vcpu
);
8895 kvm_clear_interrupt_queue(vcpu
);
8897 if (!idtv_info_valid
)
8900 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8902 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8903 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8906 case INTR_TYPE_NMI_INTR
:
8907 vcpu
->arch
.nmi_injected
= true;
8909 * SDM 3: 27.7.1.2 (September 2008)
8910 * Clear bit "block by NMI" before VM entry if a NMI
8913 vmx_set_nmi_mask(vcpu
, false);
8915 case INTR_TYPE_SOFT_EXCEPTION
:
8916 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8918 case INTR_TYPE_HARD_EXCEPTION
:
8919 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8920 u32 err
= vmcs_read32(error_code_field
);
8921 kvm_requeue_exception_e(vcpu
, vector
, err
);
8923 kvm_requeue_exception(vcpu
, vector
);
8925 case INTR_TYPE_SOFT_INTR
:
8926 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8928 case INTR_TYPE_EXT_INTR
:
8929 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8936 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8938 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8939 VM_EXIT_INSTRUCTION_LEN
,
8940 IDT_VECTORING_ERROR_CODE
);
8943 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8945 __vmx_complete_interrupts(vcpu
,
8946 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8947 VM_ENTRY_INSTRUCTION_LEN
,
8948 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8950 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8953 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8956 struct perf_guest_switch_msr
*msrs
;
8958 msrs
= perf_guest_get_msrs(&nr_msrs
);
8963 for (i
= 0; i
< nr_msrs
; i
++)
8964 if (msrs
[i
].host
== msrs
[i
].guest
)
8965 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8967 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8971 static void vmx_arm_hv_timer(struct kvm_vcpu
*vcpu
)
8973 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8977 if (vmx
->hv_deadline_tsc
== -1)
8981 if (vmx
->hv_deadline_tsc
> tscl
)
8982 /* sure to be 32 bit only because checked on set_hv_timer */
8983 delta_tsc
= (u32
)((vmx
->hv_deadline_tsc
- tscl
) >>
8984 cpu_preemption_timer_multi
);
8988 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE
, delta_tsc
);
8991 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8993 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8994 unsigned long debugctlmsr
, cr3
, cr4
;
8996 /* Don't enter VMX if guest state is invalid, let the exit handler
8997 start emulation until we arrive back to a valid state */
8998 if (vmx
->emulation_required
)
9001 if (vmx
->ple_window_dirty
) {
9002 vmx
->ple_window_dirty
= false;
9003 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
9006 if (vmx
->nested
.sync_shadow_vmcs
) {
9007 copy_vmcs12_to_shadow(vmx
);
9008 vmx
->nested
.sync_shadow_vmcs
= false;
9011 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9012 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
9013 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
9014 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
9016 cr3
= __get_current_cr3_fast();
9017 if (unlikely(cr3
!= vmx
->loaded_vmcs
->vmcs_host_cr3
)) {
9018 vmcs_writel(HOST_CR3
, cr3
);
9019 vmx
->loaded_vmcs
->vmcs_host_cr3
= cr3
;
9022 cr4
= cr4_read_shadow();
9023 if (unlikely(cr4
!= vmx
->loaded_vmcs
->vmcs_host_cr4
)) {
9024 vmcs_writel(HOST_CR4
, cr4
);
9025 vmx
->loaded_vmcs
->vmcs_host_cr4
= cr4
;
9028 /* When single-stepping over STI and MOV SS, we must clear the
9029 * corresponding interruptibility bits in the guest state. Otherwise
9030 * vmentry fails as it then expects bit 14 (BS) in pending debug
9031 * exceptions being set, but that's not correct for the guest debugging
9033 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
9034 vmx_set_interrupt_shadow(vcpu
, 0);
9036 if (static_cpu_has(X86_FEATURE_PKU
) &&
9037 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
) &&
9038 vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9039 __write_pkru(vcpu
->arch
.pkru
);
9041 atomic_switch_perf_msrs(vmx
);
9043 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL
))
9044 add_atomic_switch_msr(vmx
, MSR_IA32_SPEC_CTRL
,
9045 vcpu
->arch
.spec_ctrl
, FEATURE_ENABLE_IBRS
);
9047 debugctlmsr
= get_debugctlmsr();
9049 vmx_arm_hv_timer(vcpu
);
9051 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
9053 /* Store host registers */
9054 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
9055 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
9056 "push %%" _ASM_CX
" \n\t"
9057 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9059 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
9060 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
9062 /* Reload cr2 if changed */
9063 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
9064 "mov %%cr2, %%" _ASM_DX
" \n\t"
9065 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
9067 "mov %%" _ASM_AX
", %%cr2 \n\t"
9069 /* Check if vmlaunch of vmresume is needed */
9070 "cmpl $0, %c[launched](%0) \n\t"
9071 /* Load guest registers. Don't clobber flags. */
9072 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
9073 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
9074 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
9075 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
9076 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
9077 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
9078 #ifdef CONFIG_X86_64
9079 "mov %c[r8](%0), %%r8 \n\t"
9080 "mov %c[r9](%0), %%r9 \n\t"
9081 "mov %c[r10](%0), %%r10 \n\t"
9082 "mov %c[r11](%0), %%r11 \n\t"
9083 "mov %c[r12](%0), %%r12 \n\t"
9084 "mov %c[r13](%0), %%r13 \n\t"
9085 "mov %c[r14](%0), %%r14 \n\t"
9086 "mov %c[r15](%0), %%r15 \n\t"
9088 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
9090 /* Enter guest mode */
9092 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
9094 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
9096 /* Save guest registers, load host registers, keep flags */
9097 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
9099 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
9100 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
9101 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
9102 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
9103 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
9104 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
9105 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
9106 #ifdef CONFIG_X86_64
9107 "mov %%r8, %c[r8](%0) \n\t"
9108 "mov %%r9, %c[r9](%0) \n\t"
9109 "mov %%r10, %c[r10](%0) \n\t"
9110 "mov %%r11, %c[r11](%0) \n\t"
9111 "mov %%r12, %c[r12](%0) \n\t"
9112 "mov %%r13, %c[r13](%0) \n\t"
9113 "mov %%r14, %c[r14](%0) \n\t"
9114 "mov %%r15, %c[r15](%0) \n\t"
9116 "mov %%cr2, %%" _ASM_AX
" \n\t"
9117 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
9119 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
9120 "setbe %c[fail](%0) \n\t"
9121 ".pushsection .rodata \n\t"
9122 ".global vmx_return \n\t"
9123 "vmx_return: " _ASM_PTR
" 2b \n\t"
9125 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
9126 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
9127 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
9128 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
9129 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
9130 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
9131 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
9132 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
9133 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
9134 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
9135 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
9136 #ifdef CONFIG_X86_64
9137 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
9138 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
9139 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
9140 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
9141 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
9142 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
9143 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
9144 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
9146 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
9147 [wordsize
]"i"(sizeof(ulong
))
9149 #ifdef CONFIG_X86_64
9150 , "rax", "rbx", "rdi", "rsi"
9151 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
9153 , "eax", "ebx", "edi", "esi"
9157 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
9159 update_debugctlmsr(debugctlmsr
);
9161 #ifndef CONFIG_X86_64
9163 * The sysexit path does not restore ds/es, so we must set them to
9164 * a reasonable value ourselves.
9166 * We can't defer this to vmx_load_host_state() since that function
9167 * may be executed in interrupt context, which saves and restore segments
9168 * around it, nullifying its effect.
9170 loadsegment(ds
, __USER_DS
);
9171 loadsegment(es
, __USER_DS
);
9174 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
9175 | (1 << VCPU_EXREG_RFLAGS
)
9176 | (1 << VCPU_EXREG_PDPTR
)
9177 | (1 << VCPU_EXREG_SEGMENTS
)
9178 | (1 << VCPU_EXREG_CR3
));
9179 vcpu
->arch
.regs_dirty
= 0;
9181 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
9183 vmx
->loaded_vmcs
->launched
= 1;
9185 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
9188 * eager fpu is enabled if PKEY is supported and CR4 is switched
9189 * back on host, so it is safe to read guest PKRU from current
9192 if (static_cpu_has(X86_FEATURE_PKU
) &&
9193 kvm_read_cr4_bits(vcpu
, X86_CR4_PKE
)) {
9194 vcpu
->arch
.pkru
= __read_pkru();
9195 if (vcpu
->arch
.pkru
!= vmx
->host_pkru
)
9196 __write_pkru(vmx
->host_pkru
);
9200 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
9201 * we did not inject a still-pending event to L1 now because of
9202 * nested_run_pending, we need to re-enable this bit.
9204 if (vmx
->nested
.nested_run_pending
)
9205 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
9207 vmx
->nested
.nested_run_pending
= 0;
9209 vmx_complete_atomic_exit(vmx
);
9210 vmx_recover_nmi_blocking(vmx
);
9211 vmx_complete_interrupts(vmx
);
9213 STACK_FRAME_NON_STANDARD(vmx_vcpu_run
);
9215 static void vmx_switch_vmcs(struct kvm_vcpu
*vcpu
, struct loaded_vmcs
*vmcs
)
9217 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9220 if (vmx
->loaded_vmcs
== vmcs
)
9224 vmx
->loaded_vmcs
= vmcs
;
9226 vmx_vcpu_load(vcpu
, cpu
);
9232 * Ensure that the current vmcs of the logical processor is the
9233 * vmcs01 of the vcpu before calling free_nested().
9235 static void vmx_free_vcpu_nested(struct kvm_vcpu
*vcpu
)
9237 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9240 r
= vcpu_load(vcpu
);
9242 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
9247 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
9249 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9252 vmx_destroy_pml_buffer(vmx
);
9253 free_vpid(vmx
->vpid
);
9254 leave_guest_mode(vcpu
);
9255 vmx_free_vcpu_nested(vcpu
);
9256 free_loaded_vmcs(vmx
->loaded_vmcs
);
9257 kfree(vmx
->guest_msrs
);
9258 kvm_vcpu_uninit(vcpu
);
9259 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9262 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
9265 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
9269 return ERR_PTR(-ENOMEM
);
9271 vmx
->vpid
= allocate_vpid();
9273 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
9280 * If PML is turned on, failure on enabling PML just results in failure
9281 * of creating the vcpu, therefore we can simplify PML logic (by
9282 * avoiding dealing with cases, such as enabling PML partially on vcpus
9283 * for the guest, etc.
9286 vmx
->pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
9291 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
9292 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
9295 if (!vmx
->guest_msrs
)
9298 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
9299 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
9300 vmx
->loaded_vmcs
->shadow_vmcs
= NULL
;
9301 if (!vmx
->loaded_vmcs
->vmcs
)
9303 loaded_vmcs_init(vmx
->loaded_vmcs
);
9306 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
9307 vmx
->vcpu
.cpu
= cpu
;
9308 err
= vmx_vcpu_setup(vmx
);
9309 vmx_vcpu_put(&vmx
->vcpu
);
9313 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9314 err
= alloc_apic_access_page(kvm
);
9320 if (!kvm
->arch
.ept_identity_map_addr
)
9321 kvm
->arch
.ept_identity_map_addr
=
9322 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
9323 err
= init_rmode_identity_map(kvm
);
9329 nested_vmx_setup_ctls_msrs(vmx
);
9330 vmx
->nested
.vpid02
= allocate_vpid();
9333 vmx
->nested
.posted_intr_nv
= -1;
9334 vmx
->nested
.current_vmptr
= -1ull;
9336 vmx
->msr_ia32_feature_control_valid_bits
= FEATURE_CONTROL_LOCKED
;
9339 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
9340 * or POSTED_INTR_WAKEUP_VECTOR.
9342 vmx
->pi_desc
.nv
= POSTED_INTR_VECTOR
;
9343 vmx
->pi_desc
.sn
= 1;
9348 free_vpid(vmx
->nested
.vpid02
);
9349 free_loaded_vmcs(vmx
->loaded_vmcs
);
9351 kfree(vmx
->guest_msrs
);
9353 vmx_destroy_pml_buffer(vmx
);
9355 kvm_vcpu_uninit(&vmx
->vcpu
);
9357 free_vpid(vmx
->vpid
);
9358 kmem_cache_free(kvm_vcpu_cache
, vmx
);
9359 return ERR_PTR(err
);
9362 static void __init
vmx_check_processor_compat(void *rtn
)
9364 struct vmcs_config vmcs_conf
;
9367 if (setup_vmcs_config(&vmcs_conf
) < 0)
9369 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
9370 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
9371 smp_processor_id());
9376 static int get_ept_level(void)
9378 return VMX_EPT_DEFAULT_GAW
+ 1;
9381 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
9386 /* For VT-d and EPT combination
9387 * 1. MMIO: always map as UC
9389 * a. VT-d without snooping control feature: can't guarantee the
9390 * result, try to trust guest.
9391 * b. VT-d with snooping control feature: snooping control feature of
9392 * VT-d engine can guarantee the cache correctness. Just set it
9393 * to WB to keep consistent with host. So the same as item 3.
9394 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
9395 * consistent with host MTRR
9398 cache
= MTRR_TYPE_UNCACHABLE
;
9402 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
9403 ipat
= VMX_EPT_IPAT_BIT
;
9404 cache
= MTRR_TYPE_WRBACK
;
9408 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
9409 ipat
= VMX_EPT_IPAT_BIT
;
9410 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
9411 cache
= MTRR_TYPE_WRBACK
;
9413 cache
= MTRR_TYPE_UNCACHABLE
;
9417 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
9420 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
9423 static int vmx_get_lpage_level(void)
9425 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
9426 return PT_DIRECTORY_LEVEL
;
9428 /* For shadow and EPT supported 1GB page */
9429 return PT_PDPE_LEVEL
;
9432 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
9435 * These bits in the secondary execution controls field
9436 * are dynamic, the others are mostly based on the hypervisor
9437 * architecture and the guest's CPUID. Do not touch the
9441 SECONDARY_EXEC_SHADOW_VMCS
|
9442 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
9443 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9445 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
9447 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
9448 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
9452 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
9453 * (indicating "allowed-1") if they are supported in the guest's CPUID.
9455 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu
*vcpu
)
9457 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9458 struct kvm_cpuid_entry2
*entry
;
9460 vmx
->nested
.nested_vmx_cr0_fixed1
= 0xffffffff;
9461 vmx
->nested
.nested_vmx_cr4_fixed1
= X86_CR4_PCE
;
9463 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
9464 if (entry && (entry->_reg & (_cpuid_mask))) \
9465 vmx->nested.nested_vmx_cr4_fixed1 |= (_cr4_mask); \
9468 entry
= kvm_find_cpuid_entry(vcpu
, 0x1, 0);
9469 cr4_fixed1_update(X86_CR4_VME
, edx
, bit(X86_FEATURE_VME
));
9470 cr4_fixed1_update(X86_CR4_PVI
, edx
, bit(X86_FEATURE_VME
));
9471 cr4_fixed1_update(X86_CR4_TSD
, edx
, bit(X86_FEATURE_TSC
));
9472 cr4_fixed1_update(X86_CR4_DE
, edx
, bit(X86_FEATURE_DE
));
9473 cr4_fixed1_update(X86_CR4_PSE
, edx
, bit(X86_FEATURE_PSE
));
9474 cr4_fixed1_update(X86_CR4_PAE
, edx
, bit(X86_FEATURE_PAE
));
9475 cr4_fixed1_update(X86_CR4_MCE
, edx
, bit(X86_FEATURE_MCE
));
9476 cr4_fixed1_update(X86_CR4_PGE
, edx
, bit(X86_FEATURE_PGE
));
9477 cr4_fixed1_update(X86_CR4_OSFXSR
, edx
, bit(X86_FEATURE_FXSR
));
9478 cr4_fixed1_update(X86_CR4_OSXMMEXCPT
, edx
, bit(X86_FEATURE_XMM
));
9479 cr4_fixed1_update(X86_CR4_VMXE
, ecx
, bit(X86_FEATURE_VMX
));
9480 cr4_fixed1_update(X86_CR4_SMXE
, ecx
, bit(X86_FEATURE_SMX
));
9481 cr4_fixed1_update(X86_CR4_PCIDE
, ecx
, bit(X86_FEATURE_PCID
));
9482 cr4_fixed1_update(X86_CR4_OSXSAVE
, ecx
, bit(X86_FEATURE_XSAVE
));
9484 entry
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9485 cr4_fixed1_update(X86_CR4_FSGSBASE
, ebx
, bit(X86_FEATURE_FSGSBASE
));
9486 cr4_fixed1_update(X86_CR4_SMEP
, ebx
, bit(X86_FEATURE_SMEP
));
9487 cr4_fixed1_update(X86_CR4_SMAP
, ebx
, bit(X86_FEATURE_SMAP
));
9488 cr4_fixed1_update(X86_CR4_PKE
, ecx
, bit(X86_FEATURE_PKU
));
9489 /* TODO: Use X86_CR4_UMIP and X86_FEATURE_UMIP macros */
9490 cr4_fixed1_update(bit(11), ecx
, bit(2));
9492 #undef cr4_fixed1_update
9495 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
9497 struct kvm_cpuid_entry2
*best
;
9498 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9499 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
9501 if (vmx_rdtscp_supported()) {
9502 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
9503 if (!rdtscp_enabled
)
9504 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
9508 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9509 SECONDARY_EXEC_RDTSCP
;
9511 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9512 ~SECONDARY_EXEC_RDTSCP
;
9516 /* Exposing INVPCID only when PCID is exposed */
9517 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9518 if (vmx_invpcid_supported() &&
9519 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9520 !guest_cpuid_has_pcid(vcpu
))) {
9521 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9524 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9527 if (cpu_has_secondary_exec_ctrls())
9528 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9530 if (nested_vmx_allowed(vcpu
))
9531 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
9532 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9534 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
9535 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
9537 if (nested_vmx_allowed(vcpu
))
9538 nested_vmx_cr_fixed1_bits_update(vcpu
);
9541 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9543 if (func
== 1 && nested
)
9544 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9547 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9548 struct x86_exception
*fault
)
9550 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9551 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9553 unsigned long exit_qualification
= vcpu
->arch
.exit_qualification
;
9555 if (vmx
->nested
.pml_full
) {
9556 exit_reason
= EXIT_REASON_PML_FULL
;
9557 vmx
->nested
.pml_full
= false;
9558 exit_qualification
&= INTR_INFO_UNBLOCK_NMI
;
9559 } else if (fault
->error_code
& PFERR_RSVD_MASK
)
9560 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9562 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9564 nested_vmx_vmexit(vcpu
, exit_reason
, 0, exit_qualification
);
9565 vmcs12
->guest_physical_address
= fault
->address
;
9568 static bool nested_ept_ad_enabled(struct kvm_vcpu
*vcpu
)
9570 return nested_ept_get_cr3(vcpu
) & VMX_EPT_AD_ENABLE_BIT
;
9573 /* Callbacks for nested_ept_init_mmu_context: */
9575 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9577 /* return the page table to be shadowed - in our case, EPT12 */
9578 return get_vmcs12(vcpu
)->ept_pointer
;
9581 static int nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9585 WARN_ON(mmu_is_nested(vcpu
));
9586 wants_ad
= nested_ept_ad_enabled(vcpu
);
9587 if (wants_ad
&& !enable_ept_ad_bits
)
9590 kvm_mmu_unload(vcpu
);
9591 kvm_init_shadow_ept_mmu(vcpu
,
9592 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9593 VMX_EPT_EXECUTE_ONLY_BIT
,
9595 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9596 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9597 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9599 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9603 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9605 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9608 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9611 bool inequality
, bit
;
9613 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9615 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9616 vmcs12
->page_fault_error_code_match
;
9617 return inequality
^ bit
;
9620 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9621 struct x86_exception
*fault
)
9623 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9625 WARN_ON(!is_guest_mode(vcpu
));
9627 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
)) {
9628 vmcs12
->vm_exit_intr_error_code
= fault
->error_code
;
9629 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9630 PF_VECTOR
| INTR_TYPE_HARD_EXCEPTION
|
9631 INTR_INFO_DELIVER_CODE_MASK
| INTR_INFO_VALID_MASK
,
9634 kvm_inject_page_fault(vcpu
, fault
);
9638 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9639 struct vmcs12
*vmcs12
);
9641 static void nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9642 struct vmcs12
*vmcs12
)
9644 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9647 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9649 * Translate L1 physical address to host physical
9650 * address for vmcs02. Keep the page pinned, so this
9651 * physical address remains valid. We keep a reference
9652 * to it so we can release it later.
9654 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9655 nested_release_page(vmx
->nested
.apic_access_page
);
9656 vmx
->nested
.apic_access_page
=
9657 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9659 * If translation failed, no matter: This feature asks
9660 * to exit when accessing the given address, and if it
9661 * can never be accessed, this feature won't do
9664 if (vmx
->nested
.apic_access_page
) {
9665 hpa
= page_to_phys(vmx
->nested
.apic_access_page
);
9666 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
9668 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
9669 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9671 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9672 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9673 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
9674 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
9675 kvm_vcpu_reload_apic_access_page(vcpu
);
9678 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9679 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9680 nested_release_page(vmx
->nested
.virtual_apic_page
);
9681 vmx
->nested
.virtual_apic_page
=
9682 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9685 * If translation failed, VM entry will fail because
9686 * prepare_vmcs02 set VIRTUAL_APIC_PAGE_ADDR to -1ull.
9687 * Failing the vm entry is _not_ what the processor
9688 * does but it's basically the only possibility we
9689 * have. We could still enter the guest if CR8 load
9690 * exits are enabled, CR8 store exits are enabled, and
9691 * virtualize APIC access is disabled; in this case
9692 * the processor would never use the TPR shadow and we
9693 * could simply clear the bit from the execution
9694 * control. But such a configuration is useless, so
9695 * let's keep the code simple.
9697 if (vmx
->nested
.virtual_apic_page
) {
9698 hpa
= page_to_phys(vmx
->nested
.virtual_apic_page
);
9699 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, hpa
);
9703 if (nested_cpu_has_posted_intr(vmcs12
)) {
9704 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9705 kunmap(vmx
->nested
.pi_desc_page
);
9706 nested_release_page(vmx
->nested
.pi_desc_page
);
9708 vmx
->nested
.pi_desc_page
=
9709 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9710 vmx
->nested
.pi_desc
=
9711 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9712 if (!vmx
->nested
.pi_desc
) {
9713 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9716 vmx
->nested
.pi_desc
=
9717 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9718 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9720 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9721 page_to_phys(vmx
->nested
.pi_desc_page
) +
9722 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9725 if (cpu_has_vmx_msr_bitmap() &&
9726 nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
) &&
9727 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
))
9730 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL
,
9731 CPU_BASED_USE_MSR_BITMAPS
);
9734 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9736 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9739 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9742 /* Make sure short timeouts reliably trigger an immediate vmexit.
9743 * hrtimer_start does not guarantee this. */
9744 if (preemption_timeout
<= 1) {
9745 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9749 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9750 preemption_timeout
*= 1000000;
9751 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9752 hrtimer_start(&vmx
->nested
.preemption_timer
,
9753 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9756 static int nested_vmx_check_io_bitmap_controls(struct kvm_vcpu
*vcpu
,
9757 struct vmcs12
*vmcs12
)
9759 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
9762 if (!page_address_valid(vcpu
, vmcs12
->io_bitmap_a
) ||
9763 !page_address_valid(vcpu
, vmcs12
->io_bitmap_b
))
9769 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9770 struct vmcs12
*vmcs12
)
9772 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9775 if (!page_address_valid(vcpu
, vmcs12
->msr_bitmap
))
9782 * Merge L0's and L1's MSR bitmap, return false to indicate that
9783 * we do not use the hardware.
9785 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9786 struct vmcs12
*vmcs12
)
9790 unsigned long *msr_bitmap_l1
;
9791 unsigned long *msr_bitmap_l0
= to_vmx(vcpu
)->nested
.msr_bitmap
;
9793 /* This shortcut is ok because we support only x2APIC MSRs so far. */
9794 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9797 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9800 msr_bitmap_l1
= (unsigned long *)kmap(page
);
9802 memset(msr_bitmap_l0
, 0xff, PAGE_SIZE
);
9804 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9805 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9806 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9807 nested_vmx_disable_intercept_for_msr(
9808 msr_bitmap_l1
, msr_bitmap_l0
,
9811 nested_vmx_disable_intercept_for_msr(
9812 msr_bitmap_l1
, msr_bitmap_l0
,
9813 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9814 MSR_TYPE_R
| MSR_TYPE_W
);
9816 if (nested_cpu_has_vid(vmcs12
)) {
9817 nested_vmx_disable_intercept_for_msr(
9818 msr_bitmap_l1
, msr_bitmap_l0
,
9819 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9821 nested_vmx_disable_intercept_for_msr(
9822 msr_bitmap_l1
, msr_bitmap_l0
,
9823 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9828 nested_release_page_clean(page
);
9833 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9834 struct vmcs12
*vmcs12
)
9836 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9837 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9838 !nested_cpu_has_vid(vmcs12
) &&
9839 !nested_cpu_has_posted_intr(vmcs12
))
9843 * If virtualize x2apic mode is enabled,
9844 * virtualize apic access must be disabled.
9846 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9847 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9851 * If virtual interrupt delivery is enabled,
9852 * we must exit on external interrupts.
9854 if (nested_cpu_has_vid(vmcs12
) &&
9855 !nested_exit_on_intr(vcpu
))
9859 * bits 15:8 should be zero in posted_intr_nv,
9860 * the descriptor address has been already checked
9861 * in nested_get_vmcs12_pages.
9863 if (nested_cpu_has_posted_intr(vmcs12
) &&
9864 (!nested_cpu_has_vid(vmcs12
) ||
9865 !nested_exit_intr_ack_set(vcpu
) ||
9866 vmcs12
->posted_intr_nv
& 0xff00))
9869 /* tpr shadow is needed by all apicv features. */
9870 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9876 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9877 unsigned long count_field
,
9878 unsigned long addr_field
)
9883 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9884 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9890 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9891 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9892 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9893 pr_debug_ratelimited(
9894 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9895 addr_field
, maxphyaddr
, count
, addr
);
9901 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9902 struct vmcs12
*vmcs12
)
9904 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9905 vmcs12
->vm_exit_msr_store_count
== 0 &&
9906 vmcs12
->vm_entry_msr_load_count
== 0)
9907 return 0; /* Fast path */
9908 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9909 VM_EXIT_MSR_LOAD_ADDR
) ||
9910 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9911 VM_EXIT_MSR_STORE_ADDR
) ||
9912 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9913 VM_ENTRY_MSR_LOAD_ADDR
))
9918 static int nested_vmx_check_pml_controls(struct kvm_vcpu
*vcpu
,
9919 struct vmcs12
*vmcs12
)
9921 u64 address
= vmcs12
->pml_address
;
9922 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9924 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_PML
)) {
9925 if (!nested_cpu_has_ept(vmcs12
) ||
9926 !IS_ALIGNED(address
, 4096) ||
9927 address
>> maxphyaddr
)
9934 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9935 struct vmx_msr_entry
*e
)
9937 /* x2APIC MSR accesses are not allowed */
9938 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9940 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9941 e
->index
== MSR_IA32_UCODE_REV
)
9943 if (e
->reserved
!= 0)
9948 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9949 struct vmx_msr_entry
*e
)
9951 if (e
->index
== MSR_FS_BASE
||
9952 e
->index
== MSR_GS_BASE
||
9953 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9954 nested_vmx_msr_check_common(vcpu
, e
))
9959 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9960 struct vmx_msr_entry
*e
)
9962 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9963 nested_vmx_msr_check_common(vcpu
, e
))
9969 * Load guest's/host's msr at nested entry/exit.
9970 * return 0 for success, entry index for failure.
9972 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9975 struct vmx_msr_entry e
;
9976 struct msr_data msr
;
9978 msr
.host_initiated
= false;
9979 for (i
= 0; i
< count
; i
++) {
9980 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9982 pr_debug_ratelimited(
9983 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9984 __func__
, i
, gpa
+ i
* sizeof(e
));
9987 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9988 pr_debug_ratelimited(
9989 "%s check failed (%u, 0x%x, 0x%x)\n",
9990 __func__
, i
, e
.index
, e
.reserved
);
9993 msr
.index
= e
.index
;
9995 if (kvm_set_msr(vcpu
, &msr
)) {
9996 pr_debug_ratelimited(
9997 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9998 __func__
, i
, e
.index
, e
.value
);
10007 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
10010 struct vmx_msr_entry e
;
10012 for (i
= 0; i
< count
; i
++) {
10013 struct msr_data msr_info
;
10014 if (kvm_vcpu_read_guest(vcpu
,
10015 gpa
+ i
* sizeof(e
),
10016 &e
, 2 * sizeof(u32
))) {
10017 pr_debug_ratelimited(
10018 "%s cannot read MSR entry (%u, 0x%08llx)\n",
10019 __func__
, i
, gpa
+ i
* sizeof(e
));
10022 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
10023 pr_debug_ratelimited(
10024 "%s check failed (%u, 0x%x, 0x%x)\n",
10025 __func__
, i
, e
.index
, e
.reserved
);
10028 msr_info
.host_initiated
= false;
10029 msr_info
.index
= e
.index
;
10030 if (kvm_get_msr(vcpu
, &msr_info
)) {
10031 pr_debug_ratelimited(
10032 "%s cannot read MSR (%u, 0x%x)\n",
10033 __func__
, i
, e
.index
);
10036 if (kvm_vcpu_write_guest(vcpu
,
10037 gpa
+ i
* sizeof(e
) +
10038 offsetof(struct vmx_msr_entry
, value
),
10039 &msr_info
.data
, sizeof(msr_info
.data
))) {
10040 pr_debug_ratelimited(
10041 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
10042 __func__
, i
, e
.index
, msr_info
.data
);
10049 static bool nested_cr3_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
10051 unsigned long invalid_mask
;
10053 invalid_mask
= (~0ULL) << cpuid_maxphyaddr(vcpu
);
10054 return (val
& invalid_mask
) == 0;
10058 * Load guest's/host's cr3 at nested entry/exit. nested_ept is true if we are
10059 * emulating VM entry into a guest with EPT enabled.
10060 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10061 * is assigned to entry_failure_code on failure.
10063 static int nested_vmx_load_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
, bool nested_ept
,
10064 u32
*entry_failure_code
)
10066 if (cr3
!= kvm_read_cr3(vcpu
) || (!nested_ept
&& pdptrs_changed(vcpu
))) {
10067 if (!nested_cr3_valid(vcpu
, cr3
)) {
10068 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10073 * If PAE paging and EPT are both on, CR3 is not used by the CPU and
10074 * must not be dereferenced.
10076 if (!is_long_mode(vcpu
) && is_pae(vcpu
) && is_paging(vcpu
) &&
10078 if (!load_pdptrs(vcpu
, vcpu
->arch
.walk_mmu
, cr3
)) {
10079 *entry_failure_code
= ENTRY_FAIL_PDPTE
;
10084 vcpu
->arch
.cr3
= cr3
;
10085 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
10088 kvm_mmu_reset_context(vcpu
);
10093 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
10094 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
10095 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
10096 * guest in a way that will both be appropriate to L1's requests, and our
10097 * needs. In addition to modifying the active vmcs (which is vmcs02), this
10098 * function also has additional necessary side-effects, like setting various
10099 * vcpu->arch fields.
10100 * Returns 0 on success, 1 on failure. Invalid state exit qualification code
10101 * is assigned to entry_failure_code on failure.
10103 static int prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10104 bool from_vmentry
, u32
*entry_failure_code
)
10106 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10107 u32 exec_control
, vmcs12_exec_ctrl
;
10109 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
10110 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
10111 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
10112 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
10113 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
10114 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
10115 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
10116 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
10117 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
10118 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
10119 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
10120 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
10121 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
10122 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
10123 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
10124 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
10125 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
10126 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
10127 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
10128 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
10129 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
10130 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
10131 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
10132 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
10133 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
10134 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
10135 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
10136 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
10137 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
10138 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
10139 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
10140 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
10141 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
10142 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
10143 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
10144 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
10146 if (from_vmentry
&&
10147 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
)) {
10148 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
10149 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
10151 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
10152 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
10154 if (from_vmentry
) {
10155 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
10156 vmcs12
->vm_entry_intr_info_field
);
10157 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
10158 vmcs12
->vm_entry_exception_error_code
);
10159 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
10160 vmcs12
->vm_entry_instruction_len
);
10161 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
10162 vmcs12
->guest_interruptibility_info
);
10163 vmx
->loaded_vmcs
->nmi_known_unmasked
=
10164 !(vmcs12
->guest_interruptibility_info
& GUEST_INTR_STATE_NMI
);
10166 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
10168 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
10169 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
10170 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
10171 vmcs12
->guest_pending_dbg_exceptions
);
10172 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
10173 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
10175 if (nested_cpu_has_xsaves(vmcs12
))
10176 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
10177 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
10179 exec_control
= vmcs12
->pin_based_vm_exec_control
;
10181 /* Preemption timer setting is only taken from vmcs01. */
10182 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10183 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
10184 if (vmx
->hv_deadline_tsc
== -1)
10185 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
10187 /* Posted interrupts setting is only taken from vmcs12. */
10188 if (nested_cpu_has_posted_intr(vmcs12
)) {
10189 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
10190 vmx
->nested
.pi_pending
= false;
10191 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_NESTED_VECTOR
);
10193 exec_control
&= ~PIN_BASED_POSTED_INTR
;
10196 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
10198 vmx
->nested
.preemption_timer_expired
= false;
10199 if (nested_cpu_has_preemption_timer(vmcs12
))
10200 vmx_start_preemption_timer(vcpu
);
10203 * Whether page-faults are trapped is determined by a combination of
10204 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
10205 * If enable_ept, L0 doesn't care about page faults and we should
10206 * set all of these to L1's desires. However, if !enable_ept, L0 does
10207 * care about (at least some) page faults, and because it is not easy
10208 * (if at all possible?) to merge L0 and L1's desires, we simply ask
10209 * to exit on each and every L2 page fault. This is done by setting
10210 * MASK=MATCH=0 and (see below) EB.PF=1.
10211 * Note that below we don't need special code to set EB.PF beyond the
10212 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
10213 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
10214 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
10216 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
10217 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
10218 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
10219 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
10221 if (cpu_has_secondary_exec_ctrls()) {
10222 exec_control
= vmx_secondary_exec_control(vmx
);
10224 /* Take the following fields only from vmcs12 */
10225 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
10226 SECONDARY_EXEC_RDTSCP
|
10227 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
10228 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
10229 if (nested_cpu_has(vmcs12
,
10230 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
)) {
10231 vmcs12_exec_ctrl
= vmcs12
->secondary_vm_exec_control
&
10232 ~SECONDARY_EXEC_ENABLE_PML
;
10233 exec_control
|= vmcs12_exec_ctrl
;
10236 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
10237 vmcs_write64(EOI_EXIT_BITMAP0
,
10238 vmcs12
->eoi_exit_bitmap0
);
10239 vmcs_write64(EOI_EXIT_BITMAP1
,
10240 vmcs12
->eoi_exit_bitmap1
);
10241 vmcs_write64(EOI_EXIT_BITMAP2
,
10242 vmcs12
->eoi_exit_bitmap2
);
10243 vmcs_write64(EOI_EXIT_BITMAP3
,
10244 vmcs12
->eoi_exit_bitmap3
);
10245 vmcs_write16(GUEST_INTR_STATUS
,
10246 vmcs12
->guest_intr_status
);
10250 * Write an illegal value to APIC_ACCESS_ADDR. Later,
10251 * nested_get_vmcs12_pages will either fix it up or
10252 * remove the VM execution control.
10254 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)
10255 vmcs_write64(APIC_ACCESS_ADDR
, -1ull);
10257 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
10262 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
10263 * Some constant fields are set here by vmx_set_constant_host_state().
10264 * Other fields are different per CPU, and will be set later when
10265 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
10267 vmx_set_constant_host_state(vmx
);
10270 * Set the MSR load/store lists to match L0's settings.
10272 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
10273 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10274 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
10275 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
10276 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
10279 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
10280 * entry, but only if the current (host) sp changed from the value
10281 * we wrote last (vmx->host_rsp). This cache is no longer relevant
10282 * if we switch vmcs, and rather than hold a separate cache per vmcs,
10283 * here we just force the write to happen on entry.
10287 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
10288 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
10289 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
10290 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
10291 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
10294 * Write an illegal value to VIRTUAL_APIC_PAGE_ADDR. Later, if
10295 * nested_get_vmcs12_pages can't fix it up, the illegal value
10296 * will result in a VM entry failure.
10298 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
10299 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, -1ull);
10300 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
10302 #ifdef CONFIG_X86_64
10303 exec_control
|= CPU_BASED_CR8_LOAD_EXITING
|
10304 CPU_BASED_CR8_STORE_EXITING
;
10309 * Merging of IO bitmap not currently supported.
10310 * Rather, exit every time.
10312 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
10313 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
10315 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
10317 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
10318 * bitwise-or of what L1 wants to trap for L2, and what we want to
10319 * trap. Note that CR0.TS also needs updating - we do this later.
10321 update_exception_bitmap(vcpu
);
10322 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
10323 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10325 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
10326 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
10327 * bits are further modified by vmx_set_efer() below.
10329 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
10331 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
10332 * emulated by vmx_set_efer(), below.
10334 vm_entry_controls_init(vmx
,
10335 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
10336 ~VM_ENTRY_IA32E_MODE
) |
10337 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
10339 if (from_vmentry
&&
10340 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
)) {
10341 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
10342 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
10343 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
10344 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
10347 set_cr4_guest_host_mask(vmx
);
10349 if (from_vmentry
&&
10350 vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
10351 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
10353 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
10354 vmcs_write64(TSC_OFFSET
,
10355 vcpu
->arch
.tsc_offset
+ vmcs12
->tsc_offset
);
10357 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
10358 if (kvm_has_tsc_control
)
10359 decache_tsc_multiplier(vmx
);
10363 * There is no direct mapping between vpid02 and vpid12, the
10364 * vpid02 is per-vCPU for L0 and reused while the value of
10365 * vpid12 is changed w/ one invvpid during nested vmentry.
10366 * The vpid12 is allocated by L1 for L2, so it will not
10367 * influence global bitmap(for vpid01 and vpid02 allocation)
10368 * even if spawn a lot of nested vCPUs.
10370 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
10371 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
10372 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
10373 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
10374 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
10377 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
10378 vmx_flush_tlb(vcpu
);
10385 * Conceptually we want to copy the PML address and index from
10386 * vmcs01 here, and then back to vmcs01 on nested vmexit. But,
10387 * since we always flush the log on each vmexit, this happens
10388 * to be equivalent to simply resetting the fields in vmcs02.
10390 ASSERT(vmx
->pml_pg
);
10391 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
10392 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
10395 if (nested_cpu_has_ept(vmcs12
)) {
10396 if (nested_ept_init_mmu_context(vcpu
)) {
10397 *entry_failure_code
= ENTRY_FAIL_DEFAULT
;
10400 } else if (nested_cpu_has2(vmcs12
,
10401 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
10402 vmx_flush_tlb_ept_only(vcpu
);
10406 * This sets GUEST_CR0 to vmcs12->guest_cr0, possibly modifying those
10407 * bits which we consider mandatory enabled.
10408 * The CR0_READ_SHADOW is what L2 should have expected to read given
10409 * the specifications by L1; It's not enough to take
10410 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
10411 * have more bits than L1 expected.
10413 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
10414 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
10416 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
10417 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
10419 if (from_vmentry
&&
10420 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
))
10421 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
10422 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
10423 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10425 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10426 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
10427 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10429 /* Shadow page tables on either EPT or shadow page tables. */
10430 if (nested_vmx_load_cr3(vcpu
, vmcs12
->guest_cr3
, nested_cpu_has_ept(vmcs12
),
10431 entry_failure_code
))
10435 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
10438 * L1 may access the L2's PDPTR, so save them to construct vmcs12
10441 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
10442 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
10443 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
10444 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
10447 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
10448 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
10452 static int check_vmentry_prereqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10456 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
10457 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
)
10458 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10460 if (nested_vmx_check_io_bitmap_controls(vcpu
, vmcs12
))
10461 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10463 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
))
10464 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10466 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
))
10467 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10469 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
))
10470 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10472 if (nested_vmx_check_pml_controls(vcpu
, vmcs12
))
10473 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10475 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
10476 vmx
->nested
.nested_vmx_procbased_ctls_low
,
10477 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
10478 (nested_cpu_has(vmcs12
, CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
10479 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
10480 vmx
->nested
.nested_vmx_secondary_ctls_low
,
10481 vmx
->nested
.nested_vmx_secondary_ctls_high
)) ||
10482 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
10483 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
10484 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
10485 !vmx_control_verify(vmcs12
->vm_exit_controls
,
10486 vmx
->nested
.nested_vmx_exit_ctls_low
,
10487 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
10488 !vmx_control_verify(vmcs12
->vm_entry_controls
,
10489 vmx
->nested
.nested_vmx_entry_ctls_low
,
10490 vmx
->nested
.nested_vmx_entry_ctls_high
))
10491 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10493 if (vmcs12
->cr3_target_count
> nested_cpu_vmx_misc_cr3_count(vcpu
))
10494 return VMXERR_ENTRY_INVALID_CONTROL_FIELD
;
10496 if (!nested_host_cr0_valid(vcpu
, vmcs12
->host_cr0
) ||
10497 !nested_host_cr4_valid(vcpu
, vmcs12
->host_cr4
) ||
10498 !nested_cr3_valid(vcpu
, vmcs12
->host_cr3
))
10499 return VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
;
10504 static int check_vmentry_postreqs(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10509 *exit_qual
= ENTRY_FAIL_DEFAULT
;
10511 if (!nested_guest_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
10512 !nested_guest_cr4_valid(vcpu
, vmcs12
->guest_cr4
))
10515 if (!nested_cpu_has2(vmcs12
, SECONDARY_EXEC_SHADOW_VMCS
) &&
10516 vmcs12
->vmcs_link_pointer
!= -1ull) {
10517 *exit_qual
= ENTRY_FAIL_VMCS_LINK_PTR
;
10522 * If the load IA32_EFER VM-entry control is 1, the following checks
10523 * are performed on the field for the IA32_EFER MSR:
10524 * - Bits reserved in the IA32_EFER MSR must be 0.
10525 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
10526 * the IA-32e mode guest VM-exit control. It must also be identical
10527 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
10530 if (to_vmx(vcpu
)->nested
.nested_run_pending
&&
10531 (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)) {
10532 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
10533 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
10534 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
10535 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
10536 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
)))
10541 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10542 * IA32_EFER MSR must be 0 in the field for that register. In addition,
10543 * the values of the LMA and LME bits in the field must each be that of
10544 * the host address-space size VM-exit control.
10546 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
10547 ia32e
= (vmcs12
->vm_exit_controls
&
10548 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
10549 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
10550 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
10551 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
))
10558 static int enter_vmx_non_root_mode(struct kvm_vcpu
*vcpu
, bool from_vmentry
)
10560 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10561 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10562 struct loaded_vmcs
*vmcs02
;
10566 vmcs02
= nested_get_current_vmcs02(vmx
);
10570 enter_guest_mode(vcpu
);
10572 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
10573 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10575 vmx_switch_vmcs(vcpu
, vmcs02
);
10576 vmx_segment_cache_clear(vmx
);
10578 if (prepare_vmcs02(vcpu
, vmcs12
, from_vmentry
, &exit_qual
)) {
10579 leave_guest_mode(vcpu
);
10580 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10581 nested_vmx_entry_failure(vcpu
, vmcs12
,
10582 EXIT_REASON_INVALID_STATE
, exit_qual
);
10586 nested_get_vmcs12_pages(vcpu
, vmcs12
);
10588 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10589 vmcs12
->vm_entry_msr_load_addr
,
10590 vmcs12
->vm_entry_msr_load_count
);
10591 if (msr_entry_idx
) {
10592 leave_guest_mode(vcpu
);
10593 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
10594 nested_vmx_entry_failure(vcpu
, vmcs12
,
10595 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10600 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10601 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10602 * returned as far as L1 is concerned. It will only return (and set
10603 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10609 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
10610 * for running an L2 nested guest.
10612 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
10614 struct vmcs12
*vmcs12
;
10615 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10616 u32 interrupt_shadow
= vmx_get_interrupt_shadow(vcpu
);
10620 if (!nested_vmx_check_permission(vcpu
))
10623 if (!nested_vmx_check_vmcs12(vcpu
))
10626 vmcs12
= get_vmcs12(vcpu
);
10628 if (enable_shadow_vmcs
)
10629 copy_shadow_to_vmcs12(vmx
);
10632 * The nested entry process starts with enforcing various prerequisites
10633 * on vmcs12 as required by the Intel SDM, and act appropriately when
10634 * they fail: As the SDM explains, some conditions should cause the
10635 * instruction to fail, while others will cause the instruction to seem
10636 * to succeed, but return an EXIT_REASON_INVALID_STATE.
10637 * To speed up the normal (success) code path, we should avoid checking
10638 * for misconfigurations which will anyway be caught by the processor
10639 * when using the merged vmcs02.
10641 if (interrupt_shadow
& KVM_X86_SHADOW_INT_MOV_SS
) {
10642 nested_vmx_failValid(vcpu
,
10643 VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS
);
10647 if (vmcs12
->launch_state
== launch
) {
10648 nested_vmx_failValid(vcpu
,
10649 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
10650 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
10654 ret
= check_vmentry_prereqs(vcpu
, vmcs12
);
10656 nested_vmx_failValid(vcpu
, ret
);
10661 * After this point, the trap flag no longer triggers a singlestep trap
10662 * on the vm entry instructions; don't call kvm_skip_emulated_instruction.
10663 * This is not 100% correct; for performance reasons, we delegate most
10664 * of the checks on host state to the processor. If those fail,
10665 * the singlestep trap is missed.
10667 skip_emulated_instruction(vcpu
);
10669 ret
= check_vmentry_postreqs(vcpu
, vmcs12
, &exit_qual
);
10671 nested_vmx_entry_failure(vcpu
, vmcs12
,
10672 EXIT_REASON_INVALID_STATE
, exit_qual
);
10677 * We're finally done with prerequisite checking, and can start with
10678 * the nested entry.
10681 ret
= enter_vmx_non_root_mode(vcpu
, true);
10685 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10686 return kvm_vcpu_halt(vcpu
);
10688 vmx
->nested
.nested_run_pending
= 1;
10693 return kvm_skip_emulated_instruction(vcpu
);
10697 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10698 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10699 * This function returns the new value we should put in vmcs12.guest_cr0.
10700 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10701 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10702 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10703 * didn't trap the bit, because if L1 did, so would L0).
10704 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10705 * been modified by L2, and L1 knows it. So just leave the old value of
10706 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10707 * isn't relevant, because if L0 traps this bit it can set it to anything.
10708 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10709 * changed these bits, and therefore they need to be updated, but L0
10710 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10711 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10713 static inline unsigned long
10714 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10717 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10718 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10719 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10720 vcpu
->arch
.cr0_guest_owned_bits
));
10723 static inline unsigned long
10724 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10727 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10728 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10729 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10730 vcpu
->arch
.cr4_guest_owned_bits
));
10733 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10734 struct vmcs12
*vmcs12
)
10739 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10740 nr
= vcpu
->arch
.exception
.nr
;
10741 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10743 if (kvm_exception_is_soft(nr
)) {
10744 vmcs12
->vm_exit_instruction_len
=
10745 vcpu
->arch
.event_exit_inst_len
;
10746 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10748 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10750 if (vcpu
->arch
.exception
.has_error_code
) {
10751 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10752 vmcs12
->idt_vectoring_error_code
=
10753 vcpu
->arch
.exception
.error_code
;
10756 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10757 } else if (vcpu
->arch
.nmi_injected
) {
10758 vmcs12
->idt_vectoring_info_field
=
10759 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10760 } else if (vcpu
->arch
.interrupt
.pending
) {
10761 nr
= vcpu
->arch
.interrupt
.nr
;
10762 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10764 if (vcpu
->arch
.interrupt
.soft
) {
10765 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10766 vmcs12
->vm_entry_instruction_len
=
10767 vcpu
->arch
.event_exit_inst_len
;
10769 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10771 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10775 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10777 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10779 if (vcpu
->arch
.exception
.pending
||
10780 vcpu
->arch
.nmi_injected
||
10781 vcpu
->arch
.interrupt
.pending
)
10784 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10785 vmx
->nested
.preemption_timer_expired
) {
10786 if (vmx
->nested
.nested_run_pending
)
10788 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10792 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10793 if (vmx
->nested
.nested_run_pending
)
10795 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10796 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10797 INTR_INFO_VALID_MASK
, 0);
10799 * The NMI-triggered VM exit counts as injection:
10800 * clear this one and block further NMIs.
10802 vcpu
->arch
.nmi_pending
= 0;
10803 vmx_set_nmi_mask(vcpu
, true);
10807 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10808 nested_exit_on_intr(vcpu
)) {
10809 if (vmx
->nested
.nested_run_pending
)
10811 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10815 vmx_complete_nested_posted_interrupt(vcpu
);
10819 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10821 ktime_t remaining
=
10822 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10825 if (ktime_to_ns(remaining
) <= 0)
10828 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10829 do_div(value
, 1000000);
10830 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10834 * Update the guest state fields of vmcs12 to reflect changes that
10835 * occurred while L2 was running. (The "IA-32e mode guest" bit of the
10836 * VM-entry controls is also updated, since this is really a guest
10839 static void sync_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10841 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10842 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10844 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10845 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10846 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10848 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10849 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10850 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10851 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10852 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10853 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10854 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10855 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10856 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10857 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10858 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10859 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10860 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10861 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10862 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10863 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10864 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10865 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10866 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10867 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10868 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10869 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10870 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10871 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10872 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10873 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10874 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10875 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10876 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10877 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10878 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10879 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10880 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10881 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10882 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10883 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10885 vmcs12
->guest_interruptibility_info
=
10886 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10887 vmcs12
->guest_pending_dbg_exceptions
=
10888 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10889 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10890 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10892 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10894 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10895 if (vmcs12
->vm_exit_controls
&
10896 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10897 vmcs12
->vmx_preemption_timer_value
=
10898 vmx_get_preemption_timer_value(vcpu
);
10899 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10903 * In some cases (usually, nested EPT), L2 is allowed to change its
10904 * own CR3 without exiting. If it has changed it, we must keep it.
10905 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10906 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10908 * Additionally, restore L2's PDPTR to vmcs12.
10911 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10912 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10913 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10914 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10915 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10918 vmcs12
->guest_linear_address
= vmcs_readl(GUEST_LINEAR_ADDRESS
);
10920 if (nested_cpu_has_vid(vmcs12
))
10921 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10923 vmcs12
->vm_entry_controls
=
10924 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10925 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10927 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10928 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10929 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10932 /* TODO: These cannot have changed unless we have MSR bitmaps and
10933 * the relevant bit asks not to trap the change */
10934 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10935 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10936 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10937 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10938 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10939 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10940 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10941 if (kvm_mpx_supported())
10942 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10946 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10947 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10948 * and this function updates it to reflect the changes to the guest state while
10949 * L2 was running (and perhaps made some exits which were handled directly by L0
10950 * without going back to L1), and to reflect the exit reason.
10951 * Note that we do not have to copy here all VMCS fields, just those that
10952 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10953 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10954 * which already writes to vmcs12 directly.
10956 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10957 u32 exit_reason
, u32 exit_intr_info
,
10958 unsigned long exit_qualification
)
10960 /* update guest state fields: */
10961 sync_vmcs12(vcpu
, vmcs12
);
10963 /* update exit information fields: */
10965 vmcs12
->vm_exit_reason
= exit_reason
;
10966 vmcs12
->exit_qualification
= exit_qualification
;
10967 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10969 vmcs12
->idt_vectoring_info_field
= 0;
10970 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10971 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10973 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10974 vmcs12
->launch_state
= 1;
10976 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10977 * instead of reading the real value. */
10978 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10981 * Transfer the event that L0 or L1 may wanted to inject into
10982 * L2 to IDT_VECTORING_INFO_FIELD.
10984 vmcs12_save_pending_event(vcpu
, vmcs12
);
10988 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10989 * preserved above and would only end up incorrectly in L1.
10991 vcpu
->arch
.nmi_injected
= false;
10992 kvm_clear_exception_queue(vcpu
);
10993 kvm_clear_interrupt_queue(vcpu
);
10997 * A part of what we need to when the nested L2 guest exits and we want to
10998 * run its L1 parent, is to reset L1's guest state to the host state specified
11000 * This function is to be called not only on normal nested exit, but also on
11001 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
11002 * Failures During or After Loading Guest State").
11003 * This function should be called when the active VMCS is L1's (vmcs01).
11005 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
11006 struct vmcs12
*vmcs12
)
11008 struct kvm_segment seg
;
11009 u32 entry_failure_code
;
11011 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
11012 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
11013 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11014 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
11016 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
11017 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
11019 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
11020 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
11021 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
11023 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
11024 * actually changed, because vmx_set_cr0 refers to efer set above.
11026 * CR0_GUEST_HOST_MASK is already set in the original vmcs01
11027 * (KVM doesn't change it);
11029 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
11030 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
11032 /* Same as above - no reason to call set_cr4_guest_host_mask(). */
11033 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
11034 vmx_set_cr4(vcpu
, vmcs12
->host_cr4
);
11036 nested_ept_uninit_mmu_context(vcpu
);
11039 * Only PDPTE load can fail as the value of cr3 was checked on entry and
11040 * couldn't have changed.
11042 if (nested_vmx_load_cr3(vcpu
, vmcs12
->host_cr3
, false, &entry_failure_code
))
11043 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_PDPTE_FAIL
);
11046 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
11050 * Trivially support vpid by letting L2s share their parent
11051 * L1's vpid. TODO: move to a more elaborate solution, giving
11052 * each L2 its own vpid and exposing the vpid feature to L1.
11054 vmx_flush_tlb(vcpu
);
11056 /* Restore posted intr vector. */
11057 if (nested_cpu_has_posted_intr(vmcs12
))
11058 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
11060 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
11061 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
11062 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
11063 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
11064 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
11066 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
11067 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
11068 vmcs_write64(GUEST_BNDCFGS
, 0);
11070 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
11071 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
11072 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
11074 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
11075 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
11076 vmcs12
->host_ia32_perf_global_ctrl
);
11078 /* Set L1 segment info according to Intel SDM
11079 27.5.2 Loading Host Segment and Descriptor-Table Registers */
11080 seg
= (struct kvm_segment
) {
11082 .limit
= 0xFFFFFFFF,
11083 .selector
= vmcs12
->host_cs_selector
,
11089 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
11093 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
11094 seg
= (struct kvm_segment
) {
11096 .limit
= 0xFFFFFFFF,
11103 seg
.selector
= vmcs12
->host_ds_selector
;
11104 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
11105 seg
.selector
= vmcs12
->host_es_selector
;
11106 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
11107 seg
.selector
= vmcs12
->host_ss_selector
;
11108 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
11109 seg
.selector
= vmcs12
->host_fs_selector
;
11110 seg
.base
= vmcs12
->host_fs_base
;
11111 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
11112 seg
.selector
= vmcs12
->host_gs_selector
;
11113 seg
.base
= vmcs12
->host_gs_base
;
11114 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
11115 seg
= (struct kvm_segment
) {
11116 .base
= vmcs12
->host_tr_base
,
11118 .selector
= vmcs12
->host_tr_selector
,
11122 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
11124 kvm_set_dr(vcpu
, 7, 0x400);
11125 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
11127 if (cpu_has_vmx_msr_bitmap())
11128 vmx_set_msr_bitmap(vcpu
);
11130 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
11131 vmcs12
->vm_exit_msr_load_count
))
11132 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
11136 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
11137 * and modify vmcs12 to make it see what it would expect to see there if
11138 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
11140 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
11141 u32 exit_intr_info
,
11142 unsigned long exit_qualification
)
11144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11145 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
11146 u32 vm_inst_error
= 0;
11148 /* trying to cancel vmlaunch/vmresume is a bug */
11149 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
11151 leave_guest_mode(vcpu
);
11152 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
11153 exit_qualification
);
11155 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
11156 vmcs12
->vm_exit_msr_store_count
))
11157 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
11159 if (unlikely(vmx
->fail
))
11160 vm_inst_error
= vmcs_read32(VM_INSTRUCTION_ERROR
);
11162 vmx_switch_vmcs(vcpu
, &vmx
->vmcs01
);
11165 * TODO: SDM says that with acknowledge interrupt on exit, bit 31 of
11166 * the VM-exit interrupt information (valid interrupt) is always set to
11167 * 1 on EXIT_REASON_EXTERNAL_INTERRUPT, so we shouldn't need
11168 * kvm_cpu_has_interrupt(). See the commit message for details.
11170 if (nested_exit_intr_ack_set(vcpu
) &&
11171 exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
&&
11172 kvm_cpu_has_interrupt(vcpu
)) {
11173 int irq
= kvm_cpu_get_interrupt(vcpu
);
11175 vmcs12
->vm_exit_intr_info
= irq
|
11176 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
11179 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
11180 vmcs12
->exit_qualification
,
11181 vmcs12
->idt_vectoring_info_field
,
11182 vmcs12
->vm_exit_intr_info
,
11183 vmcs12
->vm_exit_intr_error_code
,
11186 vm_entry_controls_reset_shadow(vmx
);
11187 vm_exit_controls_reset_shadow(vmx
);
11188 vmx_segment_cache_clear(vmx
);
11190 /* if no vmcs02 cache requested, remove the one we used */
11191 if (VMCS02_POOL_SIZE
== 0)
11192 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
11194 load_vmcs12_host_state(vcpu
, vmcs12
);
11196 /* Update any VMCS fields that might have changed while L2 ran */
11197 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11198 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, vmx
->msr_autoload
.nr
);
11199 vmcs_write64(TSC_OFFSET
, vcpu
->arch
.tsc_offset
);
11200 if (vmx
->hv_deadline_tsc
== -1)
11201 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11202 PIN_BASED_VMX_PREEMPTION_TIMER
);
11204 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11205 PIN_BASED_VMX_PREEMPTION_TIMER
);
11206 if (kvm_has_tsc_control
)
11207 decache_tsc_multiplier(vmx
);
11209 if (vmx
->nested
.change_vmcs01_virtual_x2apic_mode
) {
11210 vmx
->nested
.change_vmcs01_virtual_x2apic_mode
= false;
11211 vmx_set_virtual_x2apic_mode(vcpu
,
11212 vcpu
->arch
.apic_base
& X2APIC_ENABLE
);
11213 } else if (!nested_cpu_has_ept(vmcs12
) &&
11214 nested_cpu_has2(vmcs12
,
11215 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
11216 vmx_flush_tlb_ept_only(vcpu
);
11219 /* This is needed for same reason as it was needed in prepare_vmcs02 */
11222 /* Unpin physical memory we referred to in vmcs02 */
11223 if (vmx
->nested
.apic_access_page
) {
11224 nested_release_page(vmx
->nested
.apic_access_page
);
11225 vmx
->nested
.apic_access_page
= NULL
;
11227 if (vmx
->nested
.virtual_apic_page
) {
11228 nested_release_page(vmx
->nested
.virtual_apic_page
);
11229 vmx
->nested
.virtual_apic_page
= NULL
;
11231 if (vmx
->nested
.pi_desc_page
) {
11232 kunmap(vmx
->nested
.pi_desc_page
);
11233 nested_release_page(vmx
->nested
.pi_desc_page
);
11234 vmx
->nested
.pi_desc_page
= NULL
;
11235 vmx
->nested
.pi_desc
= NULL
;
11239 * We are now running in L2, mmu_notifier will force to reload the
11240 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
11242 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
11245 * Exiting from L2 to L1, we're now back to L1 which thinks it just
11246 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
11247 * success or failure flag accordingly.
11249 if (unlikely(vmx
->fail
)) {
11251 nested_vmx_failValid(vcpu
, vm_inst_error
);
11253 nested_vmx_succeed(vcpu
);
11254 if (enable_shadow_vmcs
)
11255 vmx
->nested
.sync_shadow_vmcs
= true;
11257 /* in case we halted in L2 */
11258 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
11262 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
11264 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
11266 if (is_guest_mode(vcpu
)) {
11267 to_vmx(vcpu
)->nested
.nested_run_pending
= 0;
11268 nested_vmx_vmexit(vcpu
, -1, 0, 0);
11270 free_nested(to_vmx(vcpu
));
11274 * L1's failure to enter L2 is a subset of a normal exit, as explained in
11275 * 23.7 "VM-entry failures during or after loading guest state" (this also
11276 * lists the acceptable exit-reason and exit-qualification parameters).
11277 * It should only be called before L2 actually succeeded to run, and when
11278 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
11280 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
11281 struct vmcs12
*vmcs12
,
11282 u32 reason
, unsigned long qualification
)
11284 load_vmcs12_host_state(vcpu
, vmcs12
);
11285 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
11286 vmcs12
->exit_qualification
= qualification
;
11287 nested_vmx_succeed(vcpu
);
11288 if (enable_shadow_vmcs
)
11289 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
11292 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
11293 struct x86_instruction_info
*info
,
11294 enum x86_intercept_stage stage
)
11296 return X86EMUL_CONTINUE
;
11299 #ifdef CONFIG_X86_64
11300 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */
11301 static inline int u64_shl_div_u64(u64 a
, unsigned int shift
,
11302 u64 divisor
, u64
*result
)
11304 u64 low
= a
<< shift
, high
= a
>> (64 - shift
);
11306 /* To avoid the overflow on divq */
11307 if (high
>= divisor
)
11310 /* Low hold the result, high hold rem which is discarded */
11311 asm("divq %2\n\t" : "=a" (low
), "=d" (high
) :
11312 "rm" (divisor
), "0" (low
), "1" (high
));
11318 static int vmx_set_hv_timer(struct kvm_vcpu
*vcpu
, u64 guest_deadline_tsc
)
11320 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11321 u64 tscl
= rdtsc();
11322 u64 guest_tscl
= kvm_read_l1_tsc(vcpu
, tscl
);
11323 u64 delta_tsc
= max(guest_deadline_tsc
, guest_tscl
) - guest_tscl
;
11325 /* Convert to host delta tsc if tsc scaling is enabled */
11326 if (vcpu
->arch
.tsc_scaling_ratio
!= kvm_default_tsc_scaling_ratio
&&
11327 u64_shl_div_u64(delta_tsc
,
11328 kvm_tsc_scaling_ratio_frac_bits
,
11329 vcpu
->arch
.tsc_scaling_ratio
,
11334 * If the delta tsc can't fit in the 32 bit after the multi shift,
11335 * we can't use the preemption timer.
11336 * It's possible that it fits on later vmentries, but checking
11337 * on every vmentry is costly so we just use an hrtimer.
11339 if (delta_tsc
>> (cpu_preemption_timer_multi
+ 32))
11342 vmx
->hv_deadline_tsc
= tscl
+ delta_tsc
;
11343 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL
,
11344 PIN_BASED_VMX_PREEMPTION_TIMER
);
11346 return delta_tsc
== 0;
11349 static void vmx_cancel_hv_timer(struct kvm_vcpu
*vcpu
)
11351 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11352 vmx
->hv_deadline_tsc
= -1;
11353 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL
,
11354 PIN_BASED_VMX_PREEMPTION_TIMER
);
11358 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
11361 shrink_ple_window(vcpu
);
11364 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
11365 struct kvm_memory_slot
*slot
)
11367 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
11368 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
11371 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
11372 struct kvm_memory_slot
*slot
)
11374 kvm_mmu_slot_set_dirty(kvm
, slot
);
11377 static void vmx_flush_log_dirty(struct kvm
*kvm
)
11379 kvm_flush_pml_buffers(kvm
);
11382 static int vmx_write_pml_buffer(struct kvm_vcpu
*vcpu
)
11384 struct vmcs12
*vmcs12
;
11385 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
11387 struct page
*page
= NULL
;
11390 if (is_guest_mode(vcpu
)) {
11391 WARN_ON_ONCE(vmx
->nested
.pml_full
);
11394 * Check if PML is enabled for the nested guest.
11395 * Whether eptp bit 6 is set is already checked
11396 * as part of A/D emulation.
11398 vmcs12
= get_vmcs12(vcpu
);
11399 if (!nested_cpu_has_pml(vmcs12
))
11402 if (vmcs12
->guest_pml_index
>= PML_ENTITY_NUM
) {
11403 vmx
->nested
.pml_full
= true;
11407 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
) & ~0xFFFull
;
11409 page
= nested_get_page(vcpu
, vmcs12
->pml_address
);
11413 pml_address
= kmap(page
);
11414 pml_address
[vmcs12
->guest_pml_index
--] = gpa
;
11416 nested_release_page_clean(page
);
11422 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
11423 struct kvm_memory_slot
*memslot
,
11424 gfn_t offset
, unsigned long mask
)
11426 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
11429 static void __pi_post_block(struct kvm_vcpu
*vcpu
)
11431 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11432 struct pi_desc old
, new;
11436 old
.control
= new.control
= pi_desc
->control
;
11437 WARN(old
.nv
!= POSTED_INTR_WAKEUP_VECTOR
,
11438 "Wakeup handler not enabled while the VCPU is blocked\n");
11440 dest
= cpu_physical_id(vcpu
->cpu
);
11442 if (x2apic_enabled())
11445 new.ndst
= (dest
<< 8) & 0xFF00;
11447 /* set 'NV' to 'notification vector' */
11448 new.nv
= POSTED_INTR_VECTOR
;
11449 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11450 new.control
) != old
.control
);
11452 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
== -1)) {
11453 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11454 list_del(&vcpu
->blocked_vcpu_list
);
11455 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11456 vcpu
->pre_pcpu
= -1;
11461 * This routine does the following things for vCPU which is going
11462 * to be blocked if VT-d PI is enabled.
11463 * - Store the vCPU to the wakeup list, so when interrupts happen
11464 * we can find the right vCPU to wake up.
11465 * - Change the Posted-interrupt descriptor as below:
11466 * 'NDST' <-- vcpu->pre_pcpu
11467 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
11468 * - If 'ON' is set during this process, which means at least one
11469 * interrupt is posted for this vCPU, we cannot block it, in
11470 * this case, return 1, otherwise, return 0.
11473 static int pi_pre_block(struct kvm_vcpu
*vcpu
)
11476 struct pi_desc old
, new;
11477 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
11479 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
11480 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11481 !kvm_vcpu_apicv_active(vcpu
))
11484 WARN_ON(irqs_disabled());
11485 local_irq_disable();
11486 if (!WARN_ON_ONCE(vcpu
->pre_pcpu
!= -1)) {
11487 vcpu
->pre_pcpu
= vcpu
->cpu
;
11488 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11489 list_add_tail(&vcpu
->blocked_vcpu_list
,
11490 &per_cpu(blocked_vcpu_on_cpu
,
11492 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, vcpu
->pre_pcpu
));
11496 old
.control
= new.control
= pi_desc
->control
;
11498 WARN((pi_desc
->sn
== 1),
11499 "Warning: SN field of posted-interrupts "
11500 "is set before blocking\n");
11503 * Since vCPU can be preempted during this process,
11504 * vcpu->cpu could be different with pre_pcpu, we
11505 * need to set pre_pcpu as the destination of wakeup
11506 * notification event, then we can find the right vCPU
11507 * to wakeup in wakeup handler if interrupts happen
11508 * when the vCPU is in blocked state.
11510 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
11512 if (x2apic_enabled())
11515 new.ndst
= (dest
<< 8) & 0xFF00;
11517 /* set 'NV' to 'wakeup vector' */
11518 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
11519 } while (cmpxchg64(&pi_desc
->control
, old
.control
,
11520 new.control
) != old
.control
);
11522 /* We should not block the vCPU if an interrupt is posted for it. */
11523 if (pi_test_on(pi_desc
) == 1)
11524 __pi_post_block(vcpu
);
11526 local_irq_enable();
11527 return (vcpu
->pre_pcpu
== -1);
11530 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
11532 if (pi_pre_block(vcpu
))
11535 if (kvm_lapic_hv_timer_in_use(vcpu
))
11536 kvm_lapic_switch_to_sw_timer(vcpu
);
11541 static void pi_post_block(struct kvm_vcpu
*vcpu
)
11543 if (vcpu
->pre_pcpu
== -1)
11546 WARN_ON(irqs_disabled());
11547 local_irq_disable();
11548 __pi_post_block(vcpu
);
11549 local_irq_enable();
11552 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
11554 if (kvm_x86_ops
->set_hv_timer
)
11555 kvm_lapic_switch_to_hv_timer(vcpu
);
11557 pi_post_block(vcpu
);
11561 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
11564 * @host_irq: host irq of the interrupt
11565 * @guest_irq: gsi of the interrupt
11566 * @set: set or unset PI
11567 * returns 0 on success, < 0 on failure
11569 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
11570 uint32_t guest_irq
, bool set
)
11572 struct kvm_kernel_irq_routing_entry
*e
;
11573 struct kvm_irq_routing_table
*irq_rt
;
11574 struct kvm_lapic_irq irq
;
11575 struct kvm_vcpu
*vcpu
;
11576 struct vcpu_data vcpu_info
;
11579 if (!kvm_arch_has_assigned_device(kvm
) ||
11580 !irq_remapping_cap(IRQ_POSTING_CAP
) ||
11581 !kvm_vcpu_apicv_active(kvm
->vcpus
[0]))
11584 idx
= srcu_read_lock(&kvm
->irq_srcu
);
11585 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
11586 if (guest_irq
>= irq_rt
->nr_rt_entries
||
11587 hlist_empty(&irq_rt
->map
[guest_irq
])) {
11588 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
11589 guest_irq
, irq_rt
->nr_rt_entries
);
11593 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
11594 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
11597 * VT-d PI cannot support posting multicast/broadcast
11598 * interrupts to a vCPU, we still use interrupt remapping
11599 * for these kind of interrupts.
11601 * For lowest-priority interrupts, we only support
11602 * those with single CPU as the destination, e.g. user
11603 * configures the interrupts via /proc/irq or uses
11604 * irqbalance to make the interrupts single-CPU.
11606 * We will support full lowest-priority interrupt later.
11609 kvm_set_msi_irq(kvm
, e
, &irq
);
11610 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
11612 * Make sure the IRTE is in remapped mode if
11613 * we don't handle it in posted mode.
11615 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11618 "failed to back to remapped mode, irq: %u\n",
11626 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
11627 vcpu_info
.vector
= irq
.vector
;
11629 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
11630 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
11633 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
11635 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
11638 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
11646 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
11650 static void vmx_setup_mce(struct kvm_vcpu
*vcpu
)
11652 if (vcpu
->arch
.mcg_cap
& MCG_LMCE_P
)
11653 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
|=
11654 FEATURE_CONTROL_LMCE
;
11656 to_vmx(vcpu
)->msr_ia32_feature_control_valid_bits
&=
11657 ~FEATURE_CONTROL_LMCE
;
11660 static struct kvm_x86_ops vmx_x86_ops __ro_after_init
= {
11661 .cpu_has_kvm_support
= cpu_has_kvm_support
,
11662 .disabled_by_bios
= vmx_disabled_by_bios
,
11663 .hardware_setup
= hardware_setup
,
11664 .hardware_unsetup
= hardware_unsetup
,
11665 .check_processor_compatibility
= vmx_check_processor_compat
,
11666 .hardware_enable
= hardware_enable
,
11667 .hardware_disable
= hardware_disable
,
11668 .cpu_has_accelerated_tpr
= report_flexpriority
,
11669 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
11671 .vcpu_create
= vmx_create_vcpu
,
11672 .vcpu_free
= vmx_free_vcpu
,
11673 .vcpu_reset
= vmx_vcpu_reset
,
11675 .prepare_guest_switch
= vmx_save_host_state
,
11676 .vcpu_load
= vmx_vcpu_load
,
11677 .vcpu_put
= vmx_vcpu_put
,
11679 .update_bp_intercept
= update_exception_bitmap
,
11680 .get_msr
= vmx_get_msr
,
11681 .set_msr
= vmx_set_msr
,
11682 .get_segment_base
= vmx_get_segment_base
,
11683 .get_segment
= vmx_get_segment
,
11684 .set_segment
= vmx_set_segment
,
11685 .get_cpl
= vmx_get_cpl
,
11686 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
11687 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
11688 .decache_cr3
= vmx_decache_cr3
,
11689 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
11690 .set_cr0
= vmx_set_cr0
,
11691 .set_cr3
= vmx_set_cr3
,
11692 .set_cr4
= vmx_set_cr4
,
11693 .set_efer
= vmx_set_efer
,
11694 .get_idt
= vmx_get_idt
,
11695 .set_idt
= vmx_set_idt
,
11696 .get_gdt
= vmx_get_gdt
,
11697 .set_gdt
= vmx_set_gdt
,
11698 .get_dr6
= vmx_get_dr6
,
11699 .set_dr6
= vmx_set_dr6
,
11700 .set_dr7
= vmx_set_dr7
,
11701 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
11702 .cache_reg
= vmx_cache_reg
,
11703 .get_rflags
= vmx_get_rflags
,
11704 .set_rflags
= vmx_set_rflags
,
11706 .tlb_flush
= vmx_flush_tlb
,
11708 .run
= vmx_vcpu_run
,
11709 .handle_exit
= vmx_handle_exit
,
11710 .skip_emulated_instruction
= skip_emulated_instruction
,
11711 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
11712 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
11713 .patch_hypercall
= vmx_patch_hypercall
,
11714 .set_irq
= vmx_inject_irq
,
11715 .set_nmi
= vmx_inject_nmi
,
11716 .queue_exception
= vmx_queue_exception
,
11717 .cancel_injection
= vmx_cancel_injection
,
11718 .interrupt_allowed
= vmx_interrupt_allowed
,
11719 .nmi_allowed
= vmx_nmi_allowed
,
11720 .get_nmi_mask
= vmx_get_nmi_mask
,
11721 .set_nmi_mask
= vmx_set_nmi_mask
,
11722 .enable_nmi_window
= enable_nmi_window
,
11723 .enable_irq_window
= enable_irq_window
,
11724 .update_cr8_intercept
= update_cr8_intercept
,
11725 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
11726 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
11727 .get_enable_apicv
= vmx_get_enable_apicv
,
11728 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
11729 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
11730 .apicv_post_state_restore
= vmx_apicv_post_state_restore
,
11731 .hwapic_irr_update
= vmx_hwapic_irr_update
,
11732 .hwapic_isr_update
= vmx_hwapic_isr_update
,
11733 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
11734 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
11736 .set_tss_addr
= vmx_set_tss_addr
,
11737 .get_tdp_level
= get_ept_level
,
11738 .get_mt_mask
= vmx_get_mt_mask
,
11740 .get_exit_info
= vmx_get_exit_info
,
11742 .get_lpage_level
= vmx_get_lpage_level
,
11744 .cpuid_update
= vmx_cpuid_update
,
11746 .rdtscp_supported
= vmx_rdtscp_supported
,
11747 .invpcid_supported
= vmx_invpcid_supported
,
11749 .set_supported_cpuid
= vmx_set_supported_cpuid
,
11751 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
11753 .write_tsc_offset
= vmx_write_tsc_offset
,
11755 .set_tdp_cr3
= vmx_set_cr3
,
11757 .check_intercept
= vmx_check_intercept
,
11758 .handle_external_intr
= vmx_handle_external_intr
,
11759 .mpx_supported
= vmx_mpx_supported
,
11760 .xsaves_supported
= vmx_xsaves_supported
,
11762 .check_nested_events
= vmx_check_nested_events
,
11764 .sched_in
= vmx_sched_in
,
11766 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
11767 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
11768 .flush_log_dirty
= vmx_flush_log_dirty
,
11769 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
11770 .write_log_dirty
= vmx_write_pml_buffer
,
11772 .pre_block
= vmx_pre_block
,
11773 .post_block
= vmx_post_block
,
11775 .pmu_ops
= &intel_pmu_ops
,
11777 .update_pi_irte
= vmx_update_pi_irte
,
11779 #ifdef CONFIG_X86_64
11780 .set_hv_timer
= vmx_set_hv_timer
,
11781 .cancel_hv_timer
= vmx_cancel_hv_timer
,
11784 .setup_mce
= vmx_setup_mce
,
11787 static int __init
vmx_init(void)
11789 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
11790 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
11794 #ifdef CONFIG_KEXEC_CORE
11795 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
11796 crash_vmclear_local_loaded_vmcss
);
11802 static void __exit
vmx_exit(void)
11804 #ifdef CONFIG_KEXEC_CORE
11805 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
11812 module_init(vmx_init
)
11813 module_exit(vmx_exit
)