2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
34 #include <asm/virtext.h>
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
41 static int __read_mostly bypass_guest_pf
= 1;
42 module_param(bypass_guest_pf
, bool, S_IRUGO
);
44 static int __read_mostly enable_vpid
= 1;
45 module_param_named(vpid
, enable_vpid
, bool, 0444);
47 static int __read_mostly flexpriority_enabled
= 1;
48 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
50 static int __read_mostly enable_ept
= 1;
51 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
53 static int __read_mostly emulate_invalid_guest_state
= 0;
54 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
64 struct list_head local_vcpus_link
;
65 unsigned long host_rsp
;
68 u32 idt_vectoring_info
;
69 struct kvm_msr_entry
*guest_msrs
;
70 struct kvm_msr_entry
*host_msrs
;
75 int msr_offset_kernel_gs_base
;
80 u16 fs_sel
, gs_sel
, ldt_sel
;
81 int gs_ldt_reload_needed
;
83 int guest_efer_loaded
;
93 bool emulation_required
;
94 enum emulation_result invalid_state_emulation_result
;
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked
;
99 s64 vnmi_blocked_time
;
102 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
104 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
107 static int init_rmode(struct kvm
*kvm
);
108 static u64
construct_eptp(unsigned long root_hpa
);
110 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
111 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
112 static DEFINE_PER_CPU(struct list_head
, vcpus_on_cpu
);
114 static unsigned long *vmx_io_bitmap_a
;
115 static unsigned long *vmx_io_bitmap_b
;
116 static unsigned long *vmx_msr_bitmap_legacy
;
117 static unsigned long *vmx_msr_bitmap_longmode
;
119 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
120 static DEFINE_SPINLOCK(vmx_vpid_lock
);
122 static struct vmcs_config
{
126 u32 pin_based_exec_ctrl
;
127 u32 cpu_based_exec_ctrl
;
128 u32 cpu_based_2nd_exec_ctrl
;
133 static struct vmx_capability
{
138 #define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
146 static struct kvm_vmx_segment_field
{
151 } kvm_vmx_segment_fields
[] = {
152 VMX_SEGMENT_FIELD(CS
),
153 VMX_SEGMENT_FIELD(DS
),
154 VMX_SEGMENT_FIELD(ES
),
155 VMX_SEGMENT_FIELD(FS
),
156 VMX_SEGMENT_FIELD(GS
),
157 VMX_SEGMENT_FIELD(SS
),
158 VMX_SEGMENT_FIELD(TR
),
159 VMX_SEGMENT_FIELD(LDTR
),
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
166 static const u32 vmx_msr_index
[] = {
168 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
, MSR_KERNEL_GS_BASE
,
170 MSR_EFER
, MSR_K6_STAR
,
172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
174 static void load_msrs(struct kvm_msr_entry
*e
, int n
)
178 for (i
= 0; i
< n
; ++i
)
179 wrmsrl(e
[i
].index
, e
[i
].data
);
182 static void save_msrs(struct kvm_msr_entry
*e
, int n
)
186 for (i
= 0; i
< n
; ++i
)
187 rdmsrl(e
[i
].index
, e
[i
].data
);
190 static inline int is_page_fault(u32 intr_info
)
192 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
193 INTR_INFO_VALID_MASK
)) ==
194 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
197 static inline int is_no_device(u32 intr_info
)
199 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
200 INTR_INFO_VALID_MASK
)) ==
201 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
204 static inline int is_invalid_opcode(u32 intr_info
)
206 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
207 INTR_INFO_VALID_MASK
)) ==
208 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
211 static inline int is_external_interrupt(u32 intr_info
)
213 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
214 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
217 static inline int cpu_has_vmx_msr_bitmap(void)
219 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
222 static inline int cpu_has_vmx_tpr_shadow(void)
224 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
227 static inline int vm_need_tpr_shadow(struct kvm
*kvm
)
229 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
232 static inline int cpu_has_secondary_exec_ctrls(void)
234 return vmcs_config
.cpu_based_exec_ctrl
&
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
240 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
241 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
244 static inline bool cpu_has_vmx_flexpriority(void)
246 return cpu_has_vmx_tpr_shadow() &&
247 cpu_has_vmx_virtualize_apic_accesses();
250 static inline int cpu_has_vmx_invept_individual_addr(void)
252 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
);
255 static inline int cpu_has_vmx_invept_context(void)
257 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
);
260 static inline int cpu_has_vmx_invept_global(void)
262 return !!(vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
);
265 static inline int cpu_has_vmx_ept(void)
267 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
268 SECONDARY_EXEC_ENABLE_EPT
;
271 static inline int vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
273 return flexpriority_enabled
&&
274 (cpu_has_vmx_virtualize_apic_accesses()) &&
275 (irqchip_in_kernel(kvm
));
278 static inline int cpu_has_vmx_vpid(void)
280 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
281 SECONDARY_EXEC_ENABLE_VPID
;
284 static inline int cpu_has_virtual_nmis(void)
286 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
289 static inline bool report_flexpriority(void)
291 return flexpriority_enabled
;
294 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
298 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
299 if (vmx
->guest_msrs
[i
].index
== msr
)
304 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
310 } operand
= { vpid
, 0, gva
};
312 asm volatile (__ex(ASM_VMX_INVVPID
)
313 /* CF==1 or ZF==1 --> rc = -1 */
315 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
318 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
322 } operand
= {eptp
, gpa
};
324 asm volatile (__ex(ASM_VMX_INVEPT
)
325 /* CF==1 or ZF==1 --> rc = -1 */
326 "; ja 1f ; ud2 ; 1:\n"
327 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
330 static struct kvm_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
334 i
= __find_msr_index(vmx
, msr
);
336 return &vmx
->guest_msrs
[i
];
340 static void vmcs_clear(struct vmcs
*vmcs
)
342 u64 phys_addr
= __pa(vmcs
);
345 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
346 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
349 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
353 static void __vcpu_clear(void *arg
)
355 struct vcpu_vmx
*vmx
= arg
;
356 int cpu
= raw_smp_processor_id();
358 if (vmx
->vcpu
.cpu
== cpu
)
359 vmcs_clear(vmx
->vmcs
);
360 if (per_cpu(current_vmcs
, cpu
) == vmx
->vmcs
)
361 per_cpu(current_vmcs
, cpu
) = NULL
;
362 rdtscll(vmx
->vcpu
.arch
.host_tsc
);
363 list_del(&vmx
->local_vcpus_link
);
368 static void vcpu_clear(struct vcpu_vmx
*vmx
)
370 if (vmx
->vcpu
.cpu
== -1)
372 smp_call_function_single(vmx
->vcpu
.cpu
, __vcpu_clear
, vmx
, 1);
375 static inline void vpid_sync_vcpu_all(struct vcpu_vmx
*vmx
)
380 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
383 static inline void ept_sync_global(void)
385 if (cpu_has_vmx_invept_global())
386 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
389 static inline void ept_sync_context(u64 eptp
)
392 if (cpu_has_vmx_invept_context())
393 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
399 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
402 if (cpu_has_vmx_invept_individual_addr())
403 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
406 ept_sync_context(eptp
);
410 static unsigned long vmcs_readl(unsigned long field
)
414 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX
)
415 : "=a"(value
) : "d"(field
) : "cc");
419 static u16
vmcs_read16(unsigned long field
)
421 return vmcs_readl(field
);
424 static u32
vmcs_read32(unsigned long field
)
426 return vmcs_readl(field
);
429 static u64
vmcs_read64(unsigned long field
)
432 return vmcs_readl(field
);
434 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
438 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
440 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
441 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
445 static void vmcs_writel(unsigned long field
, unsigned long value
)
449 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
450 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
452 vmwrite_error(field
, value
);
455 static void vmcs_write16(unsigned long field
, u16 value
)
457 vmcs_writel(field
, value
);
460 static void vmcs_write32(unsigned long field
, u32 value
)
462 vmcs_writel(field
, value
);
465 static void vmcs_write64(unsigned long field
, u64 value
)
467 vmcs_writel(field
, value
);
468 #ifndef CONFIG_X86_64
470 vmcs_writel(field
+1, value
>> 32);
474 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
476 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
479 static void vmcs_set_bits(unsigned long field
, u32 mask
)
481 vmcs_writel(field
, vmcs_readl(field
) | mask
);
484 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
488 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
);
489 if (!vcpu
->fpu_active
)
490 eb
|= 1u << NM_VECTOR
;
491 if (vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
) {
492 if (vcpu
->guest_debug
&
493 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
494 eb
|= 1u << DB_VECTOR
;
495 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
496 eb
|= 1u << BP_VECTOR
;
498 if (vcpu
->arch
.rmode
.active
)
501 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
502 vmcs_write32(EXCEPTION_BITMAP
, eb
);
505 static void reload_tss(void)
508 * VT restores TR but not its size. Useless.
510 struct descriptor_table gdt
;
511 struct desc_struct
*descs
;
514 descs
= (void *)gdt
.base
;
515 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
519 static void load_transition_efer(struct vcpu_vmx
*vmx
)
521 int efer_offset
= vmx
->msr_offset_efer
;
522 u64 host_efer
= vmx
->host_msrs
[efer_offset
].data
;
523 u64 guest_efer
= vmx
->guest_msrs
[efer_offset
].data
;
529 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
532 ignore_bits
= EFER_NX
| EFER_SCE
;
534 ignore_bits
|= EFER_LMA
| EFER_LME
;
535 /* SCE is meaningful only in long mode on Intel */
536 if (guest_efer
& EFER_LMA
)
537 ignore_bits
&= ~(u64
)EFER_SCE
;
539 if ((guest_efer
& ~ignore_bits
) == (host_efer
& ~ignore_bits
))
542 vmx
->host_state
.guest_efer_loaded
= 1;
543 guest_efer
&= ~ignore_bits
;
544 guest_efer
|= host_efer
& ignore_bits
;
545 wrmsrl(MSR_EFER
, guest_efer
);
546 vmx
->vcpu
.stat
.efer_reload
++;
549 static void reload_host_efer(struct vcpu_vmx
*vmx
)
551 if (vmx
->host_state
.guest_efer_loaded
) {
552 vmx
->host_state
.guest_efer_loaded
= 0;
553 load_msrs(vmx
->host_msrs
+ vmx
->msr_offset_efer
, 1);
557 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
559 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
561 if (vmx
->host_state
.loaded
)
564 vmx
->host_state
.loaded
= 1;
566 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
567 * allow segment selectors with cpl > 0 or ti == 1.
569 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
570 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
571 vmx
->host_state
.fs_sel
= kvm_read_fs();
572 if (!(vmx
->host_state
.fs_sel
& 7)) {
573 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
574 vmx
->host_state
.fs_reload_needed
= 0;
576 vmcs_write16(HOST_FS_SELECTOR
, 0);
577 vmx
->host_state
.fs_reload_needed
= 1;
579 vmx
->host_state
.gs_sel
= kvm_read_gs();
580 if (!(vmx
->host_state
.gs_sel
& 7))
581 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
583 vmcs_write16(HOST_GS_SELECTOR
, 0);
584 vmx
->host_state
.gs_ldt_reload_needed
= 1;
588 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
589 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
591 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
592 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
596 if (is_long_mode(&vmx
->vcpu
))
597 save_msrs(vmx
->host_msrs
+
598 vmx
->msr_offset_kernel_gs_base
, 1);
601 load_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
602 load_transition_efer(vmx
);
605 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
609 if (!vmx
->host_state
.loaded
)
612 ++vmx
->vcpu
.stat
.host_state_reload
;
613 vmx
->host_state
.loaded
= 0;
614 if (vmx
->host_state
.fs_reload_needed
)
615 kvm_load_fs(vmx
->host_state
.fs_sel
);
616 if (vmx
->host_state
.gs_ldt_reload_needed
) {
617 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
619 * If we have to reload gs, we must take care to
620 * preserve our gs base.
622 local_irq_save(flags
);
623 kvm_load_gs(vmx
->host_state
.gs_sel
);
625 wrmsrl(MSR_GS_BASE
, vmcs_readl(HOST_GS_BASE
));
627 local_irq_restore(flags
);
630 save_msrs(vmx
->guest_msrs
, vmx
->save_nmsrs
);
631 load_msrs(vmx
->host_msrs
, vmx
->save_nmsrs
);
632 reload_host_efer(vmx
);
635 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
638 __vmx_load_host_state(vmx
);
643 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
644 * vcpu mutex is already taken.
646 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
648 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
649 u64 phys_addr
= __pa(vmx
->vmcs
);
650 u64 tsc_this
, delta
, new_offset
;
652 if (vcpu
->cpu
!= cpu
) {
654 kvm_migrate_timers(vcpu
);
655 vpid_sync_vcpu_all(vmx
);
657 list_add(&vmx
->local_vcpus_link
,
658 &per_cpu(vcpus_on_cpu
, cpu
));
662 if (per_cpu(current_vmcs
, cpu
) != vmx
->vmcs
) {
665 per_cpu(current_vmcs
, cpu
) = vmx
->vmcs
;
666 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
667 : "=g"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
670 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
671 vmx
->vmcs
, phys_addr
);
674 if (vcpu
->cpu
!= cpu
) {
675 struct descriptor_table dt
;
676 unsigned long sysenter_esp
;
680 * Linux uses per-cpu TSS and GDT, so set these when switching
683 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
685 vmcs_writel(HOST_GDTR_BASE
, dt
.base
); /* 22.2.4 */
687 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
688 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
691 * Make sure the time stamp counter is monotonous.
694 if (tsc_this
< vcpu
->arch
.host_tsc
) {
695 delta
= vcpu
->arch
.host_tsc
- tsc_this
;
696 new_offset
= vmcs_read64(TSC_OFFSET
) + delta
;
697 vmcs_write64(TSC_OFFSET
, new_offset
);
702 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
704 __vmx_load_host_state(to_vmx(vcpu
));
707 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
709 if (vcpu
->fpu_active
)
711 vcpu
->fpu_active
= 1;
712 vmcs_clear_bits(GUEST_CR0
, X86_CR0_TS
);
713 if (vcpu
->arch
.cr0
& X86_CR0_TS
)
714 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
715 update_exception_bitmap(vcpu
);
718 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
720 if (!vcpu
->fpu_active
)
722 vcpu
->fpu_active
= 0;
723 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
);
724 update_exception_bitmap(vcpu
);
727 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
729 return vmcs_readl(GUEST_RFLAGS
);
732 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
734 if (vcpu
->arch
.rmode
.active
)
735 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
736 vmcs_writel(GUEST_RFLAGS
, rflags
);
739 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
741 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
744 if (interruptibility
& GUEST_INTR_STATE_STI
)
745 ret
|= X86_SHADOW_INT_STI
;
746 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
747 ret
|= X86_SHADOW_INT_MOV_SS
;
752 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
754 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
755 u32 interruptibility
= interruptibility_old
;
757 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
759 if (mask
& X86_SHADOW_INT_MOV_SS
)
760 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
761 if (mask
& X86_SHADOW_INT_STI
)
762 interruptibility
|= GUEST_INTR_STATE_STI
;
764 if ((interruptibility
!= interruptibility_old
))
765 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
768 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
772 rip
= kvm_rip_read(vcpu
);
773 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
774 kvm_rip_write(vcpu
, rip
);
776 /* skipping an emulated instruction also counts */
777 vmx_set_interrupt_shadow(vcpu
, 0);
780 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
781 bool has_error_code
, u32 error_code
)
783 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
784 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
786 if (has_error_code
) {
787 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
788 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
791 if (vcpu
->arch
.rmode
.active
) {
792 vmx
->rmode
.irq
.pending
= true;
793 vmx
->rmode
.irq
.vector
= nr
;
794 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
795 if (nr
== BP_VECTOR
|| nr
== OF_VECTOR
)
796 vmx
->rmode
.irq
.rip
++;
797 intr_info
|= INTR_TYPE_SOFT_INTR
;
798 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
799 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
800 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
804 if (kvm_exception_is_soft(nr
)) {
805 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
806 vmx
->vcpu
.arch
.event_exit_inst_len
);
807 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
809 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
811 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
815 * Swap MSR entry in host/guest MSR entry array.
818 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
820 struct kvm_msr_entry tmp
;
822 tmp
= vmx
->guest_msrs
[to
];
823 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
824 vmx
->guest_msrs
[from
] = tmp
;
825 tmp
= vmx
->host_msrs
[to
];
826 vmx
->host_msrs
[to
] = vmx
->host_msrs
[from
];
827 vmx
->host_msrs
[from
] = tmp
;
832 * Set up the vmcs to automatically save and restore system
833 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
834 * mode, as fiddling with msrs is very expensive.
836 static void setup_msrs(struct vcpu_vmx
*vmx
)
839 unsigned long *msr_bitmap
;
841 vmx_load_host_state(vmx
);
844 if (is_long_mode(&vmx
->vcpu
)) {
847 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
849 move_msr_up(vmx
, index
, save_nmsrs
++);
850 index
= __find_msr_index(vmx
, MSR_LSTAR
);
852 move_msr_up(vmx
, index
, save_nmsrs
++);
853 index
= __find_msr_index(vmx
, MSR_CSTAR
);
855 move_msr_up(vmx
, index
, save_nmsrs
++);
856 index
= __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
858 move_msr_up(vmx
, index
, save_nmsrs
++);
860 * MSR_K6_STAR is only needed on long mode guests, and only
861 * if efer.sce is enabled.
863 index
= __find_msr_index(vmx
, MSR_K6_STAR
);
864 if ((index
>= 0) && (vmx
->vcpu
.arch
.shadow_efer
& EFER_SCE
))
865 move_msr_up(vmx
, index
, save_nmsrs
++);
868 vmx
->save_nmsrs
= save_nmsrs
;
871 vmx
->msr_offset_kernel_gs_base
=
872 __find_msr_index(vmx
, MSR_KERNEL_GS_BASE
);
874 vmx
->msr_offset_efer
= __find_msr_index(vmx
, MSR_EFER
);
876 if (cpu_has_vmx_msr_bitmap()) {
877 if (is_long_mode(&vmx
->vcpu
))
878 msr_bitmap
= vmx_msr_bitmap_longmode
;
880 msr_bitmap
= vmx_msr_bitmap_legacy
;
882 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
887 * reads and returns guest's timestamp counter "register"
888 * guest_tsc = host_tsc + tsc_offset -- 21.3
890 static u64
guest_read_tsc(void)
892 u64 host_tsc
, tsc_offset
;
895 tsc_offset
= vmcs_read64(TSC_OFFSET
);
896 return host_tsc
+ tsc_offset
;
900 * writes 'guest_tsc' into guest's timestamp counter "register"
901 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
903 static void guest_write_tsc(u64 guest_tsc
, u64 host_tsc
)
905 vmcs_write64(TSC_OFFSET
, guest_tsc
- host_tsc
);
909 * Reads an msr value (of 'msr_index') into 'pdata'.
910 * Returns 0 on success, non-0 otherwise.
911 * Assumes vcpu_load() was already called.
913 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
916 struct kvm_msr_entry
*msr
;
919 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
926 data
= vmcs_readl(GUEST_FS_BASE
);
929 data
= vmcs_readl(GUEST_GS_BASE
);
932 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
934 case MSR_IA32_TIME_STAMP_COUNTER
:
935 data
= guest_read_tsc();
937 case MSR_IA32_SYSENTER_CS
:
938 data
= vmcs_read32(GUEST_SYSENTER_CS
);
940 case MSR_IA32_SYSENTER_EIP
:
941 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
943 case MSR_IA32_SYSENTER_ESP
:
944 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
947 vmx_load_host_state(to_vmx(vcpu
));
948 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
953 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
961 * Writes msr value into into the appropriate "register".
962 * Returns 0 on success, non-0 otherwise.
963 * Assumes vcpu_load() was already called.
965 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
967 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
968 struct kvm_msr_entry
*msr
;
974 vmx_load_host_state(vmx
);
975 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
979 vmcs_writel(GUEST_FS_BASE
, data
);
982 vmcs_writel(GUEST_GS_BASE
, data
);
985 case MSR_IA32_SYSENTER_CS
:
986 vmcs_write32(GUEST_SYSENTER_CS
, data
);
988 case MSR_IA32_SYSENTER_EIP
:
989 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
991 case MSR_IA32_SYSENTER_ESP
:
992 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
994 case MSR_IA32_TIME_STAMP_COUNTER
:
996 guest_write_tsc(data
, host_tsc
);
998 case MSR_P6_PERFCTR0
:
999 case MSR_P6_PERFCTR1
:
1000 case MSR_P6_EVNTSEL0
:
1001 case MSR_P6_EVNTSEL1
:
1003 * Just discard all writes to the performance counters; this
1004 * should keep both older linux and windows 64-bit guests
1007 pr_unimpl(vcpu
, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index
, data
);
1010 case MSR_IA32_CR_PAT
:
1011 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1012 vmcs_write64(GUEST_IA32_PAT
, data
);
1013 vcpu
->arch
.pat
= data
;
1016 /* Otherwise falls through to kvm_set_msr_common */
1018 vmx_load_host_state(vmx
);
1019 msr
= find_msr_entry(vmx
, msr_index
);
1024 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1030 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1032 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1035 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1038 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1045 static int set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1047 int old_debug
= vcpu
->guest_debug
;
1048 unsigned long flags
;
1050 vcpu
->guest_debug
= dbg
->control
;
1051 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_ENABLE
))
1052 vcpu
->guest_debug
= 0;
1054 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1055 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1057 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1059 flags
= vmcs_readl(GUEST_RFLAGS
);
1060 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
1061 flags
|= X86_EFLAGS_TF
| X86_EFLAGS_RF
;
1062 else if (old_debug
& KVM_GUESTDBG_SINGLESTEP
)
1063 flags
&= ~(X86_EFLAGS_TF
| X86_EFLAGS_RF
);
1064 vmcs_writel(GUEST_RFLAGS
, flags
);
1066 update_exception_bitmap(vcpu
);
1071 static __init
int cpu_has_kvm_support(void)
1073 return cpu_has_vmx();
1076 static __init
int vmx_disabled_by_bios(void)
1080 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1081 return (msr
& (FEATURE_CONTROL_LOCKED
|
1082 FEATURE_CONTROL_VMXON_ENABLED
))
1083 == FEATURE_CONTROL_LOCKED
;
1084 /* locked but not enabled */
1087 static void hardware_enable(void *garbage
)
1089 int cpu
= raw_smp_processor_id();
1090 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1093 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu
, cpu
));
1094 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1095 if ((old
& (FEATURE_CONTROL_LOCKED
|
1096 FEATURE_CONTROL_VMXON_ENABLED
))
1097 != (FEATURE_CONTROL_LOCKED
|
1098 FEATURE_CONTROL_VMXON_ENABLED
))
1099 /* enable and lock */
1100 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
|
1101 FEATURE_CONTROL_LOCKED
|
1102 FEATURE_CONTROL_VMXON_ENABLED
);
1103 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1104 asm volatile (ASM_VMX_VMXON_RAX
1105 : : "a"(&phys_addr
), "m"(phys_addr
)
1109 static void vmclear_local_vcpus(void)
1111 int cpu
= raw_smp_processor_id();
1112 struct vcpu_vmx
*vmx
, *n
;
1114 list_for_each_entry_safe(vmx
, n
, &per_cpu(vcpus_on_cpu
, cpu
),
1120 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1123 static void kvm_cpu_vmxoff(void)
1125 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1126 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1129 static void hardware_disable(void *garbage
)
1131 vmclear_local_vcpus();
1135 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1136 u32 msr
, u32
*result
)
1138 u32 vmx_msr_low
, vmx_msr_high
;
1139 u32 ctl
= ctl_min
| ctl_opt
;
1141 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1143 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1144 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1146 /* Ensure minimum (required) set of control bits are supported. */
1154 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1156 u32 vmx_msr_low
, vmx_msr_high
;
1157 u32 min
, opt
, min2
, opt2
;
1158 u32 _pin_based_exec_control
= 0;
1159 u32 _cpu_based_exec_control
= 0;
1160 u32 _cpu_based_2nd_exec_control
= 0;
1161 u32 _vmexit_control
= 0;
1162 u32 _vmentry_control
= 0;
1164 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1165 opt
= PIN_BASED_VIRTUAL_NMIS
;
1166 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1167 &_pin_based_exec_control
) < 0)
1170 min
= CPU_BASED_HLT_EXITING
|
1171 #ifdef CONFIG_X86_64
1172 CPU_BASED_CR8_LOAD_EXITING
|
1173 CPU_BASED_CR8_STORE_EXITING
|
1175 CPU_BASED_CR3_LOAD_EXITING
|
1176 CPU_BASED_CR3_STORE_EXITING
|
1177 CPU_BASED_USE_IO_BITMAPS
|
1178 CPU_BASED_MOV_DR_EXITING
|
1179 CPU_BASED_USE_TSC_OFFSETING
|
1180 CPU_BASED_INVLPG_EXITING
;
1181 opt
= CPU_BASED_TPR_SHADOW
|
1182 CPU_BASED_USE_MSR_BITMAPS
|
1183 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1184 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1185 &_cpu_based_exec_control
) < 0)
1187 #ifdef CONFIG_X86_64
1188 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1189 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1190 ~CPU_BASED_CR8_STORE_EXITING
;
1192 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1194 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1195 SECONDARY_EXEC_WBINVD_EXITING
|
1196 SECONDARY_EXEC_ENABLE_VPID
|
1197 SECONDARY_EXEC_ENABLE_EPT
;
1198 if (adjust_vmx_controls(min2
, opt2
,
1199 MSR_IA32_VMX_PROCBASED_CTLS2
,
1200 &_cpu_based_2nd_exec_control
) < 0)
1203 #ifndef CONFIG_X86_64
1204 if (!(_cpu_based_2nd_exec_control
&
1205 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1206 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1208 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1209 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1211 min
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1212 CPU_BASED_CR3_STORE_EXITING
|
1213 CPU_BASED_INVLPG_EXITING
);
1214 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1215 &_cpu_based_exec_control
) < 0)
1217 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1218 vmx_capability
.ept
, vmx_capability
.vpid
);
1222 #ifdef CONFIG_X86_64
1223 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1225 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1226 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1227 &_vmexit_control
) < 0)
1231 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1232 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1233 &_vmentry_control
) < 0)
1236 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1238 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1239 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1242 #ifdef CONFIG_X86_64
1243 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1244 if (vmx_msr_high
& (1u<<16))
1248 /* Require Write-Back (WB) memory type for VMCS accesses. */
1249 if (((vmx_msr_high
>> 18) & 15) != 6)
1252 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
1253 vmcs_conf
->order
= get_order(vmcs_config
.size
);
1254 vmcs_conf
->revision_id
= vmx_msr_low
;
1256 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
1257 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
1258 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
1259 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
1260 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
1265 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
1267 int node
= cpu_to_node(cpu
);
1271 pages
= alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
1274 vmcs
= page_address(pages
);
1275 memset(vmcs
, 0, vmcs_config
.size
);
1276 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
1280 static struct vmcs
*alloc_vmcs(void)
1282 return alloc_vmcs_cpu(raw_smp_processor_id());
1285 static void free_vmcs(struct vmcs
*vmcs
)
1287 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
1290 static void free_kvm_area(void)
1294 for_each_online_cpu(cpu
)
1295 free_vmcs(per_cpu(vmxarea
, cpu
));
1298 static __init
int alloc_kvm_area(void)
1302 for_each_online_cpu(cpu
) {
1305 vmcs
= alloc_vmcs_cpu(cpu
);
1311 per_cpu(vmxarea
, cpu
) = vmcs
;
1316 static __init
int hardware_setup(void)
1318 if (setup_vmcs_config(&vmcs_config
) < 0)
1321 if (boot_cpu_has(X86_FEATURE_NX
))
1322 kvm_enable_efer_bits(EFER_NX
);
1324 if (!cpu_has_vmx_vpid())
1327 if (!cpu_has_vmx_ept())
1330 if (!cpu_has_vmx_flexpriority())
1331 flexpriority_enabled
= 0;
1333 if (!cpu_has_vmx_tpr_shadow())
1334 kvm_x86_ops
->update_cr8_intercept
= NULL
;
1336 return alloc_kvm_area();
1339 static __exit
void hardware_unsetup(void)
1344 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
1346 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1348 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
1349 vmcs_write16(sf
->selector
, save
->selector
);
1350 vmcs_writel(sf
->base
, save
->base
);
1351 vmcs_write32(sf
->limit
, save
->limit
);
1352 vmcs_write32(sf
->ar_bytes
, save
->ar
);
1354 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
1356 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
1360 static void enter_pmode(struct kvm_vcpu
*vcpu
)
1362 unsigned long flags
;
1363 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1365 vmx
->emulation_required
= 1;
1366 vcpu
->arch
.rmode
.active
= 0;
1368 vmcs_writel(GUEST_TR_BASE
, vcpu
->arch
.rmode
.tr
.base
);
1369 vmcs_write32(GUEST_TR_LIMIT
, vcpu
->arch
.rmode
.tr
.limit
);
1370 vmcs_write32(GUEST_TR_AR_BYTES
, vcpu
->arch
.rmode
.tr
.ar
);
1372 flags
= vmcs_readl(GUEST_RFLAGS
);
1373 flags
&= ~(X86_EFLAGS_IOPL
| X86_EFLAGS_VM
);
1374 flags
|= (vcpu
->arch
.rmode
.save_iopl
<< IOPL_SHIFT
);
1375 vmcs_writel(GUEST_RFLAGS
, flags
);
1377 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
1378 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
1380 update_exception_bitmap(vcpu
);
1382 if (emulate_invalid_guest_state
)
1385 fix_pmode_dataseg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1386 fix_pmode_dataseg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1387 fix_pmode_dataseg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1388 fix_pmode_dataseg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1390 vmcs_write16(GUEST_SS_SELECTOR
, 0);
1391 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
1393 vmcs_write16(GUEST_CS_SELECTOR
,
1394 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
1395 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
1398 static gva_t
rmode_tss_base(struct kvm
*kvm
)
1400 if (!kvm
->arch
.tss_addr
) {
1401 gfn_t base_gfn
= kvm
->memslots
[0].base_gfn
+
1402 kvm
->memslots
[0].npages
- 3;
1403 return base_gfn
<< PAGE_SHIFT
;
1405 return kvm
->arch
.tss_addr
;
1408 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
1410 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1412 save
->selector
= vmcs_read16(sf
->selector
);
1413 save
->base
= vmcs_readl(sf
->base
);
1414 save
->limit
= vmcs_read32(sf
->limit
);
1415 save
->ar
= vmcs_read32(sf
->ar_bytes
);
1416 vmcs_write16(sf
->selector
, save
->base
>> 4);
1417 vmcs_write32(sf
->base
, save
->base
& 0xfffff);
1418 vmcs_write32(sf
->limit
, 0xffff);
1419 vmcs_write32(sf
->ar_bytes
, 0xf3);
1422 static void enter_rmode(struct kvm_vcpu
*vcpu
)
1424 unsigned long flags
;
1425 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1427 vmx
->emulation_required
= 1;
1428 vcpu
->arch
.rmode
.active
= 1;
1430 vcpu
->arch
.rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
1431 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
1433 vcpu
->arch
.rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
1434 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
1436 vcpu
->arch
.rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1437 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
1439 flags
= vmcs_readl(GUEST_RFLAGS
);
1440 vcpu
->arch
.rmode
.save_iopl
1441 = (flags
& X86_EFLAGS_IOPL
) >> IOPL_SHIFT
;
1443 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1445 vmcs_writel(GUEST_RFLAGS
, flags
);
1446 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
1447 update_exception_bitmap(vcpu
);
1449 if (emulate_invalid_guest_state
)
1450 goto continue_rmode
;
1452 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
1453 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
1454 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
1456 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
1457 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
1458 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
1459 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
1460 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
1462 fix_rmode_seg(VCPU_SREG_ES
, &vcpu
->arch
.rmode
.es
);
1463 fix_rmode_seg(VCPU_SREG_DS
, &vcpu
->arch
.rmode
.ds
);
1464 fix_rmode_seg(VCPU_SREG_GS
, &vcpu
->arch
.rmode
.gs
);
1465 fix_rmode_seg(VCPU_SREG_FS
, &vcpu
->arch
.rmode
.fs
);
1468 kvm_mmu_reset_context(vcpu
);
1469 init_rmode(vcpu
->kvm
);
1472 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
1474 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1475 struct kvm_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
1477 vcpu
->arch
.shadow_efer
= efer
;
1480 if (efer
& EFER_LMA
) {
1481 vmcs_write32(VM_ENTRY_CONTROLS
,
1482 vmcs_read32(VM_ENTRY_CONTROLS
) |
1483 VM_ENTRY_IA32E_MODE
);
1486 vmcs_write32(VM_ENTRY_CONTROLS
,
1487 vmcs_read32(VM_ENTRY_CONTROLS
) &
1488 ~VM_ENTRY_IA32E_MODE
);
1490 msr
->data
= efer
& ~EFER_LME
;
1495 #ifdef CONFIG_X86_64
1497 static void enter_lmode(struct kvm_vcpu
*vcpu
)
1501 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
1502 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
1503 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
1505 vmcs_write32(GUEST_TR_AR_BYTES
,
1506 (guest_tr_ar
& ~AR_TYPE_MASK
)
1507 | AR_TYPE_BUSY_64_TSS
);
1509 vcpu
->arch
.shadow_efer
|= EFER_LMA
;
1510 vmx_set_efer(vcpu
, vcpu
->arch
.shadow_efer
);
1513 static void exit_lmode(struct kvm_vcpu
*vcpu
)
1515 vcpu
->arch
.shadow_efer
&= ~EFER_LMA
;
1517 vmcs_write32(VM_ENTRY_CONTROLS
,
1518 vmcs_read32(VM_ENTRY_CONTROLS
)
1519 & ~VM_ENTRY_IA32E_MODE
);
1524 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
1526 vpid_sync_vcpu_all(to_vmx(vcpu
));
1528 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
1531 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
1533 vcpu
->arch
.cr4
&= KVM_GUEST_CR4_MASK
;
1534 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & ~KVM_GUEST_CR4_MASK
;
1537 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
1539 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
1540 if (!load_pdptrs(vcpu
, vcpu
->arch
.cr3
)) {
1541 printk(KERN_ERR
"EPT: Fail to load pdptrs!\n");
1544 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.pdptrs
[0]);
1545 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.pdptrs
[1]);
1546 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.pdptrs
[2]);
1547 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.pdptrs
[3]);
1551 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
1553 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
1555 struct kvm_vcpu
*vcpu
)
1557 if (!(cr0
& X86_CR0_PG
)) {
1558 /* From paging/starting to nonpaging */
1559 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1560 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
1561 (CPU_BASED_CR3_LOAD_EXITING
|
1562 CPU_BASED_CR3_STORE_EXITING
));
1563 vcpu
->arch
.cr0
= cr0
;
1564 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1565 *hw_cr0
|= X86_CR0_PE
| X86_CR0_PG
;
1566 *hw_cr0
&= ~X86_CR0_WP
;
1567 } else if (!is_paging(vcpu
)) {
1568 /* From nonpaging to paging */
1569 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
1570 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
1571 ~(CPU_BASED_CR3_LOAD_EXITING
|
1572 CPU_BASED_CR3_STORE_EXITING
));
1573 vcpu
->arch
.cr0
= cr0
;
1574 vmx_set_cr4(vcpu
, vcpu
->arch
.cr4
);
1575 if (!(vcpu
->arch
.cr0
& X86_CR0_WP
))
1576 *hw_cr0
&= ~X86_CR0_WP
;
1580 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4
,
1581 struct kvm_vcpu
*vcpu
)
1583 if (!is_paging(vcpu
)) {
1584 *hw_cr4
&= ~X86_CR4_PAE
;
1585 *hw_cr4
|= X86_CR4_PSE
;
1586 } else if (!(vcpu
->arch
.cr4
& X86_CR4_PAE
))
1587 *hw_cr4
&= ~X86_CR4_PAE
;
1590 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
1592 unsigned long hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) |
1593 KVM_VM_CR0_ALWAYS_ON
;
1595 vmx_fpu_deactivate(vcpu
);
1597 if (vcpu
->arch
.rmode
.active
&& (cr0
& X86_CR0_PE
))
1600 if (!vcpu
->arch
.rmode
.active
&& !(cr0
& X86_CR0_PE
))
1603 #ifdef CONFIG_X86_64
1604 if (vcpu
->arch
.shadow_efer
& EFER_LME
) {
1605 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
1607 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
1613 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
1615 vmcs_writel(CR0_READ_SHADOW
, cr0
);
1616 vmcs_writel(GUEST_CR0
, hw_cr0
);
1617 vcpu
->arch
.cr0
= cr0
;
1619 if (!(cr0
& X86_CR0_TS
) || !(cr0
& X86_CR0_PE
))
1620 vmx_fpu_activate(vcpu
);
1623 static u64
construct_eptp(unsigned long root_hpa
)
1627 /* TODO write the value reading from MSR */
1628 eptp
= VMX_EPT_DEFAULT_MT
|
1629 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
1630 eptp
|= (root_hpa
& PAGE_MASK
);
1635 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
1637 unsigned long guest_cr3
;
1642 eptp
= construct_eptp(cr3
);
1643 vmcs_write64(EPT_POINTER
, eptp
);
1644 ept_sync_context(eptp
);
1645 ept_load_pdptrs(vcpu
);
1646 guest_cr3
= is_paging(vcpu
) ? vcpu
->arch
.cr3
:
1647 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
1650 vmx_flush_tlb(vcpu
);
1651 vmcs_writel(GUEST_CR3
, guest_cr3
);
1652 if (vcpu
->arch
.cr0
& X86_CR0_PE
)
1653 vmx_fpu_deactivate(vcpu
);
1656 static void vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
1658 unsigned long hw_cr4
= cr4
| (vcpu
->arch
.rmode
.active
?
1659 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
1661 vcpu
->arch
.cr4
= cr4
;
1663 ept_update_paging_mode_cr4(&hw_cr4
, vcpu
);
1665 vmcs_writel(CR4_READ_SHADOW
, cr4
);
1666 vmcs_writel(GUEST_CR4
, hw_cr4
);
1669 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
1671 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1673 return vmcs_readl(sf
->base
);
1676 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
1677 struct kvm_segment
*var
, int seg
)
1679 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1682 var
->base
= vmcs_readl(sf
->base
);
1683 var
->limit
= vmcs_read32(sf
->limit
);
1684 var
->selector
= vmcs_read16(sf
->selector
);
1685 ar
= vmcs_read32(sf
->ar_bytes
);
1686 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
1688 var
->type
= ar
& 15;
1689 var
->s
= (ar
>> 4) & 1;
1690 var
->dpl
= (ar
>> 5) & 3;
1691 var
->present
= (ar
>> 7) & 1;
1692 var
->avl
= (ar
>> 12) & 1;
1693 var
->l
= (ar
>> 13) & 1;
1694 var
->db
= (ar
>> 14) & 1;
1695 var
->g
= (ar
>> 15) & 1;
1696 var
->unusable
= (ar
>> 16) & 1;
1699 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
1701 struct kvm_segment kvm_seg
;
1703 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) /* if real mode */
1706 if (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) /* if virtual 8086 */
1709 vmx_get_segment(vcpu
, &kvm_seg
, VCPU_SREG_CS
);
1710 return kvm_seg
.selector
& 3;
1713 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
1720 ar
= var
->type
& 15;
1721 ar
|= (var
->s
& 1) << 4;
1722 ar
|= (var
->dpl
& 3) << 5;
1723 ar
|= (var
->present
& 1) << 7;
1724 ar
|= (var
->avl
& 1) << 12;
1725 ar
|= (var
->l
& 1) << 13;
1726 ar
|= (var
->db
& 1) << 14;
1727 ar
|= (var
->g
& 1) << 15;
1729 if (ar
== 0) /* a 0 value means unusable */
1730 ar
= AR_UNUSABLE_MASK
;
1735 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
1736 struct kvm_segment
*var
, int seg
)
1738 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
1741 if (vcpu
->arch
.rmode
.active
&& seg
== VCPU_SREG_TR
) {
1742 vcpu
->arch
.rmode
.tr
.selector
= var
->selector
;
1743 vcpu
->arch
.rmode
.tr
.base
= var
->base
;
1744 vcpu
->arch
.rmode
.tr
.limit
= var
->limit
;
1745 vcpu
->arch
.rmode
.tr
.ar
= vmx_segment_access_rights(var
);
1748 vmcs_writel(sf
->base
, var
->base
);
1749 vmcs_write32(sf
->limit
, var
->limit
);
1750 vmcs_write16(sf
->selector
, var
->selector
);
1751 if (vcpu
->arch
.rmode
.active
&& var
->s
) {
1753 * Hack real-mode segments into vm86 compatibility.
1755 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
1756 vmcs_writel(sf
->base
, 0xf0000);
1759 ar
= vmx_segment_access_rights(var
);
1760 vmcs_write32(sf
->ar_bytes
, ar
);
1763 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
1765 u32 ar
= vmcs_read32(GUEST_CS_AR_BYTES
);
1767 *db
= (ar
>> 14) & 1;
1768 *l
= (ar
>> 13) & 1;
1771 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1773 dt
->limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
1774 dt
->base
= vmcs_readl(GUEST_IDTR_BASE
);
1777 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1779 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->limit
);
1780 vmcs_writel(GUEST_IDTR_BASE
, dt
->base
);
1783 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1785 dt
->limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
1786 dt
->base
= vmcs_readl(GUEST_GDTR_BASE
);
1789 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct descriptor_table
*dt
)
1791 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->limit
);
1792 vmcs_writel(GUEST_GDTR_BASE
, dt
->base
);
1795 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1797 struct kvm_segment var
;
1800 vmx_get_segment(vcpu
, &var
, seg
);
1801 ar
= vmx_segment_access_rights(&var
);
1803 if (var
.base
!= (var
.selector
<< 4))
1805 if (var
.limit
!= 0xffff)
1813 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
1815 struct kvm_segment cs
;
1816 unsigned int cs_rpl
;
1818 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1819 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
1823 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
1827 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
1828 if (cs
.dpl
> cs_rpl
)
1831 if (cs
.dpl
!= cs_rpl
)
1837 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1841 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
1843 struct kvm_segment ss
;
1844 unsigned int ss_rpl
;
1846 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1847 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
1851 if (ss
.type
!= 3 && ss
.type
!= 7)
1855 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
1863 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
1865 struct kvm_segment var
;
1868 vmx_get_segment(vcpu
, &var
, seg
);
1869 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
1877 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
1878 if (var
.dpl
< rpl
) /* DPL < RPL */
1882 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1888 static bool tr_valid(struct kvm_vcpu
*vcpu
)
1890 struct kvm_segment tr
;
1892 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
1896 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
1898 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
1906 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
1908 struct kvm_segment ldtr
;
1910 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
1914 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
1924 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
1926 struct kvm_segment cs
, ss
;
1928 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
1929 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
1931 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
1932 (ss
.selector
& SELECTOR_RPL_MASK
));
1936 * Check if guest state is valid. Returns true if valid, false if
1938 * We assume that registers are always usable
1940 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
1942 /* real mode guest state checks */
1943 if (!(vcpu
->arch
.cr0
& X86_CR0_PE
)) {
1944 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
1946 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
1948 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
1950 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
1952 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
1954 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
1957 /* protected mode guest state checks */
1958 if (!cs_ss_rpl_check(vcpu
))
1960 if (!code_segment_valid(vcpu
))
1962 if (!stack_segment_valid(vcpu
))
1964 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
1966 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
1968 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
1970 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
1972 if (!tr_valid(vcpu
))
1974 if (!ldtr_valid(vcpu
))
1978 * - Add checks on RIP
1979 * - Add checks on RFLAGS
1985 static int init_rmode_tss(struct kvm
*kvm
)
1987 gfn_t fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
1992 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
1995 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
1996 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
1997 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2000 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2003 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2007 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2008 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2018 static int init_rmode_identity_map(struct kvm
*kvm
)
2021 pfn_t identity_map_pfn
;
2026 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2027 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2028 "haven't been allocated!\n");
2031 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2034 identity_map_pfn
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
>> PAGE_SHIFT
;
2035 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2038 /* Set up identity-mapping pagetable for EPT in real mode */
2039 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2040 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2041 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2042 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2043 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2047 kvm
->arch
.ept_identity_pagetable_done
= true;
2053 static void seg_setup(int seg
)
2055 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2057 vmcs_write16(sf
->selector
, 0);
2058 vmcs_writel(sf
->base
, 0);
2059 vmcs_write32(sf
->limit
, 0xffff);
2060 vmcs_write32(sf
->ar_bytes
, 0xf3);
2063 static int alloc_apic_access_page(struct kvm
*kvm
)
2065 struct kvm_userspace_memory_region kvm_userspace_mem
;
2068 down_write(&kvm
->slots_lock
);
2069 if (kvm
->arch
.apic_access_page
)
2071 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
2072 kvm_userspace_mem
.flags
= 0;
2073 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
2074 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2075 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2079 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
2081 up_write(&kvm
->slots_lock
);
2085 static int alloc_identity_pagetable(struct kvm
*kvm
)
2087 struct kvm_userspace_memory_region kvm_userspace_mem
;
2090 down_write(&kvm
->slots_lock
);
2091 if (kvm
->arch
.ept_identity_pagetable
)
2093 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
2094 kvm_userspace_mem
.flags
= 0;
2095 kvm_userspace_mem
.guest_phys_addr
= VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
2096 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
2097 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
2101 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
2102 VMX_EPT_IDENTITY_PAGETABLE_ADDR
>> PAGE_SHIFT
);
2104 up_write(&kvm
->slots_lock
);
2108 static void allocate_vpid(struct vcpu_vmx
*vmx
)
2115 spin_lock(&vmx_vpid_lock
);
2116 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
2117 if (vpid
< VMX_NR_VPIDS
) {
2119 __set_bit(vpid
, vmx_vpid_bitmap
);
2121 spin_unlock(&vmx_vpid_lock
);
2124 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
2126 int f
= sizeof(unsigned long);
2128 if (!cpu_has_vmx_msr_bitmap())
2132 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2133 * have the write-low and read-high bitmap offsets the wrong way round.
2134 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2136 if (msr
<= 0x1fff) {
2137 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
2138 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
2139 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
2141 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
2142 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
2146 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
2149 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
2150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
2154 * Sets up the vmcs for emulated real mode.
2156 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
2158 u32 host_sysenter_cs
, msr_low
, msr_high
;
2160 u64 host_pat
, tsc_this
, tsc_base
;
2162 struct descriptor_table dt
;
2164 unsigned long kvm_vmx_return
;
2168 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
2169 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
2171 if (cpu_has_vmx_msr_bitmap())
2172 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
2174 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
2177 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
2178 vmcs_config
.pin_based_exec_ctrl
);
2180 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
2181 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
2182 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2183 #ifdef CONFIG_X86_64
2184 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
2185 CPU_BASED_CR8_LOAD_EXITING
;
2189 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
2190 CPU_BASED_CR3_LOAD_EXITING
|
2191 CPU_BASED_INVLPG_EXITING
;
2192 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
2194 if (cpu_has_secondary_exec_ctrls()) {
2195 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
2196 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2198 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
2200 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
2202 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
2203 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
2206 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
2207 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
2208 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
2210 vmcs_writel(HOST_CR0
, read_cr0()); /* 22.2.3 */
2211 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
2212 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2214 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
2215 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2216 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2217 vmcs_write16(HOST_FS_SELECTOR
, kvm_read_fs()); /* 22.2.4 */
2218 vmcs_write16(HOST_GS_SELECTOR
, kvm_read_gs()); /* 22.2.4 */
2219 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
2220 #ifdef CONFIG_X86_64
2221 rdmsrl(MSR_FS_BASE
, a
);
2222 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
2223 rdmsrl(MSR_GS_BASE
, a
);
2224 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
2226 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
2227 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
2230 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
2233 vmcs_writel(HOST_IDTR_BASE
, dt
.base
); /* 22.2.4 */
2235 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
2236 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
2237 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
2238 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
2239 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
2241 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
2242 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
2243 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
2244 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
2245 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
2246 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
2248 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
2249 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2250 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2251 vmcs_write64(HOST_IA32_PAT
, host_pat
);
2253 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2254 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
2255 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
2256 /* Write the default value follow host pat */
2257 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
2258 /* Keep arch.pat sync with GUEST_IA32_PAT */
2259 vmx
->vcpu
.arch
.pat
= host_pat
;
2262 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
2263 u32 index
= vmx_msr_index
[i
];
2264 u32 data_low
, data_high
;
2268 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
2270 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
2272 data
= data_low
| ((u64
)data_high
<< 32);
2273 vmx
->host_msrs
[j
].index
= index
;
2274 vmx
->host_msrs
[j
].reserved
= 0;
2275 vmx
->host_msrs
[j
].data
= data
;
2276 vmx
->guest_msrs
[j
] = vmx
->host_msrs
[j
];
2280 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
2282 /* 22.2.1, 20.8.1 */
2283 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
2285 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
2286 vmcs_writel(CR4_GUEST_HOST_MASK
, KVM_GUEST_CR4_MASK
);
2288 tsc_base
= vmx
->vcpu
.kvm
->arch
.vm_init_tsc
;
2290 if (tsc_this
< vmx
->vcpu
.kvm
->arch
.vm_init_tsc
)
2291 tsc_base
= tsc_this
;
2293 guest_write_tsc(0, tsc_base
);
2298 static int init_rmode(struct kvm
*kvm
)
2300 if (!init_rmode_tss(kvm
))
2302 if (!init_rmode_identity_map(kvm
))
2307 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
2309 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2313 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
2314 down_read(&vcpu
->kvm
->slots_lock
);
2315 if (!init_rmode(vmx
->vcpu
.kvm
)) {
2320 vmx
->vcpu
.arch
.rmode
.active
= 0;
2322 vmx
->soft_vnmi_blocked
= 0;
2324 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
2325 kvm_set_cr8(&vmx
->vcpu
, 0);
2326 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
2327 if (vmx
->vcpu
.vcpu_id
== 0)
2328 msr
|= MSR_IA32_APICBASE_BSP
;
2329 kvm_set_apic_base(&vmx
->vcpu
, msr
);
2331 fx_init(&vmx
->vcpu
);
2333 seg_setup(VCPU_SREG_CS
);
2335 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2336 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2338 if (vmx
->vcpu
.vcpu_id
== 0) {
2339 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
2340 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
2342 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
2343 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
2346 seg_setup(VCPU_SREG_DS
);
2347 seg_setup(VCPU_SREG_ES
);
2348 seg_setup(VCPU_SREG_FS
);
2349 seg_setup(VCPU_SREG_GS
);
2350 seg_setup(VCPU_SREG_SS
);
2352 vmcs_write16(GUEST_TR_SELECTOR
, 0);
2353 vmcs_writel(GUEST_TR_BASE
, 0);
2354 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
2355 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2357 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
2358 vmcs_writel(GUEST_LDTR_BASE
, 0);
2359 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
2360 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
2362 vmcs_write32(GUEST_SYSENTER_CS
, 0);
2363 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
2364 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
2366 vmcs_writel(GUEST_RFLAGS
, 0x02);
2367 if (vmx
->vcpu
.vcpu_id
== 0)
2368 kvm_rip_write(vcpu
, 0xfff0);
2370 kvm_rip_write(vcpu
, 0);
2371 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
2373 vmcs_writel(GUEST_DR7
, 0x400);
2375 vmcs_writel(GUEST_GDTR_BASE
, 0);
2376 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
2378 vmcs_writel(GUEST_IDTR_BASE
, 0);
2379 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
2381 vmcs_write32(GUEST_ACTIVITY_STATE
, 0);
2382 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
2383 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
2385 /* Special registers */
2386 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
2390 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
2392 if (cpu_has_vmx_tpr_shadow()) {
2393 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
2394 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
2395 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
2396 page_to_phys(vmx
->vcpu
.arch
.apic
->regs_page
));
2397 vmcs_write32(TPR_THRESHOLD
, 0);
2400 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
2401 vmcs_write64(APIC_ACCESS_ADDR
,
2402 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
2405 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
2407 vmx
->vcpu
.arch
.cr0
= 0x60000010;
2408 vmx_set_cr0(&vmx
->vcpu
, vmx
->vcpu
.arch
.cr0
); /* enter rmode */
2409 vmx_set_cr4(&vmx
->vcpu
, 0);
2410 vmx_set_efer(&vmx
->vcpu
, 0);
2411 vmx_fpu_activate(&vmx
->vcpu
);
2412 update_exception_bitmap(&vmx
->vcpu
);
2414 vpid_sync_vcpu_all(vmx
);
2418 /* HACK: Don't enable emulation on guest boot/reset */
2419 vmx
->emulation_required
= 0;
2422 up_read(&vcpu
->kvm
->slots_lock
);
2426 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
2428 u32 cpu_based_vm_exec_control
;
2430 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2431 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
2432 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2435 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
2437 u32 cpu_based_vm_exec_control
;
2439 if (!cpu_has_virtual_nmis()) {
2440 enable_irq_window(vcpu
);
2444 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2445 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
2446 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2449 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
2451 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2453 int irq
= vcpu
->arch
.interrupt
.nr
;
2455 KVMTRACE_1D(INJ_VIRQ
, vcpu
, (u32
)irq
, handler
);
2457 ++vcpu
->stat
.irq_injections
;
2458 if (vcpu
->arch
.rmode
.active
) {
2459 vmx
->rmode
.irq
.pending
= true;
2460 vmx
->rmode
.irq
.vector
= irq
;
2461 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2462 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2463 irq
| INTR_TYPE_SOFT_INTR
| INTR_INFO_VALID_MASK
);
2464 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2465 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2468 intr
= irq
| INTR_INFO_VALID_MASK
;
2469 if (vcpu
->arch
.interrupt
.soft
) {
2470 intr
|= INTR_TYPE_SOFT_INTR
;
2471 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2472 vmx
->vcpu
.arch
.event_exit_inst_len
);
2474 intr
|= INTR_TYPE_EXT_INTR
;
2475 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
2478 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
2480 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2482 if (!cpu_has_virtual_nmis()) {
2484 * Tracking the NMI-blocked state in software is built upon
2485 * finding the next open IRQ window. This, in turn, depends on
2486 * well-behaving guests: They have to keep IRQs disabled at
2487 * least as long as the NMI handler runs. Otherwise we may
2488 * cause NMI nesting, maybe breaking the guest. But as this is
2489 * highly unlikely, we can live with the residual risk.
2491 vmx
->soft_vnmi_blocked
= 1;
2492 vmx
->vnmi_blocked_time
= 0;
2495 ++vcpu
->stat
.nmi_injections
;
2496 if (vcpu
->arch
.rmode
.active
) {
2497 vmx
->rmode
.irq
.pending
= true;
2498 vmx
->rmode
.irq
.vector
= NMI_VECTOR
;
2499 vmx
->rmode
.irq
.rip
= kvm_rip_read(vcpu
);
2500 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2501 NMI_VECTOR
| INTR_TYPE_SOFT_INTR
|
2502 INTR_INFO_VALID_MASK
);
2503 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
, 1);
2504 kvm_rip_write(vcpu
, vmx
->rmode
.irq
.rip
- 1);
2507 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
2508 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
2511 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
2513 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
2516 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2517 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
|
2518 GUEST_INTR_STATE_NMI
));
2521 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
2523 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
2524 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
2525 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
2528 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
2531 struct kvm_userspace_memory_region tss_mem
= {
2532 .slot
= TSS_PRIVATE_MEMSLOT
,
2533 .guest_phys_addr
= addr
,
2534 .memory_size
= PAGE_SIZE
* 3,
2538 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
2541 kvm
->arch
.tss_addr
= addr
;
2545 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
2546 int vec
, u32 err_code
)
2549 * Instruction with address size override prefix opcode 0x67
2550 * Cause the #SS fault with 0 error code in VM86 mode.
2552 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
2553 if (emulate_instruction(vcpu
, NULL
, 0, 0, 0) == EMULATE_DONE
)
2556 * Forward all other exceptions that are valid in real mode.
2557 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2558 * the required debugging infrastructure rework.
2562 if (vcpu
->guest_debug
&
2563 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
2565 kvm_queue_exception(vcpu
, vec
);
2568 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
2579 kvm_queue_exception(vcpu
, vec
);
2585 static int handle_exception(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2588 u32 intr_info
, ex_no
, error_code
;
2589 unsigned long cr2
, rip
, dr6
;
2591 enum emulation_result er
;
2593 vect_info
= vmx
->idt_vectoring_info
;
2594 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
2596 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
2597 !is_page_fault(intr_info
))
2598 printk(KERN_ERR
"%s: unexpected, vectoring info 0x%x "
2599 "intr info 0x%x\n", __func__
, vect_info
, intr_info
);
2601 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
2602 return 1; /* already handled by vmx_vcpu_run() */
2604 if (is_no_device(intr_info
)) {
2605 vmx_fpu_activate(vcpu
);
2609 if (is_invalid_opcode(intr_info
)) {
2610 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, EMULTYPE_TRAP_UD
);
2611 if (er
!= EMULATE_DONE
)
2612 kvm_queue_exception(vcpu
, UD_VECTOR
);
2617 rip
= kvm_rip_read(vcpu
);
2618 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
2619 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
2620 if (is_page_fault(intr_info
)) {
2621 /* EPT won't cause page fault directly */
2624 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
2625 KVMTRACE_3D(PAGE_FAULT
, vcpu
, error_code
, (u32
)cr2
,
2626 (u32
)((u64
)cr2
>> 32), handler
);
2627 if (kvm_event_needs_reinjection(vcpu
))
2628 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
2629 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
);
2632 if (vcpu
->arch
.rmode
.active
&&
2633 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
2635 if (vcpu
->arch
.halt_request
) {
2636 vcpu
->arch
.halt_request
= 0;
2637 return kvm_emulate_halt(vcpu
);
2642 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
2645 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
2646 if (!(vcpu
->guest_debug
&
2647 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
2648 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
2649 kvm_queue_exception(vcpu
, DB_VECTOR
);
2652 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
2653 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
2656 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2657 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
2658 kvm_run
->debug
.arch
.exception
= ex_no
;
2661 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
2662 kvm_run
->ex
.exception
= ex_no
;
2663 kvm_run
->ex
.error_code
= error_code
;
2669 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
,
2670 struct kvm_run
*kvm_run
)
2672 ++vcpu
->stat
.irq_exits
;
2673 KVMTRACE_1D(INTR
, vcpu
, vmcs_read32(VM_EXIT_INTR_INFO
), handler
);
2677 static int handle_triple_fault(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2679 kvm_run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
2683 static int handle_io(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2685 unsigned long exit_qualification
;
2686 int size
, in
, string
;
2689 ++vcpu
->stat
.io_exits
;
2690 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2691 string
= (exit_qualification
& 16) != 0;
2694 if (emulate_instruction(vcpu
,
2695 kvm_run
, 0, 0, 0) == EMULATE_DO_MMIO
)
2700 size
= (exit_qualification
& 7) + 1;
2701 in
= (exit_qualification
& 8) != 0;
2702 port
= exit_qualification
>> 16;
2704 skip_emulated_instruction(vcpu
);
2705 return kvm_emulate_pio(vcpu
, kvm_run
, in
, size
, port
);
2709 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
2712 * Patch in the VMCALL instruction:
2714 hypercall
[0] = 0x0f;
2715 hypercall
[1] = 0x01;
2716 hypercall
[2] = 0xc1;
2719 static int handle_cr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2721 unsigned long exit_qualification
;
2725 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2726 cr
= exit_qualification
& 15;
2727 reg
= (exit_qualification
>> 8) & 15;
2728 switch ((exit_qualification
>> 4) & 3) {
2729 case 0: /* mov to cr */
2730 KVMTRACE_3D(CR_WRITE
, vcpu
, (u32
)cr
,
2731 (u32
)kvm_register_read(vcpu
, reg
),
2732 (u32
)((u64
)kvm_register_read(vcpu
, reg
) >> 32),
2736 kvm_set_cr0(vcpu
, kvm_register_read(vcpu
, reg
));
2737 skip_emulated_instruction(vcpu
);
2740 kvm_set_cr3(vcpu
, kvm_register_read(vcpu
, reg
));
2741 skip_emulated_instruction(vcpu
);
2744 kvm_set_cr4(vcpu
, kvm_register_read(vcpu
, reg
));
2745 skip_emulated_instruction(vcpu
);
2748 u8 cr8_prev
= kvm_get_cr8(vcpu
);
2749 u8 cr8
= kvm_register_read(vcpu
, reg
);
2750 kvm_set_cr8(vcpu
, cr8
);
2751 skip_emulated_instruction(vcpu
);
2752 if (irqchip_in_kernel(vcpu
->kvm
))
2754 if (cr8_prev
<= cr8
)
2756 kvm_run
->exit_reason
= KVM_EXIT_SET_TPR
;
2762 vmx_fpu_deactivate(vcpu
);
2763 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
2764 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2765 vmx_fpu_activate(vcpu
);
2766 KVMTRACE_0D(CLTS
, vcpu
, handler
);
2767 skip_emulated_instruction(vcpu
);
2769 case 1: /*mov from cr*/
2772 kvm_register_write(vcpu
, reg
, vcpu
->arch
.cr3
);
2773 KVMTRACE_3D(CR_READ
, vcpu
, (u32
)cr
,
2774 (u32
)kvm_register_read(vcpu
, reg
),
2775 (u32
)((u64
)kvm_register_read(vcpu
, reg
) >> 32),
2777 skip_emulated_instruction(vcpu
);
2780 kvm_register_write(vcpu
, reg
, kvm_get_cr8(vcpu
));
2781 KVMTRACE_2D(CR_READ
, vcpu
, (u32
)cr
,
2782 (u32
)kvm_register_read(vcpu
, reg
), handler
);
2783 skip_emulated_instruction(vcpu
);
2788 kvm_lmsw(vcpu
, (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f);
2790 skip_emulated_instruction(vcpu
);
2795 kvm_run
->exit_reason
= 0;
2796 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
2797 (int)(exit_qualification
>> 4) & 3, cr
);
2801 static int handle_dr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2803 unsigned long exit_qualification
;
2807 dr
= vmcs_readl(GUEST_DR7
);
2810 * As the vm-exit takes precedence over the debug trap, we
2811 * need to emulate the latter, either for the host or the
2812 * guest debugging itself.
2814 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
2815 kvm_run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
2816 kvm_run
->debug
.arch
.dr7
= dr
;
2817 kvm_run
->debug
.arch
.pc
=
2818 vmcs_readl(GUEST_CS_BASE
) +
2819 vmcs_readl(GUEST_RIP
);
2820 kvm_run
->debug
.arch
.exception
= DB_VECTOR
;
2821 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
2824 vcpu
->arch
.dr7
&= ~DR7_GD
;
2825 vcpu
->arch
.dr6
|= DR6_BD
;
2826 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2827 kvm_queue_exception(vcpu
, DB_VECTOR
);
2832 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2833 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
2834 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
2835 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
2838 val
= vcpu
->arch
.db
[dr
];
2841 val
= vcpu
->arch
.dr6
;
2844 val
= vcpu
->arch
.dr7
;
2849 kvm_register_write(vcpu
, reg
, val
);
2850 KVMTRACE_2D(DR_READ
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
2852 val
= vcpu
->arch
.regs
[reg
];
2855 vcpu
->arch
.db
[dr
] = val
;
2856 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
))
2857 vcpu
->arch
.eff_db
[dr
] = val
;
2860 if (vcpu
->arch
.cr4
& X86_CR4_DE
)
2861 kvm_queue_exception(vcpu
, UD_VECTOR
);
2864 if (val
& 0xffffffff00000000ULL
) {
2865 kvm_queue_exception(vcpu
, GP_VECTOR
);
2868 vcpu
->arch
.dr6
= (val
& DR6_VOLATILE
) | DR6_FIXED_1
;
2871 if (val
& 0xffffffff00000000ULL
) {
2872 kvm_queue_exception(vcpu
, GP_VECTOR
);
2875 vcpu
->arch
.dr7
= (val
& DR7_VOLATILE
) | DR7_FIXED_1
;
2876 if (!(vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)) {
2877 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
2878 vcpu
->arch
.switch_db_regs
=
2879 (val
& DR7_BP_EN_MASK
);
2883 KVMTRACE_2D(DR_WRITE
, vcpu
, (u32
)dr
, (u32
)val
, handler
);
2885 skip_emulated_instruction(vcpu
);
2889 static int handle_cpuid(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2891 kvm_emulate_cpuid(vcpu
);
2895 static int handle_rdmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2897 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2900 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
2901 kvm_inject_gp(vcpu
, 0);
2905 KVMTRACE_3D(MSR_READ
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2908 /* FIXME: handling of bits 32:63 of rax, rdx */
2909 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
2910 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
2911 skip_emulated_instruction(vcpu
);
2915 static int handle_wrmsr(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2917 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
2918 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
2919 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
2921 KVMTRACE_3D(MSR_WRITE
, vcpu
, ecx
, (u32
)data
, (u32
)(data
>> 32),
2924 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
2925 kvm_inject_gp(vcpu
, 0);
2929 skip_emulated_instruction(vcpu
);
2933 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
,
2934 struct kvm_run
*kvm_run
)
2939 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
,
2940 struct kvm_run
*kvm_run
)
2942 u32 cpu_based_vm_exec_control
;
2944 /* clear pending irq */
2945 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
2946 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
2947 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
2949 KVMTRACE_0D(PEND_INTR
, vcpu
, handler
);
2950 ++vcpu
->stat
.irq_window_exits
;
2953 * If the user space waits to inject interrupts, exit as soon as
2956 if (!irqchip_in_kernel(vcpu
->kvm
) &&
2957 kvm_run
->request_interrupt_window
&&
2958 !kvm_cpu_has_interrupt(vcpu
)) {
2959 kvm_run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
2965 static int handle_halt(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2967 skip_emulated_instruction(vcpu
);
2968 return kvm_emulate_halt(vcpu
);
2971 static int handle_vmcall(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2973 skip_emulated_instruction(vcpu
);
2974 kvm_emulate_hypercall(vcpu
);
2978 static int handle_invlpg(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2980 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
2982 kvm_mmu_invlpg(vcpu
, exit_qualification
);
2983 skip_emulated_instruction(vcpu
);
2987 static int handle_wbinvd(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2989 skip_emulated_instruction(vcpu
);
2990 /* TODO: Add support for VT-d/pass-through device */
2994 static int handle_apic_access(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
2996 unsigned long exit_qualification
;
2997 enum emulation_result er
;
2998 unsigned long offset
;
3000 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3001 offset
= exit_qualification
& 0xffful
;
3003 er
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3005 if (er
!= EMULATE_DONE
) {
3007 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3014 static int handle_task_switch(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3016 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3017 unsigned long exit_qualification
;
3019 int reason
, type
, idt_v
;
3021 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
3022 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
3024 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3026 reason
= (u32
)exit_qualification
>> 30;
3027 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
3029 case INTR_TYPE_NMI_INTR
:
3030 vcpu
->arch
.nmi_injected
= false;
3031 if (cpu_has_virtual_nmis())
3032 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3033 GUEST_INTR_STATE_NMI
);
3035 case INTR_TYPE_EXT_INTR
:
3036 case INTR_TYPE_SOFT_INTR
:
3037 kvm_clear_interrupt_queue(vcpu
);
3039 case INTR_TYPE_HARD_EXCEPTION
:
3040 case INTR_TYPE_SOFT_EXCEPTION
:
3041 kvm_clear_exception_queue(vcpu
);
3047 tss_selector
= exit_qualification
;
3049 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
3050 type
!= INTR_TYPE_EXT_INTR
&&
3051 type
!= INTR_TYPE_NMI_INTR
))
3052 skip_emulated_instruction(vcpu
);
3054 if (!kvm_task_switch(vcpu
, tss_selector
, reason
))
3057 /* clear all local breakpoint enable flags */
3058 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
3061 * TODO: What about debug traps on tss switch?
3062 * Are we supposed to inject them and update dr6?
3068 static int handle_ept_violation(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3070 unsigned long exit_qualification
;
3074 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3076 if (exit_qualification
& (1 << 6)) {
3077 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
3081 gla_validity
= (exit_qualification
>> 7) & 0x3;
3082 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
3083 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
3084 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3085 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
3086 vmcs_readl(GUEST_LINEAR_ADDRESS
));
3087 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
3088 (long unsigned int)exit_qualification
);
3089 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3090 kvm_run
->hw
.hardware_exit_reason
= 0;
3094 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
3095 return kvm_mmu_page_fault(vcpu
, gpa
& PAGE_MASK
, 0);
3098 static int handle_nmi_window(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3100 u32 cpu_based_vm_exec_control
;
3102 /* clear pending NMI */
3103 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3104 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
3105 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3106 ++vcpu
->stat
.nmi_window_exits
;
3111 static void handle_invalid_guest_state(struct kvm_vcpu
*vcpu
,
3112 struct kvm_run
*kvm_run
)
3114 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3115 enum emulation_result err
= EMULATE_DONE
;
3120 while (!guest_state_valid(vcpu
)) {
3121 err
= emulate_instruction(vcpu
, kvm_run
, 0, 0, 0);
3123 if (err
== EMULATE_DO_MMIO
)
3126 if (err
!= EMULATE_DONE
) {
3127 kvm_report_emulation_failure(vcpu
, "emulation failure");
3131 if (signal_pending(current
))
3137 local_irq_disable();
3140 vmx
->invalid_state_emulation_result
= err
;
3144 * The exit handlers return 1 if the exit was handled fully and guest execution
3145 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3146 * to be done to userspace and return 0.
3148 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
,
3149 struct kvm_run
*kvm_run
) = {
3150 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
3151 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
3152 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
3153 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
3154 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
3155 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
3156 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
3157 [EXIT_REASON_CPUID
] = handle_cpuid
,
3158 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
3159 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
3160 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
3161 [EXIT_REASON_HLT
] = handle_halt
,
3162 [EXIT_REASON_INVLPG
] = handle_invlpg
,
3163 [EXIT_REASON_VMCALL
] = handle_vmcall
,
3164 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
3165 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
3166 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
3167 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
3168 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
3171 static const int kvm_vmx_max_exit_handlers
=
3172 ARRAY_SIZE(kvm_vmx_exit_handlers
);
3175 * The guest has exited. See if we can fix it or if we need userspace
3178 static int vmx_handle_exit(struct kvm_run
*kvm_run
, struct kvm_vcpu
*vcpu
)
3180 u32 exit_reason
= vmcs_read32(VM_EXIT_REASON
);
3181 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3182 u32 vectoring_info
= vmx
->idt_vectoring_info
;
3184 KVMTRACE_3D(VMEXIT
, vcpu
, exit_reason
, (u32
)kvm_rip_read(vcpu
),
3185 (u32
)((u64
)kvm_rip_read(vcpu
) >> 32), entryexit
);
3187 /* If we need to emulate an MMIO from handle_invalid_guest_state
3188 * we just return 0 */
3189 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3190 if (guest_state_valid(vcpu
))
3191 vmx
->emulation_required
= 0;
3192 return vmx
->invalid_state_emulation_result
!= EMULATE_DO_MMIO
;
3195 /* Access CR3 don't cause VMExit in paging mode, so we need
3196 * to sync with guest real CR3. */
3197 if (enable_ept
&& is_paging(vcpu
)) {
3198 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3199 ept_load_pdptrs(vcpu
);
3202 if (unlikely(vmx
->fail
)) {
3203 kvm_run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
3204 kvm_run
->fail_entry
.hardware_entry_failure_reason
3205 = vmcs_read32(VM_INSTRUCTION_ERROR
);
3209 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
3210 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
3211 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
3212 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
3213 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
3214 "(0x%x) and exit reason is 0x%x\n",
3215 __func__
, vectoring_info
, exit_reason
);
3217 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
3218 if (vmx_interrupt_allowed(vcpu
)) {
3219 vmx
->soft_vnmi_blocked
= 0;
3220 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
3221 vcpu
->arch
.nmi_pending
) {
3223 * This CPU don't support us in finding the end of an
3224 * NMI-blocked window if the guest runs with IRQs
3225 * disabled. So we pull the trigger after 1 s of
3226 * futile waiting, but inform the user about this.
3228 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
3229 "state on VCPU %d after 1 s timeout\n",
3230 __func__
, vcpu
->vcpu_id
);
3231 vmx
->soft_vnmi_blocked
= 0;
3235 if (exit_reason
< kvm_vmx_max_exit_handlers
3236 && kvm_vmx_exit_handlers
[exit_reason
])
3237 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
, kvm_run
);
3239 kvm_run
->exit_reason
= KVM_EXIT_UNKNOWN
;
3240 kvm_run
->hw
.hardware_exit_reason
= exit_reason
;
3245 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
3247 if (irr
== -1 || tpr
< irr
) {
3248 vmcs_write32(TPR_THRESHOLD
, 0);
3252 vmcs_write32(TPR_THRESHOLD
, irr
);
3255 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
3258 u32 idt_vectoring_info
= vmx
->idt_vectoring_info
;
3262 bool idtv_info_valid
;
3264 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
3266 /* We need to handle NMIs before interrupts are enabled */
3267 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
3268 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
3269 KVMTRACE_0D(NMI
, &vmx
->vcpu
, handler
);
3273 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
3275 if (cpu_has_virtual_nmis()) {
3276 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
3277 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
3279 * SDM 3: 27.7.1.2 (September 2008)
3280 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3281 * a guest IRET fault.
3282 * SDM 3: 23.2.2 (September 2008)
3283 * Bit 12 is undefined in any of the following cases:
3284 * If the VM exit sets the valid bit in the IDT-vectoring
3285 * information field.
3286 * If the VM exit is due to a double fault.
3288 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
3289 vector
!= DF_VECTOR
&& !idtv_info_valid
)
3290 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3291 GUEST_INTR_STATE_NMI
);
3292 } else if (unlikely(vmx
->soft_vnmi_blocked
))
3293 vmx
->vnmi_blocked_time
+=
3294 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
3296 vmx
->vcpu
.arch
.nmi_injected
= false;
3297 kvm_clear_exception_queue(&vmx
->vcpu
);
3298 kvm_clear_interrupt_queue(&vmx
->vcpu
);
3300 if (!idtv_info_valid
)
3303 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
3304 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
3307 case INTR_TYPE_NMI_INTR
:
3308 vmx
->vcpu
.arch
.nmi_injected
= true;
3310 * SDM 3: 27.7.1.2 (September 2008)
3311 * Clear bit "block by NMI" before VM entry if a NMI
3314 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3315 GUEST_INTR_STATE_NMI
);
3317 case INTR_TYPE_SOFT_EXCEPTION
:
3318 vmx
->vcpu
.arch
.event_exit_inst_len
=
3319 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3321 case INTR_TYPE_HARD_EXCEPTION
:
3322 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
3323 u32 err
= vmcs_read32(IDT_VECTORING_ERROR_CODE
);
3324 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
3326 kvm_queue_exception(&vmx
->vcpu
, vector
);
3328 case INTR_TYPE_SOFT_INTR
:
3329 vmx
->vcpu
.arch
.event_exit_inst_len
=
3330 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3332 case INTR_TYPE_EXT_INTR
:
3333 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
3334 type
== INTR_TYPE_SOFT_INTR
);
3342 * Failure to inject an interrupt should give us the information
3343 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3344 * when fetching the interrupt redirection bitmap in the real-mode
3345 * tss, this doesn't happen. So we do it ourselves.
3347 static void fixup_rmode_irq(struct vcpu_vmx
*vmx
)
3349 vmx
->rmode
.irq
.pending
= 0;
3350 if (kvm_rip_read(&vmx
->vcpu
) + 1 != vmx
->rmode
.irq
.rip
)
3352 kvm_rip_write(&vmx
->vcpu
, vmx
->rmode
.irq
.rip
);
3353 if (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) {
3354 vmx
->idt_vectoring_info
&= ~VECTORING_INFO_TYPE_MASK
;
3355 vmx
->idt_vectoring_info
|= INTR_TYPE_EXT_INTR
;
3358 vmx
->idt_vectoring_info
=
3359 VECTORING_INFO_VALID_MASK
3360 | INTR_TYPE_EXT_INTR
3361 | vmx
->rmode
.irq
.vector
;
3364 #ifdef CONFIG_X86_64
3372 static void vmx_vcpu_run(struct kvm_vcpu
*vcpu
, struct kvm_run
*kvm_run
)
3374 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3376 /* Record the guest's net vcpu time for enforced NMI injections. */
3377 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
3378 vmx
->entry_time
= ktime_get();
3380 /* Handle invalid guest state instead of entering VMX */
3381 if (vmx
->emulation_required
&& emulate_invalid_guest_state
) {
3382 handle_invalid_guest_state(vcpu
, kvm_run
);
3386 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3387 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
3388 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
3389 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
3392 * Loading guest fpu may have cleared host cr0.ts
3394 vmcs_writel(HOST_CR0
, read_cr0());
3396 set_debugreg(vcpu
->arch
.dr6
, 6);
3399 /* Store host registers */
3400 "push %%"R
"dx; push %%"R
"bp;"
3402 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
3404 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
3405 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
3407 /* Check if vmlaunch of vmresume is needed */
3408 "cmpl $0, %c[launched](%0) \n\t"
3409 /* Load guest registers. Don't clobber flags. */
3410 "mov %c[cr2](%0), %%"R
"ax \n\t"
3411 "mov %%"R
"ax, %%cr2 \n\t"
3412 "mov %c[rax](%0), %%"R
"ax \n\t"
3413 "mov %c[rbx](%0), %%"R
"bx \n\t"
3414 "mov %c[rdx](%0), %%"R
"dx \n\t"
3415 "mov %c[rsi](%0), %%"R
"si \n\t"
3416 "mov %c[rdi](%0), %%"R
"di \n\t"
3417 "mov %c[rbp](%0), %%"R
"bp \n\t"
3418 #ifdef CONFIG_X86_64
3419 "mov %c[r8](%0), %%r8 \n\t"
3420 "mov %c[r9](%0), %%r9 \n\t"
3421 "mov %c[r10](%0), %%r10 \n\t"
3422 "mov %c[r11](%0), %%r11 \n\t"
3423 "mov %c[r12](%0), %%r12 \n\t"
3424 "mov %c[r13](%0), %%r13 \n\t"
3425 "mov %c[r14](%0), %%r14 \n\t"
3426 "mov %c[r15](%0), %%r15 \n\t"
3428 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
3430 /* Enter guest mode */
3431 "jne .Llaunched \n\t"
3432 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
3433 "jmp .Lkvm_vmx_return \n\t"
3434 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
3435 ".Lkvm_vmx_return: "
3436 /* Save guest registers, load host registers, keep flags */
3437 "xchg %0, (%%"R
"sp) \n\t"
3438 "mov %%"R
"ax, %c[rax](%0) \n\t"
3439 "mov %%"R
"bx, %c[rbx](%0) \n\t"
3440 "push"Q
" (%%"R
"sp); pop"Q
" %c[rcx](%0) \n\t"
3441 "mov %%"R
"dx, %c[rdx](%0) \n\t"
3442 "mov %%"R
"si, %c[rsi](%0) \n\t"
3443 "mov %%"R
"di, %c[rdi](%0) \n\t"
3444 "mov %%"R
"bp, %c[rbp](%0) \n\t"
3445 #ifdef CONFIG_X86_64
3446 "mov %%r8, %c[r8](%0) \n\t"
3447 "mov %%r9, %c[r9](%0) \n\t"
3448 "mov %%r10, %c[r10](%0) \n\t"
3449 "mov %%r11, %c[r11](%0) \n\t"
3450 "mov %%r12, %c[r12](%0) \n\t"
3451 "mov %%r13, %c[r13](%0) \n\t"
3452 "mov %%r14, %c[r14](%0) \n\t"
3453 "mov %%r15, %c[r15](%0) \n\t"
3455 "mov %%cr2, %%"R
"ax \n\t"
3456 "mov %%"R
"ax, %c[cr2](%0) \n\t"
3458 "pop %%"R
"bp; pop %%"R
"bp; pop %%"R
"dx \n\t"
3459 "setbe %c[fail](%0) \n\t"
3460 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
3461 [launched
]"i"(offsetof(struct vcpu_vmx
, launched
)),
3462 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
3463 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
3464 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
3465 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
3466 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
3467 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
3468 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
3469 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
3470 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
3471 #ifdef CONFIG_X86_64
3472 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
3473 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
3474 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
3475 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
3476 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
3477 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
3478 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
3479 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
3481 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
))
3483 , R
"bx", R
"di", R
"si"
3484 #ifdef CONFIG_X86_64
3485 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3489 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3490 vcpu
->arch
.regs_dirty
= 0;
3492 get_debugreg(vcpu
->arch
.dr6
, 6);
3494 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
3495 if (vmx
->rmode
.irq
.pending
)
3496 fixup_rmode_irq(vmx
);
3498 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
3501 vmx_complete_interrupts(vmx
);
3507 static void vmx_free_vmcs(struct kvm_vcpu
*vcpu
)
3509 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3513 free_vmcs(vmx
->vmcs
);
3518 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
3520 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3522 spin_lock(&vmx_vpid_lock
);
3524 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3525 spin_unlock(&vmx_vpid_lock
);
3526 vmx_free_vmcs(vcpu
);
3527 kfree(vmx
->host_msrs
);
3528 kfree(vmx
->guest_msrs
);
3529 kvm_vcpu_uninit(vcpu
);
3530 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3533 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
3536 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
3540 return ERR_PTR(-ENOMEM
);
3544 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
3548 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3549 if (!vmx
->guest_msrs
) {
3554 vmx
->host_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
3555 if (!vmx
->host_msrs
)
3556 goto free_guest_msrs
;
3558 vmx
->vmcs
= alloc_vmcs();
3562 vmcs_clear(vmx
->vmcs
);
3565 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
3566 err
= vmx_vcpu_setup(vmx
);
3567 vmx_vcpu_put(&vmx
->vcpu
);
3571 if (vm_need_virtualize_apic_accesses(kvm
))
3572 if (alloc_apic_access_page(kvm
) != 0)
3576 if (alloc_identity_pagetable(kvm
) != 0)
3582 free_vmcs(vmx
->vmcs
);
3584 kfree(vmx
->host_msrs
);
3586 kfree(vmx
->guest_msrs
);
3588 kvm_vcpu_uninit(&vmx
->vcpu
);
3590 kmem_cache_free(kvm_vcpu_cache
, vmx
);
3591 return ERR_PTR(err
);
3594 static void __init
vmx_check_processor_compat(void *rtn
)
3596 struct vmcs_config vmcs_conf
;
3599 if (setup_vmcs_config(&vmcs_conf
) < 0)
3601 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
3602 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
3603 smp_processor_id());
3608 static int get_ept_level(void)
3610 return VMX_EPT_DEFAULT_GAW
+ 1;
3613 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
3617 /* For VT-d and EPT combination
3618 * 1. MMIO: always map as UC
3620 * a. VT-d without snooping control feature: can't guarantee the
3621 * result, try to trust guest.
3622 * b. VT-d with snooping control feature: snooping control feature of
3623 * VT-d engine can guarantee the cache correctness. Just set it
3624 * to WB to keep consistent with host. So the same as item 3.
3625 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3626 * consistent with host MTRR
3629 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
3630 else if (vcpu
->kvm
->arch
.iommu_domain
&&
3631 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
3632 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
3633 VMX_EPT_MT_EPTE_SHIFT
;
3635 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
3641 static struct kvm_x86_ops vmx_x86_ops
= {
3642 .cpu_has_kvm_support
= cpu_has_kvm_support
,
3643 .disabled_by_bios
= vmx_disabled_by_bios
,
3644 .hardware_setup
= hardware_setup
,
3645 .hardware_unsetup
= hardware_unsetup
,
3646 .check_processor_compatibility
= vmx_check_processor_compat
,
3647 .hardware_enable
= hardware_enable
,
3648 .hardware_disable
= hardware_disable
,
3649 .cpu_has_accelerated_tpr
= report_flexpriority
,
3651 .vcpu_create
= vmx_create_vcpu
,
3652 .vcpu_free
= vmx_free_vcpu
,
3653 .vcpu_reset
= vmx_vcpu_reset
,
3655 .prepare_guest_switch
= vmx_save_host_state
,
3656 .vcpu_load
= vmx_vcpu_load
,
3657 .vcpu_put
= vmx_vcpu_put
,
3659 .set_guest_debug
= set_guest_debug
,
3660 .get_msr
= vmx_get_msr
,
3661 .set_msr
= vmx_set_msr
,
3662 .get_segment_base
= vmx_get_segment_base
,
3663 .get_segment
= vmx_get_segment
,
3664 .set_segment
= vmx_set_segment
,
3665 .get_cpl
= vmx_get_cpl
,
3666 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
3667 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
3668 .set_cr0
= vmx_set_cr0
,
3669 .set_cr3
= vmx_set_cr3
,
3670 .set_cr4
= vmx_set_cr4
,
3671 .set_efer
= vmx_set_efer
,
3672 .get_idt
= vmx_get_idt
,
3673 .set_idt
= vmx_set_idt
,
3674 .get_gdt
= vmx_get_gdt
,
3675 .set_gdt
= vmx_set_gdt
,
3676 .cache_reg
= vmx_cache_reg
,
3677 .get_rflags
= vmx_get_rflags
,
3678 .set_rflags
= vmx_set_rflags
,
3680 .tlb_flush
= vmx_flush_tlb
,
3682 .run
= vmx_vcpu_run
,
3683 .handle_exit
= vmx_handle_exit
,
3684 .skip_emulated_instruction
= skip_emulated_instruction
,
3685 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
3686 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
3687 .patch_hypercall
= vmx_patch_hypercall
,
3688 .set_irq
= vmx_inject_irq
,
3689 .set_nmi
= vmx_inject_nmi
,
3690 .queue_exception
= vmx_queue_exception
,
3691 .interrupt_allowed
= vmx_interrupt_allowed
,
3692 .nmi_allowed
= vmx_nmi_allowed
,
3693 .enable_nmi_window
= enable_nmi_window
,
3694 .enable_irq_window
= enable_irq_window
,
3695 .update_cr8_intercept
= update_cr8_intercept
,
3697 .set_tss_addr
= vmx_set_tss_addr
,
3698 .get_tdp_level
= get_ept_level
,
3699 .get_mt_mask
= vmx_get_mt_mask
,
3702 static int __init
vmx_init(void)
3706 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3707 if (!vmx_io_bitmap_a
)
3710 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3711 if (!vmx_io_bitmap_b
) {
3716 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3717 if (!vmx_msr_bitmap_legacy
) {
3722 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
3723 if (!vmx_msr_bitmap_longmode
) {
3729 * Allow direct access to the PC debug port (it is often used for I/O
3730 * delays, but the vmexits simply slow things down).
3732 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
3733 clear_bit(0x80, vmx_io_bitmap_a
);
3735 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
3737 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
3738 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
3740 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
3742 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
), THIS_MODULE
);
3746 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
3747 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
3748 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
3749 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
3750 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
3751 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
3754 bypass_guest_pf
= 0;
3755 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK
|
3756 VMX_EPT_WRITABLE_MASK
);
3757 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3758 VMX_EPT_EXECUTABLE_MASK
);
3763 if (bypass_guest_pf
)
3764 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
3771 free_page((unsigned long)vmx_msr_bitmap_longmode
);
3773 free_page((unsigned long)vmx_msr_bitmap_legacy
);
3775 free_page((unsigned long)vmx_io_bitmap_b
);
3777 free_page((unsigned long)vmx_io_bitmap_a
);
3781 static void __exit
vmx_exit(void)
3783 free_page((unsigned long)vmx_msr_bitmap_legacy
);
3784 free_page((unsigned long)vmx_msr_bitmap_longmode
);
3785 free_page((unsigned long)vmx_io_bitmap_b
);
3786 free_page((unsigned long)vmx_io_bitmap_a
);
3791 module_init(vmx_init
)
3792 module_exit(vmx_exit
)