2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
38 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
46 #define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49 MODULE_AUTHOR("Qumranet");
50 MODULE_LICENSE("GPL");
52 static int __read_mostly bypass_guest_pf
= 1;
53 module_param(bypass_guest_pf
, bool, S_IRUGO
);
55 static int __read_mostly enable_vpid
= 1;
56 module_param_named(vpid
, enable_vpid
, bool, 0444);
58 static int __read_mostly flexpriority_enabled
= 1;
59 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
61 static int __read_mostly enable_ept
= 1;
62 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
64 static int __read_mostly enable_unrestricted_guest
= 1;
65 module_param_named(unrestricted_guest
,
66 enable_unrestricted_guest
, bool, S_IRUGO
);
68 static int __read_mostly emulate_invalid_guest_state
= 0;
69 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
71 static int __read_mostly vmm_exclusive
= 1;
72 module_param(vmm_exclusive
, bool, S_IRUGO
);
74 static int __read_mostly yield_on_hlt
= 1;
75 module_param(yield_on_hlt
, bool, S_IRUGO
);
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
82 static int __read_mostly nested
= 0;
83 module_param(nested
, bool, S_IRUGO
);
85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87 #define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
90 (X86_CR0_WP | X86_CR0_NE)
91 #define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
93 #define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
106 * According to test, this time is usually smaller than 128 cycles.
107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 #define KVM_VMX_DEFAULT_PLE_GAP 128
114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
116 module_param(ple_gap
, int, S_IRUGO
);
118 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
119 module_param(ple_window
, int, S_IRUGO
);
121 #define NR_AUTOLOAD_MSRS 1
130 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
131 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
132 * loaded on this CPU (so we can clear them if the CPU goes down).
138 struct list_head loaded_vmcss_on_cpu_link
;
141 struct shared_msr_entry
{
148 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
149 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
150 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
151 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
152 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
153 * More than one of these structures may exist, if L1 runs multiple L2 guests.
154 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
155 * underlying hardware which will be used to run L2.
156 * This structure is packed to ensure that its layout is identical across
157 * machines (necessary for live migration).
158 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 struct __packed vmcs12
{
161 /* According to the Intel spec, a VMCS region must start with the
162 * following two fields. Then follow implementation-specific data.
169 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
170 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
171 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
173 #define VMCS12_REVISION 0x11e57ed0
176 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
177 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
178 * current implementation, 4K are reserved to avoid future complications.
180 #define VMCS12_SIZE 0x1000
183 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
184 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
187 /* Has the level1 guest done vmxon? */
190 /* The guest-physical address of the current VMCS L1 keeps for L2 */
192 /* The host-usable pointer to the above */
193 struct page
*current_vmcs12_page
;
194 struct vmcs12
*current_vmcs12
;
198 struct kvm_vcpu vcpu
;
199 unsigned long host_rsp
;
202 bool nmi_known_unmasked
;
204 u32 idt_vectoring_info
;
206 struct shared_msr_entry
*guest_msrs
;
210 u64 msr_host_kernel_gs_base
;
211 u64 msr_guest_kernel_gs_base
;
214 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
215 * non-nested (L1) guest, it always points to vmcs01. For a nested
216 * guest (L2), it points to a different VMCS.
218 struct loaded_vmcs vmcs01
;
219 struct loaded_vmcs
*loaded_vmcs
;
220 bool __launched
; /* temporary, used in vmx_vcpu_run */
221 struct msr_autoload
{
223 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
224 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
228 u16 fs_sel
, gs_sel
, ldt_sel
;
229 int gs_ldt_reload_needed
;
230 int fs_reload_needed
;
235 struct kvm_save_segment
{
240 } tr
, es
, ds
, fs
, gs
;
243 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
244 struct kvm_save_segment seg
[8];
247 bool emulation_required
;
249 /* Support for vnmi-less CPUs */
250 int soft_vnmi_blocked
;
252 s64 vnmi_blocked_time
;
257 /* Support for a guest hypervisor (nested VMX) */
258 struct nested_vmx nested
;
261 enum segment_cache_field
{
270 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
272 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
275 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
277 return to_vmx(vcpu
)->nested
.current_vmcs12
;
280 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
282 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
283 if (is_error_page(page
)) {
284 kvm_release_page_clean(page
);
290 static void nested_release_page(struct page
*page
)
292 kvm_release_page_dirty(page
);
295 static void nested_release_page_clean(struct page
*page
)
297 kvm_release_page_clean(page
);
300 static u64
construct_eptp(unsigned long root_hpa
);
301 static void kvm_cpu_vmxon(u64 addr
);
302 static void kvm_cpu_vmxoff(void);
303 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
);
304 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
306 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
307 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
309 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
310 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
312 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
313 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
315 static unsigned long *vmx_io_bitmap_a
;
316 static unsigned long *vmx_io_bitmap_b
;
317 static unsigned long *vmx_msr_bitmap_legacy
;
318 static unsigned long *vmx_msr_bitmap_longmode
;
320 static bool cpu_has_load_ia32_efer
;
322 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
323 static DEFINE_SPINLOCK(vmx_vpid_lock
);
325 static struct vmcs_config
{
329 u32 pin_based_exec_ctrl
;
330 u32 cpu_based_exec_ctrl
;
331 u32 cpu_based_2nd_exec_ctrl
;
336 static struct vmx_capability
{
341 #define VMX_SEGMENT_FIELD(seg) \
342 [VCPU_SREG_##seg] = { \
343 .selector = GUEST_##seg##_SELECTOR, \
344 .base = GUEST_##seg##_BASE, \
345 .limit = GUEST_##seg##_LIMIT, \
346 .ar_bytes = GUEST_##seg##_AR_BYTES, \
349 static struct kvm_vmx_segment_field
{
354 } kvm_vmx_segment_fields
[] = {
355 VMX_SEGMENT_FIELD(CS
),
356 VMX_SEGMENT_FIELD(DS
),
357 VMX_SEGMENT_FIELD(ES
),
358 VMX_SEGMENT_FIELD(FS
),
359 VMX_SEGMENT_FIELD(GS
),
360 VMX_SEGMENT_FIELD(SS
),
361 VMX_SEGMENT_FIELD(TR
),
362 VMX_SEGMENT_FIELD(LDTR
),
365 static u64 host_efer
;
367 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
370 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
371 * away by decrementing the array size.
373 static const u32 vmx_msr_index
[] = {
375 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
377 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
379 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
381 static inline bool is_page_fault(u32 intr_info
)
383 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
384 INTR_INFO_VALID_MASK
)) ==
385 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
388 static inline bool is_no_device(u32 intr_info
)
390 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
391 INTR_INFO_VALID_MASK
)) ==
392 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
395 static inline bool is_invalid_opcode(u32 intr_info
)
397 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
398 INTR_INFO_VALID_MASK
)) ==
399 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
402 static inline bool is_external_interrupt(u32 intr_info
)
404 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
405 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
408 static inline bool is_machine_check(u32 intr_info
)
410 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
411 INTR_INFO_VALID_MASK
)) ==
412 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
415 static inline bool cpu_has_vmx_msr_bitmap(void)
417 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
420 static inline bool cpu_has_vmx_tpr_shadow(void)
422 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
425 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
427 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
430 static inline bool cpu_has_secondary_exec_ctrls(void)
432 return vmcs_config
.cpu_based_exec_ctrl
&
433 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
436 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
438 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
439 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
442 static inline bool cpu_has_vmx_flexpriority(void)
444 return cpu_has_vmx_tpr_shadow() &&
445 cpu_has_vmx_virtualize_apic_accesses();
448 static inline bool cpu_has_vmx_ept_execute_only(void)
450 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
453 static inline bool cpu_has_vmx_eptp_uncacheable(void)
455 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
458 static inline bool cpu_has_vmx_eptp_writeback(void)
460 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
463 static inline bool cpu_has_vmx_ept_2m_page(void)
465 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
468 static inline bool cpu_has_vmx_ept_1g_page(void)
470 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
473 static inline bool cpu_has_vmx_ept_4levels(void)
475 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
478 static inline bool cpu_has_vmx_invept_individual_addr(void)
480 return vmx_capability
.ept
& VMX_EPT_EXTENT_INDIVIDUAL_BIT
;
483 static inline bool cpu_has_vmx_invept_context(void)
485 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
488 static inline bool cpu_has_vmx_invept_global(void)
490 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
493 static inline bool cpu_has_vmx_invvpid_single(void)
495 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
498 static inline bool cpu_has_vmx_invvpid_global(void)
500 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
503 static inline bool cpu_has_vmx_ept(void)
505 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
506 SECONDARY_EXEC_ENABLE_EPT
;
509 static inline bool cpu_has_vmx_unrestricted_guest(void)
511 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
512 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
515 static inline bool cpu_has_vmx_ple(void)
517 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
518 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
521 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
523 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
526 static inline bool cpu_has_vmx_vpid(void)
528 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
529 SECONDARY_EXEC_ENABLE_VPID
;
532 static inline bool cpu_has_vmx_rdtscp(void)
534 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
535 SECONDARY_EXEC_RDTSCP
;
538 static inline bool cpu_has_virtual_nmis(void)
540 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
543 static inline bool cpu_has_vmx_wbinvd_exit(void)
545 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
546 SECONDARY_EXEC_WBINVD_EXITING
;
549 static inline bool report_flexpriority(void)
551 return flexpriority_enabled
;
554 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
558 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
559 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
564 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
570 } operand
= { vpid
, 0, gva
};
572 asm volatile (__ex(ASM_VMX_INVVPID
)
573 /* CF==1 or ZF==1 --> rc = -1 */
575 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
578 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
582 } operand
= {eptp
, gpa
};
584 asm volatile (__ex(ASM_VMX_INVEPT
)
585 /* CF==1 or ZF==1 --> rc = -1 */
586 "; ja 1f ; ud2 ; 1:\n"
587 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
590 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
594 i
= __find_msr_index(vmx
, msr
);
596 return &vmx
->guest_msrs
[i
];
600 static void vmcs_clear(struct vmcs
*vmcs
)
602 u64 phys_addr
= __pa(vmcs
);
605 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
606 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
609 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
613 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
615 vmcs_clear(loaded_vmcs
->vmcs
);
616 loaded_vmcs
->cpu
= -1;
617 loaded_vmcs
->launched
= 0;
620 static void vmcs_load(struct vmcs
*vmcs
)
622 u64 phys_addr
= __pa(vmcs
);
625 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
626 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
629 printk(KERN_ERR
"kvm: vmptrld %p/%llx fail\n",
633 static void __loaded_vmcs_clear(void *arg
)
635 struct loaded_vmcs
*loaded_vmcs
= arg
;
636 int cpu
= raw_smp_processor_id();
638 if (loaded_vmcs
->cpu
!= cpu
)
639 return; /* vcpu migration can race with cpu offline */
640 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
641 per_cpu(current_vmcs
, cpu
) = NULL
;
642 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
643 loaded_vmcs_init(loaded_vmcs
);
646 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
648 if (loaded_vmcs
->cpu
!= -1)
649 smp_call_function_single(
650 loaded_vmcs
->cpu
, __loaded_vmcs_clear
, loaded_vmcs
, 1);
653 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
658 if (cpu_has_vmx_invvpid_single())
659 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
662 static inline void vpid_sync_vcpu_global(void)
664 if (cpu_has_vmx_invvpid_global())
665 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
668 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
670 if (cpu_has_vmx_invvpid_single())
671 vpid_sync_vcpu_single(vmx
);
673 vpid_sync_vcpu_global();
676 static inline void ept_sync_global(void)
678 if (cpu_has_vmx_invept_global())
679 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
682 static inline void ept_sync_context(u64 eptp
)
685 if (cpu_has_vmx_invept_context())
686 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
692 static inline void ept_sync_individual_addr(u64 eptp
, gpa_t gpa
)
695 if (cpu_has_vmx_invept_individual_addr())
696 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR
,
699 ept_sync_context(eptp
);
703 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
707 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
708 : "=a"(value
) : "d"(field
) : "cc");
712 static __always_inline u16
vmcs_read16(unsigned long field
)
714 return vmcs_readl(field
);
717 static __always_inline u32
vmcs_read32(unsigned long field
)
719 return vmcs_readl(field
);
722 static __always_inline u64
vmcs_read64(unsigned long field
)
725 return vmcs_readl(field
);
727 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
731 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
733 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
734 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
738 static void vmcs_writel(unsigned long field
, unsigned long value
)
742 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
743 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
745 vmwrite_error(field
, value
);
748 static void vmcs_write16(unsigned long field
, u16 value
)
750 vmcs_writel(field
, value
);
753 static void vmcs_write32(unsigned long field
, u32 value
)
755 vmcs_writel(field
, value
);
758 static void vmcs_write64(unsigned long field
, u64 value
)
760 vmcs_writel(field
, value
);
761 #ifndef CONFIG_X86_64
763 vmcs_writel(field
+1, value
>> 32);
767 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
769 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
772 static void vmcs_set_bits(unsigned long field
, u32 mask
)
774 vmcs_writel(field
, vmcs_readl(field
) | mask
);
777 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
779 vmx
->segment_cache
.bitmask
= 0;
782 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
786 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
788 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
789 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
790 vmx
->segment_cache
.bitmask
= 0;
792 ret
= vmx
->segment_cache
.bitmask
& mask
;
793 vmx
->segment_cache
.bitmask
|= mask
;
797 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
799 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
801 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
802 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
806 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
808 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
810 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
811 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
815 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
817 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
819 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
820 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
824 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
826 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
828 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
829 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
833 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
837 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
838 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
839 if ((vcpu
->guest_debug
&
840 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
841 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
842 eb
|= 1u << BP_VECTOR
;
843 if (to_vmx(vcpu
)->rmode
.vm86_active
)
846 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
847 if (vcpu
->fpu_active
)
848 eb
&= ~(1u << NM_VECTOR
);
849 vmcs_write32(EXCEPTION_BITMAP
, eb
);
852 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
855 struct msr_autoload
*m
= &vmx
->msr_autoload
;
857 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
858 vmcs_clear_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
859 vmcs_clear_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
863 for (i
= 0; i
< m
->nr
; ++i
)
864 if (m
->guest
[i
].index
== msr
)
870 m
->guest
[i
] = m
->guest
[m
->nr
];
871 m
->host
[i
] = m
->host
[m
->nr
];
872 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
873 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
876 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
877 u64 guest_val
, u64 host_val
)
880 struct msr_autoload
*m
= &vmx
->msr_autoload
;
882 if (msr
== MSR_EFER
&& cpu_has_load_ia32_efer
) {
883 vmcs_write64(GUEST_IA32_EFER
, guest_val
);
884 vmcs_write64(HOST_IA32_EFER
, host_val
);
885 vmcs_set_bits(VM_ENTRY_CONTROLS
, VM_ENTRY_LOAD_IA32_EFER
);
886 vmcs_set_bits(VM_EXIT_CONTROLS
, VM_EXIT_LOAD_IA32_EFER
);
890 for (i
= 0; i
< m
->nr
; ++i
)
891 if (m
->guest
[i
].index
== msr
)
896 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
897 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
900 m
->guest
[i
].index
= msr
;
901 m
->guest
[i
].value
= guest_val
;
902 m
->host
[i
].index
= msr
;
903 m
->host
[i
].value
= host_val
;
906 static void reload_tss(void)
909 * VT restores TR but not its size. Useless.
911 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
912 struct desc_struct
*descs
;
914 descs
= (void *)gdt
->address
;
915 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
919 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
924 guest_efer
= vmx
->vcpu
.arch
.efer
;
927 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
930 ignore_bits
= EFER_NX
| EFER_SCE
;
932 ignore_bits
|= EFER_LMA
| EFER_LME
;
933 /* SCE is meaningful only in long mode on Intel */
934 if (guest_efer
& EFER_LMA
)
935 ignore_bits
&= ~(u64
)EFER_SCE
;
937 guest_efer
&= ~ignore_bits
;
938 guest_efer
|= host_efer
& ignore_bits
;
939 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
940 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
942 clear_atomic_switch_msr(vmx
, MSR_EFER
);
943 /* On ept, can't emulate nx, and must switch nx atomically */
944 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
945 guest_efer
= vmx
->vcpu
.arch
.efer
;
946 if (!(guest_efer
& EFER_LMA
))
947 guest_efer
&= ~EFER_LME
;
948 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
955 static unsigned long segment_base(u16 selector
)
957 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
958 struct desc_struct
*d
;
959 unsigned long table_base
;
962 if (!(selector
& ~3))
965 table_base
= gdt
->address
;
967 if (selector
& 4) { /* from ldt */
968 u16 ldt_selector
= kvm_read_ldt();
970 if (!(ldt_selector
& ~3))
973 table_base
= segment_base(ldt_selector
);
975 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
976 v
= get_desc_base(d
);
978 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
979 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
984 static inline unsigned long kvm_read_tr_base(void)
987 asm("str %0" : "=g"(tr
));
988 return segment_base(tr
);
991 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
993 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
996 if (vmx
->host_state
.loaded
)
999 vmx
->host_state
.loaded
= 1;
1001 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1002 * allow segment selectors with cpl > 0 or ti == 1.
1004 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1005 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1006 savesegment(fs
, vmx
->host_state
.fs_sel
);
1007 if (!(vmx
->host_state
.fs_sel
& 7)) {
1008 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1009 vmx
->host_state
.fs_reload_needed
= 0;
1011 vmcs_write16(HOST_FS_SELECTOR
, 0);
1012 vmx
->host_state
.fs_reload_needed
= 1;
1014 savesegment(gs
, vmx
->host_state
.gs_sel
);
1015 if (!(vmx
->host_state
.gs_sel
& 7))
1016 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1018 vmcs_write16(HOST_GS_SELECTOR
, 0);
1019 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1022 #ifdef CONFIG_X86_64
1023 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1024 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1026 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1027 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1030 #ifdef CONFIG_X86_64
1031 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1032 if (is_long_mode(&vmx
->vcpu
))
1033 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1035 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1036 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1037 vmx
->guest_msrs
[i
].data
,
1038 vmx
->guest_msrs
[i
].mask
);
1041 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1043 if (!vmx
->host_state
.loaded
)
1046 ++vmx
->vcpu
.stat
.host_state_reload
;
1047 vmx
->host_state
.loaded
= 0;
1048 #ifdef CONFIG_X86_64
1049 if (is_long_mode(&vmx
->vcpu
))
1050 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1052 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1053 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1054 #ifdef CONFIG_X86_64
1055 load_gs_index(vmx
->host_state
.gs_sel
);
1057 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1060 if (vmx
->host_state
.fs_reload_needed
)
1061 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1063 #ifdef CONFIG_X86_64
1064 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1066 if (current_thread_info()->status
& TS_USEDFPU
)
1068 load_gdt(&__get_cpu_var(host_gdt
));
1071 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1074 __vmx_load_host_state(vmx
);
1079 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1080 * vcpu mutex is already taken.
1082 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1084 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1085 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1088 kvm_cpu_vmxon(phys_addr
);
1089 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1090 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1092 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1093 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1094 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1097 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1098 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1099 unsigned long sysenter_esp
;
1101 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1102 local_irq_disable();
1103 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1104 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1108 * Linux uses per-cpu TSS and GDT, so set these when switching
1111 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1112 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1114 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1115 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1116 vmx
->loaded_vmcs
->cpu
= cpu
;
1120 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1122 __vmx_load_host_state(to_vmx(vcpu
));
1123 if (!vmm_exclusive
) {
1124 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1130 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1134 if (vcpu
->fpu_active
)
1136 vcpu
->fpu_active
= 1;
1137 cr0
= vmcs_readl(GUEST_CR0
);
1138 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1139 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1140 vmcs_writel(GUEST_CR0
, cr0
);
1141 update_exception_bitmap(vcpu
);
1142 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1143 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1146 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1148 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1150 vmx_decache_cr0_guest_bits(vcpu
);
1151 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1152 update_exception_bitmap(vcpu
);
1153 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1154 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1155 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1158 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1160 unsigned long rflags
, save_rflags
;
1162 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1163 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1164 rflags
= vmcs_readl(GUEST_RFLAGS
);
1165 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1166 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1167 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1168 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1170 to_vmx(vcpu
)->rflags
= rflags
;
1172 return to_vmx(vcpu
)->rflags
;
1175 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1177 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1178 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
1179 to_vmx(vcpu
)->rflags
= rflags
;
1180 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1181 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1182 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1184 vmcs_writel(GUEST_RFLAGS
, rflags
);
1187 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1189 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1192 if (interruptibility
& GUEST_INTR_STATE_STI
)
1193 ret
|= KVM_X86_SHADOW_INT_STI
;
1194 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1195 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1200 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1202 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1203 u32 interruptibility
= interruptibility_old
;
1205 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1207 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1208 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1209 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1210 interruptibility
|= GUEST_INTR_STATE_STI
;
1212 if ((interruptibility
!= interruptibility_old
))
1213 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1216 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1220 rip
= kvm_rip_read(vcpu
);
1221 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1222 kvm_rip_write(vcpu
, rip
);
1224 /* skipping an emulated instruction also counts */
1225 vmx_set_interrupt_shadow(vcpu
, 0);
1228 static void vmx_clear_hlt(struct kvm_vcpu
*vcpu
)
1230 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1231 * explicitly skip the instruction because if the HLT state is set, then
1232 * the instruction is already executing and RIP has already been
1234 if (!yield_on_hlt
&&
1235 vmcs_read32(GUEST_ACTIVITY_STATE
) == GUEST_ACTIVITY_HLT
)
1236 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
1239 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
1240 bool has_error_code
, u32 error_code
,
1243 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1244 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
1246 if (has_error_code
) {
1247 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
1248 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
1251 if (vmx
->rmode
.vm86_active
) {
1253 if (kvm_exception_is_soft(nr
))
1254 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
1255 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
1256 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
1260 if (kvm_exception_is_soft(nr
)) {
1261 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
1262 vmx
->vcpu
.arch
.event_exit_inst_len
);
1263 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
1265 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
1267 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
1268 vmx_clear_hlt(vcpu
);
1271 static bool vmx_rdtscp_supported(void)
1273 return cpu_has_vmx_rdtscp();
1277 * Swap MSR entry in host/guest MSR entry array.
1279 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
1281 struct shared_msr_entry tmp
;
1283 tmp
= vmx
->guest_msrs
[to
];
1284 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
1285 vmx
->guest_msrs
[from
] = tmp
;
1289 * Set up the vmcs to automatically save and restore system
1290 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1291 * mode, as fiddling with msrs is very expensive.
1293 static void setup_msrs(struct vcpu_vmx
*vmx
)
1295 int save_nmsrs
, index
;
1296 unsigned long *msr_bitmap
;
1298 vmx_load_host_state(vmx
);
1300 #ifdef CONFIG_X86_64
1301 if (is_long_mode(&vmx
->vcpu
)) {
1302 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
1304 move_msr_up(vmx
, index
, save_nmsrs
++);
1305 index
= __find_msr_index(vmx
, MSR_LSTAR
);
1307 move_msr_up(vmx
, index
, save_nmsrs
++);
1308 index
= __find_msr_index(vmx
, MSR_CSTAR
);
1310 move_msr_up(vmx
, index
, save_nmsrs
++);
1311 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
1312 if (index
>= 0 && vmx
->rdtscp_enabled
)
1313 move_msr_up(vmx
, index
, save_nmsrs
++);
1315 * MSR_STAR is only needed on long mode guests, and only
1316 * if efer.sce is enabled.
1318 index
= __find_msr_index(vmx
, MSR_STAR
);
1319 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
1320 move_msr_up(vmx
, index
, save_nmsrs
++);
1323 index
= __find_msr_index(vmx
, MSR_EFER
);
1324 if (index
>= 0 && update_transition_efer(vmx
, index
))
1325 move_msr_up(vmx
, index
, save_nmsrs
++);
1327 vmx
->save_nmsrs
= save_nmsrs
;
1329 if (cpu_has_vmx_msr_bitmap()) {
1330 if (is_long_mode(&vmx
->vcpu
))
1331 msr_bitmap
= vmx_msr_bitmap_longmode
;
1333 msr_bitmap
= vmx_msr_bitmap_legacy
;
1335 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
1340 * reads and returns guest's timestamp counter "register"
1341 * guest_tsc = host_tsc + tsc_offset -- 21.3
1343 static u64
guest_read_tsc(void)
1345 u64 host_tsc
, tsc_offset
;
1348 tsc_offset
= vmcs_read64(TSC_OFFSET
);
1349 return host_tsc
+ tsc_offset
;
1353 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1354 * ioctl. In this case the call-back should update internal vmx state to make
1355 * the changes effective.
1357 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
)
1359 /* Nothing to do here */
1363 * writes 'offset' into guest's timestamp counter offset register
1365 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
1367 vmcs_write64(TSC_OFFSET
, offset
);
1370 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
)
1372 u64 offset
= vmcs_read64(TSC_OFFSET
);
1373 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
1376 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
1378 return target_tsc
- native_read_tsc();
1381 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
1383 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
1384 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
1388 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1389 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1390 * all guests if the "nested" module option is off, and can also be disabled
1391 * for a single guest by disabling its VMX cpuid bit.
1393 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
1395 return nested
&& guest_cpuid_has_vmx(vcpu
);
1399 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1400 * returned for the various VMX controls MSRs when nested VMX is enabled.
1401 * The same values should also be used to verify that vmcs12 control fields are
1402 * valid during nested entry from L1 to L2.
1403 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1404 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1405 * bit in the high half is on if the corresponding bit in the control field
1406 * may be on. See also vmx_control_verify().
1407 * TODO: allow these variables to be modified (downgraded) by module options
1410 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
1411 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
1412 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
1413 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
1414 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
1415 static __init
void nested_vmx_setup_ctls_msrs(void)
1418 * Note that as a general rule, the high half of the MSRs (bits in
1419 * the control fields which may be 1) should be initialized by the
1420 * intersection of the underlying hardware's MSR (i.e., features which
1421 * can be supported) and the list of features we want to expose -
1422 * because they are known to be properly supported in our code.
1423 * Also, usually, the low half of the MSRs (bits which must be 1) can
1424 * be set to 0, meaning that L1 may turn off any of these bits. The
1425 * reason is that if one of these bits is necessary, it will appear
1426 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1427 * fields of vmcs01 and vmcs02, will turn these bits off - and
1428 * nested_vmx_exit_handled() will not pass related exits to L1.
1429 * These rules have exceptions below.
1432 /* pin-based controls */
1434 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1435 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1437 nested_vmx_pinbased_ctls_low
= 0x16 ;
1438 nested_vmx_pinbased_ctls_high
= 0x16 |
1439 PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
|
1440 PIN_BASED_VIRTUAL_NMIS
;
1443 nested_vmx_exit_ctls_low
= 0;
1444 #ifdef CONFIG_X86_64
1445 nested_vmx_exit_ctls_high
= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1447 nested_vmx_exit_ctls_high
= 0;
1450 /* entry controls */
1451 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
1452 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
1453 nested_vmx_entry_ctls_low
= 0;
1454 nested_vmx_entry_ctls_high
&=
1455 VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_IA32E_MODE
;
1457 /* cpu-based controls */
1458 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
1459 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
1460 nested_vmx_procbased_ctls_low
= 0;
1461 nested_vmx_procbased_ctls_high
&=
1462 CPU_BASED_VIRTUAL_INTR_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
1463 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
1464 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
1465 CPU_BASED_CR3_STORE_EXITING
|
1466 #ifdef CONFIG_X86_64
1467 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
1469 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
1470 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
1471 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1473 * We can allow some features even when not supported by the
1474 * hardware. For example, L1 can specify an MSR bitmap - and we
1475 * can use it to avoid exits to L1 - even when L0 runs L2
1476 * without MSR bitmaps.
1478 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
1480 /* secondary cpu-based controls */
1481 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
1482 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
1483 nested_vmx_secondary_ctls_low
= 0;
1484 nested_vmx_secondary_ctls_high
&=
1485 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1488 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
1491 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1493 return ((control
& high
) | low
) == control
;
1496 static inline u64
vmx_control_msr(u32 low
, u32 high
)
1498 return low
| ((u64
)high
<< 32);
1502 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1503 * also let it use VMX-specific MSRs.
1504 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1505 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1506 * like all other MSRs).
1508 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1510 if (!nested_vmx_allowed(vcpu
) && msr_index
>= MSR_IA32_VMX_BASIC
&&
1511 msr_index
<= MSR_IA32_VMX_TRUE_ENTRY_CTLS
) {
1513 * According to the spec, processors which do not support VMX
1514 * should throw a #GP(0) when VMX capability MSRs are read.
1516 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
1520 switch (msr_index
) {
1521 case MSR_IA32_FEATURE_CONTROL
:
1524 case MSR_IA32_VMX_BASIC
:
1526 * This MSR reports some information about VMX support. We
1527 * should return information about the VMX we emulate for the
1528 * guest, and the VMCS structure we give it - not about the
1529 * VMX support of the underlying hardware.
1531 *pdata
= VMCS12_REVISION
|
1532 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
1533 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
1535 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
1536 case MSR_IA32_VMX_PINBASED_CTLS
:
1537 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
1538 nested_vmx_pinbased_ctls_high
);
1540 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
1541 case MSR_IA32_VMX_PROCBASED_CTLS
:
1542 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
1543 nested_vmx_procbased_ctls_high
);
1545 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
1546 case MSR_IA32_VMX_EXIT_CTLS
:
1547 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
1548 nested_vmx_exit_ctls_high
);
1550 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
1551 case MSR_IA32_VMX_ENTRY_CTLS
:
1552 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
1553 nested_vmx_entry_ctls_high
);
1555 case MSR_IA32_VMX_MISC
:
1559 * These MSRs specify bits which the guest must keep fixed (on or off)
1560 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1561 * We picked the standard core2 setting.
1563 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1564 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1565 case MSR_IA32_VMX_CR0_FIXED0
:
1566 *pdata
= VMXON_CR0_ALWAYSON
;
1568 case MSR_IA32_VMX_CR0_FIXED1
:
1571 case MSR_IA32_VMX_CR4_FIXED0
:
1572 *pdata
= VMXON_CR4_ALWAYSON
;
1574 case MSR_IA32_VMX_CR4_FIXED1
:
1577 case MSR_IA32_VMX_VMCS_ENUM
:
1580 case MSR_IA32_VMX_PROCBASED_CTLS2
:
1581 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
1582 nested_vmx_secondary_ctls_high
);
1584 case MSR_IA32_VMX_EPT_VPID_CAP
:
1585 /* Currently, no nested ept or nested vpid */
1595 static int vmx_set_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1597 if (!nested_vmx_allowed(vcpu
))
1600 if (msr_index
== MSR_IA32_FEATURE_CONTROL
)
1601 /* TODO: the right thing. */
1604 * No need to treat VMX capability MSRs specially: If we don't handle
1605 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1611 * Reads an msr value (of 'msr_index') into 'pdata'.
1612 * Returns 0 on success, non-0 otherwise.
1613 * Assumes vcpu_load() was already called.
1615 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
1618 struct shared_msr_entry
*msr
;
1621 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
1625 switch (msr_index
) {
1626 #ifdef CONFIG_X86_64
1628 data
= vmcs_readl(GUEST_FS_BASE
);
1631 data
= vmcs_readl(GUEST_GS_BASE
);
1633 case MSR_KERNEL_GS_BASE
:
1634 vmx_load_host_state(to_vmx(vcpu
));
1635 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
1639 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1641 data
= guest_read_tsc();
1643 case MSR_IA32_SYSENTER_CS
:
1644 data
= vmcs_read32(GUEST_SYSENTER_CS
);
1646 case MSR_IA32_SYSENTER_EIP
:
1647 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
1649 case MSR_IA32_SYSENTER_ESP
:
1650 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
1653 if (!to_vmx(vcpu
)->rdtscp_enabled
)
1655 /* Otherwise falls through */
1657 vmx_load_host_state(to_vmx(vcpu
));
1658 if (vmx_get_vmx_msr(vcpu
, msr_index
, pdata
))
1660 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
1662 vmx_load_host_state(to_vmx(vcpu
));
1666 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
1674 * Writes msr value into into the appropriate "register".
1675 * Returns 0 on success, non-0 otherwise.
1676 * Assumes vcpu_load() was already called.
1678 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64 data
)
1680 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1681 struct shared_msr_entry
*msr
;
1684 switch (msr_index
) {
1686 vmx_load_host_state(vmx
);
1687 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1689 #ifdef CONFIG_X86_64
1691 vmx_segment_cache_clear(vmx
);
1692 vmcs_writel(GUEST_FS_BASE
, data
);
1695 vmx_segment_cache_clear(vmx
);
1696 vmcs_writel(GUEST_GS_BASE
, data
);
1698 case MSR_KERNEL_GS_BASE
:
1699 vmx_load_host_state(vmx
);
1700 vmx
->msr_guest_kernel_gs_base
= data
;
1703 case MSR_IA32_SYSENTER_CS
:
1704 vmcs_write32(GUEST_SYSENTER_CS
, data
);
1706 case MSR_IA32_SYSENTER_EIP
:
1707 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
1709 case MSR_IA32_SYSENTER_ESP
:
1710 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
1713 kvm_write_tsc(vcpu
, data
);
1715 case MSR_IA32_CR_PAT
:
1716 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
1717 vmcs_write64(GUEST_IA32_PAT
, data
);
1718 vcpu
->arch
.pat
= data
;
1721 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1724 if (!vmx
->rdtscp_enabled
)
1726 /* Check reserved bit, higher 32 bits should be zero */
1727 if ((data
>> 32) != 0)
1729 /* Otherwise falls through */
1731 if (vmx_set_vmx_msr(vcpu
, msr_index
, data
))
1733 msr
= find_msr_entry(vmx
, msr_index
);
1735 vmx_load_host_state(vmx
);
1739 ret
= kvm_set_msr_common(vcpu
, msr_index
, data
);
1745 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
1747 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
1750 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
1753 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
1755 case VCPU_EXREG_PDPTR
:
1757 ept_save_pdptrs(vcpu
);
1764 static void set_guest_debug(struct kvm_vcpu
*vcpu
, struct kvm_guest_debug
*dbg
)
1766 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
)
1767 vmcs_writel(GUEST_DR7
, dbg
->arch
.debugreg
[7]);
1769 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
1771 update_exception_bitmap(vcpu
);
1774 static __init
int cpu_has_kvm_support(void)
1776 return cpu_has_vmx();
1779 static __init
int vmx_disabled_by_bios(void)
1783 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
1784 if (msr
& FEATURE_CONTROL_LOCKED
) {
1785 /* launched w/ TXT and VMX disabled */
1786 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1789 /* launched w/o TXT and VMX only enabled w/ TXT */
1790 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1791 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
1792 && !tboot_enabled()) {
1793 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
1794 "activate TXT before enabling KVM\n");
1797 /* launched w/o TXT and VMX disabled */
1798 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
1799 && !tboot_enabled())
1806 static void kvm_cpu_vmxon(u64 addr
)
1808 asm volatile (ASM_VMX_VMXON_RAX
1809 : : "a"(&addr
), "m"(addr
)
1813 static int hardware_enable(void *garbage
)
1815 int cpu
= raw_smp_processor_id();
1816 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1819 if (read_cr4() & X86_CR4_VMXE
)
1822 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
1823 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
1825 test_bits
= FEATURE_CONTROL_LOCKED
;
1826 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
1827 if (tboot_enabled())
1828 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
1830 if ((old
& test_bits
) != test_bits
) {
1831 /* enable and lock */
1832 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
1834 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
1836 if (vmm_exclusive
) {
1837 kvm_cpu_vmxon(phys_addr
);
1841 store_gdt(&__get_cpu_var(host_gdt
));
1846 static void vmclear_local_loaded_vmcss(void)
1848 int cpu
= raw_smp_processor_id();
1849 struct loaded_vmcs
*v
, *n
;
1851 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1852 loaded_vmcss_on_cpu_link
)
1853 __loaded_vmcs_clear(v
);
1857 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1860 static void kvm_cpu_vmxoff(void)
1862 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
1865 static void hardware_disable(void *garbage
)
1867 if (vmm_exclusive
) {
1868 vmclear_local_loaded_vmcss();
1871 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
1874 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
1875 u32 msr
, u32
*result
)
1877 u32 vmx_msr_low
, vmx_msr_high
;
1878 u32 ctl
= ctl_min
| ctl_opt
;
1880 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1882 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
1883 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
1885 /* Ensure minimum (required) set of control bits are supported. */
1893 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
1895 u32 vmx_msr_low
, vmx_msr_high
;
1897 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
1898 return vmx_msr_high
& ctl
;
1901 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
1903 u32 vmx_msr_low
, vmx_msr_high
;
1904 u32 min
, opt
, min2
, opt2
;
1905 u32 _pin_based_exec_control
= 0;
1906 u32 _cpu_based_exec_control
= 0;
1907 u32 _cpu_based_2nd_exec_control
= 0;
1908 u32 _vmexit_control
= 0;
1909 u32 _vmentry_control
= 0;
1911 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
1912 opt
= PIN_BASED_VIRTUAL_NMIS
;
1913 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
1914 &_pin_based_exec_control
) < 0)
1918 #ifdef CONFIG_X86_64
1919 CPU_BASED_CR8_LOAD_EXITING
|
1920 CPU_BASED_CR8_STORE_EXITING
|
1922 CPU_BASED_CR3_LOAD_EXITING
|
1923 CPU_BASED_CR3_STORE_EXITING
|
1924 CPU_BASED_USE_IO_BITMAPS
|
1925 CPU_BASED_MOV_DR_EXITING
|
1926 CPU_BASED_USE_TSC_OFFSETING
|
1927 CPU_BASED_MWAIT_EXITING
|
1928 CPU_BASED_MONITOR_EXITING
|
1929 CPU_BASED_INVLPG_EXITING
;
1932 min
|= CPU_BASED_HLT_EXITING
;
1934 opt
= CPU_BASED_TPR_SHADOW
|
1935 CPU_BASED_USE_MSR_BITMAPS
|
1936 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1937 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
1938 &_cpu_based_exec_control
) < 0)
1940 #ifdef CONFIG_X86_64
1941 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
1942 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
1943 ~CPU_BASED_CR8_STORE_EXITING
;
1945 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
1947 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
1948 SECONDARY_EXEC_WBINVD_EXITING
|
1949 SECONDARY_EXEC_ENABLE_VPID
|
1950 SECONDARY_EXEC_ENABLE_EPT
|
1951 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
1952 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
1953 SECONDARY_EXEC_RDTSCP
;
1954 if (adjust_vmx_controls(min2
, opt2
,
1955 MSR_IA32_VMX_PROCBASED_CTLS2
,
1956 &_cpu_based_2nd_exec_control
) < 0)
1959 #ifndef CONFIG_X86_64
1960 if (!(_cpu_based_2nd_exec_control
&
1961 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
1962 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
1964 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
1965 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1967 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
1968 CPU_BASED_CR3_STORE_EXITING
|
1969 CPU_BASED_INVLPG_EXITING
);
1970 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
1971 vmx_capability
.ept
, vmx_capability
.vpid
);
1975 #ifdef CONFIG_X86_64
1976 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
1978 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
;
1979 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
1980 &_vmexit_control
) < 0)
1984 opt
= VM_ENTRY_LOAD_IA32_PAT
;
1985 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
1986 &_vmentry_control
) < 0)
1989 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
1991 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1992 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
1995 #ifdef CONFIG_X86_64
1996 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1997 if (vmx_msr_high
& (1u<<16))
2001 /* Require Write-Back (WB) memory type for VMCS accesses. */
2002 if (((vmx_msr_high
>> 18) & 15) != 6)
2005 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2006 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2007 vmcs_conf
->revision_id
= vmx_msr_low
;
2009 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2010 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2011 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2012 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2013 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2015 cpu_has_load_ia32_efer
=
2016 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2017 VM_ENTRY_LOAD_IA32_EFER
)
2018 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2019 VM_EXIT_LOAD_IA32_EFER
);
2024 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2026 int node
= cpu_to_node(cpu
);
2030 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2033 vmcs
= page_address(pages
);
2034 memset(vmcs
, 0, vmcs_config
.size
);
2035 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2039 static struct vmcs
*alloc_vmcs(void)
2041 return alloc_vmcs_cpu(raw_smp_processor_id());
2044 static void free_vmcs(struct vmcs
*vmcs
)
2046 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2050 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2052 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2054 if (!loaded_vmcs
->vmcs
)
2056 loaded_vmcs_clear(loaded_vmcs
);
2057 free_vmcs(loaded_vmcs
->vmcs
);
2058 loaded_vmcs
->vmcs
= NULL
;
2061 static void free_kvm_area(void)
2065 for_each_possible_cpu(cpu
) {
2066 free_vmcs(per_cpu(vmxarea
, cpu
));
2067 per_cpu(vmxarea
, cpu
) = NULL
;
2071 static __init
int alloc_kvm_area(void)
2075 for_each_possible_cpu(cpu
) {
2078 vmcs
= alloc_vmcs_cpu(cpu
);
2084 per_cpu(vmxarea
, cpu
) = vmcs
;
2089 static __init
int hardware_setup(void)
2091 if (setup_vmcs_config(&vmcs_config
) < 0)
2094 if (boot_cpu_has(X86_FEATURE_NX
))
2095 kvm_enable_efer_bits(EFER_NX
);
2097 if (!cpu_has_vmx_vpid())
2100 if (!cpu_has_vmx_ept() ||
2101 !cpu_has_vmx_ept_4levels()) {
2103 enable_unrestricted_guest
= 0;
2106 if (!cpu_has_vmx_unrestricted_guest())
2107 enable_unrestricted_guest
= 0;
2109 if (!cpu_has_vmx_flexpriority())
2110 flexpriority_enabled
= 0;
2112 if (!cpu_has_vmx_tpr_shadow())
2113 kvm_x86_ops
->update_cr8_intercept
= NULL
;
2115 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
2116 kvm_disable_largepages();
2118 if (!cpu_has_vmx_ple())
2122 nested_vmx_setup_ctls_msrs();
2124 return alloc_kvm_area();
2127 static __exit
void hardware_unsetup(void)
2132 static void fix_pmode_dataseg(int seg
, struct kvm_save_segment
*save
)
2134 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2136 if (vmcs_readl(sf
->base
) == save
->base
&& (save
->base
& AR_S_MASK
)) {
2137 vmcs_write16(sf
->selector
, save
->selector
);
2138 vmcs_writel(sf
->base
, save
->base
);
2139 vmcs_write32(sf
->limit
, save
->limit
);
2140 vmcs_write32(sf
->ar_bytes
, save
->ar
);
2142 u32 dpl
= (vmcs_read16(sf
->selector
) & SELECTOR_RPL_MASK
)
2144 vmcs_write32(sf
->ar_bytes
, 0x93 | dpl
);
2148 static void enter_pmode(struct kvm_vcpu
*vcpu
)
2150 unsigned long flags
;
2151 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2153 vmx
->emulation_required
= 1;
2154 vmx
->rmode
.vm86_active
= 0;
2156 vmx_segment_cache_clear(vmx
);
2158 vmcs_write16(GUEST_TR_SELECTOR
, vmx
->rmode
.tr
.selector
);
2159 vmcs_writel(GUEST_TR_BASE
, vmx
->rmode
.tr
.base
);
2160 vmcs_write32(GUEST_TR_LIMIT
, vmx
->rmode
.tr
.limit
);
2161 vmcs_write32(GUEST_TR_AR_BYTES
, vmx
->rmode
.tr
.ar
);
2163 flags
= vmcs_readl(GUEST_RFLAGS
);
2164 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2165 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2166 vmcs_writel(GUEST_RFLAGS
, flags
);
2168 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
2169 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
2171 update_exception_bitmap(vcpu
);
2173 if (emulate_invalid_guest_state
)
2176 fix_pmode_dataseg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2177 fix_pmode_dataseg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2178 fix_pmode_dataseg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2179 fix_pmode_dataseg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2181 vmx_segment_cache_clear(vmx
);
2183 vmcs_write16(GUEST_SS_SELECTOR
, 0);
2184 vmcs_write32(GUEST_SS_AR_BYTES
, 0x93);
2186 vmcs_write16(GUEST_CS_SELECTOR
,
2187 vmcs_read16(GUEST_CS_SELECTOR
) & ~SELECTOR_RPL_MASK
);
2188 vmcs_write32(GUEST_CS_AR_BYTES
, 0x9b);
2191 static gva_t
rmode_tss_base(struct kvm
*kvm
)
2193 if (!kvm
->arch
.tss_addr
) {
2194 struct kvm_memslots
*slots
;
2197 slots
= kvm_memslots(kvm
);
2198 base_gfn
= slots
->memslots
[0].base_gfn
+
2199 kvm
->memslots
->memslots
[0].npages
- 3;
2200 return base_gfn
<< PAGE_SHIFT
;
2202 return kvm
->arch
.tss_addr
;
2205 static void fix_rmode_seg(int seg
, struct kvm_save_segment
*save
)
2207 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2209 save
->selector
= vmcs_read16(sf
->selector
);
2210 save
->base
= vmcs_readl(sf
->base
);
2211 save
->limit
= vmcs_read32(sf
->limit
);
2212 save
->ar
= vmcs_read32(sf
->ar_bytes
);
2213 vmcs_write16(sf
->selector
, save
->base
>> 4);
2214 vmcs_write32(sf
->base
, save
->base
& 0xffff0);
2215 vmcs_write32(sf
->limit
, 0xffff);
2216 vmcs_write32(sf
->ar_bytes
, 0xf3);
2217 if (save
->base
& 0xf)
2218 printk_once(KERN_WARNING
"kvm: segment base is not paragraph"
2219 " aligned when entering protected mode (seg=%d)",
2223 static void enter_rmode(struct kvm_vcpu
*vcpu
)
2225 unsigned long flags
;
2226 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2228 if (enable_unrestricted_guest
)
2231 vmx
->emulation_required
= 1;
2232 vmx
->rmode
.vm86_active
= 1;
2235 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2236 * vcpu. Call it here with phys address pointing 16M below 4G.
2238 if (!vcpu
->kvm
->arch
.tss_addr
) {
2239 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
2240 "called before entering vcpu\n");
2241 srcu_read_unlock(&vcpu
->kvm
->srcu
, vcpu
->srcu_idx
);
2242 vmx_set_tss_addr(vcpu
->kvm
, 0xfeffd000);
2243 vcpu
->srcu_idx
= srcu_read_lock(&vcpu
->kvm
->srcu
);
2246 vmx_segment_cache_clear(vmx
);
2248 vmx
->rmode
.tr
.selector
= vmcs_read16(GUEST_TR_SELECTOR
);
2249 vmx
->rmode
.tr
.base
= vmcs_readl(GUEST_TR_BASE
);
2250 vmcs_writel(GUEST_TR_BASE
, rmode_tss_base(vcpu
->kvm
));
2252 vmx
->rmode
.tr
.limit
= vmcs_read32(GUEST_TR_LIMIT
);
2253 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
2255 vmx
->rmode
.tr
.ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2256 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
2258 flags
= vmcs_readl(GUEST_RFLAGS
);
2259 vmx
->rmode
.save_rflags
= flags
;
2261 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2263 vmcs_writel(GUEST_RFLAGS
, flags
);
2264 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
2265 update_exception_bitmap(vcpu
);
2267 if (emulate_invalid_guest_state
)
2268 goto continue_rmode
;
2270 vmcs_write16(GUEST_SS_SELECTOR
, vmcs_readl(GUEST_SS_BASE
) >> 4);
2271 vmcs_write32(GUEST_SS_LIMIT
, 0xffff);
2272 vmcs_write32(GUEST_SS_AR_BYTES
, 0xf3);
2274 vmcs_write32(GUEST_CS_AR_BYTES
, 0xf3);
2275 vmcs_write32(GUEST_CS_LIMIT
, 0xffff);
2276 if (vmcs_readl(GUEST_CS_BASE
) == 0xffff0000)
2277 vmcs_writel(GUEST_CS_BASE
, 0xf0000);
2278 vmcs_write16(GUEST_CS_SELECTOR
, vmcs_readl(GUEST_CS_BASE
) >> 4);
2280 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.es
);
2281 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.ds
);
2282 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.gs
);
2283 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.fs
);
2286 kvm_mmu_reset_context(vcpu
);
2289 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
2291 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2292 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
2298 * Force kernel_gs_base reloading before EFER changes, as control
2299 * of this msr depends on is_long_mode().
2301 vmx_load_host_state(to_vmx(vcpu
));
2302 vcpu
->arch
.efer
= efer
;
2303 if (efer
& EFER_LMA
) {
2304 vmcs_write32(VM_ENTRY_CONTROLS
,
2305 vmcs_read32(VM_ENTRY_CONTROLS
) |
2306 VM_ENTRY_IA32E_MODE
);
2309 vmcs_write32(VM_ENTRY_CONTROLS
,
2310 vmcs_read32(VM_ENTRY_CONTROLS
) &
2311 ~VM_ENTRY_IA32E_MODE
);
2313 msr
->data
= efer
& ~EFER_LME
;
2318 #ifdef CONFIG_X86_64
2320 static void enter_lmode(struct kvm_vcpu
*vcpu
)
2324 vmx_segment_cache_clear(to_vmx(vcpu
));
2326 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
2327 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
2328 printk(KERN_DEBUG
"%s: tss fixup for long mode. \n",
2330 vmcs_write32(GUEST_TR_AR_BYTES
,
2331 (guest_tr_ar
& ~AR_TYPE_MASK
)
2332 | AR_TYPE_BUSY_64_TSS
);
2334 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
2337 static void exit_lmode(struct kvm_vcpu
*vcpu
)
2339 vmcs_write32(VM_ENTRY_CONTROLS
,
2340 vmcs_read32(VM_ENTRY_CONTROLS
)
2341 & ~VM_ENTRY_IA32E_MODE
);
2342 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
2347 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
2349 vpid_sync_context(to_vmx(vcpu
));
2351 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
2353 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
2357 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
2359 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
2361 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
2362 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
2365 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
2367 if (enable_ept
&& is_paging(vcpu
))
2368 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
2369 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
2372 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
2374 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
2376 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
2377 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
2380 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
2382 if (!test_bit(VCPU_EXREG_PDPTR
,
2383 (unsigned long *)&vcpu
->arch
.regs_dirty
))
2386 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2387 vmcs_write64(GUEST_PDPTR0
, vcpu
->arch
.mmu
.pdptrs
[0]);
2388 vmcs_write64(GUEST_PDPTR1
, vcpu
->arch
.mmu
.pdptrs
[1]);
2389 vmcs_write64(GUEST_PDPTR2
, vcpu
->arch
.mmu
.pdptrs
[2]);
2390 vmcs_write64(GUEST_PDPTR3
, vcpu
->arch
.mmu
.pdptrs
[3]);
2394 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
2396 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
2397 vcpu
->arch
.mmu
.pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
2398 vcpu
->arch
.mmu
.pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
2399 vcpu
->arch
.mmu
.pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
2400 vcpu
->arch
.mmu
.pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
2403 __set_bit(VCPU_EXREG_PDPTR
,
2404 (unsigned long *)&vcpu
->arch
.regs_avail
);
2405 __set_bit(VCPU_EXREG_PDPTR
,
2406 (unsigned long *)&vcpu
->arch
.regs_dirty
);
2409 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
2411 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
2413 struct kvm_vcpu
*vcpu
)
2415 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
2416 vmx_decache_cr3(vcpu
);
2417 if (!(cr0
& X86_CR0_PG
)) {
2418 /* From paging/starting to nonpaging */
2419 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2420 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
2421 (CPU_BASED_CR3_LOAD_EXITING
|
2422 CPU_BASED_CR3_STORE_EXITING
));
2423 vcpu
->arch
.cr0
= cr0
;
2424 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2425 } else if (!is_paging(vcpu
)) {
2426 /* From nonpaging to paging */
2427 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
2428 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
2429 ~(CPU_BASED_CR3_LOAD_EXITING
|
2430 CPU_BASED_CR3_STORE_EXITING
));
2431 vcpu
->arch
.cr0
= cr0
;
2432 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
2435 if (!(cr0
& X86_CR0_WP
))
2436 *hw_cr0
&= ~X86_CR0_WP
;
2439 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
2441 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2442 unsigned long hw_cr0
;
2444 if (enable_unrestricted_guest
)
2445 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST
)
2446 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
2448 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
) | KVM_VM_CR0_ALWAYS_ON
;
2450 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
2453 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
2456 #ifdef CONFIG_X86_64
2457 if (vcpu
->arch
.efer
& EFER_LME
) {
2458 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
2460 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
2466 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
2468 if (!vcpu
->fpu_active
)
2469 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
2471 vmcs_writel(CR0_READ_SHADOW
, cr0
);
2472 vmcs_writel(GUEST_CR0
, hw_cr0
);
2473 vcpu
->arch
.cr0
= cr0
;
2474 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2477 static u64
construct_eptp(unsigned long root_hpa
)
2481 /* TODO write the value reading from MSR */
2482 eptp
= VMX_EPT_DEFAULT_MT
|
2483 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
2484 eptp
|= (root_hpa
& PAGE_MASK
);
2489 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
2491 unsigned long guest_cr3
;
2496 eptp
= construct_eptp(cr3
);
2497 vmcs_write64(EPT_POINTER
, eptp
);
2498 guest_cr3
= is_paging(vcpu
) ? kvm_read_cr3(vcpu
) :
2499 vcpu
->kvm
->arch
.ept_identity_map_addr
;
2500 ept_load_pdptrs(vcpu
);
2503 vmx_flush_tlb(vcpu
);
2504 vmcs_writel(GUEST_CR3
, guest_cr3
);
2507 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
2509 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
2510 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
2512 if (cr4
& X86_CR4_VMXE
) {
2514 * To use VMXON (and later other VMX instructions), a guest
2515 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2516 * So basically the check on whether to allow nested VMX
2519 if (!nested_vmx_allowed(vcpu
))
2521 } else if (to_vmx(vcpu
)->nested
.vmxon
)
2524 vcpu
->arch
.cr4
= cr4
;
2526 if (!is_paging(vcpu
)) {
2527 hw_cr4
&= ~X86_CR4_PAE
;
2528 hw_cr4
|= X86_CR4_PSE
;
2529 } else if (!(cr4
& X86_CR4_PAE
)) {
2530 hw_cr4
&= ~X86_CR4_PAE
;
2534 vmcs_writel(CR4_READ_SHADOW
, cr4
);
2535 vmcs_writel(GUEST_CR4
, hw_cr4
);
2539 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
2540 struct kvm_segment
*var
, int seg
)
2542 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2543 struct kvm_save_segment
*save
;
2546 if (vmx
->rmode
.vm86_active
2547 && (seg
== VCPU_SREG_TR
|| seg
== VCPU_SREG_ES
2548 || seg
== VCPU_SREG_DS
|| seg
== VCPU_SREG_FS
2549 || seg
== VCPU_SREG_GS
)
2550 && !emulate_invalid_guest_state
) {
2552 case VCPU_SREG_TR
: save
= &vmx
->rmode
.tr
; break;
2553 case VCPU_SREG_ES
: save
= &vmx
->rmode
.es
; break;
2554 case VCPU_SREG_DS
: save
= &vmx
->rmode
.ds
; break;
2555 case VCPU_SREG_FS
: save
= &vmx
->rmode
.fs
; break;
2556 case VCPU_SREG_GS
: save
= &vmx
->rmode
.gs
; break;
2559 var
->selector
= save
->selector
;
2560 var
->base
= save
->base
;
2561 var
->limit
= save
->limit
;
2563 if (seg
== VCPU_SREG_TR
2564 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
2565 goto use_saved_rmode_seg
;
2567 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
2568 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
2569 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
2570 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
2571 use_saved_rmode_seg
:
2572 if ((ar
& AR_UNUSABLE_MASK
) && !emulate_invalid_guest_state
)
2574 var
->type
= ar
& 15;
2575 var
->s
= (ar
>> 4) & 1;
2576 var
->dpl
= (ar
>> 5) & 3;
2577 var
->present
= (ar
>> 7) & 1;
2578 var
->avl
= (ar
>> 12) & 1;
2579 var
->l
= (ar
>> 13) & 1;
2580 var
->db
= (ar
>> 14) & 1;
2581 var
->g
= (ar
>> 15) & 1;
2582 var
->unusable
= (ar
>> 16) & 1;
2585 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
2587 struct kvm_segment s
;
2589 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2590 vmx_get_segment(vcpu
, &s
, seg
);
2593 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
2596 static int __vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2598 if (!is_protmode(vcpu
))
2601 if (!is_long_mode(vcpu
)
2602 && (kvm_get_rflags(vcpu
) & X86_EFLAGS_VM
)) /* if virtual 8086 */
2605 return vmx_read_guest_seg_selector(to_vmx(vcpu
), VCPU_SREG_CS
) & 3;
2608 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
2610 if (!test_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2611 __set_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2612 to_vmx(vcpu
)->cpl
= __vmx_get_cpl(vcpu
);
2614 return to_vmx(vcpu
)->cpl
;
2618 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
2625 ar
= var
->type
& 15;
2626 ar
|= (var
->s
& 1) << 4;
2627 ar
|= (var
->dpl
& 3) << 5;
2628 ar
|= (var
->present
& 1) << 7;
2629 ar
|= (var
->avl
& 1) << 12;
2630 ar
|= (var
->l
& 1) << 13;
2631 ar
|= (var
->db
& 1) << 14;
2632 ar
|= (var
->g
& 1) << 15;
2634 if (ar
== 0) /* a 0 value means unusable */
2635 ar
= AR_UNUSABLE_MASK
;
2640 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
2641 struct kvm_segment
*var
, int seg
)
2643 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2644 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2647 vmx_segment_cache_clear(vmx
);
2649 if (vmx
->rmode
.vm86_active
&& seg
== VCPU_SREG_TR
) {
2650 vmcs_write16(sf
->selector
, var
->selector
);
2651 vmx
->rmode
.tr
.selector
= var
->selector
;
2652 vmx
->rmode
.tr
.base
= var
->base
;
2653 vmx
->rmode
.tr
.limit
= var
->limit
;
2654 vmx
->rmode
.tr
.ar
= vmx_segment_access_rights(var
);
2657 vmcs_writel(sf
->base
, var
->base
);
2658 vmcs_write32(sf
->limit
, var
->limit
);
2659 vmcs_write16(sf
->selector
, var
->selector
);
2660 if (vmx
->rmode
.vm86_active
&& var
->s
) {
2662 * Hack real-mode segments into vm86 compatibility.
2664 if (var
->base
== 0xffff0000 && var
->selector
== 0xf000)
2665 vmcs_writel(sf
->base
, 0xf0000);
2668 ar
= vmx_segment_access_rights(var
);
2671 * Fix the "Accessed" bit in AR field of segment registers for older
2673 * IA32 arch specifies that at the time of processor reset the
2674 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2675 * is setting it to 0 in the usedland code. This causes invalid guest
2676 * state vmexit when "unrestricted guest" mode is turned on.
2677 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2678 * tree. Newer qemu binaries with that qemu fix would not need this
2681 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
2682 ar
|= 0x1; /* Accessed */
2684 vmcs_write32(sf
->ar_bytes
, ar
);
2685 __clear_bit(VCPU_EXREG_CPL
, (ulong
*)&vcpu
->arch
.regs_avail
);
2688 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
2690 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
2692 *db
= (ar
>> 14) & 1;
2693 *l
= (ar
>> 13) & 1;
2696 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2698 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
2699 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
2702 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2704 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
2705 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
2708 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2710 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
2711 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
2714 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
2716 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
2717 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
2720 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2722 struct kvm_segment var
;
2725 vmx_get_segment(vcpu
, &var
, seg
);
2726 ar
= vmx_segment_access_rights(&var
);
2728 if (var
.base
!= (var
.selector
<< 4))
2730 if (var
.limit
!= 0xffff)
2738 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
2740 struct kvm_segment cs
;
2741 unsigned int cs_rpl
;
2743 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2744 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
2748 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
2752 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
2753 if (cs
.dpl
> cs_rpl
)
2756 if (cs
.dpl
!= cs_rpl
)
2762 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2766 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
2768 struct kvm_segment ss
;
2769 unsigned int ss_rpl
;
2771 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2772 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
2776 if (ss
.type
!= 3 && ss
.type
!= 7)
2780 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
2788 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
2790 struct kvm_segment var
;
2793 vmx_get_segment(vcpu
, &var
, seg
);
2794 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
2802 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
2803 if (var
.dpl
< rpl
) /* DPL < RPL */
2807 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2813 static bool tr_valid(struct kvm_vcpu
*vcpu
)
2815 struct kvm_segment tr
;
2817 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
2821 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2823 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
2831 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
2833 struct kvm_segment ldtr
;
2835 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
2839 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
2849 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
2851 struct kvm_segment cs
, ss
;
2853 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
2854 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
2856 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
2857 (ss
.selector
& SELECTOR_RPL_MASK
));
2861 * Check if guest state is valid. Returns true if valid, false if
2863 * We assume that registers are always usable
2865 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
2867 /* real mode guest state checks */
2868 if (!is_protmode(vcpu
)) {
2869 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
2871 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
2873 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
2875 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
2877 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
2879 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
2882 /* protected mode guest state checks */
2883 if (!cs_ss_rpl_check(vcpu
))
2885 if (!code_segment_valid(vcpu
))
2887 if (!stack_segment_valid(vcpu
))
2889 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
2891 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
2893 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
2895 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
2897 if (!tr_valid(vcpu
))
2899 if (!ldtr_valid(vcpu
))
2903 * - Add checks on RIP
2904 * - Add checks on RFLAGS
2910 static int init_rmode_tss(struct kvm
*kvm
)
2914 int r
, idx
, ret
= 0;
2916 idx
= srcu_read_lock(&kvm
->srcu
);
2917 fn
= rmode_tss_base(kvm
) >> PAGE_SHIFT
;
2918 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2921 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
2922 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
2923 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
2926 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
2929 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
2933 r
= kvm_write_guest_page(kvm
, fn
, &data
,
2934 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
2941 srcu_read_unlock(&kvm
->srcu
, idx
);
2945 static int init_rmode_identity_map(struct kvm
*kvm
)
2948 pfn_t identity_map_pfn
;
2953 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
2954 printk(KERN_ERR
"EPT: identity-mapping pagetable "
2955 "haven't been allocated!\n");
2958 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
2961 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
2962 idx
= srcu_read_lock(&kvm
->srcu
);
2963 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
2966 /* Set up identity-mapping pagetable for EPT in real mode */
2967 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
2968 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
2969 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
2970 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
2971 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
2975 kvm
->arch
.ept_identity_pagetable_done
= true;
2978 srcu_read_unlock(&kvm
->srcu
, idx
);
2982 static void seg_setup(int seg
)
2984 struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
2987 vmcs_write16(sf
->selector
, 0);
2988 vmcs_writel(sf
->base
, 0);
2989 vmcs_write32(sf
->limit
, 0xffff);
2990 if (enable_unrestricted_guest
) {
2992 if (seg
== VCPU_SREG_CS
)
2993 ar
|= 0x08; /* code segment */
2997 vmcs_write32(sf
->ar_bytes
, ar
);
3000 static int alloc_apic_access_page(struct kvm
*kvm
)
3002 struct kvm_userspace_memory_region kvm_userspace_mem
;
3005 mutex_lock(&kvm
->slots_lock
);
3006 if (kvm
->arch
.apic_access_page
)
3008 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3009 kvm_userspace_mem
.flags
= 0;
3010 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3011 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3012 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3016 kvm
->arch
.apic_access_page
= gfn_to_page(kvm
, 0xfee00);
3018 mutex_unlock(&kvm
->slots_lock
);
3022 static int alloc_identity_pagetable(struct kvm
*kvm
)
3024 struct kvm_userspace_memory_region kvm_userspace_mem
;
3027 mutex_lock(&kvm
->slots_lock
);
3028 if (kvm
->arch
.ept_identity_pagetable
)
3030 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
3031 kvm_userspace_mem
.flags
= 0;
3032 kvm_userspace_mem
.guest_phys_addr
=
3033 kvm
->arch
.ept_identity_map_addr
;
3034 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3035 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
, 0);
3039 kvm
->arch
.ept_identity_pagetable
= gfn_to_page(kvm
,
3040 kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
3042 mutex_unlock(&kvm
->slots_lock
);
3046 static void allocate_vpid(struct vcpu_vmx
*vmx
)
3053 spin_lock(&vmx_vpid_lock
);
3054 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
3055 if (vpid
< VMX_NR_VPIDS
) {
3057 __set_bit(vpid
, vmx_vpid_bitmap
);
3059 spin_unlock(&vmx_vpid_lock
);
3062 static void free_vpid(struct vcpu_vmx
*vmx
)
3066 spin_lock(&vmx_vpid_lock
);
3068 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
3069 spin_unlock(&vmx_vpid_lock
);
3072 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
, u32 msr
)
3074 int f
= sizeof(unsigned long);
3076 if (!cpu_has_vmx_msr_bitmap())
3080 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3081 * have the write-low and read-high bitmap offsets the wrong way round.
3082 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3084 if (msr
<= 0x1fff) {
3085 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
); /* read-low */
3086 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
); /* write-low */
3087 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
3089 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
); /* read-high */
3090 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
); /* write-high */
3094 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
3097 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
, msr
);
3098 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
, msr
);
3102 * Sets up the vmcs for emulated real mode.
3104 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
3106 u32 host_sysenter_cs
, msr_low
, msr_high
;
3112 unsigned long kvm_vmx_return
;
3116 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
3117 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
3119 if (cpu_has_vmx_msr_bitmap())
3120 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
3122 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
3125 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
,
3126 vmcs_config
.pin_based_exec_ctrl
);
3128 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
3129 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
3130 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3131 #ifdef CONFIG_X86_64
3132 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
3133 CPU_BASED_CR8_LOAD_EXITING
;
3137 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
3138 CPU_BASED_CR3_LOAD_EXITING
|
3139 CPU_BASED_INVLPG_EXITING
;
3140 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
3142 if (cpu_has_secondary_exec_ctrls()) {
3143 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
3144 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3146 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
3148 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
3150 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
3151 enable_unrestricted_guest
= 0;
3153 if (!enable_unrestricted_guest
)
3154 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
3156 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
3157 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
3161 vmcs_write32(PLE_GAP
, ple_gap
);
3162 vmcs_write32(PLE_WINDOW
, ple_window
);
3165 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, !!bypass_guest_pf
);
3166 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, !!bypass_guest_pf
);
3167 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
3169 vmcs_writel(HOST_CR0
, read_cr0() | X86_CR0_TS
); /* 22.2.3 */
3170 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
3171 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3173 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
3174 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3175 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3176 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
3177 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
3178 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
3179 #ifdef CONFIG_X86_64
3180 rdmsrl(MSR_FS_BASE
, a
);
3181 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
3182 rdmsrl(MSR_GS_BASE
, a
);
3183 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
3185 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
3186 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
3189 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
3191 native_store_idt(&dt
);
3192 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
3194 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return
));
3195 vmcs_writel(HOST_RIP
, kvm_vmx_return
); /* 22.2.5 */
3196 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
3197 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
3198 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
3199 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
3200 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
3202 rdmsr(MSR_IA32_SYSENTER_CS
, host_sysenter_cs
, junk
);
3203 vmcs_write32(HOST_IA32_SYSENTER_CS
, host_sysenter_cs
);
3204 rdmsrl(MSR_IA32_SYSENTER_ESP
, a
);
3205 vmcs_writel(HOST_IA32_SYSENTER_ESP
, a
); /* 22.2.3 */
3206 rdmsrl(MSR_IA32_SYSENTER_EIP
, a
);
3207 vmcs_writel(HOST_IA32_SYSENTER_EIP
, a
); /* 22.2.3 */
3209 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
3210 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3211 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3212 vmcs_write64(HOST_IA32_PAT
, host_pat
);
3214 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
3215 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
3216 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
3217 /* Write the default value follow host pat */
3218 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
3219 /* Keep arch.pat sync with GUEST_IA32_PAT */
3220 vmx
->vcpu
.arch
.pat
= host_pat
;
3223 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
3224 u32 index
= vmx_msr_index
[i
];
3225 u32 data_low
, data_high
;
3228 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
3230 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
3232 vmx
->guest_msrs
[j
].index
= i
;
3233 vmx
->guest_msrs
[j
].data
= 0;
3234 vmx
->guest_msrs
[j
].mask
= -1ull;
3238 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
3240 /* 22.2.1, 20.8.1 */
3241 vmcs_write32(VM_ENTRY_CONTROLS
, vmcs_config
.vmentry_ctrl
);
3243 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
3244 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
3246 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
3247 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
3249 kvm_write_tsc(&vmx
->vcpu
, 0);
3254 static int vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
3256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3260 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
));
3262 vmx
->rmode
.vm86_active
= 0;
3264 vmx
->soft_vnmi_blocked
= 0;
3266 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
3267 kvm_set_cr8(&vmx
->vcpu
, 0);
3268 msr
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
3269 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3270 msr
|= MSR_IA32_APICBASE_BSP
;
3271 kvm_set_apic_base(&vmx
->vcpu
, msr
);
3273 ret
= fx_init(&vmx
->vcpu
);
3277 vmx_segment_cache_clear(vmx
);
3279 seg_setup(VCPU_SREG_CS
);
3281 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3282 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3284 if (kvm_vcpu_is_bsp(&vmx
->vcpu
)) {
3285 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
3286 vmcs_writel(GUEST_CS_BASE
, 0x000f0000);
3288 vmcs_write16(GUEST_CS_SELECTOR
, vmx
->vcpu
.arch
.sipi_vector
<< 8);
3289 vmcs_writel(GUEST_CS_BASE
, vmx
->vcpu
.arch
.sipi_vector
<< 12);
3292 seg_setup(VCPU_SREG_DS
);
3293 seg_setup(VCPU_SREG_ES
);
3294 seg_setup(VCPU_SREG_FS
);
3295 seg_setup(VCPU_SREG_GS
);
3296 seg_setup(VCPU_SREG_SS
);
3298 vmcs_write16(GUEST_TR_SELECTOR
, 0);
3299 vmcs_writel(GUEST_TR_BASE
, 0);
3300 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
3301 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3303 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
3304 vmcs_writel(GUEST_LDTR_BASE
, 0);
3305 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
3306 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
3308 vmcs_write32(GUEST_SYSENTER_CS
, 0);
3309 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
3310 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
3312 vmcs_writel(GUEST_RFLAGS
, 0x02);
3313 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
3314 kvm_rip_write(vcpu
, 0xfff0);
3316 kvm_rip_write(vcpu
, 0);
3317 kvm_register_write(vcpu
, VCPU_REGS_RSP
, 0);
3319 vmcs_writel(GUEST_DR7
, 0x400);
3321 vmcs_writel(GUEST_GDTR_BASE
, 0);
3322 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
3324 vmcs_writel(GUEST_IDTR_BASE
, 0);
3325 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
3327 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
3328 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
3329 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
3331 /* Special registers */
3332 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
3336 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
3338 if (cpu_has_vmx_tpr_shadow()) {
3339 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
3340 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
3341 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
3342 __pa(vmx
->vcpu
.arch
.apic
->regs
));
3343 vmcs_write32(TPR_THRESHOLD
, 0);
3346 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
3347 vmcs_write64(APIC_ACCESS_ADDR
,
3348 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
3351 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
3353 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
3354 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
3355 vmx_set_cr4(&vmx
->vcpu
, 0);
3356 vmx_set_efer(&vmx
->vcpu
, 0);
3357 vmx_fpu_activate(&vmx
->vcpu
);
3358 update_exception_bitmap(&vmx
->vcpu
);
3360 vpid_sync_context(vmx
);
3364 /* HACK: Don't enable emulation on guest boot/reset */
3365 vmx
->emulation_required
= 0;
3371 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
3373 u32 cpu_based_vm_exec_control
;
3375 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3376 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
3377 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3380 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
3382 u32 cpu_based_vm_exec_control
;
3384 if (!cpu_has_virtual_nmis()) {
3385 enable_irq_window(vcpu
);
3389 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
3390 enable_irq_window(vcpu
);
3393 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3394 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
3395 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3398 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
3400 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3402 int irq
= vcpu
->arch
.interrupt
.nr
;
3404 trace_kvm_inj_virq(irq
);
3406 ++vcpu
->stat
.irq_injections
;
3407 if (vmx
->rmode
.vm86_active
) {
3409 if (vcpu
->arch
.interrupt
.soft
)
3410 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
3411 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
3412 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3415 intr
= irq
| INTR_INFO_VALID_MASK
;
3416 if (vcpu
->arch
.interrupt
.soft
) {
3417 intr
|= INTR_TYPE_SOFT_INTR
;
3418 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
3419 vmx
->vcpu
.arch
.event_exit_inst_len
);
3421 intr
|= INTR_TYPE_EXT_INTR
;
3422 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
3423 vmx_clear_hlt(vcpu
);
3426 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
3428 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3430 if (!cpu_has_virtual_nmis()) {
3432 * Tracking the NMI-blocked state in software is built upon
3433 * finding the next open IRQ window. This, in turn, depends on
3434 * well-behaving guests: They have to keep IRQs disabled at
3435 * least as long as the NMI handler runs. Otherwise we may
3436 * cause NMI nesting, maybe breaking the guest. But as this is
3437 * highly unlikely, we can live with the residual risk.
3439 vmx
->soft_vnmi_blocked
= 1;
3440 vmx
->vnmi_blocked_time
= 0;
3443 ++vcpu
->stat
.nmi_injections
;
3444 vmx
->nmi_known_unmasked
= false;
3445 if (vmx
->rmode
.vm86_active
) {
3446 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
3447 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
3450 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
3451 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
3452 vmx_clear_hlt(vcpu
);
3455 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
3457 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
3460 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3461 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
3462 | GUEST_INTR_STATE_NMI
));
3465 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
3467 if (!cpu_has_virtual_nmis())
3468 return to_vmx(vcpu
)->soft_vnmi_blocked
;
3469 if (to_vmx(vcpu
)->nmi_known_unmasked
)
3471 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
3474 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
3476 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3478 if (!cpu_has_virtual_nmis()) {
3479 if (vmx
->soft_vnmi_blocked
!= masked
) {
3480 vmx
->soft_vnmi_blocked
= masked
;
3481 vmx
->vnmi_blocked_time
= 0;
3484 vmx
->nmi_known_unmasked
= !masked
;
3486 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
3487 GUEST_INTR_STATE_NMI
);
3489 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
3490 GUEST_INTR_STATE_NMI
);
3494 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
3496 return (vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
3497 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
3498 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
3501 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
3504 struct kvm_userspace_memory_region tss_mem
= {
3505 .slot
= TSS_PRIVATE_MEMSLOT
,
3506 .guest_phys_addr
= addr
,
3507 .memory_size
= PAGE_SIZE
* 3,
3511 ret
= kvm_set_memory_region(kvm
, &tss_mem
, 0);
3514 kvm
->arch
.tss_addr
= addr
;
3515 if (!init_rmode_tss(kvm
))
3521 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
3522 int vec
, u32 err_code
)
3525 * Instruction with address size override prefix opcode 0x67
3526 * Cause the #SS fault with 0 error code in VM86 mode.
3528 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0)
3529 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
)
3532 * Forward all other exceptions that are valid in real mode.
3533 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3534 * the required debugging infrastructure rework.
3538 if (vcpu
->guest_debug
&
3539 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
3541 kvm_queue_exception(vcpu
, vec
);
3545 * Update instruction length as we may reinject the exception
3546 * from user space while in guest debugging mode.
3548 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
3549 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3550 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
3561 kvm_queue_exception(vcpu
, vec
);
3568 * Trigger machine check on the host. We assume all the MSRs are already set up
3569 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3570 * We pass a fake environment to the machine check handler because we want
3571 * the guest to be always treated like user space, no matter what context
3572 * it used internally.
3574 static void kvm_machine_check(void)
3576 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3577 struct pt_regs regs
= {
3578 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
3579 .flags
= X86_EFLAGS_IF
,
3582 do_machine_check(®s
, 0);
3586 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
3588 /* already handled by vcpu_run */
3592 static int handle_exception(struct kvm_vcpu
*vcpu
)
3594 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3595 struct kvm_run
*kvm_run
= vcpu
->run
;
3596 u32 intr_info
, ex_no
, error_code
;
3597 unsigned long cr2
, rip
, dr6
;
3599 enum emulation_result er
;
3601 vect_info
= vmx
->idt_vectoring_info
;
3602 intr_info
= vmx
->exit_intr_info
;
3604 if (is_machine_check(intr_info
))
3605 return handle_machine_check(vcpu
);
3607 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
3608 !is_page_fault(intr_info
)) {
3609 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
3610 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
3611 vcpu
->run
->internal
.ndata
= 2;
3612 vcpu
->run
->internal
.data
[0] = vect_info
;
3613 vcpu
->run
->internal
.data
[1] = intr_info
;
3617 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
3618 return 1; /* already handled by vmx_vcpu_run() */
3620 if (is_no_device(intr_info
)) {
3621 vmx_fpu_activate(vcpu
);
3625 if (is_invalid_opcode(intr_info
)) {
3626 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
3627 if (er
!= EMULATE_DONE
)
3628 kvm_queue_exception(vcpu
, UD_VECTOR
);
3633 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
3634 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
3635 if (is_page_fault(intr_info
)) {
3636 /* EPT won't cause page fault directly */
3639 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
3640 trace_kvm_page_fault(cr2
, error_code
);
3642 if (kvm_event_needs_reinjection(vcpu
))
3643 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
3644 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
3647 if (vmx
->rmode
.vm86_active
&&
3648 handle_rmode_exception(vcpu
, intr_info
& INTR_INFO_VECTOR_MASK
,
3650 if (vcpu
->arch
.halt_request
) {
3651 vcpu
->arch
.halt_request
= 0;
3652 return kvm_emulate_halt(vcpu
);
3657 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
3660 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
3661 if (!(vcpu
->guest_debug
&
3662 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
3663 vcpu
->arch
.dr6
= dr6
| DR6_FIXED_1
;
3664 kvm_queue_exception(vcpu
, DB_VECTOR
);
3667 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
3668 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
3672 * Update instruction length as we may reinject #BP from
3673 * user space while in guest debugging mode. Reading it for
3674 * #DB as well causes no harm, it is not used in that case.
3676 vmx
->vcpu
.arch
.event_exit_inst_len
=
3677 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
3678 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
3679 rip
= kvm_rip_read(vcpu
);
3680 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
3681 kvm_run
->debug
.arch
.exception
= ex_no
;
3684 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
3685 kvm_run
->ex
.exception
= ex_no
;
3686 kvm_run
->ex
.error_code
= error_code
;
3692 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
3694 ++vcpu
->stat
.irq_exits
;
3698 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
3700 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
3704 static int handle_io(struct kvm_vcpu
*vcpu
)
3706 unsigned long exit_qualification
;
3707 int size
, in
, string
;
3710 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3711 string
= (exit_qualification
& 16) != 0;
3712 in
= (exit_qualification
& 8) != 0;
3714 ++vcpu
->stat
.io_exits
;
3717 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3719 port
= exit_qualification
>> 16;
3720 size
= (exit_qualification
& 7) + 1;
3721 skip_emulated_instruction(vcpu
);
3723 return kvm_fast_pio_out(vcpu
, size
, port
);
3727 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
3730 * Patch in the VMCALL instruction:
3732 hypercall
[0] = 0x0f;
3733 hypercall
[1] = 0x01;
3734 hypercall
[2] = 0xc1;
3737 static int handle_cr(struct kvm_vcpu
*vcpu
)
3739 unsigned long exit_qualification
, val
;
3744 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3745 cr
= exit_qualification
& 15;
3746 reg
= (exit_qualification
>> 8) & 15;
3747 switch ((exit_qualification
>> 4) & 3) {
3748 case 0: /* mov to cr */
3749 val
= kvm_register_read(vcpu
, reg
);
3750 trace_kvm_cr_write(cr
, val
);
3753 err
= kvm_set_cr0(vcpu
, val
);
3754 kvm_complete_insn_gp(vcpu
, err
);
3757 err
= kvm_set_cr3(vcpu
, val
);
3758 kvm_complete_insn_gp(vcpu
, err
);
3761 err
= kvm_set_cr4(vcpu
, val
);
3762 kvm_complete_insn_gp(vcpu
, err
);
3765 u8 cr8_prev
= kvm_get_cr8(vcpu
);
3766 u8 cr8
= kvm_register_read(vcpu
, reg
);
3767 err
= kvm_set_cr8(vcpu
, cr8
);
3768 kvm_complete_insn_gp(vcpu
, err
);
3769 if (irqchip_in_kernel(vcpu
->kvm
))
3771 if (cr8_prev
<= cr8
)
3773 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
3779 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
3780 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
3781 skip_emulated_instruction(vcpu
);
3782 vmx_fpu_activate(vcpu
);
3784 case 1: /*mov from cr*/
3787 val
= kvm_read_cr3(vcpu
);
3788 kvm_register_write(vcpu
, reg
, val
);
3789 trace_kvm_cr_read(cr
, val
);
3790 skip_emulated_instruction(vcpu
);
3793 val
= kvm_get_cr8(vcpu
);
3794 kvm_register_write(vcpu
, reg
, val
);
3795 trace_kvm_cr_read(cr
, val
);
3796 skip_emulated_instruction(vcpu
);
3801 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
3802 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
3803 kvm_lmsw(vcpu
, val
);
3805 skip_emulated_instruction(vcpu
);
3810 vcpu
->run
->exit_reason
= 0;
3811 pr_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
3812 (int)(exit_qualification
>> 4) & 3, cr
);
3816 static int handle_dr(struct kvm_vcpu
*vcpu
)
3818 unsigned long exit_qualification
;
3821 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3822 if (!kvm_require_cpl(vcpu
, 0))
3824 dr
= vmcs_readl(GUEST_DR7
);
3827 * As the vm-exit takes precedence over the debug trap, we
3828 * need to emulate the latter, either for the host or the
3829 * guest debugging itself.
3831 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
3832 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
3833 vcpu
->run
->debug
.arch
.dr7
= dr
;
3834 vcpu
->run
->debug
.arch
.pc
=
3835 vmcs_readl(GUEST_CS_BASE
) +
3836 vmcs_readl(GUEST_RIP
);
3837 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
3838 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
3841 vcpu
->arch
.dr7
&= ~DR7_GD
;
3842 vcpu
->arch
.dr6
|= DR6_BD
;
3843 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
3844 kvm_queue_exception(vcpu
, DB_VECTOR
);
3849 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3850 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
3851 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
3852 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
3854 if (!kvm_get_dr(vcpu
, dr
, &val
))
3855 kvm_register_write(vcpu
, reg
, val
);
3857 kvm_set_dr(vcpu
, dr
, vcpu
->arch
.regs
[reg
]);
3858 skip_emulated_instruction(vcpu
);
3862 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
3864 vmcs_writel(GUEST_DR7
, val
);
3867 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
3869 kvm_emulate_cpuid(vcpu
);
3873 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
3875 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3878 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
3879 trace_kvm_msr_read_ex(ecx
);
3880 kvm_inject_gp(vcpu
, 0);
3884 trace_kvm_msr_read(ecx
, data
);
3886 /* FIXME: handling of bits 32:63 of rax, rdx */
3887 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
3888 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
3889 skip_emulated_instruction(vcpu
);
3893 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
3895 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
3896 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
3897 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
3899 if (vmx_set_msr(vcpu
, ecx
, data
) != 0) {
3900 trace_kvm_msr_write_ex(ecx
, data
);
3901 kvm_inject_gp(vcpu
, 0);
3905 trace_kvm_msr_write(ecx
, data
);
3906 skip_emulated_instruction(vcpu
);
3910 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
3912 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3916 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
3918 u32 cpu_based_vm_exec_control
;
3920 /* clear pending irq */
3921 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
3922 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
3923 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
3925 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
3927 ++vcpu
->stat
.irq_window_exits
;
3930 * If the user space waits to inject interrupts, exit as soon as
3933 if (!irqchip_in_kernel(vcpu
->kvm
) &&
3934 vcpu
->run
->request_interrupt_window
&&
3935 !kvm_cpu_has_interrupt(vcpu
)) {
3936 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
3942 static int handle_halt(struct kvm_vcpu
*vcpu
)
3944 skip_emulated_instruction(vcpu
);
3945 return kvm_emulate_halt(vcpu
);
3948 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
3950 skip_emulated_instruction(vcpu
);
3951 kvm_emulate_hypercall(vcpu
);
3955 static int handle_vmx_insn(struct kvm_vcpu
*vcpu
)
3957 kvm_queue_exception(vcpu
, UD_VECTOR
);
3961 static int handle_invd(struct kvm_vcpu
*vcpu
)
3963 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3966 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
3968 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
3970 kvm_mmu_invlpg(vcpu
, exit_qualification
);
3971 skip_emulated_instruction(vcpu
);
3975 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
3977 skip_emulated_instruction(vcpu
);
3978 kvm_emulate_wbinvd(vcpu
);
3982 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
3984 u64 new_bv
= kvm_read_edx_eax(vcpu
);
3985 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
3987 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
3988 skip_emulated_instruction(vcpu
);
3992 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
3994 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
3997 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
3999 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4000 unsigned long exit_qualification
;
4001 bool has_error_code
= false;
4004 int reason
, type
, idt_v
;
4006 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
4007 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
4009 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4011 reason
= (u32
)exit_qualification
>> 30;
4012 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
4014 case INTR_TYPE_NMI_INTR
:
4015 vcpu
->arch
.nmi_injected
= false;
4016 vmx_set_nmi_mask(vcpu
, true);
4018 case INTR_TYPE_EXT_INTR
:
4019 case INTR_TYPE_SOFT_INTR
:
4020 kvm_clear_interrupt_queue(vcpu
);
4022 case INTR_TYPE_HARD_EXCEPTION
:
4023 if (vmx
->idt_vectoring_info
&
4024 VECTORING_INFO_DELIVER_CODE_MASK
) {
4025 has_error_code
= true;
4027 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
4030 case INTR_TYPE_SOFT_EXCEPTION
:
4031 kvm_clear_exception_queue(vcpu
);
4037 tss_selector
= exit_qualification
;
4039 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
4040 type
!= INTR_TYPE_EXT_INTR
&&
4041 type
!= INTR_TYPE_NMI_INTR
))
4042 skip_emulated_instruction(vcpu
);
4044 if (kvm_task_switch(vcpu
, tss_selector
, reason
,
4045 has_error_code
, error_code
) == EMULATE_FAIL
) {
4046 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4047 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
4048 vcpu
->run
->internal
.ndata
= 0;
4052 /* clear all local breakpoint enable flags */
4053 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~55);
4056 * TODO: What about debug traps on tss switch?
4057 * Are we supposed to inject them and update dr6?
4063 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
4065 unsigned long exit_qualification
;
4069 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4071 if (exit_qualification
& (1 << 6)) {
4072 printk(KERN_ERR
"EPT: GPA exceeds GAW!\n");
4076 gla_validity
= (exit_qualification
>> 7) & 0x3;
4077 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
4078 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
4079 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4080 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
4081 vmcs_readl(GUEST_LINEAR_ADDRESS
));
4082 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
4083 (long unsigned int)exit_qualification
);
4084 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4085 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
4089 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4090 trace_kvm_page_fault(gpa
, exit_qualification
);
4091 return kvm_mmu_page_fault(vcpu
, gpa
, exit_qualification
& 0x3, NULL
, 0);
4094 static u64
ept_rsvd_mask(u64 spte
, int level
)
4099 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
4100 mask
|= (1ULL << i
);
4103 /* bits 7:3 reserved */
4105 else if (level
== 2) {
4106 if (spte
& (1ULL << 7))
4107 /* 2MB ref, bits 20:12 reserved */
4110 /* bits 6:3 reserved */
4117 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
4120 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
4122 /* 010b (write-only) */
4123 WARN_ON((spte
& 0x7) == 0x2);
4125 /* 110b (write/execute) */
4126 WARN_ON((spte
& 0x7) == 0x6);
4128 /* 100b (execute-only) and value not supported by logical processor */
4129 if (!cpu_has_vmx_ept_execute_only())
4130 WARN_ON((spte
& 0x7) == 0x4);
4134 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
4136 if (rsvd_bits
!= 0) {
4137 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
4138 __func__
, rsvd_bits
);
4142 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
4143 u64 ept_mem_type
= (spte
& 0x38) >> 3;
4145 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
4146 ept_mem_type
== 7) {
4147 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
4148 __func__
, ept_mem_type
);
4155 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
4161 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
4163 printk(KERN_ERR
"EPT: Misconfiguration.\n");
4164 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
4166 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
4168 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
4169 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
4171 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4172 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
4177 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
4179 u32 cpu_based_vm_exec_control
;
4181 /* clear pending NMI */
4182 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4183 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
4184 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4185 ++vcpu
->stat
.nmi_window_exits
;
4186 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4191 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
4193 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4194 enum emulation_result err
= EMULATE_DONE
;
4197 bool intr_window_requested
;
4199 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4200 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
4202 while (!guest_state_valid(vcpu
)) {
4203 if (intr_window_requested
4204 && (kvm_get_rflags(&vmx
->vcpu
) & X86_EFLAGS_IF
))
4205 return handle_interrupt_window(&vmx
->vcpu
);
4207 err
= emulate_instruction(vcpu
, 0);
4209 if (err
== EMULATE_DO_MMIO
) {
4214 if (err
!= EMULATE_DONE
)
4217 if (signal_pending(current
))
4223 vmx
->emulation_required
= 0;
4229 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4230 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4232 static int handle_pause(struct kvm_vcpu
*vcpu
)
4234 skip_emulated_instruction(vcpu
);
4235 kvm_vcpu_on_spin(vcpu
);
4240 static int handle_invalid_op(struct kvm_vcpu
*vcpu
)
4242 kvm_queue_exception(vcpu
, UD_VECTOR
);
4247 * Emulate the VMXON instruction.
4248 * Currently, we just remember that VMX is active, and do not save or even
4249 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4250 * do not currently need to store anything in that guest-allocated memory
4251 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4252 * argument is different from the VMXON pointer (which the spec says they do).
4254 static int handle_vmon(struct kvm_vcpu
*vcpu
)
4256 struct kvm_segment cs
;
4257 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4259 /* The Intel VMX Instruction Reference lists a bunch of bits that
4260 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4261 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4262 * Otherwise, we should fail with #UD. We test these now:
4264 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
4265 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
4266 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4267 kvm_queue_exception(vcpu
, UD_VECTOR
);
4271 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4272 if (is_long_mode(vcpu
) && !cs
.l
) {
4273 kvm_queue_exception(vcpu
, UD_VECTOR
);
4277 if (vmx_get_cpl(vcpu
)) {
4278 kvm_inject_gp(vcpu
, 0);
4282 vmx
->nested
.vmxon
= true;
4284 skip_emulated_instruction(vcpu
);
4289 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4290 * for running VMX instructions (except VMXON, whose prerequisites are
4291 * slightly different). It also specifies what exception to inject otherwise.
4293 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
4295 struct kvm_segment cs
;
4296 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4298 if (!vmx
->nested
.vmxon
) {
4299 kvm_queue_exception(vcpu
, UD_VECTOR
);
4303 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4304 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
4305 (is_long_mode(vcpu
) && !cs
.l
)) {
4306 kvm_queue_exception(vcpu
, UD_VECTOR
);
4310 if (vmx_get_cpl(vcpu
)) {
4311 kvm_inject_gp(vcpu
, 0);
4319 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4320 * just stops using VMX.
4322 static void free_nested(struct vcpu_vmx
*vmx
)
4324 if (!vmx
->nested
.vmxon
)
4326 vmx
->nested
.vmxon
= false;
4327 if (vmx
->nested
.current_vmptr
!= -1ull) {
4328 kunmap(vmx
->nested
.current_vmcs12_page
);
4329 nested_release_page(vmx
->nested
.current_vmcs12_page
);
4330 vmx
->nested
.current_vmptr
= -1ull;
4331 vmx
->nested
.current_vmcs12
= NULL
;
4335 /* Emulate the VMXOFF instruction */
4336 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
4338 if (!nested_vmx_check_permission(vcpu
))
4340 free_nested(to_vmx(vcpu
));
4341 skip_emulated_instruction(vcpu
);
4346 * Decode the memory-address operand of a vmx instruction, as recorded on an
4347 * exit caused by such an instruction (run by a guest hypervisor).
4348 * On success, returns 0. When the operand is invalid, returns 1 and throws
4351 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
4352 unsigned long exit_qualification
,
4353 u32 vmx_instruction_info
, gva_t
*ret
)
4356 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4357 * Execution", on an exit, vmx_instruction_info holds most of the
4358 * addressing components of the operand. Only the displacement part
4359 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4360 * For how an actual address is calculated from all these components,
4361 * refer to Vol. 1, "Operand Addressing".
4363 int scaling
= vmx_instruction_info
& 3;
4364 int addr_size
= (vmx_instruction_info
>> 7) & 7;
4365 bool is_reg
= vmx_instruction_info
& (1u << 10);
4366 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
4367 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
4368 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
4369 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
4370 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
4373 kvm_queue_exception(vcpu
, UD_VECTOR
);
4377 /* Addr = segment_base + offset */
4378 /* offset = base + [index * scale] + displacement */
4379 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
4381 *ret
+= kvm_register_read(vcpu
, base_reg
);
4383 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
4384 *ret
+= exit_qualification
; /* holds the displacement */
4386 if (addr_size
== 1) /* 32 bit */
4390 * TODO: throw #GP (and return 1) in various cases that the VM*
4391 * instructions require it - e.g., offset beyond segment limit,
4392 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4393 * address, and so on. Currently these are not checked.
4399 * The exit handlers return 1 if the exit was handled fully and guest execution
4400 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
4401 * to be done to userspace and return 0.
4403 static int (*kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
4404 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
4405 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
4406 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
4407 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
4408 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
4409 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
4410 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
4411 [EXIT_REASON_CPUID
] = handle_cpuid
,
4412 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
4413 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
4414 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
4415 [EXIT_REASON_HLT
] = handle_halt
,
4416 [EXIT_REASON_INVD
] = handle_invd
,
4417 [EXIT_REASON_INVLPG
] = handle_invlpg
,
4418 [EXIT_REASON_VMCALL
] = handle_vmcall
,
4419 [EXIT_REASON_VMCLEAR
] = handle_vmx_insn
,
4420 [EXIT_REASON_VMLAUNCH
] = handle_vmx_insn
,
4421 [EXIT_REASON_VMPTRLD
] = handle_vmx_insn
,
4422 [EXIT_REASON_VMPTRST
] = handle_vmx_insn
,
4423 [EXIT_REASON_VMREAD
] = handle_vmx_insn
,
4424 [EXIT_REASON_VMRESUME
] = handle_vmx_insn
,
4425 [EXIT_REASON_VMWRITE
] = handle_vmx_insn
,
4426 [EXIT_REASON_VMOFF
] = handle_vmoff
,
4427 [EXIT_REASON_VMON
] = handle_vmon
,
4428 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
4429 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
4430 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
4431 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
4432 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
4433 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
4434 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
4435 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
4436 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
4437 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_invalid_op
,
4438 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_invalid_op
,
4441 static const int kvm_vmx_max_exit_handlers
=
4442 ARRAY_SIZE(kvm_vmx_exit_handlers
);
4444 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
4446 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
4447 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
4451 * The guest has exited. See if we can fix it or if we need userspace
4454 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
4456 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4457 u32 exit_reason
= vmx
->exit_reason
;
4458 u32 vectoring_info
= vmx
->idt_vectoring_info
;
4460 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
4462 /* If guest state is invalid, start emulating */
4463 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
4464 return handle_invalid_guest_state(vcpu
);
4466 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
4467 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4468 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
4473 if (unlikely(vmx
->fail
)) {
4474 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
4475 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
4476 = vmcs_read32(VM_INSTRUCTION_ERROR
);
4480 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
4481 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
4482 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
4483 exit_reason
!= EXIT_REASON_TASK_SWITCH
))
4484 printk(KERN_WARNING
"%s: unexpected, valid vectoring info "
4485 "(0x%x) and exit reason is 0x%x\n",
4486 __func__
, vectoring_info
, exit_reason
);
4488 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
)) {
4489 if (vmx_interrupt_allowed(vcpu
)) {
4490 vmx
->soft_vnmi_blocked
= 0;
4491 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
4492 vcpu
->arch
.nmi_pending
) {
4494 * This CPU don't support us in finding the end of an
4495 * NMI-blocked window if the guest runs with IRQs
4496 * disabled. So we pull the trigger after 1 s of
4497 * futile waiting, but inform the user about this.
4499 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
4500 "state on VCPU %d after 1 s timeout\n",
4501 __func__
, vcpu
->vcpu_id
);
4502 vmx
->soft_vnmi_blocked
= 0;
4506 if (exit_reason
< kvm_vmx_max_exit_handlers
4507 && kvm_vmx_exit_handlers
[exit_reason
])
4508 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
4510 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
4511 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
4516 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
4518 if (irr
== -1 || tpr
< irr
) {
4519 vmcs_write32(TPR_THRESHOLD
, 0);
4523 vmcs_write32(TPR_THRESHOLD
, irr
);
4526 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
4530 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
4531 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
4534 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
4535 exit_intr_info
= vmx
->exit_intr_info
;
4537 /* Handle machine checks before interrupts are enabled */
4538 if (is_machine_check(exit_intr_info
))
4539 kvm_machine_check();
4541 /* We need to handle NMIs before interrupts are enabled */
4542 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
4543 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
4544 kvm_before_handle_nmi(&vmx
->vcpu
);
4546 kvm_after_handle_nmi(&vmx
->vcpu
);
4550 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
4555 bool idtv_info_valid
;
4557 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
4559 if (cpu_has_virtual_nmis()) {
4560 if (vmx
->nmi_known_unmasked
)
4563 * Can't use vmx->exit_intr_info since we're not sure what
4564 * the exit reason is.
4566 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
4567 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
4568 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
4570 * SDM 3: 27.7.1.2 (September 2008)
4571 * Re-set bit "block by NMI" before VM entry if vmexit caused by
4572 * a guest IRET fault.
4573 * SDM 3: 23.2.2 (September 2008)
4574 * Bit 12 is undefined in any of the following cases:
4575 * If the VM exit sets the valid bit in the IDT-vectoring
4576 * information field.
4577 * If the VM exit is due to a double fault.
4579 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
4580 vector
!= DF_VECTOR
&& !idtv_info_valid
)
4581 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4582 GUEST_INTR_STATE_NMI
);
4584 vmx
->nmi_known_unmasked
=
4585 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
4586 & GUEST_INTR_STATE_NMI
);
4587 } else if (unlikely(vmx
->soft_vnmi_blocked
))
4588 vmx
->vnmi_blocked_time
+=
4589 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
4592 static void __vmx_complete_interrupts(struct vcpu_vmx
*vmx
,
4593 u32 idt_vectoring_info
,
4594 int instr_len_field
,
4595 int error_code_field
)
4599 bool idtv_info_valid
;
4601 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
4603 vmx
->vcpu
.arch
.nmi_injected
= false;
4604 kvm_clear_exception_queue(&vmx
->vcpu
);
4605 kvm_clear_interrupt_queue(&vmx
->vcpu
);
4607 if (!idtv_info_valid
)
4610 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
4612 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
4613 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
4616 case INTR_TYPE_NMI_INTR
:
4617 vmx
->vcpu
.arch
.nmi_injected
= true;
4619 * SDM 3: 27.7.1.2 (September 2008)
4620 * Clear bit "block by NMI" before VM entry if a NMI
4623 vmx_set_nmi_mask(&vmx
->vcpu
, false);
4625 case INTR_TYPE_SOFT_EXCEPTION
:
4626 vmx
->vcpu
.arch
.event_exit_inst_len
=
4627 vmcs_read32(instr_len_field
);
4629 case INTR_TYPE_HARD_EXCEPTION
:
4630 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
4631 u32 err
= vmcs_read32(error_code_field
);
4632 kvm_queue_exception_e(&vmx
->vcpu
, vector
, err
);
4634 kvm_queue_exception(&vmx
->vcpu
, vector
);
4636 case INTR_TYPE_SOFT_INTR
:
4637 vmx
->vcpu
.arch
.event_exit_inst_len
=
4638 vmcs_read32(instr_len_field
);
4640 case INTR_TYPE_EXT_INTR
:
4641 kvm_queue_interrupt(&vmx
->vcpu
, vector
,
4642 type
== INTR_TYPE_SOFT_INTR
);
4649 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
4651 __vmx_complete_interrupts(vmx
, vmx
->idt_vectoring_info
,
4652 VM_EXIT_INSTRUCTION_LEN
,
4653 IDT_VECTORING_ERROR_CODE
);
4656 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
4658 __vmx_complete_interrupts(to_vmx(vcpu
),
4659 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
4660 VM_ENTRY_INSTRUCTION_LEN
,
4661 VM_ENTRY_EXCEPTION_ERROR_CODE
);
4663 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
4666 #ifdef CONFIG_X86_64
4674 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
4676 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4678 /* Record the guest's net vcpu time for enforced NMI injections. */
4679 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
4680 vmx
->entry_time
= ktime_get();
4682 /* Don't enter VMX if guest state is invalid, let the exit handler
4683 start emulation until we arrive back to a valid state */
4684 if (vmx
->emulation_required
&& emulate_invalid_guest_state
)
4687 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
4688 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
4689 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
4690 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
4692 /* When single-stepping over STI and MOV SS, we must clear the
4693 * corresponding interruptibility bits in the guest state. Otherwise
4694 * vmentry fails as it then expects bit 14 (BS) in pending debug
4695 * exceptions being set, but that's not correct for the guest debugging
4697 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
4698 vmx_set_interrupt_shadow(vcpu
, 0);
4700 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
4702 /* Store host registers */
4703 "push %%"R
"dx; push %%"R
"bp;"
4704 "push %%"R
"cx \n\t" /* placeholder for guest rcx */
4706 "cmp %%"R
"sp, %c[host_rsp](%0) \n\t"
4708 "mov %%"R
"sp, %c[host_rsp](%0) \n\t"
4709 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
4711 /* Reload cr2 if changed */
4712 "mov %c[cr2](%0), %%"R
"ax \n\t"
4713 "mov %%cr2, %%"R
"dx \n\t"
4714 "cmp %%"R
"ax, %%"R
"dx \n\t"
4716 "mov %%"R
"ax, %%cr2 \n\t"
4718 /* Check if vmlaunch of vmresume is needed */
4719 "cmpl $0, %c[launched](%0) \n\t"
4720 /* Load guest registers. Don't clobber flags. */
4721 "mov %c[rax](%0), %%"R
"ax \n\t"
4722 "mov %c[rbx](%0), %%"R
"bx \n\t"
4723 "mov %c[rdx](%0), %%"R
"dx \n\t"
4724 "mov %c[rsi](%0), %%"R
"si \n\t"
4725 "mov %c[rdi](%0), %%"R
"di \n\t"
4726 "mov %c[rbp](%0), %%"R
"bp \n\t"
4727 #ifdef CONFIG_X86_64
4728 "mov %c[r8](%0), %%r8 \n\t"
4729 "mov %c[r9](%0), %%r9 \n\t"
4730 "mov %c[r10](%0), %%r10 \n\t"
4731 "mov %c[r11](%0), %%r11 \n\t"
4732 "mov %c[r12](%0), %%r12 \n\t"
4733 "mov %c[r13](%0), %%r13 \n\t"
4734 "mov %c[r14](%0), %%r14 \n\t"
4735 "mov %c[r15](%0), %%r15 \n\t"
4737 "mov %c[rcx](%0), %%"R
"cx \n\t" /* kills %0 (ecx) */
4739 /* Enter guest mode */
4740 "jne .Llaunched \n\t"
4741 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
4742 "jmp .Lkvm_vmx_return \n\t"
4743 ".Llaunched: " __ex(ASM_VMX_VMRESUME
) "\n\t"
4744 ".Lkvm_vmx_return: "
4745 /* Save guest registers, load host registers, keep flags */
4746 "mov %0, %c[wordsize](%%"R
"sp) \n\t"
4748 "mov %%"R
"ax, %c[rax](%0) \n\t"
4749 "mov %%"R
"bx, %c[rbx](%0) \n\t"
4750 "pop"Q
" %c[rcx](%0) \n\t"
4751 "mov %%"R
"dx, %c[rdx](%0) \n\t"
4752 "mov %%"R
"si, %c[rsi](%0) \n\t"
4753 "mov %%"R
"di, %c[rdi](%0) \n\t"
4754 "mov %%"R
"bp, %c[rbp](%0) \n\t"
4755 #ifdef CONFIG_X86_64
4756 "mov %%r8, %c[r8](%0) \n\t"
4757 "mov %%r9, %c[r9](%0) \n\t"
4758 "mov %%r10, %c[r10](%0) \n\t"
4759 "mov %%r11, %c[r11](%0) \n\t"
4760 "mov %%r12, %c[r12](%0) \n\t"
4761 "mov %%r13, %c[r13](%0) \n\t"
4762 "mov %%r14, %c[r14](%0) \n\t"
4763 "mov %%r15, %c[r15](%0) \n\t"
4765 "mov %%cr2, %%"R
"ax \n\t"
4766 "mov %%"R
"ax, %c[cr2](%0) \n\t"
4768 "pop %%"R
"bp; pop %%"R
"dx \n\t"
4769 "setbe %c[fail](%0) \n\t"
4770 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
4771 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
4772 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
4773 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
4774 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
4775 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
4776 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
4777 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
4778 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
4779 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
4780 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
4781 #ifdef CONFIG_X86_64
4782 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
4783 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
4784 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
4785 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
4786 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
4787 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
4788 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
4789 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
4791 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
4792 [wordsize
]"i"(sizeof(ulong
))
4794 , R
"ax", R
"bx", R
"di", R
"si"
4795 #ifdef CONFIG_X86_64
4796 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4800 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
4801 | (1 << VCPU_EXREG_RFLAGS
)
4802 | (1 << VCPU_EXREG_CPL
)
4803 | (1 << VCPU_EXREG_PDPTR
)
4804 | (1 << VCPU_EXREG_SEGMENTS
)
4805 | (1 << VCPU_EXREG_CR3
));
4806 vcpu
->arch
.regs_dirty
= 0;
4808 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
4810 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS
));
4811 vmx
->loaded_vmcs
->launched
= 1;
4813 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
4815 vmx_complete_atomic_exit(vmx
);
4816 vmx_recover_nmi_blocking(vmx
);
4817 vmx_complete_interrupts(vmx
);
4823 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
4825 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4829 free_loaded_vmcs(vmx
->loaded_vmcs
);
4830 kfree(vmx
->guest_msrs
);
4831 kvm_vcpu_uninit(vcpu
);
4832 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4835 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
4838 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
4842 return ERR_PTR(-ENOMEM
);
4846 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
4850 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
4852 if (!vmx
->guest_msrs
) {
4856 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
4857 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
4858 if (!vmx
->loaded_vmcs
->vmcs
)
4861 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
4862 loaded_vmcs_init(vmx
->loaded_vmcs
);
4867 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
4868 vmx
->vcpu
.cpu
= cpu
;
4869 err
= vmx_vcpu_setup(vmx
);
4870 vmx_vcpu_put(&vmx
->vcpu
);
4874 if (vm_need_virtualize_apic_accesses(kvm
))
4875 err
= alloc_apic_access_page(kvm
);
4880 if (!kvm
->arch
.ept_identity_map_addr
)
4881 kvm
->arch
.ept_identity_map_addr
=
4882 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
4884 if (alloc_identity_pagetable(kvm
) != 0)
4886 if (!init_rmode_identity_map(kvm
))
4890 vmx
->nested
.current_vmptr
= -1ull;
4891 vmx
->nested
.current_vmcs12
= NULL
;
4896 free_vmcs(vmx
->loaded_vmcs
->vmcs
);
4898 kfree(vmx
->guest_msrs
);
4900 kvm_vcpu_uninit(&vmx
->vcpu
);
4903 kmem_cache_free(kvm_vcpu_cache
, vmx
);
4904 return ERR_PTR(err
);
4907 static void __init
vmx_check_processor_compat(void *rtn
)
4909 struct vmcs_config vmcs_conf
;
4912 if (setup_vmcs_config(&vmcs_conf
) < 0)
4914 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
4915 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
4916 smp_processor_id());
4921 static int get_ept_level(void)
4923 return VMX_EPT_DEFAULT_GAW
+ 1;
4926 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
4930 /* For VT-d and EPT combination
4931 * 1. MMIO: always map as UC
4933 * a. VT-d without snooping control feature: can't guarantee the
4934 * result, try to trust guest.
4935 * b. VT-d with snooping control feature: snooping control feature of
4936 * VT-d engine can guarantee the cache correctness. Just set it
4937 * to WB to keep consistent with host. So the same as item 3.
4938 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4939 * consistent with host MTRR
4942 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
4943 else if (vcpu
->kvm
->arch
.iommu_domain
&&
4944 !(vcpu
->kvm
->arch
.iommu_flags
& KVM_IOMMU_CACHE_COHERENCY
))
4945 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
4946 VMX_EPT_MT_EPTE_SHIFT
;
4948 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
4954 #define _ER(x) { EXIT_REASON_##x, #x }
4956 static const struct trace_print_flags vmx_exit_reasons_str
[] = {
4958 _ER(EXTERNAL_INTERRUPT
),
4960 _ER(PENDING_INTERRUPT
),
4980 _ER(IO_INSTRUCTION
),
4983 _ER(MWAIT_INSTRUCTION
),
4984 _ER(MONITOR_INSTRUCTION
),
4985 _ER(PAUSE_INSTRUCTION
),
4986 _ER(MCE_DURING_VMENTRY
),
4987 _ER(TPR_BELOW_THRESHOLD
),
4997 static int vmx_get_lpage_level(void)
4999 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
5000 return PT_DIRECTORY_LEVEL
;
5002 /* For shadow and EPT supported 1GB page */
5003 return PT_PDPE_LEVEL
;
5006 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
5008 struct kvm_cpuid_entry2
*best
;
5009 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5012 vmx
->rdtscp_enabled
= false;
5013 if (vmx_rdtscp_supported()) {
5014 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
5015 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
5016 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
5017 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
5018 vmx
->rdtscp_enabled
= true;
5020 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
5021 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
5028 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
5032 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
5033 struct x86_instruction_info
*info
,
5034 enum x86_intercept_stage stage
)
5036 return X86EMUL_CONTINUE
;
5039 static struct kvm_x86_ops vmx_x86_ops
= {
5040 .cpu_has_kvm_support
= cpu_has_kvm_support
,
5041 .disabled_by_bios
= vmx_disabled_by_bios
,
5042 .hardware_setup
= hardware_setup
,
5043 .hardware_unsetup
= hardware_unsetup
,
5044 .check_processor_compatibility
= vmx_check_processor_compat
,
5045 .hardware_enable
= hardware_enable
,
5046 .hardware_disable
= hardware_disable
,
5047 .cpu_has_accelerated_tpr
= report_flexpriority
,
5049 .vcpu_create
= vmx_create_vcpu
,
5050 .vcpu_free
= vmx_free_vcpu
,
5051 .vcpu_reset
= vmx_vcpu_reset
,
5053 .prepare_guest_switch
= vmx_save_host_state
,
5054 .vcpu_load
= vmx_vcpu_load
,
5055 .vcpu_put
= vmx_vcpu_put
,
5057 .set_guest_debug
= set_guest_debug
,
5058 .get_msr
= vmx_get_msr
,
5059 .set_msr
= vmx_set_msr
,
5060 .get_segment_base
= vmx_get_segment_base
,
5061 .get_segment
= vmx_get_segment
,
5062 .set_segment
= vmx_set_segment
,
5063 .get_cpl
= vmx_get_cpl
,
5064 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
5065 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
5066 .decache_cr3
= vmx_decache_cr3
,
5067 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
5068 .set_cr0
= vmx_set_cr0
,
5069 .set_cr3
= vmx_set_cr3
,
5070 .set_cr4
= vmx_set_cr4
,
5071 .set_efer
= vmx_set_efer
,
5072 .get_idt
= vmx_get_idt
,
5073 .set_idt
= vmx_set_idt
,
5074 .get_gdt
= vmx_get_gdt
,
5075 .set_gdt
= vmx_set_gdt
,
5076 .set_dr7
= vmx_set_dr7
,
5077 .cache_reg
= vmx_cache_reg
,
5078 .get_rflags
= vmx_get_rflags
,
5079 .set_rflags
= vmx_set_rflags
,
5080 .fpu_activate
= vmx_fpu_activate
,
5081 .fpu_deactivate
= vmx_fpu_deactivate
,
5083 .tlb_flush
= vmx_flush_tlb
,
5085 .run
= vmx_vcpu_run
,
5086 .handle_exit
= vmx_handle_exit
,
5087 .skip_emulated_instruction
= skip_emulated_instruction
,
5088 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
5089 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
5090 .patch_hypercall
= vmx_patch_hypercall
,
5091 .set_irq
= vmx_inject_irq
,
5092 .set_nmi
= vmx_inject_nmi
,
5093 .queue_exception
= vmx_queue_exception
,
5094 .cancel_injection
= vmx_cancel_injection
,
5095 .interrupt_allowed
= vmx_interrupt_allowed
,
5096 .nmi_allowed
= vmx_nmi_allowed
,
5097 .get_nmi_mask
= vmx_get_nmi_mask
,
5098 .set_nmi_mask
= vmx_set_nmi_mask
,
5099 .enable_nmi_window
= enable_nmi_window
,
5100 .enable_irq_window
= enable_irq_window
,
5101 .update_cr8_intercept
= update_cr8_intercept
,
5103 .set_tss_addr
= vmx_set_tss_addr
,
5104 .get_tdp_level
= get_ept_level
,
5105 .get_mt_mask
= vmx_get_mt_mask
,
5107 .get_exit_info
= vmx_get_exit_info
,
5108 .exit_reasons_str
= vmx_exit_reasons_str
,
5110 .get_lpage_level
= vmx_get_lpage_level
,
5112 .cpuid_update
= vmx_cpuid_update
,
5114 .rdtscp_supported
= vmx_rdtscp_supported
,
5116 .set_supported_cpuid
= vmx_set_supported_cpuid
,
5118 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
5120 .set_tsc_khz
= vmx_set_tsc_khz
,
5121 .write_tsc_offset
= vmx_write_tsc_offset
,
5122 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
5123 .compute_tsc_offset
= vmx_compute_tsc_offset
,
5125 .set_tdp_cr3
= vmx_set_cr3
,
5127 .check_intercept
= vmx_check_intercept
,
5130 static int __init
vmx_init(void)
5134 rdmsrl_safe(MSR_EFER
, &host_efer
);
5136 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
5137 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
5139 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5140 if (!vmx_io_bitmap_a
)
5143 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5144 if (!vmx_io_bitmap_b
) {
5149 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5150 if (!vmx_msr_bitmap_legacy
) {
5155 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
5156 if (!vmx_msr_bitmap_longmode
) {
5162 * Allow direct access to the PC debug port (it is often used for I/O
5163 * delays, but the vmexits simply slow things down).
5165 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
5166 clear_bit(0x80, vmx_io_bitmap_a
);
5168 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
5170 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
5171 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
5173 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
5175 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
5176 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
5180 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
5181 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
5182 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
5183 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
5184 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
5185 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
5188 bypass_guest_pf
= 0;
5189 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
5190 VMX_EPT_EXECUTABLE_MASK
);
5195 if (bypass_guest_pf
)
5196 kvm_mmu_set_nonpresent_ptes(~0xffeull
, 0ull);
5201 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5203 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5205 free_page((unsigned long)vmx_io_bitmap_b
);
5207 free_page((unsigned long)vmx_io_bitmap_a
);
5211 static void __exit
vmx_exit(void)
5213 free_page((unsigned long)vmx_msr_bitmap_legacy
);
5214 free_page((unsigned long)vmx_msr_bitmap_longmode
);
5215 free_page((unsigned long)vmx_io_bitmap_b
);
5216 free_page((unsigned long)vmx_io_bitmap_a
);
5221 module_init(vmx_init
)
5222 module_exit(vmx_exit
)