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KVM: Timer event should not unconditionally unhalt vcpu.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35
36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
37
38 MODULE_AUTHOR("Qumranet");
39 MODULE_LICENSE("GPL");
40
41 static int __read_mostly bypass_guest_pf = 1;
42 module_param(bypass_guest_pf, bool, S_IRUGO);
43
44 static int __read_mostly enable_vpid = 1;
45 module_param_named(vpid, enable_vpid, bool, 0444);
46
47 static int __read_mostly flexpriority_enabled = 1;
48 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
49
50 static int __read_mostly enable_ept = 1;
51 module_param_named(ept, enable_ept, bool, S_IRUGO);
52
53 static int __read_mostly emulate_invalid_guest_state = 0;
54 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
55
56 struct vmcs {
57 u32 revision_id;
58 u32 abort;
59 char data[0];
60 };
61
62 struct vcpu_vmx {
63 struct kvm_vcpu vcpu;
64 struct list_head local_vcpus_link;
65 unsigned long host_rsp;
66 int launched;
67 u8 fail;
68 u32 idt_vectoring_info;
69 struct kvm_msr_entry *guest_msrs;
70 struct kvm_msr_entry *host_msrs;
71 int nmsrs;
72 int save_nmsrs;
73 int msr_offset_efer;
74 #ifdef CONFIG_X86_64
75 int msr_offset_kernel_gs_base;
76 #endif
77 struct vmcs *vmcs;
78 struct {
79 int loaded;
80 u16 fs_sel, gs_sel, ldt_sel;
81 int gs_ldt_reload_needed;
82 int fs_reload_needed;
83 int guest_efer_loaded;
84 } host_state;
85 struct {
86 struct {
87 bool pending;
88 u8 vector;
89 unsigned rip;
90 } irq;
91 } rmode;
92 int vpid;
93 bool emulation_required;
94 enum emulation_result invalid_state_emulation_result;
95
96 /* Support for vnmi-less CPUs */
97 int soft_vnmi_blocked;
98 ktime_t entry_time;
99 s64 vnmi_blocked_time;
100 };
101
102 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
103 {
104 return container_of(vcpu, struct vcpu_vmx, vcpu);
105 }
106
107 static int init_rmode(struct kvm *kvm);
108 static u64 construct_eptp(unsigned long root_hpa);
109
110 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
111 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
112 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
113
114 static unsigned long *vmx_io_bitmap_a;
115 static unsigned long *vmx_io_bitmap_b;
116 static unsigned long *vmx_msr_bitmap_legacy;
117 static unsigned long *vmx_msr_bitmap_longmode;
118
119 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
120 static DEFINE_SPINLOCK(vmx_vpid_lock);
121
122 static struct vmcs_config {
123 int size;
124 int order;
125 u32 revision_id;
126 u32 pin_based_exec_ctrl;
127 u32 cpu_based_exec_ctrl;
128 u32 cpu_based_2nd_exec_ctrl;
129 u32 vmexit_ctrl;
130 u32 vmentry_ctrl;
131 } vmcs_config;
132
133 static struct vmx_capability {
134 u32 ept;
135 u32 vpid;
136 } vmx_capability;
137
138 #define VMX_SEGMENT_FIELD(seg) \
139 [VCPU_SREG_##seg] = { \
140 .selector = GUEST_##seg##_SELECTOR, \
141 .base = GUEST_##seg##_BASE, \
142 .limit = GUEST_##seg##_LIMIT, \
143 .ar_bytes = GUEST_##seg##_AR_BYTES, \
144 }
145
146 static struct kvm_vmx_segment_field {
147 unsigned selector;
148 unsigned base;
149 unsigned limit;
150 unsigned ar_bytes;
151 } kvm_vmx_segment_fields[] = {
152 VMX_SEGMENT_FIELD(CS),
153 VMX_SEGMENT_FIELD(DS),
154 VMX_SEGMENT_FIELD(ES),
155 VMX_SEGMENT_FIELD(FS),
156 VMX_SEGMENT_FIELD(GS),
157 VMX_SEGMENT_FIELD(SS),
158 VMX_SEGMENT_FIELD(TR),
159 VMX_SEGMENT_FIELD(LDTR),
160 };
161
162 /*
163 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
164 * away by decrementing the array size.
165 */
166 static const u32 vmx_msr_index[] = {
167 #ifdef CONFIG_X86_64
168 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
169 #endif
170 MSR_EFER, MSR_K6_STAR,
171 };
172 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
173
174 static void load_msrs(struct kvm_msr_entry *e, int n)
175 {
176 int i;
177
178 for (i = 0; i < n; ++i)
179 wrmsrl(e[i].index, e[i].data);
180 }
181
182 static void save_msrs(struct kvm_msr_entry *e, int n)
183 {
184 int i;
185
186 for (i = 0; i < n; ++i)
187 rdmsrl(e[i].index, e[i].data);
188 }
189
190 static inline int is_page_fault(u32 intr_info)
191 {
192 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
193 INTR_INFO_VALID_MASK)) ==
194 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
195 }
196
197 static inline int is_no_device(u32 intr_info)
198 {
199 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
200 INTR_INFO_VALID_MASK)) ==
201 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
202 }
203
204 static inline int is_invalid_opcode(u32 intr_info)
205 {
206 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
207 INTR_INFO_VALID_MASK)) ==
208 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
209 }
210
211 static inline int is_external_interrupt(u32 intr_info)
212 {
213 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
214 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
215 }
216
217 static inline int cpu_has_vmx_msr_bitmap(void)
218 {
219 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS);
220 }
221
222 static inline int cpu_has_vmx_tpr_shadow(void)
223 {
224 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
225 }
226
227 static inline int vm_need_tpr_shadow(struct kvm *kvm)
228 {
229 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
230 }
231
232 static inline int cpu_has_secondary_exec_ctrls(void)
233 {
234 return (vmcs_config.cpu_based_exec_ctrl &
235 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
236 }
237
238 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
239 {
240 return flexpriority_enabled
241 && (vmcs_config.cpu_based_2nd_exec_ctrl &
242 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
243 }
244
245 static inline int cpu_has_vmx_invept_individual_addr(void)
246 {
247 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT));
248 }
249
250 static inline int cpu_has_vmx_invept_context(void)
251 {
252 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT));
253 }
254
255 static inline int cpu_has_vmx_invept_global(void)
256 {
257 return (!!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT));
258 }
259
260 static inline int cpu_has_vmx_ept(void)
261 {
262 return (vmcs_config.cpu_based_2nd_exec_ctrl &
263 SECONDARY_EXEC_ENABLE_EPT);
264 }
265
266 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
267 {
268 return ((cpu_has_vmx_virtualize_apic_accesses()) &&
269 (irqchip_in_kernel(kvm)));
270 }
271
272 static inline int cpu_has_vmx_vpid(void)
273 {
274 return (vmcs_config.cpu_based_2nd_exec_ctrl &
275 SECONDARY_EXEC_ENABLE_VPID);
276 }
277
278 static inline int cpu_has_virtual_nmis(void)
279 {
280 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
281 }
282
283 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
284 {
285 int i;
286
287 for (i = 0; i < vmx->nmsrs; ++i)
288 if (vmx->guest_msrs[i].index == msr)
289 return i;
290 return -1;
291 }
292
293 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
294 {
295 struct {
296 u64 vpid : 16;
297 u64 rsvd : 48;
298 u64 gva;
299 } operand = { vpid, 0, gva };
300
301 asm volatile (__ex(ASM_VMX_INVVPID)
302 /* CF==1 or ZF==1 --> rc = -1 */
303 "; ja 1f ; ud2 ; 1:"
304 : : "a"(&operand), "c"(ext) : "cc", "memory");
305 }
306
307 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
308 {
309 struct {
310 u64 eptp, gpa;
311 } operand = {eptp, gpa};
312
313 asm volatile (__ex(ASM_VMX_INVEPT)
314 /* CF==1 or ZF==1 --> rc = -1 */
315 "; ja 1f ; ud2 ; 1:\n"
316 : : "a" (&operand), "c" (ext) : "cc", "memory");
317 }
318
319 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
320 {
321 int i;
322
323 i = __find_msr_index(vmx, msr);
324 if (i >= 0)
325 return &vmx->guest_msrs[i];
326 return NULL;
327 }
328
329 static void vmcs_clear(struct vmcs *vmcs)
330 {
331 u64 phys_addr = __pa(vmcs);
332 u8 error;
333
334 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
335 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
336 : "cc", "memory");
337 if (error)
338 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
339 vmcs, phys_addr);
340 }
341
342 static void __vcpu_clear(void *arg)
343 {
344 struct vcpu_vmx *vmx = arg;
345 int cpu = raw_smp_processor_id();
346
347 if (vmx->vcpu.cpu == cpu)
348 vmcs_clear(vmx->vmcs);
349 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
350 per_cpu(current_vmcs, cpu) = NULL;
351 rdtscll(vmx->vcpu.arch.host_tsc);
352 list_del(&vmx->local_vcpus_link);
353 vmx->vcpu.cpu = -1;
354 vmx->launched = 0;
355 }
356
357 static void vcpu_clear(struct vcpu_vmx *vmx)
358 {
359 if (vmx->vcpu.cpu == -1)
360 return;
361 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
362 }
363
364 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
365 {
366 if (vmx->vpid == 0)
367 return;
368
369 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
370 }
371
372 static inline void ept_sync_global(void)
373 {
374 if (cpu_has_vmx_invept_global())
375 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
376 }
377
378 static inline void ept_sync_context(u64 eptp)
379 {
380 if (enable_ept) {
381 if (cpu_has_vmx_invept_context())
382 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
383 else
384 ept_sync_global();
385 }
386 }
387
388 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
389 {
390 if (enable_ept) {
391 if (cpu_has_vmx_invept_individual_addr())
392 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
393 eptp, gpa);
394 else
395 ept_sync_context(eptp);
396 }
397 }
398
399 static unsigned long vmcs_readl(unsigned long field)
400 {
401 unsigned long value;
402
403 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
404 : "=a"(value) : "d"(field) : "cc");
405 return value;
406 }
407
408 static u16 vmcs_read16(unsigned long field)
409 {
410 return vmcs_readl(field);
411 }
412
413 static u32 vmcs_read32(unsigned long field)
414 {
415 return vmcs_readl(field);
416 }
417
418 static u64 vmcs_read64(unsigned long field)
419 {
420 #ifdef CONFIG_X86_64
421 return vmcs_readl(field);
422 #else
423 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
424 #endif
425 }
426
427 static noinline void vmwrite_error(unsigned long field, unsigned long value)
428 {
429 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
430 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
431 dump_stack();
432 }
433
434 static void vmcs_writel(unsigned long field, unsigned long value)
435 {
436 u8 error;
437
438 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
439 : "=q"(error) : "a"(value), "d"(field) : "cc");
440 if (unlikely(error))
441 vmwrite_error(field, value);
442 }
443
444 static void vmcs_write16(unsigned long field, u16 value)
445 {
446 vmcs_writel(field, value);
447 }
448
449 static void vmcs_write32(unsigned long field, u32 value)
450 {
451 vmcs_writel(field, value);
452 }
453
454 static void vmcs_write64(unsigned long field, u64 value)
455 {
456 vmcs_writel(field, value);
457 #ifndef CONFIG_X86_64
458 asm volatile ("");
459 vmcs_writel(field+1, value >> 32);
460 #endif
461 }
462
463 static void vmcs_clear_bits(unsigned long field, u32 mask)
464 {
465 vmcs_writel(field, vmcs_readl(field) & ~mask);
466 }
467
468 static void vmcs_set_bits(unsigned long field, u32 mask)
469 {
470 vmcs_writel(field, vmcs_readl(field) | mask);
471 }
472
473 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
474 {
475 u32 eb;
476
477 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
478 if (!vcpu->fpu_active)
479 eb |= 1u << NM_VECTOR;
480 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
481 if (vcpu->guest_debug &
482 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
483 eb |= 1u << DB_VECTOR;
484 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
485 eb |= 1u << BP_VECTOR;
486 }
487 if (vcpu->arch.rmode.active)
488 eb = ~0;
489 if (enable_ept)
490 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
491 vmcs_write32(EXCEPTION_BITMAP, eb);
492 }
493
494 static void reload_tss(void)
495 {
496 /*
497 * VT restores TR but not its size. Useless.
498 */
499 struct descriptor_table gdt;
500 struct desc_struct *descs;
501
502 kvm_get_gdt(&gdt);
503 descs = (void *)gdt.base;
504 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
505 load_TR_desc();
506 }
507
508 static void load_transition_efer(struct vcpu_vmx *vmx)
509 {
510 int efer_offset = vmx->msr_offset_efer;
511 u64 host_efer = vmx->host_msrs[efer_offset].data;
512 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
513 u64 ignore_bits;
514
515 if (efer_offset < 0)
516 return;
517 /*
518 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
519 * outside long mode
520 */
521 ignore_bits = EFER_NX | EFER_SCE;
522 #ifdef CONFIG_X86_64
523 ignore_bits |= EFER_LMA | EFER_LME;
524 /* SCE is meaningful only in long mode on Intel */
525 if (guest_efer & EFER_LMA)
526 ignore_bits &= ~(u64)EFER_SCE;
527 #endif
528 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
529 return;
530
531 vmx->host_state.guest_efer_loaded = 1;
532 guest_efer &= ~ignore_bits;
533 guest_efer |= host_efer & ignore_bits;
534 wrmsrl(MSR_EFER, guest_efer);
535 vmx->vcpu.stat.efer_reload++;
536 }
537
538 static void reload_host_efer(struct vcpu_vmx *vmx)
539 {
540 if (vmx->host_state.guest_efer_loaded) {
541 vmx->host_state.guest_efer_loaded = 0;
542 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
543 }
544 }
545
546 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
547 {
548 struct vcpu_vmx *vmx = to_vmx(vcpu);
549
550 if (vmx->host_state.loaded)
551 return;
552
553 vmx->host_state.loaded = 1;
554 /*
555 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
556 * allow segment selectors with cpl > 0 or ti == 1.
557 */
558 vmx->host_state.ldt_sel = kvm_read_ldt();
559 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
560 vmx->host_state.fs_sel = kvm_read_fs();
561 if (!(vmx->host_state.fs_sel & 7)) {
562 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
563 vmx->host_state.fs_reload_needed = 0;
564 } else {
565 vmcs_write16(HOST_FS_SELECTOR, 0);
566 vmx->host_state.fs_reload_needed = 1;
567 }
568 vmx->host_state.gs_sel = kvm_read_gs();
569 if (!(vmx->host_state.gs_sel & 7))
570 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
571 else {
572 vmcs_write16(HOST_GS_SELECTOR, 0);
573 vmx->host_state.gs_ldt_reload_needed = 1;
574 }
575
576 #ifdef CONFIG_X86_64
577 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
578 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
579 #else
580 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
581 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
582 #endif
583
584 #ifdef CONFIG_X86_64
585 if (is_long_mode(&vmx->vcpu))
586 save_msrs(vmx->host_msrs +
587 vmx->msr_offset_kernel_gs_base, 1);
588
589 #endif
590 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
591 load_transition_efer(vmx);
592 }
593
594 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
595 {
596 unsigned long flags;
597
598 if (!vmx->host_state.loaded)
599 return;
600
601 ++vmx->vcpu.stat.host_state_reload;
602 vmx->host_state.loaded = 0;
603 if (vmx->host_state.fs_reload_needed)
604 kvm_load_fs(vmx->host_state.fs_sel);
605 if (vmx->host_state.gs_ldt_reload_needed) {
606 kvm_load_ldt(vmx->host_state.ldt_sel);
607 /*
608 * If we have to reload gs, we must take care to
609 * preserve our gs base.
610 */
611 local_irq_save(flags);
612 kvm_load_gs(vmx->host_state.gs_sel);
613 #ifdef CONFIG_X86_64
614 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
615 #endif
616 local_irq_restore(flags);
617 }
618 reload_tss();
619 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
620 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
621 reload_host_efer(vmx);
622 }
623
624 static void vmx_load_host_state(struct vcpu_vmx *vmx)
625 {
626 preempt_disable();
627 __vmx_load_host_state(vmx);
628 preempt_enable();
629 }
630
631 /*
632 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
633 * vcpu mutex is already taken.
634 */
635 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
636 {
637 struct vcpu_vmx *vmx = to_vmx(vcpu);
638 u64 phys_addr = __pa(vmx->vmcs);
639 u64 tsc_this, delta, new_offset;
640
641 if (vcpu->cpu != cpu) {
642 vcpu_clear(vmx);
643 kvm_migrate_timers(vcpu);
644 vpid_sync_vcpu_all(vmx);
645 local_irq_disable();
646 list_add(&vmx->local_vcpus_link,
647 &per_cpu(vcpus_on_cpu, cpu));
648 local_irq_enable();
649 }
650
651 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
652 u8 error;
653
654 per_cpu(current_vmcs, cpu) = vmx->vmcs;
655 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
656 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
657 : "cc");
658 if (error)
659 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
660 vmx->vmcs, phys_addr);
661 }
662
663 if (vcpu->cpu != cpu) {
664 struct descriptor_table dt;
665 unsigned long sysenter_esp;
666
667 vcpu->cpu = cpu;
668 /*
669 * Linux uses per-cpu TSS and GDT, so set these when switching
670 * processors.
671 */
672 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
673 kvm_get_gdt(&dt);
674 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
675
676 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
677 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
678
679 /*
680 * Make sure the time stamp counter is monotonous.
681 */
682 rdtscll(tsc_this);
683 if (tsc_this < vcpu->arch.host_tsc) {
684 delta = vcpu->arch.host_tsc - tsc_this;
685 new_offset = vmcs_read64(TSC_OFFSET) + delta;
686 vmcs_write64(TSC_OFFSET, new_offset);
687 }
688 }
689 }
690
691 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
692 {
693 __vmx_load_host_state(to_vmx(vcpu));
694 }
695
696 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
697 {
698 if (vcpu->fpu_active)
699 return;
700 vcpu->fpu_active = 1;
701 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
702 if (vcpu->arch.cr0 & X86_CR0_TS)
703 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
704 update_exception_bitmap(vcpu);
705 }
706
707 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
708 {
709 if (!vcpu->fpu_active)
710 return;
711 vcpu->fpu_active = 0;
712 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
713 update_exception_bitmap(vcpu);
714 }
715
716 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
717 {
718 return vmcs_readl(GUEST_RFLAGS);
719 }
720
721 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
722 {
723 if (vcpu->arch.rmode.active)
724 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
725 vmcs_writel(GUEST_RFLAGS, rflags);
726 }
727
728 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
729 {
730 unsigned long rip;
731 u32 interruptibility;
732
733 rip = kvm_rip_read(vcpu);
734 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
735 kvm_rip_write(vcpu, rip);
736
737 /*
738 * We emulated an instruction, so temporary interrupt blocking
739 * should be removed, if set.
740 */
741 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
742 if (interruptibility & 3)
743 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
744 interruptibility & ~3);
745 vcpu->arch.interrupt_window_open = 1;
746 }
747
748 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
749 bool has_error_code, u32 error_code)
750 {
751 struct vcpu_vmx *vmx = to_vmx(vcpu);
752 u32 intr_info = nr | INTR_INFO_VALID_MASK;
753
754 if (has_error_code) {
755 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
756 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
757 }
758
759 if (vcpu->arch.rmode.active) {
760 vmx->rmode.irq.pending = true;
761 vmx->rmode.irq.vector = nr;
762 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
763 if (nr == BP_VECTOR || nr == OF_VECTOR)
764 vmx->rmode.irq.rip++;
765 intr_info |= INTR_TYPE_SOFT_INTR;
766 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
767 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
768 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
769 return;
770 }
771
772 if (nr == BP_VECTOR || nr == OF_VECTOR) {
773 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
774 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
775 } else
776 intr_info |= INTR_TYPE_HARD_EXCEPTION;
777
778 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
779 }
780
781 static bool vmx_exception_injected(struct kvm_vcpu *vcpu)
782 {
783 return false;
784 }
785
786 /*
787 * Swap MSR entry in host/guest MSR entry array.
788 */
789 #ifdef CONFIG_X86_64
790 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
791 {
792 struct kvm_msr_entry tmp;
793
794 tmp = vmx->guest_msrs[to];
795 vmx->guest_msrs[to] = vmx->guest_msrs[from];
796 vmx->guest_msrs[from] = tmp;
797 tmp = vmx->host_msrs[to];
798 vmx->host_msrs[to] = vmx->host_msrs[from];
799 vmx->host_msrs[from] = tmp;
800 }
801 #endif
802
803 /*
804 * Set up the vmcs to automatically save and restore system
805 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
806 * mode, as fiddling with msrs is very expensive.
807 */
808 static void setup_msrs(struct vcpu_vmx *vmx)
809 {
810 int save_nmsrs;
811 unsigned long *msr_bitmap;
812
813 vmx_load_host_state(vmx);
814 save_nmsrs = 0;
815 #ifdef CONFIG_X86_64
816 if (is_long_mode(&vmx->vcpu)) {
817 int index;
818
819 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
820 if (index >= 0)
821 move_msr_up(vmx, index, save_nmsrs++);
822 index = __find_msr_index(vmx, MSR_LSTAR);
823 if (index >= 0)
824 move_msr_up(vmx, index, save_nmsrs++);
825 index = __find_msr_index(vmx, MSR_CSTAR);
826 if (index >= 0)
827 move_msr_up(vmx, index, save_nmsrs++);
828 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
829 if (index >= 0)
830 move_msr_up(vmx, index, save_nmsrs++);
831 /*
832 * MSR_K6_STAR is only needed on long mode guests, and only
833 * if efer.sce is enabled.
834 */
835 index = __find_msr_index(vmx, MSR_K6_STAR);
836 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
837 move_msr_up(vmx, index, save_nmsrs++);
838 }
839 #endif
840 vmx->save_nmsrs = save_nmsrs;
841
842 #ifdef CONFIG_X86_64
843 vmx->msr_offset_kernel_gs_base =
844 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
845 #endif
846 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
847
848 if (cpu_has_vmx_msr_bitmap()) {
849 if (is_long_mode(&vmx->vcpu))
850 msr_bitmap = vmx_msr_bitmap_longmode;
851 else
852 msr_bitmap = vmx_msr_bitmap_legacy;
853
854 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
855 }
856 }
857
858 /*
859 * reads and returns guest's timestamp counter "register"
860 * guest_tsc = host_tsc + tsc_offset -- 21.3
861 */
862 static u64 guest_read_tsc(void)
863 {
864 u64 host_tsc, tsc_offset;
865
866 rdtscll(host_tsc);
867 tsc_offset = vmcs_read64(TSC_OFFSET);
868 return host_tsc + tsc_offset;
869 }
870
871 /*
872 * writes 'guest_tsc' into guest's timestamp counter "register"
873 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
874 */
875 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
876 {
877 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
878 }
879
880 /*
881 * Reads an msr value (of 'msr_index') into 'pdata'.
882 * Returns 0 on success, non-0 otherwise.
883 * Assumes vcpu_load() was already called.
884 */
885 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
886 {
887 u64 data;
888 struct kvm_msr_entry *msr;
889
890 if (!pdata) {
891 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
892 return -EINVAL;
893 }
894
895 switch (msr_index) {
896 #ifdef CONFIG_X86_64
897 case MSR_FS_BASE:
898 data = vmcs_readl(GUEST_FS_BASE);
899 break;
900 case MSR_GS_BASE:
901 data = vmcs_readl(GUEST_GS_BASE);
902 break;
903 case MSR_EFER:
904 return kvm_get_msr_common(vcpu, msr_index, pdata);
905 #endif
906 case MSR_IA32_TIME_STAMP_COUNTER:
907 data = guest_read_tsc();
908 break;
909 case MSR_IA32_SYSENTER_CS:
910 data = vmcs_read32(GUEST_SYSENTER_CS);
911 break;
912 case MSR_IA32_SYSENTER_EIP:
913 data = vmcs_readl(GUEST_SYSENTER_EIP);
914 break;
915 case MSR_IA32_SYSENTER_ESP:
916 data = vmcs_readl(GUEST_SYSENTER_ESP);
917 break;
918 default:
919 vmx_load_host_state(to_vmx(vcpu));
920 msr = find_msr_entry(to_vmx(vcpu), msr_index);
921 if (msr) {
922 data = msr->data;
923 break;
924 }
925 return kvm_get_msr_common(vcpu, msr_index, pdata);
926 }
927
928 *pdata = data;
929 return 0;
930 }
931
932 /*
933 * Writes msr value into into the appropriate "register".
934 * Returns 0 on success, non-0 otherwise.
935 * Assumes vcpu_load() was already called.
936 */
937 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
938 {
939 struct vcpu_vmx *vmx = to_vmx(vcpu);
940 struct kvm_msr_entry *msr;
941 u64 host_tsc;
942 int ret = 0;
943
944 switch (msr_index) {
945 case MSR_EFER:
946 vmx_load_host_state(vmx);
947 ret = kvm_set_msr_common(vcpu, msr_index, data);
948 break;
949 #ifdef CONFIG_X86_64
950 case MSR_FS_BASE:
951 vmcs_writel(GUEST_FS_BASE, data);
952 break;
953 case MSR_GS_BASE:
954 vmcs_writel(GUEST_GS_BASE, data);
955 break;
956 #endif
957 case MSR_IA32_SYSENTER_CS:
958 vmcs_write32(GUEST_SYSENTER_CS, data);
959 break;
960 case MSR_IA32_SYSENTER_EIP:
961 vmcs_writel(GUEST_SYSENTER_EIP, data);
962 break;
963 case MSR_IA32_SYSENTER_ESP:
964 vmcs_writel(GUEST_SYSENTER_ESP, data);
965 break;
966 case MSR_IA32_TIME_STAMP_COUNTER:
967 rdtscll(host_tsc);
968 guest_write_tsc(data, host_tsc);
969 break;
970 case MSR_P6_PERFCTR0:
971 case MSR_P6_PERFCTR1:
972 case MSR_P6_EVNTSEL0:
973 case MSR_P6_EVNTSEL1:
974 /*
975 * Just discard all writes to the performance counters; this
976 * should keep both older linux and windows 64-bit guests
977 * happy
978 */
979 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
980
981 break;
982 case MSR_IA32_CR_PAT:
983 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
984 vmcs_write64(GUEST_IA32_PAT, data);
985 vcpu->arch.pat = data;
986 break;
987 }
988 /* Otherwise falls through to kvm_set_msr_common */
989 default:
990 vmx_load_host_state(vmx);
991 msr = find_msr_entry(vmx, msr_index);
992 if (msr) {
993 msr->data = data;
994 break;
995 }
996 ret = kvm_set_msr_common(vcpu, msr_index, data);
997 }
998
999 return ret;
1000 }
1001
1002 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1003 {
1004 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1005 switch (reg) {
1006 case VCPU_REGS_RSP:
1007 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1008 break;
1009 case VCPU_REGS_RIP:
1010 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1011 break;
1012 default:
1013 break;
1014 }
1015 }
1016
1017 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1018 {
1019 int old_debug = vcpu->guest_debug;
1020 unsigned long flags;
1021
1022 vcpu->guest_debug = dbg->control;
1023 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1024 vcpu->guest_debug = 0;
1025
1026 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1027 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1028 else
1029 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1030
1031 flags = vmcs_readl(GUEST_RFLAGS);
1032 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1033 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1034 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1035 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1036 vmcs_writel(GUEST_RFLAGS, flags);
1037
1038 update_exception_bitmap(vcpu);
1039
1040 return 0;
1041 }
1042
1043 static int vmx_get_irq(struct kvm_vcpu *vcpu)
1044 {
1045 if (!vcpu->arch.interrupt.pending)
1046 return -1;
1047 return vcpu->arch.interrupt.nr;
1048 }
1049
1050 static __init int cpu_has_kvm_support(void)
1051 {
1052 return cpu_has_vmx();
1053 }
1054
1055 static __init int vmx_disabled_by_bios(void)
1056 {
1057 u64 msr;
1058
1059 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1060 return (msr & (FEATURE_CONTROL_LOCKED |
1061 FEATURE_CONTROL_VMXON_ENABLED))
1062 == FEATURE_CONTROL_LOCKED;
1063 /* locked but not enabled */
1064 }
1065
1066 static void hardware_enable(void *garbage)
1067 {
1068 int cpu = raw_smp_processor_id();
1069 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1070 u64 old;
1071
1072 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1073 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1074 if ((old & (FEATURE_CONTROL_LOCKED |
1075 FEATURE_CONTROL_VMXON_ENABLED))
1076 != (FEATURE_CONTROL_LOCKED |
1077 FEATURE_CONTROL_VMXON_ENABLED))
1078 /* enable and lock */
1079 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1080 FEATURE_CONTROL_LOCKED |
1081 FEATURE_CONTROL_VMXON_ENABLED);
1082 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1083 asm volatile (ASM_VMX_VMXON_RAX
1084 : : "a"(&phys_addr), "m"(phys_addr)
1085 : "memory", "cc");
1086 }
1087
1088 static void vmclear_local_vcpus(void)
1089 {
1090 int cpu = raw_smp_processor_id();
1091 struct vcpu_vmx *vmx, *n;
1092
1093 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1094 local_vcpus_link)
1095 __vcpu_clear(vmx);
1096 }
1097
1098
1099 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1100 * tricks.
1101 */
1102 static void kvm_cpu_vmxoff(void)
1103 {
1104 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1105 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1106 }
1107
1108 static void hardware_disable(void *garbage)
1109 {
1110 vmclear_local_vcpus();
1111 kvm_cpu_vmxoff();
1112 }
1113
1114 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1115 u32 msr, u32 *result)
1116 {
1117 u32 vmx_msr_low, vmx_msr_high;
1118 u32 ctl = ctl_min | ctl_opt;
1119
1120 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1121
1122 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1123 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1124
1125 /* Ensure minimum (required) set of control bits are supported. */
1126 if (ctl_min & ~ctl)
1127 return -EIO;
1128
1129 *result = ctl;
1130 return 0;
1131 }
1132
1133 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1134 {
1135 u32 vmx_msr_low, vmx_msr_high;
1136 u32 min, opt, min2, opt2;
1137 u32 _pin_based_exec_control = 0;
1138 u32 _cpu_based_exec_control = 0;
1139 u32 _cpu_based_2nd_exec_control = 0;
1140 u32 _vmexit_control = 0;
1141 u32 _vmentry_control = 0;
1142
1143 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1144 opt = PIN_BASED_VIRTUAL_NMIS;
1145 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1146 &_pin_based_exec_control) < 0)
1147 return -EIO;
1148
1149 min = CPU_BASED_HLT_EXITING |
1150 #ifdef CONFIG_X86_64
1151 CPU_BASED_CR8_LOAD_EXITING |
1152 CPU_BASED_CR8_STORE_EXITING |
1153 #endif
1154 CPU_BASED_CR3_LOAD_EXITING |
1155 CPU_BASED_CR3_STORE_EXITING |
1156 CPU_BASED_USE_IO_BITMAPS |
1157 CPU_BASED_MOV_DR_EXITING |
1158 CPU_BASED_USE_TSC_OFFSETING |
1159 CPU_BASED_INVLPG_EXITING;
1160 opt = CPU_BASED_TPR_SHADOW |
1161 CPU_BASED_USE_MSR_BITMAPS |
1162 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1163 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1164 &_cpu_based_exec_control) < 0)
1165 return -EIO;
1166 #ifdef CONFIG_X86_64
1167 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1168 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1169 ~CPU_BASED_CR8_STORE_EXITING;
1170 #endif
1171 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1172 min2 = 0;
1173 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1174 SECONDARY_EXEC_WBINVD_EXITING |
1175 SECONDARY_EXEC_ENABLE_VPID |
1176 SECONDARY_EXEC_ENABLE_EPT;
1177 if (adjust_vmx_controls(min2, opt2,
1178 MSR_IA32_VMX_PROCBASED_CTLS2,
1179 &_cpu_based_2nd_exec_control) < 0)
1180 return -EIO;
1181 }
1182 #ifndef CONFIG_X86_64
1183 if (!(_cpu_based_2nd_exec_control &
1184 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1185 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1186 #endif
1187 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1188 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1189 enabled */
1190 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1191 CPU_BASED_CR3_STORE_EXITING |
1192 CPU_BASED_INVLPG_EXITING);
1193 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1194 &_cpu_based_exec_control) < 0)
1195 return -EIO;
1196 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1197 vmx_capability.ept, vmx_capability.vpid);
1198 }
1199
1200 if (!cpu_has_vmx_vpid())
1201 enable_vpid = 0;
1202
1203 if (!cpu_has_vmx_ept())
1204 enable_ept = 0;
1205
1206 min = 0;
1207 #ifdef CONFIG_X86_64
1208 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1209 #endif
1210 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1211 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1212 &_vmexit_control) < 0)
1213 return -EIO;
1214
1215 min = 0;
1216 opt = VM_ENTRY_LOAD_IA32_PAT;
1217 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1218 &_vmentry_control) < 0)
1219 return -EIO;
1220
1221 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1222
1223 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1224 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1225 return -EIO;
1226
1227 #ifdef CONFIG_X86_64
1228 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1229 if (vmx_msr_high & (1u<<16))
1230 return -EIO;
1231 #endif
1232
1233 /* Require Write-Back (WB) memory type for VMCS accesses. */
1234 if (((vmx_msr_high >> 18) & 15) != 6)
1235 return -EIO;
1236
1237 vmcs_conf->size = vmx_msr_high & 0x1fff;
1238 vmcs_conf->order = get_order(vmcs_config.size);
1239 vmcs_conf->revision_id = vmx_msr_low;
1240
1241 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1242 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1243 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1244 vmcs_conf->vmexit_ctrl = _vmexit_control;
1245 vmcs_conf->vmentry_ctrl = _vmentry_control;
1246
1247 return 0;
1248 }
1249
1250 static struct vmcs *alloc_vmcs_cpu(int cpu)
1251 {
1252 int node = cpu_to_node(cpu);
1253 struct page *pages;
1254 struct vmcs *vmcs;
1255
1256 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1257 if (!pages)
1258 return NULL;
1259 vmcs = page_address(pages);
1260 memset(vmcs, 0, vmcs_config.size);
1261 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1262 return vmcs;
1263 }
1264
1265 static struct vmcs *alloc_vmcs(void)
1266 {
1267 return alloc_vmcs_cpu(raw_smp_processor_id());
1268 }
1269
1270 static void free_vmcs(struct vmcs *vmcs)
1271 {
1272 free_pages((unsigned long)vmcs, vmcs_config.order);
1273 }
1274
1275 static void free_kvm_area(void)
1276 {
1277 int cpu;
1278
1279 for_each_online_cpu(cpu)
1280 free_vmcs(per_cpu(vmxarea, cpu));
1281 }
1282
1283 static __init int alloc_kvm_area(void)
1284 {
1285 int cpu;
1286
1287 for_each_online_cpu(cpu) {
1288 struct vmcs *vmcs;
1289
1290 vmcs = alloc_vmcs_cpu(cpu);
1291 if (!vmcs) {
1292 free_kvm_area();
1293 return -ENOMEM;
1294 }
1295
1296 per_cpu(vmxarea, cpu) = vmcs;
1297 }
1298 return 0;
1299 }
1300
1301 static __init int hardware_setup(void)
1302 {
1303 if (setup_vmcs_config(&vmcs_config) < 0)
1304 return -EIO;
1305
1306 if (boot_cpu_has(X86_FEATURE_NX))
1307 kvm_enable_efer_bits(EFER_NX);
1308
1309 return alloc_kvm_area();
1310 }
1311
1312 static __exit void hardware_unsetup(void)
1313 {
1314 free_kvm_area();
1315 }
1316
1317 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1318 {
1319 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1320
1321 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1322 vmcs_write16(sf->selector, save->selector);
1323 vmcs_writel(sf->base, save->base);
1324 vmcs_write32(sf->limit, save->limit);
1325 vmcs_write32(sf->ar_bytes, save->ar);
1326 } else {
1327 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1328 << AR_DPL_SHIFT;
1329 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1330 }
1331 }
1332
1333 static void enter_pmode(struct kvm_vcpu *vcpu)
1334 {
1335 unsigned long flags;
1336 struct vcpu_vmx *vmx = to_vmx(vcpu);
1337
1338 vmx->emulation_required = 1;
1339 vcpu->arch.rmode.active = 0;
1340
1341 vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
1342 vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
1343 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
1344
1345 flags = vmcs_readl(GUEST_RFLAGS);
1346 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1347 flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
1348 vmcs_writel(GUEST_RFLAGS, flags);
1349
1350 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1351 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1352
1353 update_exception_bitmap(vcpu);
1354
1355 if (emulate_invalid_guest_state)
1356 return;
1357
1358 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1359 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1360 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1361 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1362
1363 vmcs_write16(GUEST_SS_SELECTOR, 0);
1364 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1365
1366 vmcs_write16(GUEST_CS_SELECTOR,
1367 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1368 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1369 }
1370
1371 static gva_t rmode_tss_base(struct kvm *kvm)
1372 {
1373 if (!kvm->arch.tss_addr) {
1374 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1375 kvm->memslots[0].npages - 3;
1376 return base_gfn << PAGE_SHIFT;
1377 }
1378 return kvm->arch.tss_addr;
1379 }
1380
1381 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1382 {
1383 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1384
1385 save->selector = vmcs_read16(sf->selector);
1386 save->base = vmcs_readl(sf->base);
1387 save->limit = vmcs_read32(sf->limit);
1388 save->ar = vmcs_read32(sf->ar_bytes);
1389 vmcs_write16(sf->selector, save->base >> 4);
1390 vmcs_write32(sf->base, save->base & 0xfffff);
1391 vmcs_write32(sf->limit, 0xffff);
1392 vmcs_write32(sf->ar_bytes, 0xf3);
1393 }
1394
1395 static void enter_rmode(struct kvm_vcpu *vcpu)
1396 {
1397 unsigned long flags;
1398 struct vcpu_vmx *vmx = to_vmx(vcpu);
1399
1400 vmx->emulation_required = 1;
1401 vcpu->arch.rmode.active = 1;
1402
1403 vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1404 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1405
1406 vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1407 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1408
1409 vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1410 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1411
1412 flags = vmcs_readl(GUEST_RFLAGS);
1413 vcpu->arch.rmode.save_iopl
1414 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1415
1416 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1417
1418 vmcs_writel(GUEST_RFLAGS, flags);
1419 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1420 update_exception_bitmap(vcpu);
1421
1422 if (emulate_invalid_guest_state)
1423 goto continue_rmode;
1424
1425 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1426 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1427 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1428
1429 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1430 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1431 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1432 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1433 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1434
1435 fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
1436 fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
1437 fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
1438 fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
1439
1440 continue_rmode:
1441 kvm_mmu_reset_context(vcpu);
1442 init_rmode(vcpu->kvm);
1443 }
1444
1445 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1446 {
1447 struct vcpu_vmx *vmx = to_vmx(vcpu);
1448 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1449
1450 vcpu->arch.shadow_efer = efer;
1451 if (!msr)
1452 return;
1453 if (efer & EFER_LMA) {
1454 vmcs_write32(VM_ENTRY_CONTROLS,
1455 vmcs_read32(VM_ENTRY_CONTROLS) |
1456 VM_ENTRY_IA32E_MODE);
1457 msr->data = efer;
1458 } else {
1459 vmcs_write32(VM_ENTRY_CONTROLS,
1460 vmcs_read32(VM_ENTRY_CONTROLS) &
1461 ~VM_ENTRY_IA32E_MODE);
1462
1463 msr->data = efer & ~EFER_LME;
1464 }
1465 setup_msrs(vmx);
1466 }
1467
1468 #ifdef CONFIG_X86_64
1469
1470 static void enter_lmode(struct kvm_vcpu *vcpu)
1471 {
1472 u32 guest_tr_ar;
1473
1474 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1475 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1476 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1477 __func__);
1478 vmcs_write32(GUEST_TR_AR_BYTES,
1479 (guest_tr_ar & ~AR_TYPE_MASK)
1480 | AR_TYPE_BUSY_64_TSS);
1481 }
1482 vcpu->arch.shadow_efer |= EFER_LMA;
1483 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1484 }
1485
1486 static void exit_lmode(struct kvm_vcpu *vcpu)
1487 {
1488 vcpu->arch.shadow_efer &= ~EFER_LMA;
1489
1490 vmcs_write32(VM_ENTRY_CONTROLS,
1491 vmcs_read32(VM_ENTRY_CONTROLS)
1492 & ~VM_ENTRY_IA32E_MODE);
1493 }
1494
1495 #endif
1496
1497 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1498 {
1499 vpid_sync_vcpu_all(to_vmx(vcpu));
1500 if (enable_ept)
1501 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1502 }
1503
1504 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1505 {
1506 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1507 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1508 }
1509
1510 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1511 {
1512 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1513 if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
1514 printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
1515 return;
1516 }
1517 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1518 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1519 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1520 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1521 }
1522 }
1523
1524 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1525
1526 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1527 unsigned long cr0,
1528 struct kvm_vcpu *vcpu)
1529 {
1530 if (!(cr0 & X86_CR0_PG)) {
1531 /* From paging/starting to nonpaging */
1532 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1533 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1534 (CPU_BASED_CR3_LOAD_EXITING |
1535 CPU_BASED_CR3_STORE_EXITING));
1536 vcpu->arch.cr0 = cr0;
1537 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1538 *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
1539 *hw_cr0 &= ~X86_CR0_WP;
1540 } else if (!is_paging(vcpu)) {
1541 /* From nonpaging to paging */
1542 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1543 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1544 ~(CPU_BASED_CR3_LOAD_EXITING |
1545 CPU_BASED_CR3_STORE_EXITING));
1546 vcpu->arch.cr0 = cr0;
1547 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1548 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1549 *hw_cr0 &= ~X86_CR0_WP;
1550 }
1551 }
1552
1553 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1554 struct kvm_vcpu *vcpu)
1555 {
1556 if (!is_paging(vcpu)) {
1557 *hw_cr4 &= ~X86_CR4_PAE;
1558 *hw_cr4 |= X86_CR4_PSE;
1559 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1560 *hw_cr4 &= ~X86_CR4_PAE;
1561 }
1562
1563 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1564 {
1565 unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
1566 KVM_VM_CR0_ALWAYS_ON;
1567
1568 vmx_fpu_deactivate(vcpu);
1569
1570 if (vcpu->arch.rmode.active && (cr0 & X86_CR0_PE))
1571 enter_pmode(vcpu);
1572
1573 if (!vcpu->arch.rmode.active && !(cr0 & X86_CR0_PE))
1574 enter_rmode(vcpu);
1575
1576 #ifdef CONFIG_X86_64
1577 if (vcpu->arch.shadow_efer & EFER_LME) {
1578 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1579 enter_lmode(vcpu);
1580 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1581 exit_lmode(vcpu);
1582 }
1583 #endif
1584
1585 if (enable_ept)
1586 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1587
1588 vmcs_writel(CR0_READ_SHADOW, cr0);
1589 vmcs_writel(GUEST_CR0, hw_cr0);
1590 vcpu->arch.cr0 = cr0;
1591
1592 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1593 vmx_fpu_activate(vcpu);
1594 }
1595
1596 static u64 construct_eptp(unsigned long root_hpa)
1597 {
1598 u64 eptp;
1599
1600 /* TODO write the value reading from MSR */
1601 eptp = VMX_EPT_DEFAULT_MT |
1602 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1603 eptp |= (root_hpa & PAGE_MASK);
1604
1605 return eptp;
1606 }
1607
1608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1609 {
1610 unsigned long guest_cr3;
1611 u64 eptp;
1612
1613 guest_cr3 = cr3;
1614 if (enable_ept) {
1615 eptp = construct_eptp(cr3);
1616 vmcs_write64(EPT_POINTER, eptp);
1617 ept_sync_context(eptp);
1618 ept_load_pdptrs(vcpu);
1619 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1620 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1621 }
1622
1623 vmx_flush_tlb(vcpu);
1624 vmcs_writel(GUEST_CR3, guest_cr3);
1625 if (vcpu->arch.cr0 & X86_CR0_PE)
1626 vmx_fpu_deactivate(vcpu);
1627 }
1628
1629 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1630 {
1631 unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.active ?
1632 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1633
1634 vcpu->arch.cr4 = cr4;
1635 if (enable_ept)
1636 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1637
1638 vmcs_writel(CR4_READ_SHADOW, cr4);
1639 vmcs_writel(GUEST_CR4, hw_cr4);
1640 }
1641
1642 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1643 {
1644 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1645
1646 return vmcs_readl(sf->base);
1647 }
1648
1649 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1650 struct kvm_segment *var, int seg)
1651 {
1652 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1653 u32 ar;
1654
1655 var->base = vmcs_readl(sf->base);
1656 var->limit = vmcs_read32(sf->limit);
1657 var->selector = vmcs_read16(sf->selector);
1658 ar = vmcs_read32(sf->ar_bytes);
1659 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1660 ar = 0;
1661 var->type = ar & 15;
1662 var->s = (ar >> 4) & 1;
1663 var->dpl = (ar >> 5) & 3;
1664 var->present = (ar >> 7) & 1;
1665 var->avl = (ar >> 12) & 1;
1666 var->l = (ar >> 13) & 1;
1667 var->db = (ar >> 14) & 1;
1668 var->g = (ar >> 15) & 1;
1669 var->unusable = (ar >> 16) & 1;
1670 }
1671
1672 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1673 {
1674 struct kvm_segment kvm_seg;
1675
1676 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1677 return 0;
1678
1679 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1680 return 3;
1681
1682 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1683 return kvm_seg.selector & 3;
1684 }
1685
1686 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1687 {
1688 u32 ar;
1689
1690 if (var->unusable)
1691 ar = 1 << 16;
1692 else {
1693 ar = var->type & 15;
1694 ar |= (var->s & 1) << 4;
1695 ar |= (var->dpl & 3) << 5;
1696 ar |= (var->present & 1) << 7;
1697 ar |= (var->avl & 1) << 12;
1698 ar |= (var->l & 1) << 13;
1699 ar |= (var->db & 1) << 14;
1700 ar |= (var->g & 1) << 15;
1701 }
1702 if (ar == 0) /* a 0 value means unusable */
1703 ar = AR_UNUSABLE_MASK;
1704
1705 return ar;
1706 }
1707
1708 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1709 struct kvm_segment *var, int seg)
1710 {
1711 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1712 u32 ar;
1713
1714 if (vcpu->arch.rmode.active && seg == VCPU_SREG_TR) {
1715 vcpu->arch.rmode.tr.selector = var->selector;
1716 vcpu->arch.rmode.tr.base = var->base;
1717 vcpu->arch.rmode.tr.limit = var->limit;
1718 vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
1719 return;
1720 }
1721 vmcs_writel(sf->base, var->base);
1722 vmcs_write32(sf->limit, var->limit);
1723 vmcs_write16(sf->selector, var->selector);
1724 if (vcpu->arch.rmode.active && var->s) {
1725 /*
1726 * Hack real-mode segments into vm86 compatibility.
1727 */
1728 if (var->base == 0xffff0000 && var->selector == 0xf000)
1729 vmcs_writel(sf->base, 0xf0000);
1730 ar = 0xf3;
1731 } else
1732 ar = vmx_segment_access_rights(var);
1733 vmcs_write32(sf->ar_bytes, ar);
1734 }
1735
1736 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1737 {
1738 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1739
1740 *db = (ar >> 14) & 1;
1741 *l = (ar >> 13) & 1;
1742 }
1743
1744 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1745 {
1746 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1747 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1748 }
1749
1750 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1751 {
1752 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1753 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1754 }
1755
1756 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1757 {
1758 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1759 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1760 }
1761
1762 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1763 {
1764 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1765 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1766 }
1767
1768 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1769 {
1770 struct kvm_segment var;
1771 u32 ar;
1772
1773 vmx_get_segment(vcpu, &var, seg);
1774 ar = vmx_segment_access_rights(&var);
1775
1776 if (var.base != (var.selector << 4))
1777 return false;
1778 if (var.limit != 0xffff)
1779 return false;
1780 if (ar != 0xf3)
1781 return false;
1782
1783 return true;
1784 }
1785
1786 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1787 {
1788 struct kvm_segment cs;
1789 unsigned int cs_rpl;
1790
1791 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1792 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1793
1794 if (cs.unusable)
1795 return false;
1796 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1797 return false;
1798 if (!cs.s)
1799 return false;
1800 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1801 if (cs.dpl > cs_rpl)
1802 return false;
1803 } else {
1804 if (cs.dpl != cs_rpl)
1805 return false;
1806 }
1807 if (!cs.present)
1808 return false;
1809
1810 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1811 return true;
1812 }
1813
1814 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1815 {
1816 struct kvm_segment ss;
1817 unsigned int ss_rpl;
1818
1819 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1820 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1821
1822 if (ss.unusable)
1823 return true;
1824 if (ss.type != 3 && ss.type != 7)
1825 return false;
1826 if (!ss.s)
1827 return false;
1828 if (ss.dpl != ss_rpl) /* DPL != RPL */
1829 return false;
1830 if (!ss.present)
1831 return false;
1832
1833 return true;
1834 }
1835
1836 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1837 {
1838 struct kvm_segment var;
1839 unsigned int rpl;
1840
1841 vmx_get_segment(vcpu, &var, seg);
1842 rpl = var.selector & SELECTOR_RPL_MASK;
1843
1844 if (var.unusable)
1845 return true;
1846 if (!var.s)
1847 return false;
1848 if (!var.present)
1849 return false;
1850 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1851 if (var.dpl < rpl) /* DPL < RPL */
1852 return false;
1853 }
1854
1855 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1856 * rights flags
1857 */
1858 return true;
1859 }
1860
1861 static bool tr_valid(struct kvm_vcpu *vcpu)
1862 {
1863 struct kvm_segment tr;
1864
1865 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1866
1867 if (tr.unusable)
1868 return false;
1869 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1870 return false;
1871 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1872 return false;
1873 if (!tr.present)
1874 return false;
1875
1876 return true;
1877 }
1878
1879 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1880 {
1881 struct kvm_segment ldtr;
1882
1883 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1884
1885 if (ldtr.unusable)
1886 return true;
1887 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1888 return false;
1889 if (ldtr.type != 2)
1890 return false;
1891 if (!ldtr.present)
1892 return false;
1893
1894 return true;
1895 }
1896
1897 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
1898 {
1899 struct kvm_segment cs, ss;
1900
1901 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1902 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1903
1904 return ((cs.selector & SELECTOR_RPL_MASK) ==
1905 (ss.selector & SELECTOR_RPL_MASK));
1906 }
1907
1908 /*
1909 * Check if guest state is valid. Returns true if valid, false if
1910 * not.
1911 * We assume that registers are always usable
1912 */
1913 static bool guest_state_valid(struct kvm_vcpu *vcpu)
1914 {
1915 /* real mode guest state checks */
1916 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
1917 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
1918 return false;
1919 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
1920 return false;
1921 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
1922 return false;
1923 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
1924 return false;
1925 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
1926 return false;
1927 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
1928 return false;
1929 } else {
1930 /* protected mode guest state checks */
1931 if (!cs_ss_rpl_check(vcpu))
1932 return false;
1933 if (!code_segment_valid(vcpu))
1934 return false;
1935 if (!stack_segment_valid(vcpu))
1936 return false;
1937 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
1938 return false;
1939 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
1940 return false;
1941 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
1942 return false;
1943 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
1944 return false;
1945 if (!tr_valid(vcpu))
1946 return false;
1947 if (!ldtr_valid(vcpu))
1948 return false;
1949 }
1950 /* TODO:
1951 * - Add checks on RIP
1952 * - Add checks on RFLAGS
1953 */
1954
1955 return true;
1956 }
1957
1958 static int init_rmode_tss(struct kvm *kvm)
1959 {
1960 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1961 u16 data = 0;
1962 int ret = 0;
1963 int r;
1964
1965 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1966 if (r < 0)
1967 goto out;
1968 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1969 r = kvm_write_guest_page(kvm, fn++, &data,
1970 TSS_IOPB_BASE_OFFSET, sizeof(u16));
1971 if (r < 0)
1972 goto out;
1973 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1974 if (r < 0)
1975 goto out;
1976 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1977 if (r < 0)
1978 goto out;
1979 data = ~0;
1980 r = kvm_write_guest_page(kvm, fn, &data,
1981 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1982 sizeof(u8));
1983 if (r < 0)
1984 goto out;
1985
1986 ret = 1;
1987 out:
1988 return ret;
1989 }
1990
1991 static int init_rmode_identity_map(struct kvm *kvm)
1992 {
1993 int i, r, ret;
1994 pfn_t identity_map_pfn;
1995 u32 tmp;
1996
1997 if (!enable_ept)
1998 return 1;
1999 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2000 printk(KERN_ERR "EPT: identity-mapping pagetable "
2001 "haven't been allocated!\n");
2002 return 0;
2003 }
2004 if (likely(kvm->arch.ept_identity_pagetable_done))
2005 return 1;
2006 ret = 0;
2007 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2008 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2009 if (r < 0)
2010 goto out;
2011 /* Set up identity-mapping pagetable for EPT in real mode */
2012 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2013 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2014 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2015 r = kvm_write_guest_page(kvm, identity_map_pfn,
2016 &tmp, i * sizeof(tmp), sizeof(tmp));
2017 if (r < 0)
2018 goto out;
2019 }
2020 kvm->arch.ept_identity_pagetable_done = true;
2021 ret = 1;
2022 out:
2023 return ret;
2024 }
2025
2026 static void seg_setup(int seg)
2027 {
2028 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2029
2030 vmcs_write16(sf->selector, 0);
2031 vmcs_writel(sf->base, 0);
2032 vmcs_write32(sf->limit, 0xffff);
2033 vmcs_write32(sf->ar_bytes, 0xf3);
2034 }
2035
2036 static int alloc_apic_access_page(struct kvm *kvm)
2037 {
2038 struct kvm_userspace_memory_region kvm_userspace_mem;
2039 int r = 0;
2040
2041 down_write(&kvm->slots_lock);
2042 if (kvm->arch.apic_access_page)
2043 goto out;
2044 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2045 kvm_userspace_mem.flags = 0;
2046 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2047 kvm_userspace_mem.memory_size = PAGE_SIZE;
2048 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2049 if (r)
2050 goto out;
2051
2052 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2053 out:
2054 up_write(&kvm->slots_lock);
2055 return r;
2056 }
2057
2058 static int alloc_identity_pagetable(struct kvm *kvm)
2059 {
2060 struct kvm_userspace_memory_region kvm_userspace_mem;
2061 int r = 0;
2062
2063 down_write(&kvm->slots_lock);
2064 if (kvm->arch.ept_identity_pagetable)
2065 goto out;
2066 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2067 kvm_userspace_mem.flags = 0;
2068 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2069 kvm_userspace_mem.memory_size = PAGE_SIZE;
2070 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2071 if (r)
2072 goto out;
2073
2074 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2075 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2076 out:
2077 up_write(&kvm->slots_lock);
2078 return r;
2079 }
2080
2081 static void allocate_vpid(struct vcpu_vmx *vmx)
2082 {
2083 int vpid;
2084
2085 vmx->vpid = 0;
2086 if (!enable_vpid)
2087 return;
2088 spin_lock(&vmx_vpid_lock);
2089 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2090 if (vpid < VMX_NR_VPIDS) {
2091 vmx->vpid = vpid;
2092 __set_bit(vpid, vmx_vpid_bitmap);
2093 }
2094 spin_unlock(&vmx_vpid_lock);
2095 }
2096
2097 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2098 {
2099 int f = sizeof(unsigned long);
2100
2101 if (!cpu_has_vmx_msr_bitmap())
2102 return;
2103
2104 /*
2105 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2106 * have the write-low and read-high bitmap offsets the wrong way round.
2107 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2108 */
2109 if (msr <= 0x1fff) {
2110 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2111 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2112 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2113 msr &= 0x1fff;
2114 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2115 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2116 }
2117 }
2118
2119 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2120 {
2121 if (!longmode_only)
2122 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2123 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2124 }
2125
2126 /*
2127 * Sets up the vmcs for emulated real mode.
2128 */
2129 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2130 {
2131 u32 host_sysenter_cs, msr_low, msr_high;
2132 u32 junk;
2133 u64 host_pat, tsc_this, tsc_base;
2134 unsigned long a;
2135 struct descriptor_table dt;
2136 int i;
2137 unsigned long kvm_vmx_return;
2138 u32 exec_control;
2139
2140 /* I/O */
2141 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2142 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2143
2144 if (cpu_has_vmx_msr_bitmap())
2145 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2146
2147 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2148
2149 /* Control */
2150 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2151 vmcs_config.pin_based_exec_ctrl);
2152
2153 exec_control = vmcs_config.cpu_based_exec_ctrl;
2154 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2155 exec_control &= ~CPU_BASED_TPR_SHADOW;
2156 #ifdef CONFIG_X86_64
2157 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2158 CPU_BASED_CR8_LOAD_EXITING;
2159 #endif
2160 }
2161 if (!enable_ept)
2162 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2163 CPU_BASED_CR3_LOAD_EXITING |
2164 CPU_BASED_INVLPG_EXITING;
2165 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2166
2167 if (cpu_has_secondary_exec_ctrls()) {
2168 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2169 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2170 exec_control &=
2171 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2172 if (vmx->vpid == 0)
2173 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2174 if (!enable_ept)
2175 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2176 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2177 }
2178
2179 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2180 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2181 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2182
2183 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2184 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2185 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2186
2187 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2188 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2189 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2190 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2191 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2192 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2193 #ifdef CONFIG_X86_64
2194 rdmsrl(MSR_FS_BASE, a);
2195 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2196 rdmsrl(MSR_GS_BASE, a);
2197 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2198 #else
2199 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2200 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2201 #endif
2202
2203 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2204
2205 kvm_get_idt(&dt);
2206 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2207
2208 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2209 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2210 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2211 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2212 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2213
2214 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2215 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2216 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2217 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2218 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2219 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2220
2221 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2222 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2223 host_pat = msr_low | ((u64) msr_high << 32);
2224 vmcs_write64(HOST_IA32_PAT, host_pat);
2225 }
2226 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2227 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2228 host_pat = msr_low | ((u64) msr_high << 32);
2229 /* Write the default value follow host pat */
2230 vmcs_write64(GUEST_IA32_PAT, host_pat);
2231 /* Keep arch.pat sync with GUEST_IA32_PAT */
2232 vmx->vcpu.arch.pat = host_pat;
2233 }
2234
2235 for (i = 0; i < NR_VMX_MSR; ++i) {
2236 u32 index = vmx_msr_index[i];
2237 u32 data_low, data_high;
2238 u64 data;
2239 int j = vmx->nmsrs;
2240
2241 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2242 continue;
2243 if (wrmsr_safe(index, data_low, data_high) < 0)
2244 continue;
2245 data = data_low | ((u64)data_high << 32);
2246 vmx->host_msrs[j].index = index;
2247 vmx->host_msrs[j].reserved = 0;
2248 vmx->host_msrs[j].data = data;
2249 vmx->guest_msrs[j] = vmx->host_msrs[j];
2250 ++vmx->nmsrs;
2251 }
2252
2253 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2254
2255 /* 22.2.1, 20.8.1 */
2256 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2257
2258 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2259 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2260
2261 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2262 rdtscll(tsc_this);
2263 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2264 tsc_base = tsc_this;
2265
2266 guest_write_tsc(0, tsc_base);
2267
2268 return 0;
2269 }
2270
2271 static int init_rmode(struct kvm *kvm)
2272 {
2273 if (!init_rmode_tss(kvm))
2274 return 0;
2275 if (!init_rmode_identity_map(kvm))
2276 return 0;
2277 return 1;
2278 }
2279
2280 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2281 {
2282 struct vcpu_vmx *vmx = to_vmx(vcpu);
2283 u64 msr;
2284 int ret;
2285
2286 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2287 down_read(&vcpu->kvm->slots_lock);
2288 if (!init_rmode(vmx->vcpu.kvm)) {
2289 ret = -ENOMEM;
2290 goto out;
2291 }
2292
2293 vmx->vcpu.arch.rmode.active = 0;
2294
2295 vmx->soft_vnmi_blocked = 0;
2296
2297 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2298 kvm_set_cr8(&vmx->vcpu, 0);
2299 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2300 if (vmx->vcpu.vcpu_id == 0)
2301 msr |= MSR_IA32_APICBASE_BSP;
2302 kvm_set_apic_base(&vmx->vcpu, msr);
2303
2304 fx_init(&vmx->vcpu);
2305
2306 seg_setup(VCPU_SREG_CS);
2307 /*
2308 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2309 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2310 */
2311 if (vmx->vcpu.vcpu_id == 0) {
2312 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2313 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2314 } else {
2315 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2316 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2317 }
2318
2319 seg_setup(VCPU_SREG_DS);
2320 seg_setup(VCPU_SREG_ES);
2321 seg_setup(VCPU_SREG_FS);
2322 seg_setup(VCPU_SREG_GS);
2323 seg_setup(VCPU_SREG_SS);
2324
2325 vmcs_write16(GUEST_TR_SELECTOR, 0);
2326 vmcs_writel(GUEST_TR_BASE, 0);
2327 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2328 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2329
2330 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2331 vmcs_writel(GUEST_LDTR_BASE, 0);
2332 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2333 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2334
2335 vmcs_write32(GUEST_SYSENTER_CS, 0);
2336 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2337 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2338
2339 vmcs_writel(GUEST_RFLAGS, 0x02);
2340 if (vmx->vcpu.vcpu_id == 0)
2341 kvm_rip_write(vcpu, 0xfff0);
2342 else
2343 kvm_rip_write(vcpu, 0);
2344 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2345
2346 vmcs_writel(GUEST_DR7, 0x400);
2347
2348 vmcs_writel(GUEST_GDTR_BASE, 0);
2349 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2350
2351 vmcs_writel(GUEST_IDTR_BASE, 0);
2352 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2353
2354 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2355 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2356 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2357
2358 /* Special registers */
2359 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2360
2361 setup_msrs(vmx);
2362
2363 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2364
2365 if (cpu_has_vmx_tpr_shadow()) {
2366 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2367 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2368 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2369 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2370 vmcs_write32(TPR_THRESHOLD, 0);
2371 }
2372
2373 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2374 vmcs_write64(APIC_ACCESS_ADDR,
2375 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2376
2377 if (vmx->vpid != 0)
2378 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2379
2380 vmx->vcpu.arch.cr0 = 0x60000010;
2381 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2382 vmx_set_cr4(&vmx->vcpu, 0);
2383 vmx_set_efer(&vmx->vcpu, 0);
2384 vmx_fpu_activate(&vmx->vcpu);
2385 update_exception_bitmap(&vmx->vcpu);
2386
2387 vpid_sync_vcpu_all(vmx);
2388
2389 ret = 0;
2390
2391 /* HACK: Don't enable emulation on guest boot/reset */
2392 vmx->emulation_required = 0;
2393
2394 out:
2395 up_read(&vcpu->kvm->slots_lock);
2396 return ret;
2397 }
2398
2399 static void enable_irq_window(struct kvm_vcpu *vcpu)
2400 {
2401 u32 cpu_based_vm_exec_control;
2402
2403 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2404 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2406 }
2407
2408 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2409 {
2410 u32 cpu_based_vm_exec_control;
2411
2412 if (!cpu_has_virtual_nmis()) {
2413 enable_irq_window(vcpu);
2414 return;
2415 }
2416
2417 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2418 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2419 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2420 }
2421
2422 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
2423 {
2424 struct vcpu_vmx *vmx = to_vmx(vcpu);
2425
2426 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2427
2428 ++vcpu->stat.irq_injections;
2429 if (vcpu->arch.rmode.active) {
2430 vmx->rmode.irq.pending = true;
2431 vmx->rmode.irq.vector = irq;
2432 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2433 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2434 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2435 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2436 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2437 return;
2438 }
2439 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2440 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
2441 }
2442
2443 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2444 {
2445 struct vcpu_vmx *vmx = to_vmx(vcpu);
2446
2447 if (!cpu_has_virtual_nmis()) {
2448 /*
2449 * Tracking the NMI-blocked state in software is built upon
2450 * finding the next open IRQ window. This, in turn, depends on
2451 * well-behaving guests: They have to keep IRQs disabled at
2452 * least as long as the NMI handler runs. Otherwise we may
2453 * cause NMI nesting, maybe breaking the guest. But as this is
2454 * highly unlikely, we can live with the residual risk.
2455 */
2456 vmx->soft_vnmi_blocked = 1;
2457 vmx->vnmi_blocked_time = 0;
2458 }
2459
2460 ++vcpu->stat.nmi_injections;
2461 if (vcpu->arch.rmode.active) {
2462 vmx->rmode.irq.pending = true;
2463 vmx->rmode.irq.vector = NMI_VECTOR;
2464 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2465 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2466 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2467 INTR_INFO_VALID_MASK);
2468 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2469 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2470 return;
2471 }
2472 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2473 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2474 }
2475
2476 static void vmx_update_window_states(struct kvm_vcpu *vcpu)
2477 {
2478 u32 guest_intr = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2479
2480 vcpu->arch.nmi_window_open =
2481 !(guest_intr & (GUEST_INTR_STATE_STI |
2482 GUEST_INTR_STATE_MOV_SS |
2483 GUEST_INTR_STATE_NMI));
2484 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2485 vcpu->arch.nmi_window_open = 0;
2486
2487 vcpu->arch.interrupt_window_open =
2488 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2489 !(guest_intr & (GUEST_INTR_STATE_STI |
2490 GUEST_INTR_STATE_MOV_SS)));
2491 }
2492
2493 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
2494 struct kvm_run *kvm_run)
2495 {
2496 vmx_update_window_states(vcpu);
2497
2498 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
2499 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2500 GUEST_INTR_STATE_STI |
2501 GUEST_INTR_STATE_MOV_SS);
2502
2503 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
2504 if (vcpu->arch.interrupt.pending) {
2505 enable_nmi_window(vcpu);
2506 } else if (vcpu->arch.nmi_window_open) {
2507 vcpu->arch.nmi_pending = false;
2508 vcpu->arch.nmi_injected = true;
2509 } else {
2510 enable_nmi_window(vcpu);
2511 return;
2512 }
2513 }
2514 if (vcpu->arch.nmi_injected) {
2515 vmx_inject_nmi(vcpu);
2516 if (vcpu->arch.nmi_pending)
2517 enable_nmi_window(vcpu);
2518 else if (vcpu->arch.irq_summary
2519 || kvm_run->request_interrupt_window)
2520 enable_irq_window(vcpu);
2521 return;
2522 }
2523
2524 if (vcpu->arch.interrupt_window_open) {
2525 if (vcpu->arch.irq_summary && !vcpu->arch.interrupt.pending)
2526 kvm_queue_interrupt(vcpu, kvm_pop_irq(vcpu));
2527
2528 if (vcpu->arch.interrupt.pending)
2529 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
2530 }
2531 if (!vcpu->arch.interrupt_window_open &&
2532 (vcpu->arch.irq_summary || kvm_run->request_interrupt_window))
2533 enable_irq_window(vcpu);
2534 }
2535
2536 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2537 {
2538 int ret;
2539 struct kvm_userspace_memory_region tss_mem = {
2540 .slot = TSS_PRIVATE_MEMSLOT,
2541 .guest_phys_addr = addr,
2542 .memory_size = PAGE_SIZE * 3,
2543 .flags = 0,
2544 };
2545
2546 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2547 if (ret)
2548 return ret;
2549 kvm->arch.tss_addr = addr;
2550 return 0;
2551 }
2552
2553 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2554 int vec, u32 err_code)
2555 {
2556 /*
2557 * Instruction with address size override prefix opcode 0x67
2558 * Cause the #SS fault with 0 error code in VM86 mode.
2559 */
2560 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2561 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2562 return 1;
2563 /*
2564 * Forward all other exceptions that are valid in real mode.
2565 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2566 * the required debugging infrastructure rework.
2567 */
2568 switch (vec) {
2569 case DB_VECTOR:
2570 if (vcpu->guest_debug &
2571 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2572 return 0;
2573 kvm_queue_exception(vcpu, vec);
2574 return 1;
2575 case BP_VECTOR:
2576 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2577 return 0;
2578 /* fall through */
2579 case DE_VECTOR:
2580 case OF_VECTOR:
2581 case BR_VECTOR:
2582 case UD_VECTOR:
2583 case DF_VECTOR:
2584 case SS_VECTOR:
2585 case GP_VECTOR:
2586 case MF_VECTOR:
2587 kvm_queue_exception(vcpu, vec);
2588 return 1;
2589 }
2590 return 0;
2591 }
2592
2593 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2594 {
2595 struct vcpu_vmx *vmx = to_vmx(vcpu);
2596 u32 intr_info, ex_no, error_code;
2597 unsigned long cr2, rip, dr6;
2598 u32 vect_info;
2599 enum emulation_result er;
2600
2601 vect_info = vmx->idt_vectoring_info;
2602 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2603
2604 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2605 !is_page_fault(intr_info))
2606 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2607 "intr info 0x%x\n", __func__, vect_info, intr_info);
2608
2609 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
2610 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
2611 kvm_push_irq(vcpu, irq);
2612 }
2613
2614 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2615 return 1; /* already handled by vmx_vcpu_run() */
2616
2617 if (is_no_device(intr_info)) {
2618 vmx_fpu_activate(vcpu);
2619 return 1;
2620 }
2621
2622 if (is_invalid_opcode(intr_info)) {
2623 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2624 if (er != EMULATE_DONE)
2625 kvm_queue_exception(vcpu, UD_VECTOR);
2626 return 1;
2627 }
2628
2629 error_code = 0;
2630 rip = kvm_rip_read(vcpu);
2631 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2632 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2633 if (is_page_fault(intr_info)) {
2634 /* EPT won't cause page fault directly */
2635 if (enable_ept)
2636 BUG();
2637 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2638 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2639 (u32)((u64)cr2 >> 32), handler);
2640 if (vcpu->arch.interrupt.pending || vcpu->arch.exception.pending)
2641 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2642 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2643 }
2644
2645 if (vcpu->arch.rmode.active &&
2646 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2647 error_code)) {
2648 if (vcpu->arch.halt_request) {
2649 vcpu->arch.halt_request = 0;
2650 return kvm_emulate_halt(vcpu);
2651 }
2652 return 1;
2653 }
2654
2655 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2656 switch (ex_no) {
2657 case DB_VECTOR:
2658 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2659 if (!(vcpu->guest_debug &
2660 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2661 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2662 kvm_queue_exception(vcpu, DB_VECTOR);
2663 return 1;
2664 }
2665 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2666 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2667 /* fall through */
2668 case BP_VECTOR:
2669 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2670 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2671 kvm_run->debug.arch.exception = ex_no;
2672 break;
2673 default:
2674 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2675 kvm_run->ex.exception = ex_no;
2676 kvm_run->ex.error_code = error_code;
2677 break;
2678 }
2679 return 0;
2680 }
2681
2682 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2683 struct kvm_run *kvm_run)
2684 {
2685 ++vcpu->stat.irq_exits;
2686 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2687 return 1;
2688 }
2689
2690 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2691 {
2692 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2693 return 0;
2694 }
2695
2696 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2697 {
2698 unsigned long exit_qualification;
2699 int size, in, string;
2700 unsigned port;
2701
2702 ++vcpu->stat.io_exits;
2703 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2704 string = (exit_qualification & 16) != 0;
2705
2706 if (string) {
2707 if (emulate_instruction(vcpu,
2708 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2709 return 0;
2710 return 1;
2711 }
2712
2713 size = (exit_qualification & 7) + 1;
2714 in = (exit_qualification & 8) != 0;
2715 port = exit_qualification >> 16;
2716
2717 skip_emulated_instruction(vcpu);
2718 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2719 }
2720
2721 static void
2722 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2723 {
2724 /*
2725 * Patch in the VMCALL instruction:
2726 */
2727 hypercall[0] = 0x0f;
2728 hypercall[1] = 0x01;
2729 hypercall[2] = 0xc1;
2730 }
2731
2732 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2733 {
2734 unsigned long exit_qualification;
2735 int cr;
2736 int reg;
2737
2738 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2739 cr = exit_qualification & 15;
2740 reg = (exit_qualification >> 8) & 15;
2741 switch ((exit_qualification >> 4) & 3) {
2742 case 0: /* mov to cr */
2743 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2744 (u32)kvm_register_read(vcpu, reg),
2745 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2746 handler);
2747 switch (cr) {
2748 case 0:
2749 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2750 skip_emulated_instruction(vcpu);
2751 return 1;
2752 case 3:
2753 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2754 skip_emulated_instruction(vcpu);
2755 return 1;
2756 case 4:
2757 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2758 skip_emulated_instruction(vcpu);
2759 return 1;
2760 case 8:
2761 kvm_set_cr8(vcpu, kvm_register_read(vcpu, reg));
2762 skip_emulated_instruction(vcpu);
2763 if (irqchip_in_kernel(vcpu->kvm))
2764 return 1;
2765 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2766 return 0;
2767 };
2768 break;
2769 case 2: /* clts */
2770 vmx_fpu_deactivate(vcpu);
2771 vcpu->arch.cr0 &= ~X86_CR0_TS;
2772 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2773 vmx_fpu_activate(vcpu);
2774 KVMTRACE_0D(CLTS, vcpu, handler);
2775 skip_emulated_instruction(vcpu);
2776 return 1;
2777 case 1: /*mov from cr*/
2778 switch (cr) {
2779 case 3:
2780 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2781 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2782 (u32)kvm_register_read(vcpu, reg),
2783 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2784 handler);
2785 skip_emulated_instruction(vcpu);
2786 return 1;
2787 case 8:
2788 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2789 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2790 (u32)kvm_register_read(vcpu, reg), handler);
2791 skip_emulated_instruction(vcpu);
2792 return 1;
2793 }
2794 break;
2795 case 3: /* lmsw */
2796 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2797
2798 skip_emulated_instruction(vcpu);
2799 return 1;
2800 default:
2801 break;
2802 }
2803 kvm_run->exit_reason = 0;
2804 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2805 (int)(exit_qualification >> 4) & 3, cr);
2806 return 0;
2807 }
2808
2809 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2810 {
2811 unsigned long exit_qualification;
2812 unsigned long val;
2813 int dr, reg;
2814
2815 dr = vmcs_readl(GUEST_DR7);
2816 if (dr & DR7_GD) {
2817 /*
2818 * As the vm-exit takes precedence over the debug trap, we
2819 * need to emulate the latter, either for the host or the
2820 * guest debugging itself.
2821 */
2822 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2823 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2824 kvm_run->debug.arch.dr7 = dr;
2825 kvm_run->debug.arch.pc =
2826 vmcs_readl(GUEST_CS_BASE) +
2827 vmcs_readl(GUEST_RIP);
2828 kvm_run->debug.arch.exception = DB_VECTOR;
2829 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2830 return 0;
2831 } else {
2832 vcpu->arch.dr7 &= ~DR7_GD;
2833 vcpu->arch.dr6 |= DR6_BD;
2834 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2835 kvm_queue_exception(vcpu, DB_VECTOR);
2836 return 1;
2837 }
2838 }
2839
2840 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2841 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2842 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2843 if (exit_qualification & TYPE_MOV_FROM_DR) {
2844 switch (dr) {
2845 case 0 ... 3:
2846 val = vcpu->arch.db[dr];
2847 break;
2848 case 6:
2849 val = vcpu->arch.dr6;
2850 break;
2851 case 7:
2852 val = vcpu->arch.dr7;
2853 break;
2854 default:
2855 val = 0;
2856 }
2857 kvm_register_write(vcpu, reg, val);
2858 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2859 } else {
2860 val = vcpu->arch.regs[reg];
2861 switch (dr) {
2862 case 0 ... 3:
2863 vcpu->arch.db[dr] = val;
2864 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2865 vcpu->arch.eff_db[dr] = val;
2866 break;
2867 case 4 ... 5:
2868 if (vcpu->arch.cr4 & X86_CR4_DE)
2869 kvm_queue_exception(vcpu, UD_VECTOR);
2870 break;
2871 case 6:
2872 if (val & 0xffffffff00000000ULL) {
2873 kvm_queue_exception(vcpu, GP_VECTOR);
2874 break;
2875 }
2876 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2877 break;
2878 case 7:
2879 if (val & 0xffffffff00000000ULL) {
2880 kvm_queue_exception(vcpu, GP_VECTOR);
2881 break;
2882 }
2883 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
2884 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
2885 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2886 vcpu->arch.switch_db_regs =
2887 (val & DR7_BP_EN_MASK);
2888 }
2889 break;
2890 }
2891 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
2892 }
2893 skip_emulated_instruction(vcpu);
2894 return 1;
2895 }
2896
2897 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2898 {
2899 kvm_emulate_cpuid(vcpu);
2900 return 1;
2901 }
2902
2903 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2904 {
2905 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2906 u64 data;
2907
2908 if (vmx_get_msr(vcpu, ecx, &data)) {
2909 kvm_inject_gp(vcpu, 0);
2910 return 1;
2911 }
2912
2913 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
2914 handler);
2915
2916 /* FIXME: handling of bits 32:63 of rax, rdx */
2917 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
2918 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2919 skip_emulated_instruction(vcpu);
2920 return 1;
2921 }
2922
2923 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2924 {
2925 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
2926 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
2927 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2928
2929 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
2930 handler);
2931
2932 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2933 kvm_inject_gp(vcpu, 0);
2934 return 1;
2935 }
2936
2937 skip_emulated_instruction(vcpu);
2938 return 1;
2939 }
2940
2941 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2942 struct kvm_run *kvm_run)
2943 {
2944 return 1;
2945 }
2946
2947 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2948 struct kvm_run *kvm_run)
2949 {
2950 u32 cpu_based_vm_exec_control;
2951
2952 /* clear pending irq */
2953 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2954 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2955 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2956
2957 KVMTRACE_0D(PEND_INTR, vcpu, handler);
2958 ++vcpu->stat.irq_window_exits;
2959
2960 /*
2961 * If the user space waits to inject interrupts, exit as soon as
2962 * possible
2963 */
2964 if (kvm_run->request_interrupt_window &&
2965 !vcpu->arch.irq_summary) {
2966 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2967 return 0;
2968 }
2969 return 1;
2970 }
2971
2972 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2973 {
2974 skip_emulated_instruction(vcpu);
2975 return kvm_emulate_halt(vcpu);
2976 }
2977
2978 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2979 {
2980 skip_emulated_instruction(vcpu);
2981 kvm_emulate_hypercall(vcpu);
2982 return 1;
2983 }
2984
2985 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2986 {
2987 u64 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2988
2989 kvm_mmu_invlpg(vcpu, exit_qualification);
2990 skip_emulated_instruction(vcpu);
2991 return 1;
2992 }
2993
2994 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2995 {
2996 skip_emulated_instruction(vcpu);
2997 /* TODO: Add support for VT-d/pass-through device */
2998 return 1;
2999 }
3000
3001 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3002 {
3003 u64 exit_qualification;
3004 enum emulation_result er;
3005 unsigned long offset;
3006
3007 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3008 offset = exit_qualification & 0xffful;
3009
3010 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3011
3012 if (er != EMULATE_DONE) {
3013 printk(KERN_ERR
3014 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3015 offset);
3016 return -ENOTSUPP;
3017 }
3018 return 1;
3019 }
3020
3021 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022 {
3023 struct vcpu_vmx *vmx = to_vmx(vcpu);
3024 unsigned long exit_qualification;
3025 u16 tss_selector;
3026 int reason;
3027
3028 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3029
3030 reason = (u32)exit_qualification >> 30;
3031 if (reason == TASK_SWITCH_GATE && vmx->vcpu.arch.nmi_injected &&
3032 (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
3033 (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK)
3034 == INTR_TYPE_NMI_INTR) {
3035 vcpu->arch.nmi_injected = false;
3036 if (cpu_has_virtual_nmis())
3037 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3038 GUEST_INTR_STATE_NMI);
3039 }
3040 tss_selector = exit_qualification;
3041
3042 if (!kvm_task_switch(vcpu, tss_selector, reason))
3043 return 0;
3044
3045 /* clear all local breakpoint enable flags */
3046 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3047
3048 /*
3049 * TODO: What about debug traps on tss switch?
3050 * Are we supposed to inject them and update dr6?
3051 */
3052
3053 return 1;
3054 }
3055
3056 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3057 {
3058 u64 exit_qualification;
3059 gpa_t gpa;
3060 int gla_validity;
3061
3062 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
3063
3064 if (exit_qualification & (1 << 6)) {
3065 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3066 return -ENOTSUPP;
3067 }
3068
3069 gla_validity = (exit_qualification >> 7) & 0x3;
3070 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3071 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3072 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3073 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3074 (long unsigned int)vmcs_read64(GUEST_LINEAR_ADDRESS));
3075 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3076 (long unsigned int)exit_qualification);
3077 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3078 kvm_run->hw.hardware_exit_reason = 0;
3079 return -ENOTSUPP;
3080 }
3081
3082 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3083 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3084 }
3085
3086 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3087 {
3088 u32 cpu_based_vm_exec_control;
3089
3090 /* clear pending NMI */
3091 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3092 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3093 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3094 ++vcpu->stat.nmi_window_exits;
3095
3096 return 1;
3097 }
3098
3099 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3100 struct kvm_run *kvm_run)
3101 {
3102 struct vcpu_vmx *vmx = to_vmx(vcpu);
3103 enum emulation_result err = EMULATE_DONE;
3104
3105 preempt_enable();
3106 local_irq_enable();
3107
3108 while (!guest_state_valid(vcpu)) {
3109 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3110
3111 if (err == EMULATE_DO_MMIO)
3112 break;
3113
3114 if (err != EMULATE_DONE) {
3115 kvm_report_emulation_failure(vcpu, "emulation failure");
3116 return;
3117 }
3118
3119 if (signal_pending(current))
3120 break;
3121 if (need_resched())
3122 schedule();
3123 }
3124
3125 local_irq_disable();
3126 preempt_disable();
3127
3128 vmx->invalid_state_emulation_result = err;
3129 }
3130
3131 /*
3132 * The exit handlers return 1 if the exit was handled fully and guest execution
3133 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3134 * to be done to userspace and return 0.
3135 */
3136 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3137 struct kvm_run *kvm_run) = {
3138 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3139 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3140 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3141 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3142 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3143 [EXIT_REASON_CR_ACCESS] = handle_cr,
3144 [EXIT_REASON_DR_ACCESS] = handle_dr,
3145 [EXIT_REASON_CPUID] = handle_cpuid,
3146 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3147 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3148 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3149 [EXIT_REASON_HLT] = handle_halt,
3150 [EXIT_REASON_INVLPG] = handle_invlpg,
3151 [EXIT_REASON_VMCALL] = handle_vmcall,
3152 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3153 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3154 [EXIT_REASON_WBINVD] = handle_wbinvd,
3155 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3156 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3157 };
3158
3159 static const int kvm_vmx_max_exit_handlers =
3160 ARRAY_SIZE(kvm_vmx_exit_handlers);
3161
3162 /*
3163 * The guest has exited. See if we can fix it or if we need userspace
3164 * assistance.
3165 */
3166 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3167 {
3168 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
3169 struct vcpu_vmx *vmx = to_vmx(vcpu);
3170 u32 vectoring_info = vmx->idt_vectoring_info;
3171
3172 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3173 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3174
3175 /* If we need to emulate an MMIO from handle_invalid_guest_state
3176 * we just return 0 */
3177 if (vmx->emulation_required && emulate_invalid_guest_state) {
3178 if (guest_state_valid(vcpu))
3179 vmx->emulation_required = 0;
3180 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3181 }
3182
3183 /* Access CR3 don't cause VMExit in paging mode, so we need
3184 * to sync with guest real CR3. */
3185 if (enable_ept && is_paging(vcpu)) {
3186 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3187 ept_load_pdptrs(vcpu);
3188 }
3189
3190 if (unlikely(vmx->fail)) {
3191 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3192 kvm_run->fail_entry.hardware_entry_failure_reason
3193 = vmcs_read32(VM_INSTRUCTION_ERROR);
3194 return 0;
3195 }
3196
3197 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3198 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3199 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3200 exit_reason != EXIT_REASON_TASK_SWITCH))
3201 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3202 "(0x%x) and exit reason is 0x%x\n",
3203 __func__, vectoring_info, exit_reason);
3204
3205 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3206 if (vcpu->arch.interrupt_window_open) {
3207 vmx->soft_vnmi_blocked = 0;
3208 vcpu->arch.nmi_window_open = 1;
3209 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3210 vcpu->arch.nmi_pending) {
3211 /*
3212 * This CPU don't support us in finding the end of an
3213 * NMI-blocked window if the guest runs with IRQs
3214 * disabled. So we pull the trigger after 1 s of
3215 * futile waiting, but inform the user about this.
3216 */
3217 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3218 "state on VCPU %d after 1 s timeout\n",
3219 __func__, vcpu->vcpu_id);
3220 vmx->soft_vnmi_blocked = 0;
3221 vmx->vcpu.arch.nmi_window_open = 1;
3222 }
3223 }
3224
3225 if (exit_reason < kvm_vmx_max_exit_handlers
3226 && kvm_vmx_exit_handlers[exit_reason])
3227 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3228 else {
3229 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3230 kvm_run->hw.hardware_exit_reason = exit_reason;
3231 }
3232 return 0;
3233 }
3234
3235 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
3236 {
3237 int max_irr, tpr;
3238
3239 if (!vm_need_tpr_shadow(vcpu->kvm))
3240 return;
3241
3242 if (!kvm_lapic_enabled(vcpu) ||
3243 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
3244 vmcs_write32(TPR_THRESHOLD, 0);
3245 return;
3246 }
3247
3248 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
3249 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
3250 }
3251
3252 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3253 {
3254 u32 exit_intr_info;
3255 u32 idt_vectoring_info;
3256 bool unblock_nmi;
3257 u8 vector;
3258 int type;
3259 bool idtv_info_valid;
3260 u32 error;
3261
3262 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3263 if (cpu_has_virtual_nmis()) {
3264 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3265 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3266 /*
3267 * SDM 3: 25.7.1.2
3268 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3269 * a guest IRET fault.
3270 */
3271 if (unblock_nmi && vector != DF_VECTOR)
3272 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3273 GUEST_INTR_STATE_NMI);
3274 } else if (unlikely(vmx->soft_vnmi_blocked))
3275 vmx->vnmi_blocked_time +=
3276 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3277
3278 idt_vectoring_info = vmx->idt_vectoring_info;
3279 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3280 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3281 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3282 if (vmx->vcpu.arch.nmi_injected) {
3283 /*
3284 * SDM 3: 25.7.1.2
3285 * Clear bit "block by NMI" before VM entry if a NMI delivery
3286 * faulted.
3287 */
3288 if (idtv_info_valid && type == INTR_TYPE_NMI_INTR)
3289 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3290 GUEST_INTR_STATE_NMI);
3291 else
3292 vmx->vcpu.arch.nmi_injected = false;
3293 }
3294 kvm_clear_exception_queue(&vmx->vcpu);
3295 if (idtv_info_valid && (type == INTR_TYPE_HARD_EXCEPTION ||
3296 type == INTR_TYPE_SOFT_EXCEPTION)) {
3297 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3298 error = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3299 kvm_queue_exception_e(&vmx->vcpu, vector, error);
3300 } else
3301 kvm_queue_exception(&vmx->vcpu, vector);
3302 vmx->idt_vectoring_info = 0;
3303 }
3304 kvm_clear_interrupt_queue(&vmx->vcpu);
3305 if (idtv_info_valid && type == INTR_TYPE_EXT_INTR) {
3306 kvm_queue_interrupt(&vmx->vcpu, vector);
3307 vmx->idt_vectoring_info = 0;
3308 }
3309 }
3310
3311 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
3312 {
3313 update_tpr_threshold(vcpu);
3314
3315 vmx_update_window_states(vcpu);
3316
3317 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3318 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3319 GUEST_INTR_STATE_STI |
3320 GUEST_INTR_STATE_MOV_SS);
3321
3322 if (vcpu->arch.nmi_pending && !vcpu->arch.nmi_injected) {
3323 if (vcpu->arch.interrupt.pending) {
3324 enable_nmi_window(vcpu);
3325 } else if (vcpu->arch.nmi_window_open) {
3326 vcpu->arch.nmi_pending = false;
3327 vcpu->arch.nmi_injected = true;
3328 } else {
3329 enable_nmi_window(vcpu);
3330 return;
3331 }
3332 }
3333 if (vcpu->arch.nmi_injected) {
3334 vmx_inject_nmi(vcpu);
3335 if (vcpu->arch.nmi_pending)
3336 enable_nmi_window(vcpu);
3337 else if (kvm_cpu_has_interrupt(vcpu))
3338 enable_irq_window(vcpu);
3339 return;
3340 }
3341 if (!vcpu->arch.interrupt.pending && kvm_cpu_has_interrupt(vcpu)) {
3342 if (vcpu->arch.interrupt_window_open)
3343 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu));
3344 else
3345 enable_irq_window(vcpu);
3346 }
3347 if (vcpu->arch.interrupt.pending) {
3348 vmx_inject_irq(vcpu, vcpu->arch.interrupt.nr);
3349 if (kvm_cpu_has_interrupt(vcpu))
3350 enable_irq_window(vcpu);
3351 }
3352 }
3353
3354 /*
3355 * Failure to inject an interrupt should give us the information
3356 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3357 * when fetching the interrupt redirection bitmap in the real-mode
3358 * tss, this doesn't happen. So we do it ourselves.
3359 */
3360 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3361 {
3362 vmx->rmode.irq.pending = 0;
3363 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3364 return;
3365 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3366 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3367 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3368 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3369 return;
3370 }
3371 vmx->idt_vectoring_info =
3372 VECTORING_INFO_VALID_MASK
3373 | INTR_TYPE_EXT_INTR
3374 | vmx->rmode.irq.vector;
3375 }
3376
3377 #ifdef CONFIG_X86_64
3378 #define R "r"
3379 #define Q "q"
3380 #else
3381 #define R "e"
3382 #define Q "l"
3383 #endif
3384
3385 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3386 {
3387 struct vcpu_vmx *vmx = to_vmx(vcpu);
3388 u32 intr_info;
3389
3390 /* Record the guest's net vcpu time for enforced NMI injections. */
3391 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3392 vmx->entry_time = ktime_get();
3393
3394 /* Handle invalid guest state instead of entering VMX */
3395 if (vmx->emulation_required && emulate_invalid_guest_state) {
3396 handle_invalid_guest_state(vcpu, kvm_run);
3397 return;
3398 }
3399
3400 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3401 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3402 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3403 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3404
3405 /*
3406 * Loading guest fpu may have cleared host cr0.ts
3407 */
3408 vmcs_writel(HOST_CR0, read_cr0());
3409
3410 set_debugreg(vcpu->arch.dr6, 6);
3411
3412 asm(
3413 /* Store host registers */
3414 "push %%"R"dx; push %%"R"bp;"
3415 "push %%"R"cx \n\t"
3416 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3417 "je 1f \n\t"
3418 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3419 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3420 "1: \n\t"
3421 /* Check if vmlaunch of vmresume is needed */
3422 "cmpl $0, %c[launched](%0) \n\t"
3423 /* Load guest registers. Don't clobber flags. */
3424 "mov %c[cr2](%0), %%"R"ax \n\t"
3425 "mov %%"R"ax, %%cr2 \n\t"
3426 "mov %c[rax](%0), %%"R"ax \n\t"
3427 "mov %c[rbx](%0), %%"R"bx \n\t"
3428 "mov %c[rdx](%0), %%"R"dx \n\t"
3429 "mov %c[rsi](%0), %%"R"si \n\t"
3430 "mov %c[rdi](%0), %%"R"di \n\t"
3431 "mov %c[rbp](%0), %%"R"bp \n\t"
3432 #ifdef CONFIG_X86_64
3433 "mov %c[r8](%0), %%r8 \n\t"
3434 "mov %c[r9](%0), %%r9 \n\t"
3435 "mov %c[r10](%0), %%r10 \n\t"
3436 "mov %c[r11](%0), %%r11 \n\t"
3437 "mov %c[r12](%0), %%r12 \n\t"
3438 "mov %c[r13](%0), %%r13 \n\t"
3439 "mov %c[r14](%0), %%r14 \n\t"
3440 "mov %c[r15](%0), %%r15 \n\t"
3441 #endif
3442 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3443
3444 /* Enter guest mode */
3445 "jne .Llaunched \n\t"
3446 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3447 "jmp .Lkvm_vmx_return \n\t"
3448 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3449 ".Lkvm_vmx_return: "
3450 /* Save guest registers, load host registers, keep flags */
3451 "xchg %0, (%%"R"sp) \n\t"
3452 "mov %%"R"ax, %c[rax](%0) \n\t"
3453 "mov %%"R"bx, %c[rbx](%0) \n\t"
3454 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3455 "mov %%"R"dx, %c[rdx](%0) \n\t"
3456 "mov %%"R"si, %c[rsi](%0) \n\t"
3457 "mov %%"R"di, %c[rdi](%0) \n\t"
3458 "mov %%"R"bp, %c[rbp](%0) \n\t"
3459 #ifdef CONFIG_X86_64
3460 "mov %%r8, %c[r8](%0) \n\t"
3461 "mov %%r9, %c[r9](%0) \n\t"
3462 "mov %%r10, %c[r10](%0) \n\t"
3463 "mov %%r11, %c[r11](%0) \n\t"
3464 "mov %%r12, %c[r12](%0) \n\t"
3465 "mov %%r13, %c[r13](%0) \n\t"
3466 "mov %%r14, %c[r14](%0) \n\t"
3467 "mov %%r15, %c[r15](%0) \n\t"
3468 #endif
3469 "mov %%cr2, %%"R"ax \n\t"
3470 "mov %%"R"ax, %c[cr2](%0) \n\t"
3471
3472 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3473 "setbe %c[fail](%0) \n\t"
3474 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3475 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3476 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3477 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3478 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3479 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3480 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3481 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3482 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3483 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3484 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3485 #ifdef CONFIG_X86_64
3486 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3487 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3488 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3489 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3490 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3491 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3492 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3493 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3494 #endif
3495 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3496 : "cc", "memory"
3497 , R"bx", R"di", R"si"
3498 #ifdef CONFIG_X86_64
3499 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3500 #endif
3501 );
3502
3503 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3504 vcpu->arch.regs_dirty = 0;
3505
3506 get_debugreg(vcpu->arch.dr6, 6);
3507
3508 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3509 if (vmx->rmode.irq.pending)
3510 fixup_rmode_irq(vmx);
3511
3512 vmx_update_window_states(vcpu);
3513
3514 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3515 vmx->launched = 1;
3516
3517 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3518
3519 /* We need to handle NMIs before interrupts are enabled */
3520 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3521 (intr_info & INTR_INFO_VALID_MASK)) {
3522 KVMTRACE_0D(NMI, vcpu, handler);
3523 asm("int $2");
3524 }
3525
3526 vmx_complete_interrupts(vmx);
3527 }
3528
3529 #undef R
3530 #undef Q
3531
3532 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3533 {
3534 struct vcpu_vmx *vmx = to_vmx(vcpu);
3535
3536 if (vmx->vmcs) {
3537 vcpu_clear(vmx);
3538 free_vmcs(vmx->vmcs);
3539 vmx->vmcs = NULL;
3540 }
3541 }
3542
3543 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3544 {
3545 struct vcpu_vmx *vmx = to_vmx(vcpu);
3546
3547 spin_lock(&vmx_vpid_lock);
3548 if (vmx->vpid != 0)
3549 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3550 spin_unlock(&vmx_vpid_lock);
3551 vmx_free_vmcs(vcpu);
3552 kfree(vmx->host_msrs);
3553 kfree(vmx->guest_msrs);
3554 kvm_vcpu_uninit(vcpu);
3555 kmem_cache_free(kvm_vcpu_cache, vmx);
3556 }
3557
3558 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3559 {
3560 int err;
3561 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3562 int cpu;
3563
3564 if (!vmx)
3565 return ERR_PTR(-ENOMEM);
3566
3567 allocate_vpid(vmx);
3568
3569 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3570 if (err)
3571 goto free_vcpu;
3572
3573 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3574 if (!vmx->guest_msrs) {
3575 err = -ENOMEM;
3576 goto uninit_vcpu;
3577 }
3578
3579 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3580 if (!vmx->host_msrs)
3581 goto free_guest_msrs;
3582
3583 vmx->vmcs = alloc_vmcs();
3584 if (!vmx->vmcs)
3585 goto free_msrs;
3586
3587 vmcs_clear(vmx->vmcs);
3588
3589 cpu = get_cpu();
3590 vmx_vcpu_load(&vmx->vcpu, cpu);
3591 err = vmx_vcpu_setup(vmx);
3592 vmx_vcpu_put(&vmx->vcpu);
3593 put_cpu();
3594 if (err)
3595 goto free_vmcs;
3596 if (vm_need_virtualize_apic_accesses(kvm))
3597 if (alloc_apic_access_page(kvm) != 0)
3598 goto free_vmcs;
3599
3600 if (enable_ept)
3601 if (alloc_identity_pagetable(kvm) != 0)
3602 goto free_vmcs;
3603
3604 return &vmx->vcpu;
3605
3606 free_vmcs:
3607 free_vmcs(vmx->vmcs);
3608 free_msrs:
3609 kfree(vmx->host_msrs);
3610 free_guest_msrs:
3611 kfree(vmx->guest_msrs);
3612 uninit_vcpu:
3613 kvm_vcpu_uninit(&vmx->vcpu);
3614 free_vcpu:
3615 kmem_cache_free(kvm_vcpu_cache, vmx);
3616 return ERR_PTR(err);
3617 }
3618
3619 static void __init vmx_check_processor_compat(void *rtn)
3620 {
3621 struct vmcs_config vmcs_conf;
3622
3623 *(int *)rtn = 0;
3624 if (setup_vmcs_config(&vmcs_conf) < 0)
3625 *(int *)rtn = -EIO;
3626 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3627 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3628 smp_processor_id());
3629 *(int *)rtn = -EIO;
3630 }
3631 }
3632
3633 static int get_ept_level(void)
3634 {
3635 return VMX_EPT_DEFAULT_GAW + 1;
3636 }
3637
3638 static int vmx_get_mt_mask_shift(void)
3639 {
3640 return VMX_EPT_MT_EPTE_SHIFT;
3641 }
3642
3643 static struct kvm_x86_ops vmx_x86_ops = {
3644 .cpu_has_kvm_support = cpu_has_kvm_support,
3645 .disabled_by_bios = vmx_disabled_by_bios,
3646 .hardware_setup = hardware_setup,
3647 .hardware_unsetup = hardware_unsetup,
3648 .check_processor_compatibility = vmx_check_processor_compat,
3649 .hardware_enable = hardware_enable,
3650 .hardware_disable = hardware_disable,
3651 .cpu_has_accelerated_tpr = cpu_has_vmx_virtualize_apic_accesses,
3652
3653 .vcpu_create = vmx_create_vcpu,
3654 .vcpu_free = vmx_free_vcpu,
3655 .vcpu_reset = vmx_vcpu_reset,
3656
3657 .prepare_guest_switch = vmx_save_host_state,
3658 .vcpu_load = vmx_vcpu_load,
3659 .vcpu_put = vmx_vcpu_put,
3660
3661 .set_guest_debug = set_guest_debug,
3662 .get_msr = vmx_get_msr,
3663 .set_msr = vmx_set_msr,
3664 .get_segment_base = vmx_get_segment_base,
3665 .get_segment = vmx_get_segment,
3666 .set_segment = vmx_set_segment,
3667 .get_cpl = vmx_get_cpl,
3668 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3669 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3670 .set_cr0 = vmx_set_cr0,
3671 .set_cr3 = vmx_set_cr3,
3672 .set_cr4 = vmx_set_cr4,
3673 .set_efer = vmx_set_efer,
3674 .get_idt = vmx_get_idt,
3675 .set_idt = vmx_set_idt,
3676 .get_gdt = vmx_get_gdt,
3677 .set_gdt = vmx_set_gdt,
3678 .cache_reg = vmx_cache_reg,
3679 .get_rflags = vmx_get_rflags,
3680 .set_rflags = vmx_set_rflags,
3681
3682 .tlb_flush = vmx_flush_tlb,
3683
3684 .run = vmx_vcpu_run,
3685 .handle_exit = vmx_handle_exit,
3686 .skip_emulated_instruction = skip_emulated_instruction,
3687 .patch_hypercall = vmx_patch_hypercall,
3688 .get_irq = vmx_get_irq,
3689 .set_irq = vmx_inject_irq,
3690 .queue_exception = vmx_queue_exception,
3691 .exception_injected = vmx_exception_injected,
3692 .inject_pending_irq = vmx_intr_assist,
3693 .inject_pending_vectors = do_interrupt_requests,
3694
3695 .set_tss_addr = vmx_set_tss_addr,
3696 .get_tdp_level = get_ept_level,
3697 .get_mt_mask_shift = vmx_get_mt_mask_shift,
3698 };
3699
3700 static int __init vmx_init(void)
3701 {
3702 int r;
3703
3704 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3705 if (!vmx_io_bitmap_a)
3706 return -ENOMEM;
3707
3708 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3709 if (!vmx_io_bitmap_b) {
3710 r = -ENOMEM;
3711 goto out;
3712 }
3713
3714 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3715 if (!vmx_msr_bitmap_legacy) {
3716 r = -ENOMEM;
3717 goto out1;
3718 }
3719
3720 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3721 if (!vmx_msr_bitmap_longmode) {
3722 r = -ENOMEM;
3723 goto out2;
3724 }
3725
3726 /*
3727 * Allow direct access to the PC debug port (it is often used for I/O
3728 * delays, but the vmexits simply slow things down).
3729 */
3730 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3731 clear_bit(0x80, vmx_io_bitmap_a);
3732
3733 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3734
3735 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3736 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3737
3738 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3739
3740 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3741 if (r)
3742 goto out3;
3743
3744 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3745 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3746 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3747 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3748 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3749 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3750
3751 if (enable_ept) {
3752 bypass_guest_pf = 0;
3753 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
3754 VMX_EPT_WRITABLE_MASK);
3755 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
3756 VMX_EPT_EXECUTABLE_MASK,
3757 VMX_EPT_DEFAULT_MT << VMX_EPT_MT_EPTE_SHIFT);
3758 kvm_enable_tdp();
3759 } else
3760 kvm_disable_tdp();
3761
3762 if (bypass_guest_pf)
3763 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
3764
3765 ept_sync_global();
3766
3767 return 0;
3768
3769 out3:
3770 free_page((unsigned long)vmx_msr_bitmap_longmode);
3771 out2:
3772 free_page((unsigned long)vmx_msr_bitmap_legacy);
3773 out1:
3774 free_page((unsigned long)vmx_io_bitmap_b);
3775 out:
3776 free_page((unsigned long)vmx_io_bitmap_a);
3777 return r;
3778 }
3779
3780 static void __exit vmx_exit(void)
3781 {
3782 free_page((unsigned long)vmx_msr_bitmap_legacy);
3783 free_page((unsigned long)vmx_msr_bitmap_longmode);
3784 free_page((unsigned long)vmx_io_bitmap_b);
3785 free_page((unsigned long)vmx_io_bitmap_a);
3786
3787 kvm_exit();
3788 }
3789
3790 module_init(vmx_init)
3791 module_exit(vmx_exit)
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