2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
52 #define __ex(x) __kvm_handle_fault_on_reboot(x)
53 #define __ex_clear(x, reg) \
54 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
56 MODULE_AUTHOR("Qumranet");
57 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id vmx_cpu_id
[] = {
60 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
63 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
65 static bool __read_mostly enable_vpid
= 1;
66 module_param_named(vpid
, enable_vpid
, bool, 0444);
68 static bool __read_mostly flexpriority_enabled
= 1;
69 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
71 static bool __read_mostly enable_ept
= 1;
72 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
74 static bool __read_mostly enable_unrestricted_guest
= 1;
75 module_param_named(unrestricted_guest
,
76 enable_unrestricted_guest
, bool, S_IRUGO
);
78 static bool __read_mostly enable_ept_ad_bits
= 1;
79 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
81 static bool __read_mostly emulate_invalid_guest_state
= true;
82 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
84 static bool __read_mostly vmm_exclusive
= 1;
85 module_param(vmm_exclusive
, bool, S_IRUGO
);
87 static bool __read_mostly fasteoi
= 1;
88 module_param(fasteoi
, bool, S_IRUGO
);
90 static bool __read_mostly enable_apicv
= 1;
91 module_param(enable_apicv
, bool, S_IRUGO
);
93 static bool __read_mostly enable_shadow_vmcs
= 1;
94 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
96 * If nested=1, nested virtualization is supported, i.e., guests may use
97 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
98 * use VMX instructions.
100 static bool __read_mostly nested
= 0;
101 module_param(nested
, bool, S_IRUGO
);
103 static u64 __read_mostly host_xss
;
105 static bool __read_mostly enable_pml
= 1;
106 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
108 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
109 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
110 #define KVM_VM_CR0_ALWAYS_ON \
111 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
112 #define KVM_CR4_GUEST_OWNED_BITS \
113 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
114 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
116 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
117 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
119 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
121 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
124 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
125 * ple_gap: upper bound on the amount of time between two successive
126 * executions of PAUSE in a loop. Also indicate if ple enabled.
127 * According to test, this time is usually smaller than 128 cycles.
128 * ple_window: upper bound on the amount of time a guest is allowed to execute
129 * in a PAUSE loop. Tests indicate that most spinlocks are held for
130 * less than 2^12 cycles
131 * Time is measured based on a counter that runs at the same rate as the TSC,
132 * refer SDM volume 3b section 21.6.13 & 22.1.3.
134 #define KVM_VMX_DEFAULT_PLE_GAP 128
135 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
136 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
137 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
138 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
139 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
141 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
142 module_param(ple_gap
, int, S_IRUGO
);
144 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
145 module_param(ple_window
, int, S_IRUGO
);
147 /* Default doubles per-vcpu window every exit. */
148 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
149 module_param(ple_window_grow
, int, S_IRUGO
);
151 /* Default resets per-vcpu window every exit to ple_window. */
152 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
153 module_param(ple_window_shrink
, int, S_IRUGO
);
155 /* Default is to compute the maximum so we can never overflow. */
156 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
157 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
158 module_param(ple_window_max
, int, S_IRUGO
);
160 extern const ulong vmx_return
;
162 #define NR_AUTOLOAD_MSRS 8
163 #define VMCS02_POOL_SIZE 1
172 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
173 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
174 * loaded on this CPU (so we can clear them if the CPU goes down).
180 struct list_head loaded_vmcss_on_cpu_link
;
183 struct shared_msr_entry
{
190 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
191 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
192 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
193 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
194 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
195 * More than one of these structures may exist, if L1 runs multiple L2 guests.
196 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
197 * underlying hardware which will be used to run L2.
198 * This structure is packed to ensure that its layout is identical across
199 * machines (necessary for live migration).
200 * If there are changes in this struct, VMCS12_REVISION must be changed.
202 typedef u64 natural_width
;
203 struct __packed vmcs12
{
204 /* According to the Intel spec, a VMCS region must start with the
205 * following two fields. Then follow implementation-specific data.
210 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
211 u32 padding
[7]; /* room for future expansion */
216 u64 vm_exit_msr_store_addr
;
217 u64 vm_exit_msr_load_addr
;
218 u64 vm_entry_msr_load_addr
;
220 u64 virtual_apic_page_addr
;
221 u64 apic_access_addr
;
222 u64 posted_intr_desc_addr
;
224 u64 eoi_exit_bitmap0
;
225 u64 eoi_exit_bitmap1
;
226 u64 eoi_exit_bitmap2
;
227 u64 eoi_exit_bitmap3
;
229 u64 guest_physical_address
;
230 u64 vmcs_link_pointer
;
231 u64 guest_ia32_debugctl
;
234 u64 guest_ia32_perf_global_ctrl
;
242 u64 host_ia32_perf_global_ctrl
;
243 u64 padding64
[8]; /* room for future expansion */
245 * To allow migration of L1 (complete with its L2 guests) between
246 * machines of different natural widths (32 or 64 bit), we cannot have
247 * unsigned long fields with no explict size. We use u64 (aliased
248 * natural_width) instead. Luckily, x86 is little-endian.
250 natural_width cr0_guest_host_mask
;
251 natural_width cr4_guest_host_mask
;
252 natural_width cr0_read_shadow
;
253 natural_width cr4_read_shadow
;
254 natural_width cr3_target_value0
;
255 natural_width cr3_target_value1
;
256 natural_width cr3_target_value2
;
257 natural_width cr3_target_value3
;
258 natural_width exit_qualification
;
259 natural_width guest_linear_address
;
260 natural_width guest_cr0
;
261 natural_width guest_cr3
;
262 natural_width guest_cr4
;
263 natural_width guest_es_base
;
264 natural_width guest_cs_base
;
265 natural_width guest_ss_base
;
266 natural_width guest_ds_base
;
267 natural_width guest_fs_base
;
268 natural_width guest_gs_base
;
269 natural_width guest_ldtr_base
;
270 natural_width guest_tr_base
;
271 natural_width guest_gdtr_base
;
272 natural_width guest_idtr_base
;
273 natural_width guest_dr7
;
274 natural_width guest_rsp
;
275 natural_width guest_rip
;
276 natural_width guest_rflags
;
277 natural_width guest_pending_dbg_exceptions
;
278 natural_width guest_sysenter_esp
;
279 natural_width guest_sysenter_eip
;
280 natural_width host_cr0
;
281 natural_width host_cr3
;
282 natural_width host_cr4
;
283 natural_width host_fs_base
;
284 natural_width host_gs_base
;
285 natural_width host_tr_base
;
286 natural_width host_gdtr_base
;
287 natural_width host_idtr_base
;
288 natural_width host_ia32_sysenter_esp
;
289 natural_width host_ia32_sysenter_eip
;
290 natural_width host_rsp
;
291 natural_width host_rip
;
292 natural_width paddingl
[8]; /* room for future expansion */
293 u32 pin_based_vm_exec_control
;
294 u32 cpu_based_vm_exec_control
;
295 u32 exception_bitmap
;
296 u32 page_fault_error_code_mask
;
297 u32 page_fault_error_code_match
;
298 u32 cr3_target_count
;
299 u32 vm_exit_controls
;
300 u32 vm_exit_msr_store_count
;
301 u32 vm_exit_msr_load_count
;
302 u32 vm_entry_controls
;
303 u32 vm_entry_msr_load_count
;
304 u32 vm_entry_intr_info_field
;
305 u32 vm_entry_exception_error_code
;
306 u32 vm_entry_instruction_len
;
308 u32 secondary_vm_exec_control
;
309 u32 vm_instruction_error
;
311 u32 vm_exit_intr_info
;
312 u32 vm_exit_intr_error_code
;
313 u32 idt_vectoring_info_field
;
314 u32 idt_vectoring_error_code
;
315 u32 vm_exit_instruction_len
;
316 u32 vmx_instruction_info
;
323 u32 guest_ldtr_limit
;
325 u32 guest_gdtr_limit
;
326 u32 guest_idtr_limit
;
327 u32 guest_es_ar_bytes
;
328 u32 guest_cs_ar_bytes
;
329 u32 guest_ss_ar_bytes
;
330 u32 guest_ds_ar_bytes
;
331 u32 guest_fs_ar_bytes
;
332 u32 guest_gs_ar_bytes
;
333 u32 guest_ldtr_ar_bytes
;
334 u32 guest_tr_ar_bytes
;
335 u32 guest_interruptibility_info
;
336 u32 guest_activity_state
;
337 u32 guest_sysenter_cs
;
338 u32 host_ia32_sysenter_cs
;
339 u32 vmx_preemption_timer_value
;
340 u32 padding32
[7]; /* room for future expansion */
341 u16 virtual_processor_id
;
343 u16 guest_es_selector
;
344 u16 guest_cs_selector
;
345 u16 guest_ss_selector
;
346 u16 guest_ds_selector
;
347 u16 guest_fs_selector
;
348 u16 guest_gs_selector
;
349 u16 guest_ldtr_selector
;
350 u16 guest_tr_selector
;
351 u16 guest_intr_status
;
352 u16 host_es_selector
;
353 u16 host_cs_selector
;
354 u16 host_ss_selector
;
355 u16 host_ds_selector
;
356 u16 host_fs_selector
;
357 u16 host_gs_selector
;
358 u16 host_tr_selector
;
362 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
363 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
364 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
366 #define VMCS12_REVISION 0x11e57ed0
369 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
370 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
371 * current implementation, 4K are reserved to avoid future complications.
373 #define VMCS12_SIZE 0x1000
375 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
377 struct list_head list
;
379 struct loaded_vmcs vmcs02
;
383 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
384 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
387 /* Has the level1 guest done vmxon? */
391 /* The guest-physical address of the current VMCS L1 keeps for L2 */
393 /* The host-usable pointer to the above */
394 struct page
*current_vmcs12_page
;
395 struct vmcs12
*current_vmcs12
;
396 struct vmcs
*current_shadow_vmcs
;
398 * Indicates if the shadow vmcs must be updated with the
399 * data hold by vmcs12
401 bool sync_shadow_vmcs
;
403 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
404 struct list_head vmcs02_pool
;
406 u64 vmcs01_tsc_offset
;
407 /* L2 must run next, and mustn't decide to exit to L1. */
408 bool nested_run_pending
;
410 * Guest pages referred to in vmcs02 with host-physical pointers, so
411 * we must keep them pinned while L2 runs.
413 struct page
*apic_access_page
;
414 struct page
*virtual_apic_page
;
415 struct page
*pi_desc_page
;
416 struct pi_desc
*pi_desc
;
419 u64 msr_ia32_feature_control
;
421 struct hrtimer preemption_timer
;
422 bool preemption_timer_expired
;
424 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
427 u32 nested_vmx_procbased_ctls_low
;
428 u32 nested_vmx_procbased_ctls_high
;
429 u32 nested_vmx_true_procbased_ctls_low
;
430 u32 nested_vmx_secondary_ctls_low
;
431 u32 nested_vmx_secondary_ctls_high
;
432 u32 nested_vmx_pinbased_ctls_low
;
433 u32 nested_vmx_pinbased_ctls_high
;
434 u32 nested_vmx_exit_ctls_low
;
435 u32 nested_vmx_exit_ctls_high
;
436 u32 nested_vmx_true_exit_ctls_low
;
437 u32 nested_vmx_entry_ctls_low
;
438 u32 nested_vmx_entry_ctls_high
;
439 u32 nested_vmx_true_entry_ctls_low
;
440 u32 nested_vmx_misc_low
;
441 u32 nested_vmx_misc_high
;
442 u32 nested_vmx_ept_caps
;
445 #define POSTED_INTR_ON 0
446 /* Posted-Interrupt Descriptor */
448 u32 pir
[8]; /* Posted interrupt requested */
449 u32 control
; /* bit 0 of control is outstanding notification bit */
453 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
455 return test_and_set_bit(POSTED_INTR_ON
,
456 (unsigned long *)&pi_desc
->control
);
459 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
461 return test_and_clear_bit(POSTED_INTR_ON
,
462 (unsigned long *)&pi_desc
->control
);
465 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
467 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
471 struct kvm_vcpu vcpu
;
472 unsigned long host_rsp
;
474 bool nmi_known_unmasked
;
476 u32 idt_vectoring_info
;
478 struct shared_msr_entry
*guest_msrs
;
481 unsigned long host_idt_base
;
483 u64 msr_host_kernel_gs_base
;
484 u64 msr_guest_kernel_gs_base
;
486 u32 vm_entry_controls_shadow
;
487 u32 vm_exit_controls_shadow
;
489 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
490 * non-nested (L1) guest, it always points to vmcs01. For a nested
491 * guest (L2), it points to a different VMCS.
493 struct loaded_vmcs vmcs01
;
494 struct loaded_vmcs
*loaded_vmcs
;
495 bool __launched
; /* temporary, used in vmx_vcpu_run */
496 struct msr_autoload
{
498 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
499 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
503 u16 fs_sel
, gs_sel
, ldt_sel
;
507 int gs_ldt_reload_needed
;
508 int fs_reload_needed
;
509 u64 msr_host_bndcfgs
;
510 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
515 struct kvm_segment segs
[8];
518 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
519 struct kvm_save_segment
{
527 bool emulation_required
;
529 /* Support for vnmi-less CPUs */
530 int soft_vnmi_blocked
;
532 s64 vnmi_blocked_time
;
537 /* Posted interrupt descriptor */
538 struct pi_desc pi_desc
;
540 /* Support for a guest hypervisor (nested VMX) */
541 struct nested_vmx nested
;
543 /* Dynamic PLE window. */
545 bool ple_window_dirty
;
547 /* Support for PML */
548 #define PML_ENTITY_NUM 512
552 enum segment_cache_field
{
561 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
563 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
566 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
567 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
568 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
569 [number##_HIGH] = VMCS12_OFFSET(name)+4
572 static unsigned long shadow_read_only_fields
[] = {
574 * We do NOT shadow fields that are modified when L0
575 * traps and emulates any vmx instruction (e.g. VMPTRLD,
576 * VMXON...) executed by L1.
577 * For example, VM_INSTRUCTION_ERROR is read
578 * by L1 if a vmx instruction fails (part of the error path).
579 * Note the code assumes this logic. If for some reason
580 * we start shadowing these fields then we need to
581 * force a shadow sync when L0 emulates vmx instructions
582 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
583 * by nested_vmx_failValid)
587 VM_EXIT_INSTRUCTION_LEN
,
588 IDT_VECTORING_INFO_FIELD
,
589 IDT_VECTORING_ERROR_CODE
,
590 VM_EXIT_INTR_ERROR_CODE
,
592 GUEST_LINEAR_ADDRESS
,
593 GUEST_PHYSICAL_ADDRESS
595 static int max_shadow_read_only_fields
=
596 ARRAY_SIZE(shadow_read_only_fields
);
598 static unsigned long shadow_read_write_fields
[] = {
605 GUEST_INTERRUPTIBILITY_INFO
,
618 CPU_BASED_VM_EXEC_CONTROL
,
619 VM_ENTRY_EXCEPTION_ERROR_CODE
,
620 VM_ENTRY_INTR_INFO_FIELD
,
621 VM_ENTRY_INSTRUCTION_LEN
,
622 VM_ENTRY_EXCEPTION_ERROR_CODE
,
628 static int max_shadow_read_write_fields
=
629 ARRAY_SIZE(shadow_read_write_fields
);
631 static const unsigned short vmcs_field_to_offset_table
[] = {
632 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
633 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
634 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
635 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
636 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
637 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
638 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
639 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
640 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
641 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
642 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
643 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
644 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
645 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
646 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
647 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
648 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
649 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
650 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
651 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
652 FIELD64(MSR_BITMAP
, msr_bitmap
),
653 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
654 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
655 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
656 FIELD64(TSC_OFFSET
, tsc_offset
),
657 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
658 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
659 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
660 FIELD64(EPT_POINTER
, ept_pointer
),
661 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
662 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
663 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
664 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
665 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
666 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
667 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
668 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
669 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
670 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
671 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
672 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
673 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
674 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
675 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
676 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
677 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
678 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
679 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
680 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
681 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
682 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
683 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
684 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
685 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
686 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
687 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
688 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
689 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
690 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
691 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
692 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
693 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
694 FIELD(TPR_THRESHOLD
, tpr_threshold
),
695 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
696 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
697 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
698 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
699 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
700 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
701 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
702 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
703 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
704 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
705 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
706 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
707 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
708 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
709 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
710 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
711 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
712 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
713 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
714 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
715 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
716 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
717 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
718 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
719 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
720 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
721 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
722 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
723 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
724 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
725 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
726 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
727 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
728 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
729 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
730 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
731 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
732 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
733 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
734 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
735 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
736 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
737 FIELD(GUEST_CR0
, guest_cr0
),
738 FIELD(GUEST_CR3
, guest_cr3
),
739 FIELD(GUEST_CR4
, guest_cr4
),
740 FIELD(GUEST_ES_BASE
, guest_es_base
),
741 FIELD(GUEST_CS_BASE
, guest_cs_base
),
742 FIELD(GUEST_SS_BASE
, guest_ss_base
),
743 FIELD(GUEST_DS_BASE
, guest_ds_base
),
744 FIELD(GUEST_FS_BASE
, guest_fs_base
),
745 FIELD(GUEST_GS_BASE
, guest_gs_base
),
746 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
747 FIELD(GUEST_TR_BASE
, guest_tr_base
),
748 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
749 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
750 FIELD(GUEST_DR7
, guest_dr7
),
751 FIELD(GUEST_RSP
, guest_rsp
),
752 FIELD(GUEST_RIP
, guest_rip
),
753 FIELD(GUEST_RFLAGS
, guest_rflags
),
754 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
755 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
756 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
757 FIELD(HOST_CR0
, host_cr0
),
758 FIELD(HOST_CR3
, host_cr3
),
759 FIELD(HOST_CR4
, host_cr4
),
760 FIELD(HOST_FS_BASE
, host_fs_base
),
761 FIELD(HOST_GS_BASE
, host_gs_base
),
762 FIELD(HOST_TR_BASE
, host_tr_base
),
763 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
764 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
765 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
766 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
767 FIELD(HOST_RSP
, host_rsp
),
768 FIELD(HOST_RIP
, host_rip
),
771 static inline short vmcs_field_to_offset(unsigned long field
)
773 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
775 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
776 vmcs_field_to_offset_table
[field
] == 0)
779 return vmcs_field_to_offset_table
[field
];
782 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
784 return to_vmx(vcpu
)->nested
.current_vmcs12
;
787 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
789 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
790 if (is_error_page(page
))
796 static void nested_release_page(struct page
*page
)
798 kvm_release_page_dirty(page
);
801 static void nested_release_page_clean(struct page
*page
)
803 kvm_release_page_clean(page
);
806 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
807 static u64
construct_eptp(unsigned long root_hpa
);
808 static void kvm_cpu_vmxon(u64 addr
);
809 static void kvm_cpu_vmxoff(void);
810 static bool vmx_mpx_supported(void);
811 static bool vmx_xsaves_supported(void);
812 static int vmx_vm_has_apicv(struct kvm
*kvm
);
813 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
814 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
815 struct kvm_segment
*var
, int seg
);
816 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
817 struct kvm_segment
*var
, int seg
);
818 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
819 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
820 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
821 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
822 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
823 static int alloc_identity_pagetable(struct kvm
*kvm
);
825 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
826 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
828 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
829 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
831 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
832 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
834 static unsigned long *vmx_io_bitmap_a
;
835 static unsigned long *vmx_io_bitmap_b
;
836 static unsigned long *vmx_msr_bitmap_legacy
;
837 static unsigned long *vmx_msr_bitmap_longmode
;
838 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
839 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
840 static unsigned long *vmx_msr_bitmap_nested
;
841 static unsigned long *vmx_vmread_bitmap
;
842 static unsigned long *vmx_vmwrite_bitmap
;
844 static bool cpu_has_load_ia32_efer
;
845 static bool cpu_has_load_perf_global_ctrl
;
847 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
848 static DEFINE_SPINLOCK(vmx_vpid_lock
);
850 static struct vmcs_config
{
854 u32 pin_based_exec_ctrl
;
855 u32 cpu_based_exec_ctrl
;
856 u32 cpu_based_2nd_exec_ctrl
;
861 static struct vmx_capability
{
866 #define VMX_SEGMENT_FIELD(seg) \
867 [VCPU_SREG_##seg] = { \
868 .selector = GUEST_##seg##_SELECTOR, \
869 .base = GUEST_##seg##_BASE, \
870 .limit = GUEST_##seg##_LIMIT, \
871 .ar_bytes = GUEST_##seg##_AR_BYTES, \
874 static const struct kvm_vmx_segment_field
{
879 } kvm_vmx_segment_fields
[] = {
880 VMX_SEGMENT_FIELD(CS
),
881 VMX_SEGMENT_FIELD(DS
),
882 VMX_SEGMENT_FIELD(ES
),
883 VMX_SEGMENT_FIELD(FS
),
884 VMX_SEGMENT_FIELD(GS
),
885 VMX_SEGMENT_FIELD(SS
),
886 VMX_SEGMENT_FIELD(TR
),
887 VMX_SEGMENT_FIELD(LDTR
),
890 static u64 host_efer
;
892 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
895 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
896 * away by decrementing the array size.
898 static const u32 vmx_msr_index
[] = {
900 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
902 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
905 static inline bool is_page_fault(u32 intr_info
)
907 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
908 INTR_INFO_VALID_MASK
)) ==
909 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
912 static inline bool is_no_device(u32 intr_info
)
914 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
915 INTR_INFO_VALID_MASK
)) ==
916 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
919 static inline bool is_invalid_opcode(u32 intr_info
)
921 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
922 INTR_INFO_VALID_MASK
)) ==
923 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
926 static inline bool is_external_interrupt(u32 intr_info
)
928 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
929 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
932 static inline bool is_machine_check(u32 intr_info
)
934 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
935 INTR_INFO_VALID_MASK
)) ==
936 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
939 static inline bool cpu_has_vmx_msr_bitmap(void)
941 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
944 static inline bool cpu_has_vmx_tpr_shadow(void)
946 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
949 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
951 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
954 static inline bool cpu_has_secondary_exec_ctrls(void)
956 return vmcs_config
.cpu_based_exec_ctrl
&
957 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
960 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
962 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
963 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
966 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
968 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
969 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
972 static inline bool cpu_has_vmx_apic_register_virt(void)
974 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
975 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
978 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
980 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
981 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
984 static inline bool cpu_has_vmx_posted_intr(void)
986 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
989 static inline bool cpu_has_vmx_apicv(void)
991 return cpu_has_vmx_apic_register_virt() &&
992 cpu_has_vmx_virtual_intr_delivery() &&
993 cpu_has_vmx_posted_intr();
996 static inline bool cpu_has_vmx_flexpriority(void)
998 return cpu_has_vmx_tpr_shadow() &&
999 cpu_has_vmx_virtualize_apic_accesses();
1002 static inline bool cpu_has_vmx_ept_execute_only(void)
1004 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1007 static inline bool cpu_has_vmx_ept_2m_page(void)
1009 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1012 static inline bool cpu_has_vmx_ept_1g_page(void)
1014 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1017 static inline bool cpu_has_vmx_ept_4levels(void)
1019 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1022 static inline bool cpu_has_vmx_ept_ad_bits(void)
1024 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1027 static inline bool cpu_has_vmx_invept_context(void)
1029 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1032 static inline bool cpu_has_vmx_invept_global(void)
1034 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1037 static inline bool cpu_has_vmx_invvpid_single(void)
1039 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1042 static inline bool cpu_has_vmx_invvpid_global(void)
1044 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1047 static inline bool cpu_has_vmx_ept(void)
1049 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1050 SECONDARY_EXEC_ENABLE_EPT
;
1053 static inline bool cpu_has_vmx_unrestricted_guest(void)
1055 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1056 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1059 static inline bool cpu_has_vmx_ple(void)
1061 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1062 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1065 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
1067 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1070 static inline bool cpu_has_vmx_vpid(void)
1072 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1073 SECONDARY_EXEC_ENABLE_VPID
;
1076 static inline bool cpu_has_vmx_rdtscp(void)
1078 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1079 SECONDARY_EXEC_RDTSCP
;
1082 static inline bool cpu_has_vmx_invpcid(void)
1084 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1085 SECONDARY_EXEC_ENABLE_INVPCID
;
1088 static inline bool cpu_has_virtual_nmis(void)
1090 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1093 static inline bool cpu_has_vmx_wbinvd_exit(void)
1095 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1096 SECONDARY_EXEC_WBINVD_EXITING
;
1099 static inline bool cpu_has_vmx_shadow_vmcs(void)
1102 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1103 /* check if the cpu supports writing r/o exit information fields */
1104 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1107 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1108 SECONDARY_EXEC_SHADOW_VMCS
;
1111 static inline bool cpu_has_vmx_pml(void)
1113 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1116 static inline bool report_flexpriority(void)
1118 return flexpriority_enabled
;
1121 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1123 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1126 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1128 return (vmcs12
->cpu_based_vm_exec_control
&
1129 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1130 (vmcs12
->secondary_vm_exec_control
& bit
);
1133 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1135 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1138 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1140 return vmcs12
->pin_based_vm_exec_control
&
1141 PIN_BASED_VMX_PREEMPTION_TIMER
;
1144 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1146 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1149 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1151 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1152 vmx_xsaves_supported();
1155 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1157 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1160 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1162 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1165 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1167 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1170 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1172 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1175 static inline bool is_exception(u32 intr_info
)
1177 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1178 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1181 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1183 unsigned long exit_qualification
);
1184 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1185 struct vmcs12
*vmcs12
,
1186 u32 reason
, unsigned long qualification
);
1188 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1192 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1193 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1198 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1204 } operand
= { vpid
, 0, gva
};
1206 asm volatile (__ex(ASM_VMX_INVVPID
)
1207 /* CF==1 or ZF==1 --> rc = -1 */
1208 "; ja 1f ; ud2 ; 1:"
1209 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1212 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1216 } operand
= {eptp
, gpa
};
1218 asm volatile (__ex(ASM_VMX_INVEPT
)
1219 /* CF==1 or ZF==1 --> rc = -1 */
1220 "; ja 1f ; ud2 ; 1:\n"
1221 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1224 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1228 i
= __find_msr_index(vmx
, msr
);
1230 return &vmx
->guest_msrs
[i
];
1234 static void vmcs_clear(struct vmcs
*vmcs
)
1236 u64 phys_addr
= __pa(vmcs
);
1239 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1240 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1243 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1247 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1249 vmcs_clear(loaded_vmcs
->vmcs
);
1250 loaded_vmcs
->cpu
= -1;
1251 loaded_vmcs
->launched
= 0;
1254 static void vmcs_load(struct vmcs
*vmcs
)
1256 u64 phys_addr
= __pa(vmcs
);
1259 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1260 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1263 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1269 * This bitmap is used to indicate whether the vmclear
1270 * operation is enabled on all cpus. All disabled by
1273 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1275 static inline void crash_enable_local_vmclear(int cpu
)
1277 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1280 static inline void crash_disable_local_vmclear(int cpu
)
1282 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1285 static inline int crash_local_vmclear_enabled(int cpu
)
1287 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1290 static void crash_vmclear_local_loaded_vmcss(void)
1292 int cpu
= raw_smp_processor_id();
1293 struct loaded_vmcs
*v
;
1295 if (!crash_local_vmclear_enabled(cpu
))
1298 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1299 loaded_vmcss_on_cpu_link
)
1300 vmcs_clear(v
->vmcs
);
1303 static inline void crash_enable_local_vmclear(int cpu
) { }
1304 static inline void crash_disable_local_vmclear(int cpu
) { }
1305 #endif /* CONFIG_KEXEC */
1307 static void __loaded_vmcs_clear(void *arg
)
1309 struct loaded_vmcs
*loaded_vmcs
= arg
;
1310 int cpu
= raw_smp_processor_id();
1312 if (loaded_vmcs
->cpu
!= cpu
)
1313 return; /* vcpu migration can race with cpu offline */
1314 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1315 per_cpu(current_vmcs
, cpu
) = NULL
;
1316 crash_disable_local_vmclear(cpu
);
1317 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1320 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1321 * is before setting loaded_vmcs->vcpu to -1 which is done in
1322 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1323 * then adds the vmcs into percpu list before it is deleted.
1327 loaded_vmcs_init(loaded_vmcs
);
1328 crash_enable_local_vmclear(cpu
);
1331 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1333 int cpu
= loaded_vmcs
->cpu
;
1336 smp_call_function_single(cpu
,
1337 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1340 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1345 if (cpu_has_vmx_invvpid_single())
1346 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1349 static inline void vpid_sync_vcpu_global(void)
1351 if (cpu_has_vmx_invvpid_global())
1352 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1355 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1357 if (cpu_has_vmx_invvpid_single())
1358 vpid_sync_vcpu_single(vmx
);
1360 vpid_sync_vcpu_global();
1363 static inline void ept_sync_global(void)
1365 if (cpu_has_vmx_invept_global())
1366 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1369 static inline void ept_sync_context(u64 eptp
)
1372 if (cpu_has_vmx_invept_context())
1373 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1379 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1381 unsigned long value
;
1383 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1384 : "=a"(value
) : "d"(field
) : "cc");
1388 static __always_inline u16
vmcs_read16(unsigned long field
)
1390 return vmcs_readl(field
);
1393 static __always_inline u32
vmcs_read32(unsigned long field
)
1395 return vmcs_readl(field
);
1398 static __always_inline u64
vmcs_read64(unsigned long field
)
1400 #ifdef CONFIG_X86_64
1401 return vmcs_readl(field
);
1403 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1407 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1409 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1410 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1414 static void vmcs_writel(unsigned long field
, unsigned long value
)
1418 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1419 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1420 if (unlikely(error
))
1421 vmwrite_error(field
, value
);
1424 static void vmcs_write16(unsigned long field
, u16 value
)
1426 vmcs_writel(field
, value
);
1429 static void vmcs_write32(unsigned long field
, u32 value
)
1431 vmcs_writel(field
, value
);
1434 static void vmcs_write64(unsigned long field
, u64 value
)
1436 vmcs_writel(field
, value
);
1437 #ifndef CONFIG_X86_64
1439 vmcs_writel(field
+1, value
>> 32);
1443 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1445 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1448 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1450 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1453 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1455 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1456 vmx
->vm_entry_controls_shadow
= val
;
1459 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1461 if (vmx
->vm_entry_controls_shadow
!= val
)
1462 vm_entry_controls_init(vmx
, val
);
1465 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1467 return vmx
->vm_entry_controls_shadow
;
1471 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1473 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1476 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1478 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1481 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1483 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1484 vmx
->vm_exit_controls_shadow
= val
;
1487 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1489 if (vmx
->vm_exit_controls_shadow
!= val
)
1490 vm_exit_controls_init(vmx
, val
);
1493 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1495 return vmx
->vm_exit_controls_shadow
;
1499 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1501 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1504 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1506 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1509 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1511 vmx
->segment_cache
.bitmask
= 0;
1514 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1518 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1520 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1521 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1522 vmx
->segment_cache
.bitmask
= 0;
1524 ret
= vmx
->segment_cache
.bitmask
& mask
;
1525 vmx
->segment_cache
.bitmask
|= mask
;
1529 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1531 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1533 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1534 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1538 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1540 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1542 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1543 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1547 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1549 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1551 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1552 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1556 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1558 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1560 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1561 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1565 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1569 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1570 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1571 if ((vcpu
->guest_debug
&
1572 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1573 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1574 eb
|= 1u << BP_VECTOR
;
1575 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1578 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1579 if (vcpu
->fpu_active
)
1580 eb
&= ~(1u << NM_VECTOR
);
1582 /* When we are running a nested L2 guest and L1 specified for it a
1583 * certain exception bitmap, we must trap the same exceptions and pass
1584 * them to L1. When running L2, we will only handle the exceptions
1585 * specified above if L1 did not want them.
1587 if (is_guest_mode(vcpu
))
1588 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1590 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1593 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1594 unsigned long entry
, unsigned long exit
)
1596 vm_entry_controls_clearbit(vmx
, entry
);
1597 vm_exit_controls_clearbit(vmx
, exit
);
1600 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1603 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1607 if (cpu_has_load_ia32_efer
) {
1608 clear_atomic_switch_msr_special(vmx
,
1609 VM_ENTRY_LOAD_IA32_EFER
,
1610 VM_EXIT_LOAD_IA32_EFER
);
1614 case MSR_CORE_PERF_GLOBAL_CTRL
:
1615 if (cpu_has_load_perf_global_ctrl
) {
1616 clear_atomic_switch_msr_special(vmx
,
1617 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1618 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1624 for (i
= 0; i
< m
->nr
; ++i
)
1625 if (m
->guest
[i
].index
== msr
)
1631 m
->guest
[i
] = m
->guest
[m
->nr
];
1632 m
->host
[i
] = m
->host
[m
->nr
];
1633 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1634 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1637 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1638 unsigned long entry
, unsigned long exit
,
1639 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1640 u64 guest_val
, u64 host_val
)
1642 vmcs_write64(guest_val_vmcs
, guest_val
);
1643 vmcs_write64(host_val_vmcs
, host_val
);
1644 vm_entry_controls_setbit(vmx
, entry
);
1645 vm_exit_controls_setbit(vmx
, exit
);
1648 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1649 u64 guest_val
, u64 host_val
)
1652 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1656 if (cpu_has_load_ia32_efer
) {
1657 add_atomic_switch_msr_special(vmx
,
1658 VM_ENTRY_LOAD_IA32_EFER
,
1659 VM_EXIT_LOAD_IA32_EFER
,
1662 guest_val
, host_val
);
1666 case MSR_CORE_PERF_GLOBAL_CTRL
:
1667 if (cpu_has_load_perf_global_ctrl
) {
1668 add_atomic_switch_msr_special(vmx
,
1669 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1670 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1671 GUEST_IA32_PERF_GLOBAL_CTRL
,
1672 HOST_IA32_PERF_GLOBAL_CTRL
,
1673 guest_val
, host_val
);
1679 for (i
= 0; i
< m
->nr
; ++i
)
1680 if (m
->guest
[i
].index
== msr
)
1683 if (i
== NR_AUTOLOAD_MSRS
) {
1684 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1685 "Can't add msr %x\n", msr
);
1687 } else if (i
== m
->nr
) {
1689 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1690 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1693 m
->guest
[i
].index
= msr
;
1694 m
->guest
[i
].value
= guest_val
;
1695 m
->host
[i
].index
= msr
;
1696 m
->host
[i
].value
= host_val
;
1699 static void reload_tss(void)
1702 * VT restores TR but not its size. Useless.
1704 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1705 struct desc_struct
*descs
;
1707 descs
= (void *)gdt
->address
;
1708 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1712 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1717 guest_efer
= vmx
->vcpu
.arch
.efer
;
1720 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1723 ignore_bits
= EFER_NX
| EFER_SCE
;
1724 #ifdef CONFIG_X86_64
1725 ignore_bits
|= EFER_LMA
| EFER_LME
;
1726 /* SCE is meaningful only in long mode on Intel */
1727 if (guest_efer
& EFER_LMA
)
1728 ignore_bits
&= ~(u64
)EFER_SCE
;
1730 guest_efer
&= ~ignore_bits
;
1731 guest_efer
|= host_efer
& ignore_bits
;
1732 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1733 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1735 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1738 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1739 * On CPUs that support "load IA32_EFER", always switch EFER
1740 * atomically, since it's faster than switching it manually.
1742 if (cpu_has_load_ia32_efer
||
1743 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1744 guest_efer
= vmx
->vcpu
.arch
.efer
;
1745 if (!(guest_efer
& EFER_LMA
))
1746 guest_efer
&= ~EFER_LME
;
1747 if (guest_efer
!= host_efer
)
1748 add_atomic_switch_msr(vmx
, MSR_EFER
,
1749 guest_efer
, host_efer
);
1756 static unsigned long segment_base(u16 selector
)
1758 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1759 struct desc_struct
*d
;
1760 unsigned long table_base
;
1763 if (!(selector
& ~3))
1766 table_base
= gdt
->address
;
1768 if (selector
& 4) { /* from ldt */
1769 u16 ldt_selector
= kvm_read_ldt();
1771 if (!(ldt_selector
& ~3))
1774 table_base
= segment_base(ldt_selector
);
1776 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1777 v
= get_desc_base(d
);
1778 #ifdef CONFIG_X86_64
1779 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1780 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1785 static inline unsigned long kvm_read_tr_base(void)
1788 asm("str %0" : "=g"(tr
));
1789 return segment_base(tr
);
1792 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1794 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1797 if (vmx
->host_state
.loaded
)
1800 vmx
->host_state
.loaded
= 1;
1802 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1803 * allow segment selectors with cpl > 0 or ti == 1.
1805 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1806 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1807 savesegment(fs
, vmx
->host_state
.fs_sel
);
1808 if (!(vmx
->host_state
.fs_sel
& 7)) {
1809 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1810 vmx
->host_state
.fs_reload_needed
= 0;
1812 vmcs_write16(HOST_FS_SELECTOR
, 0);
1813 vmx
->host_state
.fs_reload_needed
= 1;
1815 savesegment(gs
, vmx
->host_state
.gs_sel
);
1816 if (!(vmx
->host_state
.gs_sel
& 7))
1817 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1819 vmcs_write16(HOST_GS_SELECTOR
, 0);
1820 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1823 #ifdef CONFIG_X86_64
1824 savesegment(ds
, vmx
->host_state
.ds_sel
);
1825 savesegment(es
, vmx
->host_state
.es_sel
);
1828 #ifdef CONFIG_X86_64
1829 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1830 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1832 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1833 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1836 #ifdef CONFIG_X86_64
1837 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1838 if (is_long_mode(&vmx
->vcpu
))
1839 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1841 if (boot_cpu_has(X86_FEATURE_MPX
))
1842 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1843 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1844 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1845 vmx
->guest_msrs
[i
].data
,
1846 vmx
->guest_msrs
[i
].mask
);
1849 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1851 if (!vmx
->host_state
.loaded
)
1854 ++vmx
->vcpu
.stat
.host_state_reload
;
1855 vmx
->host_state
.loaded
= 0;
1856 #ifdef CONFIG_X86_64
1857 if (is_long_mode(&vmx
->vcpu
))
1858 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1860 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1861 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1862 #ifdef CONFIG_X86_64
1863 load_gs_index(vmx
->host_state
.gs_sel
);
1865 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1868 if (vmx
->host_state
.fs_reload_needed
)
1869 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1870 #ifdef CONFIG_X86_64
1871 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1872 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1873 loadsegment(es
, vmx
->host_state
.es_sel
);
1877 #ifdef CONFIG_X86_64
1878 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1880 if (vmx
->host_state
.msr_host_bndcfgs
)
1881 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1883 * If the FPU is not active (through the host task or
1884 * the guest vcpu), then restore the cr0.TS bit.
1886 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1888 load_gdt(this_cpu_ptr(&host_gdt
));
1891 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1894 __vmx_load_host_state(vmx
);
1899 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1900 * vcpu mutex is already taken.
1902 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1904 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1905 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1908 kvm_cpu_vmxon(phys_addr
);
1909 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1910 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1912 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1913 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1914 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1917 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1918 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1919 unsigned long sysenter_esp
;
1921 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1922 local_irq_disable();
1923 crash_disable_local_vmclear(cpu
);
1926 * Read loaded_vmcs->cpu should be before fetching
1927 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1928 * See the comments in __loaded_vmcs_clear().
1932 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1933 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1934 crash_enable_local_vmclear(cpu
);
1938 * Linux uses per-cpu TSS and GDT, so set these when switching
1941 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1942 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1944 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1945 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1946 vmx
->loaded_vmcs
->cpu
= cpu
;
1950 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1952 __vmx_load_host_state(to_vmx(vcpu
));
1953 if (!vmm_exclusive
) {
1954 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1960 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1964 if (vcpu
->fpu_active
)
1966 vcpu
->fpu_active
= 1;
1967 cr0
= vmcs_readl(GUEST_CR0
);
1968 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1969 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1970 vmcs_writel(GUEST_CR0
, cr0
);
1971 update_exception_bitmap(vcpu
);
1972 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1973 if (is_guest_mode(vcpu
))
1974 vcpu
->arch
.cr0_guest_owned_bits
&=
1975 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1976 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1979 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1982 * Return the cr0 value that a nested guest would read. This is a combination
1983 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1984 * its hypervisor (cr0_read_shadow).
1986 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1988 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1989 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1991 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1993 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1994 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1997 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1999 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2000 * set this *before* calling this function.
2002 vmx_decache_cr0_guest_bits(vcpu
);
2003 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2004 update_exception_bitmap(vcpu
);
2005 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2006 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2007 if (is_guest_mode(vcpu
)) {
2009 * L1's specified read shadow might not contain the TS bit,
2010 * so now that we turned on shadowing of this bit, we need to
2011 * set this bit of the shadow. Like in nested_vmx_run we need
2012 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2013 * up-to-date here because we just decached cr0.TS (and we'll
2014 * only update vmcs12->guest_cr0 on nested exit).
2016 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2017 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2018 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2019 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2021 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2024 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2026 unsigned long rflags
, save_rflags
;
2028 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2029 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2030 rflags
= vmcs_readl(GUEST_RFLAGS
);
2031 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2032 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2033 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2034 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2036 to_vmx(vcpu
)->rflags
= rflags
;
2038 return to_vmx(vcpu
)->rflags
;
2041 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2043 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2044 to_vmx(vcpu
)->rflags
= rflags
;
2045 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2046 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2047 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2049 vmcs_writel(GUEST_RFLAGS
, rflags
);
2052 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2054 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2057 if (interruptibility
& GUEST_INTR_STATE_STI
)
2058 ret
|= KVM_X86_SHADOW_INT_STI
;
2059 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2060 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2065 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2067 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2068 u32 interruptibility
= interruptibility_old
;
2070 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2072 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2073 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2074 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2075 interruptibility
|= GUEST_INTR_STATE_STI
;
2077 if ((interruptibility
!= interruptibility_old
))
2078 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2081 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2085 rip
= kvm_rip_read(vcpu
);
2086 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2087 kvm_rip_write(vcpu
, rip
);
2089 /* skipping an emulated instruction also counts */
2090 vmx_set_interrupt_shadow(vcpu
, 0);
2094 * KVM wants to inject page-faults which it got to the guest. This function
2095 * checks whether in a nested guest, we need to inject them to L1 or L2.
2097 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2099 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2101 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2104 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2105 vmcs_read32(VM_EXIT_INTR_INFO
),
2106 vmcs_readl(EXIT_QUALIFICATION
));
2110 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2111 bool has_error_code
, u32 error_code
,
2114 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2115 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2117 if (!reinject
&& is_guest_mode(vcpu
) &&
2118 nested_vmx_check_exception(vcpu
, nr
))
2121 if (has_error_code
) {
2122 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2123 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2126 if (vmx
->rmode
.vm86_active
) {
2128 if (kvm_exception_is_soft(nr
))
2129 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2130 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2131 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2135 if (kvm_exception_is_soft(nr
)) {
2136 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2137 vmx
->vcpu
.arch
.event_exit_inst_len
);
2138 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2140 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2142 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2145 static bool vmx_rdtscp_supported(void)
2147 return cpu_has_vmx_rdtscp();
2150 static bool vmx_invpcid_supported(void)
2152 return cpu_has_vmx_invpcid() && enable_ept
;
2156 * Swap MSR entry in host/guest MSR entry array.
2158 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2160 struct shared_msr_entry tmp
;
2162 tmp
= vmx
->guest_msrs
[to
];
2163 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2164 vmx
->guest_msrs
[from
] = tmp
;
2167 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2169 unsigned long *msr_bitmap
;
2171 if (is_guest_mode(vcpu
))
2172 msr_bitmap
= vmx_msr_bitmap_nested
;
2173 else if (irqchip_in_kernel(vcpu
->kvm
) &&
2174 apic_x2apic_mode(vcpu
->arch
.apic
)) {
2175 if (is_long_mode(vcpu
))
2176 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2178 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2180 if (is_long_mode(vcpu
))
2181 msr_bitmap
= vmx_msr_bitmap_longmode
;
2183 msr_bitmap
= vmx_msr_bitmap_legacy
;
2186 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2190 * Set up the vmcs to automatically save and restore system
2191 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2192 * mode, as fiddling with msrs is very expensive.
2194 static void setup_msrs(struct vcpu_vmx
*vmx
)
2196 int save_nmsrs
, index
;
2199 #ifdef CONFIG_X86_64
2200 if (is_long_mode(&vmx
->vcpu
)) {
2201 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2203 move_msr_up(vmx
, index
, save_nmsrs
++);
2204 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2206 move_msr_up(vmx
, index
, save_nmsrs
++);
2207 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2209 move_msr_up(vmx
, index
, save_nmsrs
++);
2210 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2211 if (index
>= 0 && vmx
->rdtscp_enabled
)
2212 move_msr_up(vmx
, index
, save_nmsrs
++);
2214 * MSR_STAR is only needed on long mode guests, and only
2215 * if efer.sce is enabled.
2217 index
= __find_msr_index(vmx
, MSR_STAR
);
2218 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2219 move_msr_up(vmx
, index
, save_nmsrs
++);
2222 index
= __find_msr_index(vmx
, MSR_EFER
);
2223 if (index
>= 0 && update_transition_efer(vmx
, index
))
2224 move_msr_up(vmx
, index
, save_nmsrs
++);
2226 vmx
->save_nmsrs
= save_nmsrs
;
2228 if (cpu_has_vmx_msr_bitmap())
2229 vmx_set_msr_bitmap(&vmx
->vcpu
);
2233 * reads and returns guest's timestamp counter "register"
2234 * guest_tsc = host_tsc + tsc_offset -- 21.3
2236 static u64
guest_read_tsc(void)
2238 u64 host_tsc
, tsc_offset
;
2241 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2242 return host_tsc
+ tsc_offset
;
2246 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2247 * counter, even if a nested guest (L2) is currently running.
2249 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2253 tsc_offset
= is_guest_mode(vcpu
) ?
2254 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2255 vmcs_read64(TSC_OFFSET
);
2256 return host_tsc
+ tsc_offset
;
2260 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2261 * software catchup for faster rates on slower CPUs.
2263 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2268 if (user_tsc_khz
> tsc_khz
) {
2269 vcpu
->arch
.tsc_catchup
= 1;
2270 vcpu
->arch
.tsc_always_catchup
= 1;
2272 WARN(1, "user requested TSC rate below hardware speed\n");
2275 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2277 return vmcs_read64(TSC_OFFSET
);
2281 * writes 'offset' into guest's timestamp counter offset register
2283 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2285 if (is_guest_mode(vcpu
)) {
2287 * We're here if L1 chose not to trap WRMSR to TSC. According
2288 * to the spec, this should set L1's TSC; The offset that L1
2289 * set for L2 remains unchanged, and still needs to be added
2290 * to the newly set TSC to get L2's TSC.
2292 struct vmcs12
*vmcs12
;
2293 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2294 /* recalculate vmcs02.TSC_OFFSET: */
2295 vmcs12
= get_vmcs12(vcpu
);
2296 vmcs_write64(TSC_OFFSET
, offset
+
2297 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2298 vmcs12
->tsc_offset
: 0));
2300 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2301 vmcs_read64(TSC_OFFSET
), offset
);
2302 vmcs_write64(TSC_OFFSET
, offset
);
2306 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2308 u64 offset
= vmcs_read64(TSC_OFFSET
);
2310 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2311 if (is_guest_mode(vcpu
)) {
2312 /* Even when running L2, the adjustment needs to apply to L1 */
2313 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2315 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2316 offset
+ adjustment
);
2319 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2321 return target_tsc
- native_read_tsc();
2324 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2326 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2327 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2331 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2332 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2333 * all guests if the "nested" module option is off, and can also be disabled
2334 * for a single guest by disabling its VMX cpuid bit.
2336 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2338 return nested
&& guest_cpuid_has_vmx(vcpu
);
2342 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2343 * returned for the various VMX controls MSRs when nested VMX is enabled.
2344 * The same values should also be used to verify that vmcs12 control fields are
2345 * valid during nested entry from L1 to L2.
2346 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2347 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2348 * bit in the high half is on if the corresponding bit in the control field
2349 * may be on. See also vmx_control_verify().
2351 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2354 * Note that as a general rule, the high half of the MSRs (bits in
2355 * the control fields which may be 1) should be initialized by the
2356 * intersection of the underlying hardware's MSR (i.e., features which
2357 * can be supported) and the list of features we want to expose -
2358 * because they are known to be properly supported in our code.
2359 * Also, usually, the low half of the MSRs (bits which must be 1) can
2360 * be set to 0, meaning that L1 may turn off any of these bits. The
2361 * reason is that if one of these bits is necessary, it will appear
2362 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2363 * fields of vmcs01 and vmcs02, will turn these bits off - and
2364 * nested_vmx_exit_handled() will not pass related exits to L1.
2365 * These rules have exceptions below.
2368 /* pin-based controls */
2369 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2370 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2371 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2372 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2373 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2374 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2375 PIN_BASED_EXT_INTR_MASK
|
2376 PIN_BASED_NMI_EXITING
|
2377 PIN_BASED_VIRTUAL_NMIS
;
2378 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2379 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2380 PIN_BASED_VMX_PREEMPTION_TIMER
;
2381 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
2382 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2383 PIN_BASED_POSTED_INTR
;
2386 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2387 vmx
->nested
.nested_vmx_exit_ctls_low
,
2388 vmx
->nested
.nested_vmx_exit_ctls_high
);
2389 vmx
->nested
.nested_vmx_exit_ctls_low
=
2390 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2392 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2393 #ifdef CONFIG_X86_64
2394 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2396 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2397 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2398 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2399 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2400 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2402 if (vmx_mpx_supported())
2403 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2405 /* We support free control of debug control saving. */
2406 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2407 vmx
->nested
.nested_vmx_exit_ctls_low
&
2408 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2410 /* entry controls */
2411 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2412 vmx
->nested
.nested_vmx_entry_ctls_low
,
2413 vmx
->nested
.nested_vmx_entry_ctls_high
);
2414 vmx
->nested
.nested_vmx_entry_ctls_low
=
2415 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2416 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2417 #ifdef CONFIG_X86_64
2418 VM_ENTRY_IA32E_MODE
|
2420 VM_ENTRY_LOAD_IA32_PAT
;
2421 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2422 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2423 if (vmx_mpx_supported())
2424 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2426 /* We support free control of debug control loading. */
2427 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2428 vmx
->nested
.nested_vmx_entry_ctls_low
&
2429 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2431 /* cpu-based controls */
2432 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2433 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2434 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2435 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2436 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2437 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2438 CPU_BASED_VIRTUAL_INTR_PENDING
|
2439 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2440 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2441 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2442 CPU_BASED_CR3_STORE_EXITING
|
2443 #ifdef CONFIG_X86_64
2444 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2446 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2447 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2448 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2449 CPU_BASED_PAUSE_EXITING
| CPU_BASED_TPR_SHADOW
|
2450 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2452 * We can allow some features even when not supported by the
2453 * hardware. For example, L1 can specify an MSR bitmap - and we
2454 * can use it to avoid exits to L1 - even when L0 runs L2
2455 * without MSR bitmaps.
2457 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2458 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2459 CPU_BASED_USE_MSR_BITMAPS
;
2461 /* We support free control of CR3 access interception. */
2462 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2463 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2464 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2466 /* secondary cpu-based controls */
2467 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2468 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2469 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2470 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2471 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2472 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2473 SECONDARY_EXEC_RDTSCP
|
2474 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2475 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2476 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2477 SECONDARY_EXEC_WBINVD_EXITING
|
2478 SECONDARY_EXEC_XSAVES
;
2481 /* nested EPT: emulate EPT also to L1 */
2482 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2483 SECONDARY_EXEC_ENABLE_EPT
;
2484 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2485 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2487 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2489 * For nested guests, we don't do anything specific
2490 * for single context invalidation. Hence, only advertise
2491 * support for global context invalidation.
2493 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2495 vmx
->nested
.nested_vmx_ept_caps
= 0;
2497 if (enable_unrestricted_guest
)
2498 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2499 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2501 /* miscellaneous data */
2502 rdmsr(MSR_IA32_VMX_MISC
,
2503 vmx
->nested
.nested_vmx_misc_low
,
2504 vmx
->nested
.nested_vmx_misc_high
);
2505 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2506 vmx
->nested
.nested_vmx_misc_low
|=
2507 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2508 VMX_MISC_ACTIVITY_HLT
;
2509 vmx
->nested
.nested_vmx_misc_high
= 0;
2512 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2515 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2517 return ((control
& high
) | low
) == control
;
2520 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2522 return low
| ((u64
)high
<< 32);
2525 /* Returns 0 on success, non-0 otherwise. */
2526 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2528 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2530 switch (msr_index
) {
2531 case MSR_IA32_VMX_BASIC
:
2533 * This MSR reports some information about VMX support. We
2534 * should return information about the VMX we emulate for the
2535 * guest, and the VMCS structure we give it - not about the
2536 * VMX support of the underlying hardware.
2538 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2539 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2540 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2542 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2543 case MSR_IA32_VMX_PINBASED_CTLS
:
2544 *pdata
= vmx_control_msr(
2545 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2546 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2548 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2549 *pdata
= vmx_control_msr(
2550 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2551 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2553 case MSR_IA32_VMX_PROCBASED_CTLS
:
2554 *pdata
= vmx_control_msr(
2555 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2556 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2558 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2559 *pdata
= vmx_control_msr(
2560 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2561 vmx
->nested
.nested_vmx_exit_ctls_high
);
2563 case MSR_IA32_VMX_EXIT_CTLS
:
2564 *pdata
= vmx_control_msr(
2565 vmx
->nested
.nested_vmx_exit_ctls_low
,
2566 vmx
->nested
.nested_vmx_exit_ctls_high
);
2568 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2569 *pdata
= vmx_control_msr(
2570 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2571 vmx
->nested
.nested_vmx_entry_ctls_high
);
2573 case MSR_IA32_VMX_ENTRY_CTLS
:
2574 *pdata
= vmx_control_msr(
2575 vmx
->nested
.nested_vmx_entry_ctls_low
,
2576 vmx
->nested
.nested_vmx_entry_ctls_high
);
2578 case MSR_IA32_VMX_MISC
:
2579 *pdata
= vmx_control_msr(
2580 vmx
->nested
.nested_vmx_misc_low
,
2581 vmx
->nested
.nested_vmx_misc_high
);
2584 * These MSRs specify bits which the guest must keep fixed (on or off)
2585 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2586 * We picked the standard core2 setting.
2588 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2589 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2590 case MSR_IA32_VMX_CR0_FIXED0
:
2591 *pdata
= VMXON_CR0_ALWAYSON
;
2593 case MSR_IA32_VMX_CR0_FIXED1
:
2596 case MSR_IA32_VMX_CR4_FIXED0
:
2597 *pdata
= VMXON_CR4_ALWAYSON
;
2599 case MSR_IA32_VMX_CR4_FIXED1
:
2602 case MSR_IA32_VMX_VMCS_ENUM
:
2603 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2605 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2606 *pdata
= vmx_control_msr(
2607 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2608 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2610 case MSR_IA32_VMX_EPT_VPID_CAP
:
2611 /* Currently, no nested vpid support */
2612 *pdata
= vmx
->nested
.nested_vmx_ept_caps
;
2622 * Reads an msr value (of 'msr_index') into 'pdata'.
2623 * Returns 0 on success, non-0 otherwise.
2624 * Assumes vcpu_load() was already called.
2626 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2629 struct shared_msr_entry
*msr
;
2632 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2636 switch (msr_index
) {
2637 #ifdef CONFIG_X86_64
2639 data
= vmcs_readl(GUEST_FS_BASE
);
2642 data
= vmcs_readl(GUEST_GS_BASE
);
2644 case MSR_KERNEL_GS_BASE
:
2645 vmx_load_host_state(to_vmx(vcpu
));
2646 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2650 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2652 data
= guest_read_tsc();
2654 case MSR_IA32_SYSENTER_CS
:
2655 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2657 case MSR_IA32_SYSENTER_EIP
:
2658 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2660 case MSR_IA32_SYSENTER_ESP
:
2661 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2663 case MSR_IA32_BNDCFGS
:
2664 if (!vmx_mpx_supported())
2666 data
= vmcs_read64(GUEST_BNDCFGS
);
2668 case MSR_IA32_FEATURE_CONTROL
:
2669 if (!nested_vmx_allowed(vcpu
))
2671 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2673 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2674 if (!nested_vmx_allowed(vcpu
))
2676 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2678 if (!vmx_xsaves_supported())
2680 data
= vcpu
->arch
.ia32_xss
;
2683 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2685 /* Otherwise falls through */
2687 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2692 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2699 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2702 * Writes msr value into into the appropriate "register".
2703 * Returns 0 on success, non-0 otherwise.
2704 * Assumes vcpu_load() was already called.
2706 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2708 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2709 struct shared_msr_entry
*msr
;
2711 u32 msr_index
= msr_info
->index
;
2712 u64 data
= msr_info
->data
;
2714 switch (msr_index
) {
2716 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2718 #ifdef CONFIG_X86_64
2720 vmx_segment_cache_clear(vmx
);
2721 vmcs_writel(GUEST_FS_BASE
, data
);
2724 vmx_segment_cache_clear(vmx
);
2725 vmcs_writel(GUEST_GS_BASE
, data
);
2727 case MSR_KERNEL_GS_BASE
:
2728 vmx_load_host_state(vmx
);
2729 vmx
->msr_guest_kernel_gs_base
= data
;
2732 case MSR_IA32_SYSENTER_CS
:
2733 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2735 case MSR_IA32_SYSENTER_EIP
:
2736 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2738 case MSR_IA32_SYSENTER_ESP
:
2739 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2741 case MSR_IA32_BNDCFGS
:
2742 if (!vmx_mpx_supported())
2744 vmcs_write64(GUEST_BNDCFGS
, data
);
2747 kvm_write_tsc(vcpu
, msr_info
);
2749 case MSR_IA32_CR_PAT
:
2750 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2751 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2753 vmcs_write64(GUEST_IA32_PAT
, data
);
2754 vcpu
->arch
.pat
= data
;
2757 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2759 case MSR_IA32_TSC_ADJUST
:
2760 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2762 case MSR_IA32_FEATURE_CONTROL
:
2763 if (!nested_vmx_allowed(vcpu
) ||
2764 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2765 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2767 vmx
->nested
.msr_ia32_feature_control
= data
;
2768 if (msr_info
->host_initiated
&& data
== 0)
2769 vmx_leave_nested(vcpu
);
2771 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2772 return 1; /* they are read-only */
2774 if (!vmx_xsaves_supported())
2777 * The only supported bit as of Skylake is bit 8, but
2778 * it is not supported on KVM.
2782 vcpu
->arch
.ia32_xss
= data
;
2783 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2784 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2785 vcpu
->arch
.ia32_xss
, host_xss
);
2787 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2790 if (!vmx
->rdtscp_enabled
)
2792 /* Check reserved bit, higher 32 bits should be zero */
2793 if ((data
>> 32) != 0)
2795 /* Otherwise falls through */
2797 msr
= find_msr_entry(vmx
, msr_index
);
2799 u64 old_msr_data
= msr
->data
;
2801 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2803 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
2807 msr
->data
= old_msr_data
;
2811 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2817 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2819 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2822 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2825 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2827 case VCPU_EXREG_PDPTR
:
2829 ept_save_pdptrs(vcpu
);
2836 static __init
int cpu_has_kvm_support(void)
2838 return cpu_has_vmx();
2841 static __init
int vmx_disabled_by_bios(void)
2845 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2846 if (msr
& FEATURE_CONTROL_LOCKED
) {
2847 /* launched w/ TXT and VMX disabled */
2848 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2851 /* launched w/o TXT and VMX only enabled w/ TXT */
2852 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2853 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2854 && !tboot_enabled()) {
2855 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2856 "activate TXT before enabling KVM\n");
2859 /* launched w/o TXT and VMX disabled */
2860 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2861 && !tboot_enabled())
2868 static void kvm_cpu_vmxon(u64 addr
)
2870 asm volatile (ASM_VMX_VMXON_RAX
2871 : : "a"(&addr
), "m"(addr
)
2875 static int hardware_enable(void)
2877 int cpu
= raw_smp_processor_id();
2878 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2881 if (cr4_read_shadow() & X86_CR4_VMXE
)
2884 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2887 * Now we can enable the vmclear operation in kdump
2888 * since the loaded_vmcss_on_cpu list on this cpu
2889 * has been initialized.
2891 * Though the cpu is not in VMX operation now, there
2892 * is no problem to enable the vmclear operation
2893 * for the loaded_vmcss_on_cpu list is empty!
2895 crash_enable_local_vmclear(cpu
);
2897 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2899 test_bits
= FEATURE_CONTROL_LOCKED
;
2900 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2901 if (tboot_enabled())
2902 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2904 if ((old
& test_bits
) != test_bits
) {
2905 /* enable and lock */
2906 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2908 cr4_set_bits(X86_CR4_VMXE
);
2910 if (vmm_exclusive
) {
2911 kvm_cpu_vmxon(phys_addr
);
2915 native_store_gdt(this_cpu_ptr(&host_gdt
));
2920 static void vmclear_local_loaded_vmcss(void)
2922 int cpu
= raw_smp_processor_id();
2923 struct loaded_vmcs
*v
, *n
;
2925 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2926 loaded_vmcss_on_cpu_link
)
2927 __loaded_vmcs_clear(v
);
2931 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2934 static void kvm_cpu_vmxoff(void)
2936 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2939 static void hardware_disable(void)
2941 if (vmm_exclusive
) {
2942 vmclear_local_loaded_vmcss();
2945 cr4_clear_bits(X86_CR4_VMXE
);
2948 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2949 u32 msr
, u32
*result
)
2951 u32 vmx_msr_low
, vmx_msr_high
;
2952 u32 ctl
= ctl_min
| ctl_opt
;
2954 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2956 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2957 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2959 /* Ensure minimum (required) set of control bits are supported. */
2967 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2969 u32 vmx_msr_low
, vmx_msr_high
;
2971 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2972 return vmx_msr_high
& ctl
;
2975 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2977 u32 vmx_msr_low
, vmx_msr_high
;
2978 u32 min
, opt
, min2
, opt2
;
2979 u32 _pin_based_exec_control
= 0;
2980 u32 _cpu_based_exec_control
= 0;
2981 u32 _cpu_based_2nd_exec_control
= 0;
2982 u32 _vmexit_control
= 0;
2983 u32 _vmentry_control
= 0;
2985 min
= CPU_BASED_HLT_EXITING
|
2986 #ifdef CONFIG_X86_64
2987 CPU_BASED_CR8_LOAD_EXITING
|
2988 CPU_BASED_CR8_STORE_EXITING
|
2990 CPU_BASED_CR3_LOAD_EXITING
|
2991 CPU_BASED_CR3_STORE_EXITING
|
2992 CPU_BASED_USE_IO_BITMAPS
|
2993 CPU_BASED_MOV_DR_EXITING
|
2994 CPU_BASED_USE_TSC_OFFSETING
|
2995 CPU_BASED_MWAIT_EXITING
|
2996 CPU_BASED_MONITOR_EXITING
|
2997 CPU_BASED_INVLPG_EXITING
|
2998 CPU_BASED_RDPMC_EXITING
;
3000 opt
= CPU_BASED_TPR_SHADOW
|
3001 CPU_BASED_USE_MSR_BITMAPS
|
3002 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3003 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3004 &_cpu_based_exec_control
) < 0)
3006 #ifdef CONFIG_X86_64
3007 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3008 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3009 ~CPU_BASED_CR8_STORE_EXITING
;
3011 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3013 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3014 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3015 SECONDARY_EXEC_WBINVD_EXITING
|
3016 SECONDARY_EXEC_ENABLE_VPID
|
3017 SECONDARY_EXEC_ENABLE_EPT
|
3018 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3019 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3020 SECONDARY_EXEC_RDTSCP
|
3021 SECONDARY_EXEC_ENABLE_INVPCID
|
3022 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3023 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3024 SECONDARY_EXEC_SHADOW_VMCS
|
3025 SECONDARY_EXEC_XSAVES
|
3026 SECONDARY_EXEC_ENABLE_PML
;
3027 if (adjust_vmx_controls(min2
, opt2
,
3028 MSR_IA32_VMX_PROCBASED_CTLS2
,
3029 &_cpu_based_2nd_exec_control
) < 0)
3032 #ifndef CONFIG_X86_64
3033 if (!(_cpu_based_2nd_exec_control
&
3034 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3035 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3038 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3039 _cpu_based_2nd_exec_control
&= ~(
3040 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3041 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3042 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3044 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3045 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3047 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3048 CPU_BASED_CR3_STORE_EXITING
|
3049 CPU_BASED_INVLPG_EXITING
);
3050 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3051 vmx_capability
.ept
, vmx_capability
.vpid
);
3054 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3055 #ifdef CONFIG_X86_64
3056 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3058 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3059 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3060 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3061 &_vmexit_control
) < 0)
3064 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3065 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3066 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3067 &_pin_based_exec_control
) < 0)
3070 if (!(_cpu_based_2nd_exec_control
&
3071 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3072 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3073 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3075 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3076 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3077 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3078 &_vmentry_control
) < 0)
3081 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3083 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3084 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3087 #ifdef CONFIG_X86_64
3088 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3089 if (vmx_msr_high
& (1u<<16))
3093 /* Require Write-Back (WB) memory type for VMCS accesses. */
3094 if (((vmx_msr_high
>> 18) & 15) != 6)
3097 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3098 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3099 vmcs_conf
->revision_id
= vmx_msr_low
;
3101 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3102 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3103 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3104 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3105 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3107 cpu_has_load_ia32_efer
=
3108 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3109 VM_ENTRY_LOAD_IA32_EFER
)
3110 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3111 VM_EXIT_LOAD_IA32_EFER
);
3113 cpu_has_load_perf_global_ctrl
=
3114 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3115 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3116 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3117 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3120 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3121 * but due to arrata below it can't be used. Workaround is to use
3122 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3124 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3129 * BC86,AAY89,BD102 (model 44)
3133 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3134 switch (boot_cpu_data
.x86_model
) {
3140 cpu_has_load_perf_global_ctrl
= false;
3141 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3142 "does not work properly. Using workaround\n");
3150 rdmsrl(MSR_IA32_XSS
, host_xss
);
3155 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3157 int node
= cpu_to_node(cpu
);
3161 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3164 vmcs
= page_address(pages
);
3165 memset(vmcs
, 0, vmcs_config
.size
);
3166 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3170 static struct vmcs
*alloc_vmcs(void)
3172 return alloc_vmcs_cpu(raw_smp_processor_id());
3175 static void free_vmcs(struct vmcs
*vmcs
)
3177 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3181 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3183 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3185 if (!loaded_vmcs
->vmcs
)
3187 loaded_vmcs_clear(loaded_vmcs
);
3188 free_vmcs(loaded_vmcs
->vmcs
);
3189 loaded_vmcs
->vmcs
= NULL
;
3192 static void free_kvm_area(void)
3196 for_each_possible_cpu(cpu
) {
3197 free_vmcs(per_cpu(vmxarea
, cpu
));
3198 per_cpu(vmxarea
, cpu
) = NULL
;
3202 static void init_vmcs_shadow_fields(void)
3206 /* No checks for read only fields yet */
3208 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3209 switch (shadow_read_write_fields
[i
]) {
3211 if (!vmx_mpx_supported())
3219 shadow_read_write_fields
[j
] =
3220 shadow_read_write_fields
[i
];
3223 max_shadow_read_write_fields
= j
;
3225 /* shadowed fields guest access without vmexit */
3226 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3227 clear_bit(shadow_read_write_fields
[i
],
3228 vmx_vmwrite_bitmap
);
3229 clear_bit(shadow_read_write_fields
[i
],
3232 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3233 clear_bit(shadow_read_only_fields
[i
],
3237 static __init
int alloc_kvm_area(void)
3241 for_each_possible_cpu(cpu
) {
3244 vmcs
= alloc_vmcs_cpu(cpu
);
3250 per_cpu(vmxarea
, cpu
) = vmcs
;
3255 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3257 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3260 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3261 struct kvm_segment
*save
)
3263 if (!emulate_invalid_guest_state
) {
3265 * CS and SS RPL should be equal during guest entry according
3266 * to VMX spec, but in reality it is not always so. Since vcpu
3267 * is in the middle of the transition from real mode to
3268 * protected mode it is safe to assume that RPL 0 is a good
3271 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3272 save
->selector
&= ~SEGMENT_RPL_MASK
;
3273 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3276 vmx_set_segment(vcpu
, save
, seg
);
3279 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3281 unsigned long flags
;
3282 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3285 * Update real mode segment cache. It may be not up-to-date if sement
3286 * register was written while vcpu was in a guest mode.
3288 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3289 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3290 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3291 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3292 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3293 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3295 vmx
->rmode
.vm86_active
= 0;
3297 vmx_segment_cache_clear(vmx
);
3299 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3301 flags
= vmcs_readl(GUEST_RFLAGS
);
3302 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3303 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3304 vmcs_writel(GUEST_RFLAGS
, flags
);
3306 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3307 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3309 update_exception_bitmap(vcpu
);
3311 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3312 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3313 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3314 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3315 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3316 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3319 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3321 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3322 struct kvm_segment var
= *save
;
3325 if (seg
== VCPU_SREG_CS
)
3328 if (!emulate_invalid_guest_state
) {
3329 var
.selector
= var
.base
>> 4;
3330 var
.base
= var
.base
& 0xffff0;
3340 if (save
->base
& 0xf)
3341 printk_once(KERN_WARNING
"kvm: segment base is not "
3342 "paragraph aligned when entering "
3343 "protected mode (seg=%d)", seg
);
3346 vmcs_write16(sf
->selector
, var
.selector
);
3347 vmcs_write32(sf
->base
, var
.base
);
3348 vmcs_write32(sf
->limit
, var
.limit
);
3349 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3352 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3354 unsigned long flags
;
3355 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3357 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3358 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3359 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3360 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3361 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3362 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3363 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3365 vmx
->rmode
.vm86_active
= 1;
3368 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3369 * vcpu. Warn the user that an update is overdue.
3371 if (!vcpu
->kvm
->arch
.tss_addr
)
3372 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3373 "called before entering vcpu\n");
3375 vmx_segment_cache_clear(vmx
);
3377 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3378 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3379 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3381 flags
= vmcs_readl(GUEST_RFLAGS
);
3382 vmx
->rmode
.save_rflags
= flags
;
3384 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3386 vmcs_writel(GUEST_RFLAGS
, flags
);
3387 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3388 update_exception_bitmap(vcpu
);
3390 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3391 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3392 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3393 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3394 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3395 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3397 kvm_mmu_reset_context(vcpu
);
3400 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3402 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3403 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3409 * Force kernel_gs_base reloading before EFER changes, as control
3410 * of this msr depends on is_long_mode().
3412 vmx_load_host_state(to_vmx(vcpu
));
3413 vcpu
->arch
.efer
= efer
;
3414 if (efer
& EFER_LMA
) {
3415 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3418 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3420 msr
->data
= efer
& ~EFER_LME
;
3425 #ifdef CONFIG_X86_64
3427 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3431 vmx_segment_cache_clear(to_vmx(vcpu
));
3433 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3434 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3435 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3437 vmcs_write32(GUEST_TR_AR_BYTES
,
3438 (guest_tr_ar
& ~AR_TYPE_MASK
)
3439 | AR_TYPE_BUSY_64_TSS
);
3441 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3444 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3446 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3447 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3452 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3454 vpid_sync_context(to_vmx(vcpu
));
3456 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3458 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3462 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3464 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3466 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3467 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3470 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3472 if (enable_ept
&& is_paging(vcpu
))
3473 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3474 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3477 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3479 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3481 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3482 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3485 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3487 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3489 if (!test_bit(VCPU_EXREG_PDPTR
,
3490 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3493 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3494 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3495 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3496 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3497 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3501 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3503 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3505 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3506 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3507 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3508 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3509 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3512 __set_bit(VCPU_EXREG_PDPTR
,
3513 (unsigned long *)&vcpu
->arch
.regs_avail
);
3514 __set_bit(VCPU_EXREG_PDPTR
,
3515 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3518 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3520 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3522 struct kvm_vcpu
*vcpu
)
3524 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3525 vmx_decache_cr3(vcpu
);
3526 if (!(cr0
& X86_CR0_PG
)) {
3527 /* From paging/starting to nonpaging */
3528 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3529 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3530 (CPU_BASED_CR3_LOAD_EXITING
|
3531 CPU_BASED_CR3_STORE_EXITING
));
3532 vcpu
->arch
.cr0
= cr0
;
3533 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3534 } else if (!is_paging(vcpu
)) {
3535 /* From nonpaging to paging */
3536 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3537 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3538 ~(CPU_BASED_CR3_LOAD_EXITING
|
3539 CPU_BASED_CR3_STORE_EXITING
));
3540 vcpu
->arch
.cr0
= cr0
;
3541 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3544 if (!(cr0
& X86_CR0_WP
))
3545 *hw_cr0
&= ~X86_CR0_WP
;
3548 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3550 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3551 unsigned long hw_cr0
;
3553 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3554 if (enable_unrestricted_guest
)
3555 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3557 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3559 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3562 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3566 #ifdef CONFIG_X86_64
3567 if (vcpu
->arch
.efer
& EFER_LME
) {
3568 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3570 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3576 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3578 if (!vcpu
->fpu_active
)
3579 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3581 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3582 vmcs_writel(GUEST_CR0
, hw_cr0
);
3583 vcpu
->arch
.cr0
= cr0
;
3585 /* depends on vcpu->arch.cr0 to be set to a new value */
3586 vmx
->emulation_required
= emulation_required(vcpu
);
3589 static u64
construct_eptp(unsigned long root_hpa
)
3593 /* TODO write the value reading from MSR */
3594 eptp
= VMX_EPT_DEFAULT_MT
|
3595 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3596 if (enable_ept_ad_bits
)
3597 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3598 eptp
|= (root_hpa
& PAGE_MASK
);
3603 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3605 unsigned long guest_cr3
;
3610 eptp
= construct_eptp(cr3
);
3611 vmcs_write64(EPT_POINTER
, eptp
);
3612 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3613 guest_cr3
= kvm_read_cr3(vcpu
);
3615 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3616 ept_load_pdptrs(vcpu
);
3619 vmx_flush_tlb(vcpu
);
3620 vmcs_writel(GUEST_CR3
, guest_cr3
);
3623 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3625 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3626 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3628 if (cr4
& X86_CR4_VMXE
) {
3630 * To use VMXON (and later other VMX instructions), a guest
3631 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3632 * So basically the check on whether to allow nested VMX
3635 if (!nested_vmx_allowed(vcpu
))
3638 if (to_vmx(vcpu
)->nested
.vmxon
&&
3639 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3642 vcpu
->arch
.cr4
= cr4
;
3644 if (!is_paging(vcpu
)) {
3645 hw_cr4
&= ~X86_CR4_PAE
;
3646 hw_cr4
|= X86_CR4_PSE
;
3648 * SMEP/SMAP is disabled if CPU is in non-paging mode
3649 * in hardware. However KVM always uses paging mode to
3650 * emulate guest non-paging mode with TDP.
3651 * To emulate this behavior, SMEP/SMAP needs to be
3652 * manually disabled when guest switches to non-paging
3655 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3656 } else if (!(cr4
& X86_CR4_PAE
)) {
3657 hw_cr4
&= ~X86_CR4_PAE
;
3661 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3662 vmcs_writel(GUEST_CR4
, hw_cr4
);
3666 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3667 struct kvm_segment
*var
, int seg
)
3669 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3672 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3673 *var
= vmx
->rmode
.segs
[seg
];
3674 if (seg
== VCPU_SREG_TR
3675 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3677 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3678 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3681 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3682 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3683 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3684 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3685 var
->unusable
= (ar
>> 16) & 1;
3686 var
->type
= ar
& 15;
3687 var
->s
= (ar
>> 4) & 1;
3688 var
->dpl
= (ar
>> 5) & 3;
3690 * Some userspaces do not preserve unusable property. Since usable
3691 * segment has to be present according to VMX spec we can use present
3692 * property to amend userspace bug by making unusable segment always
3693 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3694 * segment as unusable.
3696 var
->present
= !var
->unusable
;
3697 var
->avl
= (ar
>> 12) & 1;
3698 var
->l
= (ar
>> 13) & 1;
3699 var
->db
= (ar
>> 14) & 1;
3700 var
->g
= (ar
>> 15) & 1;
3703 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3705 struct kvm_segment s
;
3707 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3708 vmx_get_segment(vcpu
, &s
, seg
);
3711 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3714 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3716 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3718 if (unlikely(vmx
->rmode
.vm86_active
))
3721 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3726 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3730 if (var
->unusable
|| !var
->present
)
3733 ar
= var
->type
& 15;
3734 ar
|= (var
->s
& 1) << 4;
3735 ar
|= (var
->dpl
& 3) << 5;
3736 ar
|= (var
->present
& 1) << 7;
3737 ar
|= (var
->avl
& 1) << 12;
3738 ar
|= (var
->l
& 1) << 13;
3739 ar
|= (var
->db
& 1) << 14;
3740 ar
|= (var
->g
& 1) << 15;
3746 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3747 struct kvm_segment
*var
, int seg
)
3749 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3750 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3752 vmx_segment_cache_clear(vmx
);
3754 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3755 vmx
->rmode
.segs
[seg
] = *var
;
3756 if (seg
== VCPU_SREG_TR
)
3757 vmcs_write16(sf
->selector
, var
->selector
);
3759 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3763 vmcs_writel(sf
->base
, var
->base
);
3764 vmcs_write32(sf
->limit
, var
->limit
);
3765 vmcs_write16(sf
->selector
, var
->selector
);
3768 * Fix the "Accessed" bit in AR field of segment registers for older
3770 * IA32 arch specifies that at the time of processor reset the
3771 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3772 * is setting it to 0 in the userland code. This causes invalid guest
3773 * state vmexit when "unrestricted guest" mode is turned on.
3774 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3775 * tree. Newer qemu binaries with that qemu fix would not need this
3778 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3779 var
->type
|= 0x1; /* Accessed */
3781 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3784 vmx
->emulation_required
= emulation_required(vcpu
);
3787 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3789 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3791 *db
= (ar
>> 14) & 1;
3792 *l
= (ar
>> 13) & 1;
3795 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3797 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3798 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3801 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3803 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3804 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3807 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3809 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3810 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3813 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3815 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3816 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3819 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3821 struct kvm_segment var
;
3824 vmx_get_segment(vcpu
, &var
, seg
);
3826 if (seg
== VCPU_SREG_CS
)
3828 ar
= vmx_segment_access_rights(&var
);
3830 if (var
.base
!= (var
.selector
<< 4))
3832 if (var
.limit
!= 0xffff)
3840 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3842 struct kvm_segment cs
;
3843 unsigned int cs_rpl
;
3845 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3846 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
3850 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3854 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3855 if (cs
.dpl
> cs_rpl
)
3858 if (cs
.dpl
!= cs_rpl
)
3864 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3868 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3870 struct kvm_segment ss
;
3871 unsigned int ss_rpl
;
3873 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3874 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
3878 if (ss
.type
!= 3 && ss
.type
!= 7)
3882 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3890 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3892 struct kvm_segment var
;
3895 vmx_get_segment(vcpu
, &var
, seg
);
3896 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
3904 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3905 if (var
.dpl
< rpl
) /* DPL < RPL */
3909 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3915 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3917 struct kvm_segment tr
;
3919 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3923 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3925 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3933 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3935 struct kvm_segment ldtr
;
3937 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3941 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
3951 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3953 struct kvm_segment cs
, ss
;
3955 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3956 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3958 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
3959 (ss
.selector
& SEGMENT_RPL_MASK
));
3963 * Check if guest state is valid. Returns true if valid, false if
3965 * We assume that registers are always usable
3967 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3969 if (enable_unrestricted_guest
)
3972 /* real mode guest state checks */
3973 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3974 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3976 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3978 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3980 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3982 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3984 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3987 /* protected mode guest state checks */
3988 if (!cs_ss_rpl_check(vcpu
))
3990 if (!code_segment_valid(vcpu
))
3992 if (!stack_segment_valid(vcpu
))
3994 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3996 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3998 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4000 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4002 if (!tr_valid(vcpu
))
4004 if (!ldtr_valid(vcpu
))
4008 * - Add checks on RIP
4009 * - Add checks on RFLAGS
4015 static int init_rmode_tss(struct kvm
*kvm
)
4021 idx
= srcu_read_lock(&kvm
->srcu
);
4022 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4023 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4026 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4027 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4028 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4031 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4034 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4038 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4039 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4042 srcu_read_unlock(&kvm
->srcu
, idx
);
4046 static int init_rmode_identity_map(struct kvm
*kvm
)
4049 pfn_t identity_map_pfn
;
4055 /* Protect kvm->arch.ept_identity_pagetable_done. */
4056 mutex_lock(&kvm
->slots_lock
);
4058 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4061 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4063 r
= alloc_identity_pagetable(kvm
);
4067 idx
= srcu_read_lock(&kvm
->srcu
);
4068 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4071 /* Set up identity-mapping pagetable for EPT in real mode */
4072 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4073 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4074 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4075 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4076 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4080 kvm
->arch
.ept_identity_pagetable_done
= true;
4083 srcu_read_unlock(&kvm
->srcu
, idx
);
4086 mutex_unlock(&kvm
->slots_lock
);
4090 static void seg_setup(int seg
)
4092 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4095 vmcs_write16(sf
->selector
, 0);
4096 vmcs_writel(sf
->base
, 0);
4097 vmcs_write32(sf
->limit
, 0xffff);
4099 if (seg
== VCPU_SREG_CS
)
4100 ar
|= 0x08; /* code segment */
4102 vmcs_write32(sf
->ar_bytes
, ar
);
4105 static int alloc_apic_access_page(struct kvm
*kvm
)
4108 struct kvm_userspace_memory_region kvm_userspace_mem
;
4111 mutex_lock(&kvm
->slots_lock
);
4112 if (kvm
->arch
.apic_access_page_done
)
4114 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
4115 kvm_userspace_mem
.flags
= 0;
4116 kvm_userspace_mem
.guest_phys_addr
= APIC_DEFAULT_PHYS_BASE
;
4117 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4118 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4122 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4123 if (is_error_page(page
)) {
4129 * Do not pin the page in memory, so that memory hot-unplug
4130 * is able to migrate it.
4133 kvm
->arch
.apic_access_page_done
= true;
4135 mutex_unlock(&kvm
->slots_lock
);
4139 static int alloc_identity_pagetable(struct kvm
*kvm
)
4141 /* Called with kvm->slots_lock held. */
4143 struct kvm_userspace_memory_region kvm_userspace_mem
;
4146 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4148 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4149 kvm_userspace_mem
.flags
= 0;
4150 kvm_userspace_mem
.guest_phys_addr
=
4151 kvm
->arch
.ept_identity_map_addr
;
4152 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4153 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4158 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4165 spin_lock(&vmx_vpid_lock
);
4166 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4167 if (vpid
< VMX_NR_VPIDS
) {
4169 __set_bit(vpid
, vmx_vpid_bitmap
);
4171 spin_unlock(&vmx_vpid_lock
);
4174 static void free_vpid(struct vcpu_vmx
*vmx
)
4178 spin_lock(&vmx_vpid_lock
);
4180 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4181 spin_unlock(&vmx_vpid_lock
);
4184 #define MSR_TYPE_R 1
4185 #define MSR_TYPE_W 2
4186 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4189 int f
= sizeof(unsigned long);
4191 if (!cpu_has_vmx_msr_bitmap())
4195 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4196 * have the write-low and read-high bitmap offsets the wrong way round.
4197 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4199 if (msr
<= 0x1fff) {
4200 if (type
& MSR_TYPE_R
)
4202 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4204 if (type
& MSR_TYPE_W
)
4206 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4208 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4210 if (type
& MSR_TYPE_R
)
4212 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4214 if (type
& MSR_TYPE_W
)
4216 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4221 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4224 int f
= sizeof(unsigned long);
4226 if (!cpu_has_vmx_msr_bitmap())
4230 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4231 * have the write-low and read-high bitmap offsets the wrong way round.
4232 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4234 if (msr
<= 0x1fff) {
4235 if (type
& MSR_TYPE_R
)
4237 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4239 if (type
& MSR_TYPE_W
)
4241 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4243 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4245 if (type
& MSR_TYPE_R
)
4247 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4249 if (type
& MSR_TYPE_W
)
4251 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4257 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4258 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4260 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4261 unsigned long *msr_bitmap_nested
,
4264 int f
= sizeof(unsigned long);
4266 if (!cpu_has_vmx_msr_bitmap()) {
4272 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4273 * have the write-low and read-high bitmap offsets the wrong way round.
4274 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4276 if (msr
<= 0x1fff) {
4277 if (type
& MSR_TYPE_R
&&
4278 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4280 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4282 if (type
& MSR_TYPE_W
&&
4283 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4285 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4287 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4289 if (type
& MSR_TYPE_R
&&
4290 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4292 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4294 if (type
& MSR_TYPE_W
&&
4295 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4297 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4302 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4305 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4306 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4307 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4308 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4311 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4313 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4315 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4319 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4321 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4323 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4327 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4329 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4331 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4335 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4337 return enable_apicv
&& irqchip_in_kernel(kvm
);
4340 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4342 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4347 if (vmx
->nested
.pi_desc
&&
4348 vmx
->nested
.pi_pending
) {
4349 vmx
->nested
.pi_pending
= false;
4350 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4353 max_irr
= find_last_bit(
4354 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4359 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4364 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4365 kunmap(vmx
->nested
.virtual_apic_page
);
4367 status
= vmcs_read16(GUEST_INTR_STATUS
);
4368 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4370 status
|= (u8
)max_irr
;
4371 vmcs_write16(GUEST_INTR_STATUS
, status
);
4377 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4380 if (vcpu
->mode
== IN_GUEST_MODE
) {
4381 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4382 POSTED_INTR_VECTOR
);
4389 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4392 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4394 if (is_guest_mode(vcpu
) &&
4395 vector
== vmx
->nested
.posted_intr_nv
) {
4396 /* the PIR and ON have been set by L1. */
4397 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4399 * If a posted intr is not recognized by hardware,
4400 * we will accomplish it in the next vmentry.
4402 vmx
->nested
.pi_pending
= true;
4403 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4409 * Send interrupt to vcpu via posted interrupt way.
4410 * 1. If target vcpu is running(non-root mode), send posted interrupt
4411 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4412 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4413 * interrupt from PIR in next vmentry.
4415 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4417 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4420 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4424 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4427 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4428 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4429 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4430 kvm_vcpu_kick(vcpu
);
4433 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4435 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4437 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4440 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4443 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4449 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4450 * will not change in the lifetime of the guest.
4451 * Note that host-state that does change is set elsewhere. E.g., host-state
4452 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4454 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4461 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4462 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4464 /* Save the most likely value for this task's CR4 in the VMCS. */
4465 cr4
= cr4_read_shadow();
4466 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4467 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4469 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4470 #ifdef CONFIG_X86_64
4472 * Load null selectors, so we can avoid reloading them in
4473 * __vmx_load_host_state(), in case userspace uses the null selectors
4474 * too (the expected case).
4476 vmcs_write16(HOST_DS_SELECTOR
, 0);
4477 vmcs_write16(HOST_ES_SELECTOR
, 0);
4479 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4480 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4482 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4483 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4485 native_store_idt(&dt
);
4486 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4487 vmx
->host_idt_base
= dt
.address
;
4489 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4491 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4492 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4493 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4494 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4496 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4497 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4498 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4502 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4504 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4506 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4507 if (is_guest_mode(&vmx
->vcpu
))
4508 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4509 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4510 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4513 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4515 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4517 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4518 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4519 return pin_based_exec_ctrl
;
4522 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4524 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4526 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4527 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4529 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4530 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4531 #ifdef CONFIG_X86_64
4532 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4533 CPU_BASED_CR8_LOAD_EXITING
;
4537 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4538 CPU_BASED_CR3_LOAD_EXITING
|
4539 CPU_BASED_INVLPG_EXITING
;
4540 return exec_control
;
4543 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4545 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4546 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4547 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4549 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4551 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4552 enable_unrestricted_guest
= 0;
4553 /* Enable INVPCID for non-ept guests may cause performance regression. */
4554 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4556 if (!enable_unrestricted_guest
)
4557 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4559 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4560 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4561 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4562 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4563 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4564 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4566 We can NOT enable shadow_vmcs here because we don't have yet
4569 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4570 /* PML is enabled/disabled in creating/destorying vcpu */
4571 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4573 return exec_control
;
4576 static void ept_set_mmio_spte_mask(void)
4579 * EPT Misconfigurations can be generated if the value of bits 2:0
4580 * of an EPT paging-structure entry is 110b (write/execute).
4581 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4584 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4587 #define VMX_XSS_EXIT_BITMAP 0
4589 * Sets up the vmcs for emulated real mode.
4591 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4593 #ifdef CONFIG_X86_64
4599 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4600 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4602 if (enable_shadow_vmcs
) {
4603 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4604 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4606 if (cpu_has_vmx_msr_bitmap())
4607 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4609 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4612 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4614 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4616 if (cpu_has_secondary_exec_ctrls()) {
4617 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4618 vmx_secondary_exec_control(vmx
));
4621 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4622 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4623 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4624 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4625 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4627 vmcs_write16(GUEST_INTR_STATUS
, 0);
4629 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4630 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4634 vmcs_write32(PLE_GAP
, ple_gap
);
4635 vmx
->ple_window
= ple_window
;
4636 vmx
->ple_window_dirty
= true;
4639 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4640 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4641 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4643 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4644 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4645 vmx_set_constant_host_state(vmx
);
4646 #ifdef CONFIG_X86_64
4647 rdmsrl(MSR_FS_BASE
, a
);
4648 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4649 rdmsrl(MSR_GS_BASE
, a
);
4650 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4652 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4653 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4656 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4657 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4658 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4659 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4660 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4662 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4663 u32 msr_low
, msr_high
;
4665 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4666 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4667 /* Write the default value follow host pat */
4668 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4669 /* Keep arch.pat sync with GUEST_IA32_PAT */
4670 vmx
->vcpu
.arch
.pat
= host_pat
;
4673 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4674 u32 index
= vmx_msr_index
[i
];
4675 u32 data_low
, data_high
;
4678 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4680 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4682 vmx
->guest_msrs
[j
].index
= i
;
4683 vmx
->guest_msrs
[j
].data
= 0;
4684 vmx
->guest_msrs
[j
].mask
= -1ull;
4689 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4691 /* 22.2.1, 20.8.1 */
4692 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4694 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4695 set_cr4_guest_host_mask(vmx
);
4697 if (vmx_xsaves_supported())
4698 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4703 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4705 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4706 struct msr_data apic_base_msr
;
4708 vmx
->rmode
.vm86_active
= 0;
4710 vmx
->soft_vnmi_blocked
= 0;
4712 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4713 kvm_set_cr8(&vmx
->vcpu
, 0);
4714 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
| MSR_IA32_APICBASE_ENABLE
;
4715 if (kvm_vcpu_is_reset_bsp(&vmx
->vcpu
))
4716 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4717 apic_base_msr
.host_initiated
= true;
4718 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4720 vmx_segment_cache_clear(vmx
);
4722 seg_setup(VCPU_SREG_CS
);
4723 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4724 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4726 seg_setup(VCPU_SREG_DS
);
4727 seg_setup(VCPU_SREG_ES
);
4728 seg_setup(VCPU_SREG_FS
);
4729 seg_setup(VCPU_SREG_GS
);
4730 seg_setup(VCPU_SREG_SS
);
4732 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4733 vmcs_writel(GUEST_TR_BASE
, 0);
4734 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4735 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4737 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4738 vmcs_writel(GUEST_LDTR_BASE
, 0);
4739 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4740 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4742 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4743 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4744 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4746 vmcs_writel(GUEST_RFLAGS
, 0x02);
4747 kvm_rip_write(vcpu
, 0xfff0);
4749 vmcs_writel(GUEST_GDTR_BASE
, 0);
4750 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4752 vmcs_writel(GUEST_IDTR_BASE
, 0);
4753 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4755 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4756 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4757 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4759 /* Special registers */
4760 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4764 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4766 if (cpu_has_vmx_tpr_shadow()) {
4767 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4768 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4769 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4770 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4771 vmcs_write32(TPR_THRESHOLD
, 0);
4774 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
4776 if (vmx_vm_has_apicv(vcpu
->kvm
))
4777 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4780 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4782 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4783 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4784 vmx_set_cr4(&vmx
->vcpu
, 0);
4785 vmx_set_efer(&vmx
->vcpu
, 0);
4786 vmx_fpu_activate(&vmx
->vcpu
);
4787 update_exception_bitmap(&vmx
->vcpu
);
4789 vpid_sync_context(vmx
);
4793 * In nested virtualization, check if L1 asked to exit on external interrupts.
4794 * For most existing hypervisors, this will always return true.
4796 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4798 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4799 PIN_BASED_EXT_INTR_MASK
;
4803 * In nested virtualization, check if L1 has set
4804 * VM_EXIT_ACK_INTR_ON_EXIT
4806 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4808 return get_vmcs12(vcpu
)->vm_exit_controls
&
4809 VM_EXIT_ACK_INTR_ON_EXIT
;
4812 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4814 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4815 PIN_BASED_NMI_EXITING
;
4818 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4820 u32 cpu_based_vm_exec_control
;
4822 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4823 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4824 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4827 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4829 u32 cpu_based_vm_exec_control
;
4831 if (!cpu_has_virtual_nmis() ||
4832 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4833 enable_irq_window(vcpu
);
4837 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4838 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4839 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4842 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4844 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4846 int irq
= vcpu
->arch
.interrupt
.nr
;
4848 trace_kvm_inj_virq(irq
);
4850 ++vcpu
->stat
.irq_injections
;
4851 if (vmx
->rmode
.vm86_active
) {
4853 if (vcpu
->arch
.interrupt
.soft
)
4854 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4855 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4856 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4859 intr
= irq
| INTR_INFO_VALID_MASK
;
4860 if (vcpu
->arch
.interrupt
.soft
) {
4861 intr
|= INTR_TYPE_SOFT_INTR
;
4862 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4863 vmx
->vcpu
.arch
.event_exit_inst_len
);
4865 intr
|= INTR_TYPE_EXT_INTR
;
4866 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4869 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4871 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4873 if (is_guest_mode(vcpu
))
4876 if (!cpu_has_virtual_nmis()) {
4878 * Tracking the NMI-blocked state in software is built upon
4879 * finding the next open IRQ window. This, in turn, depends on
4880 * well-behaving guests: They have to keep IRQs disabled at
4881 * least as long as the NMI handler runs. Otherwise we may
4882 * cause NMI nesting, maybe breaking the guest. But as this is
4883 * highly unlikely, we can live with the residual risk.
4885 vmx
->soft_vnmi_blocked
= 1;
4886 vmx
->vnmi_blocked_time
= 0;
4889 ++vcpu
->stat
.nmi_injections
;
4890 vmx
->nmi_known_unmasked
= false;
4891 if (vmx
->rmode
.vm86_active
) {
4892 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4893 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4896 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4897 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4900 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4902 if (!cpu_has_virtual_nmis())
4903 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4904 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4906 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4909 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4911 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4913 if (!cpu_has_virtual_nmis()) {
4914 if (vmx
->soft_vnmi_blocked
!= masked
) {
4915 vmx
->soft_vnmi_blocked
= masked
;
4916 vmx
->vnmi_blocked_time
= 0;
4919 vmx
->nmi_known_unmasked
= !masked
;
4921 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4922 GUEST_INTR_STATE_NMI
);
4924 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4925 GUEST_INTR_STATE_NMI
);
4929 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4931 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4934 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4937 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4938 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4939 | GUEST_INTR_STATE_NMI
));
4942 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4944 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4945 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4946 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4947 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4950 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4953 struct kvm_userspace_memory_region tss_mem
= {
4954 .slot
= TSS_PRIVATE_MEMSLOT
,
4955 .guest_phys_addr
= addr
,
4956 .memory_size
= PAGE_SIZE
* 3,
4960 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4963 kvm
->arch
.tss_addr
= addr
;
4964 return init_rmode_tss(kvm
);
4967 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4972 * Update instruction length as we may reinject the exception
4973 * from user space while in guest debugging mode.
4975 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4976 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4977 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4981 if (vcpu
->guest_debug
&
4982 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4999 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5000 int vec
, u32 err_code
)
5003 * Instruction with address size override prefix opcode 0x67
5004 * Cause the #SS fault with 0 error code in VM86 mode.
5006 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5007 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5008 if (vcpu
->arch
.halt_request
) {
5009 vcpu
->arch
.halt_request
= 0;
5010 return kvm_vcpu_halt(vcpu
);
5018 * Forward all other exceptions that are valid in real mode.
5019 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5020 * the required debugging infrastructure rework.
5022 kvm_queue_exception(vcpu
, vec
);
5027 * Trigger machine check on the host. We assume all the MSRs are already set up
5028 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5029 * We pass a fake environment to the machine check handler because we want
5030 * the guest to be always treated like user space, no matter what context
5031 * it used internally.
5033 static void kvm_machine_check(void)
5035 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5036 struct pt_regs regs
= {
5037 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5038 .flags
= X86_EFLAGS_IF
,
5041 do_machine_check(®s
, 0);
5045 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5047 /* already handled by vcpu_run */
5051 static int handle_exception(struct kvm_vcpu
*vcpu
)
5053 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5054 struct kvm_run
*kvm_run
= vcpu
->run
;
5055 u32 intr_info
, ex_no
, error_code
;
5056 unsigned long cr2
, rip
, dr6
;
5058 enum emulation_result er
;
5060 vect_info
= vmx
->idt_vectoring_info
;
5061 intr_info
= vmx
->exit_intr_info
;
5063 if (is_machine_check(intr_info
))
5064 return handle_machine_check(vcpu
);
5066 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5067 return 1; /* already handled by vmx_vcpu_run() */
5069 if (is_no_device(intr_info
)) {
5070 vmx_fpu_activate(vcpu
);
5074 if (is_invalid_opcode(intr_info
)) {
5075 if (is_guest_mode(vcpu
)) {
5076 kvm_queue_exception(vcpu
, UD_VECTOR
);
5079 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5080 if (er
!= EMULATE_DONE
)
5081 kvm_queue_exception(vcpu
, UD_VECTOR
);
5086 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5087 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5090 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5091 * MMIO, it is better to report an internal error.
5092 * See the comments in vmx_handle_exit.
5094 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5095 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5096 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5097 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5098 vcpu
->run
->internal
.ndata
= 3;
5099 vcpu
->run
->internal
.data
[0] = vect_info
;
5100 vcpu
->run
->internal
.data
[1] = intr_info
;
5101 vcpu
->run
->internal
.data
[2] = error_code
;
5105 if (is_page_fault(intr_info
)) {
5106 /* EPT won't cause page fault directly */
5108 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5109 trace_kvm_page_fault(cr2
, error_code
);
5111 if (kvm_event_needs_reinjection(vcpu
))
5112 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5113 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5116 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5118 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5119 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5123 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5124 if (!(vcpu
->guest_debug
&
5125 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5126 vcpu
->arch
.dr6
&= ~15;
5127 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5128 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5129 skip_emulated_instruction(vcpu
);
5131 kvm_queue_exception(vcpu
, DB_VECTOR
);
5134 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5135 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5139 * Update instruction length as we may reinject #BP from
5140 * user space while in guest debugging mode. Reading it for
5141 * #DB as well causes no harm, it is not used in that case.
5143 vmx
->vcpu
.arch
.event_exit_inst_len
=
5144 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5145 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5146 rip
= kvm_rip_read(vcpu
);
5147 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5148 kvm_run
->debug
.arch
.exception
= ex_no
;
5151 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5152 kvm_run
->ex
.exception
= ex_no
;
5153 kvm_run
->ex
.error_code
= error_code
;
5159 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5161 ++vcpu
->stat
.irq_exits
;
5165 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5167 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5171 static int handle_io(struct kvm_vcpu
*vcpu
)
5173 unsigned long exit_qualification
;
5174 int size
, in
, string
;
5177 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5178 string
= (exit_qualification
& 16) != 0;
5179 in
= (exit_qualification
& 8) != 0;
5181 ++vcpu
->stat
.io_exits
;
5184 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5186 port
= exit_qualification
>> 16;
5187 size
= (exit_qualification
& 7) + 1;
5188 skip_emulated_instruction(vcpu
);
5190 return kvm_fast_pio_out(vcpu
, size
, port
);
5194 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5197 * Patch in the VMCALL instruction:
5199 hypercall
[0] = 0x0f;
5200 hypercall
[1] = 0x01;
5201 hypercall
[2] = 0xc1;
5204 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5206 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5207 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5209 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5210 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5211 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5212 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5213 return (val
& always_on
) == always_on
;
5216 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5217 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5219 if (is_guest_mode(vcpu
)) {
5220 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5221 unsigned long orig_val
= val
;
5224 * We get here when L2 changed cr0 in a way that did not change
5225 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5226 * but did change L0 shadowed bits. So we first calculate the
5227 * effective cr0 value that L1 would like to write into the
5228 * hardware. It consists of the L2-owned bits from the new
5229 * value combined with the L1-owned bits from L1's guest_cr0.
5231 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5232 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5234 if (!nested_cr0_valid(vcpu
, val
))
5237 if (kvm_set_cr0(vcpu
, val
))
5239 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5242 if (to_vmx(vcpu
)->nested
.vmxon
&&
5243 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5245 return kvm_set_cr0(vcpu
, val
);
5249 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5251 if (is_guest_mode(vcpu
)) {
5252 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5253 unsigned long orig_val
= val
;
5255 /* analogously to handle_set_cr0 */
5256 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5257 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5258 if (kvm_set_cr4(vcpu
, val
))
5260 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5263 return kvm_set_cr4(vcpu
, val
);
5266 /* called to set cr0 as approriate for clts instruction exit. */
5267 static void handle_clts(struct kvm_vcpu
*vcpu
)
5269 if (is_guest_mode(vcpu
)) {
5271 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5272 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5273 * just pretend it's off (also in arch.cr0 for fpu_activate).
5275 vmcs_writel(CR0_READ_SHADOW
,
5276 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5277 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5279 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5282 static int handle_cr(struct kvm_vcpu
*vcpu
)
5284 unsigned long exit_qualification
, val
;
5289 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5290 cr
= exit_qualification
& 15;
5291 reg
= (exit_qualification
>> 8) & 15;
5292 switch ((exit_qualification
>> 4) & 3) {
5293 case 0: /* mov to cr */
5294 val
= kvm_register_readl(vcpu
, reg
);
5295 trace_kvm_cr_write(cr
, val
);
5298 err
= handle_set_cr0(vcpu
, val
);
5299 kvm_complete_insn_gp(vcpu
, err
);
5302 err
= kvm_set_cr3(vcpu
, val
);
5303 kvm_complete_insn_gp(vcpu
, err
);
5306 err
= handle_set_cr4(vcpu
, val
);
5307 kvm_complete_insn_gp(vcpu
, err
);
5310 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5312 err
= kvm_set_cr8(vcpu
, cr8
);
5313 kvm_complete_insn_gp(vcpu
, err
);
5314 if (irqchip_in_kernel(vcpu
->kvm
))
5316 if (cr8_prev
<= cr8
)
5318 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5325 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5326 skip_emulated_instruction(vcpu
);
5327 vmx_fpu_activate(vcpu
);
5329 case 1: /*mov from cr*/
5332 val
= kvm_read_cr3(vcpu
);
5333 kvm_register_write(vcpu
, reg
, val
);
5334 trace_kvm_cr_read(cr
, val
);
5335 skip_emulated_instruction(vcpu
);
5338 val
= kvm_get_cr8(vcpu
);
5339 kvm_register_write(vcpu
, reg
, val
);
5340 trace_kvm_cr_read(cr
, val
);
5341 skip_emulated_instruction(vcpu
);
5346 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5347 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5348 kvm_lmsw(vcpu
, val
);
5350 skip_emulated_instruction(vcpu
);
5355 vcpu
->run
->exit_reason
= 0;
5356 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5357 (int)(exit_qualification
>> 4) & 3, cr
);
5361 static int handle_dr(struct kvm_vcpu
*vcpu
)
5363 unsigned long exit_qualification
;
5366 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5367 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5369 /* First, if DR does not exist, trigger UD */
5370 if (!kvm_require_dr(vcpu
, dr
))
5373 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5374 if (!kvm_require_cpl(vcpu
, 0))
5376 dr7
= vmcs_readl(GUEST_DR7
);
5379 * As the vm-exit takes precedence over the debug trap, we
5380 * need to emulate the latter, either for the host or the
5381 * guest debugging itself.
5383 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5384 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5385 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5386 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5387 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5388 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5391 vcpu
->arch
.dr6
&= ~15;
5392 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5393 kvm_queue_exception(vcpu
, DB_VECTOR
);
5398 if (vcpu
->guest_debug
== 0) {
5399 u32 cpu_based_vm_exec_control
;
5401 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5402 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5403 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5406 * No more DR vmexits; force a reload of the debug registers
5407 * and reenter on this instruction. The next vmexit will
5408 * retrieve the full state of the debug registers.
5410 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5414 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5415 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5418 if (kvm_get_dr(vcpu
, dr
, &val
))
5420 kvm_register_write(vcpu
, reg
, val
);
5422 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5425 skip_emulated_instruction(vcpu
);
5429 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5431 return vcpu
->arch
.dr6
;
5434 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5438 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5440 u32 cpu_based_vm_exec_control
;
5442 get_debugreg(vcpu
->arch
.db
[0], 0);
5443 get_debugreg(vcpu
->arch
.db
[1], 1);
5444 get_debugreg(vcpu
->arch
.db
[2], 2);
5445 get_debugreg(vcpu
->arch
.db
[3], 3);
5446 get_debugreg(vcpu
->arch
.dr6
, 6);
5447 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5449 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5451 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5452 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5453 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5456 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5458 vmcs_writel(GUEST_DR7
, val
);
5461 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5463 kvm_emulate_cpuid(vcpu
);
5467 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5469 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5472 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5473 trace_kvm_msr_read_ex(ecx
);
5474 kvm_inject_gp(vcpu
, 0);
5478 trace_kvm_msr_read(ecx
, data
);
5480 /* FIXME: handling of bits 32:63 of rax, rdx */
5481 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5482 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5483 skip_emulated_instruction(vcpu
);
5487 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5489 struct msr_data msr
;
5490 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5491 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5492 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5496 msr
.host_initiated
= false;
5497 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5498 trace_kvm_msr_write_ex(ecx
, data
);
5499 kvm_inject_gp(vcpu
, 0);
5503 trace_kvm_msr_write(ecx
, data
);
5504 skip_emulated_instruction(vcpu
);
5508 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5510 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5514 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5516 u32 cpu_based_vm_exec_control
;
5518 /* clear pending irq */
5519 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5520 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5521 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5523 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5525 ++vcpu
->stat
.irq_window_exits
;
5528 * If the user space waits to inject interrupts, exit as soon as
5531 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5532 vcpu
->run
->request_interrupt_window
&&
5533 !kvm_cpu_has_interrupt(vcpu
)) {
5534 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5540 static int handle_halt(struct kvm_vcpu
*vcpu
)
5542 return kvm_emulate_halt(vcpu
);
5545 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5547 kvm_emulate_hypercall(vcpu
);
5551 static int handle_invd(struct kvm_vcpu
*vcpu
)
5553 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5556 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5558 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5560 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5561 skip_emulated_instruction(vcpu
);
5565 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5569 err
= kvm_rdpmc(vcpu
);
5570 kvm_complete_insn_gp(vcpu
, err
);
5575 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5577 kvm_emulate_wbinvd(vcpu
);
5581 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5583 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5584 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5586 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5587 skip_emulated_instruction(vcpu
);
5591 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5593 skip_emulated_instruction(vcpu
);
5594 WARN(1, "this should never happen\n");
5598 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5600 skip_emulated_instruction(vcpu
);
5601 WARN(1, "this should never happen\n");
5605 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5607 if (likely(fasteoi
)) {
5608 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5609 int access_type
, offset
;
5611 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5612 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5614 * Sane guest uses MOV to write EOI, with written value
5615 * not cared. So make a short-circuit here by avoiding
5616 * heavy instruction emulation.
5618 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5619 (offset
== APIC_EOI
)) {
5620 kvm_lapic_set_eoi(vcpu
);
5621 skip_emulated_instruction(vcpu
);
5625 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5628 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5630 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5631 int vector
= exit_qualification
& 0xff;
5633 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5634 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5638 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5640 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5641 u32 offset
= exit_qualification
& 0xfff;
5643 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5644 kvm_apic_write_nodecode(vcpu
, offset
);
5648 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5650 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5651 unsigned long exit_qualification
;
5652 bool has_error_code
= false;
5655 int reason
, type
, idt_v
, idt_index
;
5657 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5658 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5659 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5661 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5663 reason
= (u32
)exit_qualification
>> 30;
5664 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5666 case INTR_TYPE_NMI_INTR
:
5667 vcpu
->arch
.nmi_injected
= false;
5668 vmx_set_nmi_mask(vcpu
, true);
5670 case INTR_TYPE_EXT_INTR
:
5671 case INTR_TYPE_SOFT_INTR
:
5672 kvm_clear_interrupt_queue(vcpu
);
5674 case INTR_TYPE_HARD_EXCEPTION
:
5675 if (vmx
->idt_vectoring_info
&
5676 VECTORING_INFO_DELIVER_CODE_MASK
) {
5677 has_error_code
= true;
5679 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5682 case INTR_TYPE_SOFT_EXCEPTION
:
5683 kvm_clear_exception_queue(vcpu
);
5689 tss_selector
= exit_qualification
;
5691 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5692 type
!= INTR_TYPE_EXT_INTR
&&
5693 type
!= INTR_TYPE_NMI_INTR
))
5694 skip_emulated_instruction(vcpu
);
5696 if (kvm_task_switch(vcpu
, tss_selector
,
5697 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5698 has_error_code
, error_code
) == EMULATE_FAIL
) {
5699 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5700 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5701 vcpu
->run
->internal
.ndata
= 0;
5705 /* clear all local breakpoint enable flags */
5706 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x155);
5709 * TODO: What about debug traps on tss switch?
5710 * Are we supposed to inject them and update dr6?
5716 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5718 unsigned long exit_qualification
;
5723 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5725 gla_validity
= (exit_qualification
>> 7) & 0x3;
5726 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5727 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5728 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5729 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5730 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5731 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5732 (long unsigned int)exit_qualification
);
5733 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5734 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5739 * EPT violation happened while executing iret from NMI,
5740 * "blocked by NMI" bit has to be set before next VM entry.
5741 * There are errata that may cause this bit to not be set:
5744 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5745 cpu_has_virtual_nmis() &&
5746 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5747 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5749 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5750 trace_kvm_page_fault(gpa
, exit_qualification
);
5752 /* It is a write fault? */
5753 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5754 /* It is a fetch fault? */
5755 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5756 /* ept page table is present? */
5757 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5759 vcpu
->arch
.exit_qualification
= exit_qualification
;
5761 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5764 static u64
ept_rsvd_mask(u64 spte
, int level
)
5769 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5770 mask
|= (1ULL << i
);
5773 /* bits 7:3 reserved */
5775 else if (spte
& (1ULL << 7))
5777 * 1GB/2MB page, bits 29:12 or 20:12 reserved respectively,
5778 * level == 1 if the hypervisor is using the ignored bit 7.
5780 mask
|= (PAGE_SIZE
<< ((level
- 1) * 9)) - PAGE_SIZE
;
5782 /* bits 6:3 reserved */
5788 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5791 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5793 /* 010b (write-only) */
5794 WARN_ON((spte
& 0x7) == 0x2);
5796 /* 110b (write/execute) */
5797 WARN_ON((spte
& 0x7) == 0x6);
5799 /* 100b (execute-only) and value not supported by logical processor */
5800 if (!cpu_has_vmx_ept_execute_only())
5801 WARN_ON((spte
& 0x7) == 0x4);
5805 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5807 if (rsvd_bits
!= 0) {
5808 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5809 __func__
, rsvd_bits
);
5813 /* bits 5:3 are _not_ reserved for large page or leaf page */
5814 if ((rsvd_bits
& 0x38) == 0) {
5815 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5817 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5818 ept_mem_type
== 7) {
5819 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5820 __func__
, ept_mem_type
);
5827 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5830 int nr_sptes
, i
, ret
;
5833 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5834 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5835 skip_emulated_instruction(vcpu
);
5839 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5840 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5841 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5844 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5845 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5847 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5850 /* It is the real ept misconfig */
5851 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5852 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5854 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5856 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5857 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5859 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5860 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5865 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5867 u32 cpu_based_vm_exec_control
;
5869 /* clear pending NMI */
5870 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5871 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5872 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5873 ++vcpu
->stat
.nmi_window_exits
;
5874 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5879 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5881 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5882 enum emulation_result err
= EMULATE_DONE
;
5885 bool intr_window_requested
;
5886 unsigned count
= 130;
5888 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5889 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5891 while (vmx
->emulation_required
&& count
-- != 0) {
5892 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5893 return handle_interrupt_window(&vmx
->vcpu
);
5895 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5898 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5900 if (err
== EMULATE_USER_EXIT
) {
5901 ++vcpu
->stat
.mmio_exits
;
5906 if (err
!= EMULATE_DONE
) {
5907 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5908 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5909 vcpu
->run
->internal
.ndata
= 0;
5913 if (vcpu
->arch
.halt_request
) {
5914 vcpu
->arch
.halt_request
= 0;
5915 ret
= kvm_vcpu_halt(vcpu
);
5919 if (signal_pending(current
))
5929 static int __grow_ple_window(int val
)
5931 if (ple_window_grow
< 1)
5934 val
= min(val
, ple_window_actual_max
);
5936 if (ple_window_grow
< ple_window
)
5937 val
*= ple_window_grow
;
5939 val
+= ple_window_grow
;
5944 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
5949 if (modifier
< ple_window
)
5954 return max(val
, minimum
);
5957 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
5959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5960 int old
= vmx
->ple_window
;
5962 vmx
->ple_window
= __grow_ple_window(old
);
5964 if (vmx
->ple_window
!= old
)
5965 vmx
->ple_window_dirty
= true;
5967 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5970 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
5972 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5973 int old
= vmx
->ple_window
;
5975 vmx
->ple_window
= __shrink_ple_window(old
,
5976 ple_window_shrink
, ple_window
);
5978 if (vmx
->ple_window
!= old
)
5979 vmx
->ple_window_dirty
= true;
5981 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
5985 * ple_window_actual_max is computed to be one grow_ple_window() below
5986 * ple_window_max. (See __grow_ple_window for the reason.)
5987 * This prevents overflows, because ple_window_max is int.
5988 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
5990 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
5992 static void update_ple_window_actual_max(void)
5994 ple_window_actual_max
=
5995 __shrink_ple_window(max(ple_window_max
, ple_window
),
5996 ple_window_grow
, INT_MIN
);
5999 static __init
int hardware_setup(void)
6001 int r
= -ENOMEM
, i
, msr
;
6003 rdmsrl_safe(MSR_EFER
, &host_efer
);
6005 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6006 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6008 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6009 if (!vmx_io_bitmap_a
)
6012 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6013 if (!vmx_io_bitmap_b
)
6016 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6017 if (!vmx_msr_bitmap_legacy
)
6020 vmx_msr_bitmap_legacy_x2apic
=
6021 (unsigned long *)__get_free_page(GFP_KERNEL
);
6022 if (!vmx_msr_bitmap_legacy_x2apic
)
6025 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6026 if (!vmx_msr_bitmap_longmode
)
6029 vmx_msr_bitmap_longmode_x2apic
=
6030 (unsigned long *)__get_free_page(GFP_KERNEL
);
6031 if (!vmx_msr_bitmap_longmode_x2apic
)
6035 vmx_msr_bitmap_nested
=
6036 (unsigned long *)__get_free_page(GFP_KERNEL
);
6037 if (!vmx_msr_bitmap_nested
)
6041 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6042 if (!vmx_vmread_bitmap
)
6045 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6046 if (!vmx_vmwrite_bitmap
)
6049 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6050 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6053 * Allow direct access to the PC debug port (it is often used for I/O
6054 * delays, but the vmexits simply slow things down).
6056 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6057 clear_bit(0x80, vmx_io_bitmap_a
);
6059 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6061 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6062 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6064 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6066 if (setup_vmcs_config(&vmcs_config
) < 0) {
6071 if (boot_cpu_has(X86_FEATURE_NX
))
6072 kvm_enable_efer_bits(EFER_NX
);
6074 if (!cpu_has_vmx_vpid())
6076 if (!cpu_has_vmx_shadow_vmcs())
6077 enable_shadow_vmcs
= 0;
6078 if (enable_shadow_vmcs
)
6079 init_vmcs_shadow_fields();
6081 if (!cpu_has_vmx_ept() ||
6082 !cpu_has_vmx_ept_4levels()) {
6084 enable_unrestricted_guest
= 0;
6085 enable_ept_ad_bits
= 0;
6088 if (!cpu_has_vmx_ept_ad_bits())
6089 enable_ept_ad_bits
= 0;
6091 if (!cpu_has_vmx_unrestricted_guest())
6092 enable_unrestricted_guest
= 0;
6094 if (!cpu_has_vmx_flexpriority())
6095 flexpriority_enabled
= 0;
6098 * set_apic_access_page_addr() is used to reload apic access
6099 * page upon invalidation. No need to do anything if not
6100 * using the APIC_ACCESS_ADDR VMCS field.
6102 if (!flexpriority_enabled
)
6103 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6105 if (!cpu_has_vmx_tpr_shadow())
6106 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6108 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6109 kvm_disable_largepages();
6111 if (!cpu_has_vmx_ple())
6114 if (!cpu_has_vmx_apicv())
6118 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6120 kvm_x86_ops
->hwapic_irr_update
= NULL
;
6121 kvm_x86_ops
->hwapic_isr_update
= NULL
;
6122 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
6123 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
6126 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6127 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6128 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6129 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6130 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6131 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6132 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6134 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6135 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6136 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6137 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6140 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6141 vmx_disable_intercept_msr_read_x2apic(msr
);
6143 /* According SDM, in x2apic mode, the whole id reg is used.
6144 * But in KVM, it only use the highest eight bits. Need to
6146 vmx_enable_intercept_msr_read_x2apic(0x802);
6148 vmx_enable_intercept_msr_read_x2apic(0x839);
6150 vmx_disable_intercept_msr_write_x2apic(0x808);
6152 vmx_disable_intercept_msr_write_x2apic(0x80b);
6154 vmx_disable_intercept_msr_write_x2apic(0x83f);
6158 kvm_mmu_set_mask_ptes(0ull,
6159 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6160 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6161 0ull, VMX_EPT_EXECUTABLE_MASK
);
6162 ept_set_mmio_spte_mask();
6167 update_ple_window_actual_max();
6170 * Only enable PML when hardware supports PML feature, and both EPT
6171 * and EPT A/D bit features are enabled -- PML depends on them to work.
6173 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6177 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6178 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6179 kvm_x86_ops
->flush_log_dirty
= NULL
;
6180 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6183 return alloc_kvm_area();
6186 free_page((unsigned long)vmx_vmwrite_bitmap
);
6188 free_page((unsigned long)vmx_vmread_bitmap
);
6191 free_page((unsigned long)vmx_msr_bitmap_nested
);
6193 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6195 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6197 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6199 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6201 free_page((unsigned long)vmx_io_bitmap_b
);
6203 free_page((unsigned long)vmx_io_bitmap_a
);
6208 static __exit
void hardware_unsetup(void)
6210 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6211 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6212 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6213 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6214 free_page((unsigned long)vmx_io_bitmap_b
);
6215 free_page((unsigned long)vmx_io_bitmap_a
);
6216 free_page((unsigned long)vmx_vmwrite_bitmap
);
6217 free_page((unsigned long)vmx_vmread_bitmap
);
6219 free_page((unsigned long)vmx_msr_bitmap_nested
);
6225 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6226 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6228 static int handle_pause(struct kvm_vcpu
*vcpu
)
6231 grow_ple_window(vcpu
);
6233 skip_emulated_instruction(vcpu
);
6234 kvm_vcpu_on_spin(vcpu
);
6239 static int handle_nop(struct kvm_vcpu
*vcpu
)
6241 skip_emulated_instruction(vcpu
);
6245 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6247 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6248 return handle_nop(vcpu
);
6251 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6253 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6254 return handle_nop(vcpu
);
6258 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6259 * We could reuse a single VMCS for all the L2 guests, but we also want the
6260 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6261 * allows keeping them loaded on the processor, and in the future will allow
6262 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6263 * every entry if they never change.
6264 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6265 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6267 * The following functions allocate and free a vmcs02 in this pool.
6270 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6271 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6273 struct vmcs02_list
*item
;
6274 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6275 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6276 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6277 return &item
->vmcs02
;
6280 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6281 /* Recycle the least recently used VMCS. */
6282 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6283 struct vmcs02_list
, list
);
6284 item
->vmptr
= vmx
->nested
.current_vmptr
;
6285 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6286 return &item
->vmcs02
;
6289 /* Create a new VMCS */
6290 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6293 item
->vmcs02
.vmcs
= alloc_vmcs();
6294 if (!item
->vmcs02
.vmcs
) {
6298 loaded_vmcs_init(&item
->vmcs02
);
6299 item
->vmptr
= vmx
->nested
.current_vmptr
;
6300 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6301 vmx
->nested
.vmcs02_num
++;
6302 return &item
->vmcs02
;
6305 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6306 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6308 struct vmcs02_list
*item
;
6309 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6310 if (item
->vmptr
== vmptr
) {
6311 free_loaded_vmcs(&item
->vmcs02
);
6312 list_del(&item
->list
);
6314 vmx
->nested
.vmcs02_num
--;
6320 * Free all VMCSs saved for this vcpu, except the one pointed by
6321 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6322 * must be &vmx->vmcs01.
6324 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6326 struct vmcs02_list
*item
, *n
;
6328 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6329 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6331 * Something will leak if the above WARN triggers. Better than
6334 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6337 free_loaded_vmcs(&item
->vmcs02
);
6338 list_del(&item
->list
);
6340 vmx
->nested
.vmcs02_num
--;
6345 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6346 * set the success or error code of an emulated VMX instruction, as specified
6347 * by Vol 2B, VMX Instruction Reference, "Conventions".
6349 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6351 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6352 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6353 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6356 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6358 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6359 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6360 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6364 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6365 u32 vm_instruction_error
)
6367 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6369 * failValid writes the error number to the current VMCS, which
6370 * can't be done there isn't a current VMCS.
6372 nested_vmx_failInvalid(vcpu
);
6375 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6376 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6377 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6379 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6381 * We don't need to force a shadow sync because
6382 * VM_INSTRUCTION_ERROR is not shadowed
6386 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6388 /* TODO: not to reset guest simply here. */
6389 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6390 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6393 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6395 struct vcpu_vmx
*vmx
=
6396 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6398 vmx
->nested
.preemption_timer_expired
= true;
6399 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6400 kvm_vcpu_kick(&vmx
->vcpu
);
6402 return HRTIMER_NORESTART
;
6406 * Decode the memory-address operand of a vmx instruction, as recorded on an
6407 * exit caused by such an instruction (run by a guest hypervisor).
6408 * On success, returns 0. When the operand is invalid, returns 1 and throws
6411 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6412 unsigned long exit_qualification
,
6413 u32 vmx_instruction_info
, gva_t
*ret
)
6416 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6417 * Execution", on an exit, vmx_instruction_info holds most of the
6418 * addressing components of the operand. Only the displacement part
6419 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6420 * For how an actual address is calculated from all these components,
6421 * refer to Vol. 1, "Operand Addressing".
6423 int scaling
= vmx_instruction_info
& 3;
6424 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6425 bool is_reg
= vmx_instruction_info
& (1u << 10);
6426 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6427 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6428 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6429 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6430 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6433 kvm_queue_exception(vcpu
, UD_VECTOR
);
6437 /* Addr = segment_base + offset */
6438 /* offset = base + [index * scale] + displacement */
6439 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
6441 *ret
+= kvm_register_read(vcpu
, base_reg
);
6443 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6444 *ret
+= exit_qualification
; /* holds the displacement */
6446 if (addr_size
== 1) /* 32 bit */
6450 * TODO: throw #GP (and return 1) in various cases that the VM*
6451 * instructions require it - e.g., offset beyond segment limit,
6452 * unusable or unreadable/unwritable segment, non-canonical 64-bit
6453 * address, and so on. Currently these are not checked.
6459 * This function performs the various checks including
6460 * - if it's 4KB aligned
6461 * - No bits beyond the physical address width are set
6462 * - Returns 0 on success or else 1
6463 * (Intel SDM Section 30.3)
6465 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6470 struct x86_exception e
;
6472 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6473 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6475 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6476 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
6479 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6480 sizeof(vmptr
), &e
)) {
6481 kvm_inject_page_fault(vcpu
, &e
);
6485 switch (exit_reason
) {
6486 case EXIT_REASON_VMON
:
6489 * The first 4 bytes of VMXON region contain the supported
6490 * VMCS revision identifier
6492 * Note - IA32_VMX_BASIC[48] will never be 1
6493 * for the nested case;
6494 * which replaces physical address width with 32
6497 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6498 nested_vmx_failInvalid(vcpu
);
6499 skip_emulated_instruction(vcpu
);
6503 page
= nested_get_page(vcpu
, vmptr
);
6505 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6506 nested_vmx_failInvalid(vcpu
);
6508 skip_emulated_instruction(vcpu
);
6512 vmx
->nested
.vmxon_ptr
= vmptr
;
6514 case EXIT_REASON_VMCLEAR
:
6515 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6516 nested_vmx_failValid(vcpu
,
6517 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6518 skip_emulated_instruction(vcpu
);
6522 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6523 nested_vmx_failValid(vcpu
,
6524 VMXERR_VMCLEAR_VMXON_POINTER
);
6525 skip_emulated_instruction(vcpu
);
6529 case EXIT_REASON_VMPTRLD
:
6530 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6531 nested_vmx_failValid(vcpu
,
6532 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6533 skip_emulated_instruction(vcpu
);
6537 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6538 nested_vmx_failValid(vcpu
,
6539 VMXERR_VMCLEAR_VMXON_POINTER
);
6540 skip_emulated_instruction(vcpu
);
6545 return 1; /* shouldn't happen */
6554 * Emulate the VMXON instruction.
6555 * Currently, we just remember that VMX is active, and do not save or even
6556 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6557 * do not currently need to store anything in that guest-allocated memory
6558 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6559 * argument is different from the VMXON pointer (which the spec says they do).
6561 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6563 struct kvm_segment cs
;
6564 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6565 struct vmcs
*shadow_vmcs
;
6566 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6567 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6569 /* The Intel VMX Instruction Reference lists a bunch of bits that
6570 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6571 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6572 * Otherwise, we should fail with #UD. We test these now:
6574 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6575 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6576 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6577 kvm_queue_exception(vcpu
, UD_VECTOR
);
6581 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6582 if (is_long_mode(vcpu
) && !cs
.l
) {
6583 kvm_queue_exception(vcpu
, UD_VECTOR
);
6587 if (vmx_get_cpl(vcpu
)) {
6588 kvm_inject_gp(vcpu
, 0);
6592 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6595 if (vmx
->nested
.vmxon
) {
6596 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6597 skip_emulated_instruction(vcpu
);
6601 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6602 != VMXON_NEEDED_FEATURES
) {
6603 kvm_inject_gp(vcpu
, 0);
6607 if (enable_shadow_vmcs
) {
6608 shadow_vmcs
= alloc_vmcs();
6611 /* mark vmcs as shadow */
6612 shadow_vmcs
->revision_id
|= (1u << 31);
6613 /* init shadow vmcs */
6614 vmcs_clear(shadow_vmcs
);
6615 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6618 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6619 vmx
->nested
.vmcs02_num
= 0;
6621 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6623 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6625 vmx
->nested
.vmxon
= true;
6627 skip_emulated_instruction(vcpu
);
6628 nested_vmx_succeed(vcpu
);
6633 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6634 * for running VMX instructions (except VMXON, whose prerequisites are
6635 * slightly different). It also specifies what exception to inject otherwise.
6637 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6639 struct kvm_segment cs
;
6640 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6642 if (!vmx
->nested
.vmxon
) {
6643 kvm_queue_exception(vcpu
, UD_VECTOR
);
6647 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6648 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6649 (is_long_mode(vcpu
) && !cs
.l
)) {
6650 kvm_queue_exception(vcpu
, UD_VECTOR
);
6654 if (vmx_get_cpl(vcpu
)) {
6655 kvm_inject_gp(vcpu
, 0);
6662 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6665 if (vmx
->nested
.current_vmptr
== -1ull)
6668 /* current_vmptr and current_vmcs12 are always set/reset together */
6669 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6672 if (enable_shadow_vmcs
) {
6673 /* copy to memory all shadowed fields in case
6674 they were modified */
6675 copy_shadow_to_vmcs12(vmx
);
6676 vmx
->nested
.sync_shadow_vmcs
= false;
6677 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6678 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6679 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6680 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6682 vmx
->nested
.posted_intr_nv
= -1;
6683 kunmap(vmx
->nested
.current_vmcs12_page
);
6684 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6685 vmx
->nested
.current_vmptr
= -1ull;
6686 vmx
->nested
.current_vmcs12
= NULL
;
6690 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6691 * just stops using VMX.
6693 static void free_nested(struct vcpu_vmx
*vmx
)
6695 if (!vmx
->nested
.vmxon
)
6698 vmx
->nested
.vmxon
= false;
6699 nested_release_vmcs12(vmx
);
6700 if (enable_shadow_vmcs
)
6701 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6702 /* Unpin physical memory we referred to in current vmcs02 */
6703 if (vmx
->nested
.apic_access_page
) {
6704 nested_release_page(vmx
->nested
.apic_access_page
);
6705 vmx
->nested
.apic_access_page
= NULL
;
6707 if (vmx
->nested
.virtual_apic_page
) {
6708 nested_release_page(vmx
->nested
.virtual_apic_page
);
6709 vmx
->nested
.virtual_apic_page
= NULL
;
6711 if (vmx
->nested
.pi_desc_page
) {
6712 kunmap(vmx
->nested
.pi_desc_page
);
6713 nested_release_page(vmx
->nested
.pi_desc_page
);
6714 vmx
->nested
.pi_desc_page
= NULL
;
6715 vmx
->nested
.pi_desc
= NULL
;
6718 nested_free_all_saved_vmcss(vmx
);
6721 /* Emulate the VMXOFF instruction */
6722 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6724 if (!nested_vmx_check_permission(vcpu
))
6726 free_nested(to_vmx(vcpu
));
6727 skip_emulated_instruction(vcpu
);
6728 nested_vmx_succeed(vcpu
);
6732 /* Emulate the VMCLEAR instruction */
6733 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6735 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6737 struct vmcs12
*vmcs12
;
6740 if (!nested_vmx_check_permission(vcpu
))
6743 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6746 if (vmptr
== vmx
->nested
.current_vmptr
)
6747 nested_release_vmcs12(vmx
);
6749 page
= nested_get_page(vcpu
, vmptr
);
6752 * For accurate processor emulation, VMCLEAR beyond available
6753 * physical memory should do nothing at all. However, it is
6754 * possible that a nested vmx bug, not a guest hypervisor bug,
6755 * resulted in this case, so let's shut down before doing any
6758 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6761 vmcs12
= kmap(page
);
6762 vmcs12
->launch_state
= 0;
6764 nested_release_page(page
);
6766 nested_free_vmcs02(vmx
, vmptr
);
6768 skip_emulated_instruction(vcpu
);
6769 nested_vmx_succeed(vcpu
);
6773 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6775 /* Emulate the VMLAUNCH instruction */
6776 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6778 return nested_vmx_run(vcpu
, true);
6781 /* Emulate the VMRESUME instruction */
6782 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6785 return nested_vmx_run(vcpu
, false);
6788 enum vmcs_field_type
{
6789 VMCS_FIELD_TYPE_U16
= 0,
6790 VMCS_FIELD_TYPE_U64
= 1,
6791 VMCS_FIELD_TYPE_U32
= 2,
6792 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6795 static inline int vmcs_field_type(unsigned long field
)
6797 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6798 return VMCS_FIELD_TYPE_U32
;
6799 return (field
>> 13) & 0x3 ;
6802 static inline int vmcs_field_readonly(unsigned long field
)
6804 return (((field
>> 10) & 0x3) == 1);
6808 * Read a vmcs12 field. Since these can have varying lengths and we return
6809 * one type, we chose the biggest type (u64) and zero-extend the return value
6810 * to that size. Note that the caller, handle_vmread, might need to use only
6811 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6812 * 64-bit fields are to be returned).
6814 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6815 unsigned long field
, u64
*ret
)
6817 short offset
= vmcs_field_to_offset(field
);
6823 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6825 switch (vmcs_field_type(field
)) {
6826 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6827 *ret
= *((natural_width
*)p
);
6829 case VMCS_FIELD_TYPE_U16
:
6832 case VMCS_FIELD_TYPE_U32
:
6835 case VMCS_FIELD_TYPE_U64
:
6845 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6846 unsigned long field
, u64 field_value
){
6847 short offset
= vmcs_field_to_offset(field
);
6848 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6852 switch (vmcs_field_type(field
)) {
6853 case VMCS_FIELD_TYPE_U16
:
6854 *(u16
*)p
= field_value
;
6856 case VMCS_FIELD_TYPE_U32
:
6857 *(u32
*)p
= field_value
;
6859 case VMCS_FIELD_TYPE_U64
:
6860 *(u64
*)p
= field_value
;
6862 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6863 *(natural_width
*)p
= field_value
;
6872 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6875 unsigned long field
;
6877 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6878 const unsigned long *fields
= shadow_read_write_fields
;
6879 const int num_fields
= max_shadow_read_write_fields
;
6883 vmcs_load(shadow_vmcs
);
6885 for (i
= 0; i
< num_fields
; i
++) {
6887 switch (vmcs_field_type(field
)) {
6888 case VMCS_FIELD_TYPE_U16
:
6889 field_value
= vmcs_read16(field
);
6891 case VMCS_FIELD_TYPE_U32
:
6892 field_value
= vmcs_read32(field
);
6894 case VMCS_FIELD_TYPE_U64
:
6895 field_value
= vmcs_read64(field
);
6897 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6898 field_value
= vmcs_readl(field
);
6904 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6907 vmcs_clear(shadow_vmcs
);
6908 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6913 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6915 const unsigned long *fields
[] = {
6916 shadow_read_write_fields
,
6917 shadow_read_only_fields
6919 const int max_fields
[] = {
6920 max_shadow_read_write_fields
,
6921 max_shadow_read_only_fields
6924 unsigned long field
;
6925 u64 field_value
= 0;
6926 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6928 vmcs_load(shadow_vmcs
);
6930 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6931 for (i
= 0; i
< max_fields
[q
]; i
++) {
6932 field
= fields
[q
][i
];
6933 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6935 switch (vmcs_field_type(field
)) {
6936 case VMCS_FIELD_TYPE_U16
:
6937 vmcs_write16(field
, (u16
)field_value
);
6939 case VMCS_FIELD_TYPE_U32
:
6940 vmcs_write32(field
, (u32
)field_value
);
6942 case VMCS_FIELD_TYPE_U64
:
6943 vmcs_write64(field
, (u64
)field_value
);
6945 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6946 vmcs_writel(field
, (long)field_value
);
6955 vmcs_clear(shadow_vmcs
);
6956 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6960 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6961 * used before) all generate the same failure when it is missing.
6963 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6965 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6966 if (vmx
->nested
.current_vmptr
== -1ull) {
6967 nested_vmx_failInvalid(vcpu
);
6968 skip_emulated_instruction(vcpu
);
6974 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6976 unsigned long field
;
6978 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6979 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6982 if (!nested_vmx_check_permission(vcpu
) ||
6983 !nested_vmx_check_vmcs12(vcpu
))
6986 /* Decode instruction info and find the field to read */
6987 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6988 /* Read the field, zero-extended to a u64 field_value */
6989 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
6990 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6991 skip_emulated_instruction(vcpu
);
6995 * Now copy part of this value to register or memory, as requested.
6996 * Note that the number of bits actually copied is 32 or 64 depending
6997 * on the guest's mode (32 or 64 bit), not on the given field's length.
6999 if (vmx_instruction_info
& (1u << 10)) {
7000 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7003 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7004 vmx_instruction_info
, &gva
))
7006 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7007 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7008 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7011 nested_vmx_succeed(vcpu
);
7012 skip_emulated_instruction(vcpu
);
7017 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7019 unsigned long field
;
7021 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7022 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7023 /* The value to write might be 32 or 64 bits, depending on L1's long
7024 * mode, and eventually we need to write that into a field of several
7025 * possible lengths. The code below first zero-extends the value to 64
7026 * bit (field_value), and then copies only the approriate number of
7027 * bits into the vmcs12 field.
7029 u64 field_value
= 0;
7030 struct x86_exception e
;
7032 if (!nested_vmx_check_permission(vcpu
) ||
7033 !nested_vmx_check_vmcs12(vcpu
))
7036 if (vmx_instruction_info
& (1u << 10))
7037 field_value
= kvm_register_readl(vcpu
,
7038 (((vmx_instruction_info
) >> 3) & 0xf));
7040 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7041 vmx_instruction_info
, &gva
))
7043 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7044 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7045 kvm_inject_page_fault(vcpu
, &e
);
7051 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7052 if (vmcs_field_readonly(field
)) {
7053 nested_vmx_failValid(vcpu
,
7054 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7055 skip_emulated_instruction(vcpu
);
7059 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7060 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7061 skip_emulated_instruction(vcpu
);
7065 nested_vmx_succeed(vcpu
);
7066 skip_emulated_instruction(vcpu
);
7070 /* Emulate the VMPTRLD instruction */
7071 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7073 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7077 if (!nested_vmx_check_permission(vcpu
))
7080 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7083 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7084 struct vmcs12
*new_vmcs12
;
7086 page
= nested_get_page(vcpu
, vmptr
);
7088 nested_vmx_failInvalid(vcpu
);
7089 skip_emulated_instruction(vcpu
);
7092 new_vmcs12
= kmap(page
);
7093 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7095 nested_release_page_clean(page
);
7096 nested_vmx_failValid(vcpu
,
7097 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7098 skip_emulated_instruction(vcpu
);
7102 nested_release_vmcs12(vmx
);
7103 vmx
->nested
.current_vmptr
= vmptr
;
7104 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7105 vmx
->nested
.current_vmcs12_page
= page
;
7106 if (enable_shadow_vmcs
) {
7107 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7108 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
7109 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7110 vmcs_write64(VMCS_LINK_POINTER
,
7111 __pa(vmx
->nested
.current_shadow_vmcs
));
7112 vmx
->nested
.sync_shadow_vmcs
= true;
7116 nested_vmx_succeed(vcpu
);
7117 skip_emulated_instruction(vcpu
);
7121 /* Emulate the VMPTRST instruction */
7122 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7124 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7125 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7127 struct x86_exception e
;
7129 if (!nested_vmx_check_permission(vcpu
))
7132 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7133 vmx_instruction_info
, &vmcs_gva
))
7135 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7136 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7137 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7139 kvm_inject_page_fault(vcpu
, &e
);
7142 nested_vmx_succeed(vcpu
);
7143 skip_emulated_instruction(vcpu
);
7147 /* Emulate the INVEPT instruction */
7148 static int handle_invept(struct kvm_vcpu
*vcpu
)
7150 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7151 u32 vmx_instruction_info
, types
;
7154 struct x86_exception e
;
7159 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7160 SECONDARY_EXEC_ENABLE_EPT
) ||
7161 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7162 kvm_queue_exception(vcpu
, UD_VECTOR
);
7166 if (!nested_vmx_check_permission(vcpu
))
7169 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7170 kvm_queue_exception(vcpu
, UD_VECTOR
);
7174 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7175 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7177 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7179 if (!(types
& (1UL << type
))) {
7180 nested_vmx_failValid(vcpu
,
7181 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7185 /* According to the Intel VMX instruction reference, the memory
7186 * operand is read even if it isn't needed (e.g., for type==global)
7188 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7189 vmx_instruction_info
, &gva
))
7191 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7192 sizeof(operand
), &e
)) {
7193 kvm_inject_page_fault(vcpu
, &e
);
7198 case VMX_EPT_EXTENT_GLOBAL
:
7199 kvm_mmu_sync_roots(vcpu
);
7200 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7201 nested_vmx_succeed(vcpu
);
7204 /* Trap single context invalidation invept calls */
7209 skip_emulated_instruction(vcpu
);
7213 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7215 kvm_queue_exception(vcpu
, UD_VECTOR
);
7219 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7221 unsigned long exit_qualification
;
7223 trace_kvm_pml_full(vcpu
->vcpu_id
);
7225 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7228 * PML buffer FULL happened while executing iret from NMI,
7229 * "blocked by NMI" bit has to be set before next VM entry.
7231 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7232 cpu_has_virtual_nmis() &&
7233 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7234 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7235 GUEST_INTR_STATE_NMI
);
7238 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7239 * here.., and there's no userspace involvement needed for PML.
7245 * The exit handlers return 1 if the exit was handled fully and guest execution
7246 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7247 * to be done to userspace and return 0.
7249 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7250 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7251 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7252 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7253 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7254 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7255 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7256 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7257 [EXIT_REASON_CPUID
] = handle_cpuid
,
7258 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7259 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7260 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7261 [EXIT_REASON_HLT
] = handle_halt
,
7262 [EXIT_REASON_INVD
] = handle_invd
,
7263 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7264 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7265 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7266 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7267 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7268 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7269 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7270 [EXIT_REASON_VMREAD
] = handle_vmread
,
7271 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7272 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7273 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7274 [EXIT_REASON_VMON
] = handle_vmon
,
7275 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7276 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7277 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7278 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7279 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7280 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7281 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7282 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7283 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7284 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7285 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7286 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7287 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7288 [EXIT_REASON_INVEPT
] = handle_invept
,
7289 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7290 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7291 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7292 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7295 static const int kvm_vmx_max_exit_handlers
=
7296 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7298 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7299 struct vmcs12
*vmcs12
)
7301 unsigned long exit_qualification
;
7302 gpa_t bitmap
, last_bitmap
;
7307 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7308 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7310 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7312 port
= exit_qualification
>> 16;
7313 size
= (exit_qualification
& 7) + 1;
7315 last_bitmap
= (gpa_t
)-1;
7320 bitmap
= vmcs12
->io_bitmap_a
;
7321 else if (port
< 0x10000)
7322 bitmap
= vmcs12
->io_bitmap_b
;
7325 bitmap
+= (port
& 0x7fff) / 8;
7327 if (last_bitmap
!= bitmap
)
7328 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
7330 if (b
& (1 << (port
& 7)))
7335 last_bitmap
= bitmap
;
7342 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7343 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7344 * disinterest in the current event (read or write a specific MSR) by using an
7345 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7347 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7348 struct vmcs12
*vmcs12
, u32 exit_reason
)
7350 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7353 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7357 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7358 * for the four combinations of read/write and low/high MSR numbers.
7359 * First we need to figure out which of the four to use:
7361 bitmap
= vmcs12
->msr_bitmap
;
7362 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7364 if (msr_index
>= 0xc0000000) {
7365 msr_index
-= 0xc0000000;
7369 /* Then read the msr_index'th bit from this bitmap: */
7370 if (msr_index
< 1024*8) {
7372 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
7374 return 1 & (b
>> (msr_index
& 7));
7376 return true; /* let L1 handle the wrong parameter */
7380 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7381 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7382 * intercept (via guest_host_mask etc.) the current event.
7384 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7385 struct vmcs12
*vmcs12
)
7387 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7388 int cr
= exit_qualification
& 15;
7389 int reg
= (exit_qualification
>> 8) & 15;
7390 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7392 switch ((exit_qualification
>> 4) & 3) {
7393 case 0: /* mov to cr */
7396 if (vmcs12
->cr0_guest_host_mask
&
7397 (val
^ vmcs12
->cr0_read_shadow
))
7401 if ((vmcs12
->cr3_target_count
>= 1 &&
7402 vmcs12
->cr3_target_value0
== val
) ||
7403 (vmcs12
->cr3_target_count
>= 2 &&
7404 vmcs12
->cr3_target_value1
== val
) ||
7405 (vmcs12
->cr3_target_count
>= 3 &&
7406 vmcs12
->cr3_target_value2
== val
) ||
7407 (vmcs12
->cr3_target_count
>= 4 &&
7408 vmcs12
->cr3_target_value3
== val
))
7410 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7414 if (vmcs12
->cr4_guest_host_mask
&
7415 (vmcs12
->cr4_read_shadow
^ val
))
7419 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7425 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7426 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7429 case 1: /* mov from cr */
7432 if (vmcs12
->cpu_based_vm_exec_control
&
7433 CPU_BASED_CR3_STORE_EXITING
)
7437 if (vmcs12
->cpu_based_vm_exec_control
&
7438 CPU_BASED_CR8_STORE_EXITING
)
7445 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7446 * cr0. Other attempted changes are ignored, with no exit.
7448 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7449 (val
^ vmcs12
->cr0_read_shadow
))
7451 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7452 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7461 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7462 * should handle it ourselves in L0 (and then continue L2). Only call this
7463 * when in is_guest_mode (L2).
7465 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7467 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7469 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7470 u32 exit_reason
= vmx
->exit_reason
;
7472 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7473 vmcs_readl(EXIT_QUALIFICATION
),
7474 vmx
->idt_vectoring_info
,
7476 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7479 if (vmx
->nested
.nested_run_pending
)
7482 if (unlikely(vmx
->fail
)) {
7483 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7484 vmcs_read32(VM_INSTRUCTION_ERROR
));
7488 switch (exit_reason
) {
7489 case EXIT_REASON_EXCEPTION_NMI
:
7490 if (!is_exception(intr_info
))
7492 else if (is_page_fault(intr_info
))
7494 else if (is_no_device(intr_info
) &&
7495 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7497 return vmcs12
->exception_bitmap
&
7498 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7499 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7501 case EXIT_REASON_TRIPLE_FAULT
:
7503 case EXIT_REASON_PENDING_INTERRUPT
:
7504 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7505 case EXIT_REASON_NMI_WINDOW
:
7506 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7507 case EXIT_REASON_TASK_SWITCH
:
7509 case EXIT_REASON_CPUID
:
7510 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7513 case EXIT_REASON_HLT
:
7514 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7515 case EXIT_REASON_INVD
:
7517 case EXIT_REASON_INVLPG
:
7518 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7519 case EXIT_REASON_RDPMC
:
7520 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7521 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7522 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7523 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7524 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7525 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7526 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7527 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7528 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7530 * VMX instructions trap unconditionally. This allows L1 to
7531 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7534 case EXIT_REASON_CR_ACCESS
:
7535 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7536 case EXIT_REASON_DR_ACCESS
:
7537 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7538 case EXIT_REASON_IO_INSTRUCTION
:
7539 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7540 case EXIT_REASON_MSR_READ
:
7541 case EXIT_REASON_MSR_WRITE
:
7542 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7543 case EXIT_REASON_INVALID_STATE
:
7545 case EXIT_REASON_MWAIT_INSTRUCTION
:
7546 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7547 case EXIT_REASON_MONITOR_INSTRUCTION
:
7548 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7549 case EXIT_REASON_PAUSE_INSTRUCTION
:
7550 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7551 nested_cpu_has2(vmcs12
,
7552 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7553 case EXIT_REASON_MCE_DURING_VMENTRY
:
7555 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7556 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7557 case EXIT_REASON_APIC_ACCESS
:
7558 return nested_cpu_has2(vmcs12
,
7559 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7560 case EXIT_REASON_APIC_WRITE
:
7561 case EXIT_REASON_EOI_INDUCED
:
7562 /* apic_write and eoi_induced should exit unconditionally. */
7564 case EXIT_REASON_EPT_VIOLATION
:
7566 * L0 always deals with the EPT violation. If nested EPT is
7567 * used, and the nested mmu code discovers that the address is
7568 * missing in the guest EPT table (EPT12), the EPT violation
7569 * will be injected with nested_ept_inject_page_fault()
7572 case EXIT_REASON_EPT_MISCONFIG
:
7574 * L2 never uses directly L1's EPT, but rather L0's own EPT
7575 * table (shadow on EPT) or a merged EPT table that L0 built
7576 * (EPT on EPT). So any problems with the structure of the
7577 * table is L0's fault.
7580 case EXIT_REASON_WBINVD
:
7581 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7582 case EXIT_REASON_XSETBV
:
7584 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7586 * This should never happen, since it is not possible to
7587 * set XSS to a non-zero value---neither in L1 nor in L2.
7588 * If if it were, XSS would have to be checked against
7589 * the XSS exit bitmap in vmcs12.
7591 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7597 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7599 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7600 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7603 static int vmx_enable_pml(struct vcpu_vmx
*vmx
)
7605 struct page
*pml_pg
;
7608 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7612 vmx
->pml_pg
= pml_pg
;
7614 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7615 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7617 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7618 exec_control
|= SECONDARY_EXEC_ENABLE_PML
;
7619 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7624 static void vmx_disable_pml(struct vcpu_vmx
*vmx
)
7628 ASSERT(vmx
->pml_pg
);
7629 __free_page(vmx
->pml_pg
);
7632 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7633 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
7634 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7637 static void vmx_flush_pml_buffer(struct vcpu_vmx
*vmx
)
7639 struct kvm
*kvm
= vmx
->vcpu
.kvm
;
7643 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7645 /* Do nothing if PML buffer is empty */
7646 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7649 /* PML index always points to next available PML buffer entity */
7650 if (pml_idx
>= PML_ENTITY_NUM
)
7655 pml_buf
= page_address(vmx
->pml_pg
);
7656 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7659 gpa
= pml_buf
[pml_idx
];
7660 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7661 mark_page_dirty(kvm
, gpa
>> PAGE_SHIFT
);
7664 /* reset PML index */
7665 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7669 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7670 * Called before reporting dirty_bitmap to userspace.
7672 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7675 struct kvm_vcpu
*vcpu
;
7677 * We only need to kick vcpu out of guest mode here, as PML buffer
7678 * is flushed at beginning of all VMEXITs, and it's obvious that only
7679 * vcpus running in guest are possible to have unflushed GPAs in PML
7682 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7683 kvm_vcpu_kick(vcpu
);
7687 * The guest has exited. See if we can fix it or if we need userspace
7690 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
7692 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7693 u32 exit_reason
= vmx
->exit_reason
;
7694 u32 vectoring_info
= vmx
->idt_vectoring_info
;
7697 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
7698 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
7699 * querying dirty_bitmap, we only need to kick all vcpus out of guest
7700 * mode as if vcpus is in root mode, the PML buffer must has been
7704 vmx_flush_pml_buffer(vmx
);
7706 /* If guest state is invalid, start emulating */
7707 if (vmx
->emulation_required
)
7708 return handle_invalid_guest_state(vcpu
);
7710 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
7711 nested_vmx_vmexit(vcpu
, exit_reason
,
7712 vmcs_read32(VM_EXIT_INTR_INFO
),
7713 vmcs_readl(EXIT_QUALIFICATION
));
7717 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
7718 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7719 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7724 if (unlikely(vmx
->fail
)) {
7725 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
7726 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
7727 = vmcs_read32(VM_INSTRUCTION_ERROR
);
7733 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
7734 * delivery event since it indicates guest is accessing MMIO.
7735 * The vm-exit can be triggered again after return to guest that
7736 * will cause infinite loop.
7738 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7739 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
7740 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
7741 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
7742 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7743 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7744 vcpu
->run
->internal
.ndata
= 2;
7745 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7746 vcpu
->run
->internal
.data
[1] = exit_reason
;
7750 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7751 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7752 get_vmcs12(vcpu
))))) {
7753 if (vmx_interrupt_allowed(vcpu
)) {
7754 vmx
->soft_vnmi_blocked
= 0;
7755 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7756 vcpu
->arch
.nmi_pending
) {
7758 * This CPU don't support us in finding the end of an
7759 * NMI-blocked window if the guest runs with IRQs
7760 * disabled. So we pull the trigger after 1 s of
7761 * futile waiting, but inform the user about this.
7763 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7764 "state on VCPU %d after 1 s timeout\n",
7765 __func__
, vcpu
->vcpu_id
);
7766 vmx
->soft_vnmi_blocked
= 0;
7770 if (exit_reason
< kvm_vmx_max_exit_handlers
7771 && kvm_vmx_exit_handlers
[exit_reason
])
7772 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7774 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
7775 kvm_queue_exception(vcpu
, UD_VECTOR
);
7780 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7782 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7784 if (is_guest_mode(vcpu
) &&
7785 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
7788 if (irr
== -1 || tpr
< irr
) {
7789 vmcs_write32(TPR_THRESHOLD
, 0);
7793 vmcs_write32(TPR_THRESHOLD
, irr
);
7796 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7798 u32 sec_exec_control
;
7801 * There is not point to enable virtualize x2apic without enable
7804 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7805 !vmx_vm_has_apicv(vcpu
->kvm
))
7808 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7811 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7814 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7815 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7817 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7818 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7820 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7822 vmx_set_msr_bitmap(vcpu
);
7825 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
7827 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7830 * Currently we do not handle the nested case where L2 has an
7831 * APIC access page of its own; that page is still pinned.
7832 * Hence, we skip the case where the VCPU is in guest mode _and_
7833 * L1 prepared an APIC access page for L2.
7835 * For the case where L1 and L2 share the same APIC access page
7836 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
7837 * in the vmcs12), this function will only update either the vmcs01
7838 * or the vmcs02. If the former, the vmcs02 will be updated by
7839 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
7840 * the next L2->L1 exit.
7842 if (!is_guest_mode(vcpu
) ||
7843 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
7844 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
7845 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
7848 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7856 status
= vmcs_read16(GUEST_INTR_STATUS
);
7861 vmcs_write16(GUEST_INTR_STATUS
, status
);
7865 static void vmx_set_rvi(int vector
)
7873 status
= vmcs_read16(GUEST_INTR_STATUS
);
7874 old
= (u8
)status
& 0xff;
7875 if ((u8
)vector
!= old
) {
7877 status
|= (u8
)vector
;
7878 vmcs_write16(GUEST_INTR_STATUS
, status
);
7882 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7884 if (!is_guest_mode(vcpu
)) {
7885 vmx_set_rvi(max_irr
);
7893 * In guest mode. If a vmexit is needed, vmx_check_nested_events
7896 if (nested_exit_on_intr(vcpu
))
7900 * Else, fall back to pre-APICv interrupt injection since L2
7901 * is run without virtual interrupt delivery.
7903 if (!kvm_event_needs_reinjection(vcpu
) &&
7904 vmx_interrupt_allowed(vcpu
)) {
7905 kvm_queue_interrupt(vcpu
, max_irr
, false);
7906 vmx_inject_irq(vcpu
);
7910 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7912 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7915 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7916 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7917 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7918 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7921 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7925 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7926 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7929 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7930 exit_intr_info
= vmx
->exit_intr_info
;
7932 /* Handle machine checks before interrupts are enabled */
7933 if (is_machine_check(exit_intr_info
))
7934 kvm_machine_check();
7936 /* We need to handle NMIs before interrupts are enabled */
7937 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7938 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7939 kvm_before_handle_nmi(&vmx
->vcpu
);
7941 kvm_after_handle_nmi(&vmx
->vcpu
);
7945 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7947 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7950 * If external interrupt exists, IF bit is set in rflags/eflags on the
7951 * interrupt stack frame, and interrupt will be enabled on a return
7952 * from interrupt handler.
7954 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7955 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7956 unsigned int vector
;
7957 unsigned long entry
;
7959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7960 #ifdef CONFIG_X86_64
7964 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7965 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7966 entry
= gate_offset(*desc
);
7968 #ifdef CONFIG_X86_64
7969 "mov %%" _ASM_SP
", %[sp]\n\t"
7970 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7975 "orl $0x200, (%%" _ASM_SP
")\n\t"
7976 __ASM_SIZE(push
) " $%c[cs]\n\t"
7977 "call *%[entry]\n\t"
7979 #ifdef CONFIG_X86_64
7984 [ss
]"i"(__KERNEL_DS
),
7985 [cs
]"i"(__KERNEL_CS
)
7991 static bool vmx_mpx_supported(void)
7993 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7994 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7997 static bool vmx_xsaves_supported(void)
7999 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8000 SECONDARY_EXEC_XSAVES
;
8003 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8008 bool idtv_info_valid
;
8010 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8012 if (cpu_has_virtual_nmis()) {
8013 if (vmx
->nmi_known_unmasked
)
8016 * Can't use vmx->exit_intr_info since we're not sure what
8017 * the exit reason is.
8019 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8020 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8021 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8023 * SDM 3: 27.7.1.2 (September 2008)
8024 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8025 * a guest IRET fault.
8026 * SDM 3: 23.2.2 (September 2008)
8027 * Bit 12 is undefined in any of the following cases:
8028 * If the VM exit sets the valid bit in the IDT-vectoring
8029 * information field.
8030 * If the VM exit is due to a double fault.
8032 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8033 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8034 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8035 GUEST_INTR_STATE_NMI
);
8037 vmx
->nmi_known_unmasked
=
8038 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8039 & GUEST_INTR_STATE_NMI
);
8040 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8041 vmx
->vnmi_blocked_time
+=
8042 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8045 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8046 u32 idt_vectoring_info
,
8047 int instr_len_field
,
8048 int error_code_field
)
8052 bool idtv_info_valid
;
8054 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8056 vcpu
->arch
.nmi_injected
= false;
8057 kvm_clear_exception_queue(vcpu
);
8058 kvm_clear_interrupt_queue(vcpu
);
8060 if (!idtv_info_valid
)
8063 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8065 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8066 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8069 case INTR_TYPE_NMI_INTR
:
8070 vcpu
->arch
.nmi_injected
= true;
8072 * SDM 3: 27.7.1.2 (September 2008)
8073 * Clear bit "block by NMI" before VM entry if a NMI
8076 vmx_set_nmi_mask(vcpu
, false);
8078 case INTR_TYPE_SOFT_EXCEPTION
:
8079 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8081 case INTR_TYPE_HARD_EXCEPTION
:
8082 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8083 u32 err
= vmcs_read32(error_code_field
);
8084 kvm_requeue_exception_e(vcpu
, vector
, err
);
8086 kvm_requeue_exception(vcpu
, vector
);
8088 case INTR_TYPE_SOFT_INTR
:
8089 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8091 case INTR_TYPE_EXT_INTR
:
8092 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8099 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8101 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8102 VM_EXIT_INSTRUCTION_LEN
,
8103 IDT_VECTORING_ERROR_CODE
);
8106 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8108 __vmx_complete_interrupts(vcpu
,
8109 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8110 VM_ENTRY_INSTRUCTION_LEN
,
8111 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8113 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8116 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8119 struct perf_guest_switch_msr
*msrs
;
8121 msrs
= perf_guest_get_msrs(&nr_msrs
);
8126 for (i
= 0; i
< nr_msrs
; i
++)
8127 if (msrs
[i
].host
== msrs
[i
].guest
)
8128 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8130 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8134 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8137 unsigned long debugctlmsr
, cr4
;
8139 /* Record the guest's net vcpu time for enforced NMI injections. */
8140 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8141 vmx
->entry_time
= ktime_get();
8143 /* Don't enter VMX if guest state is invalid, let the exit handler
8144 start emulation until we arrive back to a valid state */
8145 if (vmx
->emulation_required
)
8148 if (vmx
->ple_window_dirty
) {
8149 vmx
->ple_window_dirty
= false;
8150 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8153 if (vmx
->nested
.sync_shadow_vmcs
) {
8154 copy_vmcs12_to_shadow(vmx
);
8155 vmx
->nested
.sync_shadow_vmcs
= false;
8158 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8159 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8160 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8161 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8163 cr4
= cr4_read_shadow();
8164 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8165 vmcs_writel(HOST_CR4
, cr4
);
8166 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8169 /* When single-stepping over STI and MOV SS, we must clear the
8170 * corresponding interruptibility bits in the guest state. Otherwise
8171 * vmentry fails as it then expects bit 14 (BS) in pending debug
8172 * exceptions being set, but that's not correct for the guest debugging
8174 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8175 vmx_set_interrupt_shadow(vcpu
, 0);
8177 atomic_switch_perf_msrs(vmx
);
8178 debugctlmsr
= get_debugctlmsr();
8180 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8182 /* Store host registers */
8183 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8184 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8185 "push %%" _ASM_CX
" \n\t"
8186 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8188 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8189 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8191 /* Reload cr2 if changed */
8192 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8193 "mov %%cr2, %%" _ASM_DX
" \n\t"
8194 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8196 "mov %%" _ASM_AX
", %%cr2 \n\t"
8198 /* Check if vmlaunch of vmresume is needed */
8199 "cmpl $0, %c[launched](%0) \n\t"
8200 /* Load guest registers. Don't clobber flags. */
8201 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8202 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8203 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8204 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8205 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8206 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8207 #ifdef CONFIG_X86_64
8208 "mov %c[r8](%0), %%r8 \n\t"
8209 "mov %c[r9](%0), %%r9 \n\t"
8210 "mov %c[r10](%0), %%r10 \n\t"
8211 "mov %c[r11](%0), %%r11 \n\t"
8212 "mov %c[r12](%0), %%r12 \n\t"
8213 "mov %c[r13](%0), %%r13 \n\t"
8214 "mov %c[r14](%0), %%r14 \n\t"
8215 "mov %c[r15](%0), %%r15 \n\t"
8217 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8219 /* Enter guest mode */
8221 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8223 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8225 /* Save guest registers, load host registers, keep flags */
8226 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8228 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8229 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8230 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8231 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8232 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8233 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8234 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8235 #ifdef CONFIG_X86_64
8236 "mov %%r8, %c[r8](%0) \n\t"
8237 "mov %%r9, %c[r9](%0) \n\t"
8238 "mov %%r10, %c[r10](%0) \n\t"
8239 "mov %%r11, %c[r11](%0) \n\t"
8240 "mov %%r12, %c[r12](%0) \n\t"
8241 "mov %%r13, %c[r13](%0) \n\t"
8242 "mov %%r14, %c[r14](%0) \n\t"
8243 "mov %%r15, %c[r15](%0) \n\t"
8245 "mov %%cr2, %%" _ASM_AX
" \n\t"
8246 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8248 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8249 "setbe %c[fail](%0) \n\t"
8250 ".pushsection .rodata \n\t"
8251 ".global vmx_return \n\t"
8252 "vmx_return: " _ASM_PTR
" 2b \n\t"
8254 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8255 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8256 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8257 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8258 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8259 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8260 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8261 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8262 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8263 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8264 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8265 #ifdef CONFIG_X86_64
8266 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8267 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8268 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8269 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8270 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8271 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8272 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8273 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8275 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8276 [wordsize
]"i"(sizeof(ulong
))
8278 #ifdef CONFIG_X86_64
8279 , "rax", "rbx", "rdi", "rsi"
8280 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8282 , "eax", "ebx", "edi", "esi"
8286 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8288 update_debugctlmsr(debugctlmsr
);
8290 #ifndef CONFIG_X86_64
8292 * The sysexit path does not restore ds/es, so we must set them to
8293 * a reasonable value ourselves.
8295 * We can't defer this to vmx_load_host_state() since that function
8296 * may be executed in interrupt context, which saves and restore segments
8297 * around it, nullifying its effect.
8299 loadsegment(ds
, __USER_DS
);
8300 loadsegment(es
, __USER_DS
);
8303 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8304 | (1 << VCPU_EXREG_RFLAGS
)
8305 | (1 << VCPU_EXREG_PDPTR
)
8306 | (1 << VCPU_EXREG_SEGMENTS
)
8307 | (1 << VCPU_EXREG_CR3
));
8308 vcpu
->arch
.regs_dirty
= 0;
8310 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8312 vmx
->loaded_vmcs
->launched
= 1;
8314 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8315 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
8318 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8319 * we did not inject a still-pending event to L1 now because of
8320 * nested_run_pending, we need to re-enable this bit.
8322 if (vmx
->nested
.nested_run_pending
)
8323 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8325 vmx
->nested
.nested_run_pending
= 0;
8327 vmx_complete_atomic_exit(vmx
);
8328 vmx_recover_nmi_blocking(vmx
);
8329 vmx_complete_interrupts(vmx
);
8332 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8334 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8337 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8341 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8343 vmx_vcpu_load(vcpu
, cpu
);
8348 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8350 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8353 vmx_disable_pml(vmx
);
8355 leave_guest_mode(vcpu
);
8356 vmx_load_vmcs01(vcpu
);
8358 free_loaded_vmcs(vmx
->loaded_vmcs
);
8359 kfree(vmx
->guest_msrs
);
8360 kvm_vcpu_uninit(vcpu
);
8361 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8364 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8367 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8371 return ERR_PTR(-ENOMEM
);
8375 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8379 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8380 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8384 if (!vmx
->guest_msrs
) {
8388 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8389 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8390 if (!vmx
->loaded_vmcs
->vmcs
)
8393 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8394 loaded_vmcs_init(vmx
->loaded_vmcs
);
8399 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8400 vmx
->vcpu
.cpu
= cpu
;
8401 err
= vmx_vcpu_setup(vmx
);
8402 vmx_vcpu_put(&vmx
->vcpu
);
8406 if (vm_need_virtualize_apic_accesses(kvm
)) {
8407 err
= alloc_apic_access_page(kvm
);
8413 if (!kvm
->arch
.ept_identity_map_addr
)
8414 kvm
->arch
.ept_identity_map_addr
=
8415 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8416 err
= init_rmode_identity_map(kvm
);
8422 nested_vmx_setup_ctls_msrs(vmx
);
8424 vmx
->nested
.posted_intr_nv
= -1;
8425 vmx
->nested
.current_vmptr
= -1ull;
8426 vmx
->nested
.current_vmcs12
= NULL
;
8429 * If PML is turned on, failure on enabling PML just results in failure
8430 * of creating the vcpu, therefore we can simplify PML logic (by
8431 * avoiding dealing with cases, such as enabling PML partially on vcpus
8432 * for the guest, etc.
8435 err
= vmx_enable_pml(vmx
);
8443 free_loaded_vmcs(vmx
->loaded_vmcs
);
8445 kfree(vmx
->guest_msrs
);
8447 kvm_vcpu_uninit(&vmx
->vcpu
);
8450 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8451 return ERR_PTR(err
);
8454 static void __init
vmx_check_processor_compat(void *rtn
)
8456 struct vmcs_config vmcs_conf
;
8459 if (setup_vmcs_config(&vmcs_conf
) < 0)
8461 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8462 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8463 smp_processor_id());
8468 static int get_ept_level(void)
8470 return VMX_EPT_DEFAULT_GAW
+ 1;
8473 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8477 /* For VT-d and EPT combination
8478 * 1. MMIO: always map as UC
8480 * a. VT-d without snooping control feature: can't guarantee the
8481 * result, try to trust guest.
8482 * b. VT-d with snooping control feature: snooping control feature of
8483 * VT-d engine can guarantee the cache correctness. Just set it
8484 * to WB to keep consistent with host. So the same as item 3.
8485 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8486 * consistent with host MTRR
8489 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
8490 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
8491 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
8492 VMX_EPT_MT_EPTE_SHIFT
;
8494 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
8500 static int vmx_get_lpage_level(void)
8502 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8503 return PT_DIRECTORY_LEVEL
;
8505 /* For shadow and EPT supported 1GB page */
8506 return PT_PDPE_LEVEL
;
8509 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8511 struct kvm_cpuid_entry2
*best
;
8512 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8515 vmx
->rdtscp_enabled
= false;
8516 if (vmx_rdtscp_supported()) {
8517 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8518 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
8519 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
8520 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
8521 vmx
->rdtscp_enabled
= true;
8523 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
8524 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8528 if (nested
&& !vmx
->rdtscp_enabled
)
8529 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8530 ~SECONDARY_EXEC_RDTSCP
;
8533 /* Exposing INVPCID only when PCID is exposed */
8534 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
8535 if (vmx_invpcid_supported() &&
8536 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
8537 guest_cpuid_has_pcid(vcpu
)) {
8538 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8539 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
8540 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8543 if (cpu_has_secondary_exec_ctrls()) {
8544 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8545 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
8546 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8550 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
8554 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
8556 if (func
== 1 && nested
)
8557 entry
->ecx
|= bit(X86_FEATURE_VMX
);
8560 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
8561 struct x86_exception
*fault
)
8563 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8566 if (fault
->error_code
& PFERR_RSVD_MASK
)
8567 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
8569 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
8570 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
8571 vmcs12
->guest_physical_address
= fault
->address
;
8574 /* Callbacks for nested_ept_init_mmu_context: */
8576 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
8578 /* return the page table to be shadowed - in our case, EPT12 */
8579 return get_vmcs12(vcpu
)->ept_pointer
;
8582 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
8584 WARN_ON(mmu_is_nested(vcpu
));
8585 kvm_init_shadow_ept_mmu(vcpu
,
8586 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
8587 VMX_EPT_EXECUTE_ONLY_BIT
);
8588 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
8589 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
8590 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
8592 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
8595 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
8597 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
8600 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
8603 bool inequality
, bit
;
8605 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
8607 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
8608 vmcs12
->page_fault_error_code_match
;
8609 return inequality
^ bit
;
8612 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
8613 struct x86_exception
*fault
)
8615 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8617 WARN_ON(!is_guest_mode(vcpu
));
8619 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
8620 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
8621 vmcs_read32(VM_EXIT_INTR_INFO
),
8622 vmcs_readl(EXIT_QUALIFICATION
));
8624 kvm_inject_page_fault(vcpu
, fault
);
8627 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
8628 struct vmcs12
*vmcs12
)
8630 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8631 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8633 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
8634 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
8635 vmcs12
->apic_access_addr
>> maxphyaddr
)
8639 * Translate L1 physical address to host physical
8640 * address for vmcs02. Keep the page pinned, so this
8641 * physical address remains valid. We keep a reference
8642 * to it so we can release it later.
8644 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
8645 nested_release_page(vmx
->nested
.apic_access_page
);
8646 vmx
->nested
.apic_access_page
=
8647 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
8650 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
8651 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
8652 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
8655 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
8656 nested_release_page(vmx
->nested
.virtual_apic_page
);
8657 vmx
->nested
.virtual_apic_page
=
8658 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
8661 * Failing the vm entry is _not_ what the processor does
8662 * but it's basically the only possibility we have.
8663 * We could still enter the guest if CR8 load exits are
8664 * enabled, CR8 store exits are enabled, and virtualize APIC
8665 * access is disabled; in this case the processor would never
8666 * use the TPR shadow and we could simply clear the bit from
8667 * the execution control. But such a configuration is useless,
8668 * so let's keep the code simple.
8670 if (!vmx
->nested
.virtual_apic_page
)
8674 if (nested_cpu_has_posted_intr(vmcs12
)) {
8675 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
8676 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
8679 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
8680 kunmap(vmx
->nested
.pi_desc_page
);
8681 nested_release_page(vmx
->nested
.pi_desc_page
);
8683 vmx
->nested
.pi_desc_page
=
8684 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
8685 if (!vmx
->nested
.pi_desc_page
)
8688 vmx
->nested
.pi_desc
=
8689 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
8690 if (!vmx
->nested
.pi_desc
) {
8691 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
8694 vmx
->nested
.pi_desc
=
8695 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
8696 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
8703 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
8705 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
8706 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8708 if (vcpu
->arch
.virtual_tsc_khz
== 0)
8711 /* Make sure short timeouts reliably trigger an immediate vmexit.
8712 * hrtimer_start does not guarantee this. */
8713 if (preemption_timeout
<= 1) {
8714 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
8718 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8719 preemption_timeout
*= 1000000;
8720 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
8721 hrtimer_start(&vmx
->nested
.preemption_timer
,
8722 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
8725 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
8726 struct vmcs12
*vmcs12
)
8731 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
8734 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
8738 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8740 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
8741 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
8748 * Merge L0's and L1's MSR bitmap, return false to indicate that
8749 * we do not use the hardware.
8751 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
8752 struct vmcs12
*vmcs12
)
8756 unsigned long *msr_bitmap
;
8758 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
8761 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
8766 msr_bitmap
= (unsigned long *)kmap(page
);
8768 nested_release_page_clean(page
);
8773 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
8774 if (nested_cpu_has_apic_reg_virt(vmcs12
))
8775 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8776 nested_vmx_disable_intercept_for_msr(
8778 vmx_msr_bitmap_nested
,
8780 /* TPR is allowed */
8781 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
8782 vmx_msr_bitmap_nested
,
8783 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8784 MSR_TYPE_R
| MSR_TYPE_W
);
8785 if (nested_cpu_has_vid(vmcs12
)) {
8786 /* EOI and self-IPI are allowed */
8787 nested_vmx_disable_intercept_for_msr(
8789 vmx_msr_bitmap_nested
,
8790 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
8792 nested_vmx_disable_intercept_for_msr(
8794 vmx_msr_bitmap_nested
,
8795 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
8800 * Enable reading intercept of all the x2apic
8801 * MSRs. We should not rely on vmcs12 to do any
8802 * optimizations here, it may have been modified
8805 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8806 __vmx_enable_intercept_for_msr(
8807 vmx_msr_bitmap_nested
,
8811 __vmx_enable_intercept_for_msr(
8812 vmx_msr_bitmap_nested
,
8813 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
8815 __vmx_enable_intercept_for_msr(
8816 vmx_msr_bitmap_nested
,
8817 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
8819 __vmx_enable_intercept_for_msr(
8820 vmx_msr_bitmap_nested
,
8821 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
8825 nested_release_page_clean(page
);
8830 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
8831 struct vmcs12
*vmcs12
)
8833 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
8834 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
8835 !nested_cpu_has_vid(vmcs12
) &&
8836 !nested_cpu_has_posted_intr(vmcs12
))
8840 * If virtualize x2apic mode is enabled,
8841 * virtualize apic access must be disabled.
8843 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
8844 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8848 * If virtual interrupt delivery is enabled,
8849 * we must exit on external interrupts.
8851 if (nested_cpu_has_vid(vmcs12
) &&
8852 !nested_exit_on_intr(vcpu
))
8856 * bits 15:8 should be zero in posted_intr_nv,
8857 * the descriptor address has been already checked
8858 * in nested_get_vmcs12_pages.
8860 if (nested_cpu_has_posted_intr(vmcs12
) &&
8861 (!nested_cpu_has_vid(vmcs12
) ||
8862 !nested_exit_intr_ack_set(vcpu
) ||
8863 vmcs12
->posted_intr_nv
& 0xff00))
8866 /* tpr shadow is needed by all apicv features. */
8867 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8873 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
8874 unsigned long count_field
,
8875 unsigned long addr_field
)
8880 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
8881 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
8887 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
8888 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
8889 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
8890 pr_warn_ratelimited(
8891 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
8892 addr_field
, maxphyaddr
, count
, addr
);
8898 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
8899 struct vmcs12
*vmcs12
)
8901 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
8902 vmcs12
->vm_exit_msr_store_count
== 0 &&
8903 vmcs12
->vm_entry_msr_load_count
== 0)
8904 return 0; /* Fast path */
8905 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
8906 VM_EXIT_MSR_LOAD_ADDR
) ||
8907 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
8908 VM_EXIT_MSR_STORE_ADDR
) ||
8909 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
8910 VM_ENTRY_MSR_LOAD_ADDR
))
8915 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
8916 struct vmx_msr_entry
*e
)
8918 /* x2APIC MSR accesses are not allowed */
8919 if (apic_x2apic_mode(vcpu
->arch
.apic
) && e
->index
>> 8 == 0x8)
8921 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
8922 e
->index
== MSR_IA32_UCODE_REV
)
8924 if (e
->reserved
!= 0)
8929 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
8930 struct vmx_msr_entry
*e
)
8932 if (e
->index
== MSR_FS_BASE
||
8933 e
->index
== MSR_GS_BASE
||
8934 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
8935 nested_vmx_msr_check_common(vcpu
, e
))
8940 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
8941 struct vmx_msr_entry
*e
)
8943 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
8944 nested_vmx_msr_check_common(vcpu
, e
))
8950 * Load guest's/host's msr at nested entry/exit.
8951 * return 0 for success, entry index for failure.
8953 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
8956 struct vmx_msr_entry e
;
8957 struct msr_data msr
;
8959 msr
.host_initiated
= false;
8960 for (i
= 0; i
< count
; i
++) {
8961 if (kvm_read_guest(vcpu
->kvm
, gpa
+ i
* sizeof(e
),
8963 pr_warn_ratelimited(
8964 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8965 __func__
, i
, gpa
+ i
* sizeof(e
));
8968 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
8969 pr_warn_ratelimited(
8970 "%s check failed (%u, 0x%x, 0x%x)\n",
8971 __func__
, i
, e
.index
, e
.reserved
);
8974 msr
.index
= e
.index
;
8976 if (kvm_set_msr(vcpu
, &msr
)) {
8977 pr_warn_ratelimited(
8978 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
8979 __func__
, i
, e
.index
, e
.value
);
8988 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
8991 struct vmx_msr_entry e
;
8993 for (i
= 0; i
< count
; i
++) {
8994 if (kvm_read_guest(vcpu
->kvm
,
8995 gpa
+ i
* sizeof(e
),
8996 &e
, 2 * sizeof(u32
))) {
8997 pr_warn_ratelimited(
8998 "%s cannot read MSR entry (%u, 0x%08llx)\n",
8999 __func__
, i
, gpa
+ i
* sizeof(e
));
9002 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9003 pr_warn_ratelimited(
9004 "%s check failed (%u, 0x%x, 0x%x)\n",
9005 __func__
, i
, e
.index
, e
.reserved
);
9008 if (kvm_get_msr(vcpu
, e
.index
, &e
.value
)) {
9009 pr_warn_ratelimited(
9010 "%s cannot read MSR (%u, 0x%x)\n",
9011 __func__
, i
, e
.index
);
9014 if (kvm_write_guest(vcpu
->kvm
,
9015 gpa
+ i
* sizeof(e
) +
9016 offsetof(struct vmx_msr_entry
, value
),
9017 &e
.value
, sizeof(e
.value
))) {
9018 pr_warn_ratelimited(
9019 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9020 __func__
, i
, e
.index
, e
.value
);
9028 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9029 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9030 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9031 * guest in a way that will both be appropriate to L1's requests, and our
9032 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9033 * function also has additional necessary side-effects, like setting various
9034 * vcpu->arch fields.
9036 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9038 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9041 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9042 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9043 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9044 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9045 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9046 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9047 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9048 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9049 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9050 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9051 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9052 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9053 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9054 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9055 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9056 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9057 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9058 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9059 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9060 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9061 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9062 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9063 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9064 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9065 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9066 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9067 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9068 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9069 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9070 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9071 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9072 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9073 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9074 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9075 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9076 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9078 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9079 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9080 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9082 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9083 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9085 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9086 vmcs12
->vm_entry_intr_info_field
);
9087 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9088 vmcs12
->vm_entry_exception_error_code
);
9089 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9090 vmcs12
->vm_entry_instruction_len
);
9091 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9092 vmcs12
->guest_interruptibility_info
);
9093 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9094 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9095 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9096 vmcs12
->guest_pending_dbg_exceptions
);
9097 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9098 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9100 if (nested_cpu_has_xsaves(vmcs12
))
9101 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9102 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9104 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9105 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9106 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9108 if (nested_cpu_has_posted_intr(vmcs12
)) {
9110 * Note that we use L0's vector here and in
9111 * vmx_deliver_nested_posted_interrupt.
9113 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9114 vmx
->nested
.pi_pending
= false;
9115 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9116 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9117 page_to_phys(vmx
->nested
.pi_desc_page
) +
9118 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9121 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9123 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9125 vmx
->nested
.preemption_timer_expired
= false;
9126 if (nested_cpu_has_preemption_timer(vmcs12
))
9127 vmx_start_preemption_timer(vcpu
);
9130 * Whether page-faults are trapped is determined by a combination of
9131 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9132 * If enable_ept, L0 doesn't care about page faults and we should
9133 * set all of these to L1's desires. However, if !enable_ept, L0 does
9134 * care about (at least some) page faults, and because it is not easy
9135 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9136 * to exit on each and every L2 page fault. This is done by setting
9137 * MASK=MATCH=0 and (see below) EB.PF=1.
9138 * Note that below we don't need special code to set EB.PF beyond the
9139 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9140 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9141 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9143 * A problem with this approach (when !enable_ept) is that L1 may be
9144 * injected with more page faults than it asked for. This could have
9145 * caused problems, but in practice existing hypervisors don't care.
9146 * To fix this, we will need to emulate the PFEC checking (on the L1
9147 * page tables), using walk_addr(), when injecting PFs to L1.
9149 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9150 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9151 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9152 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9154 if (cpu_has_secondary_exec_ctrls()) {
9155 exec_control
= vmx_secondary_exec_control(vmx
);
9156 if (!vmx
->rdtscp_enabled
)
9157 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
9158 /* Take the following fields only from vmcs12 */
9159 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9160 SECONDARY_EXEC_RDTSCP
|
9161 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9162 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
9163 if (nested_cpu_has(vmcs12
,
9164 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9165 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9167 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9169 * If translation failed, no matter: This feature asks
9170 * to exit when accessing the given address, and if it
9171 * can never be accessed, this feature won't do
9174 if (!vmx
->nested
.apic_access_page
)
9176 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9178 vmcs_write64(APIC_ACCESS_ADDR
,
9179 page_to_phys(vmx
->nested
.apic_access_page
));
9180 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9181 (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))) {
9183 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9184 kvm_vcpu_reload_apic_access_page(vcpu
);
9187 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9188 vmcs_write64(EOI_EXIT_BITMAP0
,
9189 vmcs12
->eoi_exit_bitmap0
);
9190 vmcs_write64(EOI_EXIT_BITMAP1
,
9191 vmcs12
->eoi_exit_bitmap1
);
9192 vmcs_write64(EOI_EXIT_BITMAP2
,
9193 vmcs12
->eoi_exit_bitmap2
);
9194 vmcs_write64(EOI_EXIT_BITMAP3
,
9195 vmcs12
->eoi_exit_bitmap3
);
9196 vmcs_write16(GUEST_INTR_STATUS
,
9197 vmcs12
->guest_intr_status
);
9200 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9205 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9206 * Some constant fields are set here by vmx_set_constant_host_state().
9207 * Other fields are different per CPU, and will be set later when
9208 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9210 vmx_set_constant_host_state(vmx
);
9213 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9214 * entry, but only if the current (host) sp changed from the value
9215 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9216 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9217 * here we just force the write to happen on entry.
9221 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9222 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9223 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9224 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9225 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9227 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9228 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9229 page_to_phys(vmx
->nested
.virtual_apic_page
));
9230 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9233 if (cpu_has_vmx_msr_bitmap() &&
9234 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9235 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9236 /* MSR_BITMAP will be set by following vmx_set_efer. */
9238 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9241 * Merging of IO bitmap not currently supported.
9242 * Rather, exit every time.
9244 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9245 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9247 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9249 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9250 * bitwise-or of what L1 wants to trap for L2, and what we want to
9251 * trap. Note that CR0.TS also needs updating - we do this later.
9253 update_exception_bitmap(vcpu
);
9254 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9255 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9257 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9258 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9259 * bits are further modified by vmx_set_efer() below.
9261 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9263 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9264 * emulated by vmx_set_efer(), below.
9266 vm_entry_controls_init(vmx
,
9267 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9268 ~VM_ENTRY_IA32E_MODE
) |
9269 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9271 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9272 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9273 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9274 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9275 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9278 set_cr4_guest_host_mask(vmx
);
9280 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9281 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9283 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9284 vmcs_write64(TSC_OFFSET
,
9285 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9287 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9291 * Trivially support vpid by letting L2s share their parent
9292 * L1's vpid. TODO: move to a more elaborate solution, giving
9293 * each L2 its own vpid and exposing the vpid feature to L1.
9295 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9296 vmx_flush_tlb(vcpu
);
9299 if (nested_cpu_has_ept(vmcs12
)) {
9300 kvm_mmu_unload(vcpu
);
9301 nested_ept_init_mmu_context(vcpu
);
9304 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9305 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9306 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9307 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9309 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9310 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9311 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9314 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9315 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9316 * The CR0_READ_SHADOW is what L2 should have expected to read given
9317 * the specifications by L1; It's not enough to take
9318 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9319 * have more bits than L1 expected.
9321 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9322 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9324 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9325 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9327 /* shadow page tables on either EPT or shadow page tables */
9328 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9329 kvm_mmu_reset_context(vcpu
);
9332 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9335 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9338 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9339 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9340 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9341 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9344 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9345 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9349 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9350 * for running an L2 nested guest.
9352 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9354 struct vmcs12
*vmcs12
;
9355 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9357 struct loaded_vmcs
*vmcs02
;
9361 if (!nested_vmx_check_permission(vcpu
) ||
9362 !nested_vmx_check_vmcs12(vcpu
))
9365 skip_emulated_instruction(vcpu
);
9366 vmcs12
= get_vmcs12(vcpu
);
9368 if (enable_shadow_vmcs
)
9369 copy_shadow_to_vmcs12(vmx
);
9372 * The nested entry process starts with enforcing various prerequisites
9373 * on vmcs12 as required by the Intel SDM, and act appropriately when
9374 * they fail: As the SDM explains, some conditions should cause the
9375 * instruction to fail, while others will cause the instruction to seem
9376 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9377 * To speed up the normal (success) code path, we should avoid checking
9378 * for misconfigurations which will anyway be caught by the processor
9379 * when using the merged vmcs02.
9381 if (vmcs12
->launch_state
== launch
) {
9382 nested_vmx_failValid(vcpu
,
9383 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9384 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9388 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9389 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9390 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9394 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9395 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9399 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9400 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9404 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9405 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9409 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9410 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9414 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9415 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9416 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9417 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9418 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9419 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9420 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9421 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9422 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9423 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9424 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9425 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9426 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9427 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9428 vmx
->nested
.nested_vmx_entry_ctls_high
))
9430 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9434 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9435 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9436 nested_vmx_failValid(vcpu
,
9437 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9441 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9442 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9443 nested_vmx_entry_failure(vcpu
, vmcs12
,
9444 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9447 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9448 nested_vmx_entry_failure(vcpu
, vmcs12
,
9449 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9454 * If the load IA32_EFER VM-entry control is 1, the following checks
9455 * are performed on the field for the IA32_EFER MSR:
9456 * - Bits reserved in the IA32_EFER MSR must be 0.
9457 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9458 * the IA-32e mode guest VM-exit control. It must also be identical
9459 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9462 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9463 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9464 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9465 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9466 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9467 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9468 nested_vmx_entry_failure(vcpu
, vmcs12
,
9469 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9475 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9476 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9477 * the values of the LMA and LME bits in the field must each be that of
9478 * the host address-space size VM-exit control.
9480 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9481 ia32e
= (vmcs12
->vm_exit_controls
&
9482 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9483 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9484 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9485 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9486 nested_vmx_entry_failure(vcpu
, vmcs12
,
9487 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9493 * We're finally done with prerequisite checking, and can start with
9497 vmcs02
= nested_get_current_vmcs02(vmx
);
9501 enter_guest_mode(vcpu
);
9503 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9505 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9506 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9509 vmx
->loaded_vmcs
= vmcs02
;
9511 vmx_vcpu_load(vcpu
, cpu
);
9515 vmx_segment_cache_clear(vmx
);
9517 prepare_vmcs02(vcpu
, vmcs12
);
9519 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
9520 vmcs12
->vm_entry_msr_load_addr
,
9521 vmcs12
->vm_entry_msr_load_count
);
9522 if (msr_entry_idx
) {
9523 leave_guest_mode(vcpu
);
9524 vmx_load_vmcs01(vcpu
);
9525 nested_vmx_entry_failure(vcpu
, vmcs12
,
9526 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
9530 vmcs12
->launch_state
= 1;
9532 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
9533 return kvm_vcpu_halt(vcpu
);
9535 vmx
->nested
.nested_run_pending
= 1;
9538 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9539 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9540 * returned as far as L1 is concerned. It will only return (and set
9541 * the success flag) when L2 exits (see nested_vmx_vmexit()).
9547 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9548 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9549 * This function returns the new value we should put in vmcs12.guest_cr0.
9550 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9551 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9552 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9553 * didn't trap the bit, because if L1 did, so would L0).
9554 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9555 * been modified by L2, and L1 knows it. So just leave the old value of
9556 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
9557 * isn't relevant, because if L0 traps this bit it can set it to anything.
9558 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
9559 * changed these bits, and therefore they need to be updated, but L0
9560 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
9561 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
9563 static inline unsigned long
9564 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9567 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
9568 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
9569 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
9570 vcpu
->arch
.cr0_guest_owned_bits
));
9573 static inline unsigned long
9574 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9577 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
9578 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
9579 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
9580 vcpu
->arch
.cr4_guest_owned_bits
));
9583 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
9584 struct vmcs12
*vmcs12
)
9589 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
9590 nr
= vcpu
->arch
.exception
.nr
;
9591 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9593 if (kvm_exception_is_soft(nr
)) {
9594 vmcs12
->vm_exit_instruction_len
=
9595 vcpu
->arch
.event_exit_inst_len
;
9596 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
9598 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
9600 if (vcpu
->arch
.exception
.has_error_code
) {
9601 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
9602 vmcs12
->idt_vectoring_error_code
=
9603 vcpu
->arch
.exception
.error_code
;
9606 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9607 } else if (vcpu
->arch
.nmi_injected
) {
9608 vmcs12
->idt_vectoring_info_field
=
9609 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
9610 } else if (vcpu
->arch
.interrupt
.pending
) {
9611 nr
= vcpu
->arch
.interrupt
.nr
;
9612 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
9614 if (vcpu
->arch
.interrupt
.soft
) {
9615 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
9616 vmcs12
->vm_entry_instruction_len
=
9617 vcpu
->arch
.event_exit_inst_len
;
9619 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
9621 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
9625 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
9627 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9629 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
9630 vmx
->nested
.preemption_timer_expired
) {
9631 if (vmx
->nested
.nested_run_pending
)
9633 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
9637 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
9638 if (vmx
->nested
.nested_run_pending
||
9639 vcpu
->arch
.interrupt
.pending
)
9641 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
9642 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
9643 INTR_INFO_VALID_MASK
, 0);
9645 * The NMI-triggered VM exit counts as injection:
9646 * clear this one and block further NMIs.
9648 vcpu
->arch
.nmi_pending
= 0;
9649 vmx_set_nmi_mask(vcpu
, true);
9653 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
9654 nested_exit_on_intr(vcpu
)) {
9655 if (vmx
->nested
.nested_run_pending
)
9657 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
9661 return vmx_complete_nested_posted_interrupt(vcpu
);
9664 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
9667 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
9670 if (ktime_to_ns(remaining
) <= 0)
9673 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
9674 do_div(value
, 1000000);
9675 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9679 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
9680 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
9681 * and this function updates it to reflect the changes to the guest state while
9682 * L2 was running (and perhaps made some exits which were handled directly by L0
9683 * without going back to L1), and to reflect the exit reason.
9684 * Note that we do not have to copy here all VMCS fields, just those that
9685 * could have changed by the L2 guest or the exit - i.e., the guest-state and
9686 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
9687 * which already writes to vmcs12 directly.
9689 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
9690 u32 exit_reason
, u32 exit_intr_info
,
9691 unsigned long exit_qualification
)
9693 /* update guest state fields: */
9694 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
9695 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
9697 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
9698 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
9699 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
9701 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
9702 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
9703 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
9704 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
9705 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
9706 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
9707 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
9708 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
9709 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
9710 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
9711 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
9712 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
9713 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
9714 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
9715 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
9716 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
9717 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
9718 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
9719 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
9720 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
9721 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
9722 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
9723 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
9724 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
9725 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
9726 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
9727 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
9728 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
9729 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
9730 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
9731 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
9732 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
9733 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
9734 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
9735 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
9736 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
9738 vmcs12
->guest_interruptibility_info
=
9739 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
9740 vmcs12
->guest_pending_dbg_exceptions
=
9741 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
9742 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
9743 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
9745 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
9747 if (nested_cpu_has_preemption_timer(vmcs12
)) {
9748 if (vmcs12
->vm_exit_controls
&
9749 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
9750 vmcs12
->vmx_preemption_timer_value
=
9751 vmx_get_preemption_timer_value(vcpu
);
9752 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
9756 * In some cases (usually, nested EPT), L2 is allowed to change its
9757 * own CR3 without exiting. If it has changed it, we must keep it.
9758 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
9759 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
9761 * Additionally, restore L2's PDPTR to vmcs12.
9764 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
9765 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
9766 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
9767 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
9768 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
9771 if (nested_cpu_has_vid(vmcs12
))
9772 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
9774 vmcs12
->vm_entry_controls
=
9775 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
9776 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
9778 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
9779 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
9780 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9783 /* TODO: These cannot have changed unless we have MSR bitmaps and
9784 * the relevant bit asks not to trap the change */
9785 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
9786 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
9787 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
9788 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
9789 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
9790 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
9791 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
9792 if (vmx_mpx_supported())
9793 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
9794 if (nested_cpu_has_xsaves(vmcs12
))
9795 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
9797 /* update exit information fields: */
9799 vmcs12
->vm_exit_reason
= exit_reason
;
9800 vmcs12
->exit_qualification
= exit_qualification
;
9802 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
9803 if ((vmcs12
->vm_exit_intr_info
&
9804 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
9805 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
9806 vmcs12
->vm_exit_intr_error_code
=
9807 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
9808 vmcs12
->idt_vectoring_info_field
= 0;
9809 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
9810 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
9812 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
9813 /* vm_entry_intr_info_field is cleared on exit. Emulate this
9814 * instead of reading the real value. */
9815 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
9818 * Transfer the event that L0 or L1 may wanted to inject into
9819 * L2 to IDT_VECTORING_INFO_FIELD.
9821 vmcs12_save_pending_event(vcpu
, vmcs12
);
9825 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
9826 * preserved above and would only end up incorrectly in L1.
9828 vcpu
->arch
.nmi_injected
= false;
9829 kvm_clear_exception_queue(vcpu
);
9830 kvm_clear_interrupt_queue(vcpu
);
9834 * A part of what we need to when the nested L2 guest exits and we want to
9835 * run its L1 parent, is to reset L1's guest state to the host state specified
9837 * This function is to be called not only on normal nested exit, but also on
9838 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
9839 * Failures During or After Loading Guest State").
9840 * This function should be called when the active VMCS is L1's (vmcs01).
9842 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
9843 struct vmcs12
*vmcs12
)
9845 struct kvm_segment seg
;
9847 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
9848 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
9849 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
9850 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9852 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9853 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9855 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
9856 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
9857 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
9859 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
9860 * actually changed, because it depends on the current state of
9861 * fpu_active (which may have changed).
9862 * Note that vmx_set_cr0 refers to efer set above.
9864 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
9866 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
9867 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
9868 * but we also need to update cr0_guest_host_mask and exception_bitmap.
9870 update_exception_bitmap(vcpu
);
9871 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
9872 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9875 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
9876 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
9878 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
9879 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
9881 nested_ept_uninit_mmu_context(vcpu
);
9883 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
9884 kvm_mmu_reset_context(vcpu
);
9887 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
9891 * Trivially support vpid by letting L2s share their parent
9892 * L1's vpid. TODO: move to a more elaborate solution, giving
9893 * each L2 its own vpid and exposing the vpid feature to L1.
9895 vmx_flush_tlb(vcpu
);
9899 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
9900 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
9901 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
9902 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
9903 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
9905 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
9906 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
9907 vmcs_write64(GUEST_BNDCFGS
, 0);
9909 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
9910 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
9911 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
9913 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
9914 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
9915 vmcs12
->host_ia32_perf_global_ctrl
);
9917 /* Set L1 segment info according to Intel SDM
9918 27.5.2 Loading Host Segment and Descriptor-Table Registers */
9919 seg
= (struct kvm_segment
) {
9921 .limit
= 0xFFFFFFFF,
9922 .selector
= vmcs12
->host_cs_selector
,
9928 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
9932 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
9933 seg
= (struct kvm_segment
) {
9935 .limit
= 0xFFFFFFFF,
9942 seg
.selector
= vmcs12
->host_ds_selector
;
9943 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
9944 seg
.selector
= vmcs12
->host_es_selector
;
9945 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
9946 seg
.selector
= vmcs12
->host_ss_selector
;
9947 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
9948 seg
.selector
= vmcs12
->host_fs_selector
;
9949 seg
.base
= vmcs12
->host_fs_base
;
9950 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
9951 seg
.selector
= vmcs12
->host_gs_selector
;
9952 seg
.base
= vmcs12
->host_gs_base
;
9953 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
9954 seg
= (struct kvm_segment
) {
9955 .base
= vmcs12
->host_tr_base
,
9957 .selector
= vmcs12
->host_tr_selector
,
9961 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
9963 kvm_set_dr(vcpu
, 7, 0x400);
9964 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
9966 if (cpu_has_vmx_msr_bitmap())
9967 vmx_set_msr_bitmap(vcpu
);
9969 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
9970 vmcs12
->vm_exit_msr_load_count
))
9971 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
9975 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
9976 * and modify vmcs12 to make it see what it would expect to see there if
9977 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
9979 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
9981 unsigned long exit_qualification
)
9983 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9984 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9986 /* trying to cancel vmlaunch/vmresume is a bug */
9987 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
9989 leave_guest_mode(vcpu
);
9990 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
9991 exit_qualification
);
9993 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
9994 vmcs12
->vm_exit_msr_store_count
))
9995 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
9997 vmx_load_vmcs01(vcpu
);
9999 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10000 && nested_exit_intr_ack_set(vcpu
)) {
10001 int irq
= kvm_cpu_get_interrupt(vcpu
);
10003 vmcs12
->vm_exit_intr_info
= irq
|
10004 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10007 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10008 vmcs12
->exit_qualification
,
10009 vmcs12
->idt_vectoring_info_field
,
10010 vmcs12
->vm_exit_intr_info
,
10011 vmcs12
->vm_exit_intr_error_code
,
10014 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10015 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10016 vmx_segment_cache_clear(vmx
);
10018 /* if no vmcs02 cache requested, remove the one we used */
10019 if (VMCS02_POOL_SIZE
== 0)
10020 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10022 load_vmcs12_host_state(vcpu
, vmcs12
);
10024 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10025 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10027 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10030 /* Unpin physical memory we referred to in vmcs02 */
10031 if (vmx
->nested
.apic_access_page
) {
10032 nested_release_page(vmx
->nested
.apic_access_page
);
10033 vmx
->nested
.apic_access_page
= NULL
;
10035 if (vmx
->nested
.virtual_apic_page
) {
10036 nested_release_page(vmx
->nested
.virtual_apic_page
);
10037 vmx
->nested
.virtual_apic_page
= NULL
;
10039 if (vmx
->nested
.pi_desc_page
) {
10040 kunmap(vmx
->nested
.pi_desc_page
);
10041 nested_release_page(vmx
->nested
.pi_desc_page
);
10042 vmx
->nested
.pi_desc_page
= NULL
;
10043 vmx
->nested
.pi_desc
= NULL
;
10047 * We are now running in L2, mmu_notifier will force to reload the
10048 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10050 kvm_vcpu_reload_apic_access_page(vcpu
);
10053 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10054 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10055 * success or failure flag accordingly.
10057 if (unlikely(vmx
->fail
)) {
10059 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10061 nested_vmx_succeed(vcpu
);
10062 if (enable_shadow_vmcs
)
10063 vmx
->nested
.sync_shadow_vmcs
= true;
10065 /* in case we halted in L2 */
10066 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10070 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10072 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10074 if (is_guest_mode(vcpu
))
10075 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10076 free_nested(to_vmx(vcpu
));
10080 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10081 * 23.7 "VM-entry failures during or after loading guest state" (this also
10082 * lists the acceptable exit-reason and exit-qualification parameters).
10083 * It should only be called before L2 actually succeeded to run, and when
10084 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10086 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10087 struct vmcs12
*vmcs12
,
10088 u32 reason
, unsigned long qualification
)
10090 load_vmcs12_host_state(vcpu
, vmcs12
);
10091 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10092 vmcs12
->exit_qualification
= qualification
;
10093 nested_vmx_succeed(vcpu
);
10094 if (enable_shadow_vmcs
)
10095 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10098 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10099 struct x86_instruction_info
*info
,
10100 enum x86_intercept_stage stage
)
10102 return X86EMUL_CONTINUE
;
10105 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10108 shrink_ple_window(vcpu
);
10111 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10112 struct kvm_memory_slot
*slot
)
10114 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10115 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10118 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10119 struct kvm_memory_slot
*slot
)
10121 kvm_mmu_slot_set_dirty(kvm
, slot
);
10124 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10126 kvm_flush_pml_buffers(kvm
);
10129 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10130 struct kvm_memory_slot
*memslot
,
10131 gfn_t offset
, unsigned long mask
)
10133 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10136 static struct kvm_x86_ops vmx_x86_ops
= {
10137 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10138 .disabled_by_bios
= vmx_disabled_by_bios
,
10139 .hardware_setup
= hardware_setup
,
10140 .hardware_unsetup
= hardware_unsetup
,
10141 .check_processor_compatibility
= vmx_check_processor_compat
,
10142 .hardware_enable
= hardware_enable
,
10143 .hardware_disable
= hardware_disable
,
10144 .cpu_has_accelerated_tpr
= report_flexpriority
,
10146 .vcpu_create
= vmx_create_vcpu
,
10147 .vcpu_free
= vmx_free_vcpu
,
10148 .vcpu_reset
= vmx_vcpu_reset
,
10150 .prepare_guest_switch
= vmx_save_host_state
,
10151 .vcpu_load
= vmx_vcpu_load
,
10152 .vcpu_put
= vmx_vcpu_put
,
10154 .update_db_bp_intercept
= update_exception_bitmap
,
10155 .get_msr
= vmx_get_msr
,
10156 .set_msr
= vmx_set_msr
,
10157 .get_segment_base
= vmx_get_segment_base
,
10158 .get_segment
= vmx_get_segment
,
10159 .set_segment
= vmx_set_segment
,
10160 .get_cpl
= vmx_get_cpl
,
10161 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10162 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10163 .decache_cr3
= vmx_decache_cr3
,
10164 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10165 .set_cr0
= vmx_set_cr0
,
10166 .set_cr3
= vmx_set_cr3
,
10167 .set_cr4
= vmx_set_cr4
,
10168 .set_efer
= vmx_set_efer
,
10169 .get_idt
= vmx_get_idt
,
10170 .set_idt
= vmx_set_idt
,
10171 .get_gdt
= vmx_get_gdt
,
10172 .set_gdt
= vmx_set_gdt
,
10173 .get_dr6
= vmx_get_dr6
,
10174 .set_dr6
= vmx_set_dr6
,
10175 .set_dr7
= vmx_set_dr7
,
10176 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10177 .cache_reg
= vmx_cache_reg
,
10178 .get_rflags
= vmx_get_rflags
,
10179 .set_rflags
= vmx_set_rflags
,
10180 .fpu_deactivate
= vmx_fpu_deactivate
,
10182 .tlb_flush
= vmx_flush_tlb
,
10184 .run
= vmx_vcpu_run
,
10185 .handle_exit
= vmx_handle_exit
,
10186 .skip_emulated_instruction
= skip_emulated_instruction
,
10187 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10188 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10189 .patch_hypercall
= vmx_patch_hypercall
,
10190 .set_irq
= vmx_inject_irq
,
10191 .set_nmi
= vmx_inject_nmi
,
10192 .queue_exception
= vmx_queue_exception
,
10193 .cancel_injection
= vmx_cancel_injection
,
10194 .interrupt_allowed
= vmx_interrupt_allowed
,
10195 .nmi_allowed
= vmx_nmi_allowed
,
10196 .get_nmi_mask
= vmx_get_nmi_mask
,
10197 .set_nmi_mask
= vmx_set_nmi_mask
,
10198 .enable_nmi_window
= enable_nmi_window
,
10199 .enable_irq_window
= enable_irq_window
,
10200 .update_cr8_intercept
= update_cr8_intercept
,
10201 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10202 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10203 .vm_has_apicv
= vmx_vm_has_apicv
,
10204 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10205 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10206 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10207 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10208 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10210 .set_tss_addr
= vmx_set_tss_addr
,
10211 .get_tdp_level
= get_ept_level
,
10212 .get_mt_mask
= vmx_get_mt_mask
,
10214 .get_exit_info
= vmx_get_exit_info
,
10216 .get_lpage_level
= vmx_get_lpage_level
,
10218 .cpuid_update
= vmx_cpuid_update
,
10220 .rdtscp_supported
= vmx_rdtscp_supported
,
10221 .invpcid_supported
= vmx_invpcid_supported
,
10223 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10225 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10227 .set_tsc_khz
= vmx_set_tsc_khz
,
10228 .read_tsc_offset
= vmx_read_tsc_offset
,
10229 .write_tsc_offset
= vmx_write_tsc_offset
,
10230 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
10231 .compute_tsc_offset
= vmx_compute_tsc_offset
,
10232 .read_l1_tsc
= vmx_read_l1_tsc
,
10234 .set_tdp_cr3
= vmx_set_cr3
,
10236 .check_intercept
= vmx_check_intercept
,
10237 .handle_external_intr
= vmx_handle_external_intr
,
10238 .mpx_supported
= vmx_mpx_supported
,
10239 .xsaves_supported
= vmx_xsaves_supported
,
10241 .check_nested_events
= vmx_check_nested_events
,
10243 .sched_in
= vmx_sched_in
,
10245 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10246 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10247 .flush_log_dirty
= vmx_flush_log_dirty
,
10248 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10251 static int __init
vmx_init(void)
10253 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10254 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10258 #ifdef CONFIG_KEXEC
10259 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10260 crash_vmclear_local_loaded_vmcss
);
10266 static void __exit
vmx_exit(void)
10268 #ifdef CONFIG_KEXEC
10269 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10276 module_init(vmx_init
)
10277 module_exit(vmx_exit
)