2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
24 #include <linux/kvm_host.h>
25 #include <linux/module.h>
26 #include <linux/kernel.h>
28 #include <linux/highmem.h>
29 #include <linux/sched.h>
30 #include <linux/moduleparam.h>
31 #include <linux/mod_devicetable.h>
32 #include <linux/trace_events.h>
33 #include <linux/slab.h>
34 #include <linux/tboot.h>
35 #include <linux/hrtimer.h>
36 #include "kvm_cache_regs.h"
43 #include <asm/virtext.h>
45 #include <asm/fpu/internal.h>
46 #include <asm/perf_event.h>
47 #include <asm/debugreg.h>
48 #include <asm/kexec.h>
50 #include <asm/irq_remapping.h>
55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
56 #define __ex_clear(x, reg) \
57 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
59 MODULE_AUTHOR("Qumranet");
60 MODULE_LICENSE("GPL");
62 static const struct x86_cpu_id vmx_cpu_id
[] = {
63 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
66 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
68 static bool __read_mostly enable_vpid
= 1;
69 module_param_named(vpid
, enable_vpid
, bool, 0444);
71 static bool __read_mostly flexpriority_enabled
= 1;
72 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
74 static bool __read_mostly enable_ept
= 1;
75 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
77 static bool __read_mostly enable_unrestricted_guest
= 1;
78 module_param_named(unrestricted_guest
,
79 enable_unrestricted_guest
, bool, S_IRUGO
);
81 static bool __read_mostly enable_ept_ad_bits
= 1;
82 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
84 static bool __read_mostly emulate_invalid_guest_state
= true;
85 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
87 static bool __read_mostly vmm_exclusive
= 1;
88 module_param(vmm_exclusive
, bool, S_IRUGO
);
90 static bool __read_mostly fasteoi
= 1;
91 module_param(fasteoi
, bool, S_IRUGO
);
93 static bool __read_mostly enable_apicv
= 1;
94 module_param(enable_apicv
, bool, S_IRUGO
);
96 static bool __read_mostly enable_shadow_vmcs
= 1;
97 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
99 * If nested=1, nested virtualization is supported, i.e., guests may use
100 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
101 * use VMX instructions.
103 static bool __read_mostly nested
= 0;
104 module_param(nested
, bool, S_IRUGO
);
106 static u64 __read_mostly host_xss
;
108 static bool __read_mostly enable_pml
= 1;
109 module_param_named(pml
, enable_pml
, bool, S_IRUGO
);
111 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
115 #define KVM_VM_CR0_ALWAYS_ON \
116 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
117 #define KVM_CR4_GUEST_OWNED_BITS \
118 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
119 | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
129 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
130 * ple_gap: upper bound on the amount of time between two successive
131 * executions of PAUSE in a loop. Also indicate if ple enabled.
132 * According to test, this time is usually smaller than 128 cycles.
133 * ple_window: upper bound on the amount of time a guest is allowed to execute
134 * in a PAUSE loop. Tests indicate that most spinlocks are held for
135 * less than 2^12 cycles
136 * Time is measured based on a counter that runs at the same rate as the TSC,
137 * refer SDM volume 3b section 21.6.13 & 22.1.3.
139 #define KVM_VMX_DEFAULT_PLE_GAP 128
140 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW 2
142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX \
144 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
146 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
147 module_param(ple_gap
, int, S_IRUGO
);
149 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
150 module_param(ple_window
, int, S_IRUGO
);
152 /* Default doubles per-vcpu window every exit. */
153 static int ple_window_grow
= KVM_VMX_DEFAULT_PLE_WINDOW_GROW
;
154 module_param(ple_window_grow
, int, S_IRUGO
);
156 /* Default resets per-vcpu window every exit to ple_window. */
157 static int ple_window_shrink
= KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK
;
158 module_param(ple_window_shrink
, int, S_IRUGO
);
160 /* Default is to compute the maximum so we can never overflow. */
161 static int ple_window_actual_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
162 static int ple_window_max
= KVM_VMX_DEFAULT_PLE_WINDOW_MAX
;
163 module_param(ple_window_max
, int, S_IRUGO
);
165 extern const ulong vmx_return
;
167 #define NR_AUTOLOAD_MSRS 8
168 #define VMCS02_POOL_SIZE 1
177 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
178 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
179 * loaded on this CPU (so we can clear them if the CPU goes down).
185 struct list_head loaded_vmcss_on_cpu_link
;
188 struct shared_msr_entry
{
195 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
196 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
197 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
198 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
199 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
200 * More than one of these structures may exist, if L1 runs multiple L2 guests.
201 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
202 * underlying hardware which will be used to run L2.
203 * This structure is packed to ensure that its layout is identical across
204 * machines (necessary for live migration).
205 * If there are changes in this struct, VMCS12_REVISION must be changed.
207 typedef u64 natural_width
;
208 struct __packed vmcs12
{
209 /* According to the Intel spec, a VMCS region must start with the
210 * following two fields. Then follow implementation-specific data.
215 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
216 u32 padding
[7]; /* room for future expansion */
221 u64 vm_exit_msr_store_addr
;
222 u64 vm_exit_msr_load_addr
;
223 u64 vm_entry_msr_load_addr
;
225 u64 virtual_apic_page_addr
;
226 u64 apic_access_addr
;
227 u64 posted_intr_desc_addr
;
229 u64 eoi_exit_bitmap0
;
230 u64 eoi_exit_bitmap1
;
231 u64 eoi_exit_bitmap2
;
232 u64 eoi_exit_bitmap3
;
234 u64 guest_physical_address
;
235 u64 vmcs_link_pointer
;
236 u64 guest_ia32_debugctl
;
239 u64 guest_ia32_perf_global_ctrl
;
247 u64 host_ia32_perf_global_ctrl
;
248 u64 padding64
[8]; /* room for future expansion */
250 * To allow migration of L1 (complete with its L2 guests) between
251 * machines of different natural widths (32 or 64 bit), we cannot have
252 * unsigned long fields with no explict size. We use u64 (aliased
253 * natural_width) instead. Luckily, x86 is little-endian.
255 natural_width cr0_guest_host_mask
;
256 natural_width cr4_guest_host_mask
;
257 natural_width cr0_read_shadow
;
258 natural_width cr4_read_shadow
;
259 natural_width cr3_target_value0
;
260 natural_width cr3_target_value1
;
261 natural_width cr3_target_value2
;
262 natural_width cr3_target_value3
;
263 natural_width exit_qualification
;
264 natural_width guest_linear_address
;
265 natural_width guest_cr0
;
266 natural_width guest_cr3
;
267 natural_width guest_cr4
;
268 natural_width guest_es_base
;
269 natural_width guest_cs_base
;
270 natural_width guest_ss_base
;
271 natural_width guest_ds_base
;
272 natural_width guest_fs_base
;
273 natural_width guest_gs_base
;
274 natural_width guest_ldtr_base
;
275 natural_width guest_tr_base
;
276 natural_width guest_gdtr_base
;
277 natural_width guest_idtr_base
;
278 natural_width guest_dr7
;
279 natural_width guest_rsp
;
280 natural_width guest_rip
;
281 natural_width guest_rflags
;
282 natural_width guest_pending_dbg_exceptions
;
283 natural_width guest_sysenter_esp
;
284 natural_width guest_sysenter_eip
;
285 natural_width host_cr0
;
286 natural_width host_cr3
;
287 natural_width host_cr4
;
288 natural_width host_fs_base
;
289 natural_width host_gs_base
;
290 natural_width host_tr_base
;
291 natural_width host_gdtr_base
;
292 natural_width host_idtr_base
;
293 natural_width host_ia32_sysenter_esp
;
294 natural_width host_ia32_sysenter_eip
;
295 natural_width host_rsp
;
296 natural_width host_rip
;
297 natural_width paddingl
[8]; /* room for future expansion */
298 u32 pin_based_vm_exec_control
;
299 u32 cpu_based_vm_exec_control
;
300 u32 exception_bitmap
;
301 u32 page_fault_error_code_mask
;
302 u32 page_fault_error_code_match
;
303 u32 cr3_target_count
;
304 u32 vm_exit_controls
;
305 u32 vm_exit_msr_store_count
;
306 u32 vm_exit_msr_load_count
;
307 u32 vm_entry_controls
;
308 u32 vm_entry_msr_load_count
;
309 u32 vm_entry_intr_info_field
;
310 u32 vm_entry_exception_error_code
;
311 u32 vm_entry_instruction_len
;
313 u32 secondary_vm_exec_control
;
314 u32 vm_instruction_error
;
316 u32 vm_exit_intr_info
;
317 u32 vm_exit_intr_error_code
;
318 u32 idt_vectoring_info_field
;
319 u32 idt_vectoring_error_code
;
320 u32 vm_exit_instruction_len
;
321 u32 vmx_instruction_info
;
328 u32 guest_ldtr_limit
;
330 u32 guest_gdtr_limit
;
331 u32 guest_idtr_limit
;
332 u32 guest_es_ar_bytes
;
333 u32 guest_cs_ar_bytes
;
334 u32 guest_ss_ar_bytes
;
335 u32 guest_ds_ar_bytes
;
336 u32 guest_fs_ar_bytes
;
337 u32 guest_gs_ar_bytes
;
338 u32 guest_ldtr_ar_bytes
;
339 u32 guest_tr_ar_bytes
;
340 u32 guest_interruptibility_info
;
341 u32 guest_activity_state
;
342 u32 guest_sysenter_cs
;
343 u32 host_ia32_sysenter_cs
;
344 u32 vmx_preemption_timer_value
;
345 u32 padding32
[7]; /* room for future expansion */
346 u16 virtual_processor_id
;
348 u16 guest_es_selector
;
349 u16 guest_cs_selector
;
350 u16 guest_ss_selector
;
351 u16 guest_ds_selector
;
352 u16 guest_fs_selector
;
353 u16 guest_gs_selector
;
354 u16 guest_ldtr_selector
;
355 u16 guest_tr_selector
;
356 u16 guest_intr_status
;
357 u16 host_es_selector
;
358 u16 host_cs_selector
;
359 u16 host_ss_selector
;
360 u16 host_ds_selector
;
361 u16 host_fs_selector
;
362 u16 host_gs_selector
;
363 u16 host_tr_selector
;
367 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
368 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
369 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
371 #define VMCS12_REVISION 0x11e57ed0
374 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
375 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
376 * current implementation, 4K are reserved to avoid future complications.
378 #define VMCS12_SIZE 0x1000
380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
382 struct list_head list
;
384 struct loaded_vmcs vmcs02
;
388 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
389 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
392 /* Has the level1 guest done vmxon? */
396 /* The guest-physical address of the current VMCS L1 keeps for L2 */
398 /* The host-usable pointer to the above */
399 struct page
*current_vmcs12_page
;
400 struct vmcs12
*current_vmcs12
;
401 struct vmcs
*current_shadow_vmcs
;
403 * Indicates if the shadow vmcs must be updated with the
404 * data hold by vmcs12
406 bool sync_shadow_vmcs
;
408 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
409 struct list_head vmcs02_pool
;
411 u64 vmcs01_tsc_offset
;
412 /* L2 must run next, and mustn't decide to exit to L1. */
413 bool nested_run_pending
;
415 * Guest pages referred to in vmcs02 with host-physical pointers, so
416 * we must keep them pinned while L2 runs.
418 struct page
*apic_access_page
;
419 struct page
*virtual_apic_page
;
420 struct page
*pi_desc_page
;
421 struct pi_desc
*pi_desc
;
424 u64 msr_ia32_feature_control
;
426 struct hrtimer preemption_timer
;
427 bool preemption_timer_expired
;
429 /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
435 u32 nested_vmx_procbased_ctls_low
;
436 u32 nested_vmx_procbased_ctls_high
;
437 u32 nested_vmx_true_procbased_ctls_low
;
438 u32 nested_vmx_secondary_ctls_low
;
439 u32 nested_vmx_secondary_ctls_high
;
440 u32 nested_vmx_pinbased_ctls_low
;
441 u32 nested_vmx_pinbased_ctls_high
;
442 u32 nested_vmx_exit_ctls_low
;
443 u32 nested_vmx_exit_ctls_high
;
444 u32 nested_vmx_true_exit_ctls_low
;
445 u32 nested_vmx_entry_ctls_low
;
446 u32 nested_vmx_entry_ctls_high
;
447 u32 nested_vmx_true_entry_ctls_low
;
448 u32 nested_vmx_misc_low
;
449 u32 nested_vmx_misc_high
;
450 u32 nested_vmx_ept_caps
;
451 u32 nested_vmx_vpid_caps
;
454 #define POSTED_INTR_ON 0
455 #define POSTED_INTR_SN 1
457 /* Posted-Interrupt Descriptor */
459 u32 pir
[8]; /* Posted interrupt requested */
462 /* bit 256 - Outstanding Notification */
464 /* bit 257 - Suppress Notification */
466 /* bit 271:258 - Reserved */
468 /* bit 279:272 - Notification Vector */
470 /* bit 287:280 - Reserved */
472 /* bit 319:288 - Notification Destination */
480 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
482 return test_and_set_bit(POSTED_INTR_ON
,
483 (unsigned long *)&pi_desc
->control
);
486 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
488 return test_and_clear_bit(POSTED_INTR_ON
,
489 (unsigned long *)&pi_desc
->control
);
492 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
494 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
497 static inline void pi_clear_sn(struct pi_desc
*pi_desc
)
499 return clear_bit(POSTED_INTR_SN
,
500 (unsigned long *)&pi_desc
->control
);
503 static inline void pi_set_sn(struct pi_desc
*pi_desc
)
505 return set_bit(POSTED_INTR_SN
,
506 (unsigned long *)&pi_desc
->control
);
509 static inline int pi_test_on(struct pi_desc
*pi_desc
)
511 return test_bit(POSTED_INTR_ON
,
512 (unsigned long *)&pi_desc
->control
);
515 static inline int pi_test_sn(struct pi_desc
*pi_desc
)
517 return test_bit(POSTED_INTR_SN
,
518 (unsigned long *)&pi_desc
->control
);
522 struct kvm_vcpu vcpu
;
523 unsigned long host_rsp
;
525 bool nmi_known_unmasked
;
527 u32 idt_vectoring_info
;
529 struct shared_msr_entry
*guest_msrs
;
532 unsigned long host_idt_base
;
534 u64 msr_host_kernel_gs_base
;
535 u64 msr_guest_kernel_gs_base
;
537 u32 vm_entry_controls_shadow
;
538 u32 vm_exit_controls_shadow
;
540 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
541 * non-nested (L1) guest, it always points to vmcs01. For a nested
542 * guest (L2), it points to a different VMCS.
544 struct loaded_vmcs vmcs01
;
545 struct loaded_vmcs
*loaded_vmcs
;
546 bool __launched
; /* temporary, used in vmx_vcpu_run */
547 struct msr_autoload
{
549 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
550 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
554 u16 fs_sel
, gs_sel
, ldt_sel
;
558 int gs_ldt_reload_needed
;
559 int fs_reload_needed
;
560 u64 msr_host_bndcfgs
;
561 unsigned long vmcs_host_cr4
; /* May not match real cr4 */
566 struct kvm_segment segs
[8];
569 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
570 struct kvm_save_segment
{
578 bool emulation_required
;
580 /* Support for vnmi-less CPUs */
581 int soft_vnmi_blocked
;
583 s64 vnmi_blocked_time
;
586 /* Posted interrupt descriptor */
587 struct pi_desc pi_desc
;
589 /* Support for a guest hypervisor (nested VMX) */
590 struct nested_vmx nested
;
592 /* Dynamic PLE window. */
594 bool ple_window_dirty
;
596 /* Support for PML */
597 #define PML_ENTITY_NUM 512
601 enum segment_cache_field
{
610 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
612 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
615 static struct pi_desc
*vcpu_to_pi_desc(struct kvm_vcpu
*vcpu
)
617 return &(to_vmx(vcpu
)->pi_desc
);
620 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
621 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
622 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
623 [number##_HIGH] = VMCS12_OFFSET(name)+4
626 static unsigned long shadow_read_only_fields
[] = {
628 * We do NOT shadow fields that are modified when L0
629 * traps and emulates any vmx instruction (e.g. VMPTRLD,
630 * VMXON...) executed by L1.
631 * For example, VM_INSTRUCTION_ERROR is read
632 * by L1 if a vmx instruction fails (part of the error path).
633 * Note the code assumes this logic. If for some reason
634 * we start shadowing these fields then we need to
635 * force a shadow sync when L0 emulates vmx instructions
636 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
637 * by nested_vmx_failValid)
641 VM_EXIT_INSTRUCTION_LEN
,
642 IDT_VECTORING_INFO_FIELD
,
643 IDT_VECTORING_ERROR_CODE
,
644 VM_EXIT_INTR_ERROR_CODE
,
646 GUEST_LINEAR_ADDRESS
,
647 GUEST_PHYSICAL_ADDRESS
649 static int max_shadow_read_only_fields
=
650 ARRAY_SIZE(shadow_read_only_fields
);
652 static unsigned long shadow_read_write_fields
[] = {
659 GUEST_INTERRUPTIBILITY_INFO
,
672 CPU_BASED_VM_EXEC_CONTROL
,
673 VM_ENTRY_EXCEPTION_ERROR_CODE
,
674 VM_ENTRY_INTR_INFO_FIELD
,
675 VM_ENTRY_INSTRUCTION_LEN
,
676 VM_ENTRY_EXCEPTION_ERROR_CODE
,
682 static int max_shadow_read_write_fields
=
683 ARRAY_SIZE(shadow_read_write_fields
);
685 static const unsigned short vmcs_field_to_offset_table
[] = {
686 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
687 FIELD(POSTED_INTR_NV
, posted_intr_nv
),
688 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
689 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
690 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
691 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
692 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
693 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
694 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
695 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
696 FIELD(GUEST_INTR_STATUS
, guest_intr_status
),
697 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
698 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
699 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
700 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
701 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
702 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
703 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
704 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
705 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
706 FIELD64(MSR_BITMAP
, msr_bitmap
),
707 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
708 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
709 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
710 FIELD64(TSC_OFFSET
, tsc_offset
),
711 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
712 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
713 FIELD64(POSTED_INTR_DESC_ADDR
, posted_intr_desc_addr
),
714 FIELD64(EPT_POINTER
, ept_pointer
),
715 FIELD64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap0
),
716 FIELD64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap1
),
717 FIELD64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap2
),
718 FIELD64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap3
),
719 FIELD64(XSS_EXIT_BITMAP
, xss_exit_bitmap
),
720 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
721 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
722 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
723 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
724 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
725 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
726 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
727 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
728 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
729 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
730 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
731 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
732 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
733 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
734 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
735 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
736 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
737 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
738 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
739 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
740 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
741 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
742 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
743 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
744 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
745 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
746 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
747 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
748 FIELD(TPR_THRESHOLD
, tpr_threshold
),
749 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
750 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
751 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
752 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
753 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
754 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
755 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
756 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
757 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
758 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
759 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
760 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
761 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
762 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
763 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
764 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
765 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
766 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
767 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
768 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
769 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
770 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
771 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
772 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
773 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
774 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
775 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
776 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
777 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
778 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
779 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
780 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
781 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
782 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
783 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
784 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
785 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
786 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
787 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
788 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
789 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
790 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
791 FIELD(GUEST_CR0
, guest_cr0
),
792 FIELD(GUEST_CR3
, guest_cr3
),
793 FIELD(GUEST_CR4
, guest_cr4
),
794 FIELD(GUEST_ES_BASE
, guest_es_base
),
795 FIELD(GUEST_CS_BASE
, guest_cs_base
),
796 FIELD(GUEST_SS_BASE
, guest_ss_base
),
797 FIELD(GUEST_DS_BASE
, guest_ds_base
),
798 FIELD(GUEST_FS_BASE
, guest_fs_base
),
799 FIELD(GUEST_GS_BASE
, guest_gs_base
),
800 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
801 FIELD(GUEST_TR_BASE
, guest_tr_base
),
802 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
803 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
804 FIELD(GUEST_DR7
, guest_dr7
),
805 FIELD(GUEST_RSP
, guest_rsp
),
806 FIELD(GUEST_RIP
, guest_rip
),
807 FIELD(GUEST_RFLAGS
, guest_rflags
),
808 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
809 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
810 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
811 FIELD(HOST_CR0
, host_cr0
),
812 FIELD(HOST_CR3
, host_cr3
),
813 FIELD(HOST_CR4
, host_cr4
),
814 FIELD(HOST_FS_BASE
, host_fs_base
),
815 FIELD(HOST_GS_BASE
, host_gs_base
),
816 FIELD(HOST_TR_BASE
, host_tr_base
),
817 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
818 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
819 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
820 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
821 FIELD(HOST_RSP
, host_rsp
),
822 FIELD(HOST_RIP
, host_rip
),
825 static inline short vmcs_field_to_offset(unsigned long field
)
827 BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table
) > SHRT_MAX
);
829 if (field
>= ARRAY_SIZE(vmcs_field_to_offset_table
) ||
830 vmcs_field_to_offset_table
[field
] == 0)
833 return vmcs_field_to_offset_table
[field
];
836 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
838 return to_vmx(vcpu
)->nested
.current_vmcs12
;
841 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
843 struct page
*page
= kvm_vcpu_gfn_to_page(vcpu
, addr
>> PAGE_SHIFT
);
844 if (is_error_page(page
))
850 static void nested_release_page(struct page
*page
)
852 kvm_release_page_dirty(page
);
855 static void nested_release_page_clean(struct page
*page
)
857 kvm_release_page_clean(page
);
860 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
861 static u64
construct_eptp(unsigned long root_hpa
);
862 static void kvm_cpu_vmxon(u64 addr
);
863 static void kvm_cpu_vmxoff(void);
864 static bool vmx_mpx_supported(void);
865 static bool vmx_xsaves_supported(void);
866 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
867 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
868 struct kvm_segment
*var
, int seg
);
869 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
870 struct kvm_segment
*var
, int seg
);
871 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
872 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
873 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
874 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
875 static int alloc_identity_pagetable(struct kvm
*kvm
);
877 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
878 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
880 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
881 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
883 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
884 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
887 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
888 * can find which vCPU should be waken up.
890 static DEFINE_PER_CPU(struct list_head
, blocked_vcpu_on_cpu
);
891 static DEFINE_PER_CPU(spinlock_t
, blocked_vcpu_on_cpu_lock
);
893 static unsigned long *vmx_io_bitmap_a
;
894 static unsigned long *vmx_io_bitmap_b
;
895 static unsigned long *vmx_msr_bitmap_legacy
;
896 static unsigned long *vmx_msr_bitmap_longmode
;
897 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
898 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
899 static unsigned long *vmx_msr_bitmap_nested
;
900 static unsigned long *vmx_vmread_bitmap
;
901 static unsigned long *vmx_vmwrite_bitmap
;
903 static bool cpu_has_load_ia32_efer
;
904 static bool cpu_has_load_perf_global_ctrl
;
906 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
907 static DEFINE_SPINLOCK(vmx_vpid_lock
);
909 static struct vmcs_config
{
913 u32 pin_based_exec_ctrl
;
914 u32 cpu_based_exec_ctrl
;
915 u32 cpu_based_2nd_exec_ctrl
;
920 static struct vmx_capability
{
925 #define VMX_SEGMENT_FIELD(seg) \
926 [VCPU_SREG_##seg] = { \
927 .selector = GUEST_##seg##_SELECTOR, \
928 .base = GUEST_##seg##_BASE, \
929 .limit = GUEST_##seg##_LIMIT, \
930 .ar_bytes = GUEST_##seg##_AR_BYTES, \
933 static const struct kvm_vmx_segment_field
{
938 } kvm_vmx_segment_fields
[] = {
939 VMX_SEGMENT_FIELD(CS
),
940 VMX_SEGMENT_FIELD(DS
),
941 VMX_SEGMENT_FIELD(ES
),
942 VMX_SEGMENT_FIELD(FS
),
943 VMX_SEGMENT_FIELD(GS
),
944 VMX_SEGMENT_FIELD(SS
),
945 VMX_SEGMENT_FIELD(TR
),
946 VMX_SEGMENT_FIELD(LDTR
),
949 static u64 host_efer
;
951 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
954 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
955 * away by decrementing the array size.
957 static const u32 vmx_msr_index
[] = {
959 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
961 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
964 static inline bool is_exception_n(u32 intr_info
, u8 vector
)
966 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
967 INTR_INFO_VALID_MASK
)) ==
968 (INTR_TYPE_HARD_EXCEPTION
| vector
| INTR_INFO_VALID_MASK
);
971 static inline bool is_debug(u32 intr_info
)
973 return is_exception_n(intr_info
, DB_VECTOR
);
976 static inline bool is_breakpoint(u32 intr_info
)
978 return is_exception_n(intr_info
, BP_VECTOR
);
981 static inline bool is_page_fault(u32 intr_info
)
983 return is_exception_n(intr_info
, PF_VECTOR
);
986 static inline bool is_no_device(u32 intr_info
)
988 return is_exception_n(intr_info
, NM_VECTOR
);
991 static inline bool is_invalid_opcode(u32 intr_info
)
993 return is_exception_n(intr_info
, UD_VECTOR
);
996 static inline bool is_external_interrupt(u32 intr_info
)
998 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
999 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
1002 static inline bool is_machine_check(u32 intr_info
)
1004 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
1005 INTR_INFO_VALID_MASK
)) ==
1006 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
1009 static inline bool cpu_has_vmx_msr_bitmap(void)
1011 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
1014 static inline bool cpu_has_vmx_tpr_shadow(void)
1016 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
1019 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu
*vcpu
)
1021 return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu
);
1024 static inline bool cpu_has_secondary_exec_ctrls(void)
1026 return vmcs_config
.cpu_based_exec_ctrl
&
1027 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
1030 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1032 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1033 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
1036 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1038 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1039 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
1042 static inline bool cpu_has_vmx_apic_register_virt(void)
1044 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1045 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
1048 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1050 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1051 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
1054 static inline bool cpu_has_vmx_posted_intr(void)
1056 return IS_ENABLED(CONFIG_X86_LOCAL_APIC
) &&
1057 vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
1060 static inline bool cpu_has_vmx_apicv(void)
1062 return cpu_has_vmx_apic_register_virt() &&
1063 cpu_has_vmx_virtual_intr_delivery() &&
1064 cpu_has_vmx_posted_intr();
1067 static inline bool cpu_has_vmx_flexpriority(void)
1069 return cpu_has_vmx_tpr_shadow() &&
1070 cpu_has_vmx_virtualize_apic_accesses();
1073 static inline bool cpu_has_vmx_ept_execute_only(void)
1075 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
1078 static inline bool cpu_has_vmx_ept_2m_page(void)
1080 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
1083 static inline bool cpu_has_vmx_ept_1g_page(void)
1085 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
1088 static inline bool cpu_has_vmx_ept_4levels(void)
1090 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
1093 static inline bool cpu_has_vmx_ept_ad_bits(void)
1095 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
1098 static inline bool cpu_has_vmx_invept_context(void)
1100 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
1103 static inline bool cpu_has_vmx_invept_global(void)
1105 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
1108 static inline bool cpu_has_vmx_invvpid_single(void)
1110 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
1113 static inline bool cpu_has_vmx_invvpid_global(void)
1115 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
1118 static inline bool cpu_has_vmx_ept(void)
1120 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1121 SECONDARY_EXEC_ENABLE_EPT
;
1124 static inline bool cpu_has_vmx_unrestricted_guest(void)
1126 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1127 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
1130 static inline bool cpu_has_vmx_ple(void)
1132 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1133 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
1136 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu
*vcpu
)
1138 return flexpriority_enabled
&& lapic_in_kernel(vcpu
);
1141 static inline bool cpu_has_vmx_vpid(void)
1143 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1144 SECONDARY_EXEC_ENABLE_VPID
;
1147 static inline bool cpu_has_vmx_rdtscp(void)
1149 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1150 SECONDARY_EXEC_RDTSCP
;
1153 static inline bool cpu_has_vmx_invpcid(void)
1155 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1156 SECONDARY_EXEC_ENABLE_INVPCID
;
1159 static inline bool cpu_has_virtual_nmis(void)
1161 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1164 static inline bool cpu_has_vmx_wbinvd_exit(void)
1166 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1167 SECONDARY_EXEC_WBINVD_EXITING
;
1170 static inline bool cpu_has_vmx_shadow_vmcs(void)
1173 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1174 /* check if the cpu supports writing r/o exit information fields */
1175 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1178 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1179 SECONDARY_EXEC_SHADOW_VMCS
;
1182 static inline bool cpu_has_vmx_pml(void)
1184 return vmcs_config
.cpu_based_2nd_exec_ctrl
& SECONDARY_EXEC_ENABLE_PML
;
1187 static inline bool cpu_has_vmx_tsc_scaling(void)
1189 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1190 SECONDARY_EXEC_TSC_SCALING
;
1193 static inline bool report_flexpriority(void)
1195 return flexpriority_enabled
;
1198 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1200 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1203 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1205 return (vmcs12
->cpu_based_vm_exec_control
&
1206 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1207 (vmcs12
->secondary_vm_exec_control
& bit
);
1210 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1212 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1215 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1217 return vmcs12
->pin_based_vm_exec_control
&
1218 PIN_BASED_VMX_PREEMPTION_TIMER
;
1221 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1223 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1226 static inline bool nested_cpu_has_xsaves(struct vmcs12
*vmcs12
)
1228 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
) &&
1229 vmx_xsaves_supported();
1232 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12
*vmcs12
)
1234 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
);
1237 static inline bool nested_cpu_has_vpid(struct vmcs12
*vmcs12
)
1239 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_VPID
);
1242 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12
*vmcs12
)
1244 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_APIC_REGISTER_VIRT
);
1247 static inline bool nested_cpu_has_vid(struct vmcs12
*vmcs12
)
1249 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
1252 static inline bool nested_cpu_has_posted_intr(struct vmcs12
*vmcs12
)
1254 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_POSTED_INTR
;
1257 static inline bool is_exception(u32 intr_info
)
1259 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1260 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1263 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1265 unsigned long exit_qualification
);
1266 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1267 struct vmcs12
*vmcs12
,
1268 u32 reason
, unsigned long qualification
);
1270 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1274 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1275 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1280 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1286 } operand
= { vpid
, 0, gva
};
1288 asm volatile (__ex(ASM_VMX_INVVPID
)
1289 /* CF==1 or ZF==1 --> rc = -1 */
1290 "; ja 1f ; ud2 ; 1:"
1291 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1294 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1298 } operand
= {eptp
, gpa
};
1300 asm volatile (__ex(ASM_VMX_INVEPT
)
1301 /* CF==1 or ZF==1 --> rc = -1 */
1302 "; ja 1f ; ud2 ; 1:\n"
1303 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1306 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1310 i
= __find_msr_index(vmx
, msr
);
1312 return &vmx
->guest_msrs
[i
];
1316 static void vmcs_clear(struct vmcs
*vmcs
)
1318 u64 phys_addr
= __pa(vmcs
);
1321 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1322 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1325 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1329 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1331 vmcs_clear(loaded_vmcs
->vmcs
);
1332 loaded_vmcs
->cpu
= -1;
1333 loaded_vmcs
->launched
= 0;
1336 static void vmcs_load(struct vmcs
*vmcs
)
1338 u64 phys_addr
= __pa(vmcs
);
1341 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1342 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1345 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1349 #ifdef CONFIG_KEXEC_CORE
1351 * This bitmap is used to indicate whether the vmclear
1352 * operation is enabled on all cpus. All disabled by
1355 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1357 static inline void crash_enable_local_vmclear(int cpu
)
1359 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1362 static inline void crash_disable_local_vmclear(int cpu
)
1364 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1367 static inline int crash_local_vmclear_enabled(int cpu
)
1369 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1372 static void crash_vmclear_local_loaded_vmcss(void)
1374 int cpu
= raw_smp_processor_id();
1375 struct loaded_vmcs
*v
;
1377 if (!crash_local_vmclear_enabled(cpu
))
1380 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1381 loaded_vmcss_on_cpu_link
)
1382 vmcs_clear(v
->vmcs
);
1385 static inline void crash_enable_local_vmclear(int cpu
) { }
1386 static inline void crash_disable_local_vmclear(int cpu
) { }
1387 #endif /* CONFIG_KEXEC_CORE */
1389 static void __loaded_vmcs_clear(void *arg
)
1391 struct loaded_vmcs
*loaded_vmcs
= arg
;
1392 int cpu
= raw_smp_processor_id();
1394 if (loaded_vmcs
->cpu
!= cpu
)
1395 return; /* vcpu migration can race with cpu offline */
1396 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1397 per_cpu(current_vmcs
, cpu
) = NULL
;
1398 crash_disable_local_vmclear(cpu
);
1399 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1402 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1403 * is before setting loaded_vmcs->vcpu to -1 which is done in
1404 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1405 * then adds the vmcs into percpu list before it is deleted.
1409 loaded_vmcs_init(loaded_vmcs
);
1410 crash_enable_local_vmclear(cpu
);
1413 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1415 int cpu
= loaded_vmcs
->cpu
;
1418 smp_call_function_single(cpu
,
1419 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1422 static inline void vpid_sync_vcpu_single(int vpid
)
1427 if (cpu_has_vmx_invvpid_single())
1428 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vpid
, 0);
1431 static inline void vpid_sync_vcpu_global(void)
1433 if (cpu_has_vmx_invvpid_global())
1434 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1437 static inline void vpid_sync_context(int vpid
)
1439 if (cpu_has_vmx_invvpid_single())
1440 vpid_sync_vcpu_single(vpid
);
1442 vpid_sync_vcpu_global();
1445 static inline void ept_sync_global(void)
1447 if (cpu_has_vmx_invept_global())
1448 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1451 static inline void ept_sync_context(u64 eptp
)
1454 if (cpu_has_vmx_invept_context())
1455 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1461 static __always_inline
void vmcs_check16(unsigned long field
)
1463 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1464 "16-bit accessor invalid for 64-bit field");
1465 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1466 "16-bit accessor invalid for 64-bit high field");
1467 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1468 "16-bit accessor invalid for 32-bit high field");
1469 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1470 "16-bit accessor invalid for natural width field");
1473 static __always_inline
void vmcs_check32(unsigned long field
)
1475 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1476 "32-bit accessor invalid for 16-bit field");
1477 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1478 "32-bit accessor invalid for natural width field");
1481 static __always_inline
void vmcs_check64(unsigned long field
)
1483 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1484 "64-bit accessor invalid for 16-bit field");
1485 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1486 "64-bit accessor invalid for 64-bit high field");
1487 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1488 "64-bit accessor invalid for 32-bit field");
1489 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x6000,
1490 "64-bit accessor invalid for natural width field");
1493 static __always_inline
void vmcs_checkl(unsigned long field
)
1495 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0,
1496 "Natural width accessor invalid for 16-bit field");
1497 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2000,
1498 "Natural width accessor invalid for 64-bit field");
1499 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6001) == 0x2001,
1500 "Natural width accessor invalid for 64-bit high field");
1501 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x4000,
1502 "Natural width accessor invalid for 32-bit field");
1505 static __always_inline
unsigned long __vmcs_readl(unsigned long field
)
1507 unsigned long value
;
1509 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1510 : "=a"(value
) : "d"(field
) : "cc");
1514 static __always_inline u16
vmcs_read16(unsigned long field
)
1516 vmcs_check16(field
);
1517 return __vmcs_readl(field
);
1520 static __always_inline u32
vmcs_read32(unsigned long field
)
1522 vmcs_check32(field
);
1523 return __vmcs_readl(field
);
1526 static __always_inline u64
vmcs_read64(unsigned long field
)
1528 vmcs_check64(field
);
1529 #ifdef CONFIG_X86_64
1530 return __vmcs_readl(field
);
1532 return __vmcs_readl(field
) | ((u64
)__vmcs_readl(field
+1) << 32);
1536 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1539 return __vmcs_readl(field
);
1542 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1544 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1545 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1549 static __always_inline
void __vmcs_writel(unsigned long field
, unsigned long value
)
1553 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1554 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1555 if (unlikely(error
))
1556 vmwrite_error(field
, value
);
1559 static __always_inline
void vmcs_write16(unsigned long field
, u16 value
)
1561 vmcs_check16(field
);
1562 __vmcs_writel(field
, value
);
1565 static __always_inline
void vmcs_write32(unsigned long field
, u32 value
)
1567 vmcs_check32(field
);
1568 __vmcs_writel(field
, value
);
1571 static __always_inline
void vmcs_write64(unsigned long field
, u64 value
)
1573 vmcs_check64(field
);
1574 __vmcs_writel(field
, value
);
1575 #ifndef CONFIG_X86_64
1577 __vmcs_writel(field
+1, value
>> 32);
1581 static __always_inline
void vmcs_writel(unsigned long field
, unsigned long value
)
1584 __vmcs_writel(field
, value
);
1587 static __always_inline
void vmcs_clear_bits(unsigned long field
, u32 mask
)
1589 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1590 "vmcs_clear_bits does not support 64-bit fields");
1591 __vmcs_writel(field
, __vmcs_readl(field
) & ~mask
);
1594 static __always_inline
void vmcs_set_bits(unsigned long field
, u32 mask
)
1596 BUILD_BUG_ON_MSG(__builtin_constant_p(field
) && ((field
) & 0x6000) == 0x2000,
1597 "vmcs_set_bits does not support 64-bit fields");
1598 __vmcs_writel(field
, __vmcs_readl(field
) | mask
);
1601 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1603 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1604 vmx
->vm_entry_controls_shadow
= val
;
1607 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1609 if (vmx
->vm_entry_controls_shadow
!= val
)
1610 vm_entry_controls_init(vmx
, val
);
1613 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1615 return vmx
->vm_entry_controls_shadow
;
1619 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1621 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1624 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1626 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1629 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1631 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1632 vmx
->vm_exit_controls_shadow
= val
;
1635 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1637 if (vmx
->vm_exit_controls_shadow
!= val
)
1638 vm_exit_controls_init(vmx
, val
);
1641 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1643 return vmx
->vm_exit_controls_shadow
;
1647 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1649 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1652 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1654 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1657 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1659 vmx
->segment_cache
.bitmask
= 0;
1662 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1666 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1668 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1669 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1670 vmx
->segment_cache
.bitmask
= 0;
1672 ret
= vmx
->segment_cache
.bitmask
& mask
;
1673 vmx
->segment_cache
.bitmask
|= mask
;
1677 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1679 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1681 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1682 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1686 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1688 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1690 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1691 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1695 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1697 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1699 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1700 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1704 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1706 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1708 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1709 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1713 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1717 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1718 (1u << NM_VECTOR
) | (1u << DB_VECTOR
) | (1u << AC_VECTOR
);
1719 if ((vcpu
->guest_debug
&
1720 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1721 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1722 eb
|= 1u << BP_VECTOR
;
1723 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1726 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1727 if (vcpu
->fpu_active
)
1728 eb
&= ~(1u << NM_VECTOR
);
1730 /* When we are running a nested L2 guest and L1 specified for it a
1731 * certain exception bitmap, we must trap the same exceptions and pass
1732 * them to L1. When running L2, we will only handle the exceptions
1733 * specified above if L1 did not want them.
1735 if (is_guest_mode(vcpu
))
1736 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1738 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1741 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1742 unsigned long entry
, unsigned long exit
)
1744 vm_entry_controls_clearbit(vmx
, entry
);
1745 vm_exit_controls_clearbit(vmx
, exit
);
1748 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1751 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1755 if (cpu_has_load_ia32_efer
) {
1756 clear_atomic_switch_msr_special(vmx
,
1757 VM_ENTRY_LOAD_IA32_EFER
,
1758 VM_EXIT_LOAD_IA32_EFER
);
1762 case MSR_CORE_PERF_GLOBAL_CTRL
:
1763 if (cpu_has_load_perf_global_ctrl
) {
1764 clear_atomic_switch_msr_special(vmx
,
1765 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1766 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1772 for (i
= 0; i
< m
->nr
; ++i
)
1773 if (m
->guest
[i
].index
== msr
)
1779 m
->guest
[i
] = m
->guest
[m
->nr
];
1780 m
->host
[i
] = m
->host
[m
->nr
];
1781 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1782 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1785 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1786 unsigned long entry
, unsigned long exit
,
1787 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1788 u64 guest_val
, u64 host_val
)
1790 vmcs_write64(guest_val_vmcs
, guest_val
);
1791 vmcs_write64(host_val_vmcs
, host_val
);
1792 vm_entry_controls_setbit(vmx
, entry
);
1793 vm_exit_controls_setbit(vmx
, exit
);
1796 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1797 u64 guest_val
, u64 host_val
)
1800 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1804 if (cpu_has_load_ia32_efer
) {
1805 add_atomic_switch_msr_special(vmx
,
1806 VM_ENTRY_LOAD_IA32_EFER
,
1807 VM_EXIT_LOAD_IA32_EFER
,
1810 guest_val
, host_val
);
1814 case MSR_CORE_PERF_GLOBAL_CTRL
:
1815 if (cpu_has_load_perf_global_ctrl
) {
1816 add_atomic_switch_msr_special(vmx
,
1817 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1818 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1819 GUEST_IA32_PERF_GLOBAL_CTRL
,
1820 HOST_IA32_PERF_GLOBAL_CTRL
,
1821 guest_val
, host_val
);
1827 for (i
= 0; i
< m
->nr
; ++i
)
1828 if (m
->guest
[i
].index
== msr
)
1831 if (i
== NR_AUTOLOAD_MSRS
) {
1832 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1833 "Can't add msr %x\n", msr
);
1835 } else if (i
== m
->nr
) {
1837 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1838 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1841 m
->guest
[i
].index
= msr
;
1842 m
->guest
[i
].value
= guest_val
;
1843 m
->host
[i
].index
= msr
;
1844 m
->host
[i
].value
= host_val
;
1847 static void reload_tss(void)
1850 * VT restores TR but not its size. Useless.
1852 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1853 struct desc_struct
*descs
;
1855 descs
= (void *)gdt
->address
;
1856 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1860 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1865 guest_efer
= vmx
->vcpu
.arch
.efer
;
1868 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1871 ignore_bits
= EFER_NX
| EFER_SCE
;
1872 #ifdef CONFIG_X86_64
1873 ignore_bits
|= EFER_LMA
| EFER_LME
;
1874 /* SCE is meaningful only in long mode on Intel */
1875 if (guest_efer
& EFER_LMA
)
1876 ignore_bits
&= ~(u64
)EFER_SCE
;
1878 guest_efer
&= ~ignore_bits
;
1879 guest_efer
|= host_efer
& ignore_bits
;
1880 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1881 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1883 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1886 * On EPT, we can't emulate NX, so we must switch EFER atomically.
1887 * On CPUs that support "load IA32_EFER", always switch EFER
1888 * atomically, since it's faster than switching it manually.
1890 if (cpu_has_load_ia32_efer
||
1891 (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
))) {
1892 guest_efer
= vmx
->vcpu
.arch
.efer
;
1893 if (!(guest_efer
& EFER_LMA
))
1894 guest_efer
&= ~EFER_LME
;
1895 if (guest_efer
!= host_efer
)
1896 add_atomic_switch_msr(vmx
, MSR_EFER
,
1897 guest_efer
, host_efer
);
1904 static unsigned long segment_base(u16 selector
)
1906 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
1907 struct desc_struct
*d
;
1908 unsigned long table_base
;
1911 if (!(selector
& ~3))
1914 table_base
= gdt
->address
;
1916 if (selector
& 4) { /* from ldt */
1917 u16 ldt_selector
= kvm_read_ldt();
1919 if (!(ldt_selector
& ~3))
1922 table_base
= segment_base(ldt_selector
);
1924 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1925 v
= get_desc_base(d
);
1926 #ifdef CONFIG_X86_64
1927 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1928 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1933 static inline unsigned long kvm_read_tr_base(void)
1936 asm("str %0" : "=g"(tr
));
1937 return segment_base(tr
);
1940 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1942 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1945 if (vmx
->host_state
.loaded
)
1948 vmx
->host_state
.loaded
= 1;
1950 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1951 * allow segment selectors with cpl > 0 or ti == 1.
1953 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1954 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1955 savesegment(fs
, vmx
->host_state
.fs_sel
);
1956 if (!(vmx
->host_state
.fs_sel
& 7)) {
1957 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1958 vmx
->host_state
.fs_reload_needed
= 0;
1960 vmcs_write16(HOST_FS_SELECTOR
, 0);
1961 vmx
->host_state
.fs_reload_needed
= 1;
1963 savesegment(gs
, vmx
->host_state
.gs_sel
);
1964 if (!(vmx
->host_state
.gs_sel
& 7))
1965 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1967 vmcs_write16(HOST_GS_SELECTOR
, 0);
1968 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1971 #ifdef CONFIG_X86_64
1972 savesegment(ds
, vmx
->host_state
.ds_sel
);
1973 savesegment(es
, vmx
->host_state
.es_sel
);
1976 #ifdef CONFIG_X86_64
1977 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1978 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1980 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1981 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1984 #ifdef CONFIG_X86_64
1985 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1986 if (is_long_mode(&vmx
->vcpu
))
1987 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1989 if (boot_cpu_has(X86_FEATURE_MPX
))
1990 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1991 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1992 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1993 vmx
->guest_msrs
[i
].data
,
1994 vmx
->guest_msrs
[i
].mask
);
1997 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1999 if (!vmx
->host_state
.loaded
)
2002 ++vmx
->vcpu
.stat
.host_state_reload
;
2003 vmx
->host_state
.loaded
= 0;
2004 #ifdef CONFIG_X86_64
2005 if (is_long_mode(&vmx
->vcpu
))
2006 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
2008 if (vmx
->host_state
.gs_ldt_reload_needed
) {
2009 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
2010 #ifdef CONFIG_X86_64
2011 load_gs_index(vmx
->host_state
.gs_sel
);
2013 loadsegment(gs
, vmx
->host_state
.gs_sel
);
2016 if (vmx
->host_state
.fs_reload_needed
)
2017 loadsegment(fs
, vmx
->host_state
.fs_sel
);
2018 #ifdef CONFIG_X86_64
2019 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
2020 loadsegment(ds
, vmx
->host_state
.ds_sel
);
2021 loadsegment(es
, vmx
->host_state
.es_sel
);
2025 #ifdef CONFIG_X86_64
2026 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
2028 if (vmx
->host_state
.msr_host_bndcfgs
)
2029 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
2031 * If the FPU is not active (through the host task or
2032 * the guest vcpu), then restore the cr0.TS bit.
2034 if (!fpregs_active() && !vmx
->vcpu
.guest_fpu_loaded
)
2036 load_gdt(this_cpu_ptr(&host_gdt
));
2039 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
2042 __vmx_load_host_state(vmx
);
2046 static void vmx_vcpu_pi_load(struct kvm_vcpu
*vcpu
, int cpu
)
2048 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2049 struct pi_desc old
, new;
2052 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2053 !irq_remapping_cap(IRQ_POSTING_CAP
))
2057 old
.control
= new.control
= pi_desc
->control
;
2060 * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2061 * are two possible cases:
2062 * 1. After running 'pre_block', context switch
2063 * happened. For this case, 'sn' was set in
2064 * vmx_vcpu_put(), so we need to clear it here.
2065 * 2. After running 'pre_block', we were blocked,
2066 * and woken up by some other guy. For this case,
2067 * we don't need to do anything, 'pi_post_block'
2068 * will do everything for us. However, we cannot
2069 * check whether it is case #1 or case #2 here
2070 * (maybe, not needed), so we also clear sn here,
2071 * I think it is not a big deal.
2073 if (pi_desc
->nv
!= POSTED_INTR_WAKEUP_VECTOR
) {
2074 if (vcpu
->cpu
!= cpu
) {
2075 dest
= cpu_physical_id(cpu
);
2077 if (x2apic_enabled())
2080 new.ndst
= (dest
<< 8) & 0xFF00;
2083 /* set 'NV' to 'notification vector' */
2084 new.nv
= POSTED_INTR_VECTOR
;
2087 /* Allow posting non-urgent interrupts */
2089 } while (cmpxchg(&pi_desc
->control
, old
.control
,
2090 new.control
) != old
.control
);
2093 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2094 * vcpu mutex is already taken.
2096 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
2098 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2099 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2102 kvm_cpu_vmxon(phys_addr
);
2103 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
2104 loaded_vmcs_clear(vmx
->loaded_vmcs
);
2106 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
2107 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
2108 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
2111 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
2112 struct desc_ptr
*gdt
= this_cpu_ptr(&host_gdt
);
2113 unsigned long sysenter_esp
;
2115 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
2116 local_irq_disable();
2117 crash_disable_local_vmclear(cpu
);
2120 * Read loaded_vmcs->cpu should be before fetching
2121 * loaded_vmcs->loaded_vmcss_on_cpu_link.
2122 * See the comments in __loaded_vmcs_clear().
2126 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
2127 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
2128 crash_enable_local_vmclear(cpu
);
2132 * Linux uses per-cpu TSS and GDT, so set these when switching
2135 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
2136 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
2138 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
2139 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
2141 /* Setup TSC multiplier */
2142 if (cpu_has_vmx_tsc_scaling())
2143 vmcs_write64(TSC_MULTIPLIER
,
2144 vcpu
->arch
.tsc_scaling_ratio
);
2146 vmx
->loaded_vmcs
->cpu
= cpu
;
2149 vmx_vcpu_pi_load(vcpu
, cpu
);
2152 static void vmx_vcpu_pi_put(struct kvm_vcpu
*vcpu
)
2154 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
2156 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
2157 !irq_remapping_cap(IRQ_POSTING_CAP
))
2160 /* Set SN when the vCPU is preempted */
2161 if (vcpu
->preempted
)
2165 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
2167 vmx_vcpu_pi_put(vcpu
);
2169 __vmx_load_host_state(to_vmx(vcpu
));
2170 if (!vmm_exclusive
) {
2171 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
2177 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
2181 if (vcpu
->fpu_active
)
2183 vcpu
->fpu_active
= 1;
2184 cr0
= vmcs_readl(GUEST_CR0
);
2185 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
2186 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
2187 vmcs_writel(GUEST_CR0
, cr0
);
2188 update_exception_bitmap(vcpu
);
2189 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
2190 if (is_guest_mode(vcpu
))
2191 vcpu
->arch
.cr0_guest_owned_bits
&=
2192 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
2193 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2196 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
2199 * Return the cr0 value that a nested guest would read. This is a combination
2200 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2201 * its hypervisor (cr0_read_shadow).
2203 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
2205 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
2206 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
2208 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
2210 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
2211 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
2214 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
2216 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2217 * set this *before* calling this function.
2219 vmx_decache_cr0_guest_bits(vcpu
);
2220 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
2221 update_exception_bitmap(vcpu
);
2222 vcpu
->arch
.cr0_guest_owned_bits
= 0;
2223 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
2224 if (is_guest_mode(vcpu
)) {
2226 * L1's specified read shadow might not contain the TS bit,
2227 * so now that we turned on shadowing of this bit, we need to
2228 * set this bit of the shadow. Like in nested_vmx_run we need
2229 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2230 * up-to-date here because we just decached cr0.TS (and we'll
2231 * only update vmcs12->guest_cr0 on nested exit).
2233 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2234 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
2235 (vcpu
->arch
.cr0
& X86_CR0_TS
);
2236 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
2238 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
2241 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
2243 unsigned long rflags
, save_rflags
;
2245 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
2246 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2247 rflags
= vmcs_readl(GUEST_RFLAGS
);
2248 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2249 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
2250 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
2251 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
2253 to_vmx(vcpu
)->rflags
= rflags
;
2255 return to_vmx(vcpu
)->rflags
;
2258 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
2260 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
2261 to_vmx(vcpu
)->rflags
= rflags
;
2262 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
2263 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
2264 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
2266 vmcs_writel(GUEST_RFLAGS
, rflags
);
2269 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
)
2271 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2274 if (interruptibility
& GUEST_INTR_STATE_STI
)
2275 ret
|= KVM_X86_SHADOW_INT_STI
;
2276 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
2277 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
2282 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
2284 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
2285 u32 interruptibility
= interruptibility_old
;
2287 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
2289 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
2290 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
2291 else if (mask
& KVM_X86_SHADOW_INT_STI
)
2292 interruptibility
|= GUEST_INTR_STATE_STI
;
2294 if ((interruptibility
!= interruptibility_old
))
2295 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
2298 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
2302 rip
= kvm_rip_read(vcpu
);
2303 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
2304 kvm_rip_write(vcpu
, rip
);
2306 /* skipping an emulated instruction also counts */
2307 vmx_set_interrupt_shadow(vcpu
, 0);
2311 * KVM wants to inject page-faults which it got to the guest. This function
2312 * checks whether in a nested guest, we need to inject them to L1 or L2.
2314 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
2316 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
2318 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
2321 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
2322 vmcs_read32(VM_EXIT_INTR_INFO
),
2323 vmcs_readl(EXIT_QUALIFICATION
));
2327 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2328 bool has_error_code
, u32 error_code
,
2331 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2332 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2334 if (!reinject
&& is_guest_mode(vcpu
) &&
2335 nested_vmx_check_exception(vcpu
, nr
))
2338 if (has_error_code
) {
2339 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2340 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2343 if (vmx
->rmode
.vm86_active
) {
2345 if (kvm_exception_is_soft(nr
))
2346 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2347 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2348 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2352 if (kvm_exception_is_soft(nr
)) {
2353 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2354 vmx
->vcpu
.arch
.event_exit_inst_len
);
2355 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2357 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2359 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2362 static bool vmx_rdtscp_supported(void)
2364 return cpu_has_vmx_rdtscp();
2367 static bool vmx_invpcid_supported(void)
2369 return cpu_has_vmx_invpcid() && enable_ept
;
2373 * Swap MSR entry in host/guest MSR entry array.
2375 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2377 struct shared_msr_entry tmp
;
2379 tmp
= vmx
->guest_msrs
[to
];
2380 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2381 vmx
->guest_msrs
[from
] = tmp
;
2384 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2386 unsigned long *msr_bitmap
;
2388 if (is_guest_mode(vcpu
))
2389 msr_bitmap
= vmx_msr_bitmap_nested
;
2390 else if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
) {
2391 if (is_long_mode(vcpu
))
2392 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2394 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2396 if (is_long_mode(vcpu
))
2397 msr_bitmap
= vmx_msr_bitmap_longmode
;
2399 msr_bitmap
= vmx_msr_bitmap_legacy
;
2402 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2406 * Set up the vmcs to automatically save and restore system
2407 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2408 * mode, as fiddling with msrs is very expensive.
2410 static void setup_msrs(struct vcpu_vmx
*vmx
)
2412 int save_nmsrs
, index
;
2415 #ifdef CONFIG_X86_64
2416 if (is_long_mode(&vmx
->vcpu
)) {
2417 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2419 move_msr_up(vmx
, index
, save_nmsrs
++);
2420 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2422 move_msr_up(vmx
, index
, save_nmsrs
++);
2423 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2425 move_msr_up(vmx
, index
, save_nmsrs
++);
2426 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2427 if (index
>= 0 && guest_cpuid_has_rdtscp(&vmx
->vcpu
))
2428 move_msr_up(vmx
, index
, save_nmsrs
++);
2430 * MSR_STAR is only needed on long mode guests, and only
2431 * if efer.sce is enabled.
2433 index
= __find_msr_index(vmx
, MSR_STAR
);
2434 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2435 move_msr_up(vmx
, index
, save_nmsrs
++);
2438 index
= __find_msr_index(vmx
, MSR_EFER
);
2439 if (index
>= 0 && update_transition_efer(vmx
, index
))
2440 move_msr_up(vmx
, index
, save_nmsrs
++);
2442 vmx
->save_nmsrs
= save_nmsrs
;
2444 if (cpu_has_vmx_msr_bitmap())
2445 vmx_set_msr_bitmap(&vmx
->vcpu
);
2449 * reads and returns guest's timestamp counter "register"
2450 * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2451 * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2453 static u64
guest_read_tsc(struct kvm_vcpu
*vcpu
)
2455 u64 host_tsc
, tsc_offset
;
2458 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2459 return kvm_scale_tsc(vcpu
, host_tsc
) + tsc_offset
;
2463 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2464 * counter, even if a nested guest (L2) is currently running.
2466 static u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2470 tsc_offset
= is_guest_mode(vcpu
) ?
2471 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2472 vmcs_read64(TSC_OFFSET
);
2473 return host_tsc
+ tsc_offset
;
2476 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2478 return vmcs_read64(TSC_OFFSET
);
2482 * writes 'offset' into guest's timestamp counter offset register
2484 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2486 if (is_guest_mode(vcpu
)) {
2488 * We're here if L1 chose not to trap WRMSR to TSC. According
2489 * to the spec, this should set L1's TSC; The offset that L1
2490 * set for L2 remains unchanged, and still needs to be added
2491 * to the newly set TSC to get L2's TSC.
2493 struct vmcs12
*vmcs12
;
2494 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2495 /* recalculate vmcs02.TSC_OFFSET: */
2496 vmcs12
= get_vmcs12(vcpu
);
2497 vmcs_write64(TSC_OFFSET
, offset
+
2498 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2499 vmcs12
->tsc_offset
: 0));
2501 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2502 vmcs_read64(TSC_OFFSET
), offset
);
2503 vmcs_write64(TSC_OFFSET
, offset
);
2507 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu
*vcpu
, s64 adjustment
)
2509 u64 offset
= vmcs_read64(TSC_OFFSET
);
2511 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2512 if (is_guest_mode(vcpu
)) {
2513 /* Even when running L2, the adjustment needs to apply to L1 */
2514 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2516 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2517 offset
+ adjustment
);
2520 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2522 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2523 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2527 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2528 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2529 * all guests if the "nested" module option is off, and can also be disabled
2530 * for a single guest by disabling its VMX cpuid bit.
2532 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2534 return nested
&& guest_cpuid_has_vmx(vcpu
);
2538 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2539 * returned for the various VMX controls MSRs when nested VMX is enabled.
2540 * The same values should also be used to verify that vmcs12 control fields are
2541 * valid during nested entry from L1 to L2.
2542 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2543 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2544 * bit in the high half is on if the corresponding bit in the control field
2545 * may be on. See also vmx_control_verify().
2547 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx
*vmx
)
2550 * Note that as a general rule, the high half of the MSRs (bits in
2551 * the control fields which may be 1) should be initialized by the
2552 * intersection of the underlying hardware's MSR (i.e., features which
2553 * can be supported) and the list of features we want to expose -
2554 * because they are known to be properly supported in our code.
2555 * Also, usually, the low half of the MSRs (bits which must be 1) can
2556 * be set to 0, meaning that L1 may turn off any of these bits. The
2557 * reason is that if one of these bits is necessary, it will appear
2558 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2559 * fields of vmcs01 and vmcs02, will turn these bits off - and
2560 * nested_vmx_exit_handled() will not pass related exits to L1.
2561 * These rules have exceptions below.
2564 /* pin-based controls */
2565 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2566 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2567 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2568 vmx
->nested
.nested_vmx_pinbased_ctls_low
|=
2569 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2570 vmx
->nested
.nested_vmx_pinbased_ctls_high
&=
2571 PIN_BASED_EXT_INTR_MASK
|
2572 PIN_BASED_NMI_EXITING
|
2573 PIN_BASED_VIRTUAL_NMIS
;
2574 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2575 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2576 PIN_BASED_VMX_PREEMPTION_TIMER
;
2577 if (kvm_vcpu_apicv_active(&vmx
->vcpu
))
2578 vmx
->nested
.nested_vmx_pinbased_ctls_high
|=
2579 PIN_BASED_POSTED_INTR
;
2582 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2583 vmx
->nested
.nested_vmx_exit_ctls_low
,
2584 vmx
->nested
.nested_vmx_exit_ctls_high
);
2585 vmx
->nested
.nested_vmx_exit_ctls_low
=
2586 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2588 vmx
->nested
.nested_vmx_exit_ctls_high
&=
2589 #ifdef CONFIG_X86_64
2590 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2592 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2593 vmx
->nested
.nested_vmx_exit_ctls_high
|=
2594 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2595 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2596 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2598 if (vmx_mpx_supported())
2599 vmx
->nested
.nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2601 /* We support free control of debug control saving. */
2602 vmx
->nested
.nested_vmx_true_exit_ctls_low
=
2603 vmx
->nested
.nested_vmx_exit_ctls_low
&
2604 ~VM_EXIT_SAVE_DEBUG_CONTROLS
;
2606 /* entry controls */
2607 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2608 vmx
->nested
.nested_vmx_entry_ctls_low
,
2609 vmx
->nested
.nested_vmx_entry_ctls_high
);
2610 vmx
->nested
.nested_vmx_entry_ctls_low
=
2611 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2612 vmx
->nested
.nested_vmx_entry_ctls_high
&=
2613 #ifdef CONFIG_X86_64
2614 VM_ENTRY_IA32E_MODE
|
2616 VM_ENTRY_LOAD_IA32_PAT
;
2617 vmx
->nested
.nested_vmx_entry_ctls_high
|=
2618 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
| VM_ENTRY_LOAD_IA32_EFER
);
2619 if (vmx_mpx_supported())
2620 vmx
->nested
.nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2622 /* We support free control of debug control loading. */
2623 vmx
->nested
.nested_vmx_true_entry_ctls_low
=
2624 vmx
->nested
.nested_vmx_entry_ctls_low
&
2625 ~VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2627 /* cpu-based controls */
2628 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2629 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2630 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2631 vmx
->nested
.nested_vmx_procbased_ctls_low
=
2632 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2633 vmx
->nested
.nested_vmx_procbased_ctls_high
&=
2634 CPU_BASED_VIRTUAL_INTR_PENDING
|
2635 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2636 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2637 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2638 CPU_BASED_CR3_STORE_EXITING
|
2639 #ifdef CONFIG_X86_64
2640 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2642 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2643 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_TRAP_FLAG
|
2644 CPU_BASED_MONITOR_EXITING
| CPU_BASED_RDPMC_EXITING
|
2645 CPU_BASED_RDTSC_EXITING
| CPU_BASED_PAUSE_EXITING
|
2646 CPU_BASED_TPR_SHADOW
| CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2648 * We can allow some features even when not supported by the
2649 * hardware. For example, L1 can specify an MSR bitmap - and we
2650 * can use it to avoid exits to L1 - even when L0 runs L2
2651 * without MSR bitmaps.
2653 vmx
->nested
.nested_vmx_procbased_ctls_high
|=
2654 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2655 CPU_BASED_USE_MSR_BITMAPS
;
2657 /* We support free control of CR3 access interception. */
2658 vmx
->nested
.nested_vmx_true_procbased_ctls_low
=
2659 vmx
->nested
.nested_vmx_procbased_ctls_low
&
2660 ~(CPU_BASED_CR3_LOAD_EXITING
| CPU_BASED_CR3_STORE_EXITING
);
2662 /* secondary cpu-based controls */
2663 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2664 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2665 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2666 vmx
->nested
.nested_vmx_secondary_ctls_low
= 0;
2667 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
2668 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2669 SECONDARY_EXEC_RDTSCP
|
2670 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2671 SECONDARY_EXEC_ENABLE_VPID
|
2672 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2673 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2674 SECONDARY_EXEC_WBINVD_EXITING
|
2675 SECONDARY_EXEC_XSAVES
|
2676 SECONDARY_EXEC_PCOMMIT
;
2679 /* nested EPT: emulate EPT also to L1 */
2680 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2681 SECONDARY_EXEC_ENABLE_EPT
;
2682 vmx
->nested
.nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2683 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2685 vmx
->nested
.nested_vmx_ept_caps
&= vmx_capability
.ept
;
2687 * For nested guests, we don't do anything specific
2688 * for single context invalidation. Hence, only advertise
2689 * support for global context invalidation.
2691 vmx
->nested
.nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2693 vmx
->nested
.nested_vmx_ept_caps
= 0;
2696 vmx
->nested
.nested_vmx_vpid_caps
= VMX_VPID_INVVPID_BIT
|
2697 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
2699 vmx
->nested
.nested_vmx_vpid_caps
= 0;
2701 if (enable_unrestricted_guest
)
2702 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
2703 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
2705 /* miscellaneous data */
2706 rdmsr(MSR_IA32_VMX_MISC
,
2707 vmx
->nested
.nested_vmx_misc_low
,
2708 vmx
->nested
.nested_vmx_misc_high
);
2709 vmx
->nested
.nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2710 vmx
->nested
.nested_vmx_misc_low
|=
2711 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2712 VMX_MISC_ACTIVITY_HLT
;
2713 vmx
->nested
.nested_vmx_misc_high
= 0;
2716 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2719 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2721 return ((control
& high
) | low
) == control
;
2724 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2726 return low
| ((u64
)high
<< 32);
2729 /* Returns 0 on success, non-0 otherwise. */
2730 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2732 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2734 switch (msr_index
) {
2735 case MSR_IA32_VMX_BASIC
:
2737 * This MSR reports some information about VMX support. We
2738 * should return information about the VMX we emulate for the
2739 * guest, and the VMCS structure we give it - not about the
2740 * VMX support of the underlying hardware.
2742 *pdata
= VMCS12_REVISION
| VMX_BASIC_TRUE_CTLS
|
2743 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2744 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2746 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2747 case MSR_IA32_VMX_PINBASED_CTLS
:
2748 *pdata
= vmx_control_msr(
2749 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
2750 vmx
->nested
.nested_vmx_pinbased_ctls_high
);
2752 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2753 *pdata
= vmx_control_msr(
2754 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
2755 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2757 case MSR_IA32_VMX_PROCBASED_CTLS
:
2758 *pdata
= vmx_control_msr(
2759 vmx
->nested
.nested_vmx_procbased_ctls_low
,
2760 vmx
->nested
.nested_vmx_procbased_ctls_high
);
2762 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2763 *pdata
= vmx_control_msr(
2764 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
2765 vmx
->nested
.nested_vmx_exit_ctls_high
);
2767 case MSR_IA32_VMX_EXIT_CTLS
:
2768 *pdata
= vmx_control_msr(
2769 vmx
->nested
.nested_vmx_exit_ctls_low
,
2770 vmx
->nested
.nested_vmx_exit_ctls_high
);
2772 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2773 *pdata
= vmx_control_msr(
2774 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
2775 vmx
->nested
.nested_vmx_entry_ctls_high
);
2777 case MSR_IA32_VMX_ENTRY_CTLS
:
2778 *pdata
= vmx_control_msr(
2779 vmx
->nested
.nested_vmx_entry_ctls_low
,
2780 vmx
->nested
.nested_vmx_entry_ctls_high
);
2782 case MSR_IA32_VMX_MISC
:
2783 *pdata
= vmx_control_msr(
2784 vmx
->nested
.nested_vmx_misc_low
,
2785 vmx
->nested
.nested_vmx_misc_high
);
2788 * These MSRs specify bits which the guest must keep fixed (on or off)
2789 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2790 * We picked the standard core2 setting.
2792 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2793 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2794 case MSR_IA32_VMX_CR0_FIXED0
:
2795 *pdata
= VMXON_CR0_ALWAYSON
;
2797 case MSR_IA32_VMX_CR0_FIXED1
:
2800 case MSR_IA32_VMX_CR4_FIXED0
:
2801 *pdata
= VMXON_CR4_ALWAYSON
;
2803 case MSR_IA32_VMX_CR4_FIXED1
:
2806 case MSR_IA32_VMX_VMCS_ENUM
:
2807 *pdata
= 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2809 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2810 *pdata
= vmx_control_msr(
2811 vmx
->nested
.nested_vmx_secondary_ctls_low
,
2812 vmx
->nested
.nested_vmx_secondary_ctls_high
);
2814 case MSR_IA32_VMX_EPT_VPID_CAP
:
2815 /* Currently, no nested vpid support */
2816 *pdata
= vmx
->nested
.nested_vmx_ept_caps
|
2817 ((u64
)vmx
->nested
.nested_vmx_vpid_caps
<< 32);
2827 * Reads an msr value (of 'msr_index') into 'pdata'.
2828 * Returns 0 on success, non-0 otherwise.
2829 * Assumes vcpu_load() was already called.
2831 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2833 struct shared_msr_entry
*msr
;
2835 switch (msr_info
->index
) {
2836 #ifdef CONFIG_X86_64
2838 msr_info
->data
= vmcs_readl(GUEST_FS_BASE
);
2841 msr_info
->data
= vmcs_readl(GUEST_GS_BASE
);
2843 case MSR_KERNEL_GS_BASE
:
2844 vmx_load_host_state(to_vmx(vcpu
));
2845 msr_info
->data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2849 return kvm_get_msr_common(vcpu
, msr_info
);
2851 msr_info
->data
= guest_read_tsc(vcpu
);
2853 case MSR_IA32_SYSENTER_CS
:
2854 msr_info
->data
= vmcs_read32(GUEST_SYSENTER_CS
);
2856 case MSR_IA32_SYSENTER_EIP
:
2857 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2859 case MSR_IA32_SYSENTER_ESP
:
2860 msr_info
->data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2862 case MSR_IA32_BNDCFGS
:
2863 if (!vmx_mpx_supported())
2865 msr_info
->data
= vmcs_read64(GUEST_BNDCFGS
);
2867 case MSR_IA32_FEATURE_CONTROL
:
2868 if (!nested_vmx_allowed(vcpu
))
2870 msr_info
->data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2872 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2873 if (!nested_vmx_allowed(vcpu
))
2875 return vmx_get_vmx_msr(vcpu
, msr_info
->index
, &msr_info
->data
);
2877 if (!vmx_xsaves_supported())
2879 msr_info
->data
= vcpu
->arch
.ia32_xss
;
2882 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2884 /* Otherwise falls through */
2886 msr
= find_msr_entry(to_vmx(vcpu
), msr_info
->index
);
2888 msr_info
->data
= msr
->data
;
2891 return kvm_get_msr_common(vcpu
, msr_info
);
2897 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2900 * Writes msr value into into the appropriate "register".
2901 * Returns 0 on success, non-0 otherwise.
2902 * Assumes vcpu_load() was already called.
2904 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2906 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2907 struct shared_msr_entry
*msr
;
2909 u32 msr_index
= msr_info
->index
;
2910 u64 data
= msr_info
->data
;
2912 switch (msr_index
) {
2914 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2916 #ifdef CONFIG_X86_64
2918 vmx_segment_cache_clear(vmx
);
2919 vmcs_writel(GUEST_FS_BASE
, data
);
2922 vmx_segment_cache_clear(vmx
);
2923 vmcs_writel(GUEST_GS_BASE
, data
);
2925 case MSR_KERNEL_GS_BASE
:
2926 vmx_load_host_state(vmx
);
2927 vmx
->msr_guest_kernel_gs_base
= data
;
2930 case MSR_IA32_SYSENTER_CS
:
2931 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2933 case MSR_IA32_SYSENTER_EIP
:
2934 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2936 case MSR_IA32_SYSENTER_ESP
:
2937 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2939 case MSR_IA32_BNDCFGS
:
2940 if (!vmx_mpx_supported())
2942 vmcs_write64(GUEST_BNDCFGS
, data
);
2945 kvm_write_tsc(vcpu
, msr_info
);
2947 case MSR_IA32_CR_PAT
:
2948 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2949 if (!kvm_mtrr_valid(vcpu
, MSR_IA32_CR_PAT
, data
))
2951 vmcs_write64(GUEST_IA32_PAT
, data
);
2952 vcpu
->arch
.pat
= data
;
2955 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2957 case MSR_IA32_TSC_ADJUST
:
2958 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2960 case MSR_IA32_FEATURE_CONTROL
:
2961 if (!nested_vmx_allowed(vcpu
) ||
2962 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2963 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2965 vmx
->nested
.msr_ia32_feature_control
= data
;
2966 if (msr_info
->host_initiated
&& data
== 0)
2967 vmx_leave_nested(vcpu
);
2969 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2970 return 1; /* they are read-only */
2972 if (!vmx_xsaves_supported())
2975 * The only supported bit as of Skylake is bit 8, but
2976 * it is not supported on KVM.
2980 vcpu
->arch
.ia32_xss
= data
;
2981 if (vcpu
->arch
.ia32_xss
!= host_xss
)
2982 add_atomic_switch_msr(vmx
, MSR_IA32_XSS
,
2983 vcpu
->arch
.ia32_xss
, host_xss
);
2985 clear_atomic_switch_msr(vmx
, MSR_IA32_XSS
);
2988 if (!guest_cpuid_has_rdtscp(vcpu
) && !msr_info
->host_initiated
)
2990 /* Check reserved bit, higher 32 bits should be zero */
2991 if ((data
>> 32) != 0)
2993 /* Otherwise falls through */
2995 msr
= find_msr_entry(vmx
, msr_index
);
2997 u64 old_msr_data
= msr
->data
;
2999 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
3001 ret
= kvm_set_shared_msr(msr
->index
, msr
->data
,
3005 msr
->data
= old_msr_data
;
3009 ret
= kvm_set_msr_common(vcpu
, msr_info
);
3015 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
3017 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
3020 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
3023 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
3025 case VCPU_EXREG_PDPTR
:
3027 ept_save_pdptrs(vcpu
);
3034 static __init
int cpu_has_kvm_support(void)
3036 return cpu_has_vmx();
3039 static __init
int vmx_disabled_by_bios(void)
3043 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
3044 if (msr
& FEATURE_CONTROL_LOCKED
) {
3045 /* launched w/ TXT and VMX disabled */
3046 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3049 /* launched w/o TXT and VMX only enabled w/ TXT */
3050 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3051 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
3052 && !tboot_enabled()) {
3053 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
3054 "activate TXT before enabling KVM\n");
3057 /* launched w/o TXT and VMX disabled */
3058 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
3059 && !tboot_enabled())
3066 static void kvm_cpu_vmxon(u64 addr
)
3068 asm volatile (ASM_VMX_VMXON_RAX
3069 : : "a"(&addr
), "m"(addr
)
3073 static int hardware_enable(void)
3075 int cpu
= raw_smp_processor_id();
3076 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
3079 if (cr4_read_shadow() & X86_CR4_VMXE
)
3082 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
3083 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu
, cpu
));
3084 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
3087 * Now we can enable the vmclear operation in kdump
3088 * since the loaded_vmcss_on_cpu list on this cpu
3089 * has been initialized.
3091 * Though the cpu is not in VMX operation now, there
3092 * is no problem to enable the vmclear operation
3093 * for the loaded_vmcss_on_cpu list is empty!
3095 crash_enable_local_vmclear(cpu
);
3097 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
3099 test_bits
= FEATURE_CONTROL_LOCKED
;
3100 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
3101 if (tboot_enabled())
3102 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
3104 if ((old
& test_bits
) != test_bits
) {
3105 /* enable and lock */
3106 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
3108 cr4_set_bits(X86_CR4_VMXE
);
3110 if (vmm_exclusive
) {
3111 kvm_cpu_vmxon(phys_addr
);
3115 native_store_gdt(this_cpu_ptr(&host_gdt
));
3120 static void vmclear_local_loaded_vmcss(void)
3122 int cpu
= raw_smp_processor_id();
3123 struct loaded_vmcs
*v
, *n
;
3125 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
3126 loaded_vmcss_on_cpu_link
)
3127 __loaded_vmcs_clear(v
);
3131 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3134 static void kvm_cpu_vmxoff(void)
3136 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
3139 static void hardware_disable(void)
3141 if (vmm_exclusive
) {
3142 vmclear_local_loaded_vmcss();
3145 cr4_clear_bits(X86_CR4_VMXE
);
3148 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
3149 u32 msr
, u32
*result
)
3151 u32 vmx_msr_low
, vmx_msr_high
;
3152 u32 ctl
= ctl_min
| ctl_opt
;
3154 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3156 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
3157 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
3159 /* Ensure minimum (required) set of control bits are supported. */
3167 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
3169 u32 vmx_msr_low
, vmx_msr_high
;
3171 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
3172 return vmx_msr_high
& ctl
;
3175 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
3177 u32 vmx_msr_low
, vmx_msr_high
;
3178 u32 min
, opt
, min2
, opt2
;
3179 u32 _pin_based_exec_control
= 0;
3180 u32 _cpu_based_exec_control
= 0;
3181 u32 _cpu_based_2nd_exec_control
= 0;
3182 u32 _vmexit_control
= 0;
3183 u32 _vmentry_control
= 0;
3185 min
= CPU_BASED_HLT_EXITING
|
3186 #ifdef CONFIG_X86_64
3187 CPU_BASED_CR8_LOAD_EXITING
|
3188 CPU_BASED_CR8_STORE_EXITING
|
3190 CPU_BASED_CR3_LOAD_EXITING
|
3191 CPU_BASED_CR3_STORE_EXITING
|
3192 CPU_BASED_USE_IO_BITMAPS
|
3193 CPU_BASED_MOV_DR_EXITING
|
3194 CPU_BASED_USE_TSC_OFFSETING
|
3195 CPU_BASED_MWAIT_EXITING
|
3196 CPU_BASED_MONITOR_EXITING
|
3197 CPU_BASED_INVLPG_EXITING
|
3198 CPU_BASED_RDPMC_EXITING
;
3200 opt
= CPU_BASED_TPR_SHADOW
|
3201 CPU_BASED_USE_MSR_BITMAPS
|
3202 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
3203 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
3204 &_cpu_based_exec_control
) < 0)
3206 #ifdef CONFIG_X86_64
3207 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3208 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
3209 ~CPU_BASED_CR8_STORE_EXITING
;
3211 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
3213 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
3214 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3215 SECONDARY_EXEC_WBINVD_EXITING
|
3216 SECONDARY_EXEC_ENABLE_VPID
|
3217 SECONDARY_EXEC_ENABLE_EPT
|
3218 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
3219 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
3220 SECONDARY_EXEC_RDTSCP
|
3221 SECONDARY_EXEC_ENABLE_INVPCID
|
3222 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3223 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
3224 SECONDARY_EXEC_SHADOW_VMCS
|
3225 SECONDARY_EXEC_XSAVES
|
3226 SECONDARY_EXEC_ENABLE_PML
|
3227 SECONDARY_EXEC_PCOMMIT
|
3228 SECONDARY_EXEC_TSC_SCALING
;
3229 if (adjust_vmx_controls(min2
, opt2
,
3230 MSR_IA32_VMX_PROCBASED_CTLS2
,
3231 &_cpu_based_2nd_exec_control
) < 0)
3234 #ifndef CONFIG_X86_64
3235 if (!(_cpu_based_2nd_exec_control
&
3236 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
3237 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
3240 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
3241 _cpu_based_2nd_exec_control
&= ~(
3242 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
3243 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
3244 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
3246 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
3247 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3249 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
3250 CPU_BASED_CR3_STORE_EXITING
|
3251 CPU_BASED_INVLPG_EXITING
);
3252 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
3253 vmx_capability
.ept
, vmx_capability
.vpid
);
3256 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
3257 #ifdef CONFIG_X86_64
3258 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
3260 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
3261 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
3262 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
3263 &_vmexit_control
) < 0)
3266 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
3267 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
3268 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
3269 &_pin_based_exec_control
) < 0)
3272 if (!(_cpu_based_2nd_exec_control
&
3273 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
3274 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
3275 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
3277 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
3278 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
3279 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
3280 &_vmentry_control
) < 0)
3283 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
3285 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3286 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
3289 #ifdef CONFIG_X86_64
3290 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3291 if (vmx_msr_high
& (1u<<16))
3295 /* Require Write-Back (WB) memory type for VMCS accesses. */
3296 if (((vmx_msr_high
>> 18) & 15) != 6)
3299 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
3300 vmcs_conf
->order
= get_order(vmcs_config
.size
);
3301 vmcs_conf
->revision_id
= vmx_msr_low
;
3303 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
3304 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
3305 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
3306 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
3307 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
3309 cpu_has_load_ia32_efer
=
3310 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3311 VM_ENTRY_LOAD_IA32_EFER
)
3312 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3313 VM_EXIT_LOAD_IA32_EFER
);
3315 cpu_has_load_perf_global_ctrl
=
3316 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
3317 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
3318 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
3319 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
3322 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3323 * but due to arrata below it can't be used. Workaround is to use
3324 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3326 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3331 * BC86,AAY89,BD102 (model 44)
3335 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
3336 switch (boot_cpu_data
.x86_model
) {
3342 cpu_has_load_perf_global_ctrl
= false;
3343 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3344 "does not work properly. Using workaround\n");
3352 rdmsrl(MSR_IA32_XSS
, host_xss
);
3357 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
3359 int node
= cpu_to_node(cpu
);
3363 pages
= __alloc_pages_node(node
, GFP_KERNEL
, vmcs_config
.order
);
3366 vmcs
= page_address(pages
);
3367 memset(vmcs
, 0, vmcs_config
.size
);
3368 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
3372 static struct vmcs
*alloc_vmcs(void)
3374 return alloc_vmcs_cpu(raw_smp_processor_id());
3377 static void free_vmcs(struct vmcs
*vmcs
)
3379 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
3383 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3385 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
3387 if (!loaded_vmcs
->vmcs
)
3389 loaded_vmcs_clear(loaded_vmcs
);
3390 free_vmcs(loaded_vmcs
->vmcs
);
3391 loaded_vmcs
->vmcs
= NULL
;
3394 static void free_kvm_area(void)
3398 for_each_possible_cpu(cpu
) {
3399 free_vmcs(per_cpu(vmxarea
, cpu
));
3400 per_cpu(vmxarea
, cpu
) = NULL
;
3404 static void init_vmcs_shadow_fields(void)
3408 /* No checks for read only fields yet */
3410 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3411 switch (shadow_read_write_fields
[i
]) {
3413 if (!vmx_mpx_supported())
3421 shadow_read_write_fields
[j
] =
3422 shadow_read_write_fields
[i
];
3425 max_shadow_read_write_fields
= j
;
3427 /* shadowed fields guest access without vmexit */
3428 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3429 clear_bit(shadow_read_write_fields
[i
],
3430 vmx_vmwrite_bitmap
);
3431 clear_bit(shadow_read_write_fields
[i
],
3434 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3435 clear_bit(shadow_read_only_fields
[i
],
3439 static __init
int alloc_kvm_area(void)
3443 for_each_possible_cpu(cpu
) {
3446 vmcs
= alloc_vmcs_cpu(cpu
);
3452 per_cpu(vmxarea
, cpu
) = vmcs
;
3457 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3459 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3462 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3463 struct kvm_segment
*save
)
3465 if (!emulate_invalid_guest_state
) {
3467 * CS and SS RPL should be equal during guest entry according
3468 * to VMX spec, but in reality it is not always so. Since vcpu
3469 * is in the middle of the transition from real mode to
3470 * protected mode it is safe to assume that RPL 0 is a good
3473 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3474 save
->selector
&= ~SEGMENT_RPL_MASK
;
3475 save
->dpl
= save
->selector
& SEGMENT_RPL_MASK
;
3478 vmx_set_segment(vcpu
, save
, seg
);
3481 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3483 unsigned long flags
;
3484 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3487 * Update real mode segment cache. It may be not up-to-date if sement
3488 * register was written while vcpu was in a guest mode.
3490 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3491 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3492 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3493 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3494 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3495 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3497 vmx
->rmode
.vm86_active
= 0;
3499 vmx_segment_cache_clear(vmx
);
3501 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3503 flags
= vmcs_readl(GUEST_RFLAGS
);
3504 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3505 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3506 vmcs_writel(GUEST_RFLAGS
, flags
);
3508 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3509 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3511 update_exception_bitmap(vcpu
);
3513 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3514 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3515 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3516 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3517 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3518 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3521 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3523 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3524 struct kvm_segment var
= *save
;
3527 if (seg
== VCPU_SREG_CS
)
3530 if (!emulate_invalid_guest_state
) {
3531 var
.selector
= var
.base
>> 4;
3532 var
.base
= var
.base
& 0xffff0;
3542 if (save
->base
& 0xf)
3543 printk_once(KERN_WARNING
"kvm: segment base is not "
3544 "paragraph aligned when entering "
3545 "protected mode (seg=%d)", seg
);
3548 vmcs_write16(sf
->selector
, var
.selector
);
3549 vmcs_write32(sf
->base
, var
.base
);
3550 vmcs_write32(sf
->limit
, var
.limit
);
3551 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3554 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3556 unsigned long flags
;
3557 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3559 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3560 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3561 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3562 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3563 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3564 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3565 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3567 vmx
->rmode
.vm86_active
= 1;
3570 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3571 * vcpu. Warn the user that an update is overdue.
3573 if (!vcpu
->kvm
->arch
.tss_addr
)
3574 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3575 "called before entering vcpu\n");
3577 vmx_segment_cache_clear(vmx
);
3579 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3580 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3581 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3583 flags
= vmcs_readl(GUEST_RFLAGS
);
3584 vmx
->rmode
.save_rflags
= flags
;
3586 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3588 vmcs_writel(GUEST_RFLAGS
, flags
);
3589 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3590 update_exception_bitmap(vcpu
);
3592 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3593 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3594 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3595 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3596 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3597 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3599 kvm_mmu_reset_context(vcpu
);
3602 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3604 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3605 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3611 * Force kernel_gs_base reloading before EFER changes, as control
3612 * of this msr depends on is_long_mode().
3614 vmx_load_host_state(to_vmx(vcpu
));
3615 vcpu
->arch
.efer
= efer
;
3616 if (efer
& EFER_LMA
) {
3617 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3620 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3622 msr
->data
= efer
& ~EFER_LME
;
3627 #ifdef CONFIG_X86_64
3629 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3633 vmx_segment_cache_clear(to_vmx(vcpu
));
3635 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3636 if ((guest_tr_ar
& VMX_AR_TYPE_MASK
) != VMX_AR_TYPE_BUSY_64_TSS
) {
3637 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3639 vmcs_write32(GUEST_TR_AR_BYTES
,
3640 (guest_tr_ar
& ~VMX_AR_TYPE_MASK
)
3641 | VMX_AR_TYPE_BUSY_64_TSS
);
3643 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3646 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3648 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3649 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3654 static inline void __vmx_flush_tlb(struct kvm_vcpu
*vcpu
, int vpid
)
3656 vpid_sync_context(vpid
);
3658 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3660 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3664 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3666 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->vpid
);
3669 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3671 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3673 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3674 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3677 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3679 if (enable_ept
&& is_paging(vcpu
))
3680 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3681 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3684 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3686 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3688 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3689 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3692 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3694 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3696 if (!test_bit(VCPU_EXREG_PDPTR
,
3697 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3700 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3701 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3702 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3703 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3704 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3708 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3710 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3712 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3713 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3714 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3715 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3716 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3719 __set_bit(VCPU_EXREG_PDPTR
,
3720 (unsigned long *)&vcpu
->arch
.regs_avail
);
3721 __set_bit(VCPU_EXREG_PDPTR
,
3722 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3725 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3727 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3729 struct kvm_vcpu
*vcpu
)
3731 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3732 vmx_decache_cr3(vcpu
);
3733 if (!(cr0
& X86_CR0_PG
)) {
3734 /* From paging/starting to nonpaging */
3735 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3736 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3737 (CPU_BASED_CR3_LOAD_EXITING
|
3738 CPU_BASED_CR3_STORE_EXITING
));
3739 vcpu
->arch
.cr0
= cr0
;
3740 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3741 } else if (!is_paging(vcpu
)) {
3742 /* From nonpaging to paging */
3743 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3744 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3745 ~(CPU_BASED_CR3_LOAD_EXITING
|
3746 CPU_BASED_CR3_STORE_EXITING
));
3747 vcpu
->arch
.cr0
= cr0
;
3748 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3751 if (!(cr0
& X86_CR0_WP
))
3752 *hw_cr0
&= ~X86_CR0_WP
;
3755 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3757 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3758 unsigned long hw_cr0
;
3760 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3761 if (enable_unrestricted_guest
)
3762 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3764 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3766 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3769 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3773 #ifdef CONFIG_X86_64
3774 if (vcpu
->arch
.efer
& EFER_LME
) {
3775 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3777 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3783 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3785 if (!vcpu
->fpu_active
)
3786 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3788 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3789 vmcs_writel(GUEST_CR0
, hw_cr0
);
3790 vcpu
->arch
.cr0
= cr0
;
3792 /* depends on vcpu->arch.cr0 to be set to a new value */
3793 vmx
->emulation_required
= emulation_required(vcpu
);
3796 static u64
construct_eptp(unsigned long root_hpa
)
3800 /* TODO write the value reading from MSR */
3801 eptp
= VMX_EPT_DEFAULT_MT
|
3802 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3803 if (enable_ept_ad_bits
)
3804 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3805 eptp
|= (root_hpa
& PAGE_MASK
);
3810 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3812 unsigned long guest_cr3
;
3817 eptp
= construct_eptp(cr3
);
3818 vmcs_write64(EPT_POINTER
, eptp
);
3819 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3820 guest_cr3
= kvm_read_cr3(vcpu
);
3822 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3823 ept_load_pdptrs(vcpu
);
3826 vmx_flush_tlb(vcpu
);
3827 vmcs_writel(GUEST_CR3
, guest_cr3
);
3830 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3833 * Pass through host's Machine Check Enable value to hw_cr4, which
3834 * is in force while we are in guest mode. Do not let guests control
3835 * this bit, even if host CR4.MCE == 0.
3837 unsigned long hw_cr4
=
3838 (cr4_read_shadow() & X86_CR4_MCE
) |
3839 (cr4
& ~X86_CR4_MCE
) |
3840 (to_vmx(vcpu
)->rmode
.vm86_active
?
3841 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3843 if (cr4
& X86_CR4_VMXE
) {
3845 * To use VMXON (and later other VMX instructions), a guest
3846 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3847 * So basically the check on whether to allow nested VMX
3850 if (!nested_vmx_allowed(vcpu
))
3853 if (to_vmx(vcpu
)->nested
.vmxon
&&
3854 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3857 vcpu
->arch
.cr4
= cr4
;
3859 if (!is_paging(vcpu
)) {
3860 hw_cr4
&= ~X86_CR4_PAE
;
3861 hw_cr4
|= X86_CR4_PSE
;
3862 } else if (!(cr4
& X86_CR4_PAE
)) {
3863 hw_cr4
&= ~X86_CR4_PAE
;
3867 if (!enable_unrestricted_guest
&& !is_paging(vcpu
))
3869 * SMEP/SMAP is disabled if CPU is in non-paging mode in
3870 * hardware. However KVM always uses paging mode without
3871 * unrestricted guest.
3872 * To emulate this behavior, SMEP/SMAP needs to be manually
3873 * disabled when guest switches to non-paging mode.
3875 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3877 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3878 vmcs_writel(GUEST_CR4
, hw_cr4
);
3882 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3883 struct kvm_segment
*var
, int seg
)
3885 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3888 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3889 *var
= vmx
->rmode
.segs
[seg
];
3890 if (seg
== VCPU_SREG_TR
3891 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3893 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3894 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3897 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3898 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3899 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3900 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3901 var
->unusable
= (ar
>> 16) & 1;
3902 var
->type
= ar
& 15;
3903 var
->s
= (ar
>> 4) & 1;
3904 var
->dpl
= (ar
>> 5) & 3;
3906 * Some userspaces do not preserve unusable property. Since usable
3907 * segment has to be present according to VMX spec we can use present
3908 * property to amend userspace bug by making unusable segment always
3909 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3910 * segment as unusable.
3912 var
->present
= !var
->unusable
;
3913 var
->avl
= (ar
>> 12) & 1;
3914 var
->l
= (ar
>> 13) & 1;
3915 var
->db
= (ar
>> 14) & 1;
3916 var
->g
= (ar
>> 15) & 1;
3919 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3921 struct kvm_segment s
;
3923 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3924 vmx_get_segment(vcpu
, &s
, seg
);
3927 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3930 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3932 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3934 if (unlikely(vmx
->rmode
.vm86_active
))
3937 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3938 return VMX_AR_DPL(ar
);
3942 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3946 if (var
->unusable
|| !var
->present
)
3949 ar
= var
->type
& 15;
3950 ar
|= (var
->s
& 1) << 4;
3951 ar
|= (var
->dpl
& 3) << 5;
3952 ar
|= (var
->present
& 1) << 7;
3953 ar
|= (var
->avl
& 1) << 12;
3954 ar
|= (var
->l
& 1) << 13;
3955 ar
|= (var
->db
& 1) << 14;
3956 ar
|= (var
->g
& 1) << 15;
3962 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3963 struct kvm_segment
*var
, int seg
)
3965 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3966 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3968 vmx_segment_cache_clear(vmx
);
3970 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3971 vmx
->rmode
.segs
[seg
] = *var
;
3972 if (seg
== VCPU_SREG_TR
)
3973 vmcs_write16(sf
->selector
, var
->selector
);
3975 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3979 vmcs_writel(sf
->base
, var
->base
);
3980 vmcs_write32(sf
->limit
, var
->limit
);
3981 vmcs_write16(sf
->selector
, var
->selector
);
3984 * Fix the "Accessed" bit in AR field of segment registers for older
3986 * IA32 arch specifies that at the time of processor reset the
3987 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3988 * is setting it to 0 in the userland code. This causes invalid guest
3989 * state vmexit when "unrestricted guest" mode is turned on.
3990 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3991 * tree. Newer qemu binaries with that qemu fix would not need this
3994 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3995 var
->type
|= 0x1; /* Accessed */
3997 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
4000 vmx
->emulation_required
= emulation_required(vcpu
);
4003 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
4005 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
4007 *db
= (ar
>> 14) & 1;
4008 *l
= (ar
>> 13) & 1;
4011 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4013 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
4014 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
4017 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4019 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
4020 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
4023 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4025 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
4026 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
4029 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
4031 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
4032 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
4035 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4037 struct kvm_segment var
;
4040 vmx_get_segment(vcpu
, &var
, seg
);
4042 if (seg
== VCPU_SREG_CS
)
4044 ar
= vmx_segment_access_rights(&var
);
4046 if (var
.base
!= (var
.selector
<< 4))
4048 if (var
.limit
!= 0xffff)
4056 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
4058 struct kvm_segment cs
;
4059 unsigned int cs_rpl
;
4061 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4062 cs_rpl
= cs
.selector
& SEGMENT_RPL_MASK
;
4066 if (~cs
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_ACCESSES_MASK
))
4070 if (cs
.type
& VMX_AR_TYPE_WRITEABLE_MASK
) {
4071 if (cs
.dpl
> cs_rpl
)
4074 if (cs
.dpl
!= cs_rpl
)
4080 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4084 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
4086 struct kvm_segment ss
;
4087 unsigned int ss_rpl
;
4089 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4090 ss_rpl
= ss
.selector
& SEGMENT_RPL_MASK
;
4094 if (ss
.type
!= 3 && ss
.type
!= 7)
4098 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
4106 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
4108 struct kvm_segment var
;
4111 vmx_get_segment(vcpu
, &var
, seg
);
4112 rpl
= var
.selector
& SEGMENT_RPL_MASK
;
4120 if (~var
.type
& (VMX_AR_TYPE_CODE_MASK
|VMX_AR_TYPE_WRITEABLE_MASK
)) {
4121 if (var
.dpl
< rpl
) /* DPL < RPL */
4125 /* TODO: Add other members to kvm_segment_field to allow checking for other access
4131 static bool tr_valid(struct kvm_vcpu
*vcpu
)
4133 struct kvm_segment tr
;
4135 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
4139 if (tr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4141 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
4149 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
4151 struct kvm_segment ldtr
;
4153 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
4157 if (ldtr
.selector
& SEGMENT_TI_MASK
) /* TI = 1 */
4167 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
4169 struct kvm_segment cs
, ss
;
4171 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
4172 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
4174 return ((cs
.selector
& SEGMENT_RPL_MASK
) ==
4175 (ss
.selector
& SEGMENT_RPL_MASK
));
4179 * Check if guest state is valid. Returns true if valid, false if
4181 * We assume that registers are always usable
4183 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
4185 if (enable_unrestricted_guest
)
4188 /* real mode guest state checks */
4189 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
4190 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
4192 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
4194 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
4196 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
4198 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
4200 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
4203 /* protected mode guest state checks */
4204 if (!cs_ss_rpl_check(vcpu
))
4206 if (!code_segment_valid(vcpu
))
4208 if (!stack_segment_valid(vcpu
))
4210 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
4212 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
4214 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
4216 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
4218 if (!tr_valid(vcpu
))
4220 if (!ldtr_valid(vcpu
))
4224 * - Add checks on RIP
4225 * - Add checks on RFLAGS
4231 static int init_rmode_tss(struct kvm
*kvm
)
4237 idx
= srcu_read_lock(&kvm
->srcu
);
4238 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
4239 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4242 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
4243 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
4244 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
4247 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
4250 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
4254 r
= kvm_write_guest_page(kvm
, fn
, &data
,
4255 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
4258 srcu_read_unlock(&kvm
->srcu
, idx
);
4262 static int init_rmode_identity_map(struct kvm
*kvm
)
4265 kvm_pfn_t identity_map_pfn
;
4271 /* Protect kvm->arch.ept_identity_pagetable_done. */
4272 mutex_lock(&kvm
->slots_lock
);
4274 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
4277 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
4279 r
= alloc_identity_pagetable(kvm
);
4283 idx
= srcu_read_lock(&kvm
->srcu
);
4284 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
4287 /* Set up identity-mapping pagetable for EPT in real mode */
4288 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
4289 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
4290 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
4291 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
4292 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
4296 kvm
->arch
.ept_identity_pagetable_done
= true;
4299 srcu_read_unlock(&kvm
->srcu
, idx
);
4302 mutex_unlock(&kvm
->slots_lock
);
4306 static void seg_setup(int seg
)
4308 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
4311 vmcs_write16(sf
->selector
, 0);
4312 vmcs_writel(sf
->base
, 0);
4313 vmcs_write32(sf
->limit
, 0xffff);
4315 if (seg
== VCPU_SREG_CS
)
4316 ar
|= 0x08; /* code segment */
4318 vmcs_write32(sf
->ar_bytes
, ar
);
4321 static int alloc_apic_access_page(struct kvm
*kvm
)
4326 mutex_lock(&kvm
->slots_lock
);
4327 if (kvm
->arch
.apic_access_page_done
)
4329 r
= __x86_set_memory_region(kvm
, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
,
4330 APIC_DEFAULT_PHYS_BASE
, PAGE_SIZE
);
4334 page
= gfn_to_page(kvm
, APIC_DEFAULT_PHYS_BASE
>> PAGE_SHIFT
);
4335 if (is_error_page(page
)) {
4341 * Do not pin the page in memory, so that memory hot-unplug
4342 * is able to migrate it.
4345 kvm
->arch
.apic_access_page_done
= true;
4347 mutex_unlock(&kvm
->slots_lock
);
4351 static int alloc_identity_pagetable(struct kvm
*kvm
)
4353 /* Called with kvm->slots_lock held. */
4357 BUG_ON(kvm
->arch
.ept_identity_pagetable_done
);
4359 r
= __x86_set_memory_region(kvm
, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
,
4360 kvm
->arch
.ept_identity_map_addr
, PAGE_SIZE
);
4365 static int allocate_vpid(void)
4371 spin_lock(&vmx_vpid_lock
);
4372 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4373 if (vpid
< VMX_NR_VPIDS
)
4374 __set_bit(vpid
, vmx_vpid_bitmap
);
4377 spin_unlock(&vmx_vpid_lock
);
4381 static void free_vpid(int vpid
)
4383 if (!enable_vpid
|| vpid
== 0)
4385 spin_lock(&vmx_vpid_lock
);
4386 __clear_bit(vpid
, vmx_vpid_bitmap
);
4387 spin_unlock(&vmx_vpid_lock
);
4390 #define MSR_TYPE_R 1
4391 #define MSR_TYPE_W 2
4392 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4395 int f
= sizeof(unsigned long);
4397 if (!cpu_has_vmx_msr_bitmap())
4401 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4402 * have the write-low and read-high bitmap offsets the wrong way round.
4403 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4405 if (msr
<= 0x1fff) {
4406 if (type
& MSR_TYPE_R
)
4408 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4410 if (type
& MSR_TYPE_W
)
4412 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4414 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4416 if (type
& MSR_TYPE_R
)
4418 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4420 if (type
& MSR_TYPE_W
)
4422 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4427 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4430 int f
= sizeof(unsigned long);
4432 if (!cpu_has_vmx_msr_bitmap())
4436 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4437 * have the write-low and read-high bitmap offsets the wrong way round.
4438 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4440 if (msr
<= 0x1fff) {
4441 if (type
& MSR_TYPE_R
)
4443 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4445 if (type
& MSR_TYPE_W
)
4447 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4449 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4451 if (type
& MSR_TYPE_R
)
4453 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4455 if (type
& MSR_TYPE_W
)
4457 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4463 * If a msr is allowed by L0, we should check whether it is allowed by L1.
4464 * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4466 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1
,
4467 unsigned long *msr_bitmap_nested
,
4470 int f
= sizeof(unsigned long);
4472 if (!cpu_has_vmx_msr_bitmap()) {
4478 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4479 * have the write-low and read-high bitmap offsets the wrong way round.
4480 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4482 if (msr
<= 0x1fff) {
4483 if (type
& MSR_TYPE_R
&&
4484 !test_bit(msr
, msr_bitmap_l1
+ 0x000 / f
))
4486 __clear_bit(msr
, msr_bitmap_nested
+ 0x000 / f
);
4488 if (type
& MSR_TYPE_W
&&
4489 !test_bit(msr
, msr_bitmap_l1
+ 0x800 / f
))
4491 __clear_bit(msr
, msr_bitmap_nested
+ 0x800 / f
);
4493 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4495 if (type
& MSR_TYPE_R
&&
4496 !test_bit(msr
, msr_bitmap_l1
+ 0x400 / f
))
4498 __clear_bit(msr
, msr_bitmap_nested
+ 0x400 / f
);
4500 if (type
& MSR_TYPE_W
&&
4501 !test_bit(msr
, msr_bitmap_l1
+ 0xc00 / f
))
4503 __clear_bit(msr
, msr_bitmap_nested
+ 0xc00 / f
);
4508 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4511 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4512 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4513 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4514 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4517 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4519 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4521 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4525 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4527 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4529 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4533 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4535 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4537 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4541 static bool vmx_get_enable_apicv(void)
4543 return enable_apicv
;
4546 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu
*vcpu
)
4548 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4553 if (vmx
->nested
.pi_desc
&&
4554 vmx
->nested
.pi_pending
) {
4555 vmx
->nested
.pi_pending
= false;
4556 if (!pi_test_and_clear_on(vmx
->nested
.pi_desc
))
4559 max_irr
= find_last_bit(
4560 (unsigned long *)vmx
->nested
.pi_desc
->pir
, 256);
4565 vapic_page
= kmap(vmx
->nested
.virtual_apic_page
);
4570 __kvm_apic_update_irr(vmx
->nested
.pi_desc
->pir
, vapic_page
);
4571 kunmap(vmx
->nested
.virtual_apic_page
);
4573 status
= vmcs_read16(GUEST_INTR_STATUS
);
4574 if ((u8
)max_irr
> ((u8
)status
& 0xff)) {
4576 status
|= (u8
)max_irr
;
4577 vmcs_write16(GUEST_INTR_STATUS
, status
);
4583 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu
*vcpu
)
4586 if (vcpu
->mode
== IN_GUEST_MODE
) {
4587 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4590 * Currently, we don't support urgent interrupt,
4591 * all interrupts are recognized as non-urgent
4592 * interrupt, so we cannot post interrupts when
4595 * If the vcpu is in guest mode, it means it is
4596 * running instead of being scheduled out and
4597 * waiting in the run queue, and that's the only
4598 * case when 'SN' is set currently, warning if
4601 WARN_ON_ONCE(pi_test_sn(&vmx
->pi_desc
));
4603 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4604 POSTED_INTR_VECTOR
);
4611 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu
*vcpu
,
4614 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4616 if (is_guest_mode(vcpu
) &&
4617 vector
== vmx
->nested
.posted_intr_nv
) {
4618 /* the PIR and ON have been set by L1. */
4619 kvm_vcpu_trigger_posted_interrupt(vcpu
);
4621 * If a posted intr is not recognized by hardware,
4622 * we will accomplish it in the next vmentry.
4624 vmx
->nested
.pi_pending
= true;
4625 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4631 * Send interrupt to vcpu via posted interrupt way.
4632 * 1. If target vcpu is running(non-root mode), send posted interrupt
4633 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4634 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4635 * interrupt from PIR in next vmentry.
4637 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4639 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4642 r
= vmx_deliver_nested_posted_interrupt(vcpu
, vector
);
4646 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4649 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4650 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4651 if (r
|| !kvm_vcpu_trigger_posted_interrupt(vcpu
))
4652 kvm_vcpu_kick(vcpu
);
4655 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4657 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4659 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4662 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4666 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4667 * will not change in the lifetime of the guest.
4668 * Note that host-state that does change is set elsewhere. E.g., host-state
4669 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4671 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4678 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4679 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4681 /* Save the most likely value for this task's CR4 in the VMCS. */
4682 cr4
= cr4_read_shadow();
4683 vmcs_writel(HOST_CR4
, cr4
); /* 22.2.3, 22.2.5 */
4684 vmx
->host_state
.vmcs_host_cr4
= cr4
;
4686 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4687 #ifdef CONFIG_X86_64
4689 * Load null selectors, so we can avoid reloading them in
4690 * __vmx_load_host_state(), in case userspace uses the null selectors
4691 * too (the expected case).
4693 vmcs_write16(HOST_DS_SELECTOR
, 0);
4694 vmcs_write16(HOST_ES_SELECTOR
, 0);
4696 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4697 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4699 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4700 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4702 native_store_idt(&dt
);
4703 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4704 vmx
->host_idt_base
= dt
.address
;
4706 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4708 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4709 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4710 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4711 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4713 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4714 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4715 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4719 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4721 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4723 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4724 if (is_guest_mode(&vmx
->vcpu
))
4725 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4726 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4727 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4730 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4732 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4734 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4735 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4736 return pin_based_exec_ctrl
;
4739 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu
*vcpu
)
4741 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4743 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4746 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4748 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4750 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4751 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4753 if (!cpu_need_tpr_shadow(&vmx
->vcpu
)) {
4754 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4755 #ifdef CONFIG_X86_64
4756 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4757 CPU_BASED_CR8_LOAD_EXITING
;
4761 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4762 CPU_BASED_CR3_LOAD_EXITING
|
4763 CPU_BASED_INVLPG_EXITING
;
4764 return exec_control
;
4767 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4769 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4770 if (!cpu_need_virtualize_apic_accesses(&vmx
->vcpu
))
4771 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4773 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4775 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4776 enable_unrestricted_guest
= 0;
4777 /* Enable INVPCID for non-ept guests may cause performance regression. */
4778 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4780 if (!enable_unrestricted_guest
)
4781 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4783 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4784 if (!kvm_vcpu_apicv_active(&vmx
->vcpu
))
4785 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4786 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4787 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4788 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4790 We can NOT enable shadow_vmcs here because we don't have yet
4793 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4796 exec_control
&= ~SECONDARY_EXEC_ENABLE_PML
;
4798 /* Currently, we allow L1 guest to directly run pcommit instruction. */
4799 exec_control
&= ~SECONDARY_EXEC_PCOMMIT
;
4801 return exec_control
;
4804 static void ept_set_mmio_spte_mask(void)
4807 * EPT Misconfigurations can be generated if the value of bits 2:0
4808 * of an EPT paging-structure entry is 110b (write/execute).
4809 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4812 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4815 #define VMX_XSS_EXIT_BITMAP 0
4817 * Sets up the vmcs for emulated real mode.
4819 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4821 #ifdef CONFIG_X86_64
4827 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4828 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4830 if (enable_shadow_vmcs
) {
4831 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4832 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4834 if (cpu_has_vmx_msr_bitmap())
4835 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4837 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4840 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4842 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4844 if (cpu_has_secondary_exec_ctrls())
4845 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4846 vmx_secondary_exec_control(vmx
));
4848 if (kvm_vcpu_apicv_active(&vmx
->vcpu
)) {
4849 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4850 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4851 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4852 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4854 vmcs_write16(GUEST_INTR_STATUS
, 0);
4856 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4857 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4861 vmcs_write32(PLE_GAP
, ple_gap
);
4862 vmx
->ple_window
= ple_window
;
4863 vmx
->ple_window_dirty
= true;
4866 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4867 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4868 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4870 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4871 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4872 vmx_set_constant_host_state(vmx
);
4873 #ifdef CONFIG_X86_64
4874 rdmsrl(MSR_FS_BASE
, a
);
4875 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4876 rdmsrl(MSR_GS_BASE
, a
);
4877 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4879 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4880 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4883 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4884 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4885 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4886 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4887 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4889 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
4890 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
4892 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
) {
4893 u32 index
= vmx_msr_index
[i
];
4894 u32 data_low
, data_high
;
4897 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4899 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4901 vmx
->guest_msrs
[j
].index
= i
;
4902 vmx
->guest_msrs
[j
].data
= 0;
4903 vmx
->guest_msrs
[j
].mask
= -1ull;
4908 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4910 /* 22.2.1, 20.8.1 */
4911 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4913 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4914 set_cr4_guest_host_mask(vmx
);
4916 if (vmx_xsaves_supported())
4917 vmcs_write64(XSS_EXIT_BITMAP
, VMX_XSS_EXIT_BITMAP
);
4922 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
, bool init_event
)
4924 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4925 struct msr_data apic_base_msr
;
4928 vmx
->rmode
.vm86_active
= 0;
4930 vmx
->soft_vnmi_blocked
= 0;
4932 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4933 kvm_set_cr8(vcpu
, 0);
4936 apic_base_msr
.data
= APIC_DEFAULT_PHYS_BASE
|
4937 MSR_IA32_APICBASE_ENABLE
;
4938 if (kvm_vcpu_is_reset_bsp(vcpu
))
4939 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4940 apic_base_msr
.host_initiated
= true;
4941 kvm_set_apic_base(vcpu
, &apic_base_msr
);
4944 vmx_segment_cache_clear(vmx
);
4946 seg_setup(VCPU_SREG_CS
);
4947 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4948 vmcs_writel(GUEST_CS_BASE
, 0xffff0000ul
);
4950 seg_setup(VCPU_SREG_DS
);
4951 seg_setup(VCPU_SREG_ES
);
4952 seg_setup(VCPU_SREG_FS
);
4953 seg_setup(VCPU_SREG_GS
);
4954 seg_setup(VCPU_SREG_SS
);
4956 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4957 vmcs_writel(GUEST_TR_BASE
, 0);
4958 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4959 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4961 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4962 vmcs_writel(GUEST_LDTR_BASE
, 0);
4963 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4964 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4967 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4968 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4969 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4970 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4973 vmcs_writel(GUEST_RFLAGS
, 0x02);
4974 kvm_rip_write(vcpu
, 0xfff0);
4976 vmcs_writel(GUEST_GDTR_BASE
, 0);
4977 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4979 vmcs_writel(GUEST_IDTR_BASE
, 0);
4980 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4982 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4983 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4984 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4988 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4990 if (cpu_has_vmx_tpr_shadow() && !init_event
) {
4991 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4992 if (cpu_need_tpr_shadow(vcpu
))
4993 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4994 __pa(vcpu
->arch
.apic
->regs
));
4995 vmcs_write32(TPR_THRESHOLD
, 0);
4998 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD
, vcpu
);
5000 if (kvm_vcpu_apicv_active(vcpu
))
5001 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
5004 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
5006 cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
5007 vmx_set_cr0(vcpu
, cr0
); /* enter rmode */
5008 vmx
->vcpu
.arch
.cr0
= cr0
;
5009 vmx_set_cr4(vcpu
, 0);
5010 vmx_set_efer(vcpu
, 0);
5011 vmx_fpu_activate(vcpu
);
5012 update_exception_bitmap(vcpu
);
5014 vpid_sync_context(vmx
->vpid
);
5018 * In nested virtualization, check if L1 asked to exit on external interrupts.
5019 * For most existing hypervisors, this will always return true.
5021 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
5023 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5024 PIN_BASED_EXT_INTR_MASK
;
5028 * In nested virtualization, check if L1 has set
5029 * VM_EXIT_ACK_INTR_ON_EXIT
5031 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
5033 return get_vmcs12(vcpu
)->vm_exit_controls
&
5034 VM_EXIT_ACK_INTR_ON_EXIT
;
5037 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
5039 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
5040 PIN_BASED_NMI_EXITING
;
5043 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
5045 u32 cpu_based_vm_exec_control
;
5047 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5048 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
5049 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5052 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
5054 u32 cpu_based_vm_exec_control
;
5056 if (!cpu_has_virtual_nmis() ||
5057 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
5058 enable_irq_window(vcpu
);
5062 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5063 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
5064 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5067 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
5069 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5071 int irq
= vcpu
->arch
.interrupt
.nr
;
5073 trace_kvm_inj_virq(irq
);
5075 ++vcpu
->stat
.irq_injections
;
5076 if (vmx
->rmode
.vm86_active
) {
5078 if (vcpu
->arch
.interrupt
.soft
)
5079 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
5080 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
5081 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5084 intr
= irq
| INTR_INFO_VALID_MASK
;
5085 if (vcpu
->arch
.interrupt
.soft
) {
5086 intr
|= INTR_TYPE_SOFT_INTR
;
5087 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
5088 vmx
->vcpu
.arch
.event_exit_inst_len
);
5090 intr
|= INTR_TYPE_EXT_INTR
;
5091 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
5094 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
5096 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5098 if (is_guest_mode(vcpu
))
5101 if (!cpu_has_virtual_nmis()) {
5103 * Tracking the NMI-blocked state in software is built upon
5104 * finding the next open IRQ window. This, in turn, depends on
5105 * well-behaving guests: They have to keep IRQs disabled at
5106 * least as long as the NMI handler runs. Otherwise we may
5107 * cause NMI nesting, maybe breaking the guest. But as this is
5108 * highly unlikely, we can live with the residual risk.
5110 vmx
->soft_vnmi_blocked
= 1;
5111 vmx
->vnmi_blocked_time
= 0;
5114 ++vcpu
->stat
.nmi_injections
;
5115 vmx
->nmi_known_unmasked
= false;
5116 if (vmx
->rmode
.vm86_active
) {
5117 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
5118 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
5121 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
5122 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
5125 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
5127 if (!cpu_has_virtual_nmis())
5128 return to_vmx(vcpu
)->soft_vnmi_blocked
;
5129 if (to_vmx(vcpu
)->nmi_known_unmasked
)
5131 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
5134 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
5136 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5138 if (!cpu_has_virtual_nmis()) {
5139 if (vmx
->soft_vnmi_blocked
!= masked
) {
5140 vmx
->soft_vnmi_blocked
= masked
;
5141 vmx
->vnmi_blocked_time
= 0;
5144 vmx
->nmi_known_unmasked
= !masked
;
5146 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
5147 GUEST_INTR_STATE_NMI
);
5149 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
5150 GUEST_INTR_STATE_NMI
);
5154 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
5156 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
5159 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
5162 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5163 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
5164 | GUEST_INTR_STATE_NMI
));
5167 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
5169 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
5170 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
5171 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
5172 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
5175 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
5179 ret
= x86_set_memory_region(kvm
, TSS_PRIVATE_MEMSLOT
, addr
,
5183 kvm
->arch
.tss_addr
= addr
;
5184 return init_rmode_tss(kvm
);
5187 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
5192 * Update instruction length as we may reinject the exception
5193 * from user space while in guest debugging mode.
5195 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
5196 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5197 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
5201 if (vcpu
->guest_debug
&
5202 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
5219 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
5220 int vec
, u32 err_code
)
5223 * Instruction with address size override prefix opcode 0x67
5224 * Cause the #SS fault with 0 error code in VM86 mode.
5226 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
5227 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
5228 if (vcpu
->arch
.halt_request
) {
5229 vcpu
->arch
.halt_request
= 0;
5230 return kvm_vcpu_halt(vcpu
);
5238 * Forward all other exceptions that are valid in real mode.
5239 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5240 * the required debugging infrastructure rework.
5242 kvm_queue_exception(vcpu
, vec
);
5247 * Trigger machine check on the host. We assume all the MSRs are already set up
5248 * by the CPU and that we still run on the same CPU as the MCE occurred on.
5249 * We pass a fake environment to the machine check handler because we want
5250 * the guest to be always treated like user space, no matter what context
5251 * it used internally.
5253 static void kvm_machine_check(void)
5255 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5256 struct pt_regs regs
= {
5257 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
5258 .flags
= X86_EFLAGS_IF
,
5261 do_machine_check(®s
, 0);
5265 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
5267 /* already handled by vcpu_run */
5271 static int handle_exception(struct kvm_vcpu
*vcpu
)
5273 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5274 struct kvm_run
*kvm_run
= vcpu
->run
;
5275 u32 intr_info
, ex_no
, error_code
;
5276 unsigned long cr2
, rip
, dr6
;
5278 enum emulation_result er
;
5280 vect_info
= vmx
->idt_vectoring_info
;
5281 intr_info
= vmx
->exit_intr_info
;
5283 if (is_machine_check(intr_info
))
5284 return handle_machine_check(vcpu
);
5286 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
5287 return 1; /* already handled by vmx_vcpu_run() */
5289 if (is_no_device(intr_info
)) {
5290 vmx_fpu_activate(vcpu
);
5294 if (is_invalid_opcode(intr_info
)) {
5295 if (is_guest_mode(vcpu
)) {
5296 kvm_queue_exception(vcpu
, UD_VECTOR
);
5299 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
5300 if (er
!= EMULATE_DONE
)
5301 kvm_queue_exception(vcpu
, UD_VECTOR
);
5306 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
5307 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
5310 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5311 * MMIO, it is better to report an internal error.
5312 * See the comments in vmx_handle_exit.
5314 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
5315 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
5316 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5317 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
5318 vcpu
->run
->internal
.ndata
= 3;
5319 vcpu
->run
->internal
.data
[0] = vect_info
;
5320 vcpu
->run
->internal
.data
[1] = intr_info
;
5321 vcpu
->run
->internal
.data
[2] = error_code
;
5325 if (is_page_fault(intr_info
)) {
5326 /* EPT won't cause page fault directly */
5328 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
5329 trace_kvm_page_fault(cr2
, error_code
);
5331 if (kvm_event_needs_reinjection(vcpu
))
5332 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
5333 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
5336 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
5338 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
5339 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
5343 kvm_queue_exception_e(vcpu
, AC_VECTOR
, error_code
);
5346 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
5347 if (!(vcpu
->guest_debug
&
5348 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
5349 vcpu
->arch
.dr6
&= ~15;
5350 vcpu
->arch
.dr6
|= dr6
| DR6_RTM
;
5351 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
5352 skip_emulated_instruction(vcpu
);
5354 kvm_queue_exception(vcpu
, DB_VECTOR
);
5357 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
5358 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
5362 * Update instruction length as we may reinject #BP from
5363 * user space while in guest debugging mode. Reading it for
5364 * #DB as well causes no harm, it is not used in that case.
5366 vmx
->vcpu
.arch
.event_exit_inst_len
=
5367 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
5368 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
5369 rip
= kvm_rip_read(vcpu
);
5370 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
5371 kvm_run
->debug
.arch
.exception
= ex_no
;
5374 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
5375 kvm_run
->ex
.exception
= ex_no
;
5376 kvm_run
->ex
.error_code
= error_code
;
5382 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
5384 ++vcpu
->stat
.irq_exits
;
5388 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
5390 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
5394 static int handle_io(struct kvm_vcpu
*vcpu
)
5396 unsigned long exit_qualification
;
5397 int size
, in
, string
;
5400 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5401 string
= (exit_qualification
& 16) != 0;
5402 in
= (exit_qualification
& 8) != 0;
5404 ++vcpu
->stat
.io_exits
;
5407 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5409 port
= exit_qualification
>> 16;
5410 size
= (exit_qualification
& 7) + 1;
5411 skip_emulated_instruction(vcpu
);
5413 return kvm_fast_pio_out(vcpu
, size
, port
);
5417 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
5420 * Patch in the VMCALL instruction:
5422 hypercall
[0] = 0x0f;
5423 hypercall
[1] = 0x01;
5424 hypercall
[2] = 0xc1;
5427 static bool nested_cr0_valid(struct kvm_vcpu
*vcpu
, unsigned long val
)
5429 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
5430 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5432 if (to_vmx(vcpu
)->nested
.nested_vmx_secondary_ctls_high
&
5433 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
5434 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
5435 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
5436 return (val
& always_on
) == always_on
;
5439 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5440 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
5442 if (is_guest_mode(vcpu
)) {
5443 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5444 unsigned long orig_val
= val
;
5447 * We get here when L2 changed cr0 in a way that did not change
5448 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5449 * but did change L0 shadowed bits. So we first calculate the
5450 * effective cr0 value that L1 would like to write into the
5451 * hardware. It consists of the L2-owned bits from the new
5452 * value combined with the L1-owned bits from L1's guest_cr0.
5454 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
5455 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
5457 if (!nested_cr0_valid(vcpu
, val
))
5460 if (kvm_set_cr0(vcpu
, val
))
5462 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
5465 if (to_vmx(vcpu
)->nested
.vmxon
&&
5466 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
5468 return kvm_set_cr0(vcpu
, val
);
5472 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
5474 if (is_guest_mode(vcpu
)) {
5475 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5476 unsigned long orig_val
= val
;
5478 /* analogously to handle_set_cr0 */
5479 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5480 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5481 if (kvm_set_cr4(vcpu
, val
))
5483 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5486 return kvm_set_cr4(vcpu
, val
);
5489 /* called to set cr0 as approriate for clts instruction exit. */
5490 static void handle_clts(struct kvm_vcpu
*vcpu
)
5492 if (is_guest_mode(vcpu
)) {
5494 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5495 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5496 * just pretend it's off (also in arch.cr0 for fpu_activate).
5498 vmcs_writel(CR0_READ_SHADOW
,
5499 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5500 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5502 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5505 static int handle_cr(struct kvm_vcpu
*vcpu
)
5507 unsigned long exit_qualification
, val
;
5512 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5513 cr
= exit_qualification
& 15;
5514 reg
= (exit_qualification
>> 8) & 15;
5515 switch ((exit_qualification
>> 4) & 3) {
5516 case 0: /* mov to cr */
5517 val
= kvm_register_readl(vcpu
, reg
);
5518 trace_kvm_cr_write(cr
, val
);
5521 err
= handle_set_cr0(vcpu
, val
);
5522 kvm_complete_insn_gp(vcpu
, err
);
5525 err
= kvm_set_cr3(vcpu
, val
);
5526 kvm_complete_insn_gp(vcpu
, err
);
5529 err
= handle_set_cr4(vcpu
, val
);
5530 kvm_complete_insn_gp(vcpu
, err
);
5533 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5535 err
= kvm_set_cr8(vcpu
, cr8
);
5536 kvm_complete_insn_gp(vcpu
, err
);
5537 if (lapic_in_kernel(vcpu
))
5539 if (cr8_prev
<= cr8
)
5541 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5548 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5549 skip_emulated_instruction(vcpu
);
5550 vmx_fpu_activate(vcpu
);
5552 case 1: /*mov from cr*/
5555 val
= kvm_read_cr3(vcpu
);
5556 kvm_register_write(vcpu
, reg
, val
);
5557 trace_kvm_cr_read(cr
, val
);
5558 skip_emulated_instruction(vcpu
);
5561 val
= kvm_get_cr8(vcpu
);
5562 kvm_register_write(vcpu
, reg
, val
);
5563 trace_kvm_cr_read(cr
, val
);
5564 skip_emulated_instruction(vcpu
);
5569 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5570 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5571 kvm_lmsw(vcpu
, val
);
5573 skip_emulated_instruction(vcpu
);
5578 vcpu
->run
->exit_reason
= 0;
5579 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5580 (int)(exit_qualification
>> 4) & 3, cr
);
5584 static int handle_dr(struct kvm_vcpu
*vcpu
)
5586 unsigned long exit_qualification
;
5589 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5590 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5592 /* First, if DR does not exist, trigger UD */
5593 if (!kvm_require_dr(vcpu
, dr
))
5596 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5597 if (!kvm_require_cpl(vcpu
, 0))
5599 dr7
= vmcs_readl(GUEST_DR7
);
5602 * As the vm-exit takes precedence over the debug trap, we
5603 * need to emulate the latter, either for the host or the
5604 * guest debugging itself.
5606 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5607 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5608 vcpu
->run
->debug
.arch
.dr7
= dr7
;
5609 vcpu
->run
->debug
.arch
.pc
= kvm_get_linear_rip(vcpu
);
5610 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5611 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5614 vcpu
->arch
.dr6
&= ~15;
5615 vcpu
->arch
.dr6
|= DR6_BD
| DR6_RTM
;
5616 kvm_queue_exception(vcpu
, DB_VECTOR
);
5621 if (vcpu
->guest_debug
== 0) {
5622 u32 cpu_based_vm_exec_control
;
5624 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5625 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5626 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5629 * No more DR vmexits; force a reload of the debug registers
5630 * and reenter on this instruction. The next vmexit will
5631 * retrieve the full state of the debug registers.
5633 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5637 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5638 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5641 if (kvm_get_dr(vcpu
, dr
, &val
))
5643 kvm_register_write(vcpu
, reg
, val
);
5645 if (kvm_set_dr(vcpu
, dr
, kvm_register_readl(vcpu
, reg
)))
5648 skip_emulated_instruction(vcpu
);
5652 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5654 return vcpu
->arch
.dr6
;
5657 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5661 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5663 u32 cpu_based_vm_exec_control
;
5665 get_debugreg(vcpu
->arch
.db
[0], 0);
5666 get_debugreg(vcpu
->arch
.db
[1], 1);
5667 get_debugreg(vcpu
->arch
.db
[2], 2);
5668 get_debugreg(vcpu
->arch
.db
[3], 3);
5669 get_debugreg(vcpu
->arch
.dr6
, 6);
5670 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5672 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5674 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5675 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5676 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5679 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5681 vmcs_writel(GUEST_DR7
, val
);
5684 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5686 kvm_emulate_cpuid(vcpu
);
5690 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5692 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5693 struct msr_data msr_info
;
5695 msr_info
.index
= ecx
;
5696 msr_info
.host_initiated
= false;
5697 if (vmx_get_msr(vcpu
, &msr_info
)) {
5698 trace_kvm_msr_read_ex(ecx
);
5699 kvm_inject_gp(vcpu
, 0);
5703 trace_kvm_msr_read(ecx
, msr_info
.data
);
5705 /* FIXME: handling of bits 32:63 of rax, rdx */
5706 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = msr_info
.data
& -1u;
5707 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (msr_info
.data
>> 32) & -1u;
5708 skip_emulated_instruction(vcpu
);
5712 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5714 struct msr_data msr
;
5715 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5716 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5717 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5721 msr
.host_initiated
= false;
5722 if (kvm_set_msr(vcpu
, &msr
) != 0) {
5723 trace_kvm_msr_write_ex(ecx
, data
);
5724 kvm_inject_gp(vcpu
, 0);
5728 trace_kvm_msr_write(ecx
, data
);
5729 skip_emulated_instruction(vcpu
);
5733 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5735 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5739 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5741 u32 cpu_based_vm_exec_control
;
5743 /* clear pending irq */
5744 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5745 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5746 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5748 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5750 ++vcpu
->stat
.irq_window_exits
;
5754 static int handle_halt(struct kvm_vcpu
*vcpu
)
5756 return kvm_emulate_halt(vcpu
);
5759 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5761 kvm_emulate_hypercall(vcpu
);
5765 static int handle_invd(struct kvm_vcpu
*vcpu
)
5767 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5770 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5772 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5774 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5775 skip_emulated_instruction(vcpu
);
5779 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5783 err
= kvm_rdpmc(vcpu
);
5784 kvm_complete_insn_gp(vcpu
, err
);
5789 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5791 kvm_emulate_wbinvd(vcpu
);
5795 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5797 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5798 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5800 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5801 skip_emulated_instruction(vcpu
);
5805 static int handle_xsaves(struct kvm_vcpu
*vcpu
)
5807 skip_emulated_instruction(vcpu
);
5808 WARN(1, "this should never happen\n");
5812 static int handle_xrstors(struct kvm_vcpu
*vcpu
)
5814 skip_emulated_instruction(vcpu
);
5815 WARN(1, "this should never happen\n");
5819 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5821 if (likely(fasteoi
)) {
5822 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5823 int access_type
, offset
;
5825 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5826 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5828 * Sane guest uses MOV to write EOI, with written value
5829 * not cared. So make a short-circuit here by avoiding
5830 * heavy instruction emulation.
5832 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5833 (offset
== APIC_EOI
)) {
5834 kvm_lapic_set_eoi(vcpu
);
5835 skip_emulated_instruction(vcpu
);
5839 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5842 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5844 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5845 int vector
= exit_qualification
& 0xff;
5847 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5848 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5852 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5854 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5855 u32 offset
= exit_qualification
& 0xfff;
5857 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5858 kvm_apic_write_nodecode(vcpu
, offset
);
5862 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5864 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5865 unsigned long exit_qualification
;
5866 bool has_error_code
= false;
5869 int reason
, type
, idt_v
, idt_index
;
5871 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5872 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5873 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5875 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5877 reason
= (u32
)exit_qualification
>> 30;
5878 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5880 case INTR_TYPE_NMI_INTR
:
5881 vcpu
->arch
.nmi_injected
= false;
5882 vmx_set_nmi_mask(vcpu
, true);
5884 case INTR_TYPE_EXT_INTR
:
5885 case INTR_TYPE_SOFT_INTR
:
5886 kvm_clear_interrupt_queue(vcpu
);
5888 case INTR_TYPE_HARD_EXCEPTION
:
5889 if (vmx
->idt_vectoring_info
&
5890 VECTORING_INFO_DELIVER_CODE_MASK
) {
5891 has_error_code
= true;
5893 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5896 case INTR_TYPE_SOFT_EXCEPTION
:
5897 kvm_clear_exception_queue(vcpu
);
5903 tss_selector
= exit_qualification
;
5905 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5906 type
!= INTR_TYPE_EXT_INTR
&&
5907 type
!= INTR_TYPE_NMI_INTR
))
5908 skip_emulated_instruction(vcpu
);
5910 if (kvm_task_switch(vcpu
, tss_selector
,
5911 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5912 has_error_code
, error_code
) == EMULATE_FAIL
) {
5913 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5914 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5915 vcpu
->run
->internal
.ndata
= 0;
5920 * TODO: What about debug traps on tss switch?
5921 * Are we supposed to inject them and update dr6?
5927 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5929 unsigned long exit_qualification
;
5934 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5936 gla_validity
= (exit_qualification
>> 7) & 0x3;
5937 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5938 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5939 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5940 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5941 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5942 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5943 (long unsigned int)exit_qualification
);
5944 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5945 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5950 * EPT violation happened while executing iret from NMI,
5951 * "blocked by NMI" bit has to be set before next VM entry.
5952 * There are errata that may cause this bit to not be set:
5955 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5956 cpu_has_virtual_nmis() &&
5957 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5958 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5960 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5961 trace_kvm_page_fault(gpa
, exit_qualification
);
5963 /* It is a write fault? */
5964 error_code
= exit_qualification
& PFERR_WRITE_MASK
;
5965 /* It is a fetch fault? */
5966 error_code
|= (exit_qualification
<< 2) & PFERR_FETCH_MASK
;
5967 /* ept page table is present? */
5968 error_code
|= (exit_qualification
>> 3) & PFERR_PRESENT_MASK
;
5970 vcpu
->arch
.exit_qualification
= exit_qualification
;
5972 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5975 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5980 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5981 if (!kvm_io_bus_write(vcpu
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5982 skip_emulated_instruction(vcpu
);
5983 trace_kvm_fast_mmio(gpa
);
5987 ret
= handle_mmio_page_fault(vcpu
, gpa
, true);
5988 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5989 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5992 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5993 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5995 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5998 /* It is the real ept misconfig */
6001 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
6002 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
6007 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
6009 u32 cpu_based_vm_exec_control
;
6011 /* clear pending NMI */
6012 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6013 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
6014 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
6015 ++vcpu
->stat
.nmi_window_exits
;
6016 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
6021 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
6023 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6024 enum emulation_result err
= EMULATE_DONE
;
6027 bool intr_window_requested
;
6028 unsigned count
= 130;
6030 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
6031 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
6033 while (vmx
->emulation_required
&& count
-- != 0) {
6034 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
6035 return handle_interrupt_window(&vmx
->vcpu
);
6037 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
6040 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
6042 if (err
== EMULATE_USER_EXIT
) {
6043 ++vcpu
->stat
.mmio_exits
;
6048 if (err
!= EMULATE_DONE
) {
6049 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
6050 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
6051 vcpu
->run
->internal
.ndata
= 0;
6055 if (vcpu
->arch
.halt_request
) {
6056 vcpu
->arch
.halt_request
= 0;
6057 ret
= kvm_vcpu_halt(vcpu
);
6061 if (signal_pending(current
))
6071 static int __grow_ple_window(int val
)
6073 if (ple_window_grow
< 1)
6076 val
= min(val
, ple_window_actual_max
);
6078 if (ple_window_grow
< ple_window
)
6079 val
*= ple_window_grow
;
6081 val
+= ple_window_grow
;
6086 static int __shrink_ple_window(int val
, int modifier
, int minimum
)
6091 if (modifier
< ple_window
)
6096 return max(val
, minimum
);
6099 static void grow_ple_window(struct kvm_vcpu
*vcpu
)
6101 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6102 int old
= vmx
->ple_window
;
6104 vmx
->ple_window
= __grow_ple_window(old
);
6106 if (vmx
->ple_window
!= old
)
6107 vmx
->ple_window_dirty
= true;
6109 trace_kvm_ple_window_grow(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6112 static void shrink_ple_window(struct kvm_vcpu
*vcpu
)
6114 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6115 int old
= vmx
->ple_window
;
6117 vmx
->ple_window
= __shrink_ple_window(old
,
6118 ple_window_shrink
, ple_window
);
6120 if (vmx
->ple_window
!= old
)
6121 vmx
->ple_window_dirty
= true;
6123 trace_kvm_ple_window_shrink(vcpu
->vcpu_id
, vmx
->ple_window
, old
);
6127 * ple_window_actual_max is computed to be one grow_ple_window() below
6128 * ple_window_max. (See __grow_ple_window for the reason.)
6129 * This prevents overflows, because ple_window_max is int.
6130 * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6132 * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6134 static void update_ple_window_actual_max(void)
6136 ple_window_actual_max
=
6137 __shrink_ple_window(max(ple_window_max
, ple_window
),
6138 ple_window_grow
, INT_MIN
);
6142 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6144 static void wakeup_handler(void)
6146 struct kvm_vcpu
*vcpu
;
6147 int cpu
= smp_processor_id();
6149 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6150 list_for_each_entry(vcpu
, &per_cpu(blocked_vcpu_on_cpu
, cpu
),
6151 blocked_vcpu_list
) {
6152 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
6154 if (pi_test_on(pi_desc
) == 1)
6155 kvm_vcpu_kick(vcpu
);
6157 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock
, cpu
));
6160 static __init
int hardware_setup(void)
6162 int r
= -ENOMEM
, i
, msr
;
6164 rdmsrl_safe(MSR_EFER
, &host_efer
);
6166 for (i
= 0; i
< ARRAY_SIZE(vmx_msr_index
); ++i
)
6167 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
6169 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6170 if (!vmx_io_bitmap_a
)
6173 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6174 if (!vmx_io_bitmap_b
)
6177 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6178 if (!vmx_msr_bitmap_legacy
)
6181 vmx_msr_bitmap_legacy_x2apic
=
6182 (unsigned long *)__get_free_page(GFP_KERNEL
);
6183 if (!vmx_msr_bitmap_legacy_x2apic
)
6186 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6187 if (!vmx_msr_bitmap_longmode
)
6190 vmx_msr_bitmap_longmode_x2apic
=
6191 (unsigned long *)__get_free_page(GFP_KERNEL
);
6192 if (!vmx_msr_bitmap_longmode_x2apic
)
6196 vmx_msr_bitmap_nested
=
6197 (unsigned long *)__get_free_page(GFP_KERNEL
);
6198 if (!vmx_msr_bitmap_nested
)
6202 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6203 if (!vmx_vmread_bitmap
)
6206 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
6207 if (!vmx_vmwrite_bitmap
)
6210 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
6211 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
6214 * Allow direct access to the PC debug port (it is often used for I/O
6215 * delays, but the vmexits simply slow things down).
6217 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
6218 clear_bit(0x80, vmx_io_bitmap_a
);
6220 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
6222 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
6223 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
6225 memset(vmx_msr_bitmap_nested
, 0xff, PAGE_SIZE
);
6227 if (setup_vmcs_config(&vmcs_config
) < 0) {
6232 if (boot_cpu_has(X86_FEATURE_NX
))
6233 kvm_enable_efer_bits(EFER_NX
);
6235 if (!cpu_has_vmx_vpid())
6237 if (!cpu_has_vmx_shadow_vmcs())
6238 enable_shadow_vmcs
= 0;
6239 if (enable_shadow_vmcs
)
6240 init_vmcs_shadow_fields();
6242 if (!cpu_has_vmx_ept() ||
6243 !cpu_has_vmx_ept_4levels()) {
6245 enable_unrestricted_guest
= 0;
6246 enable_ept_ad_bits
= 0;
6249 if (!cpu_has_vmx_ept_ad_bits())
6250 enable_ept_ad_bits
= 0;
6252 if (!cpu_has_vmx_unrestricted_guest())
6253 enable_unrestricted_guest
= 0;
6255 if (!cpu_has_vmx_flexpriority())
6256 flexpriority_enabled
= 0;
6259 * set_apic_access_page_addr() is used to reload apic access
6260 * page upon invalidation. No need to do anything if not
6261 * using the APIC_ACCESS_ADDR VMCS field.
6263 if (!flexpriority_enabled
)
6264 kvm_x86_ops
->set_apic_access_page_addr
= NULL
;
6266 if (!cpu_has_vmx_tpr_shadow())
6267 kvm_x86_ops
->update_cr8_intercept
= NULL
;
6269 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
6270 kvm_disable_largepages();
6272 if (!cpu_has_vmx_ple())
6275 if (!cpu_has_vmx_apicv())
6278 if (cpu_has_vmx_tsc_scaling()) {
6279 kvm_has_tsc_control
= true;
6280 kvm_max_tsc_scaling_ratio
= KVM_VMX_TSC_MULTIPLIER_MAX
;
6281 kvm_tsc_scaling_ratio_frac_bits
= 48;
6284 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
6285 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
6286 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
6287 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
6288 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
6289 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
6290 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
6292 memcpy(vmx_msr_bitmap_legacy_x2apic
,
6293 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
6294 memcpy(vmx_msr_bitmap_longmode_x2apic
,
6295 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
6297 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
6300 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
6301 vmx_disable_intercept_msr_read_x2apic(msr
);
6303 /* According SDM, in x2apic mode, the whole id reg is used.
6304 * But in KVM, it only use the highest eight bits. Need to
6306 vmx_enable_intercept_msr_read_x2apic(0x802);
6308 vmx_enable_intercept_msr_read_x2apic(0x839);
6310 vmx_disable_intercept_msr_write_x2apic(0x808);
6312 vmx_disable_intercept_msr_write_x2apic(0x80b);
6314 vmx_disable_intercept_msr_write_x2apic(0x83f);
6318 kvm_mmu_set_mask_ptes(0ull,
6319 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
6320 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
6321 0ull, VMX_EPT_EXECUTABLE_MASK
);
6322 ept_set_mmio_spte_mask();
6327 update_ple_window_actual_max();
6330 * Only enable PML when hardware supports PML feature, and both EPT
6331 * and EPT A/D bit features are enabled -- PML depends on them to work.
6333 if (!enable_ept
|| !enable_ept_ad_bits
|| !cpu_has_vmx_pml())
6337 kvm_x86_ops
->slot_enable_log_dirty
= NULL
;
6338 kvm_x86_ops
->slot_disable_log_dirty
= NULL
;
6339 kvm_x86_ops
->flush_log_dirty
= NULL
;
6340 kvm_x86_ops
->enable_log_dirty_pt_masked
= NULL
;
6343 kvm_set_posted_intr_wakeup_handler(wakeup_handler
);
6345 return alloc_kvm_area();
6348 free_page((unsigned long)vmx_vmwrite_bitmap
);
6350 free_page((unsigned long)vmx_vmread_bitmap
);
6353 free_page((unsigned long)vmx_msr_bitmap_nested
);
6355 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6357 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6359 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6361 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6363 free_page((unsigned long)vmx_io_bitmap_b
);
6365 free_page((unsigned long)vmx_io_bitmap_a
);
6370 static __exit
void hardware_unsetup(void)
6372 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
6373 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
6374 free_page((unsigned long)vmx_msr_bitmap_legacy
);
6375 free_page((unsigned long)vmx_msr_bitmap_longmode
);
6376 free_page((unsigned long)vmx_io_bitmap_b
);
6377 free_page((unsigned long)vmx_io_bitmap_a
);
6378 free_page((unsigned long)vmx_vmwrite_bitmap
);
6379 free_page((unsigned long)vmx_vmread_bitmap
);
6381 free_page((unsigned long)vmx_msr_bitmap_nested
);
6387 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6388 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6390 static int handle_pause(struct kvm_vcpu
*vcpu
)
6393 grow_ple_window(vcpu
);
6395 skip_emulated_instruction(vcpu
);
6396 kvm_vcpu_on_spin(vcpu
);
6401 static int handle_nop(struct kvm_vcpu
*vcpu
)
6403 skip_emulated_instruction(vcpu
);
6407 static int handle_mwait(struct kvm_vcpu
*vcpu
)
6409 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
6410 return handle_nop(vcpu
);
6413 static int handle_monitor_trap(struct kvm_vcpu
*vcpu
)
6418 static int handle_monitor(struct kvm_vcpu
*vcpu
)
6420 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
6421 return handle_nop(vcpu
);
6425 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6426 * We could reuse a single VMCS for all the L2 guests, but we also want the
6427 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6428 * allows keeping them loaded on the processor, and in the future will allow
6429 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6430 * every entry if they never change.
6431 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6432 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6434 * The following functions allocate and free a vmcs02 in this pool.
6437 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6438 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
6440 struct vmcs02_list
*item
;
6441 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6442 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
6443 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6444 return &item
->vmcs02
;
6447 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
6448 /* Recycle the least recently used VMCS. */
6449 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
6450 struct vmcs02_list
, list
);
6451 item
->vmptr
= vmx
->nested
.current_vmptr
;
6452 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
6453 return &item
->vmcs02
;
6456 /* Create a new VMCS */
6457 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
6460 item
->vmcs02
.vmcs
= alloc_vmcs();
6461 if (!item
->vmcs02
.vmcs
) {
6465 loaded_vmcs_init(&item
->vmcs02
);
6466 item
->vmptr
= vmx
->nested
.current_vmptr
;
6467 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
6468 vmx
->nested
.vmcs02_num
++;
6469 return &item
->vmcs02
;
6472 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6473 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
6475 struct vmcs02_list
*item
;
6476 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
6477 if (item
->vmptr
== vmptr
) {
6478 free_loaded_vmcs(&item
->vmcs02
);
6479 list_del(&item
->list
);
6481 vmx
->nested
.vmcs02_num
--;
6487 * Free all VMCSs saved for this vcpu, except the one pointed by
6488 * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6489 * must be &vmx->vmcs01.
6491 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
6493 struct vmcs02_list
*item
, *n
;
6495 WARN_ON(vmx
->loaded_vmcs
!= &vmx
->vmcs01
);
6496 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
6498 * Something will leak if the above WARN triggers. Better than
6501 if (vmx
->loaded_vmcs
== &item
->vmcs02
)
6504 free_loaded_vmcs(&item
->vmcs02
);
6505 list_del(&item
->list
);
6507 vmx
->nested
.vmcs02_num
--;
6512 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6513 * set the success or error code of an emulated VMX instruction, as specified
6514 * by Vol 2B, VMX Instruction Reference, "Conventions".
6516 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
6518 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
6519 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6520 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
6523 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
6525 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6526 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
6527 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6531 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
6532 u32 vm_instruction_error
)
6534 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
6536 * failValid writes the error number to the current VMCS, which
6537 * can't be done there isn't a current VMCS.
6539 nested_vmx_failInvalid(vcpu
);
6542 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
6543 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
6544 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
6546 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
6548 * We don't need to force a shadow sync because
6549 * VM_INSTRUCTION_ERROR is not shadowed
6553 static void nested_vmx_abort(struct kvm_vcpu
*vcpu
, u32 indicator
)
6555 /* TODO: not to reset guest simply here. */
6556 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6557 pr_warn("kvm: nested vmx abort, indicator %d\n", indicator
);
6560 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
6562 struct vcpu_vmx
*vmx
=
6563 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
6565 vmx
->nested
.preemption_timer_expired
= true;
6566 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
6567 kvm_vcpu_kick(&vmx
->vcpu
);
6569 return HRTIMER_NORESTART
;
6573 * Decode the memory-address operand of a vmx instruction, as recorded on an
6574 * exit caused by such an instruction (run by a guest hypervisor).
6575 * On success, returns 0. When the operand is invalid, returns 1 and throws
6578 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
6579 unsigned long exit_qualification
,
6580 u32 vmx_instruction_info
, bool wr
, gva_t
*ret
)
6584 struct kvm_segment s
;
6587 * According to Vol. 3B, "Information for VM Exits Due to Instruction
6588 * Execution", on an exit, vmx_instruction_info holds most of the
6589 * addressing components of the operand. Only the displacement part
6590 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6591 * For how an actual address is calculated from all these components,
6592 * refer to Vol. 1, "Operand Addressing".
6594 int scaling
= vmx_instruction_info
& 3;
6595 int addr_size
= (vmx_instruction_info
>> 7) & 7;
6596 bool is_reg
= vmx_instruction_info
& (1u << 10);
6597 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
6598 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
6599 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
6600 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
6601 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
6604 kvm_queue_exception(vcpu
, UD_VECTOR
);
6608 /* Addr = segment_base + offset */
6609 /* offset = base + [index * scale] + displacement */
6610 off
= exit_qualification
; /* holds the displacement */
6612 off
+= kvm_register_read(vcpu
, base_reg
);
6614 off
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
6615 vmx_get_segment(vcpu
, &s
, seg_reg
);
6616 *ret
= s
.base
+ off
;
6618 if (addr_size
== 1) /* 32 bit */
6621 /* Checks for #GP/#SS exceptions. */
6623 if (is_protmode(vcpu
)) {
6624 /* Protected mode: apply checks for segment validity in the
6626 * - segment type check (#GP(0) may be thrown)
6627 * - usability check (#GP(0)/#SS(0))
6628 * - limit check (#GP(0)/#SS(0))
6631 /* #GP(0) if the destination operand is located in a
6632 * read-only data segment or any code segment.
6634 exn
= ((s
.type
& 0xa) == 0 || (s
.type
& 8));
6636 /* #GP(0) if the source operand is located in an
6637 * execute-only code segment
6639 exn
= ((s
.type
& 0xa) == 8);
6642 kvm_queue_exception_e(vcpu
, GP_VECTOR
, 0);
6645 if (is_long_mode(vcpu
)) {
6646 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6647 * non-canonical form. This is an only check for long mode.
6649 exn
= is_noncanonical_address(*ret
);
6650 } else if (is_protmode(vcpu
)) {
6651 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6653 exn
= (s
.unusable
!= 0);
6654 /* Protected mode: #GP(0)/#SS(0) if the memory
6655 * operand is outside the segment limit.
6657 exn
= exn
|| (off
+ sizeof(u64
) > s
.limit
);
6660 kvm_queue_exception_e(vcpu
,
6661 seg_reg
== VCPU_SREG_SS
?
6662 SS_VECTOR
: GP_VECTOR
,
6671 * This function performs the various checks including
6672 * - if it's 4KB aligned
6673 * - No bits beyond the physical address width are set
6674 * - Returns 0 on success or else 1
6675 * (Intel SDM Section 30.3)
6677 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
6682 struct x86_exception e
;
6684 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6685 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
6687 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6688 vmcs_read32(VMX_INSTRUCTION_INFO
), false, &gva
))
6691 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
6692 sizeof(vmptr
), &e
)) {
6693 kvm_inject_page_fault(vcpu
, &e
);
6697 switch (exit_reason
) {
6698 case EXIT_REASON_VMON
:
6701 * The first 4 bytes of VMXON region contain the supported
6702 * VMCS revision identifier
6704 * Note - IA32_VMX_BASIC[48] will never be 1
6705 * for the nested case;
6706 * which replaces physical address width with 32
6709 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6710 nested_vmx_failInvalid(vcpu
);
6711 skip_emulated_instruction(vcpu
);
6715 page
= nested_get_page(vcpu
, vmptr
);
6717 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
6718 nested_vmx_failInvalid(vcpu
);
6720 skip_emulated_instruction(vcpu
);
6724 vmx
->nested
.vmxon_ptr
= vmptr
;
6726 case EXIT_REASON_VMCLEAR
:
6727 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6728 nested_vmx_failValid(vcpu
,
6729 VMXERR_VMCLEAR_INVALID_ADDRESS
);
6730 skip_emulated_instruction(vcpu
);
6734 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6735 nested_vmx_failValid(vcpu
,
6736 VMXERR_VMCLEAR_VMXON_POINTER
);
6737 skip_emulated_instruction(vcpu
);
6741 case EXIT_REASON_VMPTRLD
:
6742 if (!PAGE_ALIGNED(vmptr
) || (vmptr
>> maxphyaddr
)) {
6743 nested_vmx_failValid(vcpu
,
6744 VMXERR_VMPTRLD_INVALID_ADDRESS
);
6745 skip_emulated_instruction(vcpu
);
6749 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
6750 nested_vmx_failValid(vcpu
,
6751 VMXERR_VMCLEAR_VMXON_POINTER
);
6752 skip_emulated_instruction(vcpu
);
6757 return 1; /* shouldn't happen */
6766 * Emulate the VMXON instruction.
6767 * Currently, we just remember that VMX is active, and do not save or even
6768 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6769 * do not currently need to store anything in that guest-allocated memory
6770 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6771 * argument is different from the VMXON pointer (which the spec says they do).
6773 static int handle_vmon(struct kvm_vcpu
*vcpu
)
6775 struct kvm_segment cs
;
6776 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6777 struct vmcs
*shadow_vmcs
;
6778 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
6779 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
6781 /* The Intel VMX Instruction Reference lists a bunch of bits that
6782 * are prerequisite to running VMXON, most notably cr4.VMXE must be
6783 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6784 * Otherwise, we should fail with #UD. We test these now:
6786 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
6787 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6788 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6789 kvm_queue_exception(vcpu
, UD_VECTOR
);
6793 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6794 if (is_long_mode(vcpu
) && !cs
.l
) {
6795 kvm_queue_exception(vcpu
, UD_VECTOR
);
6799 if (vmx_get_cpl(vcpu
)) {
6800 kvm_inject_gp(vcpu
, 0);
6804 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6807 if (vmx
->nested
.vmxon
) {
6808 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6809 skip_emulated_instruction(vcpu
);
6813 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6814 != VMXON_NEEDED_FEATURES
) {
6815 kvm_inject_gp(vcpu
, 0);
6819 if (enable_shadow_vmcs
) {
6820 shadow_vmcs
= alloc_vmcs();
6823 /* mark vmcs as shadow */
6824 shadow_vmcs
->revision_id
|= (1u << 31);
6825 /* init shadow vmcs */
6826 vmcs_clear(shadow_vmcs
);
6827 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6830 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6831 vmx
->nested
.vmcs02_num
= 0;
6833 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6835 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6837 vmx
->nested
.vmxon
= true;
6839 skip_emulated_instruction(vcpu
);
6840 nested_vmx_succeed(vcpu
);
6845 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6846 * for running VMX instructions (except VMXON, whose prerequisites are
6847 * slightly different). It also specifies what exception to inject otherwise.
6849 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6851 struct kvm_segment cs
;
6852 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6854 if (!vmx
->nested
.vmxon
) {
6855 kvm_queue_exception(vcpu
, UD_VECTOR
);
6859 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6860 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6861 (is_long_mode(vcpu
) && !cs
.l
)) {
6862 kvm_queue_exception(vcpu
, UD_VECTOR
);
6866 if (vmx_get_cpl(vcpu
)) {
6867 kvm_inject_gp(vcpu
, 0);
6874 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6876 if (vmx
->nested
.current_vmptr
== -1ull)
6879 /* current_vmptr and current_vmcs12 are always set/reset together */
6880 if (WARN_ON(vmx
->nested
.current_vmcs12
== NULL
))
6883 if (enable_shadow_vmcs
) {
6884 /* copy to memory all shadowed fields in case
6885 they were modified */
6886 copy_shadow_to_vmcs12(vmx
);
6887 vmx
->nested
.sync_shadow_vmcs
= false;
6888 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL
,
6889 SECONDARY_EXEC_SHADOW_VMCS
);
6890 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6892 vmx
->nested
.posted_intr_nv
= -1;
6893 kunmap(vmx
->nested
.current_vmcs12_page
);
6894 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6895 vmx
->nested
.current_vmptr
= -1ull;
6896 vmx
->nested
.current_vmcs12
= NULL
;
6900 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6901 * just stops using VMX.
6903 static void free_nested(struct vcpu_vmx
*vmx
)
6905 if (!vmx
->nested
.vmxon
)
6908 vmx
->nested
.vmxon
= false;
6909 free_vpid(vmx
->nested
.vpid02
);
6910 nested_release_vmcs12(vmx
);
6911 if (enable_shadow_vmcs
)
6912 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6913 /* Unpin physical memory we referred to in current vmcs02 */
6914 if (vmx
->nested
.apic_access_page
) {
6915 nested_release_page(vmx
->nested
.apic_access_page
);
6916 vmx
->nested
.apic_access_page
= NULL
;
6918 if (vmx
->nested
.virtual_apic_page
) {
6919 nested_release_page(vmx
->nested
.virtual_apic_page
);
6920 vmx
->nested
.virtual_apic_page
= NULL
;
6922 if (vmx
->nested
.pi_desc_page
) {
6923 kunmap(vmx
->nested
.pi_desc_page
);
6924 nested_release_page(vmx
->nested
.pi_desc_page
);
6925 vmx
->nested
.pi_desc_page
= NULL
;
6926 vmx
->nested
.pi_desc
= NULL
;
6929 nested_free_all_saved_vmcss(vmx
);
6932 /* Emulate the VMXOFF instruction */
6933 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6935 if (!nested_vmx_check_permission(vcpu
))
6937 free_nested(to_vmx(vcpu
));
6938 skip_emulated_instruction(vcpu
);
6939 nested_vmx_succeed(vcpu
);
6943 /* Emulate the VMCLEAR instruction */
6944 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6946 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6948 struct vmcs12
*vmcs12
;
6951 if (!nested_vmx_check_permission(vcpu
))
6954 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6957 if (vmptr
== vmx
->nested
.current_vmptr
)
6958 nested_release_vmcs12(vmx
);
6960 page
= nested_get_page(vcpu
, vmptr
);
6963 * For accurate processor emulation, VMCLEAR beyond available
6964 * physical memory should do nothing at all. However, it is
6965 * possible that a nested vmx bug, not a guest hypervisor bug,
6966 * resulted in this case, so let's shut down before doing any
6969 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6972 vmcs12
= kmap(page
);
6973 vmcs12
->launch_state
= 0;
6975 nested_release_page(page
);
6977 nested_free_vmcs02(vmx
, vmptr
);
6979 skip_emulated_instruction(vcpu
);
6980 nested_vmx_succeed(vcpu
);
6984 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6986 /* Emulate the VMLAUNCH instruction */
6987 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6989 return nested_vmx_run(vcpu
, true);
6992 /* Emulate the VMRESUME instruction */
6993 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6996 return nested_vmx_run(vcpu
, false);
6999 enum vmcs_field_type
{
7000 VMCS_FIELD_TYPE_U16
= 0,
7001 VMCS_FIELD_TYPE_U64
= 1,
7002 VMCS_FIELD_TYPE_U32
= 2,
7003 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
7006 static inline int vmcs_field_type(unsigned long field
)
7008 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
7009 return VMCS_FIELD_TYPE_U32
;
7010 return (field
>> 13) & 0x3 ;
7013 static inline int vmcs_field_readonly(unsigned long field
)
7015 return (((field
>> 10) & 0x3) == 1);
7019 * Read a vmcs12 field. Since these can have varying lengths and we return
7020 * one type, we chose the biggest type (u64) and zero-extend the return value
7021 * to that size. Note that the caller, handle_vmread, might need to use only
7022 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7023 * 64-bit fields are to be returned).
7025 static inline int vmcs12_read_any(struct kvm_vcpu
*vcpu
,
7026 unsigned long field
, u64
*ret
)
7028 short offset
= vmcs_field_to_offset(field
);
7034 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
7036 switch (vmcs_field_type(field
)) {
7037 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7038 *ret
= *((natural_width
*)p
);
7040 case VMCS_FIELD_TYPE_U16
:
7043 case VMCS_FIELD_TYPE_U32
:
7046 case VMCS_FIELD_TYPE_U64
:
7056 static inline int vmcs12_write_any(struct kvm_vcpu
*vcpu
,
7057 unsigned long field
, u64 field_value
){
7058 short offset
= vmcs_field_to_offset(field
);
7059 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
7063 switch (vmcs_field_type(field
)) {
7064 case VMCS_FIELD_TYPE_U16
:
7065 *(u16
*)p
= field_value
;
7067 case VMCS_FIELD_TYPE_U32
:
7068 *(u32
*)p
= field_value
;
7070 case VMCS_FIELD_TYPE_U64
:
7071 *(u64
*)p
= field_value
;
7073 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7074 *(natural_width
*)p
= field_value
;
7083 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
7086 unsigned long field
;
7088 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7089 const unsigned long *fields
= shadow_read_write_fields
;
7090 const int num_fields
= max_shadow_read_write_fields
;
7094 vmcs_load(shadow_vmcs
);
7096 for (i
= 0; i
< num_fields
; i
++) {
7098 switch (vmcs_field_type(field
)) {
7099 case VMCS_FIELD_TYPE_U16
:
7100 field_value
= vmcs_read16(field
);
7102 case VMCS_FIELD_TYPE_U32
:
7103 field_value
= vmcs_read32(field
);
7105 case VMCS_FIELD_TYPE_U64
:
7106 field_value
= vmcs_read64(field
);
7108 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7109 field_value
= vmcs_readl(field
);
7115 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
7118 vmcs_clear(shadow_vmcs
);
7119 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7124 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
7126 const unsigned long *fields
[] = {
7127 shadow_read_write_fields
,
7128 shadow_read_only_fields
7130 const int max_fields
[] = {
7131 max_shadow_read_write_fields
,
7132 max_shadow_read_only_fields
7135 unsigned long field
;
7136 u64 field_value
= 0;
7137 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
7139 vmcs_load(shadow_vmcs
);
7141 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
7142 for (i
= 0; i
< max_fields
[q
]; i
++) {
7143 field
= fields
[q
][i
];
7144 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
7146 switch (vmcs_field_type(field
)) {
7147 case VMCS_FIELD_TYPE_U16
:
7148 vmcs_write16(field
, (u16
)field_value
);
7150 case VMCS_FIELD_TYPE_U32
:
7151 vmcs_write32(field
, (u32
)field_value
);
7153 case VMCS_FIELD_TYPE_U64
:
7154 vmcs_write64(field
, (u64
)field_value
);
7156 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
7157 vmcs_writel(field
, (long)field_value
);
7166 vmcs_clear(shadow_vmcs
);
7167 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
7171 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7172 * used before) all generate the same failure when it is missing.
7174 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
7176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7177 if (vmx
->nested
.current_vmptr
== -1ull) {
7178 nested_vmx_failInvalid(vcpu
);
7179 skip_emulated_instruction(vcpu
);
7185 static int handle_vmread(struct kvm_vcpu
*vcpu
)
7187 unsigned long field
;
7189 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7190 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7193 if (!nested_vmx_check_permission(vcpu
) ||
7194 !nested_vmx_check_vmcs12(vcpu
))
7197 /* Decode instruction info and find the field to read */
7198 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7199 /* Read the field, zero-extended to a u64 field_value */
7200 if (vmcs12_read_any(vcpu
, field
, &field_value
) < 0) {
7201 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7202 skip_emulated_instruction(vcpu
);
7206 * Now copy part of this value to register or memory, as requested.
7207 * Note that the number of bits actually copied is 32 or 64 depending
7208 * on the guest's mode (32 or 64 bit), not on the given field's length.
7210 if (vmx_instruction_info
& (1u << 10)) {
7211 kvm_register_writel(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
7214 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7215 vmx_instruction_info
, true, &gva
))
7217 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7218 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
7219 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
7222 nested_vmx_succeed(vcpu
);
7223 skip_emulated_instruction(vcpu
);
7228 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
7230 unsigned long field
;
7232 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7233 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7234 /* The value to write might be 32 or 64 bits, depending on L1's long
7235 * mode, and eventually we need to write that into a field of several
7236 * possible lengths. The code below first zero-extends the value to 64
7237 * bit (field_value), and then copies only the approriate number of
7238 * bits into the vmcs12 field.
7240 u64 field_value
= 0;
7241 struct x86_exception e
;
7243 if (!nested_vmx_check_permission(vcpu
) ||
7244 !nested_vmx_check_vmcs12(vcpu
))
7247 if (vmx_instruction_info
& (1u << 10))
7248 field_value
= kvm_register_readl(vcpu
,
7249 (((vmx_instruction_info
) >> 3) & 0xf));
7251 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7252 vmx_instruction_info
, false, &gva
))
7254 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
7255 &field_value
, (is_64_bit_mode(vcpu
) ? 8 : 4), &e
)) {
7256 kvm_inject_page_fault(vcpu
, &e
);
7262 field
= kvm_register_readl(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
7263 if (vmcs_field_readonly(field
)) {
7264 nested_vmx_failValid(vcpu
,
7265 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
7266 skip_emulated_instruction(vcpu
);
7270 if (vmcs12_write_any(vcpu
, field
, field_value
) < 0) {
7271 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
7272 skip_emulated_instruction(vcpu
);
7276 nested_vmx_succeed(vcpu
);
7277 skip_emulated_instruction(vcpu
);
7281 /* Emulate the VMPTRLD instruction */
7282 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
7284 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7287 if (!nested_vmx_check_permission(vcpu
))
7290 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
7293 if (vmx
->nested
.current_vmptr
!= vmptr
) {
7294 struct vmcs12
*new_vmcs12
;
7296 page
= nested_get_page(vcpu
, vmptr
);
7298 nested_vmx_failInvalid(vcpu
);
7299 skip_emulated_instruction(vcpu
);
7302 new_vmcs12
= kmap(page
);
7303 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
7305 nested_release_page_clean(page
);
7306 nested_vmx_failValid(vcpu
,
7307 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
7308 skip_emulated_instruction(vcpu
);
7312 nested_release_vmcs12(vmx
);
7313 vmx
->nested
.current_vmptr
= vmptr
;
7314 vmx
->nested
.current_vmcs12
= new_vmcs12
;
7315 vmx
->nested
.current_vmcs12_page
= page
;
7316 if (enable_shadow_vmcs
) {
7317 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL
,
7318 SECONDARY_EXEC_SHADOW_VMCS
);
7319 vmcs_write64(VMCS_LINK_POINTER
,
7320 __pa(vmx
->nested
.current_shadow_vmcs
));
7321 vmx
->nested
.sync_shadow_vmcs
= true;
7325 nested_vmx_succeed(vcpu
);
7326 skip_emulated_instruction(vcpu
);
7330 /* Emulate the VMPTRST instruction */
7331 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
7333 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7334 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7336 struct x86_exception e
;
7338 if (!nested_vmx_check_permission(vcpu
))
7341 if (get_vmx_mem_address(vcpu
, exit_qualification
,
7342 vmx_instruction_info
, true, &vmcs_gva
))
7344 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7345 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
7346 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
7348 kvm_inject_page_fault(vcpu
, &e
);
7351 nested_vmx_succeed(vcpu
);
7352 skip_emulated_instruction(vcpu
);
7356 /* Emulate the INVEPT instruction */
7357 static int handle_invept(struct kvm_vcpu
*vcpu
)
7359 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7360 u32 vmx_instruction_info
, types
;
7363 struct x86_exception e
;
7368 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7369 SECONDARY_EXEC_ENABLE_EPT
) ||
7370 !(vmx
->nested
.nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
7371 kvm_queue_exception(vcpu
, UD_VECTOR
);
7375 if (!nested_vmx_check_permission(vcpu
))
7378 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
7379 kvm_queue_exception(vcpu
, UD_VECTOR
);
7383 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7384 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7386 types
= (vmx
->nested
.nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
7388 if (!(types
& (1UL << type
))) {
7389 nested_vmx_failValid(vcpu
,
7390 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7394 /* According to the Intel VMX instruction reference, the memory
7395 * operand is read even if it isn't needed (e.g., for type==global)
7397 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7398 vmx_instruction_info
, false, &gva
))
7400 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
7401 sizeof(operand
), &e
)) {
7402 kvm_inject_page_fault(vcpu
, &e
);
7407 case VMX_EPT_EXTENT_GLOBAL
:
7408 kvm_mmu_sync_roots(vcpu
);
7409 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
7410 nested_vmx_succeed(vcpu
);
7413 /* Trap single context invalidation invept calls */
7418 skip_emulated_instruction(vcpu
);
7422 static int handle_invvpid(struct kvm_vcpu
*vcpu
)
7424 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7425 u32 vmx_instruction_info
;
7426 unsigned long type
, types
;
7428 struct x86_exception e
;
7431 if (!(vmx
->nested
.nested_vmx_secondary_ctls_high
&
7432 SECONDARY_EXEC_ENABLE_VPID
) ||
7433 !(vmx
->nested
.nested_vmx_vpid_caps
& VMX_VPID_INVVPID_BIT
)) {
7434 kvm_queue_exception(vcpu
, UD_VECTOR
);
7438 if (!nested_vmx_check_permission(vcpu
))
7441 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
7442 type
= kvm_register_readl(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
7444 types
= (vmx
->nested
.nested_vmx_vpid_caps
>> 8) & 0x7;
7446 if (!(types
& (1UL << type
))) {
7447 nested_vmx_failValid(vcpu
,
7448 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
7452 /* according to the intel vmx instruction reference, the memory
7453 * operand is read even if it isn't needed (e.g., for type==global)
7455 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
7456 vmx_instruction_info
, false, &gva
))
7458 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vpid
,
7460 kvm_inject_page_fault(vcpu
, &e
);
7465 case VMX_VPID_EXTENT_ALL_CONTEXT
:
7466 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
7467 nested_vmx_succeed(vcpu
);
7470 /* Trap single context invalidation invvpid calls */
7475 skip_emulated_instruction(vcpu
);
7479 static int handle_pml_full(struct kvm_vcpu
*vcpu
)
7481 unsigned long exit_qualification
;
7483 trace_kvm_pml_full(vcpu
->vcpu_id
);
7485 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7488 * PML buffer FULL happened while executing iret from NMI,
7489 * "blocked by NMI" bit has to be set before next VM entry.
7491 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
7492 cpu_has_virtual_nmis() &&
7493 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
7494 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7495 GUEST_INTR_STATE_NMI
);
7498 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7499 * here.., and there's no userspace involvement needed for PML.
7504 static int handle_pcommit(struct kvm_vcpu
*vcpu
)
7506 /* we never catch pcommit instruct for L1 guest. */
7512 * The exit handlers return 1 if the exit was handled fully and guest execution
7513 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
7514 * to be done to userspace and return 0.
7516 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
7517 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
7518 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
7519 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
7520 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
7521 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
7522 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
7523 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
7524 [EXIT_REASON_CPUID
] = handle_cpuid
,
7525 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
7526 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
7527 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
7528 [EXIT_REASON_HLT
] = handle_halt
,
7529 [EXIT_REASON_INVD
] = handle_invd
,
7530 [EXIT_REASON_INVLPG
] = handle_invlpg
,
7531 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
7532 [EXIT_REASON_VMCALL
] = handle_vmcall
,
7533 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
7534 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
7535 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
7536 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
7537 [EXIT_REASON_VMREAD
] = handle_vmread
,
7538 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
7539 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
7540 [EXIT_REASON_VMOFF
] = handle_vmoff
,
7541 [EXIT_REASON_VMON
] = handle_vmon
,
7542 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
7543 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
7544 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
7545 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
7546 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
7547 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
7548 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
7549 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
7550 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
7551 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
7552 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
7553 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
7554 [EXIT_REASON_MONITOR_TRAP_FLAG
] = handle_monitor_trap
,
7555 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
7556 [EXIT_REASON_INVEPT
] = handle_invept
,
7557 [EXIT_REASON_INVVPID
] = handle_invvpid
,
7558 [EXIT_REASON_XSAVES
] = handle_xsaves
,
7559 [EXIT_REASON_XRSTORS
] = handle_xrstors
,
7560 [EXIT_REASON_PML_FULL
] = handle_pml_full
,
7561 [EXIT_REASON_PCOMMIT
] = handle_pcommit
,
7564 static const int kvm_vmx_max_exit_handlers
=
7565 ARRAY_SIZE(kvm_vmx_exit_handlers
);
7567 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
7568 struct vmcs12
*vmcs12
)
7570 unsigned long exit_qualification
;
7571 gpa_t bitmap
, last_bitmap
;
7576 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
7577 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
7579 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7581 port
= exit_qualification
>> 16;
7582 size
= (exit_qualification
& 7) + 1;
7584 last_bitmap
= (gpa_t
)-1;
7589 bitmap
= vmcs12
->io_bitmap_a
;
7590 else if (port
< 0x10000)
7591 bitmap
= vmcs12
->io_bitmap_b
;
7594 bitmap
+= (port
& 0x7fff) / 8;
7596 if (last_bitmap
!= bitmap
)
7597 if (kvm_vcpu_read_guest(vcpu
, bitmap
, &b
, 1))
7599 if (b
& (1 << (port
& 7)))
7604 last_bitmap
= bitmap
;
7611 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7612 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7613 * disinterest in the current event (read or write a specific MSR) by using an
7614 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7616 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
7617 struct vmcs12
*vmcs12
, u32 exit_reason
)
7619 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
7622 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
7626 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7627 * for the four combinations of read/write and low/high MSR numbers.
7628 * First we need to figure out which of the four to use:
7630 bitmap
= vmcs12
->msr_bitmap
;
7631 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
7633 if (msr_index
>= 0xc0000000) {
7634 msr_index
-= 0xc0000000;
7638 /* Then read the msr_index'th bit from this bitmap: */
7639 if (msr_index
< 1024*8) {
7641 if (kvm_vcpu_read_guest(vcpu
, bitmap
+ msr_index
/8, &b
, 1))
7643 return 1 & (b
>> (msr_index
& 7));
7645 return true; /* let L1 handle the wrong parameter */
7649 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7650 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7651 * intercept (via guest_host_mask etc.) the current event.
7653 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
7654 struct vmcs12
*vmcs12
)
7656 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
7657 int cr
= exit_qualification
& 15;
7658 int reg
= (exit_qualification
>> 8) & 15;
7659 unsigned long val
= kvm_register_readl(vcpu
, reg
);
7661 switch ((exit_qualification
>> 4) & 3) {
7662 case 0: /* mov to cr */
7665 if (vmcs12
->cr0_guest_host_mask
&
7666 (val
^ vmcs12
->cr0_read_shadow
))
7670 if ((vmcs12
->cr3_target_count
>= 1 &&
7671 vmcs12
->cr3_target_value0
== val
) ||
7672 (vmcs12
->cr3_target_count
>= 2 &&
7673 vmcs12
->cr3_target_value1
== val
) ||
7674 (vmcs12
->cr3_target_count
>= 3 &&
7675 vmcs12
->cr3_target_value2
== val
) ||
7676 (vmcs12
->cr3_target_count
>= 4 &&
7677 vmcs12
->cr3_target_value3
== val
))
7679 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
7683 if (vmcs12
->cr4_guest_host_mask
&
7684 (vmcs12
->cr4_read_shadow
^ val
))
7688 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
7694 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
7695 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
7698 case 1: /* mov from cr */
7701 if (vmcs12
->cpu_based_vm_exec_control
&
7702 CPU_BASED_CR3_STORE_EXITING
)
7706 if (vmcs12
->cpu_based_vm_exec_control
&
7707 CPU_BASED_CR8_STORE_EXITING
)
7714 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7715 * cr0. Other attempted changes are ignored, with no exit.
7717 if (vmcs12
->cr0_guest_host_mask
& 0xe &
7718 (val
^ vmcs12
->cr0_read_shadow
))
7720 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
7721 !(vmcs12
->cr0_read_shadow
& 0x1) &&
7730 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7731 * should handle it ourselves in L0 (and then continue L2). Only call this
7732 * when in is_guest_mode (L2).
7734 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
7736 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7737 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7738 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7739 u32 exit_reason
= vmx
->exit_reason
;
7741 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
7742 vmcs_readl(EXIT_QUALIFICATION
),
7743 vmx
->idt_vectoring_info
,
7745 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
7748 if (vmx
->nested
.nested_run_pending
)
7751 if (unlikely(vmx
->fail
)) {
7752 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
7753 vmcs_read32(VM_INSTRUCTION_ERROR
));
7757 switch (exit_reason
) {
7758 case EXIT_REASON_EXCEPTION_NMI
:
7759 if (!is_exception(intr_info
))
7761 else if (is_page_fault(intr_info
))
7763 else if (is_no_device(intr_info
) &&
7764 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
7766 else if (is_debug(intr_info
) &&
7768 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
7770 else if (is_breakpoint(intr_info
) &&
7771 vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
7773 return vmcs12
->exception_bitmap
&
7774 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
7775 case EXIT_REASON_EXTERNAL_INTERRUPT
:
7777 case EXIT_REASON_TRIPLE_FAULT
:
7779 case EXIT_REASON_PENDING_INTERRUPT
:
7780 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
7781 case EXIT_REASON_NMI_WINDOW
:
7782 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
7783 case EXIT_REASON_TASK_SWITCH
:
7785 case EXIT_REASON_CPUID
:
7786 if (kvm_register_read(vcpu
, VCPU_REGS_RAX
) == 0xa)
7789 case EXIT_REASON_HLT
:
7790 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
7791 case EXIT_REASON_INVD
:
7793 case EXIT_REASON_INVLPG
:
7794 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
7795 case EXIT_REASON_RDPMC
:
7796 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
7797 case EXIT_REASON_RDTSC
: case EXIT_REASON_RDTSCP
:
7798 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
7799 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
7800 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
7801 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
7802 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
7803 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
7804 case EXIT_REASON_INVEPT
: case EXIT_REASON_INVVPID
:
7806 * VMX instructions trap unconditionally. This allows L1 to
7807 * emulate them for its L2 guest, i.e., allows 3-level nesting!
7810 case EXIT_REASON_CR_ACCESS
:
7811 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
7812 case EXIT_REASON_DR_ACCESS
:
7813 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
7814 case EXIT_REASON_IO_INSTRUCTION
:
7815 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
7816 case EXIT_REASON_MSR_READ
:
7817 case EXIT_REASON_MSR_WRITE
:
7818 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
7819 case EXIT_REASON_INVALID_STATE
:
7821 case EXIT_REASON_MWAIT_INSTRUCTION
:
7822 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
7823 case EXIT_REASON_MONITOR_TRAP_FLAG
:
7824 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_TRAP_FLAG
);
7825 case EXIT_REASON_MONITOR_INSTRUCTION
:
7826 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
7827 case EXIT_REASON_PAUSE_INSTRUCTION
:
7828 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
7829 nested_cpu_has2(vmcs12
,
7830 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
7831 case EXIT_REASON_MCE_DURING_VMENTRY
:
7833 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
7834 return nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
);
7835 case EXIT_REASON_APIC_ACCESS
:
7836 return nested_cpu_has2(vmcs12
,
7837 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
7838 case EXIT_REASON_APIC_WRITE
:
7839 case EXIT_REASON_EOI_INDUCED
:
7840 /* apic_write and eoi_induced should exit unconditionally. */
7842 case EXIT_REASON_EPT_VIOLATION
:
7844 * L0 always deals with the EPT violation. If nested EPT is
7845 * used, and the nested mmu code discovers that the address is
7846 * missing in the guest EPT table (EPT12), the EPT violation
7847 * will be injected with nested_ept_inject_page_fault()
7850 case EXIT_REASON_EPT_MISCONFIG
:
7852 * L2 never uses directly L1's EPT, but rather L0's own EPT
7853 * table (shadow on EPT) or a merged EPT table that L0 built
7854 * (EPT on EPT). So any problems with the structure of the
7855 * table is L0's fault.
7858 case EXIT_REASON_WBINVD
:
7859 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
7860 case EXIT_REASON_XSETBV
:
7862 case EXIT_REASON_XSAVES
: case EXIT_REASON_XRSTORS
:
7864 * This should never happen, since it is not possible to
7865 * set XSS to a non-zero value---neither in L1 nor in L2.
7866 * If if it were, XSS would have to be checked against
7867 * the XSS exit bitmap in vmcs12.
7869 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_XSAVES
);
7870 case EXIT_REASON_PCOMMIT
:
7871 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_PCOMMIT
);
7877 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
7879 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
7880 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
7883 static int vmx_create_pml_buffer(struct vcpu_vmx
*vmx
)
7885 struct page
*pml_pg
;
7887 pml_pg
= alloc_page(GFP_KERNEL
| __GFP_ZERO
);
7891 vmx
->pml_pg
= pml_pg
;
7893 vmcs_write64(PML_ADDRESS
, page_to_phys(vmx
->pml_pg
));
7894 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7899 static void vmx_destroy_pml_buffer(struct vcpu_vmx
*vmx
)
7902 __free_page(vmx
->pml_pg
);
7907 static void vmx_flush_pml_buffer(struct kvm_vcpu
*vcpu
)
7909 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7913 pml_idx
= vmcs_read16(GUEST_PML_INDEX
);
7915 /* Do nothing if PML buffer is empty */
7916 if (pml_idx
== (PML_ENTITY_NUM
- 1))
7919 /* PML index always points to next available PML buffer entity */
7920 if (pml_idx
>= PML_ENTITY_NUM
)
7925 pml_buf
= page_address(vmx
->pml_pg
);
7926 for (; pml_idx
< PML_ENTITY_NUM
; pml_idx
++) {
7929 gpa
= pml_buf
[pml_idx
];
7930 WARN_ON(gpa
& (PAGE_SIZE
- 1));
7931 kvm_vcpu_mark_page_dirty(vcpu
, gpa
>> PAGE_SHIFT
);
7934 /* reset PML index */
7935 vmcs_write16(GUEST_PML_INDEX
, PML_ENTITY_NUM
- 1);
7939 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7940 * Called before reporting dirty_bitmap to userspace.
7942 static void kvm_flush_pml_buffers(struct kvm
*kvm
)
7945 struct kvm_vcpu
*vcpu
;
7947 * We only need to kick vcpu out of guest mode here, as PML buffer
7948 * is flushed at beginning of all VMEXITs, and it's obvious that only
7949 * vcpus running in guest are possible to have unflushed GPAs in PML
7952 kvm_for_each_vcpu(i
, vcpu
, kvm
)
7953 kvm_vcpu_kick(vcpu
);
7956 static void vmx_dump_sel(char *name
, uint32_t sel
)
7958 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7959 name
, vmcs_read32(sel
),
7960 vmcs_read32(sel
+ GUEST_ES_AR_BYTES
- GUEST_ES_SELECTOR
),
7961 vmcs_read32(sel
+ GUEST_ES_LIMIT
- GUEST_ES_SELECTOR
),
7962 vmcs_readl(sel
+ GUEST_ES_BASE
- GUEST_ES_SELECTOR
));
7965 static void vmx_dump_dtsel(char *name
, uint32_t limit
)
7967 pr_err("%s limit=0x%08x, base=0x%016lx\n",
7968 name
, vmcs_read32(limit
),
7969 vmcs_readl(limit
+ GUEST_GDTR_BASE
- GUEST_GDTR_LIMIT
));
7972 static void dump_vmcs(void)
7974 u32 vmentry_ctl
= vmcs_read32(VM_ENTRY_CONTROLS
);
7975 u32 vmexit_ctl
= vmcs_read32(VM_EXIT_CONTROLS
);
7976 u32 cpu_based_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
7977 u32 pin_based_exec_ctrl
= vmcs_read32(PIN_BASED_VM_EXEC_CONTROL
);
7978 u32 secondary_exec_control
= 0;
7979 unsigned long cr4
= vmcs_readl(GUEST_CR4
);
7980 u64 efer
= vmcs_read64(GUEST_IA32_EFER
);
7983 if (cpu_has_secondary_exec_ctrls())
7984 secondary_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7986 pr_err("*** Guest State ***\n");
7987 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7988 vmcs_readl(GUEST_CR0
), vmcs_readl(CR0_READ_SHADOW
),
7989 vmcs_readl(CR0_GUEST_HOST_MASK
));
7990 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7991 cr4
, vmcs_readl(CR4_READ_SHADOW
), vmcs_readl(CR4_GUEST_HOST_MASK
));
7992 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3
));
7993 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) &&
7994 (cr4
& X86_CR4_PAE
) && !(efer
& EFER_LMA
))
7996 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
7997 vmcs_read64(GUEST_PDPTR0
), vmcs_read64(GUEST_PDPTR1
));
7998 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
7999 vmcs_read64(GUEST_PDPTR2
), vmcs_read64(GUEST_PDPTR3
));
8001 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
8002 vmcs_readl(GUEST_RSP
), vmcs_readl(GUEST_RIP
));
8003 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
8004 vmcs_readl(GUEST_RFLAGS
), vmcs_readl(GUEST_DR7
));
8005 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8006 vmcs_readl(GUEST_SYSENTER_ESP
),
8007 vmcs_read32(GUEST_SYSENTER_CS
), vmcs_readl(GUEST_SYSENTER_EIP
));
8008 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR
);
8009 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR
);
8010 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR
);
8011 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR
);
8012 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR
);
8013 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR
);
8014 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT
);
8015 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR
);
8016 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT
);
8017 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR
);
8018 if ((vmexit_ctl
& (VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_SAVE_IA32_EFER
)) ||
8019 (vmentry_ctl
& (VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_IA32_EFER
)))
8020 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8021 efer
, vmcs_read64(GUEST_IA32_PAT
));
8022 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
8023 vmcs_read64(GUEST_IA32_DEBUGCTL
),
8024 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
));
8025 if (vmentry_ctl
& VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
8026 pr_err("PerfGlobCtl = 0x%016llx\n",
8027 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL
));
8028 if (vmentry_ctl
& VM_ENTRY_LOAD_BNDCFGS
)
8029 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS
));
8030 pr_err("Interruptibility = %08x ActivityState = %08x\n",
8031 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
),
8032 vmcs_read32(GUEST_ACTIVITY_STATE
));
8033 if (secondary_exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
)
8034 pr_err("InterruptStatus = %04x\n",
8035 vmcs_read16(GUEST_INTR_STATUS
));
8037 pr_err("*** Host State ***\n");
8038 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
8039 vmcs_readl(HOST_RIP
), vmcs_readl(HOST_RSP
));
8040 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8041 vmcs_read16(HOST_CS_SELECTOR
), vmcs_read16(HOST_SS_SELECTOR
),
8042 vmcs_read16(HOST_DS_SELECTOR
), vmcs_read16(HOST_ES_SELECTOR
),
8043 vmcs_read16(HOST_FS_SELECTOR
), vmcs_read16(HOST_GS_SELECTOR
),
8044 vmcs_read16(HOST_TR_SELECTOR
));
8045 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8046 vmcs_readl(HOST_FS_BASE
), vmcs_readl(HOST_GS_BASE
),
8047 vmcs_readl(HOST_TR_BASE
));
8048 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8049 vmcs_readl(HOST_GDTR_BASE
), vmcs_readl(HOST_IDTR_BASE
));
8050 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8051 vmcs_readl(HOST_CR0
), vmcs_readl(HOST_CR3
),
8052 vmcs_readl(HOST_CR4
));
8053 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8054 vmcs_readl(HOST_IA32_SYSENTER_ESP
),
8055 vmcs_read32(HOST_IA32_SYSENTER_CS
),
8056 vmcs_readl(HOST_IA32_SYSENTER_EIP
));
8057 if (vmexit_ctl
& (VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_LOAD_IA32_EFER
))
8058 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
8059 vmcs_read64(HOST_IA32_EFER
),
8060 vmcs_read64(HOST_IA32_PAT
));
8061 if (vmexit_ctl
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8062 pr_err("PerfGlobCtl = 0x%016llx\n",
8063 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL
));
8065 pr_err("*** Control State ***\n");
8066 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8067 pin_based_exec_ctrl
, cpu_based_exec_ctrl
, secondary_exec_control
);
8068 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl
, vmexit_ctl
);
8069 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8070 vmcs_read32(EXCEPTION_BITMAP
),
8071 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK
),
8072 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH
));
8073 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8074 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8075 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE
),
8076 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN
));
8077 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8078 vmcs_read32(VM_EXIT_INTR_INFO
),
8079 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
8080 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
));
8081 pr_err(" reason=%08x qualification=%016lx\n",
8082 vmcs_read32(VM_EXIT_REASON
), vmcs_readl(EXIT_QUALIFICATION
));
8083 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8084 vmcs_read32(IDT_VECTORING_INFO_FIELD
),
8085 vmcs_read32(IDT_VECTORING_ERROR_CODE
));
8086 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET
));
8087 if (secondary_exec_control
& SECONDARY_EXEC_TSC_SCALING
)
8088 pr_err("TSC Multiplier = 0x%016llx\n",
8089 vmcs_read64(TSC_MULTIPLIER
));
8090 if (cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
)
8091 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD
));
8092 if (pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
)
8093 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV
));
8094 if ((secondary_exec_control
& SECONDARY_EXEC_ENABLE_EPT
))
8095 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER
));
8096 n
= vmcs_read32(CR3_TARGET_COUNT
);
8097 for (i
= 0; i
+ 1 < n
; i
+= 4)
8098 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8099 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2),
8100 i
+ 1, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2 + 2));
8102 pr_err("CR3 target%u=%016lx\n",
8103 i
, vmcs_readl(CR3_TARGET_VALUE0
+ i
* 2));
8104 if (secondary_exec_control
& SECONDARY_EXEC_PAUSE_LOOP_EXITING
)
8105 pr_err("PLE Gap=%08x Window=%08x\n",
8106 vmcs_read32(PLE_GAP
), vmcs_read32(PLE_WINDOW
));
8107 if (secondary_exec_control
& SECONDARY_EXEC_ENABLE_VPID
)
8108 pr_err("Virtual processor ID = 0x%04x\n",
8109 vmcs_read16(VIRTUAL_PROCESSOR_ID
));
8113 * The guest has exited. See if we can fix it or if we need userspace
8116 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
8118 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8119 u32 exit_reason
= vmx
->exit_reason
;
8120 u32 vectoring_info
= vmx
->idt_vectoring_info
;
8122 trace_kvm_exit(exit_reason
, vcpu
, KVM_ISA_VMX
);
8125 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8126 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8127 * querying dirty_bitmap, we only need to kick all vcpus out of guest
8128 * mode as if vcpus is in root mode, the PML buffer must has been
8132 vmx_flush_pml_buffer(vcpu
);
8134 /* If guest state is invalid, start emulating */
8135 if (vmx
->emulation_required
)
8136 return handle_invalid_guest_state(vcpu
);
8138 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
8139 nested_vmx_vmexit(vcpu
, exit_reason
,
8140 vmcs_read32(VM_EXIT_INTR_INFO
),
8141 vmcs_readl(EXIT_QUALIFICATION
));
8145 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
8147 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8148 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8153 if (unlikely(vmx
->fail
)) {
8154 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
8155 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
8156 = vmcs_read32(VM_INSTRUCTION_ERROR
);
8162 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8163 * delivery event since it indicates guest is accessing MMIO.
8164 * The vm-exit can be triggered again after return to guest that
8165 * will cause infinite loop.
8167 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
8168 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
8169 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
8170 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
8171 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
8172 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
8173 vcpu
->run
->internal
.ndata
= 2;
8174 vcpu
->run
->internal
.data
[0] = vectoring_info
;
8175 vcpu
->run
->internal
.data
[1] = exit_reason
;
8179 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
8180 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
8181 get_vmcs12(vcpu
))))) {
8182 if (vmx_interrupt_allowed(vcpu
)) {
8183 vmx
->soft_vnmi_blocked
= 0;
8184 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
8185 vcpu
->arch
.nmi_pending
) {
8187 * This CPU don't support us in finding the end of an
8188 * NMI-blocked window if the guest runs with IRQs
8189 * disabled. So we pull the trigger after 1 s of
8190 * futile waiting, but inform the user about this.
8192 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
8193 "state on VCPU %d after 1 s timeout\n",
8194 __func__
, vcpu
->vcpu_id
);
8195 vmx
->soft_vnmi_blocked
= 0;
8199 if (exit_reason
< kvm_vmx_max_exit_handlers
8200 && kvm_vmx_exit_handlers
[exit_reason
])
8201 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
8203 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason
);
8204 kvm_queue_exception(vcpu
, UD_VECTOR
);
8209 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
8211 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8213 if (is_guest_mode(vcpu
) &&
8214 nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
8217 if (irr
== -1 || tpr
< irr
) {
8218 vmcs_write32(TPR_THRESHOLD
, 0);
8222 vmcs_write32(TPR_THRESHOLD
, irr
);
8225 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
8227 u32 sec_exec_control
;
8230 * There is not point to enable virtualize x2apic without enable
8233 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8234 !kvm_vcpu_apicv_active(vcpu
))
8237 if (!cpu_need_tpr_shadow(vcpu
))
8240 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8243 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8244 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8246 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
8247 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8249 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
8251 vmx_set_msr_bitmap(vcpu
);
8254 static void vmx_set_apic_access_page_addr(struct kvm_vcpu
*vcpu
, hpa_t hpa
)
8256 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8259 * Currently we do not handle the nested case where L2 has an
8260 * APIC access page of its own; that page is still pinned.
8261 * Hence, we skip the case where the VCPU is in guest mode _and_
8262 * L1 prepared an APIC access page for L2.
8264 * For the case where L1 and L2 share the same APIC access page
8265 * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8266 * in the vmcs12), this function will only update either the vmcs01
8267 * or the vmcs02. If the former, the vmcs02 will be updated by
8268 * prepare_vmcs02. If the latter, the vmcs01 will be updated in
8269 * the next L2->L1 exit.
8271 if (!is_guest_mode(vcpu
) ||
8272 !nested_cpu_has2(vmx
->nested
.current_vmcs12
,
8273 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
8274 vmcs_write64(APIC_ACCESS_ADDR
, hpa
);
8277 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
8285 status
= vmcs_read16(GUEST_INTR_STATUS
);
8290 vmcs_write16(GUEST_INTR_STATUS
, status
);
8294 static void vmx_set_rvi(int vector
)
8302 status
= vmcs_read16(GUEST_INTR_STATUS
);
8303 old
= (u8
)status
& 0xff;
8304 if ((u8
)vector
!= old
) {
8306 status
|= (u8
)vector
;
8307 vmcs_write16(GUEST_INTR_STATUS
, status
);
8311 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
8313 if (!is_guest_mode(vcpu
)) {
8314 vmx_set_rvi(max_irr
);
8322 * In guest mode. If a vmexit is needed, vmx_check_nested_events
8325 if (nested_exit_on_intr(vcpu
))
8329 * Else, fall back to pre-APICv interrupt injection since L2
8330 * is run without virtual interrupt delivery.
8332 if (!kvm_event_needs_reinjection(vcpu
) &&
8333 vmx_interrupt_allowed(vcpu
)) {
8334 kvm_queue_interrupt(vcpu
, max_irr
, false);
8335 vmx_inject_irq(vcpu
);
8339 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
8341 if (!kvm_vcpu_apicv_active(vcpu
))
8344 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
8345 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
8346 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
8347 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
8350 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
8354 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
8355 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
8358 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8359 exit_intr_info
= vmx
->exit_intr_info
;
8361 /* Handle machine checks before interrupts are enabled */
8362 if (is_machine_check(exit_intr_info
))
8363 kvm_machine_check();
8365 /* We need to handle NMIs before interrupts are enabled */
8366 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
8367 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
8368 kvm_before_handle_nmi(&vmx
->vcpu
);
8370 kvm_after_handle_nmi(&vmx
->vcpu
);
8374 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
8376 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8379 * If external interrupt exists, IF bit is set in rflags/eflags on the
8380 * interrupt stack frame, and interrupt will be enabled on a return
8381 * from interrupt handler.
8383 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
8384 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
8385 unsigned int vector
;
8386 unsigned long entry
;
8388 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8389 #ifdef CONFIG_X86_64
8393 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8394 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
8395 entry
= gate_offset(*desc
);
8397 #ifdef CONFIG_X86_64
8398 "mov %%" _ASM_SP
", %[sp]\n\t"
8399 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
8404 "orl $0x200, (%%" _ASM_SP
")\n\t"
8405 __ASM_SIZE(push
) " $%c[cs]\n\t"
8406 "call *%[entry]\n\t"
8408 #ifdef CONFIG_X86_64
8413 [ss
]"i"(__KERNEL_DS
),
8414 [cs
]"i"(__KERNEL_CS
)
8420 static bool vmx_has_high_real_mode_segbase(void)
8422 return enable_unrestricted_guest
|| emulate_invalid_guest_state
;
8425 static bool vmx_mpx_supported(void)
8427 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
8428 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
8431 static bool vmx_xsaves_supported(void)
8433 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
8434 SECONDARY_EXEC_XSAVES
;
8437 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
8442 bool idtv_info_valid
;
8444 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8446 if (cpu_has_virtual_nmis()) {
8447 if (vmx
->nmi_known_unmasked
)
8450 * Can't use vmx->exit_intr_info since we're not sure what
8451 * the exit reason is.
8453 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
8454 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
8455 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
8457 * SDM 3: 27.7.1.2 (September 2008)
8458 * Re-set bit "block by NMI" before VM entry if vmexit caused by
8459 * a guest IRET fault.
8460 * SDM 3: 23.2.2 (September 2008)
8461 * Bit 12 is undefined in any of the following cases:
8462 * If the VM exit sets the valid bit in the IDT-vectoring
8463 * information field.
8464 * If the VM exit is due to a double fault.
8466 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
8467 vector
!= DF_VECTOR
&& !idtv_info_valid
)
8468 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
8469 GUEST_INTR_STATE_NMI
);
8471 vmx
->nmi_known_unmasked
=
8472 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
8473 & GUEST_INTR_STATE_NMI
);
8474 } else if (unlikely(vmx
->soft_vnmi_blocked
))
8475 vmx
->vnmi_blocked_time
+=
8476 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
8479 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
8480 u32 idt_vectoring_info
,
8481 int instr_len_field
,
8482 int error_code_field
)
8486 bool idtv_info_valid
;
8488 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
8490 vcpu
->arch
.nmi_injected
= false;
8491 kvm_clear_exception_queue(vcpu
);
8492 kvm_clear_interrupt_queue(vcpu
);
8494 if (!idtv_info_valid
)
8497 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8499 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
8500 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
8503 case INTR_TYPE_NMI_INTR
:
8504 vcpu
->arch
.nmi_injected
= true;
8506 * SDM 3: 27.7.1.2 (September 2008)
8507 * Clear bit "block by NMI" before VM entry if a NMI
8510 vmx_set_nmi_mask(vcpu
, false);
8512 case INTR_TYPE_SOFT_EXCEPTION
:
8513 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8515 case INTR_TYPE_HARD_EXCEPTION
:
8516 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
8517 u32 err
= vmcs_read32(error_code_field
);
8518 kvm_requeue_exception_e(vcpu
, vector
, err
);
8520 kvm_requeue_exception(vcpu
, vector
);
8522 case INTR_TYPE_SOFT_INTR
:
8523 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
8525 case INTR_TYPE_EXT_INTR
:
8526 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
8533 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
8535 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
8536 VM_EXIT_INSTRUCTION_LEN
,
8537 IDT_VECTORING_ERROR_CODE
);
8540 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
8542 __vmx_complete_interrupts(vcpu
,
8543 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
8544 VM_ENTRY_INSTRUCTION_LEN
,
8545 VM_ENTRY_EXCEPTION_ERROR_CODE
);
8547 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
8550 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
8553 struct perf_guest_switch_msr
*msrs
;
8555 msrs
= perf_guest_get_msrs(&nr_msrs
);
8560 for (i
= 0; i
< nr_msrs
; i
++)
8561 if (msrs
[i
].host
== msrs
[i
].guest
)
8562 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
8564 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
8568 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
8570 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8571 unsigned long debugctlmsr
, cr4
;
8573 /* Record the guest's net vcpu time for enforced NMI injections. */
8574 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
8575 vmx
->entry_time
= ktime_get();
8577 /* Don't enter VMX if guest state is invalid, let the exit handler
8578 start emulation until we arrive back to a valid state */
8579 if (vmx
->emulation_required
)
8582 if (vmx
->ple_window_dirty
) {
8583 vmx
->ple_window_dirty
= false;
8584 vmcs_write32(PLE_WINDOW
, vmx
->ple_window
);
8587 if (vmx
->nested
.sync_shadow_vmcs
) {
8588 copy_vmcs12_to_shadow(vmx
);
8589 vmx
->nested
.sync_shadow_vmcs
= false;
8592 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8593 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
8594 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
8595 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
8597 cr4
= cr4_read_shadow();
8598 if (unlikely(cr4
!= vmx
->host_state
.vmcs_host_cr4
)) {
8599 vmcs_writel(HOST_CR4
, cr4
);
8600 vmx
->host_state
.vmcs_host_cr4
= cr4
;
8603 /* When single-stepping over STI and MOV SS, we must clear the
8604 * corresponding interruptibility bits in the guest state. Otherwise
8605 * vmentry fails as it then expects bit 14 (BS) in pending debug
8606 * exceptions being set, but that's not correct for the guest debugging
8608 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
8609 vmx_set_interrupt_shadow(vcpu
, 0);
8611 atomic_switch_perf_msrs(vmx
);
8612 debugctlmsr
= get_debugctlmsr();
8614 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
8616 /* Store host registers */
8617 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
8618 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
8619 "push %%" _ASM_CX
" \n\t"
8620 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8622 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
8623 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
8625 /* Reload cr2 if changed */
8626 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
8627 "mov %%cr2, %%" _ASM_DX
" \n\t"
8628 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
8630 "mov %%" _ASM_AX
", %%cr2 \n\t"
8632 /* Check if vmlaunch of vmresume is needed */
8633 "cmpl $0, %c[launched](%0) \n\t"
8634 /* Load guest registers. Don't clobber flags. */
8635 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
8636 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
8637 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
8638 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
8639 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
8640 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
8641 #ifdef CONFIG_X86_64
8642 "mov %c[r8](%0), %%r8 \n\t"
8643 "mov %c[r9](%0), %%r9 \n\t"
8644 "mov %c[r10](%0), %%r10 \n\t"
8645 "mov %c[r11](%0), %%r11 \n\t"
8646 "mov %c[r12](%0), %%r12 \n\t"
8647 "mov %c[r13](%0), %%r13 \n\t"
8648 "mov %c[r14](%0), %%r14 \n\t"
8649 "mov %c[r15](%0), %%r15 \n\t"
8651 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
8653 /* Enter guest mode */
8655 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
8657 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
8659 /* Save guest registers, load host registers, keep flags */
8660 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
8662 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
8663 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
8664 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
8665 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
8666 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
8667 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
8668 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
8669 #ifdef CONFIG_X86_64
8670 "mov %%r8, %c[r8](%0) \n\t"
8671 "mov %%r9, %c[r9](%0) \n\t"
8672 "mov %%r10, %c[r10](%0) \n\t"
8673 "mov %%r11, %c[r11](%0) \n\t"
8674 "mov %%r12, %c[r12](%0) \n\t"
8675 "mov %%r13, %c[r13](%0) \n\t"
8676 "mov %%r14, %c[r14](%0) \n\t"
8677 "mov %%r15, %c[r15](%0) \n\t"
8679 "mov %%cr2, %%" _ASM_AX
" \n\t"
8680 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
8682 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
8683 "setbe %c[fail](%0) \n\t"
8684 ".pushsection .rodata \n\t"
8685 ".global vmx_return \n\t"
8686 "vmx_return: " _ASM_PTR
" 2b \n\t"
8688 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
8689 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
8690 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
8691 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
8692 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
8693 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
8694 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
8695 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
8696 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
8697 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
8698 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
8699 #ifdef CONFIG_X86_64
8700 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
8701 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
8702 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
8703 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
8704 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
8705 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
8706 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
8707 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
8709 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
8710 [wordsize
]"i"(sizeof(ulong
))
8712 #ifdef CONFIG_X86_64
8713 , "rax", "rbx", "rdi", "rsi"
8714 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8716 , "eax", "ebx", "edi", "esi"
8720 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8722 update_debugctlmsr(debugctlmsr
);
8724 #ifndef CONFIG_X86_64
8726 * The sysexit path does not restore ds/es, so we must set them to
8727 * a reasonable value ourselves.
8729 * We can't defer this to vmx_load_host_state() since that function
8730 * may be executed in interrupt context, which saves and restore segments
8731 * around it, nullifying its effect.
8733 loadsegment(ds
, __USER_DS
);
8734 loadsegment(es
, __USER_DS
);
8737 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
8738 | (1 << VCPU_EXREG_RFLAGS
)
8739 | (1 << VCPU_EXREG_PDPTR
)
8740 | (1 << VCPU_EXREG_SEGMENTS
)
8741 | (1 << VCPU_EXREG_CR3
));
8742 vcpu
->arch
.regs_dirty
= 0;
8744 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
8746 vmx
->loaded_vmcs
->launched
= 1;
8748 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
8751 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8752 * we did not inject a still-pending event to L1 now because of
8753 * nested_run_pending, we need to re-enable this bit.
8755 if (vmx
->nested
.nested_run_pending
)
8756 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
8758 vmx
->nested
.nested_run_pending
= 0;
8760 vmx_complete_atomic_exit(vmx
);
8761 vmx_recover_nmi_blocking(vmx
);
8762 vmx_complete_interrupts(vmx
);
8765 static void vmx_load_vmcs01(struct kvm_vcpu
*vcpu
)
8767 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8770 if (vmx
->loaded_vmcs
== &vmx
->vmcs01
)
8774 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8776 vmx_vcpu_load(vcpu
, cpu
);
8781 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
8783 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8786 vmx_destroy_pml_buffer(vmx
);
8787 free_vpid(vmx
->vpid
);
8788 leave_guest_mode(vcpu
);
8789 vmx_load_vmcs01(vcpu
);
8791 free_loaded_vmcs(vmx
->loaded_vmcs
);
8792 kfree(vmx
->guest_msrs
);
8793 kvm_vcpu_uninit(vcpu
);
8794 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8797 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
8800 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
8804 return ERR_PTR(-ENOMEM
);
8806 vmx
->vpid
= allocate_vpid();
8808 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
8812 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
8813 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index
) * sizeof(vmx
->guest_msrs
[0])
8817 if (!vmx
->guest_msrs
) {
8821 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8822 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
8823 if (!vmx
->loaded_vmcs
->vmcs
)
8826 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
8827 loaded_vmcs_init(vmx
->loaded_vmcs
);
8832 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
8833 vmx
->vcpu
.cpu
= cpu
;
8834 err
= vmx_vcpu_setup(vmx
);
8835 vmx_vcpu_put(&vmx
->vcpu
);
8839 if (cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
8840 err
= alloc_apic_access_page(kvm
);
8846 if (!kvm
->arch
.ept_identity_map_addr
)
8847 kvm
->arch
.ept_identity_map_addr
=
8848 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
8849 err
= init_rmode_identity_map(kvm
);
8855 nested_vmx_setup_ctls_msrs(vmx
);
8856 vmx
->nested
.vpid02
= allocate_vpid();
8859 vmx
->nested
.posted_intr_nv
= -1;
8860 vmx
->nested
.current_vmptr
= -1ull;
8861 vmx
->nested
.current_vmcs12
= NULL
;
8864 * If PML is turned on, failure on enabling PML just results in failure
8865 * of creating the vcpu, therefore we can simplify PML logic (by
8866 * avoiding dealing with cases, such as enabling PML partially on vcpus
8867 * for the guest, etc.
8870 err
= vmx_create_pml_buffer(vmx
);
8878 free_vpid(vmx
->nested
.vpid02
);
8879 free_loaded_vmcs(vmx
->loaded_vmcs
);
8881 kfree(vmx
->guest_msrs
);
8883 kvm_vcpu_uninit(&vmx
->vcpu
);
8885 free_vpid(vmx
->vpid
);
8886 kmem_cache_free(kvm_vcpu_cache
, vmx
);
8887 return ERR_PTR(err
);
8890 static void __init
vmx_check_processor_compat(void *rtn
)
8892 struct vmcs_config vmcs_conf
;
8895 if (setup_vmcs_config(&vmcs_conf
) < 0)
8897 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
8898 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
8899 smp_processor_id());
8904 static int get_ept_level(void)
8906 return VMX_EPT_DEFAULT_GAW
+ 1;
8909 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
8914 /* For VT-d and EPT combination
8915 * 1. MMIO: always map as UC
8917 * a. VT-d without snooping control feature: can't guarantee the
8918 * result, try to trust guest.
8919 * b. VT-d with snooping control feature: snooping control feature of
8920 * VT-d engine can guarantee the cache correctness. Just set it
8921 * to WB to keep consistent with host. So the same as item 3.
8922 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8923 * consistent with host MTRR
8926 cache
= MTRR_TYPE_UNCACHABLE
;
8930 if (!kvm_arch_has_noncoherent_dma(vcpu
->kvm
)) {
8931 ipat
= VMX_EPT_IPAT_BIT
;
8932 cache
= MTRR_TYPE_WRBACK
;
8936 if (kvm_read_cr0(vcpu
) & X86_CR0_CD
) {
8937 ipat
= VMX_EPT_IPAT_BIT
;
8938 if (kvm_check_has_quirk(vcpu
->kvm
, KVM_X86_QUIRK_CD_NW_CLEARED
))
8939 cache
= MTRR_TYPE_WRBACK
;
8941 cache
= MTRR_TYPE_UNCACHABLE
;
8945 cache
= kvm_mtrr_get_guest_memory_type(vcpu
, gfn
);
8948 return (cache
<< VMX_EPT_MT_EPTE_SHIFT
) | ipat
;
8951 static int vmx_get_lpage_level(void)
8953 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
8954 return PT_DIRECTORY_LEVEL
;
8956 /* For shadow and EPT supported 1GB page */
8957 return PT_PDPE_LEVEL
;
8960 static void vmcs_set_secondary_exec_control(u32 new_ctl
)
8963 * These bits in the secondary execution controls field
8964 * are dynamic, the others are mostly based on the hypervisor
8965 * architecture and the guest's CPUID. Do not touch the
8969 SECONDARY_EXEC_SHADOW_VMCS
|
8970 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
8971 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
8973 u32 cur_ctl
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
8975 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
8976 (new_ctl
& ~mask
) | (cur_ctl
& mask
));
8979 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
8981 struct kvm_cpuid_entry2
*best
;
8982 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8983 u32 secondary_exec_ctl
= vmx_secondary_exec_control(vmx
);
8985 if (vmx_rdtscp_supported()) {
8986 bool rdtscp_enabled
= guest_cpuid_has_rdtscp(vcpu
);
8987 if (!rdtscp_enabled
)
8988 secondary_exec_ctl
&= ~SECONDARY_EXEC_RDTSCP
;
8992 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
8993 SECONDARY_EXEC_RDTSCP
;
8995 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
8996 ~SECONDARY_EXEC_RDTSCP
;
9000 /* Exposing INVPCID only when PCID is exposed */
9001 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
9002 if (vmx_invpcid_supported() &&
9003 (!best
|| !(best
->ebx
& bit(X86_FEATURE_INVPCID
)) ||
9004 !guest_cpuid_has_pcid(vcpu
))) {
9005 secondary_exec_ctl
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
9008 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
9011 if (cpu_has_secondary_exec_ctrls())
9012 vmcs_set_secondary_exec_control(secondary_exec_ctl
);
9014 if (static_cpu_has(X86_FEATURE_PCOMMIT
) && nested
) {
9015 if (guest_cpuid_has_pcommit(vcpu
))
9016 vmx
->nested
.nested_vmx_secondary_ctls_high
|=
9017 SECONDARY_EXEC_PCOMMIT
;
9019 vmx
->nested
.nested_vmx_secondary_ctls_high
&=
9020 ~SECONDARY_EXEC_PCOMMIT
;
9024 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
9026 if (func
== 1 && nested
)
9027 entry
->ecx
|= bit(X86_FEATURE_VMX
);
9030 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
9031 struct x86_exception
*fault
)
9033 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9036 if (fault
->error_code
& PFERR_RSVD_MASK
)
9037 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
9039 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
9040 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
9041 vmcs12
->guest_physical_address
= fault
->address
;
9044 /* Callbacks for nested_ept_init_mmu_context: */
9046 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
9048 /* return the page table to be shadowed - in our case, EPT12 */
9049 return get_vmcs12(vcpu
)->ept_pointer
;
9052 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
9054 WARN_ON(mmu_is_nested(vcpu
));
9055 kvm_init_shadow_ept_mmu(vcpu
,
9056 to_vmx(vcpu
)->nested
.nested_vmx_ept_caps
&
9057 VMX_EPT_EXECUTE_ONLY_BIT
);
9058 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
9059 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
9060 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
9062 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
9065 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
9067 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
9070 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12
*vmcs12
,
9073 bool inequality
, bit
;
9075 bit
= (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
)) != 0;
9077 (error_code
& vmcs12
->page_fault_error_code_mask
) !=
9078 vmcs12
->page_fault_error_code_match
;
9079 return inequality
^ bit
;
9082 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
9083 struct x86_exception
*fault
)
9085 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
9087 WARN_ON(!is_guest_mode(vcpu
));
9089 if (nested_vmx_is_page_fault_vmexit(vmcs12
, fault
->error_code
))
9090 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
9091 vmcs_read32(VM_EXIT_INTR_INFO
),
9092 vmcs_readl(EXIT_QUALIFICATION
));
9094 kvm_inject_page_fault(vcpu
, fault
);
9097 static bool nested_get_vmcs12_pages(struct kvm_vcpu
*vcpu
,
9098 struct vmcs12
*vmcs12
)
9100 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9101 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9103 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
)) {
9104 if (!PAGE_ALIGNED(vmcs12
->apic_access_addr
) ||
9105 vmcs12
->apic_access_addr
>> maxphyaddr
)
9109 * Translate L1 physical address to host physical
9110 * address for vmcs02. Keep the page pinned, so this
9111 * physical address remains valid. We keep a reference
9112 * to it so we can release it later.
9114 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
9115 nested_release_page(vmx
->nested
.apic_access_page
);
9116 vmx
->nested
.apic_access_page
=
9117 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
9120 if (nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
)) {
9121 if (!PAGE_ALIGNED(vmcs12
->virtual_apic_page_addr
) ||
9122 vmcs12
->virtual_apic_page_addr
>> maxphyaddr
)
9125 if (vmx
->nested
.virtual_apic_page
) /* shouldn't happen */
9126 nested_release_page(vmx
->nested
.virtual_apic_page
);
9127 vmx
->nested
.virtual_apic_page
=
9128 nested_get_page(vcpu
, vmcs12
->virtual_apic_page_addr
);
9131 * Failing the vm entry is _not_ what the processor does
9132 * but it's basically the only possibility we have.
9133 * We could still enter the guest if CR8 load exits are
9134 * enabled, CR8 store exits are enabled, and virtualize APIC
9135 * access is disabled; in this case the processor would never
9136 * use the TPR shadow and we could simply clear the bit from
9137 * the execution control. But such a configuration is useless,
9138 * so let's keep the code simple.
9140 if (!vmx
->nested
.virtual_apic_page
)
9144 if (nested_cpu_has_posted_intr(vmcs12
)) {
9145 if (!IS_ALIGNED(vmcs12
->posted_intr_desc_addr
, 64) ||
9146 vmcs12
->posted_intr_desc_addr
>> maxphyaddr
)
9149 if (vmx
->nested
.pi_desc_page
) { /* shouldn't happen */
9150 kunmap(vmx
->nested
.pi_desc_page
);
9151 nested_release_page(vmx
->nested
.pi_desc_page
);
9153 vmx
->nested
.pi_desc_page
=
9154 nested_get_page(vcpu
, vmcs12
->posted_intr_desc_addr
);
9155 if (!vmx
->nested
.pi_desc_page
)
9158 vmx
->nested
.pi_desc
=
9159 (struct pi_desc
*)kmap(vmx
->nested
.pi_desc_page
);
9160 if (!vmx
->nested
.pi_desc
) {
9161 nested_release_page_clean(vmx
->nested
.pi_desc_page
);
9164 vmx
->nested
.pi_desc
=
9165 (struct pi_desc
*)((void *)vmx
->nested
.pi_desc
+
9166 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9173 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
9175 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
9176 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9178 if (vcpu
->arch
.virtual_tsc_khz
== 0)
9181 /* Make sure short timeouts reliably trigger an immediate vmexit.
9182 * hrtimer_start does not guarantee this. */
9183 if (preemption_timeout
<= 1) {
9184 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
9188 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
9189 preemption_timeout
*= 1000000;
9190 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
9191 hrtimer_start(&vmx
->nested
.preemption_timer
,
9192 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
9195 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu
*vcpu
,
9196 struct vmcs12
*vmcs12
)
9201 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
9204 if (vmcs12_read_any(vcpu
, MSR_BITMAP
, &addr
)) {
9208 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9210 if (!PAGE_ALIGNED(vmcs12
->msr_bitmap
) ||
9211 ((addr
+ PAGE_SIZE
) >> maxphyaddr
))
9218 * Merge L0's and L1's MSR bitmap, return false to indicate that
9219 * we do not use the hardware.
9221 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu
*vcpu
,
9222 struct vmcs12
*vmcs12
)
9226 unsigned long *msr_bitmap
;
9228 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
))
9231 page
= nested_get_page(vcpu
, vmcs12
->msr_bitmap
);
9236 msr_bitmap
= (unsigned long *)kmap(page
);
9238 nested_release_page_clean(page
);
9243 if (nested_cpu_has_virt_x2apic_mode(vmcs12
)) {
9244 if (nested_cpu_has_apic_reg_virt(vmcs12
))
9245 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9246 nested_vmx_disable_intercept_for_msr(
9248 vmx_msr_bitmap_nested
,
9250 /* TPR is allowed */
9251 nested_vmx_disable_intercept_for_msr(msr_bitmap
,
9252 vmx_msr_bitmap_nested
,
9253 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9254 MSR_TYPE_R
| MSR_TYPE_W
);
9255 if (nested_cpu_has_vid(vmcs12
)) {
9256 /* EOI and self-IPI are allowed */
9257 nested_vmx_disable_intercept_for_msr(
9259 vmx_msr_bitmap_nested
,
9260 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9262 nested_vmx_disable_intercept_for_msr(
9264 vmx_msr_bitmap_nested
,
9265 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9270 * Enable reading intercept of all the x2apic
9271 * MSRs. We should not rely on vmcs12 to do any
9272 * optimizations here, it may have been modified
9275 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
9276 __vmx_enable_intercept_for_msr(
9277 vmx_msr_bitmap_nested
,
9281 __vmx_enable_intercept_for_msr(
9282 vmx_msr_bitmap_nested
,
9283 APIC_BASE_MSR
+ (APIC_TASKPRI
>> 4),
9285 __vmx_enable_intercept_for_msr(
9286 vmx_msr_bitmap_nested
,
9287 APIC_BASE_MSR
+ (APIC_EOI
>> 4),
9289 __vmx_enable_intercept_for_msr(
9290 vmx_msr_bitmap_nested
,
9291 APIC_BASE_MSR
+ (APIC_SELF_IPI
>> 4),
9295 nested_release_page_clean(page
);
9300 static int nested_vmx_check_apicv_controls(struct kvm_vcpu
*vcpu
,
9301 struct vmcs12
*vmcs12
)
9303 if (!nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9304 !nested_cpu_has_apic_reg_virt(vmcs12
) &&
9305 !nested_cpu_has_vid(vmcs12
) &&
9306 !nested_cpu_has_posted_intr(vmcs12
))
9310 * If virtualize x2apic mode is enabled,
9311 * virtualize apic access must be disabled.
9313 if (nested_cpu_has_virt_x2apic_mode(vmcs12
) &&
9314 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
9318 * If virtual interrupt delivery is enabled,
9319 * we must exit on external interrupts.
9321 if (nested_cpu_has_vid(vmcs12
) &&
9322 !nested_exit_on_intr(vcpu
))
9326 * bits 15:8 should be zero in posted_intr_nv,
9327 * the descriptor address has been already checked
9328 * in nested_get_vmcs12_pages.
9330 if (nested_cpu_has_posted_intr(vmcs12
) &&
9331 (!nested_cpu_has_vid(vmcs12
) ||
9332 !nested_exit_intr_ack_set(vcpu
) ||
9333 vmcs12
->posted_intr_nv
& 0xff00))
9336 /* tpr shadow is needed by all apicv features. */
9337 if (!nested_cpu_has(vmcs12
, CPU_BASED_TPR_SHADOW
))
9343 static int nested_vmx_check_msr_switch(struct kvm_vcpu
*vcpu
,
9344 unsigned long count_field
,
9345 unsigned long addr_field
)
9350 if (vmcs12_read_any(vcpu
, count_field
, &count
) ||
9351 vmcs12_read_any(vcpu
, addr_field
, &addr
)) {
9357 maxphyaddr
= cpuid_maxphyaddr(vcpu
);
9358 if (!IS_ALIGNED(addr
, 16) || addr
>> maxphyaddr
||
9359 (addr
+ count
* sizeof(struct vmx_msr_entry
) - 1) >> maxphyaddr
) {
9360 pr_warn_ratelimited(
9361 "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9362 addr_field
, maxphyaddr
, count
, addr
);
9368 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu
*vcpu
,
9369 struct vmcs12
*vmcs12
)
9371 if (vmcs12
->vm_exit_msr_load_count
== 0 &&
9372 vmcs12
->vm_exit_msr_store_count
== 0 &&
9373 vmcs12
->vm_entry_msr_load_count
== 0)
9374 return 0; /* Fast path */
9375 if (nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_LOAD_COUNT
,
9376 VM_EXIT_MSR_LOAD_ADDR
) ||
9377 nested_vmx_check_msr_switch(vcpu
, VM_EXIT_MSR_STORE_COUNT
,
9378 VM_EXIT_MSR_STORE_ADDR
) ||
9379 nested_vmx_check_msr_switch(vcpu
, VM_ENTRY_MSR_LOAD_COUNT
,
9380 VM_ENTRY_MSR_LOAD_ADDR
))
9385 static int nested_vmx_msr_check_common(struct kvm_vcpu
*vcpu
,
9386 struct vmx_msr_entry
*e
)
9388 /* x2APIC MSR accesses are not allowed */
9389 if (vcpu
->arch
.apic_base
& X2APIC_ENABLE
&& e
->index
>> 8 == 0x8)
9391 if (e
->index
== MSR_IA32_UCODE_WRITE
|| /* SDM Table 35-2 */
9392 e
->index
== MSR_IA32_UCODE_REV
)
9394 if (e
->reserved
!= 0)
9399 static int nested_vmx_load_msr_check(struct kvm_vcpu
*vcpu
,
9400 struct vmx_msr_entry
*e
)
9402 if (e
->index
== MSR_FS_BASE
||
9403 e
->index
== MSR_GS_BASE
||
9404 e
->index
== MSR_IA32_SMM_MONITOR_CTL
|| /* SMM is not supported */
9405 nested_vmx_msr_check_common(vcpu
, e
))
9410 static int nested_vmx_store_msr_check(struct kvm_vcpu
*vcpu
,
9411 struct vmx_msr_entry
*e
)
9413 if (e
->index
== MSR_IA32_SMBASE
|| /* SMM is not supported */
9414 nested_vmx_msr_check_common(vcpu
, e
))
9420 * Load guest's/host's msr at nested entry/exit.
9421 * return 0 for success, entry index for failure.
9423 static u32
nested_vmx_load_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9426 struct vmx_msr_entry e
;
9427 struct msr_data msr
;
9429 msr
.host_initiated
= false;
9430 for (i
= 0; i
< count
; i
++) {
9431 if (kvm_vcpu_read_guest(vcpu
, gpa
+ i
* sizeof(e
),
9433 pr_warn_ratelimited(
9434 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9435 __func__
, i
, gpa
+ i
* sizeof(e
));
9438 if (nested_vmx_load_msr_check(vcpu
, &e
)) {
9439 pr_warn_ratelimited(
9440 "%s check failed (%u, 0x%x, 0x%x)\n",
9441 __func__
, i
, e
.index
, e
.reserved
);
9444 msr
.index
= e
.index
;
9446 if (kvm_set_msr(vcpu
, &msr
)) {
9447 pr_warn_ratelimited(
9448 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9449 __func__
, i
, e
.index
, e
.value
);
9458 static int nested_vmx_store_msr(struct kvm_vcpu
*vcpu
, u64 gpa
, u32 count
)
9461 struct vmx_msr_entry e
;
9463 for (i
= 0; i
< count
; i
++) {
9464 struct msr_data msr_info
;
9465 if (kvm_vcpu_read_guest(vcpu
,
9466 gpa
+ i
* sizeof(e
),
9467 &e
, 2 * sizeof(u32
))) {
9468 pr_warn_ratelimited(
9469 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9470 __func__
, i
, gpa
+ i
* sizeof(e
));
9473 if (nested_vmx_store_msr_check(vcpu
, &e
)) {
9474 pr_warn_ratelimited(
9475 "%s check failed (%u, 0x%x, 0x%x)\n",
9476 __func__
, i
, e
.index
, e
.reserved
);
9479 msr_info
.host_initiated
= false;
9480 msr_info
.index
= e
.index
;
9481 if (kvm_get_msr(vcpu
, &msr_info
)) {
9482 pr_warn_ratelimited(
9483 "%s cannot read MSR (%u, 0x%x)\n",
9484 __func__
, i
, e
.index
);
9487 if (kvm_vcpu_write_guest(vcpu
,
9488 gpa
+ i
* sizeof(e
) +
9489 offsetof(struct vmx_msr_entry
, value
),
9490 &msr_info
.data
, sizeof(msr_info
.data
))) {
9491 pr_warn_ratelimited(
9492 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9493 __func__
, i
, e
.index
, msr_info
.data
);
9501 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9502 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9503 * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9504 * guest in a way that will both be appropriate to L1's requests, and our
9505 * needs. In addition to modifying the active vmcs (which is vmcs02), this
9506 * function also has additional necessary side-effects, like setting various
9507 * vcpu->arch fields.
9509 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
9511 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9514 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
9515 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
9516 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
9517 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
9518 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
9519 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
9520 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
9521 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
9522 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
9523 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
9524 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
9525 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
9526 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
9527 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
9528 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
9529 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
9530 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
9531 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
9532 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
9533 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
9534 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
9535 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
9536 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
9537 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
9538 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
9539 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
9540 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
9541 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
9542 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
9543 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
9544 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
9545 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
9546 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
9547 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
9548 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
9549 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
9551 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
) {
9552 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
9553 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
9555 kvm_set_dr(vcpu
, 7, vcpu
->arch
.dr7
);
9556 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmx
->nested
.vmcs01_debugctl
);
9558 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
9559 vmcs12
->vm_entry_intr_info_field
);
9560 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
9561 vmcs12
->vm_entry_exception_error_code
);
9562 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
9563 vmcs12
->vm_entry_instruction_len
);
9564 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
9565 vmcs12
->guest_interruptibility_info
);
9566 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
9567 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
9568 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
9569 vmcs12
->guest_pending_dbg_exceptions
);
9570 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
9571 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
9573 if (nested_cpu_has_xsaves(vmcs12
))
9574 vmcs_write64(XSS_EXIT_BITMAP
, vmcs12
->xss_exit_bitmap
);
9575 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
9577 exec_control
= vmcs12
->pin_based_vm_exec_control
;
9578 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
9579 exec_control
&= ~PIN_BASED_VMX_PREEMPTION_TIMER
;
9581 if (nested_cpu_has_posted_intr(vmcs12
)) {
9583 * Note that we use L0's vector here and in
9584 * vmx_deliver_nested_posted_interrupt.
9586 vmx
->nested
.posted_intr_nv
= vmcs12
->posted_intr_nv
;
9587 vmx
->nested
.pi_pending
= false;
9588 vmcs_write16(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
9589 vmcs_write64(POSTED_INTR_DESC_ADDR
,
9590 page_to_phys(vmx
->nested
.pi_desc_page
) +
9591 (unsigned long)(vmcs12
->posted_intr_desc_addr
&
9594 exec_control
&= ~PIN_BASED_POSTED_INTR
;
9596 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
9598 vmx
->nested
.preemption_timer_expired
= false;
9599 if (nested_cpu_has_preemption_timer(vmcs12
))
9600 vmx_start_preemption_timer(vcpu
);
9603 * Whether page-faults are trapped is determined by a combination of
9604 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9605 * If enable_ept, L0 doesn't care about page faults and we should
9606 * set all of these to L1's desires. However, if !enable_ept, L0 does
9607 * care about (at least some) page faults, and because it is not easy
9608 * (if at all possible?) to merge L0 and L1's desires, we simply ask
9609 * to exit on each and every L2 page fault. This is done by setting
9610 * MASK=MATCH=0 and (see below) EB.PF=1.
9611 * Note that below we don't need special code to set EB.PF beyond the
9612 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9613 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9614 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9616 * A problem with this approach (when !enable_ept) is that L1 may be
9617 * injected with more page faults than it asked for. This could have
9618 * caused problems, but in practice existing hypervisors don't care.
9619 * To fix this, we will need to emulate the PFEC checking (on the L1
9620 * page tables), using walk_addr(), when injecting PFs to L1.
9622 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
9623 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
9624 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
9625 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
9627 if (cpu_has_secondary_exec_ctrls()) {
9628 exec_control
= vmx_secondary_exec_control(vmx
);
9630 /* Take the following fields only from vmcs12 */
9631 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
9632 SECONDARY_EXEC_RDTSCP
|
9633 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
9634 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
9635 SECONDARY_EXEC_PCOMMIT
);
9636 if (nested_cpu_has(vmcs12
,
9637 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
9638 exec_control
|= vmcs12
->secondary_vm_exec_control
;
9640 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
9642 * If translation failed, no matter: This feature asks
9643 * to exit when accessing the given address, and if it
9644 * can never be accessed, this feature won't do
9647 if (!vmx
->nested
.apic_access_page
)
9649 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9651 vmcs_write64(APIC_ACCESS_ADDR
,
9652 page_to_phys(vmx
->nested
.apic_access_page
));
9653 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12
)) &&
9654 cpu_need_virtualize_apic_accesses(&vmx
->vcpu
)) {
9656 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
9657 kvm_vcpu_reload_apic_access_page(vcpu
);
9660 if (exec_control
& SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) {
9661 vmcs_write64(EOI_EXIT_BITMAP0
,
9662 vmcs12
->eoi_exit_bitmap0
);
9663 vmcs_write64(EOI_EXIT_BITMAP1
,
9664 vmcs12
->eoi_exit_bitmap1
);
9665 vmcs_write64(EOI_EXIT_BITMAP2
,
9666 vmcs12
->eoi_exit_bitmap2
);
9667 vmcs_write64(EOI_EXIT_BITMAP3
,
9668 vmcs12
->eoi_exit_bitmap3
);
9669 vmcs_write16(GUEST_INTR_STATUS
,
9670 vmcs12
->guest_intr_status
);
9673 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
9678 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9679 * Some constant fields are set here by vmx_set_constant_host_state().
9680 * Other fields are different per CPU, and will be set later when
9681 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9683 vmx_set_constant_host_state(vmx
);
9686 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9687 * entry, but only if the current (host) sp changed from the value
9688 * we wrote last (vmx->host_rsp). This cache is no longer relevant
9689 * if we switch vmcs, and rather than hold a separate cache per vmcs,
9690 * here we just force the write to happen on entry.
9694 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
9695 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
9696 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
9697 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
9698 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
9700 if (exec_control
& CPU_BASED_TPR_SHADOW
) {
9701 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
9702 page_to_phys(vmx
->nested
.virtual_apic_page
));
9703 vmcs_write32(TPR_THRESHOLD
, vmcs12
->tpr_threshold
);
9706 if (cpu_has_vmx_msr_bitmap() &&
9707 exec_control
& CPU_BASED_USE_MSR_BITMAPS
) {
9708 nested_vmx_merge_msr_bitmap(vcpu
, vmcs12
);
9709 /* MSR_BITMAP will be set by following vmx_set_efer. */
9711 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
9714 * Merging of IO bitmap not currently supported.
9715 * Rather, exit every time.
9717 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
9718 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
9720 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
9722 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9723 * bitwise-or of what L1 wants to trap for L2, and what we want to
9724 * trap. Note that CR0.TS also needs updating - we do this later.
9726 update_exception_bitmap(vcpu
);
9727 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
9728 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
9730 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9731 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9732 * bits are further modified by vmx_set_efer() below.
9734 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
9736 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9737 * emulated by vmx_set_efer(), below.
9739 vm_entry_controls_init(vmx
,
9740 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
9741 ~VM_ENTRY_IA32E_MODE
) |
9742 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
9744 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
9745 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
9746 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
9747 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
9748 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
9751 set_cr4_guest_host_mask(vmx
);
9753 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
9754 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
9756 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
9757 vmcs_write64(TSC_OFFSET
,
9758 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
9760 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
9764 * There is no direct mapping between vpid02 and vpid12, the
9765 * vpid02 is per-vCPU for L0 and reused while the value of
9766 * vpid12 is changed w/ one invvpid during nested vmentry.
9767 * The vpid12 is allocated by L1 for L2, so it will not
9768 * influence global bitmap(for vpid01 and vpid02 allocation)
9769 * even if spawn a lot of nested vCPUs.
9771 if (nested_cpu_has_vpid(vmcs12
) && vmx
->nested
.vpid02
) {
9772 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->nested
.vpid02
);
9773 if (vmcs12
->virtual_processor_id
!= vmx
->nested
.last_vpid
) {
9774 vmx
->nested
.last_vpid
= vmcs12
->virtual_processor_id
;
9775 __vmx_flush_tlb(vcpu
, to_vmx(vcpu
)->nested
.vpid02
);
9778 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
9779 vmx_flush_tlb(vcpu
);
9784 if (nested_cpu_has_ept(vmcs12
)) {
9785 kvm_mmu_unload(vcpu
);
9786 nested_ept_init_mmu_context(vcpu
);
9789 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
9790 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
9791 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
9792 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
9794 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
9795 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9796 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
9799 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9800 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9801 * The CR0_READ_SHADOW is what L2 should have expected to read given
9802 * the specifications by L1; It's not enough to take
9803 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9804 * have more bits than L1 expected.
9806 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
9807 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
9809 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
9810 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
9812 /* shadow page tables on either EPT or shadow page tables */
9813 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
9814 kvm_mmu_reset_context(vcpu
);
9817 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
9820 * L1 may access the L2's PDPTR, so save them to construct vmcs12
9823 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
9824 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
9825 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
9826 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
9829 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
9830 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
9834 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9835 * for running an L2 nested guest.
9837 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
9839 struct vmcs12
*vmcs12
;
9840 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
9842 struct loaded_vmcs
*vmcs02
;
9846 if (!nested_vmx_check_permission(vcpu
) ||
9847 !nested_vmx_check_vmcs12(vcpu
))
9850 skip_emulated_instruction(vcpu
);
9851 vmcs12
= get_vmcs12(vcpu
);
9853 if (enable_shadow_vmcs
)
9854 copy_shadow_to_vmcs12(vmx
);
9857 * The nested entry process starts with enforcing various prerequisites
9858 * on vmcs12 as required by the Intel SDM, and act appropriately when
9859 * they fail: As the SDM explains, some conditions should cause the
9860 * instruction to fail, while others will cause the instruction to seem
9861 * to succeed, but return an EXIT_REASON_INVALID_STATE.
9862 * To speed up the normal (success) code path, we should avoid checking
9863 * for misconfigurations which will anyway be caught by the processor
9864 * when using the merged vmcs02.
9866 if (vmcs12
->launch_state
== launch
) {
9867 nested_vmx_failValid(vcpu
,
9868 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9869 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
9873 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
9874 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
9875 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9879 if (!nested_get_vmcs12_pages(vcpu
, vmcs12
)) {
9880 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9884 if (nested_vmx_check_msr_bitmap_controls(vcpu
, vmcs12
)) {
9885 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9889 if (nested_vmx_check_apicv_controls(vcpu
, vmcs12
)) {
9890 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9894 if (nested_vmx_check_msr_switch_controls(vcpu
, vmcs12
)) {
9895 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9899 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
9900 vmx
->nested
.nested_vmx_true_procbased_ctls_low
,
9901 vmx
->nested
.nested_vmx_procbased_ctls_high
) ||
9902 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
9903 vmx
->nested
.nested_vmx_secondary_ctls_low
,
9904 vmx
->nested
.nested_vmx_secondary_ctls_high
) ||
9905 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
9906 vmx
->nested
.nested_vmx_pinbased_ctls_low
,
9907 vmx
->nested
.nested_vmx_pinbased_ctls_high
) ||
9908 !vmx_control_verify(vmcs12
->vm_exit_controls
,
9909 vmx
->nested
.nested_vmx_true_exit_ctls_low
,
9910 vmx
->nested
.nested_vmx_exit_ctls_high
) ||
9911 !vmx_control_verify(vmcs12
->vm_entry_controls
,
9912 vmx
->nested
.nested_vmx_true_entry_ctls_low
,
9913 vmx
->nested
.nested_vmx_entry_ctls_high
))
9915 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
9919 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
9920 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9921 nested_vmx_failValid(vcpu
,
9922 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
9926 if (!nested_cr0_valid(vcpu
, vmcs12
->guest_cr0
) ||
9927 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
9928 nested_vmx_entry_failure(vcpu
, vmcs12
,
9929 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9932 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
9933 nested_vmx_entry_failure(vcpu
, vmcs12
,
9934 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
9939 * If the load IA32_EFER VM-entry control is 1, the following checks
9940 * are performed on the field for the IA32_EFER MSR:
9941 * - Bits reserved in the IA32_EFER MSR must be 0.
9942 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9943 * the IA-32e mode guest VM-exit control. It must also be identical
9944 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9947 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
9948 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
9949 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
9950 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
9951 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
9952 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
9953 nested_vmx_entry_failure(vcpu
, vmcs12
,
9954 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9960 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9961 * IA32_EFER MSR must be 0 in the field for that register. In addition,
9962 * the values of the LMA and LME bits in the field must each be that of
9963 * the host address-space size VM-exit control.
9965 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
9966 ia32e
= (vmcs12
->vm_exit_controls
&
9967 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
9968 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
9969 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
9970 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
9971 nested_vmx_entry_failure(vcpu
, vmcs12
,
9972 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
9978 * We're finally done with prerequisite checking, and can start with
9982 vmcs02
= nested_get_current_vmcs02(vmx
);
9986 enter_guest_mode(vcpu
);
9988 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
9990 if (!(vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_DEBUG_CONTROLS
))
9991 vmx
->nested
.vmcs01_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
9994 vmx
->loaded_vmcs
= vmcs02
;
9996 vmx_vcpu_load(vcpu
, cpu
);
10000 vmx_segment_cache_clear(vmx
);
10002 prepare_vmcs02(vcpu
, vmcs12
);
10004 msr_entry_idx
= nested_vmx_load_msr(vcpu
,
10005 vmcs12
->vm_entry_msr_load_addr
,
10006 vmcs12
->vm_entry_msr_load_count
);
10007 if (msr_entry_idx
) {
10008 leave_guest_mode(vcpu
);
10009 vmx_load_vmcs01(vcpu
);
10010 nested_vmx_entry_failure(vcpu
, vmcs12
,
10011 EXIT_REASON_MSR_LOAD_FAIL
, msr_entry_idx
);
10015 vmcs12
->launch_state
= 1;
10017 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
10018 return kvm_vcpu_halt(vcpu
);
10020 vmx
->nested
.nested_run_pending
= 1;
10023 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10024 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10025 * returned as far as L1 is concerned. It will only return (and set
10026 * the success flag) when L2 exits (see nested_vmx_vmexit()).
10032 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10033 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10034 * This function returns the new value we should put in vmcs12.guest_cr0.
10035 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10036 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10037 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10038 * didn't trap the bit, because if L1 did, so would L0).
10039 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10040 * been modified by L2, and L1 knows it. So just leave the old value of
10041 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10042 * isn't relevant, because if L0 traps this bit it can set it to anything.
10043 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10044 * changed these bits, and therefore they need to be updated, but L0
10045 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10046 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10048 static inline unsigned long
10049 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10052 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
10053 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
10054 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
10055 vcpu
->arch
.cr0_guest_owned_bits
));
10058 static inline unsigned long
10059 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
10062 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
10063 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
10064 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
10065 vcpu
->arch
.cr4_guest_owned_bits
));
10068 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
10069 struct vmcs12
*vmcs12
)
10074 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
10075 nr
= vcpu
->arch
.exception
.nr
;
10076 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10078 if (kvm_exception_is_soft(nr
)) {
10079 vmcs12
->vm_exit_instruction_len
=
10080 vcpu
->arch
.event_exit_inst_len
;
10081 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
10083 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
10085 if (vcpu
->arch
.exception
.has_error_code
) {
10086 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
10087 vmcs12
->idt_vectoring_error_code
=
10088 vcpu
->arch
.exception
.error_code
;
10091 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10092 } else if (vcpu
->arch
.nmi_injected
) {
10093 vmcs12
->idt_vectoring_info_field
=
10094 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
10095 } else if (vcpu
->arch
.interrupt
.pending
) {
10096 nr
= vcpu
->arch
.interrupt
.nr
;
10097 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
10099 if (vcpu
->arch
.interrupt
.soft
) {
10100 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
10101 vmcs12
->vm_entry_instruction_len
=
10102 vcpu
->arch
.event_exit_inst_len
;
10104 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
10106 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
10110 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
10112 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10114 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
10115 vmx
->nested
.preemption_timer_expired
) {
10116 if (vmx
->nested
.nested_run_pending
)
10118 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
10122 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
10123 if (vmx
->nested
.nested_run_pending
||
10124 vcpu
->arch
.interrupt
.pending
)
10126 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
10127 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
10128 INTR_INFO_VALID_MASK
, 0);
10130 * The NMI-triggered VM exit counts as injection:
10131 * clear this one and block further NMIs.
10133 vcpu
->arch
.nmi_pending
= 0;
10134 vmx_set_nmi_mask(vcpu
, true);
10138 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
10139 nested_exit_on_intr(vcpu
)) {
10140 if (vmx
->nested
.nested_run_pending
)
10142 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
10146 return vmx_complete_nested_posted_interrupt(vcpu
);
10149 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
10151 ktime_t remaining
=
10152 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
10155 if (ktime_to_ns(remaining
) <= 0)
10158 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
10159 do_div(value
, 1000000);
10160 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
10164 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10165 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10166 * and this function updates it to reflect the changes to the guest state while
10167 * L2 was running (and perhaps made some exits which were handled directly by L0
10168 * without going back to L1), and to reflect the exit reason.
10169 * Note that we do not have to copy here all VMCS fields, just those that
10170 * could have changed by the L2 guest or the exit - i.e., the guest-state and
10171 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10172 * which already writes to vmcs12 directly.
10174 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
10175 u32 exit_reason
, u32 exit_intr_info
,
10176 unsigned long exit_qualification
)
10178 /* update guest state fields: */
10179 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
10180 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
10182 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
10183 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
10184 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
10186 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
10187 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
10188 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
10189 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
10190 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
10191 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
10192 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
10193 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
10194 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
10195 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
10196 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
10197 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
10198 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
10199 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
10200 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
10201 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
10202 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
10203 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
10204 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
10205 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
10206 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
10207 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
10208 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
10209 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
10210 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
10211 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
10212 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
10213 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
10214 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
10215 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
10216 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
10217 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
10218 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
10219 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
10220 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
10221 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
10223 vmcs12
->guest_interruptibility_info
=
10224 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
10225 vmcs12
->guest_pending_dbg_exceptions
=
10226 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
10227 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
10228 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
10230 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
10232 if (nested_cpu_has_preemption_timer(vmcs12
)) {
10233 if (vmcs12
->vm_exit_controls
&
10234 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
10235 vmcs12
->vmx_preemption_timer_value
=
10236 vmx_get_preemption_timer_value(vcpu
);
10237 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
10241 * In some cases (usually, nested EPT), L2 is allowed to change its
10242 * own CR3 without exiting. If it has changed it, we must keep it.
10243 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10244 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10246 * Additionally, restore L2's PDPTR to vmcs12.
10249 vmcs12
->guest_cr3
= vmcs_readl(GUEST_CR3
);
10250 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
10251 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
10252 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
10253 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
10256 if (nested_cpu_has_vid(vmcs12
))
10257 vmcs12
->guest_intr_status
= vmcs_read16(GUEST_INTR_STATUS
);
10259 vmcs12
->vm_entry_controls
=
10260 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
10261 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
10263 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_DEBUG_CONTROLS
) {
10264 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
10265 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
10268 /* TODO: These cannot have changed unless we have MSR bitmaps and
10269 * the relevant bit asks not to trap the change */
10270 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
10271 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
10272 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
10273 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
10274 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
10275 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
10276 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
10277 if (vmx_mpx_supported())
10278 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
10279 if (nested_cpu_has_xsaves(vmcs12
))
10280 vmcs12
->xss_exit_bitmap
= vmcs_read64(XSS_EXIT_BITMAP
);
10282 /* update exit information fields: */
10284 vmcs12
->vm_exit_reason
= exit_reason
;
10285 vmcs12
->exit_qualification
= exit_qualification
;
10287 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
10288 if ((vmcs12
->vm_exit_intr_info
&
10289 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
10290 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
10291 vmcs12
->vm_exit_intr_error_code
=
10292 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
10293 vmcs12
->idt_vectoring_info_field
= 0;
10294 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
10295 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
10297 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
10298 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10299 * instead of reading the real value. */
10300 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
10303 * Transfer the event that L0 or L1 may wanted to inject into
10304 * L2 to IDT_VECTORING_INFO_FIELD.
10306 vmcs12_save_pending_event(vcpu
, vmcs12
);
10310 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10311 * preserved above and would only end up incorrectly in L1.
10313 vcpu
->arch
.nmi_injected
= false;
10314 kvm_clear_exception_queue(vcpu
);
10315 kvm_clear_interrupt_queue(vcpu
);
10319 * A part of what we need to when the nested L2 guest exits and we want to
10320 * run its L1 parent, is to reset L1's guest state to the host state specified
10322 * This function is to be called not only on normal nested exit, but also on
10323 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10324 * Failures During or After Loading Guest State").
10325 * This function should be called when the active VMCS is L1's (vmcs01).
10327 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
10328 struct vmcs12
*vmcs12
)
10330 struct kvm_segment seg
;
10332 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
10333 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
10334 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10335 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
10337 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
10338 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
10340 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
10341 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
10342 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
10344 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10345 * actually changed, because it depends on the current state of
10346 * fpu_active (which may have changed).
10347 * Note that vmx_set_cr0 refers to efer set above.
10349 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
10351 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10352 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10353 * but we also need to update cr0_guest_host_mask and exception_bitmap.
10355 update_exception_bitmap(vcpu
);
10356 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
10357 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
10360 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10361 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10363 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
10364 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
10366 nested_ept_uninit_mmu_context(vcpu
);
10368 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
10369 kvm_mmu_reset_context(vcpu
);
10372 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
10376 * Trivially support vpid by letting L2s share their parent
10377 * L1's vpid. TODO: move to a more elaborate solution, giving
10378 * each L2 its own vpid and exposing the vpid feature to L1.
10380 vmx_flush_tlb(vcpu
);
10384 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
10385 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
10386 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
10387 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
10388 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
10390 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
10391 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
10392 vmcs_write64(GUEST_BNDCFGS
, 0);
10394 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
10395 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
10396 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
10398 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
10399 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
10400 vmcs12
->host_ia32_perf_global_ctrl
);
10402 /* Set L1 segment info according to Intel SDM
10403 27.5.2 Loading Host Segment and Descriptor-Table Registers */
10404 seg
= (struct kvm_segment
) {
10406 .limit
= 0xFFFFFFFF,
10407 .selector
= vmcs12
->host_cs_selector
,
10413 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
10417 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
10418 seg
= (struct kvm_segment
) {
10420 .limit
= 0xFFFFFFFF,
10427 seg
.selector
= vmcs12
->host_ds_selector
;
10428 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
10429 seg
.selector
= vmcs12
->host_es_selector
;
10430 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
10431 seg
.selector
= vmcs12
->host_ss_selector
;
10432 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
10433 seg
.selector
= vmcs12
->host_fs_selector
;
10434 seg
.base
= vmcs12
->host_fs_base
;
10435 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
10436 seg
.selector
= vmcs12
->host_gs_selector
;
10437 seg
.base
= vmcs12
->host_gs_base
;
10438 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
10439 seg
= (struct kvm_segment
) {
10440 .base
= vmcs12
->host_tr_base
,
10442 .selector
= vmcs12
->host_tr_selector
,
10446 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
10448 kvm_set_dr(vcpu
, 7, 0x400);
10449 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
10451 if (cpu_has_vmx_msr_bitmap())
10452 vmx_set_msr_bitmap(vcpu
);
10454 if (nested_vmx_load_msr(vcpu
, vmcs12
->vm_exit_msr_load_addr
,
10455 vmcs12
->vm_exit_msr_load_count
))
10456 nested_vmx_abort(vcpu
, VMX_ABORT_LOAD_HOST_MSR_FAIL
);
10460 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10461 * and modify vmcs12 to make it see what it would expect to see there if
10462 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10464 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
10465 u32 exit_intr_info
,
10466 unsigned long exit_qualification
)
10468 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
10469 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
10471 /* trying to cancel vmlaunch/vmresume is a bug */
10472 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
10474 leave_guest_mode(vcpu
);
10475 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
10476 exit_qualification
);
10478 if (nested_vmx_store_msr(vcpu
, vmcs12
->vm_exit_msr_store_addr
,
10479 vmcs12
->vm_exit_msr_store_count
))
10480 nested_vmx_abort(vcpu
, VMX_ABORT_SAVE_GUEST_MSR_FAIL
);
10482 vmx_load_vmcs01(vcpu
);
10484 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
10485 && nested_exit_intr_ack_set(vcpu
)) {
10486 int irq
= kvm_cpu_get_interrupt(vcpu
);
10488 vmcs12
->vm_exit_intr_info
= irq
|
10489 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
10492 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
10493 vmcs12
->exit_qualification
,
10494 vmcs12
->idt_vectoring_info_field
,
10495 vmcs12
->vm_exit_intr_info
,
10496 vmcs12
->vm_exit_intr_error_code
,
10499 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
10500 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
10501 vmx_segment_cache_clear(vmx
);
10503 /* if no vmcs02 cache requested, remove the one we used */
10504 if (VMCS02_POOL_SIZE
== 0)
10505 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
10507 load_vmcs12_host_state(vcpu
, vmcs12
);
10509 /* Update TSC_OFFSET if TSC was changed while L2 ran */
10510 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
10512 /* This is needed for same reason as it was needed in prepare_vmcs02 */
10515 /* Unpin physical memory we referred to in vmcs02 */
10516 if (vmx
->nested
.apic_access_page
) {
10517 nested_release_page(vmx
->nested
.apic_access_page
);
10518 vmx
->nested
.apic_access_page
= NULL
;
10520 if (vmx
->nested
.virtual_apic_page
) {
10521 nested_release_page(vmx
->nested
.virtual_apic_page
);
10522 vmx
->nested
.virtual_apic_page
= NULL
;
10524 if (vmx
->nested
.pi_desc_page
) {
10525 kunmap(vmx
->nested
.pi_desc_page
);
10526 nested_release_page(vmx
->nested
.pi_desc_page
);
10527 vmx
->nested
.pi_desc_page
= NULL
;
10528 vmx
->nested
.pi_desc
= NULL
;
10532 * We are now running in L2, mmu_notifier will force to reload the
10533 * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10535 kvm_vcpu_reload_apic_access_page(vcpu
);
10538 * Exiting from L2 to L1, we're now back to L1 which thinks it just
10539 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10540 * success or failure flag accordingly.
10542 if (unlikely(vmx
->fail
)) {
10544 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
10546 nested_vmx_succeed(vcpu
);
10547 if (enable_shadow_vmcs
)
10548 vmx
->nested
.sync_shadow_vmcs
= true;
10550 /* in case we halted in L2 */
10551 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
10555 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10557 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
10559 if (is_guest_mode(vcpu
))
10560 nested_vmx_vmexit(vcpu
, -1, 0, 0);
10561 free_nested(to_vmx(vcpu
));
10565 * L1's failure to enter L2 is a subset of a normal exit, as explained in
10566 * 23.7 "VM-entry failures during or after loading guest state" (this also
10567 * lists the acceptable exit-reason and exit-qualification parameters).
10568 * It should only be called before L2 actually succeeded to run, and when
10569 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10571 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
10572 struct vmcs12
*vmcs12
,
10573 u32 reason
, unsigned long qualification
)
10575 load_vmcs12_host_state(vcpu
, vmcs12
);
10576 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
10577 vmcs12
->exit_qualification
= qualification
;
10578 nested_vmx_succeed(vcpu
);
10579 if (enable_shadow_vmcs
)
10580 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
10583 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
10584 struct x86_instruction_info
*info
,
10585 enum x86_intercept_stage stage
)
10587 return X86EMUL_CONTINUE
;
10590 static void vmx_sched_in(struct kvm_vcpu
*vcpu
, int cpu
)
10593 shrink_ple_window(vcpu
);
10596 static void vmx_slot_enable_log_dirty(struct kvm
*kvm
,
10597 struct kvm_memory_slot
*slot
)
10599 kvm_mmu_slot_leaf_clear_dirty(kvm
, slot
);
10600 kvm_mmu_slot_largepage_remove_write_access(kvm
, slot
);
10603 static void vmx_slot_disable_log_dirty(struct kvm
*kvm
,
10604 struct kvm_memory_slot
*slot
)
10606 kvm_mmu_slot_set_dirty(kvm
, slot
);
10609 static void vmx_flush_log_dirty(struct kvm
*kvm
)
10611 kvm_flush_pml_buffers(kvm
);
10614 static void vmx_enable_log_dirty_pt_masked(struct kvm
*kvm
,
10615 struct kvm_memory_slot
*memslot
,
10616 gfn_t offset
, unsigned long mask
)
10618 kvm_mmu_clear_dirty_pt_masked(kvm
, memslot
, offset
, mask
);
10622 * This routine does the following things for vCPU which is going
10623 * to be blocked if VT-d PI is enabled.
10624 * - Store the vCPU to the wakeup list, so when interrupts happen
10625 * we can find the right vCPU to wake up.
10626 * - Change the Posted-interrupt descriptor as below:
10627 * 'NDST' <-- vcpu->pre_pcpu
10628 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10629 * - If 'ON' is set during this process, which means at least one
10630 * interrupt is posted for this vCPU, we cannot block it, in
10631 * this case, return 1, otherwise, return 0.
10634 static int vmx_pre_block(struct kvm_vcpu
*vcpu
)
10636 unsigned long flags
;
10638 struct pi_desc old
, new;
10639 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10641 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10642 !irq_remapping_cap(IRQ_POSTING_CAP
))
10645 vcpu
->pre_pcpu
= vcpu
->cpu
;
10646 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10647 vcpu
->pre_pcpu
), flags
);
10648 list_add_tail(&vcpu
->blocked_vcpu_list
,
10649 &per_cpu(blocked_vcpu_on_cpu
,
10651 spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock
,
10652 vcpu
->pre_pcpu
), flags
);
10655 old
.control
= new.control
= pi_desc
->control
;
10658 * We should not block the vCPU if
10659 * an interrupt is posted for it.
10661 if (pi_test_on(pi_desc
) == 1) {
10662 spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock
,
10663 vcpu
->pre_pcpu
), flags
);
10664 list_del(&vcpu
->blocked_vcpu_list
);
10665 spin_unlock_irqrestore(
10666 &per_cpu(blocked_vcpu_on_cpu_lock
,
10667 vcpu
->pre_pcpu
), flags
);
10668 vcpu
->pre_pcpu
= -1;
10673 WARN((pi_desc
->sn
== 1),
10674 "Warning: SN field of posted-interrupts "
10675 "is set before blocking\n");
10678 * Since vCPU can be preempted during this process,
10679 * vcpu->cpu could be different with pre_pcpu, we
10680 * need to set pre_pcpu as the destination of wakeup
10681 * notification event, then we can find the right vCPU
10682 * to wakeup in wakeup handler if interrupts happen
10683 * when the vCPU is in blocked state.
10685 dest
= cpu_physical_id(vcpu
->pre_pcpu
);
10687 if (x2apic_enabled())
10690 new.ndst
= (dest
<< 8) & 0xFF00;
10692 /* set 'NV' to 'wakeup vector' */
10693 new.nv
= POSTED_INTR_WAKEUP_VECTOR
;
10694 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10695 new.control
) != old
.control
);
10700 static void vmx_post_block(struct kvm_vcpu
*vcpu
)
10702 struct pi_desc
*pi_desc
= vcpu_to_pi_desc(vcpu
);
10703 struct pi_desc old
, new;
10705 unsigned long flags
;
10707 if (!kvm_arch_has_assigned_device(vcpu
->kvm
) ||
10708 !irq_remapping_cap(IRQ_POSTING_CAP
))
10712 old
.control
= new.control
= pi_desc
->control
;
10714 dest
= cpu_physical_id(vcpu
->cpu
);
10716 if (x2apic_enabled())
10719 new.ndst
= (dest
<< 8) & 0xFF00;
10721 /* Allow posting non-urgent interrupts */
10724 /* set 'NV' to 'notification vector' */
10725 new.nv
= POSTED_INTR_VECTOR
;
10726 } while (cmpxchg(&pi_desc
->control
, old
.control
,
10727 new.control
) != old
.control
);
10729 if(vcpu
->pre_pcpu
!= -1) {
10731 &per_cpu(blocked_vcpu_on_cpu_lock
,
10732 vcpu
->pre_pcpu
), flags
);
10733 list_del(&vcpu
->blocked_vcpu_list
);
10734 spin_unlock_irqrestore(
10735 &per_cpu(blocked_vcpu_on_cpu_lock
,
10736 vcpu
->pre_pcpu
), flags
);
10737 vcpu
->pre_pcpu
= -1;
10742 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10745 * @host_irq: host irq of the interrupt
10746 * @guest_irq: gsi of the interrupt
10747 * @set: set or unset PI
10748 * returns 0 on success, < 0 on failure
10750 static int vmx_update_pi_irte(struct kvm
*kvm
, unsigned int host_irq
,
10751 uint32_t guest_irq
, bool set
)
10753 struct kvm_kernel_irq_routing_entry
*e
;
10754 struct kvm_irq_routing_table
*irq_rt
;
10755 struct kvm_lapic_irq irq
;
10756 struct kvm_vcpu
*vcpu
;
10757 struct vcpu_data vcpu_info
;
10758 int idx
, ret
= -EINVAL
;
10760 if (!kvm_arch_has_assigned_device(kvm
) ||
10761 !irq_remapping_cap(IRQ_POSTING_CAP
))
10764 idx
= srcu_read_lock(&kvm
->irq_srcu
);
10765 irq_rt
= srcu_dereference(kvm
->irq_routing
, &kvm
->irq_srcu
);
10766 BUG_ON(guest_irq
>= irq_rt
->nr_rt_entries
);
10768 hlist_for_each_entry(e
, &irq_rt
->map
[guest_irq
], link
) {
10769 if (e
->type
!= KVM_IRQ_ROUTING_MSI
)
10772 * VT-d PI cannot support posting multicast/broadcast
10773 * interrupts to a vCPU, we still use interrupt remapping
10774 * for these kind of interrupts.
10776 * For lowest-priority interrupts, we only support
10777 * those with single CPU as the destination, e.g. user
10778 * configures the interrupts via /proc/irq or uses
10779 * irqbalance to make the interrupts single-CPU.
10781 * We will support full lowest-priority interrupt later.
10784 kvm_set_msi_irq(e
, &irq
);
10785 if (!kvm_intr_is_single_vcpu(kvm
, &irq
, &vcpu
)) {
10787 * Make sure the IRTE is in remapped mode if
10788 * we don't handle it in posted mode.
10790 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10793 "failed to back to remapped mode, irq: %u\n",
10801 vcpu_info
.pi_desc_addr
= __pa(vcpu_to_pi_desc(vcpu
));
10802 vcpu_info
.vector
= irq
.vector
;
10804 trace_kvm_pi_irte_update(vcpu
->vcpu_id
, host_irq
, e
->gsi
,
10805 vcpu_info
.vector
, vcpu_info
.pi_desc_addr
, set
);
10808 ret
= irq_set_vcpu_affinity(host_irq
, &vcpu_info
);
10810 /* suppress notification event before unposting */
10811 pi_set_sn(vcpu_to_pi_desc(vcpu
));
10812 ret
= irq_set_vcpu_affinity(host_irq
, NULL
);
10813 pi_clear_sn(vcpu_to_pi_desc(vcpu
));
10817 printk(KERN_INFO
"%s: failed to update PI IRTE\n",
10825 srcu_read_unlock(&kvm
->irq_srcu
, idx
);
10829 static struct kvm_x86_ops vmx_x86_ops
= {
10830 .cpu_has_kvm_support
= cpu_has_kvm_support
,
10831 .disabled_by_bios
= vmx_disabled_by_bios
,
10832 .hardware_setup
= hardware_setup
,
10833 .hardware_unsetup
= hardware_unsetup
,
10834 .check_processor_compatibility
= vmx_check_processor_compat
,
10835 .hardware_enable
= hardware_enable
,
10836 .hardware_disable
= hardware_disable
,
10837 .cpu_has_accelerated_tpr
= report_flexpriority
,
10838 .cpu_has_high_real_mode_segbase
= vmx_has_high_real_mode_segbase
,
10840 .vcpu_create
= vmx_create_vcpu
,
10841 .vcpu_free
= vmx_free_vcpu
,
10842 .vcpu_reset
= vmx_vcpu_reset
,
10844 .prepare_guest_switch
= vmx_save_host_state
,
10845 .vcpu_load
= vmx_vcpu_load
,
10846 .vcpu_put
= vmx_vcpu_put
,
10848 .update_bp_intercept
= update_exception_bitmap
,
10849 .get_msr
= vmx_get_msr
,
10850 .set_msr
= vmx_set_msr
,
10851 .get_segment_base
= vmx_get_segment_base
,
10852 .get_segment
= vmx_get_segment
,
10853 .set_segment
= vmx_set_segment
,
10854 .get_cpl
= vmx_get_cpl
,
10855 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
10856 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
10857 .decache_cr3
= vmx_decache_cr3
,
10858 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
10859 .set_cr0
= vmx_set_cr0
,
10860 .set_cr3
= vmx_set_cr3
,
10861 .set_cr4
= vmx_set_cr4
,
10862 .set_efer
= vmx_set_efer
,
10863 .get_idt
= vmx_get_idt
,
10864 .set_idt
= vmx_set_idt
,
10865 .get_gdt
= vmx_get_gdt
,
10866 .set_gdt
= vmx_set_gdt
,
10867 .get_dr6
= vmx_get_dr6
,
10868 .set_dr6
= vmx_set_dr6
,
10869 .set_dr7
= vmx_set_dr7
,
10870 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
10871 .cache_reg
= vmx_cache_reg
,
10872 .get_rflags
= vmx_get_rflags
,
10873 .set_rflags
= vmx_set_rflags
,
10874 .fpu_activate
= vmx_fpu_activate
,
10875 .fpu_deactivate
= vmx_fpu_deactivate
,
10877 .tlb_flush
= vmx_flush_tlb
,
10879 .run
= vmx_vcpu_run
,
10880 .handle_exit
= vmx_handle_exit
,
10881 .skip_emulated_instruction
= skip_emulated_instruction
,
10882 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
10883 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
10884 .patch_hypercall
= vmx_patch_hypercall
,
10885 .set_irq
= vmx_inject_irq
,
10886 .set_nmi
= vmx_inject_nmi
,
10887 .queue_exception
= vmx_queue_exception
,
10888 .cancel_injection
= vmx_cancel_injection
,
10889 .interrupt_allowed
= vmx_interrupt_allowed
,
10890 .nmi_allowed
= vmx_nmi_allowed
,
10891 .get_nmi_mask
= vmx_get_nmi_mask
,
10892 .set_nmi_mask
= vmx_set_nmi_mask
,
10893 .enable_nmi_window
= enable_nmi_window
,
10894 .enable_irq_window
= enable_irq_window
,
10895 .update_cr8_intercept
= update_cr8_intercept
,
10896 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
10897 .set_apic_access_page_addr
= vmx_set_apic_access_page_addr
,
10898 .get_enable_apicv
= vmx_get_enable_apicv
,
10899 .refresh_apicv_exec_ctrl
= vmx_refresh_apicv_exec_ctrl
,
10900 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
10901 .hwapic_irr_update
= vmx_hwapic_irr_update
,
10902 .hwapic_isr_update
= vmx_hwapic_isr_update
,
10903 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
10904 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
10906 .set_tss_addr
= vmx_set_tss_addr
,
10907 .get_tdp_level
= get_ept_level
,
10908 .get_mt_mask
= vmx_get_mt_mask
,
10910 .get_exit_info
= vmx_get_exit_info
,
10912 .get_lpage_level
= vmx_get_lpage_level
,
10914 .cpuid_update
= vmx_cpuid_update
,
10916 .rdtscp_supported
= vmx_rdtscp_supported
,
10917 .invpcid_supported
= vmx_invpcid_supported
,
10919 .set_supported_cpuid
= vmx_set_supported_cpuid
,
10921 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
10923 .read_tsc_offset
= vmx_read_tsc_offset
,
10924 .write_tsc_offset
= vmx_write_tsc_offset
,
10925 .adjust_tsc_offset_guest
= vmx_adjust_tsc_offset_guest
,
10926 .read_l1_tsc
= vmx_read_l1_tsc
,
10928 .set_tdp_cr3
= vmx_set_cr3
,
10930 .check_intercept
= vmx_check_intercept
,
10931 .handle_external_intr
= vmx_handle_external_intr
,
10932 .mpx_supported
= vmx_mpx_supported
,
10933 .xsaves_supported
= vmx_xsaves_supported
,
10935 .check_nested_events
= vmx_check_nested_events
,
10937 .sched_in
= vmx_sched_in
,
10939 .slot_enable_log_dirty
= vmx_slot_enable_log_dirty
,
10940 .slot_disable_log_dirty
= vmx_slot_disable_log_dirty
,
10941 .flush_log_dirty
= vmx_flush_log_dirty
,
10942 .enable_log_dirty_pt_masked
= vmx_enable_log_dirty_pt_masked
,
10944 .pre_block
= vmx_pre_block
,
10945 .post_block
= vmx_post_block
,
10947 .pmu_ops
= &intel_pmu_ops
,
10949 .update_pi_irte
= vmx_update_pi_irte
,
10952 static int __init
vmx_init(void)
10954 int r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
10955 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
10959 #ifdef CONFIG_KEXEC_CORE
10960 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
10961 crash_vmclear_local_loaded_vmcss
);
10967 static void __exit
vmx_exit(void)
10969 #ifdef CONFIG_KEXEC_CORE
10970 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss
, NULL
);
10977 module_init(vmx_init
)
10978 module_exit(vmx_exit
)