2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
23 #include <linux/kvm_host.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
30 #include <linux/mod_devicetable.h>
31 #include <linux/ftrace_event.h>
32 #include <linux/slab.h>
33 #include <linux/tboot.h>
34 #include <linux/hrtimer.h>
35 #include "kvm_cache_regs.h"
41 #include <asm/virtext.h>
45 #include <asm/perf_event.h>
46 #include <asm/debugreg.h>
47 #include <asm/kexec.h>
51 #define __ex(x) __kvm_handle_fault_on_reboot(x)
52 #define __ex_clear(x, reg) \
53 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
58 static const struct x86_cpu_id vmx_cpu_id
[] = {
59 X86_FEATURE_MATCH(X86_FEATURE_VMX
),
62 MODULE_DEVICE_TABLE(x86cpu
, vmx_cpu_id
);
64 static bool __read_mostly enable_vpid
= 1;
65 module_param_named(vpid
, enable_vpid
, bool, 0444);
67 static bool __read_mostly flexpriority_enabled
= 1;
68 module_param_named(flexpriority
, flexpriority_enabled
, bool, S_IRUGO
);
70 static bool __read_mostly enable_ept
= 1;
71 module_param_named(ept
, enable_ept
, bool, S_IRUGO
);
73 static bool __read_mostly enable_unrestricted_guest
= 1;
74 module_param_named(unrestricted_guest
,
75 enable_unrestricted_guest
, bool, S_IRUGO
);
77 static bool __read_mostly enable_ept_ad_bits
= 1;
78 module_param_named(eptad
, enable_ept_ad_bits
, bool, S_IRUGO
);
80 static bool __read_mostly emulate_invalid_guest_state
= true;
81 module_param(emulate_invalid_guest_state
, bool, S_IRUGO
);
83 static bool __read_mostly vmm_exclusive
= 1;
84 module_param(vmm_exclusive
, bool, S_IRUGO
);
86 static bool __read_mostly fasteoi
= 1;
87 module_param(fasteoi
, bool, S_IRUGO
);
89 static bool __read_mostly enable_apicv
= 1;
90 module_param(enable_apicv
, bool, S_IRUGO
);
92 static bool __read_mostly enable_shadow_vmcs
= 1;
93 module_param_named(enable_shadow_vmcs
, enable_shadow_vmcs
, bool, S_IRUGO
);
95 * If nested=1, nested virtualization is supported, i.e., guests may use
96 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
97 * use VMX instructions.
99 static bool __read_mostly nested
= 0;
100 module_param(nested
, bool, S_IRUGO
);
102 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
103 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
104 #define KVM_VM_CR0_ALWAYS_ON \
105 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
106 #define KVM_CR4_GUEST_OWNED_BITS \
107 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
108 | X86_CR4_OSXMMEXCPT)
110 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
111 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
113 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
115 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
118 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
119 * ple_gap: upper bound on the amount of time between two successive
120 * executions of PAUSE in a loop. Also indicate if ple enabled.
121 * According to test, this time is usually smaller than 128 cycles.
122 * ple_window: upper bound on the amount of time a guest is allowed to execute
123 * in a PAUSE loop. Tests indicate that most spinlocks are held for
124 * less than 2^12 cycles
125 * Time is measured based on a counter that runs at the same rate as the TSC,
126 * refer SDM volume 3b section 21.6.13 & 22.1.3.
128 #define KVM_VMX_DEFAULT_PLE_GAP 128
129 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
130 static int ple_gap
= KVM_VMX_DEFAULT_PLE_GAP
;
131 module_param(ple_gap
, int, S_IRUGO
);
133 static int ple_window
= KVM_VMX_DEFAULT_PLE_WINDOW
;
134 module_param(ple_window
, int, S_IRUGO
);
136 extern const ulong vmx_return
;
138 #define NR_AUTOLOAD_MSRS 8
139 #define VMCS02_POOL_SIZE 1
148 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
149 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
150 * loaded on this CPU (so we can clear them if the CPU goes down).
156 struct list_head loaded_vmcss_on_cpu_link
;
159 struct shared_msr_entry
{
166 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
167 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
168 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
169 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
170 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
171 * More than one of these structures may exist, if L1 runs multiple L2 guests.
172 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
173 * underlying hardware which will be used to run L2.
174 * This structure is packed to ensure that its layout is identical across
175 * machines (necessary for live migration).
176 * If there are changes in this struct, VMCS12_REVISION must be changed.
178 typedef u64 natural_width
;
179 struct __packed vmcs12
{
180 /* According to the Intel spec, a VMCS region must start with the
181 * following two fields. Then follow implementation-specific data.
186 u32 launch_state
; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
187 u32 padding
[7]; /* room for future expansion */
192 u64 vm_exit_msr_store_addr
;
193 u64 vm_exit_msr_load_addr
;
194 u64 vm_entry_msr_load_addr
;
196 u64 virtual_apic_page_addr
;
197 u64 apic_access_addr
;
199 u64 guest_physical_address
;
200 u64 vmcs_link_pointer
;
201 u64 guest_ia32_debugctl
;
204 u64 guest_ia32_perf_global_ctrl
;
212 u64 host_ia32_perf_global_ctrl
;
213 u64 padding64
[8]; /* room for future expansion */
215 * To allow migration of L1 (complete with its L2 guests) between
216 * machines of different natural widths (32 or 64 bit), we cannot have
217 * unsigned long fields with no explict size. We use u64 (aliased
218 * natural_width) instead. Luckily, x86 is little-endian.
220 natural_width cr0_guest_host_mask
;
221 natural_width cr4_guest_host_mask
;
222 natural_width cr0_read_shadow
;
223 natural_width cr4_read_shadow
;
224 natural_width cr3_target_value0
;
225 natural_width cr3_target_value1
;
226 natural_width cr3_target_value2
;
227 natural_width cr3_target_value3
;
228 natural_width exit_qualification
;
229 natural_width guest_linear_address
;
230 natural_width guest_cr0
;
231 natural_width guest_cr3
;
232 natural_width guest_cr4
;
233 natural_width guest_es_base
;
234 natural_width guest_cs_base
;
235 natural_width guest_ss_base
;
236 natural_width guest_ds_base
;
237 natural_width guest_fs_base
;
238 natural_width guest_gs_base
;
239 natural_width guest_ldtr_base
;
240 natural_width guest_tr_base
;
241 natural_width guest_gdtr_base
;
242 natural_width guest_idtr_base
;
243 natural_width guest_dr7
;
244 natural_width guest_rsp
;
245 natural_width guest_rip
;
246 natural_width guest_rflags
;
247 natural_width guest_pending_dbg_exceptions
;
248 natural_width guest_sysenter_esp
;
249 natural_width guest_sysenter_eip
;
250 natural_width host_cr0
;
251 natural_width host_cr3
;
252 natural_width host_cr4
;
253 natural_width host_fs_base
;
254 natural_width host_gs_base
;
255 natural_width host_tr_base
;
256 natural_width host_gdtr_base
;
257 natural_width host_idtr_base
;
258 natural_width host_ia32_sysenter_esp
;
259 natural_width host_ia32_sysenter_eip
;
260 natural_width host_rsp
;
261 natural_width host_rip
;
262 natural_width paddingl
[8]; /* room for future expansion */
263 u32 pin_based_vm_exec_control
;
264 u32 cpu_based_vm_exec_control
;
265 u32 exception_bitmap
;
266 u32 page_fault_error_code_mask
;
267 u32 page_fault_error_code_match
;
268 u32 cr3_target_count
;
269 u32 vm_exit_controls
;
270 u32 vm_exit_msr_store_count
;
271 u32 vm_exit_msr_load_count
;
272 u32 vm_entry_controls
;
273 u32 vm_entry_msr_load_count
;
274 u32 vm_entry_intr_info_field
;
275 u32 vm_entry_exception_error_code
;
276 u32 vm_entry_instruction_len
;
278 u32 secondary_vm_exec_control
;
279 u32 vm_instruction_error
;
281 u32 vm_exit_intr_info
;
282 u32 vm_exit_intr_error_code
;
283 u32 idt_vectoring_info_field
;
284 u32 idt_vectoring_error_code
;
285 u32 vm_exit_instruction_len
;
286 u32 vmx_instruction_info
;
293 u32 guest_ldtr_limit
;
295 u32 guest_gdtr_limit
;
296 u32 guest_idtr_limit
;
297 u32 guest_es_ar_bytes
;
298 u32 guest_cs_ar_bytes
;
299 u32 guest_ss_ar_bytes
;
300 u32 guest_ds_ar_bytes
;
301 u32 guest_fs_ar_bytes
;
302 u32 guest_gs_ar_bytes
;
303 u32 guest_ldtr_ar_bytes
;
304 u32 guest_tr_ar_bytes
;
305 u32 guest_interruptibility_info
;
306 u32 guest_activity_state
;
307 u32 guest_sysenter_cs
;
308 u32 host_ia32_sysenter_cs
;
309 u32 vmx_preemption_timer_value
;
310 u32 padding32
[7]; /* room for future expansion */
311 u16 virtual_processor_id
;
312 u16 guest_es_selector
;
313 u16 guest_cs_selector
;
314 u16 guest_ss_selector
;
315 u16 guest_ds_selector
;
316 u16 guest_fs_selector
;
317 u16 guest_gs_selector
;
318 u16 guest_ldtr_selector
;
319 u16 guest_tr_selector
;
320 u16 host_es_selector
;
321 u16 host_cs_selector
;
322 u16 host_ss_selector
;
323 u16 host_ds_selector
;
324 u16 host_fs_selector
;
325 u16 host_gs_selector
;
326 u16 host_tr_selector
;
330 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
331 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
332 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
334 #define VMCS12_REVISION 0x11e57ed0
337 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
338 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
339 * current implementation, 4K are reserved to avoid future complications.
341 #define VMCS12_SIZE 0x1000
343 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
345 struct list_head list
;
347 struct loaded_vmcs vmcs02
;
351 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
352 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
355 /* Has the level1 guest done vmxon? */
359 /* The guest-physical address of the current VMCS L1 keeps for L2 */
361 /* The host-usable pointer to the above */
362 struct page
*current_vmcs12_page
;
363 struct vmcs12
*current_vmcs12
;
364 struct vmcs
*current_shadow_vmcs
;
366 * Indicates if the shadow vmcs must be updated with the
367 * data hold by vmcs12
369 bool sync_shadow_vmcs
;
371 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
372 struct list_head vmcs02_pool
;
374 u64 vmcs01_tsc_offset
;
375 /* L2 must run next, and mustn't decide to exit to L1. */
376 bool nested_run_pending
;
378 * Guest pages referred to in vmcs02 with host-physical pointers, so
379 * we must keep them pinned while L2 runs.
381 struct page
*apic_access_page
;
382 u64 msr_ia32_feature_control
;
384 struct hrtimer preemption_timer
;
385 bool preemption_timer_expired
;
388 #define POSTED_INTR_ON 0
389 /* Posted-Interrupt Descriptor */
391 u32 pir
[8]; /* Posted interrupt requested */
392 u32 control
; /* bit 0 of control is outstanding notification bit */
396 static bool pi_test_and_set_on(struct pi_desc
*pi_desc
)
398 return test_and_set_bit(POSTED_INTR_ON
,
399 (unsigned long *)&pi_desc
->control
);
402 static bool pi_test_and_clear_on(struct pi_desc
*pi_desc
)
404 return test_and_clear_bit(POSTED_INTR_ON
,
405 (unsigned long *)&pi_desc
->control
);
408 static int pi_test_and_set_pir(int vector
, struct pi_desc
*pi_desc
)
410 return test_and_set_bit(vector
, (unsigned long *)pi_desc
->pir
);
414 struct kvm_vcpu vcpu
;
415 unsigned long host_rsp
;
417 bool nmi_known_unmasked
;
419 u32 idt_vectoring_info
;
421 struct shared_msr_entry
*guest_msrs
;
424 unsigned long host_idt_base
;
426 u64 msr_host_kernel_gs_base
;
427 u64 msr_guest_kernel_gs_base
;
429 u32 vm_entry_controls_shadow
;
430 u32 vm_exit_controls_shadow
;
432 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
433 * non-nested (L1) guest, it always points to vmcs01. For a nested
434 * guest (L2), it points to a different VMCS.
436 struct loaded_vmcs vmcs01
;
437 struct loaded_vmcs
*loaded_vmcs
;
438 bool __launched
; /* temporary, used in vmx_vcpu_run */
439 struct msr_autoload
{
441 struct vmx_msr_entry guest
[NR_AUTOLOAD_MSRS
];
442 struct vmx_msr_entry host
[NR_AUTOLOAD_MSRS
];
446 u16 fs_sel
, gs_sel
, ldt_sel
;
450 int gs_ldt_reload_needed
;
451 int fs_reload_needed
;
452 u64 msr_host_bndcfgs
;
457 struct kvm_segment segs
[8];
460 u32 bitmask
; /* 4 bits per segment (1 bit per field) */
461 struct kvm_save_segment
{
469 bool emulation_required
;
471 /* Support for vnmi-less CPUs */
472 int soft_vnmi_blocked
;
474 s64 vnmi_blocked_time
;
479 /* Posted interrupt descriptor */
480 struct pi_desc pi_desc
;
482 /* Support for a guest hypervisor (nested VMX) */
483 struct nested_vmx nested
;
486 enum segment_cache_field
{
495 static inline struct vcpu_vmx
*to_vmx(struct kvm_vcpu
*vcpu
)
497 return container_of(vcpu
, struct vcpu_vmx
, vcpu
);
500 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
501 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
502 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
503 [number##_HIGH] = VMCS12_OFFSET(name)+4
506 static unsigned long shadow_read_only_fields
[] = {
508 * We do NOT shadow fields that are modified when L0
509 * traps and emulates any vmx instruction (e.g. VMPTRLD,
510 * VMXON...) executed by L1.
511 * For example, VM_INSTRUCTION_ERROR is read
512 * by L1 if a vmx instruction fails (part of the error path).
513 * Note the code assumes this logic. If for some reason
514 * we start shadowing these fields then we need to
515 * force a shadow sync when L0 emulates vmx instructions
516 * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
517 * by nested_vmx_failValid)
521 VM_EXIT_INSTRUCTION_LEN
,
522 IDT_VECTORING_INFO_FIELD
,
523 IDT_VECTORING_ERROR_CODE
,
524 VM_EXIT_INTR_ERROR_CODE
,
526 GUEST_LINEAR_ADDRESS
,
527 GUEST_PHYSICAL_ADDRESS
529 static int max_shadow_read_only_fields
=
530 ARRAY_SIZE(shadow_read_only_fields
);
532 static unsigned long shadow_read_write_fields
[] = {
538 GUEST_INTERRUPTIBILITY_INFO
,
551 CPU_BASED_VM_EXEC_CONTROL
,
552 VM_ENTRY_EXCEPTION_ERROR_CODE
,
553 VM_ENTRY_INTR_INFO_FIELD
,
554 VM_ENTRY_INSTRUCTION_LEN
,
555 VM_ENTRY_EXCEPTION_ERROR_CODE
,
561 static int max_shadow_read_write_fields
=
562 ARRAY_SIZE(shadow_read_write_fields
);
564 static const unsigned short vmcs_field_to_offset_table
[] = {
565 FIELD(VIRTUAL_PROCESSOR_ID
, virtual_processor_id
),
566 FIELD(GUEST_ES_SELECTOR
, guest_es_selector
),
567 FIELD(GUEST_CS_SELECTOR
, guest_cs_selector
),
568 FIELD(GUEST_SS_SELECTOR
, guest_ss_selector
),
569 FIELD(GUEST_DS_SELECTOR
, guest_ds_selector
),
570 FIELD(GUEST_FS_SELECTOR
, guest_fs_selector
),
571 FIELD(GUEST_GS_SELECTOR
, guest_gs_selector
),
572 FIELD(GUEST_LDTR_SELECTOR
, guest_ldtr_selector
),
573 FIELD(GUEST_TR_SELECTOR
, guest_tr_selector
),
574 FIELD(HOST_ES_SELECTOR
, host_es_selector
),
575 FIELD(HOST_CS_SELECTOR
, host_cs_selector
),
576 FIELD(HOST_SS_SELECTOR
, host_ss_selector
),
577 FIELD(HOST_DS_SELECTOR
, host_ds_selector
),
578 FIELD(HOST_FS_SELECTOR
, host_fs_selector
),
579 FIELD(HOST_GS_SELECTOR
, host_gs_selector
),
580 FIELD(HOST_TR_SELECTOR
, host_tr_selector
),
581 FIELD64(IO_BITMAP_A
, io_bitmap_a
),
582 FIELD64(IO_BITMAP_B
, io_bitmap_b
),
583 FIELD64(MSR_BITMAP
, msr_bitmap
),
584 FIELD64(VM_EXIT_MSR_STORE_ADDR
, vm_exit_msr_store_addr
),
585 FIELD64(VM_EXIT_MSR_LOAD_ADDR
, vm_exit_msr_load_addr
),
586 FIELD64(VM_ENTRY_MSR_LOAD_ADDR
, vm_entry_msr_load_addr
),
587 FIELD64(TSC_OFFSET
, tsc_offset
),
588 FIELD64(VIRTUAL_APIC_PAGE_ADDR
, virtual_apic_page_addr
),
589 FIELD64(APIC_ACCESS_ADDR
, apic_access_addr
),
590 FIELD64(EPT_POINTER
, ept_pointer
),
591 FIELD64(GUEST_PHYSICAL_ADDRESS
, guest_physical_address
),
592 FIELD64(VMCS_LINK_POINTER
, vmcs_link_pointer
),
593 FIELD64(GUEST_IA32_DEBUGCTL
, guest_ia32_debugctl
),
594 FIELD64(GUEST_IA32_PAT
, guest_ia32_pat
),
595 FIELD64(GUEST_IA32_EFER
, guest_ia32_efer
),
596 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL
, guest_ia32_perf_global_ctrl
),
597 FIELD64(GUEST_PDPTR0
, guest_pdptr0
),
598 FIELD64(GUEST_PDPTR1
, guest_pdptr1
),
599 FIELD64(GUEST_PDPTR2
, guest_pdptr2
),
600 FIELD64(GUEST_PDPTR3
, guest_pdptr3
),
601 FIELD64(GUEST_BNDCFGS
, guest_bndcfgs
),
602 FIELD64(HOST_IA32_PAT
, host_ia32_pat
),
603 FIELD64(HOST_IA32_EFER
, host_ia32_efer
),
604 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL
, host_ia32_perf_global_ctrl
),
605 FIELD(PIN_BASED_VM_EXEC_CONTROL
, pin_based_vm_exec_control
),
606 FIELD(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
),
607 FIELD(EXCEPTION_BITMAP
, exception_bitmap
),
608 FIELD(PAGE_FAULT_ERROR_CODE_MASK
, page_fault_error_code_mask
),
609 FIELD(PAGE_FAULT_ERROR_CODE_MATCH
, page_fault_error_code_match
),
610 FIELD(CR3_TARGET_COUNT
, cr3_target_count
),
611 FIELD(VM_EXIT_CONTROLS
, vm_exit_controls
),
612 FIELD(VM_EXIT_MSR_STORE_COUNT
, vm_exit_msr_store_count
),
613 FIELD(VM_EXIT_MSR_LOAD_COUNT
, vm_exit_msr_load_count
),
614 FIELD(VM_ENTRY_CONTROLS
, vm_entry_controls
),
615 FIELD(VM_ENTRY_MSR_LOAD_COUNT
, vm_entry_msr_load_count
),
616 FIELD(VM_ENTRY_INTR_INFO_FIELD
, vm_entry_intr_info_field
),
617 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE
, vm_entry_exception_error_code
),
618 FIELD(VM_ENTRY_INSTRUCTION_LEN
, vm_entry_instruction_len
),
619 FIELD(TPR_THRESHOLD
, tpr_threshold
),
620 FIELD(SECONDARY_VM_EXEC_CONTROL
, secondary_vm_exec_control
),
621 FIELD(VM_INSTRUCTION_ERROR
, vm_instruction_error
),
622 FIELD(VM_EXIT_REASON
, vm_exit_reason
),
623 FIELD(VM_EXIT_INTR_INFO
, vm_exit_intr_info
),
624 FIELD(VM_EXIT_INTR_ERROR_CODE
, vm_exit_intr_error_code
),
625 FIELD(IDT_VECTORING_INFO_FIELD
, idt_vectoring_info_field
),
626 FIELD(IDT_VECTORING_ERROR_CODE
, idt_vectoring_error_code
),
627 FIELD(VM_EXIT_INSTRUCTION_LEN
, vm_exit_instruction_len
),
628 FIELD(VMX_INSTRUCTION_INFO
, vmx_instruction_info
),
629 FIELD(GUEST_ES_LIMIT
, guest_es_limit
),
630 FIELD(GUEST_CS_LIMIT
, guest_cs_limit
),
631 FIELD(GUEST_SS_LIMIT
, guest_ss_limit
),
632 FIELD(GUEST_DS_LIMIT
, guest_ds_limit
),
633 FIELD(GUEST_FS_LIMIT
, guest_fs_limit
),
634 FIELD(GUEST_GS_LIMIT
, guest_gs_limit
),
635 FIELD(GUEST_LDTR_LIMIT
, guest_ldtr_limit
),
636 FIELD(GUEST_TR_LIMIT
, guest_tr_limit
),
637 FIELD(GUEST_GDTR_LIMIT
, guest_gdtr_limit
),
638 FIELD(GUEST_IDTR_LIMIT
, guest_idtr_limit
),
639 FIELD(GUEST_ES_AR_BYTES
, guest_es_ar_bytes
),
640 FIELD(GUEST_CS_AR_BYTES
, guest_cs_ar_bytes
),
641 FIELD(GUEST_SS_AR_BYTES
, guest_ss_ar_bytes
),
642 FIELD(GUEST_DS_AR_BYTES
, guest_ds_ar_bytes
),
643 FIELD(GUEST_FS_AR_BYTES
, guest_fs_ar_bytes
),
644 FIELD(GUEST_GS_AR_BYTES
, guest_gs_ar_bytes
),
645 FIELD(GUEST_LDTR_AR_BYTES
, guest_ldtr_ar_bytes
),
646 FIELD(GUEST_TR_AR_BYTES
, guest_tr_ar_bytes
),
647 FIELD(GUEST_INTERRUPTIBILITY_INFO
, guest_interruptibility_info
),
648 FIELD(GUEST_ACTIVITY_STATE
, guest_activity_state
),
649 FIELD(GUEST_SYSENTER_CS
, guest_sysenter_cs
),
650 FIELD(HOST_IA32_SYSENTER_CS
, host_ia32_sysenter_cs
),
651 FIELD(VMX_PREEMPTION_TIMER_VALUE
, vmx_preemption_timer_value
),
652 FIELD(CR0_GUEST_HOST_MASK
, cr0_guest_host_mask
),
653 FIELD(CR4_GUEST_HOST_MASK
, cr4_guest_host_mask
),
654 FIELD(CR0_READ_SHADOW
, cr0_read_shadow
),
655 FIELD(CR4_READ_SHADOW
, cr4_read_shadow
),
656 FIELD(CR3_TARGET_VALUE0
, cr3_target_value0
),
657 FIELD(CR3_TARGET_VALUE1
, cr3_target_value1
),
658 FIELD(CR3_TARGET_VALUE2
, cr3_target_value2
),
659 FIELD(CR3_TARGET_VALUE3
, cr3_target_value3
),
660 FIELD(EXIT_QUALIFICATION
, exit_qualification
),
661 FIELD(GUEST_LINEAR_ADDRESS
, guest_linear_address
),
662 FIELD(GUEST_CR0
, guest_cr0
),
663 FIELD(GUEST_CR3
, guest_cr3
),
664 FIELD(GUEST_CR4
, guest_cr4
),
665 FIELD(GUEST_ES_BASE
, guest_es_base
),
666 FIELD(GUEST_CS_BASE
, guest_cs_base
),
667 FIELD(GUEST_SS_BASE
, guest_ss_base
),
668 FIELD(GUEST_DS_BASE
, guest_ds_base
),
669 FIELD(GUEST_FS_BASE
, guest_fs_base
),
670 FIELD(GUEST_GS_BASE
, guest_gs_base
),
671 FIELD(GUEST_LDTR_BASE
, guest_ldtr_base
),
672 FIELD(GUEST_TR_BASE
, guest_tr_base
),
673 FIELD(GUEST_GDTR_BASE
, guest_gdtr_base
),
674 FIELD(GUEST_IDTR_BASE
, guest_idtr_base
),
675 FIELD(GUEST_DR7
, guest_dr7
),
676 FIELD(GUEST_RSP
, guest_rsp
),
677 FIELD(GUEST_RIP
, guest_rip
),
678 FIELD(GUEST_RFLAGS
, guest_rflags
),
679 FIELD(GUEST_PENDING_DBG_EXCEPTIONS
, guest_pending_dbg_exceptions
),
680 FIELD(GUEST_SYSENTER_ESP
, guest_sysenter_esp
),
681 FIELD(GUEST_SYSENTER_EIP
, guest_sysenter_eip
),
682 FIELD(HOST_CR0
, host_cr0
),
683 FIELD(HOST_CR3
, host_cr3
),
684 FIELD(HOST_CR4
, host_cr4
),
685 FIELD(HOST_FS_BASE
, host_fs_base
),
686 FIELD(HOST_GS_BASE
, host_gs_base
),
687 FIELD(HOST_TR_BASE
, host_tr_base
),
688 FIELD(HOST_GDTR_BASE
, host_gdtr_base
),
689 FIELD(HOST_IDTR_BASE
, host_idtr_base
),
690 FIELD(HOST_IA32_SYSENTER_ESP
, host_ia32_sysenter_esp
),
691 FIELD(HOST_IA32_SYSENTER_EIP
, host_ia32_sysenter_eip
),
692 FIELD(HOST_RSP
, host_rsp
),
693 FIELD(HOST_RIP
, host_rip
),
695 static const int max_vmcs_field
= ARRAY_SIZE(vmcs_field_to_offset_table
);
697 static inline short vmcs_field_to_offset(unsigned long field
)
699 if (field
>= max_vmcs_field
|| vmcs_field_to_offset_table
[field
] == 0)
701 return vmcs_field_to_offset_table
[field
];
704 static inline struct vmcs12
*get_vmcs12(struct kvm_vcpu
*vcpu
)
706 return to_vmx(vcpu
)->nested
.current_vmcs12
;
709 static struct page
*nested_get_page(struct kvm_vcpu
*vcpu
, gpa_t addr
)
711 struct page
*page
= gfn_to_page(vcpu
->kvm
, addr
>> PAGE_SHIFT
);
712 if (is_error_page(page
))
718 static void nested_release_page(struct page
*page
)
720 kvm_release_page_dirty(page
);
723 static void nested_release_page_clean(struct page
*page
)
725 kvm_release_page_clean(page
);
728 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
);
729 static u64
construct_eptp(unsigned long root_hpa
);
730 static void kvm_cpu_vmxon(u64 addr
);
731 static void kvm_cpu_vmxoff(void);
732 static bool vmx_mpx_supported(void);
733 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
);
734 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
735 struct kvm_segment
*var
, int seg
);
736 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
737 struct kvm_segment
*var
, int seg
);
738 static bool guest_state_valid(struct kvm_vcpu
*vcpu
);
739 static u32
vmx_segment_access_rights(struct kvm_segment
*var
);
740 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
);
741 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
);
742 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
);
743 static bool vmx_mpx_supported(void);
745 static DEFINE_PER_CPU(struct vmcs
*, vmxarea
);
746 static DEFINE_PER_CPU(struct vmcs
*, current_vmcs
);
748 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
749 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
751 static DEFINE_PER_CPU(struct list_head
, loaded_vmcss_on_cpu
);
752 static DEFINE_PER_CPU(struct desc_ptr
, host_gdt
);
754 static unsigned long *vmx_io_bitmap_a
;
755 static unsigned long *vmx_io_bitmap_b
;
756 static unsigned long *vmx_msr_bitmap_legacy
;
757 static unsigned long *vmx_msr_bitmap_longmode
;
758 static unsigned long *vmx_msr_bitmap_legacy_x2apic
;
759 static unsigned long *vmx_msr_bitmap_longmode_x2apic
;
760 static unsigned long *vmx_vmread_bitmap
;
761 static unsigned long *vmx_vmwrite_bitmap
;
763 static bool cpu_has_load_ia32_efer
;
764 static bool cpu_has_load_perf_global_ctrl
;
766 static DECLARE_BITMAP(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
767 static DEFINE_SPINLOCK(vmx_vpid_lock
);
769 static struct vmcs_config
{
773 u32 pin_based_exec_ctrl
;
774 u32 cpu_based_exec_ctrl
;
775 u32 cpu_based_2nd_exec_ctrl
;
780 static struct vmx_capability
{
785 #define VMX_SEGMENT_FIELD(seg) \
786 [VCPU_SREG_##seg] = { \
787 .selector = GUEST_##seg##_SELECTOR, \
788 .base = GUEST_##seg##_BASE, \
789 .limit = GUEST_##seg##_LIMIT, \
790 .ar_bytes = GUEST_##seg##_AR_BYTES, \
793 static const struct kvm_vmx_segment_field
{
798 } kvm_vmx_segment_fields
[] = {
799 VMX_SEGMENT_FIELD(CS
),
800 VMX_SEGMENT_FIELD(DS
),
801 VMX_SEGMENT_FIELD(ES
),
802 VMX_SEGMENT_FIELD(FS
),
803 VMX_SEGMENT_FIELD(GS
),
804 VMX_SEGMENT_FIELD(SS
),
805 VMX_SEGMENT_FIELD(TR
),
806 VMX_SEGMENT_FIELD(LDTR
),
809 static u64 host_efer
;
811 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
);
814 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
815 * away by decrementing the array size.
817 static const u32 vmx_msr_index
[] = {
819 MSR_SYSCALL_MASK
, MSR_LSTAR
, MSR_CSTAR
,
821 MSR_EFER
, MSR_TSC_AUX
, MSR_STAR
,
823 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
825 static inline bool is_page_fault(u32 intr_info
)
827 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
828 INTR_INFO_VALID_MASK
)) ==
829 (INTR_TYPE_HARD_EXCEPTION
| PF_VECTOR
| INTR_INFO_VALID_MASK
);
832 static inline bool is_no_device(u32 intr_info
)
834 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
835 INTR_INFO_VALID_MASK
)) ==
836 (INTR_TYPE_HARD_EXCEPTION
| NM_VECTOR
| INTR_INFO_VALID_MASK
);
839 static inline bool is_invalid_opcode(u32 intr_info
)
841 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
842 INTR_INFO_VALID_MASK
)) ==
843 (INTR_TYPE_HARD_EXCEPTION
| UD_VECTOR
| INTR_INFO_VALID_MASK
);
846 static inline bool is_external_interrupt(u32 intr_info
)
848 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
849 == (INTR_TYPE_EXT_INTR
| INTR_INFO_VALID_MASK
);
852 static inline bool is_machine_check(u32 intr_info
)
854 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VECTOR_MASK
|
855 INTR_INFO_VALID_MASK
)) ==
856 (INTR_TYPE_HARD_EXCEPTION
| MC_VECTOR
| INTR_INFO_VALID_MASK
);
859 static inline bool cpu_has_vmx_msr_bitmap(void)
861 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_USE_MSR_BITMAPS
;
864 static inline bool cpu_has_vmx_tpr_shadow(void)
866 return vmcs_config
.cpu_based_exec_ctrl
& CPU_BASED_TPR_SHADOW
;
869 static inline bool vm_need_tpr_shadow(struct kvm
*kvm
)
871 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm
));
874 static inline bool cpu_has_secondary_exec_ctrls(void)
876 return vmcs_config
.cpu_based_exec_ctrl
&
877 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
880 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
882 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
883 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
886 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
888 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
889 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
892 static inline bool cpu_has_vmx_apic_register_virt(void)
894 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
895 SECONDARY_EXEC_APIC_REGISTER_VIRT
;
898 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
900 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
901 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
;
904 static inline bool cpu_has_vmx_posted_intr(void)
906 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_POSTED_INTR
;
909 static inline bool cpu_has_vmx_apicv(void)
911 return cpu_has_vmx_apic_register_virt() &&
912 cpu_has_vmx_virtual_intr_delivery() &&
913 cpu_has_vmx_posted_intr();
916 static inline bool cpu_has_vmx_flexpriority(void)
918 return cpu_has_vmx_tpr_shadow() &&
919 cpu_has_vmx_virtualize_apic_accesses();
922 static inline bool cpu_has_vmx_ept_execute_only(void)
924 return vmx_capability
.ept
& VMX_EPT_EXECUTE_ONLY_BIT
;
927 static inline bool cpu_has_vmx_eptp_uncacheable(void)
929 return vmx_capability
.ept
& VMX_EPTP_UC_BIT
;
932 static inline bool cpu_has_vmx_eptp_writeback(void)
934 return vmx_capability
.ept
& VMX_EPTP_WB_BIT
;
937 static inline bool cpu_has_vmx_ept_2m_page(void)
939 return vmx_capability
.ept
& VMX_EPT_2MB_PAGE_BIT
;
942 static inline bool cpu_has_vmx_ept_1g_page(void)
944 return vmx_capability
.ept
& VMX_EPT_1GB_PAGE_BIT
;
947 static inline bool cpu_has_vmx_ept_4levels(void)
949 return vmx_capability
.ept
& VMX_EPT_PAGE_WALK_4_BIT
;
952 static inline bool cpu_has_vmx_ept_ad_bits(void)
954 return vmx_capability
.ept
& VMX_EPT_AD_BIT
;
957 static inline bool cpu_has_vmx_invept_context(void)
959 return vmx_capability
.ept
& VMX_EPT_EXTENT_CONTEXT_BIT
;
962 static inline bool cpu_has_vmx_invept_global(void)
964 return vmx_capability
.ept
& VMX_EPT_EXTENT_GLOBAL_BIT
;
967 static inline bool cpu_has_vmx_invvpid_single(void)
969 return vmx_capability
.vpid
& VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT
;
972 static inline bool cpu_has_vmx_invvpid_global(void)
974 return vmx_capability
.vpid
& VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT
;
977 static inline bool cpu_has_vmx_ept(void)
979 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
980 SECONDARY_EXEC_ENABLE_EPT
;
983 static inline bool cpu_has_vmx_unrestricted_guest(void)
985 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
986 SECONDARY_EXEC_UNRESTRICTED_GUEST
;
989 static inline bool cpu_has_vmx_ple(void)
991 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
992 SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
995 static inline bool vm_need_virtualize_apic_accesses(struct kvm
*kvm
)
997 return flexpriority_enabled
&& irqchip_in_kernel(kvm
);
1000 static inline bool cpu_has_vmx_vpid(void)
1002 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1003 SECONDARY_EXEC_ENABLE_VPID
;
1006 static inline bool cpu_has_vmx_rdtscp(void)
1008 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1009 SECONDARY_EXEC_RDTSCP
;
1012 static inline bool cpu_has_vmx_invpcid(void)
1014 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1015 SECONDARY_EXEC_ENABLE_INVPCID
;
1018 static inline bool cpu_has_virtual_nmis(void)
1020 return vmcs_config
.pin_based_exec_ctrl
& PIN_BASED_VIRTUAL_NMIS
;
1023 static inline bool cpu_has_vmx_wbinvd_exit(void)
1025 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1026 SECONDARY_EXEC_WBINVD_EXITING
;
1029 static inline bool cpu_has_vmx_shadow_vmcs(void)
1032 rdmsrl(MSR_IA32_VMX_MISC
, vmx_msr
);
1033 /* check if the cpu supports writing r/o exit information fields */
1034 if (!(vmx_msr
& MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS
))
1037 return vmcs_config
.cpu_based_2nd_exec_ctrl
&
1038 SECONDARY_EXEC_SHADOW_VMCS
;
1041 static inline bool report_flexpriority(void)
1043 return flexpriority_enabled
;
1046 static inline bool nested_cpu_has(struct vmcs12
*vmcs12
, u32 bit
)
1048 return vmcs12
->cpu_based_vm_exec_control
& bit
;
1051 static inline bool nested_cpu_has2(struct vmcs12
*vmcs12
, u32 bit
)
1053 return (vmcs12
->cpu_based_vm_exec_control
&
1054 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) &&
1055 (vmcs12
->secondary_vm_exec_control
& bit
);
1058 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12
*vmcs12
)
1060 return vmcs12
->pin_based_vm_exec_control
& PIN_BASED_VIRTUAL_NMIS
;
1063 static inline bool nested_cpu_has_preemption_timer(struct vmcs12
*vmcs12
)
1065 return vmcs12
->pin_based_vm_exec_control
&
1066 PIN_BASED_VMX_PREEMPTION_TIMER
;
1069 static inline int nested_cpu_has_ept(struct vmcs12
*vmcs12
)
1071 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_ENABLE_EPT
);
1074 static inline bool is_exception(u32 intr_info
)
1076 return (intr_info
& (INTR_INFO_INTR_TYPE_MASK
| INTR_INFO_VALID_MASK
))
1077 == (INTR_TYPE_HARD_EXCEPTION
| INTR_INFO_VALID_MASK
);
1080 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
1082 unsigned long exit_qualification
);
1083 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
1084 struct vmcs12
*vmcs12
,
1085 u32 reason
, unsigned long qualification
);
1087 static int __find_msr_index(struct vcpu_vmx
*vmx
, u32 msr
)
1091 for (i
= 0; i
< vmx
->nmsrs
; ++i
)
1092 if (vmx_msr_index
[vmx
->guest_msrs
[i
].index
] == msr
)
1097 static inline void __invvpid(int ext
, u16 vpid
, gva_t gva
)
1103 } operand
= { vpid
, 0, gva
};
1105 asm volatile (__ex(ASM_VMX_INVVPID
)
1106 /* CF==1 or ZF==1 --> rc = -1 */
1107 "; ja 1f ; ud2 ; 1:"
1108 : : "a"(&operand
), "c"(ext
) : "cc", "memory");
1111 static inline void __invept(int ext
, u64 eptp
, gpa_t gpa
)
1115 } operand
= {eptp
, gpa
};
1117 asm volatile (__ex(ASM_VMX_INVEPT
)
1118 /* CF==1 or ZF==1 --> rc = -1 */
1119 "; ja 1f ; ud2 ; 1:\n"
1120 : : "a" (&operand
), "c" (ext
) : "cc", "memory");
1123 static struct shared_msr_entry
*find_msr_entry(struct vcpu_vmx
*vmx
, u32 msr
)
1127 i
= __find_msr_index(vmx
, msr
);
1129 return &vmx
->guest_msrs
[i
];
1133 static void vmcs_clear(struct vmcs
*vmcs
)
1135 u64 phys_addr
= __pa(vmcs
);
1138 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX
) "; setna %0"
1139 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1142 printk(KERN_ERR
"kvm: vmclear fail: %p/%llx\n",
1146 static inline void loaded_vmcs_init(struct loaded_vmcs
*loaded_vmcs
)
1148 vmcs_clear(loaded_vmcs
->vmcs
);
1149 loaded_vmcs
->cpu
= -1;
1150 loaded_vmcs
->launched
= 0;
1153 static void vmcs_load(struct vmcs
*vmcs
)
1155 u64 phys_addr
= __pa(vmcs
);
1158 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX
) "; setna %0"
1159 : "=qm"(error
) : "a"(&phys_addr
), "m"(phys_addr
)
1162 printk(KERN_ERR
"kvm: vmptrld %p/%llx failed\n",
1168 * This bitmap is used to indicate whether the vmclear
1169 * operation is enabled on all cpus. All disabled by
1172 static cpumask_t crash_vmclear_enabled_bitmap
= CPU_MASK_NONE
;
1174 static inline void crash_enable_local_vmclear(int cpu
)
1176 cpumask_set_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1179 static inline void crash_disable_local_vmclear(int cpu
)
1181 cpumask_clear_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1184 static inline int crash_local_vmclear_enabled(int cpu
)
1186 return cpumask_test_cpu(cpu
, &crash_vmclear_enabled_bitmap
);
1189 static void crash_vmclear_local_loaded_vmcss(void)
1191 int cpu
= raw_smp_processor_id();
1192 struct loaded_vmcs
*v
;
1194 if (!crash_local_vmclear_enabled(cpu
))
1197 list_for_each_entry(v
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
1198 loaded_vmcss_on_cpu_link
)
1199 vmcs_clear(v
->vmcs
);
1202 static inline void crash_enable_local_vmclear(int cpu
) { }
1203 static inline void crash_disable_local_vmclear(int cpu
) { }
1204 #endif /* CONFIG_KEXEC */
1206 static void __loaded_vmcs_clear(void *arg
)
1208 struct loaded_vmcs
*loaded_vmcs
= arg
;
1209 int cpu
= raw_smp_processor_id();
1211 if (loaded_vmcs
->cpu
!= cpu
)
1212 return; /* vcpu migration can race with cpu offline */
1213 if (per_cpu(current_vmcs
, cpu
) == loaded_vmcs
->vmcs
)
1214 per_cpu(current_vmcs
, cpu
) = NULL
;
1215 crash_disable_local_vmclear(cpu
);
1216 list_del(&loaded_vmcs
->loaded_vmcss_on_cpu_link
);
1219 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1220 * is before setting loaded_vmcs->vcpu to -1 which is done in
1221 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1222 * then adds the vmcs into percpu list before it is deleted.
1226 loaded_vmcs_init(loaded_vmcs
);
1227 crash_enable_local_vmclear(cpu
);
1230 static void loaded_vmcs_clear(struct loaded_vmcs
*loaded_vmcs
)
1232 int cpu
= loaded_vmcs
->cpu
;
1235 smp_call_function_single(cpu
,
1236 __loaded_vmcs_clear
, loaded_vmcs
, 1);
1239 static inline void vpid_sync_vcpu_single(struct vcpu_vmx
*vmx
)
1244 if (cpu_has_vmx_invvpid_single())
1245 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT
, vmx
->vpid
, 0);
1248 static inline void vpid_sync_vcpu_global(void)
1250 if (cpu_has_vmx_invvpid_global())
1251 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT
, 0, 0);
1254 static inline void vpid_sync_context(struct vcpu_vmx
*vmx
)
1256 if (cpu_has_vmx_invvpid_single())
1257 vpid_sync_vcpu_single(vmx
);
1259 vpid_sync_vcpu_global();
1262 static inline void ept_sync_global(void)
1264 if (cpu_has_vmx_invept_global())
1265 __invept(VMX_EPT_EXTENT_GLOBAL
, 0, 0);
1268 static inline void ept_sync_context(u64 eptp
)
1271 if (cpu_has_vmx_invept_context())
1272 __invept(VMX_EPT_EXTENT_CONTEXT
, eptp
, 0);
1278 static __always_inline
unsigned long vmcs_readl(unsigned long field
)
1280 unsigned long value
;
1282 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX
, "%0")
1283 : "=a"(value
) : "d"(field
) : "cc");
1287 static __always_inline u16
vmcs_read16(unsigned long field
)
1289 return vmcs_readl(field
);
1292 static __always_inline u32
vmcs_read32(unsigned long field
)
1294 return vmcs_readl(field
);
1297 static __always_inline u64
vmcs_read64(unsigned long field
)
1299 #ifdef CONFIG_X86_64
1300 return vmcs_readl(field
);
1302 return vmcs_readl(field
) | ((u64
)vmcs_readl(field
+1) << 32);
1306 static noinline
void vmwrite_error(unsigned long field
, unsigned long value
)
1308 printk(KERN_ERR
"vmwrite error: reg %lx value %lx (err %d)\n",
1309 field
, value
, vmcs_read32(VM_INSTRUCTION_ERROR
));
1313 static void vmcs_writel(unsigned long field
, unsigned long value
)
1317 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX
) "; setna %0"
1318 : "=q"(error
) : "a"(value
), "d"(field
) : "cc");
1319 if (unlikely(error
))
1320 vmwrite_error(field
, value
);
1323 static void vmcs_write16(unsigned long field
, u16 value
)
1325 vmcs_writel(field
, value
);
1328 static void vmcs_write32(unsigned long field
, u32 value
)
1330 vmcs_writel(field
, value
);
1333 static void vmcs_write64(unsigned long field
, u64 value
)
1335 vmcs_writel(field
, value
);
1336 #ifndef CONFIG_X86_64
1338 vmcs_writel(field
+1, value
>> 32);
1342 static void vmcs_clear_bits(unsigned long field
, u32 mask
)
1344 vmcs_writel(field
, vmcs_readl(field
) & ~mask
);
1347 static void vmcs_set_bits(unsigned long field
, u32 mask
)
1349 vmcs_writel(field
, vmcs_readl(field
) | mask
);
1352 static inline void vm_entry_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1354 vmcs_write32(VM_ENTRY_CONTROLS
, val
);
1355 vmx
->vm_entry_controls_shadow
= val
;
1358 static inline void vm_entry_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1360 if (vmx
->vm_entry_controls_shadow
!= val
)
1361 vm_entry_controls_init(vmx
, val
);
1364 static inline u32
vm_entry_controls_get(struct vcpu_vmx
*vmx
)
1366 return vmx
->vm_entry_controls_shadow
;
1370 static inline void vm_entry_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1372 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) | val
);
1375 static inline void vm_entry_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1377 vm_entry_controls_set(vmx
, vm_entry_controls_get(vmx
) & ~val
);
1380 static inline void vm_exit_controls_init(struct vcpu_vmx
*vmx
, u32 val
)
1382 vmcs_write32(VM_EXIT_CONTROLS
, val
);
1383 vmx
->vm_exit_controls_shadow
= val
;
1386 static inline void vm_exit_controls_set(struct vcpu_vmx
*vmx
, u32 val
)
1388 if (vmx
->vm_exit_controls_shadow
!= val
)
1389 vm_exit_controls_init(vmx
, val
);
1392 static inline u32
vm_exit_controls_get(struct vcpu_vmx
*vmx
)
1394 return vmx
->vm_exit_controls_shadow
;
1398 static inline void vm_exit_controls_setbit(struct vcpu_vmx
*vmx
, u32 val
)
1400 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) | val
);
1403 static inline void vm_exit_controls_clearbit(struct vcpu_vmx
*vmx
, u32 val
)
1405 vm_exit_controls_set(vmx
, vm_exit_controls_get(vmx
) & ~val
);
1408 static void vmx_segment_cache_clear(struct vcpu_vmx
*vmx
)
1410 vmx
->segment_cache
.bitmask
= 0;
1413 static bool vmx_segment_cache_test_set(struct vcpu_vmx
*vmx
, unsigned seg
,
1417 u32 mask
= 1 << (seg
* SEG_FIELD_NR
+ field
);
1419 if (!(vmx
->vcpu
.arch
.regs_avail
& (1 << VCPU_EXREG_SEGMENTS
))) {
1420 vmx
->vcpu
.arch
.regs_avail
|= (1 << VCPU_EXREG_SEGMENTS
);
1421 vmx
->segment_cache
.bitmask
= 0;
1423 ret
= vmx
->segment_cache
.bitmask
& mask
;
1424 vmx
->segment_cache
.bitmask
|= mask
;
1428 static u16
vmx_read_guest_seg_selector(struct vcpu_vmx
*vmx
, unsigned seg
)
1430 u16
*p
= &vmx
->segment_cache
.seg
[seg
].selector
;
1432 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_SEL
))
1433 *p
= vmcs_read16(kvm_vmx_segment_fields
[seg
].selector
);
1437 static ulong
vmx_read_guest_seg_base(struct vcpu_vmx
*vmx
, unsigned seg
)
1439 ulong
*p
= &vmx
->segment_cache
.seg
[seg
].base
;
1441 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_BASE
))
1442 *p
= vmcs_readl(kvm_vmx_segment_fields
[seg
].base
);
1446 static u32
vmx_read_guest_seg_limit(struct vcpu_vmx
*vmx
, unsigned seg
)
1448 u32
*p
= &vmx
->segment_cache
.seg
[seg
].limit
;
1450 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_LIMIT
))
1451 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].limit
);
1455 static u32
vmx_read_guest_seg_ar(struct vcpu_vmx
*vmx
, unsigned seg
)
1457 u32
*p
= &vmx
->segment_cache
.seg
[seg
].ar
;
1459 if (!vmx_segment_cache_test_set(vmx
, seg
, SEG_FIELD_AR
))
1460 *p
= vmcs_read32(kvm_vmx_segment_fields
[seg
].ar_bytes
);
1464 static void update_exception_bitmap(struct kvm_vcpu
*vcpu
)
1468 eb
= (1u << PF_VECTOR
) | (1u << UD_VECTOR
) | (1u << MC_VECTOR
) |
1469 (1u << NM_VECTOR
) | (1u << DB_VECTOR
);
1470 if ((vcpu
->guest_debug
&
1471 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
)) ==
1472 (KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
))
1473 eb
|= 1u << BP_VECTOR
;
1474 if (to_vmx(vcpu
)->rmode
.vm86_active
)
1477 eb
&= ~(1u << PF_VECTOR
); /* bypass_guest_pf = 0 */
1478 if (vcpu
->fpu_active
)
1479 eb
&= ~(1u << NM_VECTOR
);
1481 /* When we are running a nested L2 guest and L1 specified for it a
1482 * certain exception bitmap, we must trap the same exceptions and pass
1483 * them to L1. When running L2, we will only handle the exceptions
1484 * specified above if L1 did not want them.
1486 if (is_guest_mode(vcpu
))
1487 eb
|= get_vmcs12(vcpu
)->exception_bitmap
;
1489 vmcs_write32(EXCEPTION_BITMAP
, eb
);
1492 static void clear_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1493 unsigned long entry
, unsigned long exit
)
1495 vm_entry_controls_clearbit(vmx
, entry
);
1496 vm_exit_controls_clearbit(vmx
, exit
);
1499 static void clear_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
)
1502 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1506 if (cpu_has_load_ia32_efer
) {
1507 clear_atomic_switch_msr_special(vmx
,
1508 VM_ENTRY_LOAD_IA32_EFER
,
1509 VM_EXIT_LOAD_IA32_EFER
);
1513 case MSR_CORE_PERF_GLOBAL_CTRL
:
1514 if (cpu_has_load_perf_global_ctrl
) {
1515 clear_atomic_switch_msr_special(vmx
,
1516 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1517 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
1523 for (i
= 0; i
< m
->nr
; ++i
)
1524 if (m
->guest
[i
].index
== msr
)
1530 m
->guest
[i
] = m
->guest
[m
->nr
];
1531 m
->host
[i
] = m
->host
[m
->nr
];
1532 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1533 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1536 static void add_atomic_switch_msr_special(struct vcpu_vmx
*vmx
,
1537 unsigned long entry
, unsigned long exit
,
1538 unsigned long guest_val_vmcs
, unsigned long host_val_vmcs
,
1539 u64 guest_val
, u64 host_val
)
1541 vmcs_write64(guest_val_vmcs
, guest_val
);
1542 vmcs_write64(host_val_vmcs
, host_val
);
1543 vm_entry_controls_setbit(vmx
, entry
);
1544 vm_exit_controls_setbit(vmx
, exit
);
1547 static void add_atomic_switch_msr(struct vcpu_vmx
*vmx
, unsigned msr
,
1548 u64 guest_val
, u64 host_val
)
1551 struct msr_autoload
*m
= &vmx
->msr_autoload
;
1555 if (cpu_has_load_ia32_efer
) {
1556 add_atomic_switch_msr_special(vmx
,
1557 VM_ENTRY_LOAD_IA32_EFER
,
1558 VM_EXIT_LOAD_IA32_EFER
,
1561 guest_val
, host_val
);
1565 case MSR_CORE_PERF_GLOBAL_CTRL
:
1566 if (cpu_has_load_perf_global_ctrl
) {
1567 add_atomic_switch_msr_special(vmx
,
1568 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
,
1569 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
,
1570 GUEST_IA32_PERF_GLOBAL_CTRL
,
1571 HOST_IA32_PERF_GLOBAL_CTRL
,
1572 guest_val
, host_val
);
1578 for (i
= 0; i
< m
->nr
; ++i
)
1579 if (m
->guest
[i
].index
== msr
)
1582 if (i
== NR_AUTOLOAD_MSRS
) {
1583 printk_once(KERN_WARNING
"Not enough msr switch entries. "
1584 "Can't add msr %x\n", msr
);
1586 } else if (i
== m
->nr
) {
1588 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, m
->nr
);
1589 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, m
->nr
);
1592 m
->guest
[i
].index
= msr
;
1593 m
->guest
[i
].value
= guest_val
;
1594 m
->host
[i
].index
= msr
;
1595 m
->host
[i
].value
= host_val
;
1598 static void reload_tss(void)
1601 * VT restores TR but not its size. Useless.
1603 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1604 struct desc_struct
*descs
;
1606 descs
= (void *)gdt
->address
;
1607 descs
[GDT_ENTRY_TSS
].type
= 9; /* available TSS */
1611 static bool update_transition_efer(struct vcpu_vmx
*vmx
, int efer_offset
)
1616 guest_efer
= vmx
->vcpu
.arch
.efer
;
1619 * NX is emulated; LMA and LME handled by hardware; SCE meaningless
1622 ignore_bits
= EFER_NX
| EFER_SCE
;
1623 #ifdef CONFIG_X86_64
1624 ignore_bits
|= EFER_LMA
| EFER_LME
;
1625 /* SCE is meaningful only in long mode on Intel */
1626 if (guest_efer
& EFER_LMA
)
1627 ignore_bits
&= ~(u64
)EFER_SCE
;
1629 guest_efer
&= ~ignore_bits
;
1630 guest_efer
|= host_efer
& ignore_bits
;
1631 vmx
->guest_msrs
[efer_offset
].data
= guest_efer
;
1632 vmx
->guest_msrs
[efer_offset
].mask
= ~ignore_bits
;
1634 clear_atomic_switch_msr(vmx
, MSR_EFER
);
1635 /* On ept, can't emulate nx, and must switch nx atomically */
1636 if (enable_ept
&& ((vmx
->vcpu
.arch
.efer
^ host_efer
) & EFER_NX
)) {
1637 guest_efer
= vmx
->vcpu
.arch
.efer
;
1638 if (!(guest_efer
& EFER_LMA
))
1639 guest_efer
&= ~EFER_LME
;
1640 add_atomic_switch_msr(vmx
, MSR_EFER
, guest_efer
, host_efer
);
1647 static unsigned long segment_base(u16 selector
)
1649 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1650 struct desc_struct
*d
;
1651 unsigned long table_base
;
1654 if (!(selector
& ~3))
1657 table_base
= gdt
->address
;
1659 if (selector
& 4) { /* from ldt */
1660 u16 ldt_selector
= kvm_read_ldt();
1662 if (!(ldt_selector
& ~3))
1665 table_base
= segment_base(ldt_selector
);
1667 d
= (struct desc_struct
*)(table_base
+ (selector
& ~7));
1668 v
= get_desc_base(d
);
1669 #ifdef CONFIG_X86_64
1670 if (d
->s
== 0 && (d
->type
== 2 || d
->type
== 9 || d
->type
== 11))
1671 v
|= ((unsigned long)((struct ldttss_desc64
*)d
)->base3
) << 32;
1676 static inline unsigned long kvm_read_tr_base(void)
1679 asm("str %0" : "=g"(tr
));
1680 return segment_base(tr
);
1683 static void vmx_save_host_state(struct kvm_vcpu
*vcpu
)
1685 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1688 if (vmx
->host_state
.loaded
)
1691 vmx
->host_state
.loaded
= 1;
1693 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1694 * allow segment selectors with cpl > 0 or ti == 1.
1696 vmx
->host_state
.ldt_sel
= kvm_read_ldt();
1697 vmx
->host_state
.gs_ldt_reload_needed
= vmx
->host_state
.ldt_sel
;
1698 savesegment(fs
, vmx
->host_state
.fs_sel
);
1699 if (!(vmx
->host_state
.fs_sel
& 7)) {
1700 vmcs_write16(HOST_FS_SELECTOR
, vmx
->host_state
.fs_sel
);
1701 vmx
->host_state
.fs_reload_needed
= 0;
1703 vmcs_write16(HOST_FS_SELECTOR
, 0);
1704 vmx
->host_state
.fs_reload_needed
= 1;
1706 savesegment(gs
, vmx
->host_state
.gs_sel
);
1707 if (!(vmx
->host_state
.gs_sel
& 7))
1708 vmcs_write16(HOST_GS_SELECTOR
, vmx
->host_state
.gs_sel
);
1710 vmcs_write16(HOST_GS_SELECTOR
, 0);
1711 vmx
->host_state
.gs_ldt_reload_needed
= 1;
1714 #ifdef CONFIG_X86_64
1715 savesegment(ds
, vmx
->host_state
.ds_sel
);
1716 savesegment(es
, vmx
->host_state
.es_sel
);
1719 #ifdef CONFIG_X86_64
1720 vmcs_writel(HOST_FS_BASE
, read_msr(MSR_FS_BASE
));
1721 vmcs_writel(HOST_GS_BASE
, read_msr(MSR_GS_BASE
));
1723 vmcs_writel(HOST_FS_BASE
, segment_base(vmx
->host_state
.fs_sel
));
1724 vmcs_writel(HOST_GS_BASE
, segment_base(vmx
->host_state
.gs_sel
));
1727 #ifdef CONFIG_X86_64
1728 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1729 if (is_long_mode(&vmx
->vcpu
))
1730 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1732 if (boot_cpu_has(X86_FEATURE_MPX
))
1733 rdmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1734 for (i
= 0; i
< vmx
->save_nmsrs
; ++i
)
1735 kvm_set_shared_msr(vmx
->guest_msrs
[i
].index
,
1736 vmx
->guest_msrs
[i
].data
,
1737 vmx
->guest_msrs
[i
].mask
);
1740 static void __vmx_load_host_state(struct vcpu_vmx
*vmx
)
1742 if (!vmx
->host_state
.loaded
)
1745 ++vmx
->vcpu
.stat
.host_state_reload
;
1746 vmx
->host_state
.loaded
= 0;
1747 #ifdef CONFIG_X86_64
1748 if (is_long_mode(&vmx
->vcpu
))
1749 rdmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_guest_kernel_gs_base
);
1751 if (vmx
->host_state
.gs_ldt_reload_needed
) {
1752 kvm_load_ldt(vmx
->host_state
.ldt_sel
);
1753 #ifdef CONFIG_X86_64
1754 load_gs_index(vmx
->host_state
.gs_sel
);
1756 loadsegment(gs
, vmx
->host_state
.gs_sel
);
1759 if (vmx
->host_state
.fs_reload_needed
)
1760 loadsegment(fs
, vmx
->host_state
.fs_sel
);
1761 #ifdef CONFIG_X86_64
1762 if (unlikely(vmx
->host_state
.ds_sel
| vmx
->host_state
.es_sel
)) {
1763 loadsegment(ds
, vmx
->host_state
.ds_sel
);
1764 loadsegment(es
, vmx
->host_state
.es_sel
);
1768 #ifdef CONFIG_X86_64
1769 wrmsrl(MSR_KERNEL_GS_BASE
, vmx
->msr_host_kernel_gs_base
);
1771 if (vmx
->host_state
.msr_host_bndcfgs
)
1772 wrmsrl(MSR_IA32_BNDCFGS
, vmx
->host_state
.msr_host_bndcfgs
);
1774 * If the FPU is not active (through the host task or
1775 * the guest vcpu), then restore the cr0.TS bit.
1777 if (!user_has_fpu() && !vmx
->vcpu
.guest_fpu_loaded
)
1779 load_gdt(&__get_cpu_var(host_gdt
));
1782 static void vmx_load_host_state(struct vcpu_vmx
*vmx
)
1785 __vmx_load_host_state(vmx
);
1790 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1791 * vcpu mutex is already taken.
1793 static void vmx_vcpu_load(struct kvm_vcpu
*vcpu
, int cpu
)
1795 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
1796 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
1799 kvm_cpu_vmxon(phys_addr
);
1800 else if (vmx
->loaded_vmcs
->cpu
!= cpu
)
1801 loaded_vmcs_clear(vmx
->loaded_vmcs
);
1803 if (per_cpu(current_vmcs
, cpu
) != vmx
->loaded_vmcs
->vmcs
) {
1804 per_cpu(current_vmcs
, cpu
) = vmx
->loaded_vmcs
->vmcs
;
1805 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
1808 if (vmx
->loaded_vmcs
->cpu
!= cpu
) {
1809 struct desc_ptr
*gdt
= &__get_cpu_var(host_gdt
);
1810 unsigned long sysenter_esp
;
1812 kvm_make_request(KVM_REQ_TLB_FLUSH
, vcpu
);
1813 local_irq_disable();
1814 crash_disable_local_vmclear(cpu
);
1817 * Read loaded_vmcs->cpu should be before fetching
1818 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1819 * See the comments in __loaded_vmcs_clear().
1823 list_add(&vmx
->loaded_vmcs
->loaded_vmcss_on_cpu_link
,
1824 &per_cpu(loaded_vmcss_on_cpu
, cpu
));
1825 crash_enable_local_vmclear(cpu
);
1829 * Linux uses per-cpu TSS and GDT, so set these when switching
1832 vmcs_writel(HOST_TR_BASE
, kvm_read_tr_base()); /* 22.2.4 */
1833 vmcs_writel(HOST_GDTR_BASE
, gdt
->address
); /* 22.2.4 */
1835 rdmsrl(MSR_IA32_SYSENTER_ESP
, sysenter_esp
);
1836 vmcs_writel(HOST_IA32_SYSENTER_ESP
, sysenter_esp
); /* 22.2.3 */
1837 vmx
->loaded_vmcs
->cpu
= cpu
;
1841 static void vmx_vcpu_put(struct kvm_vcpu
*vcpu
)
1843 __vmx_load_host_state(to_vmx(vcpu
));
1844 if (!vmm_exclusive
) {
1845 __loaded_vmcs_clear(to_vmx(vcpu
)->loaded_vmcs
);
1851 static void vmx_fpu_activate(struct kvm_vcpu
*vcpu
)
1855 if (vcpu
->fpu_active
)
1857 vcpu
->fpu_active
= 1;
1858 cr0
= vmcs_readl(GUEST_CR0
);
1859 cr0
&= ~(X86_CR0_TS
| X86_CR0_MP
);
1860 cr0
|= kvm_read_cr0_bits(vcpu
, X86_CR0_TS
| X86_CR0_MP
);
1861 vmcs_writel(GUEST_CR0
, cr0
);
1862 update_exception_bitmap(vcpu
);
1863 vcpu
->arch
.cr0_guest_owned_bits
= X86_CR0_TS
;
1864 if (is_guest_mode(vcpu
))
1865 vcpu
->arch
.cr0_guest_owned_bits
&=
1866 ~get_vmcs12(vcpu
)->cr0_guest_host_mask
;
1867 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1870 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
);
1873 * Return the cr0 value that a nested guest would read. This is a combination
1874 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1875 * its hypervisor (cr0_read_shadow).
1877 static inline unsigned long nested_read_cr0(struct vmcs12
*fields
)
1879 return (fields
->guest_cr0
& ~fields
->cr0_guest_host_mask
) |
1880 (fields
->cr0_read_shadow
& fields
->cr0_guest_host_mask
);
1882 static inline unsigned long nested_read_cr4(struct vmcs12
*fields
)
1884 return (fields
->guest_cr4
& ~fields
->cr4_guest_host_mask
) |
1885 (fields
->cr4_read_shadow
& fields
->cr4_guest_host_mask
);
1888 static void vmx_fpu_deactivate(struct kvm_vcpu
*vcpu
)
1890 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1891 * set this *before* calling this function.
1893 vmx_decache_cr0_guest_bits(vcpu
);
1894 vmcs_set_bits(GUEST_CR0
, X86_CR0_TS
| X86_CR0_MP
);
1895 update_exception_bitmap(vcpu
);
1896 vcpu
->arch
.cr0_guest_owned_bits
= 0;
1897 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
1898 if (is_guest_mode(vcpu
)) {
1900 * L1's specified read shadow might not contain the TS bit,
1901 * so now that we turned on shadowing of this bit, we need to
1902 * set this bit of the shadow. Like in nested_vmx_run we need
1903 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1904 * up-to-date here because we just decached cr0.TS (and we'll
1905 * only update vmcs12->guest_cr0 on nested exit).
1907 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1908 vmcs12
->guest_cr0
= (vmcs12
->guest_cr0
& ~X86_CR0_TS
) |
1909 (vcpu
->arch
.cr0
& X86_CR0_TS
);
1910 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
1912 vmcs_writel(CR0_READ_SHADOW
, vcpu
->arch
.cr0
);
1915 static unsigned long vmx_get_rflags(struct kvm_vcpu
*vcpu
)
1917 unsigned long rflags
, save_rflags
;
1919 if (!test_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
)) {
1920 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1921 rflags
= vmcs_readl(GUEST_RFLAGS
);
1922 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1923 rflags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
1924 save_rflags
= to_vmx(vcpu
)->rmode
.save_rflags
;
1925 rflags
|= save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
1927 to_vmx(vcpu
)->rflags
= rflags
;
1929 return to_vmx(vcpu
)->rflags
;
1932 static void vmx_set_rflags(struct kvm_vcpu
*vcpu
, unsigned long rflags
)
1934 __set_bit(VCPU_EXREG_RFLAGS
, (ulong
*)&vcpu
->arch
.regs_avail
);
1935 to_vmx(vcpu
)->rflags
= rflags
;
1936 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
1937 to_vmx(vcpu
)->rmode
.save_rflags
= rflags
;
1938 rflags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
1940 vmcs_writel(GUEST_RFLAGS
, rflags
);
1943 static u32
vmx_get_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1945 u32 interruptibility
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1948 if (interruptibility
& GUEST_INTR_STATE_STI
)
1949 ret
|= KVM_X86_SHADOW_INT_STI
;
1950 if (interruptibility
& GUEST_INTR_STATE_MOV_SS
)
1951 ret
|= KVM_X86_SHADOW_INT_MOV_SS
;
1956 static void vmx_set_interrupt_shadow(struct kvm_vcpu
*vcpu
, int mask
)
1958 u32 interruptibility_old
= vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
1959 u32 interruptibility
= interruptibility_old
;
1961 interruptibility
&= ~(GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
);
1963 if (mask
& KVM_X86_SHADOW_INT_MOV_SS
)
1964 interruptibility
|= GUEST_INTR_STATE_MOV_SS
;
1965 else if (mask
& KVM_X86_SHADOW_INT_STI
)
1966 interruptibility
|= GUEST_INTR_STATE_STI
;
1968 if ((interruptibility
!= interruptibility_old
))
1969 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, interruptibility
);
1972 static void skip_emulated_instruction(struct kvm_vcpu
*vcpu
)
1976 rip
= kvm_rip_read(vcpu
);
1977 rip
+= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
1978 kvm_rip_write(vcpu
, rip
);
1980 /* skipping an emulated instruction also counts */
1981 vmx_set_interrupt_shadow(vcpu
, 0);
1985 * KVM wants to inject page-faults which it got to the guest. This function
1986 * checks whether in a nested guest, we need to inject them to L1 or L2.
1988 static int nested_vmx_check_exception(struct kvm_vcpu
*vcpu
, unsigned nr
)
1990 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
1992 if (!(vmcs12
->exception_bitmap
& (1u << nr
)))
1995 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
1996 vmcs_read32(VM_EXIT_INTR_INFO
),
1997 vmcs_readl(EXIT_QUALIFICATION
));
2001 static void vmx_queue_exception(struct kvm_vcpu
*vcpu
, unsigned nr
,
2002 bool has_error_code
, u32 error_code
,
2005 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2006 u32 intr_info
= nr
| INTR_INFO_VALID_MASK
;
2008 if (!reinject
&& is_guest_mode(vcpu
) &&
2009 nested_vmx_check_exception(vcpu
, nr
))
2012 if (has_error_code
) {
2013 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
, error_code
);
2014 intr_info
|= INTR_INFO_DELIVER_CODE_MASK
;
2017 if (vmx
->rmode
.vm86_active
) {
2019 if (kvm_exception_is_soft(nr
))
2020 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
2021 if (kvm_inject_realmode_interrupt(vcpu
, nr
, inc_eip
) != EMULATE_DONE
)
2022 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
2026 if (kvm_exception_is_soft(nr
)) {
2027 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
2028 vmx
->vcpu
.arch
.event_exit_inst_len
);
2029 intr_info
|= INTR_TYPE_SOFT_EXCEPTION
;
2031 intr_info
|= INTR_TYPE_HARD_EXCEPTION
;
2033 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr_info
);
2036 static bool vmx_rdtscp_supported(void)
2038 return cpu_has_vmx_rdtscp();
2041 static bool vmx_invpcid_supported(void)
2043 return cpu_has_vmx_invpcid() && enable_ept
;
2047 * Swap MSR entry in host/guest MSR entry array.
2049 static void move_msr_up(struct vcpu_vmx
*vmx
, int from
, int to
)
2051 struct shared_msr_entry tmp
;
2053 tmp
= vmx
->guest_msrs
[to
];
2054 vmx
->guest_msrs
[to
] = vmx
->guest_msrs
[from
];
2055 vmx
->guest_msrs
[from
] = tmp
;
2058 static void vmx_set_msr_bitmap(struct kvm_vcpu
*vcpu
)
2060 unsigned long *msr_bitmap
;
2062 if (irqchip_in_kernel(vcpu
->kvm
) && apic_x2apic_mode(vcpu
->arch
.apic
)) {
2063 if (is_long_mode(vcpu
))
2064 msr_bitmap
= vmx_msr_bitmap_longmode_x2apic
;
2066 msr_bitmap
= vmx_msr_bitmap_legacy_x2apic
;
2068 if (is_long_mode(vcpu
))
2069 msr_bitmap
= vmx_msr_bitmap_longmode
;
2071 msr_bitmap
= vmx_msr_bitmap_legacy
;
2074 vmcs_write64(MSR_BITMAP
, __pa(msr_bitmap
));
2078 * Set up the vmcs to automatically save and restore system
2079 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
2080 * mode, as fiddling with msrs is very expensive.
2082 static void setup_msrs(struct vcpu_vmx
*vmx
)
2084 int save_nmsrs
, index
;
2087 #ifdef CONFIG_X86_64
2088 if (is_long_mode(&vmx
->vcpu
)) {
2089 index
= __find_msr_index(vmx
, MSR_SYSCALL_MASK
);
2091 move_msr_up(vmx
, index
, save_nmsrs
++);
2092 index
= __find_msr_index(vmx
, MSR_LSTAR
);
2094 move_msr_up(vmx
, index
, save_nmsrs
++);
2095 index
= __find_msr_index(vmx
, MSR_CSTAR
);
2097 move_msr_up(vmx
, index
, save_nmsrs
++);
2098 index
= __find_msr_index(vmx
, MSR_TSC_AUX
);
2099 if (index
>= 0 && vmx
->rdtscp_enabled
)
2100 move_msr_up(vmx
, index
, save_nmsrs
++);
2102 * MSR_STAR is only needed on long mode guests, and only
2103 * if efer.sce is enabled.
2105 index
= __find_msr_index(vmx
, MSR_STAR
);
2106 if ((index
>= 0) && (vmx
->vcpu
.arch
.efer
& EFER_SCE
))
2107 move_msr_up(vmx
, index
, save_nmsrs
++);
2110 index
= __find_msr_index(vmx
, MSR_EFER
);
2111 if (index
>= 0 && update_transition_efer(vmx
, index
))
2112 move_msr_up(vmx
, index
, save_nmsrs
++);
2114 vmx
->save_nmsrs
= save_nmsrs
;
2116 if (cpu_has_vmx_msr_bitmap())
2117 vmx_set_msr_bitmap(&vmx
->vcpu
);
2121 * reads and returns guest's timestamp counter "register"
2122 * guest_tsc = host_tsc + tsc_offset -- 21.3
2124 static u64
guest_read_tsc(void)
2126 u64 host_tsc
, tsc_offset
;
2129 tsc_offset
= vmcs_read64(TSC_OFFSET
);
2130 return host_tsc
+ tsc_offset
;
2134 * Like guest_read_tsc, but always returns L1's notion of the timestamp
2135 * counter, even if a nested guest (L2) is currently running.
2137 u64
vmx_read_l1_tsc(struct kvm_vcpu
*vcpu
, u64 host_tsc
)
2141 tsc_offset
= is_guest_mode(vcpu
) ?
2142 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
:
2143 vmcs_read64(TSC_OFFSET
);
2144 return host_tsc
+ tsc_offset
;
2148 * Engage any workarounds for mis-matched TSC rates. Currently limited to
2149 * software catchup for faster rates on slower CPUs.
2151 static void vmx_set_tsc_khz(struct kvm_vcpu
*vcpu
, u32 user_tsc_khz
, bool scale
)
2156 if (user_tsc_khz
> tsc_khz
) {
2157 vcpu
->arch
.tsc_catchup
= 1;
2158 vcpu
->arch
.tsc_always_catchup
= 1;
2160 WARN(1, "user requested TSC rate below hardware speed\n");
2163 static u64
vmx_read_tsc_offset(struct kvm_vcpu
*vcpu
)
2165 return vmcs_read64(TSC_OFFSET
);
2169 * writes 'offset' into guest's timestamp counter offset register
2171 static void vmx_write_tsc_offset(struct kvm_vcpu
*vcpu
, u64 offset
)
2173 if (is_guest_mode(vcpu
)) {
2175 * We're here if L1 chose not to trap WRMSR to TSC. According
2176 * to the spec, this should set L1's TSC; The offset that L1
2177 * set for L2 remains unchanged, and still needs to be added
2178 * to the newly set TSC to get L2's TSC.
2180 struct vmcs12
*vmcs12
;
2181 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
= offset
;
2182 /* recalculate vmcs02.TSC_OFFSET: */
2183 vmcs12
= get_vmcs12(vcpu
);
2184 vmcs_write64(TSC_OFFSET
, offset
+
2185 (nested_cpu_has(vmcs12
, CPU_BASED_USE_TSC_OFFSETING
) ?
2186 vmcs12
->tsc_offset
: 0));
2188 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
,
2189 vmcs_read64(TSC_OFFSET
), offset
);
2190 vmcs_write64(TSC_OFFSET
, offset
);
2194 static void vmx_adjust_tsc_offset(struct kvm_vcpu
*vcpu
, s64 adjustment
, bool host
)
2196 u64 offset
= vmcs_read64(TSC_OFFSET
);
2198 vmcs_write64(TSC_OFFSET
, offset
+ adjustment
);
2199 if (is_guest_mode(vcpu
)) {
2200 /* Even when running L2, the adjustment needs to apply to L1 */
2201 to_vmx(vcpu
)->nested
.vmcs01_tsc_offset
+= adjustment
;
2203 trace_kvm_write_tsc_offset(vcpu
->vcpu_id
, offset
,
2204 offset
+ adjustment
);
2207 static u64
vmx_compute_tsc_offset(struct kvm_vcpu
*vcpu
, u64 target_tsc
)
2209 return target_tsc
- native_read_tsc();
2212 static bool guest_cpuid_has_vmx(struct kvm_vcpu
*vcpu
)
2214 struct kvm_cpuid_entry2
*best
= kvm_find_cpuid_entry(vcpu
, 1, 0);
2215 return best
&& (best
->ecx
& (1 << (X86_FEATURE_VMX
& 31)));
2219 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2220 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2221 * all guests if the "nested" module option is off, and can also be disabled
2222 * for a single guest by disabling its VMX cpuid bit.
2224 static inline bool nested_vmx_allowed(struct kvm_vcpu
*vcpu
)
2226 return nested
&& guest_cpuid_has_vmx(vcpu
);
2230 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2231 * returned for the various VMX controls MSRs when nested VMX is enabled.
2232 * The same values should also be used to verify that vmcs12 control fields are
2233 * valid during nested entry from L1 to L2.
2234 * Each of these control msrs has a low and high 32-bit half: A low bit is on
2235 * if the corresponding bit in the (32-bit) control field *must* be on, and a
2236 * bit in the high half is on if the corresponding bit in the control field
2237 * may be on. See also vmx_control_verify().
2238 * TODO: allow these variables to be modified (downgraded) by module options
2241 static u32 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
;
2242 static u32 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
;
2243 static u32 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
;
2244 static u32 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
;
2245 static u32 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
;
2246 static u32 nested_vmx_misc_low
, nested_vmx_misc_high
;
2247 static u32 nested_vmx_ept_caps
;
2248 static __init
void nested_vmx_setup_ctls_msrs(void)
2251 * Note that as a general rule, the high half of the MSRs (bits in
2252 * the control fields which may be 1) should be initialized by the
2253 * intersection of the underlying hardware's MSR (i.e., features which
2254 * can be supported) and the list of features we want to expose -
2255 * because they are known to be properly supported in our code.
2256 * Also, usually, the low half of the MSRs (bits which must be 1) can
2257 * be set to 0, meaning that L1 may turn off any of these bits. The
2258 * reason is that if one of these bits is necessary, it will appear
2259 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2260 * fields of vmcs01 and vmcs02, will turn these bits off - and
2261 * nested_vmx_exit_handled() will not pass related exits to L1.
2262 * These rules have exceptions below.
2265 /* pin-based controls */
2266 rdmsr(MSR_IA32_VMX_PINBASED_CTLS
,
2267 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
);
2269 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
2270 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
2272 nested_vmx_pinbased_ctls_low
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
;
2273 nested_vmx_pinbased_ctls_high
&= PIN_BASED_EXT_INTR_MASK
|
2274 PIN_BASED_NMI_EXITING
| PIN_BASED_VIRTUAL_NMIS
;
2275 nested_vmx_pinbased_ctls_high
|= PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR
|
2276 PIN_BASED_VMX_PREEMPTION_TIMER
;
2280 * If bit 55 of VMX_BASIC is off, bits 0-8 and 10, 11, 13, 14, 16 and
2283 rdmsr(MSR_IA32_VMX_EXIT_CTLS
,
2284 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
);
2285 nested_vmx_exit_ctls_low
= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
;
2287 nested_vmx_exit_ctls_high
&=
2288 #ifdef CONFIG_X86_64
2289 VM_EXIT_HOST_ADDR_SPACE_SIZE
|
2291 VM_EXIT_LOAD_IA32_PAT
| VM_EXIT_SAVE_IA32_PAT
;
2292 nested_vmx_exit_ctls_high
|= VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR
|
2293 VM_EXIT_LOAD_IA32_EFER
| VM_EXIT_SAVE_IA32_EFER
|
2294 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
| VM_EXIT_ACK_INTR_ON_EXIT
;
2296 if (vmx_mpx_supported())
2297 nested_vmx_exit_ctls_high
|= VM_EXIT_CLEAR_BNDCFGS
;
2299 /* entry controls */
2300 rdmsr(MSR_IA32_VMX_ENTRY_CTLS
,
2301 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
);
2302 /* If bit 55 of VMX_BASIC is off, bits 0-8 and 12 must be 1. */
2303 nested_vmx_entry_ctls_low
= VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
;
2304 nested_vmx_entry_ctls_high
&=
2305 #ifdef CONFIG_X86_64
2306 VM_ENTRY_IA32E_MODE
|
2308 VM_ENTRY_LOAD_IA32_PAT
;
2309 nested_vmx_entry_ctls_high
|= (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR
|
2310 VM_ENTRY_LOAD_IA32_EFER
);
2311 if (vmx_mpx_supported())
2312 nested_vmx_entry_ctls_high
|= VM_ENTRY_LOAD_BNDCFGS
;
2314 /* cpu-based controls */
2315 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS
,
2316 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
);
2317 nested_vmx_procbased_ctls_low
= 0;
2318 nested_vmx_procbased_ctls_high
&=
2319 CPU_BASED_VIRTUAL_INTR_PENDING
|
2320 CPU_BASED_VIRTUAL_NMI_PENDING
| CPU_BASED_USE_TSC_OFFSETING
|
2321 CPU_BASED_HLT_EXITING
| CPU_BASED_INVLPG_EXITING
|
2322 CPU_BASED_MWAIT_EXITING
| CPU_BASED_CR3_LOAD_EXITING
|
2323 CPU_BASED_CR3_STORE_EXITING
|
2324 #ifdef CONFIG_X86_64
2325 CPU_BASED_CR8_LOAD_EXITING
| CPU_BASED_CR8_STORE_EXITING
|
2327 CPU_BASED_MOV_DR_EXITING
| CPU_BASED_UNCOND_IO_EXITING
|
2328 CPU_BASED_USE_IO_BITMAPS
| CPU_BASED_MONITOR_EXITING
|
2329 CPU_BASED_RDPMC_EXITING
| CPU_BASED_RDTSC_EXITING
|
2330 CPU_BASED_PAUSE_EXITING
|
2331 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2333 * We can allow some features even when not supported by the
2334 * hardware. For example, L1 can specify an MSR bitmap - and we
2335 * can use it to avoid exits to L1 - even when L0 runs L2
2336 * without MSR bitmaps.
2338 nested_vmx_procbased_ctls_high
|= CPU_BASED_USE_MSR_BITMAPS
;
2340 /* secondary cpu-based controls */
2341 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2
,
2342 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
);
2343 nested_vmx_secondary_ctls_low
= 0;
2344 nested_vmx_secondary_ctls_high
&=
2345 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2346 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2347 SECONDARY_EXEC_WBINVD_EXITING
;
2350 /* nested EPT: emulate EPT also to L1 */
2351 nested_vmx_secondary_ctls_high
|= SECONDARY_EXEC_ENABLE_EPT
;
2352 nested_vmx_ept_caps
= VMX_EPT_PAGE_WALK_4_BIT
|
2353 VMX_EPTP_WB_BIT
| VMX_EPT_2MB_PAGE_BIT
|
2355 nested_vmx_ept_caps
&= vmx_capability
.ept
;
2357 * For nested guests, we don't do anything specific
2358 * for single context invalidation. Hence, only advertise
2359 * support for global context invalidation.
2361 nested_vmx_ept_caps
|= VMX_EPT_EXTENT_GLOBAL_BIT
;
2363 nested_vmx_ept_caps
= 0;
2365 /* miscellaneous data */
2366 rdmsr(MSR_IA32_VMX_MISC
, nested_vmx_misc_low
, nested_vmx_misc_high
);
2367 nested_vmx_misc_low
&= VMX_MISC_SAVE_EFER_LMA
;
2368 nested_vmx_misc_low
|= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
|
2369 VMX_MISC_ACTIVITY_HLT
;
2370 nested_vmx_misc_high
= 0;
2373 static inline bool vmx_control_verify(u32 control
, u32 low
, u32 high
)
2376 * Bits 0 in high must be 0, and bits 1 in low must be 1.
2378 return ((control
& high
) | low
) == control
;
2381 static inline u64
vmx_control_msr(u32 low
, u32 high
)
2383 return low
| ((u64
)high
<< 32);
2386 /* Returns 0 on success, non-0 otherwise. */
2387 static int vmx_get_vmx_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2389 switch (msr_index
) {
2390 case MSR_IA32_VMX_BASIC
:
2392 * This MSR reports some information about VMX support. We
2393 * should return information about the VMX we emulate for the
2394 * guest, and the VMCS structure we give it - not about the
2395 * VMX support of the underlying hardware.
2397 *pdata
= VMCS12_REVISION
|
2398 ((u64
)VMCS12_SIZE
<< VMX_BASIC_VMCS_SIZE_SHIFT
) |
2399 (VMX_BASIC_MEM_TYPE_WB
<< VMX_BASIC_MEM_TYPE_SHIFT
);
2401 case MSR_IA32_VMX_TRUE_PINBASED_CTLS
:
2402 case MSR_IA32_VMX_PINBASED_CTLS
:
2403 *pdata
= vmx_control_msr(nested_vmx_pinbased_ctls_low
,
2404 nested_vmx_pinbased_ctls_high
);
2406 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS
:
2407 case MSR_IA32_VMX_PROCBASED_CTLS
:
2408 *pdata
= vmx_control_msr(nested_vmx_procbased_ctls_low
,
2409 nested_vmx_procbased_ctls_high
);
2411 case MSR_IA32_VMX_TRUE_EXIT_CTLS
:
2412 case MSR_IA32_VMX_EXIT_CTLS
:
2413 *pdata
= vmx_control_msr(nested_vmx_exit_ctls_low
,
2414 nested_vmx_exit_ctls_high
);
2416 case MSR_IA32_VMX_TRUE_ENTRY_CTLS
:
2417 case MSR_IA32_VMX_ENTRY_CTLS
:
2418 *pdata
= vmx_control_msr(nested_vmx_entry_ctls_low
,
2419 nested_vmx_entry_ctls_high
);
2421 case MSR_IA32_VMX_MISC
:
2422 *pdata
= vmx_control_msr(nested_vmx_misc_low
,
2423 nested_vmx_misc_high
);
2426 * These MSRs specify bits which the guest must keep fixed (on or off)
2427 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2428 * We picked the standard core2 setting.
2430 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2431 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2432 case MSR_IA32_VMX_CR0_FIXED0
:
2433 *pdata
= VMXON_CR0_ALWAYSON
;
2435 case MSR_IA32_VMX_CR0_FIXED1
:
2438 case MSR_IA32_VMX_CR4_FIXED0
:
2439 *pdata
= VMXON_CR4_ALWAYSON
;
2441 case MSR_IA32_VMX_CR4_FIXED1
:
2444 case MSR_IA32_VMX_VMCS_ENUM
:
2447 case MSR_IA32_VMX_PROCBASED_CTLS2
:
2448 *pdata
= vmx_control_msr(nested_vmx_secondary_ctls_low
,
2449 nested_vmx_secondary_ctls_high
);
2451 case MSR_IA32_VMX_EPT_VPID_CAP
:
2452 /* Currently, no nested vpid support */
2453 *pdata
= nested_vmx_ept_caps
;
2463 * Reads an msr value (of 'msr_index') into 'pdata'.
2464 * Returns 0 on success, non-0 otherwise.
2465 * Assumes vcpu_load() was already called.
2467 static int vmx_get_msr(struct kvm_vcpu
*vcpu
, u32 msr_index
, u64
*pdata
)
2470 struct shared_msr_entry
*msr
;
2473 printk(KERN_ERR
"BUG: get_msr called with NULL pdata\n");
2477 switch (msr_index
) {
2478 #ifdef CONFIG_X86_64
2480 data
= vmcs_readl(GUEST_FS_BASE
);
2483 data
= vmcs_readl(GUEST_GS_BASE
);
2485 case MSR_KERNEL_GS_BASE
:
2486 vmx_load_host_state(to_vmx(vcpu
));
2487 data
= to_vmx(vcpu
)->msr_guest_kernel_gs_base
;
2491 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2493 data
= guest_read_tsc();
2495 case MSR_IA32_SYSENTER_CS
:
2496 data
= vmcs_read32(GUEST_SYSENTER_CS
);
2498 case MSR_IA32_SYSENTER_EIP
:
2499 data
= vmcs_readl(GUEST_SYSENTER_EIP
);
2501 case MSR_IA32_SYSENTER_ESP
:
2502 data
= vmcs_readl(GUEST_SYSENTER_ESP
);
2504 case MSR_IA32_BNDCFGS
:
2505 if (!vmx_mpx_supported())
2507 data
= vmcs_read64(GUEST_BNDCFGS
);
2509 case MSR_IA32_FEATURE_CONTROL
:
2510 if (!nested_vmx_allowed(vcpu
))
2512 data
= to_vmx(vcpu
)->nested
.msr_ia32_feature_control
;
2514 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2515 if (!nested_vmx_allowed(vcpu
))
2517 return vmx_get_vmx_msr(vcpu
, msr_index
, pdata
);
2519 if (!to_vmx(vcpu
)->rdtscp_enabled
)
2521 /* Otherwise falls through */
2523 msr
= find_msr_entry(to_vmx(vcpu
), msr_index
);
2528 return kvm_get_msr_common(vcpu
, msr_index
, pdata
);
2535 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
);
2538 * Writes msr value into into the appropriate "register".
2539 * Returns 0 on success, non-0 otherwise.
2540 * Assumes vcpu_load() was already called.
2542 static int vmx_set_msr(struct kvm_vcpu
*vcpu
, struct msr_data
*msr_info
)
2544 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
2545 struct shared_msr_entry
*msr
;
2547 u32 msr_index
= msr_info
->index
;
2548 u64 data
= msr_info
->data
;
2550 switch (msr_index
) {
2552 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2554 #ifdef CONFIG_X86_64
2556 vmx_segment_cache_clear(vmx
);
2557 vmcs_writel(GUEST_FS_BASE
, data
);
2560 vmx_segment_cache_clear(vmx
);
2561 vmcs_writel(GUEST_GS_BASE
, data
);
2563 case MSR_KERNEL_GS_BASE
:
2564 vmx_load_host_state(vmx
);
2565 vmx
->msr_guest_kernel_gs_base
= data
;
2568 case MSR_IA32_SYSENTER_CS
:
2569 vmcs_write32(GUEST_SYSENTER_CS
, data
);
2571 case MSR_IA32_SYSENTER_EIP
:
2572 vmcs_writel(GUEST_SYSENTER_EIP
, data
);
2574 case MSR_IA32_SYSENTER_ESP
:
2575 vmcs_writel(GUEST_SYSENTER_ESP
, data
);
2577 case MSR_IA32_BNDCFGS
:
2578 if (!vmx_mpx_supported())
2580 vmcs_write64(GUEST_BNDCFGS
, data
);
2583 kvm_write_tsc(vcpu
, msr_info
);
2585 case MSR_IA32_CR_PAT
:
2586 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
2587 vmcs_write64(GUEST_IA32_PAT
, data
);
2588 vcpu
->arch
.pat
= data
;
2591 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2593 case MSR_IA32_TSC_ADJUST
:
2594 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2596 case MSR_IA32_FEATURE_CONTROL
:
2597 if (!nested_vmx_allowed(vcpu
) ||
2598 (to_vmx(vcpu
)->nested
.msr_ia32_feature_control
&
2599 FEATURE_CONTROL_LOCKED
&& !msr_info
->host_initiated
))
2601 vmx
->nested
.msr_ia32_feature_control
= data
;
2602 if (msr_info
->host_initiated
&& data
== 0)
2603 vmx_leave_nested(vcpu
);
2605 case MSR_IA32_VMX_BASIC
... MSR_IA32_VMX_VMFUNC
:
2606 return 1; /* they are read-only */
2608 if (!vmx
->rdtscp_enabled
)
2610 /* Check reserved bit, higher 32 bits should be zero */
2611 if ((data
>> 32) != 0)
2613 /* Otherwise falls through */
2615 msr
= find_msr_entry(vmx
, msr_index
);
2618 if (msr
- vmx
->guest_msrs
< vmx
->save_nmsrs
) {
2620 kvm_set_shared_msr(msr
->index
, msr
->data
,
2626 ret
= kvm_set_msr_common(vcpu
, msr_info
);
2632 static void vmx_cache_reg(struct kvm_vcpu
*vcpu
, enum kvm_reg reg
)
2634 __set_bit(reg
, (unsigned long *)&vcpu
->arch
.regs_avail
);
2637 vcpu
->arch
.regs
[VCPU_REGS_RSP
] = vmcs_readl(GUEST_RSP
);
2640 vcpu
->arch
.regs
[VCPU_REGS_RIP
] = vmcs_readl(GUEST_RIP
);
2642 case VCPU_EXREG_PDPTR
:
2644 ept_save_pdptrs(vcpu
);
2651 static __init
int cpu_has_kvm_support(void)
2653 return cpu_has_vmx();
2656 static __init
int vmx_disabled_by_bios(void)
2660 rdmsrl(MSR_IA32_FEATURE_CONTROL
, msr
);
2661 if (msr
& FEATURE_CONTROL_LOCKED
) {
2662 /* launched w/ TXT and VMX disabled */
2663 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2666 /* launched w/o TXT and VMX only enabled w/ TXT */
2667 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2668 && (msr
& FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
)
2669 && !tboot_enabled()) {
2670 printk(KERN_WARNING
"kvm: disable TXT in the BIOS or "
2671 "activate TXT before enabling KVM\n");
2674 /* launched w/o TXT and VMX disabled */
2675 if (!(msr
& FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
)
2676 && !tboot_enabled())
2683 static void kvm_cpu_vmxon(u64 addr
)
2685 asm volatile (ASM_VMX_VMXON_RAX
2686 : : "a"(&addr
), "m"(addr
)
2690 static int hardware_enable(void *garbage
)
2692 int cpu
= raw_smp_processor_id();
2693 u64 phys_addr
= __pa(per_cpu(vmxarea
, cpu
));
2696 if (read_cr4() & X86_CR4_VMXE
)
2699 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu
, cpu
));
2702 * Now we can enable the vmclear operation in kdump
2703 * since the loaded_vmcss_on_cpu list on this cpu
2704 * has been initialized.
2706 * Though the cpu is not in VMX operation now, there
2707 * is no problem to enable the vmclear operation
2708 * for the loaded_vmcss_on_cpu list is empty!
2710 crash_enable_local_vmclear(cpu
);
2712 rdmsrl(MSR_IA32_FEATURE_CONTROL
, old
);
2714 test_bits
= FEATURE_CONTROL_LOCKED
;
2715 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
2716 if (tboot_enabled())
2717 test_bits
|= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX
;
2719 if ((old
& test_bits
) != test_bits
) {
2720 /* enable and lock */
2721 wrmsrl(MSR_IA32_FEATURE_CONTROL
, old
| test_bits
);
2723 write_cr4(read_cr4() | X86_CR4_VMXE
); /* FIXME: not cpu hotplug safe */
2725 if (vmm_exclusive
) {
2726 kvm_cpu_vmxon(phys_addr
);
2730 native_store_gdt(&__get_cpu_var(host_gdt
));
2735 static void vmclear_local_loaded_vmcss(void)
2737 int cpu
= raw_smp_processor_id();
2738 struct loaded_vmcs
*v
, *n
;
2740 list_for_each_entry_safe(v
, n
, &per_cpu(loaded_vmcss_on_cpu
, cpu
),
2741 loaded_vmcss_on_cpu_link
)
2742 __loaded_vmcs_clear(v
);
2746 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2749 static void kvm_cpu_vmxoff(void)
2751 asm volatile (__ex(ASM_VMX_VMXOFF
) : : : "cc");
2754 static void hardware_disable(void *garbage
)
2756 if (vmm_exclusive
) {
2757 vmclear_local_loaded_vmcss();
2760 write_cr4(read_cr4() & ~X86_CR4_VMXE
);
2763 static __init
int adjust_vmx_controls(u32 ctl_min
, u32 ctl_opt
,
2764 u32 msr
, u32
*result
)
2766 u32 vmx_msr_low
, vmx_msr_high
;
2767 u32 ctl
= ctl_min
| ctl_opt
;
2769 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2771 ctl
&= vmx_msr_high
; /* bit == 0 in high word ==> must be zero */
2772 ctl
|= vmx_msr_low
; /* bit == 1 in low word ==> must be one */
2774 /* Ensure minimum (required) set of control bits are supported. */
2782 static __init
bool allow_1_setting(u32 msr
, u32 ctl
)
2784 u32 vmx_msr_low
, vmx_msr_high
;
2786 rdmsr(msr
, vmx_msr_low
, vmx_msr_high
);
2787 return vmx_msr_high
& ctl
;
2790 static __init
int setup_vmcs_config(struct vmcs_config
*vmcs_conf
)
2792 u32 vmx_msr_low
, vmx_msr_high
;
2793 u32 min
, opt
, min2
, opt2
;
2794 u32 _pin_based_exec_control
= 0;
2795 u32 _cpu_based_exec_control
= 0;
2796 u32 _cpu_based_2nd_exec_control
= 0;
2797 u32 _vmexit_control
= 0;
2798 u32 _vmentry_control
= 0;
2800 min
= CPU_BASED_HLT_EXITING
|
2801 #ifdef CONFIG_X86_64
2802 CPU_BASED_CR8_LOAD_EXITING
|
2803 CPU_BASED_CR8_STORE_EXITING
|
2805 CPU_BASED_CR3_LOAD_EXITING
|
2806 CPU_BASED_CR3_STORE_EXITING
|
2807 CPU_BASED_USE_IO_BITMAPS
|
2808 CPU_BASED_MOV_DR_EXITING
|
2809 CPU_BASED_USE_TSC_OFFSETING
|
2810 CPU_BASED_MWAIT_EXITING
|
2811 CPU_BASED_MONITOR_EXITING
|
2812 CPU_BASED_INVLPG_EXITING
|
2813 CPU_BASED_RDPMC_EXITING
;
2815 opt
= CPU_BASED_TPR_SHADOW
|
2816 CPU_BASED_USE_MSR_BITMAPS
|
2817 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
;
2818 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PROCBASED_CTLS
,
2819 &_cpu_based_exec_control
) < 0)
2821 #ifdef CONFIG_X86_64
2822 if ((_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2823 _cpu_based_exec_control
&= ~CPU_BASED_CR8_LOAD_EXITING
&
2824 ~CPU_BASED_CR8_STORE_EXITING
;
2826 if (_cpu_based_exec_control
& CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
) {
2828 opt2
= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
2829 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2830 SECONDARY_EXEC_WBINVD_EXITING
|
2831 SECONDARY_EXEC_ENABLE_VPID
|
2832 SECONDARY_EXEC_ENABLE_EPT
|
2833 SECONDARY_EXEC_UNRESTRICTED_GUEST
|
2834 SECONDARY_EXEC_PAUSE_LOOP_EXITING
|
2835 SECONDARY_EXEC_RDTSCP
|
2836 SECONDARY_EXEC_ENABLE_INVPCID
|
2837 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2838 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
2839 SECONDARY_EXEC_SHADOW_VMCS
;
2840 if (adjust_vmx_controls(min2
, opt2
,
2841 MSR_IA32_VMX_PROCBASED_CTLS2
,
2842 &_cpu_based_2nd_exec_control
) < 0)
2845 #ifndef CONFIG_X86_64
2846 if (!(_cpu_based_2nd_exec_control
&
2847 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
))
2848 _cpu_based_exec_control
&= ~CPU_BASED_TPR_SHADOW
;
2851 if (!(_cpu_based_exec_control
& CPU_BASED_TPR_SHADOW
))
2852 _cpu_based_2nd_exec_control
&= ~(
2853 SECONDARY_EXEC_APIC_REGISTER_VIRT
|
2854 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
|
2855 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
2857 if (_cpu_based_2nd_exec_control
& SECONDARY_EXEC_ENABLE_EPT
) {
2858 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2860 _cpu_based_exec_control
&= ~(CPU_BASED_CR3_LOAD_EXITING
|
2861 CPU_BASED_CR3_STORE_EXITING
|
2862 CPU_BASED_INVLPG_EXITING
);
2863 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP
,
2864 vmx_capability
.ept
, vmx_capability
.vpid
);
2867 min
= VM_EXIT_SAVE_DEBUG_CONTROLS
;
2868 #ifdef CONFIG_X86_64
2869 min
|= VM_EXIT_HOST_ADDR_SPACE_SIZE
;
2871 opt
= VM_EXIT_SAVE_IA32_PAT
| VM_EXIT_LOAD_IA32_PAT
|
2872 VM_EXIT_ACK_INTR_ON_EXIT
| VM_EXIT_CLEAR_BNDCFGS
;
2873 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_EXIT_CTLS
,
2874 &_vmexit_control
) < 0)
2877 min
= PIN_BASED_EXT_INTR_MASK
| PIN_BASED_NMI_EXITING
;
2878 opt
= PIN_BASED_VIRTUAL_NMIS
| PIN_BASED_POSTED_INTR
;
2879 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_PINBASED_CTLS
,
2880 &_pin_based_exec_control
) < 0)
2883 if (!(_cpu_based_2nd_exec_control
&
2884 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
) ||
2885 !(_vmexit_control
& VM_EXIT_ACK_INTR_ON_EXIT
))
2886 _pin_based_exec_control
&= ~PIN_BASED_POSTED_INTR
;
2888 min
= VM_ENTRY_LOAD_DEBUG_CONTROLS
;
2889 opt
= VM_ENTRY_LOAD_IA32_PAT
| VM_ENTRY_LOAD_BNDCFGS
;
2890 if (adjust_vmx_controls(min
, opt
, MSR_IA32_VMX_ENTRY_CTLS
,
2891 &_vmentry_control
) < 0)
2894 rdmsr(MSR_IA32_VMX_BASIC
, vmx_msr_low
, vmx_msr_high
);
2896 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2897 if ((vmx_msr_high
& 0x1fff) > PAGE_SIZE
)
2900 #ifdef CONFIG_X86_64
2901 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2902 if (vmx_msr_high
& (1u<<16))
2906 /* Require Write-Back (WB) memory type for VMCS accesses. */
2907 if (((vmx_msr_high
>> 18) & 15) != 6)
2910 vmcs_conf
->size
= vmx_msr_high
& 0x1fff;
2911 vmcs_conf
->order
= get_order(vmcs_config
.size
);
2912 vmcs_conf
->revision_id
= vmx_msr_low
;
2914 vmcs_conf
->pin_based_exec_ctrl
= _pin_based_exec_control
;
2915 vmcs_conf
->cpu_based_exec_ctrl
= _cpu_based_exec_control
;
2916 vmcs_conf
->cpu_based_2nd_exec_ctrl
= _cpu_based_2nd_exec_control
;
2917 vmcs_conf
->vmexit_ctrl
= _vmexit_control
;
2918 vmcs_conf
->vmentry_ctrl
= _vmentry_control
;
2920 cpu_has_load_ia32_efer
=
2921 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2922 VM_ENTRY_LOAD_IA32_EFER
)
2923 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2924 VM_EXIT_LOAD_IA32_EFER
);
2926 cpu_has_load_perf_global_ctrl
=
2927 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS
,
2928 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
)
2929 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS
,
2930 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
);
2933 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2934 * but due to arrata below it can't be used. Workaround is to use
2935 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2937 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2942 * BC86,AAY89,BD102 (model 44)
2946 if (cpu_has_load_perf_global_ctrl
&& boot_cpu_data
.x86
== 0x6) {
2947 switch (boot_cpu_data
.x86_model
) {
2953 cpu_has_load_perf_global_ctrl
= false;
2954 printk_once(KERN_WARNING
"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2955 "does not work properly. Using workaround\n");
2965 static struct vmcs
*alloc_vmcs_cpu(int cpu
)
2967 int node
= cpu_to_node(cpu
);
2971 pages
= alloc_pages_exact_node(node
, GFP_KERNEL
, vmcs_config
.order
);
2974 vmcs
= page_address(pages
);
2975 memset(vmcs
, 0, vmcs_config
.size
);
2976 vmcs
->revision_id
= vmcs_config
.revision_id
; /* vmcs revision id */
2980 static struct vmcs
*alloc_vmcs(void)
2982 return alloc_vmcs_cpu(raw_smp_processor_id());
2985 static void free_vmcs(struct vmcs
*vmcs
)
2987 free_pages((unsigned long)vmcs
, vmcs_config
.order
);
2991 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2993 static void free_loaded_vmcs(struct loaded_vmcs
*loaded_vmcs
)
2995 if (!loaded_vmcs
->vmcs
)
2997 loaded_vmcs_clear(loaded_vmcs
);
2998 free_vmcs(loaded_vmcs
->vmcs
);
2999 loaded_vmcs
->vmcs
= NULL
;
3002 static void free_kvm_area(void)
3006 for_each_possible_cpu(cpu
) {
3007 free_vmcs(per_cpu(vmxarea
, cpu
));
3008 per_cpu(vmxarea
, cpu
) = NULL
;
3012 static void init_vmcs_shadow_fields(void)
3016 /* No checks for read only fields yet */
3018 for (i
= j
= 0; i
< max_shadow_read_write_fields
; i
++) {
3019 switch (shadow_read_write_fields
[i
]) {
3021 if (!vmx_mpx_supported())
3029 shadow_read_write_fields
[j
] =
3030 shadow_read_write_fields
[i
];
3033 max_shadow_read_write_fields
= j
;
3035 /* shadowed fields guest access without vmexit */
3036 for (i
= 0; i
< max_shadow_read_write_fields
; i
++) {
3037 clear_bit(shadow_read_write_fields
[i
],
3038 vmx_vmwrite_bitmap
);
3039 clear_bit(shadow_read_write_fields
[i
],
3042 for (i
= 0; i
< max_shadow_read_only_fields
; i
++)
3043 clear_bit(shadow_read_only_fields
[i
],
3047 static __init
int alloc_kvm_area(void)
3051 for_each_possible_cpu(cpu
) {
3054 vmcs
= alloc_vmcs_cpu(cpu
);
3060 per_cpu(vmxarea
, cpu
) = vmcs
;
3065 static __init
int hardware_setup(void)
3067 if (setup_vmcs_config(&vmcs_config
) < 0)
3070 if (boot_cpu_has(X86_FEATURE_NX
))
3071 kvm_enable_efer_bits(EFER_NX
);
3073 if (!cpu_has_vmx_vpid())
3075 if (!cpu_has_vmx_shadow_vmcs())
3076 enable_shadow_vmcs
= 0;
3077 if (enable_shadow_vmcs
)
3078 init_vmcs_shadow_fields();
3080 if (!cpu_has_vmx_ept() ||
3081 !cpu_has_vmx_ept_4levels()) {
3083 enable_unrestricted_guest
= 0;
3084 enable_ept_ad_bits
= 0;
3087 if (!cpu_has_vmx_ept_ad_bits())
3088 enable_ept_ad_bits
= 0;
3090 if (!cpu_has_vmx_unrestricted_guest())
3091 enable_unrestricted_guest
= 0;
3093 if (!cpu_has_vmx_flexpriority())
3094 flexpriority_enabled
= 0;
3096 if (!cpu_has_vmx_tpr_shadow())
3097 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3099 if (enable_ept
&& !cpu_has_vmx_ept_2m_page())
3100 kvm_disable_largepages();
3102 if (!cpu_has_vmx_ple())
3105 if (!cpu_has_vmx_apicv())
3109 kvm_x86_ops
->update_cr8_intercept
= NULL
;
3111 kvm_x86_ops
->hwapic_irr_update
= NULL
;
3112 kvm_x86_ops
->deliver_posted_interrupt
= NULL
;
3113 kvm_x86_ops
->sync_pir_to_irr
= vmx_sync_pir_to_irr_dummy
;
3117 nested_vmx_setup_ctls_msrs();
3119 return alloc_kvm_area();
3122 static __exit
void hardware_unsetup(void)
3127 static bool emulation_required(struct kvm_vcpu
*vcpu
)
3129 return emulate_invalid_guest_state
&& !guest_state_valid(vcpu
);
3132 static void fix_pmode_seg(struct kvm_vcpu
*vcpu
, int seg
,
3133 struct kvm_segment
*save
)
3135 if (!emulate_invalid_guest_state
) {
3137 * CS and SS RPL should be equal during guest entry according
3138 * to VMX spec, but in reality it is not always so. Since vcpu
3139 * is in the middle of the transition from real mode to
3140 * protected mode it is safe to assume that RPL 0 is a good
3143 if (seg
== VCPU_SREG_CS
|| seg
== VCPU_SREG_SS
)
3144 save
->selector
&= ~SELECTOR_RPL_MASK
;
3145 save
->dpl
= save
->selector
& SELECTOR_RPL_MASK
;
3148 vmx_set_segment(vcpu
, save
, seg
);
3151 static void enter_pmode(struct kvm_vcpu
*vcpu
)
3153 unsigned long flags
;
3154 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3157 * Update real mode segment cache. It may be not up-to-date if sement
3158 * register was written while vcpu was in a guest mode.
3160 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3161 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3162 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3163 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3164 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3165 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3167 vmx
->rmode
.vm86_active
= 0;
3169 vmx_segment_cache_clear(vmx
);
3171 vmx_set_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3173 flags
= vmcs_readl(GUEST_RFLAGS
);
3174 flags
&= RMODE_GUEST_OWNED_EFLAGS_BITS
;
3175 flags
|= vmx
->rmode
.save_rflags
& ~RMODE_GUEST_OWNED_EFLAGS_BITS
;
3176 vmcs_writel(GUEST_RFLAGS
, flags
);
3178 vmcs_writel(GUEST_CR4
, (vmcs_readl(GUEST_CR4
) & ~X86_CR4_VME
) |
3179 (vmcs_readl(CR4_READ_SHADOW
) & X86_CR4_VME
));
3181 update_exception_bitmap(vcpu
);
3183 fix_pmode_seg(vcpu
, VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3184 fix_pmode_seg(vcpu
, VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3185 fix_pmode_seg(vcpu
, VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3186 fix_pmode_seg(vcpu
, VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3187 fix_pmode_seg(vcpu
, VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3188 fix_pmode_seg(vcpu
, VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3191 static void fix_rmode_seg(int seg
, struct kvm_segment
*save
)
3193 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3194 struct kvm_segment var
= *save
;
3197 if (seg
== VCPU_SREG_CS
)
3200 if (!emulate_invalid_guest_state
) {
3201 var
.selector
= var
.base
>> 4;
3202 var
.base
= var
.base
& 0xffff0;
3212 if (save
->base
& 0xf)
3213 printk_once(KERN_WARNING
"kvm: segment base is not "
3214 "paragraph aligned when entering "
3215 "protected mode (seg=%d)", seg
);
3218 vmcs_write16(sf
->selector
, var
.selector
);
3219 vmcs_write32(sf
->base
, var
.base
);
3220 vmcs_write32(sf
->limit
, var
.limit
);
3221 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(&var
));
3224 static void enter_rmode(struct kvm_vcpu
*vcpu
)
3226 unsigned long flags
;
3227 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3229 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_TR
], VCPU_SREG_TR
);
3230 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_ES
], VCPU_SREG_ES
);
3231 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_DS
], VCPU_SREG_DS
);
3232 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_FS
], VCPU_SREG_FS
);
3233 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_GS
], VCPU_SREG_GS
);
3234 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_SS
], VCPU_SREG_SS
);
3235 vmx_get_segment(vcpu
, &vmx
->rmode
.segs
[VCPU_SREG_CS
], VCPU_SREG_CS
);
3237 vmx
->rmode
.vm86_active
= 1;
3240 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3241 * vcpu. Warn the user that an update is overdue.
3243 if (!vcpu
->kvm
->arch
.tss_addr
)
3244 printk_once(KERN_WARNING
"kvm: KVM_SET_TSS_ADDR need to be "
3245 "called before entering vcpu\n");
3247 vmx_segment_cache_clear(vmx
);
3249 vmcs_writel(GUEST_TR_BASE
, vcpu
->kvm
->arch
.tss_addr
);
3250 vmcs_write32(GUEST_TR_LIMIT
, RMODE_TSS_SIZE
- 1);
3251 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
3253 flags
= vmcs_readl(GUEST_RFLAGS
);
3254 vmx
->rmode
.save_rflags
= flags
;
3256 flags
|= X86_EFLAGS_IOPL
| X86_EFLAGS_VM
;
3258 vmcs_writel(GUEST_RFLAGS
, flags
);
3259 vmcs_writel(GUEST_CR4
, vmcs_readl(GUEST_CR4
) | X86_CR4_VME
);
3260 update_exception_bitmap(vcpu
);
3262 fix_rmode_seg(VCPU_SREG_SS
, &vmx
->rmode
.segs
[VCPU_SREG_SS
]);
3263 fix_rmode_seg(VCPU_SREG_CS
, &vmx
->rmode
.segs
[VCPU_SREG_CS
]);
3264 fix_rmode_seg(VCPU_SREG_ES
, &vmx
->rmode
.segs
[VCPU_SREG_ES
]);
3265 fix_rmode_seg(VCPU_SREG_DS
, &vmx
->rmode
.segs
[VCPU_SREG_DS
]);
3266 fix_rmode_seg(VCPU_SREG_GS
, &vmx
->rmode
.segs
[VCPU_SREG_GS
]);
3267 fix_rmode_seg(VCPU_SREG_FS
, &vmx
->rmode
.segs
[VCPU_SREG_FS
]);
3269 kvm_mmu_reset_context(vcpu
);
3272 static void vmx_set_efer(struct kvm_vcpu
*vcpu
, u64 efer
)
3274 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3275 struct shared_msr_entry
*msr
= find_msr_entry(vmx
, MSR_EFER
);
3281 * Force kernel_gs_base reloading before EFER changes, as control
3282 * of this msr depends on is_long_mode().
3284 vmx_load_host_state(to_vmx(vcpu
));
3285 vcpu
->arch
.efer
= efer
;
3286 if (efer
& EFER_LMA
) {
3287 vm_entry_controls_setbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3290 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3292 msr
->data
= efer
& ~EFER_LME
;
3297 #ifdef CONFIG_X86_64
3299 static void enter_lmode(struct kvm_vcpu
*vcpu
)
3303 vmx_segment_cache_clear(to_vmx(vcpu
));
3305 guest_tr_ar
= vmcs_read32(GUEST_TR_AR_BYTES
);
3306 if ((guest_tr_ar
& AR_TYPE_MASK
) != AR_TYPE_BUSY_64_TSS
) {
3307 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3309 vmcs_write32(GUEST_TR_AR_BYTES
,
3310 (guest_tr_ar
& ~AR_TYPE_MASK
)
3311 | AR_TYPE_BUSY_64_TSS
);
3313 vmx_set_efer(vcpu
, vcpu
->arch
.efer
| EFER_LMA
);
3316 static void exit_lmode(struct kvm_vcpu
*vcpu
)
3318 vm_entry_controls_clearbit(to_vmx(vcpu
), VM_ENTRY_IA32E_MODE
);
3319 vmx_set_efer(vcpu
, vcpu
->arch
.efer
& ~EFER_LMA
);
3324 static void vmx_flush_tlb(struct kvm_vcpu
*vcpu
)
3326 vpid_sync_context(to_vmx(vcpu
));
3328 if (!VALID_PAGE(vcpu
->arch
.mmu
.root_hpa
))
3330 ept_sync_context(construct_eptp(vcpu
->arch
.mmu
.root_hpa
));
3334 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu
*vcpu
)
3336 ulong cr0_guest_owned_bits
= vcpu
->arch
.cr0_guest_owned_bits
;
3338 vcpu
->arch
.cr0
&= ~cr0_guest_owned_bits
;
3339 vcpu
->arch
.cr0
|= vmcs_readl(GUEST_CR0
) & cr0_guest_owned_bits
;
3342 static void vmx_decache_cr3(struct kvm_vcpu
*vcpu
)
3344 if (enable_ept
&& is_paging(vcpu
))
3345 vcpu
->arch
.cr3
= vmcs_readl(GUEST_CR3
);
3346 __set_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
);
3349 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu
*vcpu
)
3351 ulong cr4_guest_owned_bits
= vcpu
->arch
.cr4_guest_owned_bits
;
3353 vcpu
->arch
.cr4
&= ~cr4_guest_owned_bits
;
3354 vcpu
->arch
.cr4
|= vmcs_readl(GUEST_CR4
) & cr4_guest_owned_bits
;
3357 static void ept_load_pdptrs(struct kvm_vcpu
*vcpu
)
3359 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3361 if (!test_bit(VCPU_EXREG_PDPTR
,
3362 (unsigned long *)&vcpu
->arch
.regs_dirty
))
3365 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3366 vmcs_write64(GUEST_PDPTR0
, mmu
->pdptrs
[0]);
3367 vmcs_write64(GUEST_PDPTR1
, mmu
->pdptrs
[1]);
3368 vmcs_write64(GUEST_PDPTR2
, mmu
->pdptrs
[2]);
3369 vmcs_write64(GUEST_PDPTR3
, mmu
->pdptrs
[3]);
3373 static void ept_save_pdptrs(struct kvm_vcpu
*vcpu
)
3375 struct kvm_mmu
*mmu
= vcpu
->arch
.walk_mmu
;
3377 if (is_paging(vcpu
) && is_pae(vcpu
) && !is_long_mode(vcpu
)) {
3378 mmu
->pdptrs
[0] = vmcs_read64(GUEST_PDPTR0
);
3379 mmu
->pdptrs
[1] = vmcs_read64(GUEST_PDPTR1
);
3380 mmu
->pdptrs
[2] = vmcs_read64(GUEST_PDPTR2
);
3381 mmu
->pdptrs
[3] = vmcs_read64(GUEST_PDPTR3
);
3384 __set_bit(VCPU_EXREG_PDPTR
,
3385 (unsigned long *)&vcpu
->arch
.regs_avail
);
3386 __set_bit(VCPU_EXREG_PDPTR
,
3387 (unsigned long *)&vcpu
->arch
.regs_dirty
);
3390 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
);
3392 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0
,
3394 struct kvm_vcpu
*vcpu
)
3396 if (!test_bit(VCPU_EXREG_CR3
, (ulong
*)&vcpu
->arch
.regs_avail
))
3397 vmx_decache_cr3(vcpu
);
3398 if (!(cr0
& X86_CR0_PG
)) {
3399 /* From paging/starting to nonpaging */
3400 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3401 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) |
3402 (CPU_BASED_CR3_LOAD_EXITING
|
3403 CPU_BASED_CR3_STORE_EXITING
));
3404 vcpu
->arch
.cr0
= cr0
;
3405 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3406 } else if (!is_paging(vcpu
)) {
3407 /* From nonpaging to paging */
3408 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
,
3409 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
) &
3410 ~(CPU_BASED_CR3_LOAD_EXITING
|
3411 CPU_BASED_CR3_STORE_EXITING
));
3412 vcpu
->arch
.cr0
= cr0
;
3413 vmx_set_cr4(vcpu
, kvm_read_cr4(vcpu
));
3416 if (!(cr0
& X86_CR0_WP
))
3417 *hw_cr0
&= ~X86_CR0_WP
;
3420 static void vmx_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long cr0
)
3422 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3423 unsigned long hw_cr0
;
3425 hw_cr0
= (cr0
& ~KVM_GUEST_CR0_MASK
);
3426 if (enable_unrestricted_guest
)
3427 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST
;
3429 hw_cr0
|= KVM_VM_CR0_ALWAYS_ON
;
3431 if (vmx
->rmode
.vm86_active
&& (cr0
& X86_CR0_PE
))
3434 if (!vmx
->rmode
.vm86_active
&& !(cr0
& X86_CR0_PE
))
3438 #ifdef CONFIG_X86_64
3439 if (vcpu
->arch
.efer
& EFER_LME
) {
3440 if (!is_paging(vcpu
) && (cr0
& X86_CR0_PG
))
3442 if (is_paging(vcpu
) && !(cr0
& X86_CR0_PG
))
3448 ept_update_paging_mode_cr0(&hw_cr0
, cr0
, vcpu
);
3450 if (!vcpu
->fpu_active
)
3451 hw_cr0
|= X86_CR0_TS
| X86_CR0_MP
;
3453 vmcs_writel(CR0_READ_SHADOW
, cr0
);
3454 vmcs_writel(GUEST_CR0
, hw_cr0
);
3455 vcpu
->arch
.cr0
= cr0
;
3457 /* depends on vcpu->arch.cr0 to be set to a new value */
3458 vmx
->emulation_required
= emulation_required(vcpu
);
3461 static u64
construct_eptp(unsigned long root_hpa
)
3465 /* TODO write the value reading from MSR */
3466 eptp
= VMX_EPT_DEFAULT_MT
|
3467 VMX_EPT_DEFAULT_GAW
<< VMX_EPT_GAW_EPTP_SHIFT
;
3468 if (enable_ept_ad_bits
)
3469 eptp
|= VMX_EPT_AD_ENABLE_BIT
;
3470 eptp
|= (root_hpa
& PAGE_MASK
);
3475 static void vmx_set_cr3(struct kvm_vcpu
*vcpu
, unsigned long cr3
)
3477 unsigned long guest_cr3
;
3482 eptp
= construct_eptp(cr3
);
3483 vmcs_write64(EPT_POINTER
, eptp
);
3484 if (is_paging(vcpu
) || is_guest_mode(vcpu
))
3485 guest_cr3
= kvm_read_cr3(vcpu
);
3487 guest_cr3
= vcpu
->kvm
->arch
.ept_identity_map_addr
;
3488 ept_load_pdptrs(vcpu
);
3491 vmx_flush_tlb(vcpu
);
3492 vmcs_writel(GUEST_CR3
, guest_cr3
);
3495 static int vmx_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long cr4
)
3497 unsigned long hw_cr4
= cr4
| (to_vmx(vcpu
)->rmode
.vm86_active
?
3498 KVM_RMODE_VM_CR4_ALWAYS_ON
: KVM_PMODE_VM_CR4_ALWAYS_ON
);
3500 if (cr4
& X86_CR4_VMXE
) {
3502 * To use VMXON (and later other VMX instructions), a guest
3503 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3504 * So basically the check on whether to allow nested VMX
3507 if (!nested_vmx_allowed(vcpu
))
3510 if (to_vmx(vcpu
)->nested
.vmxon
&&
3511 ((cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
))
3514 vcpu
->arch
.cr4
= cr4
;
3516 if (!is_paging(vcpu
)) {
3517 hw_cr4
&= ~X86_CR4_PAE
;
3518 hw_cr4
|= X86_CR4_PSE
;
3520 * SMEP/SMAP is disabled if CPU is in non-paging mode
3521 * in hardware. However KVM always uses paging mode to
3522 * emulate guest non-paging mode with TDP.
3523 * To emulate this behavior, SMEP/SMAP needs to be
3524 * manually disabled when guest switches to non-paging
3527 hw_cr4
&= ~(X86_CR4_SMEP
| X86_CR4_SMAP
);
3528 } else if (!(cr4
& X86_CR4_PAE
)) {
3529 hw_cr4
&= ~X86_CR4_PAE
;
3533 vmcs_writel(CR4_READ_SHADOW
, cr4
);
3534 vmcs_writel(GUEST_CR4
, hw_cr4
);
3538 static void vmx_get_segment(struct kvm_vcpu
*vcpu
,
3539 struct kvm_segment
*var
, int seg
)
3541 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3544 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3545 *var
= vmx
->rmode
.segs
[seg
];
3546 if (seg
== VCPU_SREG_TR
3547 || var
->selector
== vmx_read_guest_seg_selector(vmx
, seg
))
3549 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3550 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3553 var
->base
= vmx_read_guest_seg_base(vmx
, seg
);
3554 var
->limit
= vmx_read_guest_seg_limit(vmx
, seg
);
3555 var
->selector
= vmx_read_guest_seg_selector(vmx
, seg
);
3556 ar
= vmx_read_guest_seg_ar(vmx
, seg
);
3557 var
->unusable
= (ar
>> 16) & 1;
3558 var
->type
= ar
& 15;
3559 var
->s
= (ar
>> 4) & 1;
3560 var
->dpl
= (ar
>> 5) & 3;
3562 * Some userspaces do not preserve unusable property. Since usable
3563 * segment has to be present according to VMX spec we can use present
3564 * property to amend userspace bug by making unusable segment always
3565 * nonpresent. vmx_segment_access_rights() already marks nonpresent
3566 * segment as unusable.
3568 var
->present
= !var
->unusable
;
3569 var
->avl
= (ar
>> 12) & 1;
3570 var
->l
= (ar
>> 13) & 1;
3571 var
->db
= (ar
>> 14) & 1;
3572 var
->g
= (ar
>> 15) & 1;
3575 static u64
vmx_get_segment_base(struct kvm_vcpu
*vcpu
, int seg
)
3577 struct kvm_segment s
;
3579 if (to_vmx(vcpu
)->rmode
.vm86_active
) {
3580 vmx_get_segment(vcpu
, &s
, seg
);
3583 return vmx_read_guest_seg_base(to_vmx(vcpu
), seg
);
3586 static int vmx_get_cpl(struct kvm_vcpu
*vcpu
)
3588 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3590 if (unlikely(vmx
->rmode
.vm86_active
))
3593 int ar
= vmx_read_guest_seg_ar(vmx
, VCPU_SREG_SS
);
3598 static u32
vmx_segment_access_rights(struct kvm_segment
*var
)
3602 if (var
->unusable
|| !var
->present
)
3605 ar
= var
->type
& 15;
3606 ar
|= (var
->s
& 1) << 4;
3607 ar
|= (var
->dpl
& 3) << 5;
3608 ar
|= (var
->present
& 1) << 7;
3609 ar
|= (var
->avl
& 1) << 12;
3610 ar
|= (var
->l
& 1) << 13;
3611 ar
|= (var
->db
& 1) << 14;
3612 ar
|= (var
->g
& 1) << 15;
3618 static void vmx_set_segment(struct kvm_vcpu
*vcpu
,
3619 struct kvm_segment
*var
, int seg
)
3621 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
3622 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3624 vmx_segment_cache_clear(vmx
);
3626 if (vmx
->rmode
.vm86_active
&& seg
!= VCPU_SREG_LDTR
) {
3627 vmx
->rmode
.segs
[seg
] = *var
;
3628 if (seg
== VCPU_SREG_TR
)
3629 vmcs_write16(sf
->selector
, var
->selector
);
3631 fix_rmode_seg(seg
, &vmx
->rmode
.segs
[seg
]);
3635 vmcs_writel(sf
->base
, var
->base
);
3636 vmcs_write32(sf
->limit
, var
->limit
);
3637 vmcs_write16(sf
->selector
, var
->selector
);
3640 * Fix the "Accessed" bit in AR field of segment registers for older
3642 * IA32 arch specifies that at the time of processor reset the
3643 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3644 * is setting it to 0 in the userland code. This causes invalid guest
3645 * state vmexit when "unrestricted guest" mode is turned on.
3646 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3647 * tree. Newer qemu binaries with that qemu fix would not need this
3650 if (enable_unrestricted_guest
&& (seg
!= VCPU_SREG_LDTR
))
3651 var
->type
|= 0x1; /* Accessed */
3653 vmcs_write32(sf
->ar_bytes
, vmx_segment_access_rights(var
));
3656 vmx
->emulation_required
|= emulation_required(vcpu
);
3659 static void vmx_get_cs_db_l_bits(struct kvm_vcpu
*vcpu
, int *db
, int *l
)
3661 u32 ar
= vmx_read_guest_seg_ar(to_vmx(vcpu
), VCPU_SREG_CS
);
3663 *db
= (ar
>> 14) & 1;
3664 *l
= (ar
>> 13) & 1;
3667 static void vmx_get_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3669 dt
->size
= vmcs_read32(GUEST_IDTR_LIMIT
);
3670 dt
->address
= vmcs_readl(GUEST_IDTR_BASE
);
3673 static void vmx_set_idt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3675 vmcs_write32(GUEST_IDTR_LIMIT
, dt
->size
);
3676 vmcs_writel(GUEST_IDTR_BASE
, dt
->address
);
3679 static void vmx_get_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3681 dt
->size
= vmcs_read32(GUEST_GDTR_LIMIT
);
3682 dt
->address
= vmcs_readl(GUEST_GDTR_BASE
);
3685 static void vmx_set_gdt(struct kvm_vcpu
*vcpu
, struct desc_ptr
*dt
)
3687 vmcs_write32(GUEST_GDTR_LIMIT
, dt
->size
);
3688 vmcs_writel(GUEST_GDTR_BASE
, dt
->address
);
3691 static bool rmode_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3693 struct kvm_segment var
;
3696 vmx_get_segment(vcpu
, &var
, seg
);
3698 if (seg
== VCPU_SREG_CS
)
3700 ar
= vmx_segment_access_rights(&var
);
3702 if (var
.base
!= (var
.selector
<< 4))
3704 if (var
.limit
!= 0xffff)
3712 static bool code_segment_valid(struct kvm_vcpu
*vcpu
)
3714 struct kvm_segment cs
;
3715 unsigned int cs_rpl
;
3717 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3718 cs_rpl
= cs
.selector
& SELECTOR_RPL_MASK
;
3722 if (~cs
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_ACCESSES_MASK
))
3726 if (cs
.type
& AR_TYPE_WRITEABLE_MASK
) {
3727 if (cs
.dpl
> cs_rpl
)
3730 if (cs
.dpl
!= cs_rpl
)
3736 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3740 static bool stack_segment_valid(struct kvm_vcpu
*vcpu
)
3742 struct kvm_segment ss
;
3743 unsigned int ss_rpl
;
3745 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3746 ss_rpl
= ss
.selector
& SELECTOR_RPL_MASK
;
3750 if (ss
.type
!= 3 && ss
.type
!= 7)
3754 if (ss
.dpl
!= ss_rpl
) /* DPL != RPL */
3762 static bool data_segment_valid(struct kvm_vcpu
*vcpu
, int seg
)
3764 struct kvm_segment var
;
3767 vmx_get_segment(vcpu
, &var
, seg
);
3768 rpl
= var
.selector
& SELECTOR_RPL_MASK
;
3776 if (~var
.type
& (AR_TYPE_CODE_MASK
|AR_TYPE_WRITEABLE_MASK
)) {
3777 if (var
.dpl
< rpl
) /* DPL < RPL */
3781 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3787 static bool tr_valid(struct kvm_vcpu
*vcpu
)
3789 struct kvm_segment tr
;
3791 vmx_get_segment(vcpu
, &tr
, VCPU_SREG_TR
);
3795 if (tr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3797 if (tr
.type
!= 3 && tr
.type
!= 11) /* TODO: Check if guest is in IA32e mode */
3805 static bool ldtr_valid(struct kvm_vcpu
*vcpu
)
3807 struct kvm_segment ldtr
;
3809 vmx_get_segment(vcpu
, &ldtr
, VCPU_SREG_LDTR
);
3813 if (ldtr
.selector
& SELECTOR_TI_MASK
) /* TI = 1 */
3823 static bool cs_ss_rpl_check(struct kvm_vcpu
*vcpu
)
3825 struct kvm_segment cs
, ss
;
3827 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
3828 vmx_get_segment(vcpu
, &ss
, VCPU_SREG_SS
);
3830 return ((cs
.selector
& SELECTOR_RPL_MASK
) ==
3831 (ss
.selector
& SELECTOR_RPL_MASK
));
3835 * Check if guest state is valid. Returns true if valid, false if
3837 * We assume that registers are always usable
3839 static bool guest_state_valid(struct kvm_vcpu
*vcpu
)
3841 if (enable_unrestricted_guest
)
3844 /* real mode guest state checks */
3845 if (!is_protmode(vcpu
) || (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
3846 if (!rmode_segment_valid(vcpu
, VCPU_SREG_CS
))
3848 if (!rmode_segment_valid(vcpu
, VCPU_SREG_SS
))
3850 if (!rmode_segment_valid(vcpu
, VCPU_SREG_DS
))
3852 if (!rmode_segment_valid(vcpu
, VCPU_SREG_ES
))
3854 if (!rmode_segment_valid(vcpu
, VCPU_SREG_FS
))
3856 if (!rmode_segment_valid(vcpu
, VCPU_SREG_GS
))
3859 /* protected mode guest state checks */
3860 if (!cs_ss_rpl_check(vcpu
))
3862 if (!code_segment_valid(vcpu
))
3864 if (!stack_segment_valid(vcpu
))
3866 if (!data_segment_valid(vcpu
, VCPU_SREG_DS
))
3868 if (!data_segment_valid(vcpu
, VCPU_SREG_ES
))
3870 if (!data_segment_valid(vcpu
, VCPU_SREG_FS
))
3872 if (!data_segment_valid(vcpu
, VCPU_SREG_GS
))
3874 if (!tr_valid(vcpu
))
3876 if (!ldtr_valid(vcpu
))
3880 * - Add checks on RIP
3881 * - Add checks on RFLAGS
3887 static int init_rmode_tss(struct kvm
*kvm
)
3891 int r
, idx
, ret
= 0;
3893 idx
= srcu_read_lock(&kvm
->srcu
);
3894 fn
= kvm
->arch
.tss_addr
>> PAGE_SHIFT
;
3895 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3898 data
= TSS_BASE_SIZE
+ TSS_REDIRECTION_SIZE
;
3899 r
= kvm_write_guest_page(kvm
, fn
++, &data
,
3900 TSS_IOPB_BASE_OFFSET
, sizeof(u16
));
3903 r
= kvm_clear_guest_page(kvm
, fn
++, 0, PAGE_SIZE
);
3906 r
= kvm_clear_guest_page(kvm
, fn
, 0, PAGE_SIZE
);
3910 r
= kvm_write_guest_page(kvm
, fn
, &data
,
3911 RMODE_TSS_SIZE
- 2 * PAGE_SIZE
- 1,
3918 srcu_read_unlock(&kvm
->srcu
, idx
);
3922 static int init_rmode_identity_map(struct kvm
*kvm
)
3925 pfn_t identity_map_pfn
;
3930 if (unlikely(!kvm
->arch
.ept_identity_pagetable
)) {
3931 printk(KERN_ERR
"EPT: identity-mapping pagetable "
3932 "haven't been allocated!\n");
3935 if (likely(kvm
->arch
.ept_identity_pagetable_done
))
3938 identity_map_pfn
= kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
;
3939 idx
= srcu_read_lock(&kvm
->srcu
);
3940 r
= kvm_clear_guest_page(kvm
, identity_map_pfn
, 0, PAGE_SIZE
);
3943 /* Set up identity-mapping pagetable for EPT in real mode */
3944 for (i
= 0; i
< PT32_ENT_PER_PAGE
; i
++) {
3945 tmp
= (i
<< 22) + (_PAGE_PRESENT
| _PAGE_RW
| _PAGE_USER
|
3946 _PAGE_ACCESSED
| _PAGE_DIRTY
| _PAGE_PSE
);
3947 r
= kvm_write_guest_page(kvm
, identity_map_pfn
,
3948 &tmp
, i
* sizeof(tmp
), sizeof(tmp
));
3952 kvm
->arch
.ept_identity_pagetable_done
= true;
3955 srcu_read_unlock(&kvm
->srcu
, idx
);
3959 static void seg_setup(int seg
)
3961 const struct kvm_vmx_segment_field
*sf
= &kvm_vmx_segment_fields
[seg
];
3964 vmcs_write16(sf
->selector
, 0);
3965 vmcs_writel(sf
->base
, 0);
3966 vmcs_write32(sf
->limit
, 0xffff);
3968 if (seg
== VCPU_SREG_CS
)
3969 ar
|= 0x08; /* code segment */
3971 vmcs_write32(sf
->ar_bytes
, ar
);
3974 static int alloc_apic_access_page(struct kvm
*kvm
)
3977 struct kvm_userspace_memory_region kvm_userspace_mem
;
3980 mutex_lock(&kvm
->slots_lock
);
3981 if (kvm
->arch
.apic_access_page
)
3983 kvm_userspace_mem
.slot
= APIC_ACCESS_PAGE_PRIVATE_MEMSLOT
;
3984 kvm_userspace_mem
.flags
= 0;
3985 kvm_userspace_mem
.guest_phys_addr
= 0xfee00000ULL
;
3986 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
3987 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
3991 page
= gfn_to_page(kvm
, 0xfee00);
3992 if (is_error_page(page
)) {
3997 kvm
->arch
.apic_access_page
= page
;
3999 mutex_unlock(&kvm
->slots_lock
);
4003 static int alloc_identity_pagetable(struct kvm
*kvm
)
4006 struct kvm_userspace_memory_region kvm_userspace_mem
;
4009 mutex_lock(&kvm
->slots_lock
);
4010 if (kvm
->arch
.ept_identity_pagetable
)
4012 kvm_userspace_mem
.slot
= IDENTITY_PAGETABLE_PRIVATE_MEMSLOT
;
4013 kvm_userspace_mem
.flags
= 0;
4014 kvm_userspace_mem
.guest_phys_addr
=
4015 kvm
->arch
.ept_identity_map_addr
;
4016 kvm_userspace_mem
.memory_size
= PAGE_SIZE
;
4017 r
= __kvm_set_memory_region(kvm
, &kvm_userspace_mem
);
4021 page
= gfn_to_page(kvm
, kvm
->arch
.ept_identity_map_addr
>> PAGE_SHIFT
);
4022 if (is_error_page(page
)) {
4027 kvm
->arch
.ept_identity_pagetable
= page
;
4029 mutex_unlock(&kvm
->slots_lock
);
4033 static void allocate_vpid(struct vcpu_vmx
*vmx
)
4040 spin_lock(&vmx_vpid_lock
);
4041 vpid
= find_first_zero_bit(vmx_vpid_bitmap
, VMX_NR_VPIDS
);
4042 if (vpid
< VMX_NR_VPIDS
) {
4044 __set_bit(vpid
, vmx_vpid_bitmap
);
4046 spin_unlock(&vmx_vpid_lock
);
4049 static void free_vpid(struct vcpu_vmx
*vmx
)
4053 spin_lock(&vmx_vpid_lock
);
4055 __clear_bit(vmx
->vpid
, vmx_vpid_bitmap
);
4056 spin_unlock(&vmx_vpid_lock
);
4059 #define MSR_TYPE_R 1
4060 #define MSR_TYPE_W 2
4061 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap
,
4064 int f
= sizeof(unsigned long);
4066 if (!cpu_has_vmx_msr_bitmap())
4070 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4071 * have the write-low and read-high bitmap offsets the wrong way round.
4072 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4074 if (msr
<= 0x1fff) {
4075 if (type
& MSR_TYPE_R
)
4077 __clear_bit(msr
, msr_bitmap
+ 0x000 / f
);
4079 if (type
& MSR_TYPE_W
)
4081 __clear_bit(msr
, msr_bitmap
+ 0x800 / f
);
4083 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4085 if (type
& MSR_TYPE_R
)
4087 __clear_bit(msr
, msr_bitmap
+ 0x400 / f
);
4089 if (type
& MSR_TYPE_W
)
4091 __clear_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4096 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap
,
4099 int f
= sizeof(unsigned long);
4101 if (!cpu_has_vmx_msr_bitmap())
4105 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4106 * have the write-low and read-high bitmap offsets the wrong way round.
4107 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4109 if (msr
<= 0x1fff) {
4110 if (type
& MSR_TYPE_R
)
4112 __set_bit(msr
, msr_bitmap
+ 0x000 / f
);
4114 if (type
& MSR_TYPE_W
)
4116 __set_bit(msr
, msr_bitmap
+ 0x800 / f
);
4118 } else if ((msr
>= 0xc0000000) && (msr
<= 0xc0001fff)) {
4120 if (type
& MSR_TYPE_R
)
4122 __set_bit(msr
, msr_bitmap
+ 0x400 / f
);
4124 if (type
& MSR_TYPE_W
)
4126 __set_bit(msr
, msr_bitmap
+ 0xc00 / f
);
4131 static void vmx_disable_intercept_for_msr(u32 msr
, bool longmode_only
)
4134 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy
,
4135 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4136 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode
,
4137 msr
, MSR_TYPE_R
| MSR_TYPE_W
);
4140 static void vmx_enable_intercept_msr_read_x2apic(u32 msr
)
4142 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4144 __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4148 static void vmx_disable_intercept_msr_read_x2apic(u32 msr
)
4150 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4152 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4156 static void vmx_disable_intercept_msr_write_x2apic(u32 msr
)
4158 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic
,
4160 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic
,
4164 static int vmx_vm_has_apicv(struct kvm
*kvm
)
4166 return enable_apicv
&& irqchip_in_kernel(kvm
);
4170 * Send interrupt to vcpu via posted interrupt way.
4171 * 1. If target vcpu is running(non-root mode), send posted interrupt
4172 * notification to vcpu and hardware will sync PIR to vIRR atomically.
4173 * 2. If target vcpu isn't running(root mode), kick it to pick up the
4174 * interrupt from PIR in next vmentry.
4176 static void vmx_deliver_posted_interrupt(struct kvm_vcpu
*vcpu
, int vector
)
4178 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4181 if (pi_test_and_set_pir(vector
, &vmx
->pi_desc
))
4184 r
= pi_test_and_set_on(&vmx
->pi_desc
);
4185 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
4187 if (!r
&& (vcpu
->mode
== IN_GUEST_MODE
))
4188 apic
->send_IPI_mask(get_cpu_mask(vcpu
->cpu
),
4189 POSTED_INTR_VECTOR
);
4192 kvm_vcpu_kick(vcpu
);
4195 static void vmx_sync_pir_to_irr(struct kvm_vcpu
*vcpu
)
4197 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4199 if (!pi_test_and_clear_on(&vmx
->pi_desc
))
4202 kvm_apic_update_irr(vcpu
, vmx
->pi_desc
.pir
);
4205 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu
*vcpu
)
4211 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4212 * will not change in the lifetime of the guest.
4213 * Note that host-state that does change is set elsewhere. E.g., host-state
4214 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4216 static void vmx_set_constant_host_state(struct vcpu_vmx
*vmx
)
4222 vmcs_writel(HOST_CR0
, read_cr0() & ~X86_CR0_TS
); /* 22.2.3 */
4223 vmcs_writel(HOST_CR4
, read_cr4()); /* 22.2.3, 22.2.5 */
4224 vmcs_writel(HOST_CR3
, read_cr3()); /* 22.2.3 FIXME: shadow tables */
4226 vmcs_write16(HOST_CS_SELECTOR
, __KERNEL_CS
); /* 22.2.4 */
4227 #ifdef CONFIG_X86_64
4229 * Load null selectors, so we can avoid reloading them in
4230 * __vmx_load_host_state(), in case userspace uses the null selectors
4231 * too (the expected case).
4233 vmcs_write16(HOST_DS_SELECTOR
, 0);
4234 vmcs_write16(HOST_ES_SELECTOR
, 0);
4236 vmcs_write16(HOST_DS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4237 vmcs_write16(HOST_ES_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4239 vmcs_write16(HOST_SS_SELECTOR
, __KERNEL_DS
); /* 22.2.4 */
4240 vmcs_write16(HOST_TR_SELECTOR
, GDT_ENTRY_TSS
*8); /* 22.2.4 */
4242 native_store_idt(&dt
);
4243 vmcs_writel(HOST_IDTR_BASE
, dt
.address
); /* 22.2.4 */
4244 vmx
->host_idt_base
= dt
.address
;
4246 vmcs_writel(HOST_RIP
, vmx_return
); /* 22.2.5 */
4248 rdmsr(MSR_IA32_SYSENTER_CS
, low32
, high32
);
4249 vmcs_write32(HOST_IA32_SYSENTER_CS
, low32
);
4250 rdmsrl(MSR_IA32_SYSENTER_EIP
, tmpl
);
4251 vmcs_writel(HOST_IA32_SYSENTER_EIP
, tmpl
); /* 22.2.3 */
4253 if (vmcs_config
.vmexit_ctrl
& VM_EXIT_LOAD_IA32_PAT
) {
4254 rdmsr(MSR_IA32_CR_PAT
, low32
, high32
);
4255 vmcs_write64(HOST_IA32_PAT
, low32
| ((u64
) high32
<< 32));
4259 static void set_cr4_guest_host_mask(struct vcpu_vmx
*vmx
)
4261 vmx
->vcpu
.arch
.cr4_guest_owned_bits
= KVM_CR4_GUEST_OWNED_BITS
;
4263 vmx
->vcpu
.arch
.cr4_guest_owned_bits
|= X86_CR4_PGE
;
4264 if (is_guest_mode(&vmx
->vcpu
))
4265 vmx
->vcpu
.arch
.cr4_guest_owned_bits
&=
4266 ~get_vmcs12(&vmx
->vcpu
)->cr4_guest_host_mask
;
4267 vmcs_writel(CR4_GUEST_HOST_MASK
, ~vmx
->vcpu
.arch
.cr4_guest_owned_bits
);
4270 static u32
vmx_pin_based_exec_ctrl(struct vcpu_vmx
*vmx
)
4272 u32 pin_based_exec_ctrl
= vmcs_config
.pin_based_exec_ctrl
;
4274 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4275 pin_based_exec_ctrl
&= ~PIN_BASED_POSTED_INTR
;
4276 return pin_based_exec_ctrl
;
4279 static u32
vmx_exec_control(struct vcpu_vmx
*vmx
)
4281 u32 exec_control
= vmcs_config
.cpu_based_exec_ctrl
;
4283 if (vmx
->vcpu
.arch
.switch_db_regs
& KVM_DEBUGREG_WONT_EXIT
)
4284 exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
4286 if (!vm_need_tpr_shadow(vmx
->vcpu
.kvm
)) {
4287 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
4288 #ifdef CONFIG_X86_64
4289 exec_control
|= CPU_BASED_CR8_STORE_EXITING
|
4290 CPU_BASED_CR8_LOAD_EXITING
;
4294 exec_control
|= CPU_BASED_CR3_STORE_EXITING
|
4295 CPU_BASED_CR3_LOAD_EXITING
|
4296 CPU_BASED_INVLPG_EXITING
;
4297 return exec_control
;
4300 static u32
vmx_secondary_exec_control(struct vcpu_vmx
*vmx
)
4302 u32 exec_control
= vmcs_config
.cpu_based_2nd_exec_ctrl
;
4303 if (!vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4304 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
4306 exec_control
&= ~SECONDARY_EXEC_ENABLE_VPID
;
4308 exec_control
&= ~SECONDARY_EXEC_ENABLE_EPT
;
4309 enable_unrestricted_guest
= 0;
4310 /* Enable INVPCID for non-ept guests may cause performance regression. */
4311 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
4313 if (!enable_unrestricted_guest
)
4314 exec_control
&= ~SECONDARY_EXEC_UNRESTRICTED_GUEST
;
4316 exec_control
&= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING
;
4317 if (!vmx_vm_has_apicv(vmx
->vcpu
.kvm
))
4318 exec_control
&= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT
|
4319 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
);
4320 exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
4321 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4323 We can NOT enable shadow_vmcs here because we don't have yet
4326 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
4327 return exec_control
;
4330 static void ept_set_mmio_spte_mask(void)
4333 * EPT Misconfigurations can be generated if the value of bits 2:0
4334 * of an EPT paging-structure entry is 110b (write/execute).
4335 * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4338 kvm_mmu_set_mmio_spte_mask((0x3ull
<< 62) | 0x6ull
);
4342 * Sets up the vmcs for emulated real mode.
4344 static int vmx_vcpu_setup(struct vcpu_vmx
*vmx
)
4346 #ifdef CONFIG_X86_64
4352 vmcs_write64(IO_BITMAP_A
, __pa(vmx_io_bitmap_a
));
4353 vmcs_write64(IO_BITMAP_B
, __pa(vmx_io_bitmap_b
));
4355 if (enable_shadow_vmcs
) {
4356 vmcs_write64(VMREAD_BITMAP
, __pa(vmx_vmread_bitmap
));
4357 vmcs_write64(VMWRITE_BITMAP
, __pa(vmx_vmwrite_bitmap
));
4359 if (cpu_has_vmx_msr_bitmap())
4360 vmcs_write64(MSR_BITMAP
, __pa(vmx_msr_bitmap_legacy
));
4362 vmcs_write64(VMCS_LINK_POINTER
, -1ull); /* 22.3.1.5 */
4365 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, vmx_pin_based_exec_ctrl(vmx
));
4367 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, vmx_exec_control(vmx
));
4369 if (cpu_has_secondary_exec_ctrls()) {
4370 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
4371 vmx_secondary_exec_control(vmx
));
4374 if (vmx_vm_has_apicv(vmx
->vcpu
.kvm
)) {
4375 vmcs_write64(EOI_EXIT_BITMAP0
, 0);
4376 vmcs_write64(EOI_EXIT_BITMAP1
, 0);
4377 vmcs_write64(EOI_EXIT_BITMAP2
, 0);
4378 vmcs_write64(EOI_EXIT_BITMAP3
, 0);
4380 vmcs_write16(GUEST_INTR_STATUS
, 0);
4382 vmcs_write64(POSTED_INTR_NV
, POSTED_INTR_VECTOR
);
4383 vmcs_write64(POSTED_INTR_DESC_ADDR
, __pa((&vmx
->pi_desc
)));
4387 vmcs_write32(PLE_GAP
, ple_gap
);
4388 vmcs_write32(PLE_WINDOW
, ple_window
);
4391 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
, 0);
4392 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
, 0);
4393 vmcs_write32(CR3_TARGET_COUNT
, 0); /* 22.2.1 */
4395 vmcs_write16(HOST_FS_SELECTOR
, 0); /* 22.2.4 */
4396 vmcs_write16(HOST_GS_SELECTOR
, 0); /* 22.2.4 */
4397 vmx_set_constant_host_state(vmx
);
4398 #ifdef CONFIG_X86_64
4399 rdmsrl(MSR_FS_BASE
, a
);
4400 vmcs_writel(HOST_FS_BASE
, a
); /* 22.2.4 */
4401 rdmsrl(MSR_GS_BASE
, a
);
4402 vmcs_writel(HOST_GS_BASE
, a
); /* 22.2.4 */
4404 vmcs_writel(HOST_FS_BASE
, 0); /* 22.2.4 */
4405 vmcs_writel(HOST_GS_BASE
, 0); /* 22.2.4 */
4408 vmcs_write32(VM_EXIT_MSR_STORE_COUNT
, 0);
4409 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT
, 0);
4410 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.host
));
4411 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT
, 0);
4412 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR
, __pa(vmx
->msr_autoload
.guest
));
4414 if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
) {
4415 u32 msr_low
, msr_high
;
4417 rdmsr(MSR_IA32_CR_PAT
, msr_low
, msr_high
);
4418 host_pat
= msr_low
| ((u64
) msr_high
<< 32);
4419 /* Write the default value follow host pat */
4420 vmcs_write64(GUEST_IA32_PAT
, host_pat
);
4421 /* Keep arch.pat sync with GUEST_IA32_PAT */
4422 vmx
->vcpu
.arch
.pat
= host_pat
;
4425 for (i
= 0; i
< NR_VMX_MSR
; ++i
) {
4426 u32 index
= vmx_msr_index
[i
];
4427 u32 data_low
, data_high
;
4430 if (rdmsr_safe(index
, &data_low
, &data_high
) < 0)
4432 if (wrmsr_safe(index
, data_low
, data_high
) < 0)
4434 vmx
->guest_msrs
[j
].index
= i
;
4435 vmx
->guest_msrs
[j
].data
= 0;
4436 vmx
->guest_msrs
[j
].mask
= -1ull;
4441 vm_exit_controls_init(vmx
, vmcs_config
.vmexit_ctrl
);
4443 /* 22.2.1, 20.8.1 */
4444 vm_entry_controls_init(vmx
, vmcs_config
.vmentry_ctrl
);
4446 vmcs_writel(CR0_GUEST_HOST_MASK
, ~0UL);
4447 set_cr4_guest_host_mask(vmx
);
4452 static void vmx_vcpu_reset(struct kvm_vcpu
*vcpu
)
4454 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4455 struct msr_data apic_base_msr
;
4457 vmx
->rmode
.vm86_active
= 0;
4459 vmx
->soft_vnmi_blocked
= 0;
4461 vmx
->vcpu
.arch
.regs
[VCPU_REGS_RDX
] = get_rdx_init_val();
4462 kvm_set_cr8(&vmx
->vcpu
, 0);
4463 apic_base_msr
.data
= 0xfee00000 | MSR_IA32_APICBASE_ENABLE
;
4464 if (kvm_vcpu_is_bsp(&vmx
->vcpu
))
4465 apic_base_msr
.data
|= MSR_IA32_APICBASE_BSP
;
4466 apic_base_msr
.host_initiated
= true;
4467 kvm_set_apic_base(&vmx
->vcpu
, &apic_base_msr
);
4469 vmx_segment_cache_clear(vmx
);
4471 seg_setup(VCPU_SREG_CS
);
4472 vmcs_write16(GUEST_CS_SELECTOR
, 0xf000);
4473 vmcs_write32(GUEST_CS_BASE
, 0xffff0000);
4475 seg_setup(VCPU_SREG_DS
);
4476 seg_setup(VCPU_SREG_ES
);
4477 seg_setup(VCPU_SREG_FS
);
4478 seg_setup(VCPU_SREG_GS
);
4479 seg_setup(VCPU_SREG_SS
);
4481 vmcs_write16(GUEST_TR_SELECTOR
, 0);
4482 vmcs_writel(GUEST_TR_BASE
, 0);
4483 vmcs_write32(GUEST_TR_LIMIT
, 0xffff);
4484 vmcs_write32(GUEST_TR_AR_BYTES
, 0x008b);
4486 vmcs_write16(GUEST_LDTR_SELECTOR
, 0);
4487 vmcs_writel(GUEST_LDTR_BASE
, 0);
4488 vmcs_write32(GUEST_LDTR_LIMIT
, 0xffff);
4489 vmcs_write32(GUEST_LDTR_AR_BYTES
, 0x00082);
4491 vmcs_write32(GUEST_SYSENTER_CS
, 0);
4492 vmcs_writel(GUEST_SYSENTER_ESP
, 0);
4493 vmcs_writel(GUEST_SYSENTER_EIP
, 0);
4495 vmcs_writel(GUEST_RFLAGS
, 0x02);
4496 kvm_rip_write(vcpu
, 0xfff0);
4498 vmcs_writel(GUEST_GDTR_BASE
, 0);
4499 vmcs_write32(GUEST_GDTR_LIMIT
, 0xffff);
4501 vmcs_writel(GUEST_IDTR_BASE
, 0);
4502 vmcs_write32(GUEST_IDTR_LIMIT
, 0xffff);
4504 vmcs_write32(GUEST_ACTIVITY_STATE
, GUEST_ACTIVITY_ACTIVE
);
4505 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
, 0);
4506 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS
, 0);
4508 /* Special registers */
4509 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
4513 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0); /* 22.2.1 */
4515 if (cpu_has_vmx_tpr_shadow()) {
4516 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
, 0);
4517 if (vm_need_tpr_shadow(vmx
->vcpu
.kvm
))
4518 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR
,
4519 __pa(vmx
->vcpu
.arch
.apic
->regs
));
4520 vmcs_write32(TPR_THRESHOLD
, 0);
4523 if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
))
4524 vmcs_write64(APIC_ACCESS_ADDR
,
4525 page_to_phys(vmx
->vcpu
.kvm
->arch
.apic_access_page
));
4527 if (vmx_vm_has_apicv(vcpu
->kvm
))
4528 memset(&vmx
->pi_desc
, 0, sizeof(struct pi_desc
));
4531 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
4533 vmx
->vcpu
.arch
.cr0
= X86_CR0_NW
| X86_CR0_CD
| X86_CR0_ET
;
4534 vmx_set_cr0(&vmx
->vcpu
, kvm_read_cr0(vcpu
)); /* enter rmode */
4535 vmx_set_cr4(&vmx
->vcpu
, 0);
4536 vmx_set_efer(&vmx
->vcpu
, 0);
4537 vmx_fpu_activate(&vmx
->vcpu
);
4538 update_exception_bitmap(&vmx
->vcpu
);
4540 vpid_sync_context(vmx
);
4544 * In nested virtualization, check if L1 asked to exit on external interrupts.
4545 * For most existing hypervisors, this will always return true.
4547 static bool nested_exit_on_intr(struct kvm_vcpu
*vcpu
)
4549 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4550 PIN_BASED_EXT_INTR_MASK
;
4554 * In nested virtualization, check if L1 has set
4555 * VM_EXIT_ACK_INTR_ON_EXIT
4557 static bool nested_exit_intr_ack_set(struct kvm_vcpu
*vcpu
)
4559 return get_vmcs12(vcpu
)->vm_exit_controls
&
4560 VM_EXIT_ACK_INTR_ON_EXIT
;
4563 static bool nested_exit_on_nmi(struct kvm_vcpu
*vcpu
)
4565 return get_vmcs12(vcpu
)->pin_based_vm_exec_control
&
4566 PIN_BASED_NMI_EXITING
;
4569 static void enable_irq_window(struct kvm_vcpu
*vcpu
)
4571 u32 cpu_based_vm_exec_control
;
4573 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4574 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_INTR_PENDING
;
4575 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4578 static void enable_nmi_window(struct kvm_vcpu
*vcpu
)
4580 u32 cpu_based_vm_exec_control
;
4582 if (!cpu_has_virtual_nmis() ||
4583 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_STI
) {
4584 enable_irq_window(vcpu
);
4588 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
4589 cpu_based_vm_exec_control
|= CPU_BASED_VIRTUAL_NMI_PENDING
;
4590 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
4593 static void vmx_inject_irq(struct kvm_vcpu
*vcpu
)
4595 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4597 int irq
= vcpu
->arch
.interrupt
.nr
;
4599 trace_kvm_inj_virq(irq
);
4601 ++vcpu
->stat
.irq_injections
;
4602 if (vmx
->rmode
.vm86_active
) {
4604 if (vcpu
->arch
.interrupt
.soft
)
4605 inc_eip
= vcpu
->arch
.event_exit_inst_len
;
4606 if (kvm_inject_realmode_interrupt(vcpu
, irq
, inc_eip
) != EMULATE_DONE
)
4607 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4610 intr
= irq
| INTR_INFO_VALID_MASK
;
4611 if (vcpu
->arch
.interrupt
.soft
) {
4612 intr
|= INTR_TYPE_SOFT_INTR
;
4613 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
4614 vmx
->vcpu
.arch
.event_exit_inst_len
);
4616 intr
|= INTR_TYPE_EXT_INTR
;
4617 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, intr
);
4620 static void vmx_inject_nmi(struct kvm_vcpu
*vcpu
)
4622 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4624 if (is_guest_mode(vcpu
))
4627 if (!cpu_has_virtual_nmis()) {
4629 * Tracking the NMI-blocked state in software is built upon
4630 * finding the next open IRQ window. This, in turn, depends on
4631 * well-behaving guests: They have to keep IRQs disabled at
4632 * least as long as the NMI handler runs. Otherwise we may
4633 * cause NMI nesting, maybe breaking the guest. But as this is
4634 * highly unlikely, we can live with the residual risk.
4636 vmx
->soft_vnmi_blocked
= 1;
4637 vmx
->vnmi_blocked_time
= 0;
4640 ++vcpu
->stat
.nmi_injections
;
4641 vmx
->nmi_known_unmasked
= false;
4642 if (vmx
->rmode
.vm86_active
) {
4643 if (kvm_inject_realmode_interrupt(vcpu
, NMI_VECTOR
, 0) != EMULATE_DONE
)
4644 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
4647 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
4648 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
);
4651 static bool vmx_get_nmi_mask(struct kvm_vcpu
*vcpu
)
4653 if (!cpu_has_virtual_nmis())
4654 return to_vmx(vcpu
)->soft_vnmi_blocked
;
4655 if (to_vmx(vcpu
)->nmi_known_unmasked
)
4657 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) & GUEST_INTR_STATE_NMI
;
4660 static void vmx_set_nmi_mask(struct kvm_vcpu
*vcpu
, bool masked
)
4662 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4664 if (!cpu_has_virtual_nmis()) {
4665 if (vmx
->soft_vnmi_blocked
!= masked
) {
4666 vmx
->soft_vnmi_blocked
= masked
;
4667 vmx
->vnmi_blocked_time
= 0;
4670 vmx
->nmi_known_unmasked
= !masked
;
4672 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
4673 GUEST_INTR_STATE_NMI
);
4675 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO
,
4676 GUEST_INTR_STATE_NMI
);
4680 static int vmx_nmi_allowed(struct kvm_vcpu
*vcpu
)
4682 if (to_vmx(vcpu
)->nested
.nested_run_pending
)
4685 if (!cpu_has_virtual_nmis() && to_vmx(vcpu
)->soft_vnmi_blocked
)
4688 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4689 (GUEST_INTR_STATE_MOV_SS
| GUEST_INTR_STATE_STI
4690 | GUEST_INTR_STATE_NMI
));
4693 static int vmx_interrupt_allowed(struct kvm_vcpu
*vcpu
)
4695 return (!to_vmx(vcpu
)->nested
.nested_run_pending
&&
4696 vmcs_readl(GUEST_RFLAGS
) & X86_EFLAGS_IF
) &&
4697 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
) &
4698 (GUEST_INTR_STATE_STI
| GUEST_INTR_STATE_MOV_SS
));
4701 static int vmx_set_tss_addr(struct kvm
*kvm
, unsigned int addr
)
4704 struct kvm_userspace_memory_region tss_mem
= {
4705 .slot
= TSS_PRIVATE_MEMSLOT
,
4706 .guest_phys_addr
= addr
,
4707 .memory_size
= PAGE_SIZE
* 3,
4711 ret
= kvm_set_memory_region(kvm
, &tss_mem
);
4714 kvm
->arch
.tss_addr
= addr
;
4715 if (!init_rmode_tss(kvm
))
4721 static bool rmode_exception(struct kvm_vcpu
*vcpu
, int vec
)
4726 * Update instruction length as we may reinject the exception
4727 * from user space while in guest debugging mode.
4729 to_vmx(vcpu
)->vcpu
.arch
.event_exit_inst_len
=
4730 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4731 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_SW_BP
)
4735 if (vcpu
->guest_debug
&
4736 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))
4753 static int handle_rmode_exception(struct kvm_vcpu
*vcpu
,
4754 int vec
, u32 err_code
)
4757 * Instruction with address size override prefix opcode 0x67
4758 * Cause the #SS fault with 0 error code in VM86 mode.
4760 if (((vec
== GP_VECTOR
) || (vec
== SS_VECTOR
)) && err_code
== 0) {
4761 if (emulate_instruction(vcpu
, 0) == EMULATE_DONE
) {
4762 if (vcpu
->arch
.halt_request
) {
4763 vcpu
->arch
.halt_request
= 0;
4764 return kvm_emulate_halt(vcpu
);
4772 * Forward all other exceptions that are valid in real mode.
4773 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4774 * the required debugging infrastructure rework.
4776 kvm_queue_exception(vcpu
, vec
);
4781 * Trigger machine check on the host. We assume all the MSRs are already set up
4782 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4783 * We pass a fake environment to the machine check handler because we want
4784 * the guest to be always treated like user space, no matter what context
4785 * it used internally.
4787 static void kvm_machine_check(void)
4789 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4790 struct pt_regs regs
= {
4791 .cs
= 3, /* Fake ring 3 no matter what the guest ran on */
4792 .flags
= X86_EFLAGS_IF
,
4795 do_machine_check(®s
, 0);
4799 static int handle_machine_check(struct kvm_vcpu
*vcpu
)
4801 /* already handled by vcpu_run */
4805 static int handle_exception(struct kvm_vcpu
*vcpu
)
4807 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
4808 struct kvm_run
*kvm_run
= vcpu
->run
;
4809 u32 intr_info
, ex_no
, error_code
;
4810 unsigned long cr2
, rip
, dr6
;
4812 enum emulation_result er
;
4814 vect_info
= vmx
->idt_vectoring_info
;
4815 intr_info
= vmx
->exit_intr_info
;
4817 if (is_machine_check(intr_info
))
4818 return handle_machine_check(vcpu
);
4820 if ((intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
)
4821 return 1; /* already handled by vmx_vcpu_run() */
4823 if (is_no_device(intr_info
)) {
4824 vmx_fpu_activate(vcpu
);
4828 if (is_invalid_opcode(intr_info
)) {
4829 er
= emulate_instruction(vcpu
, EMULTYPE_TRAP_UD
);
4830 if (er
!= EMULATE_DONE
)
4831 kvm_queue_exception(vcpu
, UD_VECTOR
);
4836 if (intr_info
& INTR_INFO_DELIVER_CODE_MASK
)
4837 error_code
= vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
4840 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4841 * MMIO, it is better to report an internal error.
4842 * See the comments in vmx_handle_exit.
4844 if ((vect_info
& VECTORING_INFO_VALID_MASK
) &&
4845 !(is_page_fault(intr_info
) && !(error_code
& PFERR_RSVD_MASK
))) {
4846 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
4847 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_SIMUL_EX
;
4848 vcpu
->run
->internal
.ndata
= 2;
4849 vcpu
->run
->internal
.data
[0] = vect_info
;
4850 vcpu
->run
->internal
.data
[1] = intr_info
;
4854 if (is_page_fault(intr_info
)) {
4855 /* EPT won't cause page fault directly */
4857 cr2
= vmcs_readl(EXIT_QUALIFICATION
);
4858 trace_kvm_page_fault(cr2
, error_code
);
4860 if (kvm_event_needs_reinjection(vcpu
))
4861 kvm_mmu_unprotect_page_virt(vcpu
, cr2
);
4862 return kvm_mmu_page_fault(vcpu
, cr2
, error_code
, NULL
, 0);
4865 ex_no
= intr_info
& INTR_INFO_VECTOR_MASK
;
4867 if (vmx
->rmode
.vm86_active
&& rmode_exception(vcpu
, ex_no
))
4868 return handle_rmode_exception(vcpu
, ex_no
, error_code
);
4872 dr6
= vmcs_readl(EXIT_QUALIFICATION
);
4873 if (!(vcpu
->guest_debug
&
4874 (KVM_GUESTDBG_SINGLESTEP
| KVM_GUESTDBG_USE_HW_BP
))) {
4875 vcpu
->arch
.dr6
&= ~15;
4876 vcpu
->arch
.dr6
|= dr6
;
4877 if (!(dr6
& ~DR6_RESERVED
)) /* icebp */
4878 skip_emulated_instruction(vcpu
);
4880 kvm_queue_exception(vcpu
, DB_VECTOR
);
4883 kvm_run
->debug
.arch
.dr6
= dr6
| DR6_FIXED_1
;
4884 kvm_run
->debug
.arch
.dr7
= vmcs_readl(GUEST_DR7
);
4888 * Update instruction length as we may reinject #BP from
4889 * user space while in guest debugging mode. Reading it for
4890 * #DB as well causes no harm, it is not used in that case.
4892 vmx
->vcpu
.arch
.event_exit_inst_len
=
4893 vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
4894 kvm_run
->exit_reason
= KVM_EXIT_DEBUG
;
4895 rip
= kvm_rip_read(vcpu
);
4896 kvm_run
->debug
.arch
.pc
= vmcs_readl(GUEST_CS_BASE
) + rip
;
4897 kvm_run
->debug
.arch
.exception
= ex_no
;
4900 kvm_run
->exit_reason
= KVM_EXIT_EXCEPTION
;
4901 kvm_run
->ex
.exception
= ex_no
;
4902 kvm_run
->ex
.error_code
= error_code
;
4908 static int handle_external_interrupt(struct kvm_vcpu
*vcpu
)
4910 ++vcpu
->stat
.irq_exits
;
4914 static int handle_triple_fault(struct kvm_vcpu
*vcpu
)
4916 vcpu
->run
->exit_reason
= KVM_EXIT_SHUTDOWN
;
4920 static int handle_io(struct kvm_vcpu
*vcpu
)
4922 unsigned long exit_qualification
;
4923 int size
, in
, string
;
4926 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
4927 string
= (exit_qualification
& 16) != 0;
4928 in
= (exit_qualification
& 8) != 0;
4930 ++vcpu
->stat
.io_exits
;
4933 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
4935 port
= exit_qualification
>> 16;
4936 size
= (exit_qualification
& 7) + 1;
4937 skip_emulated_instruction(vcpu
);
4939 return kvm_fast_pio_out(vcpu
, size
, port
);
4943 vmx_patch_hypercall(struct kvm_vcpu
*vcpu
, unsigned char *hypercall
)
4946 * Patch in the VMCALL instruction:
4948 hypercall
[0] = 0x0f;
4949 hypercall
[1] = 0x01;
4950 hypercall
[2] = 0xc1;
4953 static bool nested_cr0_valid(struct vmcs12
*vmcs12
, unsigned long val
)
4955 unsigned long always_on
= VMXON_CR0_ALWAYSON
;
4957 if (nested_vmx_secondary_ctls_high
&
4958 SECONDARY_EXEC_UNRESTRICTED_GUEST
&&
4959 nested_cpu_has2(vmcs12
, SECONDARY_EXEC_UNRESTRICTED_GUEST
))
4960 always_on
&= ~(X86_CR0_PE
| X86_CR0_PG
);
4961 return (val
& always_on
) == always_on
;
4964 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
4965 static int handle_set_cr0(struct kvm_vcpu
*vcpu
, unsigned long val
)
4967 if (is_guest_mode(vcpu
)) {
4968 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
4969 unsigned long orig_val
= val
;
4972 * We get here when L2 changed cr0 in a way that did not change
4973 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4974 * but did change L0 shadowed bits. So we first calculate the
4975 * effective cr0 value that L1 would like to write into the
4976 * hardware. It consists of the L2-owned bits from the new
4977 * value combined with the L1-owned bits from L1's guest_cr0.
4979 val
= (val
& ~vmcs12
->cr0_guest_host_mask
) |
4980 (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
);
4982 if (!nested_cr0_valid(vmcs12
, val
))
4985 if (kvm_set_cr0(vcpu
, val
))
4987 vmcs_writel(CR0_READ_SHADOW
, orig_val
);
4990 if (to_vmx(vcpu
)->nested
.vmxon
&&
4991 ((val
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
))
4993 return kvm_set_cr0(vcpu
, val
);
4997 static int handle_set_cr4(struct kvm_vcpu
*vcpu
, unsigned long val
)
4999 if (is_guest_mode(vcpu
)) {
5000 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
5001 unsigned long orig_val
= val
;
5003 /* analogously to handle_set_cr0 */
5004 val
= (val
& ~vmcs12
->cr4_guest_host_mask
) |
5005 (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
);
5006 if (kvm_set_cr4(vcpu
, val
))
5008 vmcs_writel(CR4_READ_SHADOW
, orig_val
);
5011 return kvm_set_cr4(vcpu
, val
);
5014 /* called to set cr0 as approriate for clts instruction exit. */
5015 static void handle_clts(struct kvm_vcpu
*vcpu
)
5017 if (is_guest_mode(vcpu
)) {
5019 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5020 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5021 * just pretend it's off (also in arch.cr0 for fpu_activate).
5023 vmcs_writel(CR0_READ_SHADOW
,
5024 vmcs_readl(CR0_READ_SHADOW
) & ~X86_CR0_TS
);
5025 vcpu
->arch
.cr0
&= ~X86_CR0_TS
;
5027 vmx_set_cr0(vcpu
, kvm_read_cr0_bits(vcpu
, ~X86_CR0_TS
));
5030 static int handle_cr(struct kvm_vcpu
*vcpu
)
5032 unsigned long exit_qualification
, val
;
5037 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5038 cr
= exit_qualification
& 15;
5039 reg
= (exit_qualification
>> 8) & 15;
5040 switch ((exit_qualification
>> 4) & 3) {
5041 case 0: /* mov to cr */
5042 val
= kvm_register_read(vcpu
, reg
);
5043 trace_kvm_cr_write(cr
, val
);
5046 err
= handle_set_cr0(vcpu
, val
);
5047 kvm_complete_insn_gp(vcpu
, err
);
5050 err
= kvm_set_cr3(vcpu
, val
);
5051 kvm_complete_insn_gp(vcpu
, err
);
5054 err
= handle_set_cr4(vcpu
, val
);
5055 kvm_complete_insn_gp(vcpu
, err
);
5058 u8 cr8_prev
= kvm_get_cr8(vcpu
);
5059 u8 cr8
= kvm_register_read(vcpu
, reg
);
5060 err
= kvm_set_cr8(vcpu
, cr8
);
5061 kvm_complete_insn_gp(vcpu
, err
);
5062 if (irqchip_in_kernel(vcpu
->kvm
))
5064 if (cr8_prev
<= cr8
)
5066 vcpu
->run
->exit_reason
= KVM_EXIT_SET_TPR
;
5073 trace_kvm_cr_write(0, kvm_read_cr0(vcpu
));
5074 skip_emulated_instruction(vcpu
);
5075 vmx_fpu_activate(vcpu
);
5077 case 1: /*mov from cr*/
5080 val
= kvm_read_cr3(vcpu
);
5081 kvm_register_write(vcpu
, reg
, val
);
5082 trace_kvm_cr_read(cr
, val
);
5083 skip_emulated_instruction(vcpu
);
5086 val
= kvm_get_cr8(vcpu
);
5087 kvm_register_write(vcpu
, reg
, val
);
5088 trace_kvm_cr_read(cr
, val
);
5089 skip_emulated_instruction(vcpu
);
5094 val
= (exit_qualification
>> LMSW_SOURCE_DATA_SHIFT
) & 0x0f;
5095 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu
) & ~0xful
) | val
);
5096 kvm_lmsw(vcpu
, val
);
5098 skip_emulated_instruction(vcpu
);
5103 vcpu
->run
->exit_reason
= 0;
5104 vcpu_unimpl(vcpu
, "unhandled control register: op %d cr %d\n",
5105 (int)(exit_qualification
>> 4) & 3, cr
);
5109 static int handle_dr(struct kvm_vcpu
*vcpu
)
5111 unsigned long exit_qualification
;
5114 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5115 if (!kvm_require_cpl(vcpu
, 0))
5117 dr
= vmcs_readl(GUEST_DR7
);
5120 * As the vm-exit takes precedence over the debug trap, we
5121 * need to emulate the latter, either for the host or the
5122 * guest debugging itself.
5124 if (vcpu
->guest_debug
& KVM_GUESTDBG_USE_HW_BP
) {
5125 vcpu
->run
->debug
.arch
.dr6
= vcpu
->arch
.dr6
;
5126 vcpu
->run
->debug
.arch
.dr7
= dr
;
5127 vcpu
->run
->debug
.arch
.pc
=
5128 vmcs_readl(GUEST_CS_BASE
) +
5129 vmcs_readl(GUEST_RIP
);
5130 vcpu
->run
->debug
.arch
.exception
= DB_VECTOR
;
5131 vcpu
->run
->exit_reason
= KVM_EXIT_DEBUG
;
5134 vcpu
->arch
.dr7
&= ~DR7_GD
;
5135 vcpu
->arch
.dr6
|= DR6_BD
;
5136 vmcs_writel(GUEST_DR7
, vcpu
->arch
.dr7
);
5137 kvm_queue_exception(vcpu
, DB_VECTOR
);
5142 if (vcpu
->guest_debug
== 0) {
5143 u32 cpu_based_vm_exec_control
;
5145 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5146 cpu_based_vm_exec_control
&= ~CPU_BASED_MOV_DR_EXITING
;
5147 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5150 * No more DR vmexits; force a reload of the debug registers
5151 * and reenter on this instruction. The next vmexit will
5152 * retrieve the full state of the debug registers.
5154 vcpu
->arch
.switch_db_regs
|= KVM_DEBUGREG_WONT_EXIT
;
5158 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5159 dr
= exit_qualification
& DEBUG_REG_ACCESS_NUM
;
5160 reg
= DEBUG_REG_ACCESS_REG(exit_qualification
);
5161 if (exit_qualification
& TYPE_MOV_FROM_DR
) {
5164 if (kvm_get_dr(vcpu
, dr
, &val
))
5166 kvm_register_write(vcpu
, reg
, val
);
5168 if (kvm_set_dr(vcpu
, dr
, kvm_register_read(vcpu
, reg
)))
5171 skip_emulated_instruction(vcpu
);
5175 static u64
vmx_get_dr6(struct kvm_vcpu
*vcpu
)
5177 return vcpu
->arch
.dr6
;
5180 static void vmx_set_dr6(struct kvm_vcpu
*vcpu
, unsigned long val
)
5184 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu
*vcpu
)
5186 u32 cpu_based_vm_exec_control
;
5188 get_debugreg(vcpu
->arch
.db
[0], 0);
5189 get_debugreg(vcpu
->arch
.db
[1], 1);
5190 get_debugreg(vcpu
->arch
.db
[2], 2);
5191 get_debugreg(vcpu
->arch
.db
[3], 3);
5192 get_debugreg(vcpu
->arch
.dr6
, 6);
5193 vcpu
->arch
.dr7
= vmcs_readl(GUEST_DR7
);
5195 vcpu
->arch
.switch_db_regs
&= ~KVM_DEBUGREG_WONT_EXIT
;
5197 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5198 cpu_based_vm_exec_control
|= CPU_BASED_MOV_DR_EXITING
;
5199 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5202 static void vmx_set_dr7(struct kvm_vcpu
*vcpu
, unsigned long val
)
5204 vmcs_writel(GUEST_DR7
, val
);
5207 static int handle_cpuid(struct kvm_vcpu
*vcpu
)
5209 kvm_emulate_cpuid(vcpu
);
5213 static int handle_rdmsr(struct kvm_vcpu
*vcpu
)
5215 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5218 if (vmx_get_msr(vcpu
, ecx
, &data
)) {
5219 trace_kvm_msr_read_ex(ecx
);
5220 kvm_inject_gp(vcpu
, 0);
5224 trace_kvm_msr_read(ecx
, data
);
5226 /* FIXME: handling of bits 32:63 of rax, rdx */
5227 vcpu
->arch
.regs
[VCPU_REGS_RAX
] = data
& -1u;
5228 vcpu
->arch
.regs
[VCPU_REGS_RDX
] = (data
>> 32) & -1u;
5229 skip_emulated_instruction(vcpu
);
5233 static int handle_wrmsr(struct kvm_vcpu
*vcpu
)
5235 struct msr_data msr
;
5236 u32 ecx
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
5237 u64 data
= (vcpu
->arch
.regs
[VCPU_REGS_RAX
] & -1u)
5238 | ((u64
)(vcpu
->arch
.regs
[VCPU_REGS_RDX
] & -1u) << 32);
5242 msr
.host_initiated
= false;
5243 if (vmx_set_msr(vcpu
, &msr
) != 0) {
5244 trace_kvm_msr_write_ex(ecx
, data
);
5245 kvm_inject_gp(vcpu
, 0);
5249 trace_kvm_msr_write(ecx
, data
);
5250 skip_emulated_instruction(vcpu
);
5254 static int handle_tpr_below_threshold(struct kvm_vcpu
*vcpu
)
5256 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5260 static int handle_interrupt_window(struct kvm_vcpu
*vcpu
)
5262 u32 cpu_based_vm_exec_control
;
5264 /* clear pending irq */
5265 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5266 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
5267 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5269 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5271 ++vcpu
->stat
.irq_window_exits
;
5274 * If the user space waits to inject interrupts, exit as soon as
5277 if (!irqchip_in_kernel(vcpu
->kvm
) &&
5278 vcpu
->run
->request_interrupt_window
&&
5279 !kvm_cpu_has_interrupt(vcpu
)) {
5280 vcpu
->run
->exit_reason
= KVM_EXIT_IRQ_WINDOW_OPEN
;
5286 static int handle_halt(struct kvm_vcpu
*vcpu
)
5288 skip_emulated_instruction(vcpu
);
5289 return kvm_emulate_halt(vcpu
);
5292 static int handle_vmcall(struct kvm_vcpu
*vcpu
)
5294 skip_emulated_instruction(vcpu
);
5295 kvm_emulate_hypercall(vcpu
);
5299 static int handle_invd(struct kvm_vcpu
*vcpu
)
5301 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5304 static int handle_invlpg(struct kvm_vcpu
*vcpu
)
5306 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5308 kvm_mmu_invlpg(vcpu
, exit_qualification
);
5309 skip_emulated_instruction(vcpu
);
5313 static int handle_rdpmc(struct kvm_vcpu
*vcpu
)
5317 err
= kvm_rdpmc(vcpu
);
5318 kvm_complete_insn_gp(vcpu
, err
);
5323 static int handle_wbinvd(struct kvm_vcpu
*vcpu
)
5325 skip_emulated_instruction(vcpu
);
5326 kvm_emulate_wbinvd(vcpu
);
5330 static int handle_xsetbv(struct kvm_vcpu
*vcpu
)
5332 u64 new_bv
= kvm_read_edx_eax(vcpu
);
5333 u32 index
= kvm_register_read(vcpu
, VCPU_REGS_RCX
);
5335 if (kvm_set_xcr(vcpu
, index
, new_bv
) == 0)
5336 skip_emulated_instruction(vcpu
);
5340 static int handle_apic_access(struct kvm_vcpu
*vcpu
)
5342 if (likely(fasteoi
)) {
5343 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5344 int access_type
, offset
;
5346 access_type
= exit_qualification
& APIC_ACCESS_TYPE
;
5347 offset
= exit_qualification
& APIC_ACCESS_OFFSET
;
5349 * Sane guest uses MOV to write EOI, with written value
5350 * not cared. So make a short-circuit here by avoiding
5351 * heavy instruction emulation.
5353 if ((access_type
== TYPE_LINEAR_APIC_INST_WRITE
) &&
5354 (offset
== APIC_EOI
)) {
5355 kvm_lapic_set_eoi(vcpu
);
5356 skip_emulated_instruction(vcpu
);
5360 return emulate_instruction(vcpu
, 0) == EMULATE_DONE
;
5363 static int handle_apic_eoi_induced(struct kvm_vcpu
*vcpu
)
5365 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5366 int vector
= exit_qualification
& 0xff;
5368 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5369 kvm_apic_set_eoi_accelerated(vcpu
, vector
);
5373 static int handle_apic_write(struct kvm_vcpu
*vcpu
)
5375 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5376 u32 offset
= exit_qualification
& 0xfff;
5378 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5379 kvm_apic_write_nodecode(vcpu
, offset
);
5383 static int handle_task_switch(struct kvm_vcpu
*vcpu
)
5385 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5386 unsigned long exit_qualification
;
5387 bool has_error_code
= false;
5390 int reason
, type
, idt_v
, idt_index
;
5392 idt_v
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
);
5393 idt_index
= (vmx
->idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
);
5394 type
= (vmx
->idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
);
5396 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5398 reason
= (u32
)exit_qualification
>> 30;
5399 if (reason
== TASK_SWITCH_GATE
&& idt_v
) {
5401 case INTR_TYPE_NMI_INTR
:
5402 vcpu
->arch
.nmi_injected
= false;
5403 vmx_set_nmi_mask(vcpu
, true);
5405 case INTR_TYPE_EXT_INTR
:
5406 case INTR_TYPE_SOFT_INTR
:
5407 kvm_clear_interrupt_queue(vcpu
);
5409 case INTR_TYPE_HARD_EXCEPTION
:
5410 if (vmx
->idt_vectoring_info
&
5411 VECTORING_INFO_DELIVER_CODE_MASK
) {
5412 has_error_code
= true;
5414 vmcs_read32(IDT_VECTORING_ERROR_CODE
);
5417 case INTR_TYPE_SOFT_EXCEPTION
:
5418 kvm_clear_exception_queue(vcpu
);
5424 tss_selector
= exit_qualification
;
5426 if (!idt_v
|| (type
!= INTR_TYPE_HARD_EXCEPTION
&&
5427 type
!= INTR_TYPE_EXT_INTR
&&
5428 type
!= INTR_TYPE_NMI_INTR
))
5429 skip_emulated_instruction(vcpu
);
5431 if (kvm_task_switch(vcpu
, tss_selector
,
5432 type
== INTR_TYPE_SOFT_INTR
? idt_index
: -1, reason
,
5433 has_error_code
, error_code
) == EMULATE_FAIL
) {
5434 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5435 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5436 vcpu
->run
->internal
.ndata
= 0;
5440 /* clear all local breakpoint enable flags */
5441 vmcs_writel(GUEST_DR7
, vmcs_readl(GUEST_DR7
) & ~0x55);
5444 * TODO: What about debug traps on tss switch?
5445 * Are we supposed to inject them and update dr6?
5451 static int handle_ept_violation(struct kvm_vcpu
*vcpu
)
5453 unsigned long exit_qualification
;
5458 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
5460 gla_validity
= (exit_qualification
>> 7) & 0x3;
5461 if (gla_validity
!= 0x3 && gla_validity
!= 0x1 && gla_validity
!= 0) {
5462 printk(KERN_ERR
"EPT: Handling EPT violation failed!\n");
5463 printk(KERN_ERR
"EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5464 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS
),
5465 vmcs_readl(GUEST_LINEAR_ADDRESS
));
5466 printk(KERN_ERR
"EPT: Exit qualification is 0x%lx\n",
5467 (long unsigned int)exit_qualification
);
5468 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5469 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_VIOLATION
;
5474 * EPT violation happened while executing iret from NMI,
5475 * "blocked by NMI" bit has to be set before next VM entry.
5476 * There are errata that may cause this bit to not be set:
5479 if (!(to_vmx(vcpu
)->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
5480 cpu_has_virtual_nmis() &&
5481 (exit_qualification
& INTR_INFO_UNBLOCK_NMI
))
5482 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
, GUEST_INTR_STATE_NMI
);
5484 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5485 trace_kvm_page_fault(gpa
, exit_qualification
);
5487 /* It is a write fault? */
5488 error_code
= exit_qualification
& (1U << 1);
5489 /* It is a fetch fault? */
5490 error_code
|= (exit_qualification
& (1U << 2)) << 2;
5491 /* ept page table is present? */
5492 error_code
|= (exit_qualification
>> 3) & 0x1;
5494 vcpu
->arch
.exit_qualification
= exit_qualification
;
5496 return kvm_mmu_page_fault(vcpu
, gpa
, error_code
, NULL
, 0);
5499 static u64
ept_rsvd_mask(u64 spte
, int level
)
5504 for (i
= 51; i
> boot_cpu_data
.x86_phys_bits
; i
--)
5505 mask
|= (1ULL << i
);
5508 /* bits 7:3 reserved */
5510 else if (level
== 2) {
5511 if (spte
& (1ULL << 7))
5512 /* 2MB ref, bits 20:12 reserved */
5515 /* bits 6:3 reserved */
5522 static void ept_misconfig_inspect_spte(struct kvm_vcpu
*vcpu
, u64 spte
,
5525 printk(KERN_ERR
"%s: spte 0x%llx level %d\n", __func__
, spte
, level
);
5527 /* 010b (write-only) */
5528 WARN_ON((spte
& 0x7) == 0x2);
5530 /* 110b (write/execute) */
5531 WARN_ON((spte
& 0x7) == 0x6);
5533 /* 100b (execute-only) and value not supported by logical processor */
5534 if (!cpu_has_vmx_ept_execute_only())
5535 WARN_ON((spte
& 0x7) == 0x4);
5539 u64 rsvd_bits
= spte
& ept_rsvd_mask(spte
, level
);
5541 if (rsvd_bits
!= 0) {
5542 printk(KERN_ERR
"%s: rsvd_bits = 0x%llx\n",
5543 __func__
, rsvd_bits
);
5547 if (level
== 1 || (level
== 2 && (spte
& (1ULL << 7)))) {
5548 u64 ept_mem_type
= (spte
& 0x38) >> 3;
5550 if (ept_mem_type
== 2 || ept_mem_type
== 3 ||
5551 ept_mem_type
== 7) {
5552 printk(KERN_ERR
"%s: ept_mem_type=0x%llx\n",
5553 __func__
, ept_mem_type
);
5560 static int handle_ept_misconfig(struct kvm_vcpu
*vcpu
)
5563 int nr_sptes
, i
, ret
;
5566 gpa
= vmcs_read64(GUEST_PHYSICAL_ADDRESS
);
5567 if (!kvm_io_bus_write(vcpu
->kvm
, KVM_FAST_MMIO_BUS
, gpa
, 0, NULL
)) {
5568 skip_emulated_instruction(vcpu
);
5572 ret
= handle_mmio_page_fault_common(vcpu
, gpa
, true);
5573 if (likely(ret
== RET_MMIO_PF_EMULATE
))
5574 return x86_emulate_instruction(vcpu
, gpa
, 0, NULL
, 0) ==
5577 if (unlikely(ret
== RET_MMIO_PF_INVALID
))
5578 return kvm_mmu_page_fault(vcpu
, gpa
, 0, NULL
, 0);
5580 if (unlikely(ret
== RET_MMIO_PF_RETRY
))
5583 /* It is the real ept misconfig */
5584 printk(KERN_ERR
"EPT: Misconfiguration.\n");
5585 printk(KERN_ERR
"EPT: GPA: 0x%llx\n", gpa
);
5587 nr_sptes
= kvm_mmu_get_spte_hierarchy(vcpu
, gpa
, sptes
);
5589 for (i
= PT64_ROOT_LEVEL
; i
> PT64_ROOT_LEVEL
- nr_sptes
; --i
)
5590 ept_misconfig_inspect_spte(vcpu
, sptes
[i
-1], i
);
5592 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
5593 vcpu
->run
->hw
.hardware_exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
5598 static int handle_nmi_window(struct kvm_vcpu
*vcpu
)
5600 u32 cpu_based_vm_exec_control
;
5602 /* clear pending NMI */
5603 cpu_based_vm_exec_control
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5604 cpu_based_vm_exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
5605 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, cpu_based_vm_exec_control
);
5606 ++vcpu
->stat
.nmi_window_exits
;
5607 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
5612 static int handle_invalid_guest_state(struct kvm_vcpu
*vcpu
)
5614 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5615 enum emulation_result err
= EMULATE_DONE
;
5618 bool intr_window_requested
;
5619 unsigned count
= 130;
5621 cpu_exec_ctrl
= vmcs_read32(CPU_BASED_VM_EXEC_CONTROL
);
5622 intr_window_requested
= cpu_exec_ctrl
& CPU_BASED_VIRTUAL_INTR_PENDING
;
5624 while (!guest_state_valid(vcpu
) && count
-- != 0) {
5625 if (intr_window_requested
&& vmx_interrupt_allowed(vcpu
))
5626 return handle_interrupt_window(&vmx
->vcpu
);
5628 if (test_bit(KVM_REQ_EVENT
, &vcpu
->requests
))
5631 err
= emulate_instruction(vcpu
, EMULTYPE_NO_REEXECUTE
);
5633 if (err
== EMULATE_USER_EXIT
) {
5634 ++vcpu
->stat
.mmio_exits
;
5639 if (err
!= EMULATE_DONE
) {
5640 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
5641 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_EMULATION
;
5642 vcpu
->run
->internal
.ndata
= 0;
5646 if (vcpu
->arch
.halt_request
) {
5647 vcpu
->arch
.halt_request
= 0;
5648 ret
= kvm_emulate_halt(vcpu
);
5652 if (signal_pending(current
))
5658 vmx
->emulation_required
= emulation_required(vcpu
);
5664 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
5665 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
5667 static int handle_pause(struct kvm_vcpu
*vcpu
)
5669 skip_emulated_instruction(vcpu
);
5670 kvm_vcpu_on_spin(vcpu
);
5675 static int handle_nop(struct kvm_vcpu
*vcpu
)
5677 skip_emulated_instruction(vcpu
);
5681 static int handle_mwait(struct kvm_vcpu
*vcpu
)
5683 printk_once(KERN_WARNING
"kvm: MWAIT instruction emulated as NOP!\n");
5684 return handle_nop(vcpu
);
5687 static int handle_monitor(struct kvm_vcpu
*vcpu
)
5689 printk_once(KERN_WARNING
"kvm: MONITOR instruction emulated as NOP!\n");
5690 return handle_nop(vcpu
);
5694 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
5695 * We could reuse a single VMCS for all the L2 guests, but we also want the
5696 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
5697 * allows keeping them loaded on the processor, and in the future will allow
5698 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
5699 * every entry if they never change.
5700 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
5701 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
5703 * The following functions allocate and free a vmcs02 in this pool.
5706 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
5707 static struct loaded_vmcs
*nested_get_current_vmcs02(struct vcpu_vmx
*vmx
)
5709 struct vmcs02_list
*item
;
5710 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5711 if (item
->vmptr
== vmx
->nested
.current_vmptr
) {
5712 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5713 return &item
->vmcs02
;
5716 if (vmx
->nested
.vmcs02_num
>= max(VMCS02_POOL_SIZE
, 1)) {
5717 /* Recycle the least recently used VMCS. */
5718 item
= list_entry(vmx
->nested
.vmcs02_pool
.prev
,
5719 struct vmcs02_list
, list
);
5720 item
->vmptr
= vmx
->nested
.current_vmptr
;
5721 list_move(&item
->list
, &vmx
->nested
.vmcs02_pool
);
5722 return &item
->vmcs02
;
5725 /* Create a new VMCS */
5726 item
= kmalloc(sizeof(struct vmcs02_list
), GFP_KERNEL
);
5729 item
->vmcs02
.vmcs
= alloc_vmcs();
5730 if (!item
->vmcs02
.vmcs
) {
5734 loaded_vmcs_init(&item
->vmcs02
);
5735 item
->vmptr
= vmx
->nested
.current_vmptr
;
5736 list_add(&(item
->list
), &(vmx
->nested
.vmcs02_pool
));
5737 vmx
->nested
.vmcs02_num
++;
5738 return &item
->vmcs02
;
5741 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
5742 static void nested_free_vmcs02(struct vcpu_vmx
*vmx
, gpa_t vmptr
)
5744 struct vmcs02_list
*item
;
5745 list_for_each_entry(item
, &vmx
->nested
.vmcs02_pool
, list
)
5746 if (item
->vmptr
== vmptr
) {
5747 free_loaded_vmcs(&item
->vmcs02
);
5748 list_del(&item
->list
);
5750 vmx
->nested
.vmcs02_num
--;
5756 * Free all VMCSs saved for this vcpu, except the one pointed by
5757 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
5758 * currently used, if running L2), and vmcs01 when running L2.
5760 static void nested_free_all_saved_vmcss(struct vcpu_vmx
*vmx
)
5762 struct vmcs02_list
*item
, *n
;
5763 list_for_each_entry_safe(item
, n
, &vmx
->nested
.vmcs02_pool
, list
) {
5764 if (vmx
->loaded_vmcs
!= &item
->vmcs02
)
5765 free_loaded_vmcs(&item
->vmcs02
);
5766 list_del(&item
->list
);
5769 vmx
->nested
.vmcs02_num
= 0;
5771 if (vmx
->loaded_vmcs
!= &vmx
->vmcs01
)
5772 free_loaded_vmcs(&vmx
->vmcs01
);
5776 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5777 * set the success or error code of an emulated VMX instruction, as specified
5778 * by Vol 2B, VMX Instruction Reference, "Conventions".
5780 static void nested_vmx_succeed(struct kvm_vcpu
*vcpu
)
5782 vmx_set_rflags(vcpu
, vmx_get_rflags(vcpu
)
5783 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5784 X86_EFLAGS_ZF
| X86_EFLAGS_SF
| X86_EFLAGS_OF
));
5787 static void nested_vmx_failInvalid(struct kvm_vcpu
*vcpu
)
5789 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5790 & ~(X86_EFLAGS_PF
| X86_EFLAGS_AF
| X86_EFLAGS_ZF
|
5791 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5795 static void nested_vmx_failValid(struct kvm_vcpu
*vcpu
,
5796 u32 vm_instruction_error
)
5798 if (to_vmx(vcpu
)->nested
.current_vmptr
== -1ull) {
5800 * failValid writes the error number to the current VMCS, which
5801 * can't be done there isn't a current VMCS.
5803 nested_vmx_failInvalid(vcpu
);
5806 vmx_set_rflags(vcpu
, (vmx_get_rflags(vcpu
)
5807 & ~(X86_EFLAGS_CF
| X86_EFLAGS_PF
| X86_EFLAGS_AF
|
5808 X86_EFLAGS_SF
| X86_EFLAGS_OF
))
5810 get_vmcs12(vcpu
)->vm_instruction_error
= vm_instruction_error
;
5812 * We don't need to force a shadow sync because
5813 * VM_INSTRUCTION_ERROR is not shadowed
5817 static enum hrtimer_restart
vmx_preemption_timer_fn(struct hrtimer
*timer
)
5819 struct vcpu_vmx
*vmx
=
5820 container_of(timer
, struct vcpu_vmx
, nested
.preemption_timer
);
5822 vmx
->nested
.preemption_timer_expired
= true;
5823 kvm_make_request(KVM_REQ_EVENT
, &vmx
->vcpu
);
5824 kvm_vcpu_kick(&vmx
->vcpu
);
5826 return HRTIMER_NORESTART
;
5830 * Decode the memory-address operand of a vmx instruction, as recorded on an
5831 * exit caused by such an instruction (run by a guest hypervisor).
5832 * On success, returns 0. When the operand is invalid, returns 1 and throws
5835 static int get_vmx_mem_address(struct kvm_vcpu
*vcpu
,
5836 unsigned long exit_qualification
,
5837 u32 vmx_instruction_info
, gva_t
*ret
)
5840 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5841 * Execution", on an exit, vmx_instruction_info holds most of the
5842 * addressing components of the operand. Only the displacement part
5843 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5844 * For how an actual address is calculated from all these components,
5845 * refer to Vol. 1, "Operand Addressing".
5847 int scaling
= vmx_instruction_info
& 3;
5848 int addr_size
= (vmx_instruction_info
>> 7) & 7;
5849 bool is_reg
= vmx_instruction_info
& (1u << 10);
5850 int seg_reg
= (vmx_instruction_info
>> 15) & 7;
5851 int index_reg
= (vmx_instruction_info
>> 18) & 0xf;
5852 bool index_is_valid
= !(vmx_instruction_info
& (1u << 22));
5853 int base_reg
= (vmx_instruction_info
>> 23) & 0xf;
5854 bool base_is_valid
= !(vmx_instruction_info
& (1u << 27));
5857 kvm_queue_exception(vcpu
, UD_VECTOR
);
5861 /* Addr = segment_base + offset */
5862 /* offset = base + [index * scale] + displacement */
5863 *ret
= vmx_get_segment_base(vcpu
, seg_reg
);
5865 *ret
+= kvm_register_read(vcpu
, base_reg
);
5867 *ret
+= kvm_register_read(vcpu
, index_reg
)<<scaling
;
5868 *ret
+= exit_qualification
; /* holds the displacement */
5870 if (addr_size
== 1) /* 32 bit */
5874 * TODO: throw #GP (and return 1) in various cases that the VM*
5875 * instructions require it - e.g., offset beyond segment limit,
5876 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5877 * address, and so on. Currently these are not checked.
5883 * This function performs the various checks including
5884 * - if it's 4KB aligned
5885 * - No bits beyond the physical address width are set
5886 * - Returns 0 on success or else 1
5887 * (Intel SDM Section 30.3)
5889 static int nested_vmx_check_vmptr(struct kvm_vcpu
*vcpu
, int exit_reason
,
5894 struct x86_exception e
;
5896 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5897 int maxphyaddr
= cpuid_maxphyaddr(vcpu
);
5899 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
5900 vmcs_read32(VMX_INSTRUCTION_INFO
), &gva
))
5903 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &vmptr
,
5904 sizeof(vmptr
), &e
)) {
5905 kvm_inject_page_fault(vcpu
, &e
);
5909 switch (exit_reason
) {
5910 case EXIT_REASON_VMON
:
5913 * The first 4 bytes of VMXON region contain the supported
5914 * VMCS revision identifier
5916 * Note - IA32_VMX_BASIC[48] will never be 1
5917 * for the nested case;
5918 * which replaces physical address width with 32
5921 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
) || (vmptr
>> maxphyaddr
)) {
5922 nested_vmx_failInvalid(vcpu
);
5923 skip_emulated_instruction(vcpu
);
5927 page
= nested_get_page(vcpu
, vmptr
);
5929 *(u32
*)kmap(page
) != VMCS12_REVISION
) {
5930 nested_vmx_failInvalid(vcpu
);
5932 skip_emulated_instruction(vcpu
);
5936 vmx
->nested
.vmxon_ptr
= vmptr
;
5938 case EXIT_REASON_VMCLEAR
:
5939 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
) || (vmptr
>> maxphyaddr
)) {
5940 nested_vmx_failValid(vcpu
,
5941 VMXERR_VMCLEAR_INVALID_ADDRESS
);
5942 skip_emulated_instruction(vcpu
);
5946 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
5947 nested_vmx_failValid(vcpu
,
5948 VMXERR_VMCLEAR_VMXON_POINTER
);
5949 skip_emulated_instruction(vcpu
);
5953 case EXIT_REASON_VMPTRLD
:
5954 if (!IS_ALIGNED(vmptr
, PAGE_SIZE
) || (vmptr
>> maxphyaddr
)) {
5955 nested_vmx_failValid(vcpu
,
5956 VMXERR_VMPTRLD_INVALID_ADDRESS
);
5957 skip_emulated_instruction(vcpu
);
5961 if (vmptr
== vmx
->nested
.vmxon_ptr
) {
5962 nested_vmx_failValid(vcpu
,
5963 VMXERR_VMCLEAR_VMXON_POINTER
);
5964 skip_emulated_instruction(vcpu
);
5969 return 1; /* shouldn't happen */
5978 * Emulate the VMXON instruction.
5979 * Currently, we just remember that VMX is active, and do not save or even
5980 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5981 * do not currently need to store anything in that guest-allocated memory
5982 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5983 * argument is different from the VMXON pointer (which the spec says they do).
5985 static int handle_vmon(struct kvm_vcpu
*vcpu
)
5987 struct kvm_segment cs
;
5988 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
5989 struct vmcs
*shadow_vmcs
;
5990 const u64 VMXON_NEEDED_FEATURES
= FEATURE_CONTROL_LOCKED
5991 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX
;
5993 /* The Intel VMX Instruction Reference lists a bunch of bits that
5994 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5995 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5996 * Otherwise, we should fail with #UD. We test these now:
5998 if (!kvm_read_cr4_bits(vcpu
, X86_CR4_VMXE
) ||
5999 !kvm_read_cr0_bits(vcpu
, X86_CR0_PE
) ||
6000 (vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
)) {
6001 kvm_queue_exception(vcpu
, UD_VECTOR
);
6005 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6006 if (is_long_mode(vcpu
) && !cs
.l
) {
6007 kvm_queue_exception(vcpu
, UD_VECTOR
);
6011 if (vmx_get_cpl(vcpu
)) {
6012 kvm_inject_gp(vcpu
, 0);
6016 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMON
, NULL
))
6019 if (vmx
->nested
.vmxon
) {
6020 nested_vmx_failValid(vcpu
, VMXERR_VMXON_IN_VMX_ROOT_OPERATION
);
6021 skip_emulated_instruction(vcpu
);
6025 if ((vmx
->nested
.msr_ia32_feature_control
& VMXON_NEEDED_FEATURES
)
6026 != VMXON_NEEDED_FEATURES
) {
6027 kvm_inject_gp(vcpu
, 0);
6031 if (enable_shadow_vmcs
) {
6032 shadow_vmcs
= alloc_vmcs();
6035 /* mark vmcs as shadow */
6036 shadow_vmcs
->revision_id
|= (1u << 31);
6037 /* init shadow vmcs */
6038 vmcs_clear(shadow_vmcs
);
6039 vmx
->nested
.current_shadow_vmcs
= shadow_vmcs
;
6042 INIT_LIST_HEAD(&(vmx
->nested
.vmcs02_pool
));
6043 vmx
->nested
.vmcs02_num
= 0;
6045 hrtimer_init(&vmx
->nested
.preemption_timer
, CLOCK_MONOTONIC
,
6047 vmx
->nested
.preemption_timer
.function
= vmx_preemption_timer_fn
;
6049 vmx
->nested
.vmxon
= true;
6051 skip_emulated_instruction(vcpu
);
6052 nested_vmx_succeed(vcpu
);
6057 * Intel's VMX Instruction Reference specifies a common set of prerequisites
6058 * for running VMX instructions (except VMXON, whose prerequisites are
6059 * slightly different). It also specifies what exception to inject otherwise.
6061 static int nested_vmx_check_permission(struct kvm_vcpu
*vcpu
)
6063 struct kvm_segment cs
;
6064 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6066 if (!vmx
->nested
.vmxon
) {
6067 kvm_queue_exception(vcpu
, UD_VECTOR
);
6071 vmx_get_segment(vcpu
, &cs
, VCPU_SREG_CS
);
6072 if ((vmx_get_rflags(vcpu
) & X86_EFLAGS_VM
) ||
6073 (is_long_mode(vcpu
) && !cs
.l
)) {
6074 kvm_queue_exception(vcpu
, UD_VECTOR
);
6078 if (vmx_get_cpl(vcpu
)) {
6079 kvm_inject_gp(vcpu
, 0);
6086 static inline void nested_release_vmcs12(struct vcpu_vmx
*vmx
)
6089 if (enable_shadow_vmcs
) {
6090 if (vmx
->nested
.current_vmcs12
!= NULL
) {
6091 /* copy to memory all shadowed fields in case
6092 they were modified */
6093 copy_shadow_to_vmcs12(vmx
);
6094 vmx
->nested
.sync_shadow_vmcs
= false;
6095 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6096 exec_control
&= ~SECONDARY_EXEC_SHADOW_VMCS
;
6097 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6098 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
6101 kunmap(vmx
->nested
.current_vmcs12_page
);
6102 nested_release_page(vmx
->nested
.current_vmcs12_page
);
6106 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6107 * just stops using VMX.
6109 static void free_nested(struct vcpu_vmx
*vmx
)
6111 if (!vmx
->nested
.vmxon
)
6113 vmx
->nested
.vmxon
= false;
6114 if (vmx
->nested
.current_vmptr
!= -1ull) {
6115 nested_release_vmcs12(vmx
);
6116 vmx
->nested
.current_vmptr
= -1ull;
6117 vmx
->nested
.current_vmcs12
= NULL
;
6119 if (enable_shadow_vmcs
)
6120 free_vmcs(vmx
->nested
.current_shadow_vmcs
);
6121 /* Unpin physical memory we referred to in current vmcs02 */
6122 if (vmx
->nested
.apic_access_page
) {
6123 nested_release_page(vmx
->nested
.apic_access_page
);
6124 vmx
->nested
.apic_access_page
= 0;
6127 nested_free_all_saved_vmcss(vmx
);
6130 /* Emulate the VMXOFF instruction */
6131 static int handle_vmoff(struct kvm_vcpu
*vcpu
)
6133 if (!nested_vmx_check_permission(vcpu
))
6135 free_nested(to_vmx(vcpu
));
6136 skip_emulated_instruction(vcpu
);
6137 nested_vmx_succeed(vcpu
);
6141 /* Emulate the VMCLEAR instruction */
6142 static int handle_vmclear(struct kvm_vcpu
*vcpu
)
6144 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6146 struct vmcs12
*vmcs12
;
6149 if (!nested_vmx_check_permission(vcpu
))
6152 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMCLEAR
, &vmptr
))
6155 if (vmptr
== vmx
->nested
.current_vmptr
) {
6156 nested_release_vmcs12(vmx
);
6157 vmx
->nested
.current_vmptr
= -1ull;
6158 vmx
->nested
.current_vmcs12
= NULL
;
6161 page
= nested_get_page(vcpu
, vmptr
);
6164 * For accurate processor emulation, VMCLEAR beyond available
6165 * physical memory should do nothing at all. However, it is
6166 * possible that a nested vmx bug, not a guest hypervisor bug,
6167 * resulted in this case, so let's shut down before doing any
6170 kvm_make_request(KVM_REQ_TRIPLE_FAULT
, vcpu
);
6173 vmcs12
= kmap(page
);
6174 vmcs12
->launch_state
= 0;
6176 nested_release_page(page
);
6178 nested_free_vmcs02(vmx
, vmptr
);
6180 skip_emulated_instruction(vcpu
);
6181 nested_vmx_succeed(vcpu
);
6185 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
);
6187 /* Emulate the VMLAUNCH instruction */
6188 static int handle_vmlaunch(struct kvm_vcpu
*vcpu
)
6190 return nested_vmx_run(vcpu
, true);
6193 /* Emulate the VMRESUME instruction */
6194 static int handle_vmresume(struct kvm_vcpu
*vcpu
)
6197 return nested_vmx_run(vcpu
, false);
6200 enum vmcs_field_type
{
6201 VMCS_FIELD_TYPE_U16
= 0,
6202 VMCS_FIELD_TYPE_U64
= 1,
6203 VMCS_FIELD_TYPE_U32
= 2,
6204 VMCS_FIELD_TYPE_NATURAL_WIDTH
= 3
6207 static inline int vmcs_field_type(unsigned long field
)
6209 if (0x1 & field
) /* the *_HIGH fields are all 32 bit */
6210 return VMCS_FIELD_TYPE_U32
;
6211 return (field
>> 13) & 0x3 ;
6214 static inline int vmcs_field_readonly(unsigned long field
)
6216 return (((field
>> 10) & 0x3) == 1);
6220 * Read a vmcs12 field. Since these can have varying lengths and we return
6221 * one type, we chose the biggest type (u64) and zero-extend the return value
6222 * to that size. Note that the caller, handle_vmread, might need to use only
6223 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6224 * 64-bit fields are to be returned).
6226 static inline bool vmcs12_read_any(struct kvm_vcpu
*vcpu
,
6227 unsigned long field
, u64
*ret
)
6229 short offset
= vmcs_field_to_offset(field
);
6235 p
= ((char *)(get_vmcs12(vcpu
))) + offset
;
6237 switch (vmcs_field_type(field
)) {
6238 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6239 *ret
= *((natural_width
*)p
);
6241 case VMCS_FIELD_TYPE_U16
:
6244 case VMCS_FIELD_TYPE_U32
:
6247 case VMCS_FIELD_TYPE_U64
:
6251 return 0; /* can never happen. */
6256 static inline bool vmcs12_write_any(struct kvm_vcpu
*vcpu
,
6257 unsigned long field
, u64 field_value
){
6258 short offset
= vmcs_field_to_offset(field
);
6259 char *p
= ((char *) get_vmcs12(vcpu
)) + offset
;
6263 switch (vmcs_field_type(field
)) {
6264 case VMCS_FIELD_TYPE_U16
:
6265 *(u16
*)p
= field_value
;
6267 case VMCS_FIELD_TYPE_U32
:
6268 *(u32
*)p
= field_value
;
6270 case VMCS_FIELD_TYPE_U64
:
6271 *(u64
*)p
= field_value
;
6273 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6274 *(natural_width
*)p
= field_value
;
6277 return false; /* can never happen. */
6282 static void copy_shadow_to_vmcs12(struct vcpu_vmx
*vmx
)
6285 unsigned long field
;
6287 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6288 const unsigned long *fields
= shadow_read_write_fields
;
6289 const int num_fields
= max_shadow_read_write_fields
;
6291 vmcs_load(shadow_vmcs
);
6293 for (i
= 0; i
< num_fields
; i
++) {
6295 switch (vmcs_field_type(field
)) {
6296 case VMCS_FIELD_TYPE_U16
:
6297 field_value
= vmcs_read16(field
);
6299 case VMCS_FIELD_TYPE_U32
:
6300 field_value
= vmcs_read32(field
);
6302 case VMCS_FIELD_TYPE_U64
:
6303 field_value
= vmcs_read64(field
);
6305 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6306 field_value
= vmcs_readl(field
);
6309 vmcs12_write_any(&vmx
->vcpu
, field
, field_value
);
6312 vmcs_clear(shadow_vmcs
);
6313 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6316 static void copy_vmcs12_to_shadow(struct vcpu_vmx
*vmx
)
6318 const unsigned long *fields
[] = {
6319 shadow_read_write_fields
,
6320 shadow_read_only_fields
6322 const int max_fields
[] = {
6323 max_shadow_read_write_fields
,
6324 max_shadow_read_only_fields
6327 unsigned long field
;
6328 u64 field_value
= 0;
6329 struct vmcs
*shadow_vmcs
= vmx
->nested
.current_shadow_vmcs
;
6331 vmcs_load(shadow_vmcs
);
6333 for (q
= 0; q
< ARRAY_SIZE(fields
); q
++) {
6334 for (i
= 0; i
< max_fields
[q
]; i
++) {
6335 field
= fields
[q
][i
];
6336 vmcs12_read_any(&vmx
->vcpu
, field
, &field_value
);
6338 switch (vmcs_field_type(field
)) {
6339 case VMCS_FIELD_TYPE_U16
:
6340 vmcs_write16(field
, (u16
)field_value
);
6342 case VMCS_FIELD_TYPE_U32
:
6343 vmcs_write32(field
, (u32
)field_value
);
6345 case VMCS_FIELD_TYPE_U64
:
6346 vmcs_write64(field
, (u64
)field_value
);
6348 case VMCS_FIELD_TYPE_NATURAL_WIDTH
:
6349 vmcs_writel(field
, (long)field_value
);
6355 vmcs_clear(shadow_vmcs
);
6356 vmcs_load(vmx
->loaded_vmcs
->vmcs
);
6360 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
6361 * used before) all generate the same failure when it is missing.
6363 static int nested_vmx_check_vmcs12(struct kvm_vcpu
*vcpu
)
6365 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6366 if (vmx
->nested
.current_vmptr
== -1ull) {
6367 nested_vmx_failInvalid(vcpu
);
6368 skip_emulated_instruction(vcpu
);
6374 static int handle_vmread(struct kvm_vcpu
*vcpu
)
6376 unsigned long field
;
6378 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6379 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6382 if (!nested_vmx_check_permission(vcpu
) ||
6383 !nested_vmx_check_vmcs12(vcpu
))
6386 /* Decode instruction info and find the field to read */
6387 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6388 /* Read the field, zero-extended to a u64 field_value */
6389 if (!vmcs12_read_any(vcpu
, field
, &field_value
)) {
6390 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6391 skip_emulated_instruction(vcpu
);
6395 * Now copy part of this value to register or memory, as requested.
6396 * Note that the number of bits actually copied is 32 or 64 depending
6397 * on the guest's mode (32 or 64 bit), not on the given field's length.
6399 if (vmx_instruction_info
& (1u << 10)) {
6400 kvm_register_write(vcpu
, (((vmx_instruction_info
) >> 3) & 0xf),
6403 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6404 vmx_instruction_info
, &gva
))
6406 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
6407 kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, gva
,
6408 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), NULL
);
6411 nested_vmx_succeed(vcpu
);
6412 skip_emulated_instruction(vcpu
);
6417 static int handle_vmwrite(struct kvm_vcpu
*vcpu
)
6419 unsigned long field
;
6421 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6422 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6423 /* The value to write might be 32 or 64 bits, depending on L1's long
6424 * mode, and eventually we need to write that into a field of several
6425 * possible lengths. The code below first zero-extends the value to 64
6426 * bit (field_value), and then copies only the approriate number of
6427 * bits into the vmcs12 field.
6429 u64 field_value
= 0;
6430 struct x86_exception e
;
6432 if (!nested_vmx_check_permission(vcpu
) ||
6433 !nested_vmx_check_vmcs12(vcpu
))
6436 if (vmx_instruction_info
& (1u << 10))
6437 field_value
= kvm_register_read(vcpu
,
6438 (((vmx_instruction_info
) >> 3) & 0xf));
6440 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6441 vmx_instruction_info
, &gva
))
6443 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
,
6444 &field_value
, (is_long_mode(vcpu
) ? 8 : 4), &e
)) {
6445 kvm_inject_page_fault(vcpu
, &e
);
6451 field
= kvm_register_read(vcpu
, (((vmx_instruction_info
) >> 28) & 0xf));
6452 if (vmcs_field_readonly(field
)) {
6453 nested_vmx_failValid(vcpu
,
6454 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT
);
6455 skip_emulated_instruction(vcpu
);
6459 if (!vmcs12_write_any(vcpu
, field
, field_value
)) {
6460 nested_vmx_failValid(vcpu
, VMXERR_UNSUPPORTED_VMCS_COMPONENT
);
6461 skip_emulated_instruction(vcpu
);
6465 nested_vmx_succeed(vcpu
);
6466 skip_emulated_instruction(vcpu
);
6470 /* Emulate the VMPTRLD instruction */
6471 static int handle_vmptrld(struct kvm_vcpu
*vcpu
)
6473 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6477 if (!nested_vmx_check_permission(vcpu
))
6480 if (nested_vmx_check_vmptr(vcpu
, EXIT_REASON_VMPTRLD
, &vmptr
))
6483 if (vmx
->nested
.current_vmptr
!= vmptr
) {
6484 struct vmcs12
*new_vmcs12
;
6486 page
= nested_get_page(vcpu
, vmptr
);
6488 nested_vmx_failInvalid(vcpu
);
6489 skip_emulated_instruction(vcpu
);
6492 new_vmcs12
= kmap(page
);
6493 if (new_vmcs12
->revision_id
!= VMCS12_REVISION
) {
6495 nested_release_page_clean(page
);
6496 nested_vmx_failValid(vcpu
,
6497 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID
);
6498 skip_emulated_instruction(vcpu
);
6501 if (vmx
->nested
.current_vmptr
!= -1ull)
6502 nested_release_vmcs12(vmx
);
6504 vmx
->nested
.current_vmptr
= vmptr
;
6505 vmx
->nested
.current_vmcs12
= new_vmcs12
;
6506 vmx
->nested
.current_vmcs12_page
= page
;
6507 if (enable_shadow_vmcs
) {
6508 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
6509 exec_control
|= SECONDARY_EXEC_SHADOW_VMCS
;
6510 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
6511 vmcs_write64(VMCS_LINK_POINTER
,
6512 __pa(vmx
->nested
.current_shadow_vmcs
));
6513 vmx
->nested
.sync_shadow_vmcs
= true;
6517 nested_vmx_succeed(vcpu
);
6518 skip_emulated_instruction(vcpu
);
6522 /* Emulate the VMPTRST instruction */
6523 static int handle_vmptrst(struct kvm_vcpu
*vcpu
)
6525 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6526 u32 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6528 struct x86_exception e
;
6530 if (!nested_vmx_check_permission(vcpu
))
6533 if (get_vmx_mem_address(vcpu
, exit_qualification
,
6534 vmx_instruction_info
, &vmcs_gva
))
6536 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
6537 if (kvm_write_guest_virt_system(&vcpu
->arch
.emulate_ctxt
, vmcs_gva
,
6538 (void *)&to_vmx(vcpu
)->nested
.current_vmptr
,
6540 kvm_inject_page_fault(vcpu
, &e
);
6543 nested_vmx_succeed(vcpu
);
6544 skip_emulated_instruction(vcpu
);
6548 /* Emulate the INVEPT instruction */
6549 static int handle_invept(struct kvm_vcpu
*vcpu
)
6551 u32 vmx_instruction_info
, types
;
6554 struct x86_exception e
;
6559 if (!(nested_vmx_secondary_ctls_high
& SECONDARY_EXEC_ENABLE_EPT
) ||
6560 !(nested_vmx_ept_caps
& VMX_EPT_INVEPT_BIT
)) {
6561 kvm_queue_exception(vcpu
, UD_VECTOR
);
6565 if (!nested_vmx_check_permission(vcpu
))
6568 if (!kvm_read_cr0_bits(vcpu
, X86_CR0_PE
)) {
6569 kvm_queue_exception(vcpu
, UD_VECTOR
);
6573 vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
6574 type
= kvm_register_read(vcpu
, (vmx_instruction_info
>> 28) & 0xf);
6576 types
= (nested_vmx_ept_caps
>> VMX_EPT_EXTENT_SHIFT
) & 6;
6578 if (!(types
& (1UL << type
))) {
6579 nested_vmx_failValid(vcpu
,
6580 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID
);
6584 /* According to the Intel VMX instruction reference, the memory
6585 * operand is read even if it isn't needed (e.g., for type==global)
6587 if (get_vmx_mem_address(vcpu
, vmcs_readl(EXIT_QUALIFICATION
),
6588 vmx_instruction_info
, &gva
))
6590 if (kvm_read_guest_virt(&vcpu
->arch
.emulate_ctxt
, gva
, &operand
,
6591 sizeof(operand
), &e
)) {
6592 kvm_inject_page_fault(vcpu
, &e
);
6597 case VMX_EPT_EXTENT_GLOBAL
:
6598 kvm_mmu_sync_roots(vcpu
);
6599 kvm_mmu_flush_tlb(vcpu
);
6600 nested_vmx_succeed(vcpu
);
6603 /* Trap single context invalidation invept calls */
6608 skip_emulated_instruction(vcpu
);
6613 * The exit handlers return 1 if the exit was handled fully and guest execution
6614 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
6615 * to be done to userspace and return 0.
6617 static int (*const kvm_vmx_exit_handlers
[])(struct kvm_vcpu
*vcpu
) = {
6618 [EXIT_REASON_EXCEPTION_NMI
] = handle_exception
,
6619 [EXIT_REASON_EXTERNAL_INTERRUPT
] = handle_external_interrupt
,
6620 [EXIT_REASON_TRIPLE_FAULT
] = handle_triple_fault
,
6621 [EXIT_REASON_NMI_WINDOW
] = handle_nmi_window
,
6622 [EXIT_REASON_IO_INSTRUCTION
] = handle_io
,
6623 [EXIT_REASON_CR_ACCESS
] = handle_cr
,
6624 [EXIT_REASON_DR_ACCESS
] = handle_dr
,
6625 [EXIT_REASON_CPUID
] = handle_cpuid
,
6626 [EXIT_REASON_MSR_READ
] = handle_rdmsr
,
6627 [EXIT_REASON_MSR_WRITE
] = handle_wrmsr
,
6628 [EXIT_REASON_PENDING_INTERRUPT
] = handle_interrupt_window
,
6629 [EXIT_REASON_HLT
] = handle_halt
,
6630 [EXIT_REASON_INVD
] = handle_invd
,
6631 [EXIT_REASON_INVLPG
] = handle_invlpg
,
6632 [EXIT_REASON_RDPMC
] = handle_rdpmc
,
6633 [EXIT_REASON_VMCALL
] = handle_vmcall
,
6634 [EXIT_REASON_VMCLEAR
] = handle_vmclear
,
6635 [EXIT_REASON_VMLAUNCH
] = handle_vmlaunch
,
6636 [EXIT_REASON_VMPTRLD
] = handle_vmptrld
,
6637 [EXIT_REASON_VMPTRST
] = handle_vmptrst
,
6638 [EXIT_REASON_VMREAD
] = handle_vmread
,
6639 [EXIT_REASON_VMRESUME
] = handle_vmresume
,
6640 [EXIT_REASON_VMWRITE
] = handle_vmwrite
,
6641 [EXIT_REASON_VMOFF
] = handle_vmoff
,
6642 [EXIT_REASON_VMON
] = handle_vmon
,
6643 [EXIT_REASON_TPR_BELOW_THRESHOLD
] = handle_tpr_below_threshold
,
6644 [EXIT_REASON_APIC_ACCESS
] = handle_apic_access
,
6645 [EXIT_REASON_APIC_WRITE
] = handle_apic_write
,
6646 [EXIT_REASON_EOI_INDUCED
] = handle_apic_eoi_induced
,
6647 [EXIT_REASON_WBINVD
] = handle_wbinvd
,
6648 [EXIT_REASON_XSETBV
] = handle_xsetbv
,
6649 [EXIT_REASON_TASK_SWITCH
] = handle_task_switch
,
6650 [EXIT_REASON_MCE_DURING_VMENTRY
] = handle_machine_check
,
6651 [EXIT_REASON_EPT_VIOLATION
] = handle_ept_violation
,
6652 [EXIT_REASON_EPT_MISCONFIG
] = handle_ept_misconfig
,
6653 [EXIT_REASON_PAUSE_INSTRUCTION
] = handle_pause
,
6654 [EXIT_REASON_MWAIT_INSTRUCTION
] = handle_mwait
,
6655 [EXIT_REASON_MONITOR_INSTRUCTION
] = handle_monitor
,
6656 [EXIT_REASON_INVEPT
] = handle_invept
,
6659 static const int kvm_vmx_max_exit_handlers
=
6660 ARRAY_SIZE(kvm_vmx_exit_handlers
);
6662 static bool nested_vmx_exit_handled_io(struct kvm_vcpu
*vcpu
,
6663 struct vmcs12
*vmcs12
)
6665 unsigned long exit_qualification
;
6666 gpa_t bitmap
, last_bitmap
;
6671 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_IO_BITMAPS
))
6672 return nested_cpu_has(vmcs12
, CPU_BASED_UNCOND_IO_EXITING
);
6674 exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6676 port
= exit_qualification
>> 16;
6677 size
= (exit_qualification
& 7) + 1;
6679 last_bitmap
= (gpa_t
)-1;
6684 bitmap
= vmcs12
->io_bitmap_a
;
6685 else if (port
< 0x10000)
6686 bitmap
= vmcs12
->io_bitmap_b
;
6689 bitmap
+= (port
& 0x7fff) / 8;
6691 if (last_bitmap
!= bitmap
)
6692 if (kvm_read_guest(vcpu
->kvm
, bitmap
, &b
, 1))
6694 if (b
& (1 << (port
& 7)))
6699 last_bitmap
= bitmap
;
6706 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
6707 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
6708 * disinterest in the current event (read or write a specific MSR) by using an
6709 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
6711 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu
*vcpu
,
6712 struct vmcs12
*vmcs12
, u32 exit_reason
)
6714 u32 msr_index
= vcpu
->arch
.regs
[VCPU_REGS_RCX
];
6717 if (!nested_cpu_has(vmcs12
, CPU_BASED_USE_MSR_BITMAPS
))
6721 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
6722 * for the four combinations of read/write and low/high MSR numbers.
6723 * First we need to figure out which of the four to use:
6725 bitmap
= vmcs12
->msr_bitmap
;
6726 if (exit_reason
== EXIT_REASON_MSR_WRITE
)
6728 if (msr_index
>= 0xc0000000) {
6729 msr_index
-= 0xc0000000;
6733 /* Then read the msr_index'th bit from this bitmap: */
6734 if (msr_index
< 1024*8) {
6736 if (kvm_read_guest(vcpu
->kvm
, bitmap
+ msr_index
/8, &b
, 1))
6738 return 1 & (b
>> (msr_index
& 7));
6740 return 1; /* let L1 handle the wrong parameter */
6744 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
6745 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
6746 * intercept (via guest_host_mask etc.) the current event.
6748 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu
*vcpu
,
6749 struct vmcs12
*vmcs12
)
6751 unsigned long exit_qualification
= vmcs_readl(EXIT_QUALIFICATION
);
6752 int cr
= exit_qualification
& 15;
6753 int reg
= (exit_qualification
>> 8) & 15;
6754 unsigned long val
= kvm_register_read(vcpu
, reg
);
6756 switch ((exit_qualification
>> 4) & 3) {
6757 case 0: /* mov to cr */
6760 if (vmcs12
->cr0_guest_host_mask
&
6761 (val
^ vmcs12
->cr0_read_shadow
))
6765 if ((vmcs12
->cr3_target_count
>= 1 &&
6766 vmcs12
->cr3_target_value0
== val
) ||
6767 (vmcs12
->cr3_target_count
>= 2 &&
6768 vmcs12
->cr3_target_value1
== val
) ||
6769 (vmcs12
->cr3_target_count
>= 3 &&
6770 vmcs12
->cr3_target_value2
== val
) ||
6771 (vmcs12
->cr3_target_count
>= 4 &&
6772 vmcs12
->cr3_target_value3
== val
))
6774 if (nested_cpu_has(vmcs12
, CPU_BASED_CR3_LOAD_EXITING
))
6778 if (vmcs12
->cr4_guest_host_mask
&
6779 (vmcs12
->cr4_read_shadow
^ val
))
6783 if (nested_cpu_has(vmcs12
, CPU_BASED_CR8_LOAD_EXITING
))
6789 if ((vmcs12
->cr0_guest_host_mask
& X86_CR0_TS
) &&
6790 (vmcs12
->cr0_read_shadow
& X86_CR0_TS
))
6793 case 1: /* mov from cr */
6796 if (vmcs12
->cpu_based_vm_exec_control
&
6797 CPU_BASED_CR3_STORE_EXITING
)
6801 if (vmcs12
->cpu_based_vm_exec_control
&
6802 CPU_BASED_CR8_STORE_EXITING
)
6809 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
6810 * cr0. Other attempted changes are ignored, with no exit.
6812 if (vmcs12
->cr0_guest_host_mask
& 0xe &
6813 (val
^ vmcs12
->cr0_read_shadow
))
6815 if ((vmcs12
->cr0_guest_host_mask
& 0x1) &&
6816 !(vmcs12
->cr0_read_shadow
& 0x1) &&
6825 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
6826 * should handle it ourselves in L0 (and then continue L2). Only call this
6827 * when in is_guest_mode (L2).
6829 static bool nested_vmx_exit_handled(struct kvm_vcpu
*vcpu
)
6831 u32 intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
6832 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6833 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
6834 u32 exit_reason
= vmx
->exit_reason
;
6836 trace_kvm_nested_vmexit(kvm_rip_read(vcpu
), exit_reason
,
6837 vmcs_readl(EXIT_QUALIFICATION
),
6838 vmx
->idt_vectoring_info
,
6840 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
),
6843 if (vmx
->nested
.nested_run_pending
)
6846 if (unlikely(vmx
->fail
)) {
6847 pr_info_ratelimited("%s failed vm entry %x\n", __func__
,
6848 vmcs_read32(VM_INSTRUCTION_ERROR
));
6852 switch (exit_reason
) {
6853 case EXIT_REASON_EXCEPTION_NMI
:
6854 if (!is_exception(intr_info
))
6856 else if (is_page_fault(intr_info
))
6858 else if (is_no_device(intr_info
) &&
6859 !(vmcs12
->guest_cr0
& X86_CR0_TS
))
6861 return vmcs12
->exception_bitmap
&
6862 (1u << (intr_info
& INTR_INFO_VECTOR_MASK
));
6863 case EXIT_REASON_EXTERNAL_INTERRUPT
:
6865 case EXIT_REASON_TRIPLE_FAULT
:
6867 case EXIT_REASON_PENDING_INTERRUPT
:
6868 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_INTR_PENDING
);
6869 case EXIT_REASON_NMI_WINDOW
:
6870 return nested_cpu_has(vmcs12
, CPU_BASED_VIRTUAL_NMI_PENDING
);
6871 case EXIT_REASON_TASK_SWITCH
:
6873 case EXIT_REASON_CPUID
:
6875 case EXIT_REASON_HLT
:
6876 return nested_cpu_has(vmcs12
, CPU_BASED_HLT_EXITING
);
6877 case EXIT_REASON_INVD
:
6879 case EXIT_REASON_INVLPG
:
6880 return nested_cpu_has(vmcs12
, CPU_BASED_INVLPG_EXITING
);
6881 case EXIT_REASON_RDPMC
:
6882 return nested_cpu_has(vmcs12
, CPU_BASED_RDPMC_EXITING
);
6883 case EXIT_REASON_RDTSC
:
6884 return nested_cpu_has(vmcs12
, CPU_BASED_RDTSC_EXITING
);
6885 case EXIT_REASON_VMCALL
: case EXIT_REASON_VMCLEAR
:
6886 case EXIT_REASON_VMLAUNCH
: case EXIT_REASON_VMPTRLD
:
6887 case EXIT_REASON_VMPTRST
: case EXIT_REASON_VMREAD
:
6888 case EXIT_REASON_VMRESUME
: case EXIT_REASON_VMWRITE
:
6889 case EXIT_REASON_VMOFF
: case EXIT_REASON_VMON
:
6890 case EXIT_REASON_INVEPT
:
6892 * VMX instructions trap unconditionally. This allows L1 to
6893 * emulate them for its L2 guest, i.e., allows 3-level nesting!
6896 case EXIT_REASON_CR_ACCESS
:
6897 return nested_vmx_exit_handled_cr(vcpu
, vmcs12
);
6898 case EXIT_REASON_DR_ACCESS
:
6899 return nested_cpu_has(vmcs12
, CPU_BASED_MOV_DR_EXITING
);
6900 case EXIT_REASON_IO_INSTRUCTION
:
6901 return nested_vmx_exit_handled_io(vcpu
, vmcs12
);
6902 case EXIT_REASON_MSR_READ
:
6903 case EXIT_REASON_MSR_WRITE
:
6904 return nested_vmx_exit_handled_msr(vcpu
, vmcs12
, exit_reason
);
6905 case EXIT_REASON_INVALID_STATE
:
6907 case EXIT_REASON_MWAIT_INSTRUCTION
:
6908 return nested_cpu_has(vmcs12
, CPU_BASED_MWAIT_EXITING
);
6909 case EXIT_REASON_MONITOR_INSTRUCTION
:
6910 return nested_cpu_has(vmcs12
, CPU_BASED_MONITOR_EXITING
);
6911 case EXIT_REASON_PAUSE_INSTRUCTION
:
6912 return nested_cpu_has(vmcs12
, CPU_BASED_PAUSE_EXITING
) ||
6913 nested_cpu_has2(vmcs12
,
6914 SECONDARY_EXEC_PAUSE_LOOP_EXITING
);
6915 case EXIT_REASON_MCE_DURING_VMENTRY
:
6917 case EXIT_REASON_TPR_BELOW_THRESHOLD
:
6919 case EXIT_REASON_APIC_ACCESS
:
6920 return nested_cpu_has2(vmcs12
,
6921 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
);
6922 case EXIT_REASON_EPT_VIOLATION
:
6924 * L0 always deals with the EPT violation. If nested EPT is
6925 * used, and the nested mmu code discovers that the address is
6926 * missing in the guest EPT table (EPT12), the EPT violation
6927 * will be injected with nested_ept_inject_page_fault()
6930 case EXIT_REASON_EPT_MISCONFIG
:
6932 * L2 never uses directly L1's EPT, but rather L0's own EPT
6933 * table (shadow on EPT) or a merged EPT table that L0 built
6934 * (EPT on EPT). So any problems with the structure of the
6935 * table is L0's fault.
6938 case EXIT_REASON_WBINVD
:
6939 return nested_cpu_has2(vmcs12
, SECONDARY_EXEC_WBINVD_EXITING
);
6940 case EXIT_REASON_XSETBV
:
6947 static void vmx_get_exit_info(struct kvm_vcpu
*vcpu
, u64
*info1
, u64
*info2
)
6949 *info1
= vmcs_readl(EXIT_QUALIFICATION
);
6950 *info2
= vmcs_read32(VM_EXIT_INTR_INFO
);
6954 * The guest has exited. See if we can fix it or if we need userspace
6957 static int vmx_handle_exit(struct kvm_vcpu
*vcpu
)
6959 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
6960 u32 exit_reason
= vmx
->exit_reason
;
6961 u32 vectoring_info
= vmx
->idt_vectoring_info
;
6963 /* If guest state is invalid, start emulating */
6964 if (vmx
->emulation_required
)
6965 return handle_invalid_guest_state(vcpu
);
6967 if (is_guest_mode(vcpu
) && nested_vmx_exit_handled(vcpu
)) {
6968 nested_vmx_vmexit(vcpu
, exit_reason
,
6969 vmcs_read32(VM_EXIT_INTR_INFO
),
6970 vmcs_readl(EXIT_QUALIFICATION
));
6974 if (exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
) {
6975 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6976 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6981 if (unlikely(vmx
->fail
)) {
6982 vcpu
->run
->exit_reason
= KVM_EXIT_FAIL_ENTRY
;
6983 vcpu
->run
->fail_entry
.hardware_entry_failure_reason
6984 = vmcs_read32(VM_INSTRUCTION_ERROR
);
6990 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
6991 * delivery event since it indicates guest is accessing MMIO.
6992 * The vm-exit can be triggered again after return to guest that
6993 * will cause infinite loop.
6995 if ((vectoring_info
& VECTORING_INFO_VALID_MASK
) &&
6996 (exit_reason
!= EXIT_REASON_EXCEPTION_NMI
&&
6997 exit_reason
!= EXIT_REASON_EPT_VIOLATION
&&
6998 exit_reason
!= EXIT_REASON_TASK_SWITCH
)) {
6999 vcpu
->run
->exit_reason
= KVM_EXIT_INTERNAL_ERROR
;
7000 vcpu
->run
->internal
.suberror
= KVM_INTERNAL_ERROR_DELIVERY_EV
;
7001 vcpu
->run
->internal
.ndata
= 2;
7002 vcpu
->run
->internal
.data
[0] = vectoring_info
;
7003 vcpu
->run
->internal
.data
[1] = exit_reason
;
7007 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
&&
7008 !(is_guest_mode(vcpu
) && nested_cpu_has_virtual_nmis(
7009 get_vmcs12(vcpu
))))) {
7010 if (vmx_interrupt_allowed(vcpu
)) {
7011 vmx
->soft_vnmi_blocked
= 0;
7012 } else if (vmx
->vnmi_blocked_time
> 1000000000LL &&
7013 vcpu
->arch
.nmi_pending
) {
7015 * This CPU don't support us in finding the end of an
7016 * NMI-blocked window if the guest runs with IRQs
7017 * disabled. So we pull the trigger after 1 s of
7018 * futile waiting, but inform the user about this.
7020 printk(KERN_WARNING
"%s: Breaking out of NMI-blocked "
7021 "state on VCPU %d after 1 s timeout\n",
7022 __func__
, vcpu
->vcpu_id
);
7023 vmx
->soft_vnmi_blocked
= 0;
7027 if (exit_reason
< kvm_vmx_max_exit_handlers
7028 && kvm_vmx_exit_handlers
[exit_reason
])
7029 return kvm_vmx_exit_handlers
[exit_reason
](vcpu
);
7031 vcpu
->run
->exit_reason
= KVM_EXIT_UNKNOWN
;
7032 vcpu
->run
->hw
.hardware_exit_reason
= exit_reason
;
7037 static void update_cr8_intercept(struct kvm_vcpu
*vcpu
, int tpr
, int irr
)
7039 if (irr
== -1 || tpr
< irr
) {
7040 vmcs_write32(TPR_THRESHOLD
, 0);
7044 vmcs_write32(TPR_THRESHOLD
, irr
);
7047 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu
*vcpu
, bool set
)
7049 u32 sec_exec_control
;
7052 * There is not point to enable virtualize x2apic without enable
7055 if (!cpu_has_vmx_virtualize_x2apic_mode() ||
7056 !vmx_vm_has_apicv(vcpu
->kvm
))
7059 if (!vm_need_tpr_shadow(vcpu
->kvm
))
7062 sec_exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7065 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7066 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7068 sec_exec_control
&= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE
;
7069 sec_exec_control
|= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7071 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, sec_exec_control
);
7073 vmx_set_msr_bitmap(vcpu
);
7076 static void vmx_hwapic_isr_update(struct kvm
*kvm
, int isr
)
7081 if (!vmx_vm_has_apicv(kvm
))
7087 status
= vmcs_read16(GUEST_INTR_STATUS
);
7092 vmcs_write16(GUEST_INTR_STATUS
, status
);
7096 static void vmx_set_rvi(int vector
)
7101 status
= vmcs_read16(GUEST_INTR_STATUS
);
7102 old
= (u8
)status
& 0xff;
7103 if ((u8
)vector
!= old
) {
7105 status
|= (u8
)vector
;
7106 vmcs_write16(GUEST_INTR_STATUS
, status
);
7110 static void vmx_hwapic_irr_update(struct kvm_vcpu
*vcpu
, int max_irr
)
7115 vmx_set_rvi(max_irr
);
7118 static void vmx_load_eoi_exitmap(struct kvm_vcpu
*vcpu
, u64
*eoi_exit_bitmap
)
7120 if (!vmx_vm_has_apicv(vcpu
->kvm
))
7123 vmcs_write64(EOI_EXIT_BITMAP0
, eoi_exit_bitmap
[0]);
7124 vmcs_write64(EOI_EXIT_BITMAP1
, eoi_exit_bitmap
[1]);
7125 vmcs_write64(EOI_EXIT_BITMAP2
, eoi_exit_bitmap
[2]);
7126 vmcs_write64(EOI_EXIT_BITMAP3
, eoi_exit_bitmap
[3]);
7129 static void vmx_complete_atomic_exit(struct vcpu_vmx
*vmx
)
7133 if (!(vmx
->exit_reason
== EXIT_REASON_MCE_DURING_VMENTRY
7134 || vmx
->exit_reason
== EXIT_REASON_EXCEPTION_NMI
))
7137 vmx
->exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7138 exit_intr_info
= vmx
->exit_intr_info
;
7140 /* Handle machine checks before interrupts are enabled */
7141 if (is_machine_check(exit_intr_info
))
7142 kvm_machine_check();
7144 /* We need to handle NMIs before interrupts are enabled */
7145 if ((exit_intr_info
& INTR_INFO_INTR_TYPE_MASK
) == INTR_TYPE_NMI_INTR
&&
7146 (exit_intr_info
& INTR_INFO_VALID_MASK
)) {
7147 kvm_before_handle_nmi(&vmx
->vcpu
);
7149 kvm_after_handle_nmi(&vmx
->vcpu
);
7153 static void vmx_handle_external_intr(struct kvm_vcpu
*vcpu
)
7155 u32 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7158 * If external interrupt exists, IF bit is set in rflags/eflags on the
7159 * interrupt stack frame, and interrupt will be enabled on a return
7160 * from interrupt handler.
7162 if ((exit_intr_info
& (INTR_INFO_VALID_MASK
| INTR_INFO_INTR_TYPE_MASK
))
7163 == (INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
)) {
7164 unsigned int vector
;
7165 unsigned long entry
;
7167 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7168 #ifdef CONFIG_X86_64
7172 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7173 desc
= (gate_desc
*)vmx
->host_idt_base
+ vector
;
7174 entry
= gate_offset(*desc
);
7176 #ifdef CONFIG_X86_64
7177 "mov %%" _ASM_SP
", %[sp]\n\t"
7178 "and $0xfffffffffffffff0, %%" _ASM_SP
"\n\t"
7183 "orl $0x200, (%%" _ASM_SP
")\n\t"
7184 __ASM_SIZE(push
) " $%c[cs]\n\t"
7185 "call *%[entry]\n\t"
7187 #ifdef CONFIG_X86_64
7192 [ss
]"i"(__KERNEL_DS
),
7193 [cs
]"i"(__KERNEL_CS
)
7199 static bool vmx_mpx_supported(void)
7201 return (vmcs_config
.vmexit_ctrl
& VM_EXIT_CLEAR_BNDCFGS
) &&
7202 (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_BNDCFGS
);
7205 static void vmx_recover_nmi_blocking(struct vcpu_vmx
*vmx
)
7210 bool idtv_info_valid
;
7212 idtv_info_valid
= vmx
->idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7214 if (cpu_has_virtual_nmis()) {
7215 if (vmx
->nmi_known_unmasked
)
7218 * Can't use vmx->exit_intr_info since we're not sure what
7219 * the exit reason is.
7221 exit_intr_info
= vmcs_read32(VM_EXIT_INTR_INFO
);
7222 unblock_nmi
= (exit_intr_info
& INTR_INFO_UNBLOCK_NMI
) != 0;
7223 vector
= exit_intr_info
& INTR_INFO_VECTOR_MASK
;
7225 * SDM 3: 27.7.1.2 (September 2008)
7226 * Re-set bit "block by NMI" before VM entry if vmexit caused by
7227 * a guest IRET fault.
7228 * SDM 3: 23.2.2 (September 2008)
7229 * Bit 12 is undefined in any of the following cases:
7230 * If the VM exit sets the valid bit in the IDT-vectoring
7231 * information field.
7232 * If the VM exit is due to a double fault.
7234 if ((exit_intr_info
& INTR_INFO_VALID_MASK
) && unblock_nmi
&&
7235 vector
!= DF_VECTOR
&& !idtv_info_valid
)
7236 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO
,
7237 GUEST_INTR_STATE_NMI
);
7239 vmx
->nmi_known_unmasked
=
7240 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
)
7241 & GUEST_INTR_STATE_NMI
);
7242 } else if (unlikely(vmx
->soft_vnmi_blocked
))
7243 vmx
->vnmi_blocked_time
+=
7244 ktime_to_ns(ktime_sub(ktime_get(), vmx
->entry_time
));
7247 static void __vmx_complete_interrupts(struct kvm_vcpu
*vcpu
,
7248 u32 idt_vectoring_info
,
7249 int instr_len_field
,
7250 int error_code_field
)
7254 bool idtv_info_valid
;
7256 idtv_info_valid
= idt_vectoring_info
& VECTORING_INFO_VALID_MASK
;
7258 vcpu
->arch
.nmi_injected
= false;
7259 kvm_clear_exception_queue(vcpu
);
7260 kvm_clear_interrupt_queue(vcpu
);
7262 if (!idtv_info_valid
)
7265 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7267 vector
= idt_vectoring_info
& VECTORING_INFO_VECTOR_MASK
;
7268 type
= idt_vectoring_info
& VECTORING_INFO_TYPE_MASK
;
7271 case INTR_TYPE_NMI_INTR
:
7272 vcpu
->arch
.nmi_injected
= true;
7274 * SDM 3: 27.7.1.2 (September 2008)
7275 * Clear bit "block by NMI" before VM entry if a NMI
7278 vmx_set_nmi_mask(vcpu
, false);
7280 case INTR_TYPE_SOFT_EXCEPTION
:
7281 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7283 case INTR_TYPE_HARD_EXCEPTION
:
7284 if (idt_vectoring_info
& VECTORING_INFO_DELIVER_CODE_MASK
) {
7285 u32 err
= vmcs_read32(error_code_field
);
7286 kvm_requeue_exception_e(vcpu
, vector
, err
);
7288 kvm_requeue_exception(vcpu
, vector
);
7290 case INTR_TYPE_SOFT_INTR
:
7291 vcpu
->arch
.event_exit_inst_len
= vmcs_read32(instr_len_field
);
7293 case INTR_TYPE_EXT_INTR
:
7294 kvm_queue_interrupt(vcpu
, vector
, type
== INTR_TYPE_SOFT_INTR
);
7301 static void vmx_complete_interrupts(struct vcpu_vmx
*vmx
)
7303 __vmx_complete_interrupts(&vmx
->vcpu
, vmx
->idt_vectoring_info
,
7304 VM_EXIT_INSTRUCTION_LEN
,
7305 IDT_VECTORING_ERROR_CODE
);
7308 static void vmx_cancel_injection(struct kvm_vcpu
*vcpu
)
7310 __vmx_complete_interrupts(vcpu
,
7311 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD
),
7312 VM_ENTRY_INSTRUCTION_LEN
,
7313 VM_ENTRY_EXCEPTION_ERROR_CODE
);
7315 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
, 0);
7318 static void atomic_switch_perf_msrs(struct vcpu_vmx
*vmx
)
7321 struct perf_guest_switch_msr
*msrs
;
7323 msrs
= perf_guest_get_msrs(&nr_msrs
);
7328 for (i
= 0; i
< nr_msrs
; i
++)
7329 if (msrs
[i
].host
== msrs
[i
].guest
)
7330 clear_atomic_switch_msr(vmx
, msrs
[i
].msr
);
7332 add_atomic_switch_msr(vmx
, msrs
[i
].msr
, msrs
[i
].guest
,
7336 static void __noclone
vmx_vcpu_run(struct kvm_vcpu
*vcpu
)
7338 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7339 unsigned long debugctlmsr
;
7341 /* Record the guest's net vcpu time for enforced NMI injections. */
7342 if (unlikely(!cpu_has_virtual_nmis() && vmx
->soft_vnmi_blocked
))
7343 vmx
->entry_time
= ktime_get();
7345 /* Don't enter VMX if guest state is invalid, let the exit handler
7346 start emulation until we arrive back to a valid state */
7347 if (vmx
->emulation_required
)
7350 if (vmx
->nested
.sync_shadow_vmcs
) {
7351 copy_vmcs12_to_shadow(vmx
);
7352 vmx
->nested
.sync_shadow_vmcs
= false;
7355 if (test_bit(VCPU_REGS_RSP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7356 vmcs_writel(GUEST_RSP
, vcpu
->arch
.regs
[VCPU_REGS_RSP
]);
7357 if (test_bit(VCPU_REGS_RIP
, (unsigned long *)&vcpu
->arch
.regs_dirty
))
7358 vmcs_writel(GUEST_RIP
, vcpu
->arch
.regs
[VCPU_REGS_RIP
]);
7360 /* When single-stepping over STI and MOV SS, we must clear the
7361 * corresponding interruptibility bits in the guest state. Otherwise
7362 * vmentry fails as it then expects bit 14 (BS) in pending debug
7363 * exceptions being set, but that's not correct for the guest debugging
7365 if (vcpu
->guest_debug
& KVM_GUESTDBG_SINGLESTEP
)
7366 vmx_set_interrupt_shadow(vcpu
, 0);
7368 atomic_switch_perf_msrs(vmx
);
7369 debugctlmsr
= get_debugctlmsr();
7371 vmx
->__launched
= vmx
->loaded_vmcs
->launched
;
7373 /* Store host registers */
7374 "push %%" _ASM_DX
"; push %%" _ASM_BP
";"
7375 "push %%" _ASM_CX
" \n\t" /* placeholder for guest rcx */
7376 "push %%" _ASM_CX
" \n\t"
7377 "cmp %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7379 "mov %%" _ASM_SP
", %c[host_rsp](%0) \n\t"
7380 __ex(ASM_VMX_VMWRITE_RSP_RDX
) "\n\t"
7382 /* Reload cr2 if changed */
7383 "mov %c[cr2](%0), %%" _ASM_AX
" \n\t"
7384 "mov %%cr2, %%" _ASM_DX
" \n\t"
7385 "cmp %%" _ASM_AX
", %%" _ASM_DX
" \n\t"
7387 "mov %%" _ASM_AX
", %%cr2 \n\t"
7389 /* Check if vmlaunch of vmresume is needed */
7390 "cmpl $0, %c[launched](%0) \n\t"
7391 /* Load guest registers. Don't clobber flags. */
7392 "mov %c[rax](%0), %%" _ASM_AX
" \n\t"
7393 "mov %c[rbx](%0), %%" _ASM_BX
" \n\t"
7394 "mov %c[rdx](%0), %%" _ASM_DX
" \n\t"
7395 "mov %c[rsi](%0), %%" _ASM_SI
" \n\t"
7396 "mov %c[rdi](%0), %%" _ASM_DI
" \n\t"
7397 "mov %c[rbp](%0), %%" _ASM_BP
" \n\t"
7398 #ifdef CONFIG_X86_64
7399 "mov %c[r8](%0), %%r8 \n\t"
7400 "mov %c[r9](%0), %%r9 \n\t"
7401 "mov %c[r10](%0), %%r10 \n\t"
7402 "mov %c[r11](%0), %%r11 \n\t"
7403 "mov %c[r12](%0), %%r12 \n\t"
7404 "mov %c[r13](%0), %%r13 \n\t"
7405 "mov %c[r14](%0), %%r14 \n\t"
7406 "mov %c[r15](%0), %%r15 \n\t"
7408 "mov %c[rcx](%0), %%" _ASM_CX
" \n\t" /* kills %0 (ecx) */
7410 /* Enter guest mode */
7412 __ex(ASM_VMX_VMLAUNCH
) "\n\t"
7414 "1: " __ex(ASM_VMX_VMRESUME
) "\n\t"
7416 /* Save guest registers, load host registers, keep flags */
7417 "mov %0, %c[wordsize](%%" _ASM_SP
") \n\t"
7419 "mov %%" _ASM_AX
", %c[rax](%0) \n\t"
7420 "mov %%" _ASM_BX
", %c[rbx](%0) \n\t"
7421 __ASM_SIZE(pop
) " %c[rcx](%0) \n\t"
7422 "mov %%" _ASM_DX
", %c[rdx](%0) \n\t"
7423 "mov %%" _ASM_SI
", %c[rsi](%0) \n\t"
7424 "mov %%" _ASM_DI
", %c[rdi](%0) \n\t"
7425 "mov %%" _ASM_BP
", %c[rbp](%0) \n\t"
7426 #ifdef CONFIG_X86_64
7427 "mov %%r8, %c[r8](%0) \n\t"
7428 "mov %%r9, %c[r9](%0) \n\t"
7429 "mov %%r10, %c[r10](%0) \n\t"
7430 "mov %%r11, %c[r11](%0) \n\t"
7431 "mov %%r12, %c[r12](%0) \n\t"
7432 "mov %%r13, %c[r13](%0) \n\t"
7433 "mov %%r14, %c[r14](%0) \n\t"
7434 "mov %%r15, %c[r15](%0) \n\t"
7436 "mov %%cr2, %%" _ASM_AX
" \n\t"
7437 "mov %%" _ASM_AX
", %c[cr2](%0) \n\t"
7439 "pop %%" _ASM_BP
"; pop %%" _ASM_DX
" \n\t"
7440 "setbe %c[fail](%0) \n\t"
7441 ".pushsection .rodata \n\t"
7442 ".global vmx_return \n\t"
7443 "vmx_return: " _ASM_PTR
" 2b \n\t"
7445 : : "c"(vmx
), "d"((unsigned long)HOST_RSP
),
7446 [launched
]"i"(offsetof(struct vcpu_vmx
, __launched
)),
7447 [fail
]"i"(offsetof(struct vcpu_vmx
, fail
)),
7448 [host_rsp
]"i"(offsetof(struct vcpu_vmx
, host_rsp
)),
7449 [rax
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RAX
])),
7450 [rbx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBX
])),
7451 [rcx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RCX
])),
7452 [rdx
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDX
])),
7453 [rsi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RSI
])),
7454 [rdi
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RDI
])),
7455 [rbp
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_RBP
])),
7456 #ifdef CONFIG_X86_64
7457 [r8
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R8
])),
7458 [r9
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R9
])),
7459 [r10
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R10
])),
7460 [r11
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R11
])),
7461 [r12
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R12
])),
7462 [r13
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R13
])),
7463 [r14
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R14
])),
7464 [r15
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.regs
[VCPU_REGS_R15
])),
7466 [cr2
]"i"(offsetof(struct vcpu_vmx
, vcpu
.arch
.cr2
)),
7467 [wordsize
]"i"(sizeof(ulong
))
7469 #ifdef CONFIG_X86_64
7470 , "rax", "rbx", "rdi", "rsi"
7471 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
7473 , "eax", "ebx", "edi", "esi"
7477 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
7479 update_debugctlmsr(debugctlmsr
);
7481 #ifndef CONFIG_X86_64
7483 * The sysexit path does not restore ds/es, so we must set them to
7484 * a reasonable value ourselves.
7486 * We can't defer this to vmx_load_host_state() since that function
7487 * may be executed in interrupt context, which saves and restore segments
7488 * around it, nullifying its effect.
7490 loadsegment(ds
, __USER_DS
);
7491 loadsegment(es
, __USER_DS
);
7494 vcpu
->arch
.regs_avail
= ~((1 << VCPU_REGS_RIP
) | (1 << VCPU_REGS_RSP
)
7495 | (1 << VCPU_EXREG_RFLAGS
)
7496 | (1 << VCPU_EXREG_PDPTR
)
7497 | (1 << VCPU_EXREG_SEGMENTS
)
7498 | (1 << VCPU_EXREG_CR3
));
7499 vcpu
->arch
.regs_dirty
= 0;
7501 vmx
->idt_vectoring_info
= vmcs_read32(IDT_VECTORING_INFO_FIELD
);
7503 vmx
->loaded_vmcs
->launched
= 1;
7505 vmx
->exit_reason
= vmcs_read32(VM_EXIT_REASON
);
7506 trace_kvm_exit(vmx
->exit_reason
, vcpu
, KVM_ISA_VMX
);
7509 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
7510 * we did not inject a still-pending event to L1 now because of
7511 * nested_run_pending, we need to re-enable this bit.
7513 if (vmx
->nested
.nested_run_pending
)
7514 kvm_make_request(KVM_REQ_EVENT
, vcpu
);
7516 vmx
->nested
.nested_run_pending
= 0;
7518 vmx_complete_atomic_exit(vmx
);
7519 vmx_recover_nmi_blocking(vmx
);
7520 vmx_complete_interrupts(vmx
);
7523 static void vmx_free_vcpu(struct kvm_vcpu
*vcpu
)
7525 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7528 free_loaded_vmcs(vmx
->loaded_vmcs
);
7530 kfree(vmx
->guest_msrs
);
7531 kvm_vcpu_uninit(vcpu
);
7532 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7535 static struct kvm_vcpu
*vmx_create_vcpu(struct kvm
*kvm
, unsigned int id
)
7538 struct vcpu_vmx
*vmx
= kmem_cache_zalloc(kvm_vcpu_cache
, GFP_KERNEL
);
7542 return ERR_PTR(-ENOMEM
);
7546 err
= kvm_vcpu_init(&vmx
->vcpu
, kvm
, id
);
7550 vmx
->guest_msrs
= kmalloc(PAGE_SIZE
, GFP_KERNEL
);
7552 if (!vmx
->guest_msrs
) {
7556 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
7557 vmx
->loaded_vmcs
->vmcs
= alloc_vmcs();
7558 if (!vmx
->loaded_vmcs
->vmcs
)
7561 kvm_cpu_vmxon(__pa(per_cpu(vmxarea
, raw_smp_processor_id())));
7562 loaded_vmcs_init(vmx
->loaded_vmcs
);
7567 vmx_vcpu_load(&vmx
->vcpu
, cpu
);
7568 vmx
->vcpu
.cpu
= cpu
;
7569 err
= vmx_vcpu_setup(vmx
);
7570 vmx_vcpu_put(&vmx
->vcpu
);
7574 if (vm_need_virtualize_apic_accesses(kvm
)) {
7575 err
= alloc_apic_access_page(kvm
);
7581 if (!kvm
->arch
.ept_identity_map_addr
)
7582 kvm
->arch
.ept_identity_map_addr
=
7583 VMX_EPT_IDENTITY_PAGETABLE_ADDR
;
7585 if (alloc_identity_pagetable(kvm
) != 0)
7587 if (!init_rmode_identity_map(kvm
))
7591 vmx
->nested
.current_vmptr
= -1ull;
7592 vmx
->nested
.current_vmcs12
= NULL
;
7597 free_loaded_vmcs(vmx
->loaded_vmcs
);
7599 kfree(vmx
->guest_msrs
);
7601 kvm_vcpu_uninit(&vmx
->vcpu
);
7604 kmem_cache_free(kvm_vcpu_cache
, vmx
);
7605 return ERR_PTR(err
);
7608 static void __init
vmx_check_processor_compat(void *rtn
)
7610 struct vmcs_config vmcs_conf
;
7613 if (setup_vmcs_config(&vmcs_conf
) < 0)
7615 if (memcmp(&vmcs_config
, &vmcs_conf
, sizeof(struct vmcs_config
)) != 0) {
7616 printk(KERN_ERR
"kvm: CPU %d feature inconsistency!\n",
7617 smp_processor_id());
7622 static int get_ept_level(void)
7624 return VMX_EPT_DEFAULT_GAW
+ 1;
7627 static u64
vmx_get_mt_mask(struct kvm_vcpu
*vcpu
, gfn_t gfn
, bool is_mmio
)
7631 /* For VT-d and EPT combination
7632 * 1. MMIO: always map as UC
7634 * a. VT-d without snooping control feature: can't guarantee the
7635 * result, try to trust guest.
7636 * b. VT-d with snooping control feature: snooping control feature of
7637 * VT-d engine can guarantee the cache correctness. Just set it
7638 * to WB to keep consistent with host. So the same as item 3.
7639 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
7640 * consistent with host MTRR
7643 ret
= MTRR_TYPE_UNCACHABLE
<< VMX_EPT_MT_EPTE_SHIFT
;
7644 else if (kvm_arch_has_noncoherent_dma(vcpu
->kvm
))
7645 ret
= kvm_get_guest_memory_type(vcpu
, gfn
) <<
7646 VMX_EPT_MT_EPTE_SHIFT
;
7648 ret
= (MTRR_TYPE_WRBACK
<< VMX_EPT_MT_EPTE_SHIFT
)
7654 static int vmx_get_lpage_level(void)
7656 if (enable_ept
&& !cpu_has_vmx_ept_1g_page())
7657 return PT_DIRECTORY_LEVEL
;
7659 /* For shadow and EPT supported 1GB page */
7660 return PT_PDPE_LEVEL
;
7663 static void vmx_cpuid_update(struct kvm_vcpu
*vcpu
)
7665 struct kvm_cpuid_entry2
*best
;
7666 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7669 vmx
->rdtscp_enabled
= false;
7670 if (vmx_rdtscp_supported()) {
7671 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7672 if (exec_control
& SECONDARY_EXEC_RDTSCP
) {
7673 best
= kvm_find_cpuid_entry(vcpu
, 0x80000001, 0);
7674 if (best
&& (best
->edx
& bit(X86_FEATURE_RDTSCP
)))
7675 vmx
->rdtscp_enabled
= true;
7677 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7678 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7684 /* Exposing INVPCID only when PCID is exposed */
7685 best
= kvm_find_cpuid_entry(vcpu
, 0x7, 0);
7686 if (vmx_invpcid_supported() &&
7687 best
&& (best
->ebx
& bit(X86_FEATURE_INVPCID
)) &&
7688 guest_cpuid_has_pcid(vcpu
)) {
7689 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7690 exec_control
|= SECONDARY_EXEC_ENABLE_INVPCID
;
7691 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7694 if (cpu_has_secondary_exec_ctrls()) {
7695 exec_control
= vmcs_read32(SECONDARY_VM_EXEC_CONTROL
);
7696 exec_control
&= ~SECONDARY_EXEC_ENABLE_INVPCID
;
7697 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
,
7701 best
->ebx
&= ~bit(X86_FEATURE_INVPCID
);
7705 static void vmx_set_supported_cpuid(u32 func
, struct kvm_cpuid_entry2
*entry
)
7707 if (func
== 1 && nested
)
7708 entry
->ecx
|= bit(X86_FEATURE_VMX
);
7711 static void nested_ept_inject_page_fault(struct kvm_vcpu
*vcpu
,
7712 struct x86_exception
*fault
)
7714 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7717 if (fault
->error_code
& PFERR_RSVD_MASK
)
7718 exit_reason
= EXIT_REASON_EPT_MISCONFIG
;
7720 exit_reason
= EXIT_REASON_EPT_VIOLATION
;
7721 nested_vmx_vmexit(vcpu
, exit_reason
, 0, vcpu
->arch
.exit_qualification
);
7722 vmcs12
->guest_physical_address
= fault
->address
;
7725 /* Callbacks for nested_ept_init_mmu_context: */
7727 static unsigned long nested_ept_get_cr3(struct kvm_vcpu
*vcpu
)
7729 /* return the page table to be shadowed - in our case, EPT12 */
7730 return get_vmcs12(vcpu
)->ept_pointer
;
7733 static void nested_ept_init_mmu_context(struct kvm_vcpu
*vcpu
)
7735 kvm_init_shadow_ept_mmu(vcpu
, &vcpu
->arch
.mmu
,
7736 nested_vmx_ept_caps
& VMX_EPT_EXECUTE_ONLY_BIT
);
7738 vcpu
->arch
.mmu
.set_cr3
= vmx_set_cr3
;
7739 vcpu
->arch
.mmu
.get_cr3
= nested_ept_get_cr3
;
7740 vcpu
->arch
.mmu
.inject_page_fault
= nested_ept_inject_page_fault
;
7742 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.nested_mmu
;
7745 static void nested_ept_uninit_mmu_context(struct kvm_vcpu
*vcpu
)
7747 vcpu
->arch
.walk_mmu
= &vcpu
->arch
.mmu
;
7750 static void vmx_inject_page_fault_nested(struct kvm_vcpu
*vcpu
,
7751 struct x86_exception
*fault
)
7753 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
7755 WARN_ON(!is_guest_mode(vcpu
));
7757 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
7758 if (vmcs12
->exception_bitmap
& (1u << PF_VECTOR
))
7759 nested_vmx_vmexit(vcpu
, to_vmx(vcpu
)->exit_reason
,
7760 vmcs_read32(VM_EXIT_INTR_INFO
),
7761 vmcs_readl(EXIT_QUALIFICATION
));
7763 kvm_inject_page_fault(vcpu
, fault
);
7766 static void vmx_start_preemption_timer(struct kvm_vcpu
*vcpu
)
7768 u64 preemption_timeout
= get_vmcs12(vcpu
)->vmx_preemption_timer_value
;
7769 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7771 if (vcpu
->arch
.virtual_tsc_khz
== 0)
7774 /* Make sure short timeouts reliably trigger an immediate vmexit.
7775 * hrtimer_start does not guarantee this. */
7776 if (preemption_timeout
<= 1) {
7777 vmx_preemption_timer_fn(&vmx
->nested
.preemption_timer
);
7781 preemption_timeout
<<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
7782 preemption_timeout
*= 1000000;
7783 do_div(preemption_timeout
, vcpu
->arch
.virtual_tsc_khz
);
7784 hrtimer_start(&vmx
->nested
.preemption_timer
,
7785 ns_to_ktime(preemption_timeout
), HRTIMER_MODE_REL
);
7789 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
7790 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
7791 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
7792 * guest in a way that will both be appropriate to L1's requests, and our
7793 * needs. In addition to modifying the active vmcs (which is vmcs02), this
7794 * function also has additional necessary side-effects, like setting various
7795 * vcpu->arch fields.
7797 static void prepare_vmcs02(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
7799 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
7802 vmcs_write16(GUEST_ES_SELECTOR
, vmcs12
->guest_es_selector
);
7803 vmcs_write16(GUEST_CS_SELECTOR
, vmcs12
->guest_cs_selector
);
7804 vmcs_write16(GUEST_SS_SELECTOR
, vmcs12
->guest_ss_selector
);
7805 vmcs_write16(GUEST_DS_SELECTOR
, vmcs12
->guest_ds_selector
);
7806 vmcs_write16(GUEST_FS_SELECTOR
, vmcs12
->guest_fs_selector
);
7807 vmcs_write16(GUEST_GS_SELECTOR
, vmcs12
->guest_gs_selector
);
7808 vmcs_write16(GUEST_LDTR_SELECTOR
, vmcs12
->guest_ldtr_selector
);
7809 vmcs_write16(GUEST_TR_SELECTOR
, vmcs12
->guest_tr_selector
);
7810 vmcs_write32(GUEST_ES_LIMIT
, vmcs12
->guest_es_limit
);
7811 vmcs_write32(GUEST_CS_LIMIT
, vmcs12
->guest_cs_limit
);
7812 vmcs_write32(GUEST_SS_LIMIT
, vmcs12
->guest_ss_limit
);
7813 vmcs_write32(GUEST_DS_LIMIT
, vmcs12
->guest_ds_limit
);
7814 vmcs_write32(GUEST_FS_LIMIT
, vmcs12
->guest_fs_limit
);
7815 vmcs_write32(GUEST_GS_LIMIT
, vmcs12
->guest_gs_limit
);
7816 vmcs_write32(GUEST_LDTR_LIMIT
, vmcs12
->guest_ldtr_limit
);
7817 vmcs_write32(GUEST_TR_LIMIT
, vmcs12
->guest_tr_limit
);
7818 vmcs_write32(GUEST_GDTR_LIMIT
, vmcs12
->guest_gdtr_limit
);
7819 vmcs_write32(GUEST_IDTR_LIMIT
, vmcs12
->guest_idtr_limit
);
7820 vmcs_write32(GUEST_ES_AR_BYTES
, vmcs12
->guest_es_ar_bytes
);
7821 vmcs_write32(GUEST_CS_AR_BYTES
, vmcs12
->guest_cs_ar_bytes
);
7822 vmcs_write32(GUEST_SS_AR_BYTES
, vmcs12
->guest_ss_ar_bytes
);
7823 vmcs_write32(GUEST_DS_AR_BYTES
, vmcs12
->guest_ds_ar_bytes
);
7824 vmcs_write32(GUEST_FS_AR_BYTES
, vmcs12
->guest_fs_ar_bytes
);
7825 vmcs_write32(GUEST_GS_AR_BYTES
, vmcs12
->guest_gs_ar_bytes
);
7826 vmcs_write32(GUEST_LDTR_AR_BYTES
, vmcs12
->guest_ldtr_ar_bytes
);
7827 vmcs_write32(GUEST_TR_AR_BYTES
, vmcs12
->guest_tr_ar_bytes
);
7828 vmcs_writel(GUEST_ES_BASE
, vmcs12
->guest_es_base
);
7829 vmcs_writel(GUEST_CS_BASE
, vmcs12
->guest_cs_base
);
7830 vmcs_writel(GUEST_SS_BASE
, vmcs12
->guest_ss_base
);
7831 vmcs_writel(GUEST_DS_BASE
, vmcs12
->guest_ds_base
);
7832 vmcs_writel(GUEST_FS_BASE
, vmcs12
->guest_fs_base
);
7833 vmcs_writel(GUEST_GS_BASE
, vmcs12
->guest_gs_base
);
7834 vmcs_writel(GUEST_LDTR_BASE
, vmcs12
->guest_ldtr_base
);
7835 vmcs_writel(GUEST_TR_BASE
, vmcs12
->guest_tr_base
);
7836 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->guest_gdtr_base
);
7837 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->guest_idtr_base
);
7839 vmcs_write64(GUEST_IA32_DEBUGCTL
, vmcs12
->guest_ia32_debugctl
);
7840 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD
,
7841 vmcs12
->vm_entry_intr_info_field
);
7842 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE
,
7843 vmcs12
->vm_entry_exception_error_code
);
7844 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN
,
7845 vmcs12
->vm_entry_instruction_len
);
7846 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO
,
7847 vmcs12
->guest_interruptibility_info
);
7848 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->guest_sysenter_cs
);
7849 kvm_set_dr(vcpu
, 7, vmcs12
->guest_dr7
);
7850 vmx_set_rflags(vcpu
, vmcs12
->guest_rflags
);
7851 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS
,
7852 vmcs12
->guest_pending_dbg_exceptions
);
7853 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->guest_sysenter_esp
);
7854 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->guest_sysenter_eip
);
7856 vmcs_write64(VMCS_LINK_POINTER
, -1ull);
7858 exec_control
= vmcs12
->pin_based_vm_exec_control
;
7859 exec_control
|= vmcs_config
.pin_based_exec_ctrl
;
7860 exec_control
&= ~(PIN_BASED_VMX_PREEMPTION_TIMER
|
7861 PIN_BASED_POSTED_INTR
);
7862 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL
, exec_control
);
7864 vmx
->nested
.preemption_timer_expired
= false;
7865 if (nested_cpu_has_preemption_timer(vmcs12
))
7866 vmx_start_preemption_timer(vcpu
);
7869 * Whether page-faults are trapped is determined by a combination of
7870 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
7871 * If enable_ept, L0 doesn't care about page faults and we should
7872 * set all of these to L1's desires. However, if !enable_ept, L0 does
7873 * care about (at least some) page faults, and because it is not easy
7874 * (if at all possible?) to merge L0 and L1's desires, we simply ask
7875 * to exit on each and every L2 page fault. This is done by setting
7876 * MASK=MATCH=0 and (see below) EB.PF=1.
7877 * Note that below we don't need special code to set EB.PF beyond the
7878 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
7879 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
7880 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
7882 * A problem with this approach (when !enable_ept) is that L1 may be
7883 * injected with more page faults than it asked for. This could have
7884 * caused problems, but in practice existing hypervisors don't care.
7885 * To fix this, we will need to emulate the PFEC checking (on the L1
7886 * page tables), using walk_addr(), when injecting PFs to L1.
7888 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK
,
7889 enable_ept
? vmcs12
->page_fault_error_code_mask
: 0);
7890 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH
,
7891 enable_ept
? vmcs12
->page_fault_error_code_match
: 0);
7893 if (cpu_has_secondary_exec_ctrls()) {
7894 exec_control
= vmx_secondary_exec_control(vmx
);
7895 if (!vmx
->rdtscp_enabled
)
7896 exec_control
&= ~SECONDARY_EXEC_RDTSCP
;
7897 /* Take the following fields only from vmcs12 */
7898 exec_control
&= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
|
7899 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY
|
7900 SECONDARY_EXEC_APIC_REGISTER_VIRT
);
7901 if (nested_cpu_has(vmcs12
,
7902 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS
))
7903 exec_control
|= vmcs12
->secondary_vm_exec_control
;
7905 if (exec_control
& SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) {
7907 * Translate L1 physical address to host physical
7908 * address for vmcs02. Keep the page pinned, so this
7909 * physical address remains valid. We keep a reference
7910 * to it so we can release it later.
7912 if (vmx
->nested
.apic_access_page
) /* shouldn't happen */
7913 nested_release_page(vmx
->nested
.apic_access_page
);
7914 vmx
->nested
.apic_access_page
=
7915 nested_get_page(vcpu
, vmcs12
->apic_access_addr
);
7917 * If translation failed, no matter: This feature asks
7918 * to exit when accessing the given address, and if it
7919 * can never be accessed, this feature won't do
7922 if (!vmx
->nested
.apic_access_page
)
7924 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7926 vmcs_write64(APIC_ACCESS_ADDR
,
7927 page_to_phys(vmx
->nested
.apic_access_page
));
7928 } else if (vm_need_virtualize_apic_accesses(vmx
->vcpu
.kvm
)) {
7930 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
;
7931 vmcs_write64(APIC_ACCESS_ADDR
,
7932 page_to_phys(vcpu
->kvm
->arch
.apic_access_page
));
7935 vmcs_write32(SECONDARY_VM_EXEC_CONTROL
, exec_control
);
7940 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
7941 * Some constant fields are set here by vmx_set_constant_host_state().
7942 * Other fields are different per CPU, and will be set later when
7943 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
7945 vmx_set_constant_host_state(vmx
);
7948 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
7949 * entry, but only if the current (host) sp changed from the value
7950 * we wrote last (vmx->host_rsp). This cache is no longer relevant
7951 * if we switch vmcs, and rather than hold a separate cache per vmcs,
7952 * here we just force the write to happen on entry.
7956 exec_control
= vmx_exec_control(vmx
); /* L0's desires */
7957 exec_control
&= ~CPU_BASED_VIRTUAL_INTR_PENDING
;
7958 exec_control
&= ~CPU_BASED_VIRTUAL_NMI_PENDING
;
7959 exec_control
&= ~CPU_BASED_TPR_SHADOW
;
7960 exec_control
|= vmcs12
->cpu_based_vm_exec_control
;
7962 * Merging of IO and MSR bitmaps not currently supported.
7963 * Rather, exit every time.
7965 exec_control
&= ~CPU_BASED_USE_MSR_BITMAPS
;
7966 exec_control
&= ~CPU_BASED_USE_IO_BITMAPS
;
7967 exec_control
|= CPU_BASED_UNCOND_IO_EXITING
;
7969 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL
, exec_control
);
7971 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
7972 * bitwise-or of what L1 wants to trap for L2, and what we want to
7973 * trap. Note that CR0.TS also needs updating - we do this later.
7975 update_exception_bitmap(vcpu
);
7976 vcpu
->arch
.cr0_guest_owned_bits
&= ~vmcs12
->cr0_guest_host_mask
;
7977 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
7979 /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
7980 * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
7981 * bits are further modified by vmx_set_efer() below.
7983 vmcs_write32(VM_EXIT_CONTROLS
, vmcs_config
.vmexit_ctrl
);
7985 /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
7986 * emulated by vmx_set_efer(), below.
7988 vm_entry_controls_init(vmx
,
7989 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_LOAD_IA32_EFER
&
7990 ~VM_ENTRY_IA32E_MODE
) |
7991 (vmcs_config
.vmentry_ctrl
& ~VM_ENTRY_IA32E_MODE
));
7993 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_PAT
) {
7994 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->guest_ia32_pat
);
7995 vcpu
->arch
.pat
= vmcs12
->guest_ia32_pat
;
7996 } else if (vmcs_config
.vmentry_ctrl
& VM_ENTRY_LOAD_IA32_PAT
)
7997 vmcs_write64(GUEST_IA32_PAT
, vmx
->vcpu
.arch
.pat
);
8000 set_cr4_guest_host_mask(vmx
);
8002 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_BNDCFGS
)
8003 vmcs_write64(GUEST_BNDCFGS
, vmcs12
->guest_bndcfgs
);
8005 if (vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_TSC_OFFSETING
)
8006 vmcs_write64(TSC_OFFSET
,
8007 vmx
->nested
.vmcs01_tsc_offset
+ vmcs12
->tsc_offset
);
8009 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8013 * Trivially support vpid by letting L2s share their parent
8014 * L1's vpid. TODO: move to a more elaborate solution, giving
8015 * each L2 its own vpid and exposing the vpid feature to L1.
8017 vmcs_write16(VIRTUAL_PROCESSOR_ID
, vmx
->vpid
);
8018 vmx_flush_tlb(vcpu
);
8021 if (nested_cpu_has_ept(vmcs12
)) {
8022 kvm_mmu_unload(vcpu
);
8023 nested_ept_init_mmu_context(vcpu
);
8026 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
)
8027 vcpu
->arch
.efer
= vmcs12
->guest_ia32_efer
;
8028 else if (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
)
8029 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8031 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8032 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
8033 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8036 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
8037 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
8038 * The CR0_READ_SHADOW is what L2 should have expected to read given
8039 * the specifications by L1; It's not enough to take
8040 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
8041 * have more bits than L1 expected.
8043 vmx_set_cr0(vcpu
, vmcs12
->guest_cr0
);
8044 vmcs_writel(CR0_READ_SHADOW
, nested_read_cr0(vmcs12
));
8046 vmx_set_cr4(vcpu
, vmcs12
->guest_cr4
);
8047 vmcs_writel(CR4_READ_SHADOW
, nested_read_cr4(vmcs12
));
8049 /* shadow page tables on either EPT or shadow page tables */
8050 kvm_set_cr3(vcpu
, vmcs12
->guest_cr3
);
8051 kvm_mmu_reset_context(vcpu
);
8054 vcpu
->arch
.walk_mmu
->inject_page_fault
= vmx_inject_page_fault_nested
;
8057 * L1 may access the L2's PDPTR, so save them to construct vmcs12
8060 vmcs_write64(GUEST_PDPTR0
, vmcs12
->guest_pdptr0
);
8061 vmcs_write64(GUEST_PDPTR1
, vmcs12
->guest_pdptr1
);
8062 vmcs_write64(GUEST_PDPTR2
, vmcs12
->guest_pdptr2
);
8063 vmcs_write64(GUEST_PDPTR3
, vmcs12
->guest_pdptr3
);
8066 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->guest_rsp
);
8067 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->guest_rip
);
8071 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
8072 * for running an L2 nested guest.
8074 static int nested_vmx_run(struct kvm_vcpu
*vcpu
, bool launch
)
8076 struct vmcs12
*vmcs12
;
8077 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8079 struct loaded_vmcs
*vmcs02
;
8082 if (!nested_vmx_check_permission(vcpu
) ||
8083 !nested_vmx_check_vmcs12(vcpu
))
8086 skip_emulated_instruction(vcpu
);
8087 vmcs12
= get_vmcs12(vcpu
);
8089 if (enable_shadow_vmcs
)
8090 copy_shadow_to_vmcs12(vmx
);
8093 * The nested entry process starts with enforcing various prerequisites
8094 * on vmcs12 as required by the Intel SDM, and act appropriately when
8095 * they fail: As the SDM explains, some conditions should cause the
8096 * instruction to fail, while others will cause the instruction to seem
8097 * to succeed, but return an EXIT_REASON_INVALID_STATE.
8098 * To speed up the normal (success) code path, we should avoid checking
8099 * for misconfigurations which will anyway be caught by the processor
8100 * when using the merged vmcs02.
8102 if (vmcs12
->launch_state
== launch
) {
8103 nested_vmx_failValid(vcpu
,
8104 launch
? VMXERR_VMLAUNCH_NONCLEAR_VMCS
8105 : VMXERR_VMRESUME_NONLAUNCHED_VMCS
);
8109 if (vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_ACTIVE
&&
8110 vmcs12
->guest_activity_state
!= GUEST_ACTIVITY_HLT
) {
8111 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8115 if ((vmcs12
->cpu_based_vm_exec_control
& CPU_BASED_USE_MSR_BITMAPS
) &&
8116 !IS_ALIGNED(vmcs12
->msr_bitmap
, PAGE_SIZE
)) {
8117 /*TODO: Also verify bits beyond physical address width are 0*/
8118 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8122 if (nested_cpu_has2(vmcs12
, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES
) &&
8123 !IS_ALIGNED(vmcs12
->apic_access_addr
, PAGE_SIZE
)) {
8124 /*TODO: Also verify bits beyond physical address width are 0*/
8125 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8129 if (vmcs12
->vm_entry_msr_load_count
> 0 ||
8130 vmcs12
->vm_exit_msr_load_count
> 0 ||
8131 vmcs12
->vm_exit_msr_store_count
> 0) {
8132 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
8134 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8138 if (!vmx_control_verify(vmcs12
->cpu_based_vm_exec_control
,
8139 nested_vmx_procbased_ctls_low
, nested_vmx_procbased_ctls_high
) ||
8140 !vmx_control_verify(vmcs12
->secondary_vm_exec_control
,
8141 nested_vmx_secondary_ctls_low
, nested_vmx_secondary_ctls_high
) ||
8142 !vmx_control_verify(vmcs12
->pin_based_vm_exec_control
,
8143 nested_vmx_pinbased_ctls_low
, nested_vmx_pinbased_ctls_high
) ||
8144 !vmx_control_verify(vmcs12
->vm_exit_controls
,
8145 nested_vmx_exit_ctls_low
, nested_vmx_exit_ctls_high
) ||
8146 !vmx_control_verify(vmcs12
->vm_entry_controls
,
8147 nested_vmx_entry_ctls_low
, nested_vmx_entry_ctls_high
))
8149 nested_vmx_failValid(vcpu
, VMXERR_ENTRY_INVALID_CONTROL_FIELD
);
8153 if (((vmcs12
->host_cr0
& VMXON_CR0_ALWAYSON
) != VMXON_CR0_ALWAYSON
) ||
8154 ((vmcs12
->host_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8155 nested_vmx_failValid(vcpu
,
8156 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD
);
8160 if (!nested_cr0_valid(vmcs12
, vmcs12
->guest_cr0
) ||
8161 ((vmcs12
->guest_cr4
& VMXON_CR4_ALWAYSON
) != VMXON_CR4_ALWAYSON
)) {
8162 nested_vmx_entry_failure(vcpu
, vmcs12
,
8163 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8166 if (vmcs12
->vmcs_link_pointer
!= -1ull) {
8167 nested_vmx_entry_failure(vcpu
, vmcs12
,
8168 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_VMCS_LINK_PTR
);
8173 * If the load IA32_EFER VM-entry control is 1, the following checks
8174 * are performed on the field for the IA32_EFER MSR:
8175 * - Bits reserved in the IA32_EFER MSR must be 0.
8176 * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
8177 * the IA-32e mode guest VM-exit control. It must also be identical
8178 * to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
8181 if (vmcs12
->vm_entry_controls
& VM_ENTRY_LOAD_IA32_EFER
) {
8182 ia32e
= (vmcs12
->vm_entry_controls
& VM_ENTRY_IA32E_MODE
) != 0;
8183 if (!kvm_valid_efer(vcpu
, vmcs12
->guest_ia32_efer
) ||
8184 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LMA
) ||
8185 ((vmcs12
->guest_cr0
& X86_CR0_PG
) &&
8186 ia32e
!= !!(vmcs12
->guest_ia32_efer
& EFER_LME
))) {
8187 nested_vmx_entry_failure(vcpu
, vmcs12
,
8188 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8194 * If the load IA32_EFER VM-exit control is 1, bits reserved in the
8195 * IA32_EFER MSR must be 0 in the field for that register. In addition,
8196 * the values of the LMA and LME bits in the field must each be that of
8197 * the host address-space size VM-exit control.
8199 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
) {
8200 ia32e
= (vmcs12
->vm_exit_controls
&
8201 VM_EXIT_HOST_ADDR_SPACE_SIZE
) != 0;
8202 if (!kvm_valid_efer(vcpu
, vmcs12
->host_ia32_efer
) ||
8203 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LMA
) ||
8204 ia32e
!= !!(vmcs12
->host_ia32_efer
& EFER_LME
)) {
8205 nested_vmx_entry_failure(vcpu
, vmcs12
,
8206 EXIT_REASON_INVALID_STATE
, ENTRY_FAIL_DEFAULT
);
8212 * We're finally done with prerequisite checking, and can start with
8216 vmcs02
= nested_get_current_vmcs02(vmx
);
8220 enter_guest_mode(vcpu
);
8222 vmx
->nested
.vmcs01_tsc_offset
= vmcs_read64(TSC_OFFSET
);
8225 vmx
->loaded_vmcs
= vmcs02
;
8227 vmx_vcpu_load(vcpu
, cpu
);
8231 vmx_segment_cache_clear(vmx
);
8233 vmcs12
->launch_state
= 1;
8235 prepare_vmcs02(vcpu
, vmcs12
);
8237 if (vmcs12
->guest_activity_state
== GUEST_ACTIVITY_HLT
)
8238 return kvm_emulate_halt(vcpu
);
8240 vmx
->nested
.nested_run_pending
= 1;
8243 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
8244 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
8245 * returned as far as L1 is concerned. It will only return (and set
8246 * the success flag) when L2 exits (see nested_vmx_vmexit()).
8252 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
8253 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
8254 * This function returns the new value we should put in vmcs12.guest_cr0.
8255 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
8256 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
8257 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
8258 * didn't trap the bit, because if L1 did, so would L0).
8259 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
8260 * been modified by L2, and L1 knows it. So just leave the old value of
8261 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
8262 * isn't relevant, because if L0 traps this bit it can set it to anything.
8263 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
8264 * changed these bits, and therefore they need to be updated, but L0
8265 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
8266 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
8268 static inline unsigned long
8269 vmcs12_guest_cr0(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8272 /*1*/ (vmcs_readl(GUEST_CR0
) & vcpu
->arch
.cr0_guest_owned_bits
) |
8273 /*2*/ (vmcs12
->guest_cr0
& vmcs12
->cr0_guest_host_mask
) |
8274 /*3*/ (vmcs_readl(CR0_READ_SHADOW
) & ~(vmcs12
->cr0_guest_host_mask
|
8275 vcpu
->arch
.cr0_guest_owned_bits
));
8278 static inline unsigned long
8279 vmcs12_guest_cr4(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
)
8282 /*1*/ (vmcs_readl(GUEST_CR4
) & vcpu
->arch
.cr4_guest_owned_bits
) |
8283 /*2*/ (vmcs12
->guest_cr4
& vmcs12
->cr4_guest_host_mask
) |
8284 /*3*/ (vmcs_readl(CR4_READ_SHADOW
) & ~(vmcs12
->cr4_guest_host_mask
|
8285 vcpu
->arch
.cr4_guest_owned_bits
));
8288 static void vmcs12_save_pending_event(struct kvm_vcpu
*vcpu
,
8289 struct vmcs12
*vmcs12
)
8294 if (vcpu
->arch
.exception
.pending
&& vcpu
->arch
.exception
.reinject
) {
8295 nr
= vcpu
->arch
.exception
.nr
;
8296 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8298 if (kvm_exception_is_soft(nr
)) {
8299 vmcs12
->vm_exit_instruction_len
=
8300 vcpu
->arch
.event_exit_inst_len
;
8301 idt_vectoring
|= INTR_TYPE_SOFT_EXCEPTION
;
8303 idt_vectoring
|= INTR_TYPE_HARD_EXCEPTION
;
8305 if (vcpu
->arch
.exception
.has_error_code
) {
8306 idt_vectoring
|= VECTORING_INFO_DELIVER_CODE_MASK
;
8307 vmcs12
->idt_vectoring_error_code
=
8308 vcpu
->arch
.exception
.error_code
;
8311 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8312 } else if (vcpu
->arch
.nmi_injected
) {
8313 vmcs12
->idt_vectoring_info_field
=
8314 INTR_TYPE_NMI_INTR
| INTR_INFO_VALID_MASK
| NMI_VECTOR
;
8315 } else if (vcpu
->arch
.interrupt
.pending
) {
8316 nr
= vcpu
->arch
.interrupt
.nr
;
8317 idt_vectoring
= nr
| VECTORING_INFO_VALID_MASK
;
8319 if (vcpu
->arch
.interrupt
.soft
) {
8320 idt_vectoring
|= INTR_TYPE_SOFT_INTR
;
8321 vmcs12
->vm_entry_instruction_len
=
8322 vcpu
->arch
.event_exit_inst_len
;
8324 idt_vectoring
|= INTR_TYPE_EXT_INTR
;
8326 vmcs12
->idt_vectoring_info_field
= idt_vectoring
;
8330 static int vmx_check_nested_events(struct kvm_vcpu
*vcpu
, bool external_intr
)
8332 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8334 if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu
)) &&
8335 vmx
->nested
.preemption_timer_expired
) {
8336 if (vmx
->nested
.nested_run_pending
)
8338 nested_vmx_vmexit(vcpu
, EXIT_REASON_PREEMPTION_TIMER
, 0, 0);
8342 if (vcpu
->arch
.nmi_pending
&& nested_exit_on_nmi(vcpu
)) {
8343 if (vmx
->nested
.nested_run_pending
||
8344 vcpu
->arch
.interrupt
.pending
)
8346 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXCEPTION_NMI
,
8347 NMI_VECTOR
| INTR_TYPE_NMI_INTR
|
8348 INTR_INFO_VALID_MASK
, 0);
8350 * The NMI-triggered VM exit counts as injection:
8351 * clear this one and block further NMIs.
8353 vcpu
->arch
.nmi_pending
= 0;
8354 vmx_set_nmi_mask(vcpu
, true);
8358 if ((kvm_cpu_has_interrupt(vcpu
) || external_intr
) &&
8359 nested_exit_on_intr(vcpu
)) {
8360 if (vmx
->nested
.nested_run_pending
)
8362 nested_vmx_vmexit(vcpu
, EXIT_REASON_EXTERNAL_INTERRUPT
, 0, 0);
8368 static u32
vmx_get_preemption_timer_value(struct kvm_vcpu
*vcpu
)
8371 hrtimer_get_remaining(&to_vmx(vcpu
)->nested
.preemption_timer
);
8374 if (ktime_to_ns(remaining
) <= 0)
8377 value
= ktime_to_ns(remaining
) * vcpu
->arch
.virtual_tsc_khz
;
8378 do_div(value
, 1000000);
8379 return value
>> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE
;
8383 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
8384 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
8385 * and this function updates it to reflect the changes to the guest state while
8386 * L2 was running (and perhaps made some exits which were handled directly by L0
8387 * without going back to L1), and to reflect the exit reason.
8388 * Note that we do not have to copy here all VMCS fields, just those that
8389 * could have changed by the L2 guest or the exit - i.e., the guest-state and
8390 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
8391 * which already writes to vmcs12 directly.
8393 static void prepare_vmcs12(struct kvm_vcpu
*vcpu
, struct vmcs12
*vmcs12
,
8394 u32 exit_reason
, u32 exit_intr_info
,
8395 unsigned long exit_qualification
)
8397 /* update guest state fields: */
8398 vmcs12
->guest_cr0
= vmcs12_guest_cr0(vcpu
, vmcs12
);
8399 vmcs12
->guest_cr4
= vmcs12_guest_cr4(vcpu
, vmcs12
);
8401 kvm_get_dr(vcpu
, 7, (unsigned long *)&vmcs12
->guest_dr7
);
8402 vmcs12
->guest_rsp
= kvm_register_read(vcpu
, VCPU_REGS_RSP
);
8403 vmcs12
->guest_rip
= kvm_register_read(vcpu
, VCPU_REGS_RIP
);
8404 vmcs12
->guest_rflags
= vmcs_readl(GUEST_RFLAGS
);
8406 vmcs12
->guest_es_selector
= vmcs_read16(GUEST_ES_SELECTOR
);
8407 vmcs12
->guest_cs_selector
= vmcs_read16(GUEST_CS_SELECTOR
);
8408 vmcs12
->guest_ss_selector
= vmcs_read16(GUEST_SS_SELECTOR
);
8409 vmcs12
->guest_ds_selector
= vmcs_read16(GUEST_DS_SELECTOR
);
8410 vmcs12
->guest_fs_selector
= vmcs_read16(GUEST_FS_SELECTOR
);
8411 vmcs12
->guest_gs_selector
= vmcs_read16(GUEST_GS_SELECTOR
);
8412 vmcs12
->guest_ldtr_selector
= vmcs_read16(GUEST_LDTR_SELECTOR
);
8413 vmcs12
->guest_tr_selector
= vmcs_read16(GUEST_TR_SELECTOR
);
8414 vmcs12
->guest_es_limit
= vmcs_read32(GUEST_ES_LIMIT
);
8415 vmcs12
->guest_cs_limit
= vmcs_read32(GUEST_CS_LIMIT
);
8416 vmcs12
->guest_ss_limit
= vmcs_read32(GUEST_SS_LIMIT
);
8417 vmcs12
->guest_ds_limit
= vmcs_read32(GUEST_DS_LIMIT
);
8418 vmcs12
->guest_fs_limit
= vmcs_read32(GUEST_FS_LIMIT
);
8419 vmcs12
->guest_gs_limit
= vmcs_read32(GUEST_GS_LIMIT
);
8420 vmcs12
->guest_ldtr_limit
= vmcs_read32(GUEST_LDTR_LIMIT
);
8421 vmcs12
->guest_tr_limit
= vmcs_read32(GUEST_TR_LIMIT
);
8422 vmcs12
->guest_gdtr_limit
= vmcs_read32(GUEST_GDTR_LIMIT
);
8423 vmcs12
->guest_idtr_limit
= vmcs_read32(GUEST_IDTR_LIMIT
);
8424 vmcs12
->guest_es_ar_bytes
= vmcs_read32(GUEST_ES_AR_BYTES
);
8425 vmcs12
->guest_cs_ar_bytes
= vmcs_read32(GUEST_CS_AR_BYTES
);
8426 vmcs12
->guest_ss_ar_bytes
= vmcs_read32(GUEST_SS_AR_BYTES
);
8427 vmcs12
->guest_ds_ar_bytes
= vmcs_read32(GUEST_DS_AR_BYTES
);
8428 vmcs12
->guest_fs_ar_bytes
= vmcs_read32(GUEST_FS_AR_BYTES
);
8429 vmcs12
->guest_gs_ar_bytes
= vmcs_read32(GUEST_GS_AR_BYTES
);
8430 vmcs12
->guest_ldtr_ar_bytes
= vmcs_read32(GUEST_LDTR_AR_BYTES
);
8431 vmcs12
->guest_tr_ar_bytes
= vmcs_read32(GUEST_TR_AR_BYTES
);
8432 vmcs12
->guest_es_base
= vmcs_readl(GUEST_ES_BASE
);
8433 vmcs12
->guest_cs_base
= vmcs_readl(GUEST_CS_BASE
);
8434 vmcs12
->guest_ss_base
= vmcs_readl(GUEST_SS_BASE
);
8435 vmcs12
->guest_ds_base
= vmcs_readl(GUEST_DS_BASE
);
8436 vmcs12
->guest_fs_base
= vmcs_readl(GUEST_FS_BASE
);
8437 vmcs12
->guest_gs_base
= vmcs_readl(GUEST_GS_BASE
);
8438 vmcs12
->guest_ldtr_base
= vmcs_readl(GUEST_LDTR_BASE
);
8439 vmcs12
->guest_tr_base
= vmcs_readl(GUEST_TR_BASE
);
8440 vmcs12
->guest_gdtr_base
= vmcs_readl(GUEST_GDTR_BASE
);
8441 vmcs12
->guest_idtr_base
= vmcs_readl(GUEST_IDTR_BASE
);
8443 vmcs12
->guest_interruptibility_info
=
8444 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO
);
8445 vmcs12
->guest_pending_dbg_exceptions
=
8446 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS
);
8447 if (vcpu
->arch
.mp_state
== KVM_MP_STATE_HALTED
)
8448 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_HLT
;
8450 vmcs12
->guest_activity_state
= GUEST_ACTIVITY_ACTIVE
;
8452 if (nested_cpu_has_preemption_timer(vmcs12
)) {
8453 if (vmcs12
->vm_exit_controls
&
8454 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER
)
8455 vmcs12
->vmx_preemption_timer_value
=
8456 vmx_get_preemption_timer_value(vcpu
);
8457 hrtimer_cancel(&to_vmx(vcpu
)->nested
.preemption_timer
);
8461 * In some cases (usually, nested EPT), L2 is allowed to change its
8462 * own CR3 without exiting. If it has changed it, we must keep it.
8463 * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
8464 * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
8466 * Additionally, restore L2's PDPTR to vmcs12.
8469 vmcs12
->guest_cr3
= vmcs_read64(GUEST_CR3
);
8470 vmcs12
->guest_pdptr0
= vmcs_read64(GUEST_PDPTR0
);
8471 vmcs12
->guest_pdptr1
= vmcs_read64(GUEST_PDPTR1
);
8472 vmcs12
->guest_pdptr2
= vmcs_read64(GUEST_PDPTR2
);
8473 vmcs12
->guest_pdptr3
= vmcs_read64(GUEST_PDPTR3
);
8476 vmcs12
->vm_entry_controls
=
8477 (vmcs12
->vm_entry_controls
& ~VM_ENTRY_IA32E_MODE
) |
8478 (vm_entry_controls_get(to_vmx(vcpu
)) & VM_ENTRY_IA32E_MODE
);
8480 /* TODO: These cannot have changed unless we have MSR bitmaps and
8481 * the relevant bit asks not to trap the change */
8482 vmcs12
->guest_ia32_debugctl
= vmcs_read64(GUEST_IA32_DEBUGCTL
);
8483 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_PAT
)
8484 vmcs12
->guest_ia32_pat
= vmcs_read64(GUEST_IA32_PAT
);
8485 if (vmcs12
->vm_exit_controls
& VM_EXIT_SAVE_IA32_EFER
)
8486 vmcs12
->guest_ia32_efer
= vcpu
->arch
.efer
;
8487 vmcs12
->guest_sysenter_cs
= vmcs_read32(GUEST_SYSENTER_CS
);
8488 vmcs12
->guest_sysenter_esp
= vmcs_readl(GUEST_SYSENTER_ESP
);
8489 vmcs12
->guest_sysenter_eip
= vmcs_readl(GUEST_SYSENTER_EIP
);
8490 if (vmx_mpx_supported())
8491 vmcs12
->guest_bndcfgs
= vmcs_read64(GUEST_BNDCFGS
);
8493 /* update exit information fields: */
8495 vmcs12
->vm_exit_reason
= exit_reason
;
8496 vmcs12
->exit_qualification
= exit_qualification
;
8498 vmcs12
->vm_exit_intr_info
= exit_intr_info
;
8499 if ((vmcs12
->vm_exit_intr_info
&
8500 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
)) ==
8501 (INTR_INFO_VALID_MASK
| INTR_INFO_DELIVER_CODE_MASK
))
8502 vmcs12
->vm_exit_intr_error_code
=
8503 vmcs_read32(VM_EXIT_INTR_ERROR_CODE
);
8504 vmcs12
->idt_vectoring_info_field
= 0;
8505 vmcs12
->vm_exit_instruction_len
= vmcs_read32(VM_EXIT_INSTRUCTION_LEN
);
8506 vmcs12
->vmx_instruction_info
= vmcs_read32(VMX_INSTRUCTION_INFO
);
8508 if (!(vmcs12
->vm_exit_reason
& VMX_EXIT_REASONS_FAILED_VMENTRY
)) {
8509 /* vm_entry_intr_info_field is cleared on exit. Emulate this
8510 * instead of reading the real value. */
8511 vmcs12
->vm_entry_intr_info_field
&= ~INTR_INFO_VALID_MASK
;
8514 * Transfer the event that L0 or L1 may wanted to inject into
8515 * L2 to IDT_VECTORING_INFO_FIELD.
8517 vmcs12_save_pending_event(vcpu
, vmcs12
);
8521 * Drop what we picked up for L2 via vmx_complete_interrupts. It is
8522 * preserved above and would only end up incorrectly in L1.
8524 vcpu
->arch
.nmi_injected
= false;
8525 kvm_clear_exception_queue(vcpu
);
8526 kvm_clear_interrupt_queue(vcpu
);
8530 * A part of what we need to when the nested L2 guest exits and we want to
8531 * run its L1 parent, is to reset L1's guest state to the host state specified
8533 * This function is to be called not only on normal nested exit, but also on
8534 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
8535 * Failures During or After Loading Guest State").
8536 * This function should be called when the active VMCS is L1's (vmcs01).
8538 static void load_vmcs12_host_state(struct kvm_vcpu
*vcpu
,
8539 struct vmcs12
*vmcs12
)
8541 struct kvm_segment seg
;
8543 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_EFER
)
8544 vcpu
->arch
.efer
= vmcs12
->host_ia32_efer
;
8545 else if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8546 vcpu
->arch
.efer
|= (EFER_LMA
| EFER_LME
);
8548 vcpu
->arch
.efer
&= ~(EFER_LMA
| EFER_LME
);
8549 vmx_set_efer(vcpu
, vcpu
->arch
.efer
);
8551 kvm_register_write(vcpu
, VCPU_REGS_RSP
, vmcs12
->host_rsp
);
8552 kvm_register_write(vcpu
, VCPU_REGS_RIP
, vmcs12
->host_rip
);
8553 vmx_set_rflags(vcpu
, X86_EFLAGS_FIXED
);
8555 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
8556 * actually changed, because it depends on the current state of
8557 * fpu_active (which may have changed).
8558 * Note that vmx_set_cr0 refers to efer set above.
8560 vmx_set_cr0(vcpu
, vmcs12
->host_cr0
);
8562 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
8563 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
8564 * but we also need to update cr0_guest_host_mask and exception_bitmap.
8566 update_exception_bitmap(vcpu
);
8567 vcpu
->arch
.cr0_guest_owned_bits
= (vcpu
->fpu_active
? X86_CR0_TS
: 0);
8568 vmcs_writel(CR0_GUEST_HOST_MASK
, ~vcpu
->arch
.cr0_guest_owned_bits
);
8571 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
8572 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
8574 vcpu
->arch
.cr4_guest_owned_bits
= ~vmcs_readl(CR4_GUEST_HOST_MASK
);
8575 kvm_set_cr4(vcpu
, vmcs12
->host_cr4
);
8577 nested_ept_uninit_mmu_context(vcpu
);
8579 kvm_set_cr3(vcpu
, vmcs12
->host_cr3
);
8580 kvm_mmu_reset_context(vcpu
);
8583 vcpu
->arch
.walk_mmu
->inject_page_fault
= kvm_inject_page_fault
;
8587 * Trivially support vpid by letting L2s share their parent
8588 * L1's vpid. TODO: move to a more elaborate solution, giving
8589 * each L2 its own vpid and exposing the vpid feature to L1.
8591 vmx_flush_tlb(vcpu
);
8595 vmcs_write32(GUEST_SYSENTER_CS
, vmcs12
->host_ia32_sysenter_cs
);
8596 vmcs_writel(GUEST_SYSENTER_ESP
, vmcs12
->host_ia32_sysenter_esp
);
8597 vmcs_writel(GUEST_SYSENTER_EIP
, vmcs12
->host_ia32_sysenter_eip
);
8598 vmcs_writel(GUEST_IDTR_BASE
, vmcs12
->host_idtr_base
);
8599 vmcs_writel(GUEST_GDTR_BASE
, vmcs12
->host_gdtr_base
);
8601 /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1. */
8602 if (vmcs12
->vm_exit_controls
& VM_EXIT_CLEAR_BNDCFGS
)
8603 vmcs_write64(GUEST_BNDCFGS
, 0);
8605 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PAT
) {
8606 vmcs_write64(GUEST_IA32_PAT
, vmcs12
->host_ia32_pat
);
8607 vcpu
->arch
.pat
= vmcs12
->host_ia32_pat
;
8609 if (vmcs12
->vm_exit_controls
& VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL
)
8610 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL
,
8611 vmcs12
->host_ia32_perf_global_ctrl
);
8613 /* Set L1 segment info according to Intel SDM
8614 27.5.2 Loading Host Segment and Descriptor-Table Registers */
8615 seg
= (struct kvm_segment
) {
8617 .limit
= 0xFFFFFFFF,
8618 .selector
= vmcs12
->host_cs_selector
,
8624 if (vmcs12
->vm_exit_controls
& VM_EXIT_HOST_ADDR_SPACE_SIZE
)
8628 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_CS
);
8629 seg
= (struct kvm_segment
) {
8631 .limit
= 0xFFFFFFFF,
8638 seg
.selector
= vmcs12
->host_ds_selector
;
8639 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_DS
);
8640 seg
.selector
= vmcs12
->host_es_selector
;
8641 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_ES
);
8642 seg
.selector
= vmcs12
->host_ss_selector
;
8643 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_SS
);
8644 seg
.selector
= vmcs12
->host_fs_selector
;
8645 seg
.base
= vmcs12
->host_fs_base
;
8646 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_FS
);
8647 seg
.selector
= vmcs12
->host_gs_selector
;
8648 seg
.base
= vmcs12
->host_gs_base
;
8649 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_GS
);
8650 seg
= (struct kvm_segment
) {
8651 .base
= vmcs12
->host_tr_base
,
8653 .selector
= vmcs12
->host_tr_selector
,
8657 vmx_set_segment(vcpu
, &seg
, VCPU_SREG_TR
);
8659 kvm_set_dr(vcpu
, 7, 0x400);
8660 vmcs_write64(GUEST_IA32_DEBUGCTL
, 0);
8664 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
8665 * and modify vmcs12 to make it see what it would expect to see there if
8666 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
8668 static void nested_vmx_vmexit(struct kvm_vcpu
*vcpu
, u32 exit_reason
,
8670 unsigned long exit_qualification
)
8672 struct vcpu_vmx
*vmx
= to_vmx(vcpu
);
8674 struct vmcs12
*vmcs12
= get_vmcs12(vcpu
);
8676 /* trying to cancel vmlaunch/vmresume is a bug */
8677 WARN_ON_ONCE(vmx
->nested
.nested_run_pending
);
8679 leave_guest_mode(vcpu
);
8680 prepare_vmcs12(vcpu
, vmcs12
, exit_reason
, exit_intr_info
,
8681 exit_qualification
);
8683 if ((exit_reason
== EXIT_REASON_EXTERNAL_INTERRUPT
)
8684 && nested_exit_intr_ack_set(vcpu
)) {
8685 int irq
= kvm_cpu_get_interrupt(vcpu
);
8687 vmcs12
->vm_exit_intr_info
= irq
|
8688 INTR_INFO_VALID_MASK
| INTR_TYPE_EXT_INTR
;
8691 trace_kvm_nested_vmexit_inject(vmcs12
->vm_exit_reason
,
8692 vmcs12
->exit_qualification
,
8693 vmcs12
->idt_vectoring_info_field
,
8694 vmcs12
->vm_exit_intr_info
,
8695 vmcs12
->vm_exit_intr_error_code
,
8699 vmx
->loaded_vmcs
= &vmx
->vmcs01
;
8701 vmx_vcpu_load(vcpu
, cpu
);
8705 vm_entry_controls_init(vmx
, vmcs_read32(VM_ENTRY_CONTROLS
));
8706 vm_exit_controls_init(vmx
, vmcs_read32(VM_EXIT_CONTROLS
));
8707 vmx_segment_cache_clear(vmx
);
8709 /* if no vmcs02 cache requested, remove the one we used */
8710 if (VMCS02_POOL_SIZE
== 0)
8711 nested_free_vmcs02(vmx
, vmx
->nested
.current_vmptr
);
8713 load_vmcs12_host_state(vcpu
, vmcs12
);
8715 /* Update TSC_OFFSET if TSC was changed while L2 ran */
8716 vmcs_write64(TSC_OFFSET
, vmx
->nested
.vmcs01_tsc_offset
);
8718 /* This is needed for same reason as it was needed in prepare_vmcs02 */
8721 /* Unpin physical memory we referred to in vmcs02 */
8722 if (vmx
->nested
.apic_access_page
) {
8723 nested_release_page(vmx
->nested
.apic_access_page
);
8724 vmx
->nested
.apic_access_page
= 0;
8728 * Exiting from L2 to L1, we're now back to L1 which thinks it just
8729 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
8730 * success or failure flag accordingly.
8732 if (unlikely(vmx
->fail
)) {
8734 nested_vmx_failValid(vcpu
, vmcs_read32(VM_INSTRUCTION_ERROR
));
8736 nested_vmx_succeed(vcpu
);
8737 if (enable_shadow_vmcs
)
8738 vmx
->nested
.sync_shadow_vmcs
= true;
8740 /* in case we halted in L2 */
8741 vcpu
->arch
.mp_state
= KVM_MP_STATE_RUNNABLE
;
8745 * Forcibly leave nested mode in order to be able to reset the VCPU later on.
8747 static void vmx_leave_nested(struct kvm_vcpu
*vcpu
)
8749 if (is_guest_mode(vcpu
))
8750 nested_vmx_vmexit(vcpu
, -1, 0, 0);
8751 free_nested(to_vmx(vcpu
));
8755 * L1's failure to enter L2 is a subset of a normal exit, as explained in
8756 * 23.7 "VM-entry failures during or after loading guest state" (this also
8757 * lists the acceptable exit-reason and exit-qualification parameters).
8758 * It should only be called before L2 actually succeeded to run, and when
8759 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
8761 static void nested_vmx_entry_failure(struct kvm_vcpu
*vcpu
,
8762 struct vmcs12
*vmcs12
,
8763 u32 reason
, unsigned long qualification
)
8765 load_vmcs12_host_state(vcpu
, vmcs12
);
8766 vmcs12
->vm_exit_reason
= reason
| VMX_EXIT_REASONS_FAILED_VMENTRY
;
8767 vmcs12
->exit_qualification
= qualification
;
8768 nested_vmx_succeed(vcpu
);
8769 if (enable_shadow_vmcs
)
8770 to_vmx(vcpu
)->nested
.sync_shadow_vmcs
= true;
8773 static int vmx_check_intercept(struct kvm_vcpu
*vcpu
,
8774 struct x86_instruction_info
*info
,
8775 enum x86_intercept_stage stage
)
8777 return X86EMUL_CONTINUE
;
8780 static struct kvm_x86_ops vmx_x86_ops
= {
8781 .cpu_has_kvm_support
= cpu_has_kvm_support
,
8782 .disabled_by_bios
= vmx_disabled_by_bios
,
8783 .hardware_setup
= hardware_setup
,
8784 .hardware_unsetup
= hardware_unsetup
,
8785 .check_processor_compatibility
= vmx_check_processor_compat
,
8786 .hardware_enable
= hardware_enable
,
8787 .hardware_disable
= hardware_disable
,
8788 .cpu_has_accelerated_tpr
= report_flexpriority
,
8790 .vcpu_create
= vmx_create_vcpu
,
8791 .vcpu_free
= vmx_free_vcpu
,
8792 .vcpu_reset
= vmx_vcpu_reset
,
8794 .prepare_guest_switch
= vmx_save_host_state
,
8795 .vcpu_load
= vmx_vcpu_load
,
8796 .vcpu_put
= vmx_vcpu_put
,
8798 .update_db_bp_intercept
= update_exception_bitmap
,
8799 .get_msr
= vmx_get_msr
,
8800 .set_msr
= vmx_set_msr
,
8801 .get_segment_base
= vmx_get_segment_base
,
8802 .get_segment
= vmx_get_segment
,
8803 .set_segment
= vmx_set_segment
,
8804 .get_cpl
= vmx_get_cpl
,
8805 .get_cs_db_l_bits
= vmx_get_cs_db_l_bits
,
8806 .decache_cr0_guest_bits
= vmx_decache_cr0_guest_bits
,
8807 .decache_cr3
= vmx_decache_cr3
,
8808 .decache_cr4_guest_bits
= vmx_decache_cr4_guest_bits
,
8809 .set_cr0
= vmx_set_cr0
,
8810 .set_cr3
= vmx_set_cr3
,
8811 .set_cr4
= vmx_set_cr4
,
8812 .set_efer
= vmx_set_efer
,
8813 .get_idt
= vmx_get_idt
,
8814 .set_idt
= vmx_set_idt
,
8815 .get_gdt
= vmx_get_gdt
,
8816 .set_gdt
= vmx_set_gdt
,
8817 .get_dr6
= vmx_get_dr6
,
8818 .set_dr6
= vmx_set_dr6
,
8819 .set_dr7
= vmx_set_dr7
,
8820 .sync_dirty_debug_regs
= vmx_sync_dirty_debug_regs
,
8821 .cache_reg
= vmx_cache_reg
,
8822 .get_rflags
= vmx_get_rflags
,
8823 .set_rflags
= vmx_set_rflags
,
8824 .fpu_activate
= vmx_fpu_activate
,
8825 .fpu_deactivate
= vmx_fpu_deactivate
,
8827 .tlb_flush
= vmx_flush_tlb
,
8829 .run
= vmx_vcpu_run
,
8830 .handle_exit
= vmx_handle_exit
,
8831 .skip_emulated_instruction
= skip_emulated_instruction
,
8832 .set_interrupt_shadow
= vmx_set_interrupt_shadow
,
8833 .get_interrupt_shadow
= vmx_get_interrupt_shadow
,
8834 .patch_hypercall
= vmx_patch_hypercall
,
8835 .set_irq
= vmx_inject_irq
,
8836 .set_nmi
= vmx_inject_nmi
,
8837 .queue_exception
= vmx_queue_exception
,
8838 .cancel_injection
= vmx_cancel_injection
,
8839 .interrupt_allowed
= vmx_interrupt_allowed
,
8840 .nmi_allowed
= vmx_nmi_allowed
,
8841 .get_nmi_mask
= vmx_get_nmi_mask
,
8842 .set_nmi_mask
= vmx_set_nmi_mask
,
8843 .enable_nmi_window
= enable_nmi_window
,
8844 .enable_irq_window
= enable_irq_window
,
8845 .update_cr8_intercept
= update_cr8_intercept
,
8846 .set_virtual_x2apic_mode
= vmx_set_virtual_x2apic_mode
,
8847 .vm_has_apicv
= vmx_vm_has_apicv
,
8848 .load_eoi_exitmap
= vmx_load_eoi_exitmap
,
8849 .hwapic_irr_update
= vmx_hwapic_irr_update
,
8850 .hwapic_isr_update
= vmx_hwapic_isr_update
,
8851 .sync_pir_to_irr
= vmx_sync_pir_to_irr
,
8852 .deliver_posted_interrupt
= vmx_deliver_posted_interrupt
,
8854 .set_tss_addr
= vmx_set_tss_addr
,
8855 .get_tdp_level
= get_ept_level
,
8856 .get_mt_mask
= vmx_get_mt_mask
,
8858 .get_exit_info
= vmx_get_exit_info
,
8860 .get_lpage_level
= vmx_get_lpage_level
,
8862 .cpuid_update
= vmx_cpuid_update
,
8864 .rdtscp_supported
= vmx_rdtscp_supported
,
8865 .invpcid_supported
= vmx_invpcid_supported
,
8867 .set_supported_cpuid
= vmx_set_supported_cpuid
,
8869 .has_wbinvd_exit
= cpu_has_vmx_wbinvd_exit
,
8871 .set_tsc_khz
= vmx_set_tsc_khz
,
8872 .read_tsc_offset
= vmx_read_tsc_offset
,
8873 .write_tsc_offset
= vmx_write_tsc_offset
,
8874 .adjust_tsc_offset
= vmx_adjust_tsc_offset
,
8875 .compute_tsc_offset
= vmx_compute_tsc_offset
,
8876 .read_l1_tsc
= vmx_read_l1_tsc
,
8878 .set_tdp_cr3
= vmx_set_cr3
,
8880 .check_intercept
= vmx_check_intercept
,
8881 .handle_external_intr
= vmx_handle_external_intr
,
8882 .mpx_supported
= vmx_mpx_supported
,
8884 .check_nested_events
= vmx_check_nested_events
,
8887 static int __init
vmx_init(void)
8891 rdmsrl_safe(MSR_EFER
, &host_efer
);
8893 for (i
= 0; i
< NR_VMX_MSR
; ++i
)
8894 kvm_define_shared_msr(i
, vmx_msr_index
[i
]);
8896 vmx_io_bitmap_a
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8897 if (!vmx_io_bitmap_a
)
8902 vmx_io_bitmap_b
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8903 if (!vmx_io_bitmap_b
)
8906 vmx_msr_bitmap_legacy
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8907 if (!vmx_msr_bitmap_legacy
)
8910 vmx_msr_bitmap_legacy_x2apic
=
8911 (unsigned long *)__get_free_page(GFP_KERNEL
);
8912 if (!vmx_msr_bitmap_legacy_x2apic
)
8915 vmx_msr_bitmap_longmode
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8916 if (!vmx_msr_bitmap_longmode
)
8919 vmx_msr_bitmap_longmode_x2apic
=
8920 (unsigned long *)__get_free_page(GFP_KERNEL
);
8921 if (!vmx_msr_bitmap_longmode_x2apic
)
8923 vmx_vmread_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8924 if (!vmx_vmread_bitmap
)
8927 vmx_vmwrite_bitmap
= (unsigned long *)__get_free_page(GFP_KERNEL
);
8928 if (!vmx_vmwrite_bitmap
)
8931 memset(vmx_vmread_bitmap
, 0xff, PAGE_SIZE
);
8932 memset(vmx_vmwrite_bitmap
, 0xff, PAGE_SIZE
);
8935 * Allow direct access to the PC debug port (it is often used for I/O
8936 * delays, but the vmexits simply slow things down).
8938 memset(vmx_io_bitmap_a
, 0xff, PAGE_SIZE
);
8939 clear_bit(0x80, vmx_io_bitmap_a
);
8941 memset(vmx_io_bitmap_b
, 0xff, PAGE_SIZE
);
8943 memset(vmx_msr_bitmap_legacy
, 0xff, PAGE_SIZE
);
8944 memset(vmx_msr_bitmap_longmode
, 0xff, PAGE_SIZE
);
8946 set_bit(0, vmx_vpid_bitmap
); /* 0 is reserved for host */
8948 r
= kvm_init(&vmx_x86_ops
, sizeof(struct vcpu_vmx
),
8949 __alignof__(struct vcpu_vmx
), THIS_MODULE
);
8954 rcu_assign_pointer(crash_vmclear_loaded_vmcss
,
8955 crash_vmclear_local_loaded_vmcss
);
8958 vmx_disable_intercept_for_msr(MSR_FS_BASE
, false);
8959 vmx_disable_intercept_for_msr(MSR_GS_BASE
, false);
8960 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE
, true);
8961 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS
, false);
8962 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP
, false);
8963 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP
, false);
8964 vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS
, true);
8966 memcpy(vmx_msr_bitmap_legacy_x2apic
,
8967 vmx_msr_bitmap_legacy
, PAGE_SIZE
);
8968 memcpy(vmx_msr_bitmap_longmode_x2apic
,
8969 vmx_msr_bitmap_longmode
, PAGE_SIZE
);
8972 for (msr
= 0x800; msr
<= 0x8ff; msr
++)
8973 vmx_disable_intercept_msr_read_x2apic(msr
);
8975 /* According SDM, in x2apic mode, the whole id reg is used.
8976 * But in KVM, it only use the highest eight bits. Need to
8978 vmx_enable_intercept_msr_read_x2apic(0x802);
8980 vmx_enable_intercept_msr_read_x2apic(0x839);
8982 vmx_disable_intercept_msr_write_x2apic(0x808);
8984 vmx_disable_intercept_msr_write_x2apic(0x80b);
8986 vmx_disable_intercept_msr_write_x2apic(0x83f);
8990 kvm_mmu_set_mask_ptes(0ull,
8991 (enable_ept_ad_bits
) ? VMX_EPT_ACCESS_BIT
: 0ull,
8992 (enable_ept_ad_bits
) ? VMX_EPT_DIRTY_BIT
: 0ull,
8993 0ull, VMX_EPT_EXECUTABLE_MASK
);
8994 ept_set_mmio_spte_mask();
9002 free_page((unsigned long)vmx_vmwrite_bitmap
);
9004 free_page((unsigned long)vmx_vmread_bitmap
);
9006 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9008 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9010 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9012 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9014 free_page((unsigned long)vmx_io_bitmap_b
);
9016 free_page((unsigned long)vmx_io_bitmap_a
);
9020 static void __exit
vmx_exit(void)
9022 free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic
);
9023 free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic
);
9024 free_page((unsigned long)vmx_msr_bitmap_legacy
);
9025 free_page((unsigned long)vmx_msr_bitmap_longmode
);
9026 free_page((unsigned long)vmx_io_bitmap_b
);
9027 free_page((unsigned long)vmx_io_bitmap_a
);
9028 free_page((unsigned long)vmx_vmwrite_bitmap
);
9029 free_page((unsigned long)vmx_vmread_bitmap
);
9032 rcu_assign_pointer(crash_vmclear_loaded_vmcss
, NULL
);
9039 module_init(vmx_init
)
9040 module_exit(vmx_exit
)