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KVM: VMX: remove unneeded vmx_load_host_state() calls.
[mirror_ubuntu-artful-kernel.git] / arch / x86 / kvm / vmx.c
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
19 #include "irq.h"
20 #include "mmu.h"
21
22 #include <linux/kvm_host.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/mm.h>
26 #include <linux/highmem.h>
27 #include <linux/sched.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31 #include <linux/tboot.h>
32 #include "kvm_cache_regs.h"
33 #include "x86.h"
34
35 #include <asm/io.h>
36 #include <asm/desc.h>
37 #include <asm/vmx.h>
38 #include <asm/virtext.h>
39 #include <asm/mce.h>
40 #include <asm/i387.h>
41 #include <asm/xcr.h>
42 #include <asm/perf_event.h>
43
44 #include "trace.h"
45
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 #define __ex_clear(x, reg) \
48 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
49
50 MODULE_AUTHOR("Qumranet");
51 MODULE_LICENSE("GPL");
52
53 static int __read_mostly enable_vpid = 1;
54 module_param_named(vpid, enable_vpid, bool, 0444);
55
56 static int __read_mostly flexpriority_enabled = 1;
57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
58
59 static int __read_mostly enable_ept = 1;
60 module_param_named(ept, enable_ept, bool, S_IRUGO);
61
62 static int __read_mostly enable_unrestricted_guest = 1;
63 module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
66 static int __read_mostly emulate_invalid_guest_state = 0;
67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
68
69 static int __read_mostly vmm_exclusive = 1;
70 module_param(vmm_exclusive, bool, S_IRUGO);
71
72 static int __read_mostly yield_on_hlt = 1;
73 module_param(yield_on_hlt, bool, S_IRUGO);
74
75 static int __read_mostly fasteoi = 1;
76 module_param(fasteoi, bool, S_IRUGO);
77
78 /*
79 * If nested=1, nested virtualization is supported, i.e., guests may use
80 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
81 * use VMX instructions.
82 */
83 static int __read_mostly nested = 0;
84 module_param(nested, bool, S_IRUGO);
85
86 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
87 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
88 #define KVM_GUEST_CR0_MASK \
89 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
90 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
91 (X86_CR0_WP | X86_CR0_NE)
92 #define KVM_VM_CR0_ALWAYS_ON \
93 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
94 #define KVM_CR4_GUEST_OWNED_BITS \
95 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
96 | X86_CR4_OSXMMEXCPT)
97
98 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
99 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
100
101 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
102
103 /*
104 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
105 * ple_gap: upper bound on the amount of time between two successive
106 * executions of PAUSE in a loop. Also indicate if ple enabled.
107 * According to test, this time is usually smaller than 128 cycles.
108 * ple_window: upper bound on the amount of time a guest is allowed to execute
109 * in a PAUSE loop. Tests indicate that most spinlocks are held for
110 * less than 2^12 cycles
111 * Time is measured based on a counter that runs at the same rate as the TSC,
112 * refer SDM volume 3b section 21.6.13 & 22.1.3.
113 */
114 #define KVM_VMX_DEFAULT_PLE_GAP 128
115 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
116 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
117 module_param(ple_gap, int, S_IRUGO);
118
119 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
120 module_param(ple_window, int, S_IRUGO);
121
122 #define NR_AUTOLOAD_MSRS 8
123 #define VMCS02_POOL_SIZE 1
124
125 struct vmcs {
126 u32 revision_id;
127 u32 abort;
128 char data[0];
129 };
130
131 /*
132 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
133 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
134 * loaded on this CPU (so we can clear them if the CPU goes down).
135 */
136 struct loaded_vmcs {
137 struct vmcs *vmcs;
138 int cpu;
139 int launched;
140 struct list_head loaded_vmcss_on_cpu_link;
141 };
142
143 struct shared_msr_entry {
144 unsigned index;
145 u64 data;
146 u64 mask;
147 };
148
149 /*
150 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
151 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
152 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
153 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
154 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
155 * More than one of these structures may exist, if L1 runs multiple L2 guests.
156 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
157 * underlying hardware which will be used to run L2.
158 * This structure is packed to ensure that its layout is identical across
159 * machines (necessary for live migration).
160 * If there are changes in this struct, VMCS12_REVISION must be changed.
161 */
162 typedef u64 natural_width;
163 struct __packed vmcs12 {
164 /* According to the Intel spec, a VMCS region must start with the
165 * following two fields. Then follow implementation-specific data.
166 */
167 u32 revision_id;
168 u32 abort;
169
170 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
171 u32 padding[7]; /* room for future expansion */
172
173 u64 io_bitmap_a;
174 u64 io_bitmap_b;
175 u64 msr_bitmap;
176 u64 vm_exit_msr_store_addr;
177 u64 vm_exit_msr_load_addr;
178 u64 vm_entry_msr_load_addr;
179 u64 tsc_offset;
180 u64 virtual_apic_page_addr;
181 u64 apic_access_addr;
182 u64 ept_pointer;
183 u64 guest_physical_address;
184 u64 vmcs_link_pointer;
185 u64 guest_ia32_debugctl;
186 u64 guest_ia32_pat;
187 u64 guest_ia32_efer;
188 u64 guest_ia32_perf_global_ctrl;
189 u64 guest_pdptr0;
190 u64 guest_pdptr1;
191 u64 guest_pdptr2;
192 u64 guest_pdptr3;
193 u64 host_ia32_pat;
194 u64 host_ia32_efer;
195 u64 host_ia32_perf_global_ctrl;
196 u64 padding64[8]; /* room for future expansion */
197 /*
198 * To allow migration of L1 (complete with its L2 guests) between
199 * machines of different natural widths (32 or 64 bit), we cannot have
200 * unsigned long fields with no explict size. We use u64 (aliased
201 * natural_width) instead. Luckily, x86 is little-endian.
202 */
203 natural_width cr0_guest_host_mask;
204 natural_width cr4_guest_host_mask;
205 natural_width cr0_read_shadow;
206 natural_width cr4_read_shadow;
207 natural_width cr3_target_value0;
208 natural_width cr3_target_value1;
209 natural_width cr3_target_value2;
210 natural_width cr3_target_value3;
211 natural_width exit_qualification;
212 natural_width guest_linear_address;
213 natural_width guest_cr0;
214 natural_width guest_cr3;
215 natural_width guest_cr4;
216 natural_width guest_es_base;
217 natural_width guest_cs_base;
218 natural_width guest_ss_base;
219 natural_width guest_ds_base;
220 natural_width guest_fs_base;
221 natural_width guest_gs_base;
222 natural_width guest_ldtr_base;
223 natural_width guest_tr_base;
224 natural_width guest_gdtr_base;
225 natural_width guest_idtr_base;
226 natural_width guest_dr7;
227 natural_width guest_rsp;
228 natural_width guest_rip;
229 natural_width guest_rflags;
230 natural_width guest_pending_dbg_exceptions;
231 natural_width guest_sysenter_esp;
232 natural_width guest_sysenter_eip;
233 natural_width host_cr0;
234 natural_width host_cr3;
235 natural_width host_cr4;
236 natural_width host_fs_base;
237 natural_width host_gs_base;
238 natural_width host_tr_base;
239 natural_width host_gdtr_base;
240 natural_width host_idtr_base;
241 natural_width host_ia32_sysenter_esp;
242 natural_width host_ia32_sysenter_eip;
243 natural_width host_rsp;
244 natural_width host_rip;
245 natural_width paddingl[8]; /* room for future expansion */
246 u32 pin_based_vm_exec_control;
247 u32 cpu_based_vm_exec_control;
248 u32 exception_bitmap;
249 u32 page_fault_error_code_mask;
250 u32 page_fault_error_code_match;
251 u32 cr3_target_count;
252 u32 vm_exit_controls;
253 u32 vm_exit_msr_store_count;
254 u32 vm_exit_msr_load_count;
255 u32 vm_entry_controls;
256 u32 vm_entry_msr_load_count;
257 u32 vm_entry_intr_info_field;
258 u32 vm_entry_exception_error_code;
259 u32 vm_entry_instruction_len;
260 u32 tpr_threshold;
261 u32 secondary_vm_exec_control;
262 u32 vm_instruction_error;
263 u32 vm_exit_reason;
264 u32 vm_exit_intr_info;
265 u32 vm_exit_intr_error_code;
266 u32 idt_vectoring_info_field;
267 u32 idt_vectoring_error_code;
268 u32 vm_exit_instruction_len;
269 u32 vmx_instruction_info;
270 u32 guest_es_limit;
271 u32 guest_cs_limit;
272 u32 guest_ss_limit;
273 u32 guest_ds_limit;
274 u32 guest_fs_limit;
275 u32 guest_gs_limit;
276 u32 guest_ldtr_limit;
277 u32 guest_tr_limit;
278 u32 guest_gdtr_limit;
279 u32 guest_idtr_limit;
280 u32 guest_es_ar_bytes;
281 u32 guest_cs_ar_bytes;
282 u32 guest_ss_ar_bytes;
283 u32 guest_ds_ar_bytes;
284 u32 guest_fs_ar_bytes;
285 u32 guest_gs_ar_bytes;
286 u32 guest_ldtr_ar_bytes;
287 u32 guest_tr_ar_bytes;
288 u32 guest_interruptibility_info;
289 u32 guest_activity_state;
290 u32 guest_sysenter_cs;
291 u32 host_ia32_sysenter_cs;
292 u32 padding32[8]; /* room for future expansion */
293 u16 virtual_processor_id;
294 u16 guest_es_selector;
295 u16 guest_cs_selector;
296 u16 guest_ss_selector;
297 u16 guest_ds_selector;
298 u16 guest_fs_selector;
299 u16 guest_gs_selector;
300 u16 guest_ldtr_selector;
301 u16 guest_tr_selector;
302 u16 host_es_selector;
303 u16 host_cs_selector;
304 u16 host_ss_selector;
305 u16 host_ds_selector;
306 u16 host_fs_selector;
307 u16 host_gs_selector;
308 u16 host_tr_selector;
309 };
310
311 /*
312 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
313 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
314 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
315 */
316 #define VMCS12_REVISION 0x11e57ed0
317
318 /*
319 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
320 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
321 * current implementation, 4K are reserved to avoid future complications.
322 */
323 #define VMCS12_SIZE 0x1000
324
325 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
326 struct vmcs02_list {
327 struct list_head list;
328 gpa_t vmptr;
329 struct loaded_vmcs vmcs02;
330 };
331
332 /*
333 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
334 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
335 */
336 struct nested_vmx {
337 /* Has the level1 guest done vmxon? */
338 bool vmxon;
339
340 /* The guest-physical address of the current VMCS L1 keeps for L2 */
341 gpa_t current_vmptr;
342 /* The host-usable pointer to the above */
343 struct page *current_vmcs12_page;
344 struct vmcs12 *current_vmcs12;
345
346 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
347 struct list_head vmcs02_pool;
348 int vmcs02_num;
349 u64 vmcs01_tsc_offset;
350 /* L2 must run next, and mustn't decide to exit to L1. */
351 bool nested_run_pending;
352 /*
353 * Guest pages referred to in vmcs02 with host-physical pointers, so
354 * we must keep them pinned while L2 runs.
355 */
356 struct page *apic_access_page;
357 };
358
359 struct vcpu_vmx {
360 struct kvm_vcpu vcpu;
361 unsigned long host_rsp;
362 u8 fail;
363 u8 cpl;
364 bool nmi_known_unmasked;
365 u32 exit_intr_info;
366 u32 idt_vectoring_info;
367 ulong rflags;
368 struct shared_msr_entry *guest_msrs;
369 int nmsrs;
370 int save_nmsrs;
371 #ifdef CONFIG_X86_64
372 u64 msr_host_kernel_gs_base;
373 u64 msr_guest_kernel_gs_base;
374 #endif
375 /*
376 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
377 * non-nested (L1) guest, it always points to vmcs01. For a nested
378 * guest (L2), it points to a different VMCS.
379 */
380 struct loaded_vmcs vmcs01;
381 struct loaded_vmcs *loaded_vmcs;
382 bool __launched; /* temporary, used in vmx_vcpu_run */
383 struct msr_autoload {
384 unsigned nr;
385 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
386 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
387 } msr_autoload;
388 struct {
389 int loaded;
390 u16 fs_sel, gs_sel, ldt_sel;
391 int gs_ldt_reload_needed;
392 int fs_reload_needed;
393 } host_state;
394 struct {
395 int vm86_active;
396 ulong save_rflags;
397 struct kvm_save_segment {
398 u16 selector;
399 unsigned long base;
400 u32 limit;
401 u32 ar;
402 } tr, es, ds, fs, gs;
403 } rmode;
404 struct {
405 u32 bitmask; /* 4 bits per segment (1 bit per field) */
406 struct kvm_save_segment seg[8];
407 } segment_cache;
408 int vpid;
409 bool emulation_required;
410
411 /* Support for vnmi-less CPUs */
412 int soft_vnmi_blocked;
413 ktime_t entry_time;
414 s64 vnmi_blocked_time;
415 u32 exit_reason;
416
417 bool rdtscp_enabled;
418
419 /* Support for a guest hypervisor (nested VMX) */
420 struct nested_vmx nested;
421 };
422
423 enum segment_cache_field {
424 SEG_FIELD_SEL = 0,
425 SEG_FIELD_BASE = 1,
426 SEG_FIELD_LIMIT = 2,
427 SEG_FIELD_AR = 3,
428
429 SEG_FIELD_NR = 4
430 };
431
432 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
433 {
434 return container_of(vcpu, struct vcpu_vmx, vcpu);
435 }
436
437 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
438 #define FIELD(number, name) [number] = VMCS12_OFFSET(name)
439 #define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
440 [number##_HIGH] = VMCS12_OFFSET(name)+4
441
442 static unsigned short vmcs_field_to_offset_table[] = {
443 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
444 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
445 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
446 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
447 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
448 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
449 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
450 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
451 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
452 FIELD(HOST_ES_SELECTOR, host_es_selector),
453 FIELD(HOST_CS_SELECTOR, host_cs_selector),
454 FIELD(HOST_SS_SELECTOR, host_ss_selector),
455 FIELD(HOST_DS_SELECTOR, host_ds_selector),
456 FIELD(HOST_FS_SELECTOR, host_fs_selector),
457 FIELD(HOST_GS_SELECTOR, host_gs_selector),
458 FIELD(HOST_TR_SELECTOR, host_tr_selector),
459 FIELD64(IO_BITMAP_A, io_bitmap_a),
460 FIELD64(IO_BITMAP_B, io_bitmap_b),
461 FIELD64(MSR_BITMAP, msr_bitmap),
462 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
463 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
464 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
465 FIELD64(TSC_OFFSET, tsc_offset),
466 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
467 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
468 FIELD64(EPT_POINTER, ept_pointer),
469 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
470 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
471 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
472 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
473 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
474 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
475 FIELD64(GUEST_PDPTR0, guest_pdptr0),
476 FIELD64(GUEST_PDPTR1, guest_pdptr1),
477 FIELD64(GUEST_PDPTR2, guest_pdptr2),
478 FIELD64(GUEST_PDPTR3, guest_pdptr3),
479 FIELD64(HOST_IA32_PAT, host_ia32_pat),
480 FIELD64(HOST_IA32_EFER, host_ia32_efer),
481 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
482 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
483 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
484 FIELD(EXCEPTION_BITMAP, exception_bitmap),
485 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
486 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
487 FIELD(CR3_TARGET_COUNT, cr3_target_count),
488 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
489 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
490 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
491 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
492 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
493 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
494 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
495 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
496 FIELD(TPR_THRESHOLD, tpr_threshold),
497 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
498 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
499 FIELD(VM_EXIT_REASON, vm_exit_reason),
500 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
501 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
502 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
503 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
504 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
505 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
506 FIELD(GUEST_ES_LIMIT, guest_es_limit),
507 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
508 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
509 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
510 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
511 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
512 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
513 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
514 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
515 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
516 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
517 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
518 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
519 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
520 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
521 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
522 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
523 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
524 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
525 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
526 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
527 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
528 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
529 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
530 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
531 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
532 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
533 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
534 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
535 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
536 FIELD(EXIT_QUALIFICATION, exit_qualification),
537 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
538 FIELD(GUEST_CR0, guest_cr0),
539 FIELD(GUEST_CR3, guest_cr3),
540 FIELD(GUEST_CR4, guest_cr4),
541 FIELD(GUEST_ES_BASE, guest_es_base),
542 FIELD(GUEST_CS_BASE, guest_cs_base),
543 FIELD(GUEST_SS_BASE, guest_ss_base),
544 FIELD(GUEST_DS_BASE, guest_ds_base),
545 FIELD(GUEST_FS_BASE, guest_fs_base),
546 FIELD(GUEST_GS_BASE, guest_gs_base),
547 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
548 FIELD(GUEST_TR_BASE, guest_tr_base),
549 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
550 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
551 FIELD(GUEST_DR7, guest_dr7),
552 FIELD(GUEST_RSP, guest_rsp),
553 FIELD(GUEST_RIP, guest_rip),
554 FIELD(GUEST_RFLAGS, guest_rflags),
555 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
556 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
557 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
558 FIELD(HOST_CR0, host_cr0),
559 FIELD(HOST_CR3, host_cr3),
560 FIELD(HOST_CR4, host_cr4),
561 FIELD(HOST_FS_BASE, host_fs_base),
562 FIELD(HOST_GS_BASE, host_gs_base),
563 FIELD(HOST_TR_BASE, host_tr_base),
564 FIELD(HOST_GDTR_BASE, host_gdtr_base),
565 FIELD(HOST_IDTR_BASE, host_idtr_base),
566 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
567 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
568 FIELD(HOST_RSP, host_rsp),
569 FIELD(HOST_RIP, host_rip),
570 };
571 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
572
573 static inline short vmcs_field_to_offset(unsigned long field)
574 {
575 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
576 return -1;
577 return vmcs_field_to_offset_table[field];
578 }
579
580 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
581 {
582 return to_vmx(vcpu)->nested.current_vmcs12;
583 }
584
585 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
586 {
587 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
588 if (is_error_page(page)) {
589 kvm_release_page_clean(page);
590 return NULL;
591 }
592 return page;
593 }
594
595 static void nested_release_page(struct page *page)
596 {
597 kvm_release_page_dirty(page);
598 }
599
600 static void nested_release_page_clean(struct page *page)
601 {
602 kvm_release_page_clean(page);
603 }
604
605 static u64 construct_eptp(unsigned long root_hpa);
606 static void kvm_cpu_vmxon(u64 addr);
607 static void kvm_cpu_vmxoff(void);
608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
609 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
610
611 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
612 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
613 /*
614 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
615 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
616 */
617 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
618 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
619
620 static unsigned long *vmx_io_bitmap_a;
621 static unsigned long *vmx_io_bitmap_b;
622 static unsigned long *vmx_msr_bitmap_legacy;
623 static unsigned long *vmx_msr_bitmap_longmode;
624
625 static bool cpu_has_load_ia32_efer;
626 static bool cpu_has_load_perf_global_ctrl;
627
628 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
629 static DEFINE_SPINLOCK(vmx_vpid_lock);
630
631 static struct vmcs_config {
632 int size;
633 int order;
634 u32 revision_id;
635 u32 pin_based_exec_ctrl;
636 u32 cpu_based_exec_ctrl;
637 u32 cpu_based_2nd_exec_ctrl;
638 u32 vmexit_ctrl;
639 u32 vmentry_ctrl;
640 } vmcs_config;
641
642 static struct vmx_capability {
643 u32 ept;
644 u32 vpid;
645 } vmx_capability;
646
647 #define VMX_SEGMENT_FIELD(seg) \
648 [VCPU_SREG_##seg] = { \
649 .selector = GUEST_##seg##_SELECTOR, \
650 .base = GUEST_##seg##_BASE, \
651 .limit = GUEST_##seg##_LIMIT, \
652 .ar_bytes = GUEST_##seg##_AR_BYTES, \
653 }
654
655 static struct kvm_vmx_segment_field {
656 unsigned selector;
657 unsigned base;
658 unsigned limit;
659 unsigned ar_bytes;
660 } kvm_vmx_segment_fields[] = {
661 VMX_SEGMENT_FIELD(CS),
662 VMX_SEGMENT_FIELD(DS),
663 VMX_SEGMENT_FIELD(ES),
664 VMX_SEGMENT_FIELD(FS),
665 VMX_SEGMENT_FIELD(GS),
666 VMX_SEGMENT_FIELD(SS),
667 VMX_SEGMENT_FIELD(TR),
668 VMX_SEGMENT_FIELD(LDTR),
669 };
670
671 static u64 host_efer;
672
673 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
674
675 /*
676 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
677 * away by decrementing the array size.
678 */
679 static const u32 vmx_msr_index[] = {
680 #ifdef CONFIG_X86_64
681 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
682 #endif
683 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
684 };
685 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
686
687 static inline bool is_page_fault(u32 intr_info)
688 {
689 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
690 INTR_INFO_VALID_MASK)) ==
691 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
692 }
693
694 static inline bool is_no_device(u32 intr_info)
695 {
696 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
697 INTR_INFO_VALID_MASK)) ==
698 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
699 }
700
701 static inline bool is_invalid_opcode(u32 intr_info)
702 {
703 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
704 INTR_INFO_VALID_MASK)) ==
705 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
706 }
707
708 static inline bool is_external_interrupt(u32 intr_info)
709 {
710 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
711 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
712 }
713
714 static inline bool is_machine_check(u32 intr_info)
715 {
716 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
717 INTR_INFO_VALID_MASK)) ==
718 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
719 }
720
721 static inline bool cpu_has_vmx_msr_bitmap(void)
722 {
723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
724 }
725
726 static inline bool cpu_has_vmx_tpr_shadow(void)
727 {
728 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
729 }
730
731 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
732 {
733 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
734 }
735
736 static inline bool cpu_has_secondary_exec_ctrls(void)
737 {
738 return vmcs_config.cpu_based_exec_ctrl &
739 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
740 }
741
742 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
743 {
744 return vmcs_config.cpu_based_2nd_exec_ctrl &
745 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
746 }
747
748 static inline bool cpu_has_vmx_flexpriority(void)
749 {
750 return cpu_has_vmx_tpr_shadow() &&
751 cpu_has_vmx_virtualize_apic_accesses();
752 }
753
754 static inline bool cpu_has_vmx_ept_execute_only(void)
755 {
756 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
757 }
758
759 static inline bool cpu_has_vmx_eptp_uncacheable(void)
760 {
761 return vmx_capability.ept & VMX_EPTP_UC_BIT;
762 }
763
764 static inline bool cpu_has_vmx_eptp_writeback(void)
765 {
766 return vmx_capability.ept & VMX_EPTP_WB_BIT;
767 }
768
769 static inline bool cpu_has_vmx_ept_2m_page(void)
770 {
771 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
772 }
773
774 static inline bool cpu_has_vmx_ept_1g_page(void)
775 {
776 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
777 }
778
779 static inline bool cpu_has_vmx_ept_4levels(void)
780 {
781 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
782 }
783
784 static inline bool cpu_has_vmx_invept_individual_addr(void)
785 {
786 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
787 }
788
789 static inline bool cpu_has_vmx_invept_context(void)
790 {
791 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
792 }
793
794 static inline bool cpu_has_vmx_invept_global(void)
795 {
796 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
797 }
798
799 static inline bool cpu_has_vmx_invvpid_single(void)
800 {
801 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
802 }
803
804 static inline bool cpu_has_vmx_invvpid_global(void)
805 {
806 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
807 }
808
809 static inline bool cpu_has_vmx_ept(void)
810 {
811 return vmcs_config.cpu_based_2nd_exec_ctrl &
812 SECONDARY_EXEC_ENABLE_EPT;
813 }
814
815 static inline bool cpu_has_vmx_unrestricted_guest(void)
816 {
817 return vmcs_config.cpu_based_2nd_exec_ctrl &
818 SECONDARY_EXEC_UNRESTRICTED_GUEST;
819 }
820
821 static inline bool cpu_has_vmx_ple(void)
822 {
823 return vmcs_config.cpu_based_2nd_exec_ctrl &
824 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
825 }
826
827 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
828 {
829 return flexpriority_enabled && irqchip_in_kernel(kvm);
830 }
831
832 static inline bool cpu_has_vmx_vpid(void)
833 {
834 return vmcs_config.cpu_based_2nd_exec_ctrl &
835 SECONDARY_EXEC_ENABLE_VPID;
836 }
837
838 static inline bool cpu_has_vmx_rdtscp(void)
839 {
840 return vmcs_config.cpu_based_2nd_exec_ctrl &
841 SECONDARY_EXEC_RDTSCP;
842 }
843
844 static inline bool cpu_has_virtual_nmis(void)
845 {
846 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
847 }
848
849 static inline bool cpu_has_vmx_wbinvd_exit(void)
850 {
851 return vmcs_config.cpu_based_2nd_exec_ctrl &
852 SECONDARY_EXEC_WBINVD_EXITING;
853 }
854
855 static inline bool report_flexpriority(void)
856 {
857 return flexpriority_enabled;
858 }
859
860 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
861 {
862 return vmcs12->cpu_based_vm_exec_control & bit;
863 }
864
865 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
866 {
867 return (vmcs12->cpu_based_vm_exec_control &
868 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
869 (vmcs12->secondary_vm_exec_control & bit);
870 }
871
872 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
873 struct kvm_vcpu *vcpu)
874 {
875 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
876 }
877
878 static inline bool is_exception(u32 intr_info)
879 {
880 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
881 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
882 }
883
884 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
885 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
886 struct vmcs12 *vmcs12,
887 u32 reason, unsigned long qualification);
888
889 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
890 {
891 int i;
892
893 for (i = 0; i < vmx->nmsrs; ++i)
894 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
895 return i;
896 return -1;
897 }
898
899 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
900 {
901 struct {
902 u64 vpid : 16;
903 u64 rsvd : 48;
904 u64 gva;
905 } operand = { vpid, 0, gva };
906
907 asm volatile (__ex(ASM_VMX_INVVPID)
908 /* CF==1 or ZF==1 --> rc = -1 */
909 "; ja 1f ; ud2 ; 1:"
910 : : "a"(&operand), "c"(ext) : "cc", "memory");
911 }
912
913 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
914 {
915 struct {
916 u64 eptp, gpa;
917 } operand = {eptp, gpa};
918
919 asm volatile (__ex(ASM_VMX_INVEPT)
920 /* CF==1 or ZF==1 --> rc = -1 */
921 "; ja 1f ; ud2 ; 1:\n"
922 : : "a" (&operand), "c" (ext) : "cc", "memory");
923 }
924
925 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
926 {
927 int i;
928
929 i = __find_msr_index(vmx, msr);
930 if (i >= 0)
931 return &vmx->guest_msrs[i];
932 return NULL;
933 }
934
935 static void vmcs_clear(struct vmcs *vmcs)
936 {
937 u64 phys_addr = __pa(vmcs);
938 u8 error;
939
940 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
941 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
942 : "cc", "memory");
943 if (error)
944 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
945 vmcs, phys_addr);
946 }
947
948 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
949 {
950 vmcs_clear(loaded_vmcs->vmcs);
951 loaded_vmcs->cpu = -1;
952 loaded_vmcs->launched = 0;
953 }
954
955 static void vmcs_load(struct vmcs *vmcs)
956 {
957 u64 phys_addr = __pa(vmcs);
958 u8 error;
959
960 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
961 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
962 : "cc", "memory");
963 if (error)
964 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
965 vmcs, phys_addr);
966 }
967
968 static void __loaded_vmcs_clear(void *arg)
969 {
970 struct loaded_vmcs *loaded_vmcs = arg;
971 int cpu = raw_smp_processor_id();
972
973 if (loaded_vmcs->cpu != cpu)
974 return; /* vcpu migration can race with cpu offline */
975 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
976 per_cpu(current_vmcs, cpu) = NULL;
977 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
978 loaded_vmcs_init(loaded_vmcs);
979 }
980
981 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
982 {
983 if (loaded_vmcs->cpu != -1)
984 smp_call_function_single(
985 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
986 }
987
988 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
989 {
990 if (vmx->vpid == 0)
991 return;
992
993 if (cpu_has_vmx_invvpid_single())
994 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
995 }
996
997 static inline void vpid_sync_vcpu_global(void)
998 {
999 if (cpu_has_vmx_invvpid_global())
1000 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 }
1002
1003 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1004 {
1005 if (cpu_has_vmx_invvpid_single())
1006 vpid_sync_vcpu_single(vmx);
1007 else
1008 vpid_sync_vcpu_global();
1009 }
1010
1011 static inline void ept_sync_global(void)
1012 {
1013 if (cpu_has_vmx_invept_global())
1014 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 }
1016
1017 static inline void ept_sync_context(u64 eptp)
1018 {
1019 if (enable_ept) {
1020 if (cpu_has_vmx_invept_context())
1021 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1022 else
1023 ept_sync_global();
1024 }
1025 }
1026
1027 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 {
1029 if (enable_ept) {
1030 if (cpu_has_vmx_invept_individual_addr())
1031 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032 eptp, gpa);
1033 else
1034 ept_sync_context(eptp);
1035 }
1036 }
1037
1038 static __always_inline unsigned long vmcs_readl(unsigned long field)
1039 {
1040 unsigned long value;
1041
1042 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043 : "=a"(value) : "d"(field) : "cc");
1044 return value;
1045 }
1046
1047 static __always_inline u16 vmcs_read16(unsigned long field)
1048 {
1049 return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u32 vmcs_read32(unsigned long field)
1053 {
1054 return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u64 vmcs_read64(unsigned long field)
1058 {
1059 #ifdef CONFIG_X86_64
1060 return vmcs_readl(field);
1061 #else
1062 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1063 #endif
1064 }
1065
1066 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1067 {
1068 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1070 dump_stack();
1071 }
1072
1073 static void vmcs_writel(unsigned long field, unsigned long value)
1074 {
1075 u8 error;
1076
1077 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1078 : "=q"(error) : "a"(value), "d"(field) : "cc");
1079 if (unlikely(error))
1080 vmwrite_error(field, value);
1081 }
1082
1083 static void vmcs_write16(unsigned long field, u16 value)
1084 {
1085 vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write32(unsigned long field, u32 value)
1089 {
1090 vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write64(unsigned long field, u64 value)
1094 {
1095 vmcs_writel(field, value);
1096 #ifndef CONFIG_X86_64
1097 asm volatile ("");
1098 vmcs_writel(field+1, value >> 32);
1099 #endif
1100 }
1101
1102 static void vmcs_clear_bits(unsigned long field, u32 mask)
1103 {
1104 vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 }
1106
1107 static void vmcs_set_bits(unsigned long field, u32 mask)
1108 {
1109 vmcs_writel(field, vmcs_readl(field) | mask);
1110 }
1111
1112 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1113 {
1114 vmx->segment_cache.bitmask = 0;
1115 }
1116
1117 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1118 unsigned field)
1119 {
1120 bool ret;
1121 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1122
1123 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125 vmx->segment_cache.bitmask = 0;
1126 }
1127 ret = vmx->segment_cache.bitmask & mask;
1128 vmx->segment_cache.bitmask |= mask;
1129 return ret;
1130 }
1131
1132 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1133 {
1134 u16 *p = &vmx->segment_cache.seg[seg].selector;
1135
1136 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1138 return *p;
1139 }
1140
1141 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1142 {
1143 ulong *p = &vmx->segment_cache.seg[seg].base;
1144
1145 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1147 return *p;
1148 }
1149
1150 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1151 {
1152 u32 *p = &vmx->segment_cache.seg[seg].limit;
1153
1154 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1156 return *p;
1157 }
1158
1159 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161 u32 *p = &vmx->segment_cache.seg[seg].ar;
1162
1163 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1165 return *p;
1166 }
1167
1168 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1169 {
1170 u32 eb;
1171
1172 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174 if ((vcpu->guest_debug &
1175 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177 eb |= 1u << BP_VECTOR;
1178 if (to_vmx(vcpu)->rmode.vm86_active)
1179 eb = ~0;
1180 if (enable_ept)
1181 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1182 if (vcpu->fpu_active)
1183 eb &= ~(1u << NM_VECTOR);
1184
1185 /* When we are running a nested L2 guest and L1 specified for it a
1186 * certain exception bitmap, we must trap the same exceptions and pass
1187 * them to L1. When running L2, we will only handle the exceptions
1188 * specified above if L1 did not want them.
1189 */
1190 if (is_guest_mode(vcpu))
1191 eb |= get_vmcs12(vcpu)->exception_bitmap;
1192
1193 vmcs_write32(EXCEPTION_BITMAP, eb);
1194 }
1195
1196 static void clear_atomic_switch_msr_special(unsigned long entry,
1197 unsigned long exit)
1198 {
1199 vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200 vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201 }
1202
1203 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204 {
1205 unsigned i;
1206 struct msr_autoload *m = &vmx->msr_autoload;
1207
1208 switch (msr) {
1209 case MSR_EFER:
1210 if (cpu_has_load_ia32_efer) {
1211 clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212 VM_EXIT_LOAD_IA32_EFER);
1213 return;
1214 }
1215 break;
1216 case MSR_CORE_PERF_GLOBAL_CTRL:
1217 if (cpu_has_load_perf_global_ctrl) {
1218 clear_atomic_switch_msr_special(
1219 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1221 return;
1222 }
1223 break;
1224 }
1225
1226 for (i = 0; i < m->nr; ++i)
1227 if (m->guest[i].index == msr)
1228 break;
1229
1230 if (i == m->nr)
1231 return;
1232 --m->nr;
1233 m->guest[i] = m->guest[m->nr];
1234 m->host[i] = m->host[m->nr];
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 static void add_atomic_switch_msr_special(unsigned long entry,
1240 unsigned long exit, unsigned long guest_val_vmcs,
1241 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1242 {
1243 vmcs_write64(guest_val_vmcs, guest_val);
1244 vmcs_write64(host_val_vmcs, host_val);
1245 vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246 vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247 }
1248
1249 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250 u64 guest_val, u64 host_val)
1251 {
1252 unsigned i;
1253 struct msr_autoload *m = &vmx->msr_autoload;
1254
1255 switch (msr) {
1256 case MSR_EFER:
1257 if (cpu_has_load_ia32_efer) {
1258 add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259 VM_EXIT_LOAD_IA32_EFER,
1260 GUEST_IA32_EFER,
1261 HOST_IA32_EFER,
1262 guest_val, host_val);
1263 return;
1264 }
1265 break;
1266 case MSR_CORE_PERF_GLOBAL_CTRL:
1267 if (cpu_has_load_perf_global_ctrl) {
1268 add_atomic_switch_msr_special(
1269 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271 GUEST_IA32_PERF_GLOBAL_CTRL,
1272 HOST_IA32_PERF_GLOBAL_CTRL,
1273 guest_val, host_val);
1274 return;
1275 }
1276 break;
1277 }
1278
1279 for (i = 0; i < m->nr; ++i)
1280 if (m->guest[i].index == msr)
1281 break;
1282
1283 if (i == NR_AUTOLOAD_MSRS) {
1284 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285 "Can't add msr %x\n", msr);
1286 return;
1287 } else if (i == m->nr) {
1288 ++m->nr;
1289 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291 }
1292
1293 m->guest[i].index = msr;
1294 m->guest[i].value = guest_val;
1295 m->host[i].index = msr;
1296 m->host[i].value = host_val;
1297 }
1298
1299 static void reload_tss(void)
1300 {
1301 /*
1302 * VT restores TR but not its size. Useless.
1303 */
1304 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1305 struct desc_struct *descs;
1306
1307 descs = (void *)gdt->address;
1308 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1309 load_TR_desc();
1310 }
1311
1312 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1313 {
1314 u64 guest_efer;
1315 u64 ignore_bits;
1316
1317 guest_efer = vmx->vcpu.arch.efer;
1318
1319 /*
1320 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321 * outside long mode
1322 */
1323 ignore_bits = EFER_NX | EFER_SCE;
1324 #ifdef CONFIG_X86_64
1325 ignore_bits |= EFER_LMA | EFER_LME;
1326 /* SCE is meaningful only in long mode on Intel */
1327 if (guest_efer & EFER_LMA)
1328 ignore_bits &= ~(u64)EFER_SCE;
1329 #endif
1330 guest_efer &= ~ignore_bits;
1331 guest_efer |= host_efer & ignore_bits;
1332 vmx->guest_msrs[efer_offset].data = guest_efer;
1333 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1334
1335 clear_atomic_switch_msr(vmx, MSR_EFER);
1336 /* On ept, can't emulate nx, and must switch nx atomically */
1337 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338 guest_efer = vmx->vcpu.arch.efer;
1339 if (!(guest_efer & EFER_LMA))
1340 guest_efer &= ~EFER_LME;
1341 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1342 return false;
1343 }
1344
1345 return true;
1346 }
1347
1348 static unsigned long segment_base(u16 selector)
1349 {
1350 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1351 struct desc_struct *d;
1352 unsigned long table_base;
1353 unsigned long v;
1354
1355 if (!(selector & ~3))
1356 return 0;
1357
1358 table_base = gdt->address;
1359
1360 if (selector & 4) { /* from ldt */
1361 u16 ldt_selector = kvm_read_ldt();
1362
1363 if (!(ldt_selector & ~3))
1364 return 0;
1365
1366 table_base = segment_base(ldt_selector);
1367 }
1368 d = (struct desc_struct *)(table_base + (selector & ~7));
1369 v = get_desc_base(d);
1370 #ifdef CONFIG_X86_64
1371 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1373 #endif
1374 return v;
1375 }
1376
1377 static inline unsigned long kvm_read_tr_base(void)
1378 {
1379 u16 tr;
1380 asm("str %0" : "=g"(tr));
1381 return segment_base(tr);
1382 }
1383
1384 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1385 {
1386 struct vcpu_vmx *vmx = to_vmx(vcpu);
1387 int i;
1388
1389 if (vmx->host_state.loaded)
1390 return;
1391
1392 vmx->host_state.loaded = 1;
1393 /*
1394 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1395 * allow segment selectors with cpl > 0 or ti == 1.
1396 */
1397 vmx->host_state.ldt_sel = kvm_read_ldt();
1398 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1399 savesegment(fs, vmx->host_state.fs_sel);
1400 if (!(vmx->host_state.fs_sel & 7)) {
1401 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1402 vmx->host_state.fs_reload_needed = 0;
1403 } else {
1404 vmcs_write16(HOST_FS_SELECTOR, 0);
1405 vmx->host_state.fs_reload_needed = 1;
1406 }
1407 savesegment(gs, vmx->host_state.gs_sel);
1408 if (!(vmx->host_state.gs_sel & 7))
1409 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1410 else {
1411 vmcs_write16(HOST_GS_SELECTOR, 0);
1412 vmx->host_state.gs_ldt_reload_needed = 1;
1413 }
1414
1415 #ifdef CONFIG_X86_64
1416 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1418 #else
1419 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1421 #endif
1422
1423 #ifdef CONFIG_X86_64
1424 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425 if (is_long_mode(&vmx->vcpu))
1426 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1427 #endif
1428 for (i = 0; i < vmx->save_nmsrs; ++i)
1429 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1430 vmx->guest_msrs[i].data,
1431 vmx->guest_msrs[i].mask);
1432 }
1433
1434 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1435 {
1436 if (!vmx->host_state.loaded)
1437 return;
1438
1439 ++vmx->vcpu.stat.host_state_reload;
1440 vmx->host_state.loaded = 0;
1441 #ifdef CONFIG_X86_64
1442 if (is_long_mode(&vmx->vcpu))
1443 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444 #endif
1445 if (vmx->host_state.gs_ldt_reload_needed) {
1446 kvm_load_ldt(vmx->host_state.ldt_sel);
1447 #ifdef CONFIG_X86_64
1448 load_gs_index(vmx->host_state.gs_sel);
1449 #else
1450 loadsegment(gs, vmx->host_state.gs_sel);
1451 #endif
1452 }
1453 if (vmx->host_state.fs_reload_needed)
1454 loadsegment(fs, vmx->host_state.fs_sel);
1455 reload_tss();
1456 #ifdef CONFIG_X86_64
1457 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1458 #endif
1459 if (current_thread_info()->status & TS_USEDFPU)
1460 clts();
1461 load_gdt(&__get_cpu_var(host_gdt));
1462 }
1463
1464 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466 preempt_disable();
1467 __vmx_load_host_state(vmx);
1468 preempt_enable();
1469 }
1470
1471 /*
1472 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473 * vcpu mutex is already taken.
1474 */
1475 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 {
1477 struct vcpu_vmx *vmx = to_vmx(vcpu);
1478 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1479
1480 if (!vmm_exclusive)
1481 kvm_cpu_vmxon(phys_addr);
1482 else if (vmx->loaded_vmcs->cpu != cpu)
1483 loaded_vmcs_clear(vmx->loaded_vmcs);
1484
1485 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487 vmcs_load(vmx->loaded_vmcs->vmcs);
1488 }
1489
1490 if (vmx->loaded_vmcs->cpu != cpu) {
1491 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1492 unsigned long sysenter_esp;
1493
1494 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1495 local_irq_disable();
1496 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497 &per_cpu(loaded_vmcss_on_cpu, cpu));
1498 local_irq_enable();
1499
1500 /*
1501 * Linux uses per-cpu TSS and GDT, so set these when switching
1502 * processors.
1503 */
1504 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1505 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
1506
1507 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1509 vmx->loaded_vmcs->cpu = cpu;
1510 }
1511 }
1512
1513 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1514 {
1515 __vmx_load_host_state(to_vmx(vcpu));
1516 if (!vmm_exclusive) {
1517 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1518 vcpu->cpu = -1;
1519 kvm_cpu_vmxoff();
1520 }
1521 }
1522
1523 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1524 {
1525 ulong cr0;
1526
1527 if (vcpu->fpu_active)
1528 return;
1529 vcpu->fpu_active = 1;
1530 cr0 = vmcs_readl(GUEST_CR0);
1531 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533 vmcs_writel(GUEST_CR0, cr0);
1534 update_exception_bitmap(vcpu);
1535 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1536 if (is_guest_mode(vcpu))
1537 vcpu->arch.cr0_guest_owned_bits &=
1538 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1539 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1540 }
1541
1542 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543
1544 /*
1545 * Return the cr0 value that a nested guest would read. This is a combination
1546 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547 * its hypervisor (cr0_read_shadow).
1548 */
1549 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1550 {
1551 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1553 }
1554 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1555 {
1556 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558 }
1559
1560 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1561 {
1562 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563 * set this *before* calling this function.
1564 */
1565 vmx_decache_cr0_guest_bits(vcpu);
1566 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1567 update_exception_bitmap(vcpu);
1568 vcpu->arch.cr0_guest_owned_bits = 0;
1569 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1570 if (is_guest_mode(vcpu)) {
1571 /*
1572 * L1's specified read shadow might not contain the TS bit,
1573 * so now that we turned on shadowing of this bit, we need to
1574 * set this bit of the shadow. Like in nested_vmx_run we need
1575 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576 * up-to-date here because we just decached cr0.TS (and we'll
1577 * only update vmcs12->guest_cr0 on nested exit).
1578 */
1579 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581 (vcpu->arch.cr0 & X86_CR0_TS);
1582 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1583 } else
1584 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1585 }
1586
1587 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1588 {
1589 unsigned long rflags, save_rflags;
1590
1591 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593 rflags = vmcs_readl(GUEST_RFLAGS);
1594 if (to_vmx(vcpu)->rmode.vm86_active) {
1595 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1598 }
1599 to_vmx(vcpu)->rflags = rflags;
1600 }
1601 return to_vmx(vcpu)->rflags;
1602 }
1603
1604 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1605 {
1606 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1607 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1608 to_vmx(vcpu)->rflags = rflags;
1609 if (to_vmx(vcpu)->rmode.vm86_active) {
1610 to_vmx(vcpu)->rmode.save_rflags = rflags;
1611 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1612 }
1613 vmcs_writel(GUEST_RFLAGS, rflags);
1614 }
1615
1616 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1617 {
1618 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619 int ret = 0;
1620
1621 if (interruptibility & GUEST_INTR_STATE_STI)
1622 ret |= KVM_X86_SHADOW_INT_STI;
1623 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1624 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1625
1626 return ret & mask;
1627 }
1628
1629 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1630 {
1631 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632 u32 interruptibility = interruptibility_old;
1633
1634 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1635
1636 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1637 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1638 else if (mask & KVM_X86_SHADOW_INT_STI)
1639 interruptibility |= GUEST_INTR_STATE_STI;
1640
1641 if ((interruptibility != interruptibility_old))
1642 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643 }
1644
1645 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1646 {
1647 unsigned long rip;
1648
1649 rip = kvm_rip_read(vcpu);
1650 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1651 kvm_rip_write(vcpu, rip);
1652
1653 /* skipping an emulated instruction also counts */
1654 vmx_set_interrupt_shadow(vcpu, 0);
1655 }
1656
1657 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1658 {
1659 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1660 * explicitly skip the instruction because if the HLT state is set, then
1661 * the instruction is already executing and RIP has already been
1662 * advanced. */
1663 if (!yield_on_hlt &&
1664 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1666 }
1667
1668 /*
1669 * KVM wants to inject page-faults which it got to the guest. This function
1670 * checks whether in a nested guest, we need to inject them to L1 or L2.
1671 * This function assumes it is called with the exit reason in vmcs02 being
1672 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1673 * is running).
1674 */
1675 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1676 {
1677 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1678
1679 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1681 return 0;
1682
1683 nested_vmx_vmexit(vcpu);
1684 return 1;
1685 }
1686
1687 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1688 bool has_error_code, u32 error_code,
1689 bool reinject)
1690 {
1691 struct vcpu_vmx *vmx = to_vmx(vcpu);
1692 u32 intr_info = nr | INTR_INFO_VALID_MASK;
1693
1694 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695 nested_pf_handled(vcpu))
1696 return;
1697
1698 if (has_error_code) {
1699 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1700 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1701 }
1702
1703 if (vmx->rmode.vm86_active) {
1704 int inc_eip = 0;
1705 if (kvm_exception_is_soft(nr))
1706 inc_eip = vcpu->arch.event_exit_inst_len;
1707 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1708 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1709 return;
1710 }
1711
1712 if (kvm_exception_is_soft(nr)) {
1713 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714 vmx->vcpu.arch.event_exit_inst_len);
1715 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1716 } else
1717 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1718
1719 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1720 vmx_clear_hlt(vcpu);
1721 }
1722
1723 static bool vmx_rdtscp_supported(void)
1724 {
1725 return cpu_has_vmx_rdtscp();
1726 }
1727
1728 /*
1729 * Swap MSR entry in host/guest MSR entry array.
1730 */
1731 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1732 {
1733 struct shared_msr_entry tmp;
1734
1735 tmp = vmx->guest_msrs[to];
1736 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737 vmx->guest_msrs[from] = tmp;
1738 }
1739
1740 /*
1741 * Set up the vmcs to automatically save and restore system
1742 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1743 * mode, as fiddling with msrs is very expensive.
1744 */
1745 static void setup_msrs(struct vcpu_vmx *vmx)
1746 {
1747 int save_nmsrs, index;
1748 unsigned long *msr_bitmap;
1749
1750 save_nmsrs = 0;
1751 #ifdef CONFIG_X86_64
1752 if (is_long_mode(&vmx->vcpu)) {
1753 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1754 if (index >= 0)
1755 move_msr_up(vmx, index, save_nmsrs++);
1756 index = __find_msr_index(vmx, MSR_LSTAR);
1757 if (index >= 0)
1758 move_msr_up(vmx, index, save_nmsrs++);
1759 index = __find_msr_index(vmx, MSR_CSTAR);
1760 if (index >= 0)
1761 move_msr_up(vmx, index, save_nmsrs++);
1762 index = __find_msr_index(vmx, MSR_TSC_AUX);
1763 if (index >= 0 && vmx->rdtscp_enabled)
1764 move_msr_up(vmx, index, save_nmsrs++);
1765 /*
1766 * MSR_STAR is only needed on long mode guests, and only
1767 * if efer.sce is enabled.
1768 */
1769 index = __find_msr_index(vmx, MSR_STAR);
1770 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1771 move_msr_up(vmx, index, save_nmsrs++);
1772 }
1773 #endif
1774 index = __find_msr_index(vmx, MSR_EFER);
1775 if (index >= 0 && update_transition_efer(vmx, index))
1776 move_msr_up(vmx, index, save_nmsrs++);
1777
1778 vmx->save_nmsrs = save_nmsrs;
1779
1780 if (cpu_has_vmx_msr_bitmap()) {
1781 if (is_long_mode(&vmx->vcpu))
1782 msr_bitmap = vmx_msr_bitmap_longmode;
1783 else
1784 msr_bitmap = vmx_msr_bitmap_legacy;
1785
1786 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1787 }
1788 }
1789
1790 /*
1791 * reads and returns guest's timestamp counter "register"
1792 * guest_tsc = host_tsc + tsc_offset -- 21.3
1793 */
1794 static u64 guest_read_tsc(void)
1795 {
1796 u64 host_tsc, tsc_offset;
1797
1798 rdtscll(host_tsc);
1799 tsc_offset = vmcs_read64(TSC_OFFSET);
1800 return host_tsc + tsc_offset;
1801 }
1802
1803 /*
1804 * Like guest_read_tsc, but always returns L1's notion of the timestamp
1805 * counter, even if a nested guest (L2) is currently running.
1806 */
1807 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1808 {
1809 u64 host_tsc, tsc_offset;
1810
1811 rdtscll(host_tsc);
1812 tsc_offset = is_guest_mode(vcpu) ?
1813 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1814 vmcs_read64(TSC_OFFSET);
1815 return host_tsc + tsc_offset;
1816 }
1817
1818 /*
1819 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1820 * ioctl. In this case the call-back should update internal vmx state to make
1821 * the changes effective.
1822 */
1823 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1824 {
1825 /* Nothing to do here */
1826 }
1827
1828 /*
1829 * writes 'offset' into guest's timestamp counter offset register
1830 */
1831 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1832 {
1833 if (is_guest_mode(vcpu)) {
1834 /*
1835 * We're here if L1 chose not to trap WRMSR to TSC. According
1836 * to the spec, this should set L1's TSC; The offset that L1
1837 * set for L2 remains unchanged, and still needs to be added
1838 * to the newly set TSC to get L2's TSC.
1839 */
1840 struct vmcs12 *vmcs12;
1841 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1842 /* recalculate vmcs02.TSC_OFFSET: */
1843 vmcs12 = get_vmcs12(vcpu);
1844 vmcs_write64(TSC_OFFSET, offset +
1845 (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1846 vmcs12->tsc_offset : 0));
1847 } else {
1848 vmcs_write64(TSC_OFFSET, offset);
1849 }
1850 }
1851
1852 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1853 {
1854 u64 offset = vmcs_read64(TSC_OFFSET);
1855 vmcs_write64(TSC_OFFSET, offset + adjustment);
1856 if (is_guest_mode(vcpu)) {
1857 /* Even when running L2, the adjustment needs to apply to L1 */
1858 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1859 }
1860 }
1861
1862 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1863 {
1864 return target_tsc - native_read_tsc();
1865 }
1866
1867 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1868 {
1869 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1870 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1871 }
1872
1873 /*
1874 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1875 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1876 * all guests if the "nested" module option is off, and can also be disabled
1877 * for a single guest by disabling its VMX cpuid bit.
1878 */
1879 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1880 {
1881 return nested && guest_cpuid_has_vmx(vcpu);
1882 }
1883
1884 /*
1885 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1886 * returned for the various VMX controls MSRs when nested VMX is enabled.
1887 * The same values should also be used to verify that vmcs12 control fields are
1888 * valid during nested entry from L1 to L2.
1889 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1890 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1891 * bit in the high half is on if the corresponding bit in the control field
1892 * may be on. See also vmx_control_verify().
1893 * TODO: allow these variables to be modified (downgraded) by module options
1894 * or other means.
1895 */
1896 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1897 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1898 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1899 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1900 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1901 static __init void nested_vmx_setup_ctls_msrs(void)
1902 {
1903 /*
1904 * Note that as a general rule, the high half of the MSRs (bits in
1905 * the control fields which may be 1) should be initialized by the
1906 * intersection of the underlying hardware's MSR (i.e., features which
1907 * can be supported) and the list of features we want to expose -
1908 * because they are known to be properly supported in our code.
1909 * Also, usually, the low half of the MSRs (bits which must be 1) can
1910 * be set to 0, meaning that L1 may turn off any of these bits. The
1911 * reason is that if one of these bits is necessary, it will appear
1912 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1913 * fields of vmcs01 and vmcs02, will turn these bits off - and
1914 * nested_vmx_exit_handled() will not pass related exits to L1.
1915 * These rules have exceptions below.
1916 */
1917
1918 /* pin-based controls */
1919 /*
1920 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1921 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1922 */
1923 nested_vmx_pinbased_ctls_low = 0x16 ;
1924 nested_vmx_pinbased_ctls_high = 0x16 |
1925 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1926 PIN_BASED_VIRTUAL_NMIS;
1927
1928 /* exit controls */
1929 nested_vmx_exit_ctls_low = 0;
1930 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1931 #ifdef CONFIG_X86_64
1932 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1933 #else
1934 nested_vmx_exit_ctls_high = 0;
1935 #endif
1936
1937 /* entry controls */
1938 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1939 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1940 nested_vmx_entry_ctls_low = 0;
1941 nested_vmx_entry_ctls_high &=
1942 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1943
1944 /* cpu-based controls */
1945 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1946 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1947 nested_vmx_procbased_ctls_low = 0;
1948 nested_vmx_procbased_ctls_high &=
1949 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1950 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1951 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1952 CPU_BASED_CR3_STORE_EXITING |
1953 #ifdef CONFIG_X86_64
1954 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1955 #endif
1956 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1957 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1958 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1959 /*
1960 * We can allow some features even when not supported by the
1961 * hardware. For example, L1 can specify an MSR bitmap - and we
1962 * can use it to avoid exits to L1 - even when L0 runs L2
1963 * without MSR bitmaps.
1964 */
1965 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1966
1967 /* secondary cpu-based controls */
1968 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1969 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1970 nested_vmx_secondary_ctls_low = 0;
1971 nested_vmx_secondary_ctls_high &=
1972 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1973 }
1974
1975 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1976 {
1977 /*
1978 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1979 */
1980 return ((control & high) | low) == control;
1981 }
1982
1983 static inline u64 vmx_control_msr(u32 low, u32 high)
1984 {
1985 return low | ((u64)high << 32);
1986 }
1987
1988 /*
1989 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1990 * also let it use VMX-specific MSRs.
1991 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1992 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1993 * like all other MSRs).
1994 */
1995 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1996 {
1997 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1998 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1999 /*
2000 * According to the spec, processors which do not support VMX
2001 * should throw a #GP(0) when VMX capability MSRs are read.
2002 */
2003 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2004 return 1;
2005 }
2006
2007 switch (msr_index) {
2008 case MSR_IA32_FEATURE_CONTROL:
2009 *pdata = 0;
2010 break;
2011 case MSR_IA32_VMX_BASIC:
2012 /*
2013 * This MSR reports some information about VMX support. We
2014 * should return information about the VMX we emulate for the
2015 * guest, and the VMCS structure we give it - not about the
2016 * VMX support of the underlying hardware.
2017 */
2018 *pdata = VMCS12_REVISION |
2019 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2020 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2021 break;
2022 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2023 case MSR_IA32_VMX_PINBASED_CTLS:
2024 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2025 nested_vmx_pinbased_ctls_high);
2026 break;
2027 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2028 case MSR_IA32_VMX_PROCBASED_CTLS:
2029 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2030 nested_vmx_procbased_ctls_high);
2031 break;
2032 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2033 case MSR_IA32_VMX_EXIT_CTLS:
2034 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2035 nested_vmx_exit_ctls_high);
2036 break;
2037 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2038 case MSR_IA32_VMX_ENTRY_CTLS:
2039 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2040 nested_vmx_entry_ctls_high);
2041 break;
2042 case MSR_IA32_VMX_MISC:
2043 *pdata = 0;
2044 break;
2045 /*
2046 * These MSRs specify bits which the guest must keep fixed (on or off)
2047 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2048 * We picked the standard core2 setting.
2049 */
2050 #define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2051 #define VMXON_CR4_ALWAYSON X86_CR4_VMXE
2052 case MSR_IA32_VMX_CR0_FIXED0:
2053 *pdata = VMXON_CR0_ALWAYSON;
2054 break;
2055 case MSR_IA32_VMX_CR0_FIXED1:
2056 *pdata = -1ULL;
2057 break;
2058 case MSR_IA32_VMX_CR4_FIXED0:
2059 *pdata = VMXON_CR4_ALWAYSON;
2060 break;
2061 case MSR_IA32_VMX_CR4_FIXED1:
2062 *pdata = -1ULL;
2063 break;
2064 case MSR_IA32_VMX_VMCS_ENUM:
2065 *pdata = 0x1f;
2066 break;
2067 case MSR_IA32_VMX_PROCBASED_CTLS2:
2068 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2069 nested_vmx_secondary_ctls_high);
2070 break;
2071 case MSR_IA32_VMX_EPT_VPID_CAP:
2072 /* Currently, no nested ept or nested vpid */
2073 *pdata = 0;
2074 break;
2075 default:
2076 return 0;
2077 }
2078
2079 return 1;
2080 }
2081
2082 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2083 {
2084 if (!nested_vmx_allowed(vcpu))
2085 return 0;
2086
2087 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2088 /* TODO: the right thing. */
2089 return 1;
2090 /*
2091 * No need to treat VMX capability MSRs specially: If we don't handle
2092 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2093 */
2094 return 0;
2095 }
2096
2097 /*
2098 * Reads an msr value (of 'msr_index') into 'pdata'.
2099 * Returns 0 on success, non-0 otherwise.
2100 * Assumes vcpu_load() was already called.
2101 */
2102 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2103 {
2104 u64 data;
2105 struct shared_msr_entry *msr;
2106
2107 if (!pdata) {
2108 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2109 return -EINVAL;
2110 }
2111
2112 switch (msr_index) {
2113 #ifdef CONFIG_X86_64
2114 case MSR_FS_BASE:
2115 data = vmcs_readl(GUEST_FS_BASE);
2116 break;
2117 case MSR_GS_BASE:
2118 data = vmcs_readl(GUEST_GS_BASE);
2119 break;
2120 case MSR_KERNEL_GS_BASE:
2121 vmx_load_host_state(to_vmx(vcpu));
2122 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2123 break;
2124 #endif
2125 case MSR_EFER:
2126 return kvm_get_msr_common(vcpu, msr_index, pdata);
2127 case MSR_IA32_TSC:
2128 data = guest_read_tsc();
2129 break;
2130 case MSR_IA32_SYSENTER_CS:
2131 data = vmcs_read32(GUEST_SYSENTER_CS);
2132 break;
2133 case MSR_IA32_SYSENTER_EIP:
2134 data = vmcs_readl(GUEST_SYSENTER_EIP);
2135 break;
2136 case MSR_IA32_SYSENTER_ESP:
2137 data = vmcs_readl(GUEST_SYSENTER_ESP);
2138 break;
2139 case MSR_TSC_AUX:
2140 if (!to_vmx(vcpu)->rdtscp_enabled)
2141 return 1;
2142 /* Otherwise falls through */
2143 default:
2144 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2145 return 0;
2146 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2147 if (msr) {
2148 data = msr->data;
2149 break;
2150 }
2151 return kvm_get_msr_common(vcpu, msr_index, pdata);
2152 }
2153
2154 *pdata = data;
2155 return 0;
2156 }
2157
2158 /*
2159 * Writes msr value into into the appropriate "register".
2160 * Returns 0 on success, non-0 otherwise.
2161 * Assumes vcpu_load() was already called.
2162 */
2163 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2164 {
2165 struct vcpu_vmx *vmx = to_vmx(vcpu);
2166 struct shared_msr_entry *msr;
2167 int ret = 0;
2168
2169 switch (msr_index) {
2170 case MSR_EFER:
2171 ret = kvm_set_msr_common(vcpu, msr_index, data);
2172 break;
2173 #ifdef CONFIG_X86_64
2174 case MSR_FS_BASE:
2175 vmx_segment_cache_clear(vmx);
2176 vmcs_writel(GUEST_FS_BASE, data);
2177 break;
2178 case MSR_GS_BASE:
2179 vmx_segment_cache_clear(vmx);
2180 vmcs_writel(GUEST_GS_BASE, data);
2181 break;
2182 case MSR_KERNEL_GS_BASE:
2183 vmx_load_host_state(vmx);
2184 vmx->msr_guest_kernel_gs_base = data;
2185 break;
2186 #endif
2187 case MSR_IA32_SYSENTER_CS:
2188 vmcs_write32(GUEST_SYSENTER_CS, data);
2189 break;
2190 case MSR_IA32_SYSENTER_EIP:
2191 vmcs_writel(GUEST_SYSENTER_EIP, data);
2192 break;
2193 case MSR_IA32_SYSENTER_ESP:
2194 vmcs_writel(GUEST_SYSENTER_ESP, data);
2195 break;
2196 case MSR_IA32_TSC:
2197 kvm_write_tsc(vcpu, data);
2198 break;
2199 case MSR_IA32_CR_PAT:
2200 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2201 vmcs_write64(GUEST_IA32_PAT, data);
2202 vcpu->arch.pat = data;
2203 break;
2204 }
2205 ret = kvm_set_msr_common(vcpu, msr_index, data);
2206 break;
2207 case MSR_TSC_AUX:
2208 if (!vmx->rdtscp_enabled)
2209 return 1;
2210 /* Check reserved bit, higher 32 bits should be zero */
2211 if ((data >> 32) != 0)
2212 return 1;
2213 /* Otherwise falls through */
2214 default:
2215 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2216 break;
2217 msr = find_msr_entry(vmx, msr_index);
2218 if (msr) {
2219 msr->data = data;
2220 break;
2221 }
2222 ret = kvm_set_msr_common(vcpu, msr_index, data);
2223 }
2224
2225 return ret;
2226 }
2227
2228 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2229 {
2230 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2231 switch (reg) {
2232 case VCPU_REGS_RSP:
2233 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2234 break;
2235 case VCPU_REGS_RIP:
2236 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2237 break;
2238 case VCPU_EXREG_PDPTR:
2239 if (enable_ept)
2240 ept_save_pdptrs(vcpu);
2241 break;
2242 default:
2243 break;
2244 }
2245 }
2246
2247 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2248 {
2249 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2250 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2251 else
2252 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2253
2254 update_exception_bitmap(vcpu);
2255 }
2256
2257 static __init int cpu_has_kvm_support(void)
2258 {
2259 return cpu_has_vmx();
2260 }
2261
2262 static __init int vmx_disabled_by_bios(void)
2263 {
2264 u64 msr;
2265
2266 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2267 if (msr & FEATURE_CONTROL_LOCKED) {
2268 /* launched w/ TXT and VMX disabled */
2269 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2270 && tboot_enabled())
2271 return 1;
2272 /* launched w/o TXT and VMX only enabled w/ TXT */
2273 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2274 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2275 && !tboot_enabled()) {
2276 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2277 "activate TXT before enabling KVM\n");
2278 return 1;
2279 }
2280 /* launched w/o TXT and VMX disabled */
2281 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2282 && !tboot_enabled())
2283 return 1;
2284 }
2285
2286 return 0;
2287 }
2288
2289 static void kvm_cpu_vmxon(u64 addr)
2290 {
2291 asm volatile (ASM_VMX_VMXON_RAX
2292 : : "a"(&addr), "m"(addr)
2293 : "memory", "cc");
2294 }
2295
2296 static int hardware_enable(void *garbage)
2297 {
2298 int cpu = raw_smp_processor_id();
2299 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2300 u64 old, test_bits;
2301
2302 if (read_cr4() & X86_CR4_VMXE)
2303 return -EBUSY;
2304
2305 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2306 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2307
2308 test_bits = FEATURE_CONTROL_LOCKED;
2309 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2310 if (tboot_enabled())
2311 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2312
2313 if ((old & test_bits) != test_bits) {
2314 /* enable and lock */
2315 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2316 }
2317 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2318
2319 if (vmm_exclusive) {
2320 kvm_cpu_vmxon(phys_addr);
2321 ept_sync_global();
2322 }
2323
2324 store_gdt(&__get_cpu_var(host_gdt));
2325
2326 return 0;
2327 }
2328
2329 static void vmclear_local_loaded_vmcss(void)
2330 {
2331 int cpu = raw_smp_processor_id();
2332 struct loaded_vmcs *v, *n;
2333
2334 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2335 loaded_vmcss_on_cpu_link)
2336 __loaded_vmcs_clear(v);
2337 }
2338
2339
2340 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2341 * tricks.
2342 */
2343 static void kvm_cpu_vmxoff(void)
2344 {
2345 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2346 }
2347
2348 static void hardware_disable(void *garbage)
2349 {
2350 if (vmm_exclusive) {
2351 vmclear_local_loaded_vmcss();
2352 kvm_cpu_vmxoff();
2353 }
2354 write_cr4(read_cr4() & ~X86_CR4_VMXE);
2355 }
2356
2357 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2358 u32 msr, u32 *result)
2359 {
2360 u32 vmx_msr_low, vmx_msr_high;
2361 u32 ctl = ctl_min | ctl_opt;
2362
2363 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2364
2365 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2366 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2367
2368 /* Ensure minimum (required) set of control bits are supported. */
2369 if (ctl_min & ~ctl)
2370 return -EIO;
2371
2372 *result = ctl;
2373 return 0;
2374 }
2375
2376 static __init bool allow_1_setting(u32 msr, u32 ctl)
2377 {
2378 u32 vmx_msr_low, vmx_msr_high;
2379
2380 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2381 return vmx_msr_high & ctl;
2382 }
2383
2384 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2385 {
2386 u32 vmx_msr_low, vmx_msr_high;
2387 u32 min, opt, min2, opt2;
2388 u32 _pin_based_exec_control = 0;
2389 u32 _cpu_based_exec_control = 0;
2390 u32 _cpu_based_2nd_exec_control = 0;
2391 u32 _vmexit_control = 0;
2392 u32 _vmentry_control = 0;
2393
2394 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2395 opt = PIN_BASED_VIRTUAL_NMIS;
2396 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2397 &_pin_based_exec_control) < 0)
2398 return -EIO;
2399
2400 min =
2401 #ifdef CONFIG_X86_64
2402 CPU_BASED_CR8_LOAD_EXITING |
2403 CPU_BASED_CR8_STORE_EXITING |
2404 #endif
2405 CPU_BASED_CR3_LOAD_EXITING |
2406 CPU_BASED_CR3_STORE_EXITING |
2407 CPU_BASED_USE_IO_BITMAPS |
2408 CPU_BASED_MOV_DR_EXITING |
2409 CPU_BASED_USE_TSC_OFFSETING |
2410 CPU_BASED_MWAIT_EXITING |
2411 CPU_BASED_MONITOR_EXITING |
2412 CPU_BASED_INVLPG_EXITING;
2413
2414 if (yield_on_hlt)
2415 min |= CPU_BASED_HLT_EXITING;
2416
2417 opt = CPU_BASED_TPR_SHADOW |
2418 CPU_BASED_USE_MSR_BITMAPS |
2419 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2420 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2421 &_cpu_based_exec_control) < 0)
2422 return -EIO;
2423 #ifdef CONFIG_X86_64
2424 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2425 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2426 ~CPU_BASED_CR8_STORE_EXITING;
2427 #endif
2428 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2429 min2 = 0;
2430 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2431 SECONDARY_EXEC_WBINVD_EXITING |
2432 SECONDARY_EXEC_ENABLE_VPID |
2433 SECONDARY_EXEC_ENABLE_EPT |
2434 SECONDARY_EXEC_UNRESTRICTED_GUEST |
2435 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2436 SECONDARY_EXEC_RDTSCP;
2437 if (adjust_vmx_controls(min2, opt2,
2438 MSR_IA32_VMX_PROCBASED_CTLS2,
2439 &_cpu_based_2nd_exec_control) < 0)
2440 return -EIO;
2441 }
2442 #ifndef CONFIG_X86_64
2443 if (!(_cpu_based_2nd_exec_control &
2444 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2445 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2446 #endif
2447 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2448 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2449 enabled */
2450 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2451 CPU_BASED_CR3_STORE_EXITING |
2452 CPU_BASED_INVLPG_EXITING);
2453 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2454 vmx_capability.ept, vmx_capability.vpid);
2455 }
2456
2457 min = 0;
2458 #ifdef CONFIG_X86_64
2459 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2460 #endif
2461 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2462 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2463 &_vmexit_control) < 0)
2464 return -EIO;
2465
2466 min = 0;
2467 opt = VM_ENTRY_LOAD_IA32_PAT;
2468 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2469 &_vmentry_control) < 0)
2470 return -EIO;
2471
2472 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2473
2474 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2475 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2476 return -EIO;
2477
2478 #ifdef CONFIG_X86_64
2479 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2480 if (vmx_msr_high & (1u<<16))
2481 return -EIO;
2482 #endif
2483
2484 /* Require Write-Back (WB) memory type for VMCS accesses. */
2485 if (((vmx_msr_high >> 18) & 15) != 6)
2486 return -EIO;
2487
2488 vmcs_conf->size = vmx_msr_high & 0x1fff;
2489 vmcs_conf->order = get_order(vmcs_config.size);
2490 vmcs_conf->revision_id = vmx_msr_low;
2491
2492 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2493 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2494 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2495 vmcs_conf->vmexit_ctrl = _vmexit_control;
2496 vmcs_conf->vmentry_ctrl = _vmentry_control;
2497
2498 cpu_has_load_ia32_efer =
2499 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2500 VM_ENTRY_LOAD_IA32_EFER)
2501 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2502 VM_EXIT_LOAD_IA32_EFER);
2503
2504 cpu_has_load_perf_global_ctrl =
2505 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2506 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2507 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2508 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2509
2510 /*
2511 * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2512 * but due to arrata below it can't be used. Workaround is to use
2513 * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2514 *
2515 * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2516 *
2517 * AAK155 (model 26)
2518 * AAP115 (model 30)
2519 * AAT100 (model 37)
2520 * BC86,AAY89,BD102 (model 44)
2521 * BA97 (model 46)
2522 *
2523 */
2524 if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2525 switch (boot_cpu_data.x86_model) {
2526 case 26:
2527 case 30:
2528 case 37:
2529 case 44:
2530 case 46:
2531 cpu_has_load_perf_global_ctrl = false;
2532 printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2533 "does not work properly. Using workaround\n");
2534 break;
2535 default:
2536 break;
2537 }
2538 }
2539
2540 return 0;
2541 }
2542
2543 static struct vmcs *alloc_vmcs_cpu(int cpu)
2544 {
2545 int node = cpu_to_node(cpu);
2546 struct page *pages;
2547 struct vmcs *vmcs;
2548
2549 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2550 if (!pages)
2551 return NULL;
2552 vmcs = page_address(pages);
2553 memset(vmcs, 0, vmcs_config.size);
2554 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2555 return vmcs;
2556 }
2557
2558 static struct vmcs *alloc_vmcs(void)
2559 {
2560 return alloc_vmcs_cpu(raw_smp_processor_id());
2561 }
2562
2563 static void free_vmcs(struct vmcs *vmcs)
2564 {
2565 free_pages((unsigned long)vmcs, vmcs_config.order);
2566 }
2567
2568 /*
2569 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2570 */
2571 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2572 {
2573 if (!loaded_vmcs->vmcs)
2574 return;
2575 loaded_vmcs_clear(loaded_vmcs);
2576 free_vmcs(loaded_vmcs->vmcs);
2577 loaded_vmcs->vmcs = NULL;
2578 }
2579
2580 static void free_kvm_area(void)
2581 {
2582 int cpu;
2583
2584 for_each_possible_cpu(cpu) {
2585 free_vmcs(per_cpu(vmxarea, cpu));
2586 per_cpu(vmxarea, cpu) = NULL;
2587 }
2588 }
2589
2590 static __init int alloc_kvm_area(void)
2591 {
2592 int cpu;
2593
2594 for_each_possible_cpu(cpu) {
2595 struct vmcs *vmcs;
2596
2597 vmcs = alloc_vmcs_cpu(cpu);
2598 if (!vmcs) {
2599 free_kvm_area();
2600 return -ENOMEM;
2601 }
2602
2603 per_cpu(vmxarea, cpu) = vmcs;
2604 }
2605 return 0;
2606 }
2607
2608 static __init int hardware_setup(void)
2609 {
2610 if (setup_vmcs_config(&vmcs_config) < 0)
2611 return -EIO;
2612
2613 if (boot_cpu_has(X86_FEATURE_NX))
2614 kvm_enable_efer_bits(EFER_NX);
2615
2616 if (!cpu_has_vmx_vpid())
2617 enable_vpid = 0;
2618
2619 if (!cpu_has_vmx_ept() ||
2620 !cpu_has_vmx_ept_4levels()) {
2621 enable_ept = 0;
2622 enable_unrestricted_guest = 0;
2623 }
2624
2625 if (!cpu_has_vmx_unrestricted_guest())
2626 enable_unrestricted_guest = 0;
2627
2628 if (!cpu_has_vmx_flexpriority())
2629 flexpriority_enabled = 0;
2630
2631 if (!cpu_has_vmx_tpr_shadow())
2632 kvm_x86_ops->update_cr8_intercept = NULL;
2633
2634 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2635 kvm_disable_largepages();
2636
2637 if (!cpu_has_vmx_ple())
2638 ple_gap = 0;
2639
2640 if (nested)
2641 nested_vmx_setup_ctls_msrs();
2642
2643 return alloc_kvm_area();
2644 }
2645
2646 static __exit void hardware_unsetup(void)
2647 {
2648 free_kvm_area();
2649 }
2650
2651 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2652 {
2653 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2654
2655 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2656 vmcs_write16(sf->selector, save->selector);
2657 vmcs_writel(sf->base, save->base);
2658 vmcs_write32(sf->limit, save->limit);
2659 vmcs_write32(sf->ar_bytes, save->ar);
2660 } else {
2661 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2662 << AR_DPL_SHIFT;
2663 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2664 }
2665 }
2666
2667 static void enter_pmode(struct kvm_vcpu *vcpu)
2668 {
2669 unsigned long flags;
2670 struct vcpu_vmx *vmx = to_vmx(vcpu);
2671
2672 vmx->emulation_required = 1;
2673 vmx->rmode.vm86_active = 0;
2674
2675 vmx_segment_cache_clear(vmx);
2676
2677 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2678 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2679 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2680 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2681
2682 flags = vmcs_readl(GUEST_RFLAGS);
2683 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2684 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2685 vmcs_writel(GUEST_RFLAGS, flags);
2686
2687 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2688 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2689
2690 update_exception_bitmap(vcpu);
2691
2692 if (emulate_invalid_guest_state)
2693 return;
2694
2695 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2696 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2697 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2698 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2699
2700 vmx_segment_cache_clear(vmx);
2701
2702 vmcs_write16(GUEST_SS_SELECTOR, 0);
2703 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2704
2705 vmcs_write16(GUEST_CS_SELECTOR,
2706 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2707 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2708 }
2709
2710 static gva_t rmode_tss_base(struct kvm *kvm)
2711 {
2712 if (!kvm->arch.tss_addr) {
2713 struct kvm_memslots *slots;
2714 gfn_t base_gfn;
2715
2716 slots = kvm_memslots(kvm);
2717 base_gfn = slots->memslots[0].base_gfn +
2718 kvm->memslots->memslots[0].npages - 3;
2719 return base_gfn << PAGE_SHIFT;
2720 }
2721 return kvm->arch.tss_addr;
2722 }
2723
2724 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2725 {
2726 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2727
2728 save->selector = vmcs_read16(sf->selector);
2729 save->base = vmcs_readl(sf->base);
2730 save->limit = vmcs_read32(sf->limit);
2731 save->ar = vmcs_read32(sf->ar_bytes);
2732 vmcs_write16(sf->selector, save->base >> 4);
2733 vmcs_write32(sf->base, save->base & 0xffff0);
2734 vmcs_write32(sf->limit, 0xffff);
2735 vmcs_write32(sf->ar_bytes, 0xf3);
2736 if (save->base & 0xf)
2737 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2738 " aligned when entering protected mode (seg=%d)",
2739 seg);
2740 }
2741
2742 static void enter_rmode(struct kvm_vcpu *vcpu)
2743 {
2744 unsigned long flags;
2745 struct vcpu_vmx *vmx = to_vmx(vcpu);
2746
2747 if (enable_unrestricted_guest)
2748 return;
2749
2750 vmx->emulation_required = 1;
2751 vmx->rmode.vm86_active = 1;
2752
2753 /*
2754 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2755 * vcpu. Call it here with phys address pointing 16M below 4G.
2756 */
2757 if (!vcpu->kvm->arch.tss_addr) {
2758 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2759 "called before entering vcpu\n");
2760 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2761 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2762 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2763 }
2764
2765 vmx_segment_cache_clear(vmx);
2766
2767 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2768 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2769 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2770
2771 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2772 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2773
2774 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2775 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2776
2777 flags = vmcs_readl(GUEST_RFLAGS);
2778 vmx->rmode.save_rflags = flags;
2779
2780 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2781
2782 vmcs_writel(GUEST_RFLAGS, flags);
2783 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2784 update_exception_bitmap(vcpu);
2785
2786 if (emulate_invalid_guest_state)
2787 goto continue_rmode;
2788
2789 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2790 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2791 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2792
2793 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2794 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2795 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2796 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2797 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2798
2799 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2800 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2801 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2802 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2803
2804 continue_rmode:
2805 kvm_mmu_reset_context(vcpu);
2806 }
2807
2808 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2809 {
2810 struct vcpu_vmx *vmx = to_vmx(vcpu);
2811 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2812
2813 if (!msr)
2814 return;
2815
2816 /*
2817 * Force kernel_gs_base reloading before EFER changes, as control
2818 * of this msr depends on is_long_mode().
2819 */
2820 vmx_load_host_state(to_vmx(vcpu));
2821 vcpu->arch.efer = efer;
2822 if (efer & EFER_LMA) {
2823 vmcs_write32(VM_ENTRY_CONTROLS,
2824 vmcs_read32(VM_ENTRY_CONTROLS) |
2825 VM_ENTRY_IA32E_MODE);
2826 msr->data = efer;
2827 } else {
2828 vmcs_write32(VM_ENTRY_CONTROLS,
2829 vmcs_read32(VM_ENTRY_CONTROLS) &
2830 ~VM_ENTRY_IA32E_MODE);
2831
2832 msr->data = efer & ~EFER_LME;
2833 }
2834 setup_msrs(vmx);
2835 }
2836
2837 #ifdef CONFIG_X86_64
2838
2839 static void enter_lmode(struct kvm_vcpu *vcpu)
2840 {
2841 u32 guest_tr_ar;
2842
2843 vmx_segment_cache_clear(to_vmx(vcpu));
2844
2845 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2846 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2847 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2848 __func__);
2849 vmcs_write32(GUEST_TR_AR_BYTES,
2850 (guest_tr_ar & ~AR_TYPE_MASK)
2851 | AR_TYPE_BUSY_64_TSS);
2852 }
2853 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2854 }
2855
2856 static void exit_lmode(struct kvm_vcpu *vcpu)
2857 {
2858 vmcs_write32(VM_ENTRY_CONTROLS,
2859 vmcs_read32(VM_ENTRY_CONTROLS)
2860 & ~VM_ENTRY_IA32E_MODE);
2861 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2862 }
2863
2864 #endif
2865
2866 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2867 {
2868 vpid_sync_context(to_vmx(vcpu));
2869 if (enable_ept) {
2870 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2871 return;
2872 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2873 }
2874 }
2875
2876 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2877 {
2878 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2879
2880 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2881 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2882 }
2883
2884 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2885 {
2886 if (enable_ept && is_paging(vcpu))
2887 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2888 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2889 }
2890
2891 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2892 {
2893 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2894
2895 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2896 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2897 }
2898
2899 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2900 {
2901 if (!test_bit(VCPU_EXREG_PDPTR,
2902 (unsigned long *)&vcpu->arch.regs_dirty))
2903 return;
2904
2905 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2906 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2907 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2908 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2909 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2910 }
2911 }
2912
2913 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2914 {
2915 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2916 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2917 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2918 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2919 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2920 }
2921
2922 __set_bit(VCPU_EXREG_PDPTR,
2923 (unsigned long *)&vcpu->arch.regs_avail);
2924 __set_bit(VCPU_EXREG_PDPTR,
2925 (unsigned long *)&vcpu->arch.regs_dirty);
2926 }
2927
2928 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2929
2930 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2931 unsigned long cr0,
2932 struct kvm_vcpu *vcpu)
2933 {
2934 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2935 vmx_decache_cr3(vcpu);
2936 if (!(cr0 & X86_CR0_PG)) {
2937 /* From paging/starting to nonpaging */
2938 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2939 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2940 (CPU_BASED_CR3_LOAD_EXITING |
2941 CPU_BASED_CR3_STORE_EXITING));
2942 vcpu->arch.cr0 = cr0;
2943 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2944 } else if (!is_paging(vcpu)) {
2945 /* From nonpaging to paging */
2946 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2947 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2948 ~(CPU_BASED_CR3_LOAD_EXITING |
2949 CPU_BASED_CR3_STORE_EXITING));
2950 vcpu->arch.cr0 = cr0;
2951 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2952 }
2953
2954 if (!(cr0 & X86_CR0_WP))
2955 *hw_cr0 &= ~X86_CR0_WP;
2956 }
2957
2958 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2959 {
2960 struct vcpu_vmx *vmx = to_vmx(vcpu);
2961 unsigned long hw_cr0;
2962
2963 if (enable_unrestricted_guest)
2964 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2965 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2966 else
2967 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2968
2969 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2970 enter_pmode(vcpu);
2971
2972 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2973 enter_rmode(vcpu);
2974
2975 #ifdef CONFIG_X86_64
2976 if (vcpu->arch.efer & EFER_LME) {
2977 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2978 enter_lmode(vcpu);
2979 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2980 exit_lmode(vcpu);
2981 }
2982 #endif
2983
2984 if (enable_ept)
2985 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2986
2987 if (!vcpu->fpu_active)
2988 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2989
2990 vmcs_writel(CR0_READ_SHADOW, cr0);
2991 vmcs_writel(GUEST_CR0, hw_cr0);
2992 vcpu->arch.cr0 = cr0;
2993 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2994 }
2995
2996 static u64 construct_eptp(unsigned long root_hpa)
2997 {
2998 u64 eptp;
2999
3000 /* TODO write the value reading from MSR */
3001 eptp = VMX_EPT_DEFAULT_MT |
3002 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3003 eptp |= (root_hpa & PAGE_MASK);
3004
3005 return eptp;
3006 }
3007
3008 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3009 {
3010 unsigned long guest_cr3;
3011 u64 eptp;
3012
3013 guest_cr3 = cr3;
3014 if (enable_ept) {
3015 eptp = construct_eptp(cr3);
3016 vmcs_write64(EPT_POINTER, eptp);
3017 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3018 vcpu->kvm->arch.ept_identity_map_addr;
3019 ept_load_pdptrs(vcpu);
3020 }
3021
3022 vmx_flush_tlb(vcpu);
3023 vmcs_writel(GUEST_CR3, guest_cr3);
3024 }
3025
3026 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3027 {
3028 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3029 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3030
3031 if (cr4 & X86_CR4_VMXE) {
3032 /*
3033 * To use VMXON (and later other VMX instructions), a guest
3034 * must first be able to turn on cr4.VMXE (see handle_vmon()).
3035 * So basically the check on whether to allow nested VMX
3036 * is here.
3037 */
3038 if (!nested_vmx_allowed(vcpu))
3039 return 1;
3040 } else if (to_vmx(vcpu)->nested.vmxon)
3041 return 1;
3042
3043 vcpu->arch.cr4 = cr4;
3044 if (enable_ept) {
3045 if (!is_paging(vcpu)) {
3046 hw_cr4 &= ~X86_CR4_PAE;
3047 hw_cr4 |= X86_CR4_PSE;
3048 } else if (!(cr4 & X86_CR4_PAE)) {
3049 hw_cr4 &= ~X86_CR4_PAE;
3050 }
3051 }
3052
3053 vmcs_writel(CR4_READ_SHADOW, cr4);
3054 vmcs_writel(GUEST_CR4, hw_cr4);
3055 return 0;
3056 }
3057
3058 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3059 struct kvm_segment *var, int seg)
3060 {
3061 struct vcpu_vmx *vmx = to_vmx(vcpu);
3062 struct kvm_save_segment *save;
3063 u32 ar;
3064
3065 if (vmx->rmode.vm86_active
3066 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3067 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3068 || seg == VCPU_SREG_GS)
3069 && !emulate_invalid_guest_state) {
3070 switch (seg) {
3071 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3072 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3073 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3074 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3075 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3076 default: BUG();
3077 }
3078 var->selector = save->selector;
3079 var->base = save->base;
3080 var->limit = save->limit;
3081 ar = save->ar;
3082 if (seg == VCPU_SREG_TR
3083 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3084 goto use_saved_rmode_seg;
3085 }
3086 var->base = vmx_read_guest_seg_base(vmx, seg);
3087 var->limit = vmx_read_guest_seg_limit(vmx, seg);
3088 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3089 ar = vmx_read_guest_seg_ar(vmx, seg);
3090 use_saved_rmode_seg:
3091 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3092 ar = 0;
3093 var->type = ar & 15;
3094 var->s = (ar >> 4) & 1;
3095 var->dpl = (ar >> 5) & 3;
3096 var->present = (ar >> 7) & 1;
3097 var->avl = (ar >> 12) & 1;
3098 var->l = (ar >> 13) & 1;
3099 var->db = (ar >> 14) & 1;
3100 var->g = (ar >> 15) & 1;
3101 var->unusable = (ar >> 16) & 1;
3102 }
3103
3104 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3105 {
3106 struct kvm_segment s;
3107
3108 if (to_vmx(vcpu)->rmode.vm86_active) {
3109 vmx_get_segment(vcpu, &s, seg);
3110 return s.base;
3111 }
3112 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3113 }
3114
3115 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3116 {
3117 if (!is_protmode(vcpu))
3118 return 0;
3119
3120 if (!is_long_mode(vcpu)
3121 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3122 return 3;
3123
3124 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3125 }
3126
3127 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3128 {
3129 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3130 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3131 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3132 }
3133 return to_vmx(vcpu)->cpl;
3134 }
3135
3136
3137 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3138 {
3139 u32 ar;
3140
3141 if (var->unusable)
3142 ar = 1 << 16;
3143 else {
3144 ar = var->type & 15;
3145 ar |= (var->s & 1) << 4;
3146 ar |= (var->dpl & 3) << 5;
3147 ar |= (var->present & 1) << 7;
3148 ar |= (var->avl & 1) << 12;
3149 ar |= (var->l & 1) << 13;
3150 ar |= (var->db & 1) << 14;
3151 ar |= (var->g & 1) << 15;
3152 }
3153 if (ar == 0) /* a 0 value means unusable */
3154 ar = AR_UNUSABLE_MASK;
3155
3156 return ar;
3157 }
3158
3159 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3160 struct kvm_segment *var, int seg)
3161 {
3162 struct vcpu_vmx *vmx = to_vmx(vcpu);
3163 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3164 u32 ar;
3165
3166 vmx_segment_cache_clear(vmx);
3167
3168 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3169 vmcs_write16(sf->selector, var->selector);
3170 vmx->rmode.tr.selector = var->selector;
3171 vmx->rmode.tr.base = var->base;
3172 vmx->rmode.tr.limit = var->limit;
3173 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3174 return;
3175 }
3176 vmcs_writel(sf->base, var->base);
3177 vmcs_write32(sf->limit, var->limit);
3178 vmcs_write16(sf->selector, var->selector);
3179 if (vmx->rmode.vm86_active && var->s) {
3180 /*
3181 * Hack real-mode segments into vm86 compatibility.
3182 */
3183 if (var->base == 0xffff0000 && var->selector == 0xf000)
3184 vmcs_writel(sf->base, 0xf0000);
3185 ar = 0xf3;
3186 } else
3187 ar = vmx_segment_access_rights(var);
3188
3189 /*
3190 * Fix the "Accessed" bit in AR field of segment registers for older
3191 * qemu binaries.
3192 * IA32 arch specifies that at the time of processor reset the
3193 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3194 * is setting it to 0 in the usedland code. This causes invalid guest
3195 * state vmexit when "unrestricted guest" mode is turned on.
3196 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3197 * tree. Newer qemu binaries with that qemu fix would not need this
3198 * kvm hack.
3199 */
3200 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3201 ar |= 0x1; /* Accessed */
3202
3203 vmcs_write32(sf->ar_bytes, ar);
3204 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3205 }
3206
3207 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3208 {
3209 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3210
3211 *db = (ar >> 14) & 1;
3212 *l = (ar >> 13) & 1;
3213 }
3214
3215 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3216 {
3217 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3218 dt->address = vmcs_readl(GUEST_IDTR_BASE);
3219 }
3220
3221 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3222 {
3223 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3224 vmcs_writel(GUEST_IDTR_BASE, dt->address);
3225 }
3226
3227 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3228 {
3229 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3230 dt->address = vmcs_readl(GUEST_GDTR_BASE);
3231 }
3232
3233 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3234 {
3235 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3236 vmcs_writel(GUEST_GDTR_BASE, dt->address);
3237 }
3238
3239 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3240 {
3241 struct kvm_segment var;
3242 u32 ar;
3243
3244 vmx_get_segment(vcpu, &var, seg);
3245 ar = vmx_segment_access_rights(&var);
3246
3247 if (var.base != (var.selector << 4))
3248 return false;
3249 if (var.limit != 0xffff)
3250 return false;
3251 if (ar != 0xf3)
3252 return false;
3253
3254 return true;
3255 }
3256
3257 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3258 {
3259 struct kvm_segment cs;
3260 unsigned int cs_rpl;
3261
3262 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3263 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3264
3265 if (cs.unusable)
3266 return false;
3267 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3268 return false;
3269 if (!cs.s)
3270 return false;
3271 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3272 if (cs.dpl > cs_rpl)
3273 return false;
3274 } else {
3275 if (cs.dpl != cs_rpl)
3276 return false;
3277 }
3278 if (!cs.present)
3279 return false;
3280
3281 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3282 return true;
3283 }
3284
3285 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3286 {
3287 struct kvm_segment ss;
3288 unsigned int ss_rpl;
3289
3290 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3291 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3292
3293 if (ss.unusable)
3294 return true;
3295 if (ss.type != 3 && ss.type != 7)
3296 return false;
3297 if (!ss.s)
3298 return false;
3299 if (ss.dpl != ss_rpl) /* DPL != RPL */
3300 return false;
3301 if (!ss.present)
3302 return false;
3303
3304 return true;
3305 }
3306
3307 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3308 {
3309 struct kvm_segment var;
3310 unsigned int rpl;
3311
3312 vmx_get_segment(vcpu, &var, seg);
3313 rpl = var.selector & SELECTOR_RPL_MASK;
3314
3315 if (var.unusable)
3316 return true;
3317 if (!var.s)
3318 return false;
3319 if (!var.present)
3320 return false;
3321 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3322 if (var.dpl < rpl) /* DPL < RPL */
3323 return false;
3324 }
3325
3326 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3327 * rights flags
3328 */
3329 return true;
3330 }
3331
3332 static bool tr_valid(struct kvm_vcpu *vcpu)
3333 {
3334 struct kvm_segment tr;
3335
3336 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3337
3338 if (tr.unusable)
3339 return false;
3340 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3341 return false;
3342 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3343 return false;
3344 if (!tr.present)
3345 return false;
3346
3347 return true;
3348 }
3349
3350 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3351 {
3352 struct kvm_segment ldtr;
3353
3354 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3355
3356 if (ldtr.unusable)
3357 return true;
3358 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3359 return false;
3360 if (ldtr.type != 2)
3361 return false;
3362 if (!ldtr.present)
3363 return false;
3364
3365 return true;
3366 }
3367
3368 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3369 {
3370 struct kvm_segment cs, ss;
3371
3372 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3373 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3374
3375 return ((cs.selector & SELECTOR_RPL_MASK) ==
3376 (ss.selector & SELECTOR_RPL_MASK));
3377 }
3378
3379 /*
3380 * Check if guest state is valid. Returns true if valid, false if
3381 * not.
3382 * We assume that registers are always usable
3383 */
3384 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3385 {
3386 /* real mode guest state checks */
3387 if (!is_protmode(vcpu)) {
3388 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3389 return false;
3390 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3391 return false;
3392 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3393 return false;
3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3395 return false;
3396 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3397 return false;
3398 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3399 return false;
3400 } else {
3401 /* protected mode guest state checks */
3402 if (!cs_ss_rpl_check(vcpu))
3403 return false;
3404 if (!code_segment_valid(vcpu))
3405 return false;
3406 if (!stack_segment_valid(vcpu))
3407 return false;
3408 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3409 return false;
3410 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3411 return false;
3412 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3413 return false;
3414 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3415 return false;
3416 if (!tr_valid(vcpu))
3417 return false;
3418 if (!ldtr_valid(vcpu))
3419 return false;
3420 }
3421 /* TODO:
3422 * - Add checks on RIP
3423 * - Add checks on RFLAGS
3424 */
3425
3426 return true;
3427 }
3428
3429 static int init_rmode_tss(struct kvm *kvm)
3430 {
3431 gfn_t fn;
3432 u16 data = 0;
3433 int r, idx, ret = 0;
3434
3435 idx = srcu_read_lock(&kvm->srcu);
3436 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3437 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3438 if (r < 0)
3439 goto out;
3440 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3441 r = kvm_write_guest_page(kvm, fn++, &data,
3442 TSS_IOPB_BASE_OFFSET, sizeof(u16));
3443 if (r < 0)
3444 goto out;
3445 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3446 if (r < 0)
3447 goto out;
3448 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3449 if (r < 0)
3450 goto out;
3451 data = ~0;
3452 r = kvm_write_guest_page(kvm, fn, &data,
3453 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3454 sizeof(u8));
3455 if (r < 0)
3456 goto out;
3457
3458 ret = 1;
3459 out:
3460 srcu_read_unlock(&kvm->srcu, idx);
3461 return ret;
3462 }
3463
3464 static int init_rmode_identity_map(struct kvm *kvm)
3465 {
3466 int i, idx, r, ret;
3467 pfn_t identity_map_pfn;
3468 u32 tmp;
3469
3470 if (!enable_ept)
3471 return 1;
3472 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3473 printk(KERN_ERR "EPT: identity-mapping pagetable "
3474 "haven't been allocated!\n");
3475 return 0;
3476 }
3477 if (likely(kvm->arch.ept_identity_pagetable_done))
3478 return 1;
3479 ret = 0;
3480 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3481 idx = srcu_read_lock(&kvm->srcu);
3482 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3483 if (r < 0)
3484 goto out;
3485 /* Set up identity-mapping pagetable for EPT in real mode */
3486 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3487 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3488 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3489 r = kvm_write_guest_page(kvm, identity_map_pfn,
3490 &tmp, i * sizeof(tmp), sizeof(tmp));
3491 if (r < 0)
3492 goto out;
3493 }
3494 kvm->arch.ept_identity_pagetable_done = true;
3495 ret = 1;
3496 out:
3497 srcu_read_unlock(&kvm->srcu, idx);
3498 return ret;
3499 }
3500
3501 static void seg_setup(int seg)
3502 {
3503 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3504 unsigned int ar;
3505
3506 vmcs_write16(sf->selector, 0);
3507 vmcs_writel(sf->base, 0);
3508 vmcs_write32(sf->limit, 0xffff);
3509 if (enable_unrestricted_guest) {
3510 ar = 0x93;
3511 if (seg == VCPU_SREG_CS)
3512 ar |= 0x08; /* code segment */
3513 } else
3514 ar = 0xf3;
3515
3516 vmcs_write32(sf->ar_bytes, ar);
3517 }
3518
3519 static int alloc_apic_access_page(struct kvm *kvm)
3520 {
3521 struct kvm_userspace_memory_region kvm_userspace_mem;
3522 int r = 0;
3523
3524 mutex_lock(&kvm->slots_lock);
3525 if (kvm->arch.apic_access_page)
3526 goto out;
3527 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3528 kvm_userspace_mem.flags = 0;
3529 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3530 kvm_userspace_mem.memory_size = PAGE_SIZE;
3531 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3532 if (r)
3533 goto out;
3534
3535 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3536 out:
3537 mutex_unlock(&kvm->slots_lock);
3538 return r;
3539 }
3540
3541 static int alloc_identity_pagetable(struct kvm *kvm)
3542 {
3543 struct kvm_userspace_memory_region kvm_userspace_mem;
3544 int r = 0;
3545
3546 mutex_lock(&kvm->slots_lock);
3547 if (kvm->arch.ept_identity_pagetable)
3548 goto out;
3549 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3550 kvm_userspace_mem.flags = 0;
3551 kvm_userspace_mem.guest_phys_addr =
3552 kvm->arch.ept_identity_map_addr;
3553 kvm_userspace_mem.memory_size = PAGE_SIZE;
3554 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3555 if (r)
3556 goto out;
3557
3558 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3559 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3560 out:
3561 mutex_unlock(&kvm->slots_lock);
3562 return r;
3563 }
3564
3565 static void allocate_vpid(struct vcpu_vmx *vmx)
3566 {
3567 int vpid;
3568
3569 vmx->vpid = 0;
3570 if (!enable_vpid)
3571 return;
3572 spin_lock(&vmx_vpid_lock);
3573 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3574 if (vpid < VMX_NR_VPIDS) {
3575 vmx->vpid = vpid;
3576 __set_bit(vpid, vmx_vpid_bitmap);
3577 }
3578 spin_unlock(&vmx_vpid_lock);
3579 }
3580
3581 static void free_vpid(struct vcpu_vmx *vmx)
3582 {
3583 if (!enable_vpid)
3584 return;
3585 spin_lock(&vmx_vpid_lock);
3586 if (vmx->vpid != 0)
3587 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3588 spin_unlock(&vmx_vpid_lock);
3589 }
3590
3591 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3592 {
3593 int f = sizeof(unsigned long);
3594
3595 if (!cpu_has_vmx_msr_bitmap())
3596 return;
3597
3598 /*
3599 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3600 * have the write-low and read-high bitmap offsets the wrong way round.
3601 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3602 */
3603 if (msr <= 0x1fff) {
3604 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3605 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3606 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3607 msr &= 0x1fff;
3608 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3609 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3610 }
3611 }
3612
3613 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3614 {
3615 if (!longmode_only)
3616 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3617 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3618 }
3619
3620 /*
3621 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3622 * will not change in the lifetime of the guest.
3623 * Note that host-state that does change is set elsewhere. E.g., host-state
3624 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3625 */
3626 static void vmx_set_constant_host_state(void)
3627 {
3628 u32 low32, high32;
3629 unsigned long tmpl;
3630 struct desc_ptr dt;
3631
3632 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3633 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3634 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3635
3636 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3637 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3638 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3639 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3640 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3641
3642 native_store_idt(&dt);
3643 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3644
3645 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3646 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3647
3648 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3649 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3650 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3651 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3652
3653 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3654 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3655 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3656 }
3657 }
3658
3659 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3660 {
3661 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3662 if (enable_ept)
3663 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3664 if (is_guest_mode(&vmx->vcpu))
3665 vmx->vcpu.arch.cr4_guest_owned_bits &=
3666 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3667 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3668 }
3669
3670 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3671 {
3672 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3673 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3674 exec_control &= ~CPU_BASED_TPR_SHADOW;
3675 #ifdef CONFIG_X86_64
3676 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3677 CPU_BASED_CR8_LOAD_EXITING;
3678 #endif
3679 }
3680 if (!enable_ept)
3681 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3682 CPU_BASED_CR3_LOAD_EXITING |
3683 CPU_BASED_INVLPG_EXITING;
3684 return exec_control;
3685 }
3686
3687 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3688 {
3689 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3690 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3691 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3692 if (vmx->vpid == 0)
3693 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3694 if (!enable_ept) {
3695 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3696 enable_unrestricted_guest = 0;
3697 }
3698 if (!enable_unrestricted_guest)
3699 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3700 if (!ple_gap)
3701 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3702 return exec_control;
3703 }
3704
3705 static void ept_set_mmio_spte_mask(void)
3706 {
3707 /*
3708 * EPT Misconfigurations can be generated if the value of bits 2:0
3709 * of an EPT paging-structure entry is 110b (write/execute).
3710 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3711 * spte.
3712 */
3713 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3714 }
3715
3716 /*
3717 * Sets up the vmcs for emulated real mode.
3718 */
3719 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3720 {
3721 #ifdef CONFIG_X86_64
3722 unsigned long a;
3723 #endif
3724 int i;
3725
3726 /* I/O */
3727 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3728 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3729
3730 if (cpu_has_vmx_msr_bitmap())
3731 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3732
3733 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3734
3735 /* Control */
3736 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3737 vmcs_config.pin_based_exec_ctrl);
3738
3739 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3740
3741 if (cpu_has_secondary_exec_ctrls()) {
3742 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3743 vmx_secondary_exec_control(vmx));
3744 }
3745
3746 if (ple_gap) {
3747 vmcs_write32(PLE_GAP, ple_gap);
3748 vmcs_write32(PLE_WINDOW, ple_window);
3749 }
3750
3751 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3752 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3753 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3754
3755 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3756 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
3757 vmx_set_constant_host_state();
3758 #ifdef CONFIG_X86_64
3759 rdmsrl(MSR_FS_BASE, a);
3760 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3761 rdmsrl(MSR_GS_BASE, a);
3762 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3763 #else
3764 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3765 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3766 #endif
3767
3768 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3769 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3770 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3771 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3772 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3773
3774 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3775 u32 msr_low, msr_high;
3776 u64 host_pat;
3777 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3778 host_pat = msr_low | ((u64) msr_high << 32);
3779 /* Write the default value follow host pat */
3780 vmcs_write64(GUEST_IA32_PAT, host_pat);
3781 /* Keep arch.pat sync with GUEST_IA32_PAT */
3782 vmx->vcpu.arch.pat = host_pat;
3783 }
3784
3785 for (i = 0; i < NR_VMX_MSR; ++i) {
3786 u32 index = vmx_msr_index[i];
3787 u32 data_low, data_high;
3788 int j = vmx->nmsrs;
3789
3790 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3791 continue;
3792 if (wrmsr_safe(index, data_low, data_high) < 0)
3793 continue;
3794 vmx->guest_msrs[j].index = i;
3795 vmx->guest_msrs[j].data = 0;
3796 vmx->guest_msrs[j].mask = -1ull;
3797 ++vmx->nmsrs;
3798 }
3799
3800 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3801
3802 /* 22.2.1, 20.8.1 */
3803 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3804
3805 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3806 set_cr4_guest_host_mask(vmx);
3807
3808 kvm_write_tsc(&vmx->vcpu, 0);
3809
3810 return 0;
3811 }
3812
3813 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3814 {
3815 struct vcpu_vmx *vmx = to_vmx(vcpu);
3816 u64 msr;
3817 int ret;
3818
3819 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3820
3821 vmx->rmode.vm86_active = 0;
3822
3823 vmx->soft_vnmi_blocked = 0;
3824
3825 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3826 kvm_set_cr8(&vmx->vcpu, 0);
3827 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3828 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3829 msr |= MSR_IA32_APICBASE_BSP;
3830 kvm_set_apic_base(&vmx->vcpu, msr);
3831
3832 ret = fx_init(&vmx->vcpu);
3833 if (ret != 0)
3834 goto out;
3835
3836 vmx_segment_cache_clear(vmx);
3837
3838 seg_setup(VCPU_SREG_CS);
3839 /*
3840 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3841 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3842 */
3843 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3844 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3845 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3846 } else {
3847 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3848 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3849 }
3850
3851 seg_setup(VCPU_SREG_DS);
3852 seg_setup(VCPU_SREG_ES);
3853 seg_setup(VCPU_SREG_FS);
3854 seg_setup(VCPU_SREG_GS);
3855 seg_setup(VCPU_SREG_SS);
3856
3857 vmcs_write16(GUEST_TR_SELECTOR, 0);
3858 vmcs_writel(GUEST_TR_BASE, 0);
3859 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3860 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3861
3862 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3863 vmcs_writel(GUEST_LDTR_BASE, 0);
3864 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3865 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3866
3867 vmcs_write32(GUEST_SYSENTER_CS, 0);
3868 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3869 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3870
3871 vmcs_writel(GUEST_RFLAGS, 0x02);
3872 if (kvm_vcpu_is_bsp(&vmx->vcpu))
3873 kvm_rip_write(vcpu, 0xfff0);
3874 else
3875 kvm_rip_write(vcpu, 0);
3876 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3877
3878 vmcs_writel(GUEST_DR7, 0x400);
3879
3880 vmcs_writel(GUEST_GDTR_BASE, 0);
3881 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3882
3883 vmcs_writel(GUEST_IDTR_BASE, 0);
3884 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3885
3886 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3887 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3888 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3889
3890 /* Special registers */
3891 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3892
3893 setup_msrs(vmx);
3894
3895 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3896
3897 if (cpu_has_vmx_tpr_shadow()) {
3898 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3899 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3900 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3901 __pa(vmx->vcpu.arch.apic->regs));
3902 vmcs_write32(TPR_THRESHOLD, 0);
3903 }
3904
3905 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3906 vmcs_write64(APIC_ACCESS_ADDR,
3907 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3908
3909 if (vmx->vpid != 0)
3910 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3911
3912 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3913 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3914 vmx_set_cr4(&vmx->vcpu, 0);
3915 vmx_set_efer(&vmx->vcpu, 0);
3916 vmx_fpu_activate(&vmx->vcpu);
3917 update_exception_bitmap(&vmx->vcpu);
3918
3919 vpid_sync_context(vmx);
3920
3921 ret = 0;
3922
3923 /* HACK: Don't enable emulation on guest boot/reset */
3924 vmx->emulation_required = 0;
3925
3926 out:
3927 return ret;
3928 }
3929
3930 /*
3931 * In nested virtualization, check if L1 asked to exit on external interrupts.
3932 * For most existing hypervisors, this will always return true.
3933 */
3934 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3935 {
3936 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3937 PIN_BASED_EXT_INTR_MASK;
3938 }
3939
3940 static void enable_irq_window(struct kvm_vcpu *vcpu)
3941 {
3942 u32 cpu_based_vm_exec_control;
3943 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3944 /*
3945 * We get here if vmx_interrupt_allowed() said we can't
3946 * inject to L1 now because L2 must run. Ask L2 to exit
3947 * right after entry, so we can inject to L1 more promptly.
3948 */
3949 kvm_make_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
3950 return;
3951 }
3952
3953 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3954 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3955 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3956 }
3957
3958 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3959 {
3960 u32 cpu_based_vm_exec_control;
3961
3962 if (!cpu_has_virtual_nmis()) {
3963 enable_irq_window(vcpu);
3964 return;
3965 }
3966
3967 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3968 enable_irq_window(vcpu);
3969 return;
3970 }
3971 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3972 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3973 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3974 }
3975
3976 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3977 {
3978 struct vcpu_vmx *vmx = to_vmx(vcpu);
3979 uint32_t intr;
3980 int irq = vcpu->arch.interrupt.nr;
3981
3982 trace_kvm_inj_virq(irq);
3983
3984 ++vcpu->stat.irq_injections;
3985 if (vmx->rmode.vm86_active) {
3986 int inc_eip = 0;
3987 if (vcpu->arch.interrupt.soft)
3988 inc_eip = vcpu->arch.event_exit_inst_len;
3989 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3990 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3991 return;
3992 }
3993 intr = irq | INTR_INFO_VALID_MASK;
3994 if (vcpu->arch.interrupt.soft) {
3995 intr |= INTR_TYPE_SOFT_INTR;
3996 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3997 vmx->vcpu.arch.event_exit_inst_len);
3998 } else
3999 intr |= INTR_TYPE_EXT_INTR;
4000 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4001 vmx_clear_hlt(vcpu);
4002 }
4003
4004 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4005 {
4006 struct vcpu_vmx *vmx = to_vmx(vcpu);
4007
4008 if (is_guest_mode(vcpu))
4009 return;
4010
4011 if (!cpu_has_virtual_nmis()) {
4012 /*
4013 * Tracking the NMI-blocked state in software is built upon
4014 * finding the next open IRQ window. This, in turn, depends on
4015 * well-behaving guests: They have to keep IRQs disabled at
4016 * least as long as the NMI handler runs. Otherwise we may
4017 * cause NMI nesting, maybe breaking the guest. But as this is
4018 * highly unlikely, we can live with the residual risk.
4019 */
4020 vmx->soft_vnmi_blocked = 1;
4021 vmx->vnmi_blocked_time = 0;
4022 }
4023
4024 ++vcpu->stat.nmi_injections;
4025 vmx->nmi_known_unmasked = false;
4026 if (vmx->rmode.vm86_active) {
4027 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4028 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4029 return;
4030 }
4031 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4032 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4033 vmx_clear_hlt(vcpu);
4034 }
4035
4036 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4037 {
4038 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4039 return 0;
4040
4041 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4042 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4043 | GUEST_INTR_STATE_NMI));
4044 }
4045
4046 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4047 {
4048 if (!cpu_has_virtual_nmis())
4049 return to_vmx(vcpu)->soft_vnmi_blocked;
4050 if (to_vmx(vcpu)->nmi_known_unmasked)
4051 return false;
4052 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4053 }
4054
4055 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4056 {
4057 struct vcpu_vmx *vmx = to_vmx(vcpu);
4058
4059 if (!cpu_has_virtual_nmis()) {
4060 if (vmx->soft_vnmi_blocked != masked) {
4061 vmx->soft_vnmi_blocked = masked;
4062 vmx->vnmi_blocked_time = 0;
4063 }
4064 } else {
4065 vmx->nmi_known_unmasked = !masked;
4066 if (masked)
4067 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4068 GUEST_INTR_STATE_NMI);
4069 else
4070 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4071 GUEST_INTR_STATE_NMI);
4072 }
4073 }
4074
4075 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4076 {
4077 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4078 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4079 if (to_vmx(vcpu)->nested.nested_run_pending ||
4080 (vmcs12->idt_vectoring_info_field &
4081 VECTORING_INFO_VALID_MASK))
4082 return 0;
4083 nested_vmx_vmexit(vcpu);
4084 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4085 vmcs12->vm_exit_intr_info = 0;
4086 /* fall through to normal code, but now in L1, not L2 */
4087 }
4088
4089 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4090 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4091 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4092 }
4093
4094 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4095 {
4096 int ret;
4097 struct kvm_userspace_memory_region tss_mem = {
4098 .slot = TSS_PRIVATE_MEMSLOT,
4099 .guest_phys_addr = addr,
4100 .memory_size = PAGE_SIZE * 3,
4101 .flags = 0,
4102 };
4103
4104 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4105 if (ret)
4106 return ret;
4107 kvm->arch.tss_addr = addr;
4108 if (!init_rmode_tss(kvm))
4109 return -ENOMEM;
4110
4111 return 0;
4112 }
4113
4114 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4115 int vec, u32 err_code)
4116 {
4117 /*
4118 * Instruction with address size override prefix opcode 0x67
4119 * Cause the #SS fault with 0 error code in VM86 mode.
4120 */
4121 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4122 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4123 return 1;
4124 /*
4125 * Forward all other exceptions that are valid in real mode.
4126 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4127 * the required debugging infrastructure rework.
4128 */
4129 switch (vec) {
4130 case DB_VECTOR:
4131 if (vcpu->guest_debug &
4132 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4133 return 0;
4134 kvm_queue_exception(vcpu, vec);
4135 return 1;
4136 case BP_VECTOR:
4137 /*
4138 * Update instruction length as we may reinject the exception
4139 * from user space while in guest debugging mode.
4140 */
4141 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4142 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4143 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4144 return 0;
4145 /* fall through */
4146 case DE_VECTOR:
4147 case OF_VECTOR:
4148 case BR_VECTOR:
4149 case UD_VECTOR:
4150 case DF_VECTOR:
4151 case SS_VECTOR:
4152 case GP_VECTOR:
4153 case MF_VECTOR:
4154 kvm_queue_exception(vcpu, vec);
4155 return 1;
4156 }
4157 return 0;
4158 }
4159
4160 /*
4161 * Trigger machine check on the host. We assume all the MSRs are already set up
4162 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4163 * We pass a fake environment to the machine check handler because we want
4164 * the guest to be always treated like user space, no matter what context
4165 * it used internally.
4166 */
4167 static void kvm_machine_check(void)
4168 {
4169 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4170 struct pt_regs regs = {
4171 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4172 .flags = X86_EFLAGS_IF,
4173 };
4174
4175 do_machine_check(&regs, 0);
4176 #endif
4177 }
4178
4179 static int handle_machine_check(struct kvm_vcpu *vcpu)
4180 {
4181 /* already handled by vcpu_run */
4182 return 1;
4183 }
4184
4185 static int handle_exception(struct kvm_vcpu *vcpu)
4186 {
4187 struct vcpu_vmx *vmx = to_vmx(vcpu);
4188 struct kvm_run *kvm_run = vcpu->run;
4189 u32 intr_info, ex_no, error_code;
4190 unsigned long cr2, rip, dr6;
4191 u32 vect_info;
4192 enum emulation_result er;
4193
4194 vect_info = vmx->idt_vectoring_info;
4195 intr_info = vmx->exit_intr_info;
4196
4197 if (is_machine_check(intr_info))
4198 return handle_machine_check(vcpu);
4199
4200 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4201 !is_page_fault(intr_info)) {
4202 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4203 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4204 vcpu->run->internal.ndata = 2;
4205 vcpu->run->internal.data[0] = vect_info;
4206 vcpu->run->internal.data[1] = intr_info;
4207 return 0;
4208 }
4209
4210 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4211 return 1; /* already handled by vmx_vcpu_run() */
4212
4213 if (is_no_device(intr_info)) {
4214 vmx_fpu_activate(vcpu);
4215 return 1;
4216 }
4217
4218 if (is_invalid_opcode(intr_info)) {
4219 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4220 if (er != EMULATE_DONE)
4221 kvm_queue_exception(vcpu, UD_VECTOR);
4222 return 1;
4223 }
4224
4225 error_code = 0;
4226 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4227 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4228 if (is_page_fault(intr_info)) {
4229 /* EPT won't cause page fault directly */
4230 BUG_ON(enable_ept);
4231 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4232 trace_kvm_page_fault(cr2, error_code);
4233
4234 if (kvm_event_needs_reinjection(vcpu))
4235 kvm_mmu_unprotect_page_virt(vcpu, cr2);
4236 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4237 }
4238
4239 if (vmx->rmode.vm86_active &&
4240 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4241 error_code)) {
4242 if (vcpu->arch.halt_request) {
4243 vcpu->arch.halt_request = 0;
4244 return kvm_emulate_halt(vcpu);
4245 }
4246 return 1;
4247 }
4248
4249 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4250 switch (ex_no) {
4251 case DB_VECTOR:
4252 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4253 if (!(vcpu->guest_debug &
4254 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4255 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4256 kvm_queue_exception(vcpu, DB_VECTOR);
4257 return 1;
4258 }
4259 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4260 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4261 /* fall through */
4262 case BP_VECTOR:
4263 /*
4264 * Update instruction length as we may reinject #BP from
4265 * user space while in guest debugging mode. Reading it for
4266 * #DB as well causes no harm, it is not used in that case.
4267 */
4268 vmx->vcpu.arch.event_exit_inst_len =
4269 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4270 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4271 rip = kvm_rip_read(vcpu);
4272 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4273 kvm_run->debug.arch.exception = ex_no;
4274 break;
4275 default:
4276 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4277 kvm_run->ex.exception = ex_no;
4278 kvm_run->ex.error_code = error_code;
4279 break;
4280 }
4281 return 0;
4282 }
4283
4284 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4285 {
4286 ++vcpu->stat.irq_exits;
4287 return 1;
4288 }
4289
4290 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4291 {
4292 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4293 return 0;
4294 }
4295
4296 static int handle_io(struct kvm_vcpu *vcpu)
4297 {
4298 unsigned long exit_qualification;
4299 int size, in, string;
4300 unsigned port;
4301
4302 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4303 string = (exit_qualification & 16) != 0;
4304 in = (exit_qualification & 8) != 0;
4305
4306 ++vcpu->stat.io_exits;
4307
4308 if (string || in)
4309 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4310
4311 port = exit_qualification >> 16;
4312 size = (exit_qualification & 7) + 1;
4313 skip_emulated_instruction(vcpu);
4314
4315 return kvm_fast_pio_out(vcpu, size, port);
4316 }
4317
4318 static void
4319 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4320 {
4321 /*
4322 * Patch in the VMCALL instruction:
4323 */
4324 hypercall[0] = 0x0f;
4325 hypercall[1] = 0x01;
4326 hypercall[2] = 0xc1;
4327 }
4328
4329 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4330 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4331 {
4332 if (to_vmx(vcpu)->nested.vmxon &&
4333 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4334 return 1;
4335
4336 if (is_guest_mode(vcpu)) {
4337 /*
4338 * We get here when L2 changed cr0 in a way that did not change
4339 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4340 * but did change L0 shadowed bits. This can currently happen
4341 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4342 * loading) while pretending to allow the guest to change it.
4343 */
4344 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4345 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4346 return 1;
4347 vmcs_writel(CR0_READ_SHADOW, val);
4348 return 0;
4349 } else
4350 return kvm_set_cr0(vcpu, val);
4351 }
4352
4353 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4354 {
4355 if (is_guest_mode(vcpu)) {
4356 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4357 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4358 return 1;
4359 vmcs_writel(CR4_READ_SHADOW, val);
4360 return 0;
4361 } else
4362 return kvm_set_cr4(vcpu, val);
4363 }
4364
4365 /* called to set cr0 as approriate for clts instruction exit. */
4366 static void handle_clts(struct kvm_vcpu *vcpu)
4367 {
4368 if (is_guest_mode(vcpu)) {
4369 /*
4370 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4371 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4372 * just pretend it's off (also in arch.cr0 for fpu_activate).
4373 */
4374 vmcs_writel(CR0_READ_SHADOW,
4375 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4376 vcpu->arch.cr0 &= ~X86_CR0_TS;
4377 } else
4378 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4379 }
4380
4381 static int handle_cr(struct kvm_vcpu *vcpu)
4382 {
4383 unsigned long exit_qualification, val;
4384 int cr;
4385 int reg;
4386 int err;
4387
4388 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4389 cr = exit_qualification & 15;
4390 reg = (exit_qualification >> 8) & 15;
4391 switch ((exit_qualification >> 4) & 3) {
4392 case 0: /* mov to cr */
4393 val = kvm_register_read(vcpu, reg);
4394 trace_kvm_cr_write(cr, val);
4395 switch (cr) {
4396 case 0:
4397 err = handle_set_cr0(vcpu, val);
4398 kvm_complete_insn_gp(vcpu, err);
4399 return 1;
4400 case 3:
4401 err = kvm_set_cr3(vcpu, val);
4402 kvm_complete_insn_gp(vcpu, err);
4403 return 1;
4404 case 4:
4405 err = handle_set_cr4(vcpu, val);
4406 kvm_complete_insn_gp(vcpu, err);
4407 return 1;
4408 case 8: {
4409 u8 cr8_prev = kvm_get_cr8(vcpu);
4410 u8 cr8 = kvm_register_read(vcpu, reg);
4411 err = kvm_set_cr8(vcpu, cr8);
4412 kvm_complete_insn_gp(vcpu, err);
4413 if (irqchip_in_kernel(vcpu->kvm))
4414 return 1;
4415 if (cr8_prev <= cr8)
4416 return 1;
4417 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4418 return 0;
4419 }
4420 };
4421 break;
4422 case 2: /* clts */
4423 handle_clts(vcpu);
4424 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4425 skip_emulated_instruction(vcpu);
4426 vmx_fpu_activate(vcpu);
4427 return 1;
4428 case 1: /*mov from cr*/
4429 switch (cr) {
4430 case 3:
4431 val = kvm_read_cr3(vcpu);
4432 kvm_register_write(vcpu, reg, val);
4433 trace_kvm_cr_read(cr, val);
4434 skip_emulated_instruction(vcpu);
4435 return 1;
4436 case 8:
4437 val = kvm_get_cr8(vcpu);
4438 kvm_register_write(vcpu, reg, val);
4439 trace_kvm_cr_read(cr, val);
4440 skip_emulated_instruction(vcpu);
4441 return 1;
4442 }
4443 break;
4444 case 3: /* lmsw */
4445 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4446 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4447 kvm_lmsw(vcpu, val);
4448
4449 skip_emulated_instruction(vcpu);
4450 return 1;
4451 default:
4452 break;
4453 }
4454 vcpu->run->exit_reason = 0;
4455 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4456 (int)(exit_qualification >> 4) & 3, cr);
4457 return 0;
4458 }
4459
4460 static int handle_dr(struct kvm_vcpu *vcpu)
4461 {
4462 unsigned long exit_qualification;
4463 int dr, reg;
4464
4465 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4466 if (!kvm_require_cpl(vcpu, 0))
4467 return 1;
4468 dr = vmcs_readl(GUEST_DR7);
4469 if (dr & DR7_GD) {
4470 /*
4471 * As the vm-exit takes precedence over the debug trap, we
4472 * need to emulate the latter, either for the host or the
4473 * guest debugging itself.
4474 */
4475 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4476 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4477 vcpu->run->debug.arch.dr7 = dr;
4478 vcpu->run->debug.arch.pc =
4479 vmcs_readl(GUEST_CS_BASE) +
4480 vmcs_readl(GUEST_RIP);
4481 vcpu->run->debug.arch.exception = DB_VECTOR;
4482 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4483 return 0;
4484 } else {
4485 vcpu->arch.dr7 &= ~DR7_GD;
4486 vcpu->arch.dr6 |= DR6_BD;
4487 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4488 kvm_queue_exception(vcpu, DB_VECTOR);
4489 return 1;
4490 }
4491 }
4492
4493 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4494 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4495 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4496 if (exit_qualification & TYPE_MOV_FROM_DR) {
4497 unsigned long val;
4498 if (!kvm_get_dr(vcpu, dr, &val))
4499 kvm_register_write(vcpu, reg, val);
4500 } else
4501 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4502 skip_emulated_instruction(vcpu);
4503 return 1;
4504 }
4505
4506 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4507 {
4508 vmcs_writel(GUEST_DR7, val);
4509 }
4510
4511 static int handle_cpuid(struct kvm_vcpu *vcpu)
4512 {
4513 kvm_emulate_cpuid(vcpu);
4514 return 1;
4515 }
4516
4517 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4518 {
4519 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4520 u64 data;
4521
4522 if (vmx_get_msr(vcpu, ecx, &data)) {
4523 trace_kvm_msr_read_ex(ecx);
4524 kvm_inject_gp(vcpu, 0);
4525 return 1;
4526 }
4527
4528 trace_kvm_msr_read(ecx, data);
4529
4530 /* FIXME: handling of bits 32:63 of rax, rdx */
4531 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4532 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4533 skip_emulated_instruction(vcpu);
4534 return 1;
4535 }
4536
4537 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4538 {
4539 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4540 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4541 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4542
4543 if (vmx_set_msr(vcpu, ecx, data) != 0) {
4544 trace_kvm_msr_write_ex(ecx, data);
4545 kvm_inject_gp(vcpu, 0);
4546 return 1;
4547 }
4548
4549 trace_kvm_msr_write(ecx, data);
4550 skip_emulated_instruction(vcpu);
4551 return 1;
4552 }
4553
4554 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4555 {
4556 kvm_make_request(KVM_REQ_EVENT, vcpu);
4557 return 1;
4558 }
4559
4560 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4561 {
4562 u32 cpu_based_vm_exec_control;
4563
4564 /* clear pending irq */
4565 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4566 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4567 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4568
4569 kvm_make_request(KVM_REQ_EVENT, vcpu);
4570
4571 ++vcpu->stat.irq_window_exits;
4572
4573 /*
4574 * If the user space waits to inject interrupts, exit as soon as
4575 * possible
4576 */
4577 if (!irqchip_in_kernel(vcpu->kvm) &&
4578 vcpu->run->request_interrupt_window &&
4579 !kvm_cpu_has_interrupt(vcpu)) {
4580 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4581 return 0;
4582 }
4583 return 1;
4584 }
4585
4586 static int handle_halt(struct kvm_vcpu *vcpu)
4587 {
4588 skip_emulated_instruction(vcpu);
4589 return kvm_emulate_halt(vcpu);
4590 }
4591
4592 static int handle_vmcall(struct kvm_vcpu *vcpu)
4593 {
4594 skip_emulated_instruction(vcpu);
4595 kvm_emulate_hypercall(vcpu);
4596 return 1;
4597 }
4598
4599 static int handle_invd(struct kvm_vcpu *vcpu)
4600 {
4601 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4602 }
4603
4604 static int handle_invlpg(struct kvm_vcpu *vcpu)
4605 {
4606 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4607
4608 kvm_mmu_invlpg(vcpu, exit_qualification);
4609 skip_emulated_instruction(vcpu);
4610 return 1;
4611 }
4612
4613 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4614 {
4615 skip_emulated_instruction(vcpu);
4616 kvm_emulate_wbinvd(vcpu);
4617 return 1;
4618 }
4619
4620 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4621 {
4622 u64 new_bv = kvm_read_edx_eax(vcpu);
4623 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4624
4625 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4626 skip_emulated_instruction(vcpu);
4627 return 1;
4628 }
4629
4630 static int handle_apic_access(struct kvm_vcpu *vcpu)
4631 {
4632 if (likely(fasteoi)) {
4633 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4634 int access_type, offset;
4635
4636 access_type = exit_qualification & APIC_ACCESS_TYPE;
4637 offset = exit_qualification & APIC_ACCESS_OFFSET;
4638 /*
4639 * Sane guest uses MOV to write EOI, with written value
4640 * not cared. So make a short-circuit here by avoiding
4641 * heavy instruction emulation.
4642 */
4643 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4644 (offset == APIC_EOI)) {
4645 kvm_lapic_set_eoi(vcpu);
4646 skip_emulated_instruction(vcpu);
4647 return 1;
4648 }
4649 }
4650 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4651 }
4652
4653 static int handle_task_switch(struct kvm_vcpu *vcpu)
4654 {
4655 struct vcpu_vmx *vmx = to_vmx(vcpu);
4656 unsigned long exit_qualification;
4657 bool has_error_code = false;
4658 u32 error_code = 0;
4659 u16 tss_selector;
4660 int reason, type, idt_v;
4661
4662 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4663 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4664
4665 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4666
4667 reason = (u32)exit_qualification >> 30;
4668 if (reason == TASK_SWITCH_GATE && idt_v) {
4669 switch (type) {
4670 case INTR_TYPE_NMI_INTR:
4671 vcpu->arch.nmi_injected = false;
4672 vmx_set_nmi_mask(vcpu, true);
4673 break;
4674 case INTR_TYPE_EXT_INTR:
4675 case INTR_TYPE_SOFT_INTR:
4676 kvm_clear_interrupt_queue(vcpu);
4677 break;
4678 case INTR_TYPE_HARD_EXCEPTION:
4679 if (vmx->idt_vectoring_info &
4680 VECTORING_INFO_DELIVER_CODE_MASK) {
4681 has_error_code = true;
4682 error_code =
4683 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4684 }
4685 /* fall through */
4686 case INTR_TYPE_SOFT_EXCEPTION:
4687 kvm_clear_exception_queue(vcpu);
4688 break;
4689 default:
4690 break;
4691 }
4692 }
4693 tss_selector = exit_qualification;
4694
4695 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4696 type != INTR_TYPE_EXT_INTR &&
4697 type != INTR_TYPE_NMI_INTR))
4698 skip_emulated_instruction(vcpu);
4699
4700 if (kvm_task_switch(vcpu, tss_selector, reason,
4701 has_error_code, error_code) == EMULATE_FAIL) {
4702 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4703 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4704 vcpu->run->internal.ndata = 0;
4705 return 0;
4706 }
4707
4708 /* clear all local breakpoint enable flags */
4709 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4710
4711 /*
4712 * TODO: What about debug traps on tss switch?
4713 * Are we supposed to inject them and update dr6?
4714 */
4715
4716 return 1;
4717 }
4718
4719 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4720 {
4721 unsigned long exit_qualification;
4722 gpa_t gpa;
4723 int gla_validity;
4724
4725 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4726
4727 if (exit_qualification & (1 << 6)) {
4728 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4729 return -EINVAL;
4730 }
4731
4732 gla_validity = (exit_qualification >> 7) & 0x3;
4733 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4734 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4735 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4736 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4737 vmcs_readl(GUEST_LINEAR_ADDRESS));
4738 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4739 (long unsigned int)exit_qualification);
4740 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4741 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4742 return 0;
4743 }
4744
4745 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4746 trace_kvm_page_fault(gpa, exit_qualification);
4747 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4748 }
4749
4750 static u64 ept_rsvd_mask(u64 spte, int level)
4751 {
4752 int i;
4753 u64 mask = 0;
4754
4755 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4756 mask |= (1ULL << i);
4757
4758 if (level > 2)
4759 /* bits 7:3 reserved */
4760 mask |= 0xf8;
4761 else if (level == 2) {
4762 if (spte & (1ULL << 7))
4763 /* 2MB ref, bits 20:12 reserved */
4764 mask |= 0x1ff000;
4765 else
4766 /* bits 6:3 reserved */
4767 mask |= 0x78;
4768 }
4769
4770 return mask;
4771 }
4772
4773 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4774 int level)
4775 {
4776 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4777
4778 /* 010b (write-only) */
4779 WARN_ON((spte & 0x7) == 0x2);
4780
4781 /* 110b (write/execute) */
4782 WARN_ON((spte & 0x7) == 0x6);
4783
4784 /* 100b (execute-only) and value not supported by logical processor */
4785 if (!cpu_has_vmx_ept_execute_only())
4786 WARN_ON((spte & 0x7) == 0x4);
4787
4788 /* not 000b */
4789 if ((spte & 0x7)) {
4790 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4791
4792 if (rsvd_bits != 0) {
4793 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4794 __func__, rsvd_bits);
4795 WARN_ON(1);
4796 }
4797
4798 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4799 u64 ept_mem_type = (spte & 0x38) >> 3;
4800
4801 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4802 ept_mem_type == 7) {
4803 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4804 __func__, ept_mem_type);
4805 WARN_ON(1);
4806 }
4807 }
4808 }
4809 }
4810
4811 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4812 {
4813 u64 sptes[4];
4814 int nr_sptes, i, ret;
4815 gpa_t gpa;
4816
4817 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4818
4819 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4820 if (likely(ret == 1))
4821 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4822 EMULATE_DONE;
4823 if (unlikely(!ret))
4824 return 1;
4825
4826 /* It is the real ept misconfig */
4827 printk(KERN_ERR "EPT: Misconfiguration.\n");
4828 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4829
4830 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4831
4832 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4833 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4834
4835 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4836 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4837
4838 return 0;
4839 }
4840
4841 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4842 {
4843 u32 cpu_based_vm_exec_control;
4844
4845 /* clear pending NMI */
4846 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4847 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4848 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4849 ++vcpu->stat.nmi_window_exits;
4850 kvm_make_request(KVM_REQ_EVENT, vcpu);
4851
4852 return 1;
4853 }
4854
4855 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4856 {
4857 struct vcpu_vmx *vmx = to_vmx(vcpu);
4858 enum emulation_result err = EMULATE_DONE;
4859 int ret = 1;
4860 u32 cpu_exec_ctrl;
4861 bool intr_window_requested;
4862
4863 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4864 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4865
4866 while (!guest_state_valid(vcpu)) {
4867 if (intr_window_requested
4868 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4869 return handle_interrupt_window(&vmx->vcpu);
4870
4871 err = emulate_instruction(vcpu, 0);
4872
4873 if (err == EMULATE_DO_MMIO) {
4874 ret = 0;
4875 goto out;
4876 }
4877
4878 if (err != EMULATE_DONE)
4879 return 0;
4880
4881 if (signal_pending(current))
4882 goto out;
4883 if (need_resched())
4884 schedule();
4885 }
4886
4887 vmx->emulation_required = 0;
4888 out:
4889 return ret;
4890 }
4891
4892 /*
4893 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4894 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4895 */
4896 static int handle_pause(struct kvm_vcpu *vcpu)
4897 {
4898 skip_emulated_instruction(vcpu);
4899 kvm_vcpu_on_spin(vcpu);
4900
4901 return 1;
4902 }
4903
4904 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4905 {
4906 kvm_queue_exception(vcpu, UD_VECTOR);
4907 return 1;
4908 }
4909
4910 /*
4911 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4912 * We could reuse a single VMCS for all the L2 guests, but we also want the
4913 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4914 * allows keeping them loaded on the processor, and in the future will allow
4915 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4916 * every entry if they never change.
4917 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4918 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4919 *
4920 * The following functions allocate and free a vmcs02 in this pool.
4921 */
4922
4923 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4924 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4925 {
4926 struct vmcs02_list *item;
4927 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4928 if (item->vmptr == vmx->nested.current_vmptr) {
4929 list_move(&item->list, &vmx->nested.vmcs02_pool);
4930 return &item->vmcs02;
4931 }
4932
4933 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4934 /* Recycle the least recently used VMCS. */
4935 item = list_entry(vmx->nested.vmcs02_pool.prev,
4936 struct vmcs02_list, list);
4937 item->vmptr = vmx->nested.current_vmptr;
4938 list_move(&item->list, &vmx->nested.vmcs02_pool);
4939 return &item->vmcs02;
4940 }
4941
4942 /* Create a new VMCS */
4943 item = (struct vmcs02_list *)
4944 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4945 if (!item)
4946 return NULL;
4947 item->vmcs02.vmcs = alloc_vmcs();
4948 if (!item->vmcs02.vmcs) {
4949 kfree(item);
4950 return NULL;
4951 }
4952 loaded_vmcs_init(&item->vmcs02);
4953 item->vmptr = vmx->nested.current_vmptr;
4954 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4955 vmx->nested.vmcs02_num++;
4956 return &item->vmcs02;
4957 }
4958
4959 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4960 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4961 {
4962 struct vmcs02_list *item;
4963 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4964 if (item->vmptr == vmptr) {
4965 free_loaded_vmcs(&item->vmcs02);
4966 list_del(&item->list);
4967 kfree(item);
4968 vmx->nested.vmcs02_num--;
4969 return;
4970 }
4971 }
4972
4973 /*
4974 * Free all VMCSs saved for this vcpu, except the one pointed by
4975 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4976 * currently used, if running L2), and vmcs01 when running L2.
4977 */
4978 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4979 {
4980 struct vmcs02_list *item, *n;
4981 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4982 if (vmx->loaded_vmcs != &item->vmcs02)
4983 free_loaded_vmcs(&item->vmcs02);
4984 list_del(&item->list);
4985 kfree(item);
4986 }
4987 vmx->nested.vmcs02_num = 0;
4988
4989 if (vmx->loaded_vmcs != &vmx->vmcs01)
4990 free_loaded_vmcs(&vmx->vmcs01);
4991 }
4992
4993 /*
4994 * Emulate the VMXON instruction.
4995 * Currently, we just remember that VMX is active, and do not save or even
4996 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4997 * do not currently need to store anything in that guest-allocated memory
4998 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4999 * argument is different from the VMXON pointer (which the spec says they do).
5000 */
5001 static int handle_vmon(struct kvm_vcpu *vcpu)
5002 {
5003 struct kvm_segment cs;
5004 struct vcpu_vmx *vmx = to_vmx(vcpu);
5005
5006 /* The Intel VMX Instruction Reference lists a bunch of bits that
5007 * are prerequisite to running VMXON, most notably cr4.VMXE must be
5008 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5009 * Otherwise, we should fail with #UD. We test these now:
5010 */
5011 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5012 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5013 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5014 kvm_queue_exception(vcpu, UD_VECTOR);
5015 return 1;
5016 }
5017
5018 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5019 if (is_long_mode(vcpu) && !cs.l) {
5020 kvm_queue_exception(vcpu, UD_VECTOR);
5021 return 1;
5022 }
5023
5024 if (vmx_get_cpl(vcpu)) {
5025 kvm_inject_gp(vcpu, 0);
5026 return 1;
5027 }
5028
5029 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5030 vmx->nested.vmcs02_num = 0;
5031
5032 vmx->nested.vmxon = true;
5033
5034 skip_emulated_instruction(vcpu);
5035 return 1;
5036 }
5037
5038 /*
5039 * Intel's VMX Instruction Reference specifies a common set of prerequisites
5040 * for running VMX instructions (except VMXON, whose prerequisites are
5041 * slightly different). It also specifies what exception to inject otherwise.
5042 */
5043 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5044 {
5045 struct kvm_segment cs;
5046 struct vcpu_vmx *vmx = to_vmx(vcpu);
5047
5048 if (!vmx->nested.vmxon) {
5049 kvm_queue_exception(vcpu, UD_VECTOR);
5050 return 0;
5051 }
5052
5053 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5054 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5055 (is_long_mode(vcpu) && !cs.l)) {
5056 kvm_queue_exception(vcpu, UD_VECTOR);
5057 return 0;
5058 }
5059
5060 if (vmx_get_cpl(vcpu)) {
5061 kvm_inject_gp(vcpu, 0);
5062 return 0;
5063 }
5064
5065 return 1;
5066 }
5067
5068 /*
5069 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5070 * just stops using VMX.
5071 */
5072 static void free_nested(struct vcpu_vmx *vmx)
5073 {
5074 if (!vmx->nested.vmxon)
5075 return;
5076 vmx->nested.vmxon = false;
5077 if (vmx->nested.current_vmptr != -1ull) {
5078 kunmap(vmx->nested.current_vmcs12_page);
5079 nested_release_page(vmx->nested.current_vmcs12_page);
5080 vmx->nested.current_vmptr = -1ull;
5081 vmx->nested.current_vmcs12 = NULL;
5082 }
5083 /* Unpin physical memory we referred to in current vmcs02 */
5084 if (vmx->nested.apic_access_page) {
5085 nested_release_page(vmx->nested.apic_access_page);
5086 vmx->nested.apic_access_page = 0;
5087 }
5088
5089 nested_free_all_saved_vmcss(vmx);
5090 }
5091
5092 /* Emulate the VMXOFF instruction */
5093 static int handle_vmoff(struct kvm_vcpu *vcpu)
5094 {
5095 if (!nested_vmx_check_permission(vcpu))
5096 return 1;
5097 free_nested(to_vmx(vcpu));
5098 skip_emulated_instruction(vcpu);
5099 return 1;
5100 }
5101
5102 /*
5103 * Decode the memory-address operand of a vmx instruction, as recorded on an
5104 * exit caused by such an instruction (run by a guest hypervisor).
5105 * On success, returns 0. When the operand is invalid, returns 1 and throws
5106 * #UD or #GP.
5107 */
5108 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5109 unsigned long exit_qualification,
5110 u32 vmx_instruction_info, gva_t *ret)
5111 {
5112 /*
5113 * According to Vol. 3B, "Information for VM Exits Due to Instruction
5114 * Execution", on an exit, vmx_instruction_info holds most of the
5115 * addressing components of the operand. Only the displacement part
5116 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5117 * For how an actual address is calculated from all these components,
5118 * refer to Vol. 1, "Operand Addressing".
5119 */
5120 int scaling = vmx_instruction_info & 3;
5121 int addr_size = (vmx_instruction_info >> 7) & 7;
5122 bool is_reg = vmx_instruction_info & (1u << 10);
5123 int seg_reg = (vmx_instruction_info >> 15) & 7;
5124 int index_reg = (vmx_instruction_info >> 18) & 0xf;
5125 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5126 int base_reg = (vmx_instruction_info >> 23) & 0xf;
5127 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
5128
5129 if (is_reg) {
5130 kvm_queue_exception(vcpu, UD_VECTOR);
5131 return 1;
5132 }
5133
5134 /* Addr = segment_base + offset */
5135 /* offset = base + [index * scale] + displacement */
5136 *ret = vmx_get_segment_base(vcpu, seg_reg);
5137 if (base_is_valid)
5138 *ret += kvm_register_read(vcpu, base_reg);
5139 if (index_is_valid)
5140 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5141 *ret += exit_qualification; /* holds the displacement */
5142
5143 if (addr_size == 1) /* 32 bit */
5144 *ret &= 0xffffffff;
5145
5146 /*
5147 * TODO: throw #GP (and return 1) in various cases that the VM*
5148 * instructions require it - e.g., offset beyond segment limit,
5149 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5150 * address, and so on. Currently these are not checked.
5151 */
5152 return 0;
5153 }
5154
5155 /*
5156 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5157 * set the success or error code of an emulated VMX instruction, as specified
5158 * by Vol 2B, VMX Instruction Reference, "Conventions".
5159 */
5160 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5161 {
5162 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5163 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5164 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5165 }
5166
5167 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5168 {
5169 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5170 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5171 X86_EFLAGS_SF | X86_EFLAGS_OF))
5172 | X86_EFLAGS_CF);
5173 }
5174
5175 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5176 u32 vm_instruction_error)
5177 {
5178 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5179 /*
5180 * failValid writes the error number to the current VMCS, which
5181 * can't be done there isn't a current VMCS.
5182 */
5183 nested_vmx_failInvalid(vcpu);
5184 return;
5185 }
5186 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5187 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5188 X86_EFLAGS_SF | X86_EFLAGS_OF))
5189 | X86_EFLAGS_ZF);
5190 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5191 }
5192
5193 /* Emulate the VMCLEAR instruction */
5194 static int handle_vmclear(struct kvm_vcpu *vcpu)
5195 {
5196 struct vcpu_vmx *vmx = to_vmx(vcpu);
5197 gva_t gva;
5198 gpa_t vmptr;
5199 struct vmcs12 *vmcs12;
5200 struct page *page;
5201 struct x86_exception e;
5202
5203 if (!nested_vmx_check_permission(vcpu))
5204 return 1;
5205
5206 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5207 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5208 return 1;
5209
5210 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5211 sizeof(vmptr), &e)) {
5212 kvm_inject_page_fault(vcpu, &e);
5213 return 1;
5214 }
5215
5216 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5217 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5218 skip_emulated_instruction(vcpu);
5219 return 1;
5220 }
5221
5222 if (vmptr == vmx->nested.current_vmptr) {
5223 kunmap(vmx->nested.current_vmcs12_page);
5224 nested_release_page(vmx->nested.current_vmcs12_page);
5225 vmx->nested.current_vmptr = -1ull;
5226 vmx->nested.current_vmcs12 = NULL;
5227 }
5228
5229 page = nested_get_page(vcpu, vmptr);
5230 if (page == NULL) {
5231 /*
5232 * For accurate processor emulation, VMCLEAR beyond available
5233 * physical memory should do nothing at all. However, it is
5234 * possible that a nested vmx bug, not a guest hypervisor bug,
5235 * resulted in this case, so let's shut down before doing any
5236 * more damage:
5237 */
5238 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5239 return 1;
5240 }
5241 vmcs12 = kmap(page);
5242 vmcs12->launch_state = 0;
5243 kunmap(page);
5244 nested_release_page(page);
5245
5246 nested_free_vmcs02(vmx, vmptr);
5247
5248 skip_emulated_instruction(vcpu);
5249 nested_vmx_succeed(vcpu);
5250 return 1;
5251 }
5252
5253 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5254
5255 /* Emulate the VMLAUNCH instruction */
5256 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5257 {
5258 return nested_vmx_run(vcpu, true);
5259 }
5260
5261 /* Emulate the VMRESUME instruction */
5262 static int handle_vmresume(struct kvm_vcpu *vcpu)
5263 {
5264
5265 return nested_vmx_run(vcpu, false);
5266 }
5267
5268 enum vmcs_field_type {
5269 VMCS_FIELD_TYPE_U16 = 0,
5270 VMCS_FIELD_TYPE_U64 = 1,
5271 VMCS_FIELD_TYPE_U32 = 2,
5272 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5273 };
5274
5275 static inline int vmcs_field_type(unsigned long field)
5276 {
5277 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5278 return VMCS_FIELD_TYPE_U32;
5279 return (field >> 13) & 0x3 ;
5280 }
5281
5282 static inline int vmcs_field_readonly(unsigned long field)
5283 {
5284 return (((field >> 10) & 0x3) == 1);
5285 }
5286
5287 /*
5288 * Read a vmcs12 field. Since these can have varying lengths and we return
5289 * one type, we chose the biggest type (u64) and zero-extend the return value
5290 * to that size. Note that the caller, handle_vmread, might need to use only
5291 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5292 * 64-bit fields are to be returned).
5293 */
5294 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5295 unsigned long field, u64 *ret)
5296 {
5297 short offset = vmcs_field_to_offset(field);
5298 char *p;
5299
5300 if (offset < 0)
5301 return 0;
5302
5303 p = ((char *)(get_vmcs12(vcpu))) + offset;
5304
5305 switch (vmcs_field_type(field)) {
5306 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5307 *ret = *((natural_width *)p);
5308 return 1;
5309 case VMCS_FIELD_TYPE_U16:
5310 *ret = *((u16 *)p);
5311 return 1;
5312 case VMCS_FIELD_TYPE_U32:
5313 *ret = *((u32 *)p);
5314 return 1;
5315 case VMCS_FIELD_TYPE_U64:
5316 *ret = *((u64 *)p);
5317 return 1;
5318 default:
5319 return 0; /* can never happen. */
5320 }
5321 }
5322
5323 /*
5324 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5325 * used before) all generate the same failure when it is missing.
5326 */
5327 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5328 {
5329 struct vcpu_vmx *vmx = to_vmx(vcpu);
5330 if (vmx->nested.current_vmptr == -1ull) {
5331 nested_vmx_failInvalid(vcpu);
5332 skip_emulated_instruction(vcpu);
5333 return 0;
5334 }
5335 return 1;
5336 }
5337
5338 static int handle_vmread(struct kvm_vcpu *vcpu)
5339 {
5340 unsigned long field;
5341 u64 field_value;
5342 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5343 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5344 gva_t gva = 0;
5345
5346 if (!nested_vmx_check_permission(vcpu) ||
5347 !nested_vmx_check_vmcs12(vcpu))
5348 return 1;
5349
5350 /* Decode instruction info and find the field to read */
5351 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5352 /* Read the field, zero-extended to a u64 field_value */
5353 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5354 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5355 skip_emulated_instruction(vcpu);
5356 return 1;
5357 }
5358 /*
5359 * Now copy part of this value to register or memory, as requested.
5360 * Note that the number of bits actually copied is 32 or 64 depending
5361 * on the guest's mode (32 or 64 bit), not on the given field's length.
5362 */
5363 if (vmx_instruction_info & (1u << 10)) {
5364 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5365 field_value);
5366 } else {
5367 if (get_vmx_mem_address(vcpu, exit_qualification,
5368 vmx_instruction_info, &gva))
5369 return 1;
5370 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5371 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5372 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5373 }
5374
5375 nested_vmx_succeed(vcpu);
5376 skip_emulated_instruction(vcpu);
5377 return 1;
5378 }
5379
5380
5381 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5382 {
5383 unsigned long field;
5384 gva_t gva;
5385 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5386 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5387 char *p;
5388 short offset;
5389 /* The value to write might be 32 or 64 bits, depending on L1's long
5390 * mode, and eventually we need to write that into a field of several
5391 * possible lengths. The code below first zero-extends the value to 64
5392 * bit (field_value), and then copies only the approriate number of
5393 * bits into the vmcs12 field.
5394 */
5395 u64 field_value = 0;
5396 struct x86_exception e;
5397
5398 if (!nested_vmx_check_permission(vcpu) ||
5399 !nested_vmx_check_vmcs12(vcpu))
5400 return 1;
5401
5402 if (vmx_instruction_info & (1u << 10))
5403 field_value = kvm_register_read(vcpu,
5404 (((vmx_instruction_info) >> 3) & 0xf));
5405 else {
5406 if (get_vmx_mem_address(vcpu, exit_qualification,
5407 vmx_instruction_info, &gva))
5408 return 1;
5409 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5410 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5411 kvm_inject_page_fault(vcpu, &e);
5412 return 1;
5413 }
5414 }
5415
5416
5417 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5418 if (vmcs_field_readonly(field)) {
5419 nested_vmx_failValid(vcpu,
5420 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5421 skip_emulated_instruction(vcpu);
5422 return 1;
5423 }
5424
5425 offset = vmcs_field_to_offset(field);
5426 if (offset < 0) {
5427 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5428 skip_emulated_instruction(vcpu);
5429 return 1;
5430 }
5431 p = ((char *) get_vmcs12(vcpu)) + offset;
5432
5433 switch (vmcs_field_type(field)) {
5434 case VMCS_FIELD_TYPE_U16:
5435 *(u16 *)p = field_value;
5436 break;
5437 case VMCS_FIELD_TYPE_U32:
5438 *(u32 *)p = field_value;
5439 break;
5440 case VMCS_FIELD_TYPE_U64:
5441 *(u64 *)p = field_value;
5442 break;
5443 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5444 *(natural_width *)p = field_value;
5445 break;
5446 default:
5447 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5448 skip_emulated_instruction(vcpu);
5449 return 1;
5450 }
5451
5452 nested_vmx_succeed(vcpu);
5453 skip_emulated_instruction(vcpu);
5454 return 1;
5455 }
5456
5457 /* Emulate the VMPTRLD instruction */
5458 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5459 {
5460 struct vcpu_vmx *vmx = to_vmx(vcpu);
5461 gva_t gva;
5462 gpa_t vmptr;
5463 struct x86_exception e;
5464
5465 if (!nested_vmx_check_permission(vcpu))
5466 return 1;
5467
5468 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5469 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5470 return 1;
5471
5472 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5473 sizeof(vmptr), &e)) {
5474 kvm_inject_page_fault(vcpu, &e);
5475 return 1;
5476 }
5477
5478 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5479 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5480 skip_emulated_instruction(vcpu);
5481 return 1;
5482 }
5483
5484 if (vmx->nested.current_vmptr != vmptr) {
5485 struct vmcs12 *new_vmcs12;
5486 struct page *page;
5487 page = nested_get_page(vcpu, vmptr);
5488 if (page == NULL) {
5489 nested_vmx_failInvalid(vcpu);
5490 skip_emulated_instruction(vcpu);
5491 return 1;
5492 }
5493 new_vmcs12 = kmap(page);
5494 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5495 kunmap(page);
5496 nested_release_page_clean(page);
5497 nested_vmx_failValid(vcpu,
5498 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5499 skip_emulated_instruction(vcpu);
5500 return 1;
5501 }
5502 if (vmx->nested.current_vmptr != -1ull) {
5503 kunmap(vmx->nested.current_vmcs12_page);
5504 nested_release_page(vmx->nested.current_vmcs12_page);
5505 }
5506
5507 vmx->nested.current_vmptr = vmptr;
5508 vmx->nested.current_vmcs12 = new_vmcs12;
5509 vmx->nested.current_vmcs12_page = page;
5510 }
5511
5512 nested_vmx_succeed(vcpu);
5513 skip_emulated_instruction(vcpu);
5514 return 1;
5515 }
5516
5517 /* Emulate the VMPTRST instruction */
5518 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5519 {
5520 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5521 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5522 gva_t vmcs_gva;
5523 struct x86_exception e;
5524
5525 if (!nested_vmx_check_permission(vcpu))
5526 return 1;
5527
5528 if (get_vmx_mem_address(vcpu, exit_qualification,
5529 vmx_instruction_info, &vmcs_gva))
5530 return 1;
5531 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5532 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5533 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5534 sizeof(u64), &e)) {
5535 kvm_inject_page_fault(vcpu, &e);
5536 return 1;
5537 }
5538 nested_vmx_succeed(vcpu);
5539 skip_emulated_instruction(vcpu);
5540 return 1;
5541 }
5542
5543 /*
5544 * The exit handlers return 1 if the exit was handled fully and guest execution
5545 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5546 * to be done to userspace and return 0.
5547 */
5548 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5549 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5550 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5551 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5552 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5553 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5554 [EXIT_REASON_CR_ACCESS] = handle_cr,
5555 [EXIT_REASON_DR_ACCESS] = handle_dr,
5556 [EXIT_REASON_CPUID] = handle_cpuid,
5557 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5558 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5559 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5560 [EXIT_REASON_HLT] = handle_halt,
5561 [EXIT_REASON_INVD] = handle_invd,
5562 [EXIT_REASON_INVLPG] = handle_invlpg,
5563 [EXIT_REASON_VMCALL] = handle_vmcall,
5564 [EXIT_REASON_VMCLEAR] = handle_vmclear,
5565 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
5566 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
5567 [EXIT_REASON_VMPTRST] = handle_vmptrst,
5568 [EXIT_REASON_VMREAD] = handle_vmread,
5569 [EXIT_REASON_VMRESUME] = handle_vmresume,
5570 [EXIT_REASON_VMWRITE] = handle_vmwrite,
5571 [EXIT_REASON_VMOFF] = handle_vmoff,
5572 [EXIT_REASON_VMON] = handle_vmon,
5573 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5574 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5575 [EXIT_REASON_WBINVD] = handle_wbinvd,
5576 [EXIT_REASON_XSETBV] = handle_xsetbv,
5577 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5578 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5579 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5580 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5581 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5582 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5583 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
5584 };
5585
5586 static const int kvm_vmx_max_exit_handlers =
5587 ARRAY_SIZE(kvm_vmx_exit_handlers);
5588
5589 /*
5590 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5591 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5592 * disinterest in the current event (read or write a specific MSR) by using an
5593 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5594 */
5595 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5596 struct vmcs12 *vmcs12, u32 exit_reason)
5597 {
5598 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5599 gpa_t bitmap;
5600
5601 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5602 return 1;
5603
5604 /*
5605 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5606 * for the four combinations of read/write and low/high MSR numbers.
5607 * First we need to figure out which of the four to use:
5608 */
5609 bitmap = vmcs12->msr_bitmap;
5610 if (exit_reason == EXIT_REASON_MSR_WRITE)
5611 bitmap += 2048;
5612 if (msr_index >= 0xc0000000) {
5613 msr_index -= 0xc0000000;
5614 bitmap += 1024;
5615 }
5616
5617 /* Then read the msr_index'th bit from this bitmap: */
5618 if (msr_index < 1024*8) {
5619 unsigned char b;
5620 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5621 return 1 & (b >> (msr_index & 7));
5622 } else
5623 return 1; /* let L1 handle the wrong parameter */
5624 }
5625
5626 /*
5627 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5628 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5629 * intercept (via guest_host_mask etc.) the current event.
5630 */
5631 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5632 struct vmcs12 *vmcs12)
5633 {
5634 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5635 int cr = exit_qualification & 15;
5636 int reg = (exit_qualification >> 8) & 15;
5637 unsigned long val = kvm_register_read(vcpu, reg);
5638
5639 switch ((exit_qualification >> 4) & 3) {
5640 case 0: /* mov to cr */
5641 switch (cr) {
5642 case 0:
5643 if (vmcs12->cr0_guest_host_mask &
5644 (val ^ vmcs12->cr0_read_shadow))
5645 return 1;
5646 break;
5647 case 3:
5648 if ((vmcs12->cr3_target_count >= 1 &&
5649 vmcs12->cr3_target_value0 == val) ||
5650 (vmcs12->cr3_target_count >= 2 &&
5651 vmcs12->cr3_target_value1 == val) ||
5652 (vmcs12->cr3_target_count >= 3 &&
5653 vmcs12->cr3_target_value2 == val) ||
5654 (vmcs12->cr3_target_count >= 4 &&
5655 vmcs12->cr3_target_value3 == val))
5656 return 0;
5657 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5658 return 1;
5659 break;
5660 case 4:
5661 if (vmcs12->cr4_guest_host_mask &
5662 (vmcs12->cr4_read_shadow ^ val))
5663 return 1;
5664 break;
5665 case 8:
5666 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5667 return 1;
5668 break;
5669 }
5670 break;
5671 case 2: /* clts */
5672 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5673 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5674 return 1;
5675 break;
5676 case 1: /* mov from cr */
5677 switch (cr) {
5678 case 3:
5679 if (vmcs12->cpu_based_vm_exec_control &
5680 CPU_BASED_CR3_STORE_EXITING)
5681 return 1;
5682 break;
5683 case 8:
5684 if (vmcs12->cpu_based_vm_exec_control &
5685 CPU_BASED_CR8_STORE_EXITING)
5686 return 1;
5687 break;
5688 }
5689 break;
5690 case 3: /* lmsw */
5691 /*
5692 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5693 * cr0. Other attempted changes are ignored, with no exit.
5694 */
5695 if (vmcs12->cr0_guest_host_mask & 0xe &
5696 (val ^ vmcs12->cr0_read_shadow))
5697 return 1;
5698 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5699 !(vmcs12->cr0_read_shadow & 0x1) &&
5700 (val & 0x1))
5701 return 1;
5702 break;
5703 }
5704 return 0;
5705 }
5706
5707 /*
5708 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5709 * should handle it ourselves in L0 (and then continue L2). Only call this
5710 * when in is_guest_mode (L2).
5711 */
5712 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5713 {
5714 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5715 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5716 struct vcpu_vmx *vmx = to_vmx(vcpu);
5717 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5718
5719 if (vmx->nested.nested_run_pending)
5720 return 0;
5721
5722 if (unlikely(vmx->fail)) {
5723 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5724 vmcs_read32(VM_INSTRUCTION_ERROR));
5725 return 1;
5726 }
5727
5728 switch (exit_reason) {
5729 case EXIT_REASON_EXCEPTION_NMI:
5730 if (!is_exception(intr_info))
5731 return 0;
5732 else if (is_page_fault(intr_info))
5733 return enable_ept;
5734 return vmcs12->exception_bitmap &
5735 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5736 case EXIT_REASON_EXTERNAL_INTERRUPT:
5737 return 0;
5738 case EXIT_REASON_TRIPLE_FAULT:
5739 return 1;
5740 case EXIT_REASON_PENDING_INTERRUPT:
5741 case EXIT_REASON_NMI_WINDOW:
5742 /*
5743 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5744 * (aka Interrupt Window Exiting) only when L1 turned it on,
5745 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5746 * Same for NMI Window Exiting.
5747 */
5748 return 1;
5749 case EXIT_REASON_TASK_SWITCH:
5750 return 1;
5751 case EXIT_REASON_CPUID:
5752 return 1;
5753 case EXIT_REASON_HLT:
5754 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5755 case EXIT_REASON_INVD:
5756 return 1;
5757 case EXIT_REASON_INVLPG:
5758 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5759 case EXIT_REASON_RDPMC:
5760 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5761 case EXIT_REASON_RDTSC:
5762 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5763 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5764 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5765 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5766 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5767 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5768 /*
5769 * VMX instructions trap unconditionally. This allows L1 to
5770 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5771 */
5772 return 1;
5773 case EXIT_REASON_CR_ACCESS:
5774 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5775 case EXIT_REASON_DR_ACCESS:
5776 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5777 case EXIT_REASON_IO_INSTRUCTION:
5778 /* TODO: support IO bitmaps */
5779 return 1;
5780 case EXIT_REASON_MSR_READ:
5781 case EXIT_REASON_MSR_WRITE:
5782 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5783 case EXIT_REASON_INVALID_STATE:
5784 return 1;
5785 case EXIT_REASON_MWAIT_INSTRUCTION:
5786 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5787 case EXIT_REASON_MONITOR_INSTRUCTION:
5788 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5789 case EXIT_REASON_PAUSE_INSTRUCTION:
5790 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5791 nested_cpu_has2(vmcs12,
5792 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5793 case EXIT_REASON_MCE_DURING_VMENTRY:
5794 return 0;
5795 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5796 return 1;
5797 case EXIT_REASON_APIC_ACCESS:
5798 return nested_cpu_has2(vmcs12,
5799 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5800 case EXIT_REASON_EPT_VIOLATION:
5801 case EXIT_REASON_EPT_MISCONFIG:
5802 return 0;
5803 case EXIT_REASON_WBINVD:
5804 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5805 case EXIT_REASON_XSETBV:
5806 return 1;
5807 default:
5808 return 1;
5809 }
5810 }
5811
5812 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5813 {
5814 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5815 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5816 }
5817
5818 /*
5819 * The guest has exited. See if we can fix it or if we need userspace
5820 * assistance.
5821 */
5822 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5823 {
5824 struct vcpu_vmx *vmx = to_vmx(vcpu);
5825 u32 exit_reason = vmx->exit_reason;
5826 u32 vectoring_info = vmx->idt_vectoring_info;
5827
5828 /* If guest state is invalid, start emulating */
5829 if (vmx->emulation_required && emulate_invalid_guest_state)
5830 return handle_invalid_guest_state(vcpu);
5831
5832 /*
5833 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5834 * we did not inject a still-pending event to L1 now because of
5835 * nested_run_pending, we need to re-enable this bit.
5836 */
5837 if (vmx->nested.nested_run_pending)
5838 kvm_make_request(KVM_REQ_EVENT, vcpu);
5839
5840 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5841 exit_reason == EXIT_REASON_VMRESUME))
5842 vmx->nested.nested_run_pending = 1;
5843 else
5844 vmx->nested.nested_run_pending = 0;
5845
5846 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5847 nested_vmx_vmexit(vcpu);
5848 return 1;
5849 }
5850
5851 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5852 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5853 vcpu->run->fail_entry.hardware_entry_failure_reason
5854 = exit_reason;
5855 return 0;
5856 }
5857
5858 if (unlikely(vmx->fail)) {
5859 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5860 vcpu->run->fail_entry.hardware_entry_failure_reason
5861 = vmcs_read32(VM_INSTRUCTION_ERROR);
5862 return 0;
5863 }
5864
5865 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5866 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5867 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5868 exit_reason != EXIT_REASON_TASK_SWITCH))
5869 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5870 "(0x%x) and exit reason is 0x%x\n",
5871 __func__, vectoring_info, exit_reason);
5872
5873 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5874 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5875 get_vmcs12(vcpu), vcpu)))) {
5876 if (vmx_interrupt_allowed(vcpu)) {
5877 vmx->soft_vnmi_blocked = 0;
5878 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5879 vcpu->arch.nmi_pending) {
5880 /*
5881 * This CPU don't support us in finding the end of an
5882 * NMI-blocked window if the guest runs with IRQs
5883 * disabled. So we pull the trigger after 1 s of
5884 * futile waiting, but inform the user about this.
5885 */
5886 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5887 "state on VCPU %d after 1 s timeout\n",
5888 __func__, vcpu->vcpu_id);
5889 vmx->soft_vnmi_blocked = 0;
5890 }
5891 }
5892
5893 if (exit_reason < kvm_vmx_max_exit_handlers
5894 && kvm_vmx_exit_handlers[exit_reason])
5895 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5896 else {
5897 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5898 vcpu->run->hw.hardware_exit_reason = exit_reason;
5899 }
5900 return 0;
5901 }
5902
5903 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5904 {
5905 if (irr == -1 || tpr < irr) {
5906 vmcs_write32(TPR_THRESHOLD, 0);
5907 return;
5908 }
5909
5910 vmcs_write32(TPR_THRESHOLD, irr);
5911 }
5912
5913 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5914 {
5915 u32 exit_intr_info;
5916
5917 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5918 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5919 return;
5920
5921 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5922 exit_intr_info = vmx->exit_intr_info;
5923
5924 /* Handle machine checks before interrupts are enabled */
5925 if (is_machine_check(exit_intr_info))
5926 kvm_machine_check();
5927
5928 /* We need to handle NMIs before interrupts are enabled */
5929 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5930 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5931 kvm_before_handle_nmi(&vmx->vcpu);
5932 asm("int $2");
5933 kvm_after_handle_nmi(&vmx->vcpu);
5934 }
5935 }
5936
5937 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5938 {
5939 u32 exit_intr_info;
5940 bool unblock_nmi;
5941 u8 vector;
5942 bool idtv_info_valid;
5943
5944 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5945
5946 if (cpu_has_virtual_nmis()) {
5947 if (vmx->nmi_known_unmasked)
5948 return;
5949 /*
5950 * Can't use vmx->exit_intr_info since we're not sure what
5951 * the exit reason is.
5952 */
5953 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5954 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5955 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5956 /*
5957 * SDM 3: 27.7.1.2 (September 2008)
5958 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5959 * a guest IRET fault.
5960 * SDM 3: 23.2.2 (September 2008)
5961 * Bit 12 is undefined in any of the following cases:
5962 * If the VM exit sets the valid bit in the IDT-vectoring
5963 * information field.
5964 * If the VM exit is due to a double fault.
5965 */
5966 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5967 vector != DF_VECTOR && !idtv_info_valid)
5968 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5969 GUEST_INTR_STATE_NMI);
5970 else
5971 vmx->nmi_known_unmasked =
5972 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5973 & GUEST_INTR_STATE_NMI);
5974 } else if (unlikely(vmx->soft_vnmi_blocked))
5975 vmx->vnmi_blocked_time +=
5976 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5977 }
5978
5979 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5980 u32 idt_vectoring_info,
5981 int instr_len_field,
5982 int error_code_field)
5983 {
5984 u8 vector;
5985 int type;
5986 bool idtv_info_valid;
5987
5988 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5989
5990 vmx->vcpu.arch.nmi_injected = false;
5991 kvm_clear_exception_queue(&vmx->vcpu);
5992 kvm_clear_interrupt_queue(&vmx->vcpu);
5993
5994 if (!idtv_info_valid)
5995 return;
5996
5997 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5998
5999 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6000 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6001
6002 switch (type) {
6003 case INTR_TYPE_NMI_INTR:
6004 vmx->vcpu.arch.nmi_injected = true;
6005 /*
6006 * SDM 3: 27.7.1.2 (September 2008)
6007 * Clear bit "block by NMI" before VM entry if a NMI
6008 * delivery faulted.
6009 */
6010 vmx_set_nmi_mask(&vmx->vcpu, false);
6011 break;
6012 case INTR_TYPE_SOFT_EXCEPTION:
6013 vmx->vcpu.arch.event_exit_inst_len =
6014 vmcs_read32(instr_len_field);
6015 /* fall through */
6016 case INTR_TYPE_HARD_EXCEPTION:
6017 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6018 u32 err = vmcs_read32(error_code_field);
6019 kvm_queue_exception_e(&vmx->vcpu, vector, err);
6020 } else
6021 kvm_queue_exception(&vmx->vcpu, vector);
6022 break;
6023 case INTR_TYPE_SOFT_INTR:
6024 vmx->vcpu.arch.event_exit_inst_len =
6025 vmcs_read32(instr_len_field);
6026 /* fall through */
6027 case INTR_TYPE_EXT_INTR:
6028 kvm_queue_interrupt(&vmx->vcpu, vector,
6029 type == INTR_TYPE_SOFT_INTR);
6030 break;
6031 default:
6032 break;
6033 }
6034 }
6035
6036 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6037 {
6038 if (is_guest_mode(&vmx->vcpu))
6039 return;
6040 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6041 VM_EXIT_INSTRUCTION_LEN,
6042 IDT_VECTORING_ERROR_CODE);
6043 }
6044
6045 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6046 {
6047 if (is_guest_mode(vcpu))
6048 return;
6049 __vmx_complete_interrupts(to_vmx(vcpu),
6050 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6051 VM_ENTRY_INSTRUCTION_LEN,
6052 VM_ENTRY_EXCEPTION_ERROR_CODE);
6053
6054 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6055 }
6056
6057 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6058 {
6059 int i, nr_msrs;
6060 struct perf_guest_switch_msr *msrs;
6061
6062 msrs = perf_guest_get_msrs(&nr_msrs);
6063
6064 if (!msrs)
6065 return;
6066
6067 for (i = 0; i < nr_msrs; i++)
6068 if (msrs[i].host == msrs[i].guest)
6069 clear_atomic_switch_msr(vmx, msrs[i].msr);
6070 else
6071 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6072 msrs[i].host);
6073 }
6074
6075 #ifdef CONFIG_X86_64
6076 #define R "r"
6077 #define Q "q"
6078 #else
6079 #define R "e"
6080 #define Q "l"
6081 #endif
6082
6083 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6084 {
6085 struct vcpu_vmx *vmx = to_vmx(vcpu);
6086
6087 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6088 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6089 if (vmcs12->idt_vectoring_info_field &
6090 VECTORING_INFO_VALID_MASK) {
6091 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6092 vmcs12->idt_vectoring_info_field);
6093 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6094 vmcs12->vm_exit_instruction_len);
6095 if (vmcs12->idt_vectoring_info_field &
6096 VECTORING_INFO_DELIVER_CODE_MASK)
6097 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6098 vmcs12->idt_vectoring_error_code);
6099 }
6100 }
6101
6102 /* Record the guest's net vcpu time for enforced NMI injections. */
6103 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6104 vmx->entry_time = ktime_get();
6105
6106 /* Don't enter VMX if guest state is invalid, let the exit handler
6107 start emulation until we arrive back to a valid state */
6108 if (vmx->emulation_required && emulate_invalid_guest_state)
6109 return;
6110
6111 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6112 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6113 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6114 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6115
6116 /* When single-stepping over STI and MOV SS, we must clear the
6117 * corresponding interruptibility bits in the guest state. Otherwise
6118 * vmentry fails as it then expects bit 14 (BS) in pending debug
6119 * exceptions being set, but that's not correct for the guest debugging
6120 * case. */
6121 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6122 vmx_set_interrupt_shadow(vcpu, 0);
6123
6124 atomic_switch_perf_msrs(vmx);
6125
6126 vmx->__launched = vmx->loaded_vmcs->launched;
6127 asm(
6128 /* Store host registers */
6129 "push %%"R"dx; push %%"R"bp;"
6130 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6131 "push %%"R"cx \n\t"
6132 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6133 "je 1f \n\t"
6134 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6135 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6136 "1: \n\t"
6137 /* Reload cr2 if changed */
6138 "mov %c[cr2](%0), %%"R"ax \n\t"
6139 "mov %%cr2, %%"R"dx \n\t"
6140 "cmp %%"R"ax, %%"R"dx \n\t"
6141 "je 2f \n\t"
6142 "mov %%"R"ax, %%cr2 \n\t"
6143 "2: \n\t"
6144 /* Check if vmlaunch of vmresume is needed */
6145 "cmpl $0, %c[launched](%0) \n\t"
6146 /* Load guest registers. Don't clobber flags. */
6147 "mov %c[rax](%0), %%"R"ax \n\t"
6148 "mov %c[rbx](%0), %%"R"bx \n\t"
6149 "mov %c[rdx](%0), %%"R"dx \n\t"
6150 "mov %c[rsi](%0), %%"R"si \n\t"
6151 "mov %c[rdi](%0), %%"R"di \n\t"
6152 "mov %c[rbp](%0), %%"R"bp \n\t"
6153 #ifdef CONFIG_X86_64
6154 "mov %c[r8](%0), %%r8 \n\t"
6155 "mov %c[r9](%0), %%r9 \n\t"
6156 "mov %c[r10](%0), %%r10 \n\t"
6157 "mov %c[r11](%0), %%r11 \n\t"
6158 "mov %c[r12](%0), %%r12 \n\t"
6159 "mov %c[r13](%0), %%r13 \n\t"
6160 "mov %c[r14](%0), %%r14 \n\t"
6161 "mov %c[r15](%0), %%r15 \n\t"
6162 #endif
6163 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6164
6165 /* Enter guest mode */
6166 "jne .Llaunched \n\t"
6167 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6168 "jmp .Lkvm_vmx_return \n\t"
6169 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6170 ".Lkvm_vmx_return: "
6171 /* Save guest registers, load host registers, keep flags */
6172 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6173 "pop %0 \n\t"
6174 "mov %%"R"ax, %c[rax](%0) \n\t"
6175 "mov %%"R"bx, %c[rbx](%0) \n\t"
6176 "pop"Q" %c[rcx](%0) \n\t"
6177 "mov %%"R"dx, %c[rdx](%0) \n\t"
6178 "mov %%"R"si, %c[rsi](%0) \n\t"
6179 "mov %%"R"di, %c[rdi](%0) \n\t"
6180 "mov %%"R"bp, %c[rbp](%0) \n\t"
6181 #ifdef CONFIG_X86_64
6182 "mov %%r8, %c[r8](%0) \n\t"
6183 "mov %%r9, %c[r9](%0) \n\t"
6184 "mov %%r10, %c[r10](%0) \n\t"
6185 "mov %%r11, %c[r11](%0) \n\t"
6186 "mov %%r12, %c[r12](%0) \n\t"
6187 "mov %%r13, %c[r13](%0) \n\t"
6188 "mov %%r14, %c[r14](%0) \n\t"
6189 "mov %%r15, %c[r15](%0) \n\t"
6190 #endif
6191 "mov %%cr2, %%"R"ax \n\t"
6192 "mov %%"R"ax, %c[cr2](%0) \n\t"
6193
6194 "pop %%"R"bp; pop %%"R"dx \n\t"
6195 "setbe %c[fail](%0) \n\t"
6196 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6197 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6198 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6199 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6200 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6201 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6202 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6203 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6204 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6205 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6206 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6207 #ifdef CONFIG_X86_64
6208 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6209 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6210 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6211 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6212 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6213 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6214 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6215 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6216 #endif
6217 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6218 [wordsize]"i"(sizeof(ulong))
6219 : "cc", "memory"
6220 , R"ax", R"bx", R"di", R"si"
6221 #ifdef CONFIG_X86_64
6222 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6223 #endif
6224 );
6225
6226 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6227 | (1 << VCPU_EXREG_RFLAGS)
6228 | (1 << VCPU_EXREG_CPL)
6229 | (1 << VCPU_EXREG_PDPTR)
6230 | (1 << VCPU_EXREG_SEGMENTS)
6231 | (1 << VCPU_EXREG_CR3));
6232 vcpu->arch.regs_dirty = 0;
6233
6234 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6235
6236 if (is_guest_mode(vcpu)) {
6237 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6238 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6239 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6240 vmcs12->idt_vectoring_error_code =
6241 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6242 vmcs12->vm_exit_instruction_len =
6243 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6244 }
6245 }
6246
6247 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6248 vmx->loaded_vmcs->launched = 1;
6249
6250 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6251 trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6252
6253 vmx_complete_atomic_exit(vmx);
6254 vmx_recover_nmi_blocking(vmx);
6255 vmx_complete_interrupts(vmx);
6256 }
6257
6258 #undef R
6259 #undef Q
6260
6261 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6262 {
6263 struct vcpu_vmx *vmx = to_vmx(vcpu);
6264
6265 free_vpid(vmx);
6266 free_nested(vmx);
6267 free_loaded_vmcs(vmx->loaded_vmcs);
6268 kfree(vmx->guest_msrs);
6269 kvm_vcpu_uninit(vcpu);
6270 kmem_cache_free(kvm_vcpu_cache, vmx);
6271 }
6272
6273 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6274 {
6275 int err;
6276 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6277 int cpu;
6278
6279 if (!vmx)
6280 return ERR_PTR(-ENOMEM);
6281
6282 allocate_vpid(vmx);
6283
6284 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6285 if (err)
6286 goto free_vcpu;
6287
6288 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6289 err = -ENOMEM;
6290 if (!vmx->guest_msrs) {
6291 goto uninit_vcpu;
6292 }
6293
6294 vmx->loaded_vmcs = &vmx->vmcs01;
6295 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6296 if (!vmx->loaded_vmcs->vmcs)
6297 goto free_msrs;
6298 if (!vmm_exclusive)
6299 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6300 loaded_vmcs_init(vmx->loaded_vmcs);
6301 if (!vmm_exclusive)
6302 kvm_cpu_vmxoff();
6303
6304 cpu = get_cpu();
6305 vmx_vcpu_load(&vmx->vcpu, cpu);
6306 vmx->vcpu.cpu = cpu;
6307 err = vmx_vcpu_setup(vmx);
6308 vmx_vcpu_put(&vmx->vcpu);
6309 put_cpu();
6310 if (err)
6311 goto free_vmcs;
6312 if (vm_need_virtualize_apic_accesses(kvm))
6313 err = alloc_apic_access_page(kvm);
6314 if (err)
6315 goto free_vmcs;
6316
6317 if (enable_ept) {
6318 if (!kvm->arch.ept_identity_map_addr)
6319 kvm->arch.ept_identity_map_addr =
6320 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6321 err = -ENOMEM;
6322 if (alloc_identity_pagetable(kvm) != 0)
6323 goto free_vmcs;
6324 if (!init_rmode_identity_map(kvm))
6325 goto free_vmcs;
6326 }
6327
6328 vmx->nested.current_vmptr = -1ull;
6329 vmx->nested.current_vmcs12 = NULL;
6330
6331 return &vmx->vcpu;
6332
6333 free_vmcs:
6334 free_vmcs(vmx->loaded_vmcs->vmcs);
6335 free_msrs:
6336 kfree(vmx->guest_msrs);
6337 uninit_vcpu:
6338 kvm_vcpu_uninit(&vmx->vcpu);
6339 free_vcpu:
6340 free_vpid(vmx);
6341 kmem_cache_free(kvm_vcpu_cache, vmx);
6342 return ERR_PTR(err);
6343 }
6344
6345 static void __init vmx_check_processor_compat(void *rtn)
6346 {
6347 struct vmcs_config vmcs_conf;
6348
6349 *(int *)rtn = 0;
6350 if (setup_vmcs_config(&vmcs_conf) < 0)
6351 *(int *)rtn = -EIO;
6352 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6353 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6354 smp_processor_id());
6355 *(int *)rtn = -EIO;
6356 }
6357 }
6358
6359 static int get_ept_level(void)
6360 {
6361 return VMX_EPT_DEFAULT_GAW + 1;
6362 }
6363
6364 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6365 {
6366 u64 ret;
6367
6368 /* For VT-d and EPT combination
6369 * 1. MMIO: always map as UC
6370 * 2. EPT with VT-d:
6371 * a. VT-d without snooping control feature: can't guarantee the
6372 * result, try to trust guest.
6373 * b. VT-d with snooping control feature: snooping control feature of
6374 * VT-d engine can guarantee the cache correctness. Just set it
6375 * to WB to keep consistent with host. So the same as item 3.
6376 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6377 * consistent with host MTRR
6378 */
6379 if (is_mmio)
6380 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6381 else if (vcpu->kvm->arch.iommu_domain &&
6382 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6383 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6384 VMX_EPT_MT_EPTE_SHIFT;
6385 else
6386 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6387 | VMX_EPT_IPAT_BIT;
6388
6389 return ret;
6390 }
6391
6392 static int vmx_get_lpage_level(void)
6393 {
6394 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6395 return PT_DIRECTORY_LEVEL;
6396 else
6397 /* For shadow and EPT supported 1GB page */
6398 return PT_PDPE_LEVEL;
6399 }
6400
6401 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6402 {
6403 struct kvm_cpuid_entry2 *best;
6404 struct vcpu_vmx *vmx = to_vmx(vcpu);
6405 u32 exec_control;
6406
6407 vmx->rdtscp_enabled = false;
6408 if (vmx_rdtscp_supported()) {
6409 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6410 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6411 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6412 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6413 vmx->rdtscp_enabled = true;
6414 else {
6415 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6416 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6417 exec_control);
6418 }
6419 }
6420 }
6421 }
6422
6423 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6424 {
6425 if (func == 1 && nested)
6426 entry->ecx |= bit(X86_FEATURE_VMX);
6427 }
6428
6429 /*
6430 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6431 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6432 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6433 * guest in a way that will both be appropriate to L1's requests, and our
6434 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6435 * function also has additional necessary side-effects, like setting various
6436 * vcpu->arch fields.
6437 */
6438 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6439 {
6440 struct vcpu_vmx *vmx = to_vmx(vcpu);
6441 u32 exec_control;
6442
6443 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6444 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6445 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6446 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6447 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6448 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6449 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6450 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6451 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6452 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6453 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6454 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6455 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6456 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6457 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6458 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6459 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6460 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6461 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6462 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6463 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6464 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6465 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6466 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6467 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6468 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6469 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6470 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6471 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6472 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6473 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6474 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6475 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6476 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6477 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6478 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6479
6480 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6481 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6482 vmcs12->vm_entry_intr_info_field);
6483 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6484 vmcs12->vm_entry_exception_error_code);
6485 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6486 vmcs12->vm_entry_instruction_len);
6487 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6488 vmcs12->guest_interruptibility_info);
6489 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6490 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6491 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6492 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6493 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6494 vmcs12->guest_pending_dbg_exceptions);
6495 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6496 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6497
6498 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6499
6500 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6501 (vmcs_config.pin_based_exec_ctrl |
6502 vmcs12->pin_based_vm_exec_control));
6503
6504 /*
6505 * Whether page-faults are trapped is determined by a combination of
6506 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6507 * If enable_ept, L0 doesn't care about page faults and we should
6508 * set all of these to L1's desires. However, if !enable_ept, L0 does
6509 * care about (at least some) page faults, and because it is not easy
6510 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6511 * to exit on each and every L2 page fault. This is done by setting
6512 * MASK=MATCH=0 and (see below) EB.PF=1.
6513 * Note that below we don't need special code to set EB.PF beyond the
6514 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6515 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6516 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6517 *
6518 * A problem with this approach (when !enable_ept) is that L1 may be
6519 * injected with more page faults than it asked for. This could have
6520 * caused problems, but in practice existing hypervisors don't care.
6521 * To fix this, we will need to emulate the PFEC checking (on the L1
6522 * page tables), using walk_addr(), when injecting PFs to L1.
6523 */
6524 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6525 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6526 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6527 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6528
6529 if (cpu_has_secondary_exec_ctrls()) {
6530 u32 exec_control = vmx_secondary_exec_control(vmx);
6531 if (!vmx->rdtscp_enabled)
6532 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6533 /* Take the following fields only from vmcs12 */
6534 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6535 if (nested_cpu_has(vmcs12,
6536 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6537 exec_control |= vmcs12->secondary_vm_exec_control;
6538
6539 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6540 /*
6541 * Translate L1 physical address to host physical
6542 * address for vmcs02. Keep the page pinned, so this
6543 * physical address remains valid. We keep a reference
6544 * to it so we can release it later.
6545 */
6546 if (vmx->nested.apic_access_page) /* shouldn't happen */
6547 nested_release_page(vmx->nested.apic_access_page);
6548 vmx->nested.apic_access_page =
6549 nested_get_page(vcpu, vmcs12->apic_access_addr);
6550 /*
6551 * If translation failed, no matter: This feature asks
6552 * to exit when accessing the given address, and if it
6553 * can never be accessed, this feature won't do
6554 * anything anyway.
6555 */
6556 if (!vmx->nested.apic_access_page)
6557 exec_control &=
6558 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6559 else
6560 vmcs_write64(APIC_ACCESS_ADDR,
6561 page_to_phys(vmx->nested.apic_access_page));
6562 }
6563
6564 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6565 }
6566
6567
6568 /*
6569 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6570 * Some constant fields are set here by vmx_set_constant_host_state().
6571 * Other fields are different per CPU, and will be set later when
6572 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6573 */
6574 vmx_set_constant_host_state();
6575
6576 /*
6577 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6578 * entry, but only if the current (host) sp changed from the value
6579 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6580 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6581 * here we just force the write to happen on entry.
6582 */
6583 vmx->host_rsp = 0;
6584
6585 exec_control = vmx_exec_control(vmx); /* L0's desires */
6586 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6587 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6588 exec_control &= ~CPU_BASED_TPR_SHADOW;
6589 exec_control |= vmcs12->cpu_based_vm_exec_control;
6590 /*
6591 * Merging of IO and MSR bitmaps not currently supported.
6592 * Rather, exit every time.
6593 */
6594 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6595 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6596 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6597
6598 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6599
6600 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6601 * bitwise-or of what L1 wants to trap for L2, and what we want to
6602 * trap. Note that CR0.TS also needs updating - we do this later.
6603 */
6604 update_exception_bitmap(vcpu);
6605 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6606 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6607
6608 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6609 vmcs_write32(VM_EXIT_CONTROLS,
6610 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6611 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6612 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6613
6614 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6615 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6616 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6617 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6618
6619
6620 set_cr4_guest_host_mask(vmx);
6621
6622 if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6623 vmcs_write64(TSC_OFFSET,
6624 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6625 else
6626 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6627
6628 if (enable_vpid) {
6629 /*
6630 * Trivially support vpid by letting L2s share their parent
6631 * L1's vpid. TODO: move to a more elaborate solution, giving
6632 * each L2 its own vpid and exposing the vpid feature to L1.
6633 */
6634 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6635 vmx_flush_tlb(vcpu);
6636 }
6637
6638 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6639 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6640 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6641 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6642 else
6643 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6644 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6645 vmx_set_efer(vcpu, vcpu->arch.efer);
6646
6647 /*
6648 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6649 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6650 * The CR0_READ_SHADOW is what L2 should have expected to read given
6651 * the specifications by L1; It's not enough to take
6652 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6653 * have more bits than L1 expected.
6654 */
6655 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6656 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6657
6658 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6659 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6660
6661 /* shadow page tables on either EPT or shadow page tables */
6662 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6663 kvm_mmu_reset_context(vcpu);
6664
6665 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6666 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6667 }
6668
6669 /*
6670 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6671 * for running an L2 nested guest.
6672 */
6673 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6674 {
6675 struct vmcs12 *vmcs12;
6676 struct vcpu_vmx *vmx = to_vmx(vcpu);
6677 int cpu;
6678 struct loaded_vmcs *vmcs02;
6679
6680 if (!nested_vmx_check_permission(vcpu) ||
6681 !nested_vmx_check_vmcs12(vcpu))
6682 return 1;
6683
6684 skip_emulated_instruction(vcpu);
6685 vmcs12 = get_vmcs12(vcpu);
6686
6687 /*
6688 * The nested entry process starts with enforcing various prerequisites
6689 * on vmcs12 as required by the Intel SDM, and act appropriately when
6690 * they fail: As the SDM explains, some conditions should cause the
6691 * instruction to fail, while others will cause the instruction to seem
6692 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6693 * To speed up the normal (success) code path, we should avoid checking
6694 * for misconfigurations which will anyway be caught by the processor
6695 * when using the merged vmcs02.
6696 */
6697 if (vmcs12->launch_state == launch) {
6698 nested_vmx_failValid(vcpu,
6699 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6700 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6701 return 1;
6702 }
6703
6704 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6705 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6706 /*TODO: Also verify bits beyond physical address width are 0*/
6707 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6708 return 1;
6709 }
6710
6711 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6712 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6713 /*TODO: Also verify bits beyond physical address width are 0*/
6714 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6715 return 1;
6716 }
6717
6718 if (vmcs12->vm_entry_msr_load_count > 0 ||
6719 vmcs12->vm_exit_msr_load_count > 0 ||
6720 vmcs12->vm_exit_msr_store_count > 0) {
6721 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6722 __func__);
6723 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6724 return 1;
6725 }
6726
6727 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6728 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6729 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6730 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6731 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6732 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6733 !vmx_control_verify(vmcs12->vm_exit_controls,
6734 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6735 !vmx_control_verify(vmcs12->vm_entry_controls,
6736 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6737 {
6738 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6739 return 1;
6740 }
6741
6742 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6743 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6744 nested_vmx_failValid(vcpu,
6745 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6746 return 1;
6747 }
6748
6749 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6750 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6751 nested_vmx_entry_failure(vcpu, vmcs12,
6752 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6753 return 1;
6754 }
6755 if (vmcs12->vmcs_link_pointer != -1ull) {
6756 nested_vmx_entry_failure(vcpu, vmcs12,
6757 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6758 return 1;
6759 }
6760
6761 /*
6762 * We're finally done with prerequisite checking, and can start with
6763 * the nested entry.
6764 */
6765
6766 vmcs02 = nested_get_current_vmcs02(vmx);
6767 if (!vmcs02)
6768 return -ENOMEM;
6769
6770 enter_guest_mode(vcpu);
6771
6772 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6773
6774 cpu = get_cpu();
6775 vmx->loaded_vmcs = vmcs02;
6776 vmx_vcpu_put(vcpu);
6777 vmx_vcpu_load(vcpu, cpu);
6778 vcpu->cpu = cpu;
6779 put_cpu();
6780
6781 vmcs12->launch_state = 1;
6782
6783 prepare_vmcs02(vcpu, vmcs12);
6784
6785 /*
6786 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6787 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6788 * returned as far as L1 is concerned. It will only return (and set
6789 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6790 */
6791 return 1;
6792 }
6793
6794 /*
6795 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6796 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6797 * This function returns the new value we should put in vmcs12.guest_cr0.
6798 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6799 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6800 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6801 * didn't trap the bit, because if L1 did, so would L0).
6802 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6803 * been modified by L2, and L1 knows it. So just leave the old value of
6804 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6805 * isn't relevant, because if L0 traps this bit it can set it to anything.
6806 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6807 * changed these bits, and therefore they need to be updated, but L0
6808 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6809 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6810 */
6811 static inline unsigned long
6812 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6813 {
6814 return
6815 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6816 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6817 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6818 vcpu->arch.cr0_guest_owned_bits));
6819 }
6820
6821 static inline unsigned long
6822 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6823 {
6824 return
6825 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6826 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6827 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6828 vcpu->arch.cr4_guest_owned_bits));
6829 }
6830
6831 /*
6832 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6833 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6834 * and this function updates it to reflect the changes to the guest state while
6835 * L2 was running (and perhaps made some exits which were handled directly by L0
6836 * without going back to L1), and to reflect the exit reason.
6837 * Note that we do not have to copy here all VMCS fields, just those that
6838 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6839 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6840 * which already writes to vmcs12 directly.
6841 */
6842 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6843 {
6844 /* update guest state fields: */
6845 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6846 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6847
6848 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6849 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6850 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6851 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6852
6853 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6854 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6855 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6856 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6857 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6858 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6859 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6860 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6861 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6862 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6863 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6864 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6865 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6866 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6867 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6868 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6869 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6870 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6871 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6872 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6873 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6874 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6875 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6876 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6877 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6878 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6879 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6880 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6881 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6882 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6883 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6884 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6885 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6886 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6887 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6888 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6889
6890 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6891 vmcs12->guest_interruptibility_info =
6892 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6893 vmcs12->guest_pending_dbg_exceptions =
6894 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6895
6896 /* TODO: These cannot have changed unless we have MSR bitmaps and
6897 * the relevant bit asks not to trap the change */
6898 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6899 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6900 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6901 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6902 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6903 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6904
6905 /* update exit information fields: */
6906
6907 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6908 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6909
6910 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6911 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6912 vmcs12->idt_vectoring_info_field =
6913 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6914 vmcs12->idt_vectoring_error_code =
6915 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6916 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6917 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6918
6919 /* clear vm-entry fields which are to be cleared on exit */
6920 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6921 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6922 }
6923
6924 /*
6925 * A part of what we need to when the nested L2 guest exits and we want to
6926 * run its L1 parent, is to reset L1's guest state to the host state specified
6927 * in vmcs12.
6928 * This function is to be called not only on normal nested exit, but also on
6929 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6930 * Failures During or After Loading Guest State").
6931 * This function should be called when the active VMCS is L1's (vmcs01).
6932 */
6933 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6934 {
6935 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6936 vcpu->arch.efer = vmcs12->host_ia32_efer;
6937 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6938 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6939 else
6940 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6941 vmx_set_efer(vcpu, vcpu->arch.efer);
6942
6943 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6944 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6945 /*
6946 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6947 * actually changed, because it depends on the current state of
6948 * fpu_active (which may have changed).
6949 * Note that vmx_set_cr0 refers to efer set above.
6950 */
6951 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6952 /*
6953 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6954 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6955 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6956 */
6957 update_exception_bitmap(vcpu);
6958 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6959 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6960
6961 /*
6962 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6963 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6964 */
6965 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6966 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6967
6968 /* shadow page tables on either EPT or shadow page tables */
6969 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6970 kvm_mmu_reset_context(vcpu);
6971
6972 if (enable_vpid) {
6973 /*
6974 * Trivially support vpid by letting L2s share their parent
6975 * L1's vpid. TODO: move to a more elaborate solution, giving
6976 * each L2 its own vpid and exposing the vpid feature to L1.
6977 */
6978 vmx_flush_tlb(vcpu);
6979 }
6980
6981
6982 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6983 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6984 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6985 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6986 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6987 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6988 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6989 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6990 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6991 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6992 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6993 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6994 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6995 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6996 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6997
6998 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6999 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7000 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7001 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7002 vmcs12->host_ia32_perf_global_ctrl);
7003 }
7004
7005 /*
7006 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7007 * and modify vmcs12 to make it see what it would expect to see there if
7008 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7009 */
7010 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7011 {
7012 struct vcpu_vmx *vmx = to_vmx(vcpu);
7013 int cpu;
7014 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7015
7016 leave_guest_mode(vcpu);
7017 prepare_vmcs12(vcpu, vmcs12);
7018
7019 cpu = get_cpu();
7020 vmx->loaded_vmcs = &vmx->vmcs01;
7021 vmx_vcpu_put(vcpu);
7022 vmx_vcpu_load(vcpu, cpu);
7023 vcpu->cpu = cpu;
7024 put_cpu();
7025
7026 /* if no vmcs02 cache requested, remove the one we used */
7027 if (VMCS02_POOL_SIZE == 0)
7028 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7029
7030 load_vmcs12_host_state(vcpu, vmcs12);
7031
7032 /* Update TSC_OFFSET if TSC was changed while L2 ran */
7033 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7034
7035 /* This is needed for same reason as it was needed in prepare_vmcs02 */
7036 vmx->host_rsp = 0;
7037
7038 /* Unpin physical memory we referred to in vmcs02 */
7039 if (vmx->nested.apic_access_page) {
7040 nested_release_page(vmx->nested.apic_access_page);
7041 vmx->nested.apic_access_page = 0;
7042 }
7043
7044 /*
7045 * Exiting from L2 to L1, we're now back to L1 which thinks it just
7046 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7047 * success or failure flag accordingly.
7048 */
7049 if (unlikely(vmx->fail)) {
7050 vmx->fail = 0;
7051 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7052 } else
7053 nested_vmx_succeed(vcpu);
7054 }
7055
7056 /*
7057 * L1's failure to enter L2 is a subset of a normal exit, as explained in
7058 * 23.7 "VM-entry failures during or after loading guest state" (this also
7059 * lists the acceptable exit-reason and exit-qualification parameters).
7060 * It should only be called before L2 actually succeeded to run, and when
7061 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7062 */
7063 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7064 struct vmcs12 *vmcs12,
7065 u32 reason, unsigned long qualification)
7066 {
7067 load_vmcs12_host_state(vcpu, vmcs12);
7068 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7069 vmcs12->exit_qualification = qualification;
7070 nested_vmx_succeed(vcpu);
7071 }
7072
7073 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7074 struct x86_instruction_info *info,
7075 enum x86_intercept_stage stage)
7076 {
7077 return X86EMUL_CONTINUE;
7078 }
7079
7080 static struct kvm_x86_ops vmx_x86_ops = {
7081 .cpu_has_kvm_support = cpu_has_kvm_support,
7082 .disabled_by_bios = vmx_disabled_by_bios,
7083 .hardware_setup = hardware_setup,
7084 .hardware_unsetup = hardware_unsetup,
7085 .check_processor_compatibility = vmx_check_processor_compat,
7086 .hardware_enable = hardware_enable,
7087 .hardware_disable = hardware_disable,
7088 .cpu_has_accelerated_tpr = report_flexpriority,
7089
7090 .vcpu_create = vmx_create_vcpu,
7091 .vcpu_free = vmx_free_vcpu,
7092 .vcpu_reset = vmx_vcpu_reset,
7093
7094 .prepare_guest_switch = vmx_save_host_state,
7095 .vcpu_load = vmx_vcpu_load,
7096 .vcpu_put = vmx_vcpu_put,
7097
7098 .set_guest_debug = set_guest_debug,
7099 .get_msr = vmx_get_msr,
7100 .set_msr = vmx_set_msr,
7101 .get_segment_base = vmx_get_segment_base,
7102 .get_segment = vmx_get_segment,
7103 .set_segment = vmx_set_segment,
7104 .get_cpl = vmx_get_cpl,
7105 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7106 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7107 .decache_cr3 = vmx_decache_cr3,
7108 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7109 .set_cr0 = vmx_set_cr0,
7110 .set_cr3 = vmx_set_cr3,
7111 .set_cr4 = vmx_set_cr4,
7112 .set_efer = vmx_set_efer,
7113 .get_idt = vmx_get_idt,
7114 .set_idt = vmx_set_idt,
7115 .get_gdt = vmx_get_gdt,
7116 .set_gdt = vmx_set_gdt,
7117 .set_dr7 = vmx_set_dr7,
7118 .cache_reg = vmx_cache_reg,
7119 .get_rflags = vmx_get_rflags,
7120 .set_rflags = vmx_set_rflags,
7121 .fpu_activate = vmx_fpu_activate,
7122 .fpu_deactivate = vmx_fpu_deactivate,
7123
7124 .tlb_flush = vmx_flush_tlb,
7125
7126 .run = vmx_vcpu_run,
7127 .handle_exit = vmx_handle_exit,
7128 .skip_emulated_instruction = skip_emulated_instruction,
7129 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7130 .get_interrupt_shadow = vmx_get_interrupt_shadow,
7131 .patch_hypercall = vmx_patch_hypercall,
7132 .set_irq = vmx_inject_irq,
7133 .set_nmi = vmx_inject_nmi,
7134 .queue_exception = vmx_queue_exception,
7135 .cancel_injection = vmx_cancel_injection,
7136 .interrupt_allowed = vmx_interrupt_allowed,
7137 .nmi_allowed = vmx_nmi_allowed,
7138 .get_nmi_mask = vmx_get_nmi_mask,
7139 .set_nmi_mask = vmx_set_nmi_mask,
7140 .enable_nmi_window = enable_nmi_window,
7141 .enable_irq_window = enable_irq_window,
7142 .update_cr8_intercept = update_cr8_intercept,
7143
7144 .set_tss_addr = vmx_set_tss_addr,
7145 .get_tdp_level = get_ept_level,
7146 .get_mt_mask = vmx_get_mt_mask,
7147
7148 .get_exit_info = vmx_get_exit_info,
7149
7150 .get_lpage_level = vmx_get_lpage_level,
7151
7152 .cpuid_update = vmx_cpuid_update,
7153
7154 .rdtscp_supported = vmx_rdtscp_supported,
7155
7156 .set_supported_cpuid = vmx_set_supported_cpuid,
7157
7158 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7159
7160 .set_tsc_khz = vmx_set_tsc_khz,
7161 .write_tsc_offset = vmx_write_tsc_offset,
7162 .adjust_tsc_offset = vmx_adjust_tsc_offset,
7163 .compute_tsc_offset = vmx_compute_tsc_offset,
7164 .read_l1_tsc = vmx_read_l1_tsc,
7165
7166 .set_tdp_cr3 = vmx_set_cr3,
7167
7168 .check_intercept = vmx_check_intercept,
7169 };
7170
7171 static int __init vmx_init(void)
7172 {
7173 int r, i;
7174
7175 rdmsrl_safe(MSR_EFER, &host_efer);
7176
7177 for (i = 0; i < NR_VMX_MSR; ++i)
7178 kvm_define_shared_msr(i, vmx_msr_index[i]);
7179
7180 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7181 if (!vmx_io_bitmap_a)
7182 return -ENOMEM;
7183
7184 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7185 if (!vmx_io_bitmap_b) {
7186 r = -ENOMEM;
7187 goto out;
7188 }
7189
7190 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7191 if (!vmx_msr_bitmap_legacy) {
7192 r = -ENOMEM;
7193 goto out1;
7194 }
7195
7196 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7197 if (!vmx_msr_bitmap_longmode) {
7198 r = -ENOMEM;
7199 goto out2;
7200 }
7201
7202 /*
7203 * Allow direct access to the PC debug port (it is often used for I/O
7204 * delays, but the vmexits simply slow things down).
7205 */
7206 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7207 clear_bit(0x80, vmx_io_bitmap_a);
7208
7209 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7210
7211 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7212 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7213
7214 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7215
7216 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7217 __alignof__(struct vcpu_vmx), THIS_MODULE);
7218 if (r)
7219 goto out3;
7220
7221 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7222 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7223 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7224 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7225 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7226 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7227
7228 if (enable_ept) {
7229 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7230 VMX_EPT_EXECUTABLE_MASK);
7231 ept_set_mmio_spte_mask();
7232 kvm_enable_tdp();
7233 } else
7234 kvm_disable_tdp();
7235
7236 return 0;
7237
7238 out3:
7239 free_page((unsigned long)vmx_msr_bitmap_longmode);
7240 out2:
7241 free_page((unsigned long)vmx_msr_bitmap_legacy);
7242 out1:
7243 free_page((unsigned long)vmx_io_bitmap_b);
7244 out:
7245 free_page((unsigned long)vmx_io_bitmap_a);
7246 return r;
7247 }
7248
7249 static void __exit vmx_exit(void)
7250 {
7251 free_page((unsigned long)vmx_msr_bitmap_legacy);
7252 free_page((unsigned long)vmx_msr_bitmap_longmode);
7253 free_page((unsigned long)vmx_io_bitmap_b);
7254 free_page((unsigned long)vmx_io_bitmap_a);
7255
7256 kvm_exit();
7257 }
7258
7259 module_init(vmx_init)
7260 module_exit(vmx_exit)
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